1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
42 } __attribute__((packed));
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
55 } __attribute__((packed));
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The device's serial number. */
76 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
77 /* Engine CKV - Per-function random nonce data. */
78 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
79 /* Engine CKV - Initialization vector. */
80 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
81 /* Engine CKV - Authentication tag. */
82 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
83 /* Engine CKV - The encrypted data. */
84 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
85 /* Engine CKV - Supported algorithms. */
86 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
87 /* Engine CKV - The EC curve name and ECC public key information. */
88 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
89 /* Engine CKV - The ECDSA signature. */
90 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
91 #define TLV_TYPE_LAST \
92 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
95 /* tlv (size:64b/8B) */
98 * The command discriminator is used to differentiate between various
99 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
100 * command messages as well as newer TLV encapsulated HWRM commands.
102 * For TLV encapsulated messages this field must be 0x8000.
108 * Indicates the presence of additional TLV encapsulated data
111 #define TLV_FLAGS_MORE UINT32_C(0x1)
112 /* Last TLV in a sequence of TLVs. */
113 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
114 /* More TLVs follow this TLV. */
115 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
117 * When an HWRM receiver detects a TLV type that it does not
118 * support with the TLV required flag set, the receiver must
119 * reject the HWRM message with an error code indicating an
120 * unsupported TLV type.
122 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
124 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
126 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
127 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
129 * This field defines the TLV type value which is divided into
130 * two ranges to differentiate between global and local TLV types.
131 * Global TLV types must be unique across all defined TLV types.
132 * Local TLV types are valid only for extensions to a given
133 * HWRM message and may be repeated across different HWRM message
134 * types. There is a direct correlation of each HWRM message type
135 * to a single global TLV type value.
137 * Global TLV range: `0 - (63k-1)`
139 * Local TLV range: `63k - (64k-1)`
143 * Length of the message data encapsulated by this TLV in bytes.
144 * This length does not include the size of the TLV header itself
145 * and it must be an integer multiple of 8B.
148 } __attribute__((packed));
151 /* input (size:128b/16B) */
154 * This value indicates what type of request this is. The format
155 * for the rest of the command is determined by this field.
159 * This value indicates the what completion ring the request will
160 * be optionally completed on. If the value is -1, then no
161 * CR completion will be generated. Any other value must be a
162 * valid CR ring_id value for this function.
165 /* This value indicates the command sequence number. */
168 * Target ID of this command.
170 * 0x0 - 0xFFF8 - Used for function ids
171 * 0xFFF8 - 0xFFFE - Reserved for internal processors
176 * This is the host address where the response will be written
177 * when the request is complete. This area must be 16B aligned
178 * and must be cleared to zero before the request is made.
181 } __attribute__((packed));
184 /* output (size:64b/8B) */
187 * Pass/Fail or error type
189 * Note: receiver to verify the in parameters, and fail the call
190 * with an error when appropriate
193 /* This field returns the type of original request. */
195 /* This field provides original sequence number of the command. */
198 * This field is the length of the response in bytes. The
199 * last byte of the response is a valid flag that will read
200 * as '1' when the command has been completely written to
204 } __attribute__((packed));
206 /* Short Command Structure */
207 /* hwrm_short_input (size:128b/16B) */
208 struct hwrm_short_input {
210 * This field indicates the type of request in the request buffer.
211 * The format for the rest of the command (request) is determined
216 * This field indicates a signature that is used to identify short
217 * form of the command listed here. This field shall be set to
221 /* Signature indicating this is a short form of HWRM command */
222 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
223 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
224 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
225 /* The target ID of the command */
227 /* Default target_id (0x0) to maintain compatibility with old driver */
228 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
229 /* Reserved for user-space HWRM interface */
230 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
231 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
232 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
233 /* This value indicates the length of the request. */
236 * This is the host address where the request was written.
237 * This area must be 16B aligned.
240 } __attribute__((packed));
244 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
245 * # So only structure definition is provided here.
247 /* cmd_nums (size:64b/8B) */
250 * This version of the specification defines the commands listed in
251 * the table below. The following are general implementation
252 * requirements for these commands:
254 * # All commands listed below that are marked neither
255 * reserved nor experimental shall be implemented by the HWRM.
256 * # A HWRM client compliant to this specification should not use
257 * commands outside of the list below.
258 * # A HWRM client compliant to this specification should not use
259 * command numbers marked reserved below.
260 * # A command marked experimental below may not be implemented
262 * # A command marked experimental may change in the
263 * future version of the HWRM specification.
264 * # A command not listed below may be implemented by the HWRM.
265 * The behavior of commands that are not listed below is outside
266 * the scope of this specification.
269 #define HWRM_VER_GET UINT32_C(0x0)
270 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
271 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
272 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
273 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
274 /* Reserved for future use. */
275 #define HWRM_RESERVED1 UINT32_C(0x10)
276 #define HWRM_FUNC_RESET UINT32_C(0x11)
277 #define HWRM_FUNC_GETFID UINT32_C(0x12)
278 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
279 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
280 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
281 #define HWRM_FUNC_QCFG UINT32_C(0x16)
282 #define HWRM_FUNC_CFG UINT32_C(0x17)
283 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
284 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
285 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
286 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
287 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
288 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
289 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
290 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
291 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
292 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
294 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
295 #define HWRM_PORT_QSTATS UINT32_C(0x23)
296 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
298 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
300 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
301 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
302 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
304 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
305 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
306 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
307 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
308 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
309 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
310 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
311 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
312 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
313 #define HWRM_QUEUE_CFG UINT32_C(0x32)
314 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
315 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
316 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
317 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
318 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
319 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
320 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
321 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
323 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 #define HWRM_RING_ALLOC UINT32_C(0x50)
341 #define HWRM_RING_FREE UINT32_C(0x51)
342 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
343 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
344 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
345 #define HWRM_RING_RESET UINT32_C(0x5e)
346 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
347 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
348 /* Reserved for future use. */
349 #define HWRM_RESERVED5 UINT32_C(0x64)
350 /* Reserved for future use. */
351 #define HWRM_RESERVED6 UINT32_C(0x65)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
353 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
354 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
355 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
356 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
357 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
358 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
359 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
360 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
362 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
364 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
365 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
366 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
367 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
369 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
371 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
373 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
374 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
375 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
376 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
377 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
378 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
379 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
380 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
381 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
382 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
383 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
384 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
385 #define HWRM_FW_RESET UINT32_C(0xc0)
386 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
387 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
388 #define HWRM_FW_SYNC UINT32_C(0xc3)
390 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
392 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
394 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
396 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
398 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
399 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
400 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
401 #define HWRM_FWD_RESP UINT32_C(0xd2)
402 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
403 #define HWRM_OEM_CMD UINT32_C(0xd4)
404 /* Tells the fw to run PRBS test on a given port and lane. */
405 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
406 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
407 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
408 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
409 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
410 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
412 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
414 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
416 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
418 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
420 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
422 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
424 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
426 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
428 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
430 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
432 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
434 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
436 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
438 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
440 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
442 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
444 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
446 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
448 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
449 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
450 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
451 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
453 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
455 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
457 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
459 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
460 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
461 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
463 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
465 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
467 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
469 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
471 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
473 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
475 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
477 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
479 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
481 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
483 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
485 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
487 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
489 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
491 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
493 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
495 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
497 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
499 #define HWRM_CFA_TFLIB UINT32_C(0x125)
500 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
501 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
502 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
503 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
504 /* Engine CKV - Add a new CKEK used to encrypt keys. */
505 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
506 /* Engine CKV - Delete a previously added CKEK. */
507 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
508 /* Engine CKV - Add a new key to the key vault. */
509 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
510 /* Engine CKV - Delete a key from the key vault. */
511 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
512 /* Engine CKV - Delete all keys from the key vault. */
513 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
514 /* Engine CKV - Get random data. */
515 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
516 /* Engine CKV - Generate and encrypt a new AES key. */
517 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
518 /* Engine CKV - Configure a label index with a label value. */
519 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
520 /* Engine CKV - Query a label */
521 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
522 /* Engine - Query the available queue groups configuration. */
523 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
524 /* Engine - Query the queue groups assigned to a function. */
525 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
526 /* Engine - Query the available queue group meter profile configuration. */
527 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
528 /* Engine - Query the configuration of a queue group meter profile. */
529 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
530 /* Engine - Allocate a queue group meter profile. */
531 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
532 /* Engine - Free a queue group meter profile. */
533 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
534 /* Engine - Query the meters assigned to a queue group. */
535 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
536 /* Engine - Bind a queue group meter profile to a queue group. */
537 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
538 /* Engine - Unbind a queue group meter profile from a queue group. */
539 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
540 /* Engine - Bind a queue group to a function. */
541 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
542 /* Engine - Query the scheduling group configuration. */
543 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
544 /* Engine - Query the queue groups assigned to a scheduling group. */
545 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
546 /* Engine - Query the configuration of a scheduling group's meter profiles. */
547 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
548 /* Engine - Configure a scheduling group's meter profiles. */
549 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
550 /* Engine - Bind a queue group to a scheduling group. */
551 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
552 /* Engine - Unbind a queue group from its scheduling group. */
553 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
554 /* Engine - Query the Engine configuration. */
555 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
556 /* Engine - Configure the statistics accumulator for an Engine. */
557 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
558 /* Engine - Clear the statistics accumulator for an Engine. */
559 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
560 /* Engine - Query the statistics accumulator for an Engine. */
561 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
562 /* Engine - Allocate an Engine RQ. */
563 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
564 /* Engine - Free an Engine RQ. */
565 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
566 /* Engine - Allocate an Engine CQ. */
567 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
568 /* Engine - Free an Engine CQ. */
569 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
570 /* Engine - Allocate an NQ. */
571 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
572 /* Engine - Free an NQ. */
573 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
574 /* Engine - Set the on-die RQE credit update location. */
575 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
576 /* Engine - Query the engine function configuration. */
577 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
579 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
581 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
583 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
585 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
587 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
588 /* Configures the BW of any VF */
589 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
590 /* Queries the BW of any VF */
591 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
593 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
595 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
597 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
599 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
601 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
603 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
604 /* Returns the current value of a free running counter from the device. */
605 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
607 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
609 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
611 * Tells the fw to run the DMA read from the host and DMA write
614 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
616 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
618 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
620 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
622 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
623 #define HWRM_DBG_DUMP UINT32_C(0xff14)
625 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
627 #define HWRM_DBG_CFG UINT32_C(0xff16)
629 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
631 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
633 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
635 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
637 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
639 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
641 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
643 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
645 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
646 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
647 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
648 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
649 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
650 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
651 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
652 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
653 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
654 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
655 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
656 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
657 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
658 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
659 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
660 #define HWRM_NVM_READ UINT32_C(0xfffd)
661 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
662 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
663 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
664 uint16_t unused_0[3];
665 } __attribute__((packed));
668 /* ret_codes (size:64b/8B) */
671 /* Request was successfully executed by the HWRM. */
672 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
673 /* The HWRM failed to execute the request. */
674 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
676 * The request contains invalid argument(s) or input
679 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
681 * The requester is not allowed to access the requested
682 * resource. This error code shall be provided in a
683 * response to a request to query or modify an existing
684 * resource that is not accessible by the requester.
686 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
688 * The HWRM is unable to allocate the requested resource.
689 * This code only applies to requests for HWRM resource
692 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
694 * Invalid combination of flags is specified in the
697 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
699 * Invalid combination of enables fields is specified in
702 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
704 * Request contains a required TLV that is not supported by
705 * the installed version of firmware.
707 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
709 * No firmware buffer available to accept the request. Driver
710 * should retry the request.
712 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
714 * This error code is only reported by firmware when some
715 * sub-option of a supported HWRM command is unsupported.
717 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
719 * This error code is only reported by firmware when the specific
720 * request is not able to process when the HOT reset in progress.
722 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
724 * This error code is only reported by firmware when the registered
725 * driver instances are not capable of hot reset.
727 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
729 * This error code is only reported by the firmware when during
730 * flow allocation when a requeest for a flow counter fails because
731 * the number of flow counters are exhausted.
733 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
735 * This error code is only reported by firmware when the registered
736 * driver instances requested to offloaded a flow but was unable to because
737 * the requested key's hash collides with the installed keys.
739 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
741 * This error code is only reported by firmware when the registered
742 * driver instances requested to offloaded a flow but was unable to because
743 * the same key has already been installed.
745 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
747 * Generic HWRM execution error that represents an
750 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
752 * This value indicates that the HWRM response is in TLV format and
753 * should be interpreted as one or more TLVs starting with the
754 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
755 * by itself, just an indicatation that the response should be parsed
756 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
758 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
760 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
761 /* Unsupported or invalid command */
762 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
763 #define HWRM_ERR_CODE_LAST \
764 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
765 uint16_t unused_0[3];
766 } __attribute__((packed));
769 /* hwrm_err_output (size:128b/16B) */
770 struct hwrm_err_output {
772 * Pass/Fail or error type
774 * Note: receiver to verify the in parameters, and fail the call
775 * with an error when appropriate
778 /* This field returns the type of original request. */
780 /* This field provides original sequence number of the command. */
783 * This field is the length of the response in bytes. The
784 * last byte of the response is a valid flag that will read
785 * as '1' when the command has been completely written to
789 /* debug info for this error response. */
791 /* debug info for this error response. */
794 * In the case of an error response, command specific error
795 * code is returned in this field.
799 * This field is used in Output records to indicate that the output
800 * is completely written to RAM. This field should be read as '1'
801 * to indicate that the output has been completely written.
802 * When writing a command completion or response to an internal processor,
803 * the order of writes has to be such that this field is written last.
806 } __attribute__((packed));
808 * Following is the signature for HWRM message field that indicates not
809 * applicable (All F's). Need to cast it the size of the field if needed.
811 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
812 /* hwrm_func_buf_rgtr */
813 #define HWRM_MAX_REQ_LEN 128
814 /* hwrm_cfa_flow_info */
815 #define HWRM_MAX_RESP_LEN 704
816 /* 7 bit indirection table index. */
817 #define HW_HASH_INDEX_SIZE 0x80
818 #define HW_HASH_KEY_SIZE 40
819 /* valid key for HWRM response */
820 #define HWRM_RESP_VALID_KEY 1
821 /* Reserved for BONO processor */
822 #define HWRM_TARGET_ID_BONO 0xFFF8
823 /* Reserved for KONG processor */
824 #define HWRM_TARGET_ID_KONG 0xFFF9
825 /* Reserved for APE processor */
826 #define HWRM_TARGET_ID_APE 0xFFFA
828 * This value will be used by tools for User-space HWRM Interface.
829 * When tool execute any HWRM command with this target_id, firmware
830 * will copy the response and/or data payload via register space instead
833 #define HWRM_TARGET_ID_TOOLS 0xFFFD
834 #define HWRM_VERSION_MAJOR 1
835 #define HWRM_VERSION_MINOR 10
836 #define HWRM_VERSION_UPDATE 0
837 /* non-zero means beta version */
838 #define HWRM_VERSION_RSVD 74
839 #define HWRM_VERSION_STR "1.10.0.74"
846 /* hwrm_ver_get_input (size:192b/24B) */
847 struct hwrm_ver_get_input {
848 /* The HWRM command request type. */
851 * The completion ring to send the completion event on. This should
852 * be the NQ ID returned from the `nq_alloc` HWRM command.
856 * The sequence ID is used by the driver for tracking multiple
857 * commands. This ID is treated as opaque data by the firmware and
858 * the value is returned in the `hwrm_resp_hdr` upon completion.
862 * The target ID of the command:
863 * * 0x0-0xFFF8 - The function ID
864 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
865 * * 0xFFFD - Reserved for user-space HWRM interface
870 * A physical address pointer pointing to a host buffer that the
871 * command's response data will be written. This can be either a host
872 * physical address (HPA) or a guest physical address (GPA) and must
873 * point to a physically contiguous block of memory.
877 * This field represents the major version of HWRM interface
878 * specification supported by the driver HWRM implementation.
879 * The interface major version is intended to change only when
880 * non backward compatible changes are made to the HWRM
881 * interface specification.
883 uint8_t hwrm_intf_maj;
885 * This field represents the minor version of HWRM interface
886 * specification supported by the driver HWRM implementation.
887 * A change in interface minor version is used to reflect
888 * significant backward compatible modification to HWRM
889 * interface specification.
890 * This can be due to addition or removal of functionality.
891 * HWRM interface specifications with the same major version
892 * but different minor versions are compatible.
894 uint8_t hwrm_intf_min;
896 * This field represents the update version of HWRM interface
897 * specification supported by the driver HWRM implementation.
898 * The interface update version is used to reflect minor
899 * changes or bug fixes to a released HWRM interface
902 uint8_t hwrm_intf_upd;
904 } __attribute__((packed));
906 /* hwrm_ver_get_output (size:1408b/176B) */
907 struct hwrm_ver_get_output {
908 /* The specific error status for the command. */
910 /* The HWRM command request type. */
912 /* The sequence ID from the original command. */
914 /* The length of the response data in number of bytes. */
917 * This field represents the major version of HWRM interface
918 * specification supported by the HWRM implementation.
919 * The interface major version is intended to change only when
920 * non backward compatible changes are made to the HWRM
921 * interface specification.
922 * A HWRM implementation that is compliant with this
923 * specification shall provide value of 1 in this field.
925 uint8_t hwrm_intf_maj_8b;
927 * This field represents the minor version of HWRM interface
928 * specification supported by the HWRM implementation.
929 * A change in interface minor version is used to reflect
930 * significant backward compatible modification to HWRM
931 * interface specification.
932 * This can be due to addition or removal of functionality.
933 * HWRM interface specifications with the same major version
934 * but different minor versions are compatible.
935 * A HWRM implementation that is compliant with this
936 * specification shall provide value of 2 in this field.
938 uint8_t hwrm_intf_min_8b;
940 * This field represents the update version of HWRM interface
941 * specification supported by the HWRM implementation.
942 * The interface update version is used to reflect minor
943 * changes or bug fixes to a released HWRM interface
945 * A HWRM implementation that is compliant with this
946 * specification shall provide value of 2 in this field.
948 uint8_t hwrm_intf_upd_8b;
949 uint8_t hwrm_intf_rsvd_8b;
951 * This field represents the major version of HWRM firmware.
952 * A change in firmware major version represents a major
955 uint8_t hwrm_fw_maj_8b;
957 * This field represents the minor version of HWRM firmware.
958 * A change in firmware minor version represents significant
959 * firmware functionality changes.
961 uint8_t hwrm_fw_min_8b;
963 * This field represents the build version of HWRM firmware.
964 * A change in firmware build version represents bug fixes
965 * to a released firmware.
967 uint8_t hwrm_fw_bld_8b;
969 * This field is a reserved field. This field can be used to
970 * represent firmware branches or customer specific releases
971 * tied to a specific (major,minor,update) version of the
974 uint8_t hwrm_fw_rsvd_8b;
976 * This field represents the major version of mgmt firmware.
977 * A change in major version represents a major release.
979 uint8_t mgmt_fw_maj_8b;
981 * This field represents the minor version of mgmt firmware.
982 * A change in minor version represents significant
983 * functionality changes.
985 uint8_t mgmt_fw_min_8b;
987 * This field represents the build version of mgmt firmware.
988 * A change in update version represents bug fixes.
990 uint8_t mgmt_fw_bld_8b;
992 * This field is a reserved field. This field can be used to
993 * represent firmware branches or customer specific releases
994 * tied to a specific (major,minor,update) version
996 uint8_t mgmt_fw_rsvd_8b;
998 * This field represents the major version of network
1000 * A change in major version represents a major release.
1002 uint8_t netctrl_fw_maj_8b;
1004 * This field represents the minor version of network
1006 * A change in minor version represents significant
1007 * functionality changes.
1009 uint8_t netctrl_fw_min_8b;
1011 * This field represents the build version of network
1013 * A change in update version represents bug fixes.
1015 uint8_t netctrl_fw_bld_8b;
1017 * This field is a reserved field. This field can be used to
1018 * represent firmware branches or customer specific releases
1019 * tied to a specific (major,minor,update) version
1021 uint8_t netctrl_fw_rsvd_8b;
1023 * This field is used to indicate device's capabilities and
1026 uint32_t dev_caps_cfg;
1028 * If set to 1, then secure firmware update behavior
1030 * If set to 0, then secure firmware update behavior is
1033 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1036 * If set to 1, then firmware based DCBX agent is supported.
1037 * If set to 0, then firmware based DCBX agent capability
1038 * is not supported on this device.
1040 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1043 * If set to 1, then HWRM short command format is supported.
1044 * If set to 0, then HWRM short command format is not supported.
1046 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1049 * If set to 1, then HWRM short command format is required.
1050 * If set to 0, then HWRM short command format is not required.
1052 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1055 * If set to 1, then the KONG host mailbox channel is supported.
1056 * If set to 0, then the KONG host mailbox channel is not supported.
1057 * By default, this flag should be 0 for older version of core firmware.
1059 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1062 * If set to 1, then the 64bit flow handle is supported in addition to the
1063 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1064 * supported. By default, this flag should be 0 for older version of core firmware.
1066 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1069 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1070 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1071 * If set to 0, then filter types not supported.
1072 * By default, this flag should be 0 for older version of core firmware.
1074 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1077 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1078 * If set to 0, firmware can't supported virtio vSwitch offload model.
1079 * By default, this flag should be 0 for older version of core firmware.
1081 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1084 * If set to 1, firmware is capable to support trusted VF.
1085 * If set to 0, firmware is not capable to support trusted VF.
1086 * By default, this flag should be 0 for older version of core firmware.
1088 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1091 * If set to 1, firmware is capable to support flow aging.
1092 * If set to 0, firmware is not capable to support flow aging.
1093 * By default, this flag should be 0 for older version of core firmware.
1095 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1098 * If set to 1, firmware is capable to support advanced flow counters like,
1099 * Meter drop counters and EEM counters.
1100 * If set to 0, firmware is not capable to support advanced flow counters.
1101 * By default, this flag should be 0 for older version of core firmware.
1103 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1106 * If set to 1, the firmware is able to support the use of the CFA
1107 * Extended Exact Match(EEM) feature.
1108 * If set to 0, firmware is not capable to support the use of the
1110 * By default, this flag should be 0 for older version of core firmware.
1112 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1115 * If set to 1, the firmware is able to support advance CFA flow management
1116 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1117 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1119 * By default, this flag should be 0 for older version of core firmware.
1121 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1124 * If set to 1, the firmware is able to support TFLIB features.
1125 * If set to 0, then the firmware doesn’t support TFLIB features.
1126 * By default, this flag should be 0 for older version of core firmware.
1128 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1131 * This field represents the major version of RoCE firmware.
1132 * A change in major version represents a major release.
1134 uint8_t roce_fw_maj_8b;
1136 * This field represents the minor version of RoCE firmware.
1137 * A change in minor version represents significant
1138 * functionality changes.
1140 uint8_t roce_fw_min_8b;
1142 * This field represents the build version of RoCE firmware.
1143 * A change in update version represents bug fixes.
1145 uint8_t roce_fw_bld_8b;
1147 * This field is a reserved field. This field can be used to
1148 * represent firmware branches or customer specific releases
1149 * tied to a specific (major,minor,update) version
1151 uint8_t roce_fw_rsvd_8b;
1153 * This field represents the name of HWRM FW (ASCII chars
1154 * with NULL at the end).
1156 char hwrm_fw_name[16];
1158 * This field represents the name of mgmt FW (ASCII chars
1159 * with NULL at the end).
1161 char mgmt_fw_name[16];
1163 * This field represents the name of network control
1164 * firmware (ASCII chars with NULL at the end).
1166 char netctrl_fw_name[16];
1167 /* This field represents the active board package name. */
1168 char active_pkg_name[16];
1170 * This field represents the name of RoCE FW (ASCII chars
1171 * with NULL at the end).
1173 char roce_fw_name[16];
1174 /* This field returns the chip number. */
1176 /* This field returns the revision of chip. */
1178 /* This field returns the chip metal number. */
1180 /* This field returns the bond id of the chip. */
1181 uint8_t chip_bond_id;
1182 /* This value indicates the type of platform used for chip implementation. */
1183 uint8_t chip_platform_type;
1185 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1186 /* FPGA platform of the chip. */
1187 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1188 /* Palladium platform of the chip. */
1189 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1190 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1191 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1193 * This field returns the maximum value of request window that
1194 * is supported by the HWRM. The request window is mapped
1195 * into device address space using MMIO.
1197 uint16_t max_req_win_len;
1199 * This field returns the maximum value of response buffer in
1202 uint16_t max_resp_len;
1204 * This field returns the default request timeout value in
1207 uint16_t def_req_timeout;
1209 * This field will indicate if any subsystems is not fully
1214 * If set to 1, device is not ready.
1215 * If set to 0, device is ready to accept all HWRM commands.
1217 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1219 * If set to 1, external version present.
1220 * If set to 0, external version not present.
1222 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1223 uint8_t unused_0[2];
1225 * For backward compatibility this field must be set to 1.
1226 * Older drivers might look for this field to be 1 before
1227 * processing the message.
1231 * This field represents the major version of HWRM interface
1232 * specification supported by the HWRM implementation.
1233 * The interface major version is intended to change only when
1234 * non backward compatible changes are made to the HWRM
1235 * interface specification. A HWRM implementation that is
1236 * compliant with this specification shall provide value of 1
1239 uint16_t hwrm_intf_major;
1241 * This field represents the minor version of HWRM interface
1242 * specification supported by the HWRM implementation.
1243 * A change in interface minor version is used to reflect
1244 * significant backward compatible modification to HWRM
1245 * interface specification. This can be due to addition or
1246 * removal of functionality. HWRM interface specifications
1247 * with the same major version but different minor versions are
1248 * compatible. A HWRM implementation that is compliant with
1249 * this specification shall provide value of 2 in this field.
1251 uint16_t hwrm_intf_minor;
1253 * This field represents the update version of HWRM interface
1254 * specification supported by the HWRM implementation. The
1255 * interface update version is used to reflect minor changes or
1256 * bug fixes to a released HWRM interface specification.
1257 * A HWRM implementation that is compliant with this
1258 * specification shall provide value of 2 in this field.
1260 uint16_t hwrm_intf_build;
1262 * This field represents the patch version of HWRM interface
1263 * specification supported by the HWRM implementation.
1265 uint16_t hwrm_intf_patch;
1267 * This field represents the major version of HWRM firmware.
1268 * A change in firmware major version represents a major
1271 uint16_t hwrm_fw_major;
1273 * This field represents the minor version of HWRM firmware.
1274 * A change in firmware minor version represents significant
1275 * firmware functionality changes.
1277 uint16_t hwrm_fw_minor;
1279 * This field represents the build version of HWRM firmware.
1280 * A change in firmware build version represents bug fixes to
1281 * a released firmware.
1283 uint16_t hwrm_fw_build;
1285 * This field is a reserved field.
1286 * This field can be used to represent firmware branches or customer
1287 * specific releases tied to a specific (major,minor,update) version
1288 * of the HWRM firmware.
1290 uint16_t hwrm_fw_patch;
1292 * This field represents the major version of mgmt firmware.
1293 * A change in major version represents a major release.
1295 uint16_t mgmt_fw_major;
1297 * This field represents the minor version of HWRM firmware.
1298 * A change in firmware minor version represents significant
1299 * firmware functionality changes.
1301 uint16_t mgmt_fw_minor;
1303 * This field represents the build version of mgmt firmware.
1304 * A change in update version represents bug fixes.
1306 uint16_t mgmt_fw_build;
1308 * This field is a reserved field. This field can be used to
1309 * represent firmware branches or customer specific releases
1310 * tied to a specific (major,minor,update) version.
1312 uint16_t mgmt_fw_patch;
1314 * This field represents the major version of network control
1315 * firmware. A change in major version represents
1318 uint16_t netctrl_fw_major;
1320 * This field represents the minor version of network control
1321 * firmware. A change in minor version represents significant
1322 * functionality changes.
1324 uint16_t netctrl_fw_minor;
1326 * This field represents the build version of network control
1327 * firmware. A change in update version represents bug fixes.
1329 uint16_t netctrl_fw_build;
1331 * This field is a reserved field. This field can be used to
1332 * represent firmware branches or customer specific releases
1333 * tied to a specific (major,minor,update) version
1335 uint16_t netctrl_fw_patch;
1337 * This field represents the major version of RoCE firmware.
1338 * A change in major version represents a major release.
1340 uint16_t roce_fw_major;
1342 * This field represents the minor version of RoCE firmware.
1343 * A change in minor version represents significant
1344 * functionality changes.
1346 uint16_t roce_fw_minor;
1348 * This field represents the build version of RoCE firmware.
1349 * A change in update version represents bug fixes.
1351 uint16_t roce_fw_build;
1353 * This field is a reserved field. This field can be used to
1354 * represent firmware branches or customer specific releases
1355 * tied to a specific (major,minor,update) version
1357 uint16_t roce_fw_patch;
1359 * This field returns the maximum extended request length acceptable
1360 * by the device which allows requests greater than mailbox size when
1361 * used with the short cmd request format.
1363 uint16_t max_ext_req_len;
1364 uint8_t unused_1[5];
1366 * This field is used in Output records to indicate that the output
1367 * is completely written to RAM. This field should be read as '1'
1368 * to indicate that the output has been completely written.
1369 * When writing a command completion or response to an internal processor,
1370 * the order of writes has to be such that this field is written last.
1373 } __attribute__((packed));
1375 /* bd_base (size:64b/8B) */
1378 /* This value identifies the type of buffer descriptor. */
1379 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1380 #define BD_BASE_TYPE_SFT 0
1382 * Indicates that this BD is 16B long and is used for
1383 * normal L2 packet transmission.
1385 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1387 * Indicates that this BD is 1BB long and is an empty
1388 * TX BD. Not valid for use by the driver.
1390 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1392 * Indicates that this BD is 16B long and is an RX Producer
1393 * (ie. empty) buffer descriptor.
1395 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1397 * Indicates that this BD is 16B long and is an RX
1398 * Producer Buffer BD.
1400 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1402 * Indicates that this BD is 16B long and is an
1403 * RX Producer Assembly Buffer Descriptor.
1405 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1407 * Indicates that this BD is 32B long and is used for
1408 * normal L2 packet transmission.
1410 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1412 * Indicates that this BD is 32B long and is used for
1413 * L2 packet transmission for small packets that require
1416 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1417 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1418 uint8_t unused_1[7];
1419 } __attribute__((packed));
1421 /* tx_bd_short (size:128b/16B) */
1422 struct tx_bd_short {
1424 * All bits in this field must be valid on the first BD of a packet.
1425 * Only the packet_end bit must be valid for the remaining BDs
1428 uint16_t flags_type;
1429 /* This value identifies the type of buffer descriptor. */
1430 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1431 #define TX_BD_SHORT_TYPE_SFT 0
1433 * Indicates that this BD is 16B long and is used for
1434 * normal L2 packet transmission.
1436 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1437 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1439 * All bits in this field must be valid on the first BD of a packet.
1440 * Only the packet_end bit must be valid for the remaining BDs
1443 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1444 #define TX_BD_SHORT_FLAGS_SFT 6
1446 * If set to 1, the packet ends with the data in the buffer
1447 * pointed to by this descriptor. This flag must be
1448 * valid on every BD.
1450 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1452 * If set to 1, the device will not generate a completion for
1453 * this transmit packet unless there is an error in it's
1456 * is set to 0, then the packet will be completed normally.
1458 * This bit must be valid only on the first BD of a packet.
1460 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1462 * This value indicates how many 16B BD locations are consumed
1463 * in the ring by this packet.
1464 * A value of 1 indicates that this BD is the only BD (and that
1465 * the it is a short BD). A value
1466 * of 3 indicates either 3 short BDs or 1 long BD and one short
1467 * BD in the packet. A value of 0 indicates
1468 * that there are 32 BD locations in the packet (the maximum).
1470 * This field is valid only on the first BD of a packet.
1472 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1473 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1475 * This value is a hint for the length of the entire packet.
1476 * It is used by the chip to optimize internal processing.
1478 * The packet will be dropped if the hint is too short.
1480 * This field is valid only on the first BD of a packet.
1482 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1483 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1484 /* indicates packet length < 512B */
1485 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1486 /* indicates 512 <= packet length < 1KB */
1487 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1488 /* indicates 1KB <= packet length < 2KB */
1489 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1490 /* indicates packet length >= 2KB */
1491 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1492 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1493 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1495 * If set to 1, the device immediately updates the Send Consumer
1496 * Index after the buffer associated with this descriptor has
1497 * been transferred via DMA to NIC memory from host memory. An
1498 * interrupt may or may not be generated according to the state
1499 * of the interrupt avoidance mechanisms. If this bit
1500 * is set to 0, then the Consumer Index is only updated as soon
1501 * as one of the host interrupt coalescing conditions has been met.
1503 * This bit must be valid on the first BD of a packet.
1505 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1507 * This is the length of the host physical buffer this BD describes
1510 * This field must be valid on all BDs of a packet.
1514 * The opaque data field is pass through to the completion and can be
1515 * used for any data that the driver wants to associate with the
1518 * This field must be valid on the first BD of a packet.
1522 * This is the host physical address for the portion of the packet
1523 * described by this TX BD.
1525 * This value must be valid on all BDs of a packet.
1528 } __attribute__((packed));
1530 /* tx_bd_long (size:128b/16B) */
1532 /* This value identifies the type of buffer descriptor. */
1533 uint16_t flags_type;
1535 * This value indicates the type of buffer descriptor.
1538 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1539 #define TX_BD_LONG_TYPE_SFT 0
1541 * Indicates that this BD is 32B long and is used for
1542 * normal L2 packet transmission.
1544 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1545 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1547 * All bits in this field must be valid on the first BD of a packet.
1548 * Only the packet_end bit must be valid for the remaining BDs
1551 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1552 #define TX_BD_LONG_FLAGS_SFT 6
1554 * If set to 1, the packet ends with the data in the buffer
1555 * pointed to by this descriptor. This flag must be
1556 * valid on every BD.
1558 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1560 * If set to 1, the device will not generate a completion for
1561 * this transmit packet unless there is an error in it's
1564 * is set to 0, then the packet will be completed normally.
1566 * This bit must be valid only on the first BD of a packet.
1568 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1570 * This value indicates how many 16B BD locations are consumed
1571 * in the ring by this packet.
1572 * A value of 1 indicates that this BD is the only BD (and that
1573 * the it is a short BD). A value
1574 * of 3 indicates either 3 short BDs or 1 long BD and one short
1575 * BD in the packet. A value of 0 indicates
1576 * that there are 32 BD locations in the packet (the maximum).
1578 * This field is valid only on the first BD of a packet.
1580 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1581 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1583 * This value is a hint for the length of the entire packet.
1584 * It is used by the chip to optimize internal processing.
1586 * The packet will be dropped if the hint is too short.
1588 * This field is valid only on the first BD of a packet.
1590 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1591 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1592 /* indicates packet length < 512B */
1593 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1594 /* indicates 512 <= packet length < 1KB */
1595 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1596 /* indicates 1KB <= packet length < 2KB */
1597 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1598 /* indicates packet length >= 2KB */
1599 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1600 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1602 * If set to 1, the device immediately updates the Send Consumer
1603 * Index after the buffer associated with this descriptor has
1604 * been transferred via DMA to NIC memory from host memory. An
1605 * interrupt may or may not be generated according to the state
1606 * of the interrupt avoidance mechanisms. If this bit
1607 * is set to 0, then the Consumer Index is only updated as soon
1608 * as one of the host interrupt coalescing conditions has been met.
1610 * This bit must be valid on the first BD of a packet.
1612 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1614 * This is the length of the host physical buffer this BD describes
1617 * This field must be valid on all BDs of a packet.
1621 * The opaque data field is pass through to the completion and can be
1622 * used for any data that the driver wants to associate with the
1625 * This field must be valid on the first BD of a packet.
1629 * This is the host physical address for the portion of the packet
1630 * described by this TX BD.
1632 * This value must be valid on all BDs of a packet.
1635 } __attribute__((packed));
1637 /* Last 16 bytes of tx_bd_long. */
1638 /* tx_bd_long_hi (size:128b/16B) */
1639 struct tx_bd_long_hi {
1641 * All bits in this field must be valid on the first BD of a packet.
1642 * Their value on other BDs of the packet will be ignored.
1646 * If set to 1, the controller replaces the TCP/UPD checksum
1647 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1648 * checksum field of the encapsulated TCP/UDP packets with the
1649 * hardware calculated TCP/UDP checksum for the packet associated
1650 * with this descriptor. The flag is ignored if the LSO flag is set.
1652 * This bit must be valid on the first BD of a packet.
1654 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1656 * If set to 1, the controller replaces the IP checksum of the
1657 * normal packets, or the inner IP checksum of the encapsulated
1658 * packets with the hardware calculated IP checksum for the
1659 * packet associated with this descriptor.
1661 * This bit must be valid on the first BD of a packet.
1663 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1665 * If set to 1, the controller will not append an Ethernet CRC
1666 * to the end of the frame.
1668 * This bit must be valid on the first BD of a packet.
1670 * Packet must be 64B or longer when this flag is set. It is not
1671 * useful to use this bit with any form of TX offload such as
1672 * CSO or LSO. The intent is that the packet from the host already
1673 * has a valid Ethernet CRC on the packet.
1675 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1677 * If set to 1, the device will record the time at which the packet
1678 * was actually transmitted at the TX MAC.
1680 * This bit must be valid on the first BD of a packet.
1682 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1684 * If set to 1, The controller replaces the tunnel IP checksum
1685 * field with hardware calculated IP checksum for the IP header
1686 * of the packet associated with this descriptor.
1688 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1689 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1690 * bit is set, outer UDP checksum will be calculated for the following
1692 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1693 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1694 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1695 * checksum will not be calculated.
1696 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1697 * as part of LSO operation.
1699 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1701 * If set to 1, the device will treat this packet with LSO(Large
1702 * Send Offload) processing for both normal or encapsulated
1703 * packets, which is a form of TCP segmentation. When this bit
1704 * is 1, the hdr_size and mss fields must be valid. The driver
1705 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1706 * flags since the controller will replace the appropriate
1707 * checksum fields for segmented packets.
1709 * When this bit is 1, the hdr_size and mss fields must be valid.
1711 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1713 * If set to zero when LSO is '1', then the IPID will be treated
1714 * as a 16b number and will be wrapped if it exceeds a value of
1717 * If set to one when LSO is '1', then the IPID will be treated
1718 * as a 15b number and will be wrapped if it exceeds a value 0f
1721 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1723 * If set to zero when LSO is '1', then the IPID of the tunnel
1724 * IP header will not be modified during LSO operations.
1726 * If set to one when LSO is '1', then the IPID of the tunnel
1727 * IP header will be incremented for each subsequent segment of an
1730 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1733 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1735 * If set to '1', then the RoCE ICRC will be appended to the
1736 * packet. Packet must be a valid RoCE format packet.
1738 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1740 * If set to '1', then the FCoE CRC will be appended to the
1741 * packet. Packet must be a valid FCoE format packet.
1743 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1746 * When LSO is '1', this field must contain the offset of the
1747 * TCP payload from the beginning of the packet in as
1748 * 16b words. In case of encapsulated/tunneling packet, this field
1749 * contains the offset of the inner TCP payload from beginning of the
1750 * packet as 16-bit words.
1752 * This value must be valid on the first BD of a packet.
1754 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1755 #define TX_BD_LONG_HDR_SIZE_SFT 0
1758 * This is the MSS value that will be used to do the LSO processing.
1759 * The value is the length in bytes of the TCP payload for each
1760 * segment generated by the LSO operation.
1762 * This value must be valid on the first BD of a packet.
1764 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1765 #define TX_BD_LONG_MSS_SFT 0
1768 * This value selects a CFA action to perform on the packet.
1769 * Set this value to zero if no CFA action is desired.
1771 * This value must be valid on the first BD of a packet.
1773 uint16_t cfa_action;
1775 * This value is action meta-data that defines CFA edit operations
1776 * that are done in addition to any action editing.
1779 /* When key=1, This is the VLAN tag VID value. */
1780 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1781 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1782 /* When key=1, This is the VLAN tag DE value. */
1783 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1784 /* When key=1, This is the VLAN tag PRI value. */
1785 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1786 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1787 /* When key=1, This is the VLAN tag TPID select value. */
1788 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1789 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1791 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1793 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1795 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1797 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1799 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1800 /* Value programmed in CFA VLANTPID register. */
1801 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1802 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1803 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1804 /* When key=1, This is the VLAN tag TPID select value. */
1805 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1806 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1808 * This field identifies the type of edit to be performed
1811 * This value must be valid on the first BD of a packet.
1813 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1814 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1816 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1818 * - meta[17:16] - TPID select value (0 = 0x8100).
1819 * - meta[15:12] - PRI/DE value.
1820 * - meta[11:0] - VID value.
1822 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1823 #define TX_BD_LONG_CFA_META_KEY_LAST \
1824 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1825 } __attribute__((packed));
1828 * This structure is used to inform the NIC of packet data that needs to be
1829 * transmitted with additional processing that requires extra data such as
1830 * VLAN insertion plus attached inline data. This BD type may be used to
1831 * improve latency for small packets needing the additional extended features
1832 * supported by long BDs.
1834 /* tx_bd_long_inline (size:256b/32B) */
1835 struct tx_bd_long_inline {
1836 uint16_t flags_type;
1837 /* This value identifies the type of buffer descriptor. */
1838 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1839 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1841 * This type of BD is 32B long and is used for inline L2 packet
1844 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1845 #define TX_BD_LONG_INLINE_TYPE_LAST \
1846 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1848 * All bits in this field may be set on the first BD of a packet.
1849 * Only the packet_end bit may be set in non-first BDs.
1851 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1852 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1854 * If set to 1, the packet ends with the data in the buffer
1855 * pointed to by this descriptor. This flag must be
1856 * valid on every BD.
1858 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1860 * If set to 1, the device will not generate a completion for
1861 * this transmit packet unless there is an error in its processing.
1862 * If this bit is set to 0, then the packet will be completed
1865 * This bit may be set only on the first BD of a packet.
1867 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1869 * This value indicates how many 16B BD locations are consumed
1870 * in the ring by this packet, including the BD and inline
1873 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1874 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1875 /* This field is deprecated. */
1876 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1877 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1879 * If set to 1, the device immediately updates the Send Consumer
1880 * Index after the buffer associated with this descriptor has
1881 * been transferred via DMA to NIC memory from host memory. An
1882 * interrupt may or may not be generated according to the state
1883 * of the interrupt avoidance mechanisms. If this bit
1884 * is set to 0, then the Consumer Index is only updated as soon
1885 * as one of the host interrupt coalescing conditions has been met.
1887 * This bit must be valid on the first BD of a packet.
1889 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1891 * This is the length of the inline data, not including BD length, in
1893 * The maximum value is 480.
1895 * This field must be valid on all BDs of a packet.
1899 * The opaque data field is passed through to the completion and can be
1900 * used for any data that the driver wants to associate with the transmit
1903 * This field must be valid on the first BD of a packet.
1908 * All bits in this field must be valid on the first BD of a packet.
1909 * Their value on other BDs of the packet is ignored.
1913 * If set to 1, the controller replaces the TCP/UPD checksum
1914 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1915 * checksum field of the encapsulated TCP/UDP packets with the
1916 * hardware calculated TCP/UDP checksum for the packet associated
1917 * with this descriptor. The flag is ignored if the LSO flag is set.
1919 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1921 * If set to 1, the controller replaces the IP checksum of the
1922 * normal packets, or the inner IP checksum of the encapsulated
1923 * packets with the hardware calculated IP checksum for the
1924 * packet associated with this descriptor.
1926 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1928 * If set to 1, the controller will not append an Ethernet CRC
1929 * to the end of the frame.
1931 * Packet must be 64B or longer when this flag is set. It is not
1932 * useful to use this bit with any form of TX offload such as
1933 * CSO or LSO. The intent is that the packet from the host already
1934 * has a valid Ethernet CRC on the packet.
1936 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1938 * If set to 1, the device will record the time at which the packet
1939 * was actually transmitted at the TX MAC.
1941 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1943 * If set to 1, the controller replaces the tunnel IP checksum
1944 * field with hardware calculated IP checksum for the IP header
1945 * of the packet associated with this descriptor. The hardware
1946 * updates an outer UDP checksum if it is non-zero.
1948 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1950 * This bit must be 0 for BDs of this type. LSO is not supported with
1953 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1954 /* Since LSO is not supported with inline BDs, this bit is not used. */
1955 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1956 /* Since LSO is not supported with inline BDs, this bit is not used. */
1957 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1959 * If set to '1', then the RoCE ICRC will be appended to the
1960 * packet. Packet must be a valid RoCE format packet.
1962 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1964 * If set to '1', then the FCoE CRC will be appended to the
1965 * packet. Packet must be a valid FCoE format packet.
1967 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1972 * This value selects a CFA action to perform on the packet.
1973 * Set this value to zero if no CFA action is desired.
1975 * This value must be valid on the first BD of a packet.
1977 uint16_t cfa_action;
1979 * This value is action meta-data that defines CFA edit operations
1980 * that are done in addition to any action editing.
1983 /* When key = 1, this is the VLAN tag VID value. */
1984 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1985 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1986 /* When key = 1, this is the VLAN tag DE value. */
1987 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1988 /* When key = 1, this is the VLAN tag PRI value. */
1989 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1990 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
1991 /* When key = 1, this is the VLAN tag TPID select value. */
1992 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1993 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
1995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
1996 (UINT32_C(0x0) << 16)
1998 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
1999 (UINT32_C(0x1) << 16)
2001 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2002 (UINT32_C(0x2) << 16)
2004 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2005 (UINT32_C(0x3) << 16)
2007 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2008 (UINT32_C(0x4) << 16)
2009 /* Value programmed in CFA VLANTPID register. */
2010 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2011 (UINT32_C(0x5) << 16)
2012 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2013 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2014 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2016 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2018 * This field identifies the type of edit to be performed
2021 * This value must be valid on the first BD of a packet.
2023 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2024 UINT32_C(0xf0000000)
2025 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2027 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2028 (UINT32_C(0x0) << 28)
2030 * - meta[17:16] - TPID select value (0 = 0x8100).
2031 * - meta[15:12] - PRI/DE value.
2032 * - meta[11:0] - VID value.
2034 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2035 (UINT32_C(0x1) << 28)
2036 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2037 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2038 } __attribute__((packed));
2040 /* tx_bd_empty (size:128b/16B) */
2041 struct tx_bd_empty {
2042 /* This value identifies the type of buffer descriptor. */
2044 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2045 #define TX_BD_EMPTY_TYPE_SFT 0
2047 * Indicates that this BD is 1BB long and is an empty
2048 * TX BD. Not valid for use by the driver.
2050 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2051 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2052 uint8_t unused_1[3];
2054 uint8_t unused_3[3];
2055 uint8_t unused_4[8];
2056 } __attribute__((packed));
2058 /* rx_prod_pkt_bd (size:128b/16B) */
2059 struct rx_prod_pkt_bd {
2060 /* This value identifies the type of buffer descriptor. */
2061 uint16_t flags_type;
2062 /* This value identifies the type of buffer descriptor. */
2063 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2064 #define RX_PROD_PKT_BD_TYPE_SFT 0
2066 * Indicates that this BD is 16B long and is an RX Producer
2067 * (ie. empty) buffer descriptor.
2069 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2070 #define RX_PROD_PKT_BD_TYPE_LAST \
2071 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2072 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2073 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2075 * If set to 1, the packet will be placed at the address plus
2076 * 2B. The 2 Bytes of padding will be written as zero.
2078 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2080 * If set to 1, the packet write will be padded out to the
2081 * nearest cache-line with zero value padding.
2083 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2085 * This value is the number of additional buffers in the ring that
2086 * describe the buffer space to be consumed for the this packet.
2087 * If the value is zero, then the packet must fit within the
2088 * space described by this BD. If this value is 1 or more, it
2089 * indicates how many additional "buffer" BDs are in the ring
2090 * immediately following this BD to be used for the same
2093 * Even if the packet to be placed does not need all the
2094 * additional buffers, they will be consumed anyway.
2096 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2097 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2099 * This is the length in Bytes of the host physical buffer where
2100 * data for the packet may be placed in host memory.
2104 * The opaque data field is pass through to the completion and can be
2105 * used for any data that the driver wants to associate with this
2106 * receive buffer set.
2110 * This is the host physical address where data for the packet may
2111 * by placed in host memory.
2114 } __attribute__((packed));
2116 /* rx_prod_bfr_bd (size:128b/16B) */
2117 struct rx_prod_bfr_bd {
2118 /* This value identifies the type of buffer descriptor. */
2119 uint16_t flags_type;
2120 /* This value identifies the type of buffer descriptor. */
2121 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2122 #define RX_PROD_BFR_BD_TYPE_SFT 0
2124 * Indicates that this BD is 16B long and is an RX
2125 * Producer Buffer BD.
2127 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2128 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2129 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2130 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2132 * This is the length in Bytes of the host physical buffer where
2133 * data for the packet may be placed in host memory.
2136 /* This field is not used. */
2139 * This is the host physical address where data for the packet may
2140 * by placed in host memory.
2143 } __attribute__((packed));
2145 /* rx_prod_agg_bd (size:128b/16B) */
2146 struct rx_prod_agg_bd {
2147 /* This value identifies the type of buffer descriptor. */
2148 uint16_t flags_type;
2149 /* This value identifies the type of buffer descriptor. */
2150 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2151 #define RX_PROD_AGG_BD_TYPE_SFT 0
2153 * Indicates that this BD is 16B long and is an
2154 * RX Producer Assembly Buffer Descriptor.
2156 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2157 #define RX_PROD_AGG_BD_TYPE_LAST \
2158 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2159 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2160 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2162 * If set to 1, the packet write will be padded out to the
2163 * nearest cache-line with zero value padding.
2165 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2167 * This is the length in Bytes of the host physical buffer where
2168 * data for the packet may be placed in host memory.
2172 * The opaque data field is pass through to the completion and can be
2173 * used for any data that the driver wants to associate with this
2174 * receive assembly buffer.
2178 * This is the host physical address where data for the packet may
2179 * by placed in host memory.
2182 } __attribute__((packed));
2184 /* cmpl_base (size:128b/16B) */
2188 * This field indicates the exact type of the completion.
2189 * By convention, the LSB identifies the length of the
2190 * record in 16B units. Even values indicate 16B
2191 * records. Odd values indicate 32B
2194 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2195 #define CMPL_BASE_TYPE_SFT 0
2198 * Completion of TX packet. Length = 16B
2200 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2203 * Completion of and L2 RX packet. Length = 32B
2205 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2207 * RX Aggregation Buffer completion :
2208 * Completion of an L2 aggregation buffer in support of
2209 * TPA, HDS, or Jumbo packet completion. Length = 16B
2211 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2213 * RX L2 TPA Start Completion:
2214 * Completion at the beginning of a TPA operation.
2217 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2219 * RX L2 TPA End Completion:
2220 * Completion at the end of a TPA operation.
2223 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2225 * Statistics Ejection Completion:
2226 * Completion of statistics data ejection buffer.
2229 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2231 * HWRM Command Completion:
2232 * Completion of an HWRM command.
2234 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2235 /* Forwarded HWRM Request */
2236 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2237 /* Forwarded HWRM Response */
2238 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2239 /* HWRM Asynchronous Event Information */
2240 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2241 /* CQ Notification */
2242 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2243 /* SRQ Threshold Event */
2244 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2245 /* DBQ Threshold Event */
2246 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2247 /* QP Async Notification */
2248 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2249 /* Function Async Notification */
2250 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2251 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2257 * This value is written by the NIC such that it will be different
2258 * for each pass through the completion queue. The even passes
2259 * will write 1. The odd passes will write 0.
2262 #define CMPL_BASE_V UINT32_C(0x1)
2263 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2264 #define CMPL_BASE_INFO3_SFT 1
2267 } __attribute__((packed));
2269 /* tx_cmpl (size:128b/16B) */
2271 uint16_t flags_type;
2273 * This field indicates the exact type of the completion.
2274 * By convention, the LSB identifies the length of the
2275 * record in 16B units. Even values indicate 16B
2276 * records. Odd values indicate 32B
2279 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2280 #define TX_CMPL_TYPE_SFT 0
2283 * Completion of TX packet. Length = 16B
2285 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2286 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2287 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2288 #define TX_CMPL_FLAGS_SFT 6
2290 * When this bit is '1', it indicates a packet that has an
2291 * error of some type. Type of error is indicated in
2294 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2296 * When this bit is '1', it indicates that the packet completed
2297 * was transmitted using the push acceleration data provided
2298 * by the driver. When this bit is '0', it indicates that the
2299 * packet had not push acceleration data written or was executed
2300 * as a normal packet even though push data was provided.
2302 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2303 /* unused1 is 16 b */
2306 * This is a copy of the opaque field from the first TX BD of this
2307 * transmitted packet.
2312 * This value is written by the NIC such that it will be different
2313 * for each pass through the completion queue. The even passes
2314 * will write 1. The odd passes will write 0.
2316 #define TX_CMPL_V UINT32_C(0x1)
2317 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2318 #define TX_CMPL_ERRORS_SFT 1
2320 * This error indicates that there was some sort of problem
2321 * with the BDs for the packet.
2323 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2324 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2326 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2329 * BDs were not formatted correctly.
2331 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2332 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2333 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2335 * When this bit is '1', it indicates that the length of
2336 * the packet was zero. No packet was transmitted.
2338 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2340 * When this bit is '1', it indicates that the packet
2341 * was longer than the programmed limit in TDI. No
2342 * packet was transmitted.
2344 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2346 * When this bit is '1', it indicates that one or more of the
2347 * BDs associated with this packet generated a PCI error.
2348 * This probably means the address was not valid.
2350 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2352 * When this bit is '1', it indicates that the packet was longer
2353 * than indicated by the hint. No packet was transmitted.
2355 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2357 * When this bit is '1', it indicates that the packet was
2358 * dropped due to Poison TLP error on one or more of the
2359 * TLPs in the PXP completion.
2361 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2362 /* unused2 is 16 b */
2364 /* unused3 is 32 b */
2366 } __attribute__((packed));
2368 /* rx_pkt_cmpl (size:128b/16B) */
2369 struct rx_pkt_cmpl {
2370 uint16_t flags_type;
2372 * This field indicates the exact type of the completion.
2373 * By convention, the LSB identifies the length of the
2374 * record in 16B units. Even values indicate 16B
2375 * records. Odd values indicate 32B
2378 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2379 #define RX_PKT_CMPL_TYPE_SFT 0
2382 * Completion of and L2 RX packet. Length = 32B
2384 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2385 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2386 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2387 #define RX_PKT_CMPL_FLAGS_SFT 6
2389 * When this bit is '1', it indicates a packet that has an
2390 * error of some type. Type of error is indicated in
2393 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2394 /* This field indicates how the packet was placed in the buffer. */
2395 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2396 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2399 * Packet was placed using normal algorithm.
2401 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2404 * Packet was placed using jumbo algorithm.
2406 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2408 * Header/Data Separation:
2409 * Packet was placed using Header/Data separation algorithm.
2410 * The separation location is indicated by the itype field.
2412 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2413 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2414 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2415 /* This bit is '1' if the RSS field in this completion is valid. */
2416 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2418 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2420 * This value indicates what the inner packet determined for the
2423 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2424 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2427 * Indicates that the packet type was not known.
2429 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2430 (UINT32_C(0x0) << 12)
2433 * Indicates that the packet was an IP packet, but further
2434 * classification was not possible.
2436 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2437 (UINT32_C(0x1) << 12)
2440 * Indicates that the packet was IP and TCP.
2441 * This indicates that the payload_offset field is valid.
2443 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2444 (UINT32_C(0x2) << 12)
2447 * Indicates that the packet was IP and UDP.
2448 * This indicates that the payload_offset field is valid.
2450 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2451 (UINT32_C(0x3) << 12)
2454 * Indicates that the packet was recognized as a FCoE.
2455 * This also indicates that the payload_offset field is valid.
2457 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2458 (UINT32_C(0x4) << 12)
2461 * Indicates that the packet was recognized as a RoCE.
2462 * This also indicates that the payload_offset field is valid.
2464 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2465 (UINT32_C(0x5) << 12)
2468 * Indicates that the packet was recognized as ICMP.
2469 * This indicates that the payload_offset field is valid.
2471 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2472 (UINT32_C(0x7) << 12)
2474 * PtP packet wo/timestamp:
2475 * Indicates that the packet was recognized as a PtP
2478 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2479 (UINT32_C(0x8) << 12)
2481 * PtP packet w/timestamp:
2482 * Indicates that the packet was recognized as a PtP
2483 * packet and that a timestamp was taken for the packet.
2485 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2486 (UINT32_C(0x9) << 12)
2487 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2488 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2490 * This is the length of the data for the packet stored in the
2491 * buffer(s) identified by the opaque value. This includes
2492 * the packet BD and any associated buffer BDs. This does not include
2493 * the the length of any data places in aggregation BDs.
2497 * This is a copy of the opaque field from the RX BD this completion
2501 uint8_t agg_bufs_v1;
2503 * This value is written by the NIC such that it will be different
2504 * for each pass through the completion queue. The even passes
2505 * will write 1. The odd passes will write 0.
2507 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2509 * This value is the number of aggregation buffers that follow this
2510 * entry in the completion ring that are a part of this packet.
2511 * If the value is zero, then the packet is completely contained
2512 * in the buffer space provided for the packet in the RX ring.
2514 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2515 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2516 /* unused1 is 2 b */
2517 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2518 #define RX_PKT_CMPL_UNUSED1_SFT 6
2520 * This is the RSS hash type for the packet. The value is packed
2521 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2523 * The value of tuple_extrac_op provides the information about
2524 * what fields the hash was computed on.
2525 * * 0: The RSS hash was computed over source IP address,
2526 * destination IP address, source port, and destination port of inner
2527 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2528 * the packet headers are considered inner packet headers for the RSS
2529 * hash computation purpose.
2530 * * 1: The RSS hash was computed over source IP address and destination
2531 * IP address of inner IP header. Note: For non-tunneled packets,
2532 * the packet headers are considered inner packet headers for the RSS
2533 * hash computation purpose.
2534 * * 2: The RSS hash was computed over source IP address,
2535 * destination IP address, source port, and destination port of
2536 * IP and TCP or UDP headers of outer tunnel headers.
2537 * Note: For non-tunneled packets, this value is not applicable.
2538 * * 3: The RSS hash was computed over source IP address and
2539 * destination IP address of IP header of outer tunnel headers.
2540 * Note: For non-tunneled packets, this value is not applicable.
2542 * Note that 4-tuples values listed above are applicable
2543 * for layer 4 protocols supported and enabled for RSS in the hardware,
2544 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2545 * enabled for TCP traffic only, then the values of tuple_extract_op
2546 * corresponding to 4-tuples are only valid for TCP traffic.
2548 uint8_t rss_hash_type;
2550 * This value indicates the offset in bytes from the beginning of the packet
2551 * where the inner payload starts. This value is valid for TCP, UDP,
2552 * FCoE, and RoCE packets.
2554 * A value of zero indicates that header is 256B into the packet.
2556 uint8_t payload_offset;
2557 /* unused2 is 8 b */
2560 * This value is the RSS hash value calculated for the packet
2561 * based on the mode bits and key value in the VNIC.
2564 } __attribute__((packed));
2566 /* Last 16 bytes of rx_pkt_cmpl. */
2567 /* rx_pkt_cmpl_hi (size:128b/16B) */
2568 struct rx_pkt_cmpl_hi {
2571 * This indicates that the ip checksum was calculated for the
2572 * inner packet and that the ip_cs_error field indicates if there
2575 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2577 * This indicates that the TCP, UDP or ICMP checksum was
2578 * calculated for the inner packet and that the l4_cs_error field
2579 * indicates if there was an error.
2581 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2583 * This indicates that the ip checksum was calculated for the
2584 * tunnel header and that the t_ip_cs_error field indicates if there
2587 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2589 * This indicates that the UDP checksum was
2590 * calculated for the tunnel packet and that the t_l4_cs_error field
2591 * indicates if there was an error.
2593 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2594 /* This value indicates what format the metadata field is. */
2595 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2596 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2597 /* No metadata informtaion. Value is zero. */
2598 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2599 (UINT32_C(0x0) << 4)
2601 * The metadata field contains the VLAN tag and TPID value.
2602 * - metadata[11:0] contains the vlan VID value.
2603 * - metadata[12] contains the vlan DE value.
2604 * - metadata[15:13] contains the vlan PRI value.
2605 * - metadata[31:16] contains the vlan TPID value.
2607 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2608 (UINT32_C(0x1) << 4)
2610 * If ext_meta_format is equal to 1, the metadata field
2611 * contains the lower 16b of the tunnel ID value, justified
2613 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2614 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2615 * - NVGRE = TNI[23:0] -> Tenant Network ID
2616 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2617 * - IPV4 = 0 (not populated)
2618 * - IPV6 = Flow Label[19:0]
2619 * - PPPoE = sessionID[15:0]
2620 * - MPLs = Outer label[19:0]
2621 * - UPAR = Selected[31:0] with bit mask
2623 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2624 (UINT32_C(0x2) << 4)
2626 * if ext_meta_format is equal to 1, metadata field contains
2627 * 16b metadata from the prepended header (chdr_data).
2629 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2630 (UINT32_C(0x3) << 4)
2632 * If ext_meta_format is equal to 1, the metadata field contains
2633 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2635 * - metadata[8:0] contains the outer_l3_offset.
2636 * - metadata[17:9] contains the inner_l2_offset.
2637 * - metadata[26:18] contains the inner_l3_offset.
2638 * - metadata[31:27] contains the inner_l4_size.
2640 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2641 (UINT32_C(0x4) << 4)
2642 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2643 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2645 * This field indicates the IP type for the inner-most IP header.
2646 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2647 * This value is only valid if itype indicates a packet
2648 * with an IP header.
2650 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2652 * This indicates that the complete 1's complement checksum was
2653 * calculated for the packet.
2655 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2657 * The combination of this value and meta_format indicated what
2658 * format the metadata field is.
2660 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2661 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2663 * This value is the complete 1's complement checksum calculated from
2664 * the start of the outer L3 header to the end of the packet (not
2665 * including the ethernet crc). It is valid when the
2666 * 'complete_checksum_calc' flag is set.
2668 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2669 UINT32_C(0xffff0000)
2670 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2672 * This is data from the CFA block as indicated by the meta_format
2676 /* When meta_format=1, this value is the VLAN VID. */
2677 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2678 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2679 /* When meta_format=1, this value is the VLAN DE. */
2680 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2681 /* When meta_format=1, this value is the VLAN PRI. */
2682 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2683 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2684 /* When meta_format=1, this value is the VLAN TPID. */
2685 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2686 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2689 * This value is written by the NIC such that it will be different
2690 * for each pass through the completion queue. The even passes
2691 * will write 1. The odd passes will write 0.
2693 #define RX_PKT_CMPL_V2 \
2695 #define RX_PKT_CMPL_ERRORS_MASK \
2697 #define RX_PKT_CMPL_ERRORS_SFT 1
2699 * This error indicates that there was some sort of problem with
2700 * the BDs for the packet that was found after part of the
2701 * packet was already placed. The packet should be treated as
2704 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2706 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2707 /* No buffer error */
2708 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2709 (UINT32_C(0x0) << 1)
2712 * Packet did not fit into packet buffer provided.
2713 * For regular placement, this means the packet did not fit
2714 * in the buffer provided. For HDS and jumbo placement, this
2715 * means that the packet could not be placed into 7 physical
2718 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2719 (UINT32_C(0x1) << 1)
2722 * All BDs needed for the packet were not on-chip when
2723 * the packet arrived.
2725 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2726 (UINT32_C(0x2) << 1)
2729 * BDs were not formatted correctly.
2731 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2732 (UINT32_C(0x3) << 1)
2735 * There was a bad_format error on the previous operation
2737 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2738 (UINT32_C(0x5) << 1)
2739 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2740 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2742 * This indicates that there was an error in the IP header
2745 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2748 * This indicates that there was an error in the TCP, UDP
2751 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2754 * This indicates that there was an error in the tunnel
2755 * IP header checksum.
2757 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2760 * This indicates that there was an error in the tunnel
2763 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2766 * This indicates that there was a CRC error on either an FCoE
2767 * or RoCE packet. The itype indicates the packet type.
2769 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2772 * This indicates that there was an error in the tunnel
2773 * portion of the packet when this
2774 * field is non-zero.
2776 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2778 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2780 * No additional error occurred on the tunnel portion
2781 * or the packet of the packet does not have a tunnel.
2783 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2784 (UINT32_C(0x0) << 9)
2786 * Indicates that IP header version does not match
2787 * expectation from L2 Ethertype for IPv4 and IPv6
2788 * in the tunnel header.
2790 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2791 (UINT32_C(0x1) << 9)
2793 * Indicates that header length is out of range in the
2794 * tunnel header. Valid for
2797 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2798 (UINT32_C(0x2) << 9)
2800 * Indicates that the physical packet is shorter than that
2801 * claimed by the PPPoE header length for a tunnel PPPoE
2804 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2805 (UINT32_C(0x3) << 9)
2807 * Indicates that physical packet is shorter than that claimed
2808 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2809 * tunnel packet packets.
2811 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2812 (UINT32_C(0x4) << 9)
2814 * Indicates that the physical packet is shorter than that
2815 * claimed by the tunnel UDP header length for a tunnel
2816 * UDP packet that is not fragmented.
2818 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2819 (UINT32_C(0x5) << 9)
2821 * indicates that the IPv4 TTL or IPv6 hop limit check
2822 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2823 * for IPv4, and IPv6.
2825 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2826 (UINT32_C(0x6) << 9)
2827 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2828 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2830 * This indicates that there was an error in the inner
2831 * portion of the packet when this
2832 * field is non-zero.
2834 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2836 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2838 * No additional error occurred on the tunnel portion
2839 * or the packet of the packet does not have a tunnel.
2841 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2842 (UINT32_C(0x0) << 12)
2844 * Indicates that IP header version does not match
2845 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2846 * option other than VFT was parsed on
2849 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2850 (UINT32_C(0x1) << 12)
2852 * indicates that header length is out of range. Valid for
2855 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2856 (UINT32_C(0x2) << 12)
2858 * indicates that the IPv4 TTL or IPv6 hop limit check
2859 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2861 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2862 (UINT32_C(0x3) << 12)
2864 * Indicates that physical packet is shorter than that
2865 * claimed by the l3 header length. Valid for IPv4,
2866 * IPv6 packet or RoCE packets.
2868 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2869 (UINT32_C(0x4) << 12)
2871 * Indicates that the physical packet is shorter than that
2872 * claimed by the UDP header length for a UDP packet that is
2875 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2876 (UINT32_C(0x5) << 12)
2878 * Indicates that TCP header length > IP payload. Valid for
2881 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2882 (UINT32_C(0x6) << 12)
2883 /* Indicates that TCP header length < 5. Valid for TCP. */
2884 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2885 (UINT32_C(0x7) << 12)
2887 * Indicates that TCP option headers result in a TCP header
2888 * size that does not match data offset in TCP header. Valid
2891 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2892 (UINT32_C(0x8) << 12)
2893 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2894 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2896 * This field identifies the CFA action rule that was used for this
2902 * This value holds the reordering sequence number for the packet.
2903 * If the reordering sequence is not valid, then this value is zero.
2904 * The reordering domain for the packet is in the bottom 8 to 10b of
2905 * the rss_hash value. The bottom 20b of this value contain the
2906 * ordering domain value for the packet.
2908 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2909 #define RX_PKT_CMPL_REORDER_SFT 0
2910 } __attribute__((packed));
2912 /* rx_tpa_start_cmpl (size:128b/16B) */
2913 struct rx_tpa_start_cmpl {
2914 uint16_t flags_type;
2916 * This field indicates the exact type of the completion.
2917 * By convention, the LSB identifies the length of the
2918 * record in 16B units. Even values indicate 16B
2919 * records. Odd values indicate 32B
2922 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2923 #define RX_TPA_START_CMPL_TYPE_SFT 0
2925 * RX L2 TPA Start Completion:
2926 * Completion at the beginning of a TPA operation.
2929 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2930 #define RX_TPA_START_CMPL_TYPE_LAST \
2931 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2932 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2933 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2934 /* This bit will always be '0' for TPA start completions. */
2935 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2936 /* This field indicates how the packet was placed in the buffer. */
2937 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2938 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2941 * TPA Packet was placed using jumbo algorithm. This means
2942 * that the first buffer will be filled with data before
2943 * moving to aggregation buffers. Each aggregation buffer
2944 * will be filled before moving to the next aggregation
2947 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2948 (UINT32_C(0x1) << 7)
2950 * Header/Data Separation:
2951 * Packet was placed using Header/Data separation algorithm.
2952 * The separation location is indicated by the itype field.
2954 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2955 (UINT32_C(0x2) << 7)
2958 * Packet will be placed using GRO/Jumbo where the first
2959 * packet is filled with data. Subsequent packets will be
2960 * placed such that any one packet does not span two
2961 * aggregation buffers unless it starts at the beginning of
2962 * an aggregation buffer.
2964 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2965 (UINT32_C(0x5) << 7)
2967 * GRO/Header-Data Separation:
2968 * Packet will be placed using GRO/HDS where the header
2969 * is in the first packet.
2970 * Payload of each packet will be
2971 * placed such that any one packet does not span two
2972 * aggregation buffers unless it starts at the beginning of
2973 * an aggregation buffer.
2975 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2976 (UINT32_C(0x6) << 7)
2977 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2978 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2979 /* This bit is '1' if the RSS field in this completion is valid. */
2980 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2982 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2984 * This value indicates what the inner packet determined for the
2987 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2988 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2991 * Indicates that the packet was IP and TCP.
2993 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2994 (UINT32_C(0x2) << 12)
2995 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2996 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2998 * This value indicates the amount of packet data written to the
2999 * buffer the opaque field in this completion corresponds to.
3003 * This is a copy of the opaque field from the RX BD this completion
3008 * This value is written by the NIC such that it will be different
3009 * for each pass through the completion queue. The even passes
3010 * will write 1. The odd passes will write 0.
3014 * This value is written by the NIC such that it will be different
3015 * for each pass through the completion queue. The even passes
3016 * will write 1. The odd passes will write 0.
3018 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3019 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3021 * This is the RSS hash type for the packet. The value is packed
3022 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3024 * The value of tuple_extrac_op provides the information about
3025 * what fields the hash was computed on.
3026 * * 0: The RSS hash was computed over source IP address,
3027 * destination IP address, source port, and destination port of inner
3028 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3029 * the packet headers are considered inner packet headers for the RSS
3030 * hash computation purpose.
3031 * * 1: The RSS hash was computed over source IP address and destination
3032 * IP address of inner IP header. Note: For non-tunneled packets,
3033 * the packet headers are considered inner packet headers for the RSS
3034 * hash computation purpose.
3035 * * 2: The RSS hash was computed over source IP address,
3036 * destination IP address, source port, and destination port of
3037 * IP and TCP or UDP headers of outer tunnel headers.
3038 * Note: For non-tunneled packets, this value is not applicable.
3039 * * 3: The RSS hash was computed over source IP address and
3040 * destination IP address of IP header of outer tunnel headers.
3041 * Note: For non-tunneled packets, this value is not applicable.
3043 * Note that 4-tuples values listed above are applicable
3044 * for layer 4 protocols supported and enabled for RSS in the hardware,
3045 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3046 * enabled for TCP traffic only, then the values of tuple_extract_op
3047 * corresponding to 4-tuples are only valid for TCP traffic.
3049 uint8_t rss_hash_type;
3051 * This is the aggregation ID that the completion is associated
3052 * with. Use this number to correlate the TPA start completion
3053 * with the TPA end completion.
3056 /* unused2 is 9 b */
3057 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3058 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3060 * This is the aggregation ID that the completion is associated
3061 * with. Use this number to correlate the TPA start completion
3062 * with the TPA end completion.
3064 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3065 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3067 * This value is the RSS hash value calculated for the packet
3068 * based on the mode bits and key value in the VNIC.
3071 } __attribute__((packed));
3073 /* Last 16 bytes of rx_tpq_start_cmpl. */
3074 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3075 struct rx_tpa_start_cmpl_hi {
3078 * This indicates that the ip checksum was calculated for the
3079 * inner packet and that the sum passed for all segments
3080 * included in the aggregation.
3082 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
3085 * This indicates that the TCP, UDP or ICMP checksum was
3086 * calculated for the inner packet and that the sum passed
3087 * for all segments included in the aggregation.
3089 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
3092 * This indicates that the ip checksum was calculated for the
3093 * tunnel header and that the sum passed for all segments
3094 * included in the aggregation.
3096 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
3099 * This indicates that the UDP checksum was
3100 * calculated for the tunnel packet and that the sum passed for
3101 * all segments included in the aggregation.
3103 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
3105 /* This value indicates what format the metadata field is. */
3106 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
3108 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3109 /* No metadata informtaion. Value is zero. */
3110 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3111 (UINT32_C(0x0) << 4)
3113 * The metadata field contains the VLAN tag and TPID value.
3114 * - metadata[11:0] contains the vlan VID value.
3115 * - metadata[12] contains the vlan DE value.
3116 * - metadata[15:13] contains the vlan PRI value.
3117 * - metadata[31:16] contains the vlan TPID value.
3119 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3120 (UINT32_C(0x1) << 4)
3122 * If ext_meta_format is equal to 1, the metadata field
3123 * contains the lower 16b of the tunnel ID value, justified
3125 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3126 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3127 * - NVGRE = TNI[23:0] -> Tenant Network ID
3128 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3129 * - IPV4 = 0 (not populated)
3130 * - IPV6 = Flow Label[19:0]
3131 * - PPPoE = sessionID[15:0]
3132 * - MPLs = Outer label[19:0]
3133 * - UPAR = Selected[31:0] with bit mask
3135 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3136 (UINT32_C(0x2) << 4)
3138 * if ext_meta_format is equal to 1, metadata field contains
3139 * 16b metadata from the prepended header (chdr_data).
3141 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3142 (UINT32_C(0x3) << 4)
3144 * If ext_meta_format is equal to 1, the metadata field contains
3145 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3147 * - metadata[8:0] contains the outer_l3_offset.
3148 * - metadata[17:9] contains the inner_l2_offset.
3149 * - metadata[26:18] contains the inner_l3_offset.
3150 * - metadata[31:27] contains the inner_l4_size.
3152 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3153 (UINT32_C(0x4) << 4)
3154 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3155 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3157 * This field indicates the IP type for the inner-most IP header.
3158 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3160 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
3163 * This indicates that the complete 1's complement checksum was
3164 * calculated for the packet.
3166 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3169 * The combination of this value and meta_format indicated what
3170 * format the metadata field is.
3172 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3174 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3176 * This value is the complete 1's complement checksum calculated from
3177 * the start of the outer L3 header to the end of the packet (not
3178 * including the ethernet crc). It is valid when the
3179 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3180 * the complete checksum is calculated for the first packet in the
3183 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3184 UINT32_C(0xffff0000)
3185 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3187 * This is data from the CFA block as indicated by the meta_format
3191 /* When meta_format=1, this value is the VLAN VID. */
3192 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3193 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3194 /* When meta_format=1, this value is the VLAN DE. */
3195 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3196 /* When meta_format=1, this value is the VLAN PRI. */
3197 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3198 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3199 /* When meta_format=1, this value is the VLAN TPID. */
3200 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3201 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3204 * This value is written by the NIC such that it will be different
3205 * for each pass through the completion queue. The even passes
3206 * will write 1. The odd passes will write 0.
3208 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3209 #define RX_TPA_START_CMPL_ERRORS_MASK \
3211 #define RX_TPA_START_CMPL_ERRORS_SFT 1
3213 * This error indicates that there was some sort of problem with
3214 * the BDs for the packet that was found after part of the
3215 * packet was already placed. The packet should be treated as
3218 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3219 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3220 /* No buffer error */
3221 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3222 (UINT32_C(0x0) << 1)
3225 * BDs were not formatted correctly.
3227 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3228 (UINT32_C(0x3) << 1)
3231 * There was a bad_format error on the previous operation
3233 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3234 (UINT32_C(0x5) << 1)
3235 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3236 RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3238 * This field identifies the CFA action rule that was used for this
3243 * This is the size in bytes of the inner most L4 header.
3244 * This can be subtracted from the payload_offset to determine
3245 * the start of the inner most L4 header.
3247 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3249 * This is the offset from the beginning of the packet in bytes for
3250 * the outer L3 header. If there is no outer L3 header, then this
3253 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3254 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3256 * This is the offset from the beginning of the packet in bytes for
3257 * the inner most L2 header.
3259 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3260 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3262 * This is the offset from the beginning of the packet in bytes for
3263 * the inner most L3 header.
3265 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3266 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3268 * This is the size in bytes of the inner most L4 header.
3269 * This can be subtracted from the payload_offset to determine
3270 * the start of the inner most L4 header.
3272 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3273 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3274 } __attribute__((packed));
3276 /* rx_tpa_end_cmpl (size:128b/16B) */
3277 struct rx_tpa_end_cmpl {
3278 uint16_t flags_type;
3280 * This field indicates the exact type of the completion.
3281 * By convention, the LSB identifies the length of the
3282 * record in 16B units. Even values indicate 16B
3283 * records. Odd values indicate 32B
3286 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3287 #define RX_TPA_END_CMPL_TYPE_SFT 0
3289 * RX L2 TPA End Completion:
3290 * Completion at the end of a TPA operation.
3293 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3294 #define RX_TPA_END_CMPL_TYPE_LAST \
3295 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3296 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3297 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3299 * When this bit is '1', it indicates a packet that has an
3300 * error of some type. Type of error is indicated in
3303 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3304 /* This field indicates how the packet was placed in the buffer. */
3305 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3306 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3309 * TPA Packet was placed using jumbo algorithm. This means
3310 * that the first buffer will be filled with data before
3311 * moving to aggregation buffers. Each aggregation buffer
3312 * will be filled before moving to the next aggregation
3315 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3316 (UINT32_C(0x1) << 7)
3318 * Header/Data Separation:
3319 * Packet was placed using Header/Data separation algorithm.
3320 * The separation location is indicated by the itype field.
3322 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3323 (UINT32_C(0x2) << 7)
3326 * Packet will be placed using GRO/Jumbo where the first
3327 * packet is filled with data. Subsequent packets will be
3328 * placed such that any one packet does not span two
3329 * aggregation buffers unless it starts at the beginning of
3330 * an aggregation buffer.
3332 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3333 (UINT32_C(0x5) << 7)
3335 * GRO/Header-Data Separation:
3336 * Packet will be placed using GRO/HDS where the header
3337 * is in the first packet.
3338 * Payload of each packet will be
3339 * placed such that any one packet does not span two
3340 * aggregation buffers unless it starts at the beginning of
3341 * an aggregation buffer.
3343 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3344 (UINT32_C(0x6) << 7)
3345 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3346 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3348 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3349 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3351 * This value indicates what the inner packet determined for the
3354 * Indicates that the packet was IP and TCP. This indicates
3355 * that the ip_cs field is valid and that the tcp_udp_cs
3356 * field is valid and contains the TCP checksum.
3357 * This also indicates that the payload_offset field is valid.
3359 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3360 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3362 * This value is zero for TPA End completions.
3363 * There is no data in the buffer that corresponds to the opaque
3364 * value in this completion.
3368 * This is a copy of the opaque field from the RX BD this completion
3373 * This value is written by the NIC such that it will be different
3374 * for each pass through the completion queue. The even passes
3375 * will write 1. The odd passes will write 0.
3377 uint8_t agg_bufs_v1;
3379 * This value is written by the NIC such that it will be different
3380 * for each pass through the completion queue. The even passes
3381 * will write 1. The odd passes will write 0.
3383 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3385 * This value is the number of aggregation buffers that follow this
3386 * entry in the completion ring that are a part of this aggregation
3388 * If the value is zero, then the packet is completely contained
3389 * in the buffer space provided in the aggregation start completion.
3391 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3392 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3393 /* This value is the number of segments in the TPA operation. */
3396 * This value indicates the offset in bytes from the beginning of the packet
3397 * where the inner payload starts. This value is valid for TCP, UDP,
3398 * FCoE, and RoCE packets.
3400 * A value of zero indicates an offset of 256 bytes.
3402 uint8_t payload_offset;
3404 /* unused2 is 1 b */
3405 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3407 * This is the aggregation ID that the completion is associated
3408 * with. Use this number to correlate the TPA start completion
3409 * with the TPA end completion.
3411 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3412 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3414 * For non-GRO packets, this value is the
3415 * timestamp delta between earliest and latest timestamp values for
3416 * TPA packet. If packets were not time stamped, then delta will be
3419 * For GRO packets, this field is zero except for the following
3422 * Timestamp present indication. When '0', no Timestamp
3423 * option is in the packet. When '1', then a Timestamp
3424 * option is present in the packet.
3427 } __attribute__((packed));
3429 /* Last 16 bytes of rx_tpa_end_cmpl. */
3430 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3431 struct rx_tpa_end_cmpl_hi {
3433 * This value is the number of duplicate ACKs that have been
3434 * received as part of the TPA operation.
3436 uint16_t tpa_dup_acks;
3438 * This value is the number of duplicate ACKs that have been
3439 * received as part of the TPA operation.
3441 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3442 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3444 * This value indicated the offset in bytes from the beginning of
3445 * the packet where the inner payload starts. This value is valid
3446 * for TCP, UDP, FCoE and RoCE packets
3448 uint8_t payload_offset;
3450 * The value is the total number of aggregation buffers that were
3451 * used in the TPA operation. All TPA aggregation buffer completions
3452 * precede the TPA End completion. If the value is zero, then the
3453 * aggregation is completely contained in the buffer space provided
3454 * in the aggregation start completion.
3455 * Note that the field is simply provided as a cross check.
3457 uint8_t tpa_agg_bufs;
3459 * This value is the valid when TPA completion is active. It
3460 * indicates the length of the longest segment of the TPA operation
3461 * for LRO mode and the length of the first segment in GRO mode.
3463 * This value may be used by GRO software to re-construct the original
3464 * packet stream from the TPA packet. This is the length of all
3465 * but the last segment for GRO. In LRO mode this value may be used
3466 * to indicate MSS size to the stack.
3468 uint16_t tpa_seg_len;
3469 /* unused4 is 16 b */
3473 * This value is written by the NIC such that it will be different
3474 * for each pass through the completion queue. The even passes
3475 * will write 1. The odd passes will write 0.
3477 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3478 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3479 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3481 * This error indicates that there was some sort of problem with
3482 * the BDs for the packet that was found after part of the
3483 * packet was already placed. The packet should be treated as
3486 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3487 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3488 /* No buffer error */
3489 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3490 (UINT32_C(0x0) << 1)
3492 * This error occurs when there is a fatal HW problem in
3493 * the chip only. It indicates that there were not
3494 * BDs on chip but that there was adequate reservation.
3495 * provided by the TPA block.
3497 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3498 (UINT32_C(0x2) << 1)
3501 * BDs were not formatted correctly.
3503 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3504 (UINT32_C(0x3) << 1)
3506 * This error occurs when TPA block was not configured to
3507 * reserve adequate BDs for TPA operations on this RX
3508 * ring. All data for the TPA operation was not placed.
3510 * This error can also be generated when the number of
3511 * segments is not programmed correctly in TPA and the
3512 * 33 total aggregation buffers allowed for the TPA
3513 * operation has been exceeded.
3515 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3516 (UINT32_C(0x4) << 1)
3519 * There was a bad_format error on the previous operation
3521 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3522 (UINT32_C(0x5) << 1)
3523 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3524 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3525 /* unused5 is 16 b */
3528 * This is the opaque value that was completed for the TPA start
3529 * completion that corresponds to this TPA end completion.
3531 uint32_t start_opaque;
3532 } __attribute__((packed));
3534 /* rx_abuf_cmpl (size:128b/16B) */
3535 struct rx_abuf_cmpl {
3538 * This field indicates the exact type of the completion.
3539 * By convention, the LSB identifies the length of the
3540 * record in 16B units. Even values indicate 16B
3541 * records. Odd values indicate 32B
3544 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
3545 #define RX_ABUF_CMPL_TYPE_SFT 0
3547 * RX Aggregation Buffer completion :
3548 * Completion of an L2 aggregation buffer in support of
3549 * TPA, HDS, or Jumbo packet completion. Length = 16B
3551 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
3552 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
3554 * This is the length of the data for the packet stored in this
3555 * aggregation buffer identified by the opaque value. This does not
3556 * include the length of any
3557 * data placed in other aggregation BDs or in the packet or buffer
3558 * BDs. This length does not include any space added due to
3559 * hdr_offset register during HDS placement mode.
3563 * This is a copy of the opaque field from the RX BD this aggregation
3564 * buffer corresponds to.
3569 * This value is written by the NIC such that it will be different
3570 * for each pass through the completion queue. The even passes
3571 * will write 1. The odd passes will write 0.
3573 #define RX_ABUF_CMPL_V UINT32_C(0x1)
3574 /* unused3 is 32 b */
3576 } __attribute__((packed));
3578 /* eject_cmpl (size:128b/16B) */
3582 * This field indicates the exact type of the completion.
3583 * By convention, the LSB identifies the length of the
3584 * record in 16B units. Even values indicate 16B
3585 * records. Odd values indicate 32B
3588 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
3589 #define EJECT_CMPL_TYPE_SFT 0
3591 * Statistics Ejection Completion:
3592 * Completion of statistics data ejection buffer.
3595 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
3596 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
3597 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3598 #define EJECT_CMPL_FLAGS_SFT 6
3600 * When this bit is '1', it indicates a packet that has an
3601 * error of some type. Type of error is indicated in
3604 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
3606 * This is the length of the statistics data stored in this
3611 * This is a copy of the opaque field from the RX BD this ejection
3612 * buffer corresponds to.
3617 * This value is written by the NIC such that it will be different
3618 * for each pass through the completion queue. The even passes
3619 * will write 1. The odd passes will write 0.
3621 #define EJECT_CMPL_V UINT32_C(0x1)
3622 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3623 #define EJECT_CMPL_ERRORS_SFT 1
3625 * This error indicates that there was some sort of problem with
3626 * the BDs for statistics ejection. The statistics ejection should
3627 * be treated as invalid
3629 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3630 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3631 /* No buffer error */
3632 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3633 (UINT32_C(0x0) << 1)
3636 * Statistics did not fit into aggregation buffer provided.
3638 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3639 (UINT32_C(0x1) << 1)
3642 * BDs were not formatted correctly.
3644 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3645 (UINT32_C(0x3) << 1)
3648 * There was a bad_format error on the previous operation
3650 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3651 (UINT32_C(0x5) << 1)
3652 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3653 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3654 /* reserved16 is 16 b */
3655 uint16_t reserved16;
3656 /* unused3 is 32 b */
3658 } __attribute__((packed));
3660 /* hwrm_cmpl (size:128b/16B) */
3664 * This field indicates the exact type of the completion.
3665 * By convention, the LSB identifies the length of the
3666 * record in 16B units. Even values indicate 16B
3667 * records. Odd values indicate 32B
3670 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3671 #define HWRM_CMPL_TYPE_SFT 0
3673 * HWRM Command Completion:
3674 * Completion of an HWRM command.
3676 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3677 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3678 /* This is the sequence_id of the HWRM command that has completed. */
3679 uint16_t sequence_id;
3680 /* unused2 is 32 b */
3684 * This value is written by the NIC such that it will be different
3685 * for each pass through the completion queue. The even passes
3686 * will write 1. The odd passes will write 0.
3688 #define HWRM_CMPL_V UINT32_C(0x1)
3689 /* unused4 is 32 b */
3691 } __attribute__((packed));
3693 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3694 struct hwrm_fwd_req_cmpl {
3696 * This field indicates the exact type of the completion.
3697 * By convention, the LSB identifies the length of the
3698 * record in 16B units. Even values indicate 16B
3699 * records. Odd values indicate 32B
3702 uint16_t req_len_type;
3704 * This field indicates the exact type of the completion.
3705 * By convention, the LSB identifies the length of the
3706 * record in 16B units. Even values indicate 16B
3707 * records. Odd values indicate 32B
3710 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3711 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3712 /* Forwarded HWRM Request */
3713 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3714 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3715 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3716 /* Length of forwarded request in bytes. */
3717 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3718 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3720 * Source ID of this request.
3721 * Typically used in forwarding requests and responses.
3722 * 0x0 - 0xFFF8 - Used for function ids
3723 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3727 /* unused1 is 32 b */
3729 /* Address of forwarded request. */
3730 uint32_t req_buf_addr_v[2];
3732 * This value is written by the NIC such that it will be different
3733 * for each pass through the completion queue. The even passes
3734 * will write 1. The odd passes will write 0.
3736 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3737 /* Address of forwarded request. */
3738 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3739 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3740 } __attribute__((packed));
3742 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3743 struct hwrm_fwd_resp_cmpl {
3746 * This field indicates the exact type of the completion.
3747 * By convention, the LSB identifies the length of the
3748 * record in 16B units. Even values indicate 16B
3749 * records. Odd values indicate 32B
3752 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3753 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3754 /* Forwarded HWRM Response */
3755 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3756 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3757 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3759 * Source ID of this response.
3760 * Typically used in forwarding requests and responses.
3761 * 0x0 - 0xFFF8 - Used for function ids
3762 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3766 /* Length of forwarded response in bytes. */
3768 /* unused2 is 16 b */
3770 /* Address of forwarded request. */
3771 uint32_t resp_buf_addr_v[2];
3773 * This value is written by the NIC such that it will be different
3774 * for each pass through the completion queue. The even passes
3775 * will write 1. The odd passes will write 0.
3777 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3778 /* Address of forwarded request. */
3779 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3780 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3781 } __attribute__((packed));
3783 /* hwrm_async_event_cmpl (size:128b/16B) */
3784 struct hwrm_async_event_cmpl {
3787 * This field indicates the exact type of the completion.
3788 * By convention, the LSB identifies the length of the
3789 * record in 16B units. Even values indicate 16B
3790 * records. Odd values indicate 32B
3793 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3794 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3795 /* HWRM Asynchronous Event Information */
3796 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3797 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3798 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3799 /* Identifiers of events. */
3801 /* Link status changed */
3802 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3804 /* Link MTU changed */
3805 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3807 /* Link speed changed */
3808 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3810 /* DCB Configuration changed */
3811 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3813 /* Port connection not allowed */
3814 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3816 /* Link speed configuration was not allowed */
3817 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3819 /* Link speed configuration change */
3820 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3822 /* Port PHY configuration change */
3823 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3825 /* Reset notification to clients */
3826 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
3828 /* Master function selection event */
3829 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
3831 /* Function driver unloaded */
3832 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3834 /* Function driver loaded */
3835 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3837 /* Function FLR related processing has completed */
3838 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3840 /* PF driver unloaded */
3841 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3843 /* PF driver loaded */
3844 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3846 /* VF Function Level Reset (FLR) */
3847 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3849 /* VF MAC Address Change */
3850 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3852 /* PF-VF communication channel status change. */
3853 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3855 /* VF Configuration Change */
3856 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3858 /* LLFC/PFC Configuration Change */
3859 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3861 /* Default VNIC Configuration Change */
3862 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
3865 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
3868 * A debug notification being posted to the driver. These
3869 * notifications are purely for diagnostic purpose and should not be
3870 * used for functional purpose. The driver is not supposed to act
3871 * on these messages except to log/record it.
3873 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
3876 * A EEM flow cached memory flush request event being posted to the PF
3879 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
3882 * A EEM flow cache memory flush completion event being posted to the
3883 * firmware by the PF driver. This is indication that host EEM flush
3884 * has completed by the PF.
3886 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
3889 * A tcp flag action change event being posted to the PF or trusted VF
3890 * driver by the firmware. The PF or trusted VF driver should query
3891 * the firmware for the new TCP flag action update after receiving
3894 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
3897 * A eem flow active event being posted to the PF or trusted VF driver
3898 * by the firmware. The PF or trusted VF driver should update the
3899 * flow's aging timer after receiving this async event.
3901 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
3904 * A eem cfg change event being posted to the trusted VF driver by the
3905 * firmware if the parent PF EEM configuration changed.
3907 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
3909 /* TFLIB unique default VNIC Configuration Change */
3910 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
3912 /* TFLIB unique link status changed */
3913 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
3916 * A trace log message. This contains firmware trace logs string
3917 * embedded in the asynchronous message. This is an experimental
3918 * event, not meant for production use at this time.
3920 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
3923 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3925 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3926 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3927 /* Event specific data */
3928 uint32_t event_data2;
3931 * This value is written by the NIC such that it will be different
3932 * for each pass through the completion queue. The even passes
3933 * will write 1. The odd passes will write 0.
3935 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3937 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3938 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3939 /* 8-lsb timestamp from POR (100-msec resolution) */
3940 uint8_t timestamp_lo;
3941 /* 16-lsb timestamp from POR (100-msec resolution) */
3942 uint16_t timestamp_hi;
3943 /* Event specific data */
3944 uint32_t event_data1;
3945 } __attribute__((packed));
3947 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3948 struct hwrm_async_event_cmpl_link_status_change {
3951 * This field indicates the exact type of the completion.
3952 * By convention, the LSB identifies the length of the
3953 * record in 16B units. Even values indicate 16B
3954 * records. Odd values indicate 32B
3957 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3959 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3960 /* HWRM Asynchronous Event Information */
3961 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3963 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3964 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3965 /* Identifiers of events. */
3967 /* Link status changed */
3968 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3970 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3971 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3972 /* Event specific data */
3973 uint32_t event_data2;
3976 * This value is written by the NIC such that it will be different
3977 * for each pass through the completion queue. The even passes
3978 * will write 1. The odd passes will write 0.
3980 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3983 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3985 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3986 /* 8-lsb timestamp from POR (100-msec resolution) */
3987 uint8_t timestamp_lo;
3988 /* 16-lsb timestamp from POR (100-msec resolution) */
3989 uint16_t timestamp_hi;
3990 /* Event specific data */
3991 uint32_t event_data1;
3992 /* Indicates link status change */
3993 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3996 * If this bit set to 0, then it indicates that the link
3997 * was up and it went down.
3999 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4002 * If this bit is set to 1, then it indicates that the link
4003 * was down and it went up.
4005 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4007 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4008 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4009 /* Indicates the physical port this link status change occur */
4010 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4012 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4015 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4017 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4019 /* Indicates the physical function this event occurred on. */
4020 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4022 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4024 } __attribute__((packed));
4026 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4027 struct hwrm_async_event_cmpl_link_mtu_change {
4030 * This field indicates the exact type of the completion.
4031 * By convention, the LSB identifies the length of the
4032 * record in 16B units. Even values indicate 16B
4033 * records. Odd values indicate 32B
4036 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4038 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4039 /* HWRM Asynchronous Event Information */
4040 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4042 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4043 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4044 /* Identifiers of events. */
4046 /* Link MTU changed */
4047 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4049 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4050 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4051 /* Event specific data */
4052 uint32_t event_data2;
4055 * This value is written by the NIC such that it will be different
4056 * for each pass through the completion queue. The even passes
4057 * will write 1. The odd passes will write 0.
4059 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4061 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4063 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4064 /* 8-lsb timestamp from POR (100-msec resolution) */
4065 uint8_t timestamp_lo;
4066 /* 16-lsb timestamp from POR (100-msec resolution) */
4067 uint16_t timestamp_hi;
4068 /* Event specific data */
4069 uint32_t event_data1;
4070 /* The new MTU of the link in bytes. */
4071 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4073 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4074 } __attribute__((packed));
4076 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4077 struct hwrm_async_event_cmpl_link_speed_change {
4080 * This field indicates the exact type of the completion.
4081 * By convention, the LSB identifies the length of the
4082 * record in 16B units. Even values indicate 16B
4083 * records. Odd values indicate 32B
4086 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4088 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4089 /* HWRM Asynchronous Event Information */
4090 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4092 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4093 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4094 /* Identifiers of events. */
4096 /* Link speed changed */
4097 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4099 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4100 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4101 /* Event specific data */
4102 uint32_t event_data2;
4105 * This value is written by the NIC such that it will be different
4106 * for each pass through the completion queue. The even passes
4107 * will write 1. The odd passes will write 0.
4109 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4112 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4114 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4115 /* 8-lsb timestamp from POR (100-msec resolution) */
4116 uint8_t timestamp_lo;
4117 /* 16-lsb timestamp from POR (100-msec resolution) */
4118 uint16_t timestamp_hi;
4119 /* Event specific data */
4120 uint32_t event_data1;
4122 * When this bit is '1', the link was forced to the
4123 * force_link_speed value.
4125 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4127 /* The new link speed in 100 Mbps units. */
4128 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4130 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4132 /* 100Mb link speed */
4133 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4134 (UINT32_C(0x1) << 1)
4135 /* 1Gb link speed */
4136 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4137 (UINT32_C(0xa) << 1)
4138 /* 2Gb link speed */
4139 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4140 (UINT32_C(0x14) << 1)
4141 /* 25Gb link speed */
4142 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4143 (UINT32_C(0x19) << 1)
4144 /* 10Gb link speed */
4145 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4146 (UINT32_C(0x64) << 1)
4147 /* 20Mb link speed */
4148 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4149 (UINT32_C(0xc8) << 1)
4150 /* 25Gb link speed */
4151 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4152 (UINT32_C(0xfa) << 1)
4153 /* 40Gb link speed */
4154 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4155 (UINT32_C(0x190) << 1)
4156 /* 50Gb link speed */
4157 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4158 (UINT32_C(0x1f4) << 1)
4159 /* 100Gb link speed */
4160 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4161 (UINT32_C(0x3e8) << 1)
4162 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4163 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4165 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4166 UINT32_C(0xffff0000)
4167 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4169 } __attribute__((packed));
4171 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4172 struct hwrm_async_event_cmpl_dcb_config_change {
4175 * This field indicates the exact type of the completion.
4176 * By convention, the LSB identifies the length of the
4177 * record in 16B units. Even values indicate 16B
4178 * records. Odd values indicate 32B
4181 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4183 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4184 /* HWRM Asynchronous Event Information */
4185 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4187 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4188 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4189 /* Identifiers of events. */
4191 /* DCB Configuration changed */
4192 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4194 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4195 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4196 /* Event specific data */
4197 uint32_t event_data2;
4198 /* ETS configuration change */
4199 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4201 /* PFC configuration change */
4202 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4204 /* APP configuration change */
4205 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4209 * This value is written by the NIC such that it will be different
4210 * for each pass through the completion queue. The even passes
4211 * will write 1. The odd passes will write 0.
4213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4216 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4218 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4219 /* 8-lsb timestamp from POR (100-msec resolution) */
4220 uint8_t timestamp_lo;
4221 /* 16-lsb timestamp from POR (100-msec resolution) */
4222 uint16_t timestamp_hi;
4223 /* Event specific data */
4224 uint32_t event_data1;
4226 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4228 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4230 /* Priority recommended for RoCE traffic */
4231 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4233 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4236 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4237 (UINT32_C(0xff) << 16)
4238 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4239 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4240 /* Priority recommended for L2 traffic */
4241 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4242 UINT32_C(0xff000000)
4243 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4246 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4247 (UINT32_C(0xff) << 24)
4248 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4249 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4250 } __attribute__((packed));
4252 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4253 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4256 * This field indicates the exact type of the completion.
4257 * By convention, the LSB identifies the length of the
4258 * record in 16B units. Even values indicate 16B
4259 * records. Odd values indicate 32B
4262 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4264 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4266 /* HWRM Asynchronous Event Information */
4267 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4269 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4270 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4271 /* Identifiers of events. */
4273 /* Port connection not allowed */
4274 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4276 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4277 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4278 /* Event specific data */
4279 uint32_t event_data2;
4282 * This value is written by the NIC such that it will be different
4283 * for each pass through the completion queue. The even passes
4284 * will write 1. The odd passes will write 0.
4286 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4289 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4291 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4292 /* 8-lsb timestamp from POR (100-msec resolution) */
4293 uint8_t timestamp_lo;
4294 /* 16-lsb timestamp from POR (100-msec resolution) */
4295 uint16_t timestamp_hi;
4296 /* Event specific data */
4297 uint32_t event_data1;
4299 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4301 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4304 * This value indicates the current port level enforcement policy
4305 * for the optics module when there is an optical module mismatch
4306 * and port is not connected.
4308 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4310 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4312 /* No enforcement */
4313 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4314 (UINT32_C(0x0) << 16)
4315 /* Disable Transmit side Laser. */
4316 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4317 (UINT32_C(0x1) << 16)
4318 /* Raise a warning message. */
4319 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4320 (UINT32_C(0x2) << 16)
4321 /* Power down the module. */
4322 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4323 (UINT32_C(0x3) << 16)
4324 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4325 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4326 } __attribute__((packed));
4328 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4329 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4332 * This field indicates the exact type of the completion.
4333 * By convention, the LSB identifies the length of the
4334 * record in 16B units. Even values indicate 16B
4335 * records. Odd values indicate 32B
4338 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4340 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4342 /* HWRM Asynchronous Event Information */
4343 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4345 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4346 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4347 /* Identifiers of events. */
4349 /* Link speed configuration was not allowed */
4350 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4352 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4353 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4354 /* Event specific data */
4355 uint32_t event_data2;
4358 * This value is written by the NIC such that it will be different
4359 * for each pass through the completion queue. The even passes
4360 * will write 1. The odd passes will write 0.
4362 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4365 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4367 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4368 /* 8-lsb timestamp from POR (100-msec resolution) */
4369 uint8_t timestamp_lo;
4370 /* 16-lsb timestamp from POR (100-msec resolution) */
4371 uint16_t timestamp_hi;
4372 /* Event specific data */
4373 uint32_t event_data1;
4375 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4377 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4379 } __attribute__((packed));
4381 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4382 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4385 * This field indicates the exact type of the completion.
4386 * By convention, the LSB identifies the length of the
4387 * record in 16B units. Even values indicate 16B
4388 * records. Odd values indicate 32B
4391 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4393 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4395 /* HWRM Asynchronous Event Information */
4396 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4398 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4399 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4400 /* Identifiers of events. */
4402 /* Link speed configuration change */
4403 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4405 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4406 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4407 /* Event specific data */
4408 uint32_t event_data2;
4411 * This value is written by the NIC such that it will be different
4412 * for each pass through the completion queue. The even passes
4413 * will write 1. The odd passes will write 0.
4415 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
4418 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
4420 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
4421 /* 8-lsb timestamp from POR (100-msec resolution) */
4422 uint8_t timestamp_lo;
4423 /* 16-lsb timestamp from POR (100-msec resolution) */
4424 uint16_t timestamp_hi;
4425 /* Event specific data */
4426 uint32_t event_data1;
4428 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4430 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4433 * If set to 1, it indicates that the supported link speeds
4434 * configuration on the port has changed.
4435 * If set to 0, then there is no change in supported link speeds
4438 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
4441 * If set to 1, it indicates that the link speed configuration
4442 * on the port has become illegal or invalid.
4443 * If set to 0, then the link speed configuration on the port is
4446 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
4448 } __attribute__((packed));
4450 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
4451 struct hwrm_async_event_cmpl_port_phy_cfg_change {
4454 * This field indicates the exact type of the completion.
4455 * By convention, the LSB identifies the length of the
4456 * record in 16B units. Even values indicate 16B
4457 * records. Odd values indicate 32B
4460 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
4462 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
4464 /* HWRM Asynchronous Event Information */
4465 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4467 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
4468 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4469 /* Identifiers of events. */
4471 /* Port PHY configuration change */
4472 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
4474 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
4475 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
4476 /* Event specific data */
4477 uint32_t event_data2;
4480 * This value is written by the NIC such that it will be different
4481 * for each pass through the completion queue. The even passes
4482 * will write 1. The odd passes will write 0.
4484 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
4487 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
4489 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
4490 /* 8-lsb timestamp from POR (100-msec resolution) */
4491 uint8_t timestamp_lo;
4492 /* 16-lsb timestamp from POR (100-msec resolution) */
4493 uint16_t timestamp_hi;
4494 /* Event specific data */
4495 uint32_t event_data1;
4497 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4499 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4502 * If set to 1, it indicates that the FEC
4503 * configuration on the port has changed.
4504 * If set to 0, then there is no change in FEC configuration.
4506 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
4509 * If set to 1, it indicates that the EEE configuration
4510 * on the port has changed.
4511 * If set to 0, then there is no change in EEE configuration
4514 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
4517 * If set to 1, it indicates that the pause configuration
4518 * on the PHY has changed.
4519 * If set to 0, then there is no change in the pause
4520 * configuration on the PHY.
4522 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
4524 } __attribute__((packed));
4526 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
4527 struct hwrm_async_event_cmpl_reset_notify {
4530 * This field indicates the exact type of the completion.
4531 * By convention, the LSB identifies the length of the
4532 * record in 16B units. Even values indicate 16B
4533 * records. Odd values indicate 32B
4536 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
4538 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
4539 /* HWRM Asynchronous Event Information */
4540 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
4542 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
4543 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
4544 /* Identifiers of events. */
4546 /* Notify clients of imminent reset. */
4547 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
4549 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
4550 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
4551 /* Event specific data */
4552 uint32_t event_data2;
4555 * This value is written by the NIC such that it will be different
4556 * for each pass through the completion queue. The even passes
4557 * will write 1. The odd passes will write 0.
4559 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
4561 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
4562 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
4564 * 8-lsb timestamp (100-msec resolution)
4565 * The Minimum time required for the Firmware readiness after sending this
4566 * notification to the driver instances.
4568 uint8_t timestamp_lo;
4570 * 16-lsb timestamp (100-msec resolution)
4571 * The Maximum Firmware Reset bail out value in the order of 100
4572 * milli seconds. The driver instances will use this value to re-initiate the
4573 * registration process again if the core firmware didn’t set the ready
4576 uint16_t timestamp_hi;
4577 /* Event specific data */
4578 uint32_t event_data1;
4579 /* Indicates driver action requested */
4580 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
4582 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
4585 * If set to 1, it indicates that the l2 client should
4586 * stop sending in band traffic to Nitro.
4587 * if set to 0, there is no change in L2 client behavior.
4589 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
4592 * If set to 1, it indicates that the L2 client should
4593 * bring down the interface.
4594 * If set to 0, then there is no change in L2 client behavior.
4596 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
4598 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
4599 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
4600 /* Indicates reason for reset. */
4601 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
4603 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
4605 /* A management client has requested reset. */
4606 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
4607 (UINT32_C(0x1) << 8)
4608 /* A fatal firmware exception has occurred. */
4609 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
4610 (UINT32_C(0x2) << 8)
4611 /* A non-fatal firmware exception has occurred. */
4612 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
4613 (UINT32_C(0x3) << 8)
4614 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
4615 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
4617 * Minimum time before driver should attempt access - units 100ms ticks.
4620 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
4621 UINT32_C(0xffff0000)
4622 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
4624 } __attribute__((packed));
4626 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
4627 struct hwrm_async_event_cmpl_error_recovery {
4630 * This field indicates the exact type of the completion.
4631 * By convention, the LSB identifies the length of the
4632 * record in 16B units. Even values indicate 16B
4633 * records. Odd values indicate 32B
4636 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
4638 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
4639 /* HWRM Asynchronous Event Information */
4640 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
4642 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
4643 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
4644 /* Identifiers of events. */
4647 * This async notification message can be used for selecting or
4648 * deselecting master function for error recovery,
4649 * and to communicate to all the functions whether error recovery
4650 * was enabled/disabled.
4652 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
4654 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
4655 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
4656 /* Event specific data */
4657 uint32_t event_data2;
4660 * This value is written by the NIC such that it will be different
4661 * for each pass through the completion queue. The even passes
4662 * will write 1. The odd passes will write 0.
4664 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
4666 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
4667 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
4668 /* 8-lsb timestamp (100-msec resolution) */
4669 uint8_t timestamp_lo;
4670 /* 16-lsb timestamp (100-msec resolution) */
4671 uint16_t timestamp_hi;
4672 /* Event specific data */
4673 uint32_t event_data1;
4674 /* Indicates driver action requested */
4675 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
4677 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
4680 * If set to 1, this function is selected as Master function.
4681 * This function has responsibility to do 'chip reset' when it
4682 * detects a fatal error. If set to 0, master function functionality
4683 * is disabled on this function.
4685 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
4688 * If set to 1, error recovery is enabled.
4689 * If set to 0, error recovery is disabled.
4691 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
4693 } __attribute__((packed));
4695 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
4696 struct hwrm_async_event_cmpl_func_drvr_unload {
4699 * This field indicates the exact type of the completion.
4700 * By convention, the LSB identifies the length of the
4701 * record in 16B units. Even values indicate 16B
4702 * records. Odd values indicate 32B
4705 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
4707 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
4708 /* HWRM Asynchronous Event Information */
4709 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4711 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
4712 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4713 /* Identifiers of events. */
4715 /* Function driver unloaded */
4716 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
4718 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
4719 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
4720 /* Event specific data */
4721 uint32_t event_data2;
4724 * This value is written by the NIC such that it will be different
4725 * for each pass through the completion queue. The even passes
4726 * will write 1. The odd passes will write 0.
4728 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
4730 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
4732 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
4733 /* 8-lsb timestamp from POR (100-msec resolution) */
4734 uint8_t timestamp_lo;
4735 /* 16-lsb timestamp from POR (100-msec resolution) */
4736 uint16_t timestamp_hi;
4737 /* Event specific data */
4738 uint32_t event_data1;
4740 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4742 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
4744 } __attribute__((packed));
4746 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
4747 struct hwrm_async_event_cmpl_func_drvr_load {
4750 * This field indicates the exact type of the completion.
4751 * By convention, the LSB identifies the length of the
4752 * record in 16B units. Even values indicate 16B
4753 * records. Odd values indicate 32B
4756 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
4758 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
4759 /* HWRM Asynchronous Event Information */
4760 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4762 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
4763 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4764 /* Identifiers of events. */
4766 /* Function driver loaded */
4767 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
4769 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
4770 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
4771 /* Event specific data */
4772 uint32_t event_data2;
4775 * This value is written by the NIC such that it will be different
4776 * for each pass through the completion queue. The even passes
4777 * will write 1. The odd passes will write 0.
4779 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
4781 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4782 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
4783 /* 8-lsb timestamp from POR (100-msec resolution) */
4784 uint8_t timestamp_lo;
4785 /* 16-lsb timestamp from POR (100-msec resolution) */
4786 uint16_t timestamp_hi;
4787 /* Event specific data */
4788 uint32_t event_data1;
4790 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4792 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4793 } __attribute__((packed));
4795 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
4796 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
4799 * This field indicates the exact type of the completion.
4800 * By convention, the LSB identifies the length of the
4801 * record in 16B units. Even values indicate 16B
4802 * records. Odd values indicate 32B
4805 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
4807 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
4809 /* HWRM Asynchronous Event Information */
4810 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
4812 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
4813 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
4814 /* Identifiers of events. */
4816 /* Function FLR related processing has completed */
4817 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4819 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
4820 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
4821 /* Event specific data */
4822 uint32_t event_data2;
4825 * This value is written by the NIC such that it will be different
4826 * for each pass through the completion queue. The even passes
4827 * will write 1. The odd passes will write 0.
4829 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
4832 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
4834 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
4835 /* 8-lsb timestamp from POR (100-msec resolution) */
4836 uint8_t timestamp_lo;
4837 /* 16-lsb timestamp from POR (100-msec resolution) */
4838 uint16_t timestamp_hi;
4839 /* Event specific data */
4840 uint32_t event_data1;
4842 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
4844 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
4846 } __attribute__((packed));
4848 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
4849 struct hwrm_async_event_cmpl_pf_drvr_unload {
4852 * This field indicates the exact type of the completion.
4853 * By convention, the LSB identifies the length of the
4854 * record in 16B units. Even values indicate 16B
4855 * records. Odd values indicate 32B
4858 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
4860 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
4861 /* HWRM Asynchronous Event Information */
4862 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4864 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
4865 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4866 /* Identifiers of events. */
4868 /* PF driver unloaded */
4869 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
4871 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
4872 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
4873 /* Event specific data */
4874 uint32_t event_data2;
4877 * This value is written by the NIC such that it will be different
4878 * for each pass through the completion queue. The even passes
4879 * will write 1. The odd passes will write 0.
4881 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
4883 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
4884 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
4885 /* 8-lsb timestamp from POR (100-msec resolution) */
4886 uint8_t timestamp_lo;
4887 /* 16-lsb timestamp from POR (100-msec resolution) */
4888 uint16_t timestamp_hi;
4889 /* Event specific data */
4890 uint32_t event_data1;
4892 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4894 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
4895 /* Indicates the physical port this pf belongs to */
4896 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
4898 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
4899 } __attribute__((packed));
4901 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
4902 struct hwrm_async_event_cmpl_pf_drvr_load {
4905 * This field indicates the exact type of the completion.
4906 * By convention, the LSB identifies the length of the
4907 * record in 16B units. Even values indicate 16B
4908 * records. Odd values indicate 32B
4911 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4913 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4914 /* HWRM Asynchronous Event Information */
4915 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4917 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4918 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4919 /* Identifiers of events. */
4921 /* PF driver loaded */
4922 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4924 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4925 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4926 /* Event specific data */
4927 uint32_t event_data2;
4930 * This value is written by the NIC such that it will be different
4931 * for each pass through the completion queue. The even passes
4932 * will write 1. The odd passes will write 0.
4934 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4936 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4937 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4938 /* 8-lsb timestamp from POR (100-msec resolution) */
4939 uint8_t timestamp_lo;
4940 /* 16-lsb timestamp from POR (100-msec resolution) */
4941 uint16_t timestamp_hi;
4942 /* Event specific data */
4943 uint32_t event_data1;
4945 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4947 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4948 /* Indicates the physical port this pf belongs to */
4949 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4951 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4952 } __attribute__((packed));
4954 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4955 struct hwrm_async_event_cmpl_vf_flr {
4958 * This field indicates the exact type of the completion.
4959 * By convention, the LSB identifies the length of the
4960 * record in 16B units. Even values indicate 16B
4961 * records. Odd values indicate 32B
4964 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4966 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4967 /* HWRM Asynchronous Event Information */
4968 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4970 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4971 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4972 /* Identifiers of events. */
4974 /* VF Function Level Reset (FLR) */
4975 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4976 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4977 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4978 /* Event specific data */
4979 uint32_t event_data2;
4982 * This value is written by the NIC such that it will be different
4983 * for each pass through the completion queue. The even passes
4984 * will write 1. The odd passes will write 0.
4986 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4988 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4989 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4990 /* 8-lsb timestamp from POR (100-msec resolution) */
4991 uint8_t timestamp_lo;
4992 /* 16-lsb timestamp from POR (100-msec resolution) */
4993 uint16_t timestamp_hi;
4994 /* Event specific data */
4995 uint32_t event_data1;
4997 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4999 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5000 /* Indicates the physical function this event occurred on. */
5001 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5003 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5004 } __attribute__((packed));
5006 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5007 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5010 * This field indicates the exact type of the completion.
5011 * By convention, the LSB identifies the length of the
5012 * record in 16B units. Even values indicate 16B
5013 * records. Odd values indicate 32B
5016 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5018 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5019 /* HWRM Asynchronous Event Information */
5020 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5022 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5023 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5024 /* Identifiers of events. */
5026 /* VF MAC Address Change */
5027 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5029 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5030 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5031 /* Event specific data */
5032 uint32_t event_data2;
5035 * This value is written by the NIC such that it will be different
5036 * for each pass through the completion queue. The even passes
5037 * will write 1. The odd passes will write 0.
5039 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5042 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5044 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5045 /* 8-lsb timestamp from POR (100-msec resolution) */
5046 uint8_t timestamp_lo;
5047 /* 16-lsb timestamp from POR (100-msec resolution) */
5048 uint16_t timestamp_hi;
5049 /* Event specific data */
5050 uint32_t event_data1;
5052 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5054 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5056 } __attribute__((packed));
5058 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5059 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5062 * This field indicates the exact type of the completion.
5063 * By convention, the LSB identifies the length of the
5064 * record in 16B units. Even values indicate 16B
5065 * records. Odd values indicate 32B
5068 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5070 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5072 /* HWRM Asynchronous Event Information */
5073 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5075 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5076 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5077 /* Identifiers of events. */
5079 /* PF-VF communication channel status change. */
5080 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5082 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5083 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5084 /* Event specific data */
5085 uint32_t event_data2;
5088 * This value is written by the NIC such that it will be different
5089 * for each pass through the completion queue. The even passes
5090 * will write 1. The odd passes will write 0.
5092 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5095 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5097 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5098 /* 8-lsb timestamp from POR (100-msec resolution) */
5099 uint8_t timestamp_lo;
5100 /* 16-lsb timestamp from POR (100-msec resolution) */
5101 uint16_t timestamp_hi;
5102 /* Event specific data */
5103 uint32_t event_data1;
5105 * If this bit is set to 1, then it indicates that the PF-VF
5106 * communication was lost and it is established.
5107 * If this bit set to 0, then it indicates that the PF-VF
5108 * communication was established and it is lost.
5110 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5112 } __attribute__((packed));
5114 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5115 struct hwrm_async_event_cmpl_vf_cfg_change {
5118 * This field indicates the exact type of the completion.
5119 * By convention, the LSB identifies the length of the
5120 * record in 16B units. Even values indicate 16B
5121 * records. Odd values indicate 32B
5124 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5126 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5127 /* HWRM Asynchronous Event Information */
5128 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5130 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5131 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5132 /* Identifiers of events. */
5134 /* VF Configuration Change */
5135 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5137 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5138 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5139 /* Event specific data */
5140 uint32_t event_data2;
5143 * This value is written by the NIC such that it will be different
5144 * for each pass through the completion queue. The even passes
5145 * will write 1. The odd passes will write 0.
5147 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5149 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5150 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5151 /* 8-lsb timestamp from POR (100-msec resolution) */
5152 uint8_t timestamp_lo;
5153 /* 16-lsb timestamp from POR (100-msec resolution) */
5154 uint16_t timestamp_hi;
5156 * Each flag provided in this field indicates a specific VF
5157 * configuration change. At least one of these flags shall be set to 1
5158 * when an asynchronous event completion of this type is provided
5161 uint32_t event_data1;
5163 * If this bit is set to 1, then the value of MTU
5164 * was changed on this VF.
5165 * If set to 0, then this bit should be ignored.
5167 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5170 * If this bit is set to 1, then the value of MRU
5171 * was changed on this VF.
5172 * If set to 0, then this bit should be ignored.
5174 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5177 * If this bit is set to 1, then the value of default MAC
5178 * address was changed on this VF.
5179 * If set to 0, then this bit should be ignored.
5181 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5184 * If this bit is set to 1, then the value of default VLAN
5185 * was changed on this VF.
5186 * If set to 0, then this bit should be ignored.
5188 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5191 * If this bit is set to 1, then the value of trusted VF enable
5192 * was changed on this VF.
5193 * If set to 0, then this bit should be ignored.
5195 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5197 } __attribute__((packed));
5199 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5200 struct hwrm_async_event_cmpl_llfc_pfc_change {
5203 * This field indicates the exact type of the completion.
5204 * By convention, the LSB identifies the length of the
5205 * record in 16B units. Even values indicate 16B
5206 * records. Odd values indicate 32B
5209 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5211 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5212 /* HWRM Asynchronous Event Information */
5213 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5215 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5216 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5217 /* unused1 is 10 b */
5218 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5220 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5221 /* Identifiers of events. */
5223 /* LLFC/PFC Configuration Change */
5224 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5226 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5227 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5228 /* Event specific data */
5229 uint32_t event_data2;
5232 * This value is written by the NIC such that it will be different
5233 * for each pass through the completion queue. The even passes
5234 * will write 1. The odd passes will write 0.
5236 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5238 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5240 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5241 /* 8-lsb timestamp from POR (100-msec resolution) */
5242 uint8_t timestamp_lo;
5243 /* 16-lsb timestamp from POR (100-msec resolution) */
5244 uint16_t timestamp_hi;
5245 /* Event specific data */
5246 uint32_t event_data1;
5247 /* Indicates llfc pfc status change */
5248 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5250 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5253 * If this field set to 1, then it indicates that llfc is
5256 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5259 * If this field is set to 2, then it indicates that pfc
5262 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5264 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5265 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5266 /* Indicates the physical port this llfc pfc change occur */
5267 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5269 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5272 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5274 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5276 } __attribute__((packed));
5278 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5279 struct hwrm_async_event_cmpl_default_vnic_change {
5282 * This field indicates the exact type of the completion.
5283 * By convention, the LSB identifies the length of the
5284 * record in 16B units. Even values indicate 16B
5285 * records. Odd values indicate 32B
5288 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5290 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5292 /* HWRM Asynchronous Event Information */
5293 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5295 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5296 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5297 /* unused1 is 10 b */
5298 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5300 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5302 /* Identifiers of events. */
5304 /* Notification of a default vnic allocaiton or free */
5305 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5307 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5308 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5309 /* Event specific data */
5310 uint32_t event_data2;
5313 * This value is written by the NIC such that it will be different
5314 * for each pass through the completion queue. The even passes
5315 * will write 1. The odd passes will write 0.
5317 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5320 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5322 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5323 /* 8-lsb timestamp from POR (100-msec resolution) */
5324 uint8_t timestamp_lo;
5325 /* 16-lsb timestamp from POR (100-msec resolution) */
5326 uint16_t timestamp_hi;
5327 /* Event specific data */
5328 uint32_t event_data1;
5329 /* Indicates default vnic configuration change */
5330 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5332 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5335 * If this field is set to 1, then it indicates that
5336 * a default VNIC has been allocate.
5338 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5341 * If this field is set to 2, then it indicates that
5342 * a default VNIC has been freed.
5344 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5346 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5347 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5348 /* Indicates the physical function this event occurred on. */
5349 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5351 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5353 /* Indicates the virtual function this event occurred on */
5354 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5356 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5358 } __attribute__((packed));
5360 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5361 struct hwrm_async_event_cmpl_hw_flow_aged {
5364 * This field indicates the exact type of the completion.
5365 * By convention, the LSB identifies the length of the
5366 * record in 16B units. Even values indicate 16B
5367 * records. Odd values indicate 32B
5370 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5372 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5373 /* HWRM Asynchronous Event Information */
5374 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5376 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5377 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5378 /* Identifiers of events. */
5380 /* Notification of a hw flow aged */
5381 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5383 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5384 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5385 /* Event specific data */
5386 uint32_t event_data2;
5389 * This value is written by the NIC such that it will be different
5390 * for each pass through the completion queue. The even passes
5391 * will write 1. The odd passes will write 0.
5393 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5395 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5396 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5397 /* 8-lsb timestamp from POR (100-msec resolution) */
5398 uint8_t timestamp_lo;
5399 /* 16-lsb timestamp from POR (100-msec resolution) */
5400 uint16_t timestamp_hi;
5401 /* Event specific data */
5402 uint32_t event_data1;
5403 /* Indicates flow ID this event occurred on. */
5404 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5405 UINT32_C(0x7fffffff)
5406 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5408 /* Indicates flow direction this event occurred on. */
5409 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5410 UINT32_C(0x80000000)
5412 * If this bit set to 0, then it indicates that the aged
5413 * event was rx flow.
5415 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
5416 (UINT32_C(0x0) << 31)
5418 * If this bit is set to 1, then it indicates that the aged
5419 * event was tx flow.
5421 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
5422 (UINT32_C(0x1) << 31)
5423 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
5424 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
5425 } __attribute__((packed));
5427 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
5428 struct hwrm_async_event_cmpl_eem_cache_flush_req {
5431 * This field indicates the exact type of the completion.
5432 * By convention, the LSB identifies the length of the
5433 * record in 16B units. Even values indicate 16B
5434 * records. Odd values indicate 32B
5437 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
5439 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
5441 /* HWRM Asynchronous Event Information */
5442 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
5444 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
5445 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
5446 /* Identifiers of events. */
5448 /* Notification of a eem_cache_flush request */
5449 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
5451 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
5452 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
5453 /* Event specific data */
5454 uint32_t event_data2;
5457 * This value is written by the NIC such that it will be different
5458 * for each pass through the completion queue. The even passes
5459 * will write 1. The odd passes will write 0.
5461 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
5464 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
5466 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
5467 /* 8-lsb timestamp from POR (100-msec resolution) */
5468 uint8_t timestamp_lo;
5469 /* 16-lsb timestamp from POR (100-msec resolution) */
5470 uint16_t timestamp_hi;
5471 /* Event specific data */
5472 uint32_t event_data1;
5473 } __attribute__((packed));
5475 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
5476 struct hwrm_async_event_cmpl_eem_cache_flush_done {
5479 * This field indicates the exact type of the completion.
5480 * By convention, the LSB identifies the length of the
5481 * record in 16B units. Even values indicate 16B
5482 * records. Odd values indicate 32B
5485 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
5487 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
5489 /* HWRM Asynchronous Event Information */
5490 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
5492 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
5493 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
5494 /* Identifiers of events. */
5497 * Notification of a host eem_cache_flush has completed. This event
5498 * is generated by the host driver.
5500 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
5502 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
5503 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
5504 /* Event specific data */
5505 uint32_t event_data2;
5508 * This value is written by the NIC such that it will be different
5509 * for each pass through the completion queue. The even passes
5510 * will write 1. The odd passes will write 0.
5512 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
5515 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
5517 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
5518 /* 8-lsb timestamp from POR (100-msec resolution) */
5519 uint8_t timestamp_lo;
5520 /* 16-lsb timestamp from POR (100-msec resolution) */
5521 uint16_t timestamp_hi;
5522 /* Event specific data */
5523 uint32_t event_data1;
5524 /* Indicates function ID that this event occurred on. */
5525 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
5527 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
5529 } __attribute__((packed));
5531 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
5532 struct hwrm_async_event_cmpl_tcp_flag_action_change {
5535 * This field indicates the exact type of the completion.
5536 * By convention, the LSB identifies the length of the
5537 * record in 16B units. Even values indicate 16B
5538 * records. Odd values indicate 32B
5541 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
5543 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
5545 /* HWRM Asynchronous Event Information */
5546 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5548 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
5549 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
5550 /* Identifiers of events. */
5552 /* Notification of tcp flag action change */
5553 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
5555 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
5556 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
5557 /* Event specific data */
5558 uint32_t event_data2;
5561 * This value is written by the NIC such that it will be different
5562 * for each pass through the completion queue. The even passes
5563 * will write 1. The odd passes will write 0.
5565 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
5568 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
5570 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
5571 /* 8-lsb timestamp from POR (100-msec resolution) */
5572 uint8_t timestamp_lo;
5573 /* 16-lsb timestamp from POR (100-msec resolution) */
5574 uint16_t timestamp_hi;
5575 /* Event specific data */
5576 uint32_t event_data1;
5577 } __attribute__((packed));
5579 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
5580 struct hwrm_async_event_cmpl_eem_flow_active {
5583 * This field indicates the exact type of the completion.
5584 * By convention, the LSB identifies the length of the
5585 * record in 16B units. Even values indicate 16B
5586 * records. Odd values indicate 32B
5589 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
5591 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
5592 /* HWRM Asynchronous Event Information */
5593 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
5595 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
5596 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
5597 /* Identifiers of events. */
5599 /* Notification of an active eem flow */
5600 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
5602 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
5603 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
5604 /* Event specific data */
5605 uint32_t event_data2;
5606 /* Indicates the 2nd global id this event occurred on. */
5607 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
5608 UINT32_C(0x3fffffff)
5609 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
5612 * Indicates flow direction of the flow identified by
5615 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
5616 UINT32_C(0x40000000)
5617 /* If this bit is set to 0, then it indicates that this rx flow. */
5618 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
5619 (UINT32_C(0x0) << 30)
5620 /* If this bit is set to 1, then it indicates that this tx flow. */
5621 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
5622 (UINT32_C(0x1) << 30)
5623 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
5624 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
5627 * This value is written by the NIC such that it will be different
5628 * for each pass through the completion queue. The even passes
5629 * will write 1. The odd passes will write 0.
5631 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
5633 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
5635 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
5636 /* 8-lsb timestamp from POR (100-msec resolution) */
5637 uint8_t timestamp_lo;
5638 /* 16-lsb timestamp from POR (100-msec resolution) */
5639 uint16_t timestamp_hi;
5640 /* Event specific data */
5641 uint32_t event_data1;
5642 /* Indicates the 1st global id this event occurred on. */
5643 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
5644 UINT32_C(0x3fffffff)
5645 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
5648 * Indicates flow direction of the flow identified by the
5651 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
5652 UINT32_C(0x40000000)
5653 /* If this bit is set to 0, then it indicates that this is rx flow. */
5654 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
5655 (UINT32_C(0x0) << 30)
5656 /* If this bit is set to 1, then it indicates that this is tx flow. */
5657 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
5658 (UINT32_C(0x1) << 30)
5659 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
5660 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
5662 * Indicates EEM flow aging mode this event occurred on. If
5663 * this bit is set to 0, the event_data1 is the EEM global
5664 * ID. If this bit is set to 1, the event_data1 is the number
5665 * of global ID in the context memory.
5667 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
5668 UINT32_C(0x80000000)
5669 /* EEM flow aging mode 0. */
5670 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
5671 (UINT32_C(0x0) << 31)
5672 /* EEM flow aging mode 1. */
5673 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
5674 (UINT32_C(0x1) << 31)
5675 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
5676 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
5677 } __attribute__((packed));
5679 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
5680 struct hwrm_async_event_cmpl_eem_cfg_change {
5683 * This field indicates the exact type of the completion.
5684 * By convention, the LSB identifies the length of the
5685 * record in 16B units. Even values indicate 16B
5686 * records. Odd values indicate 32B
5689 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
5691 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
5692 /* HWRM Asynchronous Event Information */
5693 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5695 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
5696 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5697 /* Identifiers of events. */
5699 /* Notification of EEM configuration change */
5700 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
5702 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
5703 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
5704 /* Event specific data */
5705 uint32_t event_data2;
5708 * This value is written by the NIC such that it will be different
5709 * for each pass through the completion queue. The even passes
5710 * will write 1. The odd passes will write 0.
5712 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
5714 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5715 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
5716 /* 8-lsb timestamp from POR (100-msec resolution) */
5717 uint8_t timestamp_lo;
5718 /* 16-lsb timestamp from POR (100-msec resolution) */
5719 uint16_t timestamp_hi;
5720 /* Event specific data */
5721 uint32_t event_data1;
5723 * Value of 1 to indicate EEM TX configuration is enabled. Value of
5724 * 0 to indicate the EEM TX configuration is disabled.
5726 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
5729 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
5730 * to indicate the EEM RX configuration is disabled.
5732 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
5734 } __attribute__((packed));
5736 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
5737 struct hwrm_async_event_cmpl_fw_trace_msg {
5740 * This field indicates the exact type of the completion.
5741 * By convention, the LSB identifies the length of the
5742 * record in 16B units. Even values indicate 16B
5743 * records. Odd values indicate 32B
5746 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
5748 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
5749 /* HWRM Asynchronous Event Information */
5750 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
5752 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
5753 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
5754 /* Identifiers of events. */
5756 /* Firmware trace log message */
5757 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
5759 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
5760 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
5761 /* Trace byte 0 to 3 */
5762 uint32_t event_data2;
5764 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
5766 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
5768 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
5770 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
5772 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
5774 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
5776 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
5777 UINT32_C(0xff000000)
5778 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
5781 * This value is written by the NIC such that it will be different
5782 * for each pass through the completion queue. The even passes
5783 * will write 1. The odd passes will write 0.
5785 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
5787 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
5788 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
5790 uint8_t timestamp_lo;
5791 /* Indicates if the string is partial or complete. */
5792 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
5794 /* Complete string */
5795 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
5797 /* Partial string */
5798 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
5800 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
5801 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
5802 /* Indicates the firmware that sent the trace message. */
5803 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
5805 /* Primary firmware */
5806 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
5807 (UINT32_C(0x0) << 1)
5808 /* Secondary firmware */
5809 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
5810 (UINT32_C(0x1) << 1)
5811 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
5812 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
5813 /* Trace byte 4 to 5 */
5814 uint16_t timestamp_hi;
5816 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
5818 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
5820 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
5822 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
5823 /* Trace byte 6 to 9 */
5824 uint32_t event_data1;
5826 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
5828 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
5830 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
5832 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
5834 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
5836 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
5838 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
5839 UINT32_C(0xff000000)
5840 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
5841 } __attribute__((packed));
5843 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
5844 struct hwrm_async_event_cmpl_hwrm_error {
5847 * This field indicates the exact type of the completion.
5848 * By convention, the LSB identifies the length of the
5849 * record in 16B units. Even values indicate 16B
5850 * records. Odd values indicate 32B
5853 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
5855 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
5856 /* HWRM Asynchronous Event Information */
5857 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
5859 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
5860 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
5861 /* Identifiers of events. */
5864 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
5866 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
5867 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
5868 /* Event specific data */
5869 uint32_t event_data2;
5870 /* Severity of HWRM Error */
5871 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
5873 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
5875 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
5877 /* Non-fatal Error */
5878 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
5881 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
5883 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
5884 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
5887 * This value is written by the NIC such that it will be different
5888 * for each pass through the completion queue. The even passes
5889 * will write 1. The odd passes will write 0.
5891 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
5893 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
5894 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
5895 /* 8-lsb timestamp from POR (100-msec resolution) */
5896 uint8_t timestamp_lo;
5897 /* 16-lsb timestamp from POR (100-msec resolution) */
5898 uint16_t timestamp_hi;
5899 /* Event specific data */
5900 uint32_t event_data1;
5901 /* Time stamp for error event */
5902 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
5904 } __attribute__((packed));
5906 /*******************
5908 *******************/
5911 /* hwrm_func_reset_input (size:192b/24B) */
5912 struct hwrm_func_reset_input {
5913 /* The HWRM command request type. */
5916 * The completion ring to send the completion event on. This should
5917 * be the NQ ID returned from the `nq_alloc` HWRM command.
5921 * The sequence ID is used by the driver for tracking multiple
5922 * commands. This ID is treated as opaque data by the firmware and
5923 * the value is returned in the `hwrm_resp_hdr` upon completion.
5927 * The target ID of the command:
5928 * * 0x0-0xFFF8 - The function ID
5929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
5930 * * 0xFFFD - Reserved for user-space HWRM interface
5935 * A physical address pointer pointing to a host buffer that the
5936 * command's response data will be written. This can be either a host
5937 * physical address (HPA) or a guest physical address (GPA) and must
5938 * point to a physically contiguous block of memory.
5943 * This bit must be '1' for the vf_id_valid field to be
5946 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
5948 * The ID of the VF that this PF is trying to reset.
5949 * Only the parent PF shall be allowed to reset a child VF.
5951 * A parent PF driver shall use this field only when a specific child VF
5952 * is requested to be reset.
5955 /* This value indicates the level of a function reset. */
5956 uint8_t func_reset_level;
5958 * Reset the caller function and its children VFs (if any). If no
5959 * children functions exist, then reset the caller function only.
5961 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
5963 /* Reset the caller function only */
5964 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
5967 * Reset all children VFs of the caller function driver if the
5968 * caller is a PF driver.
5969 * It is an error to specify this level by a VF driver.
5970 * It is an error to specify this level by a PF driver with
5973 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
5976 * Reset a specific VF of the caller function driver if the caller
5977 * is the parent PF driver.
5978 * It is an error to specify this level by a VF driver.
5979 * It is an error to specify this level by a PF driver that is not
5980 * the parent of the VF that is being requested to reset.
5982 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
5984 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
5985 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
5987 } __attribute__((packed));
5989 /* hwrm_func_reset_output (size:128b/16B) */
5990 struct hwrm_func_reset_output {
5991 /* The specific error status for the command. */
5992 uint16_t error_code;
5993 /* The HWRM command request type. */
5995 /* The sequence ID from the original command. */
5997 /* The length of the response data in number of bytes. */
5999 uint8_t unused_0[7];
6001 * This field is used in Output records to indicate that the output
6002 * is completely written to RAM. This field should be read as '1'
6003 * to indicate that the output has been completely written.
6004 * When writing a command completion or response to an internal processor,
6005 * the order of writes has to be such that this field is written last.
6008 } __attribute__((packed));
6010 /********************
6011 * hwrm_func_getfid *
6012 ********************/
6015 /* hwrm_func_getfid_input (size:192b/24B) */
6016 struct hwrm_func_getfid_input {
6017 /* The HWRM command request type. */
6020 * The completion ring to send the completion event on. This should
6021 * be the NQ ID returned from the `nq_alloc` HWRM command.
6025 * The sequence ID is used by the driver for tracking multiple
6026 * commands. This ID is treated as opaque data by the firmware and
6027 * the value is returned in the `hwrm_resp_hdr` upon completion.
6031 * The target ID of the command:
6032 * * 0x0-0xFFF8 - The function ID
6033 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6034 * * 0xFFFD - Reserved for user-space HWRM interface
6039 * A physical address pointer pointing to a host buffer that the
6040 * command's response data will be written. This can be either a host
6041 * physical address (HPA) or a guest physical address (GPA) and must
6042 * point to a physically contiguous block of memory.
6047 * This bit must be '1' for the pci_id field to be
6050 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6052 * This value is the PCI ID of the queried function.
6053 * If ARI is enabled, then it is
6054 * Bus Number (8b):Function Number(8b). Otherwise, it is
6055 * Bus Number (8b):Device Number (5b):Function Number(3b).
6058 uint8_t unused_0[2];
6059 } __attribute__((packed));
6061 /* hwrm_func_getfid_output (size:128b/16B) */
6062 struct hwrm_func_getfid_output {
6063 /* The specific error status for the command. */
6064 uint16_t error_code;
6065 /* The HWRM command request type. */
6067 /* The sequence ID from the original command. */
6069 /* The length of the response data in number of bytes. */
6072 * FID value. This value is used to identify operations on the PCI
6073 * bus as belonging to a particular PCI function.
6076 uint8_t unused_0[5];
6078 * This field is used in Output records to indicate that the output
6079 * is completely written to RAM. This field should be read as '1'
6080 * to indicate that the output has been completely written.
6081 * When writing a command completion or response to an internal processor,
6082 * the order of writes has to be such that this field is written last.
6085 } __attribute__((packed));
6087 /**********************
6088 * hwrm_func_vf_alloc *
6089 **********************/
6092 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6093 struct hwrm_func_vf_alloc_input {
6094 /* The HWRM command request type. */
6097 * The completion ring to send the completion event on. This should
6098 * be the NQ ID returned from the `nq_alloc` HWRM command.
6102 * The sequence ID is used by the driver for tracking multiple
6103 * commands. This ID is treated as opaque data by the firmware and
6104 * the value is returned in the `hwrm_resp_hdr` upon completion.
6108 * The target ID of the command:
6109 * * 0x0-0xFFF8 - The function ID
6110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6111 * * 0xFFFD - Reserved for user-space HWRM interface
6116 * A physical address pointer pointing to a host buffer that the
6117 * command's response data will be written. This can be either a host
6118 * physical address (HPA) or a guest physical address (GPA) and must
6119 * point to a physically contiguous block of memory.
6124 * This bit must be '1' for the first_vf_id field to be
6127 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6129 * This value is used to identify a Virtual Function (VF).
6130 * The scope of VF ID is local within a PF.
6132 uint16_t first_vf_id;
6133 /* The number of virtual functions requested. */
6135 } __attribute__((packed));
6137 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6138 struct hwrm_func_vf_alloc_output {
6139 /* The specific error status for the command. */
6140 uint16_t error_code;
6141 /* The HWRM command request type. */
6143 /* The sequence ID from the original command. */
6145 /* The length of the response data in number of bytes. */
6147 /* The ID of the first VF allocated. */
6148 uint16_t first_vf_id;
6149 uint8_t unused_0[5];
6151 * This field is used in Output records to indicate that the output
6152 * is completely written to RAM. This field should be read as '1'
6153 * to indicate that the output has been completely written.
6154 * When writing a command completion or response to an internal processor,
6155 * the order of writes has to be such that this field is written last.
6158 } __attribute__((packed));
6160 /*********************
6161 * hwrm_func_vf_free *
6162 *********************/
6165 /* hwrm_func_vf_free_input (size:192b/24B) */
6166 struct hwrm_func_vf_free_input {
6167 /* The HWRM command request type. */
6170 * The completion ring to send the completion event on. This should
6171 * be the NQ ID returned from the `nq_alloc` HWRM command.
6175 * The sequence ID is used by the driver for tracking multiple
6176 * commands. This ID is treated as opaque data by the firmware and
6177 * the value is returned in the `hwrm_resp_hdr` upon completion.
6181 * The target ID of the command:
6182 * * 0x0-0xFFF8 - The function ID
6183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6184 * * 0xFFFD - Reserved for user-space HWRM interface
6189 * A physical address pointer pointing to a host buffer that the
6190 * command's response data will be written. This can be either a host
6191 * physical address (HPA) or a guest physical address (GPA) and must
6192 * point to a physically contiguous block of memory.
6197 * This bit must be '1' for the first_vf_id field to be
6200 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6202 * This value is used to identify a Virtual Function (VF).
6203 * The scope of VF ID is local within a PF.
6205 uint16_t first_vf_id;
6207 * The number of virtual functions requested.
6208 * 0xFFFF - Cleanup all children of this PF.
6211 } __attribute__((packed));
6213 /* hwrm_func_vf_free_output (size:128b/16B) */
6214 struct hwrm_func_vf_free_output {
6215 /* The specific error status for the command. */
6216 uint16_t error_code;
6217 /* The HWRM command request type. */
6219 /* The sequence ID from the original command. */
6221 /* The length of the response data in number of bytes. */
6223 uint8_t unused_0[7];
6225 * This field is used in Output records to indicate that the output
6226 * is completely written to RAM. This field should be read as '1'
6227 * to indicate that the output has been completely written.
6228 * When writing a command completion or response to an internal processor,
6229 * the order of writes has to be such that this field is written last.
6232 } __attribute__((packed));
6234 /********************
6235 * hwrm_func_vf_cfg *
6236 ********************/
6239 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6240 struct hwrm_func_vf_cfg_input {
6241 /* The HWRM command request type. */
6244 * The completion ring to send the completion event on. This should
6245 * be the NQ ID returned from the `nq_alloc` HWRM command.
6249 * The sequence ID is used by the driver for tracking multiple
6250 * commands. This ID is treated as opaque data by the firmware and
6251 * the value is returned in the `hwrm_resp_hdr` upon completion.
6255 * The target ID of the command:
6256 * * 0x0-0xFFF8 - The function ID
6257 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6258 * * 0xFFFD - Reserved for user-space HWRM interface
6263 * A physical address pointer pointing to a host buffer that the
6264 * command's response data will be written. This can be either a host
6265 * physical address (HPA) or a guest physical address (GPA) and must
6266 * point to a physically contiguous block of memory.
6271 * This bit must be '1' for the mtu field to be
6274 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6277 * This bit must be '1' for the guest_vlan field to be
6280 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6283 * This bit must be '1' for the async_event_cr field to be
6286 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6289 * This bit must be '1' for the dflt_mac_addr field to be
6292 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6295 * This bit must be '1' for the num_rsscos_ctxs field to be
6298 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6301 * This bit must be '1' for the num_cmpl_rings field to be
6304 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6307 * This bit must be '1' for the num_tx_rings field to be
6310 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6313 * This bit must be '1' for the num_rx_rings field to be
6316 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6319 * This bit must be '1' for the num_l2_ctxs field to be
6322 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6325 * This bit must be '1' for the num_vnics field to be
6328 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
6331 * This bit must be '1' for the num_stat_ctxs field to be
6334 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6337 * This bit must be '1' for the num_hw_ring_grps field to be
6340 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6343 * The maximum transmission unit requested on the function.
6344 * The HWRM should make sure that the mtu of
6345 * the function does not exceed the mtu of the physical
6346 * port that this function is associated with.
6348 * In addition to requesting mtu per function, it is
6349 * possible to configure mtu per transmit ring.
6350 * By default, the mtu of each transmit ring associated
6351 * with a function is equal to the mtu of the function.
6352 * The HWRM should make sure that the mtu of each transmit
6353 * ring that is assigned to a function has a valid mtu.
6357 * The guest VLAN for the function being configured.
6358 * This field's format is same as 802.1Q Tag's
6359 * Tag Control Information (TCI) format that includes both
6360 * Priority Code Point (PCP) and VLAN Identifier (VID).
6362 uint16_t guest_vlan;
6364 * ID of the target completion ring for receiving asynchronous
6365 * event completions. If this field is not valid, then the
6366 * HWRM shall use the default completion ring of the function
6367 * that is being configured as the target completion ring for
6368 * providing any asynchronous event completions for that
6370 * If this field is valid, then the HWRM shall use the
6371 * completion ring identified by this ID as the target
6372 * completion ring for providing any asynchronous event
6373 * completions for the function that is being configured.
6375 uint16_t async_event_cr;
6377 * This value is the current MAC address requested by the VF
6378 * driver to be configured on this VF. A value of
6379 * 00-00-00-00-00-00 indicates no MAC address configuration
6380 * is requested by the VF driver.
6381 * The parent PF driver may reject or overwrite this
6384 uint8_t dflt_mac_addr[6];
6387 * This bit requests that the firmware test to see if all the assets
6388 * requested in this command (i.e. number of TX rings) are available.
6389 * The firmware will return an error if the requested assets are
6390 * not available. The firwmare will NOT reserve the assets if they
6393 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6396 * This bit requests that the firmware test to see if all the assets
6397 * requested in this command (i.e. number of RX rings) are available.
6398 * The firmware will return an error if the requested assets are
6399 * not available. The firwmare will NOT reserve the assets if they
6402 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6405 * This bit requests that the firmware test to see if all the assets
6406 * requested in this command (i.e. number of CMPL rings) are available.
6407 * The firmware will return an error if the requested assets are
6408 * not available. The firwmare will NOT reserve the assets if they
6411 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6414 * This bit requests that the firmware test to see if all the assets
6415 * requested in this command (i.e. number of RSS ctx) are available.
6416 * The firmware will return an error if the requested assets are
6417 * not available. The firwmare will NOT reserve the assets if they
6420 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6423 * This bit requests that the firmware test to see if all the assets
6424 * requested in this command (i.e. number of ring groups) are available.
6425 * The firmware will return an error if the requested assets are
6426 * not available. The firwmare will NOT reserve the assets if they
6429 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6432 * This bit requests that the firmware test to see if all the assets
6433 * requested in this command (i.e. number of stat ctx) are available.
6434 * The firmware will return an error if the requested assets are
6435 * not available. The firwmare will NOT reserve the assets if they
6438 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6441 * This bit requests that the firmware test to see if all the assets
6442 * requested in this command (i.e. number of VNICs) are available.
6443 * The firmware will return an error if the requested assets are
6444 * not available. The firwmare will NOT reserve the assets if they
6447 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6450 * This bit requests that the firmware test to see if all the assets
6451 * requested in this command (i.e. number of L2 ctx) are available.
6452 * The firmware will return an error if the requested assets are
6453 * not available. The firwmare will NOT reserve the assets if they
6456 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6458 /* The number of RSS/COS contexts requested for the VF. */
6459 uint16_t num_rsscos_ctxs;
6460 /* The number of completion rings requested for the VF. */
6461 uint16_t num_cmpl_rings;
6462 /* The number of transmit rings requested for the VF. */
6463 uint16_t num_tx_rings;
6464 /* The number of receive rings requested for the VF. */
6465 uint16_t num_rx_rings;
6466 /* The number of L2 contexts requested for the VF. */
6467 uint16_t num_l2_ctxs;
6468 /* The number of vnics requested for the VF. */
6470 /* The number of statistic contexts requested for the VF. */
6471 uint16_t num_stat_ctxs;
6472 /* The number of HW ring groups requested for the VF. */
6473 uint16_t num_hw_ring_grps;
6474 uint8_t unused_0[4];
6475 } __attribute__((packed));
6477 /* hwrm_func_vf_cfg_output (size:128b/16B) */
6478 struct hwrm_func_vf_cfg_output {
6479 /* The specific error status for the command. */
6480 uint16_t error_code;
6481 /* The HWRM command request type. */
6483 /* The sequence ID from the original command. */
6485 /* The length of the response data in number of bytes. */
6487 uint8_t unused_0[7];
6489 * This field is used in Output records to indicate that the output
6490 * is completely written to RAM. This field should be read as '1'
6491 * to indicate that the output has been completely written.
6492 * When writing a command completion or response to an internal processor,
6493 * the order of writes has to be such that this field is written last.
6496 } __attribute__((packed));
6498 /*******************
6500 *******************/
6503 /* hwrm_func_qcaps_input (size:192b/24B) */
6504 struct hwrm_func_qcaps_input {
6505 /* The HWRM command request type. */
6508 * The completion ring to send the completion event on. This should
6509 * be the NQ ID returned from the `nq_alloc` HWRM command.
6513 * The sequence ID is used by the driver for tracking multiple
6514 * commands. This ID is treated as opaque data by the firmware and
6515 * the value is returned in the `hwrm_resp_hdr` upon completion.
6519 * The target ID of the command:
6520 * * 0x0-0xFFF8 - The function ID
6521 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6522 * * 0xFFFD - Reserved for user-space HWRM interface
6527 * A physical address pointer pointing to a host buffer that the
6528 * command's response data will be written. This can be either a host
6529 * physical address (HPA) or a guest physical address (GPA) and must
6530 * point to a physically contiguous block of memory.
6534 * Function ID of the function that is being queried.
6535 * 0xFF... (All Fs) if the query is for the requesting
6539 uint8_t unused_0[6];
6540 } __attribute__((packed));
6542 /* hwrm_func_qcaps_output (size:640b/80B) */
6543 struct hwrm_func_qcaps_output {
6544 /* The specific error status for the command. */
6545 uint16_t error_code;
6546 /* The HWRM command request type. */
6548 /* The sequence ID from the original command. */
6550 /* The length of the response data in number of bytes. */
6553 * FID value. This value is used to identify operations on the PCI
6554 * bus as belonging to a particular PCI function.
6558 * Port ID of port that this function is associated with.
6559 * Valid only for the PF.
6560 * 0xFF... (All Fs) if this function is not associated with
6562 * 0xFF... (All Fs) if this function is called from a VF.
6566 /* If 1, then Push mode is supported on this function. */
6567 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
6570 * If 1, then the global MSI-X auto-masking is enabled for the
6573 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
6576 * If 1, then the Precision Time Protocol (PTP) processing
6577 * is supported on this function.
6578 * The HWRM should enable PTP on only a single Physical
6579 * Function (PF) per port.
6581 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
6584 * If 1, then RDMA over Converged Ethernet (RoCE) v1
6585 * is supported on this function.
6587 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
6590 * If 1, then RDMA over Converged Ethernet (RoCE) v2
6591 * is supported on this function.
6593 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
6596 * If 1, then control and configuration of WoL magic packet
6597 * are supported on this function.
6599 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
6602 * If 1, then control and configuration of bitmap pattern
6603 * packet are supported on this function.
6605 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
6608 * If set to 1, then the control and configuration of rate limit
6609 * of an allocated TX ring on the queried function is supported.
6611 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
6614 * If 1, then control and configuration of minimum and
6615 * maximum bandwidths are supported on the queried function.
6617 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
6620 * If the query is for a VF, then this flag shall be ignored.
6621 * If this query is for a PF and this flag is set to 1,
6622 * then the PF has the capability to set the rate limits
6623 * on the TX rings of its children VFs.
6624 * If this query is for a PF and this flag is set to 0, then
6625 * the PF does not have the capability to set the rate limits
6626 * on the TX rings of its children VFs.
6628 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
6631 * If the query is for a VF, then this flag shall be ignored.
6632 * If this query is for a PF and this flag is set to 1,
6633 * then the PF has the capability to set the minimum and/or
6634 * maximum bandwidths for its children VFs.
6635 * If this query is for a PF and this flag is set to 0, then
6636 * the PF does not have the capability to set the minimum or
6637 * maximum bandwidths for its children VFs.
6639 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
6642 * Standard TX Ring mode is used for the allocation of TX ring
6643 * and underlying scheduling resources that allow bandwidth
6644 * reservation and limit settings on the queried function.
6645 * If set to 1, then standard TX ring mode is supported
6646 * on the queried function.
6647 * If set to 0, then standard TX ring mode is not available
6648 * on the queried function.
6650 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
6653 * If the query is for a VF, then this flag shall be ignored,
6654 * If this query is for a PF and this flag is set to 1,
6655 * then the PF has the capability to detect GENEVE tunnel
6658 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
6661 * If the query is for a VF, then this flag shall be ignored,
6662 * If this query is for a PF and this flag is set to 1,
6663 * then the PF has the capability to detect NVGRE tunnel
6666 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
6669 * If the query is for a VF, then this flag shall be ignored,
6670 * If this query is for a PF and this flag is set to 1,
6671 * then the PF has the capability to detect GRE tunnel
6674 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
6677 * If the query is for a VF, then this flag shall be ignored,
6678 * If this query is for a PF and this flag is set to 1,
6679 * then the PF has the capability to detect MPLS tunnel
6682 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
6685 * If the query is for a VF, then this flag shall be ignored,
6686 * If this query is for a PF and this flag is set to 1,
6687 * then the PF has the capability to support pcie stats.
6689 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
6692 * If the query is for a VF, then this flag shall be ignored,
6693 * If this query is for a PF and this flag is set to 1,
6694 * then the PF has the capability to adopt the VF's belonging
6697 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
6700 * If the query is for a VF, then this flag shall be ignored,
6701 * If this query is for a PF and this flag is set to 1,
6702 * then the PF has the administrative privilege to configure another PF
6704 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
6707 * If the query is for a VF, then this flag shall be ignored.
6708 * If this query is for a PF and this flag is set to 1, then
6709 * the PF will know that the firmware has the capability to track
6710 * the virtual link status.
6712 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
6715 * If 1, then this function supports the push mode that uses
6716 * write combine buffers and the long inline tx buffer descriptor.
6718 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
6721 * If 1, then FW has capability to allocate TX rings dynamically
6722 * in ring alloc even if PF reserved pool is zero.
6723 * This bit will be used only for PFs.
6725 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
6728 * When this bit is '1', it indicates that core firmware is
6729 * capable of Hot Reset.
6731 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
6734 * This flag will be set to 1 by the FW if FW supports adapter error
6737 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
6740 * If the query is for a VF, then this flag shall be ignored.
6741 * If this query is for a PF and this flag is set to 1, then
6742 * the PF has the capability to support extended stats.
6744 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
6747 * This value is current MAC address configured for this
6748 * function. A value of 00-00-00-00-00-00 indicates no
6749 * MAC address is currently configured.
6751 uint8_t mac_address[6];
6753 * The maximum number of RSS/COS contexts that can be
6754 * allocated to the function.
6756 uint16_t max_rsscos_ctx;
6758 * The maximum number of completion rings that can be
6759 * allocated to the function.
6761 uint16_t max_cmpl_rings;
6763 * The maximum number of transmit rings that can be
6764 * allocated to the function.
6766 uint16_t max_tx_rings;
6768 * The maximum number of receive rings that can be
6769 * allocated to the function.
6771 uint16_t max_rx_rings;
6773 * The maximum number of L2 contexts that can be
6774 * allocated to the function.
6776 uint16_t max_l2_ctxs;
6778 * The maximum number of VNICs that can be
6779 * allocated to the function.
6783 * The identifier for the first VF enabled on a PF. This
6784 * is valid only on the PF with SR-IOV enabled.
6785 * 0xFF... (All Fs) if this command is called on a PF with
6786 * SR-IOV disabled or on a VF.
6788 uint16_t first_vf_id;
6790 * The maximum number of VFs that can be
6791 * allocated to the function. This is valid only on the
6792 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
6793 * command is called on a PF with SR-IOV disabled or
6798 * The maximum number of statistic contexts that can be
6799 * allocated to the function.
6801 uint16_t max_stat_ctx;
6803 * The maximum number of Encapsulation records that can be
6804 * offloaded by this function.
6806 uint32_t max_encap_records;
6808 * The maximum number of decapsulation records that can
6809 * be offloaded by this function.
6811 uint32_t max_decap_records;
6813 * The maximum number of Exact Match (EM) flows that can be
6814 * offloaded by this function on the TX side.
6816 uint32_t max_tx_em_flows;
6818 * The maximum number of Wildcard Match (WM) flows that can
6819 * be offloaded by this function on the TX side.
6821 uint32_t max_tx_wm_flows;
6823 * The maximum number of Exact Match (EM) flows that can be
6824 * offloaded by this function on the RX side.
6826 uint32_t max_rx_em_flows;
6828 * The maximum number of Wildcard Match (WM) flows that can
6829 * be offloaded by this function on the RX side.
6831 uint32_t max_rx_wm_flows;
6833 * The maximum number of multicast filters that can
6834 * be supported by this function on the RX side.
6836 uint32_t max_mcast_filters;
6838 * The maximum value of flow_id that can be supported
6839 * in completion records.
6841 uint32_t max_flow_id;
6843 * The maximum number of HW ring groups that can be
6844 * supported on this function.
6846 uint32_t max_hw_ring_grps;
6848 * The maximum number of strict priority transmit rings
6849 * that can be allocated to the function.
6850 * This number indicates the maximum number of TX rings
6851 * that can be assigned strict priorities out of the
6852 * maximum number of TX rings that can be allocated
6853 * (max_tx_rings) to the function.
6855 uint16_t max_sp_tx_rings;
6858 * This field is used in Output records to indicate that the output
6859 * is completely written to RAM. This field should be read as '1'
6860 * to indicate that the output has been completely written.
6861 * When writing a command completion or response to an internal processor,
6862 * the order of writes has to be such that this field is written last.
6865 } __attribute__((packed));
6872 /* hwrm_func_qcfg_input (size:192b/24B) */
6873 struct hwrm_func_qcfg_input {
6874 /* The HWRM command request type. */
6877 * The completion ring to send the completion event on. This should
6878 * be the NQ ID returned from the `nq_alloc` HWRM command.
6882 * The sequence ID is used by the driver for tracking multiple
6883 * commands. This ID is treated as opaque data by the firmware and
6884 * the value is returned in the `hwrm_resp_hdr` upon completion.
6888 * The target ID of the command:
6889 * * 0x0-0xFFF8 - The function ID
6890 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6891 * * 0xFFFD - Reserved for user-space HWRM interface
6896 * A physical address pointer pointing to a host buffer that the
6897 * command's response data will be written. This can be either a host
6898 * physical address (HPA) or a guest physical address (GPA) and must
6899 * point to a physically contiguous block of memory.
6903 * Function ID of the function that is being queried.
6904 * 0xFF... (All Fs) if the query is for the requesting
6908 uint8_t unused_0[6];
6909 } __attribute__((packed));
6911 /* hwrm_func_qcfg_output (size:704b/88B) */
6912 struct hwrm_func_qcfg_output {
6913 /* The specific error status for the command. */
6914 uint16_t error_code;
6915 /* The HWRM command request type. */
6917 /* The sequence ID from the original command. */
6919 /* The length of the response data in number of bytes. */
6922 * FID value. This value is used to identify operations on the PCI
6923 * bus as belonging to a particular PCI function.
6927 * Port ID of port that this function is associated with.
6928 * 0xFF... (All Fs) if this function is not associated with
6933 * This value is the current VLAN setting for this
6934 * function. The value of 0 for this field indicates
6935 * no priority tagging or VLAN is used.
6936 * This field's format is same as 802.1Q Tag's
6937 * Tag Control Information (TCI) format that includes both
6938 * Priority Code Point (PCP) and VLAN Identifier (VID).
6943 * If 1, then magic packet based Out-Of-Box WoL is enabled on
6944 * the port associated with this function.
6946 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
6949 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
6950 * on the port associated with this function.
6952 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
6955 * If set to 1, then FW based DCBX agent is enabled and running on
6956 * the port associated with this function.
6957 * If set to 0, then DCBX agent is not running in the firmware.
6959 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
6962 * Standard TX Ring mode is used for the allocation of TX ring
6963 * and underlying scheduling resources that allow bandwidth
6964 * reservation and limit settings on the queried function.
6965 * If set to 1, then standard TX ring mode is enabled
6966 * on the queried function.
6967 * If set to 0, then the standard TX ring mode is disabled
6968 * on the queried function. In this extended TX ring resource
6969 * mode, the minimum and maximum bandwidth settings are not
6970 * supported to allow the allocation of TX rings to span multiple
6973 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
6976 * If set to 1 then FW based LLDP agent is enabled and running on
6977 * the port associated with this function.
6978 * If set to 0 then the LLDP agent is not running in the firmware.
6980 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
6983 * If set to 1, then multi-host mode is active for this function.
6984 * If set to 0, then multi-host mode is inactive for this function
6985 * or not applicable for this device.
6987 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
6990 * If the function that is being queried is a PF, then the HWRM shall
6991 * set this field to 0 and the HWRM client shall ignore this field.
6992 * If the function that is being queried is a VF, then the HWRM shall
6993 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
6994 * shall set this field to 0.
6996 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
6999 * If set to 1, then secure mode is enabled for this function or device.
7000 * If set to 0, then secure mode is disabled (or normal mode) for this
7001 * function or device.
7003 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
7006 * This value is current MAC address configured for this
7007 * function. A value of 00-00-00-00-00-00 indicates no
7008 * MAC address is currently configured.
7010 uint8_t mac_address[6];
7012 * This value is current PCI ID of this
7013 * function. If ARI is enabled, then it is
7014 * Bus Number (8b):Function Number(8b). Otherwise, it is
7015 * Bus Number (8b):Device Number (4b):Function Number(4b).
7016 * If multi-host mode is active, the 4 lsb will indicate
7017 * the PF index for this function.
7021 * The number of RSS/COS contexts currently
7022 * allocated to the function.
7024 uint16_t alloc_rsscos_ctx;
7026 * The number of completion rings currently allocated to
7027 * the function. This does not include the rings allocated
7028 * to any children functions if any.
7030 uint16_t alloc_cmpl_rings;
7032 * The number of transmit rings currently allocated to
7033 * the function. This does not include the rings allocated
7034 * to any children functions if any.
7036 uint16_t alloc_tx_rings;
7038 * The number of receive rings currently allocated to
7039 * the function. This does not include the rings allocated
7040 * to any children functions if any.
7042 uint16_t alloc_rx_rings;
7043 /* The allocated number of L2 contexts to the function. */
7044 uint16_t alloc_l2_ctx;
7045 /* The allocated number of vnics to the function. */
7046 uint16_t alloc_vnics;
7048 * The maximum transmission unit of the function.
7049 * If the reported mtu value is non-zero then it will used for the
7050 * rings allocated on this function. otherwise the default
7051 * value is used if ring MTU is not specified.
7055 * The maximum receive unit of the function.
7056 * For vnics allocated on this function, this default
7057 * value is used if vnic MRU is not specified.
7060 /* The statistics context assigned to a function. */
7061 uint16_t stat_ctx_id;
7063 * The HWRM shall return Unknown value for this field
7064 * when this command is used to query VF's configuration.
7066 uint8_t port_partition_type;
7067 /* Single physical function */
7068 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
7069 /* Multiple physical functions */
7070 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
7071 /* Network Partitioning 1.0 */
7072 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
7073 /* Network Partitioning 1.5 */
7074 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
7075 /* Network Partitioning 2.0 */
7076 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
7078 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
7080 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7081 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7083 * This field will indicate number of physical functions on this port_partition.
7084 * HWRM shall return unavail (i.e. value of 0) for this field
7085 * when this command is used to query VF's configuration or
7086 * from older firmware that doesn't support this field.
7088 uint8_t port_pf_cnt;
7089 /* number of PFs is not available */
7090 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7091 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7092 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7094 * The default VNIC ID assigned to a function that is
7097 uint16_t dflt_vnic_id;
7098 uint16_t max_mtu_configured;
7100 * Minimum BW allocated for this function.
7101 * The HWRM will translate this value into byte counter and
7102 * time interval used for the scheduler inside the device.
7103 * A value of 0 indicates the minimum bandwidth is not
7107 /* The bandwidth value. */
7108 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7110 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7111 /* The granularity of the value (bits or bytes). */
7112 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7113 UINT32_C(0x10000000)
7114 /* Value is in bits. */
7115 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7116 (UINT32_C(0x0) << 28)
7117 /* Value is in bytes. */
7118 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7119 (UINT32_C(0x1) << 28)
7120 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7121 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7122 /* bw_value_unit is 3 b */
7123 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7124 UINT32_C(0xe0000000)
7125 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7126 /* Value is in Mb or MB (base 10). */
7127 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7128 (UINT32_C(0x0) << 29)
7129 /* Value is in Kb or KB (base 10). */
7130 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7131 (UINT32_C(0x2) << 29)
7132 /* Value is in bits or bytes. */
7133 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7134 (UINT32_C(0x4) << 29)
7135 /* Value is in Gb or GB (base 10). */
7136 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7137 (UINT32_C(0x6) << 29)
7138 /* Value is in 1/100th of a percentage of total bandwidth. */
7139 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7140 (UINT32_C(0x1) << 29)
7142 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7143 (UINT32_C(0x7) << 29)
7144 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7145 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7147 * Maximum BW allocated for this function.
7148 * The HWRM will translate this value into byte counter and
7149 * time interval used for the scheduler inside the device.
7150 * A value of 0 indicates that the maximum bandwidth is not
7154 /* The bandwidth value. */
7155 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7157 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7158 /* The granularity of the value (bits or bytes). */
7159 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7160 UINT32_C(0x10000000)
7161 /* Value is in bits. */
7162 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7163 (UINT32_C(0x0) << 28)
7164 /* Value is in bytes. */
7165 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7166 (UINT32_C(0x1) << 28)
7167 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7168 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7169 /* bw_value_unit is 3 b */
7170 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7171 UINT32_C(0xe0000000)
7172 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7173 /* Value is in Mb or MB (base 10). */
7174 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7175 (UINT32_C(0x0) << 29)
7176 /* Value is in Kb or KB (base 10). */
7177 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7178 (UINT32_C(0x2) << 29)
7179 /* Value is in bits or bytes. */
7180 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7181 (UINT32_C(0x4) << 29)
7182 /* Value is in Gb or GB (base 10). */
7183 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7184 (UINT32_C(0x6) << 29)
7185 /* Value is in 1/100th of a percentage of total bandwidth. */
7186 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7187 (UINT32_C(0x1) << 29)
7189 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7190 (UINT32_C(0x7) << 29)
7191 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7192 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7194 * This value indicates the Edge virtual bridge mode for the
7195 * domain that this function belongs to.
7198 /* No Edge Virtual Bridging (EVB) */
7199 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7200 /* Virtual Ethernet Bridge (VEB) */
7201 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7202 /* Virtual Ethernet Port Aggregator (VEPA) */
7203 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7204 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7205 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7208 * This value indicates the PCIE device cache line size.
7209 * The cache line size allows the DMA writes to terminate and
7210 * start at the cache boundary.
7212 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7214 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7215 /* Cache Line Size 64 bytes */
7216 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7218 /* Cache Line Size 128 bytes */
7219 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7221 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7222 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7223 /* This value is the virtual link admin state setting. */
7224 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7226 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7227 /* Admin link state is in forced down mode. */
7228 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7229 (UINT32_C(0x0) << 2)
7230 /* Admin link state is in forced up mode. */
7231 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7232 (UINT32_C(0x1) << 2)
7233 /* Admin link state is in auto mode - follows the physical link state. */
7234 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7235 (UINT32_C(0x2) << 2)
7236 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7237 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7238 /* Reserved for future. */
7239 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7241 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7243 * The number of VFs that are allocated to the function.
7244 * This is valid only on the PF with SR-IOV enabled.
7245 * 0xFF... (All Fs) if this command is called on a PF with
7246 * SR-IOV disabled or on a VF.
7250 * The number of allocated multicast filters for this
7251 * function on the RX side.
7253 uint32_t alloc_mcast_filters;
7255 * The number of allocated HW ring groups for this
7258 uint32_t alloc_hw_ring_grps;
7260 * The number of strict priority transmit rings out of
7261 * currently allocated TX rings to the function
7264 uint16_t alloc_sp_tx_rings;
7266 * The number of statistics contexts
7267 * currently reserved for the function.
7269 uint16_t alloc_stat_ctx;
7271 * This field specifies how many NQs are reserved for the PF.
7272 * Remaining NQs that belong to the PF are available for VFs.
7273 * Once a PF has created VFs, it cannot change how many NQs are
7274 * reserved for itself (since the NQs must be contiguous in HW).
7276 uint16_t alloc_msix;
7278 * The number of registered VF’s associated with the PF. This field
7279 * should be ignored when the request received on the VF interface.
7280 * This field will be updated on the PF interface to initiate
7281 * the unregister request on PF in the HOT Reset Process.
7283 uint16_t registered_vfs;
7284 uint8_t unused_1[3];
7286 * For backward compatibility this field must be set to 1.
7287 * Older drivers might look for this field to be 1 before
7288 * processing the message.
7292 * This GRC address location is used by the Host driver interfaces to poll
7293 * the adapter ready state to re-initiate the registration process again
7294 * after receiving the RESET Notify event.
7296 uint32_t reset_addr_poll;
7297 uint8_t unused_2[3];
7299 * This field is used in Output records to indicate that the output
7300 * is completely written to RAM. This field should be read as '1'
7301 * to indicate that the output has been completely written.
7302 * When writing a command completion or response to an internal processor,
7303 * the order of writes has to be such that this field is written last.
7306 } __attribute__((packed));
7313 /* hwrm_func_cfg_input (size:704b/88B) */
7314 struct hwrm_func_cfg_input {
7315 /* The HWRM command request type. */
7318 * The completion ring to send the completion event on. This should
7319 * be the NQ ID returned from the `nq_alloc` HWRM command.
7323 * The sequence ID is used by the driver for tracking multiple
7324 * commands. This ID is treated as opaque data by the firmware and
7325 * the value is returned in the `hwrm_resp_hdr` upon completion.
7329 * The target ID of the command:
7330 * * 0x0-0xFFF8 - The function ID
7331 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7332 * * 0xFFFD - Reserved for user-space HWRM interface
7337 * A physical address pointer pointing to a host buffer that the
7338 * command's response data will be written. This can be either a host
7339 * physical address (HPA) or a guest physical address (GPA) and must
7340 * point to a physically contiguous block of memory.
7344 * Function ID of the function that is being
7346 * If set to 0xFF... (All Fs), then the the configuration is
7347 * for the requesting function.
7351 * This field specifies how many NQs will be reserved for the PF.
7352 * Remaining NQs that belong to the PF become available for VFs.
7353 * Once a PF has created VFs, it cannot change how many NQs are
7354 * reserved for itself (since the NQs must be contiguous in HW).
7359 * When this bit is '1', the function is disabled with
7360 * source MAC address check.
7361 * This is an anti-spoofing check. If this flag is set,
7362 * then the function shall be configured to disallow
7363 * transmission of frames with the source MAC address that
7364 * is configured for this function.
7366 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
7369 * When this bit is '1', the function is enabled with
7370 * source MAC address check.
7371 * This is an anti-spoofing check. If this flag is set,
7372 * then the function shall be configured to allow
7373 * transmission of frames with the source MAC address that
7374 * is configured for this function.
7376 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
7379 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
7381 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7383 * Standard TX Ring mode is used for the allocation of TX ring
7384 * and underlying scheduling resources that allow bandwidth
7385 * reservation and limit settings on the queried function.
7386 * If set to 1, then standard TX ring mode is requested to be
7387 * enabled on the function being configured.
7389 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
7392 * Standard TX Ring mode is used for the allocation of TX ring
7393 * and underlying scheduling resources that allow bandwidth
7394 * reservation and limit settings on the queried function.
7395 * If set to 1, then the standard TX ring mode is requested to
7396 * be disabled on the function being configured. In this extended
7397 * TX ring resource mode, the minimum and maximum bandwidth settings
7398 * are not supported to allow the allocation of TX rings to
7399 * span multiple scheduler nodes.
7401 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
7404 * If this bit is set, virtual mac address configured
7405 * in this command will be persistent over warm boot.
7407 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
7410 * This bit only applies to the VF. If this bit is set, the statistic
7411 * context counters will not be cleared when the statistic context is freed
7412 * or a function reset is called on VF. This bit will be cleared when the PF
7413 * is unloaded or a function reset is called on the PF.
7415 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
7418 * This bit requests that the firmware test to see if all the assets
7419 * requested in this command (i.e. number of TX rings) are available.
7420 * The firmware will return an error if the requested assets are
7421 * not available. The firwmare will NOT reserve the assets if they
7424 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
7427 * This bit requests that the firmware test to see if all the assets
7428 * requested in this command (i.e. number of RX rings) are available.
7429 * The firmware will return an error if the requested assets are
7430 * not available. The firwmare will NOT reserve the assets if they
7433 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
7436 * This bit requests that the firmware test to see if all the assets
7437 * requested in this command (i.e. number of CMPL rings) are available.
7438 * The firmware will return an error if the requested assets are
7439 * not available. The firwmare will NOT reserve the assets if they
7442 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
7445 * This bit requests that the firmware test to see if all the assets
7446 * requested in this command (i.e. number of RSS ctx) are available.
7447 * The firmware will return an error if the requested assets are
7448 * not available. The firwmare will NOT reserve the assets if they
7451 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7454 * This bit requests that the firmware test to see if all the assets
7455 * requested in this command (i.e. number of ring groups) are available.
7456 * The firmware will return an error if the requested assets are
7457 * not available. The firwmare will NOT reserve the assets if they
7460 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7463 * This bit requests that the firmware test to see if all the assets
7464 * requested in this command (i.e. number of stat ctx) are available.
7465 * The firmware will return an error if the requested assets are
7466 * not available. The firwmare will NOT reserve the assets if they
7469 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7472 * This bit requests that the firmware test to see if all the assets
7473 * requested in this command (i.e. number of VNICs) are available.
7474 * The firmware will return an error if the requested assets are
7475 * not available. The firwmare will NOT reserve the assets if they
7478 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7481 * This bit requests that the firmware test to see if all the assets
7482 * requested in this command (i.e. number of L2 ctx) are available.
7483 * The firmware will return an error if the requested assets are
7484 * not available. The firwmare will NOT reserve the assets if they
7487 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7490 * This configuration change can be initiated by a PF driver. This
7491 * configuration request shall be targeted to a VF. From local host
7492 * resident HWRM clients, only the parent PF driver shall be allowed
7493 * to initiate this change on one of its children VFs. If this bit is
7494 * set to 1, then the VF that is being configured is requested to be
7497 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
7500 * When this bit it set, even if PF reserved pool size is zero,
7501 * FW will allow driver to create TX rings in ring alloc,
7502 * by reserving TX ring, S3 node dynamically.
7504 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7507 * This bit requests that the firmware test to see if all the assets
7508 * requested in this command (i.e. number of NQ rings) are available.
7509 * The firmware will return an error if the requested assets are
7510 * not available. The firwmare will NOT reserve the assets if they
7513 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
7516 * This configuration change can be initiated by a PF driver. This
7517 * configuration request shall be targeted to a VF. From local host
7518 * resident HWRM clients, only the parent PF driver shall be allowed
7519 * to initiate this change on one of its children VFs. If this bit is
7520 * set to 1, then the VF that is being configured is requested to be
7523 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
7527 * This bit must be '1' for the mtu field to be
7530 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
7533 * This bit must be '1' for the mru field to be
7536 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
7539 * This bit must be '1' for the num_rsscos_ctxs field to be
7542 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
7545 * This bit must be '1' for the num_cmpl_rings field to be
7548 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
7551 * This bit must be '1' for the num_tx_rings field to be
7554 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
7557 * This bit must be '1' for the num_rx_rings field to be
7560 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
7563 * This bit must be '1' for the num_l2_ctxs field to be
7566 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
7569 * This bit must be '1' for the num_vnics field to be
7572 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
7575 * This bit must be '1' for the num_stat_ctxs field to be
7578 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
7581 * This bit must be '1' for the dflt_mac_addr field to be
7584 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
7587 * This bit must be '1' for the dflt_vlan field to be
7590 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
7593 * This bit must be '1' for the dflt_ip_addr field to be
7596 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
7599 * This bit must be '1' for the min_bw field to be
7602 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
7605 * This bit must be '1' for the max_bw field to be
7608 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
7611 * This bit must be '1' for the async_event_cr field to be
7614 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
7617 * This bit must be '1' for the vlan_antispoof_mode field to be
7620 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
7623 * This bit must be '1' for the allowed_vlan_pris field to be
7626 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
7629 * This bit must be '1' for the evb_mode field to be
7632 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
7635 * This bit must be '1' for the num_mcast_filters field to be
7638 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
7641 * This bit must be '1' for the num_hw_ring_grps field to be
7644 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
7647 * This bit must be '1' for the cache_linesize field to be
7650 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
7653 * This bit must be '1' for the num_msix field to be
7656 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
7659 * This bit must be '1' for the link admin state field to be
7662 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
7665 * The maximum transmission unit of the function.
7666 * The HWRM should make sure that the mtu of
7667 * the function does not exceed the mtu of the physical
7668 * port that this function is associated with.
7670 * In addition to configuring mtu per function, it is
7671 * possible to configure mtu per transmit ring.
7672 * By default, the mtu of each transmit ring associated
7673 * with a function is equal to the mtu of the function.
7674 * The HWRM should make sure that the mtu of each transmit
7675 * ring that is assigned to a function has a valid mtu.
7679 * The maximum receive unit of the function.
7680 * The HWRM should make sure that the mru of
7681 * the function does not exceed the mru of the physical
7682 * port that this function is associated with.
7684 * In addition to configuring mru per function, it is
7685 * possible to configure mru per vnic.
7686 * By default, the mru of each vnic associated
7687 * with a function is equal to the mru of the function.
7688 * The HWRM should make sure that the mru of each vnic
7689 * that is assigned to a function has a valid mru.
7693 * The number of RSS/COS contexts requested for the
7696 uint16_t num_rsscos_ctxs;
7698 * The number of completion rings requested for the
7699 * function. This does not include the rings allocated
7700 * to any children functions if any.
7702 uint16_t num_cmpl_rings;
7704 * The number of transmit rings requested for the function.
7705 * This does not include the rings allocated to any
7706 * children functions if any.
7708 uint16_t num_tx_rings;
7710 * The number of receive rings requested for the function.
7711 * This does not include the rings allocated
7712 * to any children functions if any.
7714 uint16_t num_rx_rings;
7715 /* The requested number of L2 contexts for the function. */
7716 uint16_t num_l2_ctxs;
7717 /* The requested number of vnics for the function. */
7719 /* The requested number of statistic contexts for the function. */
7720 uint16_t num_stat_ctxs;
7722 * The number of HW ring groups that should
7723 * be reserved for this function.
7725 uint16_t num_hw_ring_grps;
7726 /* The default MAC address for the function being configured. */
7727 uint8_t dflt_mac_addr[6];
7729 * The default VLAN for the function being configured.
7730 * This field's format is same as 802.1Q Tag's
7731 * Tag Control Information (TCI) format that includes both
7732 * Priority Code Point (PCP) and VLAN Identifier (VID).
7736 * The default IP address for the function being configured.
7737 * This address is only used in enabling source property check.
7739 uint32_t dflt_ip_addr[4];
7741 * Minimum BW allocated for this function.
7742 * The HWRM will translate this value into byte counter and
7743 * time interval used for the scheduler inside the device.
7746 /* The bandwidth value. */
7747 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
7749 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
7750 /* The granularity of the value (bits or bytes). */
7751 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
7752 UINT32_C(0x10000000)
7753 /* Value is in bits. */
7754 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
7755 (UINT32_C(0x0) << 28)
7756 /* Value is in bytes. */
7757 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
7758 (UINT32_C(0x1) << 28)
7759 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
7760 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
7761 /* bw_value_unit is 3 b */
7762 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7763 UINT32_C(0xe0000000)
7764 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7765 /* Value is in Mb or MB (base 10). */
7766 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7767 (UINT32_C(0x0) << 29)
7768 /* Value is in Kb or KB (base 10). */
7769 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7770 (UINT32_C(0x2) << 29)
7771 /* Value is in bits or bytes. */
7772 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7773 (UINT32_C(0x4) << 29)
7774 /* Value is in Gb or GB (base 10). */
7775 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7776 (UINT32_C(0x6) << 29)
7777 /* Value is in 1/100th of a percentage of total bandwidth. */
7778 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7779 (UINT32_C(0x1) << 29)
7781 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7782 (UINT32_C(0x7) << 29)
7783 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7784 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7786 * Maximum BW allocated for this function.
7787 * The HWRM will translate this value into byte counter and
7788 * time interval used for the scheduler inside the device.
7791 /* The bandwidth value. */
7792 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
7794 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
7795 /* The granularity of the value (bits or bytes). */
7796 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
7797 UINT32_C(0x10000000)
7798 /* Value is in bits. */
7799 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
7800 (UINT32_C(0x0) << 28)
7801 /* Value is in bytes. */
7802 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
7803 (UINT32_C(0x1) << 28)
7804 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
7805 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
7806 /* bw_value_unit is 3 b */
7807 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7808 UINT32_C(0xe0000000)
7809 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7810 /* Value is in Mb or MB (base 10). */
7811 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7812 (UINT32_C(0x0) << 29)
7813 /* Value is in Kb or KB (base 10). */
7814 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7815 (UINT32_C(0x2) << 29)
7816 /* Value is in bits or bytes. */
7817 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7818 (UINT32_C(0x4) << 29)
7819 /* Value is in Gb or GB (base 10). */
7820 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7821 (UINT32_C(0x6) << 29)
7822 /* Value is in 1/100th of a percentage of total bandwidth. */
7823 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7824 (UINT32_C(0x1) << 29)
7826 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7827 (UINT32_C(0x7) << 29)
7828 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7829 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7831 * ID of the target completion ring for receiving asynchronous
7832 * event completions. If this field is not valid, then the
7833 * HWRM shall use the default completion ring of the function
7834 * that is being configured as the target completion ring for
7835 * providing any asynchronous event completions for that
7837 * If this field is valid, then the HWRM shall use the
7838 * completion ring identified by this ID as the target
7839 * completion ring for providing any asynchronous event
7840 * completions for the function that is being configured.
7842 uint16_t async_event_cr;
7843 /* VLAN Anti-spoofing mode. */
7844 uint8_t vlan_antispoof_mode;
7845 /* No VLAN anti-spoofing checks are enabled */
7846 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
7848 /* Validate VLAN against the configured VLAN(s) */
7849 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
7851 /* Insert VLAN if it does not exist, otherwise discard */
7852 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
7854 /* Insert VLAN if it does not exist, override VLAN if it exists */
7855 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
7857 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
7858 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
7860 * This bit field defines VLAN PRIs that are allowed on
7862 * If nth bit is set, then VLAN PRI n is allowed on this
7865 uint8_t allowed_vlan_pris;
7867 * The HWRM shall allow a PF driver to change EVB mode for the
7868 * partition it belongs to.
7869 * The HWRM shall not allow a VF driver to change the EVB mode.
7870 * The HWRM shall take into account the switching of EVB mode
7871 * from one to another and reconfigure hardware resources as
7873 * The switching from VEB to VEPA mode requires
7874 * the disabling of the loopback traffic. Additionally,
7875 * source knock outs are handled differently in VEB and VEPA
7879 /* No Edge Virtual Bridging (EVB) */
7880 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7881 /* Virtual Ethernet Bridge (VEB) */
7882 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
7883 /* Virtual Ethernet Port Aggregator (VEPA) */
7884 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
7885 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
7886 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
7889 * This value indicates the PCIE device cache line size.
7890 * The cache line size allows the DMA writes to terminate and
7891 * start at the cache boundary.
7893 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
7895 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7896 /* Cache Line Size 64 bytes */
7897 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7899 /* Cache Line Size 128 bytes */
7900 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7902 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
7903 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7904 /* This value is the virtual link admin state setting. */
7905 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7907 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7908 /* Admin state is forced down. */
7909 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7910 (UINT32_C(0x0) << 2)
7911 /* Admin state is forced up. */
7912 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7913 (UINT32_C(0x1) << 2)
7914 /* Admin state is in auto mode - is to follow the physical link state. */
7915 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7916 (UINT32_C(0x2) << 2)
7917 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7918 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7919 /* Reserved for future. */
7920 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
7922 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
7924 * The number of multicast filters that should
7925 * be reserved for this function on the RX side.
7927 uint16_t num_mcast_filters;
7928 } __attribute__((packed));
7930 /* hwrm_func_cfg_output (size:128b/16B) */
7931 struct hwrm_func_cfg_output {
7932 /* The specific error status for the command. */
7933 uint16_t error_code;
7934 /* The HWRM command request type. */
7936 /* The sequence ID from the original command. */
7938 /* The length of the response data in number of bytes. */
7940 uint8_t unused_0[7];
7942 * This field is used in Output records to indicate that the output
7943 * is completely written to RAM. This field should be read as '1'
7944 * to indicate that the output has been completely written.
7945 * When writing a command completion or response to an internal processor,
7946 * the order of writes has to be such that this field is written last.
7949 } __attribute__((packed));
7951 /********************
7952 * hwrm_func_qstats *
7953 ********************/
7956 /* hwrm_func_qstats_input (size:192b/24B) */
7957 struct hwrm_func_qstats_input {
7958 /* The HWRM command request type. */
7961 * The completion ring to send the completion event on. This should
7962 * be the NQ ID returned from the `nq_alloc` HWRM command.
7966 * The sequence ID is used by the driver for tracking multiple
7967 * commands. This ID is treated as opaque data by the firmware and
7968 * the value is returned in the `hwrm_resp_hdr` upon completion.
7972 * The target ID of the command:
7973 * * 0x0-0xFFF8 - The function ID
7974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7975 * * 0xFFFD - Reserved for user-space HWRM interface
7980 * A physical address pointer pointing to a host buffer that the
7981 * command's response data will be written. This can be either a host
7982 * physical address (HPA) or a guest physical address (GPA) and must
7983 * point to a physically contiguous block of memory.
7987 * Function ID of the function that is being queried.
7988 * 0xFF... (All Fs) if the query is for the requesting
7992 uint8_t unused_0[6];
7993 } __attribute__((packed));
7995 /* hwrm_func_qstats_output (size:1408b/176B) */
7996 struct hwrm_func_qstats_output {
7997 /* The specific error status for the command. */
7998 uint16_t error_code;
7999 /* The HWRM command request type. */
8001 /* The sequence ID from the original command. */
8003 /* The length of the response data in number of bytes. */
8005 /* Number of transmitted unicast packets on the function. */
8006 uint64_t tx_ucast_pkts;
8007 /* Number of transmitted multicast packets on the function. */
8008 uint64_t tx_mcast_pkts;
8009 /* Number of transmitted broadcast packets on the function. */
8010 uint64_t tx_bcast_pkts;
8012 * Number of transmitted packets that were discarded due to
8013 * internal NIC resource problems. For transmit, this
8014 * can only happen if TMP is configured to allow dropping
8015 * in HOL blocking conditions, which is not a normal
8018 uint64_t tx_discard_pkts;
8020 * Number of dropped packets on transmit path on the function.
8021 * These are packets that have been marked for drop by
8022 * the TE CFA block or are packets that exceeded the
8023 * transmit MTU limit for the function.
8025 uint64_t tx_drop_pkts;
8026 /* Number of transmitted bytes for unicast traffic on the function. */
8027 uint64_t tx_ucast_bytes;
8028 /* Number of transmitted bytes for multicast traffic on the function. */
8029 uint64_t tx_mcast_bytes;
8030 /* Number of transmitted bytes for broadcast traffic on the function. */
8031 uint64_t tx_bcast_bytes;
8032 /* Number of received unicast packets on the function. */
8033 uint64_t rx_ucast_pkts;
8034 /* Number of received multicast packets on the function. */
8035 uint64_t rx_mcast_pkts;
8036 /* Number of received broadcast packets on the function. */
8037 uint64_t rx_bcast_pkts;
8039 * Number of received packets that were discarded on the function
8040 * due to resource limitations. This can happen for 3 reasons.
8041 * # The BD used for the packet has a bad format.
8042 * # There were no BDs available in the ring for the packet.
8043 * # There were no BDs available on-chip for the packet.
8045 uint64_t rx_discard_pkts;
8047 * Number of dropped packets on received path on the function.
8048 * These are packets that have been marked for drop by the
8051 uint64_t rx_drop_pkts;
8052 /* Number of received bytes for unicast traffic on the function. */
8053 uint64_t rx_ucast_bytes;
8054 /* Number of received bytes for multicast traffic on the function. */
8055 uint64_t rx_mcast_bytes;
8056 /* Number of received bytes for broadcast traffic on the function. */
8057 uint64_t rx_bcast_bytes;
8058 /* Number of aggregated unicast packets on the function. */
8059 uint64_t rx_agg_pkts;
8060 /* Number of aggregated unicast bytes on the function. */
8061 uint64_t rx_agg_bytes;
8062 /* Number of aggregation events on the function. */
8063 uint64_t rx_agg_events;
8064 /* Number of aborted aggregations on the function. */
8065 uint64_t rx_agg_aborts;
8066 uint8_t unused_0[7];
8068 * This field is used in Output records to indicate that the output
8069 * is completely written to RAM. This field should be read as '1'
8070 * to indicate that the output has been completely written.
8071 * When writing a command completion or response to an internal processor,
8072 * the order of writes has to be such that this field is written last.
8075 } __attribute__((packed));
8077 /***********************
8078 * hwrm_func_clr_stats *
8079 ***********************/
8082 /* hwrm_func_clr_stats_input (size:192b/24B) */
8083 struct hwrm_func_clr_stats_input {
8084 /* The HWRM command request type. */
8087 * The completion ring to send the completion event on. This should
8088 * be the NQ ID returned from the `nq_alloc` HWRM command.
8092 * The sequence ID is used by the driver for tracking multiple
8093 * commands. This ID is treated as opaque data by the firmware and
8094 * the value is returned in the `hwrm_resp_hdr` upon completion.
8098 * The target ID of the command:
8099 * * 0x0-0xFFF8 - The function ID
8100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8101 * * 0xFFFD - Reserved for user-space HWRM interface
8106 * A physical address pointer pointing to a host buffer that the
8107 * command's response data will be written. This can be either a host
8108 * physical address (HPA) or a guest physical address (GPA) and must
8109 * point to a physically contiguous block of memory.
8113 * Function ID of the function.
8114 * 0xFF... (All Fs) if the query is for the requesting
8118 uint8_t unused_0[6];
8119 } __attribute__((packed));
8121 /* hwrm_func_clr_stats_output (size:128b/16B) */
8122 struct hwrm_func_clr_stats_output {
8123 /* The specific error status for the command. */
8124 uint16_t error_code;
8125 /* The HWRM command request type. */
8127 /* The sequence ID from the original command. */
8129 /* The length of the response data in number of bytes. */
8131 uint8_t unused_0[7];
8133 * This field is used in Output records to indicate that the output
8134 * is completely written to RAM. This field should be read as '1'
8135 * to indicate that the output has been completely written.
8136 * When writing a command completion or response to an internal processor,
8137 * the order of writes has to be such that this field is written last.
8140 } __attribute__((packed));
8142 /**************************
8143 * hwrm_func_vf_resc_free *
8144 **************************/
8147 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8148 struct hwrm_func_vf_resc_free_input {
8149 /* The HWRM command request type. */
8152 * The completion ring to send the completion event on. This should
8153 * be the NQ ID returned from the `nq_alloc` HWRM command.
8157 * The sequence ID is used by the driver for tracking multiple
8158 * commands. This ID is treated as opaque data by the firmware and
8159 * the value is returned in the `hwrm_resp_hdr` upon completion.
8163 * The target ID of the command:
8164 * * 0x0-0xFFF8 - The function ID
8165 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8166 * * 0xFFFD - Reserved for user-space HWRM interface
8171 * A physical address pointer pointing to a host buffer that the
8172 * command's response data will be written. This can be either a host
8173 * physical address (HPA) or a guest physical address (GPA) and must
8174 * point to a physically contiguous block of memory.
8178 * This value is used to identify a Virtual Function (VF).
8179 * The scope of VF ID is local within a PF.
8182 uint8_t unused_0[6];
8183 } __attribute__((packed));
8185 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8186 struct hwrm_func_vf_resc_free_output {
8187 /* The specific error status for the command. */
8188 uint16_t error_code;
8189 /* The HWRM command request type. */
8191 /* The sequence ID from the original command. */
8193 /* The length of the response data in number of bytes. */
8195 uint8_t unused_0[7];
8197 * This field is used in Output records to indicate that the output
8198 * is completely written to RAM. This field should be read as '1'
8199 * to indicate that the output has been completely written.
8200 * When writing a command completion or response to an internal processor,
8201 * the order of writes has to be such that this field is written last.
8204 } __attribute__((packed));
8206 /**********************
8207 * hwrm_func_drv_rgtr *
8208 **********************/
8211 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8212 struct hwrm_func_drv_rgtr_input {
8213 /* The HWRM command request type. */
8216 * The completion ring to send the completion event on. This should
8217 * be the NQ ID returned from the `nq_alloc` HWRM command.
8221 * The sequence ID is used by the driver for tracking multiple
8222 * commands. This ID is treated as opaque data by the firmware and
8223 * the value is returned in the `hwrm_resp_hdr` upon completion.
8227 * The target ID of the command:
8228 * * 0x0-0xFFF8 - The function ID
8229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8230 * * 0xFFFD - Reserved for user-space HWRM interface
8235 * A physical address pointer pointing to a host buffer that the
8236 * command's response data will be written. This can be either a host
8237 * physical address (HPA) or a guest physical address (GPA) and must
8238 * point to a physically contiguous block of memory.
8243 * When this bit is '1', the function driver is requesting
8244 * all requests from its children VF drivers to be
8245 * forwarded to itself.
8246 * This flag can only be set by the PF driver.
8247 * If a VF driver sets this flag, it should be ignored
8250 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8253 * When this bit is '1', the function is requesting none of
8254 * the requests from its children VF drivers to be
8255 * forwarded to itself.
8256 * This flag can only be set by the PF driver.
8257 * If a VF driver sets this flag, it should be ignored
8260 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
8263 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
8264 * fields shall be ignored and ver_maj, ver_min, ver_upd
8265 * and ver_patch shall be used for the driver version information.
8266 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
8267 * fields shall be used for the driver version information and
8268 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
8270 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
8273 * When this bit is '1', the function is indicating support of
8274 * 64bit flow handle. The firmware that only supports 64bit flow
8275 * handle should check this bit before allowing processing of
8276 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
8277 * with 64bit flow handle support can only be compatible with drivers
8278 * that support 64bit flow handle. The legacy drivers that don't support
8279 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
8280 * running with new firmware that only supports 64bit flow handle. The new
8281 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
8282 * status to the legacy driver when encounters these commands.
8284 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
8287 * When this bit is '1', the function is indicating support of
8288 * Hot Reset. The driver interface will destroy the resources,
8289 * unregister the function and register again up on receiving
8290 * the RESET_NOTIFY Async notification from the core firmware.
8291 * The core firmware will this use flag and trigger the Hot Reset
8292 * process only if all the registered driver instances are capable
8295 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
8298 * When this bit is 1, the function is indicating the support of the
8299 * error recovery capability. Error recovery support will be used by
8300 * firmware only if all the driver instances support error recovery
8301 * process. By setting this bit, driver is indicating support for
8302 * corresponding async event completion message. These will be
8303 * delivered to the driver even if they did not register for it.
8304 * If supported, after receiving reset notify async event with fatal
8305 * flag set in event data1, then all the drivers have to tear down
8306 * their resources without sending any HWRM commands to FW.
8308 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
8312 * This bit must be '1' for the os_type field to be
8315 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
8318 * This bit must be '1' for the ver field to be
8321 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
8324 * This bit must be '1' for the timestamp field to be
8327 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
8330 * This bit must be '1' for the vf_req_fwd field to be
8333 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
8336 * This bit must be '1' for the async_event_fwd field to be
8339 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
8341 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8344 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8345 /* Other OS not listed below. */
8346 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
8348 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8350 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8352 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8354 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
8356 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8357 /* VMware ESXi OS. */
8358 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
8359 /* Microsoft Windows 8 64-bit OS. */
8360 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8361 /* Microsoft Windows Server 2012 R2 OS. */
8362 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8364 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8365 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
8366 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
8367 /* This is the 8bit major version of the driver. */
8369 /* This is the 8bit minor version of the driver. */
8371 /* This is the 8bit update version of the driver. */
8373 uint8_t unused_0[3];
8375 * This is a 32-bit timestamp provided by the driver for
8377 * The timestamp is in multiples of 1ms.
8380 uint8_t unused_1[4];
8382 * This is a 256-bit bit mask provided by the PF driver for
8383 * letting the HWRM know what commands issued by the VF driver
8384 * to the HWRM should be forwarded to the PF driver.
8385 * Nth bit refers to the Nth req_type.
8387 * Setting Nth bit to 1 indicates that requests from the
8388 * VF driver with req_type equal to N shall be forwarded to
8389 * the parent PF driver.
8391 * This field is not valid for the VF driver.
8393 uint32_t vf_req_fwd[8];
8395 * This is a 256-bit bit mask provided by the function driver
8396 * (PF or VF driver) to indicate the list of asynchronous event
8397 * completions to be forwarded.
8399 * Nth bit refers to the Nth event_id.
8401 * Setting Nth bit to 1 by the function driver shall result in
8402 * the HWRM forwarding asynchronous event completion with
8403 * event_id equal to N.
8405 * If all bits are set to 0 (value of 0), then the HWRM shall
8406 * not forward any asynchronous event completion to this
8409 uint32_t async_event_fwd[8];
8410 /* This is the 16bit major version of the driver. */
8412 /* This is the 16bit minor version of the driver. */
8414 /* This is the 16bit update version of the driver. */
8416 /* This is the 16bit patch version of the driver. */
8418 } __attribute__((packed));
8420 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
8421 struct hwrm_func_drv_rgtr_output {
8422 /* The specific error status for the command. */
8423 uint16_t error_code;
8424 /* The HWRM command request type. */
8426 /* The sequence ID from the original command. */
8428 /* The length of the response data in number of bytes. */
8432 * When this bit is '1', it indicates that the
8433 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
8435 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
8437 uint8_t unused_0[3];
8439 * This field is used in Output records to indicate that the output
8440 * is completely written to RAM. This field should be read as '1'
8441 * to indicate that the output has been completely written.
8442 * When writing a command completion or response to an internal processor,
8443 * the order of writes has to be such that this field is written last.
8446 } __attribute__((packed));
8448 /************************
8449 * hwrm_func_drv_unrgtr *
8450 ************************/
8453 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
8454 struct hwrm_func_drv_unrgtr_input {
8455 /* The HWRM command request type. */
8458 * The completion ring to send the completion event on. This should
8459 * be the NQ ID returned from the `nq_alloc` HWRM command.
8463 * The sequence ID is used by the driver for tracking multiple
8464 * commands. This ID is treated as opaque data by the firmware and
8465 * the value is returned in the `hwrm_resp_hdr` upon completion.
8469 * The target ID of the command:
8470 * * 0x0-0xFFF8 - The function ID
8471 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8472 * * 0xFFFD - Reserved for user-space HWRM interface
8477 * A physical address pointer pointing to a host buffer that the
8478 * command's response data will be written. This can be either a host
8479 * physical address (HPA) or a guest physical address (GPA) and must
8480 * point to a physically contiguous block of memory.
8485 * When this bit is '1', the function driver is notifying
8486 * the HWRM to prepare for the shutdown.
8488 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
8490 uint8_t unused_0[4];
8491 } __attribute__((packed));
8493 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
8494 struct hwrm_func_drv_unrgtr_output {
8495 /* The specific error status for the command. */
8496 uint16_t error_code;
8497 /* The HWRM command request type. */
8499 /* The sequence ID from the original command. */
8501 /* The length of the response data in number of bytes. */
8503 uint8_t unused_0[7];
8505 * This field is used in Output records to indicate that the output
8506 * is completely written to RAM. This field should be read as '1'
8507 * to indicate that the output has been completely written.
8508 * When writing a command completion or response to an internal processor,
8509 * the order of writes has to be such that this field is written last.
8512 } __attribute__((packed));
8514 /**********************
8515 * hwrm_func_buf_rgtr *
8516 **********************/
8519 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
8520 struct hwrm_func_buf_rgtr_input {
8521 /* The HWRM command request type. */
8524 * The completion ring to send the completion event on. This should
8525 * be the NQ ID returned from the `nq_alloc` HWRM command.
8529 * The sequence ID is used by the driver for tracking multiple
8530 * commands. This ID is treated as opaque data by the firmware and
8531 * the value is returned in the `hwrm_resp_hdr` upon completion.
8535 * The target ID of the command:
8536 * * 0x0-0xFFF8 - The function ID
8537 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8538 * * 0xFFFD - Reserved for user-space HWRM interface
8543 * A physical address pointer pointing to a host buffer that the
8544 * command's response data will be written. This can be either a host
8545 * physical address (HPA) or a guest physical address (GPA) and must
8546 * point to a physically contiguous block of memory.
8551 * This bit must be '1' for the vf_id field to be
8554 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8556 * This bit must be '1' for the err_buf_addr field to be
8559 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
8561 * This value is used to identify a Virtual Function (VF).
8562 * The scope of VF ID is local within a PF.
8566 * This field represents the number of pages used for request
8569 uint16_t req_buf_num_pages;
8571 * This field represents the page size used for request
8574 uint16_t req_buf_page_size;
8576 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
8578 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
8580 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
8582 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
8584 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
8586 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
8588 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
8589 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
8590 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
8591 /* The length of the request buffer per VF in bytes. */
8592 uint16_t req_buf_len;
8593 /* The length of the response buffer in bytes. */
8594 uint16_t resp_buf_len;
8595 uint8_t unused_0[2];
8596 /* This field represents the page address of page #0. */
8597 uint64_t req_buf_page_addr0;
8598 /* This field represents the page address of page #1. */
8599 uint64_t req_buf_page_addr1;
8600 /* This field represents the page address of page #2. */
8601 uint64_t req_buf_page_addr2;
8602 /* This field represents the page address of page #3. */
8603 uint64_t req_buf_page_addr3;
8604 /* This field represents the page address of page #4. */
8605 uint64_t req_buf_page_addr4;
8606 /* This field represents the page address of page #5. */
8607 uint64_t req_buf_page_addr5;
8608 /* This field represents the page address of page #6. */
8609 uint64_t req_buf_page_addr6;
8610 /* This field represents the page address of page #7. */
8611 uint64_t req_buf_page_addr7;
8612 /* This field represents the page address of page #8. */
8613 uint64_t req_buf_page_addr8;
8614 /* This field represents the page address of page #9. */
8615 uint64_t req_buf_page_addr9;
8617 * This field is used to receive the error reporting from
8618 * the chipset. Only applicable for PFs.
8620 uint64_t error_buf_addr;
8622 * This field is used to receive the response forwarded by the
8625 uint64_t resp_buf_addr;
8626 } __attribute__((packed));
8628 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
8629 struct hwrm_func_buf_rgtr_output {
8630 /* The specific error status for the command. */
8631 uint16_t error_code;
8632 /* The HWRM command request type. */
8634 /* The sequence ID from the original command. */
8636 /* The length of the response data in number of bytes. */
8638 uint8_t unused_0[7];
8640 * This field is used in Output records to indicate that the output
8641 * is completely written to RAM. This field should be read as '1'
8642 * to indicate that the output has been completely written.
8643 * When writing a command completion or response to an internal processor,
8644 * the order of writes has to be such that this field is written last.
8647 } __attribute__((packed));
8649 /************************
8650 * hwrm_func_buf_unrgtr *
8651 ************************/
8654 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
8655 struct hwrm_func_buf_unrgtr_input {
8656 /* The HWRM command request type. */
8659 * The completion ring to send the completion event on. This should
8660 * be the NQ ID returned from the `nq_alloc` HWRM command.
8664 * The sequence ID is used by the driver for tracking multiple
8665 * commands. This ID is treated as opaque data by the firmware and
8666 * the value is returned in the `hwrm_resp_hdr` upon completion.
8670 * The target ID of the command:
8671 * * 0x0-0xFFF8 - The function ID
8672 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8673 * * 0xFFFD - Reserved for user-space HWRM interface
8678 * A physical address pointer pointing to a host buffer that the
8679 * command's response data will be written. This can be either a host
8680 * physical address (HPA) or a guest physical address (GPA) and must
8681 * point to a physically contiguous block of memory.
8686 * This bit must be '1' for the vf_id field to be
8689 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8691 * This value is used to identify a Virtual Function (VF).
8692 * The scope of VF ID is local within a PF.
8695 uint8_t unused_0[2];
8696 } __attribute__((packed));
8698 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
8699 struct hwrm_func_buf_unrgtr_output {
8700 /* The specific error status for the command. */
8701 uint16_t error_code;
8702 /* The HWRM command request type. */
8704 /* The sequence ID from the original command. */
8706 /* The length of the response data in number of bytes. */
8708 uint8_t unused_0[7];
8710 * This field is used in Output records to indicate that the output
8711 * is completely written to RAM. This field should be read as '1'
8712 * to indicate that the output has been completely written.
8713 * When writing a command completion or response to an internal processor,
8714 * the order of writes has to be such that this field is written last.
8717 } __attribute__((packed));
8719 /**********************
8720 * hwrm_func_drv_qver *
8721 **********************/
8724 /* hwrm_func_drv_qver_input (size:192b/24B) */
8725 struct hwrm_func_drv_qver_input {
8726 /* The HWRM command request type. */
8729 * The completion ring to send the completion event on. This should
8730 * be the NQ ID returned from the `nq_alloc` HWRM command.
8734 * The sequence ID is used by the driver for tracking multiple
8735 * commands. This ID is treated as opaque data by the firmware and
8736 * the value is returned in the `hwrm_resp_hdr` upon completion.
8740 * The target ID of the command:
8741 * * 0x0-0xFFF8 - The function ID
8742 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8743 * * 0xFFFD - Reserved for user-space HWRM interface
8748 * A physical address pointer pointing to a host buffer that the
8749 * command's response data will be written. This can be either a host
8750 * physical address (HPA) or a guest physical address (GPA) and must
8751 * point to a physically contiguous block of memory.
8754 /* Reserved for future use. */
8757 * Function ID of the function that is being queried.
8758 * 0xFF... (All Fs) if the query is for the requesting
8762 uint8_t unused_0[2];
8763 } __attribute__((packed));
8765 /* hwrm_func_drv_qver_output (size:256b/32B) */
8766 struct hwrm_func_drv_qver_output {
8767 /* The specific error status for the command. */
8768 uint16_t error_code;
8769 /* The HWRM command request type. */
8771 /* The sequence ID from the original command. */
8773 /* The length of the response data in number of bytes. */
8775 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8778 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8779 /* Other OS not listed below. */
8780 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
8782 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8784 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8786 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8788 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
8790 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8791 /* VMware ESXi OS. */
8792 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
8793 /* Microsoft Windows 8 64-bit OS. */
8794 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8795 /* Microsoft Windows Server 2012 R2 OS. */
8796 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8798 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8799 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
8800 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
8801 /* This is the 8bit major version of the driver. */
8803 /* This is the 8bit minor version of the driver. */
8805 /* This is the 8bit update version of the driver. */
8807 uint8_t unused_0[3];
8808 /* This is the 16bit major version of the driver. */
8810 /* This is the 16bit minor version of the driver. */
8812 /* This is the 16bit update version of the driver. */
8814 /* This is the 16bit patch version of the driver. */
8816 uint8_t unused_1[7];
8818 * This field is used in Output records to indicate that the output
8819 * is completely written to RAM. This field should be read as '1'
8820 * to indicate that the output has been completely written.
8821 * When writing a command completion or response to an internal processor,
8822 * the order of writes has to be such that this field is written last.
8825 } __attribute__((packed));
8827 /****************************
8828 * hwrm_func_resource_qcaps *
8829 ****************************/
8832 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
8833 struct hwrm_func_resource_qcaps_input {
8834 /* The HWRM command request type. */
8837 * The completion ring to send the completion event on. This should
8838 * be the NQ ID returned from the `nq_alloc` HWRM command.
8842 * The sequence ID is used by the driver for tracking multiple
8843 * commands. This ID is treated as opaque data by the firmware and
8844 * the value is returned in the `hwrm_resp_hdr` upon completion.
8848 * The target ID of the command:
8849 * * 0x0-0xFFF8 - The function ID
8850 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8851 * * 0xFFFD - Reserved for user-space HWRM interface
8856 * A physical address pointer pointing to a host buffer that the
8857 * command's response data will be written. This can be either a host
8858 * physical address (HPA) or a guest physical address (GPA) and must
8859 * point to a physically contiguous block of memory.
8863 * Function ID of the function that is being queried.
8864 * 0xFF... (All Fs) if the query is for the requesting
8868 uint8_t unused_0[6];
8869 } __attribute__((packed));
8871 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
8872 struct hwrm_func_resource_qcaps_output {
8873 /* The specific error status for the command. */
8874 uint16_t error_code;
8875 /* The HWRM command request type. */
8877 /* The sequence ID from the original command. */
8879 /* The length of the response data in number of bytes. */
8881 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
8883 /* Maximum guaranteed number of MSI-X vectors supported by function */
8885 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
8886 uint16_t vf_reservation_strategy;
8887 /* The PF driver should evenly divide its remaining resources among all VFs. */
8888 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
8890 /* The PF driver should only reserve minimal resources for each VF. */
8891 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
8894 * The PF driver should not reserve any resources for each VF until the
8895 * the VF interface is brought up.
8897 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
8899 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
8900 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
8901 /* Minimum guaranteed number of RSS/COS contexts */
8902 uint16_t min_rsscos_ctx;
8903 /* Maximum non-guaranteed number of RSS/COS contexts */
8904 uint16_t max_rsscos_ctx;
8905 /* Minimum guaranteed number of completion rings */
8906 uint16_t min_cmpl_rings;
8907 /* Maximum non-guaranteed number of completion rings */
8908 uint16_t max_cmpl_rings;
8909 /* Minimum guaranteed number of transmit rings */
8910 uint16_t min_tx_rings;
8911 /* Maximum non-guaranteed number of transmit rings */
8912 uint16_t max_tx_rings;
8913 /* Minimum guaranteed number of receive rings */
8914 uint16_t min_rx_rings;
8915 /* Maximum non-guaranteed number of receive rings */
8916 uint16_t max_rx_rings;
8917 /* Minimum guaranteed number of L2 contexts */
8918 uint16_t min_l2_ctxs;
8919 /* Maximum non-guaranteed number of L2 contexts */
8920 uint16_t max_l2_ctxs;
8921 /* Minimum guaranteed number of VNICs */
8923 /* Maximum non-guaranteed number of VNICs */
8925 /* Minimum guaranteed number of statistic contexts */
8926 uint16_t min_stat_ctx;
8927 /* Maximum non-guaranteed number of statistic contexts */
8928 uint16_t max_stat_ctx;
8929 /* Minimum guaranteed number of ring groups */
8930 uint16_t min_hw_ring_grps;
8931 /* Maximum non-guaranteed number of ring groups */
8932 uint16_t max_hw_ring_grps;
8934 * Maximum number of inputs into the transmit scheduler for this function.
8935 * The number of TX rings assigned to the function cannot exceed this value.
8937 uint16_t max_tx_scheduler_inputs;
8940 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
8941 * feature to reserve all minimum resources when minimum >= 1, otherwise
8944 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
8946 uint8_t unused_0[5];
8948 * This field is used in Output records to indicate that the output
8949 * is completely written to RAM. This field should be read as '1'
8950 * to indicate that the output has been completely written.
8951 * When writing a command completion or response to an internal processor,
8952 * the order of writes has to be such that this field is written last.
8955 } __attribute__((packed));
8957 /*********************************
8958 * hwrm_func_backing_store_qcaps *
8959 *********************************/
8962 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
8963 struct hwrm_func_backing_store_qcaps_input {
8964 /* The HWRM command request type. */
8967 * The completion ring to send the completion event on. This should
8968 * be the NQ ID returned from the `nq_alloc` HWRM command.
8972 * The sequence ID is used by the driver for tracking multiple
8973 * commands. This ID is treated as opaque data by the firmware and
8974 * the value is returned in the `hwrm_resp_hdr` upon completion.
8978 * The target ID of the command:
8979 * * 0x0-0xFFF8 - The function ID
8980 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8981 * * 0xFFFD - Reserved for user-space HWRM interface
8986 * A physical address pointer pointing to a host buffer that the
8987 * command's response data will be written. This can be either a host
8988 * physical address (HPA) or a guest physical address (GPA) and must
8989 * point to a physically contiguous block of memory.
8992 } __attribute__((packed));
8994 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
8995 struct hwrm_func_backing_store_qcaps_output {
8996 /* The specific error status for the command. */
8997 uint16_t error_code;
8998 /* The HWRM command request type. */
9000 /* The sequence ID from the original command. */
9002 /* The length of the response data in number of bytes. */
9004 /* Maximum number of QP context entries supported for this function. */
9005 uint32_t qp_max_entries;
9007 * Minimum number of QP context entries that are needed to be reserved
9008 * for QP1 for the PF and its VFs. PF drivers must allocate at least
9009 * this many QP context entries, even if RoCE will not be used.
9011 uint16_t qp_min_qp1_entries;
9012 /* Maximum number of QP context entries that can be used for L2. */
9013 uint16_t qp_max_l2_entries;
9014 /* Number of bytes that must be allocated for each context entry. */
9015 uint16_t qp_entry_size;
9016 /* Maximum number of SRQ context entries that can be used for L2. */
9017 uint16_t srq_max_l2_entries;
9018 /* Maximum number of SRQ context entries supported for this function. */
9019 uint32_t srq_max_entries;
9020 /* Number of bytes that must be allocated for each context entry. */
9021 uint16_t srq_entry_size;
9022 /* Maximum number of CQ context entries that can be used for L2. */
9023 uint16_t cq_max_l2_entries;
9024 /* Maximum number of CQ context entries supported for this function. */
9025 uint32_t cq_max_entries;
9026 /* Number of bytes that must be allocated for each context entry. */
9027 uint16_t cq_entry_size;
9028 /* Maximum number of VNIC context entries supported for this function. */
9029 uint16_t vnic_max_vnic_entries;
9030 /* Maximum number of Ring table context entries supported for this function. */
9031 uint16_t vnic_max_ring_table_entries;
9032 /* Number of bytes that must be allocated for each context entry. */
9033 uint16_t vnic_entry_size;
9034 /* Maximum number of statistic context entries supported for this function. */
9035 uint32_t stat_max_entries;
9036 /* Number of bytes that must be allocated for each context entry. */
9037 uint16_t stat_entry_size;
9038 /* Number of bytes that must be allocated for each context entry. */
9039 uint16_t tqm_entry_size;
9040 /* Minimum number of TQM context entries required per ring. */
9041 uint32_t tqm_min_entries_per_ring;
9043 * Maximum number of TQM context entries supported per ring. This is
9044 * actually a recommended TQM queue size based on worst case usage of
9047 * TQM fastpath rings should be sized large enough to accommodate the
9048 * maximum number of QPs (either L2 or RoCE, or both if shared)
9049 * that can be enqueued to the TQM ring.
9051 * TQM slowpath rings should be sized as follows:
9053 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9056 * num_vnics is the number of VNICs allocated in the VNIC backing store
9057 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9058 * num_roce_qps is the number of RoCE QPs in the QP backing store
9059 * tqm_min_size is tqm_min_entries_per_ring reported by
9060 * HWRM_FUNC_BACKING_STORE_QCAPS
9062 * Note that TQM ring sizes cannot be extended while the system is
9063 * operational. If a PF driver needs to extend a TQM ring, it needs
9064 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9065 * the backing store.
9067 uint32_t tqm_max_entries_per_ring;
9069 * Maximum number of MR plus AV context entries supported for this
9072 uint32_t mrav_max_entries;
9073 /* Number of bytes that must be allocated for each context entry. */
9074 uint16_t mrav_entry_size;
9075 /* Number of bytes that must be allocated for each context entry. */
9076 uint16_t tim_entry_size;
9077 /* Maximum number of Timer context entries supported for this function. */
9078 uint32_t tim_max_entries;
9080 * When this field is zero, the 32b `mrav_num_entries` field in the
9081 * `backing_store_cfg` and `backing_store_qcfg` commands represents
9082 * the total number of MR plus AV entries allowed in the MR/AV backing
9085 * When this field is non-zero, the 32b `mrav_num_entries` field in
9086 * the `backing_store_cfg` and `backing_store_qcfg` commands is
9087 * logically divided into two 16b fields. Bits `[31:16]` represents
9088 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
9089 * Both of these values are represented in a unit granularity
9090 * specified by this field. For example, if this field is 16 and
9091 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
9092 * is 8192 and the number of AV entries is 4096.
9094 uint16_t mrav_num_entries_units;
9096 * The number of entries specified for any TQM ring must be a
9097 * multiple of this value to prevent any resource allocation
9100 uint8_t tqm_entries_multiple;
9102 * This field is used in Output records to indicate that the output
9103 * is completely written to RAM. This field should be read as '1'
9104 * to indicate that the output has been completely written.
9105 * When writing a command completion or response to an internal processor,
9106 * the order of writes has to be such that this field is written last.
9109 } __attribute__((packed));
9111 /*******************************
9112 * hwrm_func_backing_store_cfg *
9113 *******************************/
9116 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9117 struct hwrm_func_backing_store_cfg_input {
9118 /* The HWRM command request type. */
9121 * The completion ring to send the completion event on. This should
9122 * be the NQ ID returned from the `nq_alloc` HWRM command.
9126 * The sequence ID is used by the driver for tracking multiple
9127 * commands. This ID is treated as opaque data by the firmware and
9128 * the value is returned in the `hwrm_resp_hdr` upon completion.
9132 * The target ID of the command:
9133 * * 0x0-0xFFF8 - The function ID
9134 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9135 * * 0xFFFD - Reserved for user-space HWRM interface
9140 * A physical address pointer pointing to a host buffer that the
9141 * command's response data will be written. This can be either a host
9142 * physical address (HPA) or a guest physical address (GPA) and must
9143 * point to a physically contiguous block of memory.
9148 * When set, the firmware only uses on-chip resources and does not
9149 * expect any backing store to be provided by the host driver. This
9150 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9156 * When set, the 32b `mrav_num_entries` field is logically divided
9157 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
9159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
9163 * This bit must be '1' for the qp fields to be
9166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9169 * This bit must be '1' for the srq fields to be
9172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9175 * This bit must be '1' for the cq fields to be
9178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9181 * This bit must be '1' for the vnic fields to be
9184 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9187 * This bit must be '1' for the stat fields to be
9190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9193 * This bit must be '1' for the tqm_sp fields to be
9196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9199 * This bit must be '1' for the tqm_ring0 fields to be
9202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9205 * This bit must be '1' for the tqm_ring1 fields to be
9208 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9211 * This bit must be '1' for the tqm_ring2 fields to be
9214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9217 * This bit must be '1' for the tqm_ring3 fields to be
9220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9223 * This bit must be '1' for the tqm_ring4 fields to be
9226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9229 * This bit must be '1' for the tqm_ring5 fields to be
9232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
9235 * This bit must be '1' for the tqm_ring6 fields to be
9238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
9241 * This bit must be '1' for the tqm_ring7 fields to be
9244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
9247 * This bit must be '1' for the mrav fields to be
9250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
9253 * This bit must be '1' for the tim fields to be
9256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
9258 /* QPC page size and level. */
9259 uint8_t qpc_pg_size_qpc_lvl;
9260 /* QPC PBL indirect levels. */
9261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
9263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
9264 /* PBL pointer is physical start address. */
9265 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
9267 /* PBL pointer points to PTE table. */
9268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
9270 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
9273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
9274 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
9275 /* QPC page size. */
9276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
9278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
9280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
9281 (UINT32_C(0x0) << 4)
9283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
9284 (UINT32_C(0x1) << 4)
9286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
9287 (UINT32_C(0x2) << 4)
9289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
9290 (UINT32_C(0x3) << 4)
9292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
9293 (UINT32_C(0x4) << 4)
9295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
9296 (UINT32_C(0x5) << 4)
9297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
9298 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
9299 /* SRQ page size and level. */
9300 uint8_t srq_pg_size_srq_lvl;
9301 /* SRQ PBL indirect levels. */
9302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
9304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
9305 /* PBL pointer is physical start address. */
9306 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
9308 /* PBL pointer points to PTE table. */
9309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
9311 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
9314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
9315 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
9316 /* SRQ page size. */
9317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
9319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
9321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
9322 (UINT32_C(0x0) << 4)
9324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
9325 (UINT32_C(0x1) << 4)
9327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
9328 (UINT32_C(0x2) << 4)
9330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
9331 (UINT32_C(0x3) << 4)
9333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
9334 (UINT32_C(0x4) << 4)
9336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
9337 (UINT32_C(0x5) << 4)
9338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
9339 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
9340 /* CQ page size and level. */
9341 uint8_t cq_pg_size_cq_lvl;
9342 /* CQ PBL indirect levels. */
9343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
9345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
9346 /* PBL pointer is physical start address. */
9347 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
9349 /* PBL pointer points to PTE table. */
9350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
9352 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
9355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
9356 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
9358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
9360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
9362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
9363 (UINT32_C(0x0) << 4)
9365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
9366 (UINT32_C(0x1) << 4)
9368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
9369 (UINT32_C(0x2) << 4)
9371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
9372 (UINT32_C(0x3) << 4)
9374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
9375 (UINT32_C(0x4) << 4)
9377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
9378 (UINT32_C(0x5) << 4)
9379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
9380 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
9381 /* VNIC page size and level. */
9382 uint8_t vnic_pg_size_vnic_lvl;
9383 /* VNIC PBL indirect levels. */
9384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
9386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
9387 /* PBL pointer is physical start address. */
9388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
9390 /* PBL pointer points to PTE table. */
9391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
9393 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
9396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
9397 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
9398 /* VNIC page size. */
9399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
9401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
9403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
9404 (UINT32_C(0x0) << 4)
9406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
9407 (UINT32_C(0x1) << 4)
9409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
9410 (UINT32_C(0x2) << 4)
9412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
9413 (UINT32_C(0x3) << 4)
9415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
9416 (UINT32_C(0x4) << 4)
9418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
9419 (UINT32_C(0x5) << 4)
9420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
9421 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
9422 /* Stat page size and level. */
9423 uint8_t stat_pg_size_stat_lvl;
9424 /* Stat PBL indirect levels. */
9425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
9427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
9428 /* PBL pointer is physical start address. */
9429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
9431 /* PBL pointer points to PTE table. */
9432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
9434 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
9437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
9438 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
9439 /* Stat page size. */
9440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
9442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
9444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
9445 (UINT32_C(0x0) << 4)
9447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
9448 (UINT32_C(0x1) << 4)
9450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
9451 (UINT32_C(0x2) << 4)
9453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
9454 (UINT32_C(0x3) << 4)
9456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
9457 (UINT32_C(0x4) << 4)
9459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
9460 (UINT32_C(0x5) << 4)
9461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
9462 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
9463 /* TQM slow path page size and level. */
9464 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
9465 /* TQM slow path PBL indirect levels. */
9466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
9468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
9469 /* PBL pointer is physical start address. */
9470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
9472 /* PBL pointer points to PTE table. */
9473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
9475 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
9478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
9479 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
9480 /* TQM slow path page size. */
9481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
9483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
9485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
9486 (UINT32_C(0x0) << 4)
9488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
9489 (UINT32_C(0x1) << 4)
9491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
9492 (UINT32_C(0x2) << 4)
9494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
9495 (UINT32_C(0x3) << 4)
9497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
9498 (UINT32_C(0x4) << 4)
9500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
9501 (UINT32_C(0x5) << 4)
9502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
9503 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
9504 /* TQM ring 0 page size and level. */
9505 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9506 /* TQM ring 0 PBL indirect levels. */
9507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
9509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
9510 /* PBL pointer is physical start address. */
9511 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
9513 /* PBL pointer points to PTE table. */
9514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
9516 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
9519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
9520 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
9521 /* TQM ring 0 page size. */
9522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
9524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
9526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
9527 (UINT32_C(0x0) << 4)
9529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
9530 (UINT32_C(0x1) << 4)
9532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
9533 (UINT32_C(0x2) << 4)
9535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
9536 (UINT32_C(0x3) << 4)
9538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
9539 (UINT32_C(0x4) << 4)
9541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
9542 (UINT32_C(0x5) << 4)
9543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
9544 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
9545 /* TQM ring 1 page size and level. */
9546 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9547 /* TQM ring 1 PBL indirect levels. */
9548 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
9550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
9551 /* PBL pointer is physical start address. */
9552 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
9554 /* PBL pointer points to PTE table. */
9555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
9557 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
9560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
9561 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
9562 /* TQM ring 1 page size. */
9563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
9565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
9567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
9568 (UINT32_C(0x0) << 4)
9570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
9571 (UINT32_C(0x1) << 4)
9573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
9574 (UINT32_C(0x2) << 4)
9576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
9577 (UINT32_C(0x3) << 4)
9579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
9580 (UINT32_C(0x4) << 4)
9582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
9583 (UINT32_C(0x5) << 4)
9584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
9585 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
9586 /* TQM ring 2 page size and level. */
9587 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9588 /* TQM ring 2 PBL indirect levels. */
9589 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
9591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
9592 /* PBL pointer is physical start address. */
9593 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
9595 /* PBL pointer points to PTE table. */
9596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
9598 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
9601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
9602 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
9603 /* TQM ring 2 page size. */
9604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
9606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
9608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
9609 (UINT32_C(0x0) << 4)
9611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
9612 (UINT32_C(0x1) << 4)
9614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
9615 (UINT32_C(0x2) << 4)
9617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
9618 (UINT32_C(0x3) << 4)
9620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
9621 (UINT32_C(0x4) << 4)
9623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
9624 (UINT32_C(0x5) << 4)
9625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
9626 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
9627 /* TQM ring 3 page size and level. */
9628 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9629 /* TQM ring 3 PBL indirect levels. */
9630 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
9632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
9633 /* PBL pointer is physical start address. */
9634 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
9636 /* PBL pointer points to PTE table. */
9637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
9639 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9640 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
9642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
9643 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
9644 /* TQM ring 3 page size. */
9645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
9647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
9649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
9650 (UINT32_C(0x0) << 4)
9652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
9653 (UINT32_C(0x1) << 4)
9655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
9656 (UINT32_C(0x2) << 4)
9658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
9659 (UINT32_C(0x3) << 4)
9661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
9662 (UINT32_C(0x4) << 4)
9664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
9665 (UINT32_C(0x5) << 4)
9666 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
9667 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
9668 /* TQM ring 4 page size and level. */
9669 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9670 /* TQM ring 4 PBL indirect levels. */
9671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
9673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
9674 /* PBL pointer is physical start address. */
9675 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
9677 /* PBL pointer points to PTE table. */
9678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
9680 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
9683 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
9684 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
9685 /* TQM ring 4 page size. */
9686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
9688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
9690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
9691 (UINT32_C(0x0) << 4)
9693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
9694 (UINT32_C(0x1) << 4)
9696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
9697 (UINT32_C(0x2) << 4)
9699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
9700 (UINT32_C(0x3) << 4)
9702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
9703 (UINT32_C(0x4) << 4)
9705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
9706 (UINT32_C(0x5) << 4)
9707 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
9708 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
9709 /* TQM ring 5 page size and level. */
9710 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9711 /* TQM ring 5 PBL indirect levels. */
9712 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
9714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
9715 /* PBL pointer is physical start address. */
9716 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
9718 /* PBL pointer points to PTE table. */
9719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
9721 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
9724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
9725 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
9726 /* TQM ring 5 page size. */
9727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
9729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
9731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
9732 (UINT32_C(0x0) << 4)
9734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
9735 (UINT32_C(0x1) << 4)
9737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
9738 (UINT32_C(0x2) << 4)
9740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
9741 (UINT32_C(0x3) << 4)
9743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
9744 (UINT32_C(0x4) << 4)
9746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
9747 (UINT32_C(0x5) << 4)
9748 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
9749 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
9750 /* TQM ring 6 page size and level. */
9751 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9752 /* TQM ring 6 PBL indirect levels. */
9753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
9755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
9756 /* PBL pointer is physical start address. */
9757 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
9759 /* PBL pointer points to PTE table. */
9760 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
9762 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9763 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
9765 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
9766 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
9767 /* TQM ring 6 page size. */
9768 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
9770 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
9772 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
9773 (UINT32_C(0x0) << 4)
9775 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
9776 (UINT32_C(0x1) << 4)
9778 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
9779 (UINT32_C(0x2) << 4)
9781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
9782 (UINT32_C(0x3) << 4)
9784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
9785 (UINT32_C(0x4) << 4)
9787 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
9788 (UINT32_C(0x5) << 4)
9789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
9790 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
9791 /* TQM ring 7 page size and level. */
9792 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9793 /* TQM ring 7 PBL indirect levels. */
9794 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
9796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
9797 /* PBL pointer is physical start address. */
9798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
9800 /* PBL pointer points to PTE table. */
9801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
9803 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9804 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
9806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
9807 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
9808 /* TQM ring 7 page size. */
9809 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
9811 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
9813 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
9814 (UINT32_C(0x0) << 4)
9816 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
9817 (UINT32_C(0x1) << 4)
9819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
9820 (UINT32_C(0x2) << 4)
9822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
9823 (UINT32_C(0x3) << 4)
9825 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
9826 (UINT32_C(0x4) << 4)
9828 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
9829 (UINT32_C(0x5) << 4)
9830 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
9831 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
9832 /* MR/AV page size and level. */
9833 uint8_t mrav_pg_size_mrav_lvl;
9834 /* MR/AV PBL indirect levels. */
9835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
9837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
9838 /* PBL pointer is physical start address. */
9839 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
9841 /* PBL pointer points to PTE table. */
9842 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
9844 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9845 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
9847 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
9848 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
9849 /* MR/AV page size. */
9850 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
9852 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
9854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
9855 (UINT32_C(0x0) << 4)
9857 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
9858 (UINT32_C(0x1) << 4)
9860 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
9861 (UINT32_C(0x2) << 4)
9863 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
9864 (UINT32_C(0x3) << 4)
9866 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
9867 (UINT32_C(0x4) << 4)
9869 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
9870 (UINT32_C(0x5) << 4)
9871 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
9872 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
9873 /* Timer page size and level. */
9874 uint8_t tim_pg_size_tim_lvl;
9875 /* Timer PBL indirect levels. */
9876 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
9878 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
9879 /* PBL pointer is physical start address. */
9880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
9882 /* PBL pointer points to PTE table. */
9883 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
9885 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9886 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
9888 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
9889 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
9890 /* Timer page size. */
9891 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
9893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
9895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
9896 (UINT32_C(0x0) << 4)
9898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
9899 (UINT32_C(0x1) << 4)
9901 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
9902 (UINT32_C(0x2) << 4)
9904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
9905 (UINT32_C(0x3) << 4)
9907 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
9908 (UINT32_C(0x4) << 4)
9910 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
9911 (UINT32_C(0x5) << 4)
9912 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
9913 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
9914 /* QP page directory. */
9915 uint64_t qpc_page_dir;
9916 /* SRQ page directory. */
9917 uint64_t srq_page_dir;
9918 /* CQ page directory. */
9919 uint64_t cq_page_dir;
9920 /* VNIC page directory. */
9921 uint64_t vnic_page_dir;
9922 /* Stat page directory. */
9923 uint64_t stat_page_dir;
9924 /* TQM slowpath page directory. */
9925 uint64_t tqm_sp_page_dir;
9926 /* TQM ring 0 page directory. */
9927 uint64_t tqm_ring0_page_dir;
9928 /* TQM ring 1 page directory. */
9929 uint64_t tqm_ring1_page_dir;
9930 /* TQM ring 2 page directory. */
9931 uint64_t tqm_ring2_page_dir;
9932 /* TQM ring 3 page directory. */
9933 uint64_t tqm_ring3_page_dir;
9934 /* TQM ring 4 page directory. */
9935 uint64_t tqm_ring4_page_dir;
9936 /* TQM ring 5 page directory. */
9937 uint64_t tqm_ring5_page_dir;
9938 /* TQM ring 6 page directory. */
9939 uint64_t tqm_ring6_page_dir;
9940 /* TQM ring 7 page directory. */
9941 uint64_t tqm_ring7_page_dir;
9942 /* MR/AV page directory. */
9943 uint64_t mrav_page_dir;
9944 /* Timer page directory. */
9945 uint64_t tim_page_dir;
9946 /* Number of QPs. */
9947 uint32_t qp_num_entries;
9948 /* Number of SRQs. */
9949 uint32_t srq_num_entries;
9950 /* Number of CQs. */
9951 uint32_t cq_num_entries;
9952 /* Number of Stats. */
9953 uint32_t stat_num_entries;
9955 * Number of TQM slowpath entries.
9957 * TQM slowpath rings should be sized as follows:
9959 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9962 * num_vnics is the number of VNICs allocated in the VNIC backing store
9963 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9964 * num_roce_qps is the number of RoCE QPs in the QP backing store
9965 * tqm_min_size is tqm_min_entries_per_ring reported by
9966 * HWRM_FUNC_BACKING_STORE_QCAPS
9968 * Note that TQM ring sizes cannot be extended while the system is
9969 * operational. If a PF driver needs to extend a TQM ring, it needs
9970 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9971 * the backing store.
9973 uint32_t tqm_sp_num_entries;
9975 * Number of TQM ring 0 entries.
9977 * TQM fastpath rings should be sized large enough to accommodate the
9978 * maximum number of QPs (either L2 or RoCE, or both if shared)
9979 * that can be enqueued to the TQM ring.
9981 * Note that TQM ring sizes cannot be extended while the system is
9982 * operational. If a PF driver needs to extend a TQM ring, it needs
9983 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9984 * the backing store.
9986 uint32_t tqm_ring0_num_entries;
9988 * Number of TQM ring 1 entries.
9990 * TQM fastpath rings should be sized large enough to accommodate the
9991 * maximum number of QPs (either L2 or RoCE, or both if shared)
9992 * that can be enqueued to the TQM ring.
9994 * Note that TQM ring sizes cannot be extended while the system is
9995 * operational. If a PF driver needs to extend a TQM ring, it needs
9996 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9997 * the backing store.
9999 uint32_t tqm_ring1_num_entries;
10001 * Number of TQM ring 2 entries.
10003 * TQM fastpath rings should be sized large enough to accommodate the
10004 * maximum number of QPs (either L2 or RoCE, or both if shared)
10005 * that can be enqueued to the TQM ring.
10007 * Note that TQM ring sizes cannot be extended while the system is
10008 * operational. If a PF driver needs to extend a TQM ring, it needs
10009 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10010 * the backing store.
10012 uint32_t tqm_ring2_num_entries;
10014 * Number of TQM ring 3 entries.
10016 * TQM fastpath rings should be sized large enough to accommodate the
10017 * maximum number of QPs (either L2 or RoCE, or both if shared)
10018 * that can be enqueued to the TQM ring.
10020 * Note that TQM ring sizes cannot be extended while the system is
10021 * operational. If a PF driver needs to extend a TQM ring, it needs
10022 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10023 * the backing store.
10025 uint32_t tqm_ring3_num_entries;
10027 * Number of TQM ring 4 entries.
10029 * TQM fastpath rings should be sized large enough to accommodate the
10030 * maximum number of QPs (either L2 or RoCE, or both if shared)
10031 * that can be enqueued to the TQM ring.
10033 * Note that TQM ring sizes cannot be extended while the system is
10034 * operational. If a PF driver needs to extend a TQM ring, it needs
10035 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10036 * the backing store.
10038 uint32_t tqm_ring4_num_entries;
10040 * Number of TQM ring 5 entries.
10042 * TQM fastpath rings should be sized large enough to accommodate the
10043 * maximum number of QPs (either L2 or RoCE, or both if shared)
10044 * that can be enqueued to the TQM ring.
10046 * Note that TQM ring sizes cannot be extended while the system is
10047 * operational. If a PF driver needs to extend a TQM ring, it needs
10048 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10049 * the backing store.
10051 uint32_t tqm_ring5_num_entries;
10053 * Number of TQM ring 6 entries.
10055 * TQM fastpath rings should be sized large enough to accommodate the
10056 * maximum number of QPs (either L2 or RoCE, or both if shared)
10057 * that can be enqueued to the TQM ring.
10059 * Note that TQM ring sizes cannot be extended while the system is
10060 * operational. If a PF driver needs to extend a TQM ring, it needs
10061 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10062 * the backing store.
10064 uint32_t tqm_ring6_num_entries;
10066 * Number of TQM ring 7 entries.
10068 * TQM fastpath rings should be sized large enough to accommodate the
10069 * maximum number of QPs (either L2 or RoCE, or both if shared)
10070 * that can be enqueued to the TQM ring.
10072 * Note that TQM ring sizes cannot be extended while the system is
10073 * operational. If a PF driver needs to extend a TQM ring, it needs
10074 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10075 * the backing store.
10077 uint32_t tqm_ring7_num_entries;
10079 * If the MR/AV split reservation flag is not set, then this field
10080 * represents the total number of MR plus AV entries. For versions
10081 * of firmware that support the split reservation, when it is not
10082 * specified half of the entries will be reserved for MRs and the
10083 * other half for AVs.
10085 * If the MR/AV split reservation flag is set, then this
10086 * field is logically divided into two 16b fields. Bits `[31:16]`
10087 * represents the `mr_num_entries` and bits `[15:0]` represents
10088 * `av_num_entries`. The granularity of these values is defined by
10089 * the `mrav_num_entries_unit` field returned by the
10090 * `backing_store_qcaps` command.
10092 uint32_t mrav_num_entries;
10093 /* Number of Timer entries. */
10094 uint32_t tim_num_entries;
10095 /* Number of entries to reserve for QP1 */
10096 uint16_t qp_num_qp1_entries;
10097 /* Number of entries to reserve for L2 */
10098 uint16_t qp_num_l2_entries;
10099 /* Number of bytes that have been allocated for each context entry. */
10100 uint16_t qp_entry_size;
10101 /* Number of entries to reserve for L2 */
10102 uint16_t srq_num_l2_entries;
10103 /* Number of bytes that have been allocated for each context entry. */
10104 uint16_t srq_entry_size;
10105 /* Number of entries to reserve for L2 */
10106 uint16_t cq_num_l2_entries;
10107 /* Number of bytes that have been allocated for each context entry. */
10108 uint16_t cq_entry_size;
10109 /* Number of entries to reserve for VNIC entries */
10110 uint16_t vnic_num_vnic_entries;
10111 /* Number of entries to reserve for Ring table entries */
10112 uint16_t vnic_num_ring_table_entries;
10113 /* Number of bytes that have been allocated for each context entry. */
10114 uint16_t vnic_entry_size;
10115 /* Number of bytes that have been allocated for each context entry. */
10116 uint16_t stat_entry_size;
10117 /* Number of bytes that have been allocated for each context entry. */
10118 uint16_t tqm_entry_size;
10119 /* Number of bytes that have been allocated for each context entry. */
10120 uint16_t mrav_entry_size;
10121 /* Number of bytes that have been allocated for each context entry. */
10122 uint16_t tim_entry_size;
10123 } __attribute__((packed));
10125 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
10126 struct hwrm_func_backing_store_cfg_output {
10127 /* The specific error status for the command. */
10128 uint16_t error_code;
10129 /* The HWRM command request type. */
10131 /* The sequence ID from the original command. */
10133 /* The length of the response data in number of bytes. */
10135 uint8_t unused_0[7];
10137 * This field is used in Output records to indicate that the output
10138 * is completely written to RAM. This field should be read as '1'
10139 * to indicate that the output has been completely written.
10140 * When writing a command completion or response to an internal processor,
10141 * the order of writes has to be such that this field is written last.
10144 } __attribute__((packed));
10146 /********************************
10147 * hwrm_func_backing_store_qcfg *
10148 ********************************/
10151 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10152 struct hwrm_func_backing_store_qcfg_input {
10153 /* The HWRM command request type. */
10156 * The completion ring to send the completion event on. This should
10157 * be the NQ ID returned from the `nq_alloc` HWRM command.
10159 uint16_t cmpl_ring;
10161 * The sequence ID is used by the driver for tracking multiple
10162 * commands. This ID is treated as opaque data by the firmware and
10163 * the value is returned in the `hwrm_resp_hdr` upon completion.
10167 * The target ID of the command:
10168 * * 0x0-0xFFF8 - The function ID
10169 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10170 * * 0xFFFD - Reserved for user-space HWRM interface
10173 uint16_t target_id;
10175 * A physical address pointer pointing to a host buffer that the
10176 * command's response data will be written. This can be either a host
10177 * physical address (HPA) or a guest physical address (GPA) and must
10178 * point to a physically contiguous block of memory.
10180 uint64_t resp_addr;
10181 } __attribute__((packed));
10183 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10184 struct hwrm_func_backing_store_qcfg_output {
10185 /* The specific error status for the command. */
10186 uint16_t error_code;
10187 /* The HWRM command request type. */
10189 /* The sequence ID from the original command. */
10191 /* The length of the response data in number of bytes. */
10195 * When set, the firmware only uses on-chip resources and does not
10196 * expect any backing store to be provided by the host driver. This
10197 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10203 * When set, the 32b `mrav_num_entries` field is logically divided
10204 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10208 uint8_t unused_0[4];
10210 * This bit must be '1' for the qp fields to be
10213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10216 * This bit must be '1' for the srq fields to be
10219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10222 * This bit must be '1' for the cq fields to be
10225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10228 * This bit must be '1' for the vnic fields to be
10231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
10234 * This bit must be '1' for the stat fields to be
10237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
10240 * This bit must be '1' for the tqm_sp fields to be
10243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
10246 * This bit must be '1' for the tqm_ring0 fields to be
10249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
10252 * This bit must be '1' for the tqm_ring1 fields to be
10255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
10258 * This bit must be '1' for the tqm_ring2 fields to be
10261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
10264 * This bit must be '1' for the tqm_ring3 fields to be
10267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
10270 * This bit must be '1' for the tqm_ring4 fields to be
10273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
10276 * This bit must be '1' for the tqm_ring5 fields to be
10279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
10282 * This bit must be '1' for the tqm_ring6 fields to be
10285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
10288 * This bit must be '1' for the tqm_ring7 fields to be
10291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
10294 * This bit must be '1' for the mrav fields to be
10297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
10300 * This bit must be '1' for the tim fields to be
10303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
10305 /* QPC page size and level. */
10306 uint8_t qpc_pg_size_qpc_lvl;
10307 /* QPC PBL indirect levels. */
10308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
10310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
10311 /* PBL pointer is physical start address. */
10312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
10314 /* PBL pointer points to PTE table. */
10315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
10317 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
10320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
10321 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
10322 /* QPC page size. */
10323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
10325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
10327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
10328 (UINT32_C(0x0) << 4)
10330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
10331 (UINT32_C(0x1) << 4)
10333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
10334 (UINT32_C(0x2) << 4)
10336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
10337 (UINT32_C(0x3) << 4)
10339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
10340 (UINT32_C(0x4) << 4)
10342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
10343 (UINT32_C(0x5) << 4)
10344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
10345 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
10346 /* SRQ page size and level. */
10347 uint8_t srq_pg_size_srq_lvl;
10348 /* SRQ PBL indirect levels. */
10349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
10351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
10352 /* PBL pointer is physical start address. */
10353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
10355 /* PBL pointer points to PTE table. */
10356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
10358 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
10361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
10362 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
10363 /* SRQ page size. */
10364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
10366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
10368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
10369 (UINT32_C(0x0) << 4)
10371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
10372 (UINT32_C(0x1) << 4)
10374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
10375 (UINT32_C(0x2) << 4)
10377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
10378 (UINT32_C(0x3) << 4)
10380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
10381 (UINT32_C(0x4) << 4)
10383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
10384 (UINT32_C(0x5) << 4)
10385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
10386 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
10387 /* CQ page size and level. */
10388 uint8_t cq_pg_size_cq_lvl;
10389 /* CQ PBL indirect levels. */
10390 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
10392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
10393 /* PBL pointer is physical start address. */
10394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
10396 /* PBL pointer points to PTE table. */
10397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
10399 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10400 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
10402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
10403 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
10404 /* CQ page size. */
10405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
10407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
10409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
10410 (UINT32_C(0x0) << 4)
10412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
10413 (UINT32_C(0x1) << 4)
10415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
10416 (UINT32_C(0x2) << 4)
10418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
10419 (UINT32_C(0x3) << 4)
10421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
10422 (UINT32_C(0x4) << 4)
10424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
10425 (UINT32_C(0x5) << 4)
10426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
10427 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
10428 /* VNIC page size and level. */
10429 uint8_t vnic_pg_size_vnic_lvl;
10430 /* VNIC PBL indirect levels. */
10431 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
10433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
10434 /* PBL pointer is physical start address. */
10435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
10437 /* PBL pointer points to PTE table. */
10438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
10440 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
10443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
10444 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
10445 /* VNIC page size. */
10446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
10448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
10450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
10451 (UINT32_C(0x0) << 4)
10453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
10454 (UINT32_C(0x1) << 4)
10456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
10457 (UINT32_C(0x2) << 4)
10459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
10460 (UINT32_C(0x3) << 4)
10462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
10463 (UINT32_C(0x4) << 4)
10465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
10466 (UINT32_C(0x5) << 4)
10467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
10468 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
10469 /* Stat page size and level. */
10470 uint8_t stat_pg_size_stat_lvl;
10471 /* Stat PBL indirect levels. */
10472 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
10474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
10475 /* PBL pointer is physical start address. */
10476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
10478 /* PBL pointer points to PTE table. */
10479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
10481 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
10484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
10485 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
10486 /* Stat page size. */
10487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
10489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
10491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
10492 (UINT32_C(0x0) << 4)
10494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
10495 (UINT32_C(0x1) << 4)
10497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
10498 (UINT32_C(0x2) << 4)
10500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
10501 (UINT32_C(0x3) << 4)
10503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
10504 (UINT32_C(0x4) << 4)
10506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
10507 (UINT32_C(0x5) << 4)
10508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
10509 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
10510 /* TQM slow path page size and level. */
10511 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10512 /* TQM slow path PBL indirect levels. */
10513 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
10515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
10516 /* PBL pointer is physical start address. */
10517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
10519 /* PBL pointer points to PTE table. */
10520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
10522 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
10525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
10526 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
10527 /* TQM slow path page size. */
10528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
10530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
10532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
10533 (UINT32_C(0x0) << 4)
10535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
10536 (UINT32_C(0x1) << 4)
10538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
10539 (UINT32_C(0x2) << 4)
10541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
10542 (UINT32_C(0x3) << 4)
10544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
10545 (UINT32_C(0x4) << 4)
10547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
10548 (UINT32_C(0x5) << 4)
10549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
10550 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
10551 /* TQM ring 0 page size and level. */
10552 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10553 /* TQM ring 0 PBL indirect levels. */
10554 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
10556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
10557 /* PBL pointer is physical start address. */
10558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
10560 /* PBL pointer points to PTE table. */
10561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
10563 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
10566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
10567 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
10568 /* TQM ring 0 page size. */
10569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
10571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
10573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
10574 (UINT32_C(0x0) << 4)
10576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
10577 (UINT32_C(0x1) << 4)
10579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
10580 (UINT32_C(0x2) << 4)
10582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
10583 (UINT32_C(0x3) << 4)
10585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
10586 (UINT32_C(0x4) << 4)
10588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
10589 (UINT32_C(0x5) << 4)
10590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
10591 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
10592 /* TQM ring 1 page size and level. */
10593 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10594 /* TQM ring 1 PBL indirect levels. */
10595 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
10597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
10598 /* PBL pointer is physical start address. */
10599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
10601 /* PBL pointer points to PTE table. */
10602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
10604 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
10607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
10608 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
10609 /* TQM ring 1 page size. */
10610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
10612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
10614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
10615 (UINT32_C(0x0) << 4)
10617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
10618 (UINT32_C(0x1) << 4)
10620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
10621 (UINT32_C(0x2) << 4)
10623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
10624 (UINT32_C(0x3) << 4)
10626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
10627 (UINT32_C(0x4) << 4)
10629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
10630 (UINT32_C(0x5) << 4)
10631 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
10632 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
10633 /* TQM ring 2 page size and level. */
10634 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10635 /* TQM ring 2 PBL indirect levels. */
10636 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
10638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
10639 /* PBL pointer is physical start address. */
10640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
10642 /* PBL pointer points to PTE table. */
10643 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
10645 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10646 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
10648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
10649 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
10650 /* TQM ring 2 page size. */
10651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
10653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
10655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
10656 (UINT32_C(0x0) << 4)
10658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
10659 (UINT32_C(0x1) << 4)
10661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
10662 (UINT32_C(0x2) << 4)
10664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
10665 (UINT32_C(0x3) << 4)
10667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
10668 (UINT32_C(0x4) << 4)
10670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
10671 (UINT32_C(0x5) << 4)
10672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
10673 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
10674 /* TQM ring 3 page size and level. */
10675 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10676 /* TQM ring 3 PBL indirect levels. */
10677 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
10679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
10680 /* PBL pointer is physical start address. */
10681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
10683 /* PBL pointer points to PTE table. */
10684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
10686 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
10689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
10690 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
10691 /* TQM ring 3 page size. */
10692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
10694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
10696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
10697 (UINT32_C(0x0) << 4)
10699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
10700 (UINT32_C(0x1) << 4)
10702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
10703 (UINT32_C(0x2) << 4)
10705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
10706 (UINT32_C(0x3) << 4)
10708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
10709 (UINT32_C(0x4) << 4)
10711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
10712 (UINT32_C(0x5) << 4)
10713 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
10714 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
10715 /* TQM ring 4 page size and level. */
10716 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10717 /* TQM ring 4 PBL indirect levels. */
10718 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
10720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
10721 /* PBL pointer is physical start address. */
10722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
10724 /* PBL pointer points to PTE table. */
10725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
10727 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10728 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
10730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
10731 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
10732 /* TQM ring 4 page size. */
10733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
10735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
10737 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
10738 (UINT32_C(0x0) << 4)
10740 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
10741 (UINT32_C(0x1) << 4)
10743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
10744 (UINT32_C(0x2) << 4)
10746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
10747 (UINT32_C(0x3) << 4)
10749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
10750 (UINT32_C(0x4) << 4)
10752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
10753 (UINT32_C(0x5) << 4)
10754 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
10755 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
10756 /* TQM ring 5 page size and level. */
10757 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10758 /* TQM ring 5 PBL indirect levels. */
10759 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
10761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
10762 /* PBL pointer is physical start address. */
10763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
10765 /* PBL pointer points to PTE table. */
10766 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
10768 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
10771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
10772 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
10773 /* TQM ring 5 page size. */
10774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
10776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
10778 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
10779 (UINT32_C(0x0) << 4)
10781 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
10782 (UINT32_C(0x1) << 4)
10784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
10785 (UINT32_C(0x2) << 4)
10787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
10788 (UINT32_C(0x3) << 4)
10790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
10791 (UINT32_C(0x4) << 4)
10793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
10794 (UINT32_C(0x5) << 4)
10795 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
10796 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
10797 /* TQM ring 6 page size and level. */
10798 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10799 /* TQM ring 6 PBL indirect levels. */
10800 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
10802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
10803 /* PBL pointer is physical start address. */
10804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
10806 /* PBL pointer points to PTE table. */
10807 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
10809 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10810 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
10812 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
10813 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
10814 /* TQM ring 6 page size. */
10815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
10817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
10819 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
10820 (UINT32_C(0x0) << 4)
10822 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
10823 (UINT32_C(0x1) << 4)
10825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
10826 (UINT32_C(0x2) << 4)
10828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
10829 (UINT32_C(0x3) << 4)
10831 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
10832 (UINT32_C(0x4) << 4)
10834 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
10835 (UINT32_C(0x5) << 4)
10836 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
10837 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
10838 /* TQM ring 7 page size and level. */
10839 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10840 /* TQM ring 7 PBL indirect levels. */
10841 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
10843 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
10844 /* PBL pointer is physical start address. */
10845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
10847 /* PBL pointer points to PTE table. */
10848 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
10850 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10851 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
10853 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
10854 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
10855 /* TQM ring 7 page size. */
10856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
10858 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
10860 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
10861 (UINT32_C(0x0) << 4)
10863 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
10864 (UINT32_C(0x1) << 4)
10866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
10867 (UINT32_C(0x2) << 4)
10869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
10870 (UINT32_C(0x3) << 4)
10872 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
10873 (UINT32_C(0x4) << 4)
10875 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
10876 (UINT32_C(0x5) << 4)
10877 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
10878 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
10879 /* MR/AV page size and level. */
10880 uint8_t mrav_pg_size_mrav_lvl;
10881 /* MR/AV PBL indirect levels. */
10882 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
10884 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
10885 /* PBL pointer is physical start address. */
10886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
10888 /* PBL pointer points to PTE table. */
10889 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
10891 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10892 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
10894 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
10895 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
10896 /* MR/AV page size. */
10897 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
10899 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
10901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
10902 (UINT32_C(0x0) << 4)
10904 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
10905 (UINT32_C(0x1) << 4)
10907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
10908 (UINT32_C(0x2) << 4)
10910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
10911 (UINT32_C(0x3) << 4)
10913 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
10914 (UINT32_C(0x4) << 4)
10916 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
10917 (UINT32_C(0x5) << 4)
10918 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
10919 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
10920 /* Timer page size and level. */
10921 uint8_t tim_pg_size_tim_lvl;
10922 /* Timer PBL indirect levels. */
10923 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
10925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
10926 /* PBL pointer is physical start address. */
10927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
10929 /* PBL pointer points to PTE table. */
10930 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
10932 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10933 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
10935 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
10936 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
10937 /* Timer page size. */
10938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
10940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
10942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
10943 (UINT32_C(0x0) << 4)
10945 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
10946 (UINT32_C(0x1) << 4)
10948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
10949 (UINT32_C(0x2) << 4)
10951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
10952 (UINT32_C(0x3) << 4)
10954 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
10955 (UINT32_C(0x4) << 4)
10957 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
10958 (UINT32_C(0x5) << 4)
10959 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
10960 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
10961 /* QP page directory. */
10962 uint64_t qpc_page_dir;
10963 /* SRQ page directory. */
10964 uint64_t srq_page_dir;
10965 /* CQ page directory. */
10966 uint64_t cq_page_dir;
10967 /* VNIC page directory. */
10968 uint64_t vnic_page_dir;
10969 /* Stat page directory. */
10970 uint64_t stat_page_dir;
10971 /* TQM slowpath page directory. */
10972 uint64_t tqm_sp_page_dir;
10973 /* TQM ring 0 page directory. */
10974 uint64_t tqm_ring0_page_dir;
10975 /* TQM ring 1 page directory. */
10976 uint64_t tqm_ring1_page_dir;
10977 /* TQM ring 2 page directory. */
10978 uint64_t tqm_ring2_page_dir;
10979 /* TQM ring 3 page directory. */
10980 uint64_t tqm_ring3_page_dir;
10981 /* TQM ring 4 page directory. */
10982 uint64_t tqm_ring4_page_dir;
10983 /* TQM ring 5 page directory. */
10984 uint64_t tqm_ring5_page_dir;
10985 /* TQM ring 6 page directory. */
10986 uint64_t tqm_ring6_page_dir;
10987 /* TQM ring 7 page directory. */
10988 uint64_t tqm_ring7_page_dir;
10989 /* MR/AV page directory. */
10990 uint64_t mrav_page_dir;
10991 /* Timer page directory. */
10992 uint64_t tim_page_dir;
10993 /* Number of entries to reserve for QP1 */
10994 uint16_t qp_num_qp1_entries;
10995 /* Number of entries to reserve for L2 */
10996 uint16_t qp_num_l2_entries;
10997 /* Number of QPs. */
10998 uint32_t qp_num_entries;
10999 /* Number of SRQs. */
11000 uint32_t srq_num_entries;
11001 /* Number of entries to reserve for L2 */
11002 uint16_t srq_num_l2_entries;
11003 /* Number of entries to reserve for L2 */
11004 uint16_t cq_num_l2_entries;
11005 /* Number of CQs. */
11006 uint32_t cq_num_entries;
11007 /* Number of entries to reserve for VNIC entries */
11008 uint16_t vnic_num_vnic_entries;
11009 /* Number of entries to reserve for Ring table entries */
11010 uint16_t vnic_num_ring_table_entries;
11011 /* Number of Stats. */
11012 uint32_t stat_num_entries;
11013 /* Number of TQM slowpath entries. */
11014 uint32_t tqm_sp_num_entries;
11015 /* Number of TQM ring 0 entries. */
11016 uint32_t tqm_ring0_num_entries;
11017 /* Number of TQM ring 1 entries. */
11018 uint32_t tqm_ring1_num_entries;
11019 /* Number of TQM ring 2 entries. */
11020 uint32_t tqm_ring2_num_entries;
11021 /* Number of TQM ring 3 entries. */
11022 uint32_t tqm_ring3_num_entries;
11023 /* Number of TQM ring 4 entries. */
11024 uint32_t tqm_ring4_num_entries;
11025 /* Number of TQM ring 5 entries. */
11026 uint32_t tqm_ring5_num_entries;
11027 /* Number of TQM ring 6 entries. */
11028 uint32_t tqm_ring6_num_entries;
11029 /* Number of TQM ring 7 entries. */
11030 uint32_t tqm_ring7_num_entries;
11032 * If the MR/AV split reservation flag is not set, then this field
11033 * represents the total number of MR plus AV entries. For versions
11034 * of firmware that support the split reservation, when it is not
11035 * specified half of the entries will be reserved for MRs and the
11036 * other half for AVs.
11038 * If the MR/AV split reservation flag is set, then this
11039 * field is logically divided into two 16b fields. Bits `[31:16]`
11040 * represents the `mr_num_entries` and bits `[15:0]` represents
11041 * `av_num_entries`. The granularity of these values is defined by
11042 * the `mrav_num_entries_unit` field returned by the
11043 * `backing_store_qcaps` command.
11045 uint32_t mrav_num_entries;
11046 /* Number of Timer entries. */
11047 uint32_t tim_num_entries;
11048 uint8_t unused_1[7];
11050 * This field is used in Output records to indicate that the output
11051 * is completely written to RAM. This field should be read as 1
11052 * to indicate that the output has been completely written.
11053 * When writing a command completion or response to an internal
11054 * processor, the order of writes has to be such that this field
11058 } __attribute__((packed));
11060 /****************************
11061 * hwrm_error_recovery_qcfg *
11062 ****************************/
11065 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
11066 struct hwrm_error_recovery_qcfg_input {
11067 /* The HWRM command request type. */
11070 * The completion ring to send the completion event on. This should
11071 * be the NQ ID returned from the `nq_alloc` HWRM command.
11073 uint16_t cmpl_ring;
11075 * The sequence ID is used by the driver for tracking multiple
11076 * commands. This ID is treated as opaque data by the firmware and
11077 * the value is returned in the `hwrm_resp_hdr` upon completion.
11081 * The target ID of the command:
11082 * * 0x0-0xFFF8 - The function ID
11083 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11084 * * 0xFFFD - Reserved for user-space HWRM interface
11087 uint16_t target_id;
11089 * A physical address pointer pointing to a host buffer that the
11090 * command's response data will be written. This can be either a host
11091 * physical address (HPA) or a guest physical address (GPA) and must
11092 * point to a physically contiguous block of memory.
11094 uint64_t resp_addr;
11095 uint8_t unused_0[8];
11096 } __attribute__((packed));
11098 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
11099 struct hwrm_error_recovery_qcfg_output {
11100 /* The specific error status for the command. */
11101 uint16_t error_code;
11102 /* The HWRM command request type. */
11104 /* The sequence ID from the original command. */
11106 /* The length of the response data in number of bytes. */
11110 * When this flag is set to 1, error recovery will be initiated
11111 * through master function driver.
11113 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
11115 * When this flag is set to 1, error recovery will be performed
11116 * through Co processor.
11118 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
11120 * Driver Polling frequency. This value is in units of 100msec.
11121 * Typical value would be 10 to indicate 1sec.
11122 * Drivers can poll FW health status, Heartbeat, reset_counter with
11125 uint32_t driver_polling_freq;
11127 * This value is in units of 100msec.
11128 * Typical value would be 30 to indicate 3sec.
11129 * Master function wait period from detecting a fatal error to
11130 * initiating reset. In this time period Master PF expects every
11131 * active driver will detect fatal error.
11133 uint32_t master_func_wait_period;
11135 * This value is in units of 100msec.
11136 * Typical value would be 50 to indicate 5sec.
11137 * Normal function wait period from fatal error detection to
11138 * polling FW health status. In this time period, drivers should not
11139 * do any PCIe MMIO transaction and should not send any HWRM commands.
11141 uint32_t normal_func_wait_period;
11143 * This value is in units of 100msec.
11144 * Typical value would be 20 to indicate 2sec.
11145 * This field indicates that, master function wait period after chip
11146 * reset. After this time, master function should reinitialize with
11149 uint32_t master_func_wait_period_after_reset;
11151 * This value is in units of 100msec.
11152 * Typical value would be 60 to indicate 6sec.
11153 * This field is applicable to both master and normal functions.
11154 * Even after chip reset, if FW status not changed to ready,
11155 * then all the functions can poll for this much time and bailout.
11157 uint32_t max_bailout_time_after_reset;
11159 * FW health status register.
11160 * Lower 2 bits indicates address space location and upper 30 bits
11161 * indicates upper 30bits of the register address.
11162 * A value of 0xFFFF-FFFF indicates this register does not exist.
11164 uint32_t fw_health_status_reg;
11165 /* Lower 2 bits indicates address space location. */
11166 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11168 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11171 * If value is 0, this register is located in PCIe config space.
11172 * Drivers have to map appropriate window to access this
11175 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11178 * If value is 1, this register is located in GRC address space.
11179 * Drivers have to map appropriate window to access this
11182 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11185 * If value is 2, this register is located in first BAR address
11186 * space. Drivers have to map appropriate window to access this
11189 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11192 * If value is 3, this register is located in second BAR address
11193 * space. Drivers have to map appropriate window to access this
11194 * Drivers have to map appropriate window to access this
11197 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11199 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11200 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11201 /* Upper 30bits of the register address. */
11202 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11203 UINT32_C(0xfffffffc)
11204 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11207 * FW HeartBeat register.
11208 * Lower 2 bits indicates address space location and upper 30 bits
11209 * indicates actual address.
11210 * A value of 0xFFFF-FFFF indicates this register does not exist.
11212 uint32_t fw_heartbeat_reg;
11213 /* Lower 2 bits indicates address space location. */
11214 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11216 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11219 * If value is 0, this register is located in PCIe config space.
11220 * Drivers have to map appropriate window to access this
11223 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11226 * If value is 1, this register is located in GRC address space.
11227 * Drivers have to map appropriate window to access this
11230 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11233 * If value is 2, this register is located in first BAR address
11234 * space. Drivers have to map appropriate window to access this
11237 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
11240 * If value is 3, this register is located in second BAR address
11241 * space. Drivers have to map appropriate window to access this
11244 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
11246 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
11247 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
11248 /* Upper 30bits of the register address. */
11249 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
11250 UINT32_C(0xfffffffc)
11251 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
11254 * FW reset counter.
11255 * Lower 2 bits indicates address space location and upper 30 bits
11256 * indicates actual address.
11257 * A value of 0xFFFF-FFFF indicates this register does not exist.
11259 uint32_t fw_reset_cnt_reg;
11260 /* Lower 2 bits indicates address space location. */
11261 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
11263 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
11266 * If value is 0, this register is located in PCIe config space.
11267 * Drivers have to map appropriate window to access this
11270 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
11273 * If value is 1, this register is located in GRC address space.
11274 * Drivers have to map appropriate window to access this
11277 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
11280 * If value is 2, this register is located in first BAR address
11281 * space. Drivers have to map appropriate window to access this
11284 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
11287 * If value is 3, this register is located in second BAR address
11288 * space. Drivers have to map appropriate window to access this
11291 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
11293 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
11294 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
11295 /* Upper 30bits of the register address. */
11296 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
11297 UINT32_C(0xfffffffc)
11298 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
11301 * Reset Inprogress Register address for PFs.
11302 * Lower 2 bits indicates address space location and upper 30 bits
11303 * indicates actual address.
11304 * A value of 0xFFFF-FFFF indicates this register does not exist.
11306 uint32_t reset_inprogress_reg;
11307 /* Lower 2 bits indicates address space location. */
11308 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
11310 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
11313 * If value is 0, this register is located in PCIe config space.
11314 * Drivers have to map appropriate window to access this
11317 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
11320 * If value is 1, this register is located in GRC address space.
11321 * Drivers have to map appropriate window to access this
11324 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
11327 * If value is 2, this register is located in first BAR address
11328 * space. Drivers have to map appropriate window to access this
11331 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
11334 * If value is 3, this register is located in second BAR address
11335 * space. Drivers have to map appropriate window to access this
11338 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
11340 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
11341 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
11342 /* Upper 30bits of the register address. */
11343 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
11344 UINT32_C(0xfffffffc)
11345 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
11347 /* This field indicates the mask value for reset_inprogress_reg. */
11348 uint32_t reset_inprogress_reg_mask;
11349 uint8_t unused_0[3];
11351 * Array of registers and value count to reset the Chip
11352 * Each array count has reset_reg, reset_reg_val, delay_after_reset
11353 * in TLV format. Depending upon Chip type, number of reset registers
11354 * will vary. Drivers have to write reset_reg_val in the reset_reg
11355 * location in the same sequence in order to recover from a fatal
11358 uint8_t reg_array_cnt;
11361 * Lower 2 bits indicates address space location and upper 30 bits
11362 * indicates actual address.
11363 * A value of 0xFFFF-FFFF indicates this register does not exist.
11365 uint32_t reset_reg[16];
11366 /* Lower 2 bits indicates address space location. */
11367 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
11369 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
11371 * If value is 0, this register is located in PCIe config space.
11372 * Drivers have to map appropriate window to access this
11375 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
11378 * If value is 1, this register is located in GRC address space.
11379 * Drivers have to map appropriate window to access this
11382 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
11385 * If value is 2, this register is located in first BAR address
11386 * space. Drivers have to map appropriate window to access this
11389 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
11392 * If value is 3, this register is located in second BAR address
11393 * space. Drivers have to map appropriate window to access this
11396 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
11398 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
11399 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
11400 /* Upper 30bits of the register address. */
11401 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
11402 UINT32_C(0xfffffffc)
11403 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
11404 /* Value to be written in reset_reg to reset the controller. */
11405 uint32_t reset_reg_val[16];
11407 * This value is in units of 1msec.
11408 * Typical value would be 10 to indicate 10msec.
11409 * Some of the operations like Core reset require delay before
11410 * accessing PCIE MMIO register space.
11411 * If this value is non-zero, drivers have to wait for
11412 * this much time after writing reset_reg_val in reset_reg.
11414 uint8_t delay_after_reset[16];
11415 uint8_t unused_1[7];
11417 * This field is used in Output records to indicate that the output
11418 * is completely written to RAM. This field should be read as '1'
11419 * to indicate that the output has been completely written.
11420 * When writing a command completion or response to an internal
11421 * processor, the order of writes has to be such that this field
11425 } __attribute__((packed));
11427 /***********************
11428 * hwrm_func_vlan_qcfg *
11429 ***********************/
11432 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
11433 struct hwrm_func_vlan_qcfg_input {
11434 /* The HWRM command request type. */
11437 * The completion ring to send the completion event on. This should
11438 * be the NQ ID returned from the `nq_alloc` HWRM command.
11440 uint16_t cmpl_ring;
11442 * The sequence ID is used by the driver for tracking multiple
11443 * commands. This ID is treated as opaque data by the firmware and
11444 * the value is returned in the `hwrm_resp_hdr` upon completion.
11448 * The target ID of the command:
11449 * * 0x0-0xFFF8 - The function ID
11450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11451 * * 0xFFFD - Reserved for user-space HWRM interface
11454 uint16_t target_id;
11456 * A physical address pointer pointing to a host buffer that the
11457 * command's response data will be written. This can be either a host
11458 * physical address (HPA) or a guest physical address (GPA) and must
11459 * point to a physically contiguous block of memory.
11461 uint64_t resp_addr;
11463 * Function ID of the function that is being
11465 * If set to 0xFF... (All Fs), then the configuration is
11466 * for the requesting function.
11469 uint8_t unused_0[6];
11470 } __attribute__((packed));
11472 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
11473 struct hwrm_func_vlan_qcfg_output {
11474 /* The specific error status for the command. */
11475 uint16_t error_code;
11476 /* The HWRM command request type. */
11478 /* The sequence ID from the original command. */
11480 /* The length of the response data in number of bytes. */
11483 /* S-TAG VLAN identifier configured for the function. */
11485 /* S-TAG PCP value configured for the function. */
11489 * S-TAG TPID value configured for the function. This field is specified in
11490 * network byte order.
11492 uint16_t stag_tpid;
11493 /* C-TAG VLAN identifier configured for the function. */
11495 /* C-TAG PCP value configured for the function. */
11499 * C-TAG TPID value configured for the function. This field is specified in
11500 * network byte order.
11502 uint16_t ctag_tpid;
11507 uint8_t unused_3[3];
11509 * This field is used in Output records to indicate that the output
11510 * is completely written to RAM. This field should be read as '1'
11511 * to indicate that the output has been completely written.
11512 * When writing a command completion or response to an internal processor,
11513 * the order of writes has to be such that this field is written last.
11516 } __attribute__((packed));
11518 /**********************
11519 * hwrm_func_vlan_cfg *
11520 **********************/
11523 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
11524 struct hwrm_func_vlan_cfg_input {
11525 /* The HWRM command request type. */
11528 * The completion ring to send the completion event on. This should
11529 * be the NQ ID returned from the `nq_alloc` HWRM command.
11531 uint16_t cmpl_ring;
11533 * The sequence ID is used by the driver for tracking multiple
11534 * commands. This ID is treated as opaque data by the firmware and
11535 * the value is returned in the `hwrm_resp_hdr` upon completion.
11539 * The target ID of the command:
11540 * * 0x0-0xFFF8 - The function ID
11541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11542 * * 0xFFFD - Reserved for user-space HWRM interface
11545 uint16_t target_id;
11547 * A physical address pointer pointing to a host buffer that the
11548 * command's response data will be written. This can be either a host
11549 * physical address (HPA) or a guest physical address (GPA) and must
11550 * point to a physically contiguous block of memory.
11552 uint64_t resp_addr;
11554 * Function ID of the function that is being
11556 * If set to 0xFF... (All Fs), then the configuration is
11557 * for the requesting function.
11560 uint8_t unused_0[2];
11563 * This bit must be '1' for the stag_vid field to be
11566 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
11568 * This bit must be '1' for the ctag_vid field to be
11571 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
11573 * This bit must be '1' for the stag_pcp field to be
11576 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
11578 * This bit must be '1' for the ctag_pcp field to be
11581 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
11583 * This bit must be '1' for the stag_tpid field to be
11586 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
11588 * This bit must be '1' for the ctag_tpid field to be
11591 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
11592 /* S-TAG VLAN identifier configured for the function. */
11594 /* S-TAG PCP value configured for the function. */
11598 * S-TAG TPID value configured for the function. This field is specified in
11599 * network byte order.
11601 uint16_t stag_tpid;
11602 /* C-TAG VLAN identifier configured for the function. */
11604 /* C-TAG PCP value configured for the function. */
11608 * C-TAG TPID value configured for the function. This field is specified in
11609 * network byte order.
11611 uint16_t ctag_tpid;
11616 uint8_t unused_3[4];
11617 } __attribute__((packed));
11619 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
11620 struct hwrm_func_vlan_cfg_output {
11621 /* The specific error status for the command. */
11622 uint16_t error_code;
11623 /* The HWRM command request type. */
11625 /* The sequence ID from the original command. */
11627 /* The length of the response data in number of bytes. */
11629 uint8_t unused_0[7];
11631 * This field is used in Output records to indicate that the output
11632 * is completely written to RAM. This field should be read as '1'
11633 * to indicate that the output has been completely written.
11634 * When writing a command completion or response to an internal processor,
11635 * the order of writes has to be such that this field is written last.
11638 } __attribute__((packed));
11640 /*******************************
11641 * hwrm_func_vf_vnic_ids_query *
11642 *******************************/
11645 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
11646 struct hwrm_func_vf_vnic_ids_query_input {
11647 /* The HWRM command request type. */
11650 * The completion ring to send the completion event on. This should
11651 * be the NQ ID returned from the `nq_alloc` HWRM command.
11653 uint16_t cmpl_ring;
11655 * The sequence ID is used by the driver for tracking multiple
11656 * commands. This ID is treated as opaque data by the firmware and
11657 * the value is returned in the `hwrm_resp_hdr` upon completion.
11661 * The target ID of the command:
11662 * * 0x0-0xFFF8 - The function ID
11663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11664 * * 0xFFFD - Reserved for user-space HWRM interface
11667 uint16_t target_id;
11669 * A physical address pointer pointing to a host buffer that the
11670 * command's response data will be written. This can be either a host
11671 * physical address (HPA) or a guest physical address (GPA) and must
11672 * point to a physically contiguous block of memory.
11674 uint64_t resp_addr;
11676 * This value is used to identify a Virtual Function (VF).
11677 * The scope of VF ID is local within a PF.
11680 uint8_t unused_0[2];
11681 /* Max number of vnic ids in vnic id table */
11682 uint32_t max_vnic_id_cnt;
11683 /* This is the address for VF VNIC ID table */
11684 uint64_t vnic_id_tbl_addr;
11685 } __attribute__((packed));
11687 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
11688 struct hwrm_func_vf_vnic_ids_query_output {
11689 /* The specific error status for the command. */
11690 uint16_t error_code;
11691 /* The HWRM command request type. */
11693 /* The sequence ID from the original command. */
11695 /* The length of the response data in number of bytes. */
11698 * Actual number of vnic ids
11700 * Each VNIC ID is written as a 32-bit number.
11702 uint32_t vnic_id_cnt;
11703 uint8_t unused_0[3];
11705 * This field is used in Output records to indicate that the output
11706 * is completely written to RAM. This field should be read as '1'
11707 * to indicate that the output has been completely written.
11708 * When writing a command completion or response to an internal processor,
11709 * the order of writes has to be such that this field is written last.
11712 } __attribute__((packed));
11714 /***********************
11715 * hwrm_func_vf_bw_cfg *
11716 ***********************/
11719 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
11720 struct hwrm_func_vf_bw_cfg_input {
11721 /* The HWRM command request type. */
11724 * The completion ring to send the completion event on. This should
11725 * be the NQ ID returned from the `nq_alloc` HWRM command.
11727 uint16_t cmpl_ring;
11729 * The sequence ID is used by the driver for tracking multiple
11730 * commands. This ID is treated as opaque data by the firmware and
11731 * the value is returned in the `hwrm_resp_hdr` upon completion.
11735 * The target ID of the command:
11736 * * 0x0-0xFFF8 - The function ID
11737 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11738 * * 0xFFFD - Reserved for user-space HWRM interface
11741 uint16_t target_id;
11743 * A physical address pointer pointing to a host buffer that the
11744 * command's response data will be written. This can be either a host
11745 * physical address (HPA) or a guest physical address (GPA) and must
11746 * point to a physically contiguous block of memory.
11748 uint64_t resp_addr;
11750 * The number of VF functions that are being configured.
11751 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
11754 uint16_t unused[3];
11755 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
11757 /* The physical VF id the adjustment will be made to. */
11758 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
11759 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
11761 * This field configures the rate scale percentage of the VF as specified
11762 * by the physical VF id.
11764 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
11765 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
11766 /* 0% of the max tx rate */
11767 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
11768 (UINT32_C(0x0) << 12)
11769 /* 6.66% of the max tx rate */
11770 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
11771 (UINT32_C(0x1) << 12)
11772 /* 13.33% of the max tx rate */
11773 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
11774 (UINT32_C(0x2) << 12)
11775 /* 20% of the max tx rate */
11776 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
11777 (UINT32_C(0x3) << 12)
11778 /* 26.66% of the max tx rate */
11779 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
11780 (UINT32_C(0x4) << 12)
11781 /* 33% of the max tx rate */
11782 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
11783 (UINT32_C(0x5) << 12)
11784 /* 40% of the max tx rate */
11785 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
11786 (UINT32_C(0x6) << 12)
11787 /* 46.66% of the max tx rate */
11788 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
11789 (UINT32_C(0x7) << 12)
11790 /* 53.33% of the max tx rate */
11791 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
11792 (UINT32_C(0x8) << 12)
11793 /* 60% of the max tx rate */
11794 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
11795 (UINT32_C(0x9) << 12)
11796 /* 66.66% of the max tx rate */
11797 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
11798 (UINT32_C(0xa) << 12)
11799 /* 53.33% of the max tx rate */
11800 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
11801 (UINT32_C(0xb) << 12)
11802 /* 80% of the max tx rate */
11803 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
11804 (UINT32_C(0xc) << 12)
11805 /* 86.66% of the max tx rate */
11806 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
11807 (UINT32_C(0xd) << 12)
11808 /* 93.33% of the max tx rate */
11809 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
11810 (UINT32_C(0xe) << 12)
11811 /* 100% of the max tx rate */
11812 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
11813 (UINT32_C(0xf) << 12)
11814 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
11815 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
11816 } __attribute__((packed));
11818 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
11819 struct hwrm_func_vf_bw_cfg_output {
11820 /* The specific error status for the command. */
11821 uint16_t error_code;
11822 /* The HWRM command request type. */
11824 /* The sequence ID from the original command. */
11826 /* The length of the response data in number of bytes. */
11828 uint8_t unused_0[7];
11830 * This field is used in Output records to indicate that the output
11831 * is completely written to RAM. This field should be read as '1'
11832 * to indicate that the output has been completely written.
11833 * When writing a command completion or response to an internal processor,
11834 * the order of writes has to be such that this field is written last.
11837 } __attribute__((packed));
11839 /************************
11840 * hwrm_func_vf_bw_qcfg *
11841 ************************/
11844 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
11845 struct hwrm_func_vf_bw_qcfg_input {
11846 /* The HWRM command request type. */
11849 * The completion ring to send the completion event on. This should
11850 * be the NQ ID returned from the `nq_alloc` HWRM command.
11852 uint16_t cmpl_ring;
11854 * The sequence ID is used by the driver for tracking multiple
11855 * commands. This ID is treated as opaque data by the firmware and
11856 * the value is returned in the `hwrm_resp_hdr` upon completion.
11860 * The target ID of the command:
11861 * * 0x0-0xFFF8 - The function ID
11862 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11863 * * 0xFFFD - Reserved for user-space HWRM interface
11866 uint16_t target_id;
11868 * A physical address pointer pointing to a host buffer that the
11869 * command's response data will be written. This can be either a host
11870 * physical address (HPA) or a guest physical address (GPA) and must
11871 * point to a physically contiguous block of memory.
11873 uint64_t resp_addr;
11875 * The number of VF functions that are being queried.
11876 * The inline response space allows the host to query up to 50 VFs'
11877 * rate scale percentage
11880 uint16_t unused[3];
11881 /* These 16-bit fields contain the VF fid */
11883 /* The physical VF id of interest */
11884 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
11885 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
11886 } __attribute__((packed));
11888 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
11889 struct hwrm_func_vf_bw_qcfg_output {
11890 /* The specific error status for the command. */
11891 uint16_t error_code;
11892 /* The HWRM command request type. */
11894 /* The sequence ID from the original command. */
11896 /* The length of the response data in number of bytes. */
11899 * The number of VF functions that are being queried.
11900 * The inline response space allows the host to query up to 50 VFs' rate
11904 uint16_t unused[3];
11905 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
11907 /* The physical VF id the adjustment will be made to. */
11908 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
11909 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
11911 * This field configures the rate scale percentage of the VF as specified
11912 * by the physical VF id.
11914 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
11915 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
11916 /* 0% of the max tx rate */
11917 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
11918 (UINT32_C(0x0) << 12)
11919 /* 6.66% of the max tx rate */
11920 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
11921 (UINT32_C(0x1) << 12)
11922 /* 13.33% of the max tx rate */
11923 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
11924 (UINT32_C(0x2) << 12)
11925 /* 20% of the max tx rate */
11926 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
11927 (UINT32_C(0x3) << 12)
11928 /* 26.66% of the max tx rate */
11929 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
11930 (UINT32_C(0x4) << 12)
11931 /* 33% of the max tx rate */
11932 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
11933 (UINT32_C(0x5) << 12)
11934 /* 40% of the max tx rate */
11935 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
11936 (UINT32_C(0x6) << 12)
11937 /* 46.66% of the max tx rate */
11938 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
11939 (UINT32_C(0x7) << 12)
11940 /* 53.33% of the max tx rate */
11941 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
11942 (UINT32_C(0x8) << 12)
11943 /* 60% of the max tx rate */
11944 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
11945 (UINT32_C(0x9) << 12)
11946 /* 66.66% of the max tx rate */
11947 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
11948 (UINT32_C(0xa) << 12)
11949 /* 53.33% of the max tx rate */
11950 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
11951 (UINT32_C(0xb) << 12)
11952 /* 80% of the max tx rate */
11953 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
11954 (UINT32_C(0xc) << 12)
11955 /* 86.66% of the max tx rate */
11956 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
11957 (UINT32_C(0xd) << 12)
11958 /* 93.33% of the max tx rate */
11959 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
11960 (UINT32_C(0xe) << 12)
11961 /* 100% of the max tx rate */
11962 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
11963 (UINT32_C(0xf) << 12)
11964 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
11965 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
11966 uint8_t unused_0[7];
11968 * This field is used in Output records to indicate that the output
11969 * is completely written to RAM. This field should be read as '1'
11970 * to indicate that the output has been completely written.
11971 * When writing a command completion or response to an internal processor,
11972 * the order of writes has to be such that this field is written last.
11975 } __attribute__((packed));
11977 /***************************
11978 * hwrm_func_drv_if_change *
11979 ***************************/
11982 /* hwrm_func_drv_if_change_input (size:192b/24B) */
11983 struct hwrm_func_drv_if_change_input {
11984 /* The HWRM command request type. */
11987 * The completion ring to send the completion event on. This should
11988 * be the NQ ID returned from the `nq_alloc` HWRM command.
11990 uint16_t cmpl_ring;
11992 * The sequence ID is used by the driver for tracking multiple
11993 * commands. This ID is treated as opaque data by the firmware and
11994 * the value is returned in the `hwrm_resp_hdr` upon completion.
11998 * The target ID of the command:
11999 * * 0x0-0xFFF8 - The function ID
12000 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12001 * * 0xFFFD - Reserved for user-space HWRM interface
12004 uint16_t target_id;
12006 * A physical address pointer pointing to a host buffer that the
12007 * command's response data will be written. This can be either a host
12008 * physical address (HPA) or a guest physical address (GPA) and must
12009 * point to a physically contiguous block of memory.
12011 uint64_t resp_addr;
12014 * When this bit is '1', the function driver is indicating
12015 * that the IF state is changing to UP state. The call should
12016 * be made at the beginning of the driver's open call before
12017 * resources are allocated. After making the call, the driver
12018 * should check the response to see if any resources may have
12019 * changed (see the response below). If the driver fails
12020 * the open call, the driver should make this call again with
12021 * this bit cleared to indicate that the IF state is not UP.
12022 * During the driver's close call when the IF state is changing
12023 * to DOWN, the driver should make this call with the bit cleared
12024 * after all resources have been freed.
12026 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
12028 } __attribute__((packed));
12030 /* hwrm_func_drv_if_change_output (size:128b/16B) */
12031 struct hwrm_func_drv_if_change_output {
12032 /* The specific error status for the command. */
12033 uint16_t error_code;
12034 /* The HWRM command request type. */
12036 /* The sequence ID from the original command. */
12038 /* The length of the response data in number of bytes. */
12042 * When this bit is '1', it indicates that the resources reserved
12043 * for this function may have changed. The driver should check
12044 * resource capabilities and reserve resources again before
12045 * allocating resources.
12047 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
12050 * When this bit is '1', it indicates that the firmware got changed / reset.
12051 * The driver should do complete re-initialization when that bit is set.
12053 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
12055 uint8_t unused_0[3];
12057 * This field is used in Output records to indicate that the output
12058 * is completely written to RAM. This field should be read as '1'
12059 * to indicate that the output has been completely written.
12060 * When writing a command completion or response to an internal processor,
12061 * the order of writes has to be such that this field is written last.
12064 } __attribute__((packed));
12066 /*********************
12067 * hwrm_port_phy_cfg *
12068 *********************/
12071 /* hwrm_port_phy_cfg_input (size:448b/56B) */
12072 struct hwrm_port_phy_cfg_input {
12073 /* The HWRM command request type. */
12076 * The completion ring to send the completion event on. This should
12077 * be the NQ ID returned from the `nq_alloc` HWRM command.
12079 uint16_t cmpl_ring;
12081 * The sequence ID is used by the driver for tracking multiple
12082 * commands. This ID is treated as opaque data by the firmware and
12083 * the value is returned in the `hwrm_resp_hdr` upon completion.
12087 * The target ID of the command:
12088 * * 0x0-0xFFF8 - The function ID
12089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12090 * * 0xFFFD - Reserved for user-space HWRM interface
12093 uint16_t target_id;
12095 * A physical address pointer pointing to a host buffer that the
12096 * command's response data will be written. This can be either a host
12097 * physical address (HPA) or a guest physical address (GPA) and must
12098 * point to a physically contiguous block of memory.
12100 uint64_t resp_addr;
12103 * When this bit is set to '1', the PHY for the port shall
12106 * # If this bit is set to 1, then the HWRM shall reset the
12107 * PHY after applying PHY configuration changes specified
12109 * # In order to guarantee that PHY configuration changes
12110 * specified in this command take effect, the HWRM
12111 * client should set this flag to 1.
12112 * # If this bit is not set to 1, then the HWRM may reset
12113 * the PHY depending on the current PHY configuration and
12114 * settings specified in this command.
12116 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
12118 /* deprecated bit. Do not use!!! */
12119 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
12122 * When this bit is set to '1', the link shall be forced to
12123 * the force_link_speed value.
12125 * When this bit is set to '1', the HWRM client should
12126 * not enable any of the auto negotiation related
12127 * fields represented by auto_XXX fields in this command.
12128 * When this bit is set to '1' and the HWRM client has
12129 * enabled a auto_XXX field in this command, then the
12130 * HWRM shall ignore the enabled auto_XXX field.
12132 * When this bit is set to zero, the link
12133 * shall be allowed to autoneg.
12135 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
12138 * When this bit is set to '1', the auto-negotiation process
12139 * shall be restarted on the link.
12141 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
12144 * When this bit is set to '1', Energy Efficient Ethernet
12145 * (EEE) is requested to be enabled on this link.
12146 * If EEE is not supported on this port, then this flag
12147 * shall be ignored by the HWRM.
12149 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
12152 * When this bit is set to '1', Energy Efficient Ethernet
12153 * (EEE) is requested to be disabled on this link.
12154 * If EEE is not supported on this port, then this flag
12155 * shall be ignored by the HWRM.
12157 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
12160 * When this bit is set to '1' and EEE is enabled on this
12161 * link, then TX LPI is requested to be enabled on the link.
12162 * If EEE is not supported on this port, then this flag
12163 * shall be ignored by the HWRM.
12164 * If EEE is disabled on this port, then this flag shall be
12165 * ignored by the HWRM.
12167 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
12170 * When this bit is set to '1' and EEE is enabled on this
12171 * link, then TX LPI is requested to be disabled on the link.
12172 * If EEE is not supported on this port, then this flag
12173 * shall be ignored by the HWRM.
12174 * If EEE is disabled on this port, then this flag shall be
12175 * ignored by the HWRM.
12177 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
12180 * When set to 1, then the HWRM shall enable FEC autonegotitation
12181 * on this port if supported.
12182 * When set to 0, then this flag shall be ignored.
12183 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
12186 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
12189 * When set to 1, then the HWRM shall disable FEC autonegotiation
12190 * on this port if supported.
12191 * When set to 0, then this flag shall be ignored.
12192 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
12195 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
12198 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
12199 * on this port if supported.
12200 * When set to 0, then this flag shall be ignored.
12201 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
12204 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
12207 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
12208 * on this port if supported.
12209 * When set to 0, then this flag shall be ignored.
12210 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
12213 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
12216 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
12217 * on this port if supported.
12218 * When set to 0, then this flag shall be ignored.
12219 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
12222 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
12225 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
12226 * on this port if supported.
12227 * When set to 0, then this flag shall be ignored.
12228 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
12231 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
12234 * When this bit is set to '1', the link shall be forced to
12237 * # When this bit is set to '1", all other
12238 * command input settings related to the link speed shall
12240 * Once the link state is forced down, it can be
12241 * explicitly cleared from that state by setting this flag
12243 * # If this flag is set to '0', then the link shall be
12244 * cleared from forced down state if the link is in forced
12246 * There may be conditions (e.g. out-of-band or sideband
12247 * configuration changes for the link) outside the scope
12248 * of the HWRM implementation that may clear forced down
12251 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
12255 * This bit must be '1' for the auto_mode field to be
12258 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
12261 * This bit must be '1' for the auto_duplex field to be
12264 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
12267 * This bit must be '1' for the auto_pause field to be
12270 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
12273 * This bit must be '1' for the auto_link_speed field to be
12276 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
12279 * This bit must be '1' for the auto_link_speed_mask field to be
12282 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
12285 * This bit must be '1' for the wirespeed field to be
12288 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
12291 * This bit must be '1' for the lpbk field to be
12294 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
12297 * This bit must be '1' for the preemphasis field to be
12300 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
12303 * This bit must be '1' for the force_pause field to be
12306 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
12309 * This bit must be '1' for the eee_link_speed_mask field to be
12312 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
12315 * This bit must be '1' for the tx_lpi_timer field to be
12318 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
12320 /* Port ID of port that is to be configured. */
12323 * This is the speed that will be used if the force
12324 * bit is '1'. If unsupported speed is selected, an error
12325 * will be generated.
12327 uint16_t force_link_speed;
12328 /* 100Mb link speed */
12329 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
12330 /* 1Gb link speed */
12331 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
12332 /* 2Gb link speed */
12333 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
12334 /* 25Gb link speed */
12335 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
12336 /* 10Gb link speed */
12337 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
12338 /* 20Mb link speed */
12339 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
12340 /* 25Gb link speed */
12341 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
12342 /* 40Gb link speed */
12343 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
12344 /* 50Gb link speed */
12345 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
12346 /* 100Gb link speed */
12347 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
12348 /* 200Gb link speed */
12349 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
12350 /* 10Mb link speed */
12351 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
12352 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
12353 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
12355 * This value is used to identify what autoneg mode is
12356 * used when the link speed is not being forced.
12359 /* Disable autoneg or autoneg disabled. No speeds are selected. */
12360 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
12361 /* Select all possible speeds for autoneg mode. */
12362 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
12364 * Select only the auto_link_speed speed for autoneg mode. This mode has
12365 * been DEPRECATED. An HWRM client should not use this mode.
12367 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
12369 * Select the auto_link_speed or any speed below that speed for autoneg.
12370 * This mode has been DEPRECATED. An HWRM client should not use this mode.
12372 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
12374 * Select the speeds based on the corresponding link speed mask value
12375 * that is provided.
12377 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
12378 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
12379 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
12381 * This is the duplex setting that will be used if the autoneg_mode
12382 * is "one_speed" or "one_or_below".
12384 uint8_t auto_duplex;
12385 /* Half Duplex will be requested. */
12386 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
12387 /* Full duplex will be requested. */
12388 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
12389 /* Both Half and Full dupex will be requested. */
12390 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
12391 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
12392 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
12394 * This value is used to configure the pause that will be
12395 * used for autonegotiation.
12396 * Add text on the usage of auto_pause and force_pause.
12398 uint8_t auto_pause;
12400 * When this bit is '1', Generation of tx pause messages
12401 * has been requested. Disabled otherwise.
12403 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
12406 * When this bit is '1', Reception of rx pause messages
12407 * has been requested. Disabled otherwise.
12409 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
12412 * When set to 1, the advertisement of pause is enabled.
12414 * # When the auto_mode is not set to none and this flag is
12415 * set to 1, then the auto_pause bits on this port are being
12416 * advertised and autoneg pause results are being interpreted.
12417 * # When the auto_mode is not set to none and this
12418 * flag is set to 0, the pause is forced as indicated in
12419 * force_pause, and also advertised as auto_pause bits, but
12420 * the autoneg results are not interpreted since the pause
12421 * configuration is being forced.
12422 * # When the auto_mode is set to none and this flag is set to
12423 * 1, auto_pause bits should be ignored and should be set to 0.
12425 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
12429 * This is the speed that will be used if the autoneg_mode
12430 * is "one_speed" or "one_or_below". If an unsupported speed
12431 * is selected, an error will be generated.
12433 uint16_t auto_link_speed;
12434 /* 100Mb link speed */
12435 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
12436 /* 1Gb link speed */
12437 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
12438 /* 2Gb link speed */
12439 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
12440 /* 25Gb link speed */
12441 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
12442 /* 10Gb link speed */
12443 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
12444 /* 20Mb link speed */
12445 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
12446 /* 25Gb link speed */
12447 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
12448 /* 40Gb link speed */
12449 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
12450 /* 50Gb link speed */
12451 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
12452 /* 100Gb link speed */
12453 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
12454 /* 200Gb link speed */
12455 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
12456 /* 10Mb link speed */
12457 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
12458 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
12459 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
12461 * This is a mask of link speeds that will be used if
12462 * autoneg_mode is "mask". If unsupported speed is enabled
12463 * an error will be generated.
12465 uint16_t auto_link_speed_mask;
12466 /* 100Mb link speed (Half-duplex) */
12467 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
12469 /* 100Mb link speed (Full-duplex) */
12470 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
12472 /* 1Gb link speed (Half-duplex) */
12473 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
12475 /* 1Gb link speed (Full-duplex) */
12476 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
12478 /* 2Gb link speed */
12479 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
12481 /* 25Gb link speed */
12482 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
12484 /* 10Gb link speed */
12485 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
12487 /* 20Gb link speed */
12488 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
12490 /* 25Gb link speed */
12491 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
12493 /* 40Gb link speed */
12494 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
12496 /* 50Gb link speed */
12497 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
12499 /* 100Gb link speed */
12500 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
12502 /* 10Mb link speed (Half-duplex) */
12503 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
12505 /* 10Mb link speed (Full-duplex) */
12506 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
12508 /* 200Gb link speed */
12509 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
12511 /* This value controls the wirespeed feature. */
12513 /* Wirespeed feature is disabled. */
12514 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
12515 /* Wirespeed feature is enabled. */
12516 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
12517 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
12518 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
12519 /* This value controls the loopback setting for the PHY. */
12521 /* No loopback is selected. Normal operation. */
12522 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
12524 * The HW will be configured with local loopback such that
12525 * host data is sent back to the host without modification.
12527 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
12529 * The HW will be configured with remote loopback such that
12530 * port logic will send packets back out the transmitter that
12533 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
12535 * The HW will be configured with external loopback such that
12536 * host data is sent on the trasmitter and based on the external
12537 * loopback connection the data will be received without modification.
12539 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
12540 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
12541 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
12543 * This value is used to configure the pause that will be
12544 * used for force mode.
12546 uint8_t force_pause;
12548 * When this bit is '1', Generation of tx pause messages
12549 * is supported. Disabled otherwise.
12551 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
12553 * When this bit is '1', Reception of rx pause messages
12554 * is supported. Disabled otherwise.
12556 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
12559 * This value controls the pre-emphasis to be used for the
12560 * link. Driver should not set this value (use
12561 * enable.preemphasis = 0) unless driver is sure of setting.
12562 * Normally HWRM FW will determine proper pre-emphasis.
12564 uint32_t preemphasis;
12566 * Setting for link speed mask that is used to
12567 * advertise speeds during autonegotiation when EEE is enabled.
12568 * This field is valid only when EEE is enabled.
12569 * The speeds specified in this field shall be a subset of
12570 * speeds specified in auto_link_speed_mask.
12571 * If EEE is enabled,then at least one speed shall be provided
12574 uint16_t eee_link_speed_mask;
12576 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
12578 /* 100Mb link speed (Full-duplex) */
12579 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
12582 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
12584 /* 1Gb link speed (Full-duplex) */
12585 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
12588 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
12591 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
12593 /* 10Gb link speed */
12594 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
12596 uint8_t unused_2[2];
12598 * Reuested setting of TX LPI timer in microseconds.
12599 * This field is valid only when EEE is enabled and TX LPI is
12602 uint32_t tx_lpi_timer;
12603 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
12604 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
12606 } __attribute__((packed));
12608 /* hwrm_port_phy_cfg_output (size:128b/16B) */
12609 struct hwrm_port_phy_cfg_output {
12610 /* The specific error status for the command. */
12611 uint16_t error_code;
12612 /* The HWRM command request type. */
12614 /* The sequence ID from the original command. */
12616 /* The length of the response data in number of bytes. */
12618 uint8_t unused_0[7];
12620 * This field is used in Output records to indicate that the output
12621 * is completely written to RAM. This field should be read as '1'
12622 * to indicate that the output has been completely written.
12623 * When writing a command completion or response to an internal processor,
12624 * the order of writes has to be such that this field is written last.
12627 } __attribute__((packed));
12629 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
12630 struct hwrm_port_phy_cfg_cmd_err {
12632 * command specific error codes that goes to
12633 * the cmd_err field in Common HWRM Error Response.
12636 /* Unknown error */
12637 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
12638 /* Unable to complete operation due to invalid speed */
12639 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
12641 * retry the command since the phy is not ready.
12642 * retry count is returned in opaque_0.
12643 * This is only valid for the first command and
12644 * this value will not change for successive calls.
12645 * but if a 0 is returned at any time then this should
12646 * be treated as an un recoverable failure,
12648 * retry interval in milli seconds is returned in opaque_1.
12649 * This specifies the time that user should wait before
12650 * issuing the next port_phy_cfg command.
12652 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
12653 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
12654 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
12655 uint8_t unused_0[7];
12656 } __attribute__((packed));
12658 /**********************
12659 * hwrm_port_phy_qcfg *
12660 **********************/
12663 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
12664 struct hwrm_port_phy_qcfg_input {
12665 /* The HWRM command request type. */
12668 * The completion ring to send the completion event on. This should
12669 * be the NQ ID returned from the `nq_alloc` HWRM command.
12671 uint16_t cmpl_ring;
12673 * The sequence ID is used by the driver for tracking multiple
12674 * commands. This ID is treated as opaque data by the firmware and
12675 * the value is returned in the `hwrm_resp_hdr` upon completion.
12679 * The target ID of the command:
12680 * * 0x0-0xFFF8 - The function ID
12681 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12682 * * 0xFFFD - Reserved for user-space HWRM interface
12685 uint16_t target_id;
12687 * A physical address pointer pointing to a host buffer that the
12688 * command's response data will be written. This can be either a host
12689 * physical address (HPA) or a guest physical address (GPA) and must
12690 * point to a physically contiguous block of memory.
12692 uint64_t resp_addr;
12693 /* Port ID of port that is to be queried. */
12695 uint8_t unused_0[6];
12696 } __attribute__((packed));
12698 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
12699 struct hwrm_port_phy_qcfg_output {
12700 /* The specific error status for the command. */
12701 uint16_t error_code;
12702 /* The HWRM command request type. */
12704 /* The sequence ID from the original command. */
12706 /* The length of the response data in number of bytes. */
12708 /* This value indicates the current link status. */
12710 /* There is no link or cable detected. */
12711 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
12712 /* There is no link, but a cable has been detected. */
12713 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
12714 /* There is a link. */
12715 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
12716 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
12717 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
12719 /* This value indicates the current link speed of the connection. */
12720 uint16_t link_speed;
12721 /* 100Mb link speed */
12722 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
12723 /* 1Gb link speed */
12724 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
12725 /* 2Gb link speed */
12726 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
12727 /* 25Gb link speed */
12728 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
12729 /* 10Gb link speed */
12730 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
12731 /* 20Mb link speed */
12732 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
12733 /* 25Gb link speed */
12734 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
12735 /* 40Gb link speed */
12736 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
12737 /* 50Gb link speed */
12738 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
12739 /* 100Gb link speed */
12740 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
12741 /* 200Gb link speed */
12742 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
12743 /* 10Mb link speed */
12744 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
12745 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
12746 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
12748 * This value is indicates the duplex of the current
12751 uint8_t duplex_cfg;
12752 /* Half Duplex connection. */
12753 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
12754 /* Full duplex connection. */
12755 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
12756 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
12757 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
12759 * This value is used to indicate the current
12760 * pause configuration. When autoneg is enabled, this value
12761 * represents the autoneg results of pause configuration.
12765 * When this bit is '1', Generation of tx pause messages
12766 * is supported. Disabled otherwise.
12768 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
12770 * When this bit is '1', Reception of rx pause messages
12771 * is supported. Disabled otherwise.
12773 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
12775 * The supported speeds for the port. This is a bit mask.
12776 * For each speed that is supported, the corrresponding
12777 * bit will be set to '1'.
12779 uint16_t support_speeds;
12780 /* 100Mb link speed (Half-duplex) */
12781 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
12783 /* 100Mb link speed (Full-duplex) */
12784 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
12786 /* 1Gb link speed (Half-duplex) */
12787 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
12789 /* 1Gb link speed (Full-duplex) */
12790 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
12792 /* 2Gb link speed */
12793 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
12795 /* 25Gb link speed */
12796 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
12798 /* 10Gb link speed */
12799 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
12801 /* 20Gb link speed */
12802 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
12804 /* 25Gb link speed */
12805 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
12807 /* 40Gb link speed */
12808 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
12810 /* 50Gb link speed */
12811 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
12813 /* 100Gb link speed */
12814 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
12816 /* 10Mb link speed (Half-duplex) */
12817 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
12819 /* 10Mb link speed (Full-duplex) */
12820 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
12822 /* 200Gb link speed */
12823 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
12826 * Current setting of forced link speed.
12827 * When the link speed is not being forced, this
12828 * value shall be set to 0.
12830 uint16_t force_link_speed;
12831 /* 100Mb link speed */
12832 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
12833 /* 1Gb link speed */
12834 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
12835 /* 2Gb link speed */
12836 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
12837 /* 25Gb link speed */
12838 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
12839 /* 10Gb link speed */
12840 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
12841 /* 20Mb link speed */
12842 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
12843 /* 25Gb link speed */
12844 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
12845 /* 40Gb link speed */
12846 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
12848 /* 50Gb link speed */
12849 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
12851 /* 100Gb link speed */
12852 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
12854 /* 200Gb link speed */
12855 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
12857 /* 10Mb link speed */
12858 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
12860 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
12861 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
12862 /* Current setting of auto negotiation mode. */
12864 /* Disable autoneg or autoneg disabled. No speeds are selected. */
12865 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
12866 /* Select all possible speeds for autoneg mode. */
12867 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
12869 * Select only the auto_link_speed speed for autoneg mode. This mode has
12870 * been DEPRECATED. An HWRM client should not use this mode.
12872 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
12874 * Select the auto_link_speed or any speed below that speed for autoneg.
12875 * This mode has been DEPRECATED. An HWRM client should not use this mode.
12877 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
12879 * Select the speeds based on the corresponding link speed mask value
12880 * that is provided.
12882 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
12883 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
12884 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
12886 * Current setting of pause autonegotiation.
12887 * Move autoneg_pause flag here.
12889 uint8_t auto_pause;
12891 * When this bit is '1', Generation of tx pause messages
12892 * has been requested. Disabled otherwise.
12894 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
12897 * When this bit is '1', Reception of rx pause messages
12898 * has been requested. Disabled otherwise.
12900 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
12903 * When set to 1, the advertisement of pause is enabled.
12905 * # When the auto_mode is not set to none and this flag is
12906 * set to 1, then the auto_pause bits on this port are being
12907 * advertised and autoneg pause results are being interpreted.
12908 * # When the auto_mode is not set to none and this
12909 * flag is set to 0, the pause is forced as indicated in
12910 * force_pause, and also advertised as auto_pause bits, but
12911 * the autoneg results are not interpreted since the pause
12912 * configuration is being forced.
12913 * # When the auto_mode is set to none and this flag is set to
12914 * 1, auto_pause bits should be ignored and should be set to 0.
12916 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
12919 * Current setting for auto_link_speed. This field is only
12920 * valid when auto_mode is set to "one_speed" or "one_or_below".
12922 uint16_t auto_link_speed;
12923 /* 100Mb link speed */
12924 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
12925 /* 1Gb link speed */
12926 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
12927 /* 2Gb link speed */
12928 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
12929 /* 25Gb link speed */
12930 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
12931 /* 10Gb link speed */
12932 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
12933 /* 20Mb link speed */
12934 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
12935 /* 25Gb link speed */
12936 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
12937 /* 40Gb link speed */
12938 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
12939 /* 50Gb link speed */
12940 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
12941 /* 100Gb link speed */
12942 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
12943 /* 200Gb link speed */
12944 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
12945 /* 10Mb link speed */
12946 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
12948 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
12949 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
12951 * Current setting for auto_link_speed_mask that is used to
12952 * advertise speeds during autonegotiation.
12953 * This field is only valid when auto_mode is set to "mask".
12954 * The speeds specified in this field shall be a subset of
12955 * supported speeds on this port.
12957 uint16_t auto_link_speed_mask;
12958 /* 100Mb link speed (Half-duplex) */
12959 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
12961 /* 100Mb link speed (Full-duplex) */
12962 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
12964 /* 1Gb link speed (Half-duplex) */
12965 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
12967 /* 1Gb link speed (Full-duplex) */
12968 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
12970 /* 2Gb link speed */
12971 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
12973 /* 25Gb link speed */
12974 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
12976 /* 10Gb link speed */
12977 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
12979 /* 20Gb link speed */
12980 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
12982 /* 25Gb link speed */
12983 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
12985 /* 40Gb link speed */
12986 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
12988 /* 50Gb link speed */
12989 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
12991 /* 100Gb link speed */
12992 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
12994 /* 10Mb link speed (Half-duplex) */
12995 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
12997 /* 10Mb link speed (Full-duplex) */
12998 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
13000 /* 200Gb link speed */
13001 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
13003 /* Current setting for wirespeed. */
13005 /* Wirespeed feature is disabled. */
13006 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
13007 /* Wirespeed feature is enabled. */
13008 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
13009 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
13010 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
13011 /* Current setting for loopback. */
13013 /* No loopback is selected. Normal operation. */
13014 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13016 * The HW will be configured with local loopback such that
13017 * host data is sent back to the host without modification.
13019 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13021 * The HW will be configured with remote loopback such that
13022 * port logic will send packets back out the transmitter that
13025 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13027 * The HW will be configured with external loopback such that
13028 * host data is sent on the trasmitter and based on the external
13029 * loopback connection the data will be received without modification.
13031 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
13032 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
13033 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
13035 * Current setting of forced pause.
13036 * When the pause configuration is not being forced, then
13037 * this value shall be set to 0.
13039 uint8_t force_pause;
13041 * When this bit is '1', Generation of tx pause messages
13042 * is supported. Disabled otherwise.
13044 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13046 * When this bit is '1', Reception of rx pause messages
13047 * is supported. Disabled otherwise.
13049 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13051 * This value indicates the current status of the optics module on
13054 uint8_t module_status;
13055 /* Module is inserted and accepted */
13056 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
13058 /* Module is rejected and transmit side Laser is disabled. */
13059 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
13061 /* Module mismatch warning. */
13062 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
13064 /* Module is rejected and powered down. */
13065 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
13067 /* Module is not inserted. */
13068 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
13070 /* Module status is not applicable. */
13071 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
13073 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
13074 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
13075 /* Current setting for preemphasis. */
13076 uint32_t preemphasis;
13077 /* This field represents the major version of the PHY. */
13079 /* This field represents the minor version of the PHY. */
13081 /* This field represents the build version of the PHY. */
13083 /* This value represents a PHY type. */
13086 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
13089 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
13091 /* BASE-KR4 (Deprecated) */
13092 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
13095 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
13098 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
13100 /* BASE-KR2 (Deprecated) */
13101 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
13104 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
13107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
13110 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
13112 /* EEE capable BASE-T */
13113 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
13115 /* SGMII connected external PHY */
13116 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
13118 /* 25G_BASECR_CA_L */
13119 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
13121 /* 25G_BASECR_CA_S */
13122 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
13124 /* 25G_BASECR_CA_N */
13125 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
13128 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
13131 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
13134 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
13137 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
13140 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
13142 /* 100G_BASESR10 */
13143 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
13146 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
13149 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
13152 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
13155 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
13157 /* 40G_ACTIVE_CABLE */
13158 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
13161 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
13164 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
13167 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
13170 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
13173 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
13176 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
13179 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
13181 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
13182 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
13183 /* This value represents a media type. */
13184 uint8_t media_type;
13186 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
13188 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
13189 /* Direct Attached Copper */
13190 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
13192 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
13193 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
13194 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
13195 /* This value represents a transceiver type. */
13196 uint8_t xcvr_pkg_type;
13197 /* PHY and MAC are in the same package */
13198 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
13200 /* PHY and MAC are in different packages */
13201 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
13203 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
13204 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
13205 uint8_t eee_config_phy_addr;
13206 /* This field represents PHY address. */
13207 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
13209 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
13211 * This field represents flags related to EEE configuration.
13212 * These EEE configuration flags are valid only when the
13213 * auto_mode is not set to none (in other words autonegotiation
13216 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
13218 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
13220 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
13221 * Speeds for autoneg with EEE mode enabled
13222 * are based on eee_link_speed_mask.
13224 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
13227 * This flag is valid only when eee_enabled is set to 1.
13229 * # If eee_enabled is set to 0, then EEE mode is disabled
13230 * and this flag shall be ignored.
13231 * # If eee_enabled is set to 1 and this flag is set to 1,
13232 * then Energy Efficient Ethernet (EEE) mode is enabled
13234 * # If eee_enabled is set to 1 and this flag is set to 0,
13235 * then Energy Efficient Ethernet (EEE) mode is enabled
13236 * but is currently not in use.
13238 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
13241 * This flag is valid only when eee_enabled is set to 1.
13243 * # If eee_enabled is set to 0, then EEE mode is disabled
13244 * and this flag shall be ignored.
13245 * # If eee_enabled is set to 1 and this flag is set to 1,
13246 * then Energy Efficient Ethernet (EEE) mode is enabled
13247 * and TX LPI is enabled.
13248 * # If eee_enabled is set to 1 and this flag is set to 0,
13249 * then Energy Efficient Ethernet (EEE) mode is enabled
13250 * but TX LPI is disabled.
13252 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
13255 * When set to 1, the parallel detection is used to determine
13256 * the speed of the link partner.
13258 * Parallel detection is used when a autonegotiation capable
13259 * device is connected to a link parter that is not capable
13260 * of autonegotiation.
13262 uint8_t parallel_detect;
13264 * When set to 1, the parallel detection is used to determine
13265 * the speed of the link partner.
13267 * Parallel detection is used when a autonegotiation capable
13268 * device is connected to a link parter that is not capable
13269 * of autonegotiation.
13271 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
13273 * The advertised speeds for the port by the link partner.
13274 * Each advertised speed will be set to '1'.
13276 uint16_t link_partner_adv_speeds;
13277 /* 100Mb link speed (Half-duplex) */
13278 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
13280 /* 100Mb link speed (Full-duplex) */
13281 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
13283 /* 1Gb link speed (Half-duplex) */
13284 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
13286 /* 1Gb link speed (Full-duplex) */
13287 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
13289 /* 2Gb link speed */
13290 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
13292 /* 25Gb link speed */
13293 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
13295 /* 10Gb link speed */
13296 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
13298 /* 20Gb link speed */
13299 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
13301 /* 25Gb link speed */
13302 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
13304 /* 40Gb link speed */
13305 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
13307 /* 50Gb link speed */
13308 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
13310 /* 100Gb link speed */
13311 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
13313 /* 10Mb link speed (Half-duplex) */
13314 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
13316 /* 10Mb link speed (Full-duplex) */
13317 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
13320 * The advertised autoneg for the port by the link partner.
13321 * This field is deprecated and should be set to 0.
13323 uint8_t link_partner_adv_auto_mode;
13324 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13325 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
13327 /* Select all possible speeds for autoneg mode. */
13328 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
13331 * Select only the auto_link_speed speed for autoneg mode. This mode has
13332 * been DEPRECATED. An HWRM client should not use this mode.
13334 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
13337 * Select the auto_link_speed or any speed below that speed for autoneg.
13338 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13340 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
13343 * Select the speeds based on the corresponding link speed mask value
13344 * that is provided.
13346 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
13348 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
13349 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
13350 /* The advertised pause settings on the port by the link partner. */
13351 uint8_t link_partner_adv_pause;
13353 * When this bit is '1', Generation of tx pause messages
13354 * is supported. Disabled otherwise.
13356 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
13359 * When this bit is '1', Reception of rx pause messages
13360 * is supported. Disabled otherwise.
13362 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
13365 * Current setting for link speed mask that is used to
13366 * advertise speeds during autonegotiation when EEE is enabled.
13367 * This field is valid only when eee_enabled flags is set to 1.
13368 * The speeds specified in this field shall be a subset of
13369 * speeds specified in auto_link_speed_mask.
13371 uint16_t adv_eee_link_speed_mask;
13373 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
13375 /* 100Mb link speed (Full-duplex) */
13376 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
13379 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
13381 /* 1Gb link speed (Full-duplex) */
13382 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
13385 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
13388 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
13390 /* 10Gb link speed */
13391 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
13394 * Current setting for link speed mask that is advertised by
13395 * the link partner when EEE is enabled.
13396 * This field is valid only when eee_enabled flags is set to 1.
13398 uint16_t link_partner_adv_eee_link_speed_mask;
13400 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
13402 /* 100Mb link speed (Full-duplex) */
13403 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
13406 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
13408 /* 1Gb link speed (Full-duplex) */
13409 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
13412 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
13415 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
13417 /* 10Gb link speed */
13418 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
13420 uint32_t xcvr_identifier_type_tx_lpi_timer;
13422 * Current setting of TX LPI timer in microseconds.
13423 * This field is valid only when_eee_enabled flag is set to 1
13424 * and tx_lpi_enabled is set to 1.
13426 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
13428 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
13429 /* This value represents transceiver identifier type. */
13430 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
13431 UINT32_C(0xff000000)
13432 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
13434 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
13435 (UINT32_C(0x0) << 24)
13436 /* SFP/SFP+/SFP28 */
13437 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
13438 (UINT32_C(0x3) << 24)
13440 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
13441 (UINT32_C(0xc) << 24)
13443 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
13444 (UINT32_C(0xd) << 24)
13446 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
13447 (UINT32_C(0x11) << 24)
13448 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
13449 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
13451 * This value represents the current configuration of
13452 * Forward Error Correction (FEC) on the port.
13456 * When set to 1, then FEC is not supported on this port. If this flag
13457 * is set to 1, then all other FEC configuration flags shall be ignored.
13458 * When set to 0, then FEC is supported as indicated by other
13459 * configuration flags.
13460 * If no cable is attached and the HWRM does not yet know the FEC
13461 * capability, then the HWRM shall set this flag to 1 when reporting
13464 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
13467 * When set to 1, then FEC autonegotiation is supported on this port.
13468 * When set to 0, then FEC autonegotiation is not supported on this port.
13470 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
13473 * When set to 1, then FEC autonegotiation is enabled on this port.
13474 * When set to 0, then FEC autonegotiation is disabled if supported.
13475 * This flag should be ignored if FEC autonegotiation is not supported on this port.
13477 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
13480 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
13481 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
13483 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
13486 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
13487 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
13488 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
13490 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
13493 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
13494 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
13496 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
13499 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
13500 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
13501 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
13503 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
13506 * This value is indicates the duplex of the current
13507 * connection state.
13509 uint8_t duplex_state;
13510 /* Half Duplex connection. */
13511 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
13512 /* Full duplex connection. */
13513 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
13514 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
13515 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
13516 /* Option flags fields. */
13517 uint8_t option_flags;
13518 /* When this bit is '1', Media auto detect is enabled. */
13519 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
13522 * Up to 16 bytes of null padded ASCII string representing
13524 * If the string is set to null, then the vendor name is not
13527 char phy_vendor_name[16];
13529 * Up to 16 bytes of null padded ASCII string that
13530 * identifies vendor specific part number of the PHY.
13531 * If the string is set to null, then the vendor specific
13532 * part number is not available.
13534 char phy_vendor_partnumber[16];
13535 uint8_t unused_2[7];
13537 * This field is used in Output records to indicate that the output
13538 * is completely written to RAM. This field should be read as '1'
13539 * to indicate that the output has been completely written.
13540 * When writing a command completion or response to an internal processor,
13541 * the order of writes has to be such that this field is written last.
13544 } __attribute__((packed));
13546 /*********************
13547 * hwrm_port_mac_cfg *
13548 *********************/
13551 /* hwrm_port_mac_cfg_input (size:384b/48B) */
13552 struct hwrm_port_mac_cfg_input {
13553 /* The HWRM command request type. */
13556 * The completion ring to send the completion event on. This should
13557 * be the NQ ID returned from the `nq_alloc` HWRM command.
13559 uint16_t cmpl_ring;
13561 * The sequence ID is used by the driver for tracking multiple
13562 * commands. This ID is treated as opaque data by the firmware and
13563 * the value is returned in the `hwrm_resp_hdr` upon completion.
13567 * The target ID of the command:
13568 * * 0x0-0xFFF8 - The function ID
13569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13570 * * 0xFFFD - Reserved for user-space HWRM interface
13573 uint16_t target_id;
13575 * A physical address pointer pointing to a host buffer that the
13576 * command's response data will be written. This can be either a host
13577 * physical address (HPA) or a guest physical address (GPA) and must
13578 * point to a physically contiguous block of memory.
13580 uint64_t resp_addr;
13582 * In this field, there are a number of CoS mappings related flags
13583 * that are used to configure CoS mappings and their corresponding
13584 * priorities in the hardware.
13585 * For the priorities of CoS mappings, the HWRM uses the following
13586 * priority order (high to low) by default:
13589 * # tunnel_vlan_pri
13592 * A subset of CoS mappings can be enabled.
13593 * If a priority is not specified for an enabled CoS mapping, the
13594 * priority will be assigned in the above order for the enabled CoS
13595 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
13596 * enabled and their priorities are not specified, the following
13597 * priority order (high to low) will be used by the HWRM:
13602 * vlan_pri CoS mapping together with default CoS with lower priority
13603 * are enabled by default by the HWRM.
13607 * When this bit is '1', this command will configure
13608 * the MAC to match the current link state of the PHY.
13609 * If the link is not established on the PHY, then this
13610 * bit has no effect.
13612 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
13615 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
13616 * is requested to be enabled.
13618 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
13621 * When this bit is set to '1', tunnel VLAN PRI field to
13622 * CoS mapping is requested to be enabled.
13624 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
13627 * When this bit is set to '1', the IP DSCP to CoS mapping is
13628 * requested to be enabled.
13630 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
13633 * When this bit is '1', the HWRM is requested to
13634 * enable timestamp capture capability on the receive side
13637 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
13640 * When this bit is '1', the HWRM is requested to
13641 * disable timestamp capture capability on the receive side
13644 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
13647 * When this bit is '1', the HWRM is requested to
13648 * enable timestamp capture capability on the transmit side
13651 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
13654 * When this bit is '1', the HWRM is requested to
13655 * disable timestamp capture capability on the transmit side
13658 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
13661 * When this bit is '1', the Out-Of-Box WoL is requested to
13662 * be enabled on this port.
13664 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
13667 * When this bit is '1', the the Out-Of-Box WoL is requested to
13668 * be disabled on this port.
13670 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
13673 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
13674 * is requested to be disabled.
13676 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
13679 * When this bit is set to '1', tunnel VLAN PRI field to
13680 * CoS mapping is requested to be disabled.
13682 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
13685 * When this bit is set to '1', the IP DSCP to CoS mapping is
13686 * requested to be disabled.
13688 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
13691 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
13692 * bit is set, then the device uses one step Tx timestamping.
13693 * This bit is temporary and used for experimental purposes.
13695 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
13699 * This bit must be '1' for the ipg field to be
13702 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
13705 * This bit must be '1' for the lpbk field to be
13708 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
13711 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
13714 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
13717 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
13720 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
13723 * This bit must be '1' for the dscp2cos_map_pri field to be
13726 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
13729 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
13732 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
13735 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
13738 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
13741 * This bit must be '1' for the cos_field_cfg field to be
13744 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
13747 * This bit must be '1' for the ptp_freq_adj_ppb field to be
13750 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
13752 /* Port ID of port that is to be configured. */
13755 * This value is used to configure the minimum IPG that will
13756 * be sent between packets by this port.
13759 /* This value controls the loopback setting for the MAC. */
13761 /* No loopback is selected. Normal operation. */
13762 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13764 * The HW will be configured with local loopback such that
13765 * host data is sent back to the host without modification.
13767 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13769 * The HW will be configured with remote loopback such that
13770 * port logic will send packets back out the transmitter that
13773 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13774 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
13775 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
13777 * This value controls the priority setting of VLAN PRI to CoS
13778 * mapping based on VLAN Tags of inner packet headers of
13779 * tunneled packets or packet headers of non-tunneled packets.
13781 * # Each XXX_pri variable shall have a unique priority value
13782 * when it is being specified.
13783 * # When comparing priorities of mappings, higher value
13784 * indicates higher priority.
13785 * For example, a value of 0-3 is returned where 0 is being
13786 * the lowest priority and 3 is being the highest priority.
13788 uint8_t vlan_pri2cos_map_pri;
13789 /* Reserved field. */
13792 * This value controls the priority setting of VLAN PRI to CoS
13793 * mapping based on VLAN Tags of tunneled header.
13794 * This mapping only applies when tunneled headers
13797 * # Each XXX_pri variable shall have a unique priority value
13798 * when it is being specified.
13799 * # When comparing priorities of mappings, higher value
13800 * indicates higher priority.
13801 * For example, a value of 0-3 is returned where 0 is being
13802 * the lowest priority and 3 is being the highest priority.
13804 uint8_t tunnel_pri2cos_map_pri;
13806 * This value controls the priority setting of IP DSCP to CoS
13807 * mapping based on inner IP header of tunneled packets or
13808 * IP header of non-tunneled packets.
13810 * # Each XXX_pri variable shall have a unique priority value
13811 * when it is being specified.
13812 * # When comparing priorities of mappings, higher value
13813 * indicates higher priority.
13814 * For example, a value of 0-3 is returned where 0 is being
13815 * the lowest priority and 3 is being the highest priority.
13817 uint8_t dscp2pri_map_pri;
13819 * This is a 16-bit bit mask that is used to request a
13820 * specific configuration of time stamp capture of PTP messages
13821 * on the receive side of this port.
13822 * This field shall be ignored if the ptp_rx_ts_capture_enable
13823 * flag is not set in this command.
13824 * Otherwise, if bit 'i' is set, then the HWRM is being
13825 * requested to configure the receive side of the port to
13826 * capture the time stamp of every received PTP message
13827 * with messageType field value set to i.
13829 uint16_t rx_ts_capture_ptp_msg_type;
13831 * This is a 16-bit bit mask that is used to request a
13832 * specific configuration of time stamp capture of PTP messages
13833 * on the transmit side of this port.
13834 * This field shall be ignored if the ptp_tx_ts_capture_enable
13835 * flag is not set in this command.
13836 * Otherwise, if bit 'i' is set, then the HWRM is being
13837 * requested to configure the transmit sied of the port to
13838 * capture the time stamp of every transmitted PTP message
13839 * with messageType field value set to i.
13841 uint16_t tx_ts_capture_ptp_msg_type;
13842 /* Configuration of CoS fields. */
13843 uint8_t cos_field_cfg;
13845 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
13848 * This field is used to specify selection of VLAN PRI value
13849 * based on whether one or two VLAN Tags are present in
13850 * the inner packet headers of tunneled packets or
13851 * non-tunneled packets.
13852 * This field is valid only if inner VLAN PRI to CoS mapping
13854 * If VLAN PRI to CoS mapping is not enabled, then this
13855 * field shall be ignored.
13857 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
13859 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
13862 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13863 * present in the inner packet headers
13865 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
13866 (UINT32_C(0x0) << 1)
13868 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13869 * present in the inner packet headers.
13870 * No VLAN PRI shall be selected for this configuration
13871 * if only one VLAN Tag is present in the inner
13874 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
13875 (UINT32_C(0x1) << 1)
13877 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13878 * are present in the inner packet headers
13880 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
13881 (UINT32_C(0x2) << 1)
13883 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
13884 (UINT32_C(0x3) << 1)
13885 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
13886 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
13888 * This field is used to specify selection of tunnel VLAN
13889 * PRI value based on whether one or two VLAN Tags are
13890 * present in tunnel headers.
13891 * This field is valid only if tunnel VLAN PRI to CoS mapping
13893 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
13894 * field shall be ignored.
13896 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
13898 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
13901 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13902 * present in the tunnel packet headers
13904 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
13905 (UINT32_C(0x0) << 3)
13907 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13908 * present in the tunnel packet headers.
13909 * No tunnel VLAN PRI shall be selected for this
13910 * configuration if only one VLAN Tag is present in
13911 * the tunnel packet headers.
13913 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
13914 (UINT32_C(0x1) << 3)
13916 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13917 * are present in the tunnel packet headers
13919 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
13920 (UINT32_C(0x2) << 3)
13922 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
13923 (UINT32_C(0x3) << 3)
13924 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
13925 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
13927 * This field shall be used to provide default CoS value
13928 * that has been configured on this port.
13929 * This field is valid only if default CoS mapping
13931 * If default CoS mapping is not enabled, then this
13932 * field shall be ignored.
13934 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
13936 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
13938 uint8_t unused_0[3];
13940 * This signed field specifies by how much to adjust the frequency
13941 * of sync timer updates (measured in parts per billion).
13943 int32_t ptp_freq_adj_ppb;
13944 uint8_t unused_1[4];
13945 } __attribute__((packed));
13947 /* hwrm_port_mac_cfg_output (size:128b/16B) */
13948 struct hwrm_port_mac_cfg_output {
13949 /* The specific error status for the command. */
13950 uint16_t error_code;
13951 /* The HWRM command request type. */
13953 /* The sequence ID from the original command. */
13955 /* The length of the response data in number of bytes. */
13958 * This is the configured maximum length of Ethernet packet
13959 * payload that is allowed to be received on the port.
13960 * This value does not include the number of bytes used by
13961 * Ethernet header and trailer (CRC).
13965 * This is the configured maximum length of Ethernet packet
13966 * payload that is allowed to be transmitted on the port.
13967 * This value does not include the number of bytes used by
13968 * Ethernet header and trailer (CRC).
13971 /* Current configuration of the IPG value. */
13973 /* Current value of the loopback value. */
13975 /* No loopback is selected. Normal operation. */
13976 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13978 * The HW will be configured with local loopback such that
13979 * host data is sent back to the host without modification.
13981 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13983 * The HW will be configured with remote loopback such that
13984 * port logic will send packets back out the transmitter that
13987 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13988 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
13989 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
13992 * This field is used in Output records to indicate that the output
13993 * is completely written to RAM. This field should be read as '1'
13994 * to indicate that the output has been completely written.
13995 * When writing a command completion or response to an internal processor,
13996 * the order of writes has to be such that this field is written last.
13999 } __attribute__((packed));
14001 /**********************
14002 * hwrm_port_mac_qcfg *
14003 **********************/
14006 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
14007 struct hwrm_port_mac_qcfg_input {
14008 /* The HWRM command request type. */
14011 * The completion ring to send the completion event on. This should
14012 * be the NQ ID returned from the `nq_alloc` HWRM command.
14014 uint16_t cmpl_ring;
14016 * The sequence ID is used by the driver for tracking multiple
14017 * commands. This ID is treated as opaque data by the firmware and
14018 * the value is returned in the `hwrm_resp_hdr` upon completion.
14022 * The target ID of the command:
14023 * * 0x0-0xFFF8 - The function ID
14024 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14025 * * 0xFFFD - Reserved for user-space HWRM interface
14028 uint16_t target_id;
14030 * A physical address pointer pointing to a host buffer that the
14031 * command's response data will be written. This can be either a host
14032 * physical address (HPA) or a guest physical address (GPA) and must
14033 * point to a physically contiguous block of memory.
14035 uint64_t resp_addr;
14036 /* Port ID of port that is to be configured. */
14038 uint8_t unused_0[6];
14039 } __attribute__((packed));
14041 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
14042 struct hwrm_port_mac_qcfg_output {
14043 /* The specific error status for the command. */
14044 uint16_t error_code;
14045 /* The HWRM command request type. */
14047 /* The sequence ID from the original command. */
14049 /* The length of the response data in number of bytes. */
14052 * This is the configured maximum length of Ethernet packet
14053 * payload that is allowed to be received on the port.
14054 * This value does not include the number of bytes used by the
14055 * Ethernet header and trailer (CRC).
14059 * This is the configured maximum length of Ethernet packet
14060 * payload that is allowed to be transmitted on the port.
14061 * This value does not include the number of bytes used by the
14062 * Ethernet header and trailer (CRC).
14066 * The minimum IPG that will
14067 * be sent between packets by this port.
14070 /* The loopback setting for the MAC. */
14072 /* No loopback is selected. Normal operation. */
14073 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14075 * The HW will be configured with local loopback such that
14076 * host data is sent back to the host without modification.
14078 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14080 * The HW will be configured with remote loopback such that
14081 * port logic will send packets back out the transmitter that
14084 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14085 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
14086 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
14088 * Priority setting for VLAN PRI to CoS mapping.
14089 * # Each XXX_pri variable shall have a unique priority value
14090 * when it is being used.
14091 * # When comparing priorities of mappings, higher value
14092 * indicates higher priority.
14093 * For example, a value of 0-3 is returned where 0 is being
14094 * the lowest priority and 3 is being the highest priority.
14095 * # If the correspoding CoS mapping is not enabled, then this
14096 * field should be ignored.
14097 * # This value indicates the normalized priority value retained
14100 uint8_t vlan_pri2cos_map_pri;
14102 * In this field, a number of CoS mappings related flags
14103 * are used to indicate configured CoS mappings.
14107 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14110 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14113 * When this bit is set to '1', tunnel VLAN PRI field to
14114 * CoS mapping is enabled.
14116 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14119 * When this bit is set to '1', the IP DSCP to CoS mapping is
14122 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
14125 * When this bit is '1', the Out-Of-Box WoL is enabled on this
14128 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
14130 /* When this bit is '1', PTP is enabled for RX on this port. */
14131 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14133 /* When this bit is '1', PTP is enabled for TX on this port. */
14134 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14137 * Priority setting for tunnel VLAN PRI to CoS mapping.
14138 * # Each XXX_pri variable shall have a unique priority value
14139 * when it is being used.
14140 * # When comparing priorities of mappings, higher value
14141 * indicates higher priority.
14142 * For example, a value of 0-3 is returned where 0 is being
14143 * the lowest priority and 3 is being the highest priority.
14144 * # If the correspoding CoS mapping is not enabled, then this
14145 * field should be ignored.
14146 * # This value indicates the normalized priority value retained
14149 uint8_t tunnel_pri2cos_map_pri;
14151 * Priority setting for DSCP to PRI mapping.
14152 * # Each XXX_pri variable shall have a unique priority value
14153 * when it is being used.
14154 * # When comparing priorities of mappings, higher value
14155 * indicates higher priority.
14156 * For example, a value of 0-3 is returned where 0 is being
14157 * the lowest priority and 3 is being the highest priority.
14158 * # If the correspoding CoS mapping is not enabled, then this
14159 * field should be ignored.
14160 * # This value indicates the normalized priority value retained
14163 uint8_t dscp2pri_map_pri;
14165 * This is a 16-bit bit mask that represents the
14166 * current configuration of time stamp capture of PTP messages
14167 * on the receive side of this port.
14168 * If bit 'i' is set, then the receive side of the port
14169 * is configured to capture the time stamp of every
14170 * received PTP message with messageType field value set
14172 * If all bits are set to 0 (i.e. field value set 0),
14173 * then the receive side of the port is not configured
14174 * to capture timestamp for PTP messages.
14175 * If all bits are set to 1, then the receive side of the
14176 * port is configured to capture timestamp for all PTP
14179 uint16_t rx_ts_capture_ptp_msg_type;
14181 * This is a 16-bit bit mask that represents the
14182 * current configuration of time stamp capture of PTP messages
14183 * on the transmit side of this port.
14184 * If bit 'i' is set, then the transmit side of the port
14185 * is configured to capture the time stamp of every
14186 * received PTP message with messageType field value set
14188 * If all bits are set to 0 (i.e. field value set 0),
14189 * then the transmit side of the port is not configured
14190 * to capture timestamp for PTP messages.
14191 * If all bits are set to 1, then the transmit side of the
14192 * port is configured to capture timestamp for all PTP
14195 uint16_t tx_ts_capture_ptp_msg_type;
14196 /* Configuration of CoS fields. */
14197 uint8_t cos_field_cfg;
14199 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
14202 * This field is used for selecting VLAN PRI value
14203 * based on whether one or two VLAN Tags are present in
14204 * the inner packet headers of tunneled packets or
14205 * non-tunneled packets.
14207 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14209 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14212 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14213 * present in the inner packet headers
14215 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14216 (UINT32_C(0x0) << 1)
14218 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14219 * present in the inner packet headers.
14220 * No VLAN PRI is selected for this configuration
14221 * if only one VLAN Tag is present in the inner
14224 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14225 (UINT32_C(0x1) << 1)
14227 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14228 * are present in the inner packet headers
14230 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14231 (UINT32_C(0x2) << 1)
14233 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14234 (UINT32_C(0x3) << 1)
14235 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14236 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14238 * This field is used for selecting tunnel VLAN PRI value
14239 * based on whether one or two VLAN Tags are present in
14240 * the tunnel headers of tunneled packets. This selection
14241 * does not apply to non-tunneled packets.
14243 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14245 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14248 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14249 * present in the tunnel packet headers
14251 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14252 (UINT32_C(0x0) << 3)
14254 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14255 * present in the tunnel packet headers.
14256 * No VLAN PRI is selected for this configuration
14257 * if only one VLAN Tag is present in the tunnel
14260 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14261 (UINT32_C(0x1) << 3)
14263 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14264 * are present in the tunnel packet headers
14266 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14267 (UINT32_C(0x2) << 3)
14269 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14270 (UINT32_C(0x3) << 3)
14271 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14272 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14274 * This field is used to provide default CoS value that
14275 * has been configured on this port.
14277 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14279 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14282 * This field is used in Output records to indicate that the output
14283 * is completely written to RAM. This field should be read as '1'
14284 * to indicate that the output has been completely written.
14285 * When writing a command completion or response to an internal processor,
14286 * the order of writes has to be such that this field is written last.
14289 } __attribute__((packed));
14291 /**************************
14292 * hwrm_port_mac_ptp_qcfg *
14293 **************************/
14296 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
14297 struct hwrm_port_mac_ptp_qcfg_input {
14298 /* The HWRM command request type. */
14301 * The completion ring to send the completion event on. This should
14302 * be the NQ ID returned from the `nq_alloc` HWRM command.
14304 uint16_t cmpl_ring;
14306 * The sequence ID is used by the driver for tracking multiple
14307 * commands. This ID is treated as opaque data by the firmware and
14308 * the value is returned in the `hwrm_resp_hdr` upon completion.
14312 * The target ID of the command:
14313 * * 0x0-0xFFF8 - The function ID
14314 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14315 * * 0xFFFD - Reserved for user-space HWRM interface
14318 uint16_t target_id;
14320 * A physical address pointer pointing to a host buffer that the
14321 * command's response data will be written. This can be either a host
14322 * physical address (HPA) or a guest physical address (GPA) and must
14323 * point to a physically contiguous block of memory.
14325 uint64_t resp_addr;
14326 /* Port ID of port that is being queried. */
14328 uint8_t unused_0[6];
14329 } __attribute__((packed));
14331 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
14332 struct hwrm_port_mac_ptp_qcfg_output {
14333 /* The specific error status for the command. */
14334 uint16_t error_code;
14335 /* The HWRM command request type. */
14337 /* The sequence ID from the original command. */
14339 /* The length of the response data in number of bytes. */
14342 * In this field, a number of PTP related flags
14343 * are used to indicate configured PTP capabilities.
14347 * When this bit is set to '1', the PTP related registers are
14348 * directly accessible by the host.
14350 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
14353 * When this bit is set to '1', the PTP information is accessible
14354 * via HWRM commands.
14356 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
14359 * When this bit is set to '1', the device supports one-step
14362 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
14364 uint8_t unused_0[3];
14365 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
14366 uint32_t rx_ts_reg_off_lower;
14367 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
14368 uint32_t rx_ts_reg_off_upper;
14369 /* Offset of the PTP register for the sequence ID for RX. */
14370 uint32_t rx_ts_reg_off_seq_id;
14371 /* Offset of the first PTP source ID for RX. */
14372 uint32_t rx_ts_reg_off_src_id_0;
14373 /* Offset of the second PTP source ID for RX. */
14374 uint32_t rx_ts_reg_off_src_id_1;
14375 /* Offset of the third PTP source ID for RX. */
14376 uint32_t rx_ts_reg_off_src_id_2;
14377 /* Offset of the domain ID for RX. */
14378 uint32_t rx_ts_reg_off_domain_id;
14379 /* Offset of the PTP FIFO register for RX. */
14380 uint32_t rx_ts_reg_off_fifo;
14381 /* Offset of the PTP advance FIFO register for RX. */
14382 uint32_t rx_ts_reg_off_fifo_adv;
14383 /* PTP timestamp granularity for RX. */
14384 uint32_t rx_ts_reg_off_granularity;
14385 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
14386 uint32_t tx_ts_reg_off_lower;
14387 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
14388 uint32_t tx_ts_reg_off_upper;
14389 /* Offset of the PTP register for the sequence ID for TX. */
14390 uint32_t tx_ts_reg_off_seq_id;
14391 /* Offset of the PTP FIFO register for TX. */
14392 uint32_t tx_ts_reg_off_fifo;
14393 /* PTP timestamp granularity for TX. */
14394 uint32_t tx_ts_reg_off_granularity;
14395 uint8_t unused_1[7];
14397 * This field is used in Output records to indicate that the output
14398 * is completely written to RAM. This field should be read as '1'
14399 * to indicate that the output has been completely written.
14400 * When writing a command completion or response to an internal processor,
14401 * the order of writes has to be such that this field is written last.
14404 } __attribute__((packed));
14406 /* Port Tx Statistics Formats */
14407 /* tx_port_stats (size:3264b/408B) */
14408 struct tx_port_stats {
14409 /* Total Number of 64 Bytes frames transmitted */
14410 uint64_t tx_64b_frames;
14411 /* Total Number of 65-127 Bytes frames transmitted */
14412 uint64_t tx_65b_127b_frames;
14413 /* Total Number of 128-255 Bytes frames transmitted */
14414 uint64_t tx_128b_255b_frames;
14415 /* Total Number of 256-511 Bytes frames transmitted */
14416 uint64_t tx_256b_511b_frames;
14417 /* Total Number of 512-1023 Bytes frames transmitted */
14418 uint64_t tx_512b_1023b_frames;
14419 /* Total Number of 1024-1518 Bytes frames transmitted */
14420 uint64_t tx_1024b_1518b_frames;
14422 * Total Number of each good VLAN (exludes FCS errors)
14423 * frame transmitted which is 1519 to 1522 bytes in length
14424 * inclusive (excluding framing bits but including FCS bytes).
14426 uint64_t tx_good_vlan_frames;
14427 /* Total Number of 1519-2047 Bytes frames transmitted */
14428 uint64_t tx_1519b_2047b_frames;
14429 /* Total Number of 2048-4095 Bytes frames transmitted */
14430 uint64_t tx_2048b_4095b_frames;
14431 /* Total Number of 4096-9216 Bytes frames transmitted */
14432 uint64_t tx_4096b_9216b_frames;
14433 /* Total Number of 9217-16383 Bytes frames transmitted */
14434 uint64_t tx_9217b_16383b_frames;
14435 /* Total Number of good frames transmitted */
14436 uint64_t tx_good_frames;
14437 /* Total Number of frames transmitted */
14438 uint64_t tx_total_frames;
14439 /* Total number of unicast frames transmitted */
14440 uint64_t tx_ucast_frames;
14441 /* Total number of multicast frames transmitted */
14442 uint64_t tx_mcast_frames;
14443 /* Total number of broadcast frames transmitted */
14444 uint64_t tx_bcast_frames;
14445 /* Total number of PAUSE control frames transmitted */
14446 uint64_t tx_pause_frames;
14448 * Total number of PFC/per-priority PAUSE
14449 * control frames transmitted
14451 uint64_t tx_pfc_frames;
14452 /* Total number of jabber frames transmitted */
14453 uint64_t tx_jabber_frames;
14454 /* Total number of frames transmitted with FCS error */
14455 uint64_t tx_fcs_err_frames;
14456 /* Total number of control frames transmitted */
14457 uint64_t tx_control_frames;
14458 /* Total number of over-sized frames transmitted */
14459 uint64_t tx_oversz_frames;
14460 /* Total number of frames with single deferral */
14461 uint64_t tx_single_dfrl_frames;
14462 /* Total number of frames with multiple deferrals */
14463 uint64_t tx_multi_dfrl_frames;
14464 /* Total number of frames with single collision */
14465 uint64_t tx_single_coll_frames;
14466 /* Total number of frames with multiple collisions */
14467 uint64_t tx_multi_coll_frames;
14468 /* Total number of frames with late collisions */
14469 uint64_t tx_late_coll_frames;
14470 /* Total number of frames with excessive collisions */
14471 uint64_t tx_excessive_coll_frames;
14472 /* Total number of fragmented frames transmitted */
14473 uint64_t tx_frag_frames;
14474 /* Total number of transmit errors */
14476 /* Total number of single VLAN tagged frames transmitted */
14477 uint64_t tx_tagged_frames;
14478 /* Total number of double VLAN tagged frames transmitted */
14479 uint64_t tx_dbl_tagged_frames;
14480 /* Total number of runt frames transmitted */
14481 uint64_t tx_runt_frames;
14482 /* Total number of TX FIFO under runs */
14483 uint64_t tx_fifo_underruns;
14485 * Total number of PFC frames with PFC enabled bit for
14486 * Pri 0 transmitted
14488 uint64_t tx_pfc_ena_frames_pri0;
14490 * Total number of PFC frames with PFC enabled bit for
14491 * Pri 1 transmitted
14493 uint64_t tx_pfc_ena_frames_pri1;
14495 * Total number of PFC frames with PFC enabled bit for
14496 * Pri 2 transmitted
14498 uint64_t tx_pfc_ena_frames_pri2;
14500 * Total number of PFC frames with PFC enabled bit for
14501 * Pri 3 transmitted
14503 uint64_t tx_pfc_ena_frames_pri3;
14505 * Total number of PFC frames with PFC enabled bit for
14506 * Pri 4 transmitted
14508 uint64_t tx_pfc_ena_frames_pri4;
14510 * Total number of PFC frames with PFC enabled bit for
14511 * Pri 5 transmitted
14513 uint64_t tx_pfc_ena_frames_pri5;
14515 * Total number of PFC frames with PFC enabled bit for
14516 * Pri 6 transmitted
14518 uint64_t tx_pfc_ena_frames_pri6;
14520 * Total number of PFC frames with PFC enabled bit for
14521 * Pri 7 transmitted
14523 uint64_t tx_pfc_ena_frames_pri7;
14524 /* Total number of EEE LPI Events on TX */
14525 uint64_t tx_eee_lpi_events;
14526 /* EEE LPI Duration Counter on TX */
14527 uint64_t tx_eee_lpi_duration;
14529 * Total number of Link Level Flow Control (LLFC) messages
14532 uint64_t tx_llfc_logical_msgs;
14533 /* Total number of HCFC messages transmitted */
14534 uint64_t tx_hcfc_msgs;
14535 /* Total number of TX collisions */
14536 uint64_t tx_total_collisions;
14537 /* Total number of transmitted bytes */
14539 /* Total number of end-to-end HOL frames */
14540 uint64_t tx_xthol_frames;
14541 /* Total Tx Drops per Port reported by STATS block */
14542 uint64_t tx_stat_discard;
14543 /* Total Tx Error Drops per Port reported by STATS block */
14544 uint64_t tx_stat_error;
14545 } __attribute__((packed));
14547 /* Port Rx Statistics Formats */
14548 /* rx_port_stats (size:4224b/528B) */
14549 struct rx_port_stats {
14550 /* Total Number of 64 Bytes frames received */
14551 uint64_t rx_64b_frames;
14552 /* Total Number of 65-127 Bytes frames received */
14553 uint64_t rx_65b_127b_frames;
14554 /* Total Number of 128-255 Bytes frames received */
14555 uint64_t rx_128b_255b_frames;
14556 /* Total Number of 256-511 Bytes frames received */
14557 uint64_t rx_256b_511b_frames;
14558 /* Total Number of 512-1023 Bytes frames received */
14559 uint64_t rx_512b_1023b_frames;
14560 /* Total Number of 1024-1518 Bytes frames received */
14561 uint64_t rx_1024b_1518b_frames;
14563 * Total Number of each good VLAN (exludes FCS errors)
14564 * frame received which is 1519 to 1522 bytes in length
14565 * inclusive (excluding framing bits but including FCS bytes).
14567 uint64_t rx_good_vlan_frames;
14568 /* Total Number of 1519-2047 Bytes frames received */
14569 uint64_t rx_1519b_2047b_frames;
14570 /* Total Number of 2048-4095 Bytes frames received */
14571 uint64_t rx_2048b_4095b_frames;
14572 /* Total Number of 4096-9216 Bytes frames received */
14573 uint64_t rx_4096b_9216b_frames;
14574 /* Total Number of 9217-16383 Bytes frames received */
14575 uint64_t rx_9217b_16383b_frames;
14576 /* Total number of frames received */
14577 uint64_t rx_total_frames;
14578 /* Total number of unicast frames received */
14579 uint64_t rx_ucast_frames;
14580 /* Total number of multicast frames received */
14581 uint64_t rx_mcast_frames;
14582 /* Total number of broadcast frames received */
14583 uint64_t rx_bcast_frames;
14584 /* Total number of received frames with FCS error */
14585 uint64_t rx_fcs_err_frames;
14586 /* Total number of control frames received */
14587 uint64_t rx_ctrl_frames;
14588 /* Total number of PAUSE frames received */
14589 uint64_t rx_pause_frames;
14590 /* Total number of PFC frames received */
14591 uint64_t rx_pfc_frames;
14593 * Total number of frames received with an unsupported
14596 uint64_t rx_unsupported_opcode_frames;
14598 * Total number of frames received with an unsupported
14599 * DA for pause and PFC
14601 uint64_t rx_unsupported_da_pausepfc_frames;
14602 /* Total number of frames received with an unsupported SA */
14603 uint64_t rx_wrong_sa_frames;
14604 /* Total number of received packets with alignment error */
14605 uint64_t rx_align_err_frames;
14606 /* Total number of received frames with out-of-range length */
14607 uint64_t rx_oor_len_frames;
14608 /* Total number of received frames with error termination */
14609 uint64_t rx_code_err_frames;
14611 * Total number of received frames with a false carrier is
14612 * detected during idle, as defined by RX_ER samples active
14613 * and RXD is 0xE. The event is reported along with the
14614 * statistics generated on the next received frame. Only
14615 * one false carrier condition can be detected and logged
14618 * Carrier event, valid for 10M/100M speed modes only.
14620 uint64_t rx_false_carrier_frames;
14621 /* Total number of over-sized frames received */
14622 uint64_t rx_ovrsz_frames;
14623 /* Total number of jabber packets received */
14624 uint64_t rx_jbr_frames;
14625 /* Total number of received frames with MTU error */
14626 uint64_t rx_mtu_err_frames;
14627 /* Total number of received frames with CRC match */
14628 uint64_t rx_match_crc_frames;
14629 /* Total number of frames received promiscuously */
14630 uint64_t rx_promiscuous_frames;
14632 * Total number of received frames with one or two VLAN
14635 uint64_t rx_tagged_frames;
14636 /* Total number of received frames with two VLAN tags */
14637 uint64_t rx_double_tagged_frames;
14638 /* Total number of truncated frames received */
14639 uint64_t rx_trunc_frames;
14640 /* Total number of good frames (without errors) received */
14641 uint64_t rx_good_frames;
14643 * Total number of received PFC frames with transition from
14644 * XON to XOFF on Pri 0
14646 uint64_t rx_pfc_xon2xoff_frames_pri0;
14648 * Total number of received PFC frames with transition from
14649 * XON to XOFF on Pri 1
14651 uint64_t rx_pfc_xon2xoff_frames_pri1;
14653 * Total number of received PFC frames with transition from
14654 * XON to XOFF on Pri 2
14656 uint64_t rx_pfc_xon2xoff_frames_pri2;
14658 * Total number of received PFC frames with transition from
14659 * XON to XOFF on Pri 3
14661 uint64_t rx_pfc_xon2xoff_frames_pri3;
14663 * Total number of received PFC frames with transition from
14664 * XON to XOFF on Pri 4
14666 uint64_t rx_pfc_xon2xoff_frames_pri4;
14668 * Total number of received PFC frames with transition from
14669 * XON to XOFF on Pri 5
14671 uint64_t rx_pfc_xon2xoff_frames_pri5;
14673 * Total number of received PFC frames with transition from
14674 * XON to XOFF on Pri 6
14676 uint64_t rx_pfc_xon2xoff_frames_pri6;
14678 * Total number of received PFC frames with transition from
14679 * XON to XOFF on Pri 7
14681 uint64_t rx_pfc_xon2xoff_frames_pri7;
14683 * Total number of received PFC frames with PFC enabled
14686 uint64_t rx_pfc_ena_frames_pri0;
14688 * Total number of received PFC frames with PFC enabled
14691 uint64_t rx_pfc_ena_frames_pri1;
14693 * Total number of received PFC frames with PFC enabled
14696 uint64_t rx_pfc_ena_frames_pri2;
14698 * Total number of received PFC frames with PFC enabled
14701 uint64_t rx_pfc_ena_frames_pri3;
14703 * Total number of received PFC frames with PFC enabled
14706 uint64_t rx_pfc_ena_frames_pri4;
14708 * Total number of received PFC frames with PFC enabled
14711 uint64_t rx_pfc_ena_frames_pri5;
14713 * Total number of received PFC frames with PFC enabled
14716 uint64_t rx_pfc_ena_frames_pri6;
14718 * Total number of received PFC frames with PFC enabled
14721 uint64_t rx_pfc_ena_frames_pri7;
14722 /* Total Number of frames received with SCH CRC error */
14723 uint64_t rx_sch_crc_err_frames;
14724 /* Total Number of under-sized frames received */
14725 uint64_t rx_undrsz_frames;
14726 /* Total Number of fragmented frames received */
14727 uint64_t rx_frag_frames;
14728 /* Total number of RX EEE LPI Events */
14729 uint64_t rx_eee_lpi_events;
14730 /* EEE LPI Duration Counter on RX */
14731 uint64_t rx_eee_lpi_duration;
14733 * Total number of physical type Link Level Flow Control
14734 * (LLFC) messages received
14736 uint64_t rx_llfc_physical_msgs;
14738 * Total number of logical type Link Level Flow Control
14739 * (LLFC) messages received
14741 uint64_t rx_llfc_logical_msgs;
14743 * Total number of logical type Link Level Flow Control
14744 * (LLFC) messages received with CRC error
14746 uint64_t rx_llfc_msgs_with_crc_err;
14747 /* Total number of HCFC messages received */
14748 uint64_t rx_hcfc_msgs;
14749 /* Total number of HCFC messages received with CRC error */
14750 uint64_t rx_hcfc_msgs_with_crc_err;
14751 /* Total number of received bytes */
14753 /* Total number of bytes received in runt frames */
14754 uint64_t rx_runt_bytes;
14755 /* Total number of runt frames received */
14756 uint64_t rx_runt_frames;
14757 /* Total Rx Discards per Port reported by STATS block */
14758 uint64_t rx_stat_discard;
14759 uint64_t rx_stat_err;
14760 } __attribute__((packed));
14762 /********************
14763 * hwrm_port_qstats *
14764 ********************/
14767 /* hwrm_port_qstats_input (size:320b/40B) */
14768 struct hwrm_port_qstats_input {
14769 /* The HWRM command request type. */
14772 * The completion ring to send the completion event on. This should
14773 * be the NQ ID returned from the `nq_alloc` HWRM command.
14775 uint16_t cmpl_ring;
14777 * The sequence ID is used by the driver for tracking multiple
14778 * commands. This ID is treated as opaque data by the firmware and
14779 * the value is returned in the `hwrm_resp_hdr` upon completion.
14783 * The target ID of the command:
14784 * * 0x0-0xFFF8 - The function ID
14785 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14786 * * 0xFFFD - Reserved for user-space HWRM interface
14789 uint16_t target_id;
14791 * A physical address pointer pointing to a host buffer that the
14792 * command's response data will be written. This can be either a host
14793 * physical address (HPA) or a guest physical address (GPA) and must
14794 * point to a physically contiguous block of memory.
14796 uint64_t resp_addr;
14797 /* Port ID of port that is being queried. */
14799 uint8_t unused_0[6];
14801 * This is the host address where
14802 * Tx port statistics will be stored
14804 uint64_t tx_stat_host_addr;
14806 * This is the host address where
14807 * Rx port statistics will be stored
14809 uint64_t rx_stat_host_addr;
14810 } __attribute__((packed));
14812 /* hwrm_port_qstats_output (size:128b/16B) */
14813 struct hwrm_port_qstats_output {
14814 /* The specific error status for the command. */
14815 uint16_t error_code;
14816 /* The HWRM command request type. */
14818 /* The sequence ID from the original command. */
14820 /* The length of the response data in number of bytes. */
14822 /* The size of TX port statistics block in bytes. */
14823 uint16_t tx_stat_size;
14824 /* The size of RX port statistics block in bytes. */
14825 uint16_t rx_stat_size;
14826 uint8_t unused_0[3];
14828 * This field is used in Output records to indicate that the output
14829 * is completely written to RAM. This field should be read as '1'
14830 * to indicate that the output has been completely written.
14831 * When writing a command completion or response to an internal processor,
14832 * the order of writes has to be such that this field is written last.
14835 } __attribute__((packed));
14837 /* Port Tx Statistics extended Formats */
14838 /* tx_port_stats_ext (size:2048b/256B) */
14839 struct tx_port_stats_ext {
14840 /* Total number of tx bytes count on cos queue 0 */
14841 uint64_t tx_bytes_cos0;
14842 /* Total number of tx bytes count on cos queue 1 */
14843 uint64_t tx_bytes_cos1;
14844 /* Total number of tx bytes count on cos queue 2 */
14845 uint64_t tx_bytes_cos2;
14846 /* Total number of tx bytes count on cos queue 3 */
14847 uint64_t tx_bytes_cos3;
14848 /* Total number of tx bytes count on cos queue 4 */
14849 uint64_t tx_bytes_cos4;
14850 /* Total number of tx bytes count on cos queue 5 */
14851 uint64_t tx_bytes_cos5;
14852 /* Total number of tx bytes count on cos queue 6 */
14853 uint64_t tx_bytes_cos6;
14854 /* Total number of tx bytes count on cos queue 7 */
14855 uint64_t tx_bytes_cos7;
14856 /* Total number of tx packets count on cos queue 0 */
14857 uint64_t tx_packets_cos0;
14858 /* Total number of tx packets count on cos queue 1 */
14859 uint64_t tx_packets_cos1;
14860 /* Total number of tx packets count on cos queue 2 */
14861 uint64_t tx_packets_cos2;
14862 /* Total number of tx packets count on cos queue 3 */
14863 uint64_t tx_packets_cos3;
14864 /* Total number of tx packets count on cos queue 4 */
14865 uint64_t tx_packets_cos4;
14866 /* Total number of tx packets count on cos queue 5 */
14867 uint64_t tx_packets_cos5;
14868 /* Total number of tx packets count on cos queue 6 */
14869 uint64_t tx_packets_cos6;
14870 /* Total number of tx packets count on cos queue 7 */
14871 uint64_t tx_packets_cos7;
14872 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
14873 uint64_t pfc_pri0_tx_duration_us;
14874 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
14875 uint64_t pfc_pri0_tx_transitions;
14876 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
14877 uint64_t pfc_pri1_tx_duration_us;
14878 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
14879 uint64_t pfc_pri1_tx_transitions;
14880 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
14881 uint64_t pfc_pri2_tx_duration_us;
14882 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
14883 uint64_t pfc_pri2_tx_transitions;
14884 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
14885 uint64_t pfc_pri3_tx_duration_us;
14886 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
14887 uint64_t pfc_pri3_tx_transitions;
14888 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
14889 uint64_t pfc_pri4_tx_duration_us;
14890 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
14891 uint64_t pfc_pri4_tx_transitions;
14892 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
14893 uint64_t pfc_pri5_tx_duration_us;
14894 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
14895 uint64_t pfc_pri5_tx_transitions;
14896 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
14897 uint64_t pfc_pri6_tx_duration_us;
14898 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
14899 uint64_t pfc_pri6_tx_transitions;
14900 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
14901 uint64_t pfc_pri7_tx_duration_us;
14902 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
14903 uint64_t pfc_pri7_tx_transitions;
14904 } __attribute__((packed));
14906 /* Port Rx Statistics extended Formats */
14907 /* rx_port_stats_ext (size:3648b/456B) */
14908 struct rx_port_stats_ext {
14909 /* Number of times link state changed to down */
14910 uint64_t link_down_events;
14911 /* Number of times the idle rings with pause bit are found */
14912 uint64_t continuous_pause_events;
14913 /* Number of times the active rings pause bit resumed back */
14914 uint64_t resume_pause_events;
14915 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
14916 uint64_t continuous_roce_pause_events;
14917 /* Number of times, the ROCE cos queue PFC is enabled back */
14918 uint64_t resume_roce_pause_events;
14919 /* Total number of rx bytes count on cos queue 0 */
14920 uint64_t rx_bytes_cos0;
14921 /* Total number of rx bytes count on cos queue 1 */
14922 uint64_t rx_bytes_cos1;
14923 /* Total number of rx bytes count on cos queue 2 */
14924 uint64_t rx_bytes_cos2;
14925 /* Total number of rx bytes count on cos queue 3 */
14926 uint64_t rx_bytes_cos3;
14927 /* Total number of rx bytes count on cos queue 4 */
14928 uint64_t rx_bytes_cos4;
14929 /* Total number of rx bytes count on cos queue 5 */
14930 uint64_t rx_bytes_cos5;
14931 /* Total number of rx bytes count on cos queue 6 */
14932 uint64_t rx_bytes_cos6;
14933 /* Total number of rx bytes count on cos queue 7 */
14934 uint64_t rx_bytes_cos7;
14935 /* Total number of rx packets count on cos queue 0 */
14936 uint64_t rx_packets_cos0;
14937 /* Total number of rx packets count on cos queue 1 */
14938 uint64_t rx_packets_cos1;
14939 /* Total number of rx packets count on cos queue 2 */
14940 uint64_t rx_packets_cos2;
14941 /* Total number of rx packets count on cos queue 3 */
14942 uint64_t rx_packets_cos3;
14943 /* Total number of rx packets count on cos queue 4 */
14944 uint64_t rx_packets_cos4;
14945 /* Total number of rx packets count on cos queue 5 */
14946 uint64_t rx_packets_cos5;
14947 /* Total number of rx packets count on cos queue 6 */
14948 uint64_t rx_packets_cos6;
14949 /* Total number of rx packets count on cos queue 7 */
14950 uint64_t rx_packets_cos7;
14951 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
14952 uint64_t pfc_pri0_rx_duration_us;
14953 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
14954 uint64_t pfc_pri0_rx_transitions;
14955 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
14956 uint64_t pfc_pri1_rx_duration_us;
14957 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
14958 uint64_t pfc_pri1_rx_transitions;
14959 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
14960 uint64_t pfc_pri2_rx_duration_us;
14961 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
14962 uint64_t pfc_pri2_rx_transitions;
14963 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
14964 uint64_t pfc_pri3_rx_duration_us;
14965 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
14966 uint64_t pfc_pri3_rx_transitions;
14967 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
14968 uint64_t pfc_pri4_rx_duration_us;
14969 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
14970 uint64_t pfc_pri4_rx_transitions;
14971 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
14972 uint64_t pfc_pri5_rx_duration_us;
14973 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
14974 uint64_t pfc_pri5_rx_transitions;
14975 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
14976 uint64_t pfc_pri6_rx_duration_us;
14977 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
14978 uint64_t pfc_pri6_rx_transitions;
14979 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
14980 uint64_t pfc_pri7_rx_duration_us;
14981 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
14982 uint64_t pfc_pri7_rx_transitions;
14983 /* Total number of received bits */
14985 /* The number of events where the port receive buffer was over 85% full */
14986 uint64_t rx_buffer_passed_threshold;
14988 * The number of symbol errors that wasn't corrected by FEC correction
14991 uint64_t rx_pcs_symbol_err;
14992 /* The number of corrected bits on the port according to active FEC */
14993 uint64_t rx_corrected_bits;
14994 /* Total number of rx discard bytes count on cos queue 0 */
14995 uint64_t rx_discard_bytes_cos0;
14996 /* Total number of rx discard bytes count on cos queue 1 */
14997 uint64_t rx_discard_bytes_cos1;
14998 /* Total number of rx discard bytes count on cos queue 2 */
14999 uint64_t rx_discard_bytes_cos2;
15000 /* Total number of rx discard bytes count on cos queue 3 */
15001 uint64_t rx_discard_bytes_cos3;
15002 /* Total number of rx discard bytes count on cos queue 4 */
15003 uint64_t rx_discard_bytes_cos4;
15004 /* Total number of rx discard bytes count on cos queue 5 */
15005 uint64_t rx_discard_bytes_cos5;
15006 /* Total number of rx discard bytes count on cos queue 6 */
15007 uint64_t rx_discard_bytes_cos6;
15008 /* Total number of rx discard bytes count on cos queue 7 */
15009 uint64_t rx_discard_bytes_cos7;
15010 /* Total number of rx discard packets count on cos queue 0 */
15011 uint64_t rx_discard_packets_cos0;
15012 /* Total number of rx discard packets count on cos queue 1 */
15013 uint64_t rx_discard_packets_cos1;
15014 /* Total number of rx discard packets count on cos queue 2 */
15015 uint64_t rx_discard_packets_cos2;
15016 /* Total number of rx discard packets count on cos queue 3 */
15017 uint64_t rx_discard_packets_cos3;
15018 /* Total number of rx discard packets count on cos queue 4 */
15019 uint64_t rx_discard_packets_cos4;
15020 /* Total number of rx discard packets count on cos queue 5 */
15021 uint64_t rx_discard_packets_cos5;
15022 /* Total number of rx discard packets count on cos queue 6 */
15023 uint64_t rx_discard_packets_cos6;
15024 /* Total number of rx discard packets count on cos queue 7 */
15025 uint64_t rx_discard_packets_cos7;
15026 } __attribute__((packed));
15028 /************************
15029 * hwrm_port_qstats_ext *
15030 ************************/
15033 /* hwrm_port_qstats_ext_input (size:320b/40B) */
15034 struct hwrm_port_qstats_ext_input {
15035 /* The HWRM command request type. */
15038 * The completion ring to send the completion event on. This should
15039 * be the NQ ID returned from the `nq_alloc` HWRM command.
15041 uint16_t cmpl_ring;
15043 * The sequence ID is used by the driver for tracking multiple
15044 * commands. This ID is treated as opaque data by the firmware and
15045 * the value is returned in the `hwrm_resp_hdr` upon completion.
15049 * The target ID of the command:
15050 * * 0x0-0xFFF8 - The function ID
15051 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15052 * * 0xFFFD - Reserved for user-space HWRM interface
15055 uint16_t target_id;
15057 * A physical address pointer pointing to a host buffer that the
15058 * command's response data will be written. This can be either a host
15059 * physical address (HPA) or a guest physical address (GPA) and must
15060 * point to a physically contiguous block of memory.
15062 uint64_t resp_addr;
15063 /* Port ID of port that is being queried. */
15066 * The size of TX port extended
15067 * statistics block in bytes.
15069 uint16_t tx_stat_size;
15071 * The size of RX port extended
15072 * statistics block in bytes
15074 uint16_t rx_stat_size;
15075 uint8_t unused_0[2];
15077 * This is the host address where
15078 * Tx port statistics will be stored
15080 uint64_t tx_stat_host_addr;
15082 * This is the host address where
15083 * Rx port statistics will be stored
15085 uint64_t rx_stat_host_addr;
15086 } __attribute__((packed));
15088 /* hwrm_port_qstats_ext_output (size:128b/16B) */
15089 struct hwrm_port_qstats_ext_output {
15090 /* The specific error status for the command. */
15091 uint16_t error_code;
15092 /* The HWRM command request type. */
15094 /* The sequence ID from the original command. */
15096 /* The length of the response data in number of bytes. */
15098 /* The size of TX port statistics block in bytes. */
15099 uint16_t tx_stat_size;
15100 /* The size of RX port statistics block in bytes. */
15101 uint16_t rx_stat_size;
15102 /* Total number of active cos queues available. */
15103 uint16_t total_active_cos_queues;
15106 * If set to 1, then this field indicates that clear
15107 * roce specific counters is supported.
15109 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
15112 * This field is used in Output records to indicate that the output
15113 * is completely written to RAM. This field should be read as '1'
15114 * to indicate that the output has been completely written.
15115 * When writing a command completion or response to an internal processor,
15116 * the order of writes has to be such that this field is written last.
15119 } __attribute__((packed));
15121 /*************************
15122 * hwrm_port_lpbk_qstats *
15123 *************************/
15126 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
15127 struct hwrm_port_lpbk_qstats_input {
15128 /* The HWRM command request type. */
15131 * The completion ring to send the completion event on. This should
15132 * be the NQ ID returned from the `nq_alloc` HWRM command.
15134 uint16_t cmpl_ring;
15136 * The sequence ID is used by the driver for tracking multiple
15137 * commands. This ID is treated as opaque data by the firmware and
15138 * the value is returned in the `hwrm_resp_hdr` upon completion.
15142 * The target ID of the command:
15143 * * 0x0-0xFFF8 - The function ID
15144 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15145 * * 0xFFFD - Reserved for user-space HWRM interface
15148 uint16_t target_id;
15150 * A physical address pointer pointing to a host buffer that the
15151 * command's response data will be written. This can be either a host
15152 * physical address (HPA) or a guest physical address (GPA) and must
15153 * point to a physically contiguous block of memory.
15155 uint64_t resp_addr;
15156 } __attribute__((packed));
15158 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
15159 struct hwrm_port_lpbk_qstats_output {
15160 /* The specific error status for the command. */
15161 uint16_t error_code;
15162 /* The HWRM command request type. */
15164 /* The sequence ID from the original command. */
15166 /* The length of the response data in number of bytes. */
15168 /* Number of transmitted unicast frames */
15169 uint64_t lpbk_ucast_frames;
15170 /* Number of transmitted multicast frames */
15171 uint64_t lpbk_mcast_frames;
15172 /* Number of transmitted broadcast frames */
15173 uint64_t lpbk_bcast_frames;
15174 /* Number of transmitted bytes for unicast traffic */
15175 uint64_t lpbk_ucast_bytes;
15176 /* Number of transmitted bytes for multicast traffic */
15177 uint64_t lpbk_mcast_bytes;
15178 /* Number of transmitted bytes for broadcast traffic */
15179 uint64_t lpbk_bcast_bytes;
15180 /* Total Tx Drops for loopback traffic reported by STATS block */
15181 uint64_t tx_stat_discard;
15182 /* Total Tx Error Drops for loopback traffic reported by STATS block */
15183 uint64_t tx_stat_error;
15184 /* Total Rx Drops for loopback traffic reported by STATS block */
15185 uint64_t rx_stat_discard;
15186 /* Total Rx Error Drops for loopback traffic reported by STATS block */
15187 uint64_t rx_stat_error;
15188 uint8_t unused_0[7];
15190 * This field is used in Output records to indicate that the output
15191 * is completely written to RAM. This field should be read as '1'
15192 * to indicate that the output has been completely written.
15193 * When writing a command completion or response to an internal processor,
15194 * the order of writes has to be such that this field is written last.
15197 } __attribute__((packed));
15199 /***********************
15200 * hwrm_port_clr_stats *
15201 ***********************/
15204 /* hwrm_port_clr_stats_input (size:192b/24B) */
15205 struct hwrm_port_clr_stats_input {
15206 /* The HWRM command request type. */
15209 * The completion ring to send the completion event on. This should
15210 * be the NQ ID returned from the `nq_alloc` HWRM command.
15212 uint16_t cmpl_ring;
15214 * The sequence ID is used by the driver for tracking multiple
15215 * commands. This ID is treated as opaque data by the firmware and
15216 * the value is returned in the `hwrm_resp_hdr` upon completion.
15220 * The target ID of the command:
15221 * * 0x0-0xFFF8 - The function ID
15222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15223 * * 0xFFFD - Reserved for user-space HWRM interface
15226 uint16_t target_id;
15228 * A physical address pointer pointing to a host buffer that the
15229 * command's response data will be written. This can be either a host
15230 * physical address (HPA) or a guest physical address (GPA) and must
15231 * point to a physically contiguous block of memory.
15233 uint64_t resp_addr;
15234 /* Port ID of port that is being queried. */
15238 * If set to 1, then this field indicates clear the following RoCE
15239 * specific counters.
15240 * RoCE associated TX/RX cos counters
15241 * CNP associated TX/RX cos counters
15242 * RoCE/CNP specific TX/RX flow counters
15243 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
15244 * This flag is honored only when RoCE is enabled on that port.
15246 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
15247 uint8_t unused_0[5];
15248 } __attribute__((packed));
15250 /* hwrm_port_clr_stats_output (size:128b/16B) */
15251 struct hwrm_port_clr_stats_output {
15252 /* The specific error status for the command. */
15253 uint16_t error_code;
15254 /* The HWRM command request type. */
15256 /* The sequence ID from the original command. */
15258 /* The length of the response data in number of bytes. */
15260 uint8_t unused_0[7];
15262 * This field is used in Output records to indicate that the output
15263 * is completely written to RAM. This field should be read as '1'
15264 * to indicate that the output has been completely written.
15265 * When writing a command completion or response to an internal processor,
15266 * the order of writes has to be such that this field is written last.
15269 } __attribute__((packed));
15271 /***********************
15272 * hwrm_port_phy_qcaps *
15273 ***********************/
15276 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
15277 struct hwrm_port_phy_qcaps_input {
15278 /* The HWRM command request type. */
15281 * The completion ring to send the completion event on. This should
15282 * be the NQ ID returned from the `nq_alloc` HWRM command.
15284 uint16_t cmpl_ring;
15286 * The sequence ID is used by the driver for tracking multiple
15287 * commands. This ID is treated as opaque data by the firmware and
15288 * the value is returned in the `hwrm_resp_hdr` upon completion.
15292 * The target ID of the command:
15293 * * 0x0-0xFFF8 - The function ID
15294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15295 * * 0xFFFD - Reserved for user-space HWRM interface
15298 uint16_t target_id;
15300 * A physical address pointer pointing to a host buffer that the
15301 * command's response data will be written. This can be either a host
15302 * physical address (HPA) or a guest physical address (GPA) and must
15303 * point to a physically contiguous block of memory.
15305 uint64_t resp_addr;
15306 /* Port ID of port that is being queried. */
15308 uint8_t unused_0[6];
15309 } __attribute__((packed));
15311 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
15312 struct hwrm_port_phy_qcaps_output {
15313 /* The specific error status for the command. */
15314 uint16_t error_code;
15315 /* The HWRM command request type. */
15317 /* The sequence ID from the original command. */
15319 /* The length of the response data in number of bytes. */
15321 /* PHY capability flags */
15324 * If set to 1, then this field indicates that the
15325 * link is capable of supporting EEE.
15327 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
15330 * If set to 1, then this field indicates that the
15331 * PHY is capable of supporting external loopback.
15333 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
15336 * Reserved field. The HWRM shall set this field to 0.
15337 * An HWRM client shall ignore this field.
15339 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
15341 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
15342 /* Number of front panel ports for this device. */
15344 /* Not supported or unknown */
15345 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
15346 /* single port device */
15347 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
15348 /* 2-port device */
15349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
15350 /* 3-port device */
15351 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
15352 /* 4-port device */
15353 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
15354 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
15355 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
15357 * This is a bit mask to indicate what speeds are supported
15358 * as forced speeds on this link.
15359 * For each speed that can be forced on this link, the
15360 * corresponding mask bit shall be set to '1'.
15362 uint16_t supported_speeds_force_mode;
15363 /* 100Mb link speed (Half-duplex) */
15364 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
15366 /* 100Mb link speed (Full-duplex) */
15367 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
15369 /* 1Gb link speed (Half-duplex) */
15370 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
15372 /* 1Gb link speed (Full-duplex) */
15373 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
15375 /* 2Gb link speed */
15376 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
15378 /* 25Gb link speed */
15379 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
15381 /* 10Gb link speed */
15382 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
15384 /* 20Gb link speed */
15385 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
15387 /* 25Gb link speed */
15388 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
15390 /* 40Gb link speed */
15391 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
15393 /* 50Gb link speed */
15394 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
15396 /* 100Gb link speed */
15397 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
15399 /* 10Mb link speed (Half-duplex) */
15400 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
15402 /* 10Mb link speed (Full-duplex) */
15403 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
15405 /* 200Gb link speed */
15406 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
15409 * This is a bit mask to indicate what speeds are supported
15410 * for autonegotiation on this link.
15411 * For each speed that can be autonegotiated on this link, the
15412 * corresponding mask bit shall be set to '1'.
15414 uint16_t supported_speeds_auto_mode;
15415 /* 100Mb link speed (Half-duplex) */
15416 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
15418 /* 100Mb link speed (Full-duplex) */
15419 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
15421 /* 1Gb link speed (Half-duplex) */
15422 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
15424 /* 1Gb link speed (Full-duplex) */
15425 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
15427 /* 2Gb link speed */
15428 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
15430 /* 25Gb link speed */
15431 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
15433 /* 10Gb link speed */
15434 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
15436 /* 20Gb link speed */
15437 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
15439 /* 25Gb link speed */
15440 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
15442 /* 40Gb link speed */
15443 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
15445 /* 50Gb link speed */
15446 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
15448 /* 100Gb link speed */
15449 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
15451 /* 10Mb link speed (Half-duplex) */
15452 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
15454 /* 10Mb link speed (Full-duplex) */
15455 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
15457 /* 200Gb link speed */
15458 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
15461 * This is a bit mask to indicate what speeds are supported
15462 * for EEE on this link.
15463 * For each speed that can be autonegotiated when EEE is enabled
15464 * on this link, the corresponding mask bit shall be set to '1'.
15465 * This field is only valid when the eee_suppotred is set to '1'.
15467 uint16_t supported_speeds_eee_mode;
15469 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
15471 /* 100Mb link speed (Full-duplex) */
15472 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
15475 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
15477 /* 1Gb link speed (Full-duplex) */
15478 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
15481 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
15484 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
15486 /* 10Gb link speed */
15487 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
15489 uint32_t tx_lpi_timer_low;
15491 * The lowest value of TX LPI timer that can be set on this link
15492 * when EEE is enabled. This value is in microseconds.
15493 * This field is valid only when_eee_supported is set to '1'.
15495 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
15497 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
15499 * Reserved field. The HWRM shall set this field to 0.
15500 * An HWRM client shall ignore this field.
15502 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
15503 UINT32_C(0xff000000)
15504 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
15505 uint32_t valid_tx_lpi_timer_high;
15507 * The highest value of TX LPI timer that can be set on this link
15508 * when EEE is enabled. This value is in microseconds.
15509 * This field is valid only when_eee_supported is set to '1'.
15511 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
15513 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
15515 * This field is used in Output records to indicate that the output
15516 * is completely written to RAM. This field should be read as '1'
15517 * to indicate that the output has been completely written.
15518 * When writing a command completion or response to an internal processor,
15519 * the order of writes has to be such that this field is written last.
15521 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
15522 UINT32_C(0xff000000)
15523 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
15524 } __attribute__((packed));
15526 /****************************
15527 * hwrm_port_phy_mdio_write *
15528 ****************************/
15531 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
15532 struct hwrm_port_phy_mdio_write_input {
15533 /* The HWRM command request type. */
15536 * The completion ring to send the completion event on. This should
15537 * be the NQ ID returned from the `nq_alloc` HWRM command.
15539 uint16_t cmpl_ring;
15541 * The sequence ID is used by the driver for tracking multiple
15542 * commands. This ID is treated as opaque data by the firmware and
15543 * the value is returned in the `hwrm_resp_hdr` upon completion.
15547 * The target ID of the command:
15548 * * 0x0-0xFFF8 - The function ID
15549 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15550 * * 0xFFFD - Reserved for user-space HWRM interface
15553 uint16_t target_id;
15555 * A physical address pointer pointing to a host buffer that the
15556 * command's response data will be written. This can be either a host
15557 * physical address (HPA) or a guest physical address (GPA) and must
15558 * point to a physically contiguous block of memory.
15560 uint64_t resp_addr;
15561 /* Reserved for future use. */
15562 uint32_t unused_0[2];
15563 /* Port ID of port. */
15565 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
15567 /* 8-bit device address. */
15569 /* 16-bit register address. */
15571 /* 16-bit register data. */
15574 * When this bit is set to 1 a Clause 45 mdio access is done.
15575 * when this bit is set to 0 a Clause 22 mdio access is done.
15579 uint8_t unused_1[7];
15580 } __attribute__((packed));
15582 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
15583 struct hwrm_port_phy_mdio_write_output {
15584 /* The specific error status for the command. */
15585 uint16_t error_code;
15586 /* The HWRM command request type. */
15588 /* The sequence ID from the original command. */
15590 /* The length of the response data in number of bytes. */
15592 uint8_t unused_0[7];
15594 * This field is used in Output records to indicate that the output
15595 * is completely written to RAM. This field should be read as '1'
15596 * to indicate that the output has been completely written.
15597 * When writing a command completion or response to an internal processor,
15598 * the order of writes has to be such that this field is written last.
15601 } __attribute__((packed));
15603 /***************************
15604 * hwrm_port_phy_mdio_read *
15605 ***************************/
15608 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
15609 struct hwrm_port_phy_mdio_read_input {
15610 /* The HWRM command request type. */
15613 * The completion ring to send the completion event on. This should
15614 * be the NQ ID returned from the `nq_alloc` HWRM command.
15616 uint16_t cmpl_ring;
15618 * The sequence ID is used by the driver for tracking multiple
15619 * commands. This ID is treated as opaque data by the firmware and
15620 * the value is returned in the `hwrm_resp_hdr` upon completion.
15624 * The target ID of the command:
15625 * * 0x0-0xFFF8 - The function ID
15626 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15627 * * 0xFFFD - Reserved for user-space HWRM interface
15630 uint16_t target_id;
15632 * A physical address pointer pointing to a host buffer that the
15633 * command's response data will be written. This can be either a host
15634 * physical address (HPA) or a guest physical address (GPA) and must
15635 * point to a physically contiguous block of memory.
15637 uint64_t resp_addr;
15638 /* Reserved for future use. */
15639 uint32_t unused_0[2];
15640 /* Port ID of port. */
15642 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
15644 /* 8-bit device address. */
15646 /* 16-bit register address. */
15649 * When this bit is set to 1 a Clause 45 mdio access is done.
15650 * when this bit is set to 0 a Clause 22 mdio access is done.
15655 } __attribute__((packed));
15657 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
15658 struct hwrm_port_phy_mdio_read_output {
15659 /* The specific error status for the command. */
15660 uint16_t error_code;
15661 /* The HWRM command request type. */
15663 /* The sequence ID from the original command. */
15665 /* The length of the response data in number of bytes. */
15667 /* 16-bit register data. */
15669 uint8_t unused_0[5];
15671 * This field is used in Output records to indicate that the output
15672 * is completely written to RAM. This field should be read as '1'
15673 * to indicate that the output has been completely written.
15674 * When writing a command completion or response to an internal processor,
15675 * the order of writes has to be such that this field is written last.
15678 } __attribute__((packed));
15680 /*********************
15681 * hwrm_port_led_cfg *
15682 *********************/
15685 /* hwrm_port_led_cfg_input (size:512b/64B) */
15686 struct hwrm_port_led_cfg_input {
15687 /* The HWRM command request type. */
15690 * The completion ring to send the completion event on. This should
15691 * be the NQ ID returned from the `nq_alloc` HWRM command.
15693 uint16_t cmpl_ring;
15695 * The sequence ID is used by the driver for tracking multiple
15696 * commands. This ID is treated as opaque data by the firmware and
15697 * the value is returned in the `hwrm_resp_hdr` upon completion.
15701 * The target ID of the command:
15702 * * 0x0-0xFFF8 - The function ID
15703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15704 * * 0xFFFD - Reserved for user-space HWRM interface
15707 uint16_t target_id;
15709 * A physical address pointer pointing to a host buffer that the
15710 * command's response data will be written. This can be either a host
15711 * physical address (HPA) or a guest physical address (GPA) and must
15712 * point to a physically contiguous block of memory.
15714 uint64_t resp_addr;
15717 * This bit must be '1' for the led0_id field to be
15720 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
15723 * This bit must be '1' for the led0_state field to be
15726 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
15729 * This bit must be '1' for the led0_color field to be
15732 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
15735 * This bit must be '1' for the led0_blink_on field to be
15738 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
15741 * This bit must be '1' for the led0_blink_off field to be
15744 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
15747 * This bit must be '1' for the led0_group_id field to be
15750 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
15753 * This bit must be '1' for the led1_id field to be
15756 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
15759 * This bit must be '1' for the led1_state field to be
15762 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
15765 * This bit must be '1' for the led1_color field to be
15768 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
15771 * This bit must be '1' for the led1_blink_on field to be
15774 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
15777 * This bit must be '1' for the led1_blink_off field to be
15780 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
15783 * This bit must be '1' for the led1_group_id field to be
15786 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
15789 * This bit must be '1' for the led2_id field to be
15792 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
15795 * This bit must be '1' for the led2_state field to be
15798 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
15801 * This bit must be '1' for the led2_color field to be
15804 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
15807 * This bit must be '1' for the led2_blink_on field to be
15810 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
15813 * This bit must be '1' for the led2_blink_off field to be
15816 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
15819 * This bit must be '1' for the led2_group_id field to be
15822 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
15825 * This bit must be '1' for the led3_id field to be
15828 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
15831 * This bit must be '1' for the led3_state field to be
15834 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
15837 * This bit must be '1' for the led3_color field to be
15840 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
15843 * This bit must be '1' for the led3_blink_on field to be
15846 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
15849 * This bit must be '1' for the led3_blink_off field to be
15852 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
15855 * This bit must be '1' for the led3_group_id field to be
15858 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
15860 /* Port ID of port whose LEDs are configured. */
15863 * The number of LEDs that are being configured.
15864 * Up to 4 LEDs can be configured with this command.
15867 /* Reserved field. */
15869 /* An identifier for the LED #0. */
15871 /* The requested state of the LED #0. */
15872 uint8_t led0_state;
15873 /* Default state of the LED */
15874 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
15876 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
15878 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
15880 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
15881 /* Blink Alternately */
15882 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
15883 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
15884 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
15885 /* The requested color of LED #0. */
15886 uint8_t led0_color;
15888 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
15890 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
15892 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
15893 /* Green or Amber */
15894 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
15895 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
15896 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
15899 * If the LED #0 state is "blink" or "blinkalt", then
15900 * this field represents the requested time in milliseconds
15901 * to keep LED on between cycles.
15903 uint16_t led0_blink_on;
15905 * If the LED #0 state is "blink" or "blinkalt", then
15906 * this field represents the requested time in milliseconds
15907 * to keep LED off between cycles.
15909 uint16_t led0_blink_off;
15911 * An identifier for the group of LEDs that LED #0 belongs
15913 * If set to 0, then the LED #0 shall not be grouped and
15914 * shall be treated as an individual resource.
15915 * For all other non-zero values of this field, LED #0 shall
15916 * be grouped together with the LEDs with the same group ID
15919 uint8_t led0_group_id;
15920 /* Reserved field. */
15922 /* An identifier for the LED #1. */
15924 /* The requested state of the LED #1. */
15925 uint8_t led1_state;
15926 /* Default state of the LED */
15927 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
15929 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
15931 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
15933 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
15934 /* Blink Alternately */
15935 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
15936 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
15937 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
15938 /* The requested color of LED #1. */
15939 uint8_t led1_color;
15941 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
15943 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
15945 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
15946 /* Green or Amber */
15947 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
15948 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
15949 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
15952 * If the LED #1 state is "blink" or "blinkalt", then
15953 * this field represents the requested time in milliseconds
15954 * to keep LED on between cycles.
15956 uint16_t led1_blink_on;
15958 * If the LED #1 state is "blink" or "blinkalt", then
15959 * this field represents the requested time in milliseconds
15960 * to keep LED off between cycles.
15962 uint16_t led1_blink_off;
15964 * An identifier for the group of LEDs that LED #1 belongs
15966 * If set to 0, then the LED #1 shall not be grouped and
15967 * shall be treated as an individual resource.
15968 * For all other non-zero values of this field, LED #1 shall
15969 * be grouped together with the LEDs with the same group ID
15972 uint8_t led1_group_id;
15973 /* Reserved field. */
15975 /* An identifier for the LED #2. */
15977 /* The requested state of the LED #2. */
15978 uint8_t led2_state;
15979 /* Default state of the LED */
15980 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
15982 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
15984 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
15986 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
15987 /* Blink Alternately */
15988 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
15989 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
15990 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
15991 /* The requested color of LED #2. */
15992 uint8_t led2_color;
15994 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
15996 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
15998 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
15999 /* Green or Amber */
16000 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16001 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
16002 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
16005 * If the LED #2 state is "blink" or "blinkalt", then
16006 * this field represents the requested time in milliseconds
16007 * to keep LED on between cycles.
16009 uint16_t led2_blink_on;
16011 * If the LED #2 state is "blink" or "blinkalt", then
16012 * this field represents the requested time in milliseconds
16013 * to keep LED off between cycles.
16015 uint16_t led2_blink_off;
16017 * An identifier for the group of LEDs that LED #2 belongs
16019 * If set to 0, then the LED #2 shall not be grouped and
16020 * shall be treated as an individual resource.
16021 * For all other non-zero values of this field, LED #2 shall
16022 * be grouped together with the LEDs with the same group ID
16025 uint8_t led2_group_id;
16026 /* Reserved field. */
16028 /* An identifier for the LED #3. */
16030 /* The requested state of the LED #3. */
16031 uint8_t led3_state;
16032 /* Default state of the LED */
16033 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16035 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
16037 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
16039 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
16040 /* Blink Alternately */
16041 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16042 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
16043 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
16044 /* The requested color of LED #3. */
16045 uint8_t led3_color;
16047 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16049 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16051 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16052 /* Green or Amber */
16053 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16054 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
16055 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
16058 * If the LED #3 state is "blink" or "blinkalt", then
16059 * this field represents the requested time in milliseconds
16060 * to keep LED on between cycles.
16062 uint16_t led3_blink_on;
16064 * If the LED #3 state is "blink" or "blinkalt", then
16065 * this field represents the requested time in milliseconds
16066 * to keep LED off between cycles.
16068 uint16_t led3_blink_off;
16070 * An identifier for the group of LEDs that LED #3 belongs
16072 * If set to 0, then the LED #3 shall not be grouped and
16073 * shall be treated as an individual resource.
16074 * For all other non-zero values of this field, LED #3 shall
16075 * be grouped together with the LEDs with the same group ID
16078 uint8_t led3_group_id;
16079 /* Reserved field. */
16081 } __attribute__((packed));
16083 /* hwrm_port_led_cfg_output (size:128b/16B) */
16084 struct hwrm_port_led_cfg_output {
16085 /* The specific error status for the command. */
16086 uint16_t error_code;
16087 /* The HWRM command request type. */
16089 /* The sequence ID from the original command. */
16091 /* The length of the response data in number of bytes. */
16093 uint8_t unused_0[7];
16095 * This field is used in Output records to indicate that the output
16096 * is completely written to RAM. This field should be read as '1'
16097 * to indicate that the output has been completely written.
16098 * When writing a command completion or response to an internal processor,
16099 * the order of writes has to be such that this field is written last.
16102 } __attribute__((packed));
16104 /**********************
16105 * hwrm_port_led_qcfg *
16106 **********************/
16109 /* hwrm_port_led_qcfg_input (size:192b/24B) */
16110 struct hwrm_port_led_qcfg_input {
16111 /* The HWRM command request type. */
16114 * The completion ring to send the completion event on. This should
16115 * be the NQ ID returned from the `nq_alloc` HWRM command.
16117 uint16_t cmpl_ring;
16119 * The sequence ID is used by the driver for tracking multiple
16120 * commands. This ID is treated as opaque data by the firmware and
16121 * the value is returned in the `hwrm_resp_hdr` upon completion.
16125 * The target ID of the command:
16126 * * 0x0-0xFFF8 - The function ID
16127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16128 * * 0xFFFD - Reserved for user-space HWRM interface
16131 uint16_t target_id;
16133 * A physical address pointer pointing to a host buffer that the
16134 * command's response data will be written. This can be either a host
16135 * physical address (HPA) or a guest physical address (GPA) and must
16136 * point to a physically contiguous block of memory.
16138 uint64_t resp_addr;
16139 /* Port ID of port whose LED configuration is being queried. */
16141 uint8_t unused_0[6];
16142 } __attribute__((packed));
16144 /* hwrm_port_led_qcfg_output (size:448b/56B) */
16145 struct hwrm_port_led_qcfg_output {
16146 /* The specific error status for the command. */
16147 uint16_t error_code;
16148 /* The HWRM command request type. */
16150 /* The sequence ID from the original command. */
16152 /* The length of the response data in number of bytes. */
16155 * The number of LEDs that are configured on this port.
16156 * Up to 4 LEDs can be returned in the response.
16159 /* An identifier for the LED #0. */
16161 /* The type of LED #0. */
16164 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
16166 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
16168 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
16169 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
16170 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
16171 /* The current state of the LED #0. */
16172 uint8_t led0_state;
16173 /* Default state of the LED */
16174 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16176 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
16178 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
16180 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
16181 /* Blink Alternately */
16182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
16183 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
16184 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
16185 /* The color of LED #0. */
16186 uint8_t led0_color;
16188 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
16190 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
16192 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
16193 /* Green or Amber */
16194 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
16195 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
16196 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
16199 * If the LED #0 state is "blink" or "blinkalt", then
16200 * this field represents the requested time in milliseconds
16201 * to keep LED on between cycles.
16203 uint16_t led0_blink_on;
16205 * If the LED #0 state is "blink" or "blinkalt", then
16206 * this field represents the requested time in milliseconds
16207 * to keep LED off between cycles.
16209 uint16_t led0_blink_off;
16211 * An identifier for the group of LEDs that LED #0 belongs
16213 * If set to 0, then the LED #0 is not grouped.
16214 * For all other non-zero values of this field, LED #0 is
16215 * grouped together with the LEDs with the same group ID
16218 uint8_t led0_group_id;
16219 /* An identifier for the LED #1. */
16221 /* The type of LED #1. */
16224 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
16226 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
16228 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
16229 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
16230 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
16231 /* The current state of the LED #1. */
16232 uint8_t led1_state;
16233 /* Default state of the LED */
16234 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
16236 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
16238 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
16240 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
16241 /* Blink Alternately */
16242 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16243 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
16244 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
16245 /* The color of LED #1. */
16246 uint8_t led1_color;
16248 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16250 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16252 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16253 /* Green or Amber */
16254 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16255 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
16256 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
16259 * If the LED #1 state is "blink" or "blinkalt", then
16260 * this field represents the requested time in milliseconds
16261 * to keep LED on between cycles.
16263 uint16_t led1_blink_on;
16265 * If the LED #1 state is "blink" or "blinkalt", then
16266 * this field represents the requested time in milliseconds
16267 * to keep LED off between cycles.
16269 uint16_t led1_blink_off;
16271 * An identifier for the group of LEDs that LED #1 belongs
16273 * If set to 0, then the LED #1 is not grouped.
16274 * For all other non-zero values of this field, LED #1 is
16275 * grouped together with the LEDs with the same group ID
16278 uint8_t led1_group_id;
16279 /* An identifier for the LED #2. */
16281 /* The type of LED #2. */
16284 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
16286 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
16288 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
16289 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
16290 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
16291 /* The current state of the LED #2. */
16292 uint8_t led2_state;
16293 /* Default state of the LED */
16294 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16296 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
16298 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
16300 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
16301 /* Blink Alternately */
16302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16303 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
16304 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
16305 /* The color of LED #2. */
16306 uint8_t led2_color;
16308 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16310 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16312 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16313 /* Green or Amber */
16314 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16315 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
16316 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
16319 * If the LED #2 state is "blink" or "blinkalt", then
16320 * this field represents the requested time in milliseconds
16321 * to keep LED on between cycles.
16323 uint16_t led2_blink_on;
16325 * If the LED #2 state is "blink" or "blinkalt", then
16326 * this field represents the requested time in milliseconds
16327 * to keep LED off between cycles.
16329 uint16_t led2_blink_off;
16331 * An identifier for the group of LEDs that LED #2 belongs
16333 * If set to 0, then the LED #2 is not grouped.
16334 * For all other non-zero values of this field, LED #2 is
16335 * grouped together with the LEDs with the same group ID
16338 uint8_t led2_group_id;
16339 /* An identifier for the LED #3. */
16341 /* The type of LED #3. */
16344 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
16346 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
16348 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
16349 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
16350 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
16351 /* The current state of the LED #3. */
16352 uint8_t led3_state;
16353 /* Default state of the LED */
16354 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16356 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
16358 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
16360 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
16361 /* Blink Alternately */
16362 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16363 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
16364 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
16365 /* The color of LED #3. */
16366 uint8_t led3_color;
16368 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16370 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16372 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16373 /* Green or Amber */
16374 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16375 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
16376 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
16379 * If the LED #3 state is "blink" or "blinkalt", then
16380 * this field represents the requested time in milliseconds
16381 * to keep LED on between cycles.
16383 uint16_t led3_blink_on;
16385 * If the LED #3 state is "blink" or "blinkalt", then
16386 * this field represents the requested time in milliseconds
16387 * to keep LED off between cycles.
16389 uint16_t led3_blink_off;
16391 * An identifier for the group of LEDs that LED #3 belongs
16393 * If set to 0, then the LED #3 is not grouped.
16394 * For all other non-zero values of this field, LED #3 is
16395 * grouped together with the LEDs with the same group ID
16398 uint8_t led3_group_id;
16399 uint8_t unused_4[6];
16401 * This field is used in Output records to indicate that the output
16402 * is completely written to RAM. This field should be read as '1'
16403 * to indicate that the output has been completely written.
16404 * When writing a command completion or response to an internal processor,
16405 * the order of writes has to be such that this field is written last.
16408 } __attribute__((packed));
16410 /***********************
16411 * hwrm_port_led_qcaps *
16412 ***********************/
16415 /* hwrm_port_led_qcaps_input (size:192b/24B) */
16416 struct hwrm_port_led_qcaps_input {
16417 /* The HWRM command request type. */
16420 * The completion ring to send the completion event on. This should
16421 * be the NQ ID returned from the `nq_alloc` HWRM command.
16423 uint16_t cmpl_ring;
16425 * The sequence ID is used by the driver for tracking multiple
16426 * commands. This ID is treated as opaque data by the firmware and
16427 * the value is returned in the `hwrm_resp_hdr` upon completion.
16431 * The target ID of the command:
16432 * * 0x0-0xFFF8 - The function ID
16433 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16434 * * 0xFFFD - Reserved for user-space HWRM interface
16437 uint16_t target_id;
16439 * A physical address pointer pointing to a host buffer that the
16440 * command's response data will be written. This can be either a host
16441 * physical address (HPA) or a guest physical address (GPA) and must
16442 * point to a physically contiguous block of memory.
16444 uint64_t resp_addr;
16445 /* Port ID of port whose LED configuration is being queried. */
16447 uint8_t unused_0[6];
16448 } __attribute__((packed));
16450 /* hwrm_port_led_qcaps_output (size:384b/48B) */
16451 struct hwrm_port_led_qcaps_output {
16452 /* The specific error status for the command. */
16453 uint16_t error_code;
16454 /* The HWRM command request type. */
16456 /* The sequence ID from the original command. */
16458 /* The length of the response data in number of bytes. */
16461 * The number of LEDs that are configured on this port.
16462 * Up to 4 LEDs can be returned in the response.
16465 /* Reserved for future use. */
16467 /* An identifier for the LED #0. */
16469 /* The type of LED #0. */
16472 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
16474 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
16476 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
16477 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
16478 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
16480 * An identifier for the group of LEDs that LED #0 belongs
16482 * If set to 0, then the LED #0 cannot be grouped.
16483 * For all other non-zero values of this field, LED #0 is
16484 * grouped together with the LEDs with the same group ID
16487 uint8_t led0_group_id;
16489 /* The states supported by LED #0. */
16490 uint16_t led0_state_caps;
16492 * If set to 1, this LED is enabled.
16493 * If set to 0, this LED is disabled.
16495 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
16498 * If set to 1, off state is supported on this LED.
16499 * If set to 0, off state is not supported on this LED.
16501 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
16504 * If set to 1, on state is supported on this LED.
16505 * If set to 0, on state is not supported on this LED.
16507 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
16510 * If set to 1, blink state is supported on this LED.
16511 * If set to 0, blink state is not supported on this LED.
16513 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
16516 * If set to 1, blink_alt state is supported on this LED.
16517 * If set to 0, blink_alt state is not supported on this LED.
16519 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
16521 /* The colors supported by LED #0. */
16522 uint16_t led0_color_caps;
16524 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
16527 * If set to 1, Amber color is supported on this LED.
16528 * If set to 0, Amber color is not supported on this LED.
16530 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
16533 * If set to 1, Green color is supported on this LED.
16534 * If set to 0, Green color is not supported on this LED.
16536 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
16538 /* An identifier for the LED #1. */
16540 /* The type of LED #1. */
16543 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
16545 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
16547 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
16548 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
16549 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
16551 * An identifier for the group of LEDs that LED #1 belongs
16553 * If set to 0, then the LED #0 cannot be grouped.
16554 * For all other non-zero values of this field, LED #0 is
16555 * grouped together with the LEDs with the same group ID
16558 uint8_t led1_group_id;
16560 /* The states supported by LED #1. */
16561 uint16_t led1_state_caps;
16563 * If set to 1, this LED is enabled.
16564 * If set to 0, this LED is disabled.
16566 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
16569 * If set to 1, off state is supported on this LED.
16570 * If set to 0, off state is not supported on this LED.
16572 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
16575 * If set to 1, on state is supported on this LED.
16576 * If set to 0, on state is not supported on this LED.
16578 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
16581 * If set to 1, blink state is supported on this LED.
16582 * If set to 0, blink state is not supported on this LED.
16584 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
16587 * If set to 1, blink_alt state is supported on this LED.
16588 * If set to 0, blink_alt state is not supported on this LED.
16590 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
16592 /* The colors supported by LED #1. */
16593 uint16_t led1_color_caps;
16595 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
16598 * If set to 1, Amber color is supported on this LED.
16599 * If set to 0, Amber color is not supported on this LED.
16601 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
16604 * If set to 1, Green color is supported on this LED.
16605 * If set to 0, Green color is not supported on this LED.
16607 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
16609 /* An identifier for the LED #2. */
16611 /* The type of LED #2. */
16614 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
16616 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
16618 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
16619 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
16620 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
16622 * An identifier for the group of LEDs that LED #0 belongs
16624 * If set to 0, then the LED #0 cannot be grouped.
16625 * For all other non-zero values of this field, LED #0 is
16626 * grouped together with the LEDs with the same group ID
16629 uint8_t led2_group_id;
16631 /* The states supported by LED #2. */
16632 uint16_t led2_state_caps;
16634 * If set to 1, this LED is enabled.
16635 * If set to 0, this LED is disabled.
16637 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
16640 * If set to 1, off state is supported on this LED.
16641 * If set to 0, off state is not supported on this LED.
16643 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
16646 * If set to 1, on state is supported on this LED.
16647 * If set to 0, on state is not supported on this LED.
16649 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
16652 * If set to 1, blink state is supported on this LED.
16653 * If set to 0, blink state is not supported on this LED.
16655 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
16658 * If set to 1, blink_alt state is supported on this LED.
16659 * If set to 0, blink_alt state is not supported on this LED.
16661 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
16663 /* The colors supported by LED #2. */
16664 uint16_t led2_color_caps;
16666 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
16669 * If set to 1, Amber color is supported on this LED.
16670 * If set to 0, Amber color is not supported on this LED.
16672 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
16675 * If set to 1, Green color is supported on this LED.
16676 * If set to 0, Green color is not supported on this LED.
16678 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
16680 /* An identifier for the LED #3. */
16682 /* The type of LED #3. */
16685 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
16687 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
16689 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
16690 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
16691 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
16693 * An identifier for the group of LEDs that LED #3 belongs
16695 * If set to 0, then the LED #0 cannot be grouped.
16696 * For all other non-zero values of this field, LED #0 is
16697 * grouped together with the LEDs with the same group ID
16700 uint8_t led3_group_id;
16702 /* The states supported by LED #3. */
16703 uint16_t led3_state_caps;
16705 * If set to 1, this LED is enabled.
16706 * If set to 0, this LED is disabled.
16708 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
16711 * If set to 1, off state is supported on this LED.
16712 * If set to 0, off state is not supported on this LED.
16714 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
16717 * If set to 1, on state is supported on this LED.
16718 * If set to 0, on state is not supported on this LED.
16720 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
16723 * If set to 1, blink state is supported on this LED.
16724 * If set to 0, blink state is not supported on this LED.
16726 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
16729 * If set to 1, blink_alt state is supported on this LED.
16730 * If set to 0, blink_alt state is not supported on this LED.
16732 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
16734 /* The colors supported by LED #3. */
16735 uint16_t led3_color_caps;
16737 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
16740 * If set to 1, Amber color is supported on this LED.
16741 * If set to 0, Amber color is not supported on this LED.
16743 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
16746 * If set to 1, Green color is supported on this LED.
16747 * If set to 0, Green color is not supported on this LED.
16749 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
16751 uint8_t unused_4[3];
16753 * This field is used in Output records to indicate that the output
16754 * is completely written to RAM. This field should be read as '1'
16755 * to indicate that the output has been completely written.
16756 * When writing a command completion or response to an internal processor,
16757 * the order of writes has to be such that this field is written last.
16760 } __attribute__((packed));
16762 /***********************
16763 * hwrm_port_prbs_test *
16764 ***********************/
16767 /* hwrm_port_prbs_test_input (size:384b/48B) */
16768 struct hwrm_port_prbs_test_input {
16769 /* The HWRM command request type. */
16772 * The completion ring to send the completion event on. This should
16773 * be the NQ ID returned from the `nq_alloc` HWRM command.
16775 uint16_t cmpl_ring;
16777 * The sequence ID is used by the driver for tracking multiple
16778 * commands. This ID is treated as opaque data by the firmware and
16779 * the value is returned in the `hwrm_resp_hdr` upon completion.
16783 * The target ID of the command:
16784 * * 0x0-0xFFF8 - The function ID
16785 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16786 * * 0xFFFD - Reserved for user-space HWRM interface
16789 uint16_t target_id;
16791 * A physical address pointer pointing to a host buffer that the
16792 * command's response data will be written. This can be either a host
16793 * physical address (HPA) or a guest physical address (GPA) and must
16794 * point to a physically contiguous block of memory.
16796 uint64_t resp_addr;
16797 /* Host address data is to DMA'd to. */
16798 uint64_t resp_data_addr;
16800 * Size of the buffer pointed to by resp_data_addr. The firmware may
16801 * use this entire buffer or less than the entire buffer, but never more.
16806 /* Port ID of port where PRBS test to be run. */
16808 /* Polynomial selection for PRBS test. */
16811 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
16813 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
16815 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
16817 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
16819 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
16821 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
16823 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
16825 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
16826 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
16827 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
16829 * Configuration bits for PRBS test.
16830 * Use enable bit to start/stop test.
16831 * Use tx/rx lane map bits to run test on specific lanes,
16832 * if set to 0 test will be run on all lanes.
16834 uint16_t prbs_config;
16836 * Set 0 to stop test currently in progress
16837 * Set 1 to start test with configuration provided.
16839 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
16842 * If set to 1, tx_lane_map bitmap should have lane bits set.
16843 * If set to 0, test will be run on all lanes for this port.
16845 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
16848 * If set to 1, rx_lane_map bitmap should have lane bits set.
16849 * If set to 0, test will be run on all lanes for this port.
16851 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
16853 /* Duration in seconds to run the PRBS test. */
16856 * If tx_lane_map_valid is set to 1, this field is a bitmap
16857 * of tx lanes to run PRBS test. bit0 = lane0,
16858 * bit1 = lane1 ..bit31 = lane31
16860 uint32_t tx_lane_map;
16862 * If rx_lane_map_valid is set to 1, this field is a bitmap
16863 * of rx lanes to run PRBS test. bit0 = lane0,
16864 * bit1 = lane1 ..bit31 = lane31
16866 uint32_t rx_lane_map;
16867 } __attribute__((packed));
16869 /* hwrm_port_prbs_test_output (size:128b/16B) */
16870 struct hwrm_port_prbs_test_output {
16871 /* The specific error status for the command. */
16872 uint16_t error_code;
16873 /* The HWRM command request type. */
16875 /* The sequence ID from the original command. */
16877 /* The length of the response data in number of bytes. */
16879 /* Total length of stored data. */
16880 uint16_t total_data_len;
16882 uint8_t unused_1[3];
16884 * This field is used in Output records to indicate that the output
16885 * is completely written to RAM. This field should be read as '1'
16886 * to indicate that the output has been completely written.
16887 * When writing a command completion or response to an internal processor,
16888 * the order of writes has to be such that this field is written last.
16891 } __attribute__((packed));
16893 /***********************
16894 * hwrm_queue_qportcfg *
16895 ***********************/
16898 /* hwrm_queue_qportcfg_input (size:192b/24B) */
16899 struct hwrm_queue_qportcfg_input {
16900 /* The HWRM command request type. */
16903 * The completion ring to send the completion event on. This should
16904 * be the NQ ID returned from the `nq_alloc` HWRM command.
16906 uint16_t cmpl_ring;
16908 * The sequence ID is used by the driver for tracking multiple
16909 * commands. This ID is treated as opaque data by the firmware and
16910 * the value is returned in the `hwrm_resp_hdr` upon completion.
16914 * The target ID of the command:
16915 * * 0x0-0xFFF8 - The function ID
16916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16917 * * 0xFFFD - Reserved for user-space HWRM interface
16920 uint16_t target_id;
16922 * A physical address pointer pointing to a host buffer that the
16923 * command's response data will be written. This can be either a host
16924 * physical address (HPA) or a guest physical address (GPA) and must
16925 * point to a physically contiguous block of memory.
16927 uint64_t resp_addr;
16930 * Enumeration denoting the RX, TX type of the resource.
16931 * This enumeration is used for resources that are similar for both
16932 * TX and RX paths of the chip.
16934 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
16936 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
16938 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
16939 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
16940 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
16942 * Port ID of port for which the queue configuration is being
16943 * queried. This field is only required when sent by IPC.
16947 * Drivers will set this capability when it can use
16948 * queue_idx_service_profile to map the queues to application.
16950 uint8_t drv_qmap_cap;
16952 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
16954 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
16955 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
16956 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
16958 } __attribute__((packed));
16960 /* hwrm_queue_qportcfg_output (size:256b/32B) */
16961 struct hwrm_queue_qportcfg_output {
16962 /* The specific error status for the command. */
16963 uint16_t error_code;
16964 /* The HWRM command request type. */
16966 /* The sequence ID from the original command. */
16968 /* The length of the response data in number of bytes. */
16971 * The maximum number of queues that can be configured on this
16973 * Valid values range from 1 through 8.
16975 uint8_t max_configurable_queues;
16977 * The maximum number of lossless queues that can be configured
16979 * Valid values range from 0 through 8.
16981 uint8_t max_configurable_lossless_queues;
16983 * Bitmask indicating which queues can be configured by the
16984 * hwrm_queue_cfg command.
16986 * Each bit represents a specific queue where bit 0 represents
16987 * queue 0 and bit 7 represents queue 7.
16988 * # A value of 0 indicates that the queue is not configurable
16989 * by the hwrm_queue_cfg command.
16990 * # A value of 1 indicates that the queue is configurable.
16991 * # A hwrm_queue_cfg command shall return error when trying to
16992 * configure a queue not configurable.
16994 uint8_t queue_cfg_allowed;
16995 /* Information about queue configuration. */
16996 uint8_t queue_cfg_info;
16998 * If this flag is set to '1', then the queues are
16999 * configured asymmetrically on TX and RX sides.
17000 * If this flag is set to '0', then the queues are
17001 * configured symmetrically on TX and RX sides. For
17002 * symmetric configuration, the queue configuration
17003 * including queue ids and service profiles on the
17004 * TX side is the same as the corresponding queue
17005 * configuration on the RX side.
17007 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17010 * Bitmask indicating which queues can be configured by the
17011 * hwrm_queue_pfcenable_cfg command.
17013 * Each bit represents a specific priority where bit 0 represents
17014 * priority 0 and bit 7 represents priority 7.
17015 * # A value of 0 indicates that the priority is not configurable by
17016 * the hwrm_queue_pfcenable_cfg command.
17017 * # A value of 1 indicates that the priority is configurable.
17018 * # A hwrm_queue_pfcenable_cfg command shall return error when
17019 * trying to configure a priority that is not configurable.
17021 uint8_t queue_pfcenable_cfg_allowed;
17023 * Bitmask indicating which queues can be configured by the
17024 * hwrm_queue_pri2cos_cfg command.
17026 * Each bit represents a specific queue where bit 0 represents
17027 * queue 0 and bit 7 represents queue 7.
17028 * # A value of 0 indicates that the queue is not configurable
17029 * by the hwrm_queue_pri2cos_cfg command.
17030 * # A value of 1 indicates that the queue is configurable.
17031 * # A hwrm_queue_pri2cos_cfg command shall return error when
17032 * trying to configure a queue that is not configurable.
17034 uint8_t queue_pri2cos_cfg_allowed;
17036 * Bitmask indicating which queues can be configured by the
17037 * hwrm_queue_pri2cos_cfg command.
17039 * Each bit represents a specific queue where bit 0 represents
17040 * queue 0 and bit 7 represents queue 7.
17041 * # A value of 0 indicates that the queue is not configurable
17042 * by the hwrm_queue_pri2cos_cfg command.
17043 * # A value of 1 indicates that the queue is configurable.
17044 * # A hwrm_queue_pri2cos_cfg command shall return error when
17045 * trying to configure a queue not configurable.
17047 uint8_t queue_cos2bw_cfg_allowed;
17049 * ID of CoS Queue 0.
17052 * # This ID can be used on any subsequent call to an hwrm command
17053 * that takes a queue id.
17054 * # IDs must always be queried by this command before any use
17055 * by the driver or software.
17056 * # Any driver or software should not make any assumptions about
17058 * # A value of 0xff indicates that the queue is not available.
17059 * # Available queues may not be in sequential order.
17062 /* This value is applicable to CoS queues only. */
17063 uint8_t queue_id0_service_profile;
17064 /* Lossy (best-effort) */
17065 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
17067 /* Lossless (legacy) */
17068 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
17070 /* Lossless RoCE */
17071 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
17073 /* Lossy RoCE CNP */
17074 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17077 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
17079 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17080 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
17082 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
17083 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
17085 * ID of CoS Queue 1.
17088 * # This ID can be used on any subsequent call to an hwrm command
17089 * that takes a queue id.
17090 * # IDs must always be queried by this command before any use
17091 * by the driver or software.
17092 * # Any driver or software should not make any assumptions about
17094 * # A value of 0xff indicates that the queue is not available.
17095 * # Available queues may not be in sequential order.
17098 /* This value is applicable to CoS queues only. */
17099 uint8_t queue_id1_service_profile;
17100 /* Lossy (best-effort) */
17101 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
17103 /* Lossless (legacy) */
17104 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
17106 /* Lossless RoCE */
17107 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
17109 /* Lossy RoCE CNP */
17110 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17113 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
17115 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17116 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
17118 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
17119 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
17121 * ID of CoS Queue 2.
17124 * # This ID can be used on any subsequent call to an hwrm command
17125 * that takes a queue id.
17126 * # IDs must always be queried by this command before any use
17127 * by the driver or software.
17128 * # Any driver or software should not make any assumptions about
17130 * # A value of 0xff indicates that the queue is not available.
17131 * # Available queues may not be in sequential order.
17134 /* This value is applicable to CoS queues only. */
17135 uint8_t queue_id2_service_profile;
17136 /* Lossy (best-effort) */
17137 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
17139 /* Lossless (legacy) */
17140 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
17142 /* Lossless RoCE */
17143 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
17145 /* Lossy RoCE CNP */
17146 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17149 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
17151 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17152 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
17154 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
17155 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
17157 * ID of CoS Queue 3.
17160 * # This ID can be used on any subsequent call to an hwrm command
17161 * that takes a queue id.
17162 * # IDs must always be queried by this command before any use
17163 * by the driver or software.
17164 * # Any driver or software should not make any assumptions about
17166 * # A value of 0xff indicates that the queue is not available.
17167 * # Available queues may not be in sequential order.
17170 /* This value is applicable to CoS queues only. */
17171 uint8_t queue_id3_service_profile;
17172 /* Lossy (best-effort) */
17173 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
17175 /* Lossless (legacy) */
17176 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
17178 /* Lossless RoCE */
17179 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
17181 /* Lossy RoCE CNP */
17182 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17185 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
17187 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17188 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
17190 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
17191 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
17193 * ID of CoS Queue 4.
17196 * # This ID can be used on any subsequent call to an hwrm command
17197 * that takes a queue id.
17198 * # IDs must always be queried by this command before any use
17199 * by the driver or software.
17200 * # Any driver or software should not make any assumptions about
17202 * # A value of 0xff indicates that the queue is not available.
17203 * # Available queues may not be in sequential order.
17206 /* This value is applicable to CoS queues only. */
17207 uint8_t queue_id4_service_profile;
17208 /* Lossy (best-effort) */
17209 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
17211 /* Lossless (legacy) */
17212 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
17214 /* Lossless RoCE */
17215 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
17217 /* Lossy RoCE CNP */
17218 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17221 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
17223 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17224 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
17226 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
17227 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
17229 * ID of CoS Queue 5.
17232 * # This ID can be used on any subsequent call to an hwrm command
17233 * that takes a queue id.
17234 * # IDs must always be queried by this command before any use
17235 * by the driver or software.
17236 * # Any driver or software should not make any assumptions about
17238 * # A value of 0xff indicates that the queue is not available.
17239 * # Available queues may not be in sequential order.
17242 /* This value is applicable to CoS queues only. */
17243 uint8_t queue_id5_service_profile;
17244 /* Lossy (best-effort) */
17245 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
17247 /* Lossless (legacy) */
17248 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
17250 /* Lossless RoCE */
17251 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
17253 /* Lossy RoCE CNP */
17254 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17257 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
17259 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17260 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
17262 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
17263 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
17265 * ID of CoS Queue 6.
17268 * # This ID can be used on any subsequent call to an hwrm command
17269 * that takes a queue id.
17270 * # IDs must always be queried by this command before any use
17271 * by the driver or software.
17272 * # Any driver or software should not make any assumptions about
17274 * # A value of 0xff indicates that the queue is not available.
17275 * # Available queues may not be in sequential order.
17278 /* This value is applicable to CoS queues only. */
17279 uint8_t queue_id6_service_profile;
17280 /* Lossy (best-effort) */
17281 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
17283 /* Lossless (legacy) */
17284 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
17286 /* Lossless RoCE */
17287 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
17289 /* Lossy RoCE CNP */
17290 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17293 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
17295 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17296 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
17298 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
17299 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
17301 * ID of CoS Queue 7.
17304 * # This ID can be used on any subsequent call to an hwrm command
17305 * that takes a queue id.
17306 * # IDs must always be queried by this command before any use
17307 * by the driver or software.
17308 * # Any driver or software should not make any assumptions about
17310 * # A value of 0xff indicates that the queue is not available.
17311 * # Available queues may not be in sequential order.
17314 /* This value is applicable to CoS queues only. */
17315 uint8_t queue_id7_service_profile;
17316 /* Lossy (best-effort) */
17317 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
17319 /* Lossless (legacy) */
17320 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
17322 /* Lossless RoCE */
17323 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
17325 /* Lossy RoCE CNP */
17326 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
17329 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
17331 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17332 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
17334 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
17335 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
17337 * This field is used in Output records to indicate that the output
17338 * is completely written to RAM. This field should be read as '1'
17339 * to indicate that the output has been completely written.
17340 * When writing a command completion or response to an internal processor,
17341 * the order of writes has to be such that this field is written last.
17344 } __attribute__((packed));
17346 /*******************
17347 * hwrm_queue_qcfg *
17348 *******************/
17351 /* hwrm_queue_qcfg_input (size:192b/24B) */
17352 struct hwrm_queue_qcfg_input {
17353 /* The HWRM command request type. */
17356 * The completion ring to send the completion event on. This should
17357 * be the NQ ID returned from the `nq_alloc` HWRM command.
17359 uint16_t cmpl_ring;
17361 * The sequence ID is used by the driver for tracking multiple
17362 * commands. This ID is treated as opaque data by the firmware and
17363 * the value is returned in the `hwrm_resp_hdr` upon completion.
17367 * The target ID of the command:
17368 * * 0x0-0xFFF8 - The function ID
17369 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17370 * * 0xFFFD - Reserved for user-space HWRM interface
17373 uint16_t target_id;
17375 * A physical address pointer pointing to a host buffer that the
17376 * command's response data will be written. This can be either a host
17377 * physical address (HPA) or a guest physical address (GPA) and must
17378 * point to a physically contiguous block of memory.
17380 uint64_t resp_addr;
17383 * Enumeration denoting the RX, TX type of the resource.
17384 * This enumeration is used for resources that are similar for both
17385 * TX and RX paths of the chip.
17387 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17389 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17391 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17392 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
17393 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
17394 /* Queue ID of the queue. */
17396 } __attribute__((packed));
17398 /* hwrm_queue_qcfg_output (size:128b/16B) */
17399 struct hwrm_queue_qcfg_output {
17400 /* The specific error status for the command. */
17401 uint16_t error_code;
17402 /* The HWRM command request type. */
17404 /* The sequence ID from the original command. */
17406 /* The length of the response data in number of bytes. */
17409 * This value is a the estimate packet length used in the
17412 uint32_t queue_len;
17413 /* This value is applicable to CoS queues only. */
17414 uint8_t service_profile;
17415 /* Lossy (best-effort) */
17416 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
17418 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
17419 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17420 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
17421 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
17422 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
17423 /* Information about queue configuration. */
17424 uint8_t queue_cfg_info;
17426 * If this flag is set to '1', then the queue is
17427 * configured asymmetrically on TX and RX sides.
17428 * If this flag is set to '0', then this queue is
17429 * configured symmetrically on TX and RX sides.
17431 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17435 * This field is used in Output records to indicate that the output
17436 * is completely written to RAM. This field should be read as '1'
17437 * to indicate that the output has been completely written.
17438 * When writing a command completion or response to an internal processor,
17439 * the order of writes has to be such that this field is written last.
17442 } __attribute__((packed));
17444 /******************
17446 ******************/
17449 /* hwrm_queue_cfg_input (size:320b/40B) */
17450 struct hwrm_queue_cfg_input {
17451 /* The HWRM command request type. */
17454 * The completion ring to send the completion event on. This should
17455 * be the NQ ID returned from the `nq_alloc` HWRM command.
17457 uint16_t cmpl_ring;
17459 * The sequence ID is used by the driver for tracking multiple
17460 * commands. This ID is treated as opaque data by the firmware and
17461 * the value is returned in the `hwrm_resp_hdr` upon completion.
17465 * The target ID of the command:
17466 * * 0x0-0xFFF8 - The function ID
17467 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17468 * * 0xFFFD - Reserved for user-space HWRM interface
17471 uint16_t target_id;
17473 * A physical address pointer pointing to a host buffer that the
17474 * command's response data will be written. This can be either a host
17475 * physical address (HPA) or a guest physical address (GPA) and must
17476 * point to a physically contiguous block of memory.
17478 uint64_t resp_addr;
17481 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
17482 * This enumeration is used for resources that are similar for both
17483 * TX and RX paths of the chip.
17485 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
17486 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
17488 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17490 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17491 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
17492 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
17493 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
17494 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
17497 * This bit must be '1' for the dflt_len field to be
17500 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
17502 * This bit must be '1' for the service_profile field to be
17505 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
17506 /* Queue ID of queue that is to be configured by this function. */
17509 * This value is a the estimate packet length used in the
17511 * Set to 0xFF... (All Fs) to not adjust this value.
17514 /* This value is applicable to CoS queues only. */
17515 uint8_t service_profile;
17516 /* Lossy (best-effort) */
17517 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
17519 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
17520 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17521 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
17522 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
17523 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
17524 uint8_t unused_0[7];
17525 } __attribute__((packed));
17527 /* hwrm_queue_cfg_output (size:128b/16B) */
17528 struct hwrm_queue_cfg_output {
17529 /* The specific error status for the command. */
17530 uint16_t error_code;
17531 /* The HWRM command request type. */
17533 /* The sequence ID from the original command. */
17535 /* The length of the response data in number of bytes. */
17537 uint8_t unused_0[7];
17539 * This field is used in Output records to indicate that the output
17540 * is completely written to RAM. This field should be read as '1'
17541 * to indicate that the output has been completely written.
17542 * When writing a command completion or response to an internal processor,
17543 * the order of writes has to be such that this field is written last.
17546 } __attribute__((packed));
17548 /*****************************
17549 * hwrm_queue_pfcenable_qcfg *
17550 *****************************/
17553 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
17554 struct hwrm_queue_pfcenable_qcfg_input {
17555 /* The HWRM command request type. */
17558 * The completion ring to send the completion event on. This should
17559 * be the NQ ID returned from the `nq_alloc` HWRM command.
17561 uint16_t cmpl_ring;
17563 * The sequence ID is used by the driver for tracking multiple
17564 * commands. This ID is treated as opaque data by the firmware and
17565 * the value is returned in the `hwrm_resp_hdr` upon completion.
17569 * The target ID of the command:
17570 * * 0x0-0xFFF8 - The function ID
17571 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17572 * * 0xFFFD - Reserved for user-space HWRM interface
17575 uint16_t target_id;
17577 * A physical address pointer pointing to a host buffer that the
17578 * command's response data will be written. This can be either a host
17579 * physical address (HPA) or a guest physical address (GPA) and must
17580 * point to a physically contiguous block of memory.
17582 uint64_t resp_addr;
17584 * Port ID of port for which the table is being configured.
17585 * The HWRM needs to check whether this function is allowed
17586 * to configure pri2cos mapping on this port.
17589 uint8_t unused_0[6];
17590 } __attribute__((packed));
17592 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
17593 struct hwrm_queue_pfcenable_qcfg_output {
17594 /* The specific error status for the command. */
17595 uint16_t error_code;
17596 /* The HWRM command request type. */
17598 /* The sequence ID from the original command. */
17600 /* The length of the response data in number of bytes. */
17603 /* If set to 1, then PFC is enabled on PRI 0. */
17604 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
17606 /* If set to 1, then PFC is enabled on PRI 1. */
17607 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
17609 /* If set to 1, then PFC is enabled on PRI 2. */
17610 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
17612 /* If set to 1, then PFC is enabled on PRI 3. */
17613 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
17615 /* If set to 1, then PFC is enabled on PRI 4. */
17616 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
17618 /* If set to 1, then PFC is enabled on PRI 5. */
17619 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
17621 /* If set to 1, then PFC is enabled on PRI 6. */
17622 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
17624 /* If set to 1, then PFC is enabled on PRI 7. */
17625 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
17627 uint8_t unused_0[3];
17629 * This field is used in Output records to indicate that the output
17630 * is completely written to RAM. This field should be read as '1'
17631 * to indicate that the output has been completely written.
17632 * When writing a command completion or response to an internal processor,
17633 * the order of writes has to be such that this field is written last.
17636 } __attribute__((packed));
17638 /****************************
17639 * hwrm_queue_pfcenable_cfg *
17640 ****************************/
17643 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
17644 struct hwrm_queue_pfcenable_cfg_input {
17645 /* The HWRM command request type. */
17648 * The completion ring to send the completion event on. This should
17649 * be the NQ ID returned from the `nq_alloc` HWRM command.
17651 uint16_t cmpl_ring;
17653 * The sequence ID is used by the driver for tracking multiple
17654 * commands. This ID is treated as opaque data by the firmware and
17655 * the value is returned in the `hwrm_resp_hdr` upon completion.
17659 * The target ID of the command:
17660 * * 0x0-0xFFF8 - The function ID
17661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17662 * * 0xFFFD - Reserved for user-space HWRM interface
17665 uint16_t target_id;
17667 * A physical address pointer pointing to a host buffer that the
17668 * command's response data will be written. This can be either a host
17669 * physical address (HPA) or a guest physical address (GPA) and must
17670 * point to a physically contiguous block of memory.
17672 uint64_t resp_addr;
17674 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
17675 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
17677 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
17678 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
17680 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
17681 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
17683 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
17684 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
17686 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
17687 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
17689 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
17690 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
17692 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
17693 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
17695 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
17696 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
17699 * Port ID of port for which the table is being configured.
17700 * The HWRM needs to check whether this function is allowed
17701 * to configure pri2cos mapping on this port.
17704 uint8_t unused_0[2];
17705 } __attribute__((packed));
17707 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
17708 struct hwrm_queue_pfcenable_cfg_output {
17709 /* The specific error status for the command. */
17710 uint16_t error_code;
17711 /* The HWRM command request type. */
17713 /* The sequence ID from the original command. */
17715 /* The length of the response data in number of bytes. */
17717 uint8_t unused_0[7];
17719 * This field is used in Output records to indicate that the output
17720 * is completely written to RAM. This field should be read as '1'
17721 * to indicate that the output has been completely written.
17722 * When writing a command completion or response to an internal processor,
17723 * the order of writes has to be such that this field is written last.
17726 } __attribute__((packed));
17728 /***************************
17729 * hwrm_queue_pri2cos_qcfg *
17730 ***************************/
17733 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
17734 struct hwrm_queue_pri2cos_qcfg_input {
17735 /* The HWRM command request type. */
17738 * The completion ring to send the completion event on. This should
17739 * be the NQ ID returned from the `nq_alloc` HWRM command.
17741 uint16_t cmpl_ring;
17743 * The sequence ID is used by the driver for tracking multiple
17744 * commands. This ID is treated as opaque data by the firmware and
17745 * the value is returned in the `hwrm_resp_hdr` upon completion.
17749 * The target ID of the command:
17750 * * 0x0-0xFFF8 - The function ID
17751 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17752 * * 0xFFFD - Reserved for user-space HWRM interface
17755 uint16_t target_id;
17757 * A physical address pointer pointing to a host buffer that the
17758 * command's response data will be written. This can be either a host
17759 * physical address (HPA) or a guest physical address (GPA) and must
17760 * point to a physically contiguous block of memory.
17762 uint64_t resp_addr;
17765 * Enumeration denoting the RX, TX type of the resource.
17766 * This enumeration is used for resources that are similar for both
17767 * TX and RX paths of the chip.
17769 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17771 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17773 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17774 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
17775 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
17777 * When this bit is set to '0', the query is
17778 * for VLAN PRI field in tunnel headers.
17779 * When this bit is set to '1', the query is
17780 * for VLAN PRI field in inner packet headers.
17782 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
17784 * Port ID of port for which the table is being configured.
17785 * The HWRM needs to check whether this function is allowed
17786 * to configure pri2cos mapping on this port.
17789 uint8_t unused_0[3];
17790 } __attribute__((packed));
17792 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
17793 struct hwrm_queue_pri2cos_qcfg_output {
17794 /* The specific error status for the command. */
17795 uint16_t error_code;
17796 /* The HWRM command request type. */
17798 /* The sequence ID from the original command. */
17800 /* The length of the response data in number of bytes. */
17803 * CoS Queue assigned to priority 0. This value can only
17804 * be changed before traffic has started.
17805 * A value of 0xff indicates that no CoS queue is assigned to the
17806 * specified priority.
17808 uint8_t pri0_cos_queue_id;
17810 * CoS Queue assigned to priority 1. This value can only
17811 * be changed before traffic has started.
17812 * A value of 0xff indicates that no CoS queue is assigned to the
17813 * specified priority.
17815 uint8_t pri1_cos_queue_id;
17817 * CoS Queue assigned to priority 2 This value can only
17818 * be changed before traffic has started.
17819 * A value of 0xff indicates that no CoS queue is assigned to the
17820 * specified priority.
17822 uint8_t pri2_cos_queue_id;
17824 * CoS Queue assigned to priority 3. This value can only
17825 * be changed before traffic has started.
17826 * A value of 0xff indicates that no CoS queue is assigned to the
17827 * specified priority.
17829 uint8_t pri3_cos_queue_id;
17831 * CoS Queue assigned to priority 4. This value can only
17832 * be changed before traffic has started.
17833 * A value of 0xff indicates that no CoS queue is assigned to the
17834 * specified priority.
17836 uint8_t pri4_cos_queue_id;
17838 * CoS Queue assigned to priority 5. This value can only
17839 * be changed before traffic has started.
17840 * A value of 0xff indicates that no CoS queue is assigned to the
17841 * specified priority.
17843 uint8_t pri5_cos_queue_id;
17845 * CoS Queue assigned to priority 6. This value can only
17846 * be changed before traffic has started.
17847 * A value of 0xff indicates that no CoS queue is assigned to the
17848 * specified priority.
17850 uint8_t pri6_cos_queue_id;
17852 * CoS Queue assigned to priority 7. This value can only
17853 * be changed before traffic has started.
17854 * A value of 0xff indicates that no CoS queue is assigned to the
17855 * specified priority.
17857 uint8_t pri7_cos_queue_id;
17858 /* Information about queue configuration. */
17859 uint8_t queue_cfg_info;
17861 * If this flag is set to '1', then the PRI to CoS
17862 * configuration is asymmetric on TX and RX sides.
17863 * If this flag is set to '0', then PRI to CoS configuration
17864 * is symmetric on TX and RX sides.
17866 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17868 uint8_t unused_0[6];
17870 * This field is used in Output records to indicate that the output
17871 * is completely written to RAM. This field should be read as '1'
17872 * to indicate that the output has been completely written.
17873 * When writing a command completion or response to an internal processor,
17874 * the order of writes has to be such that this field is written last.
17877 } __attribute__((packed));
17879 /**************************
17880 * hwrm_queue_pri2cos_cfg *
17881 **************************/
17884 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
17885 struct hwrm_queue_pri2cos_cfg_input {
17886 /* The HWRM command request type. */
17889 * The completion ring to send the completion event on. This should
17890 * be the NQ ID returned from the `nq_alloc` HWRM command.
17892 uint16_t cmpl_ring;
17894 * The sequence ID is used by the driver for tracking multiple
17895 * commands. This ID is treated as opaque data by the firmware and
17896 * the value is returned in the `hwrm_resp_hdr` upon completion.
17900 * The target ID of the command:
17901 * * 0x0-0xFFF8 - The function ID
17902 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17903 * * 0xFFFD - Reserved for user-space HWRM interface
17906 uint16_t target_id;
17908 * A physical address pointer pointing to a host buffer that the
17909 * command's response data will be written. This can be either a host
17910 * physical address (HPA) or a guest physical address (GPA) and must
17911 * point to a physically contiguous block of memory.
17913 uint64_t resp_addr;
17916 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
17917 * This enumeration is used for resources that are similar for both
17918 * TX and RX paths of the chip.
17920 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
17921 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
17923 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17925 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17926 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
17927 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
17928 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
17929 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
17931 * When this bit is set to '0', the mapping is requested
17932 * for VLAN PRI field in tunnel headers.
17933 * When this bit is set to '1', the mapping is requested
17934 * for VLAN PRI field in inner packet headers.
17936 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
17939 * This bit must be '1' for the pri0_cos_queue_id field to be
17942 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
17945 * This bit must be '1' for the pri1_cos_queue_id field to be
17948 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
17951 * This bit must be '1' for the pri2_cos_queue_id field to be
17954 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
17957 * This bit must be '1' for the pri3_cos_queue_id field to be
17960 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
17963 * This bit must be '1' for the pri4_cos_queue_id field to be
17966 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
17969 * This bit must be '1' for the pri5_cos_queue_id field to be
17972 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
17975 * This bit must be '1' for the pri6_cos_queue_id field to be
17978 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
17981 * This bit must be '1' for the pri7_cos_queue_id field to be
17984 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
17987 * Port ID of port for which the table is being configured.
17988 * The HWRM needs to check whether this function is allowed
17989 * to configure pri2cos mapping on this port.
17993 * CoS Queue assigned to priority 0. This value can only
17994 * be changed before traffic has started.
17996 uint8_t pri0_cos_queue_id;
17998 * CoS Queue assigned to priority 1. This value can only
17999 * be changed before traffic has started.
18001 uint8_t pri1_cos_queue_id;
18003 * CoS Queue assigned to priority 2 This value can only
18004 * be changed before traffic has started.
18006 uint8_t pri2_cos_queue_id;
18008 * CoS Queue assigned to priority 3. This value can only
18009 * be changed before traffic has started.
18011 uint8_t pri3_cos_queue_id;
18013 * CoS Queue assigned to priority 4. This value can only
18014 * be changed before traffic has started.
18016 uint8_t pri4_cos_queue_id;
18018 * CoS Queue assigned to priority 5. This value can only
18019 * be changed before traffic has started.
18021 uint8_t pri5_cos_queue_id;
18023 * CoS Queue assigned to priority 6. This value can only
18024 * be changed before traffic has started.
18026 uint8_t pri6_cos_queue_id;
18028 * CoS Queue assigned to priority 7. This value can only
18029 * be changed before traffic has started.
18031 uint8_t pri7_cos_queue_id;
18032 uint8_t unused_0[7];
18033 } __attribute__((packed));
18035 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
18036 struct hwrm_queue_pri2cos_cfg_output {
18037 /* The specific error status for the command. */
18038 uint16_t error_code;
18039 /* The HWRM command request type. */
18041 /* The sequence ID from the original command. */
18043 /* The length of the response data in number of bytes. */
18045 uint8_t unused_0[7];
18047 * This field is used in Output records to indicate that the output
18048 * is completely written to RAM. This field should be read as '1'
18049 * to indicate that the output has been completely written.
18050 * When writing a command completion or response to an internal processor,
18051 * the order of writes has to be such that this field is written last.
18054 } __attribute__((packed));
18056 /**************************
18057 * hwrm_queue_cos2bw_qcfg *
18058 **************************/
18061 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
18062 struct hwrm_queue_cos2bw_qcfg_input {
18063 /* The HWRM command request type. */
18066 * The completion ring to send the completion event on. This should
18067 * be the NQ ID returned from the `nq_alloc` HWRM command.
18069 uint16_t cmpl_ring;
18071 * The sequence ID is used by the driver for tracking multiple
18072 * commands. This ID is treated as opaque data by the firmware and
18073 * the value is returned in the `hwrm_resp_hdr` upon completion.
18077 * The target ID of the command:
18078 * * 0x0-0xFFF8 - The function ID
18079 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18080 * * 0xFFFD - Reserved for user-space HWRM interface
18083 uint16_t target_id;
18085 * A physical address pointer pointing to a host buffer that the
18086 * command's response data will be written. This can be either a host
18087 * physical address (HPA) or a guest physical address (GPA) and must
18088 * point to a physically contiguous block of memory.
18090 uint64_t resp_addr;
18092 * Port ID of port for which the table is being configured.
18093 * The HWRM needs to check whether this function is allowed
18094 * to configure TC BW assignment on this port.
18097 uint8_t unused_0[6];
18098 } __attribute__((packed));
18100 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
18101 struct hwrm_queue_cos2bw_qcfg_output {
18102 /* The specific error status for the command. */
18103 uint16_t error_code;
18104 /* The HWRM command request type. */
18106 /* The sequence ID from the original command. */
18108 /* The length of the response data in number of bytes. */
18110 /* ID of CoS Queue 0. */
18115 * Minimum BW allocated to CoS Queue.
18116 * The HWRM will translate this value into byte counter and
18117 * time interval used for this COS inside the device.
18119 uint32_t queue_id0_min_bw;
18120 /* The bandwidth value. */
18121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
18122 UINT32_C(0xfffffff)
18123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
18125 /* The granularity of the value (bits or bytes). */
18126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
18127 UINT32_C(0x10000000)
18128 /* Value is in bits. */
18129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
18130 (UINT32_C(0x0) << 28)
18131 /* Value is in bytes. */
18132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
18133 (UINT32_C(0x1) << 28)
18134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
18135 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
18136 /* bw_value_unit is 3 b */
18137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
18138 UINT32_C(0xe0000000)
18139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
18141 /* Value is in Mb or MB (base 10). */
18142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
18143 (UINT32_C(0x0) << 29)
18144 /* Value is in Kb or KB (base 10). */
18145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
18146 (UINT32_C(0x2) << 29)
18147 /* Value is in bits or bytes. */
18148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
18149 (UINT32_C(0x4) << 29)
18150 /* Value is in Gb or GB (base 10). */
18151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
18152 (UINT32_C(0x6) << 29)
18153 /* Value is in 1/100th of a percentage of total bandwidth. */
18154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18155 (UINT32_C(0x1) << 29)
18157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
18158 (UINT32_C(0x7) << 29)
18159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
18160 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
18162 * Maximum BW allocated to CoS Queue.
18163 * The HWRM will translate this value into byte counter and
18164 * time interval used for this COS inside the device.
18166 uint32_t queue_id0_max_bw;
18167 /* The bandwidth value. */
18168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
18169 UINT32_C(0xfffffff)
18170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
18172 /* The granularity of the value (bits or bytes). */
18173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
18174 UINT32_C(0x10000000)
18175 /* Value is in bits. */
18176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
18177 (UINT32_C(0x0) << 28)
18178 /* Value is in bytes. */
18179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
18180 (UINT32_C(0x1) << 28)
18181 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
18182 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
18183 /* bw_value_unit is 3 b */
18184 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
18185 UINT32_C(0xe0000000)
18186 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
18188 /* Value is in Mb or MB (base 10). */
18189 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
18190 (UINT32_C(0x0) << 29)
18191 /* Value is in Kb or KB (base 10). */
18192 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
18193 (UINT32_C(0x2) << 29)
18194 /* Value is in bits or bytes. */
18195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
18196 (UINT32_C(0x4) << 29)
18197 /* Value is in Gb or GB (base 10). */
18198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
18199 (UINT32_C(0x6) << 29)
18200 /* Value is in 1/100th of a percentage of total bandwidth. */
18201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18202 (UINT32_C(0x1) << 29)
18204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
18205 (UINT32_C(0x7) << 29)
18206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
18207 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
18208 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18209 uint8_t queue_id0_tsa_assign;
18210 /* Strict Priority */
18211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
18213 /* Enhanced Transmission Selection */
18214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
18217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
18220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
18223 * Priority level for strict priority. Valid only when the
18224 * tsa_assign is 0 - Strict Priority (SP)
18225 * 0..7 - Valid values.
18226 * 8..255 - Reserved.
18228 uint8_t queue_id0_pri_lvl;
18230 * Weight used to allocate remaining BW for this COS after
18231 * servicing guaranteed bandwidths for all COS.
18233 uint8_t queue_id0_bw_weight;
18234 /* ID of CoS Queue 1. */
18237 * Minimum BW allocated to CoS Queue.
18238 * The HWRM will translate this value into byte counter and
18239 * time interval used for this COS inside the device.
18241 uint32_t queue_id1_min_bw;
18242 /* The bandwidth value. */
18243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
18244 UINT32_C(0xfffffff)
18245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
18247 /* The granularity of the value (bits or bytes). */
18248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
18249 UINT32_C(0x10000000)
18250 /* Value is in bits. */
18251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
18252 (UINT32_C(0x0) << 28)
18253 /* Value is in bytes. */
18254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
18255 (UINT32_C(0x1) << 28)
18256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
18257 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
18258 /* bw_value_unit is 3 b */
18259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
18260 UINT32_C(0xe0000000)
18261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
18263 /* Value is in Mb or MB (base 10). */
18264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
18265 (UINT32_C(0x0) << 29)
18266 /* Value is in Kb or KB (base 10). */
18267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
18268 (UINT32_C(0x2) << 29)
18269 /* Value is in bits or bytes. */
18270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
18271 (UINT32_C(0x4) << 29)
18272 /* Value is in Gb or GB (base 10). */
18273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
18274 (UINT32_C(0x6) << 29)
18275 /* Value is in 1/100th of a percentage of total bandwidth. */
18276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18277 (UINT32_C(0x1) << 29)
18279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
18280 (UINT32_C(0x7) << 29)
18281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
18282 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
18284 * Maximum BW allocated to CoS queue.
18285 * The HWRM will translate this value into byte counter and
18286 * time interval used for this COS inside the device.
18288 uint32_t queue_id1_max_bw;
18289 /* The bandwidth value. */
18290 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
18291 UINT32_C(0xfffffff)
18292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
18294 /* The granularity of the value (bits or bytes). */
18295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
18296 UINT32_C(0x10000000)
18297 /* Value is in bits. */
18298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
18299 (UINT32_C(0x0) << 28)
18300 /* Value is in bytes. */
18301 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
18302 (UINT32_C(0x1) << 28)
18303 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
18304 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
18305 /* bw_value_unit is 3 b */
18306 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
18307 UINT32_C(0xe0000000)
18308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
18310 /* Value is in Mb or MB (base 10). */
18311 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
18312 (UINT32_C(0x0) << 29)
18313 /* Value is in Kb or KB (base 10). */
18314 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
18315 (UINT32_C(0x2) << 29)
18316 /* Value is in bits or bytes. */
18317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
18318 (UINT32_C(0x4) << 29)
18319 /* Value is in Gb or GB (base 10). */
18320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
18321 (UINT32_C(0x6) << 29)
18322 /* Value is in 1/100th of a percentage of total bandwidth. */
18323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18324 (UINT32_C(0x1) << 29)
18326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
18327 (UINT32_C(0x7) << 29)
18328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
18329 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
18330 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18331 uint8_t queue_id1_tsa_assign;
18332 /* Strict Priority */
18333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
18335 /* Enhanced Transmission Selection */
18336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
18339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
18342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
18345 * Priority level for strict priority. Valid only when the
18346 * tsa_assign is 0 - Strict Priority (SP)
18347 * 0..7 - Valid values.
18348 * 8..255 - Reserved.
18350 uint8_t queue_id1_pri_lvl;
18352 * Weight used to allocate remaining BW for this COS after
18353 * servicing guaranteed bandwidths for all COS.
18355 uint8_t queue_id1_bw_weight;
18356 /* ID of CoS Queue 2. */
18359 * Minimum BW allocated to CoS Queue.
18360 * The HWRM will translate this value into byte counter and
18361 * time interval used for this COS inside the device.
18363 uint32_t queue_id2_min_bw;
18364 /* The bandwidth value. */
18365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
18366 UINT32_C(0xfffffff)
18367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
18369 /* The granularity of the value (bits or bytes). */
18370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
18371 UINT32_C(0x10000000)
18372 /* Value is in bits. */
18373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
18374 (UINT32_C(0x0) << 28)
18375 /* Value is in bytes. */
18376 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
18377 (UINT32_C(0x1) << 28)
18378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
18379 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
18380 /* bw_value_unit is 3 b */
18381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
18382 UINT32_C(0xe0000000)
18383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
18385 /* Value is in Mb or MB (base 10). */
18386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
18387 (UINT32_C(0x0) << 29)
18388 /* Value is in Kb or KB (base 10). */
18389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
18390 (UINT32_C(0x2) << 29)
18391 /* Value is in bits or bytes. */
18392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
18393 (UINT32_C(0x4) << 29)
18394 /* Value is in Gb or GB (base 10). */
18395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
18396 (UINT32_C(0x6) << 29)
18397 /* Value is in 1/100th of a percentage of total bandwidth. */
18398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18399 (UINT32_C(0x1) << 29)
18401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
18402 (UINT32_C(0x7) << 29)
18403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
18404 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
18406 * Maximum BW allocated to CoS queue.
18407 * The HWRM will translate this value into byte counter and
18408 * time interval used for this COS inside the device.
18410 uint32_t queue_id2_max_bw;
18411 /* The bandwidth value. */
18412 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
18413 UINT32_C(0xfffffff)
18414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
18416 /* The granularity of the value (bits or bytes). */
18417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
18418 UINT32_C(0x10000000)
18419 /* Value is in bits. */
18420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
18421 (UINT32_C(0x0) << 28)
18422 /* Value is in bytes. */
18423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
18424 (UINT32_C(0x1) << 28)
18425 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
18426 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
18427 /* bw_value_unit is 3 b */
18428 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
18429 UINT32_C(0xe0000000)
18430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
18432 /* Value is in Mb or MB (base 10). */
18433 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
18434 (UINT32_C(0x0) << 29)
18435 /* Value is in Kb or KB (base 10). */
18436 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
18437 (UINT32_C(0x2) << 29)
18438 /* Value is in bits or bytes. */
18439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
18440 (UINT32_C(0x4) << 29)
18441 /* Value is in Gb or GB (base 10). */
18442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
18443 (UINT32_C(0x6) << 29)
18444 /* Value is in 1/100th of a percentage of total bandwidth. */
18445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18446 (UINT32_C(0x1) << 29)
18448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
18449 (UINT32_C(0x7) << 29)
18450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
18451 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
18452 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18453 uint8_t queue_id2_tsa_assign;
18454 /* Strict Priority */
18455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
18457 /* Enhanced Transmission Selection */
18458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
18461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
18464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
18467 * Priority level for strict priority. Valid only when the
18468 * tsa_assign is 0 - Strict Priority (SP)
18469 * 0..7 - Valid values.
18470 * 8..255 - Reserved.
18472 uint8_t queue_id2_pri_lvl;
18474 * Weight used to allocate remaining BW for this COS after
18475 * servicing guaranteed bandwidths for all COS.
18477 uint8_t queue_id2_bw_weight;
18478 /* ID of CoS Queue 3. */
18481 * Minimum BW allocated to CoS Queue.
18482 * The HWRM will translate this value into byte counter and
18483 * time interval used for this COS inside the device.
18485 uint32_t queue_id3_min_bw;
18486 /* The bandwidth value. */
18487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
18488 UINT32_C(0xfffffff)
18489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
18491 /* The granularity of the value (bits or bytes). */
18492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
18493 UINT32_C(0x10000000)
18494 /* Value is in bits. */
18495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
18496 (UINT32_C(0x0) << 28)
18497 /* Value is in bytes. */
18498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
18499 (UINT32_C(0x1) << 28)
18500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
18501 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
18502 /* bw_value_unit is 3 b */
18503 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
18504 UINT32_C(0xe0000000)
18505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
18507 /* Value is in Mb or MB (base 10). */
18508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
18509 (UINT32_C(0x0) << 29)
18510 /* Value is in Kb or KB (base 10). */
18511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
18512 (UINT32_C(0x2) << 29)
18513 /* Value is in bits or bytes. */
18514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
18515 (UINT32_C(0x4) << 29)
18516 /* Value is in Gb or GB (base 10). */
18517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
18518 (UINT32_C(0x6) << 29)
18519 /* Value is in 1/100th of a percentage of total bandwidth. */
18520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18521 (UINT32_C(0x1) << 29)
18523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
18524 (UINT32_C(0x7) << 29)
18525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
18526 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
18528 * Maximum BW allocated to CoS queue.
18529 * The HWRM will translate this value into byte counter and
18530 * time interval used for this COS inside the device.
18532 uint32_t queue_id3_max_bw;
18533 /* The bandwidth value. */
18534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
18535 UINT32_C(0xfffffff)
18536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
18538 /* The granularity of the value (bits or bytes). */
18539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
18540 UINT32_C(0x10000000)
18541 /* Value is in bits. */
18542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
18543 (UINT32_C(0x0) << 28)
18544 /* Value is in bytes. */
18545 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
18546 (UINT32_C(0x1) << 28)
18547 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
18548 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
18549 /* bw_value_unit is 3 b */
18550 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
18551 UINT32_C(0xe0000000)
18552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
18554 /* Value is in Mb or MB (base 10). */
18555 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
18556 (UINT32_C(0x0) << 29)
18557 /* Value is in Kb or KB (base 10). */
18558 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
18559 (UINT32_C(0x2) << 29)
18560 /* Value is in bits or bytes. */
18561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
18562 (UINT32_C(0x4) << 29)
18563 /* Value is in Gb or GB (base 10). */
18564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
18565 (UINT32_C(0x6) << 29)
18566 /* Value is in 1/100th of a percentage of total bandwidth. */
18567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18568 (UINT32_C(0x1) << 29)
18570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
18571 (UINT32_C(0x7) << 29)
18572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
18573 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
18574 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18575 uint8_t queue_id3_tsa_assign;
18576 /* Strict Priority */
18577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
18579 /* Enhanced Transmission Selection */
18580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
18583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
18586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
18589 * Priority level for strict priority. Valid only when the
18590 * tsa_assign is 0 - Strict Priority (SP)
18591 * 0..7 - Valid values.
18592 * 8..255 - Reserved.
18594 uint8_t queue_id3_pri_lvl;
18596 * Weight used to allocate remaining BW for this COS after
18597 * servicing guaranteed bandwidths for all COS.
18599 uint8_t queue_id3_bw_weight;
18600 /* ID of CoS Queue 4. */
18603 * Minimum BW allocated to CoS Queue.
18604 * The HWRM will translate this value into byte counter and
18605 * time interval used for this COS inside the device.
18607 uint32_t queue_id4_min_bw;
18608 /* The bandwidth value. */
18609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
18610 UINT32_C(0xfffffff)
18611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
18613 /* The granularity of the value (bits or bytes). */
18614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
18615 UINT32_C(0x10000000)
18616 /* Value is in bits. */
18617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
18618 (UINT32_C(0x0) << 28)
18619 /* Value is in bytes. */
18620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
18621 (UINT32_C(0x1) << 28)
18622 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
18623 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
18624 /* bw_value_unit is 3 b */
18625 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
18626 UINT32_C(0xe0000000)
18627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
18629 /* Value is in Mb or MB (base 10). */
18630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
18631 (UINT32_C(0x0) << 29)
18632 /* Value is in Kb or KB (base 10). */
18633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
18634 (UINT32_C(0x2) << 29)
18635 /* Value is in bits or bytes. */
18636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
18637 (UINT32_C(0x4) << 29)
18638 /* Value is in Gb or GB (base 10). */
18639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
18640 (UINT32_C(0x6) << 29)
18641 /* Value is in 1/100th of a percentage of total bandwidth. */
18642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18643 (UINT32_C(0x1) << 29)
18645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
18646 (UINT32_C(0x7) << 29)
18647 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
18648 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
18650 * Maximum BW allocated to CoS queue.
18651 * The HWRM will translate this value into byte counter and
18652 * time interval used for this COS inside the device.
18654 uint32_t queue_id4_max_bw;
18655 /* The bandwidth value. */
18656 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
18657 UINT32_C(0xfffffff)
18658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
18660 /* The granularity of the value (bits or bytes). */
18661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
18662 UINT32_C(0x10000000)
18663 /* Value is in bits. */
18664 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
18665 (UINT32_C(0x0) << 28)
18666 /* Value is in bytes. */
18667 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
18668 (UINT32_C(0x1) << 28)
18669 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
18670 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
18671 /* bw_value_unit is 3 b */
18672 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
18673 UINT32_C(0xe0000000)
18674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
18676 /* Value is in Mb or MB (base 10). */
18677 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
18678 (UINT32_C(0x0) << 29)
18679 /* Value is in Kb or KB (base 10). */
18680 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
18681 (UINT32_C(0x2) << 29)
18682 /* Value is in bits or bytes. */
18683 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
18684 (UINT32_C(0x4) << 29)
18685 /* Value is in Gb or GB (base 10). */
18686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
18687 (UINT32_C(0x6) << 29)
18688 /* Value is in 1/100th of a percentage of total bandwidth. */
18689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18690 (UINT32_C(0x1) << 29)
18692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
18693 (UINT32_C(0x7) << 29)
18694 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
18695 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
18696 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18697 uint8_t queue_id4_tsa_assign;
18698 /* Strict Priority */
18699 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
18701 /* Enhanced Transmission Selection */
18702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
18705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
18708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
18711 * Priority level for strict priority. Valid only when the
18712 * tsa_assign is 0 - Strict Priority (SP)
18713 * 0..7 - Valid values.
18714 * 8..255 - Reserved.
18716 uint8_t queue_id4_pri_lvl;
18718 * Weight used to allocate remaining BW for this COS after
18719 * servicing guaranteed bandwidths for all COS.
18721 uint8_t queue_id4_bw_weight;
18722 /* ID of CoS Queue 5. */
18725 * Minimum BW allocated to CoS Queue.
18726 * The HWRM will translate this value into byte counter and
18727 * time interval used for this COS inside the device.
18729 uint32_t queue_id5_min_bw;
18730 /* The bandwidth value. */
18731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
18732 UINT32_C(0xfffffff)
18733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
18735 /* The granularity of the value (bits or bytes). */
18736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
18737 UINT32_C(0x10000000)
18738 /* Value is in bits. */
18739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
18740 (UINT32_C(0x0) << 28)
18741 /* Value is in bytes. */
18742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
18743 (UINT32_C(0x1) << 28)
18744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
18745 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
18746 /* bw_value_unit is 3 b */
18747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
18748 UINT32_C(0xe0000000)
18749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
18751 /* Value is in Mb or MB (base 10). */
18752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
18753 (UINT32_C(0x0) << 29)
18754 /* Value is in Kb or KB (base 10). */
18755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
18756 (UINT32_C(0x2) << 29)
18757 /* Value is in bits or bytes. */
18758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
18759 (UINT32_C(0x4) << 29)
18760 /* Value is in Gb or GB (base 10). */
18761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
18762 (UINT32_C(0x6) << 29)
18763 /* Value is in 1/100th of a percentage of total bandwidth. */
18764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18765 (UINT32_C(0x1) << 29)
18767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
18768 (UINT32_C(0x7) << 29)
18769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
18770 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
18772 * Maximum BW allocated to CoS queue.
18773 * The HWRM will translate this value into byte counter and
18774 * time interval used for this COS inside the device.
18776 uint32_t queue_id5_max_bw;
18777 /* The bandwidth value. */
18778 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
18779 UINT32_C(0xfffffff)
18780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
18782 /* The granularity of the value (bits or bytes). */
18783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
18784 UINT32_C(0x10000000)
18785 /* Value is in bits. */
18786 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
18787 (UINT32_C(0x0) << 28)
18788 /* Value is in bytes. */
18789 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
18790 (UINT32_C(0x1) << 28)
18791 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
18792 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
18793 /* bw_value_unit is 3 b */
18794 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
18795 UINT32_C(0xe0000000)
18796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
18798 /* Value is in Mb or MB (base 10). */
18799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
18800 (UINT32_C(0x0) << 29)
18801 /* Value is in Kb or KB (base 10). */
18802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
18803 (UINT32_C(0x2) << 29)
18804 /* Value is in bits or bytes. */
18805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
18806 (UINT32_C(0x4) << 29)
18807 /* Value is in Gb or GB (base 10). */
18808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
18809 (UINT32_C(0x6) << 29)
18810 /* Value is in 1/100th of a percentage of total bandwidth. */
18811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18812 (UINT32_C(0x1) << 29)
18814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
18815 (UINT32_C(0x7) << 29)
18816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
18817 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
18818 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18819 uint8_t queue_id5_tsa_assign;
18820 /* Strict Priority */
18821 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
18823 /* Enhanced Transmission Selection */
18824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
18827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
18830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
18833 * Priority level for strict priority. Valid only when the
18834 * tsa_assign is 0 - Strict Priority (SP)
18835 * 0..7 - Valid values.
18836 * 8..255 - Reserved.
18838 uint8_t queue_id5_pri_lvl;
18840 * Weight used to allocate remaining BW for this COS after
18841 * servicing guaranteed bandwidths for all COS.
18843 uint8_t queue_id5_bw_weight;
18844 /* ID of CoS Queue 6. */
18847 * Minimum BW allocated to CoS Queue.
18848 * The HWRM will translate this value into byte counter and
18849 * time interval used for this COS inside the device.
18851 uint32_t queue_id6_min_bw;
18852 /* The bandwidth value. */
18853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
18854 UINT32_C(0xfffffff)
18855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
18857 /* The granularity of the value (bits or bytes). */
18858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
18859 UINT32_C(0x10000000)
18860 /* Value is in bits. */
18861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
18862 (UINT32_C(0x0) << 28)
18863 /* Value is in bytes. */
18864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
18865 (UINT32_C(0x1) << 28)
18866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
18867 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
18868 /* bw_value_unit is 3 b */
18869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
18870 UINT32_C(0xe0000000)
18871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
18873 /* Value is in Mb or MB (base 10). */
18874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
18875 (UINT32_C(0x0) << 29)
18876 /* Value is in Kb or KB (base 10). */
18877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
18878 (UINT32_C(0x2) << 29)
18879 /* Value is in bits or bytes. */
18880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
18881 (UINT32_C(0x4) << 29)
18882 /* Value is in Gb or GB (base 10). */
18883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
18884 (UINT32_C(0x6) << 29)
18885 /* Value is in 1/100th of a percentage of total bandwidth. */
18886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18887 (UINT32_C(0x1) << 29)
18889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
18890 (UINT32_C(0x7) << 29)
18891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
18892 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
18894 * Maximum BW allocated to CoS queue.
18895 * The HWRM will translate this value into byte counter and
18896 * time interval used for this COS inside the device.
18898 uint32_t queue_id6_max_bw;
18899 /* The bandwidth value. */
18900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
18901 UINT32_C(0xfffffff)
18902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
18904 /* The granularity of the value (bits or bytes). */
18905 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
18906 UINT32_C(0x10000000)
18907 /* Value is in bits. */
18908 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
18909 (UINT32_C(0x0) << 28)
18910 /* Value is in bytes. */
18911 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
18912 (UINT32_C(0x1) << 28)
18913 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
18914 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
18915 /* bw_value_unit is 3 b */
18916 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
18917 UINT32_C(0xe0000000)
18918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
18920 /* Value is in Mb or MB (base 10). */
18921 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
18922 (UINT32_C(0x0) << 29)
18923 /* Value is in Kb or KB (base 10). */
18924 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
18925 (UINT32_C(0x2) << 29)
18926 /* Value is in bits or bytes. */
18927 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
18928 (UINT32_C(0x4) << 29)
18929 /* Value is in Gb or GB (base 10). */
18930 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
18931 (UINT32_C(0x6) << 29)
18932 /* Value is in 1/100th of a percentage of total bandwidth. */
18933 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18934 (UINT32_C(0x1) << 29)
18936 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
18937 (UINT32_C(0x7) << 29)
18938 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
18939 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
18940 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18941 uint8_t queue_id6_tsa_assign;
18942 /* Strict Priority */
18943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
18945 /* Enhanced Transmission Selection */
18946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
18949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
18952 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
18955 * Priority level for strict priority. Valid only when the
18956 * tsa_assign is 0 - Strict Priority (SP)
18957 * 0..7 - Valid values.
18958 * 8..255 - Reserved.
18960 uint8_t queue_id6_pri_lvl;
18962 * Weight used to allocate remaining BW for this COS after
18963 * servicing guaranteed bandwidths for all COS.
18965 uint8_t queue_id6_bw_weight;
18966 /* ID of CoS Queue 7. */
18969 * Minimum BW allocated to CoS Queue.
18970 * The HWRM will translate this value into byte counter and
18971 * time interval used for this COS inside the device.
18973 uint32_t queue_id7_min_bw;
18974 /* The bandwidth value. */
18975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
18976 UINT32_C(0xfffffff)
18977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
18979 /* The granularity of the value (bits or bytes). */
18980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
18981 UINT32_C(0x10000000)
18982 /* Value is in bits. */
18983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
18984 (UINT32_C(0x0) << 28)
18985 /* Value is in bytes. */
18986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
18987 (UINT32_C(0x1) << 28)
18988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
18989 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
18990 /* bw_value_unit is 3 b */
18991 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
18992 UINT32_C(0xe0000000)
18993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
18995 /* Value is in Mb or MB (base 10). */
18996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
18997 (UINT32_C(0x0) << 29)
18998 /* Value is in Kb or KB (base 10). */
18999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
19000 (UINT32_C(0x2) << 29)
19001 /* Value is in bits or bytes. */
19002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
19003 (UINT32_C(0x4) << 29)
19004 /* Value is in Gb or GB (base 10). */
19005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
19006 (UINT32_C(0x6) << 29)
19007 /* Value is in 1/100th of a percentage of total bandwidth. */
19008 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19009 (UINT32_C(0x1) << 29)
19011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
19012 (UINT32_C(0x7) << 29)
19013 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
19014 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
19016 * Maximum BW allocated to CoS queue.
19017 * The HWRM will translate this value into byte counter and
19018 * time interval used for this COS inside the device.
19020 uint32_t queue_id7_max_bw;
19021 /* The bandwidth value. */
19022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
19023 UINT32_C(0xfffffff)
19024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
19026 /* The granularity of the value (bits or bytes). */
19027 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
19028 UINT32_C(0x10000000)
19029 /* Value is in bits. */
19030 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
19031 (UINT32_C(0x0) << 28)
19032 /* Value is in bytes. */
19033 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
19034 (UINT32_C(0x1) << 28)
19035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
19036 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
19037 /* bw_value_unit is 3 b */
19038 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
19039 UINT32_C(0xe0000000)
19040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
19042 /* Value is in Mb or MB (base 10). */
19043 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
19044 (UINT32_C(0x0) << 29)
19045 /* Value is in Kb or KB (base 10). */
19046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
19047 (UINT32_C(0x2) << 29)
19048 /* Value is in bits or bytes. */
19049 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
19050 (UINT32_C(0x4) << 29)
19051 /* Value is in Gb or GB (base 10). */
19052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
19053 (UINT32_C(0x6) << 29)
19054 /* Value is in 1/100th of a percentage of total bandwidth. */
19055 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19056 (UINT32_C(0x1) << 29)
19058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
19059 (UINT32_C(0x7) << 29)
19060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
19061 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
19062 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19063 uint8_t queue_id7_tsa_assign;
19064 /* Strict Priority */
19065 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
19067 /* Enhanced Transmission Selection */
19068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
19071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
19074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
19077 * Priority level for strict priority. Valid only when the
19078 * tsa_assign is 0 - Strict Priority (SP)
19079 * 0..7 - Valid values.
19080 * 8..255 - Reserved.
19082 uint8_t queue_id7_pri_lvl;
19084 * Weight used to allocate remaining BW for this COS after
19085 * servicing guaranteed bandwidths for all COS.
19087 uint8_t queue_id7_bw_weight;
19088 uint8_t unused_2[4];
19090 * This field is used in Output records to indicate that the output
19091 * is completely written to RAM. This field should be read as '1'
19092 * to indicate that the output has been completely written.
19093 * When writing a command completion or response to an internal processor,
19094 * the order of writes has to be such that this field is written last.
19097 } __attribute__((packed));
19099 /*************************
19100 * hwrm_queue_cos2bw_cfg *
19101 *************************/
19104 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
19105 struct hwrm_queue_cos2bw_cfg_input {
19106 /* The HWRM command request type. */
19109 * The completion ring to send the completion event on. This should
19110 * be the NQ ID returned from the `nq_alloc` HWRM command.
19112 uint16_t cmpl_ring;
19114 * The sequence ID is used by the driver for tracking multiple
19115 * commands. This ID is treated as opaque data by the firmware and
19116 * the value is returned in the `hwrm_resp_hdr` upon completion.
19120 * The target ID of the command:
19121 * * 0x0-0xFFF8 - The function ID
19122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19123 * * 0xFFFD - Reserved for user-space HWRM interface
19126 uint16_t target_id;
19128 * A physical address pointer pointing to a host buffer that the
19129 * command's response data will be written. This can be either a host
19130 * physical address (HPA) or a guest physical address (GPA) and must
19131 * point to a physically contiguous block of memory.
19133 uint64_t resp_addr;
19137 * If this bit is set to 1, then all queue_id0 related
19138 * parameters in this command are valid.
19140 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
19143 * If this bit is set to 1, then all queue_id1 related
19144 * parameters in this command are valid.
19146 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
19149 * If this bit is set to 1, then all queue_id2 related
19150 * parameters in this command are valid.
19152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
19155 * If this bit is set to 1, then all queue_id3 related
19156 * parameters in this command are valid.
19158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
19161 * If this bit is set to 1, then all queue_id4 related
19162 * parameters in this command are valid.
19164 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
19167 * If this bit is set to 1, then all queue_id5 related
19168 * parameters in this command are valid.
19170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
19173 * If this bit is set to 1, then all queue_id6 related
19174 * parameters in this command are valid.
19176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
19179 * If this bit is set to 1, then all queue_id7 related
19180 * parameters in this command are valid.
19182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
19185 * Port ID of port for which the table is being configured.
19186 * The HWRM needs to check whether this function is allowed
19187 * to configure TC BW assignment on this port.
19190 /* ID of CoS Queue 0. */
19194 * Minimum BW allocated to CoS Queue.
19195 * The HWRM will translate this value into byte counter and
19196 * time interval used for this COS inside the device.
19198 uint32_t queue_id0_min_bw;
19199 /* The bandwidth value. */
19200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
19201 UINT32_C(0xfffffff)
19202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
19204 /* The granularity of the value (bits or bytes). */
19205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
19206 UINT32_C(0x10000000)
19207 /* Value is in bits. */
19208 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
19209 (UINT32_C(0x0) << 28)
19210 /* Value is in bytes. */
19211 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
19212 (UINT32_C(0x1) << 28)
19213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
19214 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
19215 /* bw_value_unit is 3 b */
19216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
19217 UINT32_C(0xe0000000)
19218 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
19220 /* Value is in Mb or MB (base 10). */
19221 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
19222 (UINT32_C(0x0) << 29)
19223 /* Value is in Kb or KB (base 10). */
19224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
19225 (UINT32_C(0x2) << 29)
19226 /* Value is in bits or bytes. */
19227 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
19228 (UINT32_C(0x4) << 29)
19229 /* Value is in Gb or GB (base 10). */
19230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
19231 (UINT32_C(0x6) << 29)
19232 /* Value is in 1/100th of a percentage of total bandwidth. */
19233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19234 (UINT32_C(0x1) << 29)
19236 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
19237 (UINT32_C(0x7) << 29)
19238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
19239 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
19241 * Maximum BW allocated to CoS Queue.
19242 * The HWRM will translate this value into byte counter and
19243 * time interval used for this COS inside the device.
19245 uint32_t queue_id0_max_bw;
19246 /* The bandwidth value. */
19247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
19248 UINT32_C(0xfffffff)
19249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
19251 /* The granularity of the value (bits or bytes). */
19252 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
19253 UINT32_C(0x10000000)
19254 /* Value is in bits. */
19255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
19256 (UINT32_C(0x0) << 28)
19257 /* Value is in bytes. */
19258 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
19259 (UINT32_C(0x1) << 28)
19260 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
19261 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
19262 /* bw_value_unit is 3 b */
19263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
19264 UINT32_C(0xe0000000)
19265 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
19267 /* Value is in Mb or MB (base 10). */
19268 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
19269 (UINT32_C(0x0) << 29)
19270 /* Value is in Kb or KB (base 10). */
19271 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
19272 (UINT32_C(0x2) << 29)
19273 /* Value is in bits or bytes. */
19274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
19275 (UINT32_C(0x4) << 29)
19276 /* Value is in Gb or GB (base 10). */
19277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
19278 (UINT32_C(0x6) << 29)
19279 /* Value is in 1/100th of a percentage of total bandwidth. */
19280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19281 (UINT32_C(0x1) << 29)
19283 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
19284 (UINT32_C(0x7) << 29)
19285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
19286 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
19287 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19288 uint8_t queue_id0_tsa_assign;
19289 /* Strict Priority */
19290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
19292 /* Enhanced Transmission Selection */
19293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
19296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
19299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
19302 * Priority level for strict priority. Valid only when the
19303 * tsa_assign is 0 - Strict Priority (SP)
19304 * 0..7 - Valid values.
19305 * 8..255 - Reserved.
19307 uint8_t queue_id0_pri_lvl;
19309 * Weight used to allocate remaining BW for this COS after
19310 * servicing guaranteed bandwidths for all COS.
19312 uint8_t queue_id0_bw_weight;
19313 /* ID of CoS Queue 1. */
19316 * Minimum BW allocated to CoS Queue.
19317 * The HWRM will translate this value into byte counter and
19318 * time interval used for this COS inside the device.
19320 uint32_t queue_id1_min_bw;
19321 /* The bandwidth value. */
19322 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
19323 UINT32_C(0xfffffff)
19324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
19326 /* The granularity of the value (bits or bytes). */
19327 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
19328 UINT32_C(0x10000000)
19329 /* Value is in bits. */
19330 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
19331 (UINT32_C(0x0) << 28)
19332 /* Value is in bytes. */
19333 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
19334 (UINT32_C(0x1) << 28)
19335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
19336 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
19337 /* bw_value_unit is 3 b */
19338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
19339 UINT32_C(0xe0000000)
19340 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
19342 /* Value is in Mb or MB (base 10). */
19343 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
19344 (UINT32_C(0x0) << 29)
19345 /* Value is in Kb or KB (base 10). */
19346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
19347 (UINT32_C(0x2) << 29)
19348 /* Value is in bits or bytes. */
19349 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
19350 (UINT32_C(0x4) << 29)
19351 /* Value is in Gb or GB (base 10). */
19352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
19353 (UINT32_C(0x6) << 29)
19354 /* Value is in 1/100th of a percentage of total bandwidth. */
19355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19356 (UINT32_C(0x1) << 29)
19358 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
19359 (UINT32_C(0x7) << 29)
19360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
19361 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
19363 * Maximum BW allocated to CoS queue.
19364 * The HWRM will translate this value into byte counter and
19365 * time interval used for this COS inside the device.
19367 uint32_t queue_id1_max_bw;
19368 /* The bandwidth value. */
19369 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
19370 UINT32_C(0xfffffff)
19371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
19373 /* The granularity of the value (bits or bytes). */
19374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
19375 UINT32_C(0x10000000)
19376 /* Value is in bits. */
19377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
19378 (UINT32_C(0x0) << 28)
19379 /* Value is in bytes. */
19380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19381 (UINT32_C(0x1) << 28)
19382 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19383 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19384 /* bw_value_unit is 3 b */
19385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19386 UINT32_C(0xe0000000)
19387 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19389 /* Value is in Mb or MB (base 10). */
19390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19391 (UINT32_C(0x0) << 29)
19392 /* Value is in Kb or KB (base 10). */
19393 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19394 (UINT32_C(0x2) << 29)
19395 /* Value is in bits or bytes. */
19396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19397 (UINT32_C(0x4) << 29)
19398 /* Value is in Gb or GB (base 10). */
19399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19400 (UINT32_C(0x6) << 29)
19401 /* Value is in 1/100th of a percentage of total bandwidth. */
19402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19403 (UINT32_C(0x1) << 29)
19405 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19406 (UINT32_C(0x7) << 29)
19407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19408 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19409 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19410 uint8_t queue_id1_tsa_assign;
19411 /* Strict Priority */
19412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19414 /* Enhanced Transmission Selection */
19415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19424 * Priority level for strict priority. Valid only when the
19425 * tsa_assign is 0 - Strict Priority (SP)
19426 * 0..7 - Valid values.
19427 * 8..255 - Reserved.
19429 uint8_t queue_id1_pri_lvl;
19431 * Weight used to allocate remaining BW for this COS after
19432 * servicing guaranteed bandwidths for all COS.
19434 uint8_t queue_id1_bw_weight;
19435 /* ID of CoS Queue 2. */
19438 * Minimum BW allocated to CoS Queue.
19439 * The HWRM will translate this value into byte counter and
19440 * time interval used for this COS inside the device.
19442 uint32_t queue_id2_min_bw;
19443 /* The bandwidth value. */
19444 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19445 UINT32_C(0xfffffff)
19446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19448 /* The granularity of the value (bits or bytes). */
19449 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
19450 UINT32_C(0x10000000)
19451 /* Value is in bits. */
19452 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19453 (UINT32_C(0x0) << 28)
19454 /* Value is in bytes. */
19455 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19456 (UINT32_C(0x1) << 28)
19457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19458 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19459 /* bw_value_unit is 3 b */
19460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19461 UINT32_C(0xe0000000)
19462 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19464 /* Value is in Mb or MB (base 10). */
19465 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19466 (UINT32_C(0x0) << 29)
19467 /* Value is in Kb or KB (base 10). */
19468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19469 (UINT32_C(0x2) << 29)
19470 /* Value is in bits or bytes. */
19471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19472 (UINT32_C(0x4) << 29)
19473 /* Value is in Gb or GB (base 10). */
19474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19475 (UINT32_C(0x6) << 29)
19476 /* Value is in 1/100th of a percentage of total bandwidth. */
19477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19478 (UINT32_C(0x1) << 29)
19480 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19481 (UINT32_C(0x7) << 29)
19482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19483 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19485 * Maximum BW allocated to CoS queue.
19486 * The HWRM will translate this value into byte counter and
19487 * time interval used for this COS inside the device.
19489 uint32_t queue_id2_max_bw;
19490 /* The bandwidth value. */
19491 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19492 UINT32_C(0xfffffff)
19493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19495 /* The granularity of the value (bits or bytes). */
19496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
19497 UINT32_C(0x10000000)
19498 /* Value is in bits. */
19499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19500 (UINT32_C(0x0) << 28)
19501 /* Value is in bytes. */
19502 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19503 (UINT32_C(0x1) << 28)
19504 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19505 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19506 /* bw_value_unit is 3 b */
19507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19508 UINT32_C(0xe0000000)
19509 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19511 /* Value is in Mb or MB (base 10). */
19512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19513 (UINT32_C(0x0) << 29)
19514 /* Value is in Kb or KB (base 10). */
19515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19516 (UINT32_C(0x2) << 29)
19517 /* Value is in bits or bytes. */
19518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19519 (UINT32_C(0x4) << 29)
19520 /* Value is in Gb or GB (base 10). */
19521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19522 (UINT32_C(0x6) << 29)
19523 /* Value is in 1/100th of a percentage of total bandwidth. */
19524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19525 (UINT32_C(0x1) << 29)
19527 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19528 (UINT32_C(0x7) << 29)
19529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19530 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19531 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19532 uint8_t queue_id2_tsa_assign;
19533 /* Strict Priority */
19534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19536 /* Enhanced Transmission Selection */
19537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
19546 * Priority level for strict priority. Valid only when the
19547 * tsa_assign is 0 - Strict Priority (SP)
19548 * 0..7 - Valid values.
19549 * 8..255 - Reserved.
19551 uint8_t queue_id2_pri_lvl;
19553 * Weight used to allocate remaining BW for this COS after
19554 * servicing guaranteed bandwidths for all COS.
19556 uint8_t queue_id2_bw_weight;
19557 /* ID of CoS Queue 3. */
19560 * Minimum BW allocated to CoS Queue.
19561 * The HWRM will translate this value into byte counter and
19562 * time interval used for this COS inside the device.
19564 uint32_t queue_id3_min_bw;
19565 /* The bandwidth value. */
19566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
19567 UINT32_C(0xfffffff)
19568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
19570 /* The granularity of the value (bits or bytes). */
19571 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
19572 UINT32_C(0x10000000)
19573 /* Value is in bits. */
19574 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
19575 (UINT32_C(0x0) << 28)
19576 /* Value is in bytes. */
19577 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
19578 (UINT32_C(0x1) << 28)
19579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
19580 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
19581 /* bw_value_unit is 3 b */
19582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
19583 UINT32_C(0xe0000000)
19584 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
19586 /* Value is in Mb or MB (base 10). */
19587 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
19588 (UINT32_C(0x0) << 29)
19589 /* Value is in Kb or KB (base 10). */
19590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
19591 (UINT32_C(0x2) << 29)
19592 /* Value is in bits or bytes. */
19593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
19594 (UINT32_C(0x4) << 29)
19595 /* Value is in Gb or GB (base 10). */
19596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
19597 (UINT32_C(0x6) << 29)
19598 /* Value is in 1/100th of a percentage of total bandwidth. */
19599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19600 (UINT32_C(0x1) << 29)
19602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
19603 (UINT32_C(0x7) << 29)
19604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
19605 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
19607 * Maximum BW allocated to CoS queue.
19608 * The HWRM will translate this value into byte counter and
19609 * time interval used for this COS inside the device.
19611 uint32_t queue_id3_max_bw;
19612 /* The bandwidth value. */
19613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
19614 UINT32_C(0xfffffff)
19615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
19617 /* The granularity of the value (bits or bytes). */
19618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
19619 UINT32_C(0x10000000)
19620 /* Value is in bits. */
19621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
19622 (UINT32_C(0x0) << 28)
19623 /* Value is in bytes. */
19624 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
19625 (UINT32_C(0x1) << 28)
19626 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
19627 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
19628 /* bw_value_unit is 3 b */
19629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
19630 UINT32_C(0xe0000000)
19631 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
19633 /* Value is in Mb or MB (base 10). */
19634 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
19635 (UINT32_C(0x0) << 29)
19636 /* Value is in Kb or KB (base 10). */
19637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
19638 (UINT32_C(0x2) << 29)
19639 /* Value is in bits or bytes. */
19640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
19641 (UINT32_C(0x4) << 29)
19642 /* Value is in Gb or GB (base 10). */
19643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
19644 (UINT32_C(0x6) << 29)
19645 /* Value is in 1/100th of a percentage of total bandwidth. */
19646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19647 (UINT32_C(0x1) << 29)
19649 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
19650 (UINT32_C(0x7) << 29)
19651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
19652 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
19653 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19654 uint8_t queue_id3_tsa_assign;
19655 /* Strict Priority */
19656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
19658 /* Enhanced Transmission Selection */
19659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
19662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
19665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
19668 * Priority level for strict priority. Valid only when the
19669 * tsa_assign is 0 - Strict Priority (SP)
19670 * 0..7 - Valid values.
19671 * 8..255 - Reserved.
19673 uint8_t queue_id3_pri_lvl;
19675 * Weight used to allocate remaining BW for this COS after
19676 * servicing guaranteed bandwidths for all COS.
19678 uint8_t queue_id3_bw_weight;
19679 /* ID of CoS Queue 4. */
19682 * Minimum BW allocated to CoS Queue.
19683 * The HWRM will translate this value into byte counter and
19684 * time interval used for this COS inside the device.
19686 uint32_t queue_id4_min_bw;
19687 /* The bandwidth value. */
19688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
19689 UINT32_C(0xfffffff)
19690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
19692 /* The granularity of the value (bits or bytes). */
19693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
19694 UINT32_C(0x10000000)
19695 /* Value is in bits. */
19696 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
19697 (UINT32_C(0x0) << 28)
19698 /* Value is in bytes. */
19699 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
19700 (UINT32_C(0x1) << 28)
19701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
19702 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
19703 /* bw_value_unit is 3 b */
19704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
19705 UINT32_C(0xe0000000)
19706 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
19708 /* Value is in Mb or MB (base 10). */
19709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
19710 (UINT32_C(0x0) << 29)
19711 /* Value is in Kb or KB (base 10). */
19712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
19713 (UINT32_C(0x2) << 29)
19714 /* Value is in bits or bytes. */
19715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
19716 (UINT32_C(0x4) << 29)
19717 /* Value is in Gb or GB (base 10). */
19718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
19719 (UINT32_C(0x6) << 29)
19720 /* Value is in 1/100th of a percentage of total bandwidth. */
19721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19722 (UINT32_C(0x1) << 29)
19724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
19725 (UINT32_C(0x7) << 29)
19726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
19727 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
19729 * Maximum BW allocated to CoS queue.
19730 * The HWRM will translate this value into byte counter and
19731 * time interval used for this COS inside the device.
19733 uint32_t queue_id4_max_bw;
19734 /* The bandwidth value. */
19735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
19736 UINT32_C(0xfffffff)
19737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
19739 /* The granularity of the value (bits or bytes). */
19740 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
19741 UINT32_C(0x10000000)
19742 /* Value is in bits. */
19743 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
19744 (UINT32_C(0x0) << 28)
19745 /* Value is in bytes. */
19746 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
19747 (UINT32_C(0x1) << 28)
19748 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
19749 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
19750 /* bw_value_unit is 3 b */
19751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
19752 UINT32_C(0xe0000000)
19753 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
19755 /* Value is in Mb or MB (base 10). */
19756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
19757 (UINT32_C(0x0) << 29)
19758 /* Value is in Kb or KB (base 10). */
19759 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
19760 (UINT32_C(0x2) << 29)
19761 /* Value is in bits or bytes. */
19762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
19763 (UINT32_C(0x4) << 29)
19764 /* Value is in Gb or GB (base 10). */
19765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
19766 (UINT32_C(0x6) << 29)
19767 /* Value is in 1/100th of a percentage of total bandwidth. */
19768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19769 (UINT32_C(0x1) << 29)
19771 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
19772 (UINT32_C(0x7) << 29)
19773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
19774 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
19775 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19776 uint8_t queue_id4_tsa_assign;
19777 /* Strict Priority */
19778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
19780 /* Enhanced Transmission Selection */
19781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
19784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
19787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
19790 * Priority level for strict priority. Valid only when the
19791 * tsa_assign is 0 - Strict Priority (SP)
19792 * 0..7 - Valid values.
19793 * 8..255 - Reserved.
19795 uint8_t queue_id4_pri_lvl;
19797 * Weight used to allocate remaining BW for this COS after
19798 * servicing guaranteed bandwidths for all COS.
19800 uint8_t queue_id4_bw_weight;
19801 /* ID of CoS Queue 5. */
19804 * Minimum BW allocated to CoS Queue.
19805 * The HWRM will translate this value into byte counter and
19806 * time interval used for this COS inside the device.
19808 uint32_t queue_id5_min_bw;
19809 /* The bandwidth value. */
19810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
19811 UINT32_C(0xfffffff)
19812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
19814 /* The granularity of the value (bits or bytes). */
19815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
19816 UINT32_C(0x10000000)
19817 /* Value is in bits. */
19818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
19819 (UINT32_C(0x0) << 28)
19820 /* Value is in bytes. */
19821 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
19822 (UINT32_C(0x1) << 28)
19823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
19824 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
19825 /* bw_value_unit is 3 b */
19826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
19827 UINT32_C(0xe0000000)
19828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
19830 /* Value is in Mb or MB (base 10). */
19831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
19832 (UINT32_C(0x0) << 29)
19833 /* Value is in Kb or KB (base 10). */
19834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
19835 (UINT32_C(0x2) << 29)
19836 /* Value is in bits or bytes. */
19837 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
19838 (UINT32_C(0x4) << 29)
19839 /* Value is in Gb or GB (base 10). */
19840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
19841 (UINT32_C(0x6) << 29)
19842 /* Value is in 1/100th of a percentage of total bandwidth. */
19843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19844 (UINT32_C(0x1) << 29)
19846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
19847 (UINT32_C(0x7) << 29)
19848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
19849 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
19851 * Maximum BW allocated to CoS queue.
19852 * The HWRM will translate this value into byte counter and
19853 * time interval used for this COS inside the device.
19855 uint32_t queue_id5_max_bw;
19856 /* The bandwidth value. */
19857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
19858 UINT32_C(0xfffffff)
19859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
19861 /* The granularity of the value (bits or bytes). */
19862 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
19863 UINT32_C(0x10000000)
19864 /* Value is in bits. */
19865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
19866 (UINT32_C(0x0) << 28)
19867 /* Value is in bytes. */
19868 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
19869 (UINT32_C(0x1) << 28)
19870 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
19871 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
19872 /* bw_value_unit is 3 b */
19873 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
19874 UINT32_C(0xe0000000)
19875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
19877 /* Value is in Mb or MB (base 10). */
19878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
19879 (UINT32_C(0x0) << 29)
19880 /* Value is in Kb or KB (base 10). */
19881 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
19882 (UINT32_C(0x2) << 29)
19883 /* Value is in bits or bytes. */
19884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
19885 (UINT32_C(0x4) << 29)
19886 /* Value is in Gb or GB (base 10). */
19887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
19888 (UINT32_C(0x6) << 29)
19889 /* Value is in 1/100th of a percentage of total bandwidth. */
19890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19891 (UINT32_C(0x1) << 29)
19893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
19894 (UINT32_C(0x7) << 29)
19895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
19896 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
19897 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19898 uint8_t queue_id5_tsa_assign;
19899 /* Strict Priority */
19900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
19902 /* Enhanced Transmission Selection */
19903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
19906 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
19909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
19912 * Priority level for strict priority. Valid only when the
19913 * tsa_assign is 0 - Strict Priority (SP)
19914 * 0..7 - Valid values.
19915 * 8..255 - Reserved.
19917 uint8_t queue_id5_pri_lvl;
19919 * Weight used to allocate remaining BW for this COS after
19920 * servicing guaranteed bandwidths for all COS.
19922 uint8_t queue_id5_bw_weight;
19923 /* ID of CoS Queue 6. */
19926 * Minimum BW allocated to CoS Queue.
19927 * The HWRM will translate this value into byte counter and
19928 * time interval used for this COS inside the device.
19930 uint32_t queue_id6_min_bw;
19931 /* The bandwidth value. */
19932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
19933 UINT32_C(0xfffffff)
19934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
19936 /* The granularity of the value (bits or bytes). */
19937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
19938 UINT32_C(0x10000000)
19939 /* Value is in bits. */
19940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
19941 (UINT32_C(0x0) << 28)
19942 /* Value is in bytes. */
19943 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
19944 (UINT32_C(0x1) << 28)
19945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
19946 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
19947 /* bw_value_unit is 3 b */
19948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
19949 UINT32_C(0xe0000000)
19950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
19952 /* Value is in Mb or MB (base 10). */
19953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
19954 (UINT32_C(0x0) << 29)
19955 /* Value is in Kb or KB (base 10). */
19956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
19957 (UINT32_C(0x2) << 29)
19958 /* Value is in bits or bytes. */
19959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
19960 (UINT32_C(0x4) << 29)
19961 /* Value is in Gb or GB (base 10). */
19962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
19963 (UINT32_C(0x6) << 29)
19964 /* Value is in 1/100th of a percentage of total bandwidth. */
19965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19966 (UINT32_C(0x1) << 29)
19968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
19969 (UINT32_C(0x7) << 29)
19970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
19971 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
19973 * Maximum BW allocated to CoS queue.
19974 * The HWRM will translate this value into byte counter and
19975 * time interval used for this COS inside the device.
19977 uint32_t queue_id6_max_bw;
19978 /* The bandwidth value. */
19979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
19980 UINT32_C(0xfffffff)
19981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
19983 /* The granularity of the value (bits or bytes). */
19984 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
19985 UINT32_C(0x10000000)
19986 /* Value is in bits. */
19987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
19988 (UINT32_C(0x0) << 28)
19989 /* Value is in bytes. */
19990 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
19991 (UINT32_C(0x1) << 28)
19992 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
19993 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
19994 /* bw_value_unit is 3 b */
19995 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
19996 UINT32_C(0xe0000000)
19997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
19999 /* Value is in Mb or MB (base 10). */
20000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
20001 (UINT32_C(0x0) << 29)
20002 /* Value is in Kb or KB (base 10). */
20003 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
20004 (UINT32_C(0x2) << 29)
20005 /* Value is in bits or bytes. */
20006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
20007 (UINT32_C(0x4) << 29)
20008 /* Value is in Gb or GB (base 10). */
20009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
20010 (UINT32_C(0x6) << 29)
20011 /* Value is in 1/100th of a percentage of total bandwidth. */
20012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20013 (UINT32_C(0x1) << 29)
20015 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
20016 (UINT32_C(0x7) << 29)
20017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
20018 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
20019 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20020 uint8_t queue_id6_tsa_assign;
20021 /* Strict Priority */
20022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
20024 /* Enhanced Transmission Selection */
20025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
20028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
20031 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
20034 * Priority level for strict priority. Valid only when the
20035 * tsa_assign is 0 - Strict Priority (SP)
20036 * 0..7 - Valid values.
20037 * 8..255 - Reserved.
20039 uint8_t queue_id6_pri_lvl;
20041 * Weight used to allocate remaining BW for this COS after
20042 * servicing guaranteed bandwidths for all COS.
20044 uint8_t queue_id6_bw_weight;
20045 /* ID of CoS Queue 7. */
20048 * Minimum BW allocated to CoS Queue.
20049 * The HWRM will translate this value into byte counter and
20050 * time interval used for this COS inside the device.
20052 uint32_t queue_id7_min_bw;
20053 /* The bandwidth value. */
20054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
20055 UINT32_C(0xfffffff)
20056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
20058 /* The granularity of the value (bits or bytes). */
20059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
20060 UINT32_C(0x10000000)
20061 /* Value is in bits. */
20062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
20063 (UINT32_C(0x0) << 28)
20064 /* Value is in bytes. */
20065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
20066 (UINT32_C(0x1) << 28)
20067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
20068 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
20069 /* bw_value_unit is 3 b */
20070 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
20071 UINT32_C(0xe0000000)
20072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
20074 /* Value is in Mb or MB (base 10). */
20075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
20076 (UINT32_C(0x0) << 29)
20077 /* Value is in Kb or KB (base 10). */
20078 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
20079 (UINT32_C(0x2) << 29)
20080 /* Value is in bits or bytes. */
20081 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
20082 (UINT32_C(0x4) << 29)
20083 /* Value is in Gb or GB (base 10). */
20084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
20085 (UINT32_C(0x6) << 29)
20086 /* Value is in 1/100th of a percentage of total bandwidth. */
20087 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20088 (UINT32_C(0x1) << 29)
20090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
20091 (UINT32_C(0x7) << 29)
20092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
20093 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
20095 * Maximum BW allocated to CoS queue.
20096 * The HWRM will translate this value into byte counter and
20097 * time interval used for this COS inside the device.
20099 uint32_t queue_id7_max_bw;
20100 /* The bandwidth value. */
20101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
20102 UINT32_C(0xfffffff)
20103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
20105 /* The granularity of the value (bits or bytes). */
20106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
20107 UINT32_C(0x10000000)
20108 /* Value is in bits. */
20109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
20110 (UINT32_C(0x0) << 28)
20111 /* Value is in bytes. */
20112 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
20113 (UINT32_C(0x1) << 28)
20114 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
20115 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
20116 /* bw_value_unit is 3 b */
20117 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
20118 UINT32_C(0xe0000000)
20119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
20121 /* Value is in Mb or MB (base 10). */
20122 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
20123 (UINT32_C(0x0) << 29)
20124 /* Value is in Kb or KB (base 10). */
20125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
20126 (UINT32_C(0x2) << 29)
20127 /* Value is in bits or bytes. */
20128 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
20129 (UINT32_C(0x4) << 29)
20130 /* Value is in Gb or GB (base 10). */
20131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
20132 (UINT32_C(0x6) << 29)
20133 /* Value is in 1/100th of a percentage of total bandwidth. */
20134 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20135 (UINT32_C(0x1) << 29)
20137 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
20138 (UINT32_C(0x7) << 29)
20139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
20140 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
20141 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20142 uint8_t queue_id7_tsa_assign;
20143 /* Strict Priority */
20144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
20146 /* Enhanced Transmission Selection */
20147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
20150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
20153 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
20156 * Priority level for strict priority. Valid only when the
20157 * tsa_assign is 0 - Strict Priority (SP)
20158 * 0..7 - Valid values.
20159 * 8..255 - Reserved.
20161 uint8_t queue_id7_pri_lvl;
20163 * Weight used to allocate remaining BW for this COS after
20164 * servicing guaranteed bandwidths for all COS.
20166 uint8_t queue_id7_bw_weight;
20167 uint8_t unused_1[5];
20168 } __attribute__((packed));
20170 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
20171 struct hwrm_queue_cos2bw_cfg_output {
20172 /* The specific error status for the command. */
20173 uint16_t error_code;
20174 /* The HWRM command request type. */
20176 /* The sequence ID from the original command. */
20178 /* The length of the response data in number of bytes. */
20180 uint8_t unused_0[7];
20182 * This field is used in Output records to indicate that the output
20183 * is completely written to RAM. This field should be read as '1'
20184 * to indicate that the output has been completely written.
20185 * When writing a command completion or response to an internal processor,
20186 * the order of writes has to be such that this field is written last.
20189 } __attribute__((packed));
20191 /*******************
20192 * hwrm_vnic_alloc *
20193 *******************/
20196 /* hwrm_vnic_alloc_input (size:192b/24B) */
20197 struct hwrm_vnic_alloc_input {
20198 /* The HWRM command request type. */
20201 * The completion ring to send the completion event on. This should
20202 * be the NQ ID returned from the `nq_alloc` HWRM command.
20204 uint16_t cmpl_ring;
20206 * The sequence ID is used by the driver for tracking multiple
20207 * commands. This ID is treated as opaque data by the firmware and
20208 * the value is returned in the `hwrm_resp_hdr` upon completion.
20212 * The target ID of the command:
20213 * * 0x0-0xFFF8 - The function ID
20214 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20215 * * 0xFFFD - Reserved for user-space HWRM interface
20218 uint16_t target_id;
20220 * A physical address pointer pointing to a host buffer that the
20221 * command's response data will be written. This can be either a host
20222 * physical address (HPA) or a guest physical address (GPA) and must
20223 * point to a physically contiguous block of memory.
20225 uint64_t resp_addr;
20228 * When this bit is '1', this VNIC is requested to
20229 * be the default VNIC for this function.
20231 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
20232 uint8_t unused_0[4];
20233 } __attribute__((packed));
20235 /* hwrm_vnic_alloc_output (size:128b/16B) */
20236 struct hwrm_vnic_alloc_output {
20237 /* The specific error status for the command. */
20238 uint16_t error_code;
20239 /* The HWRM command request type. */
20241 /* The sequence ID from the original command. */
20243 /* The length of the response data in number of bytes. */
20245 /* Logical vnic ID */
20247 uint8_t unused_0[3];
20249 * This field is used in Output records to indicate that the output
20250 * is completely written to RAM. This field should be read as '1'
20251 * to indicate that the output has been completely written.
20252 * When writing a command completion or response to an internal processor,
20253 * the order of writes has to be such that this field is written last.
20256 } __attribute__((packed));
20258 /******************
20260 ******************/
20263 /* hwrm_vnic_free_input (size:192b/24B) */
20264 struct hwrm_vnic_free_input {
20265 /* The HWRM command request type. */
20268 * The completion ring to send the completion event on. This should
20269 * be the NQ ID returned from the `nq_alloc` HWRM command.
20271 uint16_t cmpl_ring;
20273 * The sequence ID is used by the driver for tracking multiple
20274 * commands. This ID is treated as opaque data by the firmware and
20275 * the value is returned in the `hwrm_resp_hdr` upon completion.
20279 * The target ID of the command:
20280 * * 0x0-0xFFF8 - The function ID
20281 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20282 * * 0xFFFD - Reserved for user-space HWRM interface
20285 uint16_t target_id;
20287 * A physical address pointer pointing to a host buffer that the
20288 * command's response data will be written. This can be either a host
20289 * physical address (HPA) or a guest physical address (GPA) and must
20290 * point to a physically contiguous block of memory.
20292 uint64_t resp_addr;
20293 /* Logical vnic ID */
20295 uint8_t unused_0[4];
20296 } __attribute__((packed));
20298 /* hwrm_vnic_free_output (size:128b/16B) */
20299 struct hwrm_vnic_free_output {
20300 /* The specific error status for the command. */
20301 uint16_t error_code;
20302 /* The HWRM command request type. */
20304 /* The sequence ID from the original command. */
20306 /* The length of the response data in number of bytes. */
20308 uint8_t unused_0[7];
20310 * This field is used in Output records to indicate that the output
20311 * is completely written to RAM. This field should be read as '1'
20312 * to indicate that the output has been completely written.
20313 * When writing a command completion or response to an internal processor,
20314 * the order of writes has to be such that this field is written last.
20317 } __attribute__((packed));
20324 /* hwrm_vnic_cfg_input (size:320b/40B) */
20325 struct hwrm_vnic_cfg_input {
20326 /* The HWRM command request type. */
20329 * The completion ring to send the completion event on. This should
20330 * be the NQ ID returned from the `nq_alloc` HWRM command.
20332 uint16_t cmpl_ring;
20334 * The sequence ID is used by the driver for tracking multiple
20335 * commands. This ID is treated as opaque data by the firmware and
20336 * the value is returned in the `hwrm_resp_hdr` upon completion.
20340 * The target ID of the command:
20341 * * 0x0-0xFFF8 - The function ID
20342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20343 * * 0xFFFD - Reserved for user-space HWRM interface
20346 uint16_t target_id;
20348 * A physical address pointer pointing to a host buffer that the
20349 * command's response data will be written. This can be either a host
20350 * physical address (HPA) or a guest physical address (GPA) and must
20351 * point to a physically contiguous block of memory.
20353 uint64_t resp_addr;
20356 * When this bit is '1', the VNIC is requested to
20357 * be the default VNIC for the function.
20359 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
20362 * When this bit is '1', the VNIC is being configured to
20363 * strip VLAN in the RX path.
20364 * If set to '0', then VLAN stripping is disabled on
20367 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
20370 * When this bit is '1', the VNIC is being configured to
20371 * buffer receive packets in the hardware until the host
20372 * posts new receive buffers.
20373 * If set to '0', then bd_stall is being configured to be
20374 * disabled on this VNIC.
20376 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
20379 * When this bit is '1', the VNIC is being configured to
20380 * receive both RoCE and non-RoCE traffic.
20381 * If set to '0', then this VNIC is not configured to be
20382 * operating in dual VNIC mode.
20384 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
20387 * When this flag is set to '1', the VNIC is requested to
20388 * be configured to receive only RoCE traffic.
20389 * If this flag is set to '0', then this flag shall be
20390 * ignored by the HWRM.
20391 * If roce_dual_vnic_mode flag is set to '1'
20392 * or roce_mirroring_capable_vnic_mode flag to 1,
20393 * then the HWRM client shall not set this flag to '1'.
20395 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
20398 * When a VNIC uses one destination ring group for certain
20399 * application (e.g. Receive Flow Steering) where
20400 * exact match is used to direct packets to a VNIC with one
20401 * destination ring group only, there is no need to configure
20402 * RSS indirection table for that VNIC as only one destination
20403 * ring group is used.
20405 * This flag is used to enable a mode where
20406 * RSS is enabled in the VNIC using a RSS context
20407 * for computing RSS hash but the RSS indirection table is
20408 * not configured using hwrm_vnic_rss_cfg.
20410 * If this mode is enabled, then the driver should not program
20411 * RSS indirection table for the RSS context that is used for
20412 * computing RSS hash only.
20414 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
20417 * When this bit is '1', the VNIC is being configured to
20418 * receive both RoCE and non-RoCE traffic, but forward only the
20419 * RoCE traffic further. Also, RoCE traffic can be mirrored to
20422 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
20426 * This bit must be '1' for the dflt_ring_grp field to be
20429 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
20432 * This bit must be '1' for the rss_rule field to be
20435 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
20438 * This bit must be '1' for the cos_rule field to be
20441 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
20444 * This bit must be '1' for the lb_rule field to be
20447 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
20450 * This bit must be '1' for the mru field to be
20453 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
20456 * This bit must be '1' for the default_rx_ring_id field to be
20459 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
20462 * This bit must be '1' for the default_cmpl_ring_id field to be
20465 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
20467 /* Logical vnic ID */
20470 * Default Completion ring for the VNIC. This ring will
20471 * be chosen if packet does not match any RSS rules and if
20472 * there is no COS rule.
20474 uint16_t dflt_ring_grp;
20476 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
20477 * there is no RSS rule.
20481 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
20482 * there is no COS rule.
20486 * RSS ID for load balancing rule/table structure.
20487 * 0xFF... (All Fs) if there is no LB rule.
20491 * The maximum receive unit of the vnic.
20492 * Each vnic is associated with a function.
20493 * The vnic mru value overwrites the mru setting of the
20494 * associated function.
20495 * The HWRM shall make sure that vnic mru does not exceed
20496 * the mru of the port the function is associated with.
20500 * Default Rx ring for the VNIC. This ring will
20501 * be chosen if packet does not match any RSS rules.
20502 * The aggregation ring associated with the Rx ring is
20503 * implied based on the Rx ring specified when the
20504 * aggregation ring was allocated.
20506 uint16_t default_rx_ring_id;
20508 * Default completion ring for the VNIC. This ring will
20509 * be chosen if packet does not match any RSS rules.
20511 uint16_t default_cmpl_ring_id;
20512 } __attribute__((packed));
20514 /* hwrm_vnic_cfg_output (size:128b/16B) */
20515 struct hwrm_vnic_cfg_output {
20516 /* The specific error status for the command. */
20517 uint16_t error_code;
20518 /* The HWRM command request type. */
20520 /* The sequence ID from the original command. */
20522 /* The length of the response data in number of bytes. */
20524 uint8_t unused_0[7];
20526 * This field is used in Output records to indicate that the output
20527 * is completely written to RAM. This field should be read as '1'
20528 * to indicate that the output has been completely written.
20529 * When writing a command completion or response to an internal processor,
20530 * the order of writes has to be such that this field is written last.
20533 } __attribute__((packed));
20535 /******************
20537 ******************/
20540 /* hwrm_vnic_qcfg_input (size:256b/32B) */
20541 struct hwrm_vnic_qcfg_input {
20542 /* The HWRM command request type. */
20545 * The completion ring to send the completion event on. This should
20546 * be the NQ ID returned from the `nq_alloc` HWRM command.
20548 uint16_t cmpl_ring;
20550 * The sequence ID is used by the driver for tracking multiple
20551 * commands. This ID is treated as opaque data by the firmware and
20552 * the value is returned in the `hwrm_resp_hdr` upon completion.
20556 * The target ID of the command:
20557 * * 0x0-0xFFF8 - The function ID
20558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20559 * * 0xFFFD - Reserved for user-space HWRM interface
20562 uint16_t target_id;
20564 * A physical address pointer pointing to a host buffer that the
20565 * command's response data will be written. This can be either a host
20566 * physical address (HPA) or a guest physical address (GPA) and must
20567 * point to a physically contiguous block of memory.
20569 uint64_t resp_addr;
20572 * This bit must be '1' for the vf_id_valid field to be
20575 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
20576 /* Logical vnic ID */
20578 /* ID of Virtual Function whose VNIC resource is being queried. */
20580 uint8_t unused_0[6];
20581 } __attribute__((packed));
20583 /* hwrm_vnic_qcfg_output (size:256b/32B) */
20584 struct hwrm_vnic_qcfg_output {
20585 /* The specific error status for the command. */
20586 uint16_t error_code;
20587 /* The HWRM command request type. */
20589 /* The sequence ID from the original command. */
20591 /* The length of the response data in number of bytes. */
20593 /* Default Completion ring for the VNIC. */
20594 uint16_t dflt_ring_grp;
20596 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
20597 * there is no RSS rule.
20601 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
20602 * there is no COS rule.
20606 * RSS ID for load balancing rule/table structure.
20607 * 0xFF... (All Fs) if there is no LB rule.
20610 /* The maximum receive unit of the vnic. */
20612 uint8_t unused_0[2];
20615 * When this bit is '1', the VNIC is the default VNIC for
20618 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
20621 * When this bit is '1', the VNIC is configured to
20622 * strip VLAN in the RX path.
20623 * If set to '0', then VLAN stripping is disabled on
20626 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
20629 * When this bit is '1', the VNIC is configured to
20630 * buffer receive packets in the hardware until the host
20631 * posts new receive buffers.
20632 * If set to '0', then bd_stall is disabled on
20635 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
20638 * When this bit is '1', the VNIC is configured to
20639 * receive both RoCE and non-RoCE traffic.
20640 * If set to '0', then this VNIC is not configured to
20641 * operate in dual VNIC mode.
20643 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
20646 * When this flag is set to '1', the VNIC is configured to
20647 * receive only RoCE traffic.
20648 * When this flag is set to '0', the VNIC is not configured
20649 * to receive only RoCE traffic.
20650 * If roce_dual_vnic_mode flag and this flag both are set
20651 * to '1', then it is an invalid configuration of the
20652 * VNIC. The HWRM should not allow that type of
20653 * mis-configuration by HWRM clients.
20655 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
20658 * When a VNIC uses one destination ring group for certain
20659 * application (e.g. Receive Flow Steering) where
20660 * exact match is used to direct packets to a VNIC with one
20661 * destination ring group only, there is no need to configure
20662 * RSS indirection table for that VNIC as only one destination
20663 * ring group is used.
20665 * When this bit is set to '1', then the VNIC is enabled in a
20666 * mode where RSS is enabled in the VNIC using a RSS context
20667 * for computing RSS hash but the RSS indirection table is
20670 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
20673 * When this bit is '1', the VNIC is configured to
20674 * receive both RoCE and non-RoCE traffic, but forward only
20675 * RoCE traffic further. Also RoCE traffic can be mirrored to
20678 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
20680 uint8_t unused_1[7];
20682 * This field is used in Output records to indicate that the output
20683 * is completely written to RAM. This field should be read as '1'
20684 * to indicate that the output has been completely written.
20685 * When writing a command completion or response to an internal processor,
20686 * the order of writes has to be such that this field is written last.
20689 } __attribute__((packed));
20691 /*******************
20692 * hwrm_vnic_qcaps *
20693 *******************/
20696 /* hwrm_vnic_qcaps_input (size:192b/24B) */
20697 struct hwrm_vnic_qcaps_input {
20698 /* The HWRM command request type. */
20701 * The completion ring to send the completion event on. This should
20702 * be the NQ ID returned from the `nq_alloc` HWRM command.
20704 uint16_t cmpl_ring;
20706 * The sequence ID is used by the driver for tracking multiple
20707 * commands. This ID is treated as opaque data by the firmware and
20708 * the value is returned in the `hwrm_resp_hdr` upon completion.
20712 * The target ID of the command:
20713 * * 0x0-0xFFF8 - The function ID
20714 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20715 * * 0xFFFD - Reserved for user-space HWRM interface
20718 uint16_t target_id;
20720 * A physical address pointer pointing to a host buffer that the
20721 * command's response data will be written. This can be either a host
20722 * physical address (HPA) or a guest physical address (GPA) and must
20723 * point to a physically contiguous block of memory.
20725 uint64_t resp_addr;
20727 uint8_t unused_0[4];
20728 } __attribute__((packed));
20730 /* hwrm_vnic_qcaps_output (size:192b/24B) */
20731 struct hwrm_vnic_qcaps_output {
20732 /* The specific error status for the command. */
20733 uint16_t error_code;
20734 /* The HWRM command request type. */
20736 /* The sequence ID from the original command. */
20738 /* The length of the response data in number of bytes. */
20740 /* The maximum receive unit that is settable on a vnic. */
20742 uint8_t unused_0[2];
20745 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
20748 * When this bit is '1', the capability of stripping VLAN in
20749 * the RX path is supported on VNIC(s).
20750 * If set to '0', then VLAN stripping capability is
20751 * not supported on VNIC(s).
20753 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
20756 * When this bit is '1', the capability to buffer receive
20757 * packets in the hardware until the host posts new receive buffers
20758 * is supported on VNIC(s).
20759 * If set to '0', then bd_stall capability is not supported
20762 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
20765 * When this bit is '1', the capability to
20766 * receive both RoCE and non-RoCE traffic on VNIC(s) is
20768 * If set to '0', then the capability to receive
20769 * both RoCE and non-RoCE traffic on VNIC(s) is
20772 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
20775 * When this bit is set to '1', the capability to configure
20776 * a VNIC to receive only RoCE traffic is supported.
20777 * When this flag is set to '0', the VNIC capability to
20778 * configure to receive only RoCE traffic is not supported.
20780 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
20783 * When this bit is set to '1', then the capability to enable
20784 * a VNIC in a mode where RSS context without configuring
20785 * RSS indirection table is supported (for RSS hash computation).
20786 * When this bit is set to '0', then a VNIC can not be configured
20787 * with a mode to enable RSS context without configuring RSS
20788 * indirection table.
20790 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
20793 * When this bit is '1', the capability to
20794 * mirror the the RoCE traffic is supported.
20795 * If set to '0', then the capability to mirror the
20796 * RoCE traffic is not supported.
20798 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
20801 * When this bit is '1', the outermost RSS hashing capability
20802 * is supported. If set to '0', then the outermost RSS hashing
20803 * capability is not supported.
20805 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
20808 * This field advertises the maximum concurrent TPA aggregations
20809 * supported by the VNIC on new devices that support TPA v2.
20810 * '0' means that TPA v2 is not supported.
20812 uint16_t max_aggs_supported;
20813 uint8_t unused_1[5];
20815 * This field is used in Output records to indicate that the output
20816 * is completely written to RAM. This field should be read as '1'
20817 * to indicate that the output has been completely written.
20818 * When writing a command completion or response to an internal processor,
20819 * the order of writes has to be such that this field is written last.
20822 } __attribute__((packed));
20824 /*********************
20825 * hwrm_vnic_tpa_cfg *
20826 *********************/
20829 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
20830 struct hwrm_vnic_tpa_cfg_input {
20831 /* The HWRM command request type. */
20834 * The completion ring to send the completion event on. This should
20835 * be the NQ ID returned from the `nq_alloc` HWRM command.
20837 uint16_t cmpl_ring;
20839 * The sequence ID is used by the driver for tracking multiple
20840 * commands. This ID is treated as opaque data by the firmware and
20841 * the value is returned in the `hwrm_resp_hdr` upon completion.
20845 * The target ID of the command:
20846 * * 0x0-0xFFF8 - The function ID
20847 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20848 * * 0xFFFD - Reserved for user-space HWRM interface
20851 uint16_t target_id;
20853 * A physical address pointer pointing to a host buffer that the
20854 * command's response data will be written. This can be either a host
20855 * physical address (HPA) or a guest physical address (GPA) and must
20856 * point to a physically contiguous block of memory.
20858 uint64_t resp_addr;
20861 * When this bit is '1', the VNIC shall be configured to
20862 * perform transparent packet aggregation (TPA) of
20863 * non-tunneled TCP packets.
20865 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
20868 * When this bit is '1', the VNIC shall be configured to
20869 * perform transparent packet aggregation (TPA) of
20870 * tunneled TCP packets.
20872 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
20875 * When this bit is '1', the VNIC shall be configured to
20876 * perform transparent packet aggregation (TPA) according
20877 * to Windows Receive Segment Coalescing (RSC) rules.
20879 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
20882 * When this bit is '1', the VNIC shall be configured to
20883 * perform transparent packet aggregation (TPA) according
20884 * to Linux Generic Receive Offload (GRO) rules.
20886 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
20889 * When this bit is '1', the VNIC shall be configured to
20890 * perform transparent packet aggregation (TPA) for TCP
20891 * packets with IP ECN set to non-zero.
20893 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
20896 * When this bit is '1', the VNIC shall be configured to
20897 * perform transparent packet aggregation (TPA) for
20898 * GRE tunneled TCP packets only if all packets have the
20899 * same GRE sequence.
20901 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
20904 * When this bit is '1' and the GRO mode is enabled,
20905 * the VNIC shall be configured to
20906 * perform transparent packet aggregation (TPA) for
20907 * TCP/IPv4 packets with consecutively increasing IPIDs.
20908 * In other words, the last packet that is being
20909 * aggregated to an already existing aggregation context
20910 * shall have IPID 1 more than the IPID of the last packet
20911 * that was aggregated in that aggregation context.
20913 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
20916 * When this bit is '1' and the GRO mode is enabled,
20917 * the VNIC shall be configured to
20918 * perform transparent packet aggregation (TPA) for
20919 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
20922 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
20925 * When this bit is '1' and the GRO mode is enabled,
20926 * the VNIC shall DMA payload data using GRO rules.
20927 * When this bit is '0', the VNIC shall DMA payload data
20928 * using the more efficient LRO rules of filling all
20929 * aggregation buffers.
20931 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
20935 * This bit must be '1' for the max_agg_segs field to be
20938 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
20940 * This bit must be '1' for the max_aggs field to be
20943 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
20945 * This bit must be '1' for the max_agg_timer field to be
20948 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
20949 /* deprecated bit. Do not use!!! */
20950 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
20951 /* Logical vnic ID */
20954 * This is the maximum number of TCP segments that can
20955 * be aggregated (unit is Log2). Max value is 31. On new
20956 * devices supporting TPA v2, the unit is multiples of 4 and
20957 * valid values are > 0 and <= 63.
20959 uint16_t max_agg_segs;
20961 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
20963 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
20965 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
20967 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
20968 /* Any segment size larger than this is not valid */
20969 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
20970 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
20971 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
20973 * This is the maximum number of aggregations this VNIC is
20974 * allowed (unit is Log2). Max value is 7. On new devices
20975 * supporting TPA v2, this is in unit of 1 and must be > 0
20976 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
20977 * to enable TPA v2.
20980 /* 1 aggregation */
20981 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
20982 /* 2 aggregations */
20983 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
20984 /* 4 aggregations */
20985 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
20986 /* 8 aggregations */
20987 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
20988 /* 16 aggregations */
20989 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
20990 /* Any aggregation size larger than this is not valid */
20991 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
20992 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
20993 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
20994 uint8_t unused_0[2];
20996 * This is the maximum amount of time allowed for
20997 * an aggregation context to complete after it was initiated.
20999 uint32_t max_agg_timer;
21001 * This is the minimum amount of payload length required to
21002 * start an aggregation context. This field is deprecated and
21003 * should be set to 0. The minimum length is set by firmware
21004 * and can be queried using hwrm_vnic_tpa_qcfg.
21006 uint32_t min_agg_len;
21007 } __attribute__((packed));
21009 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
21010 struct hwrm_vnic_tpa_cfg_output {
21011 /* The specific error status for the command. */
21012 uint16_t error_code;
21013 /* The HWRM command request type. */
21015 /* The sequence ID from the original command. */
21017 /* The length of the response data in number of bytes. */
21019 uint8_t unused_0[7];
21021 * This field is used in Output records to indicate that the output
21022 * is completely written to RAM. This field should be read as '1'
21023 * to indicate that the output has been completely written.
21024 * When writing a command completion or response to an internal processor,
21025 * the order of writes has to be such that this field is written last.
21028 } __attribute__((packed));
21030 /*********************
21031 * hwrm_vnic_rss_cfg *
21032 *********************/
21035 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
21036 struct hwrm_vnic_rss_cfg_input {
21037 /* The HWRM command request type. */
21040 * The completion ring to send the completion event on. This should
21041 * be the NQ ID returned from the `nq_alloc` HWRM command.
21043 uint16_t cmpl_ring;
21045 * The sequence ID is used by the driver for tracking multiple
21046 * commands. This ID is treated as opaque data by the firmware and
21047 * the value is returned in the `hwrm_resp_hdr` upon completion.
21051 * The target ID of the command:
21052 * * 0x0-0xFFF8 - The function ID
21053 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21054 * * 0xFFFD - Reserved for user-space HWRM interface
21057 uint16_t target_id;
21059 * A physical address pointer pointing to a host buffer that the
21060 * command's response data will be written. This can be either a host
21061 * physical address (HPA) or a guest physical address (GPA) and must
21062 * point to a physically contiguous block of memory.
21064 uint64_t resp_addr;
21065 uint32_t hash_type;
21067 * When this bit is '1', the RSS hash shall be computed
21068 * over source and destination IPv4 addresses of IPv4
21071 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
21073 * When this bit is '1', the RSS hash shall be computed
21074 * over source/destination IPv4 addresses and
21075 * source/destination ports of TCP/IPv4 packets.
21077 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
21079 * When this bit is '1', the RSS hash shall be computed
21080 * over source/destination IPv4 addresses and
21081 * source/destination ports of UDP/IPv4 packets.
21083 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
21085 * When this bit is '1', the RSS hash shall be computed
21086 * over source and destination IPv4 addresses of IPv6
21089 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
21091 * When this bit is '1', the RSS hash shall be computed
21092 * over source/destination IPv6 addresses and
21093 * source/destination ports of TCP/IPv6 packets.
21095 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
21097 * When this bit is '1', the RSS hash shall be computed
21098 * over source/destination IPv6 addresses and
21099 * source/destination ports of UDP/IPv6 packets.
21101 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
21102 /* VNIC ID of VNIC associated with RSS table being configured. */
21105 * Specifies which VNIC ring table pair to configure.
21106 * Valid values range from 0 to 7.
21108 uint8_t ring_table_pair_index;
21109 /* Flags to specify different RSS hash modes. */
21110 uint8_t hash_mode_flags;
21112 * When this bit is '1', it indicates using current RSS
21113 * hash mode setting configured in the device.
21115 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
21118 * When this bit is '1', it indicates requesting support of
21119 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
21120 * l4.src, l4.dest} for tunnel packets. For none-tunnel
21121 * packets, the RSS hash is computed over the normal
21122 * src/dest l3 and src/dest l4 headers.
21124 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
21127 * When this bit is '1', it indicates requesting support of
21128 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21129 * tunnel packets. For none-tunnel packets, the RSS hash is
21130 * computed over the normal src/dest l3 headers.
21132 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21135 * When this bit is '1', it indicates requesting support of
21136 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21137 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21138 * packets, the RSS hash is computed over the normal
21139 * src/dest l3 and src/dest l4 headers.
21141 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21144 * When this bit is '1', it indicates requesting support of
21145 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21146 * tunnel packets. For none-tunnel packets, the RSS hash is
21147 * computed over the normal src/dest l3 headers.
21149 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21151 /* This is the address for rss ring group table */
21152 uint64_t ring_grp_tbl_addr;
21153 /* This is the address for rss hash key table */
21154 uint64_t hash_key_tbl_addr;
21155 /* Index to the rss indirection table. */
21156 uint16_t rss_ctx_idx;
21157 uint8_t unused_1[6];
21158 } __attribute__((packed));
21160 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
21161 struct hwrm_vnic_rss_cfg_output {
21162 /* The specific error status for the command. */
21163 uint16_t error_code;
21164 /* The HWRM command request type. */
21166 /* The sequence ID from the original command. */
21168 /* The length of the response data in number of bytes. */
21170 uint8_t unused_0[7];
21172 * This field is used in Output records to indicate that the output
21173 * is completely written to RAM. This field should be read as '1'
21174 * to indicate that the output has been completely written.
21175 * When writing a command completion or response to an internal processor,
21176 * the order of writes has to be such that this field is written last.
21179 } __attribute__((packed));
21181 /**********************
21182 * hwrm_vnic_rss_qcfg *
21183 **********************/
21186 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
21187 struct hwrm_vnic_rss_qcfg_input {
21188 /* The HWRM command request type. */
21191 * The completion ring to send the completion event on. This should
21192 * be the NQ ID returned from the `nq_alloc` HWRM command.
21194 uint16_t cmpl_ring;
21196 * The sequence ID is used by the driver for tracking multiple
21197 * commands. This ID is treated as opaque data by the firmware and
21198 * the value is returned in the `hwrm_resp_hdr` upon completion.
21202 * The target ID of the command:
21203 * * 0x0-0xFFF8 - The function ID
21204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21205 * * 0xFFFD - Reserved for user-space HWRM interface
21208 uint16_t target_id;
21210 * A physical address pointer pointing to a host buffer that the
21211 * command's response data will be written. This can be either a host
21212 * physical address (HPA) or a guest physical address (GPA) and must
21213 * point to a physically contiguous block of memory.
21215 uint64_t resp_addr;
21216 /* Index to the rss indirection table. */
21217 uint16_t rss_ctx_idx;
21218 uint8_t unused_0[6];
21219 } __attribute__((packed));
21221 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
21222 struct hwrm_vnic_rss_qcfg_output {
21223 /* The specific error status for the command. */
21224 uint16_t error_code;
21225 /* The HWRM command request type. */
21227 /* The sequence ID from the original command. */
21229 /* The length of the response data in number of bytes. */
21231 uint32_t hash_type;
21233 * When this bit is '1', the RSS hash shall be computed
21234 * over source and destination IPv4 addresses of IPv4
21237 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
21239 * When this bit is '1', the RSS hash shall be computed
21240 * over source/destination IPv4 addresses and
21241 * source/destination ports of TCP/IPv4 packets.
21243 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
21245 * When this bit is '1', the RSS hash shall be computed
21246 * over source/destination IPv4 addresses and
21247 * source/destination ports of UDP/IPv4 packets.
21249 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
21251 * When this bit is '1', the RSS hash shall be computed
21252 * over source and destination IPv4 addresses of IPv6
21255 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
21257 * When this bit is '1', the RSS hash shall be computed
21258 * over source/destination IPv6 addresses and
21259 * source/destination ports of TCP/IPv6 packets.
21261 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
21263 * When this bit is '1', the RSS hash shall be computed
21264 * over source/destination IPv6 addresses and
21265 * source/destination ports of UDP/IPv6 packets.
21267 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
21268 uint8_t unused_0[4];
21269 /* This is the value of rss hash key */
21270 uint32_t hash_key[10];
21271 /* Flags to specify different RSS hash modes. */
21272 uint8_t hash_mode_flags;
21274 * When this bit is '1', it indicates using current RSS
21275 * hash mode setting configured in the device.
21277 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
21280 * When this bit is '1', it indicates requesting support of
21281 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
21282 * l4.src, l4.dest} for tunnel packets. For none-tunnel
21283 * packets, the RSS hash is computed over the normal
21284 * src/dest l3 and src/dest l4 headers.
21286 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
21289 * When this bit is '1', it indicates requesting support of
21290 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
21291 * tunnel packets. For none-tunnel packets, the RSS hash is
21292 * computed over the normal src/dest l3 headers.
21294 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
21297 * When this bit is '1', it indicates requesting support of
21298 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
21299 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
21300 * packets, the RSS hash is computed over the normal
21301 * src/dest l3 and src/dest l4 headers.
21303 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
21306 * When this bit is '1', it indicates requesting support of
21307 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
21308 * tunnel packets. For none-tunnel packets, the RSS hash is
21309 * computed over the normal src/dest l3 headers.
21311 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
21313 uint8_t unused_1[6];
21315 * This field is used in Output records to indicate that the output
21316 * is completely written to RAM. This field should be read as '1'
21317 * to indicate that the output has been completely written.
21318 * When writing a command completion or response to an internal processor,
21319 * the order of writes has to be such that this field is written last.
21322 } __attribute__((packed));
21324 /**************************
21325 * hwrm_vnic_plcmodes_cfg *
21326 **************************/
21329 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
21330 struct hwrm_vnic_plcmodes_cfg_input {
21331 /* The HWRM command request type. */
21334 * The completion ring to send the completion event on. This should
21335 * be the NQ ID returned from the `nq_alloc` HWRM command.
21337 uint16_t cmpl_ring;
21339 * The sequence ID is used by the driver for tracking multiple
21340 * commands. This ID is treated as opaque data by the firmware and
21341 * the value is returned in the `hwrm_resp_hdr` upon completion.
21345 * The target ID of the command:
21346 * * 0x0-0xFFF8 - The function ID
21347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21348 * * 0xFFFD - Reserved for user-space HWRM interface
21351 uint16_t target_id;
21353 * A physical address pointer pointing to a host buffer that the
21354 * command's response data will be written. This can be either a host
21355 * physical address (HPA) or a guest physical address (GPA) and must
21356 * point to a physically contiguous block of memory.
21358 uint64_t resp_addr;
21361 * When this bit is '1', the VNIC shall be configured to
21362 * use regular placement algorithm.
21363 * By default, the regular placement algorithm shall be
21364 * enabled on the VNIC.
21366 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
21369 * When this bit is '1', the VNIC shall be configured
21370 * use the jumbo placement algorithm.
21372 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
21375 * When this bit is '1', the VNIC shall be configured
21376 * to enable Header-Data split for IPv4 packets according
21377 * to the following rules:
21378 * # If the packet is identified as TCP/IPv4, then the
21379 * packet is split at the beginning of the TCP payload.
21380 * # If the packet is identified as UDP/IPv4, then the
21381 * packet is split at the beginning of UDP payload.
21382 * # If the packet is identified as non-TCP and non-UDP
21383 * IPv4 packet, then the packet is split at the beginning
21384 * of the upper layer protocol header carried in the IPv4
21387 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
21390 * When this bit is '1', the VNIC shall be configured
21391 * to enable Header-Data split for IPv6 packets according
21392 * to the following rules:
21393 * # If the packet is identified as TCP/IPv6, then the
21394 * packet is split at the beginning of the TCP payload.
21395 * # If the packet is identified as UDP/IPv6, then the
21396 * packet is split at the beginning of UDP payload.
21397 * # If the packet is identified as non-TCP and non-UDP
21398 * IPv6 packet, then the packet is split at the beginning
21399 * of the upper layer protocol header carried in the IPv6
21402 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
21405 * When this bit is '1', the VNIC shall be configured
21406 * to enable Header-Data split for FCoE packets at the
21407 * beginning of FC payload.
21409 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
21412 * When this bit is '1', the VNIC shall be configured
21413 * to enable Header-Data split for RoCE packets at the
21414 * beginning of RoCE payload (after BTH/GRH headers).
21416 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
21420 * This bit must be '1' for the jumbo_thresh_valid field to be
21423 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
21426 * This bit must be '1' for the hds_offset_valid field to be
21429 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
21432 * This bit must be '1' for the hds_threshold_valid field to be
21435 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
21437 /* Logical vnic ID */
21440 * When jumbo placement algorithm is enabled, this value
21441 * is used to determine the threshold for jumbo placement.
21442 * Packets with length larger than this value will be
21443 * placed according to the jumbo placement algorithm.
21445 uint16_t jumbo_thresh;
21447 * This value is used to determine the offset into
21448 * packet buffer where the split data (payload) will be
21449 * placed according to one of of HDS placement algorithm.
21451 * The lengths of packet buffers provided for split data
21452 * shall be larger than this value.
21454 uint16_t hds_offset;
21456 * When one of the HDS placement algorithm is enabled, this
21457 * value is used to determine the threshold for HDS
21459 * Packets with length larger than this value will be
21460 * placed according to the HDS placement algorithm.
21461 * This value shall be in multiple of 4 bytes.
21463 uint16_t hds_threshold;
21464 uint8_t unused_0[6];
21465 } __attribute__((packed));
21467 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
21468 struct hwrm_vnic_plcmodes_cfg_output {
21469 /* The specific error status for the command. */
21470 uint16_t error_code;
21471 /* The HWRM command request type. */
21473 /* The sequence ID from the original command. */
21475 /* The length of the response data in number of bytes. */
21477 uint8_t unused_0[7];
21479 * This field is used in Output records to indicate that the output
21480 * is completely written to RAM. This field should be read as '1'
21481 * to indicate that the output has been completely written.
21482 * When writing a command completion or response to an internal processor,
21483 * the order of writes has to be such that this field is written last.
21486 } __attribute__((packed));
21488 /***************************
21489 * hwrm_vnic_plcmodes_qcfg *
21490 ***************************/
21493 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
21494 struct hwrm_vnic_plcmodes_qcfg_input {
21495 /* The HWRM command request type. */
21498 * The completion ring to send the completion event on. This should
21499 * be the NQ ID returned from the `nq_alloc` HWRM command.
21501 uint16_t cmpl_ring;
21503 * The sequence ID is used by the driver for tracking multiple
21504 * commands. This ID is treated as opaque data by the firmware and
21505 * the value is returned in the `hwrm_resp_hdr` upon completion.
21509 * The target ID of the command:
21510 * * 0x0-0xFFF8 - The function ID
21511 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21512 * * 0xFFFD - Reserved for user-space HWRM interface
21515 uint16_t target_id;
21517 * A physical address pointer pointing to a host buffer that the
21518 * command's response data will be written. This can be either a host
21519 * physical address (HPA) or a guest physical address (GPA) and must
21520 * point to a physically contiguous block of memory.
21522 uint64_t resp_addr;
21523 /* Logical vnic ID */
21525 uint8_t unused_0[4];
21526 } __attribute__((packed));
21528 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
21529 struct hwrm_vnic_plcmodes_qcfg_output {
21530 /* The specific error status for the command. */
21531 uint16_t error_code;
21532 /* The HWRM command request type. */
21534 /* The sequence ID from the original command. */
21536 /* The length of the response data in number of bytes. */
21540 * When this bit is '1', the VNIC is configured to
21541 * use regular placement algorithm.
21543 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
21546 * When this bit is '1', the VNIC is configured to
21547 * use the jumbo placement algorithm.
21549 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
21552 * When this bit is '1', the VNIC is configured
21553 * to enable Header-Data split for IPv4 packets.
21555 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
21558 * When this bit is '1', the VNIC is configured
21559 * to enable Header-Data split for IPv6 packets.
21561 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
21564 * When this bit is '1', the VNIC is configured
21565 * to enable Header-Data split for FCoE packets.
21567 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
21570 * When this bit is '1', the VNIC is configured
21571 * to enable Header-Data split for RoCE packets.
21573 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
21576 * When this bit is '1', the VNIC is configured
21577 * to be the default VNIC of the requesting function.
21579 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
21582 * When jumbo placement algorithm is enabled, this value
21583 * is used to determine the threshold for jumbo placement.
21584 * Packets with length larger than this value will be
21585 * placed according to the jumbo placement algorithm.
21587 uint16_t jumbo_thresh;
21589 * This value is used to determine the offset into
21590 * packet buffer where the split data (payload) will be
21591 * placed according to one of of HDS placement algorithm.
21593 * The lengths of packet buffers provided for split data
21594 * shall be larger than this value.
21596 uint16_t hds_offset;
21598 * When one of the HDS placement algorithm is enabled, this
21599 * value is used to determine the threshold for HDS
21601 * Packets with length larger than this value will be
21602 * placed according to the HDS placement algorithm.
21603 * This value shall be in multiple of 4 bytes.
21605 uint16_t hds_threshold;
21606 uint8_t unused_0[5];
21608 * This field is used in Output records to indicate that the output
21609 * is completely written to RAM. This field should be read as '1'
21610 * to indicate that the output has been completely written.
21611 * When writing a command completion or response to an internal processor,
21612 * the order of writes has to be such that this field is written last.
21615 } __attribute__((packed));
21617 /**********************************
21618 * hwrm_vnic_rss_cos_lb_ctx_alloc *
21619 **********************************/
21622 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
21623 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
21624 /* The HWRM command request type. */
21627 * The completion ring to send the completion event on. This should
21628 * be the NQ ID returned from the `nq_alloc` HWRM command.
21630 uint16_t cmpl_ring;
21632 * The sequence ID is used by the driver for tracking multiple
21633 * commands. This ID is treated as opaque data by the firmware and
21634 * the value is returned in the `hwrm_resp_hdr` upon completion.
21638 * The target ID of the command:
21639 * * 0x0-0xFFF8 - The function ID
21640 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21641 * * 0xFFFD - Reserved for user-space HWRM interface
21644 uint16_t target_id;
21646 * A physical address pointer pointing to a host buffer that the
21647 * command's response data will be written. This can be either a host
21648 * physical address (HPA) or a guest physical address (GPA) and must
21649 * point to a physically contiguous block of memory.
21651 uint64_t resp_addr;
21652 } __attribute__((packed));
21654 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
21655 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
21656 /* The specific error status for the command. */
21657 uint16_t error_code;
21658 /* The HWRM command request type. */
21660 /* The sequence ID from the original command. */
21662 /* The length of the response data in number of bytes. */
21664 /* rss_cos_lb_ctx_id is 16 b */
21665 uint16_t rss_cos_lb_ctx_id;
21666 uint8_t unused_0[5];
21668 * This field is used in Output records to indicate that the output
21669 * is completely written to RAM. This field should be read as '1'
21670 * to indicate that the output has been completely written.
21671 * When writing a command completion or response to an internal processor,
21672 * the order of writes has to be such that this field is written last.
21675 } __attribute__((packed));
21677 /*********************************
21678 * hwrm_vnic_rss_cos_lb_ctx_free *
21679 *********************************/
21682 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
21683 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
21684 /* The HWRM command request type. */
21687 * The completion ring to send the completion event on. This should
21688 * be the NQ ID returned from the `nq_alloc` HWRM command.
21690 uint16_t cmpl_ring;
21692 * The sequence ID is used by the driver for tracking multiple
21693 * commands. This ID is treated as opaque data by the firmware and
21694 * the value is returned in the `hwrm_resp_hdr` upon completion.
21698 * The target ID of the command:
21699 * * 0x0-0xFFF8 - The function ID
21700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21701 * * 0xFFFD - Reserved for user-space HWRM interface
21704 uint16_t target_id;
21706 * A physical address pointer pointing to a host buffer that the
21707 * command's response data will be written. This can be either a host
21708 * physical address (HPA) or a guest physical address (GPA) and must
21709 * point to a physically contiguous block of memory.
21711 uint64_t resp_addr;
21712 /* rss_cos_lb_ctx_id is 16 b */
21713 uint16_t rss_cos_lb_ctx_id;
21714 uint8_t unused_0[6];
21715 } __attribute__((packed));
21717 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
21718 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
21719 /* The specific error status for the command. */
21720 uint16_t error_code;
21721 /* The HWRM command request type. */
21723 /* The sequence ID from the original command. */
21725 /* The length of the response data in number of bytes. */
21727 uint8_t unused_0[7];
21729 * This field is used in Output records to indicate that the output
21730 * is completely written to RAM. This field should be read as '1'
21731 * to indicate that the output has been completely written.
21732 * When writing a command completion or response to an internal processor,
21733 * the order of writes has to be such that this field is written last.
21736 } __attribute__((packed));
21738 /*******************
21739 * hwrm_ring_alloc *
21740 *******************/
21743 /* hwrm_ring_alloc_input (size:704b/88B) */
21744 struct hwrm_ring_alloc_input {
21745 /* The HWRM command request type. */
21748 * The completion ring to send the completion event on. This should
21749 * be the NQ ID returned from the `nq_alloc` HWRM command.
21751 uint16_t cmpl_ring;
21753 * The sequence ID is used by the driver for tracking multiple
21754 * commands. This ID is treated as opaque data by the firmware and
21755 * the value is returned in the `hwrm_resp_hdr` upon completion.
21759 * The target ID of the command:
21760 * * 0x0-0xFFF8 - The function ID
21761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21762 * * 0xFFFD - Reserved for user-space HWRM interface
21765 uint16_t target_id;
21767 * A physical address pointer pointing to a host buffer that the
21768 * command's response data will be written. This can be either a host
21769 * physical address (HPA) or a guest physical address (GPA) and must
21770 * point to a physically contiguous block of memory.
21772 uint64_t resp_addr;
21775 * This bit must be '1' for the ring_arb_cfg field to be
21778 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
21781 * This bit must be '1' for the stat_ctx_id_valid field to be
21784 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
21787 * This bit must be '1' for the max_bw_valid field to be
21790 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
21793 * This bit must be '1' for the rx_ring_id field to be
21796 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
21799 * This bit must be '1' for the nq_ring_id field to be
21802 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
21805 * This bit must be '1' for the rx_buf_size field to be
21808 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
21812 /* L2 Completion Ring (CR) */
21813 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
21815 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
21817 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
21818 /* RoCE Notification Completion Ring (ROCE_CR) */
21819 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
21820 /* RX Aggregation Ring */
21821 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
21822 /* Notification Queue */
21823 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
21824 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
21825 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
21827 /* Ring allocation flags. */
21830 * For Rx rings, the incoming packet data can be placed at either
21831 * a 0B or 2B offset from the start of the Rx packet buffer. When
21832 * '1', the received packet will be padded with 2B of zeros at the
21833 * front of the packet. Note that this flag is only used for
21834 * Rx rings and is ignored for all other rings included Rx
21835 * Aggregation rings.
21837 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
21839 * This value is a pointer to the page table for the
21842 uint64_t page_tbl_addr;
21843 /* First Byte Offset of the first entry in the first page. */
21846 * Actual page size in 2^page_size. The supported range is increments
21847 * in powers of 2 from 16 bytes to 1GB.
21849 * Page size is 16 B.
21851 * Page size is 4 KB.
21853 * Page size is 8 KB.
21855 * Page size is 64 KB.
21857 * Page size is 2 MB.
21859 * Page size is 4 MB.
21861 * Page size is 1 GB.
21865 * This value indicates the depth of page table.
21866 * For this version of the specification, value other than 0 or
21867 * 1 shall be considered as an invalid value.
21868 * When the page_tbl_depth = 0, then it is treated as a
21869 * special case with the following.
21870 * 1. FBO and page size fields are not valid.
21871 * 2. page_tbl_addr is the physical address of the first
21872 * element of the ring.
21874 uint8_t page_tbl_depth;
21875 uint8_t unused_1[2];
21877 * Number of 16B units in the ring. Minimum size for
21878 * a ring is 16 16B entries.
21882 * Logical ring number for the ring to be allocated.
21883 * This value determines the position in the doorbell
21884 * area where the update to the ring will be made.
21886 * For completion rings, this value is also the MSI-X
21887 * vector number for the function the completion ring is
21890 uint16_t logical_id;
21892 * This field is used only when ring_type is a TX ring.
21893 * This value indicates what completion ring the TX ring
21894 * is associated with.
21896 uint16_t cmpl_ring_id;
21898 * This field is used only when ring_type is a TX ring.
21899 * This value indicates what CoS queue the TX ring
21900 * is associated with.
21904 * When allocating a Rx ring or Rx aggregation ring, this field
21905 * specifies the size of the buffer descriptors posted to the ring.
21907 uint16_t rx_buf_size;
21909 * When allocating an Rx aggregation ring, this field
21910 * specifies the associated Rx ring ID.
21912 uint16_t rx_ring_id;
21914 * When allocating a completion ring, this field
21915 * specifies the associated NQ ring ID.
21917 uint16_t nq_ring_id;
21919 * This field is used only when ring_type is a TX ring.
21920 * This field is used to configure arbitration related
21921 * parameters for a TX ring.
21923 uint16_t ring_arb_cfg;
21924 /* Arbitration policy used for the ring. */
21925 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
21927 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
21929 * Use strict priority for the TX ring.
21930 * Priority value is specified in arb_policy_param
21932 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
21935 * Use weighted fair queue arbitration for the TX ring.
21936 * Weight is specified in arb_policy_param
21938 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
21940 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
21941 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
21942 /* Reserved field. */
21943 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
21945 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
21947 * Arbitration policy specific parameter.
21948 * # For strict priority arbitration policy, this field
21949 * represents a priority value. If set to 0, then the priority
21950 * is not specified and the HWRM is allowed to select
21951 * any priority for this TX ring.
21952 * # For weighted fair queue arbitration policy, this field
21953 * represents a weight value. If set to 0, then the weight
21954 * is not specified and the HWRM is allowed to select
21955 * any weight for this TX ring.
21957 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
21959 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
21962 * This field is reserved for the future use.
21963 * It shall be set to 0.
21965 uint32_t reserved3;
21967 * This field is used only when ring_type is a TX ring.
21968 * This input indicates what statistics context this ring
21969 * should be associated with.
21971 uint32_t stat_ctx_id;
21973 * This field is reserved for the future use.
21974 * It shall be set to 0.
21976 uint32_t reserved4;
21978 * This field is used only when ring_type is a TX ring
21979 * to specify maximum BW allocated to the TX ring.
21980 * The HWRM will translate this value into byte counter and
21981 * time interval used for this ring inside the device.
21984 /* The bandwidth value. */
21985 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
21986 UINT32_C(0xfffffff)
21987 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
21988 /* The granularity of the value (bits or bytes). */
21989 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
21990 UINT32_C(0x10000000)
21991 /* Value is in bits. */
21992 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
21993 (UINT32_C(0x0) << 28)
21994 /* Value is in bytes. */
21995 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
21996 (UINT32_C(0x1) << 28)
21997 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
21998 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
21999 /* bw_value_unit is 3 b */
22000 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
22001 UINT32_C(0xe0000000)
22002 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
22003 /* Value is in Mb or MB (base 10). */
22004 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
22005 (UINT32_C(0x0) << 29)
22006 /* Value is in Kb or KB (base 10). */
22007 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
22008 (UINT32_C(0x2) << 29)
22009 /* Value is in bits or bytes. */
22010 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
22011 (UINT32_C(0x4) << 29)
22012 /* Value is in Gb or GB (base 10). */
22013 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
22014 (UINT32_C(0x6) << 29)
22015 /* Value is in 1/100th of a percentage of total bandwidth. */
22016 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22017 (UINT32_C(0x1) << 29)
22019 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
22020 (UINT32_C(0x7) << 29)
22021 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
22022 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
22024 * This field is used only when ring_type is a Completion ring.
22025 * This value indicates what interrupt mode should be used
22026 * on this completion ring.
22027 * Note: In the legacy interrupt mode, no more than 16
22028 * completion rings are allowed.
22032 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
22034 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
22036 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
22037 /* No Interrupt - Polled mode */
22038 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
22039 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
22040 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
22041 uint8_t unused_4[3];
22043 * The cq_handle is specified when allocating a completion ring. For
22044 * devices that support NQs, this cq_handle will be included in the
22045 * NQE to specify which CQ should be read to retrieve the completion
22048 uint64_t cq_handle;
22049 } __attribute__((packed));
22051 /* hwrm_ring_alloc_output (size:128b/16B) */
22052 struct hwrm_ring_alloc_output {
22053 /* The specific error status for the command. */
22054 uint16_t error_code;
22055 /* The HWRM command request type. */
22057 /* The sequence ID from the original command. */
22059 /* The length of the response data in number of bytes. */
22062 * Physical number of ring allocated.
22063 * This value shall be unique for a ring type.
22066 /* Logical number of ring allocated. */
22067 uint16_t logical_ring_id;
22068 uint8_t unused_0[3];
22070 * This field is used in Output records to indicate that the output
22071 * is completely written to RAM. This field should be read as '1'
22072 * to indicate that the output has been completely written.
22073 * When writing a command completion or response to an internal processor,
22074 * the order of writes has to be such that this field is written last.
22077 } __attribute__((packed));
22079 /******************
22081 ******************/
22084 /* hwrm_ring_free_input (size:192b/24B) */
22085 struct hwrm_ring_free_input {
22086 /* The HWRM command request type. */
22089 * The completion ring to send the completion event on. This should
22090 * be the NQ ID returned from the `nq_alloc` HWRM command.
22092 uint16_t cmpl_ring;
22094 * The sequence ID is used by the driver for tracking multiple
22095 * commands. This ID is treated as opaque data by the firmware and
22096 * the value is returned in the `hwrm_resp_hdr` upon completion.
22100 * The target ID of the command:
22101 * * 0x0-0xFFF8 - The function ID
22102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22103 * * 0xFFFD - Reserved for user-space HWRM interface
22106 uint16_t target_id;
22108 * A physical address pointer pointing to a host buffer that the
22109 * command's response data will be written. This can be either a host
22110 * physical address (HPA) or a guest physical address (GPA) and must
22111 * point to a physically contiguous block of memory.
22113 uint64_t resp_addr;
22116 /* L2 Completion Ring (CR) */
22117 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22119 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
22121 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
22122 /* RoCE Notification Completion Ring (ROCE_CR) */
22123 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22124 /* RX Aggregation Ring */
22125 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
22126 /* Notification Queue */
22127 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
22128 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
22129 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
22131 /* Physical number of ring allocated. */
22133 uint8_t unused_1[4];
22134 } __attribute__((packed));
22136 /* hwrm_ring_free_output (size:128b/16B) */
22137 struct hwrm_ring_free_output {
22138 /* The specific error status for the command. */
22139 uint16_t error_code;
22140 /* The HWRM command request type. */
22142 /* The sequence ID from the original command. */
22144 /* The length of the response data in number of bytes. */
22146 uint8_t unused_0[7];
22148 * This field is used in Output records to indicate that the output
22149 * is completely written to RAM. This field should be read as '1'
22150 * to indicate that the output has been completely written.
22151 * When writing a command completion or response to an internal processor,
22152 * the order of writes has to be such that this field is written last.
22155 } __attribute__((packed));
22157 /*******************
22158 * hwrm_ring_reset *
22159 *******************/
22162 /* hwrm_ring_reset_input (size:192b/24B) */
22163 struct hwrm_ring_reset_input {
22164 /* The HWRM command request type. */
22167 * The completion ring to send the completion event on. This should
22168 * be the NQ ID returned from the `nq_alloc` HWRM command.
22170 uint16_t cmpl_ring;
22172 * The sequence ID is used by the driver for tracking multiple
22173 * commands. This ID is treated as opaque data by the firmware and
22174 * the value is returned in the `hwrm_resp_hdr` upon completion.
22178 * The target ID of the command:
22179 * * 0x0-0xFFF8 - The function ID
22180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22181 * * 0xFFFD - Reserved for user-space HWRM interface
22184 uint16_t target_id;
22186 * A physical address pointer pointing to a host buffer that the
22187 * command's response data will be written. This can be either a host
22188 * physical address (HPA) or a guest physical address (GPA) and must
22189 * point to a physically contiguous block of memory.
22191 uint64_t resp_addr;
22194 /* L2 Completion Ring (CR) */
22195 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
22197 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
22199 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
22200 /* RoCE Notification Completion Ring (ROCE_CR) */
22201 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
22202 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
22203 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
22205 /* Physical number of the ring. */
22207 uint8_t unused_1[4];
22208 } __attribute__((packed));
22210 /* hwrm_ring_reset_output (size:128b/16B) */
22211 struct hwrm_ring_reset_output {
22212 /* The specific error status for the command. */
22213 uint16_t error_code;
22214 /* The HWRM command request type. */
22216 /* The sequence ID from the original command. */
22218 /* The length of the response data in number of bytes. */
22220 uint8_t unused_0[4];
22221 /* Position of consumer index after ring reset completes. */
22222 uint8_t consumer_idx[3];
22224 * This field is used in Output records to indicate that the output
22225 * is completely written to RAM. This field should be read as '1'
22226 * to indicate that the output has been completely written.
22227 * When writing a command completion or response to an internal processor,
22228 * the order of writes has to be such that this field is written last.
22231 } __attribute__((packed));
22233 /**************************
22234 * hwrm_ring_aggint_qcaps *
22235 **************************/
22238 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
22239 struct hwrm_ring_aggint_qcaps_input {
22240 /* The HWRM command request type. */
22243 * The completion ring to send the completion event on. This should
22244 * be the NQ ID returned from the `nq_alloc` HWRM command.
22246 uint16_t cmpl_ring;
22248 * The sequence ID is used by the driver for tracking multiple
22249 * commands. This ID is treated as opaque data by the firmware and
22250 * the value is returned in the `hwrm_resp_hdr` upon completion.
22254 * The target ID of the command:
22255 * * 0x0-0xFFF8 - The function ID
22256 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22257 * * 0xFFFD - Reserved for user-space HWRM interface
22260 uint16_t target_id;
22262 * A physical address pointer pointing to a host buffer that the
22263 * command's response data will be written. This can be either a host
22264 * physical address (HPA) or a guest physical address (GPA) and must
22265 * point to a physically contiguous block of memory.
22267 uint64_t resp_addr;
22268 } __attribute__((packed));
22270 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
22271 struct hwrm_ring_aggint_qcaps_output {
22272 /* The specific error status for the command. */
22273 uint16_t error_code;
22274 /* The HWRM command request type. */
22276 /* The sequence ID from the original command. */
22278 /* The length of the response data in number of bytes. */
22280 uint32_t cmpl_params;
22282 * When this bit is set to '1', int_lat_tmr_min can be configured
22283 * on completion rings.
22285 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
22288 * When this bit is set to '1', int_lat_tmr_max can be configured
22289 * on completion rings.
22291 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
22294 * When this bit is set to '1', timer_reset can be enabled
22295 * on completion rings.
22297 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
22300 * When this bit is set to '1', ring_idle can be enabled
22301 * on completion rings.
22303 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
22306 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
22307 * on completion rings.
22309 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
22312 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
22313 * on completion rings.
22315 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
22318 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
22319 * on completion rings.
22321 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
22324 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
22325 * on completion rings.
22327 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
22330 * When this bit is set to '1', num_cmpl_aggr_int can be configured
22331 * on completion rings.
22333 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
22335 uint32_t nq_params;
22337 * When this bit is set to '1', int_lat_tmr_min can be configured
22338 * on notification queues.
22340 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
22342 /* Minimum value for num_cmpl_dma_aggr */
22343 uint16_t num_cmpl_dma_aggr_min;
22344 /* Maximum value for num_cmpl_dma_aggr */
22345 uint16_t num_cmpl_dma_aggr_max;
22346 /* Minimum value for num_cmpl_dma_aggr_during_int */
22347 uint16_t num_cmpl_dma_aggr_during_int_min;
22348 /* Maximum value for num_cmpl_dma_aggr_during_int */
22349 uint16_t num_cmpl_dma_aggr_during_int_max;
22350 /* Minimum value for cmpl_aggr_dma_tmr */
22351 uint16_t cmpl_aggr_dma_tmr_min;
22352 /* Maximum value for cmpl_aggr_dma_tmr */
22353 uint16_t cmpl_aggr_dma_tmr_max;
22354 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
22355 uint16_t cmpl_aggr_dma_tmr_during_int_min;
22356 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
22357 uint16_t cmpl_aggr_dma_tmr_during_int_max;
22358 /* Minimum value for int_lat_tmr_min */
22359 uint16_t int_lat_tmr_min_min;
22360 /* Maximum value for int_lat_tmr_min */
22361 uint16_t int_lat_tmr_min_max;
22362 /* Minimum value for int_lat_tmr_max */
22363 uint16_t int_lat_tmr_max_min;
22364 /* Maximum value for int_lat_tmr_max */
22365 uint16_t int_lat_tmr_max_max;
22366 /* Minimum value for num_cmpl_aggr_int */
22367 uint16_t num_cmpl_aggr_int_min;
22368 /* Maximum value for num_cmpl_aggr_int */
22369 uint16_t num_cmpl_aggr_int_max;
22370 /* The units for timer parameters, in nanoseconds. */
22371 uint16_t timer_units;
22372 uint8_t unused_0[1];
22374 * This field is used in Output records to indicate that the output
22375 * is completely written to RAM. This field should be read as '1'
22376 * to indicate that the output has been completely written.
22377 * When writing a command completion or response to an internal processor,
22378 * the order of writes has to be such that this field is written last.
22381 } __attribute__((packed));
22383 /**************************************
22384 * hwrm_ring_cmpl_ring_qaggint_params *
22385 **************************************/
22388 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
22389 struct hwrm_ring_cmpl_ring_qaggint_params_input {
22390 /* The HWRM command request type. */
22393 * The completion ring to send the completion event on. This should
22394 * be the NQ ID returned from the `nq_alloc` HWRM command.
22396 uint16_t cmpl_ring;
22398 * The sequence ID is used by the driver for tracking multiple
22399 * commands. This ID is treated as opaque data by the firmware and
22400 * the value is returned in the `hwrm_resp_hdr` upon completion.
22404 * The target ID of the command:
22405 * * 0x0-0xFFF8 - The function ID
22406 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22407 * * 0xFFFD - Reserved for user-space HWRM interface
22410 uint16_t target_id;
22412 * A physical address pointer pointing to a host buffer that the
22413 * command's response data will be written. This can be either a host
22414 * physical address (HPA) or a guest physical address (GPA) and must
22415 * point to a physically contiguous block of memory.
22417 uint64_t resp_addr;
22418 /* Physical number of completion ring. */
22420 uint8_t unused_0[6];
22421 } __attribute__((packed));
22423 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
22424 struct hwrm_ring_cmpl_ring_qaggint_params_output {
22425 /* The specific error status for the command. */
22426 uint16_t error_code;
22427 /* The HWRM command request type. */
22429 /* The sequence ID from the original command. */
22431 /* The length of the response data in number of bytes. */
22435 * When this bit is set to '1', interrupt max
22436 * timer is reset whenever a completion is received.
22438 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
22441 * When this bit is set to '1', ring idle mode
22442 * aggregation will be enabled.
22444 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
22447 * Number of completions to aggregate before DMA
22448 * during the normal mode.
22450 uint16_t num_cmpl_dma_aggr;
22452 * Number of completions to aggregate before DMA
22453 * during the interrupt mode.
22455 uint16_t num_cmpl_dma_aggr_during_int;
22457 * Timer in unit of 80-nsec used to aggregate completions before
22458 * DMA during the normal mode (not in interrupt mode).
22460 uint16_t cmpl_aggr_dma_tmr;
22462 * Timer in unit of 80-nsec used to aggregate completions before
22463 * DMA during the interrupt mode.
22465 uint16_t cmpl_aggr_dma_tmr_during_int;
22466 /* Minimum time (in unit of 80-nsec) between two interrupts. */
22467 uint16_t int_lat_tmr_min;
22469 * Maximum wait time (in unit of 80-nsec) spent aggregating
22470 * completions before signaling the interrupt after the
22471 * interrupt is enabled.
22473 uint16_t int_lat_tmr_max;
22475 * Minimum number of completions aggregated before signaling
22478 uint16_t num_cmpl_aggr_int;
22479 uint8_t unused_0[7];
22481 * This field is used in Output records to indicate that the output
22482 * is completely written to RAM. This field should be read as '1'
22483 * to indicate that the output has been completely written.
22484 * When writing a command completion or response to an internal processor,
22485 * the order of writes has to be such that this field is written last.
22488 } __attribute__((packed));
22490 /*****************************************
22491 * hwrm_ring_cmpl_ring_cfg_aggint_params *
22492 *****************************************/
22495 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
22496 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
22497 /* The HWRM command request type. */
22500 * The completion ring to send the completion event on. This should
22501 * be the NQ ID returned from the `nq_alloc` HWRM command.
22503 uint16_t cmpl_ring;
22505 * The sequence ID is used by the driver for tracking multiple
22506 * commands. This ID is treated as opaque data by the firmware and
22507 * the value is returned in the `hwrm_resp_hdr` upon completion.
22511 * The target ID of the command:
22512 * * 0x0-0xFFF8 - The function ID
22513 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22514 * * 0xFFFD - Reserved for user-space HWRM interface
22517 uint16_t target_id;
22519 * A physical address pointer pointing to a host buffer that the
22520 * command's response data will be written. This can be either a host
22521 * physical address (HPA) or a guest physical address (GPA) and must
22522 * point to a physically contiguous block of memory.
22524 uint64_t resp_addr;
22525 /* Physical number of completion ring. */
22529 * When this bit is set to '1', interrupt latency max
22530 * timer is reset whenever a completion is received.
22532 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
22535 * When this bit is set to '1', ring idle mode
22536 * aggregation will be enabled.
22538 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
22541 * Set this flag to 1 when configuring parameters on a
22542 * notification queue. Set this flag to 0 when configuring
22543 * parameters on a completion queue.
22545 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
22548 * Number of completions to aggregate before DMA
22549 * during the normal mode.
22551 uint16_t num_cmpl_dma_aggr;
22553 * Number of completions to aggregate before DMA
22554 * during the interrupt mode.
22556 uint16_t num_cmpl_dma_aggr_during_int;
22558 * Timer in unit of 80-nsec used to aggregate completions before
22559 * DMA during the normal mode (not in interrupt mode).
22561 uint16_t cmpl_aggr_dma_tmr;
22563 * Timer in unit of 80-nsec used to aggregate completions before
22564 * DMA during the interrupt mode.
22566 uint16_t cmpl_aggr_dma_tmr_during_int;
22567 /* Minimum time (in unit of 80-nsec) between two interrupts. */
22568 uint16_t int_lat_tmr_min;
22570 * Maximum wait time (in unit of 80-nsec) spent aggregating
22571 * cmpls before signaling the interrupt after the
22572 * interrupt is enabled.
22574 uint16_t int_lat_tmr_max;
22576 * Minimum number of completions aggregated before signaling
22579 uint16_t num_cmpl_aggr_int;
22581 * Bitfield that indicates which parameters are to be applied. Only
22582 * required when configuring devices with notification queues, and
22583 * used in that case to set certain parameters on completion queues
22584 * and others on notification queues.
22588 * This bit must be '1' for the num_cmpl_dma_aggr field to be
22591 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
22594 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
22597 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
22600 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
22603 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
22606 * This bit must be '1' for the int_lat_tmr_min field to be
22609 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
22612 * This bit must be '1' for the int_lat_tmr_max field to be
22615 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
22618 * This bit must be '1' for the num_cmpl_aggr_int field to be
22621 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
22623 uint8_t unused_0[4];
22624 } __attribute__((packed));
22626 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
22627 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
22628 /* The specific error status for the command. */
22629 uint16_t error_code;
22630 /* The HWRM command request type. */
22632 /* The sequence ID from the original command. */
22634 /* The length of the response data in number of bytes. */
22636 uint8_t unused_0[7];
22638 * This field is used in Output records to indicate that the output
22639 * is completely written to RAM. This field should be read as '1'
22640 * to indicate that the output has been completely written.
22641 * When writing a command completion or response to an internal processor,
22642 * the order of writes has to be such that this field is written last.
22645 } __attribute__((packed));
22647 /***********************
22648 * hwrm_ring_grp_alloc *
22649 ***********************/
22652 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
22653 struct hwrm_ring_grp_alloc_input {
22654 /* The HWRM command request type. */
22657 * The completion ring to send the completion event on. This should
22658 * be the NQ ID returned from the `nq_alloc` HWRM command.
22660 uint16_t cmpl_ring;
22662 * The sequence ID is used by the driver for tracking multiple
22663 * commands. This ID is treated as opaque data by the firmware and
22664 * the value is returned in the `hwrm_resp_hdr` upon completion.
22668 * The target ID of the command:
22669 * * 0x0-0xFFF8 - The function ID
22670 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22671 * * 0xFFFD - Reserved for user-space HWRM interface
22674 uint16_t target_id;
22676 * A physical address pointer pointing to a host buffer that the
22677 * command's response data will be written. This can be either a host
22678 * physical address (HPA) or a guest physical address (GPA) and must
22679 * point to a physically contiguous block of memory.
22681 uint64_t resp_addr;
22683 * This value identifies the CR associated with the ring
22688 * This value identifies the main RR associated with the ring
22693 * This value identifies the aggregation RR associated with
22694 * the ring group. If this value is 0xFF... (All Fs), then no
22695 * Aggregation ring will be set.
22699 * This value identifies the statistics context associated
22700 * with the ring group.
22703 } __attribute__((packed));
22705 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
22706 struct hwrm_ring_grp_alloc_output {
22707 /* The specific error status for the command. */
22708 uint16_t error_code;
22709 /* The HWRM command request type. */
22711 /* The sequence ID from the original command. */
22713 /* The length of the response data in number of bytes. */
22716 * This is the ring group ID value. Use this value to program
22717 * the default ring group for the VNIC or as table entries
22718 * in an RSS/COS context.
22720 uint32_t ring_group_id;
22721 uint8_t unused_0[3];
22723 * This field is used in Output records to indicate that the output
22724 * is completely written to RAM. This field should be read as '1'
22725 * to indicate that the output has been completely written.
22726 * When writing a command completion or response to an internal processor,
22727 * the order of writes has to be such that this field is written last.
22730 } __attribute__((packed));
22732 /**********************
22733 * hwrm_ring_grp_free *
22734 **********************/
22737 /* hwrm_ring_grp_free_input (size:192b/24B) */
22738 struct hwrm_ring_grp_free_input {
22739 /* The HWRM command request type. */
22742 * The completion ring to send the completion event on. This should
22743 * be the NQ ID returned from the `nq_alloc` HWRM command.
22745 uint16_t cmpl_ring;
22747 * The sequence ID is used by the driver for tracking multiple
22748 * commands. This ID is treated as opaque data by the firmware and
22749 * the value is returned in the `hwrm_resp_hdr` upon completion.
22753 * The target ID of the command:
22754 * * 0x0-0xFFF8 - The function ID
22755 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22756 * * 0xFFFD - Reserved for user-space HWRM interface
22759 uint16_t target_id;
22761 * A physical address pointer pointing to a host buffer that the
22762 * command's response data will be written. This can be either a host
22763 * physical address (HPA) or a guest physical address (GPA) and must
22764 * point to a physically contiguous block of memory.
22766 uint64_t resp_addr;
22767 /* This is the ring group ID value. */
22768 uint32_t ring_group_id;
22769 uint8_t unused_0[4];
22770 } __attribute__((packed));
22772 /* hwrm_ring_grp_free_output (size:128b/16B) */
22773 struct hwrm_ring_grp_free_output {
22774 /* The specific error status for the command. */
22775 uint16_t error_code;
22776 /* The HWRM command request type. */
22778 /* The sequence ID from the original command. */
22780 /* The length of the response data in number of bytes. */
22782 uint8_t unused_0[7];
22784 * This field is used in Output records to indicate that the output
22785 * is completely written to RAM. This field should be read as '1'
22786 * to indicate that the output has been completely written.
22787 * When writing a command completion or response to an internal processor,
22788 * the order of writes has to be such that this field is written last.
22791 } __attribute__((packed));
22793 * special reserved flow ID to identify per function default
22794 * flows for vSwitch offload
22796 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
22798 * special reserved flow ID to identify per function RoCEv1
22801 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
22803 * special reserved flow ID to identify per function RoCEv2
22806 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
22808 * special reserved flow ID to identify per function RoCEv2
22811 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
22813 /****************************
22814 * hwrm_cfa_l2_filter_alloc *
22815 ****************************/
22818 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
22819 struct hwrm_cfa_l2_filter_alloc_input {
22820 /* The HWRM command request type. */
22823 * The completion ring to send the completion event on. This should
22824 * be the NQ ID returned from the `nq_alloc` HWRM command.
22826 uint16_t cmpl_ring;
22828 * The sequence ID is used by the driver for tracking multiple
22829 * commands. This ID is treated as opaque data by the firmware and
22830 * the value is returned in the `hwrm_resp_hdr` upon completion.
22834 * The target ID of the command:
22835 * * 0x0-0xFFF8 - The function ID
22836 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22837 * * 0xFFFD - Reserved for user-space HWRM interface
22840 uint16_t target_id;
22842 * A physical address pointer pointing to a host buffer that the
22843 * command's response data will be written. This can be either a host
22844 * physical address (HPA) or a guest physical address (GPA) and must
22845 * point to a physically contiguous block of memory.
22847 uint64_t resp_addr;
22850 * Enumeration denoting the RX, TX type of the resource.
22851 * This enumeration is used for resources that are similar for both
22852 * TX and RX paths of the chip.
22854 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
22857 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
22860 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
22862 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
22863 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
22864 /* Setting of this flag indicates the applicability to the loopback path. */
22865 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
22868 * Setting of this flag indicates drop action. If this flag is not set,
22869 * then it should be considered accept action.
22871 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
22874 * If this flag is set, all t_l2_* fields are invalid
22875 * and they should not be specified.
22876 * If this flag is set, then l2_* fields refer to
22877 * fields of outermost L2 header.
22879 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
22882 * Enumeration denoting NO_ROCE_L2 to support old drivers.
22883 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
22885 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
22887 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
22888 /* To support old drivers */
22889 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
22890 (UINT32_C(0x0) << 4)
22891 /* Only L2 traffic */
22892 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
22893 (UINT32_C(0x1) << 4)
22894 /* Roce & L2 traffic */
22895 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
22896 (UINT32_C(0x2) << 4)
22897 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
22898 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
22900 * Setting of this flag indicates that no XDP filter is created with
22902 * 0 - legacy behavior, XDP filter is created with L2 filter
22903 * 1 - XDP filter won't be created with L2 filter
22905 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
22908 * Setting this flag to 1 indicate the L2 fields in this command
22909 * pertain to source fields. Setting this flag to 0 indicate the
22910 * L2 fields in this command pertain to the destination fields
22911 * and this is the default/legacy behavior.
22913 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
22917 * This bit must be '1' for the l2_addr field to be
22920 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
22923 * This bit must be '1' for the l2_addr_mask field to be
22926 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
22929 * This bit must be '1' for the l2_ovlan field to be
22932 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
22935 * This bit must be '1' for the l2_ovlan_mask field to be
22938 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
22941 * This bit must be '1' for the l2_ivlan field to be
22944 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
22947 * This bit must be '1' for the l2_ivlan_mask field to be
22950 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
22953 * This bit must be '1' for the t_l2_addr field to be
22956 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
22959 * This bit must be '1' for the t_l2_addr_mask field to be
22962 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
22965 * This bit must be '1' for the t_l2_ovlan field to be
22968 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
22971 * This bit must be '1' for the t_l2_ovlan_mask field to be
22974 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
22977 * This bit must be '1' for the t_l2_ivlan field to be
22980 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
22983 * This bit must be '1' for the t_l2_ivlan_mask field to be
22986 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
22989 * This bit must be '1' for the src_type field to be
22992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
22995 * This bit must be '1' for the src_id field to be
22998 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
23001 * This bit must be '1' for the tunnel_type field to be
23004 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23007 * This bit must be '1' for the dst_id field to be
23010 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23013 * This bit must be '1' for the mirror_vnic_id field to be
23016 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23019 * This bit must be '1' for the num_vlans field to be
23022 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
23025 * This bit must be '1' for the t_num_vlans field to be
23028 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
23031 * This value sets the match value for the L2 MAC address.
23032 * Destination MAC address for RX path.
23033 * Source MAC address for TX path.
23035 uint8_t l2_addr[6];
23036 /* This value sets the match value for the number of VLANs. */
23039 * This value sets the match value for the number of VLANs
23040 * in the tunnel headers.
23042 uint8_t t_num_vlans;
23044 * This value sets the mask value for the L2 address.
23045 * A value of 0 will mask the corresponding bit from
23048 uint8_t l2_addr_mask[6];
23049 /* This value sets VLAN ID value for outer VLAN. */
23052 * This value sets the mask value for the ovlan id.
23053 * A value of 0 will mask the corresponding bit from
23056 uint16_t l2_ovlan_mask;
23057 /* This value sets VLAN ID value for inner VLAN. */
23060 * This value sets the mask value for the ivlan id.
23061 * A value of 0 will mask the corresponding bit from
23064 uint16_t l2_ivlan_mask;
23065 uint8_t unused_1[2];
23067 * This value sets the match value for the tunnel
23069 * Destination MAC address for RX path.
23070 * Source MAC address for TX path.
23072 uint8_t t_l2_addr[6];
23073 uint8_t unused_2[2];
23075 * This value sets the mask value for the tunnel L2
23077 * A value of 0 will mask the corresponding bit from
23080 uint8_t t_l2_addr_mask[6];
23081 /* This value sets VLAN ID value for tunnel outer VLAN. */
23082 uint16_t t_l2_ovlan;
23084 * This value sets the mask value for the tunnel ovlan id.
23085 * A value of 0 will mask the corresponding bit from
23088 uint16_t t_l2_ovlan_mask;
23089 /* This value sets VLAN ID value for tunnel inner VLAN. */
23090 uint16_t t_l2_ivlan;
23092 * This value sets the mask value for the tunnel ivlan id.
23093 * A value of 0 will mask the corresponding bit from
23096 uint16_t t_l2_ivlan_mask;
23097 /* This value identifies the type of source of the packet. */
23100 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
23101 /* Physical function */
23102 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
23103 /* Virtual function */
23104 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
23105 /* Virtual NIC of a function */
23106 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
23107 /* Embedded processor for CFA management */
23108 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
23109 /* Embedded processor for OOB management */
23110 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
23111 /* Embedded processor for RoCE */
23112 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
23113 /* Embedded processor for network proxy functions */
23114 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
23115 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
23116 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
23119 * This value is the id of the source.
23120 * For a network port, it represents port_id.
23121 * For a physical function, it represents fid.
23122 * For a virtual function, it represents vf_id.
23123 * For a vnic, it represents vnic_id.
23124 * For embedded processors, this id is not valid.
23127 * 1. The function ID is implied if it src_id is
23128 * not provided for a src_type that is either
23132 uint8_t tunnel_type;
23134 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23136 /* Virtual eXtensible Local Area Network (VXLAN) */
23137 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23139 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23140 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23142 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23143 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23146 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23148 /* Generic Network Virtualization Encapsulation (Geneve) */
23149 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23151 /* Multi-Protocol Lable Switching (MPLS) */
23152 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23154 /* Stateless Transport Tunnel (STT) */
23155 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23157 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23158 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23160 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23161 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23163 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23164 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23166 /* Use fixed layer 2 ether type of 0xFFFF */
23167 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23169 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23170 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23172 /* Any tunneled traffic */
23173 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23175 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23176 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23179 * If set, this value shall represent the
23180 * Logical VNIC ID of the destination VNIC for the RX
23181 * path and network port id of the destination port for
23186 * Logical VNIC ID of the VNIC where traffic is
23189 uint16_t mirror_vnic_id;
23191 * This hint is provided to help in placing
23192 * the filter in the filter table.
23195 /* No preference */
23196 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
23198 /* Above the given filter */
23199 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
23201 /* Below the given filter */
23202 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
23204 /* As high as possible */
23205 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
23207 /* As low as possible */
23208 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
23210 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
23211 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
23215 * This is the ID of the filter that goes along with
23218 * This field is valid only for the following values.
23219 * 1 - Above the given filter
23220 * 2 - Below the given filter
23222 uint64_t l2_filter_id_hint;
23223 } __attribute__((packed));
23225 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
23226 struct hwrm_cfa_l2_filter_alloc_output {
23227 /* The specific error status for the command. */
23228 uint16_t error_code;
23229 /* The HWRM command request type. */
23231 /* The sequence ID from the original command. */
23233 /* The length of the response data in number of bytes. */
23236 * This value identifies a set of CFA data structures used for an L2
23239 uint64_t l2_filter_id;
23241 * The flow id value in bit 0-29 is the actual ID of the flow
23242 * associated with this filter and it shall be used to match
23243 * and associate the flow identifier returned in completion
23244 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
23245 * shall indicate no valid flow id.
23248 /* Indicate the flow id value. */
23249 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
23250 UINT32_C(0x3fffffff)
23251 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
23252 /* Indicate type of the flow. */
23253 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
23254 UINT32_C(0x40000000)
23256 * If this bit set to 0, then it indicates that the flow is
23259 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
23260 (UINT32_C(0x0) << 30)
23262 * If this bit is set to 1, then it indicates that the flow is
23265 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
23266 (UINT32_C(0x1) << 30)
23267 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
23268 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
23269 /* Indicate the flow direction. */
23270 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
23271 UINT32_C(0x80000000)
23272 /* If this bit set to 0, then it indicates rx flow. */
23273 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
23274 (UINT32_C(0x0) << 31)
23275 /* If this bit is set to 1, then it indicates that tx flow. */
23276 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
23277 (UINT32_C(0x1) << 31)
23278 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
23279 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
23280 uint8_t unused_0[3];
23282 * This field is used in Output records to indicate that the output
23283 * is completely written to RAM. This field should be read as '1'
23284 * to indicate that the output has been completely written.
23285 * When writing a command completion or response to an internal processor,
23286 * the order of writes has to be such that this field is written last.
23289 } __attribute__((packed));
23291 /***************************
23292 * hwrm_cfa_l2_filter_free *
23293 ***************************/
23296 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
23297 struct hwrm_cfa_l2_filter_free_input {
23298 /* The HWRM command request type. */
23301 * The completion ring to send the completion event on. This should
23302 * be the NQ ID returned from the `nq_alloc` HWRM command.
23304 uint16_t cmpl_ring;
23306 * The sequence ID is used by the driver for tracking multiple
23307 * commands. This ID is treated as opaque data by the firmware and
23308 * the value is returned in the `hwrm_resp_hdr` upon completion.
23312 * The target ID of the command:
23313 * * 0x0-0xFFF8 - The function ID
23314 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23315 * * 0xFFFD - Reserved for user-space HWRM interface
23318 uint16_t target_id;
23320 * A physical address pointer pointing to a host buffer that the
23321 * command's response data will be written. This can be either a host
23322 * physical address (HPA) or a guest physical address (GPA) and must
23323 * point to a physically contiguous block of memory.
23325 uint64_t resp_addr;
23327 * This value identifies a set of CFA data structures used for an L2
23330 uint64_t l2_filter_id;
23331 } __attribute__((packed));
23333 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
23334 struct hwrm_cfa_l2_filter_free_output {
23335 /* The specific error status for the command. */
23336 uint16_t error_code;
23337 /* The HWRM command request type. */
23339 /* The sequence ID from the original command. */
23341 /* The length of the response data in number of bytes. */
23343 uint8_t unused_0[7];
23345 * This field is used in Output records to indicate that the output
23346 * is completely written to RAM. This field should be read as '1'
23347 * to indicate that the output has been completely written.
23348 * When writing a command completion or response to an internal processor,
23349 * the order of writes has to be such that this field is written last.
23352 } __attribute__((packed));
23354 /**************************
23355 * hwrm_cfa_l2_filter_cfg *
23356 **************************/
23359 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
23360 struct hwrm_cfa_l2_filter_cfg_input {
23361 /* The HWRM command request type. */
23364 * The completion ring to send the completion event on. This should
23365 * be the NQ ID returned from the `nq_alloc` HWRM command.
23367 uint16_t cmpl_ring;
23369 * The sequence ID is used by the driver for tracking multiple
23370 * commands. This ID is treated as opaque data by the firmware and
23371 * the value is returned in the `hwrm_resp_hdr` upon completion.
23375 * The target ID of the command:
23376 * * 0x0-0xFFF8 - The function ID
23377 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23378 * * 0xFFFD - Reserved for user-space HWRM interface
23381 uint16_t target_id;
23383 * A physical address pointer pointing to a host buffer that the
23384 * command's response data will be written. This can be either a host
23385 * physical address (HPA) or a guest physical address (GPA) and must
23386 * point to a physically contiguous block of memory.
23388 uint64_t resp_addr;
23391 * Enumeration denoting the RX, TX type of the resource.
23392 * This enumeration is used for resources that are similar for both
23393 * TX and RX paths of the chip.
23395 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
23398 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
23401 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
23403 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
23404 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
23406 * Setting of this flag indicates drop action. If this flag is not set,
23407 * then it should be considered accept action.
23409 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
23412 * Enumeration denoting NO_ROCE_L2 to support old drivers.
23413 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
23415 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
23417 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
23418 /* To support old drivers */
23419 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
23420 (UINT32_C(0x0) << 2)
23421 /* Only L2 traffic */
23422 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
23423 (UINT32_C(0x1) << 2)
23424 /* Roce & L2 traffic */
23425 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
23426 (UINT32_C(0x2) << 2)
23427 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
23428 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
23431 * This bit must be '1' for the dst_id field to be
23434 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
23437 * This bit must be '1' for the new_mirror_vnic_id field to be
23440 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
23443 * This value identifies a set of CFA data structures used for an L2
23446 uint64_t l2_filter_id;
23448 * If set, this value shall represent the
23449 * Logical VNIC ID of the destination VNIC for the RX
23450 * path and network port id of the destination port for
23455 * New Logical VNIC ID of the VNIC where traffic is
23458 uint32_t new_mirror_vnic_id;
23459 } __attribute__((packed));
23461 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
23462 struct hwrm_cfa_l2_filter_cfg_output {
23463 /* The specific error status for the command. */
23464 uint16_t error_code;
23465 /* The HWRM command request type. */
23467 /* The sequence ID from the original command. */
23469 /* The length of the response data in number of bytes. */
23471 uint8_t unused_0[7];
23473 * This field is used in Output records to indicate that the output
23474 * is completely written to RAM. This field should be read as '1'
23475 * to indicate that the output has been completely written.
23476 * When writing a command completion or response to an internal processor,
23477 * the order of writes has to be such that this field is written last.
23480 } __attribute__((packed));
23482 /***************************
23483 * hwrm_cfa_l2_set_rx_mask *
23484 ***************************/
23487 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
23488 struct hwrm_cfa_l2_set_rx_mask_input {
23489 /* The HWRM command request type. */
23492 * The completion ring to send the completion event on. This should
23493 * be the NQ ID returned from the `nq_alloc` HWRM command.
23495 uint16_t cmpl_ring;
23497 * The sequence ID is used by the driver for tracking multiple
23498 * commands. This ID is treated as opaque data by the firmware and
23499 * the value is returned in the `hwrm_resp_hdr` upon completion.
23503 * The target ID of the command:
23504 * * 0x0-0xFFF8 - The function ID
23505 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23506 * * 0xFFFD - Reserved for user-space HWRM interface
23509 uint16_t target_id;
23511 * A physical address pointer pointing to a host buffer that the
23512 * command's response data will be written. This can be either a host
23513 * physical address (HPA) or a guest physical address (GPA) and must
23514 * point to a physically contiguous block of memory.
23516 uint64_t resp_addr;
23521 * When this bit is '1', the function is requested to accept
23522 * multi-cast packets specified by the multicast addr table.
23524 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
23527 * When this bit is '1', the function is requested to accept
23528 * all multi-cast packets.
23530 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
23533 * When this bit is '1', the function is requested to accept
23534 * broadcast packets.
23536 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
23539 * When this bit is '1', the function is requested to be
23540 * put in the promiscuous mode.
23542 * The HWRM should accept any function to set up
23543 * promiscuous mode.
23545 * The HWRM shall follow the semantics below for the
23546 * promiscuous mode support.
23547 * # When partitioning is not enabled on a port
23548 * (i.e. single PF on the port), then the PF shall
23549 * be allowed to be in the promiscuous mode. When the
23550 * PF is in the promiscuous mode, then it shall
23551 * receive all host bound traffic on that port.
23552 * # When partitioning is enabled on a port
23553 * (i.e. multiple PFs per port) and a PF on that
23554 * port is in the promiscuous mode, then the PF
23555 * receives all traffic within that partition as
23556 * identified by a unique identifier for the
23557 * PF (e.g. S-Tag). If a unique outer VLAN
23558 * for the PF is specified, then the setting of
23559 * promiscuous mode on that PF shall result in the
23560 * PF receiving all host bound traffic with matching
23562 * # A VF shall can be set in the promiscuous mode.
23563 * In the promiscuous mode, the VF does not receive any
23564 * traffic unless a unique outer VLAN for the
23565 * VF is specified. If a unique outer VLAN
23566 * for the VF is specified, then the setting of
23567 * promiscuous mode on that VF shall result in the
23568 * VF receiving all host bound traffic with the
23569 * matching outer VLAN.
23570 * # The HWRM shall allow the setting of promiscuous
23571 * mode on a function independently from the
23572 * promiscuous mode settings on other functions.
23574 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
23577 * If this flag is set, the corresponding RX
23578 * filters shall be set up to cover multicast/broadcast
23579 * filters for the outermost Layer 2 destination MAC
23582 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
23585 * If this flag is set, the corresponding RX
23586 * filters shall be set up to cover multicast/broadcast
23587 * filters for the VLAN-tagged packets that match the
23588 * TPID and VID fields of VLAN tags in the VLAN tag
23589 * table specified in this command.
23591 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
23594 * If this flag is set, the corresponding RX
23595 * filters shall be set up to cover multicast/broadcast
23596 * filters for non-VLAN tagged packets and VLAN-tagged
23597 * packets that match the TPID and VID fields of VLAN
23598 * tags in the VLAN tag table specified in this command.
23600 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
23603 * If this flag is set, the corresponding RX
23604 * filters shall be set up to cover multicast/broadcast
23605 * filters for non-VLAN tagged packets and VLAN-tagged
23606 * packets matching any VLAN tag.
23608 * If this flag is set, then the HWRM shall ignore
23609 * VLAN tags specified in vlan_tag_tbl.
23611 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
23612 * flags is set, then the HWRM shall ignore
23613 * VLAN tags specified in vlan_tag_tbl.
23615 * The HWRM client shall set at most one flag out of
23616 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
23618 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
23620 /* This is the address for mcast address tbl. */
23621 uint64_t mc_tbl_addr;
23623 * This value indicates how many entries in mc_tbl are valid.
23624 * Each entry is 6 bytes.
23626 uint32_t num_mc_entries;
23627 uint8_t unused_0[4];
23629 * This is the address for VLAN tag table.
23630 * Each VLAN entry in the table is 4 bytes of a VLAN tag
23631 * including TPID, PCP, DEI, and VID fields in network byte
23634 uint64_t vlan_tag_tbl_addr;
23636 * This value indicates how many entries in vlan_tag_tbl are
23637 * valid. Each entry is 4 bytes.
23639 uint32_t num_vlan_tags;
23640 uint8_t unused_1[4];
23641 } __attribute__((packed));
23643 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
23644 struct hwrm_cfa_l2_set_rx_mask_output {
23645 /* The specific error status for the command. */
23646 uint16_t error_code;
23647 /* The HWRM command request type. */
23649 /* The sequence ID from the original command. */
23651 /* The length of the response data in number of bytes. */
23653 uint8_t unused_0[7];
23655 * This field is used in Output records to indicate that the output
23656 * is completely written to RAM. This field should be read as '1'
23657 * to indicate that the output has been completely written.
23658 * When writing a command completion or response to an internal processor,
23659 * the order of writes has to be such that this field is written last.
23662 } __attribute__((packed));
23664 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
23665 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
23667 * command specific error codes that goes to
23668 * the cmd_err field in Common HWRM Error Response.
23671 /* Unknown error */
23672 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
23674 /* Unable to complete operation due to conflict with Ntuple Filter */
23675 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
23677 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
23678 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
23679 uint8_t unused_0[7];
23680 } __attribute__((packed));
23682 /*******************************
23683 * hwrm_cfa_vlan_antispoof_cfg *
23684 *******************************/
23687 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
23688 struct hwrm_cfa_vlan_antispoof_cfg_input {
23689 /* The HWRM command request type. */
23692 * The completion ring to send the completion event on. This should
23693 * be the NQ ID returned from the `nq_alloc` HWRM command.
23695 uint16_t cmpl_ring;
23697 * The sequence ID is used by the driver for tracking multiple
23698 * commands. This ID is treated as opaque data by the firmware and
23699 * the value is returned in the `hwrm_resp_hdr` upon completion.
23703 * The target ID of the command:
23704 * * 0x0-0xFFF8 - The function ID
23705 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23706 * * 0xFFFD - Reserved for user-space HWRM interface
23709 uint16_t target_id;
23711 * A physical address pointer pointing to a host buffer that the
23712 * command's response data will be written. This can be either a host
23713 * physical address (HPA) or a guest physical address (GPA) and must
23714 * point to a physically contiguous block of memory.
23716 uint64_t resp_addr;
23718 * Function ID of the function that is being configured.
23719 * Only valid for a VF FID configured by the PF.
23722 uint8_t unused_0[2];
23723 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
23724 uint32_t num_vlan_entries;
23726 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
23727 * antispoof table. Each table entry contains the 16-bit TPID
23728 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
23729 * all in network order to match hwrm_cfa_l2_set_rx_mask.
23730 * For an individual VLAN entry, the mask value should be 0xfff
23731 * for the 12-bit VLAN ID.
23733 uint64_t vlan_tag_mask_tbl_addr;
23734 } __attribute__((packed));
23736 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
23737 struct hwrm_cfa_vlan_antispoof_cfg_output {
23738 /* The specific error status for the command. */
23739 uint16_t error_code;
23740 /* The HWRM command request type. */
23742 /* The sequence ID from the original command. */
23744 /* The length of the response data in number of bytes. */
23746 uint8_t unused_0[7];
23748 * This field is used in Output records to indicate that the output
23749 * is completely written to RAM. This field should be read as '1'
23750 * to indicate that the output has been completely written.
23751 * When writing a command completion or response to an internal processor,
23752 * the order of writes has to be such that this field is written last.
23755 } __attribute__((packed));
23757 /********************************
23758 * hwrm_cfa_vlan_antispoof_qcfg *
23759 ********************************/
23762 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
23763 struct hwrm_cfa_vlan_antispoof_qcfg_input {
23764 /* The HWRM command request type. */
23767 * The completion ring to send the completion event on. This should
23768 * be the NQ ID returned from the `nq_alloc` HWRM command.
23770 uint16_t cmpl_ring;
23772 * The sequence ID is used by the driver for tracking multiple
23773 * commands. This ID is treated as opaque data by the firmware and
23774 * the value is returned in the `hwrm_resp_hdr` upon completion.
23778 * The target ID of the command:
23779 * * 0x0-0xFFF8 - The function ID
23780 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23781 * * 0xFFFD - Reserved for user-space HWRM interface
23784 uint16_t target_id;
23786 * A physical address pointer pointing to a host buffer that the
23787 * command's response data will be written. This can be either a host
23788 * physical address (HPA) or a guest physical address (GPA) and must
23789 * point to a physically contiguous block of memory.
23791 uint64_t resp_addr;
23793 * Function ID of the function that is being queried.
23794 * Only valid for a VF FID queried by the PF.
23797 uint8_t unused_0[2];
23799 * Maximum number of VLAN entries the firmware is allowed to DMA
23800 * to vlan_tag_mask_tbl.
23802 uint32_t max_vlan_entries;
23804 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
23805 * antispoof table to which firmware will DMA to. Each table
23806 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
23807 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
23808 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
23809 * the mask value should be 0xfff for the 12-bit VLAN ID.
23811 uint64_t vlan_tag_mask_tbl_addr;
23812 } __attribute__((packed));
23814 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
23815 struct hwrm_cfa_vlan_antispoof_qcfg_output {
23816 /* The specific error status for the command. */
23817 uint16_t error_code;
23818 /* The HWRM command request type. */
23820 /* The sequence ID from the original command. */
23822 /* The length of the response data in number of bytes. */
23824 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
23825 uint32_t num_vlan_entries;
23826 uint8_t unused_0[3];
23828 * This field is used in Output records to indicate that the output
23829 * is completely written to RAM. This field should be read as '1'
23830 * to indicate that the output has been completely written.
23831 * When writing a command completion or response to an internal processor,
23832 * the order of writes has to be such that this field is written last.
23835 } __attribute__((packed));
23837 /********************************
23838 * hwrm_cfa_tunnel_filter_alloc *
23839 ********************************/
23842 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
23843 struct hwrm_cfa_tunnel_filter_alloc_input {
23844 /* The HWRM command request type. */
23847 * The completion ring to send the completion event on. This should
23848 * be the NQ ID returned from the `nq_alloc` HWRM command.
23850 uint16_t cmpl_ring;
23852 * The sequence ID is used by the driver for tracking multiple
23853 * commands. This ID is treated as opaque data by the firmware and
23854 * the value is returned in the `hwrm_resp_hdr` upon completion.
23858 * The target ID of the command:
23859 * * 0x0-0xFFF8 - The function ID
23860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23861 * * 0xFFFD - Reserved for user-space HWRM interface
23864 uint16_t target_id;
23866 * A physical address pointer pointing to a host buffer that the
23867 * command's response data will be written. This can be either a host
23868 * physical address (HPA) or a guest physical address (GPA) and must
23869 * point to a physically contiguous block of memory.
23871 uint64_t resp_addr;
23873 /* Setting of this flag indicates the applicability to the loopback path. */
23874 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23878 * This bit must be '1' for the l2_filter_id field to be
23881 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
23884 * This bit must be '1' for the l2_addr field to be
23887 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
23890 * This bit must be '1' for the l2_ivlan field to be
23893 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
23896 * This bit must be '1' for the l3_addr field to be
23899 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
23902 * This bit must be '1' for the l3_addr_type field to be
23905 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
23908 * This bit must be '1' for the t_l3_addr_type field to be
23911 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
23914 * This bit must be '1' for the t_l3_addr field to be
23917 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
23920 * This bit must be '1' for the tunnel_type field to be
23923 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23926 * This bit must be '1' for the vni field to be
23929 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
23932 * This bit must be '1' for the dst_vnic_id field to be
23935 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
23938 * This bit must be '1' for the mirror_vnic_id field to be
23941 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23944 * This value identifies a set of CFA data structures used for an L2
23947 uint64_t l2_filter_id;
23949 * This value sets the match value for the inner L2
23951 * Destination MAC address for RX path.
23952 * Source MAC address for TX path.
23954 uint8_t l2_addr[6];
23956 * This value sets VLAN ID value for inner VLAN.
23957 * Only 12-bits of VLAN ID are used in setting the filter.
23961 * The value of inner destination IP address to be used in filtering.
23962 * For IPv4, first four bytes represent the IP address.
23964 uint32_t l3_addr[4];
23966 * The value of tunnel destination IP address to be used in filtering.
23967 * For IPv4, first four bytes represent the IP address.
23969 uint32_t t_l3_addr[4];
23971 * This value indicates the type of inner IP address.
23974 * All others are invalid.
23976 uint8_t l3_addr_type;
23978 * This value indicates the type of tunnel IP address.
23981 * All others are invalid.
23983 uint8_t t_l3_addr_type;
23985 uint8_t tunnel_type;
23987 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23989 /* Virtual eXtensible Local Area Network (VXLAN) */
23990 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23992 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23993 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23995 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23996 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23999 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24001 /* Generic Network Virtualization Encapsulation (Geneve) */
24002 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24004 /* Multi-Protocol Lable Switching (MPLS) */
24005 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24007 /* Stateless Transport Tunnel (STT) */
24008 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
24010 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24011 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24013 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24014 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24016 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24017 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24019 /* Use fixed layer 2 ether type of 0xFFFF */
24020 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24022 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24023 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24025 /* Any tunneled traffic */
24026 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24028 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24029 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24031 * tunnel_flags allows the user to indicate the tunnel tag detection
24032 * for the tunnel type specified in tunnel_type.
24034 uint8_t tunnel_flags;
24036 * If the tunnel_type is geneve, then this bit indicates if we
24037 * need to match the geneve OAM packet.
24038 * If the tunnel_type is nvgre or gre, then this bit indicates if
24039 * we need to detect checksum present bit in geneve header.
24040 * If the tunnel_type is mpls, then this bit indicates if we need
24041 * to match mpls packet with explicit IPV4/IPV6 null header.
24043 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
24046 * If the tunnel_type is geneve, then this bit indicates if we
24047 * need to detect the critical option bit set in the oam packet.
24048 * If the tunnel_type is nvgre or gre, then this bit indicates
24049 * if we need to match nvgre packets with key present bit set in
24051 * If the tunnel_type is mpls, then this bit indicates if we
24052 * need to match mpls packet with S bit from inner/second label.
24054 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
24057 * If the tunnel_type is geneve, then this bit indicates if we
24058 * need to match geneve packet with extended header bit set in
24060 * If the tunnel_type is nvgre or gre, then this bit indicates
24061 * if we need to match nvgre packets with sequence number
24062 * present bit set in gre header.
24063 * If the tunnel_type is mpls, then this bit indicates if we
24064 * need to match mpls packet with S bit from out/first label.
24066 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
24069 * Virtual Network Identifier (VNI). Only valid with
24070 * tunnel_types VXLAN, NVGRE, and Geneve.
24071 * Only lower 24-bits of VNI field are used
24072 * in setting up the filter.
24075 /* Logical VNIC ID of the destination VNIC. */
24076 uint32_t dst_vnic_id;
24078 * Logical VNIC ID of the VNIC where traffic is
24081 uint32_t mirror_vnic_id;
24082 } __attribute__((packed));
24084 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
24085 struct hwrm_cfa_tunnel_filter_alloc_output {
24086 /* The specific error status for the command. */
24087 uint16_t error_code;
24088 /* The HWRM command request type. */
24090 /* The sequence ID from the original command. */
24092 /* The length of the response data in number of bytes. */
24094 /* This value is an opaque id into CFA data structures. */
24095 uint64_t tunnel_filter_id;
24097 * The flow id value in bit 0-29 is the actual ID of the flow
24098 * associated with this filter and it shall be used to match
24099 * and associate the flow identifier returned in completion
24100 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
24101 * shall indicate no valid flow id.
24104 /* Indicate the flow id value. */
24105 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
24106 UINT32_C(0x3fffffff)
24107 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
24108 /* Indicate type of the flow. */
24109 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
24110 UINT32_C(0x40000000)
24112 * If this bit set to 0, then it indicates that the flow is
24115 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
24116 (UINT32_C(0x0) << 30)
24118 * If this bit is set to 1, then it indicates that the flow is
24121 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
24122 (UINT32_C(0x1) << 30)
24123 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
24124 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
24125 /* Indicate the flow direction. */
24126 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
24127 UINT32_C(0x80000000)
24128 /* If this bit set to 0, then it indicates rx flow. */
24129 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
24130 (UINT32_C(0x0) << 31)
24131 /* If this bit is set to 1, then it indicates that tx flow. */
24132 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
24133 (UINT32_C(0x1) << 31)
24134 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
24135 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
24136 uint8_t unused_0[3];
24138 * This field is used in Output records to indicate that the output
24139 * is completely written to RAM. This field should be read as '1'
24140 * to indicate that the output has been completely written.
24141 * When writing a command completion or response to an internal processor,
24142 * the order of writes has to be such that this field is written last.
24145 } __attribute__((packed));
24147 /*******************************
24148 * hwrm_cfa_tunnel_filter_free *
24149 *******************************/
24152 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
24153 struct hwrm_cfa_tunnel_filter_free_input {
24154 /* The HWRM command request type. */
24157 * The completion ring to send the completion event on. This should
24158 * be the NQ ID returned from the `nq_alloc` HWRM command.
24160 uint16_t cmpl_ring;
24162 * The sequence ID is used by the driver for tracking multiple
24163 * commands. This ID is treated as opaque data by the firmware and
24164 * the value is returned in the `hwrm_resp_hdr` upon completion.
24168 * The target ID of the command:
24169 * * 0x0-0xFFF8 - The function ID
24170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24171 * * 0xFFFD - Reserved for user-space HWRM interface
24174 uint16_t target_id;
24176 * A physical address pointer pointing to a host buffer that the
24177 * command's response data will be written. This can be either a host
24178 * physical address (HPA) or a guest physical address (GPA) and must
24179 * point to a physically contiguous block of memory.
24181 uint64_t resp_addr;
24182 /* This value is an opaque id into CFA data structures. */
24183 uint64_t tunnel_filter_id;
24184 } __attribute__((packed));
24186 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
24187 struct hwrm_cfa_tunnel_filter_free_output {
24188 /* The specific error status for the command. */
24189 uint16_t error_code;
24190 /* The HWRM command request type. */
24192 /* The sequence ID from the original command. */
24194 /* The length of the response data in number of bytes. */
24196 uint8_t unused_0[7];
24198 * This field is used in Output records to indicate that the output
24199 * is completely written to RAM. This field should be read as '1'
24200 * to indicate that the output has been completely written.
24201 * When writing a command completion or response to an internal processor,
24202 * the order of writes has to be such that this field is written last.
24205 } __attribute__((packed));
24207 /***************************************
24208 * hwrm_cfa_redirect_tunnel_type_alloc *
24209 ***************************************/
24212 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
24213 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
24214 /* The HWRM command request type. */
24217 * The completion ring to send the completion event on. This should
24218 * be the NQ ID returned from the `nq_alloc` HWRM command.
24220 uint16_t cmpl_ring;
24222 * The sequence ID is used by the driver for tracking multiple
24223 * commands. This ID is treated as opaque data by the firmware and
24224 * the value is returned in the `hwrm_resp_hdr` upon completion.
24228 * The target ID of the command:
24229 * * 0x0-0xFFF8 - The function ID
24230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24231 * * 0xFFFD - Reserved for user-space HWRM interface
24234 uint16_t target_id;
24236 * A physical address pointer pointing to a host buffer that the
24237 * command's response data will be written. This can be either a host
24238 * physical address (HPA) or a guest physical address (GPA) and must
24239 * point to a physically contiguous block of memory.
24241 uint64_t resp_addr;
24242 /* The destination function id, to whom the traffic is redirected. */
24245 uint8_t tunnel_type;
24247 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
24249 /* Virtual eXtensible Local Area Network (VXLAN) */
24250 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24252 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24253 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
24255 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24256 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
24259 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24261 /* Generic Network Virtualization Encapsulation (Geneve) */
24262 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24264 /* Multi-Protocol Lable Switching (MPLS) */
24265 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24267 /* Stateless Transport Tunnel (STT) */
24268 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
24270 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24271 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24273 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24274 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24276 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24277 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24279 /* Use fixed layer 2 ether type of 0xFFFF */
24280 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24282 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24283 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24285 /* Any tunneled traffic */
24286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24288 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24289 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24290 /* Tunnel alloc flags. */
24292 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
24293 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
24295 uint8_t unused_0[4];
24296 } __attribute__((packed));
24298 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
24299 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
24300 /* The specific error status for the command. */
24301 uint16_t error_code;
24302 /* The HWRM command request type. */
24304 /* The sequence ID from the original command. */
24306 /* The length of the response data in number of bytes. */
24308 uint8_t unused_0[7];
24310 * This field is used in Output records to indicate that the output
24311 * is completely written to RAM. This field should be read as '1'
24312 * to indicate that the output has been completely written.
24313 * When writing a command completion or response to an internal processor,
24314 * the order of writes has to be such that this field is written last.
24317 } __attribute__((packed));
24319 /**************************************
24320 * hwrm_cfa_redirect_tunnel_type_free *
24321 **************************************/
24324 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
24325 struct hwrm_cfa_redirect_tunnel_type_free_input {
24326 /* The HWRM command request type. */
24329 * The completion ring to send the completion event on. This should
24330 * be the NQ ID returned from the `nq_alloc` HWRM command.
24332 uint16_t cmpl_ring;
24334 * The sequence ID is used by the driver for tracking multiple
24335 * commands. This ID is treated as opaque data by the firmware and
24336 * the value is returned in the `hwrm_resp_hdr` upon completion.
24340 * The target ID of the command:
24341 * * 0x0-0xFFF8 - The function ID
24342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24343 * * 0xFFFD - Reserved for user-space HWRM interface
24346 uint16_t target_id;
24348 * A physical address pointer pointing to a host buffer that the
24349 * command's response data will be written. This can be either a host
24350 * physical address (HPA) or a guest physical address (GPA) and must
24351 * point to a physically contiguous block of memory.
24353 uint64_t resp_addr;
24354 /* The destination function id, to whom the traffic is redirected. */
24357 uint8_t tunnel_type;
24359 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
24361 /* Virtual eXtensible Local Area Network (VXLAN) */
24362 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
24364 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24365 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
24367 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24368 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
24371 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
24373 /* Generic Network Virtualization Encapsulation (Geneve) */
24374 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
24376 /* Multi-Protocol Lable Switching (MPLS) */
24377 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
24379 /* Stateless Transport Tunnel (STT) */
24380 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
24382 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24383 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
24385 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24386 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24388 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24389 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24391 /* Use fixed layer 2 ether type of 0xFFFF */
24392 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
24394 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24395 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24397 /* Any tunneled traffic */
24398 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24400 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
24401 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
24402 uint8_t unused_0[5];
24403 } __attribute__((packed));
24405 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
24406 struct hwrm_cfa_redirect_tunnel_type_free_output {
24407 /* The specific error status for the command. */
24408 uint16_t error_code;
24409 /* The HWRM command request type. */
24411 /* The sequence ID from the original command. */
24413 /* The length of the response data in number of bytes. */
24415 uint8_t unused_0[7];
24417 * This field is used in Output records to indicate that the output
24418 * is completely written to RAM. This field should be read as '1'
24419 * to indicate that the output has been completely written.
24420 * When writing a command completion or response to an internal processor,
24421 * the order of writes has to be such that this field is written last.
24424 } __attribute__((packed));
24426 /**************************************
24427 * hwrm_cfa_redirect_tunnel_type_info *
24428 **************************************/
24431 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
24432 struct hwrm_cfa_redirect_tunnel_type_info_input {
24433 /* The HWRM command request type. */
24436 * The completion ring to send the completion event on. This should
24437 * be the NQ ID returned from the `nq_alloc` HWRM command.
24439 uint16_t cmpl_ring;
24441 * The sequence ID is used by the driver for tracking multiple
24442 * commands. This ID is treated as opaque data by the firmware and
24443 * the value is returned in the `hwrm_resp_hdr` upon completion.
24447 * The target ID of the command:
24448 * * 0x0-0xFFF8 - The function ID
24449 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24450 * * 0xFFFD - Reserved for user-space HWRM interface
24453 uint16_t target_id;
24455 * A physical address pointer pointing to a host buffer that the
24456 * command's response data will be written. This can be either a host
24457 * physical address (HPA) or a guest physical address (GPA) and must
24458 * point to a physically contiguous block of memory.
24460 uint64_t resp_addr;
24461 /* The source function id. */
24464 uint8_t tunnel_type;
24466 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
24468 /* Virtual eXtensible Local Area Network (VXLAN) */
24469 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
24471 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24472 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
24474 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
24478 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
24480 /* Generic Network Virtualization Encapsulation (Geneve) */
24481 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
24483 /* Multi-Protocol Lable Switching (MPLS) */
24484 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
24486 /* Stateless Transport Tunnel (STT) */
24487 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
24489 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24490 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
24492 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24493 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24495 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24496 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24498 /* Use fixed layer 2 ether type of 0xFFFF */
24499 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
24501 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24502 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24504 /* Any tunneled traffic */
24505 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24507 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
24508 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
24509 uint8_t unused_0[5];
24510 } __attribute__((packed));
24512 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
24513 struct hwrm_cfa_redirect_tunnel_type_info_output {
24514 /* The specific error status for the command. */
24515 uint16_t error_code;
24516 /* The HWRM command request type. */
24518 /* The sequence ID from the original command. */
24520 /* The length of the response data in number of bytes. */
24522 /* The destination function id, to whom the traffic is redirected. */
24524 uint8_t unused_0[5];
24526 * This field is used in Output records to indicate that the output
24527 * is completely written to RAM. This field should be read as '1'
24528 * to indicate that the output has been completely written.
24529 * When writing a command completion or response to an internal processor,
24530 * the order of writes has to be such that this field is written last.
24533 } __attribute__((packed));
24535 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
24536 struct hwrm_vxlan_ipv4_hdr {
24537 /* IPv4 version and header length. */
24539 /* IPv4 header length */
24540 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
24541 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
24543 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
24544 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
24545 /* IPv4 type of service. */
24547 /* IPv4 identification. */
24549 /* IPv4 flags and offset. */
24550 uint16_t flags_frag_offset;
24553 /* IPv4 protocol. */
24555 /* IPv4 source address. */
24556 uint32_t src_ip_addr;
24557 /* IPv4 destination address. */
24558 uint32_t dest_ip_addr;
24559 } __attribute__((packed));
24561 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
24562 struct hwrm_vxlan_ipv6_hdr {
24563 /* IPv6 version, traffic class and flow label. */
24564 uint32_t ver_tc_flow_label;
24565 /* IPv6 version shift */
24566 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
24568 /* IPv6 version mask */
24569 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
24570 UINT32_C(0xf0000000)
24571 /* IPv6 TC shift */
24572 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
24575 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
24576 UINT32_C(0xff00000)
24577 /* IPv6 flow label shift */
24578 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
24580 /* IPv6 flow label mask */
24581 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
24583 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
24584 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
24585 /* IPv6 payload length. */
24586 uint16_t payload_len;
24587 /* IPv6 next header. */
24591 /* IPv6 source address. */
24592 uint32_t src_ip_addr[4];
24593 /* IPv6 destination address. */
24594 uint32_t dest_ip_addr[4];
24595 } __attribute__((packed));
24597 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
24598 struct hwrm_cfa_encap_data_vxlan {
24599 /* Source MAC address. */
24600 uint8_t src_mac_addr[6];
24603 /* Destination MAC address. */
24604 uint8_t dst_mac_addr[6];
24605 /* Number of VLAN tags. */
24606 uint8_t num_vlan_tags;
24609 /* Outer VLAN TPID. */
24610 uint16_t ovlan_tpid;
24611 /* Outer VLAN TCI. */
24612 uint16_t ovlan_tci;
24613 /* Inner VLAN TPID. */
24614 uint16_t ivlan_tpid;
24615 /* Inner VLAN TCI. */
24616 uint16_t ivlan_tci;
24617 /* L3 header fields. */
24619 /* IP version mask. */
24620 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
24621 /* IP version 4. */
24622 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
24623 /* IP version 6. */
24624 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
24625 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
24626 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
24627 /* UDP source port. */
24629 /* UDP destination port. */
24631 /* VXLAN Network Identifier. */
24633 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
24634 uint8_t hdr_rsvd0[3];
24635 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
24637 /* VXLAN header flags field. */
24640 } __attribute__((packed));
24642 /*******************************
24643 * hwrm_cfa_encap_record_alloc *
24644 *******************************/
24647 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
24648 struct hwrm_cfa_encap_record_alloc_input {
24649 /* The HWRM command request type. */
24652 * The completion ring to send the completion event on. This should
24653 * be the NQ ID returned from the `nq_alloc` HWRM command.
24655 uint16_t cmpl_ring;
24657 * The sequence ID is used by the driver for tracking multiple
24658 * commands. This ID is treated as opaque data by the firmware and
24659 * the value is returned in the `hwrm_resp_hdr` upon completion.
24663 * The target ID of the command:
24664 * * 0x0-0xFFF8 - The function ID
24665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24666 * * 0xFFFD - Reserved for user-space HWRM interface
24669 uint16_t target_id;
24671 * A physical address pointer pointing to a host buffer that the
24672 * command's response data will be written. This can be either a host
24673 * physical address (HPA) or a guest physical address (GPA) and must
24674 * point to a physically contiguous block of memory.
24676 uint64_t resp_addr;
24678 /* Setting of this flag indicates the applicability to the loopback path. */
24679 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
24682 * Setting of this flag indicates this encap record is external encap record.
24683 * Resetting of this flag indicates this flag is internal encap record and
24684 * this is the default setting.
24686 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
24688 /* Encapsulation Type. */
24689 uint8_t encap_type;
24690 /* Virtual eXtensible Local Area Network (VXLAN) */
24691 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
24693 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24694 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
24696 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
24697 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
24700 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
24702 /* Generic Network Virtualization Encapsulation (Geneve) */
24703 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
24705 /* Multi-Protocol Lable Switching (MPLS) */
24706 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
24709 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
24711 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24712 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
24714 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24715 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
24717 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24718 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
24720 /* Use fixed layer 2 ether type of 0xFFFF */
24721 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
24723 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24724 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
24726 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
24727 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
24728 uint8_t unused_0[3];
24729 /* This value is encap data used for the given encap type. */
24730 uint32_t encap_data[20];
24731 } __attribute__((packed));
24733 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
24734 struct hwrm_cfa_encap_record_alloc_output {
24735 /* The specific error status for the command. */
24736 uint16_t error_code;
24737 /* The HWRM command request type. */
24739 /* The sequence ID from the original command. */
24741 /* The length of the response data in number of bytes. */
24743 /* This value is an opaque id into CFA data structures. */
24744 uint32_t encap_record_id;
24745 uint8_t unused_0[3];
24747 * This field is used in Output records to indicate that the output
24748 * is completely written to RAM. This field should be read as '1'
24749 * to indicate that the output has been completely written.
24750 * When writing a command completion or response to an internal processor,
24751 * the order of writes has to be such that this field is written last.
24754 } __attribute__((packed));
24756 /******************************
24757 * hwrm_cfa_encap_record_free *
24758 ******************************/
24761 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
24762 struct hwrm_cfa_encap_record_free_input {
24763 /* The HWRM command request type. */
24766 * The completion ring to send the completion event on. This should
24767 * be the NQ ID returned from the `nq_alloc` HWRM command.
24769 uint16_t cmpl_ring;
24771 * The sequence ID is used by the driver for tracking multiple
24772 * commands. This ID is treated as opaque data by the firmware and
24773 * the value is returned in the `hwrm_resp_hdr` upon completion.
24777 * The target ID of the command:
24778 * * 0x0-0xFFF8 - The function ID
24779 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24780 * * 0xFFFD - Reserved for user-space HWRM interface
24783 uint16_t target_id;
24785 * A physical address pointer pointing to a host buffer that the
24786 * command's response data will be written. This can be either a host
24787 * physical address (HPA) or a guest physical address (GPA) and must
24788 * point to a physically contiguous block of memory.
24790 uint64_t resp_addr;
24791 /* This value is an opaque id into CFA data structures. */
24792 uint32_t encap_record_id;
24793 uint8_t unused_0[4];
24794 } __attribute__((packed));
24796 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
24797 struct hwrm_cfa_encap_record_free_output {
24798 /* The specific error status for the command. */
24799 uint16_t error_code;
24800 /* The HWRM command request type. */
24802 /* The sequence ID from the original command. */
24804 /* The length of the response data in number of bytes. */
24806 uint8_t unused_0[7];
24808 * This field is used in Output records to indicate that the output
24809 * is completely written to RAM. This field should be read as '1'
24810 * to indicate that the output has been completely written.
24811 * When writing a command completion or response to an internal processor,
24812 * the order of writes has to be such that this field is written last.
24815 } __attribute__((packed));
24817 /********************************
24818 * hwrm_cfa_ntuple_filter_alloc *
24819 ********************************/
24822 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
24823 struct hwrm_cfa_ntuple_filter_alloc_input {
24824 /* The HWRM command request type. */
24827 * The completion ring to send the completion event on. This should
24828 * be the NQ ID returned from the `nq_alloc` HWRM command.
24830 uint16_t cmpl_ring;
24832 * The sequence ID is used by the driver for tracking multiple
24833 * commands. This ID is treated as opaque data by the firmware and
24834 * the value is returned in the `hwrm_resp_hdr` upon completion.
24838 * The target ID of the command:
24839 * * 0x0-0xFFF8 - The function ID
24840 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24841 * * 0xFFFD - Reserved for user-space HWRM interface
24844 uint16_t target_id;
24846 * A physical address pointer pointing to a host buffer that the
24847 * command's response data will be written. This can be either a host
24848 * physical address (HPA) or a guest physical address (GPA) and must
24849 * point to a physically contiguous block of memory.
24851 uint64_t resp_addr;
24853 /* Setting of this flag indicates the applicability to the loopback path. */
24854 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
24857 * Setting of this flag indicates drop action. If this flag is not set,
24858 * then it should be considered accept action.
24860 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
24863 * Setting of this flag indicates that a meter is expected to be attached
24864 * to this flow. This hint can be used when choosing the action record
24865 * format required for the flow.
24867 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
24870 * Setting of this flag indicates that the dest_id field contains function ID.
24871 * If this is not set it indicates dest_id is VNIC or VPORT.
24873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
24877 * This bit must be '1' for the l2_filter_id field to be
24880 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24883 * This bit must be '1' for the ethertype field to be
24886 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
24889 * This bit must be '1' for the tunnel_type field to be
24892 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24895 * This bit must be '1' for the src_macaddr field to be
24898 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
24901 * This bit must be '1' for the ipaddr_type field to be
24904 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
24907 * This bit must be '1' for the src_ipaddr field to be
24910 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
24913 * This bit must be '1' for the src_ipaddr_mask field to be
24916 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
24919 * This bit must be '1' for the dst_ipaddr field to be
24922 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
24925 * This bit must be '1' for the dst_ipaddr_mask field to be
24928 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
24931 * This bit must be '1' for the ip_protocol field to be
24934 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
24937 * This bit must be '1' for the src_port field to be
24940 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
24943 * This bit must be '1' for the src_port_mask field to be
24946 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
24949 * This bit must be '1' for the dst_port field to be
24952 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
24955 * This bit must be '1' for the dst_port_mask field to be
24958 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
24961 * This bit must be '1' for the pri_hint field to be
24964 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
24967 * This bit must be '1' for the ntuple_filter_id field to be
24970 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
24973 * This bit must be '1' for the dst_id field to be
24976 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
24979 * This bit must be '1' for the mirror_vnic_id field to be
24982 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
24985 * This bit must be '1' for the dst_macaddr field to be
24988 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
24991 * This bit must be '1' for the rfs_ring_tbl_idx field to be
24994 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
24997 * This value identifies a set of CFA data structures used for an L2
25000 uint64_t l2_filter_id;
25002 * This value indicates the source MAC address in
25003 * the Ethernet header.
25005 uint8_t src_macaddr[6];
25006 /* This value indicates the ethertype in the Ethernet header. */
25007 uint16_t ethertype;
25009 * This value indicates the type of IP address.
25012 * All others are invalid.
25014 uint8_t ip_addr_type;
25016 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
25019 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
25022 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
25024 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25025 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25027 * The value of protocol filed in IP header.
25028 * Applies to UDP and TCP traffic.
25032 uint8_t ip_protocol;
25034 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
25037 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
25040 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
25042 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
25043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
25045 * If set, this value shall represent the
25046 * Logical VNIC ID of the destination VNIC for the RX
25047 * path and network port id of the destination port for
25052 * Logical VNIC ID of the VNIC where traffic is
25055 uint16_t mirror_vnic_id;
25057 * This value indicates the tunnel type for this filter.
25058 * If this field is not specified, then the filter shall
25059 * apply to both non-tunneled and tunneled packets.
25060 * If this field conflicts with the tunnel_type specified
25061 * in the l2_filter_id, then the HWRM shall return an
25062 * error for this command.
25064 uint8_t tunnel_type;
25066 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25068 /* Virtual eXtensible Local Area Network (VXLAN) */
25069 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25071 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25072 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25074 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25075 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25078 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25080 /* Generic Network Virtualization Encapsulation (Geneve) */
25081 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25083 /* Multi-Protocol Lable Switching (MPLS) */
25084 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25086 /* Stateless Transport Tunnel (STT) */
25087 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25089 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25090 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25092 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25093 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25095 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25096 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25098 /* Use fixed layer 2 ether type of 0xFFFF */
25099 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25101 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25102 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25104 /* Any tunneled traffic */
25105 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25107 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25108 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25110 * This hint is provided to help in placing
25111 * the filter in the filter table.
25114 /* No preference */
25115 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
25117 /* Above the given filter */
25118 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
25120 /* Below the given filter */
25121 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
25123 /* As high as possible */
25124 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
25126 /* As low as possible */
25127 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
25129 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
25130 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
25132 * The value of source IP address to be used in filtering.
25133 * For IPv4, first four bytes represent the IP address.
25135 uint32_t src_ipaddr[4];
25137 * The value of source IP address mask to be used in
25139 * For IPv4, first four bytes represent the IP address mask.
25141 uint32_t src_ipaddr_mask[4];
25143 * The value of destination IP address to be used in filtering.
25144 * For IPv4, first four bytes represent the IP address.
25146 uint32_t dst_ipaddr[4];
25148 * The value of destination IP address mask to be used in
25150 * For IPv4, first four bytes represent the IP address mask.
25152 uint32_t dst_ipaddr_mask[4];
25154 * The value of source port to be used in filtering.
25155 * Applies to UDP and TCP traffic.
25159 * The value of source port mask to be used in filtering.
25160 * Applies to UDP and TCP traffic.
25162 uint16_t src_port_mask;
25164 * The value of destination port to be used in filtering.
25165 * Applies to UDP and TCP traffic.
25169 * The value of destination port mask to be used in
25171 * Applies to UDP and TCP traffic.
25173 uint16_t dst_port_mask;
25175 * This is the ID of the filter that goes along with
25178 uint64_t ntuple_filter_id_hint;
25180 * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
25181 * This index is used in lieu of the RSS hash when selecting the
25182 * index into the RSS table to determine the rx ring.
25184 uint16_t rfs_ring_tbl_idx;
25185 uint8_t unused_0[6];
25186 } __attribute__((packed));
25188 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
25189 struct hwrm_cfa_ntuple_filter_alloc_output {
25190 /* The specific error status for the command. */
25191 uint16_t error_code;
25192 /* The HWRM command request type. */
25194 /* The sequence ID from the original command. */
25196 /* The length of the response data in number of bytes. */
25198 /* This value is an opaque id into CFA data structures. */
25199 uint64_t ntuple_filter_id;
25201 * The flow id value in bit 0-29 is the actual ID of the flow
25202 * associated with this filter and it shall be used to match
25203 * and associate the flow identifier returned in completion
25204 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
25205 * shall indicate no valid flow id.
25208 /* Indicate the flow id value. */
25209 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
25210 UINT32_C(0x3fffffff)
25211 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
25212 /* Indicate type of the flow. */
25213 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
25214 UINT32_C(0x40000000)
25216 * If this bit set to 0, then it indicates that the flow is
25219 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
25220 (UINT32_C(0x0) << 30)
25222 * If this bit is set to 1, then it indicates that the flow is
25225 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
25226 (UINT32_C(0x1) << 30)
25227 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
25228 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
25229 /* Indicate the flow direction. */
25230 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
25231 UINT32_C(0x80000000)
25232 /* If this bit set to 0, then it indicates rx flow. */
25233 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
25234 (UINT32_C(0x0) << 31)
25235 /* If this bit is set to 1, then it indicates that tx flow. */
25236 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
25237 (UINT32_C(0x1) << 31)
25238 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
25239 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
25240 uint8_t unused_0[3];
25242 * This field is used in Output records to indicate that the output
25243 * is completely written to RAM. This field should be read as '1'
25244 * to indicate that the output has been completely written.
25245 * When writing a command completion or response to an internal processor,
25246 * the order of writes has to be such that this field is written last.
25249 } __attribute__((packed));
25251 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
25252 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
25254 * command specific error codes that goes to
25255 * the cmd_err field in Common HWRM Error Response.
25258 /* Unknown error */
25259 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
25261 /* Unable to complete operation due to conflict with Rx Mask VLAN */
25262 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
25264 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
25265 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
25266 uint8_t unused_0[7];
25267 } __attribute__((packed));
25269 /*******************************
25270 * hwrm_cfa_ntuple_filter_free *
25271 *******************************/
25274 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
25275 struct hwrm_cfa_ntuple_filter_free_input {
25276 /* The HWRM command request type. */
25279 * The completion ring to send the completion event on. This should
25280 * be the NQ ID returned from the `nq_alloc` HWRM command.
25282 uint16_t cmpl_ring;
25284 * The sequence ID is used by the driver for tracking multiple
25285 * commands. This ID is treated as opaque data by the firmware and
25286 * the value is returned in the `hwrm_resp_hdr` upon completion.
25290 * The target ID of the command:
25291 * * 0x0-0xFFF8 - The function ID
25292 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25293 * * 0xFFFD - Reserved for user-space HWRM interface
25296 uint16_t target_id;
25298 * A physical address pointer pointing to a host buffer that the
25299 * command's response data will be written. This can be either a host
25300 * physical address (HPA) or a guest physical address (GPA) and must
25301 * point to a physically contiguous block of memory.
25303 uint64_t resp_addr;
25304 /* This value is an opaque id into CFA data structures. */
25305 uint64_t ntuple_filter_id;
25306 } __attribute__((packed));
25308 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
25309 struct hwrm_cfa_ntuple_filter_free_output {
25310 /* The specific error status for the command. */
25311 uint16_t error_code;
25312 /* The HWRM command request type. */
25314 /* The sequence ID from the original command. */
25316 /* The length of the response data in number of bytes. */
25318 uint8_t unused_0[7];
25320 * This field is used in Output records to indicate that the output
25321 * is completely written to RAM. This field should be read as '1'
25322 * to indicate that the output has been completely written.
25323 * When writing a command completion or response to an internal processor,
25324 * the order of writes has to be such that this field is written last.
25327 } __attribute__((packed));
25329 /******************************
25330 * hwrm_cfa_ntuple_filter_cfg *
25331 ******************************/
25334 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
25335 struct hwrm_cfa_ntuple_filter_cfg_input {
25336 /* The HWRM command request type. */
25339 * The completion ring to send the completion event on. This should
25340 * be the NQ ID returned from the `nq_alloc` HWRM command.
25342 uint16_t cmpl_ring;
25344 * The sequence ID is used by the driver for tracking multiple
25345 * commands. This ID is treated as opaque data by the firmware and
25346 * the value is returned in the `hwrm_resp_hdr` upon completion.
25350 * The target ID of the command:
25351 * * 0x0-0xFFF8 - The function ID
25352 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25353 * * 0xFFFD - Reserved for user-space HWRM interface
25356 uint16_t target_id;
25358 * A physical address pointer pointing to a host buffer that the
25359 * command's response data will be written. This can be either a host
25360 * physical address (HPA) or a guest physical address (GPA) and must
25361 * point to a physically contiguous block of memory.
25363 uint64_t resp_addr;
25366 * This bit must be '1' for the new_dst_id field to be
25369 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
25372 * This bit must be '1' for the new_mirror_vnic_id field to be
25375 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
25378 * This bit must be '1' for the new_meter_instance_id field to be
25381 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
25385 * Setting this bit to 1 indicates that dest_id field contains FID.
25386 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
25388 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
25390 /* This value is an opaque id into CFA data structures. */
25391 uint64_t ntuple_filter_id;
25393 * If set, this value shall represent the new
25394 * Logical VNIC ID of the destination VNIC for the RX
25395 * path and new network port id of the destination port for
25398 uint32_t new_dst_id;
25400 * New Logical VNIC ID of the VNIC where traffic is
25403 uint32_t new_mirror_vnic_id;
25405 * New meter to attach to the flow. Specifying the
25406 * invalid instance ID is used to remove any existing
25407 * meter from the flow.
25409 uint16_t new_meter_instance_id;
25411 * A value of 0xfff is considered invalid and implies the
25412 * instance is not configured.
25414 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
25416 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
25417 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
25418 uint8_t unused_1[6];
25419 } __attribute__((packed));
25421 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
25422 struct hwrm_cfa_ntuple_filter_cfg_output {
25423 /* The specific error status for the command. */
25424 uint16_t error_code;
25425 /* The HWRM command request type. */
25427 /* The sequence ID from the original command. */
25429 /* The length of the response data in number of bytes. */
25431 uint8_t unused_0[7];
25433 * This field is used in Output records to indicate that the output
25434 * is completely written to RAM. This field should be read as '1'
25435 * to indicate that the output has been completely written.
25436 * When writing a command completion or response to an internal processor,
25437 * the order of writes has to be such that this field is written last.
25440 } __attribute__((packed));
25442 /**************************
25443 * hwrm_cfa_em_flow_alloc *
25444 **************************/
25447 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
25448 struct hwrm_cfa_em_flow_alloc_input {
25449 /* The HWRM command request type. */
25452 * The completion ring to send the completion event on. This should
25453 * be the NQ ID returned from the `nq_alloc` HWRM command.
25455 uint16_t cmpl_ring;
25457 * The sequence ID is used by the driver for tracking multiple
25458 * commands. This ID is treated as opaque data by the firmware and
25459 * the value is returned in the `hwrm_resp_hdr` upon completion.
25463 * The target ID of the command:
25464 * * 0x0-0xFFF8 - The function ID
25465 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25466 * * 0xFFFD - Reserved for user-space HWRM interface
25469 uint16_t target_id;
25471 * A physical address pointer pointing to a host buffer that the
25472 * command's response data will be written. This can be either a host
25473 * physical address (HPA) or a guest physical address (GPA) and must
25474 * point to a physically contiguous block of memory.
25476 uint64_t resp_addr;
25479 * Enumeration denoting the RX, TX type of the resource.
25480 * This enumeration is used for resources that are similar for both
25481 * TX and RX paths of the chip.
25483 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
25485 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25488 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
25489 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
25491 * Setting of this flag indicates enabling of a byte counter for a given
25494 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
25496 * Setting of this flag indicates enabling of a packet counter for a given
25499 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
25500 /* Setting of this flag indicates de-capsulation action for the given flow. */
25501 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
25502 /* Setting of this flag indicates encapsulation action for the given flow. */
25503 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
25505 * Setting of this flag indicates drop action. If this flag is not set,
25506 * then it should be considered accept action.
25508 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
25510 * Setting of this flag indicates that a meter is expected to be attached
25511 * to this flow. This hint can be used when choosing the action record
25512 * format required for the flow.
25514 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
25517 * This bit must be '1' for the l2_filter_id field to be
25520 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
25523 * This bit must be '1' for the tunnel_type field to be
25526 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
25529 * This bit must be '1' for the tunnel_id field to be
25532 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
25535 * This bit must be '1' for the src_macaddr field to be
25538 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
25541 * This bit must be '1' for the dst_macaddr field to be
25544 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
25547 * This bit must be '1' for the ovlan_vid field to be
25550 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
25553 * This bit must be '1' for the ivlan_vid field to be
25556 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
25559 * This bit must be '1' for the ethertype field to be
25562 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
25565 * This bit must be '1' for the src_ipaddr field to be
25568 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
25571 * This bit must be '1' for the dst_ipaddr field to be
25574 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
25577 * This bit must be '1' for the ipaddr_type field to be
25580 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25583 * This bit must be '1' for the ip_protocol field to be
25586 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25589 * This bit must be '1' for the src_port field to be
25592 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
25595 * This bit must be '1' for the dst_port field to be
25598 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
25601 * This bit must be '1' for the dst_id field to be
25604 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
25607 * This bit must be '1' for the mirror_vnic_id field to be
25610 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25613 * This bit must be '1' for the encap_record_id field to be
25616 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
25619 * This bit must be '1' for the meter_instance_id field to be
25622 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
25625 * This value identifies a set of CFA data structures used for an L2
25628 uint64_t l2_filter_id;
25630 uint8_t tunnel_type;
25632 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25634 /* Virtual eXtensible Local Area Network (VXLAN) */
25635 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25637 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25638 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25640 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25641 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25644 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25646 /* Generic Network Virtualization Encapsulation (Geneve) */
25647 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25649 /* Multi-Protocol Lable Switching (MPLS) */
25650 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25652 /* Stateless Transport Tunnel (STT) */
25653 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
25655 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25656 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25658 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25659 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25661 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25662 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25664 /* Use fixed layer 2 ether type of 0xFFFF */
25665 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25667 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25668 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25670 /* Any tunneled traffic */
25671 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25673 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25674 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25675 uint8_t unused_0[3];
25677 * Tunnel identifier.
25678 * Virtual Network Identifier (VNI). Only valid with
25679 * tunnel_types VXLAN, NVGRE, and Geneve.
25680 * Only lower 24-bits of VNI field are used
25681 * in setting up the filter.
25683 uint32_t tunnel_id;
25685 * This value indicates the source MAC address in
25686 * the Ethernet header.
25688 uint8_t src_macaddr[6];
25689 /* The meter instance to attach to the flow. */
25690 uint16_t meter_instance_id;
25692 * A value of 0xfff is considered invalid and implies the
25693 * instance is not configured.
25695 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
25697 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
25698 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
25700 * This value indicates the destination MAC address in
25701 * the Ethernet header.
25703 uint8_t dst_macaddr[6];
25705 * This value indicates the VLAN ID of the outer VLAN tag
25706 * in the Ethernet header.
25708 uint16_t ovlan_vid;
25710 * This value indicates the VLAN ID of the inner VLAN tag
25711 * in the Ethernet header.
25713 uint16_t ivlan_vid;
25714 /* This value indicates the ethertype in the Ethernet header. */
25715 uint16_t ethertype;
25717 * This value indicates the type of IP address.
25720 * All others are invalid.
25722 uint8_t ip_addr_type;
25724 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
25726 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
25728 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
25729 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25730 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25732 * The value of protocol filed in IP header.
25733 * Applies to UDP and TCP traffic.
25737 uint8_t ip_protocol;
25739 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
25741 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
25743 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
25744 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
25745 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
25746 uint8_t unused_1[2];
25748 * The value of source IP address to be used in filtering.
25749 * For IPv4, first four bytes represent the IP address.
25751 uint32_t src_ipaddr[4];
25753 * big_endian = True
25754 * The value of destination IP address to be used in filtering.
25755 * For IPv4, first four bytes represent the IP address.
25757 uint32_t dst_ipaddr[4];
25759 * The value of source port to be used in filtering.
25760 * Applies to UDP and TCP traffic.
25764 * The value of destination port to be used in filtering.
25765 * Applies to UDP and TCP traffic.
25769 * If set, this value shall represent the
25770 * Logical VNIC ID of the destination VNIC for the RX
25771 * path and network port id of the destination port for
25776 * Logical VNIC ID of the VNIC where traffic is
25779 uint16_t mirror_vnic_id;
25780 /* Logical ID of the encapsulation record. */
25781 uint32_t encap_record_id;
25782 uint8_t unused_2[4];
25783 } __attribute__((packed));
25785 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
25786 struct hwrm_cfa_em_flow_alloc_output {
25787 /* The specific error status for the command. */
25788 uint16_t error_code;
25789 /* The HWRM command request type. */
25791 /* The sequence ID from the original command. */
25793 /* The length of the response data in number of bytes. */
25795 /* This value is an opaque id into CFA data structures. */
25796 uint64_t em_filter_id;
25798 * The flow id value in bit 0-29 is the actual ID of the flow
25799 * associated with this filter and it shall be used to match
25800 * and associate the flow identifier returned in completion
25801 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
25802 * shall indicate no valid flow id.
25805 /* Indicate the flow id value. */
25806 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
25807 UINT32_C(0x3fffffff)
25808 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
25809 /* Indicate type of the flow. */
25810 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
25811 UINT32_C(0x40000000)
25813 * If this bit set to 0, then it indicates that the flow is
25816 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
25817 (UINT32_C(0x0) << 30)
25819 * If this bit is set to 1, then it indicates that the flow is
25822 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
25823 (UINT32_C(0x1) << 30)
25824 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
25825 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
25826 /* Indicate the flow direction. */
25827 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
25828 UINT32_C(0x80000000)
25829 /* If this bit set to 0, then it indicates rx flow. */
25830 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
25831 (UINT32_C(0x0) << 31)
25832 /* If this bit is set to 1, then it indicates that tx flow. */
25833 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
25834 (UINT32_C(0x1) << 31)
25835 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
25836 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
25837 uint8_t unused_0[3];
25839 * This field is used in Output records to indicate that the output
25840 * is completely written to RAM. This field should be read as '1'
25841 * to indicate that the output has been completely written.
25842 * When writing a command completion or response to an internal processor,
25843 * the order of writes has to be such that this field is written last.
25846 } __attribute__((packed));
25848 /*************************
25849 * hwrm_cfa_em_flow_free *
25850 *************************/
25853 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
25854 struct hwrm_cfa_em_flow_free_input {
25855 /* The HWRM command request type. */
25858 * The completion ring to send the completion event on. This should
25859 * be the NQ ID returned from the `nq_alloc` HWRM command.
25861 uint16_t cmpl_ring;
25863 * The sequence ID is used by the driver for tracking multiple
25864 * commands. This ID is treated as opaque data by the firmware and
25865 * the value is returned in the `hwrm_resp_hdr` upon completion.
25869 * The target ID of the command:
25870 * * 0x0-0xFFF8 - The function ID
25871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25872 * * 0xFFFD - Reserved for user-space HWRM interface
25875 uint16_t target_id;
25877 * A physical address pointer pointing to a host buffer that the
25878 * command's response data will be written. This can be either a host
25879 * physical address (HPA) or a guest physical address (GPA) and must
25880 * point to a physically contiguous block of memory.
25882 uint64_t resp_addr;
25883 /* This value is an opaque id into CFA data structures. */
25884 uint64_t em_filter_id;
25885 } __attribute__((packed));
25887 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
25888 struct hwrm_cfa_em_flow_free_output {
25889 /* The specific error status for the command. */
25890 uint16_t error_code;
25891 /* The HWRM command request type. */
25893 /* The sequence ID from the original command. */
25895 /* The length of the response data in number of bytes. */
25897 uint8_t unused_0[7];
25899 * This field is used in Output records to indicate that the output
25900 * is completely written to RAM. This field should be read as '1'
25901 * to indicate that the output has been completely written.
25902 * When writing a command completion or response to an internal processor,
25903 * the order of writes has to be such that this field is written last.
25906 } __attribute__((packed));
25908 /************************
25909 * hwrm_cfa_meter_qcaps *
25910 ************************/
25913 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
25914 struct hwrm_cfa_meter_qcaps_input {
25915 /* The HWRM command request type. */
25918 * The completion ring to send the completion event on. This should
25919 * be the NQ ID returned from the `nq_alloc` HWRM command.
25921 uint16_t cmpl_ring;
25923 * The sequence ID is used by the driver for tracking multiple
25924 * commands. This ID is treated as opaque data by the firmware and
25925 * the value is returned in the `hwrm_resp_hdr` upon completion.
25929 * The target ID of the command:
25930 * * 0x0-0xFFF8 - The function ID
25931 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25932 * * 0xFFFD - Reserved for user-space HWRM interface
25935 uint16_t target_id;
25937 * A physical address pointer pointing to a host buffer that the
25938 * command's response data will be written. This can be either a host
25939 * physical address (HPA) or a guest physical address (GPA) and must
25940 * point to a physically contiguous block of memory.
25942 uint64_t resp_addr;
25943 } __attribute__((packed));
25945 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
25946 struct hwrm_cfa_meter_qcaps_output {
25947 /* The specific error status for the command. */
25948 uint16_t error_code;
25949 /* The HWRM command request type. */
25951 /* The sequence ID from the original command. */
25953 /* The length of the response data in number of bytes. */
25957 * Enumeration denoting the clock at which the Meter is running with.
25958 * This enumeration is used for resources that are similar for both
25959 * TX and RX paths of the chip.
25961 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
25962 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
25964 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
25966 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
25967 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
25968 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
25969 uint8_t unused_0[4];
25971 * The minimum guaranteed number of tx meter profiles supported
25972 * for this function.
25974 uint16_t min_tx_profile;
25976 * The maximum non-guaranteed number of tx meter profiles supported
25977 * for this function.
25979 uint16_t max_tx_profile;
25981 * The minimum guaranteed number of rx meter profiles supported
25982 * for this function.
25984 uint16_t min_rx_profile;
25986 * The maximum non-guaranteed number of rx meter profiles supported
25987 * for this function.
25989 uint16_t max_rx_profile;
25991 * The minimum guaranteed number of tx meter instances supported
25992 * for this function.
25994 uint16_t min_tx_instance;
25996 * The maximum non-guaranteed number of tx meter instances supported
25997 * for this function.
25999 uint16_t max_tx_instance;
26001 * The minimum guaranteed number of rx meter instances supported
26002 * for this function.
26004 uint16_t min_rx_instance;
26006 * The maximum non-guaranteed number of rx meter instances supported
26007 * for this function.
26009 uint16_t max_rx_instance;
26010 uint8_t unused_1[7];
26012 * This field is used in Output records to indicate that the output
26013 * is completely written to RAM. This field should be read as '1'
26014 * to indicate that the output has been completely written.
26015 * When writing a command completion or response to an internal processor,
26016 * the order of writes has to be such that this field is written last.
26019 } __attribute__((packed));
26021 /********************************
26022 * hwrm_cfa_meter_profile_alloc *
26023 ********************************/
26026 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
26027 struct hwrm_cfa_meter_profile_alloc_input {
26028 /* The HWRM command request type. */
26031 * The completion ring to send the completion event on. This should
26032 * be the NQ ID returned from the `nq_alloc` HWRM command.
26034 uint16_t cmpl_ring;
26036 * The sequence ID is used by the driver for tracking multiple
26037 * commands. This ID is treated as opaque data by the firmware and
26038 * the value is returned in the `hwrm_resp_hdr` upon completion.
26042 * The target ID of the command:
26043 * * 0x0-0xFFF8 - The function ID
26044 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26045 * * 0xFFFD - Reserved for user-space HWRM interface
26048 uint16_t target_id;
26050 * A physical address pointer pointing to a host buffer that the
26051 * command's response data will be written. This can be either a host
26052 * physical address (HPA) or a guest physical address (GPA) and must
26053 * point to a physically contiguous block of memory.
26055 uint64_t resp_addr;
26058 * Enumeration denoting the RX, TX type of the resource.
26059 * This enumeration is used for resources that are similar for both
26060 * TX and RX paths of the chip.
26062 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
26064 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
26067 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
26069 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
26070 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
26071 /* The meter algorithm type. */
26072 uint8_t meter_type;
26073 /* RFC 2697 (srTCM) */
26074 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
26076 /* RFC 2698 (trTCM) */
26077 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
26079 /* RFC 4115 (trTCM) */
26080 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
26082 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
26083 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
26085 * This field is reserved for the future use.
26086 * It shall be set to 0.
26088 uint16_t reserved1;
26090 * This field is reserved for the future use.
26091 * It shall be set to 0.
26093 uint32_t reserved2;
26094 /* A meter rate specified in bytes-per-second. */
26095 uint32_t commit_rate;
26096 /* The bandwidth value. */
26097 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
26098 UINT32_C(0xfffffff)
26099 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
26101 /* The granularity of the value (bits or bytes). */
26102 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
26103 UINT32_C(0x10000000)
26104 /* Value is in bits. */
26105 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
26106 (UINT32_C(0x0) << 28)
26107 /* Value is in bytes. */
26108 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
26109 (UINT32_C(0x1) << 28)
26110 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
26111 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
26112 /* bw_value_unit is 3 b */
26113 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
26114 UINT32_C(0xe0000000)
26115 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
26117 /* Value is in Mb or MB (base 10). */
26118 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
26119 (UINT32_C(0x0) << 29)
26120 /* Value is in Kb or KB (base 10). */
26121 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
26122 (UINT32_C(0x2) << 29)
26123 /* Value is in bits or bytes. */
26124 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
26125 (UINT32_C(0x4) << 29)
26126 /* Value is in Gb or GB (base 10). */
26127 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
26128 (UINT32_C(0x6) << 29)
26129 /* Value is in 1/100th of a percentage of total bandwidth. */
26130 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26131 (UINT32_C(0x1) << 29)
26133 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
26134 (UINT32_C(0x7) << 29)
26135 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
26136 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
26137 /* A meter burst size specified in bytes. */
26138 uint32_t commit_burst;
26139 /* The bandwidth value. */
26140 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
26141 UINT32_C(0xfffffff)
26142 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
26144 /* The granularity of the value (bits or bytes). */
26145 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
26146 UINT32_C(0x10000000)
26147 /* Value is in bits. */
26148 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
26149 (UINT32_C(0x0) << 28)
26150 /* Value is in bytes. */
26151 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
26152 (UINT32_C(0x1) << 28)
26153 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
26154 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
26155 /* bw_value_unit is 3 b */
26156 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
26157 UINT32_C(0xe0000000)
26158 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
26160 /* Value is in Mb or MB (base 10). */
26161 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
26162 (UINT32_C(0x0) << 29)
26163 /* Value is in Kb or KB (base 10). */
26164 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
26165 (UINT32_C(0x2) << 29)
26166 /* Value is in bits or bytes. */
26167 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
26168 (UINT32_C(0x4) << 29)
26169 /* Value is in Gb or GB (base 10). */
26170 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
26171 (UINT32_C(0x6) << 29)
26172 /* Value is in 1/100th of a percentage of total bandwidth. */
26173 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26174 (UINT32_C(0x1) << 29)
26175 /* Invalid value */
26176 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
26177 (UINT32_C(0x7) << 29)
26178 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
26179 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
26180 /* A meter rate specified in bytes-per-second. */
26181 uint32_t excess_peak_rate;
26182 /* The bandwidth value. */
26183 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
26184 UINT32_C(0xfffffff)
26185 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
26187 /* The granularity of the value (bits or bytes). */
26188 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
26189 UINT32_C(0x10000000)
26190 /* Value is in bits. */
26191 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
26192 (UINT32_C(0x0) << 28)
26193 /* Value is in bytes. */
26194 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
26195 (UINT32_C(0x1) << 28)
26196 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
26197 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
26198 /* bw_value_unit is 3 b */
26199 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
26200 UINT32_C(0xe0000000)
26201 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
26203 /* Value is in Mb or MB (base 10). */
26204 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
26205 (UINT32_C(0x0) << 29)
26206 /* Value is in Kb or KB (base 10). */
26207 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
26208 (UINT32_C(0x2) << 29)
26209 /* Value is in bits or bytes. */
26210 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
26211 (UINT32_C(0x4) << 29)
26212 /* Value is in Gb or GB (base 10). */
26213 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
26214 (UINT32_C(0x6) << 29)
26215 /* Value is in 1/100th of a percentage of total bandwidth. */
26216 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26217 (UINT32_C(0x1) << 29)
26219 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
26220 (UINT32_C(0x7) << 29)
26221 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
26222 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
26223 /* A meter burst size specified in bytes. */
26224 uint32_t excess_peak_burst;
26225 /* The bandwidth value. */
26226 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
26227 UINT32_C(0xfffffff)
26228 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
26230 /* The granularity of the value (bits or bytes). */
26231 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
26232 UINT32_C(0x10000000)
26233 /* Value is in bits. */
26234 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
26235 (UINT32_C(0x0) << 28)
26236 /* Value is in bytes. */
26237 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
26238 (UINT32_C(0x1) << 28)
26239 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
26240 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
26241 /* bw_value_unit is 3 b */
26242 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
26243 UINT32_C(0xe0000000)
26244 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
26246 /* Value is in Mb or MB (base 10). */
26247 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
26248 (UINT32_C(0x0) << 29)
26249 /* Value is in Kb or KB (base 10). */
26250 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
26251 (UINT32_C(0x2) << 29)
26252 /* Value is in bits or bytes. */
26253 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
26254 (UINT32_C(0x4) << 29)
26255 /* Value is in Gb or GB (base 10). */
26256 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
26257 (UINT32_C(0x6) << 29)
26258 /* Value is in 1/100th of a percentage of total bandwidth. */
26259 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26260 (UINT32_C(0x1) << 29)
26262 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
26263 (UINT32_C(0x7) << 29)
26264 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
26265 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
26266 } __attribute__((packed));
26268 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
26269 struct hwrm_cfa_meter_profile_alloc_output {
26270 /* The specific error status for the command. */
26271 uint16_t error_code;
26272 /* The HWRM command request type. */
26274 /* The sequence ID from the original command. */
26276 /* The length of the response data in number of bytes. */
26278 /* This value identifies a meter profile in CFA. */
26279 uint16_t meter_profile_id;
26281 * A value of 0xfff is considered invalid and implies the
26282 * profile is not configured.
26284 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
26286 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
26287 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
26288 uint8_t unused_0[5];
26290 * This field is used in Output records to indicate that the output
26291 * is completely written to RAM. This field should be read as '1'
26292 * to indicate that the output has been completely written.
26293 * When writing a command completion or response to an internal processor,
26294 * the order of writes has to be such that this field is written last.
26297 } __attribute__((packed));
26299 /*******************************
26300 * hwrm_cfa_meter_profile_free *
26301 *******************************/
26304 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
26305 struct hwrm_cfa_meter_profile_free_input {
26306 /* The HWRM command request type. */
26309 * The completion ring to send the completion event on. This should
26310 * be the NQ ID returned from the `nq_alloc` HWRM command.
26312 uint16_t cmpl_ring;
26314 * The sequence ID is used by the driver for tracking multiple
26315 * commands. This ID is treated as opaque data by the firmware and
26316 * the value is returned in the `hwrm_resp_hdr` upon completion.
26320 * The target ID of the command:
26321 * * 0x0-0xFFF8 - The function ID
26322 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26323 * * 0xFFFD - Reserved for user-space HWRM interface
26326 uint16_t target_id;
26328 * A physical address pointer pointing to a host buffer that the
26329 * command's response data will be written. This can be either a host
26330 * physical address (HPA) or a guest physical address (GPA) and must
26331 * point to a physically contiguous block of memory.
26333 uint64_t resp_addr;
26336 * Enumeration denoting the RX, TX type of the resource.
26337 * This enumeration is used for resources that are similar for both
26338 * TX and RX paths of the chip.
26340 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
26342 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
26345 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
26347 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
26348 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
26350 /* This value identifies a meter profile in CFA. */
26351 uint16_t meter_profile_id;
26353 * A value of 0xfff is considered invalid and implies the
26354 * profile is not configured.
26356 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
26358 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
26359 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
26360 uint8_t unused_1[4];
26361 } __attribute__((packed));
26363 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
26364 struct hwrm_cfa_meter_profile_free_output {
26365 /* The specific error status for the command. */
26366 uint16_t error_code;
26367 /* The HWRM command request type. */
26369 /* The sequence ID from the original command. */
26371 /* The length of the response data in number of bytes. */
26373 uint8_t unused_0[7];
26375 * This field is used in Output records to indicate that the output
26376 * is completely written to RAM. This field should be read as '1'
26377 * to indicate that the output has been completely written.
26378 * When writing a command completion or response to an internal processor,
26379 * the order of writes has to be such that this field is written last.
26382 } __attribute__((packed));
26384 /******************************
26385 * hwrm_cfa_meter_profile_cfg *
26386 ******************************/
26389 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
26390 struct hwrm_cfa_meter_profile_cfg_input {
26391 /* The HWRM command request type. */
26394 * The completion ring to send the completion event on. This should
26395 * be the NQ ID returned from the `nq_alloc` HWRM command.
26397 uint16_t cmpl_ring;
26399 * The sequence ID is used by the driver for tracking multiple
26400 * commands. This ID is treated as opaque data by the firmware and
26401 * the value is returned in the `hwrm_resp_hdr` upon completion.
26405 * The target ID of the command:
26406 * * 0x0-0xFFF8 - The function ID
26407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26408 * * 0xFFFD - Reserved for user-space HWRM interface
26411 uint16_t target_id;
26413 * A physical address pointer pointing to a host buffer that the
26414 * command's response data will be written. This can be either a host
26415 * physical address (HPA) or a guest physical address (GPA) and must
26416 * point to a physically contiguous block of memory.
26418 uint64_t resp_addr;
26421 * Enumeration denoting the RX, TX type of the resource.
26422 * This enumeration is used for resources that are similar for both
26423 * TX and RX paths of the chip.
26425 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26427 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26429 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26430 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
26431 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
26432 /* The meter algorithm type. */
26433 uint8_t meter_type;
26434 /* RFC 2697 (srTCM) */
26435 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
26437 /* RFC 2698 (trTCM) */
26438 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
26440 /* RFC 4115 (trTCM) */
26441 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
26443 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
26444 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
26445 /* This value identifies a meter profile in CFA. */
26446 uint16_t meter_profile_id;
26448 * A value of 0xfff is considered invalid and implies the
26449 * profile is not configured.
26451 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
26453 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
26454 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
26456 * This field is reserved for the future use.
26457 * It shall be set to 0.
26460 /* A meter rate specified in bytes-per-second. */
26461 uint32_t commit_rate;
26462 /* The bandwidth value. */
26463 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
26464 UINT32_C(0xfffffff)
26465 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
26467 /* The granularity of the value (bits or bytes). */
26468 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
26469 UINT32_C(0x10000000)
26470 /* Value is in bits. */
26471 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
26472 (UINT32_C(0x0) << 28)
26473 /* Value is in bytes. */
26474 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
26475 (UINT32_C(0x1) << 28)
26476 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
26477 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
26478 /* bw_value_unit is 3 b */
26479 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
26480 UINT32_C(0xe0000000)
26481 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
26483 /* Value is in Mb or MB (base 10). */
26484 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
26485 (UINT32_C(0x0) << 29)
26486 /* Value is in Kb or KB (base 10). */
26487 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
26488 (UINT32_C(0x2) << 29)
26489 /* Value is in bits or bytes. */
26490 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
26491 (UINT32_C(0x4) << 29)
26492 /* Value is in Gb or GB (base 10). */
26493 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
26494 (UINT32_C(0x6) << 29)
26495 /* Value is in 1/100th of a percentage of total bandwidth. */
26496 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26497 (UINT32_C(0x1) << 29)
26499 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
26500 (UINT32_C(0x7) << 29)
26501 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
26502 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
26503 /* A meter burst size specified in bytes. */
26504 uint32_t commit_burst;
26505 /* The bandwidth value. */
26506 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
26507 UINT32_C(0xfffffff)
26508 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
26510 /* The granularity of the value (bits or bytes). */
26511 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
26512 UINT32_C(0x10000000)
26513 /* Value is in bits. */
26514 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
26515 (UINT32_C(0x0) << 28)
26516 /* Value is in bytes. */
26517 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
26518 (UINT32_C(0x1) << 28)
26519 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
26520 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
26521 /* bw_value_unit is 3 b */
26522 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
26523 UINT32_C(0xe0000000)
26524 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
26526 /* Value is in Mb or MB (base 10). */
26527 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
26528 (UINT32_C(0x0) << 29)
26529 /* Value is in Kb or KB (base 10). */
26530 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
26531 (UINT32_C(0x2) << 29)
26532 /* Value is in bits or bytes. */
26533 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
26534 (UINT32_C(0x4) << 29)
26535 /* Value is in Gb or GB (base 10). */
26536 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
26537 (UINT32_C(0x6) << 29)
26538 /* Value is in 1/100th of a percentage of total bandwidth. */
26539 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26540 (UINT32_C(0x1) << 29)
26541 /* Invalid value */
26542 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
26543 (UINT32_C(0x7) << 29)
26544 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
26545 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
26546 /* A meter rate specified in bytes-per-second. */
26547 uint32_t excess_peak_rate;
26548 /* The bandwidth value. */
26549 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
26550 UINT32_C(0xfffffff)
26551 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
26553 /* The granularity of the value (bits or bytes). */
26554 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
26555 UINT32_C(0x10000000)
26556 /* Value is in bits. */
26557 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
26558 (UINT32_C(0x0) << 28)
26559 /* Value is in bytes. */
26560 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
26561 (UINT32_C(0x1) << 28)
26562 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
26563 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
26564 /* bw_value_unit is 3 b */
26565 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
26566 UINT32_C(0xe0000000)
26567 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
26569 /* Value is in Mb or MB (base 10). */
26570 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
26571 (UINT32_C(0x0) << 29)
26572 /* Value is in Kb or KB (base 10). */
26573 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
26574 (UINT32_C(0x2) << 29)
26575 /* Value is in bits or bytes. */
26576 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
26577 (UINT32_C(0x4) << 29)
26578 /* Value is in Gb or GB (base 10). */
26579 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
26580 (UINT32_C(0x6) << 29)
26581 /* Value is in 1/100th of a percentage of total bandwidth. */
26582 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
26583 (UINT32_C(0x1) << 29)
26585 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
26586 (UINT32_C(0x7) << 29)
26587 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
26588 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
26589 /* A meter burst size specified in bytes. */
26590 uint32_t excess_peak_burst;
26591 /* The bandwidth value. */
26592 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
26593 UINT32_C(0xfffffff)
26594 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
26596 /* The granularity of the value (bits or bytes). */
26597 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
26598 UINT32_C(0x10000000)
26599 /* Value is in bits. */
26600 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
26601 (UINT32_C(0x0) << 28)
26602 /* Value is in bytes. */
26603 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
26604 (UINT32_C(0x1) << 28)
26605 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
26606 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
26607 /* bw_value_unit is 3 b */
26608 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
26609 UINT32_C(0xe0000000)
26610 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
26612 /* Value is in Mb or MB (base 10). */
26613 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
26614 (UINT32_C(0x0) << 29)
26615 /* Value is in Kb or KB (base 10). */
26616 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
26617 (UINT32_C(0x2) << 29)
26618 /* Value is in bits or bytes. */
26619 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
26620 (UINT32_C(0x4) << 29)
26621 /* Value is in Gb or GB (base 10). */
26622 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
26623 (UINT32_C(0x6) << 29)
26624 /* Value is in 1/100th of a percentage of total bandwidth. */
26625 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26626 (UINT32_C(0x1) << 29)
26628 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
26629 (UINT32_C(0x7) << 29)
26630 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
26631 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
26632 } __attribute__((packed));
26634 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
26635 struct hwrm_cfa_meter_profile_cfg_output {
26636 /* The specific error status for the command. */
26637 uint16_t error_code;
26638 /* The HWRM command request type. */
26640 /* The sequence ID from the original command. */
26642 /* The length of the response data in number of bytes. */
26644 uint8_t unused_0[7];
26646 * This field is used in Output records to indicate that the output
26647 * is completely written to RAM. This field should be read as '1'
26648 * to indicate that the output has been completely written.
26649 * When writing a command completion or response to an internal processor,
26650 * the order of writes has to be such that this field is written last.
26653 } __attribute__((packed));
26655 /*********************************
26656 * hwrm_cfa_meter_instance_alloc *
26657 *********************************/
26660 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
26661 struct hwrm_cfa_meter_instance_alloc_input {
26662 /* The HWRM command request type. */
26665 * The completion ring to send the completion event on. This should
26666 * be the NQ ID returned from the `nq_alloc` HWRM command.
26668 uint16_t cmpl_ring;
26670 * The sequence ID is used by the driver for tracking multiple
26671 * commands. This ID is treated as opaque data by the firmware and
26672 * the value is returned in the `hwrm_resp_hdr` upon completion.
26676 * The target ID of the command:
26677 * * 0x0-0xFFF8 - The function ID
26678 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26679 * * 0xFFFD - Reserved for user-space HWRM interface
26682 uint16_t target_id;
26684 * A physical address pointer pointing to a host buffer that the
26685 * command's response data will be written. This can be either a host
26686 * physical address (HPA) or a guest physical address (GPA) and must
26687 * point to a physically contiguous block of memory.
26689 uint64_t resp_addr;
26692 * Enumeration denoting the RX, TX type of the resource.
26693 * This enumeration is used for resources that are similar for both
26694 * TX and RX paths of the chip.
26696 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
26699 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
26702 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
26704 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
26705 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
26707 /* This value identifies a meter profile in CFA. */
26708 uint16_t meter_profile_id;
26710 * A value of 0xffff is considered invalid and implies the
26711 * profile is not configured.
26713 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
26715 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
26716 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
26717 uint8_t unused_1[4];
26718 } __attribute__((packed));
26720 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
26721 struct hwrm_cfa_meter_instance_alloc_output {
26722 /* The specific error status for the command. */
26723 uint16_t error_code;
26724 /* The HWRM command request type. */
26726 /* The sequence ID from the original command. */
26728 /* The length of the response data in number of bytes. */
26730 /* This value identifies a meter instance in CFA. */
26731 uint16_t meter_instance_id;
26733 * A value of 0xffff is considered invalid and implies the
26734 * instance is not configured.
26736 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
26738 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
26739 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
26740 uint8_t unused_0[5];
26742 * This field is used in Output records to indicate that the output
26743 * is completely written to RAM. This field should be read as '1'
26744 * to indicate that the output has been completely written.
26745 * When writing a command completion or response to an internal processor,
26746 * the order of writes has to be such that this field is written last.
26749 } __attribute__((packed));
26751 /*******************************
26752 * hwrm_cfa_meter_instance_cfg *
26753 *******************************/
26756 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
26757 struct hwrm_cfa_meter_instance_cfg_input {
26758 /* The HWRM command request type. */
26761 * The completion ring to send the completion event on. This should
26762 * be the NQ ID returned from the `nq_alloc` HWRM command.
26764 uint16_t cmpl_ring;
26766 * The sequence ID is used by the driver for tracking multiple
26767 * commands. This ID is treated as opaque data by the firmware and
26768 * the value is returned in the `hwrm_resp_hdr` upon completion.
26772 * The target ID of the command:
26773 * * 0x0-0xFFF8 - The function ID
26774 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26775 * * 0xFFFD - Reserved for user-space HWRM interface
26778 uint16_t target_id;
26780 * A physical address pointer pointing to a host buffer that the
26781 * command's response data will be written. This can be either a host
26782 * physical address (HPA) or a guest physical address (GPA) and must
26783 * point to a physically contiguous block of memory.
26785 uint64_t resp_addr;
26788 * Enumeration denoting the RX, TX type of the resource.
26789 * This enumeration is used for resources that are similar for both
26790 * TX and RX paths of the chip.
26792 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26794 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
26797 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
26799 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
26800 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
26803 * This value identifies a new meter profile to be associated with
26804 * the meter instance specified in this command.
26806 uint16_t meter_profile_id;
26808 * A value of 0xffff is considered invalid and implies the
26809 * profile is not configured.
26811 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
26813 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
26814 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
26816 * This value identifies the ID of a meter instance that needs to be updated with
26817 * a new meter profile specified in this command.
26819 uint16_t meter_instance_id;
26820 uint8_t unused_1[2];
26821 } __attribute__((packed));
26823 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
26824 struct hwrm_cfa_meter_instance_cfg_output {
26825 /* The specific error status for the command. */
26826 uint16_t error_code;
26827 /* The HWRM command request type. */
26829 /* The sequence ID from the original command. */
26831 /* The length of the response data in number of bytes. */
26833 uint8_t unused_0[7];
26835 * This field is used in Output records to indicate that the output
26836 * is completely written to RAM. This field should be read as '1'
26837 * to indicate that the output has been completely written.
26838 * When writing a command completion or response to an internal processor,
26839 * the order of writes has to be such that this field is written last.
26842 } __attribute__((packed));
26844 /********************************
26845 * hwrm_cfa_meter_instance_free *
26846 ********************************/
26849 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
26850 struct hwrm_cfa_meter_instance_free_input {
26851 /* The HWRM command request type. */
26854 * The completion ring to send the completion event on. This should
26855 * be the NQ ID returned from the `nq_alloc` HWRM command.
26857 uint16_t cmpl_ring;
26859 * The sequence ID is used by the driver for tracking multiple
26860 * commands. This ID is treated as opaque data by the firmware and
26861 * the value is returned in the `hwrm_resp_hdr` upon completion.
26865 * The target ID of the command:
26866 * * 0x0-0xFFF8 - The function ID
26867 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26868 * * 0xFFFD - Reserved for user-space HWRM interface
26871 uint16_t target_id;
26873 * A physical address pointer pointing to a host buffer that the
26874 * command's response data will be written. This can be either a host
26875 * physical address (HPA) or a guest physical address (GPA) and must
26876 * point to a physically contiguous block of memory.
26878 uint64_t resp_addr;
26881 * Enumeration denoting the RX, TX type of the resource.
26882 * This enumeration is used for resources that are similar for both
26883 * TX and RX paths of the chip.
26885 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
26887 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
26890 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
26892 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
26893 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
26895 /* This value identifies a meter instance in CFA. */
26896 uint16_t meter_instance_id;
26898 * A value of 0xfff is considered invalid and implies the
26899 * instance is not configured.
26901 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
26903 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
26904 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
26905 uint8_t unused_1[4];
26906 } __attribute__((packed));
26908 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
26909 struct hwrm_cfa_meter_instance_free_output {
26910 /* The specific error status for the command. */
26911 uint16_t error_code;
26912 /* The HWRM command request type. */
26914 /* The sequence ID from the original command. */
26916 /* The length of the response data in number of bytes. */
26918 uint8_t unused_0[7];
26920 * This field is used in Output records to indicate that the output
26921 * is completely written to RAM. This field should be read as '1'
26922 * to indicate that the output has been completely written.
26923 * When writing a command completion or response to an internal processor,
26924 * the order of writes has to be such that this field is written last.
26927 } __attribute__((packed));
26929 /*******************************
26930 * hwrm_cfa_decap_filter_alloc *
26931 *******************************/
26934 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
26935 struct hwrm_cfa_decap_filter_alloc_input {
26936 /* The HWRM command request type. */
26939 * The completion ring to send the completion event on. This should
26940 * be the NQ ID returned from the `nq_alloc` HWRM command.
26942 uint16_t cmpl_ring;
26944 * The sequence ID is used by the driver for tracking multiple
26945 * commands. This ID is treated as opaque data by the firmware and
26946 * the value is returned in the `hwrm_resp_hdr` upon completion.
26950 * The target ID of the command:
26951 * * 0x0-0xFFF8 - The function ID
26952 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26953 * * 0xFFFD - Reserved for user-space HWRM interface
26956 uint16_t target_id;
26958 * A physical address pointer pointing to a host buffer that the
26959 * command's response data will be written. This can be either a host
26960 * physical address (HPA) or a guest physical address (GPA) and must
26961 * point to a physically contiguous block of memory.
26963 uint64_t resp_addr;
26965 /* ovs_tunnel is 1 b */
26966 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
26970 * This bit must be '1' for the tunnel_type field to be
26973 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26976 * This bit must be '1' for the tunnel_id field to be
26979 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
26982 * This bit must be '1' for the src_macaddr field to be
26985 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
26988 * This bit must be '1' for the dst_macaddr field to be
26991 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
26994 * This bit must be '1' for the ovlan_vid field to be
26997 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
27000 * This bit must be '1' for the ivlan_vid field to be
27003 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
27006 * This bit must be '1' for the t_ovlan_vid field to be
27009 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
27012 * This bit must be '1' for the t_ivlan_vid field to be
27015 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
27018 * This bit must be '1' for the ethertype field to be
27021 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
27024 * This bit must be '1' for the src_ipaddr field to be
27027 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27030 * This bit must be '1' for the dst_ipaddr field to be
27033 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
27036 * This bit must be '1' for the ipaddr_type field to be
27039 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27042 * This bit must be '1' for the ip_protocol field to be
27045 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27048 * This bit must be '1' for the src_port field to be
27051 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
27054 * This bit must be '1' for the dst_port field to be
27057 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
27060 * This bit must be '1' for the dst_id field to be
27063 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27066 * This bit must be '1' for the mirror_vnic_id field to be
27069 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27072 * Tunnel identifier.
27073 * Virtual Network Identifier (VNI). Only valid with
27074 * tunnel_types VXLAN, NVGRE, and Geneve.
27075 * Only lower 24-bits of VNI field are used
27076 * in setting up the filter.
27078 uint32_t tunnel_id;
27080 uint8_t tunnel_type;
27082 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27084 /* Virtual eXtensible Local Area Network (VXLAN) */
27085 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27087 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27088 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27090 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27091 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27094 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27096 /* Generic Network Virtualization Encapsulation (Geneve) */
27097 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27099 /* Multi-Protocol Lable Switching (MPLS) */
27100 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27102 /* Stateless Transport Tunnel (STT) */
27103 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27105 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27106 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27108 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27109 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27111 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27112 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27114 /* Use fixed layer 2 ether type of 0xFFFF */
27115 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27117 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27118 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27120 /* Any tunneled traffic */
27121 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27123 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27124 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27128 * This value indicates the source MAC address in
27129 * the Ethernet header.
27131 uint8_t src_macaddr[6];
27132 uint8_t unused_2[2];
27134 * This value indicates the destination MAC address in
27135 * the Ethernet header.
27137 uint8_t dst_macaddr[6];
27139 * This value indicates the VLAN ID of the outer VLAN tag
27140 * in the Ethernet header.
27142 uint16_t ovlan_vid;
27144 * This value indicates the VLAN ID of the inner VLAN tag
27145 * in the Ethernet header.
27147 uint16_t ivlan_vid;
27149 * This value indicates the VLAN ID of the outer VLAN tag
27150 * in the tunnel Ethernet header.
27152 uint16_t t_ovlan_vid;
27154 * This value indicates the VLAN ID of the inner VLAN tag
27155 * in the tunnel Ethernet header.
27157 uint16_t t_ivlan_vid;
27158 /* This value indicates the ethertype in the Ethernet header. */
27159 uint16_t ethertype;
27161 * This value indicates the type of IP address.
27164 * All others are invalid.
27166 uint8_t ip_addr_type;
27168 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
27171 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
27174 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
27176 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
27177 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
27179 * The value of protocol filed in IP header.
27180 * Applies to UDP and TCP traffic.
27184 uint8_t ip_protocol;
27186 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
27189 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
27192 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
27194 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
27195 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
27199 * The value of source IP address to be used in filtering.
27200 * For IPv4, first four bytes represent the IP address.
27202 uint32_t src_ipaddr[4];
27204 * The value of destination IP address to be used in filtering.
27205 * For IPv4, first four bytes represent the IP address.
27207 uint32_t dst_ipaddr[4];
27209 * The value of source port to be used in filtering.
27210 * Applies to UDP and TCP traffic.
27214 * The value of destination port to be used in filtering.
27215 * Applies to UDP and TCP traffic.
27219 * If set, this value shall represent the
27220 * Logical VNIC ID of the destination VNIC for the RX
27225 * If set, this value shall represent the L2 context that matches the L2
27226 * information of the decap filter.
27228 uint16_t l2_ctxt_ref_id;
27229 } __attribute__((packed));
27231 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
27232 struct hwrm_cfa_decap_filter_alloc_output {
27233 /* The specific error status for the command. */
27234 uint16_t error_code;
27235 /* The HWRM command request type. */
27237 /* The sequence ID from the original command. */
27239 /* The length of the response data in number of bytes. */
27241 /* This value is an opaque id into CFA data structures. */
27242 uint32_t decap_filter_id;
27243 uint8_t unused_0[3];
27245 * This field is used in Output records to indicate that the output
27246 * is completely written to RAM. This field should be read as '1'
27247 * to indicate that the output has been completely written.
27248 * When writing a command completion or response to an internal processor,
27249 * the order of writes has to be such that this field is written last.
27252 } __attribute__((packed));
27254 /******************************
27255 * hwrm_cfa_decap_filter_free *
27256 ******************************/
27259 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
27260 struct hwrm_cfa_decap_filter_free_input {
27261 /* The HWRM command request type. */
27264 * The completion ring to send the completion event on. This should
27265 * be the NQ ID returned from the `nq_alloc` HWRM command.
27267 uint16_t cmpl_ring;
27269 * The sequence ID is used by the driver for tracking multiple
27270 * commands. This ID is treated as opaque data by the firmware and
27271 * the value is returned in the `hwrm_resp_hdr` upon completion.
27275 * The target ID of the command:
27276 * * 0x0-0xFFF8 - The function ID
27277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27278 * * 0xFFFD - Reserved for user-space HWRM interface
27281 uint16_t target_id;
27283 * A physical address pointer pointing to a host buffer that the
27284 * command's response data will be written. This can be either a host
27285 * physical address (HPA) or a guest physical address (GPA) and must
27286 * point to a physically contiguous block of memory.
27288 uint64_t resp_addr;
27289 /* This value is an opaque id into CFA data structures. */
27290 uint32_t decap_filter_id;
27291 uint8_t unused_0[4];
27292 } __attribute__((packed));
27294 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
27295 struct hwrm_cfa_decap_filter_free_output {
27296 /* The specific error status for the command. */
27297 uint16_t error_code;
27298 /* The HWRM command request type. */
27300 /* The sequence ID from the original command. */
27302 /* The length of the response data in number of bytes. */
27304 uint8_t unused_0[7];
27306 * This field is used in Output records to indicate that the output
27307 * is completely written to RAM. This field should be read as '1'
27308 * to indicate that the output has been completely written.
27309 * When writing a command completion or response to an internal processor,
27310 * the order of writes has to be such that this field is written last.
27313 } __attribute__((packed));
27315 /***********************
27316 * hwrm_cfa_flow_alloc *
27317 ***********************/
27320 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
27321 struct hwrm_cfa_flow_alloc_input {
27322 /* The HWRM command request type. */
27325 * The completion ring to send the completion event on. This should
27326 * be the NQ ID returned from the `nq_alloc` HWRM command.
27328 uint16_t cmpl_ring;
27330 * The sequence ID is used by the driver for tracking multiple
27331 * commands. This ID is treated as opaque data by the firmware and
27332 * the value is returned in the `hwrm_resp_hdr` upon completion.
27336 * The target ID of the command:
27337 * * 0x0-0xFFF8 - The function ID
27338 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27339 * * 0xFFFD - Reserved for user-space HWRM interface
27342 uint16_t target_id;
27344 * A physical address pointer pointing to a host buffer that the
27345 * command's response data will be written. This can be either a host
27346 * physical address (HPA) or a guest physical address (GPA) and must
27347 * point to a physically contiguous block of memory.
27349 uint64_t resp_addr;
27351 /* tunnel is 1 b */
27352 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
27354 /* num_vlan is 2 b */
27355 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
27357 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
27359 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
27360 (UINT32_C(0x0) << 1)
27362 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
27363 (UINT32_C(0x1) << 1)
27365 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
27366 (UINT32_C(0x2) << 1)
27367 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
27368 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
27369 /* Enumeration denoting the Flow Type. */
27370 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
27372 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
27374 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
27375 (UINT32_C(0x0) << 3)
27377 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
27378 (UINT32_C(0x1) << 3)
27380 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
27381 (UINT32_C(0x2) << 3)
27382 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
27383 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
27385 * when set to 1, indicates TX flow offload for function specified in src_fid and
27386 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
27387 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
27388 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
27389 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
27390 * belong to the children VFs of the same PF to indicate VM to VM flow.
27392 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
27395 * when set to 1, indicates RX flow offload for function specified in dst_fid and
27396 * the src_fid should be set to invalid value.
27398 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
27401 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
27402 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
27403 * This flag is only valid when the flow direction is RX.
27405 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
27407 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
27408 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
27415 /* Tunnel handle valid when tunnel flag is set. */
27416 uint32_t tunnel_handle;
27417 uint16_t action_flags;
27419 * Setting of this flag indicates drop action. If this flag is not set,
27420 * then it should be considered accept action.
27422 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
27424 /* recycle is 1 b */
27425 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
27428 * Setting of this flag indicates drop action. If this flag is not set,
27429 * then it should be considered accept action.
27431 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
27434 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
27436 /* tunnel is 1 b */
27437 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
27439 /* nat_src is 1 b */
27440 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
27442 /* nat_dest is 1 b */
27443 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
27445 /* nat_ipv4_address is 1 b */
27446 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
27448 /* l2_header_rewrite is 1 b */
27449 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
27451 /* ttl_decrement is 1 b */
27452 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
27455 * If set to 1 and flow direction is TX, it indicates decap of L2 header
27456 * and encap of tunnel header. If set to 1 and flow direction is RX, it
27457 * indicates decap of tunnel header and encap L2 header. The type of tunnel
27458 * is specified in the tunnel_type field.
27460 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
27462 /* If set to 1, flow aging is enabled for this flow. */
27463 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
27466 * If set to 1 an attempt will be made to try to offload this flow to the
27467 * most optimal flow table resource. If set to 0, the flow will be
27468 * placed to the default flow table resource.
27470 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
27473 * If set to 1 there will be no attempt to allocate an on-chip try to
27474 * offload this flow. If set to 0, which will keep compatibility with the
27475 * older drivers, will cause the FW to attempt to allocate an on-chip flow
27476 * counter for the newly created flow. This will keep the existing behavior
27477 * with EM flows which always had an associated flow counter.
27479 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
27482 * Tx Flow: pf or vf fid.
27486 /* VLAN tpid, valid when push_vlan flag is set. */
27487 uint16_t l2_rewrite_vlan_tpid;
27488 /* VLAN tci, valid when push_vlan flag is set. */
27489 uint16_t l2_rewrite_vlan_tci;
27490 /* Meter id, valid when meter flag is set. */
27491 uint16_t act_meter_id;
27492 /* Flow with the same l2 context tcam key. */
27493 uint16_t ref_flow_handle;
27494 /* This value sets the match value for the ethertype. */
27495 uint16_t ethertype;
27496 /* valid when num tags is 1 or 2. */
27497 uint16_t outer_vlan_tci;
27498 /* This value sets the match value for the Destination MAC address. */
27500 /* valid when num tags is 2. */
27501 uint16_t inner_vlan_tci;
27502 /* This value sets the match value for the Source MAC address. */
27504 /* The bit length of destination IP address mask. */
27505 uint8_t ip_dst_mask_len;
27506 /* The bit length of source IP address mask. */
27507 uint8_t ip_src_mask_len;
27508 /* The value of destination IPv4/IPv6 address. */
27509 uint32_t ip_dst[4];
27510 /* The source IPv4/IPv6 address. */
27511 uint32_t ip_src[4];
27513 * The value of source port.
27514 * Applies to UDP and TCP traffic.
27516 uint16_t l4_src_port;
27518 * The value of source port mask.
27519 * Applies to UDP and TCP traffic.
27521 uint16_t l4_src_port_mask;
27523 * The value of destination port.
27524 * Applies to UDP and TCP traffic.
27526 uint16_t l4_dst_port;
27528 * The value of destination port mask.
27529 * Applies to UDP and TCP traffic.
27531 uint16_t l4_dst_port_mask;
27533 * NAT IPv4/6 address based on address type flag.
27534 * 0 values are ignored.
27536 uint32_t nat_ip_address[4];
27537 /* L2 header re-write Destination MAC address. */
27538 uint16_t l2_rewrite_dmac[3];
27540 * The NAT source/destination port based on direction flag.
27541 * Applies to UDP and TCP traffic.
27542 * 0 values are ignored.
27545 /* L2 header re-write Source MAC address. */
27546 uint16_t l2_rewrite_smac[3];
27547 /* The value of ip protocol. */
27550 uint8_t tunnel_type;
27552 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27554 /* Virtual eXtensible Local Area Network (VXLAN) */
27555 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27557 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27558 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27560 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27561 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27564 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27566 /* Generic Network Virtualization Encapsulation (Geneve) */
27567 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27569 /* Multi-Protocol Lable Switching (MPLS) */
27570 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27572 /* Stateless Transport Tunnel (STT) */
27573 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
27575 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27576 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27578 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27579 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27581 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27582 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27584 /* Use fixed layer 2 ether type of 0xFFFF */
27585 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27587 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27588 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27590 /* Any tunneled traffic */
27591 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27593 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27594 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27595 } __attribute__((packed));
27597 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
27598 struct hwrm_cfa_flow_alloc_output {
27599 /* The specific error status for the command. */
27600 uint16_t error_code;
27601 /* The HWRM command request type. */
27603 /* The sequence ID from the original command. */
27605 /* The length of the response data in number of bytes. */
27607 /* Flow record index. */
27608 uint16_t flow_handle;
27609 uint8_t unused_0[2];
27611 * The flow id value in bit 0-29 is the actual ID of the flow
27612 * associated with this filter and it shall be used to match
27613 * and associate the flow identifier returned in completion
27614 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
27615 * shall indicate no valid flow id.
27618 /* Indicate the flow id value. */
27619 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
27620 UINT32_C(0x3fffffff)
27621 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
27622 /* Indicate type of the flow. */
27623 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
27624 UINT32_C(0x40000000)
27626 * If this bit set to 0, then it indicates that the flow is
27629 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
27630 (UINT32_C(0x0) << 30)
27632 * If this bit is set to 1, then it indicates that the flow is
27635 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
27636 (UINT32_C(0x1) << 30)
27637 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
27638 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
27639 /* Indicate the flow direction. */
27640 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
27641 UINT32_C(0x80000000)
27642 /* If this bit set to 0, then it indicates rx flow. */
27643 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
27644 (UINT32_C(0x0) << 31)
27645 /* If this bit is set to 1, then it indicates that tx flow. */
27646 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
27647 (UINT32_C(0x1) << 31)
27648 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
27649 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
27650 /* This value identifies a set of CFA data structures used for a flow. */
27651 uint64_t ext_flow_handle;
27652 uint32_t flow_counter_id;
27653 uint8_t unused_1[3];
27655 * This field is used in Output records to indicate that the output
27656 * is completely written to RAM. This field should be read as '1'
27657 * to indicate that the output has been completely written.
27658 * When writing a command completion or response to an internal processor,
27659 * the order of writes has to be such that this field is written last.
27662 } __attribute__((packed));
27664 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
27665 struct hwrm_cfa_flow_alloc_cmd_err {
27667 * command specific error codes that goes to
27668 * the cmd_err field in Common HWRM Error Response.
27671 /* Unknown error */
27672 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27673 /* No more L2 Context TCAM */
27674 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
27675 /* No more action records */
27676 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
27677 /* No more flow counters */
27678 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
27679 /* No more wild-card TCAM */
27680 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
27681 /* Hash collsion in exact match tables */
27682 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
27683 /* Key is already installed */
27684 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
27685 /* Flow Context DB is out of resource */
27686 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
27687 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
27688 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
27689 uint8_t unused_0[7];
27690 } __attribute__((packed));
27692 /**********************
27693 * hwrm_cfa_flow_free *
27694 **********************/
27697 /* hwrm_cfa_flow_free_input (size:256b/32B) */
27698 struct hwrm_cfa_flow_free_input {
27699 /* The HWRM command request type. */
27702 * The completion ring to send the completion event on. This should
27703 * be the NQ ID returned from the `nq_alloc` HWRM command.
27705 uint16_t cmpl_ring;
27707 * The sequence ID is used by the driver for tracking multiple
27708 * commands. This ID is treated as opaque data by the firmware and
27709 * the value is returned in the `hwrm_resp_hdr` upon completion.
27713 * The target ID of the command:
27714 * * 0x0-0xFFF8 - The function ID
27715 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27716 * * 0xFFFD - Reserved for user-space HWRM interface
27719 uint16_t target_id;
27721 * A physical address pointer pointing to a host buffer that the
27722 * command's response data will be written. This can be either a host
27723 * physical address (HPA) or a guest physical address (GPA) and must
27724 * point to a physically contiguous block of memory.
27726 uint64_t resp_addr;
27727 /* Flow record index. */
27728 uint16_t flow_handle;
27730 /* Flow counter id to be freed. */
27731 uint32_t flow_counter_id;
27732 /* This value identifies a set of CFA data structures used for a flow. */
27733 uint64_t ext_flow_handle;
27734 } __attribute__((packed));
27736 /* hwrm_cfa_flow_free_output (size:256b/32B) */
27737 struct hwrm_cfa_flow_free_output {
27738 /* The specific error status for the command. */
27739 uint16_t error_code;
27740 /* The HWRM command request type. */
27742 /* The sequence ID from the original command. */
27744 /* The length of the response data in number of bytes. */
27746 /* packet is 64 b */
27750 uint8_t unused_0[7];
27752 * This field is used in Output records to indicate that the output
27753 * is completely written to RAM. This field should be read as '1'
27754 * to indicate that the output has been completely written.
27755 * When writing a command completion or response to an internal processor,
27756 * the order of writes has to be such that this field is written last.
27759 } __attribute__((packed));
27761 /* hwrm_cfa_flow_action_data (size:960b/120B) */
27762 struct hwrm_cfa_flow_action_data {
27763 uint16_t action_flags;
27764 /* Setting of this flag indicates accept action. */
27765 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
27767 /* Setting of this flag indicates recycle action. */
27768 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
27770 /* Setting of this flag indicates drop action. */
27771 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
27773 /* Setting of this flag indicates meter action. */
27774 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
27776 /* Setting of this flag indicates tunnel action. */
27777 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
27780 * If set to 1 and flow direction is TX, it indicates decap of L2 header
27781 * and encap of tunnel header. If set to 1 and flow direction is RX, it
27782 * indicates decap of tunnel header and encap L2 header.
27784 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
27786 /* Setting of this flag indicates ttl decrement action. */
27787 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
27789 /* If set to 1, flow aging is enabled for this flow. */
27790 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
27792 /* Setting of this flag indicates encap action.. */
27793 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
27795 /* Setting of this flag indicates decap action.. */
27796 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
27799 uint16_t act_meter_id;
27802 /* vport number. */
27804 /* The NAT source/destination. */
27806 uint16_t unused_0[3];
27807 /* NAT IPv4/IPv6 address. */
27808 uint32_t nat_ip_address[4];
27809 /* Encapsulation Type. */
27810 uint8_t encap_type;
27811 /* Virtual eXtensible Local Area Network (VXLAN) */
27812 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
27813 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27814 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
27815 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
27816 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
27818 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
27819 /* Generic Network Virtualization Encapsulation (Geneve) */
27820 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
27821 /* Multi-Protocol Lable Switching (MPLS) */
27822 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
27824 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
27825 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27826 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
27827 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27828 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
27829 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27830 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
27831 /* Use fixed layer 2 ether type of 0xFFFF */
27832 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
27833 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27834 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
27835 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
27836 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
27838 /* This value is encap data for the associated encap type. */
27839 uint32_t encap_data[20];
27840 } __attribute__((packed));
27842 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
27843 struct hwrm_cfa_flow_tunnel_hdr_data {
27845 uint8_t tunnel_type;
27847 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
27849 /* Virtual eXtensible Local Area Network (VXLAN) */
27850 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
27852 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27853 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
27855 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27856 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
27859 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
27861 /* Generic Network Virtualization Encapsulation (Geneve) */
27862 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
27864 /* Multi-Protocol Lable Switching (MPLS) */
27865 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
27867 /* Stateless Transport Tunnel (STT) */
27868 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
27870 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27871 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
27873 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27874 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
27876 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27877 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
27879 /* Use fixed layer 2 ether type of 0xFFFF */
27880 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
27882 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27883 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
27885 /* Any tunneled traffic */
27886 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
27888 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
27889 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
27892 * Tunnel identifier.
27893 * Virtual Network Identifier (VNI).
27895 uint32_t tunnel_id;
27896 } __attribute__((packed));
27898 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
27899 struct hwrm_cfa_flow_l4_key_data {
27900 /* The value of source port. */
27901 uint16_t l4_src_port;
27902 /* The value of destination port. */
27903 uint16_t l4_dst_port;
27905 } __attribute__((packed));
27907 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
27908 struct hwrm_cfa_flow_l3_key_data {
27909 /* The value of ip protocol. */
27910 uint8_t ip_protocol;
27911 uint8_t unused_0[7];
27912 /* The value of destination IPv4/IPv6 address. */
27913 uint32_t ip_dst[4];
27914 /* The source IPv4/IPv6 address. */
27915 uint32_t ip_src[4];
27916 /* NAT IPv4/IPv6 address. */
27917 uint32_t nat_ip_address[4];
27918 uint32_t unused[2];
27919 } __attribute__((packed));
27921 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
27922 struct hwrm_cfa_flow_l2_key_data {
27923 /* Destination MAC address. */
27926 /* Source MAC address. */
27929 /* L2 header re-write Destination MAC address. */
27930 uint16_t l2_rewrite_dmac[3];
27932 /* L2 header re-write Source MAC address. */
27933 uint16_t l2_rewrite_smac[3];
27935 uint16_t ethertype;
27936 /* Number of VLAN tags. */
27937 uint16_t num_vlan_tags;
27939 uint16_t l2_rewrite_vlan_tpid;
27941 uint16_t l2_rewrite_vlan_tci;
27942 uint8_t unused_3[2];
27943 /* Outer VLAN TPID. */
27944 uint16_t ovlan_tpid;
27945 /* Outer VLAN TCI. */
27946 uint16_t ovlan_tci;
27947 /* Inner VLAN TPID. */
27948 uint16_t ivlan_tpid;
27949 /* Inner VLAN TCI. */
27950 uint16_t ivlan_tci;
27952 } __attribute__((packed));
27954 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
27955 struct hwrm_cfa_flow_key_data {
27956 /* Flow associated tunnel L2 header key info. */
27957 uint32_t t_l2_key_data[14];
27958 /* Flow associated tunnel L2 header mask info. */
27959 uint32_t t_l2_key_mask[14];
27960 /* Flow associated tunnel L3 header key info. */
27961 uint32_t t_l3_key_data[16];
27962 /* Flow associated tunnel L3 header mask info. */
27963 uint32_t t_l3_key_mask[16];
27964 /* Flow associated tunnel L4 header key info. */
27965 uint32_t t_l4_key_data[2];
27966 /* Flow associated tunnel L4 header mask info. */
27967 uint32_t t_l4_key_mask[2];
27968 /* Flow associated tunnel header info. */
27969 uint32_t tunnel_hdr[2];
27970 /* Flow associated L2 header key info. */
27971 uint32_t l2_key_data[14];
27972 /* Flow associated L2 header mask info. */
27973 uint32_t l2_key_mask[14];
27974 /* Flow associated L3 header key info. */
27975 uint32_t l3_key_data[16];
27976 /* Flow associated L3 header mask info. */
27977 uint32_t l3_key_mask[16];
27978 /* Flow associated L4 header key info. */
27979 uint32_t l4_key_data[2];
27980 /* Flow associated L4 header mask info. */
27981 uint32_t l4_key_mask[2];
27982 } __attribute__((packed));
27984 /**********************
27985 * hwrm_cfa_flow_info *
27986 **********************/
27989 /* hwrm_cfa_flow_info_input (size:256b/32B) */
27990 struct hwrm_cfa_flow_info_input {
27991 /* The HWRM command request type. */
27994 * The completion ring to send the completion event on. This should
27995 * be the NQ ID returned from the `nq_alloc` HWRM command.
27997 uint16_t cmpl_ring;
27999 * The sequence ID is used by the driver for tracking multiple
28000 * commands. This ID is treated as opaque data by the firmware and
28001 * the value is returned in the `hwrm_resp_hdr` upon completion.
28005 * The target ID of the command:
28006 * * 0x0-0xFFF8 - The function ID
28007 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28008 * * 0xFFFD - Reserved for user-space HWRM interface
28011 uint16_t target_id;
28013 * A physical address pointer pointing to a host buffer that the
28014 * command's response data will be written. This can be either a host
28015 * physical address (HPA) or a guest physical address (GPA) and must
28016 * point to a physically contiguous block of memory.
28018 uint64_t resp_addr;
28019 /* Flow record index. */
28020 uint16_t flow_handle;
28021 /* Max flow handle */
28022 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
28024 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
28025 /* CNP flow handle */
28026 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
28028 /* RoCEv1 flow handle */
28029 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
28031 /* RoCEv2 flow handle */
28032 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
28034 /* Direction rx = 1 */
28035 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
28037 uint8_t unused_0[6];
28038 /* This value identifies a set of CFA data structures used for a flow. */
28039 uint64_t ext_flow_handle;
28040 } __attribute__((packed));
28042 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
28043 struct hwrm_cfa_flow_info_output {
28044 /* The specific error status for the command. */
28045 uint16_t error_code;
28046 /* The HWRM command request type. */
28048 /* The sequence ID from the original command. */
28050 /* The length of the response data in number of bytes. */
28053 /* When set to 1, indicates the configuration is the TX flow. */
28054 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
28055 /* When set to 1, indicates the configuration is the RX flow. */
28056 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
28057 /* profile is 8 b */
28059 /* src_fid is 16 b */
28061 /* dst_fid is 16 b */
28063 /* l2_ctxt_id is 16 b */
28064 uint16_t l2_ctxt_id;
28065 /* em_info is 64 b */
28067 /* tcam_info is 64 b */
28068 uint64_t tcam_info;
28069 /* vfp_tcam_info is 64 b */
28070 uint64_t vfp_tcam_info;
28071 /* ar_id is 16 b */
28073 /* flow_handle is 16 b */
28074 uint16_t flow_handle;
28075 /* tunnel_handle is 32 b */
28076 uint32_t tunnel_handle;
28077 /* The flow aging timer for the flow, the unit is 100 milliseconds */
28078 uint16_t flow_timer;
28079 uint8_t unused_0[6];
28080 /* Flow associated L2, L3 and L4 headers info. */
28081 uint32_t flow_key_data[130];
28082 /* Flow associated action record info. */
28083 uint32_t flow_action_info[30];
28084 uint8_t unused_1[7];
28086 * This field is used in Output records to indicate that the output
28087 * is completely written to RAM. This field should be read as '1'
28088 * to indicate that the output has been completely written.
28089 * When writing a command completion or response to an internal processor,
28090 * the order of writes has to be such that this field is written last.
28093 } __attribute__((packed));
28095 /***********************
28096 * hwrm_cfa_flow_flush *
28097 ***********************/
28100 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
28101 struct hwrm_cfa_flow_flush_input {
28102 /* The HWRM command request type. */
28105 * The completion ring to send the completion event on. This should
28106 * be the NQ ID returned from the `nq_alloc` HWRM command.
28108 uint16_t cmpl_ring;
28110 * The sequence ID is used by the driver for tracking multiple
28111 * commands. This ID is treated as opaque data by the firmware and
28112 * the value is returned in the `hwrm_resp_hdr` upon completion.
28116 * The target ID of the command:
28117 * * 0x0-0xFFF8 - The function ID
28118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28119 * * 0xFFFD - Reserved for user-space HWRM interface
28122 uint16_t target_id;
28124 * A physical address pointer pointing to a host buffer that the
28125 * command's response data will be written. This can be either a host
28126 * physical address (HPA) or a guest physical address (GPA) and must
28127 * point to a physically contiguous block of memory.
28129 uint64_t resp_addr;
28130 /* flags is 32 b */
28133 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
28134 * fields are valid. The flow flush operation should only flush the flows from the
28135 * flow table specified. This flag is set to 0 by older driver. For older firmware,
28136 * setting this flag has no effect.
28138 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
28141 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
28142 * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
28143 * setting this flag has no effect.
28145 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
28147 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
28148 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
28149 UINT32_C(0x8000000)
28151 * This specifies the size of flow handle entries provided by the driver
28152 * in the flow table specified below. Only two flow handle size enums are defined.
28154 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
28155 UINT32_C(0xc0000000)
28156 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
28158 /* The flow handle is 16bit */
28159 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
28160 (UINT32_C(0x0) << 30)
28161 /* The flow handle is 64bit */
28162 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
28163 (UINT32_C(0x1) << 30)
28164 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
28165 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
28166 /* Specify page size of the flow table memory. */
28168 /* The page size is 4K */
28169 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
28170 /* The page size is 8K */
28171 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
28172 /* The page size is 64K */
28173 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
28174 /* The page size is 256K */
28175 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
28176 /* The page size is 1M */
28177 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
28178 /* The page size is 2M */
28179 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
28180 /* The page size is 4M */
28181 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
28182 /* The page size is 1G */
28183 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
28184 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
28185 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
28186 /* FLow table memory indirect levels. */
28187 uint8_t page_level;
28188 /* PBL pointer is physical start address. */
28189 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
28190 /* PBL pointer points to PTE table. */
28191 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
28192 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
28193 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
28194 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
28195 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
28196 /* number of flows in the flow table */
28197 uint16_t num_flows;
28198 /* Pointer to the PBL, or PDL depending on number of levels */
28200 } __attribute__((packed));
28202 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
28203 struct hwrm_cfa_flow_flush_output {
28204 /* The specific error status for the command. */
28205 uint16_t error_code;
28206 /* The HWRM command request type. */
28208 /* The sequence ID from the original command. */
28210 /* The length of the response data in number of bytes. */
28212 uint8_t unused_0[7];
28214 * This field is used in Output records to indicate that the output
28215 * is completely written to RAM. This field should be read as '1'
28216 * to indicate that the output has been completely written.
28217 * When writing a command completion or response to an internal processor,
28218 * the order of writes has to be such that this field is written last.
28221 } __attribute__((packed));
28223 /***********************
28224 * hwrm_cfa_flow_stats *
28225 ***********************/
28228 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
28229 struct hwrm_cfa_flow_stats_input {
28230 /* The HWRM command request type. */
28233 * The completion ring to send the completion event on. This should
28234 * be the NQ ID returned from the `nq_alloc` HWRM command.
28236 uint16_t cmpl_ring;
28238 * The sequence ID is used by the driver for tracking multiple
28239 * commands. This ID is treated as opaque data by the firmware and
28240 * the value is returned in the `hwrm_resp_hdr` upon completion.
28244 * The target ID of the command:
28245 * * 0x0-0xFFF8 - The function ID
28246 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28247 * * 0xFFFD - Reserved for user-space HWRM interface
28250 uint16_t target_id;
28252 * A physical address pointer pointing to a host buffer that the
28253 * command's response data will be written. This can be either a host
28254 * physical address (HPA) or a guest physical address (GPA) and must
28255 * point to a physically contiguous block of memory.
28257 uint64_t resp_addr;
28259 uint16_t num_flows;
28261 uint16_t flow_handle_0;
28263 uint16_t flow_handle_1;
28265 uint16_t flow_handle_2;
28267 uint16_t flow_handle_3;
28269 uint16_t flow_handle_4;
28271 uint16_t flow_handle_5;
28273 uint16_t flow_handle_6;
28275 uint16_t flow_handle_7;
28277 uint16_t flow_handle_8;
28279 uint16_t flow_handle_9;
28280 uint8_t unused_0[2];
28281 /* Flow ID of a flow. */
28282 uint32_t flow_id_0;
28283 /* Flow ID of a flow. */
28284 uint32_t flow_id_1;
28285 /* Flow ID of a flow. */
28286 uint32_t flow_id_2;
28287 /* Flow ID of a flow. */
28288 uint32_t flow_id_3;
28289 /* Flow ID of a flow. */
28290 uint32_t flow_id_4;
28291 /* Flow ID of a flow. */
28292 uint32_t flow_id_5;
28293 /* Flow ID of a flow. */
28294 uint32_t flow_id_6;
28295 /* Flow ID of a flow. */
28296 uint32_t flow_id_7;
28297 /* Flow ID of a flow. */
28298 uint32_t flow_id_8;
28299 /* Flow ID of a flow. */
28300 uint32_t flow_id_9;
28301 } __attribute__((packed));
28303 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
28304 struct hwrm_cfa_flow_stats_output {
28305 /* The specific error status for the command. */
28306 uint16_t error_code;
28307 /* The HWRM command request type. */
28309 /* The sequence ID from the original command. */
28311 /* The length of the response data in number of bytes. */
28313 /* packet_0 is 64 b */
28315 /* packet_1 is 64 b */
28317 /* packet_2 is 64 b */
28319 /* packet_3 is 64 b */
28321 /* packet_4 is 64 b */
28323 /* packet_5 is 64 b */
28325 /* packet_6 is 64 b */
28327 /* packet_7 is 64 b */
28329 /* packet_8 is 64 b */
28331 /* packet_9 is 64 b */
28333 /* byte_0 is 64 b */
28335 /* byte_1 is 64 b */
28337 /* byte_2 is 64 b */
28339 /* byte_3 is 64 b */
28341 /* byte_4 is 64 b */
28343 /* byte_5 is 64 b */
28345 /* byte_6 is 64 b */
28347 /* byte_7 is 64 b */
28349 /* byte_8 is 64 b */
28351 /* byte_9 is 64 b */
28353 uint8_t unused_0[7];
28355 * This field is used in Output records to indicate that the output
28356 * is completely written to RAM. This field should be read as '1'
28357 * to indicate that the output has been completely written.
28358 * When writing a command completion or response to an internal processor,
28359 * the order of writes has to be such that this field is written last.
28362 } __attribute__((packed));
28364 /***********************************
28365 * hwrm_cfa_flow_aging_timer_reset *
28366 ***********************************/
28369 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
28370 struct hwrm_cfa_flow_aging_timer_reset_input {
28371 /* The HWRM command request type. */
28374 * The completion ring to send the completion event on. This should
28375 * be the NQ ID returned from the `nq_alloc` HWRM command.
28377 uint16_t cmpl_ring;
28379 * The sequence ID is used by the driver for tracking multiple
28380 * commands. This ID is treated as opaque data by the firmware and
28381 * the value is returned in the `hwrm_resp_hdr` upon completion.
28385 * The target ID of the command:
28386 * * 0x0-0xFFF8 - The function ID
28387 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28388 * * 0xFFFD - Reserved for user-space HWRM interface
28391 uint16_t target_id;
28393 * A physical address pointer pointing to a host buffer that the
28394 * command's response data will be written. This can be either a host
28395 * physical address (HPA) or a guest physical address (GPA) and must
28396 * point to a physically contiguous block of memory.
28398 uint64_t resp_addr;
28399 /* Flow record index. */
28400 uint16_t flow_handle;
28401 uint8_t unused_0[2];
28403 * New flow timer value for the flow specified in the ext_flow_handle.
28404 * The flow timer unit is 100ms.
28406 uint32_t flow_timer;
28407 /* This value identifies a set of CFA data structures used for a flow. */
28408 uint64_t ext_flow_handle;
28409 } __attribute__((packed));
28411 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
28412 struct hwrm_cfa_flow_aging_timer_reset_output {
28413 /* The specific error status for the command. */
28414 uint16_t error_code;
28415 /* The HWRM command request type. */
28417 /* The sequence ID from the original command. */
28419 /* The length of the response data in number of bytes. */
28421 uint8_t unused_0[7];
28423 * This field is used in Output records to indicate that the output
28424 * is completely written to RAM. This field should be read as '1'
28425 * to indicate that the output has been completely written.
28426 * When writing a command completion or response to an internal processor,
28427 * the order of writes has to be such that this field is written last.
28430 } __attribute__((packed));
28432 /***************************
28433 * hwrm_cfa_flow_aging_cfg *
28434 ***************************/
28437 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
28438 struct hwrm_cfa_flow_aging_cfg_input {
28439 /* The HWRM command request type. */
28442 * The completion ring to send the completion event on. This should
28443 * be the NQ ID returned from the `nq_alloc` HWRM command.
28445 uint16_t cmpl_ring;
28447 * The sequence ID is used by the driver for tracking multiple
28448 * commands. This ID is treated as opaque data by the firmware and
28449 * the value is returned in the `hwrm_resp_hdr` upon completion.
28453 * The target ID of the command:
28454 * * 0x0-0xFFF8 - The function ID
28455 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28456 * * 0xFFFD - Reserved for user-space HWRM interface
28459 uint16_t target_id;
28461 * A physical address pointer pointing to a host buffer that the
28462 * command's response data will be written. This can be either a host
28463 * physical address (HPA) or a guest physical address (GPA) and must
28464 * point to a physically contiguous block of memory.
28466 uint64_t resp_addr;
28467 /* The bit field to enable per flow aging configuration. */
28469 /* This bit must be '1' for the tcp flow timer field to be configured */
28470 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
28472 /* This bit must be '1' for the tcp finish timer field to be configured */
28473 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
28475 /* This bit must be '1' for the udp flow timer field to be configured */
28476 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
28478 /* This bit must be '1' for the eem dma interval field to be configured */
28479 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
28481 /* This bit must be '1' for the eem notice interval field to be configured */
28482 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
28484 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
28485 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
28487 /* This bit must be '1' for the eem context memory ID field to be configured */
28488 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
28490 /* This bit must be '1' for the eem context memory type field to be configured */
28491 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
28494 /* Enumeration denoting the RX, TX type of the resource. */
28495 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28497 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28499 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28500 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
28501 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
28502 /* Enumeration denoting the enable, disable eem flow aging configuration. */
28503 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
28505 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
28506 (UINT32_C(0x0) << 1)
28508 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
28509 (UINT32_C(0x1) << 1)
28510 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
28511 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
28513 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
28514 uint32_t tcp_flow_timer;
28515 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
28516 uint32_t tcp_fin_timer;
28517 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
28518 uint32_t udp_flow_timer;
28519 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
28520 uint16_t eem_dma_interval;
28521 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
28522 uint16_t eem_notice_interval;
28523 /* The maximum entries number in the eem context memory. */
28524 uint32_t eem_ctx_max_entries;
28525 /* The context memory ID for eem flow aging. */
28526 uint16_t eem_ctx_id;
28527 uint16_t eem_ctx_mem_type;
28528 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
28529 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
28531 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
28532 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
28533 uint8_t unused_1[4];
28534 } __attribute__((packed));
28536 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
28537 struct hwrm_cfa_flow_aging_cfg_output {
28538 /* The specific error status for the command. */
28539 uint16_t error_code;
28540 /* The HWRM command request type. */
28542 /* The sequence ID from the original command. */
28544 /* The length of the response data in number of bytes. */
28546 uint8_t unused_0[7];
28548 * This field is used in Output records to indicate that the output
28549 * is completely written to RAM. This field should be read as '1'
28550 * to indicate that the output has been completely written.
28551 * When writing a command completion or response to an internal processor,
28552 * the order of writes has to be such that this field is written last.
28555 } __attribute__((packed));
28557 /****************************
28558 * hwrm_cfa_flow_aging_qcfg *
28559 ****************************/
28562 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
28563 struct hwrm_cfa_flow_aging_qcfg_input {
28564 /* The HWRM command request type. */
28567 * The completion ring to send the completion event on. This should
28568 * be the NQ ID returned from the `nq_alloc` HWRM command.
28570 uint16_t cmpl_ring;
28572 * The sequence ID is used by the driver for tracking multiple
28573 * commands. This ID is treated as opaque data by the firmware and
28574 * the value is returned in the `hwrm_resp_hdr` upon completion.
28578 * The target ID of the command:
28579 * * 0x0-0xFFF8 - The function ID
28580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28581 * * 0xFFFD - Reserved for user-space HWRM interface
28584 uint16_t target_id;
28586 * A physical address pointer pointing to a host buffer that the
28587 * command's response data will be written. This can be either a host
28588 * physical address (HPA) or a guest physical address (GPA) and must
28589 * point to a physically contiguous block of memory.
28591 uint64_t resp_addr;
28592 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
28594 /* Enumeration denoting the RX, TX type of the resource. */
28595 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28597 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28599 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28600 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
28601 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
28602 uint8_t unused_0[7];
28603 } __attribute__((packed));
28605 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
28606 struct hwrm_cfa_flow_aging_qcfg_output {
28607 /* The specific error status for the command. */
28608 uint16_t error_code;
28609 /* The HWRM command request type. */
28611 /* The sequence ID from the original command. */
28613 /* The length of the response data in number of bytes. */
28615 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
28616 uint32_t tcp_flow_timer;
28617 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
28618 uint32_t tcp_fin_timer;
28619 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
28620 uint32_t udp_flow_timer;
28621 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
28622 uint16_t eem_dma_interval;
28623 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
28624 uint16_t eem_notice_interval;
28625 /* The maximum entries number in the eem context memory. */
28626 uint32_t eem_ctx_max_entries;
28627 /* The context memory ID for eem flow aging. */
28628 uint16_t eem_ctx_id;
28629 /* The context memory type for eem flow aging. */
28630 uint16_t eem_ctx_mem_type;
28631 uint8_t unused_0[7];
28633 * This field is used in Output records to indicate that the output
28634 * is completely written to RAM. This field should be read as '1'
28635 * to indicate that the output has been completely written.
28636 * When writing a command completion or response to an internal processor,
28637 * the order of writes has to be such that this field is written last.
28640 } __attribute__((packed));
28642 /*****************************
28643 * hwrm_cfa_flow_aging_qcaps *
28644 *****************************/
28647 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
28648 struct hwrm_cfa_flow_aging_qcaps_input {
28649 /* The HWRM command request type. */
28652 * The completion ring to send the completion event on. This should
28653 * be the NQ ID returned from the `nq_alloc` HWRM command.
28655 uint16_t cmpl_ring;
28657 * The sequence ID is used by the driver for tracking multiple
28658 * commands. This ID is treated as opaque data by the firmware and
28659 * the value is returned in the `hwrm_resp_hdr` upon completion.
28663 * The target ID of the command:
28664 * * 0x0-0xFFF8 - The function ID
28665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28666 * * 0xFFFD - Reserved for user-space HWRM interface
28669 uint16_t target_id;
28671 * A physical address pointer pointing to a host buffer that the
28672 * command's response data will be written. This can be either a host
28673 * physical address (HPA) or a guest physical address (GPA) and must
28674 * point to a physically contiguous block of memory.
28676 uint64_t resp_addr;
28677 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
28679 /* Enumeration denoting the RX, TX type of the resource. */
28680 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
28682 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28684 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28685 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
28686 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
28687 uint8_t unused_0[7];
28688 } __attribute__((packed));
28690 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
28691 struct hwrm_cfa_flow_aging_qcaps_output {
28692 /* The specific error status for the command. */
28693 uint16_t error_code;
28694 /* The HWRM command request type. */
28696 /* The sequence ID from the original command. */
28698 /* The length of the response data in number of bytes. */
28700 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
28701 uint32_t max_tcp_flow_timer;
28702 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
28703 uint32_t max_tcp_fin_timer;
28704 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
28705 uint32_t max_udp_flow_timer;
28706 /* The maximum aging flows that HW can support. */
28707 uint32_t max_aging_flows;
28708 uint8_t unused_0[7];
28710 * This field is used in Output records to indicate that the output
28711 * is completely written to RAM. This field should be read as '1'
28712 * to indicate that the output has been completely written.
28713 * When writing a command completion or response to an internal processor,
28714 * the order of writes has to be such that this field is written last.
28717 } __attribute__((packed));
28719 /**********************************
28720 * hwrm_cfa_tcp_flag_process_qcfg *
28721 **********************************/
28724 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
28725 struct hwrm_cfa_tcp_flag_process_qcfg_input {
28726 /* The HWRM command request type. */
28729 * The completion ring to send the completion event on. This should
28730 * be the NQ ID returned from the `nq_alloc` HWRM command.
28732 uint16_t cmpl_ring;
28734 * The sequence ID is used by the driver for tracking multiple
28735 * commands. This ID is treated as opaque data by the firmware and
28736 * the value is returned in the `hwrm_resp_hdr` upon completion.
28740 * The target ID of the command:
28741 * * 0x0-0xFFF8 - The function ID
28742 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28743 * * 0xFFFD - Reserved for user-space HWRM interface
28746 uint16_t target_id;
28748 * A physical address pointer pointing to a host buffer that the
28749 * command's response data will be written. This can be either a host
28750 * physical address (HPA) or a guest physical address (GPA) and must
28751 * point to a physically contiguous block of memory.
28753 uint64_t resp_addr;
28754 } __attribute__((packed));
28756 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
28757 struct hwrm_cfa_tcp_flag_process_qcfg_output {
28758 /* The specific error status for the command. */
28759 uint16_t error_code;
28760 /* The HWRM command request type. */
28762 /* The sequence ID from the original command. */
28764 /* The length of the response data in number of bytes. */
28766 /* The port 0 RX mirror action record ID. */
28767 uint16_t rx_ar_id_port0;
28768 /* The port 1 RX mirror action record ID. */
28769 uint16_t rx_ar_id_port1;
28770 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
28771 uint16_t tx_ar_id_port0;
28772 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
28773 uint16_t tx_ar_id_port1;
28774 uint8_t unused_0[7];
28776 * This field is used in Output records to indicate that the output
28777 * is completely written to RAM. This field should be read as '1'
28778 * to indicate that the output has been completely written.
28779 * When writing a command completion or response to an internal processor,
28780 * the order of writes has to be such that this field is written last.
28783 } __attribute__((packed));
28785 /**********************
28786 * hwrm_cfa_pair_info *
28787 **********************/
28790 /* hwrm_cfa_pair_info_input (size:448b/56B) */
28791 struct hwrm_cfa_pair_info_input {
28792 /* The HWRM command request type. */
28795 * The completion ring to send the completion event on. This should
28796 * be the NQ ID returned from the `nq_alloc` HWRM command.
28798 uint16_t cmpl_ring;
28800 * The sequence ID is used by the driver for tracking multiple
28801 * commands. This ID is treated as opaque data by the firmware and
28802 * the value is returned in the `hwrm_resp_hdr` upon completion.
28806 * The target ID of the command:
28807 * * 0x0-0xFFF8 - The function ID
28808 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28809 * * 0xFFFD - Reserved for user-space HWRM interface
28812 uint16_t target_id;
28814 * A physical address pointer pointing to a host buffer that the
28815 * command's response data will be written. This can be either a host
28816 * physical address (HPA) or a guest physical address (GPA) and must
28817 * point to a physically contiguous block of memory.
28819 uint64_t resp_addr;
28821 /* If this flag is set, lookup by name else lookup by index. */
28822 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
28823 /* If this flag is set, lookup by PF id and VF id. */
28824 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
28825 /* Pair table index. */
28826 uint16_t pair_index;
28827 /* Pair pf index. */
28829 /* Pair vf index. */
28831 /* Pair name (32 byte string). */
28832 char pair_name[32];
28833 } __attribute__((packed));
28835 /* hwrm_cfa_pair_info_output (size:576b/72B) */
28836 struct hwrm_cfa_pair_info_output {
28837 /* The specific error status for the command. */
28838 uint16_t error_code;
28839 /* The HWRM command request type. */
28841 /* The sequence ID from the original command. */
28843 /* The length of the response data in number of bytes. */
28845 /* Pair table index. */
28846 uint16_t next_pair_index;
28847 /* Pair member a's fid. */
28849 /* Logical host number. */
28850 uint8_t host_a_index;
28851 /* Logical PF number. */
28852 uint8_t pf_a_index;
28853 /* Pair member a's Linux logical VF number. */
28854 uint16_t vf_a_index;
28856 uint16_t rx_cfa_code_a;
28857 /* Tx CFA action. */
28858 uint16_t tx_cfa_action_a;
28859 /* Pair member b's fid. */
28861 /* Logical host number. */
28862 uint8_t host_b_index;
28863 /* Logical PF number. */
28864 uint8_t pf_b_index;
28865 /* Pair member a's Linux logical VF number. */
28866 uint16_t vf_b_index;
28868 uint16_t rx_cfa_code_b;
28869 /* Tx CFA action. */
28870 uint16_t tx_cfa_action_b;
28871 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
28873 /* Pair between VF on local host with PF or VF on specified host. */
28874 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
28875 /* Pair between REP on local host with PF or VF on specified host. */
28876 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
28877 /* Pair between REP on local host with REP on specified host. */
28878 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
28879 /* Pair for the proxy interface. */
28880 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
28881 /* Pair for the PF interface. */
28882 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
28883 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
28884 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
28886 uint8_t pair_state;
28887 /* Pair has been allocated */
28888 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
28889 /* Both pair members are active */
28890 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
28891 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
28892 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
28893 /* Pair name (32 byte string). */
28894 char pair_name[32];
28895 uint8_t unused_0[7];
28897 * This field is used in Output records to indicate that the output
28898 * is completely written to RAM. This field should be read as '1'
28899 * to indicate that the output has been completely written.
28900 * When writing a command completion or response to an internal processor,
28901 * the order of writes has to be such that this field is written last.
28904 } __attribute__((packed));
28906 /***************************************
28907 * hwrm_cfa_redirect_query_tunnel_type *
28908 ***************************************/
28911 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
28912 struct hwrm_cfa_redirect_query_tunnel_type_input {
28913 /* The HWRM command request type. */
28916 * The completion ring to send the completion event on. This should
28917 * be the NQ ID returned from the `nq_alloc` HWRM command.
28919 uint16_t cmpl_ring;
28921 * The sequence ID is used by the driver for tracking multiple
28922 * commands. This ID is treated as opaque data by the firmware and
28923 * the value is returned in the `hwrm_resp_hdr` upon completion.
28927 * The target ID of the command:
28928 * * 0x0-0xFFF8 - The function ID
28929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28930 * * 0xFFFD - Reserved for user-space HWRM interface
28933 uint16_t target_id;
28935 * A physical address pointer pointing to a host buffer that the
28936 * command's response data will be written. This can be either a host
28937 * physical address (HPA) or a guest physical address (GPA) and must
28938 * point to a physically contiguous block of memory.
28940 uint64_t resp_addr;
28941 /* The source function id. */
28943 uint8_t unused_0[6];
28944 } __attribute__((packed));
28946 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
28947 struct hwrm_cfa_redirect_query_tunnel_type_output {
28948 /* The specific error status for the command. */
28949 uint16_t error_code;
28950 /* The HWRM command request type. */
28952 /* The sequence ID from the original command. */
28954 /* The length of the response data in number of bytes. */
28957 uint32_t tunnel_mask;
28959 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
28961 /* Virtual eXtensible Local Area Network (VXLAN) */
28962 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
28964 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28965 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
28967 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28968 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
28971 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
28973 /* Generic Network Virtualization Encapsulation (Geneve) */
28974 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
28976 /* Multi-Protocol Lable Switching (MPLS) */
28977 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
28979 /* Stateless Transport Tunnel (STT) */
28980 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
28982 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28983 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
28985 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28986 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
28988 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28989 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
28991 /* Any tunneled traffic */
28992 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
28994 /* Use fixed layer 2 ether type of 0xFFFF */
28995 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
28997 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28998 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
29000 uint8_t unused_0[3];
29002 * This field is used in Output records to indicate that the output
29003 * is completely written to RAM. This field should be read as '1'
29004 * to indicate that the output has been completely written.
29005 * When writing a command completion or response to an internal processor,
29006 * the order of writes has to be such that this field is written last.
29009 } __attribute__((packed));
29011 /*************************
29012 * hwrm_cfa_ctx_mem_rgtr *
29013 *************************/
29016 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
29017 struct hwrm_cfa_ctx_mem_rgtr_input {
29018 /* The HWRM command request type. */
29021 * The completion ring to send the completion event on. This should
29022 * be the NQ ID returned from the `nq_alloc` HWRM command.
29024 uint16_t cmpl_ring;
29026 * The sequence ID is used by the driver for tracking multiple
29027 * commands. This ID is treated as opaque data by the firmware and
29028 * the value is returned in the `hwrm_resp_hdr` upon completion.
29032 * The target ID of the command:
29033 * * 0x0-0xFFF8 - The function ID
29034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29035 * * 0xFFFD - Reserved for user-space HWRM interface
29038 uint16_t target_id;
29040 * A physical address pointer pointing to a host buffer that the
29041 * command's response data will be written. This can be either a host
29042 * physical address (HPA) or a guest physical address (GPA) and must
29043 * point to a physically contiguous block of memory.
29045 uint64_t resp_addr;
29047 /* Counter PBL indirect levels. */
29048 uint8_t page_level;
29049 /* PBL pointer is physical start address. */
29050 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29051 /* PBL pointer points to PTE table. */
29052 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29053 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29054 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29055 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
29056 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
29059 /* 4KB page size. */
29060 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
29061 /* 8KB page size. */
29062 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
29063 /* 64KB page size. */
29064 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
29065 /* 256KB page size. */
29066 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
29067 /* 1MB page size. */
29068 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
29069 /* 2MB page size. */
29070 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
29071 /* 4MB page size. */
29072 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
29073 /* 1GB page size. */
29074 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
29075 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
29076 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
29078 /* Pointer to the PBL, or PDL depending on number of levels */
29080 } __attribute__((packed));
29082 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
29083 struct hwrm_cfa_ctx_mem_rgtr_output {
29084 /* The specific error status for the command. */
29085 uint16_t error_code;
29086 /* The HWRM command request type. */
29088 /* The sequence ID from the original command. */
29090 /* The length of the response data in number of bytes. */
29093 * Id/Handle to the recently register context memory. This handle is passed
29094 * to the CFA feature.
29097 uint8_t unused_0[5];
29099 * This field is used in Output records to indicate that the output
29100 * is completely written to RAM. This field should be read as '1'
29101 * to indicate that the output has been completely written.
29102 * When writing a command completion or response to an internal processor,
29103 * the order of writes has to be such that this field is written last.
29106 } __attribute__((packed));
29108 /***************************
29109 * hwrm_cfa_ctx_mem_unrgtr *
29110 ***************************/
29113 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
29114 struct hwrm_cfa_ctx_mem_unrgtr_input {
29115 /* The HWRM command request type. */
29118 * The completion ring to send the completion event on. This should
29119 * be the NQ ID returned from the `nq_alloc` HWRM command.
29121 uint16_t cmpl_ring;
29123 * The sequence ID is used by the driver for tracking multiple
29124 * commands. This ID is treated as opaque data by the firmware and
29125 * the value is returned in the `hwrm_resp_hdr` upon completion.
29129 * The target ID of the command:
29130 * * 0x0-0xFFF8 - The function ID
29131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29132 * * 0xFFFD - Reserved for user-space HWRM interface
29135 uint16_t target_id;
29137 * A physical address pointer pointing to a host buffer that the
29138 * command's response data will be written. This can be either a host
29139 * physical address (HPA) or a guest physical address (GPA) and must
29140 * point to a physically contiguous block of memory.
29142 uint64_t resp_addr;
29144 * Id/Handle to the recently register context memory. This handle is passed
29145 * to the CFA feature.
29148 uint8_t unused_0[6];
29149 } __attribute__((packed));
29151 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
29152 struct hwrm_cfa_ctx_mem_unrgtr_output {
29153 /* The specific error status for the command. */
29154 uint16_t error_code;
29155 /* The HWRM command request type. */
29157 /* The sequence ID from the original command. */
29159 /* The length of the response data in number of bytes. */
29161 uint8_t unused_0[7];
29163 * This field is used in Output records to indicate that the output
29164 * is completely written to RAM. This field should be read as '1'
29165 * to indicate that the output has been completely written.
29166 * When writing a command completion or response to an internal processor,
29167 * the order of writes has to be such that this field is written last.
29170 } __attribute__((packed));
29172 /*************************
29173 * hwrm_cfa_ctx_mem_qctx *
29174 *************************/
29177 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
29178 struct hwrm_cfa_ctx_mem_qctx_input {
29179 /* The HWRM command request type. */
29182 * The completion ring to send the completion event on. This should
29183 * be the NQ ID returned from the `nq_alloc` HWRM command.
29185 uint16_t cmpl_ring;
29187 * The sequence ID is used by the driver for tracking multiple
29188 * commands. This ID is treated as opaque data by the firmware and
29189 * the value is returned in the `hwrm_resp_hdr` upon completion.
29193 * The target ID of the command:
29194 * * 0x0-0xFFF8 - The function ID
29195 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29196 * * 0xFFFD - Reserved for user-space HWRM interface
29199 uint16_t target_id;
29201 * A physical address pointer pointing to a host buffer that the
29202 * command's response data will be written. This can be either a host
29203 * physical address (HPA) or a guest physical address (GPA) and must
29204 * point to a physically contiguous block of memory.
29206 uint64_t resp_addr;
29208 * Id/Handle to the recently register context memory. This handle is passed
29209 * to the CFA feature.
29212 uint8_t unused_0[6];
29213 } __attribute__((packed));
29215 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
29216 struct hwrm_cfa_ctx_mem_qctx_output {
29217 /* The specific error status for the command. */
29218 uint16_t error_code;
29219 /* The HWRM command request type. */
29221 /* The sequence ID from the original command. */
29223 /* The length of the response data in number of bytes. */
29226 /* Counter PBL indirect levels. */
29227 uint8_t page_level;
29228 /* PBL pointer is physical start address. */
29229 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
29230 /* PBL pointer points to PTE table. */
29231 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
29232 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
29233 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
29234 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
29235 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
29238 /* 4KB page size. */
29239 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
29240 /* 8KB page size. */
29241 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
29242 /* 64KB page size. */
29243 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
29244 /* 256KB page size. */
29245 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
29246 /* 1MB page size. */
29247 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
29248 /* 2MB page size. */
29249 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
29250 /* 4MB page size. */
29251 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
29252 /* 1GB page size. */
29253 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
29254 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
29255 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
29256 uint8_t unused_0[4];
29257 /* Pointer to the PBL, or PDL depending on number of levels */
29259 uint8_t unused_1[7];
29261 * This field is used in Output records to indicate that the output
29262 * is completely written to RAM. This field should be read as '1'
29263 * to indicate that the output has been completely written.
29264 * When writing a command completion or response to an internal processor,
29265 * the order of writes has to be such that this field is written last.
29268 } __attribute__((packed));
29270 /**************************
29271 * hwrm_cfa_ctx_mem_qcaps *
29272 **************************/
29275 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
29276 struct hwrm_cfa_ctx_mem_qcaps_input {
29277 /* The HWRM command request type. */
29280 * The completion ring to send the completion event on. This should
29281 * be the NQ ID returned from the `nq_alloc` HWRM command.
29283 uint16_t cmpl_ring;
29285 * The sequence ID is used by the driver for tracking multiple
29286 * commands. This ID is treated as opaque data by the firmware and
29287 * the value is returned in the `hwrm_resp_hdr` upon completion.
29291 * The target ID of the command:
29292 * * 0x0-0xFFF8 - The function ID
29293 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29294 * * 0xFFFD - Reserved for user-space HWRM interface
29297 uint16_t target_id;
29299 * A physical address pointer pointing to a host buffer that the
29300 * command's response data will be written. This can be either a host
29301 * physical address (HPA) or a guest physical address (GPA) and must
29302 * point to a physically contiguous block of memory.
29304 uint64_t resp_addr;
29305 } __attribute__((packed));
29307 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
29308 struct hwrm_cfa_ctx_mem_qcaps_output {
29309 /* The specific error status for the command. */
29310 uint16_t error_code;
29311 /* The HWRM command request type. */
29313 /* The sequence ID from the original command. */
29315 /* The length of the response data in number of bytes. */
29317 /* Indicates the maximum number of context memory which can be registered. */
29318 uint16_t max_entries;
29319 uint8_t unused_0[6];
29320 } __attribute__((packed));
29322 /**********************
29323 * hwrm_cfa_eem_qcaps *
29324 **********************/
29327 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
29328 struct hwrm_cfa_eem_qcaps_input {
29329 /* The HWRM command request type. */
29332 * The completion ring to send the completion event on. This should
29333 * be the NQ ID returned from the `nq_alloc` HWRM command.
29335 uint16_t cmpl_ring;
29337 * The sequence ID is used by the driver for tracking multiple
29338 * commands. This ID is treated as opaque data by the firmware and
29339 * the value is returned in the `hwrm_resp_hdr` upon completion.
29343 * The target ID of the command:
29344 * * 0x0-0xFFF8 - The function ID
29345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29346 * * 0xFFFD - Reserved for user-space HWRM interface
29349 uint16_t target_id;
29351 * A physical address pointer pointing to a host buffer that the
29352 * command's response data will be written. This can be either a host
29353 * physical address (HPA) or a guest physical address (GPA) and must
29354 * point to a physically contiguous block of memory.
29356 uint64_t resp_addr;
29359 * When set to 1, indicates the configuration will apply to TX flows
29360 * which are to be offloaded.
29361 * Note if this bit is set then the path_rx bit can't be set.
29363 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
29366 * When set to 1, indicates the configuration will apply to RX flows
29367 * which are to be offloaded.
29368 * Note if this bit is set then the path_tx bit can't be set.
29370 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
29372 /* When set to 1, all offloaded flows will be sent to EEM. */
29373 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
29376 } __attribute__((packed));
29378 /* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
29379 struct hwrm_cfa_eem_qcaps_output {
29380 /* The specific error status for the command. */
29381 uint16_t error_code;
29382 /* The HWRM command request type. */
29384 /* The sequence ID from the original command. */
29386 /* The length of the response data in number of bytes. */
29390 * When set to 1, indicates the configuration will apply to TX flows
29391 * which are to be offloaded.
29392 * Note if this bit is set then the path_rx bit can't be set.
29394 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
29397 * When set to 1, indicates the configuration will apply to RX flows
29398 * which are to be offloaded.
29399 * Note if this bit is set then the path_tx bit can't be set.
29401 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
29404 * When set to 1, indicates the the FW supports the Centralized
29405 * Memory Model. The concept designates one entity for the
29406 * memory allocation while all others ‘subscribe’ to it.
29408 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
29411 * When set to 1, indicates the the FW supports the Detached
29412 * Centralized Memory Model. The memory is allocated and managed
29413 * as a separate entity. All PFs and VFs will be granted direct
29414 * or semi-direct access to the allocated memory while none of
29415 * which can interfere with the management of the memory.
29417 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
29420 uint32_t supported;
29422 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
29423 * If set to 0 EEM KEY0 table is not supported.
29425 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
29428 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
29429 * If set to 0 EEM KEY1 table is not supported.
29431 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
29434 * If set to 1, then EEM External Record table is supported.
29435 * If set to 0 EEM External Record table is not supported.
29436 * (This table includes action record, EFC pointers, encap pointers)
29438 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
29441 * If set to 1, then EEM External Flow Counters table is supported.
29442 * If set to 0 EEM External Flow Counters table is not supported.
29444 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
29447 * The maximum number of entries supported by EEM. When configuring the host memory
29448 * the number of numbers of entries that can supported are -
29449 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
29450 * Any value that are not these values, the FW will round down to the closest support
29451 * number of entries.
29453 uint32_t max_entries_supported;
29454 /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
29455 uint16_t key_entry_size;
29456 /* The entry size in bytes of each entry in the RECORD EEM tables. */
29457 uint16_t record_entry_size;
29458 /* The entry size in bytes of each entry in the EFC EEM tables. */
29459 uint16_t efc_entry_size;
29462 * This field is used in Output records to indicate that the output
29463 * is completely written to RAM. This field should be read as '1'
29464 * to indicate that the output has been completely written.
29465 * When writing a command completion or response to an internal processor,
29466 * the order of writes has to be such that this field is written last.
29469 } __attribute__((packed));
29471 /********************
29472 * hwrm_cfa_eem_cfg *
29473 ********************/
29476 /* hwrm_cfa_eem_cfg_input (size:320b/40B) */
29477 struct hwrm_cfa_eem_cfg_input {
29478 /* The HWRM command request type. */
29481 * The completion ring to send the completion event on. This should
29482 * be the NQ ID returned from the `nq_alloc` HWRM command.
29484 uint16_t cmpl_ring;
29486 * The sequence ID is used by the driver for tracking multiple
29487 * commands. This ID is treated as opaque data by the firmware and
29488 * the value is returned in the `hwrm_resp_hdr` upon completion.
29492 * The target ID of the command:
29493 * * 0x0-0xFFF8 - The function ID
29494 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29495 * * 0xFFFD - Reserved for user-space HWRM interface
29498 uint16_t target_id;
29500 * A physical address pointer pointing to a host buffer that the
29501 * command's response data will be written. This can be either a host
29502 * physical address (HPA) or a guest physical address (GPA) and must
29503 * point to a physically contiguous block of memory.
29505 uint64_t resp_addr;
29508 * When set to 1, indicates the configuration will apply to TX flows
29509 * which are to be offloaded.
29510 * Note if this bit is set then the path_rx bit can't be set.
29512 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
29515 * When set to 1, indicates the configuration will apply to RX flows
29516 * which are to be offloaded.
29517 * Note if this bit is set then the path_tx bit can't be set.
29519 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
29521 /* When set to 1, all offloaded flows will be sent to EEM. */
29522 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
29524 /* When set to 1, secondary, 0 means primary. */
29525 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
29528 * Group_id which used by Firmware to identify memory pools belonging
29529 * to certain group.
29534 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
29535 * RECORD, EFC all have the same number of entries and all tables will be configured
29536 * using this value. Current minimum value is 32k. Current maximum value is 128M.
29538 uint32_t num_entries;
29540 /* Configured EEM with the given context if for KEY0 table. */
29541 uint16_t key0_ctx_id;
29542 /* Configured EEM with the given context if for KEY1 table. */
29543 uint16_t key1_ctx_id;
29544 /* Configured EEM with the given context if for RECORD table. */
29545 uint16_t record_ctx_id;
29546 /* Configured EEM with the given context if for EFC table. */
29547 uint16_t efc_ctx_id;
29548 } __attribute__((packed));
29550 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
29551 struct hwrm_cfa_eem_cfg_output {
29552 /* The specific error status for the command. */
29553 uint16_t error_code;
29554 /* The HWRM command request type. */
29556 /* The sequence ID from the original command. */
29558 /* The length of the response data in number of bytes. */
29560 uint8_t unused_0[7];
29562 * This field is used in Output records to indicate that the output
29563 * is completely written to RAM. This field should be read as '1'
29564 * to indicate that the output has been completely written.
29565 * When writing a command completion or response to an internal processor,
29566 * the order of writes has to be such that this field is written last.
29569 } __attribute__((packed));
29571 /*********************
29572 * hwrm_cfa_eem_qcfg *
29573 *********************/
29576 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
29577 struct hwrm_cfa_eem_qcfg_input {
29578 /* The HWRM command request type. */
29581 * The completion ring to send the completion event on. This should
29582 * be the NQ ID returned from the `nq_alloc` HWRM command.
29584 uint16_t cmpl_ring;
29586 * The sequence ID is used by the driver for tracking multiple
29587 * commands. This ID is treated as opaque data by the firmware and
29588 * the value is returned in the `hwrm_resp_hdr` upon completion.
29592 * The target ID of the command:
29593 * * 0x0-0xFFF8 - The function ID
29594 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29595 * * 0xFFFD - Reserved for user-space HWRM interface
29598 uint16_t target_id;
29600 * A physical address pointer pointing to a host buffer that the
29601 * command's response data will be written. This can be either a host
29602 * physical address (HPA) or a guest physical address (GPA) and must
29603 * point to a physically contiguous block of memory.
29605 uint64_t resp_addr;
29607 /* When set to 1, indicates the configuration is the TX flow. */
29608 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
29609 /* When set to 1, indicates the configuration is the RX flow. */
29610 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
29612 } __attribute__((packed));
29614 /* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
29615 struct hwrm_cfa_eem_qcfg_output {
29616 /* The specific error status for the command. */
29617 uint16_t error_code;
29618 /* The HWRM command request type. */
29620 /* The sequence ID from the original command. */
29622 /* The length of the response data in number of bytes. */
29625 /* When set to 1, indicates the configuration is the TX flow. */
29626 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
29628 /* When set to 1, indicates the configuration is the RX flow. */
29629 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
29631 /* When set to 1, all offloaded flows will be sent to EEM. */
29632 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
29634 /* The number of entries the FW has configured for EEM. */
29635 uint32_t num_entries;
29636 uint8_t unused_0[7];
29638 * This field is used in Output records to indicate that the output
29639 * is completely written to RAM. This field should be read as '1'
29640 * to indicate that the output has been completely written.
29641 * When writing a command completion or response to an internal processor,
29642 * the order of writes has to be such that this field is written last.
29645 } __attribute__((packed));
29647 /*******************
29648 * hwrm_cfa_eem_op *
29649 *******************/
29652 /* hwrm_cfa_eem_op_input (size:192b/24B) */
29653 struct hwrm_cfa_eem_op_input {
29654 /* The HWRM command request type. */
29657 * The completion ring to send the completion event on. This should
29658 * be the NQ ID returned from the `nq_alloc` HWRM command.
29660 uint16_t cmpl_ring;
29662 * The sequence ID is used by the driver for tracking multiple
29663 * commands. This ID is treated as opaque data by the firmware and
29664 * the value is returned in the `hwrm_resp_hdr` upon completion.
29668 * The target ID of the command:
29669 * * 0x0-0xFFF8 - The function ID
29670 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29671 * * 0xFFFD - Reserved for user-space HWRM interface
29674 uint16_t target_id;
29676 * A physical address pointer pointing to a host buffer that the
29677 * command's response data will be written. This can be either a host
29678 * physical address (HPA) or a guest physical address (GPA) and must
29679 * point to a physically contiguous block of memory.
29681 uint64_t resp_addr;
29684 * When set to 1, indicates the host memory which is passed will be
29685 * used for the TX flow offload function specified in fid.
29686 * Note if this bit is set then the path_rx bit can't be set.
29688 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
29690 * When set to 1, indicates the host memory which is passed will be
29691 * used for the RX flow offload function specified in fid.
29692 * Note if this bit is set then the path_tx bit can't be set.
29694 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
29696 /* The number of EEM key table entries to be configured. */
29698 /* This value is reserved and should not be used. */
29699 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
29701 * To properly stop EEM and ensure there are no DMA's, the caller
29702 * must disable EEM for the given PF, using this call. This will
29703 * safely disable EEM and ensure that all DMA'ed to the
29704 * keys/records/efc have been completed.
29706 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
29708 * Once the EEM host memory has been configured, EEM options have
29709 * been configured. Then the caller should enable EEM for the given
29710 * PF. Note once this call has been made, then the EEM mechanism
29711 * will be active and DMA's will occur as packets are processed.
29713 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
29715 * Clear EEM settings for the given PF so that the register values
29716 * are reset back to there initial state.
29718 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
29719 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
29720 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
29721 } __attribute__((packed));
29723 /* hwrm_cfa_eem_op_output (size:128b/16B) */
29724 struct hwrm_cfa_eem_op_output {
29725 /* The specific error status for the command. */
29726 uint16_t error_code;
29727 /* The HWRM command request type. */
29729 /* The sequence ID from the original command. */
29731 /* The length of the response data in number of bytes. */
29733 uint8_t unused_0[7];
29735 * This field is used in Output records to indicate that the output
29736 * is completely written to RAM. This field should be read as '1'
29737 * to indicate that the output has been completely written.
29738 * When writing a command completion or response to an internal processor,
29739 * the order of writes has to be such that this field is written last.
29742 } __attribute__((packed));
29744 /********************************
29745 * hwrm_cfa_adv_flow_mgnt_qcaps *
29746 ********************************/
29749 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
29750 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
29751 /* The HWRM command request type. */
29754 * The completion ring to send the completion event on. This should
29755 * be the NQ ID returned from the `nq_alloc` HWRM command.
29757 uint16_t cmpl_ring;
29759 * The sequence ID is used by the driver for tracking multiple
29760 * commands. This ID is treated as opaque data by the firmware and
29761 * the value is returned in the `hwrm_resp_hdr` upon completion.
29765 * The target ID of the command:
29766 * * 0x0-0xFFF8 - The function ID
29767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29768 * * 0xFFFD - Reserved for user-space HWRM interface
29771 uint16_t target_id;
29773 * A physical address pointer pointing to a host buffer that the
29774 * command's response data will be written. This can be either a host
29775 * physical address (HPA) or a guest physical address (GPA) and must
29776 * point to a physically contiguous block of memory.
29778 uint64_t resp_addr;
29779 uint32_t unused_0[4];
29780 } __attribute__((packed));
29782 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
29783 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
29784 /* The specific error status for the command. */
29785 uint16_t error_code;
29786 /* The HWRM command request type. */
29788 /* The sequence ID from the original command. */
29790 /* The length of the response data in number of bytes. */
29794 * Value of 1 to indicate firmware support 16-bit flow handle.
29795 * Value of 0 to indicate firmware not support 16-bit flow handle.
29797 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
29800 * Value of 1 to indicate firmware support 64-bit flow handle.
29801 * Value of 0 to indicate firmware not support 64-bit flow handle.
29803 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
29806 * Value of 1 to indicate firmware support flow batch delete operation through
29807 * HWRM_CFA_FLOW_FLUSH command.
29808 * Value of 0 to indicate that the firmware does not support flow batch delete
29811 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
29814 * Value of 1 to indicate that the firmware support flow reset all operation through
29815 * HWRM_CFA_FLOW_FLUSH command.
29816 * Value of 0 indicates firmware does not support flow reset all operation.
29818 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
29821 * Value of 1 to indicate that firmware supports use of FID as dest_id in
29822 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
29823 * Value of 0 indicates firmware does not support use of FID as dest_id.
29825 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
29828 * Value of 1 to indicate that firmware supports TX EEM flows.
29829 * Value of 0 indicates firmware does not support TX EEM flows.
29831 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
29834 * Value of 1 to indicate that firmware supports RX EEM flows.
29835 * Value of 0 indicates firmware does not support RX EEM flows.
29837 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
29840 * Value of 1 to indicate that firmware supports the dynamic allocation of an
29841 * on-chip flow counter which can be used for EEM flows.
29842 * Value of 0 indicates firmware does not support the dynamic allocation of an
29843 * on-chip flow counter.
29845 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
29848 * Value of 1 to indicate that firmware supports setting of
29849 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
29850 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
29852 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
29855 * Value of 1 to indicate that firmware supports untagged matching
29856 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
29857 * indicates firmware does not support untagged matching.
29859 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
29862 * Value of 1 to indicate that firmware supports XDP filter. Value
29863 * of 0 indicates firmware does not support XDP filter.
29865 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
29868 * Value of 1 to indicate that the firmware support L2 header source
29869 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
29870 * Value of 0 indicates firmware does not support L2 header source
29873 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
29875 uint8_t unused_0[3];
29877 * This field is used in Output records to indicate that the output
29878 * is completely written to RAM. This field should be read as '1'
29879 * to indicate that the output has been completely written.
29880 * When writing a command completion or response to an internal processor,
29881 * the order of writes has to be such that this field is written last.
29884 } __attribute__((packed));
29886 /******************
29888 ******************/
29891 /* hwrm_cfa_tflib_input (size:1024b/128B) */
29892 struct hwrm_cfa_tflib_input {
29893 /* The HWRM command request type. */
29896 * The completion ring to send the completion event on. This should
29897 * be the NQ ID returned from the `nq_alloc` HWRM command.
29899 uint16_t cmpl_ring;
29901 * The sequence ID is used by the driver for tracking multiple
29902 * commands. This ID is treated as opaque data by the firmware and
29903 * the value is returned in the `hwrm_resp_hdr` upon completion.
29907 * The target ID of the command:
29908 * * 0x0-0xFFF8 - The function ID
29909 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29910 * * 0xFFFD - Reserved for user-space HWRM interface
29913 uint16_t target_id;
29915 * A physical address pointer pointing to a host buffer that the
29916 * command's response data will be written. This can be either a host
29917 * physical address (HPA) or a guest physical address (GPA) and must
29918 * point to a physically contiguous block of memory.
29920 uint64_t resp_addr;
29921 /* TFLIB message type. */
29923 /* TFLIB message subtype. */
29924 uint16_t tf_subtype;
29926 uint8_t unused0[4];
29927 /* TFLIB request data. */
29928 uint32_t tf_req[26];
29929 } __attribute__((packed));
29931 /* hwrm_cfa_tflib_output (size:5632b/704B) */
29932 struct hwrm_cfa_tflib_output {
29933 /* The specific error status for the command. */
29934 uint16_t error_code;
29935 /* The HWRM command request type. */
29937 /* The sequence ID from the original command. */
29939 /* The length of the response data in number of bytes. */
29941 /* TFLIB message type. */
29943 /* TFLIB message subtype. */
29944 uint16_t tf_subtype;
29945 /* TFLIB response code */
29946 uint32_t tf_resp_code;
29947 /* TFLIB response data. */
29948 uint32_t tf_resp[170];
29950 uint8_t unused1[7];
29952 * This field is used in Output records to indicate that the output
29953 * is completely written to RAM. This field should be read as '1'
29954 * to indicate that the output has been completely written.
29955 * When writing a command completion or response to an internal processor,
29956 * the order of writes has to be such that this field is written last.
29959 } __attribute__((packed));
29961 /******************************
29962 * hwrm_tunnel_dst_port_query *
29963 ******************************/
29966 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
29967 struct hwrm_tunnel_dst_port_query_input {
29968 /* The HWRM command request type. */
29971 * The completion ring to send the completion event on. This should
29972 * be the NQ ID returned from the `nq_alloc` HWRM command.
29974 uint16_t cmpl_ring;
29976 * The sequence ID is used by the driver for tracking multiple
29977 * commands. This ID is treated as opaque data by the firmware and
29978 * the value is returned in the `hwrm_resp_hdr` upon completion.
29982 * The target ID of the command:
29983 * * 0x0-0xFFF8 - The function ID
29984 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29985 * * 0xFFFD - Reserved for user-space HWRM interface
29988 uint16_t target_id;
29990 * A physical address pointer pointing to a host buffer that the
29991 * command's response data will be written. This can be either a host
29992 * physical address (HPA) or a guest physical address (GPA) and must
29993 * point to a physically contiguous block of memory.
29995 uint64_t resp_addr;
29997 uint8_t tunnel_type;
29998 /* Virtual eXtensible Local Area Network (VXLAN) */
29999 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
30001 /* Generic Network Virtualization Encapsulation (Geneve) */
30002 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
30004 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30005 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30007 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30008 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30010 /* Use fixed layer 2 ether type of 0xFFFF */
30011 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
30013 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30014 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30016 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
30017 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30018 uint8_t unused_0[7];
30019 } __attribute__((packed));
30021 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
30022 struct hwrm_tunnel_dst_port_query_output {
30023 /* The specific error status for the command. */
30024 uint16_t error_code;
30025 /* The HWRM command request type. */
30027 /* The sequence ID from the original command. */
30029 /* The length of the response data in number of bytes. */
30032 * This field represents the identifier of L4 destination port
30033 * used for the given tunnel type. This field is valid for
30034 * specific tunnel types that use layer 4 (e.g. UDP)
30035 * transports for tunneling.
30037 uint16_t tunnel_dst_port_id;
30039 * This field represents the value of L4 destination port
30040 * identified by tunnel_dst_port_id. This field is valid for
30041 * specific tunnel types that use layer 4 (e.g. UDP)
30042 * transports for tunneling.
30043 * This field is in network byte order.
30045 * A value of 0 means that the destination port is not
30048 uint16_t tunnel_dst_port_val;
30049 uint8_t unused_0[3];
30051 * This field is used in Output records to indicate that the output
30052 * is completely written to RAM. This field should be read as '1'
30053 * to indicate that the output has been completely written.
30054 * When writing a command completion or response to an internal processor,
30055 * the order of writes has to be such that this field is written last.
30058 } __attribute__((packed));
30060 /******************************
30061 * hwrm_tunnel_dst_port_alloc *
30062 ******************************/
30065 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
30066 struct hwrm_tunnel_dst_port_alloc_input {
30067 /* The HWRM command request type. */
30070 * The completion ring to send the completion event on. This should
30071 * be the NQ ID returned from the `nq_alloc` HWRM command.
30073 uint16_t cmpl_ring;
30075 * The sequence ID is used by the driver for tracking multiple
30076 * commands. This ID is treated as opaque data by the firmware and
30077 * the value is returned in the `hwrm_resp_hdr` upon completion.
30081 * The target ID of the command:
30082 * * 0x0-0xFFF8 - The function ID
30083 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30084 * * 0xFFFD - Reserved for user-space HWRM interface
30087 uint16_t target_id;
30089 * A physical address pointer pointing to a host buffer that the
30090 * command's response data will be written. This can be either a host
30091 * physical address (HPA) or a guest physical address (GPA) and must
30092 * point to a physically contiguous block of memory.
30094 uint64_t resp_addr;
30096 uint8_t tunnel_type;
30097 /* Virtual eXtensible Local Area Network (VXLAN) */
30098 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30100 /* Generic Network Virtualization Encapsulation (Geneve) */
30101 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30103 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30104 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30106 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30107 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30109 /* Use fixed layer 2 ether type of 0xFFFF */
30110 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30112 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30113 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30115 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30116 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30119 * This field represents the value of L4 destination port used
30120 * for the given tunnel type. This field is valid for
30121 * specific tunnel types that use layer 4 (e.g. UDP)
30122 * transports for tunneling.
30124 * This field is in network byte order.
30126 * A value of 0 shall fail the command.
30128 uint16_t tunnel_dst_port_val;
30129 uint8_t unused_1[4];
30130 } __attribute__((packed));
30132 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
30133 struct hwrm_tunnel_dst_port_alloc_output {
30134 /* The specific error status for the command. */
30135 uint16_t error_code;
30136 /* The HWRM command request type. */
30138 /* The sequence ID from the original command. */
30140 /* The length of the response data in number of bytes. */
30143 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
30144 * types that has l4 destination port parameters.
30146 uint16_t tunnel_dst_port_id;
30147 uint8_t unused_0[5];
30149 * This field is used in Output records to indicate that the output
30150 * is completely written to RAM. This field should be read as '1'
30151 * to indicate that the output has been completely written.
30152 * When writing a command completion or response to an internal processor,
30153 * the order of writes has to be such that this field is written last.
30156 } __attribute__((packed));
30158 /*****************************
30159 * hwrm_tunnel_dst_port_free *
30160 *****************************/
30163 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
30164 struct hwrm_tunnel_dst_port_free_input {
30165 /* The HWRM command request type. */
30168 * The completion ring to send the completion event on. This should
30169 * be the NQ ID returned from the `nq_alloc` HWRM command.
30171 uint16_t cmpl_ring;
30173 * The sequence ID is used by the driver for tracking multiple
30174 * commands. This ID is treated as opaque data by the firmware and
30175 * the value is returned in the `hwrm_resp_hdr` upon completion.
30179 * The target ID of the command:
30180 * * 0x0-0xFFF8 - The function ID
30181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30182 * * 0xFFFD - Reserved for user-space HWRM interface
30185 uint16_t target_id;
30187 * A physical address pointer pointing to a host buffer that the
30188 * command's response data will be written. This can be either a host
30189 * physical address (HPA) or a guest physical address (GPA) and must
30190 * point to a physically contiguous block of memory.
30192 uint64_t resp_addr;
30194 uint8_t tunnel_type;
30195 /* Virtual eXtensible Local Area Network (VXLAN) */
30196 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
30198 /* Generic Network Virtualization Encapsulation (Geneve) */
30199 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
30201 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30202 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30204 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30205 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30207 /* Use fixed layer 2 ether type of 0xFFFF */
30208 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
30210 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30211 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30213 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
30214 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
30217 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
30218 * types that has l4 destination port parameters.
30220 uint16_t tunnel_dst_port_id;
30221 uint8_t unused_1[4];
30222 } __attribute__((packed));
30224 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
30225 struct hwrm_tunnel_dst_port_free_output {
30226 /* The specific error status for the command. */
30227 uint16_t error_code;
30228 /* The HWRM command request type. */
30230 /* The sequence ID from the original command. */
30232 /* The length of the response data in number of bytes. */
30234 uint8_t unused_1[7];
30236 * This field is used in Output records to indicate that the output
30237 * is completely written to RAM. This field should be read as '1'
30238 * to indicate that the output has been completely written.
30239 * When writing a command completion or response to an internal processor,
30240 * the order of writes has to be such that this field is written last.
30243 } __attribute__((packed));
30245 /* Periodic statistics context DMA to host. */
30246 /* ctx_hw_stats (size:1280b/160B) */
30247 struct ctx_hw_stats {
30248 /* Number of received unicast packets */
30249 uint64_t rx_ucast_pkts;
30250 /* Number of received multicast packets */
30251 uint64_t rx_mcast_pkts;
30252 /* Number of received broadcast packets */
30253 uint64_t rx_bcast_pkts;
30254 /* Number of discarded packets on received path */
30255 uint64_t rx_discard_pkts;
30256 /* Number of dropped packets on received path */
30257 uint64_t rx_drop_pkts;
30258 /* Number of received bytes for unicast traffic */
30259 uint64_t rx_ucast_bytes;
30260 /* Number of received bytes for multicast traffic */
30261 uint64_t rx_mcast_bytes;
30262 /* Number of received bytes for broadcast traffic */
30263 uint64_t rx_bcast_bytes;
30264 /* Number of transmitted unicast packets */
30265 uint64_t tx_ucast_pkts;
30266 /* Number of transmitted multicast packets */
30267 uint64_t tx_mcast_pkts;
30268 /* Number of transmitted broadcast packets */
30269 uint64_t tx_bcast_pkts;
30270 /* Number of discarded packets on transmit path */
30271 uint64_t tx_discard_pkts;
30272 /* Number of dropped packets on transmit path */
30273 uint64_t tx_drop_pkts;
30274 /* Number of transmitted bytes for unicast traffic */
30275 uint64_t tx_ucast_bytes;
30276 /* Number of transmitted bytes for multicast traffic */
30277 uint64_t tx_mcast_bytes;
30278 /* Number of transmitted bytes for broadcast traffic */
30279 uint64_t tx_bcast_bytes;
30280 /* Number of TPA packets */
30282 /* Number of TPA bytes */
30283 uint64_t tpa_bytes;
30284 /* Number of TPA events */
30285 uint64_t tpa_events;
30286 /* Number of TPA aborts */
30287 uint64_t tpa_aborts;
30288 } __attribute__((packed));
30290 /* Periodic Engine statistics context DMA to host. */
30291 /* ctx_eng_stats (size:512b/64B) */
30292 struct ctx_eng_stats {
30294 * Count of data bytes into the Engine.
30295 * This includes any user supplied prefix,
30296 * but does not include any predefined
30299 uint64_t eng_bytes_in;
30300 /* Count of data bytes out of the Engine. */
30301 uint64_t eng_bytes_out;
30303 * Count, in 4-byte (dword) units, of bytes
30304 * that are input as auxiliary data.
30305 * This includes the aux_cmd data.
30307 uint64_t aux_bytes_in;
30309 * Count, in 4-byte (dword) units, of bytes
30310 * that are output as auxiliary data.
30311 * This count is the buffer space for aux_data
30312 * output provided in the RQE, not the actual
30315 uint64_t aux_bytes_out;
30316 /* Count of number of commands executed. */
30319 * Count of number of error commands.
30320 * These are the commands with a
30321 * non-zero status value.
30323 uint64_t error_commands;
30325 * Compression/Encryption Engine usage,
30326 * the unit is count of clock cycles
30328 uint64_t cce_engine_usage;
30330 * De-Compression/De-cryption Engine usage,
30331 * the unit is count of clock cycles
30333 uint64_t cdd_engine_usage;
30334 } __attribute__((packed));
30336 /***********************
30337 * hwrm_stat_ctx_alloc *
30338 ***********************/
30341 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
30342 struct hwrm_stat_ctx_alloc_input {
30343 /* The HWRM command request type. */
30346 * The completion ring to send the completion event on. This should
30347 * be the NQ ID returned from the `nq_alloc` HWRM command.
30349 uint16_t cmpl_ring;
30351 * The sequence ID is used by the driver for tracking multiple
30352 * commands. This ID is treated as opaque data by the firmware and
30353 * the value is returned in the `hwrm_resp_hdr` upon completion.
30357 * The target ID of the command:
30358 * * 0x0-0xFFF8 - The function ID
30359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30360 * * 0xFFFD - Reserved for user-space HWRM interface
30363 uint16_t target_id;
30365 * A physical address pointer pointing to a host buffer that the
30366 * command's response data will be written. This can be either a host
30367 * physical address (HPA) or a guest physical address (GPA) and must
30368 * point to a physically contiguous block of memory.
30370 uint64_t resp_addr;
30372 * This is the address for statistic block.
30373 * > For new versions of the chip, this address should be 128B
30376 uint64_t stats_dma_addr;
30378 * The statistic block update period in ms.
30379 * e.g. 250ms, 500ms, 750ms, 1000ms.
30380 * If update_period_ms is 0, then the stats update
30381 * shall be never done and the DMA address shall not be used.
30382 * In this case, the stat block can only be read by
30383 * hwrm_stat_ctx_query command.
30385 uint32_t update_period_ms;
30387 * This field is used to specify statistics context specific
30388 * configuration flags.
30390 uint8_t stat_ctx_flags;
30392 * When this bit is set to '1', the statistics context shall be
30393 * allocated for RoCE traffic only. In this case, traffic other
30394 * than offloaded RoCE traffic shall not be included in this
30395 * statistic context.
30396 * When this bit is set to '0', the statistics context shall be
30397 * used for network traffic or engine traffic.
30399 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
30400 uint8_t unused_0[3];
30401 } __attribute__((packed));
30403 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
30404 struct hwrm_stat_ctx_alloc_output {
30405 /* The specific error status for the command. */
30406 uint16_t error_code;
30407 /* The HWRM command request type. */
30409 /* The sequence ID from the original command. */
30411 /* The length of the response data in number of bytes. */
30413 /* This is the statistics context ID value. */
30414 uint32_t stat_ctx_id;
30415 uint8_t unused_0[3];
30417 * This field is used in Output records to indicate that the output
30418 * is completely written to RAM. This field should be read as '1'
30419 * to indicate that the output has been completely written.
30420 * When writing a command completion or response to an internal processor,
30421 * the order of writes has to be such that this field is written last.
30424 } __attribute__((packed));
30426 /**********************
30427 * hwrm_stat_ctx_free *
30428 **********************/
30431 /* hwrm_stat_ctx_free_input (size:192b/24B) */
30432 struct hwrm_stat_ctx_free_input {
30433 /* The HWRM command request type. */
30436 * The completion ring to send the completion event on. This should
30437 * be the NQ ID returned from the `nq_alloc` HWRM command.
30439 uint16_t cmpl_ring;
30441 * The sequence ID is used by the driver for tracking multiple
30442 * commands. This ID is treated as opaque data by the firmware and
30443 * the value is returned in the `hwrm_resp_hdr` upon completion.
30447 * The target ID of the command:
30448 * * 0x0-0xFFF8 - The function ID
30449 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30450 * * 0xFFFD - Reserved for user-space HWRM interface
30453 uint16_t target_id;
30455 * A physical address pointer pointing to a host buffer that the
30456 * command's response data will be written. This can be either a host
30457 * physical address (HPA) or a guest physical address (GPA) and must
30458 * point to a physically contiguous block of memory.
30460 uint64_t resp_addr;
30461 /* ID of the statistics context that is being queried. */
30462 uint32_t stat_ctx_id;
30463 uint8_t unused_0[4];
30464 } __attribute__((packed));
30466 /* hwrm_stat_ctx_free_output (size:128b/16B) */
30467 struct hwrm_stat_ctx_free_output {
30468 /* The specific error status for the command. */
30469 uint16_t error_code;
30470 /* The HWRM command request type. */
30472 /* The sequence ID from the original command. */
30474 /* The length of the response data in number of bytes. */
30476 /* This is the statistics context ID value. */
30477 uint32_t stat_ctx_id;
30478 uint8_t unused_0[3];
30480 * This field is used in Output records to indicate that the output
30481 * is completely written to RAM. This field should be read as '1'
30482 * to indicate that the output has been completely written.
30483 * When writing a command completion or response to an internal processor,
30484 * the order of writes has to be such that this field is written last.
30487 } __attribute__((packed));
30489 /***********************
30490 * hwrm_stat_ctx_query *
30491 ***********************/
30494 /* hwrm_stat_ctx_query_input (size:192b/24B) */
30495 struct hwrm_stat_ctx_query_input {
30496 /* The HWRM command request type. */
30499 * The completion ring to send the completion event on. This should
30500 * be the NQ ID returned from the `nq_alloc` HWRM command.
30502 uint16_t cmpl_ring;
30504 * The sequence ID is used by the driver for tracking multiple
30505 * commands. This ID is treated as opaque data by the firmware and
30506 * the value is returned in the `hwrm_resp_hdr` upon completion.
30510 * The target ID of the command:
30511 * * 0x0-0xFFF8 - The function ID
30512 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30513 * * 0xFFFD - Reserved for user-space HWRM interface
30516 uint16_t target_id;
30518 * A physical address pointer pointing to a host buffer that the
30519 * command's response data will be written. This can be either a host
30520 * physical address (HPA) or a guest physical address (GPA) and must
30521 * point to a physically contiguous block of memory.
30523 uint64_t resp_addr;
30524 /* ID of the statistics context that is being queried. */
30525 uint32_t stat_ctx_id;
30526 uint8_t unused_0[4];
30527 } __attribute__((packed));
30529 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
30530 struct hwrm_stat_ctx_query_output {
30531 /* The specific error status for the command. */
30532 uint16_t error_code;
30533 /* The HWRM command request type. */
30535 /* The sequence ID from the original command. */
30537 /* The length of the response data in number of bytes. */
30539 /* Number of transmitted unicast packets */
30540 uint64_t tx_ucast_pkts;
30541 /* Number of transmitted multicast packets */
30542 uint64_t tx_mcast_pkts;
30543 /* Number of transmitted broadcast packets */
30544 uint64_t tx_bcast_pkts;
30545 /* Number of transmitted packets with error */
30546 uint64_t tx_err_pkts;
30547 /* Number of dropped packets on transmit path */
30548 uint64_t tx_drop_pkts;
30549 /* Number of transmitted bytes for unicast traffic */
30550 uint64_t tx_ucast_bytes;
30551 /* Number of transmitted bytes for multicast traffic */
30552 uint64_t tx_mcast_bytes;
30553 /* Number of transmitted bytes for broadcast traffic */
30554 uint64_t tx_bcast_bytes;
30555 /* Number of received unicast packets */
30556 uint64_t rx_ucast_pkts;
30557 /* Number of received multicast packets */
30558 uint64_t rx_mcast_pkts;
30559 /* Number of received broadcast packets */
30560 uint64_t rx_bcast_pkts;
30561 /* Number of received packets with error */
30562 uint64_t rx_err_pkts;
30563 /* Number of dropped packets on received path */
30564 uint64_t rx_drop_pkts;
30565 /* Number of received bytes for unicast traffic */
30566 uint64_t rx_ucast_bytes;
30567 /* Number of received bytes for multicast traffic */
30568 uint64_t rx_mcast_bytes;
30569 /* Number of received bytes for broadcast traffic */
30570 uint64_t rx_bcast_bytes;
30571 /* Number of aggregated unicast packets */
30572 uint64_t rx_agg_pkts;
30573 /* Number of aggregated unicast bytes */
30574 uint64_t rx_agg_bytes;
30575 /* Number of aggregation events */
30576 uint64_t rx_agg_events;
30577 /* Number of aborted aggregations */
30578 uint64_t rx_agg_aborts;
30579 uint8_t unused_0[7];
30581 * This field is used in Output records to indicate that the output
30582 * is completely written to RAM. This field should be read as '1'
30583 * to indicate that the output has been completely written.
30584 * When writing a command completion or response to an internal processor,
30585 * the order of writes has to be such that this field is written last.
30588 } __attribute__((packed));
30590 /***************************
30591 * hwrm_stat_ctx_eng_query *
30592 ***************************/
30595 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
30596 struct hwrm_stat_ctx_eng_query_input {
30597 /* The HWRM command request type. */
30600 * The completion ring to send the completion event on. This should
30601 * be the NQ ID returned from the `nq_alloc` HWRM command.
30603 uint16_t cmpl_ring;
30605 * The sequence ID is used by the driver for tracking multiple
30606 * commands. This ID is treated as opaque data by the firmware and
30607 * the value is returned in the `hwrm_resp_hdr` upon completion.
30611 * The target ID of the command:
30612 * * 0x0-0xFFF8 - The function ID
30613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30614 * * 0xFFFD - Reserved for user-space HWRM interface
30617 uint16_t target_id;
30619 * A physical address pointer pointing to a host buffer that the
30620 * command's response data will be written. This can be either a host
30621 * physical address (HPA) or a guest physical address (GPA) and must
30622 * point to a physically contiguous block of memory.
30624 uint64_t resp_addr;
30625 /* ID of the statistics context that is being queried. */
30626 uint32_t stat_ctx_id;
30627 uint8_t unused_0[4];
30628 } __attribute__((packed));
30630 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
30631 struct hwrm_stat_ctx_eng_query_output {
30632 /* The specific error status for the command. */
30633 uint16_t error_code;
30634 /* The HWRM command request type. */
30636 /* The sequence ID from the original command. */
30638 /* The length of the response data in number of bytes. */
30641 * Count of data bytes into the Engine.
30642 * This includes any user supplied prefix,
30643 * but does not include any predefined
30646 uint64_t eng_bytes_in;
30647 /* Count of data bytes out of the Engine. */
30648 uint64_t eng_bytes_out;
30650 * Count, in 4-byte (dword) units, of bytes
30651 * that are input as auxiliary data.
30652 * This includes the aux_cmd data.
30654 uint64_t aux_bytes_in;
30656 * Count, in 4-byte (dword) units, of bytes
30657 * that are output as auxiliary data.
30658 * This count is the buffer space for aux_data
30659 * output provided in the RQE, not the actual
30662 uint64_t aux_bytes_out;
30663 /* Count of number of commands executed. */
30666 * Count of number of error commands.
30667 * These are the commands with a
30668 * non-zero status value.
30670 uint64_t error_commands;
30672 * Compression/Encryption Engine usage,
30673 * the unit is count of clock cycles
30675 uint64_t cce_engine_usage;
30677 * De-Compression/De-cryption Engine usage,
30678 * the unit is count of clock cycles
30680 uint64_t cdd_engine_usage;
30681 uint8_t unused_0[7];
30683 * This field is used in Output records to indicate that the output
30684 * is completely written to RAM. This field should be read as '1'
30685 * to indicate that the output has been completely written.
30686 * When writing a command completion or response to an internal processor,
30687 * the order of writes has to be such that this field is written last.
30690 } __attribute__((packed));
30692 /***************************
30693 * hwrm_stat_ctx_clr_stats *
30694 ***************************/
30697 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
30698 struct hwrm_stat_ctx_clr_stats_input {
30699 /* The HWRM command request type. */
30702 * The completion ring to send the completion event on. This should
30703 * be the NQ ID returned from the `nq_alloc` HWRM command.
30705 uint16_t cmpl_ring;
30707 * The sequence ID is used by the driver for tracking multiple
30708 * commands. This ID is treated as opaque data by the firmware and
30709 * the value is returned in the `hwrm_resp_hdr` upon completion.
30713 * The target ID of the command:
30714 * * 0x0-0xFFF8 - The function ID
30715 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30716 * * 0xFFFD - Reserved for user-space HWRM interface
30719 uint16_t target_id;
30721 * A physical address pointer pointing to a host buffer that the
30722 * command's response data will be written. This can be either a host
30723 * physical address (HPA) or a guest physical address (GPA) and must
30724 * point to a physically contiguous block of memory.
30726 uint64_t resp_addr;
30727 /* ID of the statistics context that is being queried. */
30728 uint32_t stat_ctx_id;
30729 uint8_t unused_0[4];
30730 } __attribute__((packed));
30732 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
30733 struct hwrm_stat_ctx_clr_stats_output {
30734 /* The specific error status for the command. */
30735 uint16_t error_code;
30736 /* The HWRM command request type. */
30738 /* The sequence ID from the original command. */
30740 /* The length of the response data in number of bytes. */
30742 uint8_t unused_0[7];
30744 * This field is used in Output records to indicate that the output
30745 * is completely written to RAM. This field should be read as '1'
30746 * to indicate that the output has been completely written.
30747 * When writing a command completion or response to an internal processor,
30748 * the order of writes has to be such that this field is written last.
30751 } __attribute__((packed));
30753 /********************
30754 * hwrm_pcie_qstats *
30755 ********************/
30758 /* hwrm_pcie_qstats_input (size:256b/32B) */
30759 struct hwrm_pcie_qstats_input {
30760 /* The HWRM command request type. */
30763 * The completion ring to send the completion event on. This should
30764 * be the NQ ID returned from the `nq_alloc` HWRM command.
30766 uint16_t cmpl_ring;
30768 * The sequence ID is used by the driver for tracking multiple
30769 * commands. This ID is treated as opaque data by the firmware and
30770 * the value is returned in the `hwrm_resp_hdr` upon completion.
30774 * The target ID of the command:
30775 * * 0x0-0xFFF8 - The function ID
30776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30777 * * 0xFFFD - Reserved for user-space HWRM interface
30780 uint16_t target_id;
30782 * A physical address pointer pointing to a host buffer that the
30783 * command's response data will be written. This can be either a host
30784 * physical address (HPA) or a guest physical address (GPA) and must
30785 * point to a physically contiguous block of memory.
30787 uint64_t resp_addr;
30789 * The size of PCIe statistics block in bytes.
30790 * Firmware will DMA the PCIe statistics to
30791 * the host with this field size in the response.
30793 uint16_t pcie_stat_size;
30794 uint8_t unused_0[6];
30796 * This is the host address where
30797 * PCIe statistics will be stored
30799 uint64_t pcie_stat_host_addr;
30800 } __attribute__((packed));
30802 /* hwrm_pcie_qstats_output (size:128b/16B) */
30803 struct hwrm_pcie_qstats_output {
30804 /* The specific error status for the command. */
30805 uint16_t error_code;
30806 /* The HWRM command request type. */
30808 /* The sequence ID from the original command. */
30810 /* The length of the response data in number of bytes. */
30812 /* The size of PCIe statistics block in bytes. */
30813 uint16_t pcie_stat_size;
30814 uint8_t unused_0[5];
30816 * This field is used in Output records to indicate that the output
30817 * is completely written to RAM. This field should be read as '1'
30818 * to indicate that the output has been completely written.
30819 * When writing a command completion or response to an internal processor,
30820 * the order of writes has to be such that this field is written last.
30823 } __attribute__((packed));
30825 /* PCIe Statistics Formats */
30826 /* pcie_ctx_hw_stats (size:768b/96B) */
30827 struct pcie_ctx_hw_stats {
30828 /* Number of physical layer receiver errors */
30829 uint64_t pcie_pl_signal_integrity;
30830 /* Number of DLLP CRC errors detected by Data Link Layer */
30831 uint64_t pcie_dl_signal_integrity;
30833 * Number of TLP LCRC and sequence number errors detected
30834 * by Data Link Layer
30836 uint64_t pcie_tl_signal_integrity;
30837 /* Number of times LTSSM entered Recovery state */
30838 uint64_t pcie_link_integrity;
30839 /* Number of TLP bytes that have been trasmitted */
30840 uint64_t pcie_tx_traffic_rate;
30841 /* Number of TLP bytes that have been received */
30842 uint64_t pcie_rx_traffic_rate;
30843 /* Number of DLLP bytes that have been trasmitted */
30844 uint64_t pcie_tx_dllp_statistics;
30845 /* Number of DLLP bytes that have been received */
30846 uint64_t pcie_rx_dllp_statistics;
30848 * Number of times spent in each phase of gen3
30851 uint64_t pcie_equalization_time;
30852 /* Records the last 16 transitions of the LTSSM */
30853 uint32_t pcie_ltssm_histogram[4];
30855 * Record the last 8 reasons on why LTSSM transitioned
30858 uint64_t pcie_recovery_histogram;
30859 } __attribute__((packed));
30861 /**********************
30862 * hwrm_exec_fwd_resp *
30863 **********************/
30866 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
30867 struct hwrm_exec_fwd_resp_input {
30868 /* The HWRM command request type. */
30871 * The completion ring to send the completion event on. This should
30872 * be the NQ ID returned from the `nq_alloc` HWRM command.
30874 uint16_t cmpl_ring;
30876 * The sequence ID is used by the driver for tracking multiple
30877 * commands. This ID is treated as opaque data by the firmware and
30878 * the value is returned in the `hwrm_resp_hdr` upon completion.
30882 * The target ID of the command:
30883 * * 0x0-0xFFF8 - The function ID
30884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30885 * * 0xFFFD - Reserved for user-space HWRM interface
30888 uint16_t target_id;
30890 * A physical address pointer pointing to a host buffer that the
30891 * command's response data will be written. This can be either a host
30892 * physical address (HPA) or a guest physical address (GPA) and must
30893 * point to a physically contiguous block of memory.
30895 uint64_t resp_addr;
30897 * This is an encapsulated request. This request should
30898 * be executed by the HWRM and the response should be
30899 * provided in the response buffer inside the encapsulated
30902 uint32_t encap_request[26];
30904 * This value indicates the target id of the response to
30905 * the encapsulated request.
30906 * 0x0 - 0xFFF8 - Used for function ids
30907 * 0xFFF8 - 0xFFFE - Reserved for internal processors
30910 uint16_t encap_resp_target_id;
30911 uint8_t unused_0[6];
30912 } __attribute__((packed));
30914 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
30915 struct hwrm_exec_fwd_resp_output {
30916 /* The specific error status for the command. */
30917 uint16_t error_code;
30918 /* The HWRM command request type. */
30920 /* The sequence ID from the original command. */
30922 /* The length of the response data in number of bytes. */
30924 uint8_t unused_0[7];
30926 * This field is used in Output records to indicate that the output
30927 * is completely written to RAM. This field should be read as '1'
30928 * to indicate that the output has been completely written.
30929 * When writing a command completion or response to an internal processor,
30930 * the order of writes has to be such that this field is written last.
30933 } __attribute__((packed));
30935 /************************
30936 * hwrm_reject_fwd_resp *
30937 ************************/
30940 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
30941 struct hwrm_reject_fwd_resp_input {
30942 /* The HWRM command request type. */
30945 * The completion ring to send the completion event on. This should
30946 * be the NQ ID returned from the `nq_alloc` HWRM command.
30948 uint16_t cmpl_ring;
30950 * The sequence ID is used by the driver for tracking multiple
30951 * commands. This ID is treated as opaque data by the firmware and
30952 * the value is returned in the `hwrm_resp_hdr` upon completion.
30956 * The target ID of the command:
30957 * * 0x0-0xFFF8 - The function ID
30958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30959 * * 0xFFFD - Reserved for user-space HWRM interface
30962 uint16_t target_id;
30964 * A physical address pointer pointing to a host buffer that the
30965 * command's response data will be written. This can be either a host
30966 * physical address (HPA) or a guest physical address (GPA) and must
30967 * point to a physically contiguous block of memory.
30969 uint64_t resp_addr;
30971 * This is an encapsulated request. This request should
30972 * be rejected by the HWRM and the error response should be
30973 * provided in the response buffer inside the encapsulated
30976 uint32_t encap_request[26];
30978 * This value indicates the target id of the response to
30979 * the encapsulated request.
30980 * 0x0 - 0xFFF8 - Used for function ids
30981 * 0xFFF8 - 0xFFFE - Reserved for internal processors
30984 uint16_t encap_resp_target_id;
30985 uint8_t unused_0[6];
30986 } __attribute__((packed));
30988 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
30989 struct hwrm_reject_fwd_resp_output {
30990 /* The specific error status for the command. */
30991 uint16_t error_code;
30992 /* The HWRM command request type. */
30994 /* The sequence ID from the original command. */
30996 /* The length of the response data in number of bytes. */
30998 uint8_t unused_0[7];
31000 * This field is used in Output records to indicate that the output
31001 * is completely written to RAM. This field should be read as '1'
31002 * to indicate that the output has been completely written.
31003 * When writing a command completion or response to an internal processor,
31004 * the order of writes has to be such that this field is written last.
31007 } __attribute__((packed));
31014 /* hwrm_fwd_resp_input (size:1024b/128B) */
31015 struct hwrm_fwd_resp_input {
31016 /* The HWRM command request type. */
31019 * The completion ring to send the completion event on. This should
31020 * be the NQ ID returned from the `nq_alloc` HWRM command.
31022 uint16_t cmpl_ring;
31024 * The sequence ID is used by the driver for tracking multiple
31025 * commands. This ID is treated as opaque data by the firmware and
31026 * the value is returned in the `hwrm_resp_hdr` upon completion.
31030 * The target ID of the command:
31031 * * 0x0-0xFFF8 - The function ID
31032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31033 * * 0xFFFD - Reserved for user-space HWRM interface
31036 uint16_t target_id;
31038 * A physical address pointer pointing to a host buffer that the
31039 * command's response data will be written. This can be either a host
31040 * physical address (HPA) or a guest physical address (GPA) and must
31041 * point to a physically contiguous block of memory.
31043 uint64_t resp_addr;
31045 * This value indicates the target id of the encapsulated
31047 * 0x0 - 0xFFF8 - Used for function ids
31048 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31051 uint16_t encap_resp_target_id;
31053 * This value indicates the completion ring the encapsulated
31054 * response will be optionally completed on. If the value is
31055 * -1, then no CR completion shall be generated for the
31056 * encapsulated response. Any other value must be a
31057 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
31058 * is provided, then a CR completion shall be generated for
31059 * the encapsulated response.
31061 uint16_t encap_resp_cmpl_ring;
31062 /* This field indicates the length of encapsulated response. */
31063 uint16_t encap_resp_len;
31067 * This is the host address where the encapsulated response
31069 * This area must be 16B aligned and must be cleared to zero
31070 * before the original request is made.
31072 uint64_t encap_resp_addr;
31073 /* This is an encapsulated response. */
31074 uint32_t encap_resp[24];
31075 } __attribute__((packed));
31077 /* hwrm_fwd_resp_output (size:128b/16B) */
31078 struct hwrm_fwd_resp_output {
31079 /* The specific error status for the command. */
31080 uint16_t error_code;
31081 /* The HWRM command request type. */
31083 /* The sequence ID from the original command. */
31085 /* The length of the response data in number of bytes. */
31087 uint8_t unused_0[7];
31089 * This field is used in Output records to indicate that the output
31090 * is completely written to RAM. This field should be read as '1'
31091 * to indicate that the output has been completely written.
31092 * When writing a command completion or response to an internal processor,
31093 * the order of writes has to be such that this field is written last.
31096 } __attribute__((packed));
31098 /*****************************
31099 * hwrm_fwd_async_event_cmpl *
31100 *****************************/
31103 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
31104 struct hwrm_fwd_async_event_cmpl_input {
31105 /* The HWRM command request type. */
31108 * The completion ring to send the completion event on. This should
31109 * be the NQ ID returned from the `nq_alloc` HWRM command.
31111 uint16_t cmpl_ring;
31113 * The sequence ID is used by the driver for tracking multiple
31114 * commands. This ID is treated as opaque data by the firmware and
31115 * the value is returned in the `hwrm_resp_hdr` upon completion.
31119 * The target ID of the command:
31120 * * 0x0-0xFFF8 - The function ID
31121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31122 * * 0xFFFD - Reserved for user-space HWRM interface
31125 uint16_t target_id;
31127 * A physical address pointer pointing to a host buffer that the
31128 * command's response data will be written. This can be either a host
31129 * physical address (HPA) or a guest physical address (GPA) and must
31130 * point to a physically contiguous block of memory.
31132 uint64_t resp_addr;
31134 * This value indicates the target id of the encapsulated
31135 * asynchronous event.
31136 * 0x0 - 0xFFF8 - Used for function ids
31137 * 0xFFF8 - 0xFFFE - Reserved for internal processors
31138 * 0xFFFF - Broadcast to all children VFs (only applicable when
31139 * a PF is the requester)
31141 uint16_t encap_async_event_target_id;
31142 uint8_t unused_0[6];
31143 /* This is an encapsulated asynchronous event completion. */
31144 uint32_t encap_async_event_cmpl[4];
31145 } __attribute__((packed));
31147 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
31148 struct hwrm_fwd_async_event_cmpl_output {
31149 /* The specific error status for the command. */
31150 uint16_t error_code;
31151 /* The HWRM command request type. */
31153 /* The sequence ID from the original command. */
31155 /* The length of the response data in number of bytes. */
31157 uint8_t unused_0[7];
31159 * This field is used in Output records to indicate that the output
31160 * is completely written to RAM. This field should be read as '1'
31161 * to indicate that the output has been completely written.
31162 * When writing a command completion or response to an internal processor,
31163 * the order of writes has to be such that this field is written last.
31166 } __attribute__((packed));
31168 /**************************
31169 * hwrm_nvm_raw_write_blk *
31170 **************************/
31173 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
31174 struct hwrm_nvm_raw_write_blk_input {
31175 /* The HWRM command request type. */
31178 * The completion ring to send the completion event on. This should
31179 * be the NQ ID returned from the `nq_alloc` HWRM command.
31181 uint16_t cmpl_ring;
31183 * The sequence ID is used by the driver for tracking multiple
31184 * commands. This ID is treated as opaque data by the firmware and
31185 * the value is returned in the `hwrm_resp_hdr` upon completion.
31189 * The target ID of the command:
31190 * * 0x0-0xFFF8 - The function ID
31191 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31192 * * 0xFFFD - Reserved for user-space HWRM interface
31195 uint16_t target_id;
31197 * A physical address pointer pointing to a host buffer that the
31198 * command's response data will be written. This can be either a host
31199 * physical address (HPA) or a guest physical address (GPA) and must
31200 * point to a physically contiguous block of memory.
31202 uint64_t resp_addr;
31204 * 64-bit Host Source Address.
31205 * This is the loation of the source data to be written.
31207 uint64_t host_src_addr;
31209 * 32-bit Destination Address.
31210 * This is the NVRAM byte-offset where the source data will be written to.
31212 uint32_t dest_addr;
31213 /* Length of data to be written, in bytes. */
31215 } __attribute__((packed));
31217 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
31218 struct hwrm_nvm_raw_write_blk_output {
31219 /* The specific error status for the command. */
31220 uint16_t error_code;
31221 /* The HWRM command request type. */
31223 /* The sequence ID from the original command. */
31225 /* The length of the response data in number of bytes. */
31227 uint8_t unused_0[7];
31229 * This field is used in Output records to indicate that the output
31230 * is completely written to RAM. This field should be read as '1'
31231 * to indicate that the output has been completely written.
31232 * When writing a command completion or response to an internal processor,
31233 * the order of writes has to be such that this field is written last.
31236 } __attribute__((packed));
31243 /* hwrm_nvm_read_input (size:320b/40B) */
31244 struct hwrm_nvm_read_input {
31245 /* The HWRM command request type. */
31248 * The completion ring to send the completion event on. This should
31249 * be the NQ ID returned from the `nq_alloc` HWRM command.
31251 uint16_t cmpl_ring;
31253 * The sequence ID is used by the driver for tracking multiple
31254 * commands. This ID is treated as opaque data by the firmware and
31255 * the value is returned in the `hwrm_resp_hdr` upon completion.
31259 * The target ID of the command:
31260 * * 0x0-0xFFF8 - The function ID
31261 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31262 * * 0xFFFD - Reserved for user-space HWRM interface
31265 uint16_t target_id;
31267 * A physical address pointer pointing to a host buffer that the
31268 * command's response data will be written. This can be either a host
31269 * physical address (HPA) or a guest physical address (GPA) and must
31270 * point to a physically contiguous block of memory.
31272 uint64_t resp_addr;
31274 * 64-bit Host Destination Address.
31275 * This is the host address where the data will be written to.
31277 uint64_t host_dest_addr;
31278 /* The 0-based index of the directory entry. */
31280 uint8_t unused_0[2];
31281 /* The NVRAM byte-offset to read from. */
31283 /* The length of the data to be read, in bytes. */
31285 uint8_t unused_1[4];
31286 } __attribute__((packed));
31288 /* hwrm_nvm_read_output (size:128b/16B) */
31289 struct hwrm_nvm_read_output {
31290 /* The specific error status for the command. */
31291 uint16_t error_code;
31292 /* The HWRM command request type. */
31294 /* The sequence ID from the original command. */
31296 /* The length of the response data in number of bytes. */
31298 uint8_t unused_0[7];
31300 * This field is used in Output records to indicate that the output
31301 * is completely written to RAM. This field should be read as '1'
31302 * to indicate that the output has been completely written.
31303 * When writing a command completion or response to an internal processor,
31304 * the order of writes has to be such that this field is written last.
31307 } __attribute__((packed));
31309 /*********************
31310 * hwrm_nvm_raw_dump *
31311 *********************/
31314 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
31315 struct hwrm_nvm_raw_dump_input {
31316 /* The HWRM command request type. */
31319 * The completion ring to send the completion event on. This should
31320 * be the NQ ID returned from the `nq_alloc` HWRM command.
31322 uint16_t cmpl_ring;
31324 * The sequence ID is used by the driver for tracking multiple
31325 * commands. This ID is treated as opaque data by the firmware and
31326 * the value is returned in the `hwrm_resp_hdr` upon completion.
31330 * The target ID of the command:
31331 * * 0x0-0xFFF8 - The function ID
31332 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31333 * * 0xFFFD - Reserved for user-space HWRM interface
31336 uint16_t target_id;
31338 * A physical address pointer pointing to a host buffer that the
31339 * command's response data will be written. This can be either a host
31340 * physical address (HPA) or a guest physical address (GPA) and must
31341 * point to a physically contiguous block of memory.
31343 uint64_t resp_addr;
31345 * 64-bit Host Destination Address.
31346 * This is the host address where the data will be written to.
31348 uint64_t host_dest_addr;
31349 /* 32-bit NVRAM byte-offset to read from. */
31351 /* Total length of NVRAM contents to be read, in bytes. */
31353 } __attribute__((packed));
31355 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
31356 struct hwrm_nvm_raw_dump_output {
31357 /* The specific error status for the command. */
31358 uint16_t error_code;
31359 /* The HWRM command request type. */
31361 /* The sequence ID from the original command. */
31363 /* The length of the response data in number of bytes. */
31365 uint8_t unused_0[7];
31367 * This field is used in Output records to indicate that the output
31368 * is completely written to RAM. This field should be read as '1'
31369 * to indicate that the output has been completely written.
31370 * When writing a command completion or response to an internal processor,
31371 * the order of writes has to be such that this field is written last.
31374 } __attribute__((packed));
31376 /****************************
31377 * hwrm_nvm_get_dir_entries *
31378 ****************************/
31381 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
31382 struct hwrm_nvm_get_dir_entries_input {
31383 /* The HWRM command request type. */
31386 * The completion ring to send the completion event on. This should
31387 * be the NQ ID returned from the `nq_alloc` HWRM command.
31389 uint16_t cmpl_ring;
31391 * The sequence ID is used by the driver for tracking multiple
31392 * commands. This ID is treated as opaque data by the firmware and
31393 * the value is returned in the `hwrm_resp_hdr` upon completion.
31397 * The target ID of the command:
31398 * * 0x0-0xFFF8 - The function ID
31399 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31400 * * 0xFFFD - Reserved for user-space HWRM interface
31403 uint16_t target_id;
31405 * A physical address pointer pointing to a host buffer that the
31406 * command's response data will be written. This can be either a host
31407 * physical address (HPA) or a guest physical address (GPA) and must
31408 * point to a physically contiguous block of memory.
31410 uint64_t resp_addr;
31412 * 64-bit Host Destination Address.
31413 * This is the host address where the directory will be written.
31415 uint64_t host_dest_addr;
31416 } __attribute__((packed));
31418 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
31419 struct hwrm_nvm_get_dir_entries_output {
31420 /* The specific error status for the command. */
31421 uint16_t error_code;
31422 /* The HWRM command request type. */
31424 /* The sequence ID from the original command. */
31426 /* The length of the response data in number of bytes. */
31428 uint8_t unused_0[7];
31430 * This field is used in Output records to indicate that the output
31431 * is completely written to RAM. This field should be read as '1'
31432 * to indicate that the output has been completely written.
31433 * When writing a command completion or response to an internal processor,
31434 * the order of writes has to be such that this field is written last.
31437 } __attribute__((packed));
31439 /*************************
31440 * hwrm_nvm_get_dir_info *
31441 *************************/
31444 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
31445 struct hwrm_nvm_get_dir_info_input {
31446 /* The HWRM command request type. */
31449 * The completion ring to send the completion event on. This should
31450 * be the NQ ID returned from the `nq_alloc` HWRM command.
31452 uint16_t cmpl_ring;
31454 * The sequence ID is used by the driver for tracking multiple
31455 * commands. This ID is treated as opaque data by the firmware and
31456 * the value is returned in the `hwrm_resp_hdr` upon completion.
31460 * The target ID of the command:
31461 * * 0x0-0xFFF8 - The function ID
31462 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31463 * * 0xFFFD - Reserved for user-space HWRM interface
31466 uint16_t target_id;
31468 * A physical address pointer pointing to a host buffer that the
31469 * command's response data will be written. This can be either a host
31470 * physical address (HPA) or a guest physical address (GPA) and must
31471 * point to a physically contiguous block of memory.
31473 uint64_t resp_addr;
31474 } __attribute__((packed));
31476 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
31477 struct hwrm_nvm_get_dir_info_output {
31478 /* The specific error status for the command. */
31479 uint16_t error_code;
31480 /* The HWRM command request type. */
31482 /* The sequence ID from the original command. */
31484 /* The length of the response data in number of bytes. */
31486 /* Number of directory entries in the directory. */
31488 /* Size of each directory entry, in bytes. */
31489 uint32_t entry_length;
31490 uint8_t unused_0[7];
31492 * This field is used in Output records to indicate that the output
31493 * is completely written to RAM. This field should be read as '1'
31494 * to indicate that the output has been completely written.
31495 * When writing a command completion or response to an internal processor,
31496 * the order of writes has to be such that this field is written last.
31499 } __attribute__((packed));
31501 /******************
31503 ******************/
31506 /* hwrm_nvm_write_input (size:384b/48B) */
31507 struct hwrm_nvm_write_input {
31508 /* The HWRM command request type. */
31511 * The completion ring to send the completion event on. This should
31512 * be the NQ ID returned from the `nq_alloc` HWRM command.
31514 uint16_t cmpl_ring;
31516 * The sequence ID is used by the driver for tracking multiple
31517 * commands. This ID is treated as opaque data by the firmware and
31518 * the value is returned in the `hwrm_resp_hdr` upon completion.
31522 * The target ID of the command:
31523 * * 0x0-0xFFF8 - The function ID
31524 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31525 * * 0xFFFD - Reserved for user-space HWRM interface
31528 uint16_t target_id;
31530 * A physical address pointer pointing to a host buffer that the
31531 * command's response data will be written. This can be either a host
31532 * physical address (HPA) or a guest physical address (GPA) and must
31533 * point to a physically contiguous block of memory.
31535 uint64_t resp_addr;
31537 * 64-bit Host Source Address.
31538 * This is where the source data is.
31540 uint64_t host_src_addr;
31541 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
31544 * Directory ordinal.
31545 * The 0-based instance of the combined Directory Entry Type and Extension.
31547 uint16_t dir_ordinal;
31548 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
31550 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
31553 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
31554 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
31556 uint32_t dir_data_length;
31561 * When this bit is '1', the original active image
31562 * will not be removed. TBD: what purpose is this?
31564 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
31567 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
31568 * If this value is less than the specified data length, it will be ignored.
31569 * The response will contain the actual allocated item length, which may be greater than the requested item length.
31570 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
31571 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
31573 uint32_t dir_item_length;
31575 } __attribute__((packed));
31577 /* hwrm_nvm_write_output (size:128b/16B) */
31578 struct hwrm_nvm_write_output {
31579 /* The specific error status for the command. */
31580 uint16_t error_code;
31581 /* The HWRM command request type. */
31583 /* The sequence ID from the original command. */
31585 /* The length of the response data in number of bytes. */
31588 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
31589 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
31591 uint32_t dir_item_length;
31592 /* The directory index of the created or modified item. */
31596 * This field is used in Output records to indicate that the output
31597 * is completely written to RAM. This field should be read as '1'
31598 * to indicate that the output has been completely written.
31599 * When writing a command completion or response to an internal processor,
31600 * the order of writes has to be such that this field is written last.
31603 } __attribute__((packed));
31605 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
31606 struct hwrm_nvm_write_cmd_err {
31608 * command specific error codes that goes to
31609 * the cmd_err field in Common HWRM Error Response.
31612 /* Unknown error */
31613 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31614 /* Unable to complete operation due to fragmentation */
31615 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
31616 /* nvm is completely full. */
31617 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
31618 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
31619 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
31620 uint8_t unused_0[7];
31621 } __attribute__((packed));
31623 /*******************
31624 * hwrm_nvm_modify *
31625 *******************/
31628 /* hwrm_nvm_modify_input (size:320b/40B) */
31629 struct hwrm_nvm_modify_input {
31630 /* The HWRM command request type. */
31633 * The completion ring to send the completion event on. This should
31634 * be the NQ ID returned from the `nq_alloc` HWRM command.
31636 uint16_t cmpl_ring;
31638 * The sequence ID is used by the driver for tracking multiple
31639 * commands. This ID is treated as opaque data by the firmware and
31640 * the value is returned in the `hwrm_resp_hdr` upon completion.
31644 * The target ID of the command:
31645 * * 0x0-0xFFF8 - The function ID
31646 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31647 * * 0xFFFD - Reserved for user-space HWRM interface
31650 uint16_t target_id;
31652 * A physical address pointer pointing to a host buffer that the
31653 * command's response data will be written. This can be either a host
31654 * physical address (HPA) or a guest physical address (GPA) and must
31655 * point to a physically contiguous block of memory.
31657 uint64_t resp_addr;
31659 * 64-bit Host Source Address.
31660 * This is where the modified data is.
31662 uint64_t host_src_addr;
31663 /* 16-bit directory entry index. */
31665 uint8_t unused_0[2];
31666 /* 32-bit NVRAM byte-offset to modify content from. */
31669 * Length of data to be modified, in bytes. The length shall
31673 uint8_t unused_1[4];
31674 } __attribute__((packed));
31676 /* hwrm_nvm_modify_output (size:128b/16B) */
31677 struct hwrm_nvm_modify_output {
31678 /* The specific error status for the command. */
31679 uint16_t error_code;
31680 /* The HWRM command request type. */
31682 /* The sequence ID from the original command. */
31684 /* The length of the response data in number of bytes. */
31686 uint8_t unused_0[7];
31688 * This field is used in Output records to indicate that the output
31689 * is completely written to RAM. This field should be read as '1'
31690 * to indicate that the output has been completely written.
31691 * When writing a command completion or response to an internal processor,
31692 * the order of writes has to be such that this field is written last.
31695 } __attribute__((packed));
31697 /***************************
31698 * hwrm_nvm_find_dir_entry *
31699 ***************************/
31702 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
31703 struct hwrm_nvm_find_dir_entry_input {
31704 /* The HWRM command request type. */
31707 * The completion ring to send the completion event on. This should
31708 * be the NQ ID returned from the `nq_alloc` HWRM command.
31710 uint16_t cmpl_ring;
31712 * The sequence ID is used by the driver for tracking multiple
31713 * commands. This ID is treated as opaque data by the firmware and
31714 * the value is returned in the `hwrm_resp_hdr` upon completion.
31718 * The target ID of the command:
31719 * * 0x0-0xFFF8 - The function ID
31720 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31721 * * 0xFFFD - Reserved for user-space HWRM interface
31724 uint16_t target_id;
31726 * A physical address pointer pointing to a host buffer that the
31727 * command's response data will be written. This can be either a host
31728 * physical address (HPA) or a guest physical address (GPA) and must
31729 * point to a physically contiguous block of memory.
31731 uint64_t resp_addr;
31734 * This bit must be '1' for the dir_idx_valid field to be
31737 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
31739 /* Directory Entry Index */
31741 /* Directory Entry (Image) Type */
31744 * Directory ordinal.
31745 * The instance of this Directory Type
31747 uint16_t dir_ordinal;
31748 /* The Directory Entry Extension flags. */
31750 /* This value indicates the search option using dir_ordinal. */
31751 uint8_t opt_ordinal;
31752 /* This value indicates the search option using dir_ordinal. */
31753 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
31754 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
31755 /* Equal to specified ordinal value. */
31756 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
31757 /* Greater than or equal to specified ordinal value */
31758 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
31759 /* Greater than specified ordinal value */
31760 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
31761 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
31762 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
31763 uint8_t unused_0[3];
31764 } __attribute__((packed));
31766 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
31767 struct hwrm_nvm_find_dir_entry_output {
31768 /* The specific error status for the command. */
31769 uint16_t error_code;
31770 /* The HWRM command request type. */
31772 /* The sequence ID from the original command. */
31774 /* The length of the response data in number of bytes. */
31776 /* Allocated NVRAM for this directory entry, in bytes. */
31777 uint32_t dir_item_length;
31778 /* Size of the stored data for this directory entry, in bytes. */
31779 uint32_t dir_data_length;
31781 * Firmware version.
31782 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
31785 /* Directory ordinal. */
31786 uint16_t dir_ordinal;
31787 /* Directory Entry Index */
31789 uint8_t unused_0[7];
31791 * This field is used in Output records to indicate that the output
31792 * is completely written to RAM. This field should be read as '1'
31793 * to indicate that the output has been completely written.
31794 * When writing a command completion or response to an internal processor,
31795 * the order of writes has to be such that this field is written last.
31798 } __attribute__((packed));
31800 /****************************
31801 * hwrm_nvm_erase_dir_entry *
31802 ****************************/
31805 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
31806 struct hwrm_nvm_erase_dir_entry_input {
31807 /* The HWRM command request type. */
31810 * The completion ring to send the completion event on. This should
31811 * be the NQ ID returned from the `nq_alloc` HWRM command.
31813 uint16_t cmpl_ring;
31815 * The sequence ID is used by the driver for tracking multiple
31816 * commands. This ID is treated as opaque data by the firmware and
31817 * the value is returned in the `hwrm_resp_hdr` upon completion.
31821 * The target ID of the command:
31822 * * 0x0-0xFFF8 - The function ID
31823 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31824 * * 0xFFFD - Reserved for user-space HWRM interface
31827 uint16_t target_id;
31829 * A physical address pointer pointing to a host buffer that the
31830 * command's response data will be written. This can be either a host
31831 * physical address (HPA) or a guest physical address (GPA) and must
31832 * point to a physically contiguous block of memory.
31834 uint64_t resp_addr;
31835 /* Directory Entry Index */
31837 uint8_t unused_0[6];
31838 } __attribute__((packed));
31840 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
31841 struct hwrm_nvm_erase_dir_entry_output {
31842 /* The specific error status for the command. */
31843 uint16_t error_code;
31844 /* The HWRM command request type. */
31846 /* The sequence ID from the original command. */
31848 /* The length of the response data in number of bytes. */
31850 uint8_t unused_0[7];
31852 * This field is used in Output records to indicate that the output
31853 * is completely written to RAM. This field should be read as '1'
31854 * to indicate that the output has been completely written.
31855 * When writing a command completion or response to an internal processor,
31856 * the order of writes has to be such that this field is written last.
31859 } __attribute__((packed));
31861 /*************************
31862 * hwrm_nvm_get_dev_info *
31863 *************************/
31866 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
31867 struct hwrm_nvm_get_dev_info_input {
31868 /* The HWRM command request type. */
31871 * The completion ring to send the completion event on. This should
31872 * be the NQ ID returned from the `nq_alloc` HWRM command.
31874 uint16_t cmpl_ring;
31876 * The sequence ID is used by the driver for tracking multiple
31877 * commands. This ID is treated as opaque data by the firmware and
31878 * the value is returned in the `hwrm_resp_hdr` upon completion.
31882 * The target ID of the command:
31883 * * 0x0-0xFFF8 - The function ID
31884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31885 * * 0xFFFD - Reserved for user-space HWRM interface
31888 uint16_t target_id;
31890 * A physical address pointer pointing to a host buffer that the
31891 * command's response data will be written. This can be either a host
31892 * physical address (HPA) or a guest physical address (GPA) and must
31893 * point to a physically contiguous block of memory.
31895 uint64_t resp_addr;
31896 } __attribute__((packed));
31898 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
31899 struct hwrm_nvm_get_dev_info_output {
31900 /* The specific error status for the command. */
31901 uint16_t error_code;
31902 /* The HWRM command request type. */
31904 /* The sequence ID from the original command. */
31906 /* The length of the response data in number of bytes. */
31908 /* Manufacturer ID. */
31909 uint16_t manufacturer_id;
31911 uint16_t device_id;
31912 /* Sector size of the NVRAM device. */
31913 uint32_t sector_size;
31914 /* Total size, in bytes of the NVRAM device. */
31915 uint32_t nvram_size;
31916 uint32_t reserved_size;
31917 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
31918 uint32_t available_size;
31919 /* This field represents the major version of NVM cfg */
31920 uint8_t nvm_cfg_ver_maj;
31921 /* This field represents the minor version of NVM cfg */
31922 uint8_t nvm_cfg_ver_min;
31923 /* This field represents the update version of NVM cfg */
31924 uint8_t nvm_cfg_ver_upd;
31926 * This field is used in Output records to indicate that the output
31927 * is completely written to RAM. This field should be read as '1'
31928 * to indicate that the output has been completely written.
31929 * When writing a command completion or response to an internal processor,
31930 * the order of writes has to be such that this field is written last.
31933 } __attribute__((packed));
31935 /**************************
31936 * hwrm_nvm_mod_dir_entry *
31937 **************************/
31940 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
31941 struct hwrm_nvm_mod_dir_entry_input {
31942 /* The HWRM command request type. */
31945 * The completion ring to send the completion event on. This should
31946 * be the NQ ID returned from the `nq_alloc` HWRM command.
31948 uint16_t cmpl_ring;
31950 * The sequence ID is used by the driver for tracking multiple
31951 * commands. This ID is treated as opaque data by the firmware and
31952 * the value is returned in the `hwrm_resp_hdr` upon completion.
31956 * The target ID of the command:
31957 * * 0x0-0xFFF8 - The function ID
31958 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31959 * * 0xFFFD - Reserved for user-space HWRM interface
31962 uint16_t target_id;
31964 * A physical address pointer pointing to a host buffer that the
31965 * command's response data will be written. This can be either a host
31966 * physical address (HPA) or a guest physical address (GPA) and must
31967 * point to a physically contiguous block of memory.
31969 uint64_t resp_addr;
31972 * This bit must be '1' for the checksum field to be
31975 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
31976 /* Directory Entry Index */
31979 * Directory ordinal.
31980 * The (0-based) instance of this Directory Type.
31982 uint16_t dir_ordinal;
31983 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
31985 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
31988 * If valid, then this field updates the checksum
31989 * value of the content in the directory entry.
31992 } __attribute__((packed));
31994 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
31995 struct hwrm_nvm_mod_dir_entry_output {
31996 /* The specific error status for the command. */
31997 uint16_t error_code;
31998 /* The HWRM command request type. */
32000 /* The sequence ID from the original command. */
32002 /* The length of the response data in number of bytes. */
32004 uint8_t unused_0[7];
32006 * This field is used in Output records to indicate that the output
32007 * is completely written to RAM. This field should be read as '1'
32008 * to indicate that the output has been completely written.
32009 * When writing a command completion or response to an internal processor,
32010 * the order of writes has to be such that this field is written last.
32013 } __attribute__((packed));
32015 /**************************
32016 * hwrm_nvm_verify_update *
32017 **************************/
32020 /* hwrm_nvm_verify_update_input (size:192b/24B) */
32021 struct hwrm_nvm_verify_update_input {
32022 /* The HWRM command request type. */
32025 * The completion ring to send the completion event on. This should
32026 * be the NQ ID returned from the `nq_alloc` HWRM command.
32028 uint16_t cmpl_ring;
32030 * The sequence ID is used by the driver for tracking multiple
32031 * commands. This ID is treated as opaque data by the firmware and
32032 * the value is returned in the `hwrm_resp_hdr` upon completion.
32036 * The target ID of the command:
32037 * * 0x0-0xFFF8 - The function ID
32038 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32039 * * 0xFFFD - Reserved for user-space HWRM interface
32042 uint16_t target_id;
32044 * A physical address pointer pointing to a host buffer that the
32045 * command's response data will be written. This can be either a host
32046 * physical address (HPA) or a guest physical address (GPA) and must
32047 * point to a physically contiguous block of memory.
32049 uint64_t resp_addr;
32050 /* Directory Entry Type, to be verified. */
32053 * Directory ordinal.
32054 * The instance of the Directory Type to be verified.
32056 uint16_t dir_ordinal;
32058 * The Directory Entry Extension flags.
32059 * The "UPDATE" extension flag must be set in this value.
32060 * A corresponding directory entry with the same type and ordinal values but *without*
32061 * the "UPDATE" extension flag must also exist. The other flags of the extension must
32062 * be identical between the active and update entries.
32065 uint8_t unused_0[2];
32066 } __attribute__((packed));
32068 /* hwrm_nvm_verify_update_output (size:128b/16B) */
32069 struct hwrm_nvm_verify_update_output {
32070 /* The specific error status for the command. */
32071 uint16_t error_code;
32072 /* The HWRM command request type. */
32074 /* The sequence ID from the original command. */
32076 /* The length of the response data in number of bytes. */
32078 uint8_t unused_0[7];
32080 * This field is used in Output records to indicate that the output
32081 * is completely written to RAM. This field should be read as '1'
32082 * to indicate that the output has been completely written.
32083 * When writing a command completion or response to an internal processor,
32084 * the order of writes has to be such that this field is written last.
32087 } __attribute__((packed));
32089 /***************************
32090 * hwrm_nvm_install_update *
32091 ***************************/
32094 /* hwrm_nvm_install_update_input (size:192b/24B) */
32095 struct hwrm_nvm_install_update_input {
32096 /* The HWRM command request type. */
32099 * The completion ring to send the completion event on. This should
32100 * be the NQ ID returned from the `nq_alloc` HWRM command.
32102 uint16_t cmpl_ring;
32104 * The sequence ID is used by the driver for tracking multiple
32105 * commands. This ID is treated as opaque data by the firmware and
32106 * the value is returned in the `hwrm_resp_hdr` upon completion.
32110 * The target ID of the command:
32111 * * 0x0-0xFFF8 - The function ID
32112 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32113 * * 0xFFFD - Reserved for user-space HWRM interface
32116 uint16_t target_id;
32118 * A physical address pointer pointing to a host buffer that the
32119 * command's response data will be written. This can be either a host
32120 * physical address (HPA) or a guest physical address (GPA) and must
32121 * point to a physically contiguous block of memory.
32123 uint64_t resp_addr;
32125 * Installation type. If the value 3 through 0xffff is used,
32126 * only packaged items with that type value will be installed and
32127 * conditional installation directives for those packaged items
32128 * will be over-ridden (i.e. 'create' or 'replace' will be treated
32131 uint32_t install_type;
32133 * Perform a normal package installation. Conditional installation
32134 * directives (e.g. 'create' and 'replace') of packaged items
32135 * will be followed.
32137 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
32139 * Install all packaged items regardless of installation directive
32140 * (i.e. treat all packaged items as though they have an installation
32141 * directive of 'install').
32143 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
32144 UINT32_C(0xffffffff)
32145 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
32146 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
32148 /* If set to 1, then securely erase all unused locations in persistent storage. */
32149 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
32152 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
32153 * When combined with erase_unused_space then unspecified images will be securely erased.
32155 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
32158 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
32159 * Allow additional time for this command to complete if this bit is set to 1.
32161 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
32163 uint8_t unused_0[2];
32164 } __attribute__((packed));
32166 /* hwrm_nvm_install_update_output (size:192b/24B) */
32167 struct hwrm_nvm_install_update_output {
32168 /* The specific error status for the command. */
32169 uint16_t error_code;
32170 /* The HWRM command request type. */
32172 /* The sequence ID from the original command. */
32174 /* The length of the response data in number of bytes. */
32177 * Bit-mask of successfully installed items.
32178 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
32179 * A value of 0 indicates that no items were successfully installed.
32181 uint64_t installed_items;
32182 /* result is 8 b */
32184 /* There was no problem with the package installation. */
32185 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
32186 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
32187 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
32188 /* problem_item is 8 b */
32189 uint8_t problem_item;
32190 /* There was no problem with any packaged items. */
32191 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
32193 /* There was a problem with the NVM package itself. */
32194 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
32196 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
32197 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
32198 /* reset_required is 8 b */
32199 uint8_t reset_required;
32201 * No reset is required for installed/updated firmware or
32202 * microcode to take effect.
32204 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
32207 * A PCIe reset (e.g. system reboot) is
32208 * required for newly installed/updated firmware or
32209 * microcode to take effect.
32211 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
32214 * A controller power reset (e.g. system power-cycle) is
32215 * required for newly installed/updated firmware or
32216 * microcode to take effect. Some newly installed/updated
32217 * firmware or microcode may still take effect upon the
32220 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
32222 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
32223 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
32224 uint8_t unused_0[4];
32226 * This field is used in Output records to indicate that the output
32227 * is completely written to RAM. This field should be read as '1'
32228 * to indicate that the output has been completely written.
32229 * When writing a command completion or response to an internal processor,
32230 * the order of writes has to be such that this field is written last.
32233 } __attribute__((packed));
32235 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
32236 struct hwrm_nvm_install_update_cmd_err {
32238 * command specific error codes that goes to
32239 * the cmd_err field in Common HWRM Error Response.
32242 /* Unknown error */
32243 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32244 /* Unable to complete operation due to fragmentation */
32245 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
32246 /* nvm is completely full. */
32247 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
32248 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
32249 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
32250 uint8_t unused_0[7];
32251 } __attribute__((packed));
32253 /******************
32255 ******************/
32258 /* hwrm_nvm_flush_input (size:128b/16B) */
32259 struct hwrm_nvm_flush_input {
32260 /* The HWRM command request type. */
32263 * The completion ring to send the completion event on. This should
32264 * be the NQ ID returned from the `nq_alloc` HWRM command.
32266 uint16_t cmpl_ring;
32268 * The sequence ID is used by the driver for tracking multiple
32269 * commands. This ID is treated as opaque data by the firmware and
32270 * the value is returned in the `hwrm_resp_hdr` upon completion.
32274 * The target ID of the command:
32275 * * 0x0-0xFFF8 - The function ID
32276 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32277 * * 0xFFFD - Reserved for user-space HWRM interface
32280 uint16_t target_id;
32282 * A physical address pointer pointing to a host buffer that the
32283 * command's response data will be written. This can be either a host
32284 * physical address (HPA) or a guest physical address (GPA) and must
32285 * point to a physically contiguous block of memory.
32287 uint64_t resp_addr;
32288 } __attribute__((packed));
32290 /* hwrm_nvm_flush_output (size:128b/16B) */
32291 struct hwrm_nvm_flush_output {
32292 /* The specific error status for the command. */
32293 uint16_t error_code;
32294 /* The HWRM command request type. */
32296 /* The sequence ID from the original command. */
32298 /* The length of the response data in number of bytes. */
32300 uint8_t unused_0[7];
32302 * This field is used in Output records to indicate that the output
32303 * is completely written to RAM. This field should be read as '1'
32304 * to indicate that the output has been completely written.
32305 * When writing a command completion or response to an internal processor,
32306 * the order of writes has to be such that this field is written last.
32309 } __attribute__((packed));
32311 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
32312 struct hwrm_nvm_flush_cmd_err {
32314 * command specific error codes that goes to
32315 * the cmd_err field in Common HWRM Error Response.
32318 /* Unknown error */
32319 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32320 /* flush could not be performed */
32321 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
32322 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
32323 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
32324 uint8_t unused_0[7];
32325 } __attribute__((packed));
32327 /*************************
32328 * hwrm_nvm_get_variable *
32329 *************************/
32332 /* hwrm_nvm_get_variable_input (size:320b/40B) */
32333 struct hwrm_nvm_get_variable_input {
32334 /* The HWRM command request type. */
32337 * The completion ring to send the completion event on. This should
32338 * be the NQ ID returned from the `nq_alloc` HWRM command.
32340 uint16_t cmpl_ring;
32342 * The sequence ID is used by the driver for tracking multiple
32343 * commands. This ID is treated as opaque data by the firmware and
32344 * the value is returned in the `hwrm_resp_hdr` upon completion.
32348 * The target ID of the command:
32349 * * 0x0-0xFFF8 - The function ID
32350 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32351 * * 0xFFFD - Reserved for user-space HWRM interface
32354 uint16_t target_id;
32356 * A physical address pointer pointing to a host buffer that the
32357 * command's response data will be written. This can be either a host
32358 * physical address (HPA) or a guest physical address (GPA) and must
32359 * point to a physically contiguous block of memory.
32361 uint64_t resp_addr;
32363 * This is the host address where
32364 * nvm variable will be stored
32366 uint64_t dest_data_addr;
32367 /* size of data in bits */
32369 /* nvm cfg option number */
32370 uint16_t option_num;
32372 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
32374 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
32376 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
32377 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
32379 * Number of dimensions for this nvm configuration variable.
32380 * This value indicates how many of the indexN values to use.
32381 * A value of 0 means that none of the indexN values are valid.
32382 * A value of 1 requires at index0 is valued, a value of 2
32383 * requires that index0 and index1 are valid, and so forth
32385 uint16_t dimensions;
32386 /* index for the 1st dimensions */
32388 /* index for the 2nd dimensions */
32390 /* index for the 3rd dimensions */
32392 /* index for the 4th dimensions */
32396 * When this bit is set to 1, the factory default value will be returned,
32397 * 0 returns the operational value.
32399 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
32402 } __attribute__((packed));
32404 /* hwrm_nvm_get_variable_output (size:128b/16B) */
32405 struct hwrm_nvm_get_variable_output {
32406 /* The specific error status for the command. */
32407 uint16_t error_code;
32408 /* The HWRM command request type. */
32410 /* The sequence ID from the original command. */
32412 /* The length of the response data in number of bytes. */
32414 /* size of data of the actual variable retrieved in bits */
32417 * option_num is the option number for the data retrieved. It is possible in the
32418 * future that the option number returned would be different than requested. This
32419 * condition could occur if an option is deprecated and a new option id is defined
32420 * with similar characteristics, but has a slightly different definition. This
32421 * also makes it convenient for the caller to identify the variable result with
32422 * the option id from the response.
32424 uint16_t option_num;
32426 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
32428 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
32430 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
32431 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
32432 uint8_t unused_0[3];
32434 * This field is used in Output records to indicate that the output
32435 * is completely written to RAM. This field should be read as '1'
32436 * to indicate that the output has been completely written.
32437 * When writing a command completion or response to an internal processor,
32438 * the order of writes has to be such that this field is written last.
32441 } __attribute__((packed));
32443 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
32444 struct hwrm_nvm_get_variable_cmd_err {
32446 * command specific error codes that goes to
32447 * the cmd_err field in Common HWRM Error Response.
32450 /* Unknown error */
32451 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32452 /* variable does not exist */
32453 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
32454 /* configuration is corrupted and the variable cannot be saved */
32455 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
32456 /* length specified is too small */
32457 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
32458 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
32459 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
32460 uint8_t unused_0[7];
32461 } __attribute__((packed));
32463 /*************************
32464 * hwrm_nvm_set_variable *
32465 *************************/
32468 /* hwrm_nvm_set_variable_input (size:320b/40B) */
32469 struct hwrm_nvm_set_variable_input {
32470 /* The HWRM command request type. */
32473 * The completion ring to send the completion event on. This should
32474 * be the NQ ID returned from the `nq_alloc` HWRM command.
32476 uint16_t cmpl_ring;
32478 * The sequence ID is used by the driver for tracking multiple
32479 * commands. This ID is treated as opaque data by the firmware and
32480 * the value is returned in the `hwrm_resp_hdr` upon completion.
32484 * The target ID of the command:
32485 * * 0x0-0xFFF8 - The function ID
32486 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32487 * * 0xFFFD - Reserved for user-space HWRM interface
32490 uint16_t target_id;
32492 * A physical address pointer pointing to a host buffer that the
32493 * command's response data will be written. This can be either a host
32494 * physical address (HPA) or a guest physical address (GPA) and must
32495 * point to a physically contiguous block of memory.
32497 uint64_t resp_addr;
32499 * This is the host address where
32500 * nvm variable will be copied from
32502 uint64_t src_data_addr;
32503 /* size of data in bits */
32505 /* nvm cfg option number */
32506 uint16_t option_num;
32508 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
32510 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
32512 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
32513 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
32515 * Number of dimensions for this nvm configuration variable.
32516 * This value indicates how many of the indexN values to use.
32517 * A value of 0 means that none of the indexN values are valid.
32518 * A value of 1 requires at index0 is valued, a value of 2
32519 * requires that index0 and index1 are valid, and so forth
32521 uint16_t dimensions;
32522 /* index for the 1st dimensions */
32524 /* index for the 2nd dimensions */
32526 /* index for the 3rd dimensions */
32528 /* index for the 4th dimensions */
32531 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
32532 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
32534 /* encryption method */
32535 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
32537 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
32538 /* No encryption. */
32539 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
32540 (UINT32_C(0x0) << 1)
32541 /* one-way encryption. */
32542 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
32543 (UINT32_C(0x1) << 1)
32544 /* symmetric AES256 encryption. */
32545 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
32546 (UINT32_C(0x2) << 1)
32547 /* SHA1 digest appended to plaintext contents, for authentication */
32548 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
32549 (UINT32_C(0x3) << 1)
32550 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
32551 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
32553 } __attribute__((packed));
32555 /* hwrm_nvm_set_variable_output (size:128b/16B) */
32556 struct hwrm_nvm_set_variable_output {
32557 /* The specific error status for the command. */
32558 uint16_t error_code;
32559 /* The HWRM command request type. */
32561 /* The sequence ID from the original command. */
32563 /* The length of the response data in number of bytes. */
32565 uint8_t unused_0[7];
32567 * This field is used in Output records to indicate that the output
32568 * is completely written to RAM. This field should be read as '1'
32569 * to indicate that the output has been completely written.
32570 * When writing a command completion or response to an internal processor,
32571 * the order of writes has to be such that this field is written last.
32574 } __attribute__((packed));
32576 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
32577 struct hwrm_nvm_set_variable_cmd_err {
32579 * command specific error codes that goes to
32580 * the cmd_err field in Common HWRM Error Response.
32583 /* Unknown error */
32584 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32585 /* variable does not exist */
32586 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
32587 /* configuration is corrupted and the variable cannot be saved */
32588 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
32589 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
32590 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
32591 uint8_t unused_0[7];
32592 } __attribute__((packed));
32594 /****************************
32595 * hwrm_nvm_validate_option *
32596 ****************************/
32599 /* hwrm_nvm_validate_option_input (size:320b/40B) */
32600 struct hwrm_nvm_validate_option_input {
32601 /* The HWRM command request type. */
32604 * The completion ring to send the completion event on. This should
32605 * be the NQ ID returned from the `nq_alloc` HWRM command.
32607 uint16_t cmpl_ring;
32609 * The sequence ID is used by the driver for tracking multiple
32610 * commands. This ID is treated as opaque data by the firmware and
32611 * the value is returned in the `hwrm_resp_hdr` upon completion.
32615 * The target ID of the command:
32616 * * 0x0-0xFFF8 - The function ID
32617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32618 * * 0xFFFD - Reserved for user-space HWRM interface
32621 uint16_t target_id;
32623 * A physical address pointer pointing to a host buffer that the
32624 * command's response data will be written. This can be either a host
32625 * physical address (HPA) or a guest physical address (GPA) and must
32626 * point to a physically contiguous block of memory.
32628 uint64_t resp_addr;
32630 * This is the host address where
32631 * nvm variable will be copied from
32633 uint64_t src_data_addr;
32634 /* size of data in bits */
32636 /* nvm cfg option number */
32637 uint16_t option_num;
32639 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
32642 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
32644 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
32645 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
32647 * Number of dimensions for this nvm configuration variable.
32648 * This value indicates how many of the indexN values to use.
32649 * A value of 0 means that none of the indexN values are valid.
32650 * A value of 1 requires at index0 is valued, a value of 2
32651 * requires that index0 and index1 are valid, and so forth
32653 uint16_t dimensions;
32654 /* index for the 1st dimensions */
32656 /* index for the 2nd dimensions */
32658 /* index for the 3rd dimensions */
32660 /* index for the 4th dimensions */
32662 uint8_t unused_0[2];
32663 } __attribute__((packed));
32665 /* hwrm_nvm_validate_option_output (size:128b/16B) */
32666 struct hwrm_nvm_validate_option_output {
32667 /* The specific error status for the command. */
32668 uint16_t error_code;
32669 /* The HWRM command request type. */
32671 /* The sequence ID from the original command. */
32673 /* The length of the response data in number of bytes. */
32676 /* indicates that the value provided for the option is not matching with the saved data. */
32677 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
32678 /* indicates that the value provided for the option is matching the saved data. */
32679 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
32680 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
32681 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
32682 uint8_t unused_0[6];
32684 * This field is used in Output records to indicate that the output
32685 * is completely written to RAM. This field should be read as '1'
32686 * to indicate that the output has been completely written.
32687 * When writing a command completion or response to an internal processor,
32688 * the order of writes has to be such that this field is written last.
32691 } __attribute__((packed));
32693 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
32694 struct hwrm_nvm_validate_option_cmd_err {
32696 * command specific error codes that goes to
32697 * the cmd_err field in Common HWRM Error Response.
32700 /* Unknown error */
32701 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
32702 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
32703 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
32704 uint8_t unused_0[7];
32705 } __attribute__((packed));
32707 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */