1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* RoCE slow path command to query CC Gen1 support. */
71 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
72 /* RoCE slow path command to modify CC Gen1 support. */
73 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
74 /* Engine CKV - The device's serial number. */
75 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
76 /* Engine CKV - Per-function random nonce data. */
77 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
78 /* Engine CKV - Initialization vector. */
79 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
80 /* Engine CKV - Authentication tag. */
81 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
82 /* Engine CKV - The encrypted data. */
83 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
84 /* Engine CKV - Supported algorithms. */
85 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
86 /* Engine CKV - The EC curve name and ECC public key information. */
87 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
88 /* Engine CKV - The ECDSA signature. */
89 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
90 #define TLV_TYPE_LAST \
91 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
94 /* tlv (size:64b/8B) */
97 * The command discriminator is used to differentiate between various
98 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
99 * command messages as well as newer TLV encapsulated HWRM commands.
101 * For TLV encapsulated messages this field must be 0x8000.
107 * Indicates the presence of additional TLV encapsulated data
110 #define TLV_FLAGS_MORE UINT32_C(0x1)
111 /* Last TLV in a sequence of TLVs. */
112 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
113 /* More TLVs follow this TLV. */
114 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
116 * When an HWRM receiver detects a TLV type that it does not
117 * support with the TLV required flag set, the receiver must
118 * reject the HWRM message with an error code indicating an
119 * unsupported TLV type.
121 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
123 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
125 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
126 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
128 * This field defines the TLV type value which is divided into
129 * two ranges to differentiate between global and local TLV types.
130 * Global TLV types must be unique across all defined TLV types.
131 * Local TLV types are valid only for extensions to a given
132 * HWRM message and may be repeated across different HWRM message
133 * types. There is a direct correlation of each HWRM message type
134 * to a single global TLV type value.
136 * Global TLV range: `0 - (63k-1)`
138 * Local TLV range: `63k - (64k-1)`
142 * Length of the message data encapsulated by this TLV in bytes.
143 * This length does not include the size of the TLV header itself
144 * and it must be an integer multiple of 8B.
147 } __attribute__((packed));
150 /* input (size:128b/16B) */
153 * This value indicates what type of request this is. The format
154 * for the rest of the command is determined by this field.
158 * This value indicates the what completion ring the request will
159 * be optionally completed on. If the value is -1, then no
160 * CR completion will be generated. Any other value must be a
161 * valid CR ring_id value for this function.
164 /* This value indicates the command sequence number. */
167 * Target ID of this command.
169 * 0x0 - 0xFFF8 - Used for function ids
170 * 0xFFF8 - 0xFFFE - Reserved for internal processors
175 * This is the host address where the response will be written
176 * when the request is complete. This area must be 16B aligned
177 * and must be cleared to zero before the request is made.
180 } __attribute__((packed));
183 /* output (size:64b/8B) */
186 * Pass/Fail or error type
188 * Note: receiver to verify the in parameters, and fail the call
189 * with an error when appropriate
192 /* This field returns the type of original request. */
194 /* This field provides original sequence number of the command. */
197 * This field is the length of the response in bytes. The
198 * last byte of the response is a valid flag that will read
199 * as '1' when the command has been completely written to
203 } __attribute__((packed));
205 /* Short Command Structure */
206 /* hwrm_short_input (size:128b/16B) */
207 struct hwrm_short_input {
209 * This field indicates the type of request in the request buffer.
210 * The format for the rest of the command (request) is determined
215 * This field indicates a signature that is used to identify short
216 * form of the command listed here. This field shall be set to
220 /* Signature indicating this is a short form of HWRM command */
221 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
222 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
223 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
224 /* Reserved for future use. */
226 /* This value indicates the length of the request. */
229 * This is the host address where the request was written.
230 * This area must be 16B aligned.
233 } __attribute__((packed));
237 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
238 * # So only structure definition is provided here.
240 /* cmd_nums (size:64b/8B) */
243 * This version of the specification defines the commands listed in
244 * the table below. The following are general implementation
245 * requirements for these commands:
247 * # All commands listed below that are marked neither
248 * reserved nor experimental shall be implemented by the HWRM.
249 * # A HWRM client compliant to this specification should not use
250 * commands outside of the list below.
251 * # A HWRM client compliant to this specification should not use
252 * command numbers marked reserved below.
253 * # A command marked experimental below may not be implemented
255 * # A command marked experimental may change in the
256 * future version of the HWRM specification.
257 * # A command not listed below may be implemented by the HWRM.
258 * The behavior of commands that are not listed below is outside
259 * the scope of this specification.
262 #define HWRM_VER_GET UINT32_C(0x0)
263 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
264 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
265 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
266 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
267 /* Reserved for future use. */
268 #define HWRM_RESERVED1 UINT32_C(0x10)
269 #define HWRM_FUNC_RESET UINT32_C(0x11)
270 #define HWRM_FUNC_GETFID UINT32_C(0x12)
271 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
272 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
273 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
274 #define HWRM_FUNC_QCFG UINT32_C(0x16)
275 #define HWRM_FUNC_CFG UINT32_C(0x17)
276 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
277 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
278 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
279 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
280 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
281 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
282 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
283 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
284 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
285 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
287 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
288 #define HWRM_PORT_QSTATS UINT32_C(0x23)
289 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
291 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
293 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
294 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
295 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
297 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
298 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
299 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
300 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
301 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
302 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
303 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
304 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
305 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
306 #define HWRM_QUEUE_CFG UINT32_C(0x32)
307 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
308 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
309 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
310 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
311 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
312 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
313 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
314 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
316 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
318 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
320 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
321 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
322 #define HWRM_VNIC_FREE UINT32_C(0x41)
323 #define HWRM_VNIC_CFG UINT32_C(0x42)
324 #define HWRM_VNIC_QCFG UINT32_C(0x43)
325 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
327 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
328 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
329 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
330 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
331 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
332 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
333 #define HWRM_RING_ALLOC UINT32_C(0x50)
334 #define HWRM_RING_FREE UINT32_C(0x51)
335 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
336 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
337 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
338 #define HWRM_RING_RESET UINT32_C(0x5e)
339 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
340 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
341 /* Reserved for future use. */
342 #define HWRM_RESERVED5 UINT32_C(0x64)
343 /* Reserved for future use. */
344 #define HWRM_RESERVED6 UINT32_C(0x65)
345 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
346 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
347 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
348 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
349 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
350 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
351 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
352 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
353 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
355 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
357 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
358 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
359 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
360 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
362 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
364 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
366 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
367 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
368 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
369 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
370 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
371 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
372 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
373 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
374 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
375 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
376 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
377 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
378 #define HWRM_FW_RESET UINT32_C(0xc0)
379 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
380 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
381 #define HWRM_FW_SYNC UINT32_C(0xc3)
383 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
385 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
387 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
389 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
391 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
392 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
393 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
394 #define HWRM_FWD_RESP UINT32_C(0xd2)
395 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
396 #define HWRM_OEM_CMD UINT32_C(0xd4)
397 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
398 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
399 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
400 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
401 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
403 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
405 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
407 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
409 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
411 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
413 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
415 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
417 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
419 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
421 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
423 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
425 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
427 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
429 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
431 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
433 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
435 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
437 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
439 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
440 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
441 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
442 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
444 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
446 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
448 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
450 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
451 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
452 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
454 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
456 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
458 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
460 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
462 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
464 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
466 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
468 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
470 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
472 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
474 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
476 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
478 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
480 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
482 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
484 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
486 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
488 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
489 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
490 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
491 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
492 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
493 /* Engine CKV - Add a new CKEK used to encrypt keys. */
494 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
495 /* Engine CKV - Delete a previously added CKEK. */
496 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
497 /* Engine CKV - Add a new key to the key vault. */
498 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
499 /* Engine CKV - Delete a key from the key vault. */
500 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
501 /* Engine CKV - Delete all keys from the key vault. */
502 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
503 /* Engine CKV - Get random data. */
504 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
505 /* Engine CKV - Generate and encrypt a new AES key. */
506 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
507 /* Engine CKV - Configure a label index with a label value. */
508 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
509 /* Engine - Query the available queue groups configuration. */
510 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
511 /* Engine - Query the queue groups assigned to a function. */
512 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
513 /* Engine - Query the available queue group meter profile configuration. */
514 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
515 /* Engine - Query the configuration of a queue group meter profile. */
516 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
517 /* Engine - Allocate a queue group meter profile. */
518 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
519 /* Engine - Free a queue group meter profile. */
520 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
521 /* Engine - Query the meters assigned to a queue group. */
522 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
523 /* Engine - Bind a queue group meter profile to a queue group. */
524 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
525 /* Engine - Unbind a queue group meter profile from a queue group. */
526 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
527 /* Engine - Bind a queue group to a function. */
528 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
529 /* Engine - Query the scheduling group configuration. */
530 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
531 /* Engine - Query the queue groups assigned to a scheduling group. */
532 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
533 /* Engine - Query the configuration of a scheduling group's meter profiles. */
534 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
535 /* Engine - Configure a scheduling group's meter profiles. */
536 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
537 /* Engine - Bind a queue group to a scheduling group. */
538 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
539 /* Engine - Unbind a queue group from its scheduling group. */
540 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
541 /* Engine - Query the Engine configuration. */
542 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
543 /* Engine - Configure the statistics accumulator for an Engine. */
544 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
545 /* Engine - Clear the statistics accumulator for an Engine. */
546 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
547 /* Engine - Query the statistics accumulator for an Engine. */
548 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
549 /* Engine - Allocate an Engine RQ. */
550 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
551 /* Engine - Free an Engine RQ. */
552 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
553 /* Engine - Allocate an Engine CQ. */
554 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
555 /* Engine - Free an Engine CQ. */
556 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
557 /* Engine - Allocate an NQ. */
558 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
559 /* Engine - Free an NQ. */
560 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
561 /* Engine - Set the on-die RQE credit update location. */
562 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
563 /* Engine - Query the engine function configuration. */
564 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
566 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
568 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
570 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
572 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
574 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
575 /* Configures the BW of any VF */
576 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
577 /* Queries the BW of any VF */
578 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
580 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
582 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
584 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
586 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
588 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
590 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
592 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
594 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
596 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
597 #define HWRM_DBG_DUMP UINT32_C(0xff14)
599 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
601 #define HWRM_DBG_CFG UINT32_C(0xff16)
603 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
605 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
607 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
609 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
611 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
613 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
615 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
617 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
619 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
620 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
621 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
622 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
623 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
624 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
625 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
626 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
627 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
628 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
629 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
630 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
631 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
632 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
633 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
634 #define HWRM_NVM_READ UINT32_C(0xfffd)
635 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
636 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
637 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
638 uint16_t unused_0[3];
639 } __attribute__((packed));
642 /* ret_codes (size:64b/8B) */
645 /* Request was successfully executed by the HWRM. */
646 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
647 /* The HWRM failed to execute the request. */
648 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
650 * The request contains invalid argument(s) or input
653 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
655 * The requester is not allowed to access the requested
656 * resource. This error code shall be provided in a
657 * response to a request to query or modify an existing
658 * resource that is not accessible by the requester.
660 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
662 * The HWRM is unable to allocate the requested resource.
663 * This code only applies to requests for HWRM resource
666 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
668 * Invalid combination of flags is specified in the
671 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
673 * Invalid combination of enables fields is specified in
676 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
678 * Request contains a required TLV that is not supported by
679 * the installed version of firmware.
681 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
683 * No firmware buffer available to accept the request. Driver
684 * should retry the request.
686 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
688 * This error code is only reported by firmware when some
689 * sub-option of a supported HWRM command is unsupported.
691 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
693 * This error code is only reported by firmware when the specific
694 * request is not able to process when the HOT reset in progress.
696 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
698 * This error code is only reported by firmware when the registered
699 * driver instances are not capable of hot reset.
701 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
703 * Generic HWRM execution error that represents an
706 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
708 * This value indicates that the HWRM response is in TLV format and
709 * should be interpreted as one or more TLVs starting with the
710 * hwrm_resp_hdr TLV. This value is not an indicatation of any error
711 * by itself, just an indicatation that the response should be parsed
712 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
714 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
716 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
717 /* Unsupported or invalid command */
718 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
719 #define HWRM_ERR_CODE_LAST \
720 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
721 uint16_t unused_0[3];
722 } __attribute__((packed));
725 /* hwrm_err_output (size:128b/16B) */
726 struct hwrm_err_output {
728 * Pass/Fail or error type
730 * Note: receiver to verify the in parameters, and fail the call
731 * with an error when appropriate
734 /* This field returns the type of original request. */
736 /* This field provides original sequence number of the command. */
739 * This field is the length of the response in bytes. The
740 * last byte of the response is a valid flag that will read
741 * as '1' when the command has been completely written to
745 /* debug info for this error response. */
747 /* debug info for this error response. */
750 * In the case of an error response, command specific error
751 * code is returned in this field.
755 * This field is used in Output records to indicate that the output
756 * is completely written to RAM. This field should be read as '1'
757 * to indicate that the output has been completely written.
758 * When writing a command completion or response to an internal processor,
759 * the order of writes has to be such that this field is written last.
762 } __attribute__((packed));
764 * Following is the signature for HWRM message field that indicates not
765 * applicable (All F's). Need to cast it the size of the field if needed.
767 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
768 /* hwrm_func_buf_rgtr */
769 #define HWRM_MAX_REQ_LEN 128
770 /* hwrm_cfa_flow_info */
771 #define HWRM_MAX_RESP_LEN 704
772 /* 7 bit indirection table index. */
773 #define HW_HASH_INDEX_SIZE 0x80
774 #define HW_HASH_KEY_SIZE 40
775 /* valid key for HWRM response */
776 #define HWRM_RESP_VALID_KEY 1
777 #define HWRM_VERSION_MAJOR 1
778 #define HWRM_VERSION_MINOR 10
779 #define HWRM_VERSION_UPDATE 0
780 /* non-zero means beta version */
781 #define HWRM_VERSION_RSVD 48
782 #define HWRM_VERSION_STR "1.10.0.48"
789 /* hwrm_ver_get_input (size:192b/24B) */
790 struct hwrm_ver_get_input {
791 /* The HWRM command request type. */
794 * The completion ring to send the completion event on. This should
795 * be the NQ ID returned from the `nq_alloc` HWRM command.
799 * The sequence ID is used by the driver for tracking multiple
800 * commands. This ID is treated as opaque data by the firmware and
801 * the value is returned in the `hwrm_resp_hdr` upon completion.
805 * The target ID of the command:
806 * * 0x0-0xFFF8 - The function ID
807 * * 0xFFF8-0xFFFE - Reserved for internal processors
812 * A physical address pointer pointing to a host buffer that the
813 * command's response data will be written. This can be either a host
814 * physical address (HPA) or a guest physical address (GPA) and must
815 * point to a physically contiguous block of memory.
819 * This field represents the major version of HWRM interface
820 * specification supported by the driver HWRM implementation.
821 * The interface major version is intended to change only when
822 * non backward compatible changes are made to the HWRM
823 * interface specification.
825 uint8_t hwrm_intf_maj;
827 * This field represents the minor version of HWRM interface
828 * specification supported by the driver HWRM implementation.
829 * A change in interface minor version is used to reflect
830 * significant backward compatible modification to HWRM
831 * interface specification.
832 * This can be due to addition or removal of functionality.
833 * HWRM interface specifications with the same major version
834 * but different minor versions are compatible.
836 uint8_t hwrm_intf_min;
838 * This field represents the update version of HWRM interface
839 * specification supported by the driver HWRM implementation.
840 * The interface update version is used to reflect minor
841 * changes or bug fixes to a released HWRM interface
844 uint8_t hwrm_intf_upd;
846 } __attribute__((packed));
848 /* hwrm_ver_get_output (size:1408b/176B) */
849 struct hwrm_ver_get_output {
850 /* The specific error status for the command. */
852 /* The HWRM command request type. */
854 /* The sequence ID from the original command. */
856 /* The length of the response data in number of bytes. */
859 * This field represents the major version of HWRM interface
860 * specification supported by the HWRM implementation.
861 * The interface major version is intended to change only when
862 * non backward compatible changes are made to the HWRM
863 * interface specification.
864 * A HWRM implementation that is compliant with this
865 * specification shall provide value of 1 in this field.
867 uint8_t hwrm_intf_maj_8b;
869 * This field represents the minor version of HWRM interface
870 * specification supported by the HWRM implementation.
871 * A change in interface minor version is used to reflect
872 * significant backward compatible modification to HWRM
873 * interface specification.
874 * This can be due to addition or removal of functionality.
875 * HWRM interface specifications with the same major version
876 * but different minor versions are compatible.
877 * A HWRM implementation that is compliant with this
878 * specification shall provide value of 2 in this field.
880 uint8_t hwrm_intf_min_8b;
882 * This field represents the update version of HWRM interface
883 * specification supported by the HWRM implementation.
884 * The interface update version is used to reflect minor
885 * changes or bug fixes to a released HWRM interface
887 * A HWRM implementation that is compliant with this
888 * specification shall provide value of 2 in this field.
890 uint8_t hwrm_intf_upd_8b;
891 uint8_t hwrm_intf_rsvd_8b;
893 * This field represents the major version of HWRM firmware.
894 * A change in firmware major version represents a major
897 uint8_t hwrm_fw_maj_8b;
899 * This field represents the minor version of HWRM firmware.
900 * A change in firmware minor version represents significant
901 * firmware functionality changes.
903 uint8_t hwrm_fw_min_8b;
905 * This field represents the build version of HWRM firmware.
906 * A change in firmware build version represents bug fixes
907 * to a released firmware.
909 uint8_t hwrm_fw_bld_8b;
911 * This field is a reserved field. This field can be used to
912 * represent firmware branches or customer specific releases
913 * tied to a specific (major,minor,update) version of the
916 uint8_t hwrm_fw_rsvd_8b;
918 * This field represents the major version of mgmt firmware.
919 * A change in major version represents a major release.
921 uint8_t mgmt_fw_maj_8b;
923 * This field represents the minor version of mgmt firmware.
924 * A change in minor version represents significant
925 * functionality changes.
927 uint8_t mgmt_fw_min_8b;
929 * This field represents the build version of mgmt firmware.
930 * A change in update version represents bug fixes.
932 uint8_t mgmt_fw_bld_8b;
934 * This field is a reserved field. This field can be used to
935 * represent firmware branches or customer specific releases
936 * tied to a specific (major,minor,update) version
938 uint8_t mgmt_fw_rsvd_8b;
940 * This field represents the major version of network
942 * A change in major version represents a major release.
944 uint8_t netctrl_fw_maj_8b;
946 * This field represents the minor version of network
948 * A change in minor version represents significant
949 * functionality changes.
951 uint8_t netctrl_fw_min_8b;
953 * This field represents the build version of network
955 * A change in update version represents bug fixes.
957 uint8_t netctrl_fw_bld_8b;
959 * This field is a reserved field. This field can be used to
960 * represent firmware branches or customer specific releases
961 * tied to a specific (major,minor,update) version
963 uint8_t netctrl_fw_rsvd_8b;
965 * This field is used to indicate device's capabilities and
968 uint32_t dev_caps_cfg;
970 * If set to 1, then secure firmware update behavior
972 * If set to 0, then secure firmware update behavior is
975 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
978 * If set to 1, then firmware based DCBX agent is supported.
979 * If set to 0, then firmware based DCBX agent capability
980 * is not supported on this device.
982 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
985 * If set to 1, then HWRM short command format is supported.
986 * If set to 0, then HWRM short command format is not supported.
988 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
991 * If set to 1, then HWRM short command format is required.
992 * If set to 0, then HWRM short command format is not required.
994 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
997 * If set to 1, then the KONG host mailbox channel is supported.
998 * If set to 0, then the KONG host mailbox channel is not supported.
999 * By default, this flag should be 0 for older version of core firmware.
1001 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1004 * If set to 1, then the 64bit flow handle is supported in addition to the
1005 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1006 * supported. By default, this flag should be 0 for older version of core firmware.
1008 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1011 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1012 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1013 * If set to 0, then filter types not supported.
1014 * By default, this flag should be 0 for older version of core firmware.
1016 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1019 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1020 * If set to 0, firmware can't supported virtio vSwitch offload model.
1021 * By default, this flag should be 0 for older version of core firmware.
1023 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1026 * If set to 1, firmware is capable to support trusted VF.
1027 * If set to 0, firmware is not capable to support trusted VF.
1028 * By default, this flag should be 0 for older version of core firmware.
1030 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1033 * If set to 1, firmware is capable to support flow aging.
1034 * If set to 0, firmware is not capable to support flow aging.
1035 * By default, this flag should be 0 for older version of core firmware.
1037 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1040 * If set to 1, firmware is capable to support advanced flow counters like,
1041 * Meter drop counters and EEM counters.
1042 * If set to 0, firmware is not capable to support advanced flow counters.
1043 * By default, this flag should be 0 for older version of core firmware.
1045 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1048 * If set to 1, the firmware is able to support the use of the CFA
1049 * Extended Exact Match(EEM) feature.
1050 * If set to 0, firmware is not capable to support the use of the
1052 * By default, this flag should be 0 for older version of core firmware.
1054 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1057 * If set to 1, the firmware is able to support advance CFA flow management
1058 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1059 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1061 * By default, this flag should be 0 for older version of core firmware.
1063 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1066 * This field represents the major version of RoCE firmware.
1067 * A change in major version represents a major release.
1069 uint8_t roce_fw_maj_8b;
1071 * This field represents the minor version of RoCE firmware.
1072 * A change in minor version represents significant
1073 * functionality changes.
1075 uint8_t roce_fw_min_8b;
1077 * This field represents the build version of RoCE firmware.
1078 * A change in update version represents bug fixes.
1080 uint8_t roce_fw_bld_8b;
1082 * This field is a reserved field. This field can be used to
1083 * represent firmware branches or customer specific releases
1084 * tied to a specific (major,minor,update) version
1086 uint8_t roce_fw_rsvd_8b;
1088 * This field represents the name of HWRM FW (ASCII chars
1089 * with NULL at the end).
1091 char hwrm_fw_name[16];
1093 * This field represents the name of mgmt FW (ASCII chars
1094 * with NULL at the end).
1096 char mgmt_fw_name[16];
1098 * This field represents the name of network control
1099 * firmware (ASCII chars with NULL at the end).
1101 char netctrl_fw_name[16];
1103 * This field is reserved for future use.
1104 * The responder should set it to 0.
1105 * The requester should ignore this field.
1107 uint8_t reserved2[16];
1109 * This field represents the name of RoCE FW (ASCII chars
1110 * with NULL at the end).
1112 char roce_fw_name[16];
1113 /* This field returns the chip number. */
1115 /* This field returns the revision of chip. */
1117 /* This field returns the chip metal number. */
1119 /* This field returns the bond id of the chip. */
1120 uint8_t chip_bond_id;
1121 /* This value indicates the type of platform used for chip implementation. */
1122 uint8_t chip_platform_type;
1124 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1125 /* FPGA platform of the chip. */
1126 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1127 /* Palladium platform of the chip. */
1128 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1129 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1130 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1132 * This field returns the maximum value of request window that
1133 * is supported by the HWRM. The request window is mapped
1134 * into device address space using MMIO.
1136 uint16_t max_req_win_len;
1138 * This field returns the maximum value of response buffer in
1141 uint16_t max_resp_len;
1143 * This field returns the default request timeout value in
1146 uint16_t def_req_timeout;
1148 * This field will indicate if any subsystems is not fully
1153 * If set to 1, device is not ready.
1154 * If set to 0, device is ready to accept all HWRM commands.
1156 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1158 * If set to 1, external version present.
1159 * If set to 0, external version not present.
1161 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1162 uint8_t unused_0[2];
1164 * For backward compatibility this field must be set to 1.
1165 * Older drivers might look for this field to be 1 before
1166 * processing the message.
1170 * This field represents the major version of HWRM interface
1171 * specification supported by the HWRM implementation.
1172 * The interface major version is intended to change only when
1173 * non backward compatible changes are made to the HWRM
1174 * interface specification. A HWRM implementation that is
1175 * compliant with this specification shall provide value of 1
1178 uint16_t hwrm_intf_major;
1180 * This field represents the minor version of HWRM interface
1181 * specification supported by the HWRM implementation.
1182 * A change in interface minor version is used to reflect
1183 * significant backward compatible modification to HWRM
1184 * interface specification. This can be due to addition or
1185 * removal of functionality. HWRM interface specifications
1186 * with the same major version but different minor versions are
1187 * compatible. A HWRM implementation that is compliant with
1188 * this specification shall provide value of 2 in this field.
1190 uint16_t hwrm_intf_minor;
1192 * This field represents the update version of HWRM interface
1193 * specification supported by the HWRM implementation. The
1194 * interface update version is used to reflect minor changes or
1195 * bug fixes to a released HWRM interface specification.
1196 * A HWRM implementation that is compliant with this
1197 * specification shall provide value of 2 in this field.
1199 uint16_t hwrm_intf_build;
1201 * This field represents the patch version of HWRM interface
1202 * specification supported by the HWRM implementation.
1204 uint16_t hwrm_intf_patch;
1206 * This field represents the major version of HWRM firmware.
1207 * A change in firmware major version represents a major
1210 uint16_t hwrm_fw_major;
1212 * This field represents the minor version of HWRM firmware.
1213 * A change in firmware minor version represents significant
1214 * firmware functionality changes.
1216 uint16_t hwrm_fw_minor;
1218 * This field represents the build version of HWRM firmware.
1219 * A change in firmware build version represents bug fixes to
1220 * a released firmware.
1222 uint16_t hwrm_fw_build;
1224 * This field is a reserved field.
1225 * This field can be used to represent firmware branches or customer
1226 * specific releases tied to a specific (major,minor,update) version
1227 * of the HWRM firmware.
1229 uint16_t hwrm_fw_patch;
1231 * This field represents the major version of mgmt firmware.
1232 * A change in major version represents a major release.
1234 uint16_t mgmt_fw_major;
1236 * This field represents the minor version of HWRM firmware.
1237 * A change in firmware minor version represents significant
1238 * firmware functionality changes.
1240 uint16_t mgmt_fw_minor;
1242 * This field represents the build version of mgmt firmware.
1243 * A change in update version represents bug fixes.
1245 uint16_t mgmt_fw_build;
1247 * This field is a reserved field. This field can be used to
1248 * represent firmware branches or customer specific releases
1249 * tied to a specific (major,minor,update) version.
1251 uint16_t mgmt_fw_patch;
1253 * This field represents the major version of network control
1254 * firmware. A change in major version represents
1257 uint16_t netctrl_fw_major;
1259 * This field represents the minor version of network control
1260 * firmware. A change in minor version represents significant
1261 * functionality changes.
1263 uint16_t netctrl_fw_minor;
1265 * This field represents the build version of network control
1266 * firmware. A change in update version represents bug fixes.
1268 uint16_t netctrl_fw_build;
1270 * This field is a reserved field. This field can be used to
1271 * represent firmware branches or customer specific releases
1272 * tied to a specific (major,minor,update) version
1274 uint16_t netctrl_fw_patch;
1276 * This field represents the major version of RoCE firmware.
1277 * A change in major version represents a major release.
1279 uint16_t roce_fw_major;
1281 * This field represents the minor version of RoCE firmware.
1282 * A change in minor version represents significant
1283 * functionality changes.
1285 uint16_t roce_fw_minor;
1287 * This field represents the build version of RoCE firmware.
1288 * A change in update version represents bug fixes.
1290 uint16_t roce_fw_build;
1292 * This field is a reserved field. This field can be used to
1293 * represent firmware branches or customer specific releases
1294 * tied to a specific (major,minor,update) version
1296 uint16_t roce_fw_patch;
1298 * This field returns the maximum extended request length acceptable
1299 * by the device which allows requests greater than mailbox size when
1300 * used with the short cmd request format.
1302 uint16_t max_ext_req_len;
1303 uint8_t unused_1[5];
1305 * This field is used in Output records to indicate that the output
1306 * is completely written to RAM. This field should be read as '1'
1307 * to indicate that the output has been completely written.
1308 * When writing a command completion or response to an internal processor,
1309 * the order of writes has to be such that this field is written last.
1312 } __attribute__((packed));
1314 /* bd_base (size:64b/8B) */
1317 /* This value identifies the type of buffer descriptor. */
1318 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1319 #define BD_BASE_TYPE_SFT 0
1321 * Indicates that this BD is 16B long and is used for
1322 * normal L2 packet transmission.
1324 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1326 * Indicates that this BD is 1BB long and is an empty
1327 * TX BD. Not valid for use by the driver.
1329 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1331 * Indicates that this BD is 16B long and is an RX Producer
1332 * (ie. empty) buffer descriptor.
1334 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1336 * Indicates that this BD is 16B long and is an RX
1337 * Producer Buffer BD.
1339 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1341 * Indicates that this BD is 16B long and is an
1342 * RX Producer Assembly Buffer Descriptor.
1344 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1346 * Indicates that this BD is 32B long and is used for
1347 * normal L2 packet transmission.
1349 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1351 * Indicates that this BD is 32B long and is used for
1352 * L2 packet transmission for small packets that require
1355 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1356 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1357 uint8_t unused_1[7];
1358 } __attribute__((packed));
1360 /* tx_bd_short (size:128b/16B) */
1361 struct tx_bd_short {
1363 * All bits in this field must be valid on the first BD of a packet.
1364 * Only the packet_end bit must be valid for the remaining BDs
1367 uint16_t flags_type;
1368 /* This value identifies the type of buffer descriptor. */
1369 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1370 #define TX_BD_SHORT_TYPE_SFT 0
1372 * Indicates that this BD is 16B long and is used for
1373 * normal L2 packet transmission.
1375 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1376 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1378 * All bits in this field must be valid on the first BD of a packet.
1379 * Only the packet_end bit must be valid for the remaining BDs
1382 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1383 #define TX_BD_SHORT_FLAGS_SFT 6
1385 * If set to 1, the packet ends with the data in the buffer
1386 * pointed to by this descriptor. This flag must be
1387 * valid on every BD.
1389 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1391 * If set to 1, the device will not generate a completion for
1392 * this transmit packet unless there is an error in it's
1395 * is set to 0, then the packet will be completed normally.
1397 * This bit must be valid only on the first BD of a packet.
1399 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1401 * This value indicates how many 16B BD locations are consumed
1402 * in the ring by this packet.
1403 * A value of 1 indicates that this BD is the only BD (and that
1404 * the it is a short BD). A value
1405 * of 3 indicates either 3 short BDs or 1 long BD and one short
1406 * BD in the packet. A value of 0 indicates
1407 * that there are 32 BD locations in the packet (the maximum).
1409 * This field is valid only on the first BD of a packet.
1411 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1412 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1414 * This value is a hint for the length of the entire packet.
1415 * It is used by the chip to optimize internal processing.
1417 * The packet will be dropped if the hint is too short.
1419 * This field is valid only on the first BD of a packet.
1421 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1422 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1423 /* indicates packet length < 512B */
1424 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1425 /* indicates 512 <= packet length < 1KB */
1426 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1427 /* indicates 1KB <= packet length < 2KB */
1428 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1429 /* indicates packet length >= 2KB */
1430 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1431 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1432 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1434 * If set to 1, the device immediately updates the Send Consumer
1435 * Index after the buffer associated with this descriptor has
1436 * been transferred via DMA to NIC memory from host memory. An
1437 * interrupt may or may not be generated according to the state
1438 * of the interrupt avoidance mechanisms. If this bit
1439 * is set to 0, then the Consumer Index is only updated as soon
1440 * as one of the host interrupt coalescing conditions has been met.
1442 * This bit must be valid on the first BD of a packet.
1444 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1446 * This is the length of the host physical buffer this BD describes
1449 * This field must be valid on all BDs of a packet.
1453 * The opaque data field is pass through to the completion and can be
1454 * used for any data that the driver wants to associate with the
1457 * This field must be valid on the first BD of a packet.
1461 * This is the host physical address for the portion of the packet
1462 * described by this TX BD.
1464 * This value must be valid on all BDs of a packet.
1467 } __attribute__((packed));
1469 /* tx_bd_long (size:128b/16B) */
1471 /* This value identifies the type of buffer descriptor. */
1472 uint16_t flags_type;
1474 * This value indicates the type of buffer descriptor.
1477 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1478 #define TX_BD_LONG_TYPE_SFT 0
1480 * Indicates that this BD is 32B long and is used for
1481 * normal L2 packet transmission.
1483 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1484 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1486 * All bits in this field must be valid on the first BD of a packet.
1487 * Only the packet_end bit must be valid for the remaining BDs
1490 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1491 #define TX_BD_LONG_FLAGS_SFT 6
1493 * If set to 1, the packet ends with the data in the buffer
1494 * pointed to by this descriptor. This flag must be
1495 * valid on every BD.
1497 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1499 * If set to 1, the device will not generate a completion for
1500 * this transmit packet unless there is an error in it's
1503 * is set to 0, then the packet will be completed normally.
1505 * This bit must be valid only on the first BD of a packet.
1507 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1509 * This value indicates how many 16B BD locations are consumed
1510 * in the ring by this packet.
1511 * A value of 1 indicates that this BD is the only BD (and that
1512 * the it is a short BD). A value
1513 * of 3 indicates either 3 short BDs or 1 long BD and one short
1514 * BD in the packet. A value of 0 indicates
1515 * that there are 32 BD locations in the packet (the maximum).
1517 * This field is valid only on the first BD of a packet.
1519 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1520 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1522 * This value is a hint for the length of the entire packet.
1523 * It is used by the chip to optimize internal processing.
1525 * The packet will be dropped if the hint is too short.
1527 * This field is valid only on the first BD of a packet.
1529 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1530 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1531 /* indicates packet length < 512B */
1532 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1533 /* indicates 512 <= packet length < 1KB */
1534 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1535 /* indicates 1KB <= packet length < 2KB */
1536 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1537 /* indicates packet length >= 2KB */
1538 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1539 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1541 * If set to 1, the device immediately updates the Send Consumer
1542 * Index after the buffer associated with this descriptor has
1543 * been transferred via DMA to NIC memory from host memory. An
1544 * interrupt may or may not be generated according to the state
1545 * of the interrupt avoidance mechanisms. If this bit
1546 * is set to 0, then the Consumer Index is only updated as soon
1547 * as one of the host interrupt coalescing conditions has been met.
1549 * This bit must be valid on the first BD of a packet.
1551 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1553 * This is the length of the host physical buffer this BD describes
1556 * This field must be valid on all BDs of a packet.
1560 * The opaque data field is pass through to the completion and can be
1561 * used for any data that the driver wants to associate with the
1564 * This field must be valid on the first BD of a packet.
1568 * This is the host physical address for the portion of the packet
1569 * described by this TX BD.
1571 * This value must be valid on all BDs of a packet.
1574 } __attribute__((packed));
1576 /* Last 16 bytes of tx_bd_long. */
1577 /* tx_bd_long_hi (size:128b/16B) */
1578 struct tx_bd_long_hi {
1580 * All bits in this field must be valid on the first BD of a packet.
1581 * Their value on other BDs of the packet will be ignored.
1585 * If set to 1, the controller replaces the TCP/UPD checksum
1586 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1587 * checksum field of the encapsulated TCP/UDP packets with the
1588 * hardware calculated TCP/UDP checksum for the packet associated
1589 * with this descriptor. The flag is ignored if the LSO flag is set.
1591 * This bit must be valid on the first BD of a packet.
1593 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1595 * If set to 1, the controller replaces the IP checksum of the
1596 * normal packets, or the inner IP checksum of the encapsulated
1597 * packets with the hardware calculated IP checksum for the
1598 * packet associated with this descriptor.
1600 * This bit must be valid on the first BD of a packet.
1602 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1604 * If set to 1, the controller will not append an Ethernet CRC
1605 * to the end of the frame.
1607 * This bit must be valid on the first BD of a packet.
1609 * Packet must be 64B or longer when this flag is set. It is not
1610 * useful to use this bit with any form of TX offload such as
1611 * CSO or LSO. The intent is that the packet from the host already
1612 * has a valid Ethernet CRC on the packet.
1614 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1616 * If set to 1, the device will record the time at which the packet
1617 * was actually transmitted at the TX MAC.
1619 * This bit must be valid on the first BD of a packet.
1621 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1623 * If set to 1, The controller replaces the tunnel IP checksum
1624 * field with hardware calculated IP checksum for the IP header
1625 * of the packet associated with this descriptor.
1627 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1628 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1629 * bit is set, outer UDP checksum will be calculated for the following
1631 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1632 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1633 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1634 * checksum will not be calculated.
1635 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1636 * as part of LSO operation.
1638 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1640 * If set to 1, the device will treat this packet with LSO(Large
1641 * Send Offload) processing for both normal or encapsulated
1642 * packets, which is a form of TCP segmentation. When this bit
1643 * is 1, the hdr_size and mss fields must be valid. The driver
1644 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1645 * flags since the controller will replace the appropriate
1646 * checksum fields for segmented packets.
1648 * When this bit is 1, the hdr_size and mss fields must be valid.
1650 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1652 * If set to zero when LSO is '1', then the IPID will be treated
1653 * as a 16b number and will be wrapped if it exceeds a value of
1656 * If set to one when LSO is '1', then the IPID will be treated
1657 * as a 15b number and will be wrapped if it exceeds a value 0f
1660 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1662 * If set to zero when LSO is '1', then the IPID of the tunnel
1663 * IP header will not be modified during LSO operations.
1665 * If set to one when LSO is '1', then the IPID of the tunnel
1666 * IP header will be incremented for each subsequent segment of an
1669 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1672 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1674 * If set to '1', then the RoCE ICRC will be appended to the
1675 * packet. Packet must be a valid RoCE format packet.
1677 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1679 * If set to '1', then the FCoE CRC will be appended to the
1680 * packet. Packet must be a valid FCoE format packet.
1682 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1685 * When LSO is '1', this field must contain the offset of the
1686 * TCP payload from the beginning of the packet in as
1687 * 16b words. In case of encapsulated/tunneling packet, this field
1688 * contains the offset of the inner TCP payload from beginning of the
1689 * packet as 16-bit words.
1691 * This value must be valid on the first BD of a packet.
1693 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1694 #define TX_BD_LONG_HDR_SIZE_SFT 0
1697 * This is the MSS value that will be used to do the LSO processing.
1698 * The value is the length in bytes of the TCP payload for each
1699 * segment generated by the LSO operation.
1701 * This value must be valid on the first BD of a packet.
1703 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1704 #define TX_BD_LONG_MSS_SFT 0
1707 * This value selects a CFA action to perform on the packet.
1708 * Set this value to zero if no CFA action is desired.
1710 * This value must be valid on the first BD of a packet.
1712 uint16_t cfa_action;
1714 * This value is action meta-data that defines CFA edit operations
1715 * that are done in addition to any action editing.
1718 /* When key=1, This is the VLAN tag VID value. */
1719 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1720 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1721 /* When key=1, This is the VLAN tag DE value. */
1722 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1723 /* When key=1, This is the VLAN tag PRI value. */
1724 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1725 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1726 /* When key=1, This is the VLAN tag TPID select value. */
1727 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1728 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1730 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1732 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1734 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1736 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1738 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1739 /* Value programmed in CFA VLANTPID register. */
1740 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1741 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1742 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1743 /* When key=1, This is the VLAN tag TPID select value. */
1744 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1745 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1747 * This field identifies the type of edit to be performed
1750 * This value must be valid on the first BD of a packet.
1752 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1753 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1755 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1757 * - meta[17:16] - TPID select value (0 = 0x8100).
1758 * - meta[15:12] - PRI/DE value.
1759 * - meta[11:0] - VID value.
1761 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1762 #define TX_BD_LONG_CFA_META_KEY_LAST \
1763 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1764 } __attribute__((packed));
1767 * This structure is used to inform the NIC of packet data that needs to be
1768 * transmitted with additional processing that requires extra data such as
1769 * VLAN insertion plus attached inline data. This BD type may be used to
1770 * improve latency for small packets needing the additional extended features
1771 * supported by long BDs.
1773 /* tx_bd_long_inline (size:256b/32B) */
1774 struct tx_bd_long_inline {
1775 uint16_t flags_type;
1776 /* This value identifies the type of buffer descriptor. */
1777 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1778 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1780 * This type of BD is 32B long and is used for inline L2 packet
1783 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1784 #define TX_BD_LONG_INLINE_TYPE_LAST \
1785 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1787 * All bits in this field may be set on the first BD of a packet.
1788 * Only the packet_end bit may be set in non-first BDs.
1790 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1791 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1793 * If set to 1, the packet ends with the data in the buffer
1794 * pointed to by this descriptor. This flag must be
1795 * valid on every BD.
1797 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1799 * If set to 1, the device will not generate a completion for
1800 * this transmit packet unless there is an error in its processing.
1801 * If this bit is set to 0, then the packet will be completed
1804 * This bit may be set only on the first BD of a packet.
1806 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1808 * This value indicates how many 16B BD locations are consumed
1809 * in the ring by this packet, including the BD and inline
1812 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1813 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1814 /* This field is deprecated. */
1815 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1816 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1818 * If set to 1, the device immediately updates the Send Consumer
1819 * Index after the buffer associated with this descriptor has
1820 * been transferred via DMA to NIC memory from host memory. An
1821 * interrupt may or may not be generated according to the state
1822 * of the interrupt avoidance mechanisms. If this bit
1823 * is set to 0, then the Consumer Index is only updated as soon
1824 * as one of the host interrupt coalescing conditions has been met.
1826 * This bit must be valid on the first BD of a packet.
1828 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1830 * This is the length of the inline data, not including BD length, in
1832 * The maximum value is 480.
1834 * This field must be valid on all BDs of a packet.
1838 * The opaque data field is passed through to the completion and can be
1839 * used for any data that the driver wants to associate with the transmit
1842 * This field must be valid on the first BD of a packet.
1847 * All bits in this field must be valid on the first BD of a packet.
1848 * Their value on other BDs of the packet is ignored.
1852 * If set to 1, the controller replaces the TCP/UPD checksum
1853 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1854 * checksum field of the encapsulated TCP/UDP packets with the
1855 * hardware calculated TCP/UDP checksum for the packet associated
1856 * with this descriptor. The flag is ignored if the LSO flag is set.
1858 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1860 * If set to 1, the controller replaces the IP checksum of the
1861 * normal packets, or the inner IP checksum of the encapsulated
1862 * packets with the hardware calculated IP checksum for the
1863 * packet associated with this descriptor.
1865 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1867 * If set to 1, the controller will not append an Ethernet CRC
1868 * to the end of the frame.
1870 * Packet must be 64B or longer when this flag is set. It is not
1871 * useful to use this bit with any form of TX offload such as
1872 * CSO or LSO. The intent is that the packet from the host already
1873 * has a valid Ethernet CRC on the packet.
1875 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1877 * If set to 1, the device will record the time at which the packet
1878 * was actually transmitted at the TX MAC.
1880 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1882 * If set to 1, the controller replaces the tunnel IP checksum
1883 * field with hardware calculated IP checksum for the IP header
1884 * of the packet associated with this descriptor. The hardware
1885 * updates an outer UDP checksum if it is non-zero.
1887 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1889 * This bit must be 0 for BDs of this type. LSO is not supported with
1892 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1893 /* Since LSO is not supported with inline BDs, this bit is not used. */
1894 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1895 /* Since LSO is not supported with inline BDs, this bit is not used. */
1896 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1898 * If set to '1', then the RoCE ICRC will be appended to the
1899 * packet. Packet must be a valid RoCE format packet.
1901 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1903 * If set to '1', then the FCoE CRC will be appended to the
1904 * packet. Packet must be a valid FCoE format packet.
1906 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1911 * This value selects a CFA action to perform on the packet.
1912 * Set this value to zero if no CFA action is desired.
1914 * This value must be valid on the first BD of a packet.
1916 uint16_t cfa_action;
1918 * This value is action meta-data that defines CFA edit operations
1919 * that are done in addition to any action editing.
1922 /* When key = 1, this is the VLAN tag VID value. */
1923 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1924 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1925 /* When key = 1, this is the VLAN tag DE value. */
1926 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1927 /* When key = 1, this is the VLAN tag PRI value. */
1928 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1929 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
1930 /* When key = 1, this is the VLAN tag TPID select value. */
1931 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1932 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
1934 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
1935 (UINT32_C(0x0) << 16)
1937 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
1938 (UINT32_C(0x1) << 16)
1940 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
1941 (UINT32_C(0x2) << 16)
1943 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
1944 (UINT32_C(0x3) << 16)
1946 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
1947 (UINT32_C(0x4) << 16)
1948 /* Value programmed in CFA VLANTPID register. */
1949 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
1950 (UINT32_C(0x5) << 16)
1951 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
1952 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
1953 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
1955 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
1957 * This field identifies the type of edit to be performed
1960 * This value must be valid on the first BD of a packet.
1962 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
1963 UINT32_C(0xf0000000)
1964 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
1966 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
1967 (UINT32_C(0x0) << 28)
1969 * - meta[17:16] - TPID select value (0 = 0x8100).
1970 * - meta[15:12] - PRI/DE value.
1971 * - meta[11:0] - VID value.
1973 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
1974 (UINT32_C(0x1) << 28)
1975 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
1976 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
1977 } __attribute__((packed));
1979 /* tx_bd_empty (size:128b/16B) */
1980 struct tx_bd_empty {
1981 /* This value identifies the type of buffer descriptor. */
1983 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1984 #define TX_BD_EMPTY_TYPE_SFT 0
1986 * Indicates that this BD is 1BB long and is an empty
1987 * TX BD. Not valid for use by the driver.
1989 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1990 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1991 uint8_t unused_1[3];
1993 uint8_t unused_3[3];
1994 uint8_t unused_4[8];
1995 } __attribute__((packed));
1997 /* rx_prod_pkt_bd (size:128b/16B) */
1998 struct rx_prod_pkt_bd {
1999 /* This value identifies the type of buffer descriptor. */
2000 uint16_t flags_type;
2001 /* This value identifies the type of buffer descriptor. */
2002 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2003 #define RX_PROD_PKT_BD_TYPE_SFT 0
2005 * Indicates that this BD is 16B long and is an RX Producer
2006 * (ie. empty) buffer descriptor.
2008 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2009 #define RX_PROD_PKT_BD_TYPE_LAST \
2010 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2011 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2012 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2014 * If set to 1, the packet will be placed at the address plus
2015 * 2B. The 2 Bytes of padding will be written as zero.
2017 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2019 * If set to 1, the packet write will be padded out to the
2020 * nearest cache-line with zero value padding.
2022 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2024 * This value is the number of additional buffers in the ring that
2025 * describe the buffer space to be consumed for the this packet.
2026 * If the value is zero, then the packet must fit within the
2027 * space described by this BD. If this value is 1 or more, it
2028 * indicates how many additional "buffer" BDs are in the ring
2029 * immediately following this BD to be used for the same
2032 * Even if the packet to be placed does not need all the
2033 * additional buffers, they will be consumed anyway.
2035 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2036 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2038 * This is the length in Bytes of the host physical buffer where
2039 * data for the packet may be placed in host memory.
2043 * The opaque data field is pass through to the completion and can be
2044 * used for any data that the driver wants to associate with this
2045 * receive buffer set.
2049 * This is the host physical address where data for the packet may
2050 * by placed in host memory.
2053 } __attribute__((packed));
2055 /* rx_prod_bfr_bd (size:128b/16B) */
2056 struct rx_prod_bfr_bd {
2057 /* This value identifies the type of buffer descriptor. */
2058 uint16_t flags_type;
2059 /* This value identifies the type of buffer descriptor. */
2060 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2061 #define RX_PROD_BFR_BD_TYPE_SFT 0
2063 * Indicates that this BD is 16B long and is an RX
2064 * Producer Buffer BD.
2066 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2067 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2068 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2069 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2071 * This is the length in Bytes of the host physical buffer where
2072 * data for the packet may be placed in host memory.
2075 /* This field is not used. */
2078 * This is the host physical address where data for the packet may
2079 * by placed in host memory.
2082 } __attribute__((packed));
2084 /* rx_prod_agg_bd (size:128b/16B) */
2085 struct rx_prod_agg_bd {
2086 /* This value identifies the type of buffer descriptor. */
2087 uint16_t flags_type;
2088 /* This value identifies the type of buffer descriptor. */
2089 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2090 #define RX_PROD_AGG_BD_TYPE_SFT 0
2092 * Indicates that this BD is 16B long and is an
2093 * RX Producer Assembly Buffer Descriptor.
2095 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2096 #define RX_PROD_AGG_BD_TYPE_LAST \
2097 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2098 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2099 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2101 * If set to 1, the packet write will be padded out to the
2102 * nearest cache-line with zero value padding.
2104 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2106 * This is the length in Bytes of the host physical buffer where
2107 * data for the packet may be placed in host memory.
2111 * The opaque data field is pass through to the completion and can be
2112 * used for any data that the driver wants to associate with this
2113 * receive assembly buffer.
2117 * This is the host physical address where data for the packet may
2118 * by placed in host memory.
2121 } __attribute__((packed));
2123 /* cmpl_base (size:128b/16B) */
2127 * This field indicates the exact type of the completion.
2128 * By convention, the LSB identifies the length of the
2129 * record in 16B units. Even values indicate 16B
2130 * records. Odd values indicate 32B
2133 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2134 #define CMPL_BASE_TYPE_SFT 0
2137 * Completion of TX packet. Length = 16B
2139 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2142 * Completion of and L2 RX packet. Length = 32B
2144 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2146 * RX Aggregation Buffer completion :
2147 * Completion of an L2 aggregation buffer in support of
2148 * TPA, HDS, or Jumbo packet completion. Length = 16B
2150 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2152 * RX L2 TPA Start Completion:
2153 * Completion at the beginning of a TPA operation.
2156 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2158 * RX L2 TPA End Completion:
2159 * Completion at the end of a TPA operation.
2162 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2164 * Statistics Ejection Completion:
2165 * Completion of statistics data ejection buffer.
2168 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2170 * HWRM Command Completion:
2171 * Completion of an HWRM command.
2173 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2174 /* Forwarded HWRM Request */
2175 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2176 /* Forwarded HWRM Response */
2177 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2178 /* HWRM Asynchronous Event Information */
2179 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2180 /* CQ Notification */
2181 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2182 /* SRQ Threshold Event */
2183 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2184 /* DBQ Threshold Event */
2185 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2186 /* QP Async Notification */
2187 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2188 /* Function Async Notification */
2189 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2190 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2196 * This value is written by the NIC such that it will be different
2197 * for each pass through the completion queue. The even passes
2198 * will write 1. The odd passes will write 0.
2201 #define CMPL_BASE_V UINT32_C(0x1)
2202 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2203 #define CMPL_BASE_INFO3_SFT 1
2206 } __attribute__((packed));
2208 /* tx_cmpl (size:128b/16B) */
2210 uint16_t flags_type;
2212 * This field indicates the exact type of the completion.
2213 * By convention, the LSB identifies the length of the
2214 * record in 16B units. Even values indicate 16B
2215 * records. Odd values indicate 32B
2218 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2219 #define TX_CMPL_TYPE_SFT 0
2222 * Completion of TX packet. Length = 16B
2224 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2225 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2226 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2227 #define TX_CMPL_FLAGS_SFT 6
2229 * When this bit is '1', it indicates a packet that has an
2230 * error of some type. Type of error is indicated in
2233 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2235 * When this bit is '1', it indicates that the packet completed
2236 * was transmitted using the push acceleration data provided
2237 * by the driver. When this bit is '0', it indicates that the
2238 * packet had not push acceleration data written or was executed
2239 * as a normal packet even though push data was provided.
2241 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2242 /* unused1 is 16 b */
2245 * This is a copy of the opaque field from the first TX BD of this
2246 * transmitted packet.
2251 * This value is written by the NIC such that it will be different
2252 * for each pass through the completion queue. The even passes
2253 * will write 1. The odd passes will write 0.
2255 #define TX_CMPL_V UINT32_C(0x1)
2256 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2257 #define TX_CMPL_ERRORS_SFT 1
2259 * This error indicates that there was some sort of problem
2260 * with the BDs for the packet.
2262 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2263 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2265 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2268 * BDs were not formatted correctly.
2270 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2271 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2272 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2274 * When this bit is '1', it indicates that the length of
2275 * the packet was zero. No packet was transmitted.
2277 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2279 * When this bit is '1', it indicates that the packet
2280 * was longer than the programmed limit in TDI. No
2281 * packet was transmitted.
2283 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2285 * When this bit is '1', it indicates that one or more of the
2286 * BDs associated with this packet generated a PCI error.
2287 * This probably means the address was not valid.
2289 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2291 * When this bit is '1', it indicates that the packet was longer
2292 * than indicated by the hint. No packet was transmitted.
2294 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2296 * When this bit is '1', it indicates that the packet was
2297 * dropped due to Poison TLP error on one or more of the
2298 * TLPs in the PXP completion.
2300 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2301 /* unused2 is 16 b */
2303 /* unused3 is 32 b */
2305 } __attribute__((packed));
2307 /* rx_pkt_cmpl (size:128b/16B) */
2308 struct rx_pkt_cmpl {
2309 uint16_t flags_type;
2311 * This field indicates the exact type of the completion.
2312 * By convention, the LSB identifies the length of the
2313 * record in 16B units. Even values indicate 16B
2314 * records. Odd values indicate 32B
2317 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2318 #define RX_PKT_CMPL_TYPE_SFT 0
2321 * Completion of and L2 RX packet. Length = 32B
2323 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2324 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2325 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2326 #define RX_PKT_CMPL_FLAGS_SFT 6
2328 * When this bit is '1', it indicates a packet that has an
2329 * error of some type. Type of error is indicated in
2332 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2333 /* This field indicates how the packet was placed in the buffer. */
2334 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2335 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2338 * Packet was placed using normal algorithm.
2340 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2343 * Packet was placed using jumbo algorithm.
2345 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2347 * Header/Data Separation:
2348 * Packet was placed using Header/Data separation algorithm.
2349 * The separation location is indicated by the itype field.
2351 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2352 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2353 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2354 /* This bit is '1' if the RSS field in this completion is valid. */
2355 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2357 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2359 * This value indicates what the inner packet determined for the
2362 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2363 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2366 * Indicates that the packet type was not known.
2368 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2369 (UINT32_C(0x0) << 12)
2372 * Indicates that the packet was an IP packet, but further
2373 * classification was not possible.
2375 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2376 (UINT32_C(0x1) << 12)
2379 * Indicates that the packet was IP and TCP.
2380 * This indicates that the payload_offset field is valid.
2382 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2383 (UINT32_C(0x2) << 12)
2386 * Indicates that the packet was IP and UDP.
2387 * This indicates that the payload_offset field is valid.
2389 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2390 (UINT32_C(0x3) << 12)
2393 * Indicates that the packet was recognized as a FCoE.
2394 * This also indicates that the payload_offset field is valid.
2396 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2397 (UINT32_C(0x4) << 12)
2400 * Indicates that the packet was recognized as a RoCE.
2401 * This also indicates that the payload_offset field is valid.
2403 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2404 (UINT32_C(0x5) << 12)
2407 * Indicates that the packet was recognized as ICMP.
2408 * This indicates that the payload_offset field is valid.
2410 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2411 (UINT32_C(0x7) << 12)
2413 * PtP packet wo/timestamp:
2414 * Indicates that the packet was recognized as a PtP
2417 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2418 (UINT32_C(0x8) << 12)
2420 * PtP packet w/timestamp:
2421 * Indicates that the packet was recognized as a PtP
2422 * packet and that a timestamp was taken for the packet.
2424 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2425 (UINT32_C(0x9) << 12)
2426 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2427 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2429 * This is the length of the data for the packet stored in the
2430 * buffer(s) identified by the opaque value. This includes
2431 * the packet BD and any associated buffer BDs. This does not include
2432 * the the length of any data places in aggregation BDs.
2436 * This is a copy of the opaque field from the RX BD this completion
2440 uint8_t agg_bufs_v1;
2442 * This value is written by the NIC such that it will be different
2443 * for each pass through the completion queue. The even passes
2444 * will write 1. The odd passes will write 0.
2446 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2448 * This value is the number of aggregation buffers that follow this
2449 * entry in the completion ring that are a part of this packet.
2450 * If the value is zero, then the packet is completely contained
2451 * in the buffer space provided for the packet in the RX ring.
2453 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2454 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2455 /* unused1 is 2 b */
2456 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2457 #define RX_PKT_CMPL_UNUSED1_SFT 6
2459 * This is the RSS hash type for the packet. The value is packed
2460 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2462 * The value of tuple_extrac_op provides the information about
2463 * what fields the hash was computed on.
2464 * * 0: The RSS hash was computed over source IP address,
2465 * destination IP address, source port, and destination port of inner
2466 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2467 * the packet headers are considered inner packet headers for the RSS
2468 * hash computation purpose.
2469 * * 1: The RSS hash was computed over source IP address and destination
2470 * IP address of inner IP header. Note: For non-tunneled packets,
2471 * the packet headers are considered inner packet headers for the RSS
2472 * hash computation purpose.
2473 * * 2: The RSS hash was computed over source IP address,
2474 * destination IP address, source port, and destination port of
2475 * IP and TCP or UDP headers of outer tunnel headers.
2476 * Note: For non-tunneled packets, this value is not applicable.
2477 * * 3: The RSS hash was computed over source IP address and
2478 * destination IP address of IP header of outer tunnel headers.
2479 * Note: For non-tunneled packets, this value is not applicable.
2481 * Note that 4-tuples values listed above are applicable
2482 * for layer 4 protocols supported and enabled for RSS in the hardware,
2483 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2484 * enabled for TCP traffic only, then the values of tuple_extract_op
2485 * corresponding to 4-tuples are only valid for TCP traffic.
2487 uint8_t rss_hash_type;
2489 * This value indicates the offset in bytes from the beginning of the packet
2490 * where the inner payload starts. This value is valid for TCP, UDP,
2491 * FCoE, and RoCE packets.
2493 * A value of zero indicates that header is 256B into the packet.
2495 uint8_t payload_offset;
2496 /* unused2 is 8 b */
2499 * This value is the RSS hash value calculated for the packet
2500 * based on the mode bits and key value in the VNIC.
2503 } __attribute__((packed));
2505 /* Last 16 bytes of rx_pkt_cmpl. */
2506 /* rx_pkt_cmpl_hi (size:128b/16B) */
2507 struct rx_pkt_cmpl_hi {
2510 * This indicates that the ip checksum was calculated for the
2511 * inner packet and that the ip_cs_error field indicates if there
2514 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2516 * This indicates that the TCP, UDP or ICMP checksum was
2517 * calculated for the inner packet and that the l4_cs_error field
2518 * indicates if there was an error.
2520 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2522 * This indicates that the ip checksum was calculated for the
2523 * tunnel header and that the t_ip_cs_error field indicates if there
2526 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2528 * This indicates that the UDP checksum was
2529 * calculated for the tunnel packet and that the t_l4_cs_error field
2530 * indicates if there was an error.
2532 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2533 /* This value indicates what format the metadata field is. */
2534 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2535 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2536 /* No metadata informtaion. Value is zero. */
2537 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2538 (UINT32_C(0x0) << 4)
2540 * The metadata field contains the VLAN tag and TPID value.
2541 * - metadata[11:0] contains the vlan VID value.
2542 * - metadata[12] contains the vlan DE value.
2543 * - metadata[15:13] contains the vlan PRI value.
2544 * - metadata[31:16] contains the vlan TPID value.
2546 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2547 (UINT32_C(0x1) << 4)
2549 * If ext_meta_format is equal to 1, the metadata field
2550 * contains the lower 16b of the tunnel ID value, justified
2552 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2553 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2554 * - NVGRE = TNI[23:0] -> Tenant Network ID
2555 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
2556 * - IPV4 = 0 (not populated)
2557 * - IPV6 = Flow Label[19:0]
2558 * - PPPoE = sessionID[15:0]
2559 * - MPLs = Outer label[19:0]
2560 * - UPAR = Selected[31:0] with bit mask
2562 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2563 (UINT32_C(0x2) << 4)
2565 * if ext_meta_format is equal to 1, metadata field contains
2566 * 16b metadata from the prepended header (chdr_data).
2568 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2569 (UINT32_C(0x3) << 4)
2571 * If ext_meta_format is equal to 1, the metadata field contains
2572 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2574 * - metadata[8:0] contains the outer_l3_offset.
2575 * - metadata[17:9] contains the inner_l2_offset.
2576 * - metadata[26:18] contains the inner_l3_offset.
2577 * - metadata[31:27] contains the inner_l4_size.
2579 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2580 (UINT32_C(0x4) << 4)
2581 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2582 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2584 * This field indicates the IP type for the inner-most IP header.
2585 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2586 * This value is only valid if itype indicates a packet
2587 * with an IP header.
2589 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2591 * This indicates that the complete 1's complement checksum was
2592 * calculated for the packet.
2594 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2596 * The combination of this value and meta_format indicated what
2597 * format the metadata field is.
2599 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2600 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2602 * This value is the complete 1's complement checksum calculated from
2603 * the start of the outer L3 header to the end of the packet (not
2604 * including the ethernet crc). It is valid when the
2605 * 'complete_checksum_calc' flag is set.
2607 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2608 UINT32_C(0xffff0000)
2609 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2611 * This is data from the CFA block as indicated by the meta_format
2615 /* When meta_format=1, this value is the VLAN VID. */
2616 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2617 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2618 /* When meta_format=1, this value is the VLAN DE. */
2619 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2620 /* When meta_format=1, this value is the VLAN PRI. */
2621 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2622 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2623 /* When meta_format=1, this value is the VLAN TPID. */
2624 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2625 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2628 * This value is written by the NIC such that it will be different
2629 * for each pass through the completion queue. The even passes
2630 * will write 1. The odd passes will write 0.
2632 #define RX_PKT_CMPL_V2 \
2634 #define RX_PKT_CMPL_ERRORS_MASK \
2636 #define RX_PKT_CMPL_ERRORS_SFT 1
2638 * This error indicates that there was some sort of problem with
2639 * the BDs for the packet that was found after part of the
2640 * packet was already placed. The packet should be treated as
2643 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2645 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2646 /* No buffer error */
2647 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2648 (UINT32_C(0x0) << 1)
2651 * Packet did not fit into packet buffer provided.
2652 * For regular placement, this means the packet did not fit
2653 * in the buffer provided. For HDS and jumbo placement, this
2654 * means that the packet could not be placed into 7 physical
2657 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2658 (UINT32_C(0x1) << 1)
2661 * All BDs needed for the packet were not on-chip when
2662 * the packet arrived.
2664 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2665 (UINT32_C(0x2) << 1)
2668 * BDs were not formatted correctly.
2670 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2671 (UINT32_C(0x3) << 1)
2674 * There was a bad_format error on the previous operation
2676 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2677 (UINT32_C(0x5) << 1)
2678 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2679 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2681 * This indicates that there was an error in the IP header
2684 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2687 * This indicates that there was an error in the TCP, UDP
2690 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2693 * This indicates that there was an error in the tunnel
2694 * IP header checksum.
2696 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2699 * This indicates that there was an error in the tunnel
2702 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2705 * This indicates that there was a CRC error on either an FCoE
2706 * or RoCE packet. The itype indicates the packet type.
2708 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2711 * This indicates that there was an error in the tunnel
2712 * portion of the packet when this
2713 * field is non-zero.
2715 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2717 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2719 * No additional error occurred on the tunnel portion
2720 * or the packet of the packet does not have a tunnel.
2722 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2723 (UINT32_C(0x0) << 9)
2725 * Indicates that IP header version does not match
2726 * expectation from L2 Ethertype for IPv4 and IPv6
2727 * in the tunnel header.
2729 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2730 (UINT32_C(0x1) << 9)
2732 * Indicates that header length is out of range in the
2733 * tunnel header. Valid for
2736 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2737 (UINT32_C(0x2) << 9)
2739 * Indicates that the physical packet is shorter than that
2740 * claimed by the PPPoE header length for a tunnel PPPoE
2743 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2744 (UINT32_C(0x3) << 9)
2746 * Indicates that physical packet is shorter than that claimed
2747 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2748 * tunnel packet packets.
2750 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2751 (UINT32_C(0x4) << 9)
2753 * Indicates that the physical packet is shorter than that
2754 * claimed by the tunnel UDP header length for a tunnel
2755 * UDP packet that is not fragmented.
2757 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2758 (UINT32_C(0x5) << 9)
2760 * indicates that the IPv4 TTL or IPv6 hop limit check
2761 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2762 * for IPv4, and IPv6.
2764 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2765 (UINT32_C(0x6) << 9)
2766 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2767 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2769 * This indicates that there was an error in the inner
2770 * portion of the packet when this
2771 * field is non-zero.
2773 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2775 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2777 * No additional error occurred on the tunnel portion
2778 * or the packet of the packet does not have a tunnel.
2780 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2781 (UINT32_C(0x0) << 12)
2783 * Indicates that IP header version does not match
2784 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2785 * option other than VFT was parsed on
2788 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2789 (UINT32_C(0x1) << 12)
2791 * indicates that header length is out of range. Valid for
2794 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2795 (UINT32_C(0x2) << 12)
2797 * indicates that the IPv4 TTL or IPv6 hop limit check
2798 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2800 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2801 (UINT32_C(0x3) << 12)
2803 * Indicates that physical packet is shorter than that
2804 * claimed by the l3 header length. Valid for IPv4,
2805 * IPv6 packet or RoCE packets.
2807 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2808 (UINT32_C(0x4) << 12)
2810 * Indicates that the physical packet is shorter than that
2811 * claimed by the UDP header length for a UDP packet that is
2814 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2815 (UINT32_C(0x5) << 12)
2817 * Indicates that TCP header length > IP payload. Valid for
2820 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2821 (UINT32_C(0x6) << 12)
2822 /* Indicates that TCP header length < 5. Valid for TCP. */
2823 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2824 (UINT32_C(0x7) << 12)
2826 * Indicates that TCP option headers result in a TCP header
2827 * size that does not match data offset in TCP header. Valid
2830 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2831 (UINT32_C(0x8) << 12)
2832 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2833 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2835 * This field identifies the CFA action rule that was used for this
2841 * This value holds the reordering sequence number for the packet.
2842 * If the reordering sequence is not valid, then this value is zero.
2843 * The reordering domain for the packet is in the bottom 8 to 10b of
2844 * the rss_hash value. The bottom 20b of this value contain the
2845 * ordering domain value for the packet.
2847 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2848 #define RX_PKT_CMPL_REORDER_SFT 0
2849 } __attribute__((packed));
2851 /* rx_tpa_start_cmpl (size:128b/16B) */
2852 struct rx_tpa_start_cmpl {
2853 uint16_t flags_type;
2855 * This field indicates the exact type of the completion.
2856 * By convention, the LSB identifies the length of the
2857 * record in 16B units. Even values indicate 16B
2858 * records. Odd values indicate 32B
2861 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2862 #define RX_TPA_START_CMPL_TYPE_SFT 0
2864 * RX L2 TPA Start Completion:
2865 * Completion at the beginning of a TPA operation.
2868 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2869 #define RX_TPA_START_CMPL_TYPE_LAST \
2870 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2871 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2872 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2873 /* This bit will always be '0' for TPA start completions. */
2874 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2875 /* This field indicates how the packet was placed in the buffer. */
2876 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2877 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2880 * TPA Packet was placed using jumbo algorithm. This means
2881 * that the first buffer will be filled with data before
2882 * moving to aggregation buffers. Each aggregation buffer
2883 * will be filled before moving to the next aggregation
2886 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2887 (UINT32_C(0x1) << 7)
2889 * Header/Data Separation:
2890 * Packet was placed using Header/Data separation algorithm.
2891 * The separation location is indicated by the itype field.
2893 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2894 (UINT32_C(0x2) << 7)
2897 * Packet will be placed using GRO/Jumbo where the first
2898 * packet is filled with data. Subsequent packets will be
2899 * placed such that any one packet does not span two
2900 * aggregation buffers unless it starts at the beginning of
2901 * an aggregation buffer.
2903 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2904 (UINT32_C(0x5) << 7)
2906 * GRO/Header-Data Separation:
2907 * Packet will be placed using GRO/HDS where the header
2908 * is in the first packet.
2909 * Payload of each packet will be
2910 * placed such that any one packet does not span two
2911 * aggregation buffers unless it starts at the beginning of
2912 * an aggregation buffer.
2914 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2915 (UINT32_C(0x6) << 7)
2916 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2917 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2918 /* This bit is '1' if the RSS field in this completion is valid. */
2919 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2921 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2923 * This value indicates what the inner packet determined for the
2926 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2927 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2930 * Indicates that the packet was IP and TCP.
2932 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2933 (UINT32_C(0x2) << 12)
2934 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2935 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2937 * This value indicates the amount of packet data written to the
2938 * buffer the opaque field in this completion corresponds to.
2942 * This is a copy of the opaque field from the RX BD this completion
2947 * This value is written by the NIC such that it will be different
2948 * for each pass through the completion queue. The even passes
2949 * will write 1. The odd passes will write 0.
2953 * This value is written by the NIC such that it will be different
2954 * for each pass through the completion queue. The even passes
2955 * will write 1. The odd passes will write 0.
2957 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2958 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2960 * This is the RSS hash type for the packet. The value is packed
2961 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2963 * The value of tuple_extrac_op provides the information about
2964 * what fields the hash was computed on.
2965 * * 0: The RSS hash was computed over source IP address,
2966 * destination IP address, source port, and destination port of inner
2967 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2968 * the packet headers are considered inner packet headers for the RSS
2969 * hash computation purpose.
2970 * * 1: The RSS hash was computed over source IP address and destination
2971 * IP address of inner IP header. Note: For non-tunneled packets,
2972 * the packet headers are considered inner packet headers for the RSS
2973 * hash computation purpose.
2974 * * 2: The RSS hash was computed over source IP address,
2975 * destination IP address, source port, and destination port of
2976 * IP and TCP or UDP headers of outer tunnel headers.
2977 * Note: For non-tunneled packets, this value is not applicable.
2978 * * 3: The RSS hash was computed over source IP address and
2979 * destination IP address of IP header of outer tunnel headers.
2980 * Note: For non-tunneled packets, this value is not applicable.
2982 * Note that 4-tuples values listed above are applicable
2983 * for layer 4 protocols supported and enabled for RSS in the hardware,
2984 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2985 * enabled for TCP traffic only, then the values of tuple_extract_op
2986 * corresponding to 4-tuples are only valid for TCP traffic.
2988 uint8_t rss_hash_type;
2990 * This is the aggregation ID that the completion is associated
2991 * with. Use this number to correlate the TPA start completion
2992 * with the TPA end completion.
2995 /* unused2 is 9 b */
2996 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2997 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2999 * This is the aggregation ID that the completion is associated
3000 * with. Use this number to correlate the TPA start completion
3001 * with the TPA end completion.
3003 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3004 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3006 * This value is the RSS hash value calculated for the packet
3007 * based on the mode bits and key value in the VNIC.
3010 } __attribute__((packed));
3012 /* Last 16 bytes of rx_tpq_start_cmpl. */
3013 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3014 struct rx_tpa_start_cmpl_hi {
3017 * This indicates that the ip checksum was calculated for the
3018 * inner packet and that the sum passed for all segments
3019 * included in the aggregation.
3021 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
3024 * This indicates that the TCP, UDP or ICMP checksum was
3025 * calculated for the inner packet and that the sum passed
3026 * for all segments included in the aggregation.
3028 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
3031 * This indicates that the ip checksum was calculated for the
3032 * tunnel header and that the sum passed for all segments
3033 * included in the aggregation.
3035 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
3038 * This indicates that the UDP checksum was
3039 * calculated for the tunnel packet and that the sum passed for
3040 * all segments included in the aggregation.
3042 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
3044 /* This value indicates what format the metadata field is. */
3045 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
3047 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3048 /* No metadata informtaion. Value is zero. */
3049 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3050 (UINT32_C(0x0) << 4)
3052 * The metadata field contains the VLAN tag and TPID value.
3053 * - metadata[11:0] contains the vlan VID value.
3054 * - metadata[12] contains the vlan DE value.
3055 * - metadata[15:13] contains the vlan PRI value.
3056 * - metadata[31:16] contains the vlan TPID value.
3058 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3059 (UINT32_C(0x1) << 4)
3061 * If ext_meta_format is equal to 1, the metadata field
3062 * contains the lower 16b of the tunnel ID value, justified
3064 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3065 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3066 * - NVGRE = TNI[23:0] -> Tenant Network ID
3067 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3068 * - IPV4 = 0 (not populated)
3069 * - IPV6 = Flow Label[19:0]
3070 * - PPPoE = sessionID[15:0]
3071 * - MPLs = Outer label[19:0]
3072 * - UPAR = Selected[31:0] with bit mask
3074 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3075 (UINT32_C(0x2) << 4)
3077 * if ext_meta_format is equal to 1, metadata field contains
3078 * 16b metadata from the prepended header (chdr_data).
3080 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3081 (UINT32_C(0x3) << 4)
3083 * If ext_meta_format is equal to 1, the metadata field contains
3084 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3086 * - metadata[8:0] contains the outer_l3_offset.
3087 * - metadata[17:9] contains the inner_l2_offset.
3088 * - metadata[26:18] contains the inner_l3_offset.
3089 * - metadata[31:27] contains the inner_l4_size.
3091 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3092 (UINT32_C(0x4) << 4)
3093 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3094 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3096 * This field indicates the IP type for the inner-most IP header.
3097 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3099 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
3102 * This indicates that the complete 1's complement checksum was
3103 * calculated for the packet.
3105 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3108 * The combination of this value and meta_format indicated what
3109 * format the metadata field is.
3111 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3113 #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3115 * This value is the complete 1's complement checksum calculated from
3116 * the start of the outer L3 header to the end of the packet (not
3117 * including the ethernet crc). It is valid when the
3118 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3119 * the complete checksum is calculated for the first packet in the
3122 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3123 UINT32_C(0xffff0000)
3124 #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3126 * This is data from the CFA block as indicated by the meta_format
3130 /* When meta_format=1, this value is the VLAN VID. */
3131 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3132 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3133 /* When meta_format=1, this value is the VLAN DE. */
3134 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3135 /* When meta_format=1, this value is the VLAN PRI. */
3136 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3137 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3138 /* When meta_format=1, this value is the VLAN TPID. */
3139 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3140 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3143 * This value is written by the NIC such that it will be different
3144 * for each pass through the completion queue. The even passes
3145 * will write 1. The odd passes will write 0.
3147 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3148 #define RX_TPA_START_CMPL_ERRORS_MASK \
3150 #define RX_TPA_START_CMPL_ERRORS_SFT 1
3152 * This error indicates that there was some sort of problem with
3153 * the BDs for the packet that was found after part of the
3154 * packet was already placed. The packet should be treated as
3157 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3158 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3159 /* No buffer error */
3160 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3161 (UINT32_C(0x0) << 1)
3164 * BDs were not formatted correctly.
3166 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3167 (UINT32_C(0x3) << 1)
3170 * There was a bad_format error on the previous operation
3172 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3173 (UINT32_C(0x5) << 1)
3174 #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3175 RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3177 * This field identifies the CFA action rule that was used for this
3182 * This is the size in bytes of the inner most L4 header.
3183 * This can be subtracted from the payload_offset to determine
3184 * the start of the inner most L4 header.
3186 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3188 * This is the offset from the beginning of the packet in bytes for
3189 * the outer L3 header. If there is no outer L3 header, then this
3192 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3193 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3195 * This is the offset from the beginning of the packet in bytes for
3196 * the inner most L2 header.
3198 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3199 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3201 * This is the offset from the beginning of the packet in bytes for
3202 * the inner most L3 header.
3204 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3205 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3207 * This is the size in bytes of the inner most L4 header.
3208 * This can be subtracted from the payload_offset to determine
3209 * the start of the inner most L4 header.
3211 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3212 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3213 } __attribute__((packed));
3215 /* rx_tpa_end_cmpl (size:128b/16B) */
3216 struct rx_tpa_end_cmpl {
3217 uint16_t flags_type;
3219 * This field indicates the exact type of the completion.
3220 * By convention, the LSB identifies the length of the
3221 * record in 16B units. Even values indicate 16B
3222 * records. Odd values indicate 32B
3225 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3226 #define RX_TPA_END_CMPL_TYPE_SFT 0
3228 * RX L2 TPA End Completion:
3229 * Completion at the end of a TPA operation.
3232 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3233 #define RX_TPA_END_CMPL_TYPE_LAST \
3234 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3235 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3236 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3238 * When this bit is '1', it indicates a packet that has an
3239 * error of some type. Type of error is indicated in
3242 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3243 /* This field indicates how the packet was placed in the buffer. */
3244 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3245 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3248 * TPA Packet was placed using jumbo algorithm. This means
3249 * that the first buffer will be filled with data before
3250 * moving to aggregation buffers. Each aggregation buffer
3251 * will be filled before moving to the next aggregation
3254 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3255 (UINT32_C(0x1) << 7)
3257 * Header/Data Separation:
3258 * Packet was placed using Header/Data separation algorithm.
3259 * The separation location is indicated by the itype field.
3261 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3262 (UINT32_C(0x2) << 7)
3265 * Packet will be placed using GRO/Jumbo where the first
3266 * packet is filled with data. Subsequent packets will be
3267 * placed such that any one packet does not span two
3268 * aggregation buffers unless it starts at the beginning of
3269 * an aggregation buffer.
3271 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3272 (UINT32_C(0x5) << 7)
3274 * GRO/Header-Data Separation:
3275 * Packet will be placed using GRO/HDS where the header
3276 * is in the first packet.
3277 * Payload of each packet will be
3278 * placed such that any one packet does not span two
3279 * aggregation buffers unless it starts at the beginning of
3280 * an aggregation buffer.
3282 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3283 (UINT32_C(0x6) << 7)
3284 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3285 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3287 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3288 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3290 * This value indicates what the inner packet determined for the
3293 * Indicates that the packet was IP and TCP. This indicates
3294 * that the ip_cs field is valid and that the tcp_udp_cs
3295 * field is valid and contains the TCP checksum.
3296 * This also indicates that the payload_offset field is valid.
3298 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3299 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3301 * This value is zero for TPA End completions.
3302 * There is no data in the buffer that corresponds to the opaque
3303 * value in this completion.
3307 * This is a copy of the opaque field from the RX BD this completion
3312 * This value is written by the NIC such that it will be different
3313 * for each pass through the completion queue. The even passes
3314 * will write 1. The odd passes will write 0.
3316 uint8_t agg_bufs_v1;
3318 * This value is written by the NIC such that it will be different
3319 * for each pass through the completion queue. The even passes
3320 * will write 1. The odd passes will write 0.
3322 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3324 * This value is the number of aggregation buffers that follow this
3325 * entry in the completion ring that are a part of this aggregation
3327 * If the value is zero, then the packet is completely contained
3328 * in the buffer space provided in the aggregation start completion.
3330 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3331 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3332 /* This value is the number of segments in the TPA operation. */
3335 * This value indicates the offset in bytes from the beginning of the packet
3336 * where the inner payload starts. This value is valid for TCP, UDP,
3337 * FCoE, and RoCE packets.
3339 * A value of zero indicates an offset of 256 bytes.
3341 uint8_t payload_offset;
3343 /* unused2 is 1 b */
3344 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3346 * This is the aggregation ID that the completion is associated
3347 * with. Use this number to correlate the TPA start completion
3348 * with the TPA end completion.
3350 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3351 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3353 * For non-GRO packets, this value is the
3354 * timestamp delta between earliest and latest timestamp values for
3355 * TPA packet. If packets were not time stamped, then delta will be
3358 * For GRO packets, this field is zero except for the following
3361 * Timestamp present indication. When '0', no Timestamp
3362 * option is in the packet. When '1', then a Timestamp
3363 * option is present in the packet.
3366 } __attribute__((packed));
3368 /* Last 16 bytes of rx_tpa_end_cmpl. */
3369 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3370 struct rx_tpa_end_cmpl_hi {
3372 * This value is the number of duplicate ACKs that have been
3373 * received as part of the TPA operation.
3375 uint16_t tpa_dup_acks;
3377 * This value is the number of duplicate ACKs that have been
3378 * received as part of the TPA operation.
3380 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3381 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3383 * This value indicated the offset in bytes from the beginning of
3384 * the packet where the inner payload starts. This value is valid
3385 * for TCP, UDP, FCoE and RoCE packets
3387 uint8_t payload_offset;
3389 * The value is the total number of aggregation buffers that were
3390 * used in the TPA operation. All TPA aggregation buffer completions
3391 * precede the TPA End completion. If the value is zero, then the
3392 * aggregation is completely contained in the buffer space provided
3393 * in the aggregation start completion.
3394 * Note that the field is simply provided as a cross check.
3396 uint8_t tpa_agg_bufs;
3398 * This value is the valid when TPA completion is active. It
3399 * indicates the length of the longest segment of the TPA operation
3400 * for LRO mode and the length of the first segment in GRO mode.
3402 * This value may be used by GRO software to re-construct the original
3403 * packet stream from the TPA packet. This is the length of all
3404 * but the last segment for GRO. In LRO mode this value may be used
3405 * to indicate MSS size to the stack.
3407 uint16_t tpa_seg_len;
3408 /* unused4 is 16 b */
3412 * This value is written by the NIC such that it will be different
3413 * for each pass through the completion queue. The even passes
3414 * will write 1. The odd passes will write 0.
3416 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3417 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3418 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3420 * This error indicates that there was some sort of problem with
3421 * the BDs for the packet that was found after part of the
3422 * packet was already placed. The packet should be treated as
3425 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3426 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3427 /* No buffer error */
3428 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3429 (UINT32_C(0x0) << 1)
3431 * This error occurs when there is a fatal HW problem in
3432 * the chip only. It indicates that there were not
3433 * BDs on chip but that there was adequate reservation.
3434 * provided by the TPA block.
3436 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3437 (UINT32_C(0x2) << 1)
3440 * BDs were not formatted correctly.
3442 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3443 (UINT32_C(0x3) << 1)
3445 * This error occurs when TPA block was not configured to
3446 * reserve adequate BDs for TPA operations on this RX
3447 * ring. All data for the TPA operation was not placed.
3449 * This error can also be generated when the number of
3450 * segments is not programmed correctly in TPA and the
3451 * 33 total aggregation buffers allowed for the TPA
3452 * operation has been exceeded.
3454 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3455 (UINT32_C(0x4) << 1)
3458 * There was a bad_format error on the previous operation
3460 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3461 (UINT32_C(0x5) << 1)
3462 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3463 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3464 /* unused5 is 16 b */
3467 * This is the opaque value that was completed for the TPA start
3468 * completion that corresponds to this TPA end completion.
3470 uint32_t start_opaque;
3471 } __attribute__((packed));
3473 /* rx_abuf_cmpl (size:128b/16B) */
3474 struct rx_abuf_cmpl {
3477 * This field indicates the exact type of the completion.
3478 * By convention, the LSB identifies the length of the
3479 * record in 16B units. Even values indicate 16B
3480 * records. Odd values indicate 32B
3483 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
3484 #define RX_ABUF_CMPL_TYPE_SFT 0
3486 * RX Aggregation Buffer completion :
3487 * Completion of an L2 aggregation buffer in support of
3488 * TPA, HDS, or Jumbo packet completion. Length = 16B
3490 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
3491 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
3493 * This is the length of the data for the packet stored in this
3494 * aggregation buffer identified by the opaque value. This does not
3495 * include the length of any
3496 * data placed in other aggregation BDs or in the packet or buffer
3497 * BDs. This length does not include any space added due to
3498 * hdr_offset register during HDS placement mode.
3502 * This is a copy of the opaque field from the RX BD this aggregation
3503 * buffer corresponds to.
3508 * This value is written by the NIC such that it will be different
3509 * for each pass through the completion queue. The even passes
3510 * will write 1. The odd passes will write 0.
3512 #define RX_ABUF_CMPL_V UINT32_C(0x1)
3513 /* unused3 is 32 b */
3515 } __attribute__((packed));
3517 /* eject_cmpl (size:128b/16B) */
3521 * This field indicates the exact type of the completion.
3522 * By convention, the LSB identifies the length of the
3523 * record in 16B units. Even values indicate 16B
3524 * records. Odd values indicate 32B
3527 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
3528 #define EJECT_CMPL_TYPE_SFT 0
3530 * Statistics Ejection Completion:
3531 * Completion of statistics data ejection buffer.
3534 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
3535 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
3536 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3537 #define EJECT_CMPL_FLAGS_SFT 6
3539 * When this bit is '1', it indicates a packet that has an
3540 * error of some type. Type of error is indicated in
3543 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
3545 * This is the length of the statistics data stored in this
3550 * This is a copy of the opaque field from the RX BD this ejection
3551 * buffer corresponds to.
3556 * This value is written by the NIC such that it will be different
3557 * for each pass through the completion queue. The even passes
3558 * will write 1. The odd passes will write 0.
3560 #define EJECT_CMPL_V UINT32_C(0x1)
3561 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3562 #define EJECT_CMPL_ERRORS_SFT 1
3564 * This error indicates that there was some sort of problem with
3565 * the BDs for statistics ejection. The statistics ejection should
3566 * be treated as invalid
3568 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3569 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3570 /* No buffer error */
3571 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3572 (UINT32_C(0x0) << 1)
3575 * Statistics did not fit into aggregation buffer provided.
3577 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3578 (UINT32_C(0x1) << 1)
3581 * BDs were not formatted correctly.
3583 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3584 (UINT32_C(0x3) << 1)
3587 * There was a bad_format error on the previous operation
3589 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3590 (UINT32_C(0x5) << 1)
3591 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3592 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3593 /* reserved16 is 16 b */
3594 uint16_t reserved16;
3595 /* unused3 is 32 b */
3597 } __attribute__((packed));
3599 /* hwrm_cmpl (size:128b/16B) */
3603 * This field indicates the exact type of the completion.
3604 * By convention, the LSB identifies the length of the
3605 * record in 16B units. Even values indicate 16B
3606 * records. Odd values indicate 32B
3609 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3610 #define HWRM_CMPL_TYPE_SFT 0
3612 * HWRM Command Completion:
3613 * Completion of an HWRM command.
3615 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3616 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3617 /* This is the sequence_id of the HWRM command that has completed. */
3618 uint16_t sequence_id;
3619 /* unused2 is 32 b */
3623 * This value is written by the NIC such that it will be different
3624 * for each pass through the completion queue. The even passes
3625 * will write 1. The odd passes will write 0.
3627 #define HWRM_CMPL_V UINT32_C(0x1)
3628 /* unused4 is 32 b */
3630 } __attribute__((packed));
3632 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3633 struct hwrm_fwd_req_cmpl {
3635 * This field indicates the exact type of the completion.
3636 * By convention, the LSB identifies the length of the
3637 * record in 16B units. Even values indicate 16B
3638 * records. Odd values indicate 32B
3641 uint16_t req_len_type;
3643 * This field indicates the exact type of the completion.
3644 * By convention, the LSB identifies the length of the
3645 * record in 16B units. Even values indicate 16B
3646 * records. Odd values indicate 32B
3649 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3650 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3651 /* Forwarded HWRM Request */
3652 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3653 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3654 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3655 /* Length of forwarded request in bytes. */
3656 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3657 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3659 * Source ID of this request.
3660 * Typically used in forwarding requests and responses.
3661 * 0x0 - 0xFFF8 - Used for function ids
3662 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3666 /* unused1 is 32 b */
3668 /* Address of forwarded request. */
3669 uint32_t req_buf_addr_v[2];
3671 * This value is written by the NIC such that it will be different
3672 * for each pass through the completion queue. The even passes
3673 * will write 1. The odd passes will write 0.
3675 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3676 /* Address of forwarded request. */
3677 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3678 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3679 } __attribute__((packed));
3681 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3682 struct hwrm_fwd_resp_cmpl {
3685 * This field indicates the exact type of the completion.
3686 * By convention, the LSB identifies the length of the
3687 * record in 16B units. Even values indicate 16B
3688 * records. Odd values indicate 32B
3691 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3692 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3693 /* Forwarded HWRM Response */
3694 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3695 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3696 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3698 * Source ID of this response.
3699 * Typically used in forwarding requests and responses.
3700 * 0x0 - 0xFFF8 - Used for function ids
3701 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3705 /* Length of forwarded response in bytes. */
3707 /* unused2 is 16 b */
3709 /* Address of forwarded request. */
3710 uint32_t resp_buf_addr_v[2];
3712 * This value is written by the NIC such that it will be different
3713 * for each pass through the completion queue. The even passes
3714 * will write 1. The odd passes will write 0.
3716 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3717 /* Address of forwarded request. */
3718 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3719 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3720 } __attribute__((packed));
3722 /* hwrm_async_event_cmpl (size:128b/16B) */
3723 struct hwrm_async_event_cmpl {
3726 * This field indicates the exact type of the completion.
3727 * By convention, the LSB identifies the length of the
3728 * record in 16B units. Even values indicate 16B
3729 * records. Odd values indicate 32B
3732 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3733 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3734 /* HWRM Asynchronous Event Information */
3735 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3736 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3737 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3738 /* Identifiers of events. */
3740 /* Link status changed */
3741 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3743 /* Link MTU changed */
3744 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3746 /* Link speed changed */
3747 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3749 /* DCB Configuration changed */
3750 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3752 /* Port connection not allowed */
3753 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3755 /* Link speed configuration was not allowed */
3756 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3758 /* Link speed configuration change */
3759 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3761 /* Port PHY configuration change */
3762 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3764 /* Reset notification to clients */
3765 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
3767 /* Master function selection event */
3768 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
3770 /* Function driver unloaded */
3771 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3773 /* Function driver loaded */
3774 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3776 /* Function FLR related processing has completed */
3777 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3779 /* PF driver unloaded */
3780 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3782 /* PF driver loaded */
3783 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3785 /* VF Function Level Reset (FLR) */
3786 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3788 /* VF MAC Address Change */
3789 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3791 /* PF-VF communication channel status change. */
3792 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3794 /* VF Configuration Change */
3795 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3797 /* LLFC/PFC Configuration Change */
3798 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3800 /* Default VNIC Configuration Change */
3801 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
3804 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
3807 * A debug notification being posted to the driver. These
3808 * notifications are purely for diagnostic purpose and should not be
3809 * used for functional purpose. The driver is not supposed to act
3810 * on these messages except to log/record it.
3812 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
3815 * A EEM flow cached memory flush request event being posted to the PF
3818 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
3821 * A EEM flow cache memory flush completion event being posted to the
3822 * firmware by the PF driver. This is indication that host EEM flush
3823 * has completed by the PF.
3825 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
3828 * A tcp flag action change event being posted to the PF or trusted VF
3829 * driver by the firmware. The PF or trusted VF driver should query
3830 * the firmware for the new TCP flag action update after receiving
3833 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
3836 * A eem flow active event being posted to the PF or trusted VF driver
3837 * by the firmware. The PF or trusted VF driver should update the
3838 * flow's aging timer after receiving this async event.
3840 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
3843 * A eem cfg change event being posted to the trusted VF driver by the
3844 * firmware if the parent PF EEM configuration changed.
3846 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
3849 * A trace log message. This contains firmware trace logs string
3850 * embedded in the asynchronous message. This is an experimental
3851 * event, not meant for production use at this time.
3853 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
3856 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3858 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3859 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3860 /* Event specific data */
3861 uint32_t event_data2;
3864 * This value is written by the NIC such that it will be different
3865 * for each pass through the completion queue. The even passes
3866 * will write 1. The odd passes will write 0.
3868 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3870 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3871 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3872 /* 8-lsb timestamp from POR (100-msec resolution) */
3873 uint8_t timestamp_lo;
3874 /* 16-lsb timestamp from POR (100-msec resolution) */
3875 uint16_t timestamp_hi;
3876 /* Event specific data */
3877 uint32_t event_data1;
3878 } __attribute__((packed));
3880 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3881 struct hwrm_async_event_cmpl_link_status_change {
3884 * This field indicates the exact type of the completion.
3885 * By convention, the LSB identifies the length of the
3886 * record in 16B units. Even values indicate 16B
3887 * records. Odd values indicate 32B
3890 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3892 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3893 /* HWRM Asynchronous Event Information */
3894 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3896 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3897 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3898 /* Identifiers of events. */
3900 /* Link status changed */
3901 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3903 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3904 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3905 /* Event specific data */
3906 uint32_t event_data2;
3909 * This value is written by the NIC such that it will be different
3910 * for each pass through the completion queue. The even passes
3911 * will write 1. The odd passes will write 0.
3913 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3916 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3918 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3919 /* 8-lsb timestamp from POR (100-msec resolution) */
3920 uint8_t timestamp_lo;
3921 /* 16-lsb timestamp from POR (100-msec resolution) */
3922 uint16_t timestamp_hi;
3923 /* Event specific data */
3924 uint32_t event_data1;
3925 /* Indicates link status change */
3926 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3929 * If this bit set to 0, then it indicates that the link
3930 * was up and it went down.
3932 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3935 * If this bit is set to 1, then it indicates that the link
3936 * was down and it went up.
3938 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3940 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3941 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3942 /* Indicates the physical port this link status change occur */
3943 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3945 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3948 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3950 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3952 /* Indicates the physical function this event occurred on. */
3953 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
3955 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
3957 } __attribute__((packed));
3959 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
3960 struct hwrm_async_event_cmpl_link_mtu_change {
3963 * This field indicates the exact type of the completion.
3964 * By convention, the LSB identifies the length of the
3965 * record in 16B units. Even values indicate 16B
3966 * records. Odd values indicate 32B
3969 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
3971 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
3972 /* HWRM Asynchronous Event Information */
3973 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3975 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
3976 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
3977 /* Identifiers of events. */
3979 /* Link MTU changed */
3980 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
3982 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
3983 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
3984 /* Event specific data */
3985 uint32_t event_data2;
3988 * This value is written by the NIC such that it will be different
3989 * for each pass through the completion queue. The even passes
3990 * will write 1. The odd passes will write 0.
3992 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
3994 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
3996 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
3997 /* 8-lsb timestamp from POR (100-msec resolution) */
3998 uint8_t timestamp_lo;
3999 /* 16-lsb timestamp from POR (100-msec resolution) */
4000 uint16_t timestamp_hi;
4001 /* Event specific data */
4002 uint32_t event_data1;
4003 /* The new MTU of the link in bytes. */
4004 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4006 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4007 } __attribute__((packed));
4009 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4010 struct hwrm_async_event_cmpl_link_speed_change {
4013 * This field indicates the exact type of the completion.
4014 * By convention, the LSB identifies the length of the
4015 * record in 16B units. Even values indicate 16B
4016 * records. Odd values indicate 32B
4019 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4021 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4022 /* HWRM Asynchronous Event Information */
4023 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4025 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4026 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4027 /* Identifiers of events. */
4029 /* Link speed changed */
4030 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4032 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4033 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4034 /* Event specific data */
4035 uint32_t event_data2;
4038 * This value is written by the NIC such that it will be different
4039 * for each pass through the completion queue. The even passes
4040 * will write 1. The odd passes will write 0.
4042 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4045 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4047 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4048 /* 8-lsb timestamp from POR (100-msec resolution) */
4049 uint8_t timestamp_lo;
4050 /* 16-lsb timestamp from POR (100-msec resolution) */
4051 uint16_t timestamp_hi;
4052 /* Event specific data */
4053 uint32_t event_data1;
4055 * When this bit is '1', the link was forced to the
4056 * force_link_speed value.
4058 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4060 /* The new link speed in 100 Mbps units. */
4061 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4063 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4065 /* 100Mb link speed */
4066 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4067 (UINT32_C(0x1) << 1)
4068 /* 1Gb link speed */
4069 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4070 (UINT32_C(0xa) << 1)
4071 /* 2Gb link speed */
4072 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4073 (UINT32_C(0x14) << 1)
4074 /* 25Gb link speed */
4075 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4076 (UINT32_C(0x19) << 1)
4077 /* 10Gb link speed */
4078 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4079 (UINT32_C(0x64) << 1)
4080 /* 20Mb link speed */
4081 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4082 (UINT32_C(0xc8) << 1)
4083 /* 25Gb link speed */
4084 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4085 (UINT32_C(0xfa) << 1)
4086 /* 40Gb link speed */
4087 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4088 (UINT32_C(0x190) << 1)
4089 /* 50Gb link speed */
4090 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4091 (UINT32_C(0x1f4) << 1)
4092 /* 100Gb link speed */
4093 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4094 (UINT32_C(0x3e8) << 1)
4095 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4096 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4098 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4099 UINT32_C(0xffff0000)
4100 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4102 } __attribute__((packed));
4104 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4105 struct hwrm_async_event_cmpl_dcb_config_change {
4108 * This field indicates the exact type of the completion.
4109 * By convention, the LSB identifies the length of the
4110 * record in 16B units. Even values indicate 16B
4111 * records. Odd values indicate 32B
4114 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4116 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4117 /* HWRM Asynchronous Event Information */
4118 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4120 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4121 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4122 /* Identifiers of events. */
4124 /* DCB Configuration changed */
4125 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4127 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4128 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4129 /* Event specific data */
4130 uint32_t event_data2;
4131 /* ETS configuration change */
4132 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4134 /* PFC configuration change */
4135 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4137 /* APP configuration change */
4138 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4142 * This value is written by the NIC such that it will be different
4143 * for each pass through the completion queue. The even passes
4144 * will write 1. The odd passes will write 0.
4146 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4149 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4151 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4152 /* 8-lsb timestamp from POR (100-msec resolution) */
4153 uint8_t timestamp_lo;
4154 /* 16-lsb timestamp from POR (100-msec resolution) */
4155 uint16_t timestamp_hi;
4156 /* Event specific data */
4157 uint32_t event_data1;
4159 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4161 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4163 /* Priority recommended for RoCE traffic */
4164 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4166 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4169 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4170 (UINT32_C(0xff) << 16)
4171 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4172 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4173 /* Priority recommended for L2 traffic */
4174 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4175 UINT32_C(0xff000000)
4176 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4179 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4180 (UINT32_C(0xff) << 24)
4181 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4182 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4183 } __attribute__((packed));
4185 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4186 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4189 * This field indicates the exact type of the completion.
4190 * By convention, the LSB identifies the length of the
4191 * record in 16B units. Even values indicate 16B
4192 * records. Odd values indicate 32B
4195 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4197 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4199 /* HWRM Asynchronous Event Information */
4200 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4202 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4203 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4204 /* Identifiers of events. */
4206 /* Port connection not allowed */
4207 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4209 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4210 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4211 /* Event specific data */
4212 uint32_t event_data2;
4215 * This value is written by the NIC such that it will be different
4216 * for each pass through the completion queue. The even passes
4217 * will write 1. The odd passes will write 0.
4219 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4222 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4224 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4225 /* 8-lsb timestamp from POR (100-msec resolution) */
4226 uint8_t timestamp_lo;
4227 /* 16-lsb timestamp from POR (100-msec resolution) */
4228 uint16_t timestamp_hi;
4229 /* Event specific data */
4230 uint32_t event_data1;
4232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4234 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4237 * This value indicates the current port level enforcement policy
4238 * for the optics module when there is an optical module mismatch
4239 * and port is not connected.
4241 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4243 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4245 /* No enforcement */
4246 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4247 (UINT32_C(0x0) << 16)
4248 /* Disable Transmit side Laser. */
4249 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4250 (UINT32_C(0x1) << 16)
4251 /* Raise a warning message. */
4252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4253 (UINT32_C(0x2) << 16)
4254 /* Power down the module. */
4255 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4256 (UINT32_C(0x3) << 16)
4257 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4258 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4259 } __attribute__((packed));
4261 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4262 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4265 * This field indicates the exact type of the completion.
4266 * By convention, the LSB identifies the length of the
4267 * record in 16B units. Even values indicate 16B
4268 * records. Odd values indicate 32B
4271 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4275 /* HWRM Asynchronous Event Information */
4276 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4278 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4279 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4280 /* Identifiers of events. */
4282 /* Link speed configuration was not allowed */
4283 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4285 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4286 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4287 /* Event specific data */
4288 uint32_t event_data2;
4291 * This value is written by the NIC such that it will be different
4292 * for each pass through the completion queue. The even passes
4293 * will write 1. The odd passes will write 0.
4295 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4298 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4300 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4301 /* 8-lsb timestamp from POR (100-msec resolution) */
4302 uint8_t timestamp_lo;
4303 /* 16-lsb timestamp from POR (100-msec resolution) */
4304 uint16_t timestamp_hi;
4305 /* Event specific data */
4306 uint32_t event_data1;
4308 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4310 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4312 } __attribute__((packed));
4314 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4315 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4318 * This field indicates the exact type of the completion.
4319 * By convention, the LSB identifies the length of the
4320 * record in 16B units. Even values indicate 16B
4321 * records. Odd values indicate 32B
4324 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
4326 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
4328 /* HWRM Asynchronous Event Information */
4329 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4331 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
4332 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4333 /* Identifiers of events. */
4335 /* Link speed configuration change */
4336 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4338 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
4339 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
4340 /* Event specific data */
4341 uint32_t event_data2;
4344 * This value is written by the NIC such that it will be different
4345 * for each pass through the completion queue. The even passes
4346 * will write 1. The odd passes will write 0.
4348 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
4351 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
4353 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
4354 /* 8-lsb timestamp from POR (100-msec resolution) */
4355 uint8_t timestamp_lo;
4356 /* 16-lsb timestamp from POR (100-msec resolution) */
4357 uint16_t timestamp_hi;
4358 /* Event specific data */
4359 uint32_t event_data1;
4361 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4363 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4366 * If set to 1, it indicates that the supported link speeds
4367 * configuration on the port has changed.
4368 * If set to 0, then there is no change in supported link speeds
4371 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
4374 * If set to 1, it indicates that the link speed configuration
4375 * on the port has become illegal or invalid.
4376 * If set to 0, then the link speed configuration on the port is
4379 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
4381 } __attribute__((packed));
4383 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
4384 struct hwrm_async_event_cmpl_port_phy_cfg_change {
4387 * This field indicates the exact type of the completion.
4388 * By convention, the LSB identifies the length of the
4389 * record in 16B units. Even values indicate 16B
4390 * records. Odd values indicate 32B
4393 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
4395 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
4397 /* HWRM Asynchronous Event Information */
4398 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4400 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
4401 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4402 /* Identifiers of events. */
4404 /* Port PHY configuration change */
4405 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
4407 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
4408 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
4409 /* Event specific data */
4410 uint32_t event_data2;
4413 * This value is written by the NIC such that it will be different
4414 * for each pass through the completion queue. The even passes
4415 * will write 1. The odd passes will write 0.
4417 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
4420 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
4422 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
4423 /* 8-lsb timestamp from POR (100-msec resolution) */
4424 uint8_t timestamp_lo;
4425 /* 16-lsb timestamp from POR (100-msec resolution) */
4426 uint16_t timestamp_hi;
4427 /* Event specific data */
4428 uint32_t event_data1;
4430 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4432 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4435 * If set to 1, it indicates that the FEC
4436 * configuration on the port has changed.
4437 * If set to 0, then there is no change in FEC configuration.
4439 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
4442 * If set to 1, it indicates that the EEE configuration
4443 * on the port has changed.
4444 * If set to 0, then there is no change in EEE configuration
4447 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
4450 * If set to 1, it indicates that the pause configuration
4451 * on the PHY has changed.
4452 * If set to 0, then there is no change in the pause
4453 * configuration on the PHY.
4455 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
4457 } __attribute__((packed));
4459 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
4460 struct hwrm_async_event_cmpl_reset_notify {
4463 * This field indicates the exact type of the completion.
4464 * By convention, the LSB identifies the length of the
4465 * record in 16B units. Even values indicate 16B
4466 * records. Odd values indicate 32B
4469 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
4471 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
4472 /* HWRM Asynchronous Event Information */
4473 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
4475 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
4476 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
4477 /* Identifiers of events. */
4479 /* Notify clients of imminent reset. */
4480 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
4482 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
4483 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
4484 /* Event specific data */
4485 uint32_t event_data2;
4488 * This value is written by the NIC such that it will be different
4489 * for each pass through the completion queue. The even passes
4490 * will write 1. The odd passes will write 0.
4492 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
4494 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
4495 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
4497 * 8-lsb timestamp (100-msec resolution)
4498 * The Minimum time required for the Firmware readiness after sending this
4499 * notification to the driver instances.
4501 uint8_t timestamp_lo;
4503 * 16-lsb timestamp (100-msec resolution)
4504 * The Maximum Firmware Reset bail out value in the order of 100
4505 * milli seconds. The driver instances will use this value to re-initiate the
4506 * registration process again if the core firmware didn’t set the ready
4509 uint16_t timestamp_hi;
4510 /* Event specific data */
4511 uint32_t event_data1;
4512 /* Indicates driver action requested */
4513 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
4515 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
4518 * If set to 1, it indicates that the l2 client should
4519 * stop sending in band traffic to Nitro.
4520 * if set to 0, there is no change in L2 client behavior.
4522 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
4525 * If set to 1, it indicates that the L2 client should
4526 * bring down the interface.
4527 * If set to 0, then there is no change in L2 client behavior.
4529 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
4531 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
4532 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
4533 /* Indicates reason for reset. */
4534 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
4536 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
4538 /* A management client has requested reset. */
4539 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
4540 (UINT32_C(0x1) << 8)
4541 /* A fatal firmware exception has occurred. */
4542 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
4543 (UINT32_C(0x2) << 8)
4544 /* A non-fatal firmware exception has occurred. */
4545 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
4546 (UINT32_C(0x3) << 8)
4547 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
4548 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
4550 * Minimum time before driver should attempt access - units 100ms ticks.
4553 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
4554 UINT32_C(0xffff0000)
4555 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
4557 } __attribute__((packed));
4559 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
4560 struct hwrm_async_event_cmpl_error_recovery {
4563 * This field indicates the exact type of the completion.
4564 * By convention, the LSB identifies the length of the
4565 * record in 16B units. Even values indicate 16B
4566 * records. Odd values indicate 32B
4569 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
4571 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
4572 /* HWRM Asynchronous Event Information */
4573 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
4575 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
4576 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
4577 /* Identifiers of events. */
4580 * This async notification message can be used for selecting or
4581 * deselecting master function for error recovery,
4582 * and to communicate to all the functions whether error recovery
4583 * was enabled/disabled.
4585 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
4587 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
4588 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
4589 /* Event specific data */
4590 uint32_t event_data2;
4593 * This value is written by the NIC such that it will be different
4594 * for each pass through the completion queue. The even passes
4595 * will write 1. The odd passes will write 0.
4597 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
4599 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
4600 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
4601 /* 8-lsb timestamp (100-msec resolution) */
4602 uint8_t timestamp_lo;
4603 /* 16-lsb timestamp (100-msec resolution) */
4604 uint16_t timestamp_hi;
4605 /* Event specific data */
4606 uint32_t event_data1;
4607 /* Indicates driver action requested */
4608 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
4610 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
4613 * If set to 1, this function is selected as Master function.
4614 * This function has responsibility to do 'chip reset' when it
4615 * detects a fatal error. If set to 0, master function functionality
4616 * is disabled on this function.
4618 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
4621 * If set to 1, error recovery is enabled.
4622 * If set to 0, error recovery is disabled.
4624 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
4626 } __attribute__((packed));
4628 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
4629 struct hwrm_async_event_cmpl_func_drvr_unload {
4632 * This field indicates the exact type of the completion.
4633 * By convention, the LSB identifies the length of the
4634 * record in 16B units. Even values indicate 16B
4635 * records. Odd values indicate 32B
4638 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
4640 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
4641 /* HWRM Asynchronous Event Information */
4642 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4644 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
4645 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4646 /* Identifiers of events. */
4648 /* Function driver unloaded */
4649 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
4651 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
4652 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
4653 /* Event specific data */
4654 uint32_t event_data2;
4657 * This value is written by the NIC such that it will be different
4658 * for each pass through the completion queue. The even passes
4659 * will write 1. The odd passes will write 0.
4661 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
4663 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
4665 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
4666 /* 8-lsb timestamp from POR (100-msec resolution) */
4667 uint8_t timestamp_lo;
4668 /* 16-lsb timestamp from POR (100-msec resolution) */
4669 uint16_t timestamp_hi;
4670 /* Event specific data */
4671 uint32_t event_data1;
4673 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4675 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
4677 } __attribute__((packed));
4679 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
4680 struct hwrm_async_event_cmpl_func_drvr_load {
4683 * This field indicates the exact type of the completion.
4684 * By convention, the LSB identifies the length of the
4685 * record in 16B units. Even values indicate 16B
4686 * records. Odd values indicate 32B
4689 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
4691 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
4692 /* HWRM Asynchronous Event Information */
4693 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4695 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
4696 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4697 /* Identifiers of events. */
4699 /* Function driver loaded */
4700 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
4702 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
4703 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
4704 /* Event specific data */
4705 uint32_t event_data2;
4708 * This value is written by the NIC such that it will be different
4709 * for each pass through the completion queue. The even passes
4710 * will write 1. The odd passes will write 0.
4712 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
4714 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4715 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
4716 /* 8-lsb timestamp from POR (100-msec resolution) */
4717 uint8_t timestamp_lo;
4718 /* 16-lsb timestamp from POR (100-msec resolution) */
4719 uint16_t timestamp_hi;
4720 /* Event specific data */
4721 uint32_t event_data1;
4723 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4725 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4726 } __attribute__((packed));
4728 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
4729 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
4732 * This field indicates the exact type of the completion.
4733 * By convention, the LSB identifies the length of the
4734 * record in 16B units. Even values indicate 16B
4735 * records. Odd values indicate 32B
4738 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
4740 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
4742 /* HWRM Asynchronous Event Information */
4743 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
4745 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
4746 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
4747 /* Identifiers of events. */
4749 /* Function FLR related processing has completed */
4750 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4752 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
4753 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
4754 /* Event specific data */
4755 uint32_t event_data2;
4758 * This value is written by the NIC such that it will be different
4759 * for each pass through the completion queue. The even passes
4760 * will write 1. The odd passes will write 0.
4762 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
4765 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
4767 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
4768 /* 8-lsb timestamp from POR (100-msec resolution) */
4769 uint8_t timestamp_lo;
4770 /* 16-lsb timestamp from POR (100-msec resolution) */
4771 uint16_t timestamp_hi;
4772 /* Event specific data */
4773 uint32_t event_data1;
4775 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
4777 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
4779 } __attribute__((packed));
4781 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
4782 struct hwrm_async_event_cmpl_pf_drvr_unload {
4785 * This field indicates the exact type of the completion.
4786 * By convention, the LSB identifies the length of the
4787 * record in 16B units. Even values indicate 16B
4788 * records. Odd values indicate 32B
4791 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
4793 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
4794 /* HWRM Asynchronous Event Information */
4795 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4797 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
4798 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4799 /* Identifiers of events. */
4801 /* PF driver unloaded */
4802 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
4804 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
4805 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
4806 /* Event specific data */
4807 uint32_t event_data2;
4810 * This value is written by the NIC such that it will be different
4811 * for each pass through the completion queue. The even passes
4812 * will write 1. The odd passes will write 0.
4814 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
4816 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
4817 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
4818 /* 8-lsb timestamp from POR (100-msec resolution) */
4819 uint8_t timestamp_lo;
4820 /* 16-lsb timestamp from POR (100-msec resolution) */
4821 uint16_t timestamp_hi;
4822 /* Event specific data */
4823 uint32_t event_data1;
4825 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4827 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
4828 /* Indicates the physical port this pf belongs to */
4829 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
4831 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
4832 } __attribute__((packed));
4834 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
4835 struct hwrm_async_event_cmpl_pf_drvr_load {
4838 * This field indicates the exact type of the completion.
4839 * By convention, the LSB identifies the length of the
4840 * record in 16B units. Even values indicate 16B
4841 * records. Odd values indicate 32B
4844 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4846 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4847 /* HWRM Asynchronous Event Information */
4848 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4850 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4851 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4852 /* Identifiers of events. */
4854 /* PF driver loaded */
4855 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4857 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4858 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4859 /* Event specific data */
4860 uint32_t event_data2;
4863 * This value is written by the NIC such that it will be different
4864 * for each pass through the completion queue. The even passes
4865 * will write 1. The odd passes will write 0.
4867 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4869 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4870 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4871 /* 8-lsb timestamp from POR (100-msec resolution) */
4872 uint8_t timestamp_lo;
4873 /* 16-lsb timestamp from POR (100-msec resolution) */
4874 uint16_t timestamp_hi;
4875 /* Event specific data */
4876 uint32_t event_data1;
4878 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4880 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4881 /* Indicates the physical port this pf belongs to */
4882 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4884 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4885 } __attribute__((packed));
4887 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4888 struct hwrm_async_event_cmpl_vf_flr {
4891 * This field indicates the exact type of the completion.
4892 * By convention, the LSB identifies the length of the
4893 * record in 16B units. Even values indicate 16B
4894 * records. Odd values indicate 32B
4897 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4899 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4900 /* HWRM Asynchronous Event Information */
4901 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4903 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4904 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4905 /* Identifiers of events. */
4907 /* VF Function Level Reset (FLR) */
4908 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4909 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4910 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4911 /* Event specific data */
4912 uint32_t event_data2;
4915 * This value is written by the NIC such that it will be different
4916 * for each pass through the completion queue. The even passes
4917 * will write 1. The odd passes will write 0.
4919 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4921 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4922 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4923 /* 8-lsb timestamp from POR (100-msec resolution) */
4924 uint8_t timestamp_lo;
4925 /* 16-lsb timestamp from POR (100-msec resolution) */
4926 uint16_t timestamp_hi;
4927 /* Event specific data */
4928 uint32_t event_data1;
4930 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4932 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
4933 /* Indicates the physical function this event occurred on. */
4934 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
4936 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
4937 } __attribute__((packed));
4939 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
4940 struct hwrm_async_event_cmpl_vf_mac_addr_change {
4943 * This field indicates the exact type of the completion.
4944 * By convention, the LSB identifies the length of the
4945 * record in 16B units. Even values indicate 16B
4946 * records. Odd values indicate 32B
4949 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
4951 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
4952 /* HWRM Asynchronous Event Information */
4953 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4955 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
4956 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
4957 /* Identifiers of events. */
4959 /* VF MAC Address Change */
4960 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
4962 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
4963 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
4964 /* Event specific data */
4965 uint32_t event_data2;
4968 * This value is written by the NIC such that it will be different
4969 * for each pass through the completion queue. The even passes
4970 * will write 1. The odd passes will write 0.
4972 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
4975 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
4977 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
4978 /* 8-lsb timestamp from POR (100-msec resolution) */
4979 uint8_t timestamp_lo;
4980 /* 16-lsb timestamp from POR (100-msec resolution) */
4981 uint16_t timestamp_hi;
4982 /* Event specific data */
4983 uint32_t event_data1;
4985 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
4987 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
4989 } __attribute__((packed));
4991 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
4992 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
4995 * This field indicates the exact type of the completion.
4996 * By convention, the LSB identifies the length of the
4997 * record in 16B units. Even values indicate 16B
4998 * records. Odd values indicate 32B
5001 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5003 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5005 /* HWRM Asynchronous Event Information */
5006 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5008 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5009 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5010 /* Identifiers of events. */
5012 /* PF-VF communication channel status change. */
5013 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5015 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5016 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5017 /* Event specific data */
5018 uint32_t event_data2;
5021 * This value is written by the NIC such that it will be different
5022 * for each pass through the completion queue. The even passes
5023 * will write 1. The odd passes will write 0.
5025 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5028 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5030 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5031 /* 8-lsb timestamp from POR (100-msec resolution) */
5032 uint8_t timestamp_lo;
5033 /* 16-lsb timestamp from POR (100-msec resolution) */
5034 uint16_t timestamp_hi;
5035 /* Event specific data */
5036 uint32_t event_data1;
5038 * If this bit is set to 1, then it indicates that the PF-VF
5039 * communication was lost and it is established.
5040 * If this bit set to 0, then it indicates that the PF-VF
5041 * communication was established and it is lost.
5043 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5045 } __attribute__((packed));
5047 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5048 struct hwrm_async_event_cmpl_vf_cfg_change {
5051 * This field indicates the exact type of the completion.
5052 * By convention, the LSB identifies the length of the
5053 * record in 16B units. Even values indicate 16B
5054 * records. Odd values indicate 32B
5057 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5059 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5060 /* HWRM Asynchronous Event Information */
5061 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5063 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5064 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5065 /* Identifiers of events. */
5067 /* VF Configuration Change */
5068 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5070 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5071 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5072 /* Event specific data */
5073 uint32_t event_data2;
5076 * This value is written by the NIC such that it will be different
5077 * for each pass through the completion queue. The even passes
5078 * will write 1. The odd passes will write 0.
5080 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5082 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5083 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5084 /* 8-lsb timestamp from POR (100-msec resolution) */
5085 uint8_t timestamp_lo;
5086 /* 16-lsb timestamp from POR (100-msec resolution) */
5087 uint16_t timestamp_hi;
5089 * Each flag provided in this field indicates a specific VF
5090 * configuration change. At least one of these flags shall be set to 1
5091 * when an asynchronous event completion of this type is provided
5094 uint32_t event_data1;
5096 * If this bit is set to 1, then the value of MTU
5097 * was changed on this VF.
5098 * If set to 0, then this bit should be ignored.
5100 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5103 * If this bit is set to 1, then the value of MRU
5104 * was changed on this VF.
5105 * If set to 0, then this bit should be ignored.
5107 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5110 * If this bit is set to 1, then the value of default MAC
5111 * address was changed on this VF.
5112 * If set to 0, then this bit should be ignored.
5114 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5117 * If this bit is set to 1, then the value of default VLAN
5118 * was changed on this VF.
5119 * If set to 0, then this bit should be ignored.
5121 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5124 * If this bit is set to 1, then the value of trusted VF enable
5125 * was changed on this VF.
5126 * If set to 0, then this bit should be ignored.
5128 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5130 } __attribute__((packed));
5132 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5133 struct hwrm_async_event_cmpl_llfc_pfc_change {
5136 * This field indicates the exact type of the completion.
5137 * By convention, the LSB identifies the length of the
5138 * record in 16B units. Even values indicate 16B
5139 * records. Odd values indicate 32B
5142 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5144 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5145 /* HWRM Asynchronous Event Information */
5146 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5148 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5149 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5150 /* unused1 is 10 b */
5151 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5153 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5154 /* Identifiers of events. */
5156 /* LLFC/PFC Configuration Change */
5157 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5159 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5160 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5161 /* Event specific data */
5162 uint32_t event_data2;
5165 * This value is written by the NIC such that it will be different
5166 * for each pass through the completion queue. The even passes
5167 * will write 1. The odd passes will write 0.
5169 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5171 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5173 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5174 /* 8-lsb timestamp from POR (100-msec resolution) */
5175 uint8_t timestamp_lo;
5176 /* 16-lsb timestamp from POR (100-msec resolution) */
5177 uint16_t timestamp_hi;
5178 /* Event specific data */
5179 uint32_t event_data1;
5180 /* Indicates llfc pfc status change */
5181 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5183 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5186 * If this field set to 1, then it indicates that llfc is
5189 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5192 * If this field is set to 2, then it indicates that pfc
5195 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5197 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5198 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5199 /* Indicates the physical port this llfc pfc change occur */
5200 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5202 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5205 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5207 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5209 } __attribute__((packed));
5211 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5212 struct hwrm_async_event_cmpl_default_vnic_change {
5215 * This field indicates the exact type of the completion.
5216 * By convention, the LSB identifies the length of the
5217 * record in 16B units. Even values indicate 16B
5218 * records. Odd values indicate 32B
5221 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5223 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5225 /* HWRM Asynchronous Event Information */
5226 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5228 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5229 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5230 /* unused1 is 10 b */
5231 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5233 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5235 /* Identifiers of events. */
5237 /* Notification of a default vnic allocaiton or free */
5238 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5240 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5241 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5242 /* Event specific data */
5243 uint32_t event_data2;
5246 * This value is written by the NIC such that it will be different
5247 * for each pass through the completion queue. The even passes
5248 * will write 1. The odd passes will write 0.
5250 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5253 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5255 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5256 /* 8-lsb timestamp from POR (100-msec resolution) */
5257 uint8_t timestamp_lo;
5258 /* 16-lsb timestamp from POR (100-msec resolution) */
5259 uint16_t timestamp_hi;
5260 /* Event specific data */
5261 uint32_t event_data1;
5262 /* Indicates default vnic configuration change */
5263 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5265 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5268 * If this field is set to 1, then it indicates that
5269 * a default VNIC has been allocate.
5271 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5274 * If this field is set to 2, then it indicates that
5275 * a default VNIC has been freed.
5277 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5279 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5280 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5281 /* Indicates the physical function this event occurred on. */
5282 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5284 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5286 /* Indicates the virtual function this event occurred on */
5287 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5289 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5291 } __attribute__((packed));
5293 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5294 struct hwrm_async_event_cmpl_hw_flow_aged {
5297 * This field indicates the exact type of the completion.
5298 * By convention, the LSB identifies the length of the
5299 * record in 16B units. Even values indicate 16B
5300 * records. Odd values indicate 32B
5303 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5305 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5306 /* HWRM Asynchronous Event Information */
5307 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5309 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5310 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5311 /* Identifiers of events. */
5313 /* Notification of a hw flow aged */
5314 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5316 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5317 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5318 /* Event specific data */
5319 uint32_t event_data2;
5322 * This value is written by the NIC such that it will be different
5323 * for each pass through the completion queue. The even passes
5324 * will write 1. The odd passes will write 0.
5326 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
5328 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
5329 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
5330 /* 8-lsb timestamp from POR (100-msec resolution) */
5331 uint8_t timestamp_lo;
5332 /* 16-lsb timestamp from POR (100-msec resolution) */
5333 uint16_t timestamp_hi;
5334 /* Event specific data */
5335 uint32_t event_data1;
5336 /* Indicates flow ID this event occurred on. */
5337 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
5338 UINT32_C(0x7fffffff)
5339 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
5341 /* Indicates flow direction this event occurred on. */
5342 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
5343 UINT32_C(0x80000000)
5345 * If this bit set to 0, then it indicates that the aged
5346 * event was rx flow.
5348 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
5349 (UINT32_C(0x0) << 31)
5351 * If this bit is set to 1, then it indicates that the aged
5352 * event was tx flow.
5354 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
5355 (UINT32_C(0x1) << 31)
5356 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
5357 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
5358 } __attribute__((packed));
5360 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
5361 struct hwrm_async_event_cmpl_eem_cache_flush_req {
5364 * This field indicates the exact type of the completion.
5365 * By convention, the LSB identifies the length of the
5366 * record in 16B units. Even values indicate 16B
5367 * records. Odd values indicate 32B
5370 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
5372 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
5374 /* HWRM Asynchronous Event Information */
5375 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
5377 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
5378 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
5379 /* Identifiers of events. */
5381 /* Notification of a eem_cache_flush request */
5382 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
5384 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
5385 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
5386 /* Event specific data */
5387 uint32_t event_data2;
5390 * This value is written by the NIC such that it will be different
5391 * for each pass through the completion queue. The even passes
5392 * will write 1. The odd passes will write 0.
5394 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
5397 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
5399 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
5400 /* 8-lsb timestamp from POR (100-msec resolution) */
5401 uint8_t timestamp_lo;
5402 /* 16-lsb timestamp from POR (100-msec resolution) */
5403 uint16_t timestamp_hi;
5404 /* Event specific data */
5405 uint32_t event_data1;
5406 } __attribute__((packed));
5408 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
5409 struct hwrm_async_event_cmpl_eem_cache_flush_done {
5412 * This field indicates the exact type of the completion.
5413 * By convention, the LSB identifies the length of the
5414 * record in 16B units. Even values indicate 16B
5415 * records. Odd values indicate 32B
5418 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
5420 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
5422 /* HWRM Asynchronous Event Information */
5423 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
5425 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
5426 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
5427 /* Identifiers of events. */
5430 * Notification of a host eem_cache_flush has completed. This event
5431 * is generated by the host driver.
5433 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
5435 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
5436 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
5437 /* Event specific data */
5438 uint32_t event_data2;
5441 * This value is written by the NIC such that it will be different
5442 * for each pass through the completion queue. The even passes
5443 * will write 1. The odd passes will write 0.
5445 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
5448 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
5450 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
5451 /* 8-lsb timestamp from POR (100-msec resolution) */
5452 uint8_t timestamp_lo;
5453 /* 16-lsb timestamp from POR (100-msec resolution) */
5454 uint16_t timestamp_hi;
5455 /* Event specific data */
5456 uint32_t event_data1;
5457 /* Indicates function ID that this event occurred on. */
5458 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
5460 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
5462 } __attribute__((packed));
5464 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
5465 struct hwrm_async_event_cmpl_tcp_flag_action_change {
5468 * This field indicates the exact type of the completion.
5469 * By convention, the LSB identifies the length of the
5470 * record in 16B units. Even values indicate 16B
5471 * records. Odd values indicate 32B
5474 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
5476 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
5478 /* HWRM Asynchronous Event Information */
5479 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5481 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
5482 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
5483 /* Identifiers of events. */
5485 /* Notification of tcp flag action change */
5486 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
5488 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
5489 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
5490 /* Event specific data */
5491 uint32_t event_data2;
5494 * This value is written by the NIC such that it will be different
5495 * for each pass through the completion queue. The even passes
5496 * will write 1. The odd passes will write 0.
5498 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
5501 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
5503 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
5504 /* 8-lsb timestamp from POR (100-msec resolution) */
5505 uint8_t timestamp_lo;
5506 /* 16-lsb timestamp from POR (100-msec resolution) */
5507 uint16_t timestamp_hi;
5508 /* Event specific data */
5509 uint32_t event_data1;
5510 } __attribute__((packed));
5512 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
5513 struct hwrm_async_event_cmpl_eem_flow_active {
5516 * This field indicates the exact type of the completion.
5517 * By convention, the LSB identifies the length of the
5518 * record in 16B units. Even values indicate 16B
5519 * records. Odd values indicate 32B
5522 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
5524 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
5525 /* HWRM Asynchronous Event Information */
5526 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
5528 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
5529 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
5530 /* Identifiers of events. */
5532 /* Notification of an active eem flow */
5533 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
5535 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
5536 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
5537 /* Event specific data */
5538 uint32_t event_data2;
5539 /* Indicates the 2nd global id this event occurred on. */
5540 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
5541 UINT32_C(0x3fffffff)
5542 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
5545 * Indicates flow direction of the flow identified by
5548 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
5549 UINT32_C(0x40000000)
5550 /* If this bit is set to 0, then it indicates that this rx flow. */
5551 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
5552 (UINT32_C(0x0) << 30)
5553 /* If this bit is set to 1, then it indicates that this tx flow. */
5554 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
5555 (UINT32_C(0x1) << 30)
5556 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
5557 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
5560 * This value is written by the NIC such that it will be different
5561 * for each pass through the completion queue. The even passes
5562 * will write 1. The odd passes will write 0.
5564 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
5566 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
5568 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
5569 /* 8-lsb timestamp from POR (100-msec resolution) */
5570 uint8_t timestamp_lo;
5571 /* 16-lsb timestamp from POR (100-msec resolution) */
5572 uint16_t timestamp_hi;
5573 /* Event specific data */
5574 uint32_t event_data1;
5575 /* Indicates the 1st global id this event occurred on. */
5576 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
5577 UINT32_C(0x3fffffff)
5578 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
5581 * Indicates flow direction of the flow identified by the
5584 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
5585 UINT32_C(0x40000000)
5586 /* If this bit is set to 0, then it indicates that this is rx flow. */
5587 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
5588 (UINT32_C(0x0) << 30)
5589 /* If this bit is set to 1, then it indicates that this is tx flow. */
5590 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
5591 (UINT32_C(0x1) << 30)
5592 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
5593 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
5595 * Indicates EEM flow aging mode this event occurred on. If
5596 * this bit is set to 0, the event_data1 is the EEM global
5597 * ID. If this bit is set to 1, the event_data1 is the number
5598 * of global ID in the context memory.
5600 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
5601 UINT32_C(0x80000000)
5602 /* EEM flow aging mode 0. */
5603 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
5604 (UINT32_C(0x0) << 31)
5605 /* EEM flow aging mode 1. */
5606 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
5607 (UINT32_C(0x1) << 31)
5608 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
5609 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
5610 } __attribute__((packed));
5612 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
5613 struct hwrm_async_event_cmpl_eem_cfg_change {
5616 * This field indicates the exact type of the completion.
5617 * By convention, the LSB identifies the length of the
5618 * record in 16B units. Even values indicate 16B
5619 * records. Odd values indicate 32B
5622 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
5624 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
5625 /* HWRM Asynchronous Event Information */
5626 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5628 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
5629 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5630 /* Identifiers of events. */
5632 /* Notification of EEM configuration change */
5633 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
5635 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
5636 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
5637 /* Event specific data */
5638 uint32_t event_data2;
5641 * This value is written by the NIC such that it will be different
5642 * for each pass through the completion queue. The even passes
5643 * will write 1. The odd passes will write 0.
5645 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
5647 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5648 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
5649 /* 8-lsb timestamp from POR (100-msec resolution) */
5650 uint8_t timestamp_lo;
5651 /* 16-lsb timestamp from POR (100-msec resolution) */
5652 uint16_t timestamp_hi;
5653 /* Event specific data */
5654 uint32_t event_data1;
5656 * Value of 1 to indicate EEM TX configuration is enabled. Value of
5657 * 0 to indicate the EEM TX configuration is disabled.
5659 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
5662 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
5663 * to indicate the EEM RX configuration is disabled.
5665 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
5667 } __attribute__((packed));
5669 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
5670 struct hwrm_async_event_cmpl_fw_trace_msg {
5673 * This field indicates the exact type of the completion.
5674 * By convention, the LSB identifies the length of the
5675 * record in 16B units. Even values indicate 16B
5676 * records. Odd values indicate 32B
5679 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
5681 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
5682 /* HWRM Asynchronous Event Information */
5683 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
5685 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
5686 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
5687 /* Identifiers of events. */
5689 /* Firmware trace log message */
5690 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
5692 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
5693 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
5694 /* Trace byte 0 to 3 */
5695 uint32_t event_data2;
5697 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
5699 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
5701 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
5703 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
5705 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
5707 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
5709 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
5710 UINT32_C(0xff000000)
5711 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
5714 * This value is written by the NIC such that it will be different
5715 * for each pass through the completion queue. The even passes
5716 * will write 1. The odd passes will write 0.
5718 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
5720 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
5721 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
5723 uint8_t timestamp_lo;
5724 /* Indicates if the string is partial or complete. */
5725 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
5727 /* Complete string */
5728 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
5730 /* Partial string */
5731 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
5733 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
5734 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
5735 /* Indicates the firmware that sent the trace message. */
5736 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
5738 /* Primary firmware */
5739 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
5740 (UINT32_C(0x0) << 1)
5741 /* Secondary firmware */
5742 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
5743 (UINT32_C(0x1) << 1)
5744 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
5745 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
5746 /* Trace byte 4 to 5 */
5747 uint16_t timestamp_hi;
5749 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
5751 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
5753 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
5755 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
5756 /* Trace byte 6 to 9 */
5757 uint32_t event_data1;
5759 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
5761 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
5763 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
5765 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
5767 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
5769 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
5771 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
5772 UINT32_C(0xff000000)
5773 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
5774 } __attribute__((packed));
5776 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
5777 struct hwrm_async_event_cmpl_hwrm_error {
5780 * This field indicates the exact type of the completion.
5781 * By convention, the LSB identifies the length of the
5782 * record in 16B units. Even values indicate 16B
5783 * records. Odd values indicate 32B
5786 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
5788 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
5789 /* HWRM Asynchronous Event Information */
5790 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
5792 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
5793 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
5794 /* Identifiers of events. */
5797 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
5799 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
5800 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
5801 /* Event specific data */
5802 uint32_t event_data2;
5803 /* Severity of HWRM Error */
5804 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
5806 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
5808 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
5810 /* Non-fatal Error */
5811 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
5814 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
5816 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
5817 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
5820 * This value is written by the NIC such that it will be different
5821 * for each pass through the completion queue. The even passes
5822 * will write 1. The odd passes will write 0.
5824 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
5826 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
5827 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
5828 /* 8-lsb timestamp from POR (100-msec resolution) */
5829 uint8_t timestamp_lo;
5830 /* 16-lsb timestamp from POR (100-msec resolution) */
5831 uint16_t timestamp_hi;
5832 /* Event specific data */
5833 uint32_t event_data1;
5834 /* Time stamp for error event */
5835 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
5837 } __attribute__((packed));
5839 /*******************
5841 *******************/
5844 /* hwrm_func_reset_input (size:192b/24B) */
5845 struct hwrm_func_reset_input {
5846 /* The HWRM command request type. */
5849 * The completion ring to send the completion event on. This should
5850 * be the NQ ID returned from the `nq_alloc` HWRM command.
5854 * The sequence ID is used by the driver for tracking multiple
5855 * commands. This ID is treated as opaque data by the firmware and
5856 * the value is returned in the `hwrm_resp_hdr` upon completion.
5860 * The target ID of the command:
5861 * * 0x0-0xFFF8 - The function ID
5862 * * 0xFFF8-0xFFFE - Reserved for internal processors
5867 * A physical address pointer pointing to a host buffer that the
5868 * command's response data will be written. This can be either a host
5869 * physical address (HPA) or a guest physical address (GPA) and must
5870 * point to a physically contiguous block of memory.
5875 * This bit must be '1' for the vf_id_valid field to be
5878 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
5880 * The ID of the VF that this PF is trying to reset.
5881 * Only the parent PF shall be allowed to reset a child VF.
5883 * A parent PF driver shall use this field only when a specific child VF
5884 * is requested to be reset.
5887 /* This value indicates the level of a function reset. */
5888 uint8_t func_reset_level;
5890 * Reset the caller function and its children VFs (if any). If no
5891 * children functions exist, then reset the caller function only.
5893 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
5895 /* Reset the caller function only */
5896 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
5899 * Reset all children VFs of the caller function driver if the
5900 * caller is a PF driver.
5901 * It is an error to specify this level by a VF driver.
5902 * It is an error to specify this level by a PF driver with
5905 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
5908 * Reset a specific VF of the caller function driver if the caller
5909 * is the parent PF driver.
5910 * It is an error to specify this level by a VF driver.
5911 * It is an error to specify this level by a PF driver that is not
5912 * the parent of the VF that is being requested to reset.
5914 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
5916 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
5917 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
5919 } __attribute__((packed));
5921 /* hwrm_func_reset_output (size:128b/16B) */
5922 struct hwrm_func_reset_output {
5923 /* The specific error status for the command. */
5924 uint16_t error_code;
5925 /* The HWRM command request type. */
5927 /* The sequence ID from the original command. */
5929 /* The length of the response data in number of bytes. */
5931 uint8_t unused_0[7];
5933 * This field is used in Output records to indicate that the output
5934 * is completely written to RAM. This field should be read as '1'
5935 * to indicate that the output has been completely written.
5936 * When writing a command completion or response to an internal processor,
5937 * the order of writes has to be such that this field is written last.
5940 } __attribute__((packed));
5942 /********************
5943 * hwrm_func_getfid *
5944 ********************/
5947 /* hwrm_func_getfid_input (size:192b/24B) */
5948 struct hwrm_func_getfid_input {
5949 /* The HWRM command request type. */
5952 * The completion ring to send the completion event on. This should
5953 * be the NQ ID returned from the `nq_alloc` HWRM command.
5957 * The sequence ID is used by the driver for tracking multiple
5958 * commands. This ID is treated as opaque data by the firmware and
5959 * the value is returned in the `hwrm_resp_hdr` upon completion.
5963 * The target ID of the command:
5964 * * 0x0-0xFFF8 - The function ID
5965 * * 0xFFF8-0xFFFE - Reserved for internal processors
5970 * A physical address pointer pointing to a host buffer that the
5971 * command's response data will be written. This can be either a host
5972 * physical address (HPA) or a guest physical address (GPA) and must
5973 * point to a physically contiguous block of memory.
5978 * This bit must be '1' for the pci_id field to be
5981 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
5983 * This value is the PCI ID of the queried function.
5984 * If ARI is enabled, then it is
5985 * Bus Number (8b):Function Number(8b). Otherwise, it is
5986 * Bus Number (8b):Device Number (5b):Function Number(3b).
5989 uint8_t unused_0[2];
5990 } __attribute__((packed));
5992 /* hwrm_func_getfid_output (size:128b/16B) */
5993 struct hwrm_func_getfid_output {
5994 /* The specific error status for the command. */
5995 uint16_t error_code;
5996 /* The HWRM command request type. */
5998 /* The sequence ID from the original command. */
6000 /* The length of the response data in number of bytes. */
6003 * FID value. This value is used to identify operations on the PCI
6004 * bus as belonging to a particular PCI function.
6007 uint8_t unused_0[5];
6009 * This field is used in Output records to indicate that the output
6010 * is completely written to RAM. This field should be read as '1'
6011 * to indicate that the output has been completely written.
6012 * When writing a command completion or response to an internal processor,
6013 * the order of writes has to be such that this field is written last.
6016 } __attribute__((packed));
6018 /**********************
6019 * hwrm_func_vf_alloc *
6020 **********************/
6023 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6024 struct hwrm_func_vf_alloc_input {
6025 /* The HWRM command request type. */
6028 * The completion ring to send the completion event on. This should
6029 * be the NQ ID returned from the `nq_alloc` HWRM command.
6033 * The sequence ID is used by the driver for tracking multiple
6034 * commands. This ID is treated as opaque data by the firmware and
6035 * the value is returned in the `hwrm_resp_hdr` upon completion.
6039 * The target ID of the command:
6040 * * 0x0-0xFFF8 - The function ID
6041 * * 0xFFF8-0xFFFE - Reserved for internal processors
6046 * A physical address pointer pointing to a host buffer that the
6047 * command's response data will be written. This can be either a host
6048 * physical address (HPA) or a guest physical address (GPA) and must
6049 * point to a physically contiguous block of memory.
6054 * This bit must be '1' for the first_vf_id field to be
6057 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6059 * This value is used to identify a Virtual Function (VF).
6060 * The scope of VF ID is local within a PF.
6062 uint16_t first_vf_id;
6063 /* The number of virtual functions requested. */
6065 } __attribute__((packed));
6067 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6068 struct hwrm_func_vf_alloc_output {
6069 /* The specific error status for the command. */
6070 uint16_t error_code;
6071 /* The HWRM command request type. */
6073 /* The sequence ID from the original command. */
6075 /* The length of the response data in number of bytes. */
6077 /* The ID of the first VF allocated. */
6078 uint16_t first_vf_id;
6079 uint8_t unused_0[5];
6081 * This field is used in Output records to indicate that the output
6082 * is completely written to RAM. This field should be read as '1'
6083 * to indicate that the output has been completely written.
6084 * When writing a command completion or response to an internal processor,
6085 * the order of writes has to be such that this field is written last.
6088 } __attribute__((packed));
6090 /*********************
6091 * hwrm_func_vf_free *
6092 *********************/
6095 /* hwrm_func_vf_free_input (size:192b/24B) */
6096 struct hwrm_func_vf_free_input {
6097 /* The HWRM command request type. */
6100 * The completion ring to send the completion event on. This should
6101 * be the NQ ID returned from the `nq_alloc` HWRM command.
6105 * The sequence ID is used by the driver for tracking multiple
6106 * commands. This ID is treated as opaque data by the firmware and
6107 * the value is returned in the `hwrm_resp_hdr` upon completion.
6111 * The target ID of the command:
6112 * * 0x0-0xFFF8 - The function ID
6113 * * 0xFFF8-0xFFFE - Reserved for internal processors
6118 * A physical address pointer pointing to a host buffer that the
6119 * command's response data will be written. This can be either a host
6120 * physical address (HPA) or a guest physical address (GPA) and must
6121 * point to a physically contiguous block of memory.
6126 * This bit must be '1' for the first_vf_id field to be
6129 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6131 * This value is used to identify a Virtual Function (VF).
6132 * The scope of VF ID is local within a PF.
6134 uint16_t first_vf_id;
6136 * The number of virtual functions requested.
6137 * 0xFFFF - Cleanup all children of this PF.
6140 } __attribute__((packed));
6142 /* hwrm_func_vf_free_output (size:128b/16B) */
6143 struct hwrm_func_vf_free_output {
6144 /* The specific error status for the command. */
6145 uint16_t error_code;
6146 /* The HWRM command request type. */
6148 /* The sequence ID from the original command. */
6150 /* The length of the response data in number of bytes. */
6152 uint8_t unused_0[7];
6154 * This field is used in Output records to indicate that the output
6155 * is completely written to RAM. This field should be read as '1'
6156 * to indicate that the output has been completely written.
6157 * When writing a command completion or response to an internal processor,
6158 * the order of writes has to be such that this field is written last.
6161 } __attribute__((packed));
6163 /********************
6164 * hwrm_func_vf_cfg *
6165 ********************/
6168 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6169 struct hwrm_func_vf_cfg_input {
6170 /* The HWRM command request type. */
6173 * The completion ring to send the completion event on. This should
6174 * be the NQ ID returned from the `nq_alloc` HWRM command.
6178 * The sequence ID is used by the driver for tracking multiple
6179 * commands. This ID is treated as opaque data by the firmware and
6180 * the value is returned in the `hwrm_resp_hdr` upon completion.
6184 * The target ID of the command:
6185 * * 0x0-0xFFF8 - The function ID
6186 * * 0xFFF8-0xFFFE - Reserved for internal processors
6191 * A physical address pointer pointing to a host buffer that the
6192 * command's response data will be written. This can be either a host
6193 * physical address (HPA) or a guest physical address (GPA) and must
6194 * point to a physically contiguous block of memory.
6199 * This bit must be '1' for the mtu field to be
6202 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6205 * This bit must be '1' for the guest_vlan field to be
6208 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6211 * This bit must be '1' for the async_event_cr field to be
6214 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6217 * This bit must be '1' for the dflt_mac_addr field to be
6220 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6223 * This bit must be '1' for the num_rsscos_ctxs field to be
6226 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6229 * This bit must be '1' for the num_cmpl_rings field to be
6232 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6235 * This bit must be '1' for the num_tx_rings field to be
6238 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6241 * This bit must be '1' for the num_rx_rings field to be
6244 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6247 * This bit must be '1' for the num_l2_ctxs field to be
6250 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6253 * This bit must be '1' for the num_vnics field to be
6256 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
6259 * This bit must be '1' for the num_stat_ctxs field to be
6262 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6265 * This bit must be '1' for the num_hw_ring_grps field to be
6268 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6271 * The maximum transmission unit requested on the function.
6272 * The HWRM should make sure that the mtu of
6273 * the function does not exceed the mtu of the physical
6274 * port that this function is associated with.
6276 * In addition to requesting mtu per function, it is
6277 * possible to configure mtu per transmit ring.
6278 * By default, the mtu of each transmit ring associated
6279 * with a function is equal to the mtu of the function.
6280 * The HWRM should make sure that the mtu of each transmit
6281 * ring that is assigned to a function has a valid mtu.
6285 * The guest VLAN for the function being configured.
6286 * This field's format is same as 802.1Q Tag's
6287 * Tag Control Information (TCI) format that includes both
6288 * Priority Code Point (PCP) and VLAN Identifier (VID).
6290 uint16_t guest_vlan;
6292 * ID of the target completion ring for receiving asynchronous
6293 * event completions. If this field is not valid, then the
6294 * HWRM shall use the default completion ring of the function
6295 * that is being configured as the target completion ring for
6296 * providing any asynchronous event completions for that
6298 * If this field is valid, then the HWRM shall use the
6299 * completion ring identified by this ID as the target
6300 * completion ring for providing any asynchronous event
6301 * completions for the function that is being configured.
6303 uint16_t async_event_cr;
6305 * This value is the current MAC address requested by the VF
6306 * driver to be configured on this VF. A value of
6307 * 00-00-00-00-00-00 indicates no MAC address configuration
6308 * is requested by the VF driver.
6309 * The parent PF driver may reject or overwrite this
6312 uint8_t dflt_mac_addr[6];
6315 * This bit requests that the firmware test to see if all the assets
6316 * requested in this command (i.e. number of TX rings) are available.
6317 * The firmware will return an error if the requested assets are
6318 * not available. The firwmare will NOT reserve the assets if they
6321 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6324 * This bit requests that the firmware test to see if all the assets
6325 * requested in this command (i.e. number of RX rings) are available.
6326 * The firmware will return an error if the requested assets are
6327 * not available. The firwmare will NOT reserve the assets if they
6330 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6333 * This bit requests that the firmware test to see if all the assets
6334 * requested in this command (i.e. number of CMPL rings) are available.
6335 * The firmware will return an error if the requested assets are
6336 * not available. The firwmare will NOT reserve the assets if they
6339 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6342 * This bit requests that the firmware test to see if all the assets
6343 * requested in this command (i.e. number of RSS ctx) are available.
6344 * The firmware will return an error if the requested assets are
6345 * not available. The firwmare will NOT reserve the assets if they
6348 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6351 * This bit requests that the firmware test to see if all the assets
6352 * requested in this command (i.e. number of ring groups) are available.
6353 * The firmware will return an error if the requested assets are
6354 * not available. The firwmare will NOT reserve the assets if they
6357 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6360 * This bit requests that the firmware test to see if all the assets
6361 * requested in this command (i.e. number of stat ctx) are available.
6362 * The firmware will return an error if the requested assets are
6363 * not available. The firwmare will NOT reserve the assets if they
6366 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6369 * This bit requests that the firmware test to see if all the assets
6370 * requested in this command (i.e. number of VNICs) are available.
6371 * The firmware will return an error if the requested assets are
6372 * not available. The firwmare will NOT reserve the assets if they
6375 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6378 * This bit requests that the firmware test to see if all the assets
6379 * requested in this command (i.e. number of L2 ctx) are available.
6380 * The firmware will return an error if the requested assets are
6381 * not available. The firwmare will NOT reserve the assets if they
6384 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6386 /* The number of RSS/COS contexts requested for the VF. */
6387 uint16_t num_rsscos_ctxs;
6388 /* The number of completion rings requested for the VF. */
6389 uint16_t num_cmpl_rings;
6390 /* The number of transmit rings requested for the VF. */
6391 uint16_t num_tx_rings;
6392 /* The number of receive rings requested for the VF. */
6393 uint16_t num_rx_rings;
6394 /* The number of L2 contexts requested for the VF. */
6395 uint16_t num_l2_ctxs;
6396 /* The number of vnics requested for the VF. */
6398 /* The number of statistic contexts requested for the VF. */
6399 uint16_t num_stat_ctxs;
6400 /* The number of HW ring groups requested for the VF. */
6401 uint16_t num_hw_ring_grps;
6402 uint8_t unused_0[4];
6403 } __attribute__((packed));
6405 /* hwrm_func_vf_cfg_output (size:128b/16B) */
6406 struct hwrm_func_vf_cfg_output {
6407 /* The specific error status for the command. */
6408 uint16_t error_code;
6409 /* The HWRM command request type. */
6411 /* The sequence ID from the original command. */
6413 /* The length of the response data in number of bytes. */
6415 uint8_t unused_0[7];
6417 * This field is used in Output records to indicate that the output
6418 * is completely written to RAM. This field should be read as '1'
6419 * to indicate that the output has been completely written.
6420 * When writing a command completion or response to an internal processor,
6421 * the order of writes has to be such that this field is written last.
6424 } __attribute__((packed));
6426 /*******************
6428 *******************/
6431 /* hwrm_func_qcaps_input (size:192b/24B) */
6432 struct hwrm_func_qcaps_input {
6433 /* The HWRM command request type. */
6436 * The completion ring to send the completion event on. This should
6437 * be the NQ ID returned from the `nq_alloc` HWRM command.
6441 * The sequence ID is used by the driver for tracking multiple
6442 * commands. This ID is treated as opaque data by the firmware and
6443 * the value is returned in the `hwrm_resp_hdr` upon completion.
6447 * The target ID of the command:
6448 * * 0x0-0xFFF8 - The function ID
6449 * * 0xFFF8-0xFFFE - Reserved for internal processors
6454 * A physical address pointer pointing to a host buffer that the
6455 * command's response data will be written. This can be either a host
6456 * physical address (HPA) or a guest physical address (GPA) and must
6457 * point to a physically contiguous block of memory.
6461 * Function ID of the function that is being queried.
6462 * 0xFF... (All Fs) if the query is for the requesting
6466 uint8_t unused_0[6];
6467 } __attribute__((packed));
6469 /* hwrm_func_qcaps_output (size:640b/80B) */
6470 struct hwrm_func_qcaps_output {
6471 /* The specific error status for the command. */
6472 uint16_t error_code;
6473 /* The HWRM command request type. */
6475 /* The sequence ID from the original command. */
6477 /* The length of the response data in number of bytes. */
6480 * FID value. This value is used to identify operations on the PCI
6481 * bus as belonging to a particular PCI function.
6485 * Port ID of port that this function is associated with.
6486 * Valid only for the PF.
6487 * 0xFF... (All Fs) if this function is not associated with
6489 * 0xFF... (All Fs) if this function is called from a VF.
6493 /* If 1, then Push mode is supported on this function. */
6494 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
6497 * If 1, then the global MSI-X auto-masking is enabled for the
6500 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
6503 * If 1, then the Precision Time Protocol (PTP) processing
6504 * is supported on this function.
6505 * The HWRM should enable PTP on only a single Physical
6506 * Function (PF) per port.
6508 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
6511 * If 1, then RDMA over Converged Ethernet (RoCE) v1
6512 * is supported on this function.
6514 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
6517 * If 1, then RDMA over Converged Ethernet (RoCE) v2
6518 * is supported on this function.
6520 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
6523 * If 1, then control and configuration of WoL magic packet
6524 * are supported on this function.
6526 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
6529 * If 1, then control and configuration of bitmap pattern
6530 * packet are supported on this function.
6532 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
6535 * If set to 1, then the control and configuration of rate limit
6536 * of an allocated TX ring on the queried function is supported.
6538 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
6541 * If 1, then control and configuration of minimum and
6542 * maximum bandwidths are supported on the queried function.
6544 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
6547 * If the query is for a VF, then this flag shall be ignored.
6548 * If this query is for a PF and this flag is set to 1,
6549 * then the PF has the capability to set the rate limits
6550 * on the TX rings of its children VFs.
6551 * If this query is for a PF and this flag is set to 0, then
6552 * the PF does not have the capability to set the rate limits
6553 * on the TX rings of its children VFs.
6555 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
6558 * If the query is for a VF, then this flag shall be ignored.
6559 * If this query is for a PF and this flag is set to 1,
6560 * then the PF has the capability to set the minimum and/or
6561 * maximum bandwidths for its children VFs.
6562 * If this query is for a PF and this flag is set to 0, then
6563 * the PF does not have the capability to set the minimum or
6564 * maximum bandwidths for its children VFs.
6566 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
6569 * Standard TX Ring mode is used for the allocation of TX ring
6570 * and underlying scheduling resources that allow bandwidth
6571 * reservation and limit settings on the queried function.
6572 * If set to 1, then standard TX ring mode is supported
6573 * on the queried function.
6574 * If set to 0, then standard TX ring mode is not available
6575 * on the queried function.
6577 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
6580 * If the query is for a VF, then this flag shall be ignored,
6581 * If this query is for a PF and this flag is set to 1,
6582 * then the PF has the capability to detect GENEVE tunnel
6585 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
6588 * If the query is for a VF, then this flag shall be ignored,
6589 * If this query is for a PF and this flag is set to 1,
6590 * then the PF has the capability to detect NVGRE tunnel
6593 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
6596 * If the query is for a VF, then this flag shall be ignored,
6597 * If this query is for a PF and this flag is set to 1,
6598 * then the PF has the capability to detect GRE tunnel
6601 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
6604 * If the query is for a VF, then this flag shall be ignored,
6605 * If this query is for a PF and this flag is set to 1,
6606 * then the PF has the capability to detect MPLS tunnel
6609 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
6612 * If the query is for a VF, then this flag shall be ignored,
6613 * If this query is for a PF and this flag is set to 1,
6614 * then the PF has the capability to support pcie stats.
6616 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
6619 * If the query is for a VF, then this flag shall be ignored,
6620 * If this query is for a PF and this flag is set to 1,
6621 * then the PF has the capability to adopt the VF's belonging
6624 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
6627 * If the query is for a VF, then this flag shall be ignored,
6628 * If this query is for a PF and this flag is set to 1,
6629 * then the PF has the administrative privilege to configure another PF
6631 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
6634 * If the query is for a VF, then this flag shall be ignored.
6635 * If this query is for a PF and this flag is set to 1, then
6636 * the PF will know that the firmware has the capability to track
6637 * the virtual link status.
6639 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
6642 * If 1, then this function supports the push mode that uses
6643 * write combine buffers and the long inline tx buffer descriptor.
6645 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
6648 * If 1, then FW has capability to allocate TX rings dynamically
6649 * in ring alloc even if PF reserved pool is zero.
6650 * This bit will be used only for PFs.
6652 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
6655 * When this bit is '1', it indicates that core firmware is
6656 * capable of Hot Reset.
6658 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
6661 * This flag will be set to 1 by the FW if FW supports adapter error
6664 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
6667 * This value is current MAC address configured for this
6668 * function. A value of 00-00-00-00-00-00 indicates no
6669 * MAC address is currently configured.
6671 uint8_t mac_address[6];
6673 * The maximum number of RSS/COS contexts that can be
6674 * allocated to the function.
6676 uint16_t max_rsscos_ctx;
6678 * The maximum number of completion rings that can be
6679 * allocated to the function.
6681 uint16_t max_cmpl_rings;
6683 * The maximum number of transmit rings that can be
6684 * allocated to the function.
6686 uint16_t max_tx_rings;
6688 * The maximum number of receive rings that can be
6689 * allocated to the function.
6691 uint16_t max_rx_rings;
6693 * The maximum number of L2 contexts that can be
6694 * allocated to the function.
6696 uint16_t max_l2_ctxs;
6698 * The maximum number of VNICs that can be
6699 * allocated to the function.
6703 * The identifier for the first VF enabled on a PF. This
6704 * is valid only on the PF with SR-IOV enabled.
6705 * 0xFF... (All Fs) if this command is called on a PF with
6706 * SR-IOV disabled or on a VF.
6708 uint16_t first_vf_id;
6710 * The maximum number of VFs that can be
6711 * allocated to the function. This is valid only on the
6712 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
6713 * command is called on a PF with SR-IOV disabled or
6718 * The maximum number of statistic contexts that can be
6719 * allocated to the function.
6721 uint16_t max_stat_ctx;
6723 * The maximum number of Encapsulation records that can be
6724 * offloaded by this function.
6726 uint32_t max_encap_records;
6728 * The maximum number of decapsulation records that can
6729 * be offloaded by this function.
6731 uint32_t max_decap_records;
6733 * The maximum number of Exact Match (EM) flows that can be
6734 * offloaded by this function on the TX side.
6736 uint32_t max_tx_em_flows;
6738 * The maximum number of Wildcard Match (WM) flows that can
6739 * be offloaded by this function on the TX side.
6741 uint32_t max_tx_wm_flows;
6743 * The maximum number of Exact Match (EM) flows that can be
6744 * offloaded by this function on the RX side.
6746 uint32_t max_rx_em_flows;
6748 * The maximum number of Wildcard Match (WM) flows that can
6749 * be offloaded by this function on the RX side.
6751 uint32_t max_rx_wm_flows;
6753 * The maximum number of multicast filters that can
6754 * be supported by this function on the RX side.
6756 uint32_t max_mcast_filters;
6758 * The maximum value of flow_id that can be supported
6759 * in completion records.
6761 uint32_t max_flow_id;
6763 * The maximum number of HW ring groups that can be
6764 * supported on this function.
6766 uint32_t max_hw_ring_grps;
6768 * The maximum number of strict priority transmit rings
6769 * that can be allocated to the function.
6770 * This number indicates the maximum number of TX rings
6771 * that can be assigned strict priorities out of the
6772 * maximum number of TX rings that can be allocated
6773 * (max_tx_rings) to the function.
6775 uint16_t max_sp_tx_rings;
6778 * This field is used in Output records to indicate that the output
6779 * is completely written to RAM. This field should be read as '1'
6780 * to indicate that the output has been completely written.
6781 * When writing a command completion or response to an internal processor,
6782 * the order of writes has to be such that this field is written last.
6785 } __attribute__((packed));
6792 /* hwrm_func_qcfg_input (size:192b/24B) */
6793 struct hwrm_func_qcfg_input {
6794 /* The HWRM command request type. */
6797 * The completion ring to send the completion event on. This should
6798 * be the NQ ID returned from the `nq_alloc` HWRM command.
6802 * The sequence ID is used by the driver for tracking multiple
6803 * commands. This ID is treated as opaque data by the firmware and
6804 * the value is returned in the `hwrm_resp_hdr` upon completion.
6808 * The target ID of the command:
6809 * * 0x0-0xFFF8 - The function ID
6810 * * 0xFFF8-0xFFFE - Reserved for internal processors
6815 * A physical address pointer pointing to a host buffer that the
6816 * command's response data will be written. This can be either a host
6817 * physical address (HPA) or a guest physical address (GPA) and must
6818 * point to a physically contiguous block of memory.
6822 * Function ID of the function that is being queried.
6823 * 0xFF... (All Fs) if the query is for the requesting
6827 uint8_t unused_0[6];
6828 } __attribute__((packed));
6830 /* hwrm_func_qcfg_output (size:704b/88B) */
6831 struct hwrm_func_qcfg_output {
6832 /* The specific error status for the command. */
6833 uint16_t error_code;
6834 /* The HWRM command request type. */
6836 /* The sequence ID from the original command. */
6838 /* The length of the response data in number of bytes. */
6841 * FID value. This value is used to identify operations on the PCI
6842 * bus as belonging to a particular PCI function.
6846 * Port ID of port that this function is associated with.
6847 * 0xFF... (All Fs) if this function is not associated with
6852 * This value is the current VLAN setting for this
6853 * function. The value of 0 for this field indicates
6854 * no priority tagging or VLAN is used.
6855 * This field's format is same as 802.1Q Tag's
6856 * Tag Control Information (TCI) format that includes both
6857 * Priority Code Point (PCP) and VLAN Identifier (VID).
6862 * If 1, then magic packet based Out-Of-Box WoL is enabled on
6863 * the port associated with this function.
6865 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
6868 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
6869 * on the port associated with this function.
6871 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
6874 * If set to 1, then FW based DCBX agent is enabled and running on
6875 * the port associated with this function.
6876 * If set to 0, then DCBX agent is not running in the firmware.
6878 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
6881 * Standard TX Ring mode is used for the allocation of TX ring
6882 * and underlying scheduling resources that allow bandwidth
6883 * reservation and limit settings on the queried function.
6884 * If set to 1, then standard TX ring mode is enabled
6885 * on the queried function.
6886 * If set to 0, then the standard TX ring mode is disabled
6887 * on the queried function. In this extended TX ring resource
6888 * mode, the minimum and maximum bandwidth settings are not
6889 * supported to allow the allocation of TX rings to span multiple
6892 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
6895 * If set to 1 then FW based LLDP agent is enabled and running on
6896 * the port associated with this function.
6897 * If set to 0 then the LLDP agent is not running in the firmware.
6899 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
6902 * If set to 1, then multi-host mode is active for this function.
6903 * If set to 0, then multi-host mode is inactive for this function
6904 * or not applicable for this device.
6906 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
6909 * If the function that is being queried is a PF, then the HWRM shall
6910 * set this field to 0 and the HWRM client shall ignore this field.
6911 * If the function that is being queried is a VF, then the HWRM shall
6912 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
6913 * shall set this field to 0.
6915 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
6918 * If set to 1, then secure mode is enabled for this function or device.
6919 * If set to 0, then secure mode is disabled (or normal mode) for this
6920 * function or device.
6922 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
6925 * This value is current MAC address configured for this
6926 * function. A value of 00-00-00-00-00-00 indicates no
6927 * MAC address is currently configured.
6929 uint8_t mac_address[6];
6931 * This value is current PCI ID of this
6932 * function. If ARI is enabled, then it is
6933 * Bus Number (8b):Function Number(8b). Otherwise, it is
6934 * Bus Number (8b):Device Number (4b):Function Number(4b).
6935 * If multi-host mode is active, the 4 lsb will indicate
6936 * the PF index for this function.
6940 * The number of RSS/COS contexts currently
6941 * allocated to the function.
6943 uint16_t alloc_rsscos_ctx;
6945 * The number of completion rings currently allocated to
6946 * the function. This does not include the rings allocated
6947 * to any children functions if any.
6949 uint16_t alloc_cmpl_rings;
6951 * The number of transmit rings currently allocated to
6952 * the function. This does not include the rings allocated
6953 * to any children functions if any.
6955 uint16_t alloc_tx_rings;
6957 * The number of receive rings currently allocated to
6958 * the function. This does not include the rings allocated
6959 * to any children functions if any.
6961 uint16_t alloc_rx_rings;
6962 /* The allocated number of L2 contexts to the function. */
6963 uint16_t alloc_l2_ctx;
6964 /* The allocated number of vnics to the function. */
6965 uint16_t alloc_vnics;
6967 * The maximum transmission unit of the function.
6968 * If the reported mtu value is non-zero then it will used for the
6969 * rings allocated on this function. otherwise the default
6970 * value is used if ring MTU is not specified.
6974 * The maximum receive unit of the function.
6975 * For vnics allocated on this function, this default
6976 * value is used if vnic MRU is not specified.
6979 /* The statistics context assigned to a function. */
6980 uint16_t stat_ctx_id;
6982 * The HWRM shall return Unknown value for this field
6983 * when this command is used to query VF's configuration.
6985 uint8_t port_partition_type;
6986 /* Single physical function */
6987 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
6988 /* Multiple physical functions */
6989 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
6990 /* Network Partitioning 1.0 */
6991 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
6992 /* Network Partitioning 1.5 */
6993 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
6994 /* Network Partitioning 2.0 */
6995 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
6997 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
6999 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7000 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7002 * This field will indicate number of physical functions on this port_partition.
7003 * HWRM shall return unavail (i.e. value of 0) for this field
7004 * when this command is used to query VF's configuration or
7005 * from older firmware that doesn't support this field.
7007 uint8_t port_pf_cnt;
7008 /* number of PFs is not available */
7009 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7010 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7011 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7013 * The default VNIC ID assigned to a function that is
7016 uint16_t dflt_vnic_id;
7017 uint16_t max_mtu_configured;
7019 * Minimum BW allocated for this function.
7020 * The HWRM will translate this value into byte counter and
7021 * time interval used for the scheduler inside the device.
7022 * A value of 0 indicates the minimum bandwidth is not
7026 /* The bandwidth value. */
7027 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7029 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7030 /* The granularity of the value (bits or bytes). */
7031 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7032 UINT32_C(0x10000000)
7033 /* Value is in bits. */
7034 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7035 (UINT32_C(0x0) << 28)
7036 /* Value is in bytes. */
7037 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7038 (UINT32_C(0x1) << 28)
7039 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7040 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7041 /* bw_value_unit is 3 b */
7042 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7043 UINT32_C(0xe0000000)
7044 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7045 /* Value is in Mb or MB (base 10). */
7046 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7047 (UINT32_C(0x0) << 29)
7048 /* Value is in Kb or KB (base 10). */
7049 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7050 (UINT32_C(0x2) << 29)
7051 /* Value is in bits or bytes. */
7052 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7053 (UINT32_C(0x4) << 29)
7054 /* Value is in Gb or GB (base 10). */
7055 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7056 (UINT32_C(0x6) << 29)
7057 /* Value is in 1/100th of a percentage of total bandwidth. */
7058 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7059 (UINT32_C(0x1) << 29)
7061 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7062 (UINT32_C(0x7) << 29)
7063 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7064 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7066 * Maximum BW allocated for this function.
7067 * The HWRM will translate this value into byte counter and
7068 * time interval used for the scheduler inside the device.
7069 * A value of 0 indicates that the maximum bandwidth is not
7073 /* The bandwidth value. */
7074 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7076 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7077 /* The granularity of the value (bits or bytes). */
7078 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7079 UINT32_C(0x10000000)
7080 /* Value is in bits. */
7081 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7082 (UINT32_C(0x0) << 28)
7083 /* Value is in bytes. */
7084 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7085 (UINT32_C(0x1) << 28)
7086 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7087 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7088 /* bw_value_unit is 3 b */
7089 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7090 UINT32_C(0xe0000000)
7091 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7092 /* Value is in Mb or MB (base 10). */
7093 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7094 (UINT32_C(0x0) << 29)
7095 /* Value is in Kb or KB (base 10). */
7096 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7097 (UINT32_C(0x2) << 29)
7098 /* Value is in bits or bytes. */
7099 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7100 (UINT32_C(0x4) << 29)
7101 /* Value is in Gb or GB (base 10). */
7102 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7103 (UINT32_C(0x6) << 29)
7104 /* Value is in 1/100th of a percentage of total bandwidth. */
7105 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7106 (UINT32_C(0x1) << 29)
7108 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7109 (UINT32_C(0x7) << 29)
7110 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7111 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7113 * This value indicates the Edge virtual bridge mode for the
7114 * domain that this function belongs to.
7117 /* No Edge Virtual Bridging (EVB) */
7118 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7119 /* Virtual Ethernet Bridge (VEB) */
7120 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7121 /* Virtual Ethernet Port Aggregator (VEPA) */
7122 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7123 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7124 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7127 * This value indicates the PCIE device cache line size.
7128 * The cache line size allows the DMA writes to terminate and
7129 * start at the cache boundary.
7131 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7133 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7134 /* Cache Line Size 64 bytes */
7135 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7137 /* Cache Line Size 128 bytes */
7138 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7140 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7141 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7142 /* This value is the virtual link admin state setting. */
7143 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7145 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7146 /* Admin link state is in forced down mode. */
7147 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7148 (UINT32_C(0x0) << 2)
7149 /* Admin link state is in forced up mode. */
7150 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7151 (UINT32_C(0x1) << 2)
7152 /* Admin link state is in auto mode - follows the physical link state. */
7153 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7154 (UINT32_C(0x2) << 2)
7155 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7156 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7157 /* Reserved for future. */
7158 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7160 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7162 * The number of VFs that are allocated to the function.
7163 * This is valid only on the PF with SR-IOV enabled.
7164 * 0xFF... (All Fs) if this command is called on a PF with
7165 * SR-IOV disabled or on a VF.
7169 * The number of allocated multicast filters for this
7170 * function on the RX side.
7172 uint32_t alloc_mcast_filters;
7174 * The number of allocated HW ring groups for this
7177 uint32_t alloc_hw_ring_grps;
7179 * The number of strict priority transmit rings out of
7180 * currently allocated TX rings to the function
7183 uint16_t alloc_sp_tx_rings;
7185 * The number of statistics contexts
7186 * currently reserved for the function.
7188 uint16_t alloc_stat_ctx;
7190 * This field specifies how many NQs are reserved for the PF.
7191 * Remaining NQs that belong to the PF are available for VFs.
7192 * Once a PF has created VFs, it cannot change how many NQs are
7193 * reserved for itself (since the NQs must be contiguous in HW).
7195 uint16_t alloc_msix;
7197 * The number of registered VF’s associated with the PF. This field
7198 * should be ignored when the request received on the VF interface.
7199 * This field will be updated on the PF interface to initiate
7200 * the unregister request on PF in the HOT Reset Process.
7202 uint16_t registered_vfs;
7203 uint8_t unused_1[3];
7205 * For backward compatibility this field must be set to 1.
7206 * Older drivers might look for this field to be 1 before
7207 * processing the message.
7211 * This GRC address location is used by the Host driver interfaces to poll
7212 * the adapter ready state to re-initiate the registration process again
7213 * after receiving the RESET Notify event.
7215 uint32_t reset_addr_poll;
7216 uint8_t unused_2[3];
7218 * This field is used in Output records to indicate that the output
7219 * is completely written to RAM. This field should be read as '1'
7220 * to indicate that the output has been completely written.
7221 * When writing a command completion or response to an internal processor,
7222 * the order of writes has to be such that this field is written last.
7225 } __attribute__((packed));
7232 /* hwrm_func_cfg_input (size:704b/88B) */
7233 struct hwrm_func_cfg_input {
7234 /* The HWRM command request type. */
7237 * The completion ring to send the completion event on. This should
7238 * be the NQ ID returned from the `nq_alloc` HWRM command.
7242 * The sequence ID is used by the driver for tracking multiple
7243 * commands. This ID is treated as opaque data by the firmware and
7244 * the value is returned in the `hwrm_resp_hdr` upon completion.
7248 * The target ID of the command:
7249 * * 0x0-0xFFF8 - The function ID
7250 * * 0xFFF8-0xFFFE - Reserved for internal processors
7255 * A physical address pointer pointing to a host buffer that the
7256 * command's response data will be written. This can be either a host
7257 * physical address (HPA) or a guest physical address (GPA) and must
7258 * point to a physically contiguous block of memory.
7262 * Function ID of the function that is being
7264 * If set to 0xFF... (All Fs), then the the configuration is
7265 * for the requesting function.
7269 * This field specifies how many NQs will be reserved for the PF.
7270 * Remaining NQs that belong to the PF become available for VFs.
7271 * Once a PF has created VFs, it cannot change how many NQs are
7272 * reserved for itself (since the NQs must be contiguous in HW).
7277 * When this bit is '1', the function is disabled with
7278 * source MAC address check.
7279 * This is an anti-spoofing check. If this flag is set,
7280 * then the function shall be configured to disallow
7281 * transmission of frames with the source MAC address that
7282 * is configured for this function.
7284 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
7287 * When this bit is '1', the function is enabled with
7288 * source MAC address check.
7289 * This is an anti-spoofing check. If this flag is set,
7290 * then the function shall be configured to allow
7291 * transmission of frames with the source MAC address that
7292 * is configured for this function.
7294 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
7297 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
7299 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7301 * Standard TX Ring mode is used for the allocation of TX ring
7302 * and underlying scheduling resources that allow bandwidth
7303 * reservation and limit settings on the queried function.
7304 * If set to 1, then standard TX ring mode is requested to be
7305 * enabled on the function being configured.
7307 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
7310 * Standard TX Ring mode is used for the allocation of TX ring
7311 * and underlying scheduling resources that allow bandwidth
7312 * reservation and limit settings on the queried function.
7313 * If set to 1, then the standard TX ring mode is requested to
7314 * be disabled on the function being configured. In this extended
7315 * TX ring resource mode, the minimum and maximum bandwidth settings
7316 * are not supported to allow the allocation of TX rings to
7317 * span multiple scheduler nodes.
7319 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
7322 * If this bit is set, virtual mac address configured
7323 * in this command will be persistent over warm boot.
7325 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
7328 * This bit only applies to the VF. If this bit is set, the statistic
7329 * context counters will not be cleared when the statistic context is freed
7330 * or a function reset is called on VF. This bit will be cleared when the PF
7331 * is unloaded or a function reset is called on the PF.
7333 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
7336 * This bit requests that the firmware test to see if all the assets
7337 * requested in this command (i.e. number of TX rings) are available.
7338 * The firmware will return an error if the requested assets are
7339 * not available. The firwmare will NOT reserve the assets if they
7342 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
7345 * This bit requests that the firmware test to see if all the assets
7346 * requested in this command (i.e. number of RX rings) are available.
7347 * The firmware will return an error if the requested assets are
7348 * not available. The firwmare will NOT reserve the assets if they
7351 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
7354 * This bit requests that the firmware test to see if all the assets
7355 * requested in this command (i.e. number of CMPL rings) are available.
7356 * The firmware will return an error if the requested assets are
7357 * not available. The firwmare will NOT reserve the assets if they
7360 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
7363 * This bit requests that the firmware test to see if all the assets
7364 * requested in this command (i.e. number of RSS ctx) are available.
7365 * The firmware will return an error if the requested assets are
7366 * not available. The firwmare will NOT reserve the assets if they
7369 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7372 * This bit requests that the firmware test to see if all the assets
7373 * requested in this command (i.e. number of ring groups) are available.
7374 * The firmware will return an error if the requested assets are
7375 * not available. The firwmare will NOT reserve the assets if they
7378 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7381 * This bit requests that the firmware test to see if all the assets
7382 * requested in this command (i.e. number of stat ctx) are available.
7383 * The firmware will return an error if the requested assets are
7384 * not available. The firwmare will NOT reserve the assets if they
7387 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7390 * This bit requests that the firmware test to see if all the assets
7391 * requested in this command (i.e. number of VNICs) are available.
7392 * The firmware will return an error if the requested assets are
7393 * not available. The firwmare will NOT reserve the assets if they
7396 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7399 * This bit requests that the firmware test to see if all the assets
7400 * requested in this command (i.e. number of L2 ctx) are available.
7401 * The firmware will return an error if the requested assets are
7402 * not available. The firwmare will NOT reserve the assets if they
7405 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7408 * This configuration change can be initiated by a PF driver. This
7409 * configuration request shall be targeted to a VF. From local host
7410 * resident HWRM clients, only the parent PF driver shall be allowed
7411 * to initiate this change on one of its children VFs. If this bit is
7412 * set to 1, then the VF that is being configured is requested to be
7415 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
7418 * When this bit it set, even if PF reserved pool size is zero,
7419 * FW will allow driver to create TX rings in ring alloc,
7420 * by reserving TX ring, S3 node dynamically.
7422 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7425 * This bit requests that the firmware test to see if all the assets
7426 * requested in this command (i.e. number of NQ rings) are available.
7427 * The firmware will return an error if the requested assets are
7428 * not available. The firwmare will NOT reserve the assets if they
7431 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
7434 * This configuration change can be initiated by a PF driver. This
7435 * configuration request shall be targeted to a VF. From local host
7436 * resident HWRM clients, only the parent PF driver shall be allowed
7437 * to initiate this change on one of its children VFs. If this bit is
7438 * set to 1, then the VF that is being configured is requested to be
7441 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
7445 * This bit must be '1' for the mtu field to be
7448 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
7451 * This bit must be '1' for the mru field to be
7454 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
7457 * This bit must be '1' for the num_rsscos_ctxs field to be
7460 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
7463 * This bit must be '1' for the num_cmpl_rings field to be
7466 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
7469 * This bit must be '1' for the num_tx_rings field to be
7472 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
7475 * This bit must be '1' for the num_rx_rings field to be
7478 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
7481 * This bit must be '1' for the num_l2_ctxs field to be
7484 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
7487 * This bit must be '1' for the num_vnics field to be
7490 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
7493 * This bit must be '1' for the num_stat_ctxs field to be
7496 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
7499 * This bit must be '1' for the dflt_mac_addr field to be
7502 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
7505 * This bit must be '1' for the dflt_vlan field to be
7508 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
7511 * This bit must be '1' for the dflt_ip_addr field to be
7514 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
7517 * This bit must be '1' for the min_bw field to be
7520 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
7523 * This bit must be '1' for the max_bw field to be
7526 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
7529 * This bit must be '1' for the async_event_cr field to be
7532 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
7535 * This bit must be '1' for the vlan_antispoof_mode field to be
7538 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
7541 * This bit must be '1' for the allowed_vlan_pris field to be
7544 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
7547 * This bit must be '1' for the evb_mode field to be
7550 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
7553 * This bit must be '1' for the num_mcast_filters field to be
7556 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
7559 * This bit must be '1' for the num_hw_ring_grps field to be
7562 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
7565 * This bit must be '1' for the cache_linesize field to be
7568 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
7571 * This bit must be '1' for the num_msix field to be
7574 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
7577 * This bit must be '1' for the link admin state field to be
7580 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
7583 * The maximum transmission unit of the function.
7584 * The HWRM should make sure that the mtu of
7585 * the function does not exceed the mtu of the physical
7586 * port that this function is associated with.
7588 * In addition to configuring mtu per function, it is
7589 * possible to configure mtu per transmit ring.
7590 * By default, the mtu of each transmit ring associated
7591 * with a function is equal to the mtu of the function.
7592 * The HWRM should make sure that the mtu of each transmit
7593 * ring that is assigned to a function has a valid mtu.
7597 * The maximum receive unit of the function.
7598 * The HWRM should make sure that the mru of
7599 * the function does not exceed the mru of the physical
7600 * port that this function is associated with.
7602 * In addition to configuring mru per function, it is
7603 * possible to configure mru per vnic.
7604 * By default, the mru of each vnic associated
7605 * with a function is equal to the mru of the function.
7606 * The HWRM should make sure that the mru of each vnic
7607 * that is assigned to a function has a valid mru.
7611 * The number of RSS/COS contexts requested for the
7614 uint16_t num_rsscos_ctxs;
7616 * The number of completion rings requested for the
7617 * function. This does not include the rings allocated
7618 * to any children functions if any.
7620 uint16_t num_cmpl_rings;
7622 * The number of transmit rings requested for the function.
7623 * This does not include the rings allocated to any
7624 * children functions if any.
7626 uint16_t num_tx_rings;
7628 * The number of receive rings requested for the function.
7629 * This does not include the rings allocated
7630 * to any children functions if any.
7632 uint16_t num_rx_rings;
7633 /* The requested number of L2 contexts for the function. */
7634 uint16_t num_l2_ctxs;
7635 /* The requested number of vnics for the function. */
7637 /* The requested number of statistic contexts for the function. */
7638 uint16_t num_stat_ctxs;
7640 * The number of HW ring groups that should
7641 * be reserved for this function.
7643 uint16_t num_hw_ring_grps;
7644 /* The default MAC address for the function being configured. */
7645 uint8_t dflt_mac_addr[6];
7647 * The default VLAN for the function being configured.
7648 * This field's format is same as 802.1Q Tag's
7649 * Tag Control Information (TCI) format that includes both
7650 * Priority Code Point (PCP) and VLAN Identifier (VID).
7654 * The default IP address for the function being configured.
7655 * This address is only used in enabling source property check.
7657 uint32_t dflt_ip_addr[4];
7659 * Minimum BW allocated for this function.
7660 * The HWRM will translate this value into byte counter and
7661 * time interval used for the scheduler inside the device.
7664 /* The bandwidth value. */
7665 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
7667 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
7668 /* The granularity of the value (bits or bytes). */
7669 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
7670 UINT32_C(0x10000000)
7671 /* Value is in bits. */
7672 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
7673 (UINT32_C(0x0) << 28)
7674 /* Value is in bytes. */
7675 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
7676 (UINT32_C(0x1) << 28)
7677 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
7678 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
7679 /* bw_value_unit is 3 b */
7680 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7681 UINT32_C(0xe0000000)
7682 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7683 /* Value is in Mb or MB (base 10). */
7684 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7685 (UINT32_C(0x0) << 29)
7686 /* Value is in Kb or KB (base 10). */
7687 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7688 (UINT32_C(0x2) << 29)
7689 /* Value is in bits or bytes. */
7690 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7691 (UINT32_C(0x4) << 29)
7692 /* Value is in Gb or GB (base 10). */
7693 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7694 (UINT32_C(0x6) << 29)
7695 /* Value is in 1/100th of a percentage of total bandwidth. */
7696 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7697 (UINT32_C(0x1) << 29)
7699 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7700 (UINT32_C(0x7) << 29)
7701 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7702 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7704 * Maximum BW allocated for this function.
7705 * The HWRM will translate this value into byte counter and
7706 * time interval used for the scheduler inside the device.
7709 /* The bandwidth value. */
7710 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
7712 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
7713 /* The granularity of the value (bits or bytes). */
7714 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
7715 UINT32_C(0x10000000)
7716 /* Value is in bits. */
7717 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
7718 (UINT32_C(0x0) << 28)
7719 /* Value is in bytes. */
7720 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
7721 (UINT32_C(0x1) << 28)
7722 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
7723 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
7724 /* bw_value_unit is 3 b */
7725 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7726 UINT32_C(0xe0000000)
7727 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7728 /* Value is in Mb or MB (base 10). */
7729 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7730 (UINT32_C(0x0) << 29)
7731 /* Value is in Kb or KB (base 10). */
7732 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7733 (UINT32_C(0x2) << 29)
7734 /* Value is in bits or bytes. */
7735 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7736 (UINT32_C(0x4) << 29)
7737 /* Value is in Gb or GB (base 10). */
7738 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7739 (UINT32_C(0x6) << 29)
7740 /* Value is in 1/100th of a percentage of total bandwidth. */
7741 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7742 (UINT32_C(0x1) << 29)
7744 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7745 (UINT32_C(0x7) << 29)
7746 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7747 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7749 * ID of the target completion ring for receiving asynchronous
7750 * event completions. If this field is not valid, then the
7751 * HWRM shall use the default completion ring of the function
7752 * that is being configured as the target completion ring for
7753 * providing any asynchronous event completions for that
7755 * If this field is valid, then the HWRM shall use the
7756 * completion ring identified by this ID as the target
7757 * completion ring for providing any asynchronous event
7758 * completions for the function that is being configured.
7760 uint16_t async_event_cr;
7761 /* VLAN Anti-spoofing mode. */
7762 uint8_t vlan_antispoof_mode;
7763 /* No VLAN anti-spoofing checks are enabled */
7764 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
7766 /* Validate VLAN against the configured VLAN(s) */
7767 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
7769 /* Insert VLAN if it does not exist, otherwise discard */
7770 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
7772 /* Insert VLAN if it does not exist, override VLAN if it exists */
7773 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
7775 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
7776 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
7778 * This bit field defines VLAN PRIs that are allowed on
7780 * If nth bit is set, then VLAN PRI n is allowed on this
7783 uint8_t allowed_vlan_pris;
7785 * The HWRM shall allow a PF driver to change EVB mode for the
7786 * partition it belongs to.
7787 * The HWRM shall not allow a VF driver to change the EVB mode.
7788 * The HWRM shall take into account the switching of EVB mode
7789 * from one to another and reconfigure hardware resources as
7791 * The switching from VEB to VEPA mode requires
7792 * the disabling of the loopback traffic. Additionally,
7793 * source knock outs are handled differently in VEB and VEPA
7797 /* No Edge Virtual Bridging (EVB) */
7798 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7799 /* Virtual Ethernet Bridge (VEB) */
7800 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
7801 /* Virtual Ethernet Port Aggregator (VEPA) */
7802 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
7803 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
7804 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
7807 * This value indicates the PCIE device cache line size.
7808 * The cache line size allows the DMA writes to terminate and
7809 * start at the cache boundary.
7811 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
7813 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7814 /* Cache Line Size 64 bytes */
7815 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7817 /* Cache Line Size 128 bytes */
7818 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7820 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
7821 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7822 /* This value is the virtual link admin state setting. */
7823 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7825 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7826 /* Admin state is forced down. */
7827 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7828 (UINT32_C(0x0) << 2)
7829 /* Admin state is forced up. */
7830 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7831 (UINT32_C(0x1) << 2)
7832 /* Admin state is in auto mode - is to follow the physical link state. */
7833 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7834 (UINT32_C(0x2) << 2)
7835 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7836 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7837 /* Reserved for future. */
7838 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
7840 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
7842 * The number of multicast filters that should
7843 * be reserved for this function on the RX side.
7845 uint16_t num_mcast_filters;
7846 } __attribute__((packed));
7848 /* hwrm_func_cfg_output (size:128b/16B) */
7849 struct hwrm_func_cfg_output {
7850 /* The specific error status for the command. */
7851 uint16_t error_code;
7852 /* The HWRM command request type. */
7854 /* The sequence ID from the original command. */
7856 /* The length of the response data in number of bytes. */
7858 uint8_t unused_0[7];
7860 * This field is used in Output records to indicate that the output
7861 * is completely written to RAM. This field should be read as '1'
7862 * to indicate that the output has been completely written.
7863 * When writing a command completion or response to an internal processor,
7864 * the order of writes has to be such that this field is written last.
7867 } __attribute__((packed));
7869 /********************
7870 * hwrm_func_qstats *
7871 ********************/
7874 /* hwrm_func_qstats_input (size:192b/24B) */
7875 struct hwrm_func_qstats_input {
7876 /* The HWRM command request type. */
7879 * The completion ring to send the completion event on. This should
7880 * be the NQ ID returned from the `nq_alloc` HWRM command.
7884 * The sequence ID is used by the driver for tracking multiple
7885 * commands. This ID is treated as opaque data by the firmware and
7886 * the value is returned in the `hwrm_resp_hdr` upon completion.
7890 * The target ID of the command:
7891 * * 0x0-0xFFF8 - The function ID
7892 * * 0xFFF8-0xFFFE - Reserved for internal processors
7897 * A physical address pointer pointing to a host buffer that the
7898 * command's response data will be written. This can be either a host
7899 * physical address (HPA) or a guest physical address (GPA) and must
7900 * point to a physically contiguous block of memory.
7904 * Function ID of the function that is being queried.
7905 * 0xFF... (All Fs) if the query is for the requesting
7909 uint8_t unused_0[6];
7910 } __attribute__((packed));
7912 /* hwrm_func_qstats_output (size:1408b/176B) */
7913 struct hwrm_func_qstats_output {
7914 /* The specific error status for the command. */
7915 uint16_t error_code;
7916 /* The HWRM command request type. */
7918 /* The sequence ID from the original command. */
7920 /* The length of the response data in number of bytes. */
7922 /* Number of transmitted unicast packets on the function. */
7923 uint64_t tx_ucast_pkts;
7924 /* Number of transmitted multicast packets on the function. */
7925 uint64_t tx_mcast_pkts;
7926 /* Number of transmitted broadcast packets on the function. */
7927 uint64_t tx_bcast_pkts;
7929 * Number of transmitted packets that were discarded due to
7930 * internal NIC resource problems. For transmit, this
7931 * can only happen if TMP is configured to allow dropping
7932 * in HOL blocking conditions, which is not a normal
7935 uint64_t tx_discard_pkts;
7937 * Number of dropped packets on transmit path on the function.
7938 * These are packets that have been marked for drop by
7939 * the TE CFA block or are packets that exceeded the
7940 * transmit MTU limit for the function.
7942 uint64_t tx_drop_pkts;
7943 /* Number of transmitted bytes for unicast traffic on the function. */
7944 uint64_t tx_ucast_bytes;
7945 /* Number of transmitted bytes for multicast traffic on the function. */
7946 uint64_t tx_mcast_bytes;
7947 /* Number of transmitted bytes for broadcast traffic on the function. */
7948 uint64_t tx_bcast_bytes;
7949 /* Number of received unicast packets on the function. */
7950 uint64_t rx_ucast_pkts;
7951 /* Number of received multicast packets on the function. */
7952 uint64_t rx_mcast_pkts;
7953 /* Number of received broadcast packets on the function. */
7954 uint64_t rx_bcast_pkts;
7956 * Number of received packets that were discarded on the function
7957 * due to resource limitations. This can happen for 3 reasons.
7958 * # The BD used for the packet has a bad format.
7959 * # There were no BDs available in the ring for the packet.
7960 * # There were no BDs available on-chip for the packet.
7962 uint64_t rx_discard_pkts;
7964 * Number of dropped packets on received path on the function.
7965 * These are packets that have been marked for drop by the
7968 uint64_t rx_drop_pkts;
7969 /* Number of received bytes for unicast traffic on the function. */
7970 uint64_t rx_ucast_bytes;
7971 /* Number of received bytes for multicast traffic on the function. */
7972 uint64_t rx_mcast_bytes;
7973 /* Number of received bytes for broadcast traffic on the function. */
7974 uint64_t rx_bcast_bytes;
7975 /* Number of aggregated unicast packets on the function. */
7976 uint64_t rx_agg_pkts;
7977 /* Number of aggregated unicast bytes on the function. */
7978 uint64_t rx_agg_bytes;
7979 /* Number of aggregation events on the function. */
7980 uint64_t rx_agg_events;
7981 /* Number of aborted aggregations on the function. */
7982 uint64_t rx_agg_aborts;
7983 uint8_t unused_0[7];
7985 * This field is used in Output records to indicate that the output
7986 * is completely written to RAM. This field should be read as '1'
7987 * to indicate that the output has been completely written.
7988 * When writing a command completion or response to an internal processor,
7989 * the order of writes has to be such that this field is written last.
7992 } __attribute__((packed));
7994 /***********************
7995 * hwrm_func_clr_stats *
7996 ***********************/
7999 /* hwrm_func_clr_stats_input (size:192b/24B) */
8000 struct hwrm_func_clr_stats_input {
8001 /* The HWRM command request type. */
8004 * The completion ring to send the completion event on. This should
8005 * be the NQ ID returned from the `nq_alloc` HWRM command.
8009 * The sequence ID is used by the driver for tracking multiple
8010 * commands. This ID is treated as opaque data by the firmware and
8011 * the value is returned in the `hwrm_resp_hdr` upon completion.
8015 * The target ID of the command:
8016 * * 0x0-0xFFF8 - The function ID
8017 * * 0xFFF8-0xFFFE - Reserved for internal processors
8022 * A physical address pointer pointing to a host buffer that the
8023 * command's response data will be written. This can be either a host
8024 * physical address (HPA) or a guest physical address (GPA) and must
8025 * point to a physically contiguous block of memory.
8029 * Function ID of the function.
8030 * 0xFF... (All Fs) if the query is for the requesting
8034 uint8_t unused_0[6];
8035 } __attribute__((packed));
8037 /* hwrm_func_clr_stats_output (size:128b/16B) */
8038 struct hwrm_func_clr_stats_output {
8039 /* The specific error status for the command. */
8040 uint16_t error_code;
8041 /* The HWRM command request type. */
8043 /* The sequence ID from the original command. */
8045 /* The length of the response data in number of bytes. */
8047 uint8_t unused_0[7];
8049 * This field is used in Output records to indicate that the output
8050 * is completely written to RAM. This field should be read as '1'
8051 * to indicate that the output has been completely written.
8052 * When writing a command completion or response to an internal processor,
8053 * the order of writes has to be such that this field is written last.
8056 } __attribute__((packed));
8058 /**************************
8059 * hwrm_func_vf_resc_free *
8060 **************************/
8063 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8064 struct hwrm_func_vf_resc_free_input {
8065 /* The HWRM command request type. */
8068 * The completion ring to send the completion event on. This should
8069 * be the NQ ID returned from the `nq_alloc` HWRM command.
8073 * The sequence ID is used by the driver for tracking multiple
8074 * commands. This ID is treated as opaque data by the firmware and
8075 * the value is returned in the `hwrm_resp_hdr` upon completion.
8079 * The target ID of the command:
8080 * * 0x0-0xFFF8 - The function ID
8081 * * 0xFFF8-0xFFFE - Reserved for internal processors
8086 * A physical address pointer pointing to a host buffer that the
8087 * command's response data will be written. This can be either a host
8088 * physical address (HPA) or a guest physical address (GPA) and must
8089 * point to a physically contiguous block of memory.
8093 * This value is used to identify a Virtual Function (VF).
8094 * The scope of VF ID is local within a PF.
8097 uint8_t unused_0[6];
8098 } __attribute__((packed));
8100 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8101 struct hwrm_func_vf_resc_free_output {
8102 /* The specific error status for the command. */
8103 uint16_t error_code;
8104 /* The HWRM command request type. */
8106 /* The sequence ID from the original command. */
8108 /* The length of the response data in number of bytes. */
8110 uint8_t unused_0[7];
8112 * This field is used in Output records to indicate that the output
8113 * is completely written to RAM. This field should be read as '1'
8114 * to indicate that the output has been completely written.
8115 * When writing a command completion or response to an internal processor,
8116 * the order of writes has to be such that this field is written last.
8119 } __attribute__((packed));
8121 /**********************
8122 * hwrm_func_drv_rgtr *
8123 **********************/
8126 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8127 struct hwrm_func_drv_rgtr_input {
8128 /* The HWRM command request type. */
8131 * The completion ring to send the completion event on. This should
8132 * be the NQ ID returned from the `nq_alloc` HWRM command.
8136 * The sequence ID is used by the driver for tracking multiple
8137 * commands. This ID is treated as opaque data by the firmware and
8138 * the value is returned in the `hwrm_resp_hdr` upon completion.
8142 * The target ID of the command:
8143 * * 0x0-0xFFF8 - The function ID
8144 * * 0xFFF8-0xFFFE - Reserved for internal processors
8149 * A physical address pointer pointing to a host buffer that the
8150 * command's response data will be written. This can be either a host
8151 * physical address (HPA) or a guest physical address (GPA) and must
8152 * point to a physically contiguous block of memory.
8157 * When this bit is '1', the function driver is requesting
8158 * all requests from its children VF drivers to be
8159 * forwarded to itself.
8160 * This flag can only be set by the PF driver.
8161 * If a VF driver sets this flag, it should be ignored
8164 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8167 * When this bit is '1', the function is requesting none of
8168 * the requests from its children VF drivers to be
8169 * forwarded to itself.
8170 * This flag can only be set by the PF driver.
8171 * If a VF driver sets this flag, it should be ignored
8174 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
8177 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
8178 * fields shall be ignored and ver_maj, ver_min, ver_upd
8179 * and ver_patch shall be used for the driver version information.
8180 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
8181 * fields shall be used for the driver version information and
8182 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
8184 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
8187 * When this bit is '1', the function is indicating support of
8188 * 64bit flow handle. The firmware that only supports 64bit flow
8189 * handle should check this bit before allowing processing of
8190 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
8191 * with 64bit flow handle support can only be compatible with drivers
8192 * that support 64bit flow handle. The legacy drivers that don't support
8193 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
8194 * running with new firmware that only supports 64bit flow handle. The new
8195 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
8196 * status to the legacy driver when encounters these commands.
8198 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
8201 * When this bit is '1', the function is indicating support of
8202 * Hot Reset. The driver interface will destroy the resources,
8203 * unregister the function and register again up on receiving
8204 * the RESET_NOTIFY Async notification from the core firmware.
8205 * The core firmware will this use flag and trigger the Hot Reset
8206 * process only if all the registered driver instances are capable
8209 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
8212 * When this bit is 1, the function is indicating the support of the
8213 * error recovery capability. Error recovery support will be used by
8214 * firmware only if all the driver instances support error recovery
8215 * process. By setting this bit, driver is indicating support for
8216 * corresponding async event completion message. These will be
8217 * delivered to the driver even if they did not register for it.
8218 * If supported, after receiving reset notify async event with fatal
8219 * flag set in event data1, then all the drivers have to tear down
8220 * their resources without sending any HWRM commands to FW.
8222 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
8226 * This bit must be '1' for the os_type field to be
8229 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
8232 * This bit must be '1' for the ver field to be
8235 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
8238 * This bit must be '1' for the timestamp field to be
8241 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
8244 * This bit must be '1' for the vf_req_fwd field to be
8247 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
8250 * This bit must be '1' for the async_event_fwd field to be
8253 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
8255 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8258 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8259 /* Other OS not listed below. */
8260 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
8262 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8264 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8266 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8268 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
8270 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8271 /* VMware ESXi OS. */
8272 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
8273 /* Microsoft Windows 8 64-bit OS. */
8274 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8275 /* Microsoft Windows Server 2012 R2 OS. */
8276 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8278 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8279 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
8280 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
8281 /* This is the 8bit major version of the driver. */
8283 /* This is the 8bit minor version of the driver. */
8285 /* This is the 8bit update version of the driver. */
8287 uint8_t unused_0[3];
8289 * This is a 32-bit timestamp provided by the driver for
8291 * The timestamp is in multiples of 1ms.
8294 uint8_t unused_1[4];
8296 * This is a 256-bit bit mask provided by the PF driver for
8297 * letting the HWRM know what commands issued by the VF driver
8298 * to the HWRM should be forwarded to the PF driver.
8299 * Nth bit refers to the Nth req_type.
8301 * Setting Nth bit to 1 indicates that requests from the
8302 * VF driver with req_type equal to N shall be forwarded to
8303 * the parent PF driver.
8305 * This field is not valid for the VF driver.
8307 uint32_t vf_req_fwd[8];
8309 * This is a 256-bit bit mask provided by the function driver
8310 * (PF or VF driver) to indicate the list of asynchronous event
8311 * completions to be forwarded.
8313 * Nth bit refers to the Nth event_id.
8315 * Setting Nth bit to 1 by the function driver shall result in
8316 * the HWRM forwarding asynchronous event completion with
8317 * event_id equal to N.
8319 * If all bits are set to 0 (value of 0), then the HWRM shall
8320 * not forward any asynchronous event completion to this
8323 uint32_t async_event_fwd[8];
8324 /* This is the 16bit major version of the driver. */
8326 /* This is the 16bit minor version of the driver. */
8328 /* This is the 16bit update version of the driver. */
8330 /* This is the 16bit patch version of the driver. */
8332 } __attribute__((packed));
8334 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
8335 struct hwrm_func_drv_rgtr_output {
8336 /* The specific error status for the command. */
8337 uint16_t error_code;
8338 /* The HWRM command request type. */
8340 /* The sequence ID from the original command. */
8342 /* The length of the response data in number of bytes. */
8346 * When this bit is '1', it indicates that the
8347 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
8349 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
8351 uint8_t unused_0[3];
8353 * This field is used in Output records to indicate that the output
8354 * is completely written to RAM. This field should be read as '1'
8355 * to indicate that the output has been completely written.
8356 * When writing a command completion or response to an internal processor,
8357 * the order of writes has to be such that this field is written last.
8360 } __attribute__((packed));
8362 /************************
8363 * hwrm_func_drv_unrgtr *
8364 ************************/
8367 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
8368 struct hwrm_func_drv_unrgtr_input {
8369 /* The HWRM command request type. */
8372 * The completion ring to send the completion event on. This should
8373 * be the NQ ID returned from the `nq_alloc` HWRM command.
8377 * The sequence ID is used by the driver for tracking multiple
8378 * commands. This ID is treated as opaque data by the firmware and
8379 * the value is returned in the `hwrm_resp_hdr` upon completion.
8383 * The target ID of the command:
8384 * * 0x0-0xFFF8 - The function ID
8385 * * 0xFFF8-0xFFFE - Reserved for internal processors
8390 * A physical address pointer pointing to a host buffer that the
8391 * command's response data will be written. This can be either a host
8392 * physical address (HPA) or a guest physical address (GPA) and must
8393 * point to a physically contiguous block of memory.
8398 * When this bit is '1', the function driver is notifying
8399 * the HWRM to prepare for the shutdown.
8401 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
8403 uint8_t unused_0[4];
8404 } __attribute__((packed));
8406 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
8407 struct hwrm_func_drv_unrgtr_output {
8408 /* The specific error status for the command. */
8409 uint16_t error_code;
8410 /* The HWRM command request type. */
8412 /* The sequence ID from the original command. */
8414 /* The length of the response data in number of bytes. */
8416 uint8_t unused_0[7];
8418 * This field is used in Output records to indicate that the output
8419 * is completely written to RAM. This field should be read as '1'
8420 * to indicate that the output has been completely written.
8421 * When writing a command completion or response to an internal processor,
8422 * the order of writes has to be such that this field is written last.
8425 } __attribute__((packed));
8427 /**********************
8428 * hwrm_func_buf_rgtr *
8429 **********************/
8432 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
8433 struct hwrm_func_buf_rgtr_input {
8434 /* The HWRM command request type. */
8437 * The completion ring to send the completion event on. This should
8438 * be the NQ ID returned from the `nq_alloc` HWRM command.
8442 * The sequence ID is used by the driver for tracking multiple
8443 * commands. This ID is treated as opaque data by the firmware and
8444 * the value is returned in the `hwrm_resp_hdr` upon completion.
8448 * The target ID of the command:
8449 * * 0x0-0xFFF8 - The function ID
8450 * * 0xFFF8-0xFFFE - Reserved for internal processors
8455 * A physical address pointer pointing to a host buffer that the
8456 * command's response data will be written. This can be either a host
8457 * physical address (HPA) or a guest physical address (GPA) and must
8458 * point to a physically contiguous block of memory.
8463 * This bit must be '1' for the vf_id field to be
8466 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8468 * This bit must be '1' for the err_buf_addr field to be
8471 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
8473 * This value is used to identify a Virtual Function (VF).
8474 * The scope of VF ID is local within a PF.
8478 * This field represents the number of pages used for request
8481 uint16_t req_buf_num_pages;
8483 * This field represents the page size used for request
8486 uint16_t req_buf_page_size;
8488 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
8490 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
8492 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
8494 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
8496 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
8498 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
8500 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
8501 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
8502 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
8503 /* The length of the request buffer per VF in bytes. */
8504 uint16_t req_buf_len;
8505 /* The length of the response buffer in bytes. */
8506 uint16_t resp_buf_len;
8507 uint8_t unused_0[2];
8508 /* This field represents the page address of page #0. */
8509 uint64_t req_buf_page_addr0;
8510 /* This field represents the page address of page #1. */
8511 uint64_t req_buf_page_addr1;
8512 /* This field represents the page address of page #2. */
8513 uint64_t req_buf_page_addr2;
8514 /* This field represents the page address of page #3. */
8515 uint64_t req_buf_page_addr3;
8516 /* This field represents the page address of page #4. */
8517 uint64_t req_buf_page_addr4;
8518 /* This field represents the page address of page #5. */
8519 uint64_t req_buf_page_addr5;
8520 /* This field represents the page address of page #6. */
8521 uint64_t req_buf_page_addr6;
8522 /* This field represents the page address of page #7. */
8523 uint64_t req_buf_page_addr7;
8524 /* This field represents the page address of page #8. */
8525 uint64_t req_buf_page_addr8;
8526 /* This field represents the page address of page #9. */
8527 uint64_t req_buf_page_addr9;
8529 * This field is used to receive the error reporting from
8530 * the chipset. Only applicable for PFs.
8532 uint64_t error_buf_addr;
8534 * This field is used to receive the response forwarded by the
8537 uint64_t resp_buf_addr;
8538 } __attribute__((packed));
8540 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
8541 struct hwrm_func_buf_rgtr_output {
8542 /* The specific error status for the command. */
8543 uint16_t error_code;
8544 /* The HWRM command request type. */
8546 /* The sequence ID from the original command. */
8548 /* The length of the response data in number of bytes. */
8550 uint8_t unused_0[7];
8552 * This field is used in Output records to indicate that the output
8553 * is completely written to RAM. This field should be read as '1'
8554 * to indicate that the output has been completely written.
8555 * When writing a command completion or response to an internal processor,
8556 * the order of writes has to be such that this field is written last.
8559 } __attribute__((packed));
8561 /************************
8562 * hwrm_func_buf_unrgtr *
8563 ************************/
8566 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
8567 struct hwrm_func_buf_unrgtr_input {
8568 /* The HWRM command request type. */
8571 * The completion ring to send the completion event on. This should
8572 * be the NQ ID returned from the `nq_alloc` HWRM command.
8576 * The sequence ID is used by the driver for tracking multiple
8577 * commands. This ID is treated as opaque data by the firmware and
8578 * the value is returned in the `hwrm_resp_hdr` upon completion.
8582 * The target ID of the command:
8583 * * 0x0-0xFFF8 - The function ID
8584 * * 0xFFF8-0xFFFE - Reserved for internal processors
8589 * A physical address pointer pointing to a host buffer that the
8590 * command's response data will be written. This can be either a host
8591 * physical address (HPA) or a guest physical address (GPA) and must
8592 * point to a physically contiguous block of memory.
8597 * This bit must be '1' for the vf_id field to be
8600 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8602 * This value is used to identify a Virtual Function (VF).
8603 * The scope of VF ID is local within a PF.
8606 uint8_t unused_0[2];
8607 } __attribute__((packed));
8609 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
8610 struct hwrm_func_buf_unrgtr_output {
8611 /* The specific error status for the command. */
8612 uint16_t error_code;
8613 /* The HWRM command request type. */
8615 /* The sequence ID from the original command. */
8617 /* The length of the response data in number of bytes. */
8619 uint8_t unused_0[7];
8621 * This field is used in Output records to indicate that the output
8622 * is completely written to RAM. This field should be read as '1'
8623 * to indicate that the output has been completely written.
8624 * When writing a command completion or response to an internal processor,
8625 * the order of writes has to be such that this field is written last.
8628 } __attribute__((packed));
8630 /**********************
8631 * hwrm_func_drv_qver *
8632 **********************/
8635 /* hwrm_func_drv_qver_input (size:192b/24B) */
8636 struct hwrm_func_drv_qver_input {
8637 /* The HWRM command request type. */
8640 * The completion ring to send the completion event on. This should
8641 * be the NQ ID returned from the `nq_alloc` HWRM command.
8645 * The sequence ID is used by the driver for tracking multiple
8646 * commands. This ID is treated as opaque data by the firmware and
8647 * the value is returned in the `hwrm_resp_hdr` upon completion.
8651 * The target ID of the command:
8652 * * 0x0-0xFFF8 - The function ID
8653 * * 0xFFF8-0xFFFE - Reserved for internal processors
8658 * A physical address pointer pointing to a host buffer that the
8659 * command's response data will be written. This can be either a host
8660 * physical address (HPA) or a guest physical address (GPA) and must
8661 * point to a physically contiguous block of memory.
8664 /* Reserved for future use. */
8667 * Function ID of the function that is being queried.
8668 * 0xFF... (All Fs) if the query is for the requesting
8672 uint8_t unused_0[2];
8673 } __attribute__((packed));
8675 /* hwrm_func_drv_qver_output (size:256b/32B) */
8676 struct hwrm_func_drv_qver_output {
8677 /* The specific error status for the command. */
8678 uint16_t error_code;
8679 /* The HWRM command request type. */
8681 /* The sequence ID from the original command. */
8683 /* The length of the response data in number of bytes. */
8685 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
8688 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8689 /* Other OS not listed below. */
8690 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
8692 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8694 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8696 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8698 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
8700 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8701 /* VMware ESXi OS. */
8702 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
8703 /* Microsoft Windows 8 64-bit OS. */
8704 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8705 /* Microsoft Windows Server 2012 R2 OS. */
8706 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8708 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
8709 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
8710 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
8711 /* This is the 8bit major version of the driver. */
8713 /* This is the 8bit minor version of the driver. */
8715 /* This is the 8bit update version of the driver. */
8717 uint8_t unused_0[3];
8718 /* This is the 16bit major version of the driver. */
8720 /* This is the 16bit minor version of the driver. */
8722 /* This is the 16bit update version of the driver. */
8724 /* This is the 16bit patch version of the driver. */
8726 uint8_t unused_1[7];
8728 * This field is used in Output records to indicate that the output
8729 * is completely written to RAM. This field should be read as '1'
8730 * to indicate that the output has been completely written.
8731 * When writing a command completion or response to an internal processor,
8732 * the order of writes has to be such that this field is written last.
8735 } __attribute__((packed));
8737 /****************************
8738 * hwrm_func_resource_qcaps *
8739 ****************************/
8742 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
8743 struct hwrm_func_resource_qcaps_input {
8744 /* The HWRM command request type. */
8747 * The completion ring to send the completion event on. This should
8748 * be the NQ ID returned from the `nq_alloc` HWRM command.
8752 * The sequence ID is used by the driver for tracking multiple
8753 * commands. This ID is treated as opaque data by the firmware and
8754 * the value is returned in the `hwrm_resp_hdr` upon completion.
8758 * The target ID of the command:
8759 * * 0x0-0xFFF8 - The function ID
8760 * * 0xFFF8-0xFFFE - Reserved for internal processors
8765 * A physical address pointer pointing to a host buffer that the
8766 * command's response data will be written. This can be either a host
8767 * physical address (HPA) or a guest physical address (GPA) and must
8768 * point to a physically contiguous block of memory.
8772 * Function ID of the function that is being queried.
8773 * 0xFF... (All Fs) if the query is for the requesting
8777 uint8_t unused_0[6];
8778 } __attribute__((packed));
8780 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
8781 struct hwrm_func_resource_qcaps_output {
8782 /* The specific error status for the command. */
8783 uint16_t error_code;
8784 /* The HWRM command request type. */
8786 /* The sequence ID from the original command. */
8788 /* The length of the response data in number of bytes. */
8790 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
8792 /* Maximum guaranteed number of MSI-X vectors supported by function */
8794 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
8795 uint16_t vf_reservation_strategy;
8796 /* The PF driver should evenly divide its remaining resources among all VFs. */
8797 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
8799 /* The PF driver should only reserve minimal resources for each VF. */
8800 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
8803 * The PF driver should not reserve any resources for each VF until the
8804 * the VF interface is brought up.
8806 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
8808 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
8809 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
8810 /* Minimum guaranteed number of RSS/COS contexts */
8811 uint16_t min_rsscos_ctx;
8812 /* Maximum non-guaranteed number of RSS/COS contexts */
8813 uint16_t max_rsscos_ctx;
8814 /* Minimum guaranteed number of completion rings */
8815 uint16_t min_cmpl_rings;
8816 /* Maximum non-guaranteed number of completion rings */
8817 uint16_t max_cmpl_rings;
8818 /* Minimum guaranteed number of transmit rings */
8819 uint16_t min_tx_rings;
8820 /* Maximum non-guaranteed number of transmit rings */
8821 uint16_t max_tx_rings;
8822 /* Minimum guaranteed number of receive rings */
8823 uint16_t min_rx_rings;
8824 /* Maximum non-guaranteed number of receive rings */
8825 uint16_t max_rx_rings;
8826 /* Minimum guaranteed number of L2 contexts */
8827 uint16_t min_l2_ctxs;
8828 /* Maximum non-guaranteed number of L2 contexts */
8829 uint16_t max_l2_ctxs;
8830 /* Minimum guaranteed number of VNICs */
8832 /* Maximum non-guaranteed number of VNICs */
8834 /* Minimum guaranteed number of statistic contexts */
8835 uint16_t min_stat_ctx;
8836 /* Maximum non-guaranteed number of statistic contexts */
8837 uint16_t max_stat_ctx;
8838 /* Minimum guaranteed number of ring groups */
8839 uint16_t min_hw_ring_grps;
8840 /* Maximum non-guaranteed number of ring groups */
8841 uint16_t max_hw_ring_grps;
8843 * Maximum number of inputs into the transmit scheduler for this function.
8844 * The number of TX rings assigned to the function cannot exceed this value.
8846 uint16_t max_tx_scheduler_inputs;
8849 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
8850 * feature to reserve all minimum resources when minimum >= 1, otherwise
8853 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
8855 uint8_t unused_0[5];
8857 * This field is used in Output records to indicate that the output
8858 * is completely written to RAM. This field should be read as '1'
8859 * to indicate that the output has been completely written.
8860 * When writing a command completion or response to an internal processor,
8861 * the order of writes has to be such that this field is written last.
8864 } __attribute__((packed));
8866 /*********************************
8867 * hwrm_func_backing_store_qcaps *
8868 *********************************/
8871 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
8872 struct hwrm_func_backing_store_qcaps_input {
8873 /* The HWRM command request type. */
8876 * The completion ring to send the completion event on. This should
8877 * be the NQ ID returned from the `nq_alloc` HWRM command.
8881 * The sequence ID is used by the driver for tracking multiple
8882 * commands. This ID is treated as opaque data by the firmware and
8883 * the value is returned in the `hwrm_resp_hdr` upon completion.
8887 * The target ID of the command:
8888 * * 0x0-0xFFF8 - The function ID
8889 * * 0xFFF8-0xFFFE - Reserved for internal processors
8894 * A physical address pointer pointing to a host buffer that the
8895 * command's response data will be written. This can be either a host
8896 * physical address (HPA) or a guest physical address (GPA) and must
8897 * point to a physically contiguous block of memory.
8900 } __attribute__((packed));
8902 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
8903 struct hwrm_func_backing_store_qcaps_output {
8904 /* The specific error status for the command. */
8905 uint16_t error_code;
8906 /* The HWRM command request type. */
8908 /* The sequence ID from the original command. */
8910 /* The length of the response data in number of bytes. */
8912 /* Maximum number of QP context entries supported for this function. */
8913 uint32_t qp_max_entries;
8915 * Minimum number of QP context entries that are needed to be reserved
8916 * for QP1 for the PF and its VFs. PF drivers must allocate at least
8917 * this many QP context entries, even if RoCE will not be used.
8919 uint16_t qp_min_qp1_entries;
8920 /* Maximum number of QP context entries that can be used for L2. */
8921 uint16_t qp_max_l2_entries;
8922 /* Number of bytes that must be allocated for each context entry. */
8923 uint16_t qp_entry_size;
8924 /* Maximum number of SRQ context entries that can be used for L2. */
8925 uint16_t srq_max_l2_entries;
8926 /* Maximum number of SRQ context entries supported for this function. */
8927 uint32_t srq_max_entries;
8928 /* Number of bytes that must be allocated for each context entry. */
8929 uint16_t srq_entry_size;
8930 /* Maximum number of CQ context entries that can be used for L2. */
8931 uint16_t cq_max_l2_entries;
8932 /* Maximum number of CQ context entries supported for this function. */
8933 uint32_t cq_max_entries;
8934 /* Number of bytes that must be allocated for each context entry. */
8935 uint16_t cq_entry_size;
8936 /* Maximum number of VNIC context entries supported for this function. */
8937 uint16_t vnic_max_vnic_entries;
8938 /* Maximum number of Ring table context entries supported for this function. */
8939 uint16_t vnic_max_ring_table_entries;
8940 /* Number of bytes that must be allocated for each context entry. */
8941 uint16_t vnic_entry_size;
8942 /* Maximum number of statistic context entries supported for this function. */
8943 uint32_t stat_max_entries;
8944 /* Number of bytes that must be allocated for each context entry. */
8945 uint16_t stat_entry_size;
8946 /* Number of bytes that must be allocated for each context entry. */
8947 uint16_t tqm_entry_size;
8948 /* Minimum number of TQM context entries required per ring. */
8949 uint32_t tqm_min_entries_per_ring;
8951 * Maximum number of TQM context entries supported per ring. This is
8952 * actually a recommended TQM queue size based on worst case usage of
8955 * TQM fastpath rings should be sized large enough to accommodate the
8956 * maximum number of QPs (either L2 or RoCE, or both if shared)
8957 * that can be enqueued to the TQM ring.
8959 * TQM slowpath rings should be sized as follows:
8961 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
8964 * num_vnics is the number of VNICs allocated in the VNIC backing store
8965 * num_l2_tx_rings is the number of L2 rings in the QP backing store
8966 * num_roce_qps is the number of RoCE QPs in the QP backing store
8967 * tqm_min_size is tqm_min_entries_per_ring reported by
8968 * HWRM_FUNC_BACKING_STORE_QCAPS
8970 * Note that TQM ring sizes cannot be extended while the system is
8971 * operational. If a PF driver needs to extend a TQM ring, it needs
8972 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8973 * the backing store.
8975 uint32_t tqm_max_entries_per_ring;
8976 /* Maximum number of MR/AV context entries supported for this function. */
8977 uint32_t mrav_max_entries;
8978 /* Number of bytes that must be allocated for each context entry. */
8979 uint16_t mrav_entry_size;
8980 /* Number of bytes that must be allocated for each context entry. */
8981 uint16_t tim_entry_size;
8982 /* Maximum number of Timer context entries supported for this function. */
8983 uint32_t tim_max_entries;
8984 uint8_t unused_0[2];
8986 * The number of entries specified for any TQM ring must be a
8987 * multiple of this value to prevent any resource allocation
8990 uint8_t tqm_entries_multiple;
8992 * This field is used in Output records to indicate that the output
8993 * is completely written to RAM. This field should be read as '1'
8994 * to indicate that the output has been completely written.
8995 * When writing a command completion or response to an internal processor,
8996 * the order of writes has to be such that this field is written last.
8999 } __attribute__((packed));
9001 /*******************************
9002 * hwrm_func_backing_store_cfg *
9003 *******************************/
9006 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9007 struct hwrm_func_backing_store_cfg_input {
9008 /* The HWRM command request type. */
9011 * The completion ring to send the completion event on. This should
9012 * be the NQ ID returned from the `nq_alloc` HWRM command.
9016 * The sequence ID is used by the driver for tracking multiple
9017 * commands. This ID is treated as opaque data by the firmware and
9018 * the value is returned in the `hwrm_resp_hdr` upon completion.
9022 * The target ID of the command:
9023 * * 0x0-0xFFF8 - The function ID
9024 * * 0xFFF8-0xFFFE - Reserved for internal processors
9029 * A physical address pointer pointing to a host buffer that the
9030 * command's response data will be written. This can be either a host
9031 * physical address (HPA) or a guest physical address (GPA) and must
9032 * point to a physically contiguous block of memory.
9037 * When set, the firmware only uses on-chip resources and does not
9038 * expect any backing store to be provided by the host driver. This
9039 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9046 * This bit must be '1' for the qp fields to be
9049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9052 * This bit must be '1' for the srq fields to be
9055 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9058 * This bit must be '1' for the cq fields to be
9061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9064 * This bit must be '1' for the vnic fields to be
9067 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9070 * This bit must be '1' for the stat fields to be
9073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9076 * This bit must be '1' for the tqm_sp fields to be
9079 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9082 * This bit must be '1' for the tqm_ring0 fields to be
9085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9088 * This bit must be '1' for the tqm_ring1 fields to be
9091 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9094 * This bit must be '1' for the tqm_ring2 fields to be
9097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9100 * This bit must be '1' for the tqm_ring3 fields to be
9103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9106 * This bit must be '1' for the tqm_ring4 fields to be
9109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9112 * This bit must be '1' for the tqm_ring5 fields to be
9115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
9118 * This bit must be '1' for the tqm_ring6 fields to be
9121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
9124 * This bit must be '1' for the tqm_ring7 fields to be
9127 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
9130 * This bit must be '1' for the mrav fields to be
9133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
9136 * This bit must be '1' for the tim fields to be
9139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
9141 /* QPC page size and level. */
9142 uint8_t qpc_pg_size_qpc_lvl;
9143 /* QPC PBL indirect levels. */
9144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
9146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
9147 /* PBL pointer is physical start address. */
9148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
9150 /* PBL pointer points to PTE table. */
9151 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
9153 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
9156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
9157 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
9158 /* QPC page size. */
9159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
9161 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
9163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
9164 (UINT32_C(0x0) << 4)
9166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
9167 (UINT32_C(0x1) << 4)
9169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
9170 (UINT32_C(0x2) << 4)
9172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
9173 (UINT32_C(0x3) << 4)
9175 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
9176 (UINT32_C(0x4) << 4)
9178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
9179 (UINT32_C(0x5) << 4)
9180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
9181 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
9182 /* SRQ page size and level. */
9183 uint8_t srq_pg_size_srq_lvl;
9184 /* SRQ PBL indirect levels. */
9185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
9187 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
9188 /* PBL pointer is physical start address. */
9189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
9191 /* PBL pointer points to PTE table. */
9192 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
9194 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
9197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
9198 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
9199 /* SRQ page size. */
9200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
9202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
9204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
9205 (UINT32_C(0x0) << 4)
9207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
9208 (UINT32_C(0x1) << 4)
9210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
9211 (UINT32_C(0x2) << 4)
9213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
9214 (UINT32_C(0x3) << 4)
9216 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
9217 (UINT32_C(0x4) << 4)
9219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
9220 (UINT32_C(0x5) << 4)
9221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
9222 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
9223 /* CQ page size and level. */
9224 uint8_t cq_pg_size_cq_lvl;
9225 /* CQ PBL indirect levels. */
9226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
9228 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
9229 /* PBL pointer is physical start address. */
9230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
9232 /* PBL pointer points to PTE table. */
9233 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
9235 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
9238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
9239 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
9241 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
9243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
9245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
9246 (UINT32_C(0x0) << 4)
9248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
9249 (UINT32_C(0x1) << 4)
9251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
9252 (UINT32_C(0x2) << 4)
9254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
9255 (UINT32_C(0x3) << 4)
9257 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
9258 (UINT32_C(0x4) << 4)
9260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
9261 (UINT32_C(0x5) << 4)
9262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
9263 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
9264 /* VNIC page size and level. */
9265 uint8_t vnic_pg_size_vnic_lvl;
9266 /* VNIC PBL indirect levels. */
9267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
9269 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
9270 /* PBL pointer is physical start address. */
9271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
9273 /* PBL pointer points to PTE table. */
9274 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
9276 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
9279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
9280 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
9281 /* VNIC page size. */
9282 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
9284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
9286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
9287 (UINT32_C(0x0) << 4)
9289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
9290 (UINT32_C(0x1) << 4)
9292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
9293 (UINT32_C(0x2) << 4)
9295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
9296 (UINT32_C(0x3) << 4)
9298 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
9299 (UINT32_C(0x4) << 4)
9301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
9302 (UINT32_C(0x5) << 4)
9303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
9304 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
9305 /* Stat page size and level. */
9306 uint8_t stat_pg_size_stat_lvl;
9307 /* Stat PBL indirect levels. */
9308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
9310 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
9311 /* PBL pointer is physical start address. */
9312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
9314 /* PBL pointer points to PTE table. */
9315 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
9317 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
9320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
9321 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
9322 /* Stat page size. */
9323 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
9325 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
9327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
9328 (UINT32_C(0x0) << 4)
9330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
9331 (UINT32_C(0x1) << 4)
9333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
9334 (UINT32_C(0x2) << 4)
9336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
9337 (UINT32_C(0x3) << 4)
9339 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
9340 (UINT32_C(0x4) << 4)
9342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
9343 (UINT32_C(0x5) << 4)
9344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
9345 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
9346 /* TQM slow path page size and level. */
9347 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
9348 /* TQM slow path PBL indirect levels. */
9349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
9351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
9352 /* PBL pointer is physical start address. */
9353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
9355 /* PBL pointer points to PTE table. */
9356 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
9358 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
9361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
9362 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
9363 /* TQM slow path page size. */
9364 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
9366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
9368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
9369 (UINT32_C(0x0) << 4)
9371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
9372 (UINT32_C(0x1) << 4)
9374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
9375 (UINT32_C(0x2) << 4)
9377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
9378 (UINT32_C(0x3) << 4)
9380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
9381 (UINT32_C(0x4) << 4)
9383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
9384 (UINT32_C(0x5) << 4)
9385 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
9386 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
9387 /* TQM ring 0 page size and level. */
9388 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9389 /* TQM ring 0 PBL indirect levels. */
9390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
9392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
9393 /* PBL pointer is physical start address. */
9394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
9396 /* PBL pointer points to PTE table. */
9397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
9399 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
9402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
9403 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
9404 /* TQM ring 0 page size. */
9405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
9407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
9409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
9410 (UINT32_C(0x0) << 4)
9412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
9413 (UINT32_C(0x1) << 4)
9415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
9416 (UINT32_C(0x2) << 4)
9418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
9419 (UINT32_C(0x3) << 4)
9421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
9422 (UINT32_C(0x4) << 4)
9424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
9425 (UINT32_C(0x5) << 4)
9426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
9427 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
9428 /* TQM ring 1 page size and level. */
9429 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9430 /* TQM ring 1 PBL indirect levels. */
9431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
9433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
9434 /* PBL pointer is physical start address. */
9435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
9437 /* PBL pointer points to PTE table. */
9438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
9440 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
9443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
9444 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
9445 /* TQM ring 1 page size. */
9446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
9448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
9450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
9451 (UINT32_C(0x0) << 4)
9453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
9454 (UINT32_C(0x1) << 4)
9456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
9457 (UINT32_C(0x2) << 4)
9459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
9460 (UINT32_C(0x3) << 4)
9462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
9463 (UINT32_C(0x4) << 4)
9465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
9466 (UINT32_C(0x5) << 4)
9467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
9468 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
9469 /* TQM ring 2 page size and level. */
9470 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9471 /* TQM ring 2 PBL indirect levels. */
9472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
9474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
9475 /* PBL pointer is physical start address. */
9476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
9478 /* PBL pointer points to PTE table. */
9479 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
9481 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
9484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
9485 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
9486 /* TQM ring 2 page size. */
9487 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
9489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
9491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
9492 (UINT32_C(0x0) << 4)
9494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
9495 (UINT32_C(0x1) << 4)
9497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
9498 (UINT32_C(0x2) << 4)
9500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
9501 (UINT32_C(0x3) << 4)
9503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
9504 (UINT32_C(0x4) << 4)
9506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
9507 (UINT32_C(0x5) << 4)
9508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
9509 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
9510 /* TQM ring 3 page size and level. */
9511 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9512 /* TQM ring 3 PBL indirect levels. */
9513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
9515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
9516 /* PBL pointer is physical start address. */
9517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
9519 /* PBL pointer points to PTE table. */
9520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
9522 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
9525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
9526 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
9527 /* TQM ring 3 page size. */
9528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
9530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
9532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
9533 (UINT32_C(0x0) << 4)
9535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
9536 (UINT32_C(0x1) << 4)
9538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
9539 (UINT32_C(0x2) << 4)
9541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
9542 (UINT32_C(0x3) << 4)
9544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
9545 (UINT32_C(0x4) << 4)
9547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
9548 (UINT32_C(0x5) << 4)
9549 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
9550 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
9551 /* TQM ring 4 page size and level. */
9552 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9553 /* TQM ring 4 PBL indirect levels. */
9554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
9556 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
9557 /* PBL pointer is physical start address. */
9558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
9560 /* PBL pointer points to PTE table. */
9561 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
9563 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9564 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
9566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
9567 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
9568 /* TQM ring 4 page size. */
9569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
9571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
9573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
9574 (UINT32_C(0x0) << 4)
9576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
9577 (UINT32_C(0x1) << 4)
9579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
9580 (UINT32_C(0x2) << 4)
9582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
9583 (UINT32_C(0x3) << 4)
9585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
9586 (UINT32_C(0x4) << 4)
9588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
9589 (UINT32_C(0x5) << 4)
9590 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
9591 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
9592 /* TQM ring 5 page size and level. */
9593 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9594 /* TQM ring 5 PBL indirect levels. */
9595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
9597 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
9598 /* PBL pointer is physical start address. */
9599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
9601 /* PBL pointer points to PTE table. */
9602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
9604 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9605 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
9607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
9608 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
9609 /* TQM ring 5 page size. */
9610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
9612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
9614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
9615 (UINT32_C(0x0) << 4)
9617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
9618 (UINT32_C(0x1) << 4)
9620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
9621 (UINT32_C(0x2) << 4)
9623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
9624 (UINT32_C(0x3) << 4)
9626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
9627 (UINT32_C(0x4) << 4)
9629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
9630 (UINT32_C(0x5) << 4)
9631 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
9632 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
9633 /* TQM ring 6 page size and level. */
9634 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9635 /* TQM ring 6 PBL indirect levels. */
9636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
9638 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
9639 /* PBL pointer is physical start address. */
9640 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
9642 /* PBL pointer points to PTE table. */
9643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
9645 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
9648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
9649 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
9650 /* TQM ring 6 page size. */
9651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
9653 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
9655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
9656 (UINT32_C(0x0) << 4)
9658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
9659 (UINT32_C(0x1) << 4)
9661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
9662 (UINT32_C(0x2) << 4)
9664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
9665 (UINT32_C(0x3) << 4)
9667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
9668 (UINT32_C(0x4) << 4)
9670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
9671 (UINT32_C(0x5) << 4)
9672 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
9673 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
9674 /* TQM ring 7 page size and level. */
9675 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9676 /* TQM ring 7 PBL indirect levels. */
9677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
9679 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
9680 /* PBL pointer is physical start address. */
9681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
9683 /* PBL pointer points to PTE table. */
9684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
9686 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9687 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
9689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
9690 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
9691 /* TQM ring 7 page size. */
9692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
9694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
9696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
9697 (UINT32_C(0x0) << 4)
9699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
9700 (UINT32_C(0x1) << 4)
9702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
9703 (UINT32_C(0x2) << 4)
9705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
9706 (UINT32_C(0x3) << 4)
9708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
9709 (UINT32_C(0x4) << 4)
9711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
9712 (UINT32_C(0x5) << 4)
9713 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
9714 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
9715 /* MR/AV page size and level. */
9716 uint8_t mrav_pg_size_mrav_lvl;
9717 /* MR/AV PBL indirect levels. */
9718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
9720 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
9721 /* PBL pointer is physical start address. */
9722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
9724 /* PBL pointer points to PTE table. */
9725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
9727 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
9730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
9731 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
9732 /* MR/AV page size. */
9733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
9735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
9737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
9738 (UINT32_C(0x0) << 4)
9740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
9741 (UINT32_C(0x1) << 4)
9743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
9744 (UINT32_C(0x2) << 4)
9746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
9747 (UINT32_C(0x3) << 4)
9749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
9750 (UINT32_C(0x4) << 4)
9752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
9753 (UINT32_C(0x5) << 4)
9754 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
9755 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
9756 /* Timer page size and level. */
9757 uint8_t tim_pg_size_tim_lvl;
9758 /* Timer PBL indirect levels. */
9759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
9761 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
9762 /* PBL pointer is physical start address. */
9763 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
9765 /* PBL pointer points to PTE table. */
9766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
9768 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
9771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
9772 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
9773 /* Timer page size. */
9774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
9776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
9778 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
9779 (UINT32_C(0x0) << 4)
9781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
9782 (UINT32_C(0x1) << 4)
9784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
9785 (UINT32_C(0x2) << 4)
9787 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
9788 (UINT32_C(0x3) << 4)
9790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
9791 (UINT32_C(0x4) << 4)
9793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
9794 (UINT32_C(0x5) << 4)
9795 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
9796 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
9797 /* QP page directory. */
9798 uint64_t qpc_page_dir;
9799 /* SRQ page directory. */
9800 uint64_t srq_page_dir;
9801 /* CQ page directory. */
9802 uint64_t cq_page_dir;
9803 /* VNIC page directory. */
9804 uint64_t vnic_page_dir;
9805 /* Stat page directory. */
9806 uint64_t stat_page_dir;
9807 /* TQM slowpath page directory. */
9808 uint64_t tqm_sp_page_dir;
9809 /* TQM ring 0 page directory. */
9810 uint64_t tqm_ring0_page_dir;
9811 /* TQM ring 1 page directory. */
9812 uint64_t tqm_ring1_page_dir;
9813 /* TQM ring 2 page directory. */
9814 uint64_t tqm_ring2_page_dir;
9815 /* TQM ring 3 page directory. */
9816 uint64_t tqm_ring3_page_dir;
9817 /* TQM ring 4 page directory. */
9818 uint64_t tqm_ring4_page_dir;
9819 /* TQM ring 5 page directory. */
9820 uint64_t tqm_ring5_page_dir;
9821 /* TQM ring 6 page directory. */
9822 uint64_t tqm_ring6_page_dir;
9823 /* TQM ring 7 page directory. */
9824 uint64_t tqm_ring7_page_dir;
9825 /* MR/AV page directory. */
9826 uint64_t mrav_page_dir;
9827 /* Timer page directory. */
9828 uint64_t tim_page_dir;
9829 /* Number of QPs. */
9830 uint32_t qp_num_entries;
9831 /* Number of SRQs. */
9832 uint32_t srq_num_entries;
9833 /* Number of CQs. */
9834 uint32_t cq_num_entries;
9835 /* Number of Stats. */
9836 uint32_t stat_num_entries;
9838 * Number of TQM slowpath entries.
9840 * TQM slowpath rings should be sized as follows:
9842 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9845 * num_vnics is the number of VNICs allocated in the VNIC backing store
9846 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9847 * num_roce_qps is the number of RoCE QPs in the QP backing store
9848 * tqm_min_size is tqm_min_entries_per_ring reported by
9849 * HWRM_FUNC_BACKING_STORE_QCAPS
9851 * Note that TQM ring sizes cannot be extended while the system is
9852 * operational. If a PF driver needs to extend a TQM ring, it needs
9853 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9854 * the backing store.
9856 uint32_t tqm_sp_num_entries;
9858 * Number of TQM ring 0 entries.
9860 * TQM fastpath rings should be sized large enough to accommodate the
9861 * maximum number of QPs (either L2 or RoCE, or both if shared)
9862 * that can be enqueued to the TQM ring.
9864 * Note that TQM ring sizes cannot be extended while the system is
9865 * operational. If a PF driver needs to extend a TQM ring, it needs
9866 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9867 * the backing store.
9869 uint32_t tqm_ring0_num_entries;
9871 * Number of TQM ring 1 entries.
9873 * TQM fastpath rings should be sized large enough to accommodate the
9874 * maximum number of QPs (either L2 or RoCE, or both if shared)
9875 * that can be enqueued to the TQM ring.
9877 * Note that TQM ring sizes cannot be extended while the system is
9878 * operational. If a PF driver needs to extend a TQM ring, it needs
9879 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9880 * the backing store.
9882 uint32_t tqm_ring1_num_entries;
9884 * Number of TQM ring 2 entries.
9886 * TQM fastpath rings should be sized large enough to accommodate the
9887 * maximum number of QPs (either L2 or RoCE, or both if shared)
9888 * that can be enqueued to the TQM ring.
9890 * Note that TQM ring sizes cannot be extended while the system is
9891 * operational. If a PF driver needs to extend a TQM ring, it needs
9892 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9893 * the backing store.
9895 uint32_t tqm_ring2_num_entries;
9897 * Number of TQM ring 3 entries.
9899 * TQM fastpath rings should be sized large enough to accommodate the
9900 * maximum number of QPs (either L2 or RoCE, or both if shared)
9901 * that can be enqueued to the TQM ring.
9903 * Note that TQM ring sizes cannot be extended while the system is
9904 * operational. If a PF driver needs to extend a TQM ring, it needs
9905 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9906 * the backing store.
9908 uint32_t tqm_ring3_num_entries;
9910 * Number of TQM ring 4 entries.
9912 * TQM fastpath rings should be sized large enough to accommodate the
9913 * maximum number of QPs (either L2 or RoCE, or both if shared)
9914 * that can be enqueued to the TQM ring.
9916 * Note that TQM ring sizes cannot be extended while the system is
9917 * operational. If a PF driver needs to extend a TQM ring, it needs
9918 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9919 * the backing store.
9921 uint32_t tqm_ring4_num_entries;
9923 * Number of TQM ring 5 entries.
9925 * TQM fastpath rings should be sized large enough to accommodate the
9926 * maximum number of QPs (either L2 or RoCE, or both if shared)
9927 * that can be enqueued to the TQM ring.
9929 * Note that TQM ring sizes cannot be extended while the system is
9930 * operational. If a PF driver needs to extend a TQM ring, it needs
9931 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9932 * the backing store.
9934 uint32_t tqm_ring5_num_entries;
9936 * Number of TQM ring 6 entries.
9938 * TQM fastpath rings should be sized large enough to accommodate the
9939 * maximum number of QPs (either L2 or RoCE, or both if shared)
9940 * that can be enqueued to the TQM ring.
9942 * Note that TQM ring sizes cannot be extended while the system is
9943 * operational. If a PF driver needs to extend a TQM ring, it needs
9944 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9945 * the backing store.
9947 uint32_t tqm_ring6_num_entries;
9949 * Number of TQM ring 7 entries.
9951 * TQM fastpath rings should be sized large enough to accommodate the
9952 * maximum number of QPs (either L2 or RoCE, or both if shared)
9953 * that can be enqueued to the TQM ring.
9955 * Note that TQM ring sizes cannot be extended while the system is
9956 * operational. If a PF driver needs to extend a TQM ring, it needs
9957 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9958 * the backing store.
9960 uint32_t tqm_ring7_num_entries;
9961 /* Number of MR/AV entries. */
9962 uint32_t mrav_num_entries;
9963 /* Number of Timer entries. */
9964 uint32_t tim_num_entries;
9965 /* Number of entries to reserve for QP1 */
9966 uint16_t qp_num_qp1_entries;
9967 /* Number of entries to reserve for L2 */
9968 uint16_t qp_num_l2_entries;
9969 /* Number of bytes that have been allocated for each context entry. */
9970 uint16_t qp_entry_size;
9971 /* Number of entries to reserve for L2 */
9972 uint16_t srq_num_l2_entries;
9973 /* Number of bytes that have been allocated for each context entry. */
9974 uint16_t srq_entry_size;
9975 /* Number of entries to reserve for L2 */
9976 uint16_t cq_num_l2_entries;
9977 /* Number of bytes that have been allocated for each context entry. */
9978 uint16_t cq_entry_size;
9979 /* Number of entries to reserve for VNIC entries */
9980 uint16_t vnic_num_vnic_entries;
9981 /* Number of entries to reserve for Ring table entries */
9982 uint16_t vnic_num_ring_table_entries;
9983 /* Number of bytes that have been allocated for each context entry. */
9984 uint16_t vnic_entry_size;
9985 /* Number of bytes that have been allocated for each context entry. */
9986 uint16_t stat_entry_size;
9987 /* Number of bytes that have been allocated for each context entry. */
9988 uint16_t tqm_entry_size;
9989 /* Number of bytes that have been allocated for each context entry. */
9990 uint16_t mrav_entry_size;
9991 /* Number of bytes that have been allocated for each context entry. */
9992 uint16_t tim_entry_size;
9993 } __attribute__((packed));
9995 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
9996 struct hwrm_func_backing_store_cfg_output {
9997 /* The specific error status for the command. */
9998 uint16_t error_code;
9999 /* The HWRM command request type. */
10001 /* The sequence ID from the original command. */
10003 /* The length of the response data in number of bytes. */
10005 uint8_t unused_0[7];
10007 * This field is used in Output records to indicate that the output
10008 * is completely written to RAM. This field should be read as '1'
10009 * to indicate that the output has been completely written.
10010 * When writing a command completion or response to an internal processor,
10011 * the order of writes has to be such that this field is written last.
10014 } __attribute__((packed));
10016 /********************************
10017 * hwrm_func_backing_store_qcfg *
10018 ********************************/
10021 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10022 struct hwrm_func_backing_store_qcfg_input {
10023 /* The HWRM command request type. */
10026 * The completion ring to send the completion event on. This should
10027 * be the NQ ID returned from the `nq_alloc` HWRM command.
10029 uint16_t cmpl_ring;
10031 * The sequence ID is used by the driver for tracking multiple
10032 * commands. This ID is treated as opaque data by the firmware and
10033 * the value is returned in the `hwrm_resp_hdr` upon completion.
10037 * The target ID of the command:
10038 * * 0x0-0xFFF8 - The function ID
10039 * * 0xFFF8-0xFFFE - Reserved for internal processors
10042 uint16_t target_id;
10044 * A physical address pointer pointing to a host buffer that the
10045 * command's response data will be written. This can be either a host
10046 * physical address (HPA) or a guest physical address (GPA) and must
10047 * point to a physically contiguous block of memory.
10049 uint64_t resp_addr;
10050 } __attribute__((packed));
10052 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10053 struct hwrm_func_backing_store_qcfg_output {
10054 /* The specific error status for the command. */
10055 uint16_t error_code;
10056 /* The HWRM command request type. */
10058 /* The sequence ID from the original command. */
10060 /* The length of the response data in number of bytes. */
10064 * When set, the firmware only uses on-chip resources and does not
10065 * expect any backing store to be provided by the host driver. This
10066 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10071 uint8_t unused_0[4];
10073 * This bit must be '1' for the qp fields to be
10076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10079 * This bit must be '1' for the srq fields to be
10082 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10085 * This bit must be '1' for the cq fields to be
10088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10091 * This bit must be '1' for the vnic fields to be
10094 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
10097 * This bit must be '1' for the stat fields to be
10100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
10103 * This bit must be '1' for the tqm_sp fields to be
10106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
10109 * This bit must be '1' for the tqm_ring0 fields to be
10112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
10115 * This bit must be '1' for the tqm_ring1 fields to be
10118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
10121 * This bit must be '1' for the tqm_ring2 fields to be
10124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
10127 * This bit must be '1' for the tqm_ring3 fields to be
10130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
10133 * This bit must be '1' for the tqm_ring4 fields to be
10136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
10139 * This bit must be '1' for the tqm_ring5 fields to be
10142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
10145 * This bit must be '1' for the tqm_ring6 fields to be
10148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
10151 * This bit must be '1' for the tqm_ring7 fields to be
10154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
10157 * This bit must be '1' for the mrav fields to be
10160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
10163 * This bit must be '1' for the tim fields to be
10166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
10168 /* QPC page size and level. */
10169 uint8_t qpc_pg_size_qpc_lvl;
10170 /* QPC PBL indirect levels. */
10171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
10173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
10174 /* PBL pointer is physical start address. */
10175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
10177 /* PBL pointer points to PTE table. */
10178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
10180 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
10183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
10184 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
10185 /* QPC page size. */
10186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
10188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
10190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
10191 (UINT32_C(0x0) << 4)
10193 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
10194 (UINT32_C(0x1) << 4)
10196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
10197 (UINT32_C(0x2) << 4)
10199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
10200 (UINT32_C(0x3) << 4)
10202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
10203 (UINT32_C(0x4) << 4)
10205 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
10206 (UINT32_C(0x5) << 4)
10207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
10208 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
10209 /* SRQ page size and level. */
10210 uint8_t srq_pg_size_srq_lvl;
10211 /* SRQ PBL indirect levels. */
10212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
10214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
10215 /* PBL pointer is physical start address. */
10216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
10218 /* PBL pointer points to PTE table. */
10219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
10221 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10222 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
10224 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
10225 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
10226 /* SRQ page size. */
10227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
10229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
10231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
10232 (UINT32_C(0x0) << 4)
10234 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
10235 (UINT32_C(0x1) << 4)
10237 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
10238 (UINT32_C(0x2) << 4)
10240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
10241 (UINT32_C(0x3) << 4)
10243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
10244 (UINT32_C(0x4) << 4)
10246 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
10247 (UINT32_C(0x5) << 4)
10248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
10249 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
10250 /* CQ page size and level. */
10251 uint8_t cq_pg_size_cq_lvl;
10252 /* CQ PBL indirect levels. */
10253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
10255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
10256 /* PBL pointer is physical start address. */
10257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
10259 /* PBL pointer points to PTE table. */
10260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
10262 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10263 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
10265 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
10266 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
10267 /* CQ page size. */
10268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
10270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
10272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
10273 (UINT32_C(0x0) << 4)
10275 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
10276 (UINT32_C(0x1) << 4)
10278 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
10279 (UINT32_C(0x2) << 4)
10281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
10282 (UINT32_C(0x3) << 4)
10284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
10285 (UINT32_C(0x4) << 4)
10287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
10288 (UINT32_C(0x5) << 4)
10289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
10290 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
10291 /* VNIC page size and level. */
10292 uint8_t vnic_pg_size_vnic_lvl;
10293 /* VNIC PBL indirect levels. */
10294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
10296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
10297 /* PBL pointer is physical start address. */
10298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
10300 /* PBL pointer points to PTE table. */
10301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
10303 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10304 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
10306 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
10307 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
10308 /* VNIC page size. */
10309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
10311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
10313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
10314 (UINT32_C(0x0) << 4)
10316 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
10317 (UINT32_C(0x1) << 4)
10319 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
10320 (UINT32_C(0x2) << 4)
10322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
10323 (UINT32_C(0x3) << 4)
10325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
10326 (UINT32_C(0x4) << 4)
10328 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
10329 (UINT32_C(0x5) << 4)
10330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
10331 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
10332 /* Stat page size and level. */
10333 uint8_t stat_pg_size_stat_lvl;
10334 /* Stat PBL indirect levels. */
10335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
10337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
10338 /* PBL pointer is physical start address. */
10339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
10341 /* PBL pointer points to PTE table. */
10342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
10344 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10345 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
10347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
10348 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
10349 /* Stat page size. */
10350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
10352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
10354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
10355 (UINT32_C(0x0) << 4)
10357 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
10358 (UINT32_C(0x1) << 4)
10360 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
10361 (UINT32_C(0x2) << 4)
10363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
10364 (UINT32_C(0x3) << 4)
10366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
10367 (UINT32_C(0x4) << 4)
10369 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
10370 (UINT32_C(0x5) << 4)
10371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
10372 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
10373 /* TQM slow path page size and level. */
10374 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10375 /* TQM slow path PBL indirect levels. */
10376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
10378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
10379 /* PBL pointer is physical start address. */
10380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
10382 /* PBL pointer points to PTE table. */
10383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
10385 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
10388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
10389 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
10390 /* TQM slow path page size. */
10391 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
10393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
10395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
10396 (UINT32_C(0x0) << 4)
10398 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
10399 (UINT32_C(0x1) << 4)
10401 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
10402 (UINT32_C(0x2) << 4)
10404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
10405 (UINT32_C(0x3) << 4)
10407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
10408 (UINT32_C(0x4) << 4)
10410 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
10411 (UINT32_C(0x5) << 4)
10412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
10413 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
10414 /* TQM ring 0 page size and level. */
10415 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10416 /* TQM ring 0 PBL indirect levels. */
10417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
10419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
10420 /* PBL pointer is physical start address. */
10421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
10423 /* PBL pointer points to PTE table. */
10424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
10426 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
10429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
10430 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
10431 /* TQM ring 0 page size. */
10432 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
10434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
10436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
10437 (UINT32_C(0x0) << 4)
10439 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
10440 (UINT32_C(0x1) << 4)
10442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
10443 (UINT32_C(0x2) << 4)
10445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
10446 (UINT32_C(0x3) << 4)
10448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
10449 (UINT32_C(0x4) << 4)
10451 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
10452 (UINT32_C(0x5) << 4)
10453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
10454 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
10455 /* TQM ring 1 page size and level. */
10456 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10457 /* TQM ring 1 PBL indirect levels. */
10458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
10460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
10461 /* PBL pointer is physical start address. */
10462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
10464 /* PBL pointer points to PTE table. */
10465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
10467 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
10470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
10471 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
10472 /* TQM ring 1 page size. */
10473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
10475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
10477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
10478 (UINT32_C(0x0) << 4)
10480 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
10481 (UINT32_C(0x1) << 4)
10483 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
10484 (UINT32_C(0x2) << 4)
10486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
10487 (UINT32_C(0x3) << 4)
10489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
10490 (UINT32_C(0x4) << 4)
10492 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
10493 (UINT32_C(0x5) << 4)
10494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
10495 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
10496 /* TQM ring 2 page size and level. */
10497 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10498 /* TQM ring 2 PBL indirect levels. */
10499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
10501 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
10502 /* PBL pointer is physical start address. */
10503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
10505 /* PBL pointer points to PTE table. */
10506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
10508 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
10511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
10512 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
10513 /* TQM ring 2 page size. */
10514 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
10516 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
10518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
10519 (UINT32_C(0x0) << 4)
10521 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
10522 (UINT32_C(0x1) << 4)
10524 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
10525 (UINT32_C(0x2) << 4)
10527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
10528 (UINT32_C(0x3) << 4)
10530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
10531 (UINT32_C(0x4) << 4)
10533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
10534 (UINT32_C(0x5) << 4)
10535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
10536 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
10537 /* TQM ring 3 page size and level. */
10538 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10539 /* TQM ring 3 PBL indirect levels. */
10540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
10542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
10543 /* PBL pointer is physical start address. */
10544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
10546 /* PBL pointer points to PTE table. */
10547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
10549 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
10552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
10553 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
10554 /* TQM ring 3 page size. */
10555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
10557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
10559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
10560 (UINT32_C(0x0) << 4)
10562 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
10563 (UINT32_C(0x1) << 4)
10565 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
10566 (UINT32_C(0x2) << 4)
10568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
10569 (UINT32_C(0x3) << 4)
10571 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
10572 (UINT32_C(0x4) << 4)
10574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
10575 (UINT32_C(0x5) << 4)
10576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
10577 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
10578 /* TQM ring 4 page size and level. */
10579 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10580 /* TQM ring 4 PBL indirect levels. */
10581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
10583 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
10584 /* PBL pointer is physical start address. */
10585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
10587 /* PBL pointer points to PTE table. */
10588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
10590 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
10593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
10594 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
10595 /* TQM ring 4 page size. */
10596 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
10598 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
10600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
10601 (UINT32_C(0x0) << 4)
10603 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
10604 (UINT32_C(0x1) << 4)
10606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
10607 (UINT32_C(0x2) << 4)
10609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
10610 (UINT32_C(0x3) << 4)
10612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
10613 (UINT32_C(0x4) << 4)
10615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
10616 (UINT32_C(0x5) << 4)
10617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
10618 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
10619 /* TQM ring 5 page size and level. */
10620 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10621 /* TQM ring 5 PBL indirect levels. */
10622 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
10624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
10625 /* PBL pointer is physical start address. */
10626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
10628 /* PBL pointer points to PTE table. */
10629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
10631 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
10634 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
10635 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
10636 /* TQM ring 5 page size. */
10637 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
10639 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
10641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
10642 (UINT32_C(0x0) << 4)
10644 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
10645 (UINT32_C(0x1) << 4)
10647 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
10648 (UINT32_C(0x2) << 4)
10650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
10651 (UINT32_C(0x3) << 4)
10653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
10654 (UINT32_C(0x4) << 4)
10656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
10657 (UINT32_C(0x5) << 4)
10658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
10659 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
10660 /* TQM ring 6 page size and level. */
10661 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10662 /* TQM ring 6 PBL indirect levels. */
10663 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
10665 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
10666 /* PBL pointer is physical start address. */
10667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
10669 /* PBL pointer points to PTE table. */
10670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
10672 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
10675 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
10676 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
10677 /* TQM ring 6 page size. */
10678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
10680 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
10682 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
10683 (UINT32_C(0x0) << 4)
10685 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
10686 (UINT32_C(0x1) << 4)
10688 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
10689 (UINT32_C(0x2) << 4)
10691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
10692 (UINT32_C(0x3) << 4)
10694 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
10695 (UINT32_C(0x4) << 4)
10697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
10698 (UINT32_C(0x5) << 4)
10699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
10700 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
10701 /* TQM ring 7 page size and level. */
10702 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10703 /* TQM ring 7 PBL indirect levels. */
10704 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
10706 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
10707 /* PBL pointer is physical start address. */
10708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
10710 /* PBL pointer points to PTE table. */
10711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
10713 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
10716 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
10717 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
10718 /* TQM ring 7 page size. */
10719 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
10721 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
10723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
10724 (UINT32_C(0x0) << 4)
10726 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
10727 (UINT32_C(0x1) << 4)
10729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
10730 (UINT32_C(0x2) << 4)
10732 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
10733 (UINT32_C(0x3) << 4)
10735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
10736 (UINT32_C(0x4) << 4)
10738 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
10739 (UINT32_C(0x5) << 4)
10740 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
10741 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
10742 /* MR/AV page size and level. */
10743 uint8_t mrav_pg_size_mrav_lvl;
10744 /* MR/AV PBL indirect levels. */
10745 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
10747 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
10748 /* PBL pointer is physical start address. */
10749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
10751 /* PBL pointer points to PTE table. */
10752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
10754 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10755 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
10757 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
10758 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
10759 /* MR/AV page size. */
10760 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
10762 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
10764 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
10765 (UINT32_C(0x0) << 4)
10767 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
10768 (UINT32_C(0x1) << 4)
10770 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
10771 (UINT32_C(0x2) << 4)
10773 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
10774 (UINT32_C(0x3) << 4)
10776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
10777 (UINT32_C(0x4) << 4)
10779 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
10780 (UINT32_C(0x5) << 4)
10781 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
10782 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
10783 /* Timer page size and level. */
10784 uint8_t tim_pg_size_tim_lvl;
10785 /* Timer PBL indirect levels. */
10786 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
10788 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
10789 /* PBL pointer is physical start address. */
10790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
10792 /* PBL pointer points to PTE table. */
10793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
10795 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
10798 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
10799 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
10800 /* Timer page size. */
10801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
10803 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
10805 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
10806 (UINT32_C(0x0) << 4)
10808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
10809 (UINT32_C(0x1) << 4)
10811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
10812 (UINT32_C(0x2) << 4)
10814 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
10815 (UINT32_C(0x3) << 4)
10817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
10818 (UINT32_C(0x4) << 4)
10820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
10821 (UINT32_C(0x5) << 4)
10822 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
10823 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
10824 /* QP page directory. */
10825 uint64_t qpc_page_dir;
10826 /* SRQ page directory. */
10827 uint64_t srq_page_dir;
10828 /* CQ page directory. */
10829 uint64_t cq_page_dir;
10830 /* VNIC page directory. */
10831 uint64_t vnic_page_dir;
10832 /* Stat page directory. */
10833 uint64_t stat_page_dir;
10834 /* TQM slowpath page directory. */
10835 uint64_t tqm_sp_page_dir;
10836 /* TQM ring 0 page directory. */
10837 uint64_t tqm_ring0_page_dir;
10838 /* TQM ring 1 page directory. */
10839 uint64_t tqm_ring1_page_dir;
10840 /* TQM ring 2 page directory. */
10841 uint64_t tqm_ring2_page_dir;
10842 /* TQM ring 3 page directory. */
10843 uint64_t tqm_ring3_page_dir;
10844 /* TQM ring 4 page directory. */
10845 uint64_t tqm_ring4_page_dir;
10846 /* TQM ring 5 page directory. */
10847 uint64_t tqm_ring5_page_dir;
10848 /* TQM ring 6 page directory. */
10849 uint64_t tqm_ring6_page_dir;
10850 /* TQM ring 7 page directory. */
10851 uint64_t tqm_ring7_page_dir;
10852 /* MR/AV page directory. */
10853 uint64_t mrav_page_dir;
10854 /* Timer page directory. */
10855 uint64_t tim_page_dir;
10856 /* Number of entries to reserve for QP1 */
10857 uint16_t qp_num_qp1_entries;
10858 /* Number of entries to reserve for L2 */
10859 uint16_t qp_num_l2_entries;
10860 /* Number of QPs. */
10861 uint32_t qp_num_entries;
10862 /* Number of SRQs. */
10863 uint32_t srq_num_entries;
10864 /* Number of entries to reserve for L2 */
10865 uint16_t srq_num_l2_entries;
10866 /* Number of entries to reserve for L2 */
10867 uint16_t cq_num_l2_entries;
10868 /* Number of CQs. */
10869 uint32_t cq_num_entries;
10870 /* Number of entries to reserve for VNIC entries */
10871 uint16_t vnic_num_vnic_entries;
10872 /* Number of entries to reserve for Ring table entries */
10873 uint16_t vnic_num_ring_table_entries;
10874 /* Number of Stats. */
10875 uint32_t stat_num_entries;
10876 /* Number of TQM slowpath entries. */
10877 uint32_t tqm_sp_num_entries;
10878 /* Number of TQM ring 0 entries. */
10879 uint32_t tqm_ring0_num_entries;
10880 /* Number of TQM ring 1 entries. */
10881 uint32_t tqm_ring1_num_entries;
10882 /* Number of TQM ring 2 entries. */
10883 uint32_t tqm_ring2_num_entries;
10884 /* Number of TQM ring 3 entries. */
10885 uint32_t tqm_ring3_num_entries;
10886 /* Number of TQM ring 4 entries. */
10887 uint32_t tqm_ring4_num_entries;
10888 /* Number of TQM ring 5 entries. */
10889 uint32_t tqm_ring5_num_entries;
10890 /* Number of TQM ring 6 entries. */
10891 uint32_t tqm_ring6_num_entries;
10892 /* Number of TQM ring 7 entries. */
10893 uint32_t tqm_ring7_num_entries;
10894 /* Number of MR/AV entries. */
10895 uint32_t mrav_num_entries;
10896 /* Number of Timer entries. */
10897 uint32_t tim_num_entries;
10898 uint8_t unused_1[7];
10900 * This field is used in Output records to indicate that the output
10901 * is completely written to RAM. This field should be read as 1
10902 * to indicate that the output has been completely written.
10903 * When writing a command completion or response to an internal
10904 * processor, the order of writes has to be such that this field
10908 } __attribute__((packed));
10910 /****************************
10911 * hwrm_error_recovery_qcfg *
10912 ****************************/
10915 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
10916 struct hwrm_error_recovery_qcfg_input {
10917 /* The HWRM command request type. */
10920 * The completion ring to send the completion event on. This should
10921 * be the NQ ID returned from the `nq_alloc` HWRM command.
10923 uint16_t cmpl_ring;
10925 * The sequence ID is used by the driver for tracking multiple
10926 * commands. This ID is treated as opaque data by the firmware and
10927 * the value is returned in the `hwrm_resp_hdr` upon completion.
10931 * The target ID of the command:
10932 * * 0x0-0xFFF8 - The function ID
10933 * * 0xFFF8-0xFFFE - Reserved for internal processors
10936 uint16_t target_id;
10938 * A physical address pointer pointing to a host buffer that the
10939 * command's response data will be written. This can be either a host
10940 * physical address (HPA) or a guest physical address (GPA) and must
10941 * point to a physically contiguous block of memory.
10943 uint64_t resp_addr;
10944 uint8_t unused_0[8];
10945 } __attribute__((packed));
10947 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
10948 struct hwrm_error_recovery_qcfg_output {
10949 /* The specific error status for the command. */
10950 uint16_t error_code;
10951 /* The HWRM command request type. */
10953 /* The sequence ID from the original command. */
10955 /* The length of the response data in number of bytes. */
10959 * When this flag is set to 1, error recovery will be initiated
10960 * through master function driver.
10962 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
10964 * When this flag is set to 1, error recovery will be performed
10965 * through Co processor.
10967 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
10969 * Driver Polling frequency. This value is in units of 100msec.
10970 * Typical value would be 10 to indicate 1sec.
10971 * Drivers can poll FW health status, Heartbeat, reset_counter with
10974 uint32_t driver_polling_freq;
10976 * This value is in units of 100msec.
10977 * Typical value would be 30 to indicate 3sec.
10978 * Master function wait period from detecting a fatal error to
10979 * initiating reset. In this time period Master PF expects every
10980 * active driver will detect fatal error.
10982 uint32_t master_func_wait_period;
10984 * This value is in units of 100msec.
10985 * Typical value would be 50 to indicate 5sec.
10986 * Normal function wait period from fatal error detection to
10987 * polling FW health status. In this time period, drivers should not
10988 * do any PCIe MMIO transaction and should not send any HWRM commands.
10990 uint32_t normal_func_wait_period;
10992 * This value is in units of 100msec.
10993 * Typical value would be 20 to indicate 2sec.
10994 * This field indicates that, master function wait period after chip
10995 * reset. After this time, master function should reinitialize with
10998 uint32_t master_func_wait_period_after_reset;
11000 * This value is in units of 100msec.
11001 * Typical value would be 60 to indicate 6sec.
11002 * This field is applicable to both master and normal functions.
11003 * Even after chip reset, if FW status not changed to ready,
11004 * then all the functions can poll for this much time and bailout.
11006 uint32_t max_bailout_time_after_reset;
11008 * FW health status register.
11009 * Lower 2 bits indicates address space location and upper 30 bits
11010 * indicates upper 30bits of the register address.
11011 * A value of 0xFFFF-FFFF indicates this register does not exist.
11013 uint32_t fw_health_status_reg;
11014 /* Lower 2 bits indicates address space location. */
11015 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11017 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11020 * If value is 0, this register is located in PCIe config space.
11021 * Drivers have to map appropriate window to access this
11024 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11027 * If value is 1, this register is located in GRC address space.
11028 * Drivers have to map appropriate window to access this
11031 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11034 * If value is 2, this register is located in first BAR address
11035 * space. Drivers have to map appropriate window to access this
11038 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11041 * If value is 3, this register is located in second BAR address
11042 * space. Drivers have to map appropriate window to access this
11043 * Drivers have to map appropriate window to access this
11046 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11048 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11049 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11050 /* Upper 30bits of the register address. */
11051 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11052 UINT32_C(0xfffffffc)
11053 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11056 * FW HeartBeat register.
11057 * Lower 2 bits indicates address space location and upper 30 bits
11058 * indicates actual address.
11059 * A value of 0xFFFF-FFFF indicates this register does not exist.
11061 uint32_t fw_heartbeat_reg;
11062 /* Lower 2 bits indicates address space location. */
11063 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11065 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11068 * If value is 0, this register is located in PCIe config space.
11069 * Drivers have to map appropriate window to access this
11072 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11075 * If value is 1, this register is located in GRC address space.
11076 * Drivers have to map appropriate window to access this
11079 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11082 * If value is 2, this register is located in first BAR address
11083 * space. Drivers have to map appropriate window to access this
11086 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
11089 * If value is 3, this register is located in second BAR address
11090 * space. Drivers have to map appropriate window to access this
11093 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
11095 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
11096 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
11097 /* Upper 30bits of the register address. */
11098 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
11099 UINT32_C(0xfffffffc)
11100 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
11103 * FW reset counter.
11104 * Lower 2 bits indicates address space location and upper 30 bits
11105 * indicates actual address.
11106 * A value of 0xFFFF-FFFF indicates this register does not exist.
11108 uint32_t fw_reset_cnt_reg;
11109 /* Lower 2 bits indicates address space location. */
11110 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
11112 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
11115 * If value is 0, this register is located in PCIe config space.
11116 * Drivers have to map appropriate window to access this
11119 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
11122 * If value is 1, this register is located in GRC address space.
11123 * Drivers have to map appropriate window to access this
11126 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
11129 * If value is 2, this register is located in first BAR address
11130 * space. Drivers have to map appropriate window to access this
11133 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
11136 * If value is 3, this register is located in second BAR address
11137 * space. Drivers have to map appropriate window to access this
11140 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
11142 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
11143 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
11144 /* Upper 30bits of the register address. */
11145 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
11146 UINT32_C(0xfffffffc)
11147 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
11150 * Reset Inprogress Register address for PFs.
11151 * Lower 2 bits indicates address space location and upper 30 bits
11152 * indicates actual address.
11153 * A value of 0xFFFF-FFFF indicates this register does not exist.
11155 uint32_t reset_inprogress_reg;
11156 /* Lower 2 bits indicates address space location. */
11157 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
11159 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
11162 * If value is 0, this register is located in PCIe config space.
11163 * Drivers have to map appropriate window to access this
11166 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
11169 * If value is 1, this register is located in GRC address space.
11170 * Drivers have to map appropriate window to access this
11173 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
11176 * If value is 2, this register is located in first BAR address
11177 * space. Drivers have to map appropriate window to access this
11180 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
11183 * If value is 3, this register is located in second BAR address
11184 * space. Drivers have to map appropriate window to access this
11187 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
11189 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
11190 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
11191 /* Upper 30bits of the register address. */
11192 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
11193 UINT32_C(0xfffffffc)
11194 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
11196 /* This field indicates the mask value for reset_inprogress_reg. */
11197 uint32_t reset_inprogress_reg_mask;
11198 uint8_t unused_0[3];
11200 * Array of registers and value count to reset the Chip
11201 * Each array count has reset_reg, reset_reg_val, delay_after_reset
11202 * in TLV format. Depending upon Chip type, number of reset registers
11203 * will vary. Drivers have to write reset_reg_val in the reset_reg
11204 * location in the same sequence in order to recover from a fatal
11207 uint8_t reg_array_cnt;
11210 * Lower 2 bits indicates address space location and upper 30 bits
11211 * indicates actual address.
11212 * A value of 0xFFFF-FFFF indicates this register does not exist.
11214 uint32_t reset_reg[16];
11215 /* Lower 2 bits indicates address space location. */
11216 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
11218 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
11220 * If value is 0, this register is located in PCIe config space.
11221 * Drivers have to map appropriate window to access this
11224 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
11227 * If value is 1, this register is located in GRC address space.
11228 * Drivers have to map appropriate window to access this
11231 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
11234 * If value is 2, this register is located in first BAR address
11235 * space. Drivers have to map appropriate window to access this
11238 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
11241 * If value is 3, this register is located in second BAR address
11242 * space. Drivers have to map appropriate window to access this
11245 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
11247 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
11248 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
11249 /* Upper 30bits of the register address. */
11250 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
11251 UINT32_C(0xfffffffc)
11252 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
11253 /* Value to be written in reset_reg to reset the controller. */
11254 uint32_t reset_reg_val[16];
11256 * This value is in units of 1msec.
11257 * Typical value would be 10 to indicate 10msec.
11258 * Some of the operations like Core reset require delay before
11259 * accessing PCIE MMIO register space.
11260 * If this value is non-zero, drivers have to wait for
11261 * this much time after writing reset_reg_val in reset_reg.
11263 uint8_t delay_after_reset[16];
11264 uint8_t unused_1[7];
11266 * This field is used in Output records to indicate that the output
11267 * is completely written to RAM. This field should be read as '1'
11268 * to indicate that the output has been completely written.
11269 * When writing a command completion or response to an internal
11270 * processor, the order of writes has to be such that this field
11274 } __attribute__((packed));
11276 /***********************
11277 * hwrm_func_vlan_qcfg *
11278 ***********************/
11281 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
11282 struct hwrm_func_vlan_qcfg_input {
11283 /* The HWRM command request type. */
11286 * The completion ring to send the completion event on. This should
11287 * be the NQ ID returned from the `nq_alloc` HWRM command.
11289 uint16_t cmpl_ring;
11291 * The sequence ID is used by the driver for tracking multiple
11292 * commands. This ID is treated as opaque data by the firmware and
11293 * the value is returned in the `hwrm_resp_hdr` upon completion.
11297 * The target ID of the command:
11298 * * 0x0-0xFFF8 - The function ID
11299 * * 0xFFF8-0xFFFE - Reserved for internal processors
11302 uint16_t target_id;
11304 * A physical address pointer pointing to a host buffer that the
11305 * command's response data will be written. This can be either a host
11306 * physical address (HPA) or a guest physical address (GPA) and must
11307 * point to a physically contiguous block of memory.
11309 uint64_t resp_addr;
11311 * Function ID of the function that is being
11313 * If set to 0xFF... (All Fs), then the configuration is
11314 * for the requesting function.
11317 uint8_t unused_0[6];
11318 } __attribute__((packed));
11320 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
11321 struct hwrm_func_vlan_qcfg_output {
11322 /* The specific error status for the command. */
11323 uint16_t error_code;
11324 /* The HWRM command request type. */
11326 /* The sequence ID from the original command. */
11328 /* The length of the response data in number of bytes. */
11331 /* S-TAG VLAN identifier configured for the function. */
11333 /* S-TAG PCP value configured for the function. */
11337 * S-TAG TPID value configured for the function. This field is specified in
11338 * network byte order.
11340 uint16_t stag_tpid;
11341 /* C-TAG VLAN identifier configured for the function. */
11343 /* C-TAG PCP value configured for the function. */
11347 * C-TAG TPID value configured for the function. This field is specified in
11348 * network byte order.
11350 uint16_t ctag_tpid;
11355 uint8_t unused_3[3];
11357 * This field is used in Output records to indicate that the output
11358 * is completely written to RAM. This field should be read as '1'
11359 * to indicate that the output has been completely written.
11360 * When writing a command completion or response to an internal processor,
11361 * the order of writes has to be such that this field is written last.
11364 } __attribute__((packed));
11366 /**********************
11367 * hwrm_func_vlan_cfg *
11368 **********************/
11371 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
11372 struct hwrm_func_vlan_cfg_input {
11373 /* The HWRM command request type. */
11376 * The completion ring to send the completion event on. This should
11377 * be the NQ ID returned from the `nq_alloc` HWRM command.
11379 uint16_t cmpl_ring;
11381 * The sequence ID is used by the driver for tracking multiple
11382 * commands. This ID is treated as opaque data by the firmware and
11383 * the value is returned in the `hwrm_resp_hdr` upon completion.
11387 * The target ID of the command:
11388 * * 0x0-0xFFF8 - The function ID
11389 * * 0xFFF8-0xFFFE - Reserved for internal processors
11392 uint16_t target_id;
11394 * A physical address pointer pointing to a host buffer that the
11395 * command's response data will be written. This can be either a host
11396 * physical address (HPA) or a guest physical address (GPA) and must
11397 * point to a physically contiguous block of memory.
11399 uint64_t resp_addr;
11401 * Function ID of the function that is being
11403 * If set to 0xFF... (All Fs), then the configuration is
11404 * for the requesting function.
11407 uint8_t unused_0[2];
11410 * This bit must be '1' for the stag_vid field to be
11413 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
11415 * This bit must be '1' for the ctag_vid field to be
11418 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
11420 * This bit must be '1' for the stag_pcp field to be
11423 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
11425 * This bit must be '1' for the ctag_pcp field to be
11428 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
11430 * This bit must be '1' for the stag_tpid field to be
11433 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
11435 * This bit must be '1' for the ctag_tpid field to be
11438 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
11439 /* S-TAG VLAN identifier configured for the function. */
11441 /* S-TAG PCP value configured for the function. */
11445 * S-TAG TPID value configured for the function. This field is specified in
11446 * network byte order.
11448 uint16_t stag_tpid;
11449 /* C-TAG VLAN identifier configured for the function. */
11451 /* C-TAG PCP value configured for the function. */
11455 * C-TAG TPID value configured for the function. This field is specified in
11456 * network byte order.
11458 uint16_t ctag_tpid;
11463 uint8_t unused_3[4];
11464 } __attribute__((packed));
11466 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
11467 struct hwrm_func_vlan_cfg_output {
11468 /* The specific error status for the command. */
11469 uint16_t error_code;
11470 /* The HWRM command request type. */
11472 /* The sequence ID from the original command. */
11474 /* The length of the response data in number of bytes. */
11476 uint8_t unused_0[7];
11478 * This field is used in Output records to indicate that the output
11479 * is completely written to RAM. This field should be read as '1'
11480 * to indicate that the output has been completely written.
11481 * When writing a command completion or response to an internal processor,
11482 * the order of writes has to be such that this field is written last.
11485 } __attribute__((packed));
11487 /*******************************
11488 * hwrm_func_vf_vnic_ids_query *
11489 *******************************/
11492 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
11493 struct hwrm_func_vf_vnic_ids_query_input {
11494 /* The HWRM command request type. */
11497 * The completion ring to send the completion event on. This should
11498 * be the NQ ID returned from the `nq_alloc` HWRM command.
11500 uint16_t cmpl_ring;
11502 * The sequence ID is used by the driver for tracking multiple
11503 * commands. This ID is treated as opaque data by the firmware and
11504 * the value is returned in the `hwrm_resp_hdr` upon completion.
11508 * The target ID of the command:
11509 * * 0x0-0xFFF8 - The function ID
11510 * * 0xFFF8-0xFFFE - Reserved for internal processors
11513 uint16_t target_id;
11515 * A physical address pointer pointing to a host buffer that the
11516 * command's response data will be written. This can be either a host
11517 * physical address (HPA) or a guest physical address (GPA) and must
11518 * point to a physically contiguous block of memory.
11520 uint64_t resp_addr;
11522 * This value is used to identify a Virtual Function (VF).
11523 * The scope of VF ID is local within a PF.
11526 uint8_t unused_0[2];
11527 /* Max number of vnic ids in vnic id table */
11528 uint32_t max_vnic_id_cnt;
11529 /* This is the address for VF VNIC ID table */
11530 uint64_t vnic_id_tbl_addr;
11531 } __attribute__((packed));
11533 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
11534 struct hwrm_func_vf_vnic_ids_query_output {
11535 /* The specific error status for the command. */
11536 uint16_t error_code;
11537 /* The HWRM command request type. */
11539 /* The sequence ID from the original command. */
11541 /* The length of the response data in number of bytes. */
11544 * Actual number of vnic ids
11546 * Each VNIC ID is written as a 32-bit number.
11548 uint32_t vnic_id_cnt;
11549 uint8_t unused_0[3];
11551 * This field is used in Output records to indicate that the output
11552 * is completely written to RAM. This field should be read as '1'
11553 * to indicate that the output has been completely written.
11554 * When writing a command completion or response to an internal processor,
11555 * the order of writes has to be such that this field is written last.
11558 } __attribute__((packed));
11560 /***********************
11561 * hwrm_func_vf_bw_cfg *
11562 ***********************/
11565 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
11566 struct hwrm_func_vf_bw_cfg_input {
11567 /* The HWRM command request type. */
11570 * The completion ring to send the completion event on. This should
11571 * be the NQ ID returned from the `nq_alloc` HWRM command.
11573 uint16_t cmpl_ring;
11575 * The sequence ID is used by the driver for tracking multiple
11576 * commands. This ID is treated as opaque data by the firmware and
11577 * the value is returned in the `hwrm_resp_hdr` upon completion.
11581 * The target ID of the command:
11582 * * 0x0-0xFFF8 - The function ID
11583 * * 0xFFF8-0xFFFE - Reserved for internal processors
11586 uint16_t target_id;
11588 * A physical address pointer pointing to a host buffer that the
11589 * command's response data will be written. This can be either a host
11590 * physical address (HPA) or a guest physical address (GPA) and must
11591 * point to a physically contiguous block of memory.
11593 uint64_t resp_addr;
11595 * The number of VF functions that are being configured.
11596 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
11599 uint16_t unused[3];
11600 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
11602 /* The physical VF id the adjustment will be made to. */
11603 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
11604 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
11606 * This field configures the rate scale percentage of the VF as specified
11607 * by the physical VF id.
11609 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
11610 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
11611 /* 0% of the max tx rate */
11612 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
11613 (UINT32_C(0x0) << 12)
11614 /* 6.66% of the max tx rate */
11615 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
11616 (UINT32_C(0x1) << 12)
11617 /* 13.33% of the max tx rate */
11618 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
11619 (UINT32_C(0x2) << 12)
11620 /* 20% of the max tx rate */
11621 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
11622 (UINT32_C(0x3) << 12)
11623 /* 26.66% of the max tx rate */
11624 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
11625 (UINT32_C(0x4) << 12)
11626 /* 33% of the max tx rate */
11627 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
11628 (UINT32_C(0x5) << 12)
11629 /* 40% of the max tx rate */
11630 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
11631 (UINT32_C(0x6) << 12)
11632 /* 46.66% of the max tx rate */
11633 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
11634 (UINT32_C(0x7) << 12)
11635 /* 53.33% of the max tx rate */
11636 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
11637 (UINT32_C(0x8) << 12)
11638 /* 60% of the max tx rate */
11639 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
11640 (UINT32_C(0x9) << 12)
11641 /* 66.66% of the max tx rate */
11642 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
11643 (UINT32_C(0xa) << 12)
11644 /* 53.33% of the max tx rate */
11645 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
11646 (UINT32_C(0xb) << 12)
11647 /* 80% of the max tx rate */
11648 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
11649 (UINT32_C(0xc) << 12)
11650 /* 86.66% of the max tx rate */
11651 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
11652 (UINT32_C(0xd) << 12)
11653 /* 93.33% of the max tx rate */
11654 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
11655 (UINT32_C(0xe) << 12)
11656 /* 100% of the max tx rate */
11657 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
11658 (UINT32_C(0xf) << 12)
11659 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
11660 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
11661 } __attribute__((packed));
11663 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
11664 struct hwrm_func_vf_bw_cfg_output {
11665 /* The specific error status for the command. */
11666 uint16_t error_code;
11667 /* The HWRM command request type. */
11669 /* The sequence ID from the original command. */
11671 /* The length of the response data in number of bytes. */
11673 uint8_t unused_0[7];
11675 * This field is used in Output records to indicate that the output
11676 * is completely written to RAM. This field should be read as '1'
11677 * to indicate that the output has been completely written.
11678 * When writing a command completion or response to an internal processor,
11679 * the order of writes has to be such that this field is written last.
11682 } __attribute__((packed));
11684 /************************
11685 * hwrm_func_vf_bw_qcfg *
11686 ************************/
11689 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
11690 struct hwrm_func_vf_bw_qcfg_input {
11691 /* The HWRM command request type. */
11694 * The completion ring to send the completion event on. This should
11695 * be the NQ ID returned from the `nq_alloc` HWRM command.
11697 uint16_t cmpl_ring;
11699 * The sequence ID is used by the driver for tracking multiple
11700 * commands. This ID is treated as opaque data by the firmware and
11701 * the value is returned in the `hwrm_resp_hdr` upon completion.
11705 * The target ID of the command:
11706 * * 0x0-0xFFF8 - The function ID
11707 * * 0xFFF8-0xFFFE - Reserved for internal processors
11710 uint16_t target_id;
11712 * A physical address pointer pointing to a host buffer that the
11713 * command's response data will be written. This can be either a host
11714 * physical address (HPA) or a guest physical address (GPA) and must
11715 * point to a physically contiguous block of memory.
11717 uint64_t resp_addr;
11719 * The number of VF functions that are being queried.
11720 * The inline response space allows the host to query up to 50 VFs'
11721 * rate scale percentage
11724 uint16_t unused[3];
11725 /* These 16-bit fields contain the VF fid */
11727 /* The physical VF id of interest */
11728 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
11729 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
11730 } __attribute__((packed));
11732 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
11733 struct hwrm_func_vf_bw_qcfg_output {
11734 /* The specific error status for the command. */
11735 uint16_t error_code;
11736 /* The HWRM command request type. */
11738 /* The sequence ID from the original command. */
11740 /* The length of the response data in number of bytes. */
11743 * The number of VF functions that are being queried.
11744 * The inline response space allows the host to query up to 50 VFs' rate
11748 uint16_t unused[3];
11749 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
11751 /* The physical VF id the adjustment will be made to. */
11752 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
11753 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
11755 * This field configures the rate scale percentage of the VF as specified
11756 * by the physical VF id.
11758 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
11759 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
11760 /* 0% of the max tx rate */
11761 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
11762 (UINT32_C(0x0) << 12)
11763 /* 6.66% of the max tx rate */
11764 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
11765 (UINT32_C(0x1) << 12)
11766 /* 13.33% of the max tx rate */
11767 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
11768 (UINT32_C(0x2) << 12)
11769 /* 20% of the max tx rate */
11770 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
11771 (UINT32_C(0x3) << 12)
11772 /* 26.66% of the max tx rate */
11773 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
11774 (UINT32_C(0x4) << 12)
11775 /* 33% of the max tx rate */
11776 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
11777 (UINT32_C(0x5) << 12)
11778 /* 40% of the max tx rate */
11779 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
11780 (UINT32_C(0x6) << 12)
11781 /* 46.66% of the max tx rate */
11782 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
11783 (UINT32_C(0x7) << 12)
11784 /* 53.33% of the max tx rate */
11785 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
11786 (UINT32_C(0x8) << 12)
11787 /* 60% of the max tx rate */
11788 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
11789 (UINT32_C(0x9) << 12)
11790 /* 66.66% of the max tx rate */
11791 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
11792 (UINT32_C(0xa) << 12)
11793 /* 53.33% of the max tx rate */
11794 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
11795 (UINT32_C(0xb) << 12)
11796 /* 80% of the max tx rate */
11797 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
11798 (UINT32_C(0xc) << 12)
11799 /* 86.66% of the max tx rate */
11800 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
11801 (UINT32_C(0xd) << 12)
11802 /* 93.33% of the max tx rate */
11803 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
11804 (UINT32_C(0xe) << 12)
11805 /* 100% of the max tx rate */
11806 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
11807 (UINT32_C(0xf) << 12)
11808 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
11809 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
11810 uint8_t unused_0[7];
11812 * This field is used in Output records to indicate that the output
11813 * is completely written to RAM. This field should be read as '1'
11814 * to indicate that the output has been completely written.
11815 * When writing a command completion or response to an internal processor,
11816 * the order of writes has to be such that this field is written last.
11819 } __attribute__((packed));
11821 /***************************
11822 * hwrm_func_drv_if_change *
11823 ***************************/
11826 /* hwrm_func_drv_if_change_input (size:192b/24B) */
11827 struct hwrm_func_drv_if_change_input {
11828 /* The HWRM command request type. */
11831 * The completion ring to send the completion event on. This should
11832 * be the NQ ID returned from the `nq_alloc` HWRM command.
11834 uint16_t cmpl_ring;
11836 * The sequence ID is used by the driver for tracking multiple
11837 * commands. This ID is treated as opaque data by the firmware and
11838 * the value is returned in the `hwrm_resp_hdr` upon completion.
11842 * The target ID of the command:
11843 * * 0x0-0xFFF8 - The function ID
11844 * * 0xFFF8-0xFFFE - Reserved for internal processors
11847 uint16_t target_id;
11849 * A physical address pointer pointing to a host buffer that the
11850 * command's response data will be written. This can be either a host
11851 * physical address (HPA) or a guest physical address (GPA) and must
11852 * point to a physically contiguous block of memory.
11854 uint64_t resp_addr;
11857 * When this bit is '1', the function driver is indicating
11858 * that the IF state is changing to UP state. The call should
11859 * be made at the beginning of the driver's open call before
11860 * resources are allocated. After making the call, the driver
11861 * should check the response to see if any resources may have
11862 * changed (see the response below). If the driver fails
11863 * the open call, the driver should make this call again with
11864 * this bit cleared to indicate that the IF state is not UP.
11865 * During the driver's close call when the IF state is changing
11866 * to DOWN, the driver should make this call with the bit cleared
11867 * after all resources have been freed.
11869 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
11871 } __attribute__((packed));
11873 /* hwrm_func_drv_if_change_output (size:128b/16B) */
11874 struct hwrm_func_drv_if_change_output {
11875 /* The specific error status for the command. */
11876 uint16_t error_code;
11877 /* The HWRM command request type. */
11879 /* The sequence ID from the original command. */
11881 /* The length of the response data in number of bytes. */
11885 * When this bit is '1', it indicates that the resources reserved
11886 * for this function may have changed. The driver should check
11887 * resource capabilities and reserve resources again before
11888 * allocating resources.
11890 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
11893 * When this bit is '1', it indicates that the firmware got changed / reset.
11894 * The driver should do complete re-initialization when that bit is set.
11896 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
11898 uint8_t unused_0[3];
11900 * This field is used in Output records to indicate that the output
11901 * is completely written to RAM. This field should be read as '1'
11902 * to indicate that the output has been completely written.
11903 * When writing a command completion or response to an internal processor,
11904 * the order of writes has to be such that this field is written last.
11907 } __attribute__((packed));
11909 /*********************
11910 * hwrm_port_phy_cfg *
11911 *********************/
11914 /* hwrm_port_phy_cfg_input (size:448b/56B) */
11915 struct hwrm_port_phy_cfg_input {
11916 /* The HWRM command request type. */
11919 * The completion ring to send the completion event on. This should
11920 * be the NQ ID returned from the `nq_alloc` HWRM command.
11922 uint16_t cmpl_ring;
11924 * The sequence ID is used by the driver for tracking multiple
11925 * commands. This ID is treated as opaque data by the firmware and
11926 * the value is returned in the `hwrm_resp_hdr` upon completion.
11930 * The target ID of the command:
11931 * * 0x0-0xFFF8 - The function ID
11932 * * 0xFFF8-0xFFFE - Reserved for internal processors
11935 uint16_t target_id;
11937 * A physical address pointer pointing to a host buffer that the
11938 * command's response data will be written. This can be either a host
11939 * physical address (HPA) or a guest physical address (GPA) and must
11940 * point to a physically contiguous block of memory.
11942 uint64_t resp_addr;
11945 * When this bit is set to '1', the PHY for the port shall
11948 * # If this bit is set to 1, then the HWRM shall reset the
11949 * PHY after applying PHY configuration changes specified
11951 * # In order to guarantee that PHY configuration changes
11952 * specified in this command take effect, the HWRM
11953 * client should set this flag to 1.
11954 * # If this bit is not set to 1, then the HWRM may reset
11955 * the PHY depending on the current PHY configuration and
11956 * settings specified in this command.
11958 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
11960 /* deprecated bit. Do not use!!! */
11961 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
11964 * When this bit is set to '1', the link shall be forced to
11965 * the force_link_speed value.
11967 * When this bit is set to '1', the HWRM client should
11968 * not enable any of the auto negotiation related
11969 * fields represented by auto_XXX fields in this command.
11970 * When this bit is set to '1' and the HWRM client has
11971 * enabled a auto_XXX field in this command, then the
11972 * HWRM shall ignore the enabled auto_XXX field.
11974 * When this bit is set to zero, the link
11975 * shall be allowed to autoneg.
11977 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
11980 * When this bit is set to '1', the auto-negotiation process
11981 * shall be restarted on the link.
11983 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
11986 * When this bit is set to '1', Energy Efficient Ethernet
11987 * (EEE) is requested to be enabled on this link.
11988 * If EEE is not supported on this port, then this flag
11989 * shall be ignored by the HWRM.
11991 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
11994 * When this bit is set to '1', Energy Efficient Ethernet
11995 * (EEE) is requested to be disabled on this link.
11996 * If EEE is not supported on this port, then this flag
11997 * shall be ignored by the HWRM.
11999 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
12002 * When this bit is set to '1' and EEE is enabled on this
12003 * link, then TX LPI is requested to be enabled on the link.
12004 * If EEE is not supported on this port, then this flag
12005 * shall be ignored by the HWRM.
12006 * If EEE is disabled on this port, then this flag shall be
12007 * ignored by the HWRM.
12009 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
12012 * When this bit is set to '1' and EEE is enabled on this
12013 * link, then TX LPI is requested to be disabled on the link.
12014 * If EEE is not supported on this port, then this flag
12015 * shall be ignored by the HWRM.
12016 * If EEE is disabled on this port, then this flag shall be
12017 * ignored by the HWRM.
12019 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
12022 * When set to 1, then the HWRM shall enable FEC autonegotitation
12023 * on this port if supported.
12024 * When set to 0, then this flag shall be ignored.
12025 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
12028 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
12031 * When set to 1, then the HWRM shall disable FEC autonegotiation
12032 * on this port if supported.
12033 * When set to 0, then this flag shall be ignored.
12034 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
12037 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
12040 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
12041 * on this port if supported.
12042 * When set to 0, then this flag shall be ignored.
12043 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
12046 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
12049 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
12050 * on this port if supported.
12051 * When set to 0, then this flag shall be ignored.
12052 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
12055 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
12058 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
12059 * on this port if supported.
12060 * When set to 0, then this flag shall be ignored.
12061 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
12064 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
12067 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
12068 * on this port if supported.
12069 * When set to 0, then this flag shall be ignored.
12070 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
12073 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
12076 * When this bit is set to '1', the link shall be forced to
12079 * # When this bit is set to '1", all other
12080 * command input settings related to the link speed shall
12082 * Once the link state is forced down, it can be
12083 * explicitly cleared from that state by setting this flag
12085 * # If this flag is set to '0', then the link shall be
12086 * cleared from forced down state if the link is in forced
12088 * There may be conditions (e.g. out-of-band or sideband
12089 * configuration changes for the link) outside the scope
12090 * of the HWRM implementation that may clear forced down
12093 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
12097 * This bit must be '1' for the auto_mode field to be
12100 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
12103 * This bit must be '1' for the auto_duplex field to be
12106 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
12109 * This bit must be '1' for the auto_pause field to be
12112 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
12115 * This bit must be '1' for the auto_link_speed field to be
12118 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
12121 * This bit must be '1' for the auto_link_speed_mask field to be
12124 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
12127 * This bit must be '1' for the wirespeed field to be
12130 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
12133 * This bit must be '1' for the lpbk field to be
12136 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
12139 * This bit must be '1' for the preemphasis field to be
12142 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
12145 * This bit must be '1' for the force_pause field to be
12148 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
12151 * This bit must be '1' for the eee_link_speed_mask field to be
12154 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
12157 * This bit must be '1' for the tx_lpi_timer field to be
12160 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
12162 /* Port ID of port that is to be configured. */
12165 * This is the speed that will be used if the force
12166 * bit is '1'. If unsupported speed is selected, an error
12167 * will be generated.
12169 uint16_t force_link_speed;
12170 /* 100Mb link speed */
12171 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
12172 /* 1Gb link speed */
12173 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
12174 /* 2Gb link speed */
12175 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
12176 /* 25Gb link speed */
12177 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
12178 /* 10Gb link speed */
12179 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
12180 /* 20Mb link speed */
12181 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
12182 /* 25Gb link speed */
12183 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
12184 /* 40Gb link speed */
12185 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
12186 /* 50Gb link speed */
12187 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
12188 /* 100Gb link speed */
12189 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
12190 /* 200Gb link speed */
12191 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
12192 /* 10Mb link speed */
12193 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
12194 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
12195 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
12197 * This value is used to identify what autoneg mode is
12198 * used when the link speed is not being forced.
12201 /* Disable autoneg or autoneg disabled. No speeds are selected. */
12202 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
12203 /* Select all possible speeds for autoneg mode. */
12204 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
12206 * Select only the auto_link_speed speed for autoneg mode. This mode has
12207 * been DEPRECATED. An HWRM client should not use this mode.
12209 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
12211 * Select the auto_link_speed or any speed below that speed for autoneg.
12212 * This mode has been DEPRECATED. An HWRM client should not use this mode.
12214 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
12216 * Select the speeds based on the corresponding link speed mask value
12217 * that is provided.
12219 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
12220 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
12221 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
12223 * This is the duplex setting that will be used if the autoneg_mode
12224 * is "one_speed" or "one_or_below".
12226 uint8_t auto_duplex;
12227 /* Half Duplex will be requested. */
12228 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
12229 /* Full duplex will be requested. */
12230 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
12231 /* Both Half and Full dupex will be requested. */
12232 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
12233 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
12234 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
12236 * This value is used to configure the pause that will be
12237 * used for autonegotiation.
12238 * Add text on the usage of auto_pause and force_pause.
12240 uint8_t auto_pause;
12242 * When this bit is '1', Generation of tx pause messages
12243 * has been requested. Disabled otherwise.
12245 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
12248 * When this bit is '1', Reception of rx pause messages
12249 * has been requested. Disabled otherwise.
12251 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
12254 * When set to 1, the advertisement of pause is enabled.
12256 * # When the auto_mode is not set to none and this flag is
12257 * set to 1, then the auto_pause bits on this port are being
12258 * advertised and autoneg pause results are being interpreted.
12259 * # When the auto_mode is not set to none and this
12260 * flag is set to 0, the pause is forced as indicated in
12261 * force_pause, and also advertised as auto_pause bits, but
12262 * the autoneg results are not interpreted since the pause
12263 * configuration is being forced.
12264 * # When the auto_mode is set to none and this flag is set to
12265 * 1, auto_pause bits should be ignored and should be set to 0.
12267 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
12271 * This is the speed that will be used if the autoneg_mode
12272 * is "one_speed" or "one_or_below". If an unsupported speed
12273 * is selected, an error will be generated.
12275 uint16_t auto_link_speed;
12276 /* 100Mb link speed */
12277 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
12278 /* 1Gb link speed */
12279 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
12280 /* 2Gb link speed */
12281 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
12282 /* 25Gb link speed */
12283 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
12284 /* 10Gb link speed */
12285 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
12286 /* 20Mb link speed */
12287 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
12288 /* 25Gb link speed */
12289 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
12290 /* 40Gb link speed */
12291 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
12292 /* 50Gb link speed */
12293 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
12294 /* 100Gb link speed */
12295 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
12296 /* 200Gb link speed */
12297 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
12298 /* 10Mb link speed */
12299 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
12300 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
12301 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
12303 * This is a mask of link speeds that will be used if
12304 * autoneg_mode is "mask". If unsupported speed is enabled
12305 * an error will be generated.
12307 uint16_t auto_link_speed_mask;
12308 /* 100Mb link speed (Half-duplex) */
12309 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
12311 /* 100Mb link speed (Full-duplex) */
12312 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
12314 /* 1Gb link speed (Half-duplex) */
12315 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
12317 /* 1Gb link speed (Full-duplex) */
12318 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
12320 /* 2Gb link speed */
12321 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
12323 /* 25Gb link speed */
12324 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
12326 /* 10Gb link speed */
12327 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
12329 /* 20Gb link speed */
12330 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
12332 /* 25Gb link speed */
12333 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
12335 /* 40Gb link speed */
12336 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
12338 /* 50Gb link speed */
12339 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
12341 /* 100Gb link speed */
12342 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
12344 /* 10Mb link speed (Half-duplex) */
12345 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
12347 /* 10Mb link speed (Full-duplex) */
12348 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
12350 /* 200Gb link speed */
12351 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
12353 /* This value controls the wirespeed feature. */
12355 /* Wirespeed feature is disabled. */
12356 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
12357 /* Wirespeed feature is enabled. */
12358 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
12359 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
12360 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
12361 /* This value controls the loopback setting for the PHY. */
12363 /* No loopback is selected. Normal operation. */
12364 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
12366 * The HW will be configured with local loopback such that
12367 * host data is sent back to the host without modification.
12369 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
12371 * The HW will be configured with remote loopback such that
12372 * port logic will send packets back out the transmitter that
12375 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
12377 * The HW will be configured with external loopback such that
12378 * host data is sent on the trasmitter and based on the external
12379 * loopback connection the data will be received without modification.
12381 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
12382 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
12383 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
12385 * This value is used to configure the pause that will be
12386 * used for force mode.
12388 uint8_t force_pause;
12390 * When this bit is '1', Generation of tx pause messages
12391 * is supported. Disabled otherwise.
12393 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
12395 * When this bit is '1', Reception of rx pause messages
12396 * is supported. Disabled otherwise.
12398 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
12401 * This value controls the pre-emphasis to be used for the
12402 * link. Driver should not set this value (use
12403 * enable.preemphasis = 0) unless driver is sure of setting.
12404 * Normally HWRM FW will determine proper pre-emphasis.
12406 uint32_t preemphasis;
12408 * Setting for link speed mask that is used to
12409 * advertise speeds during autonegotiation when EEE is enabled.
12410 * This field is valid only when EEE is enabled.
12411 * The speeds specified in this field shall be a subset of
12412 * speeds specified in auto_link_speed_mask.
12413 * If EEE is enabled,then at least one speed shall be provided
12416 uint16_t eee_link_speed_mask;
12418 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
12420 /* 100Mb link speed (Full-duplex) */
12421 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
12424 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
12426 /* 1Gb link speed (Full-duplex) */
12427 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
12430 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
12433 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
12435 /* 10Gb link speed */
12436 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
12438 uint8_t unused_2[2];
12440 * Reuested setting of TX LPI timer in microseconds.
12441 * This field is valid only when EEE is enabled and TX LPI is
12444 uint32_t tx_lpi_timer;
12445 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
12446 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
12448 } __attribute__((packed));
12450 /* hwrm_port_phy_cfg_output (size:128b/16B) */
12451 struct hwrm_port_phy_cfg_output {
12452 /* The specific error status for the command. */
12453 uint16_t error_code;
12454 /* The HWRM command request type. */
12456 /* The sequence ID from the original command. */
12458 /* The length of the response data in number of bytes. */
12460 uint8_t unused_0[7];
12462 * This field is used in Output records to indicate that the output
12463 * is completely written to RAM. This field should be read as '1'
12464 * to indicate that the output has been completely written.
12465 * When writing a command completion or response to an internal processor,
12466 * the order of writes has to be such that this field is written last.
12469 } __attribute__((packed));
12471 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
12472 struct hwrm_port_phy_cfg_cmd_err {
12474 * command specific error codes that goes to
12475 * the cmd_err field in Common HWRM Error Response.
12478 /* Unknown error */
12479 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
12480 /* Unable to complete operation due to invalid speed */
12481 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
12483 * retry the command since the phy is not ready.
12484 * retry count is returned in opaque_0.
12485 * This is only valid for the first command and
12486 * this value will not change for successive calls.
12487 * but if a 0 is returned at any time then this should
12488 * be treated as an un recoverable failure,
12490 * retry interval in milli seconds is returned in opaque_1.
12491 * This specifies the time that user should wait before
12492 * issuing the next port_phy_cfg command.
12494 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
12495 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
12496 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
12497 uint8_t unused_0[7];
12498 } __attribute__((packed));
12500 /**********************
12501 * hwrm_port_phy_qcfg *
12502 **********************/
12505 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
12506 struct hwrm_port_phy_qcfg_input {
12507 /* The HWRM command request type. */
12510 * The completion ring to send the completion event on. This should
12511 * be the NQ ID returned from the `nq_alloc` HWRM command.
12513 uint16_t cmpl_ring;
12515 * The sequence ID is used by the driver for tracking multiple
12516 * commands. This ID is treated as opaque data by the firmware and
12517 * the value is returned in the `hwrm_resp_hdr` upon completion.
12521 * The target ID of the command:
12522 * * 0x0-0xFFF8 - The function ID
12523 * * 0xFFF8-0xFFFE - Reserved for internal processors
12526 uint16_t target_id;
12528 * A physical address pointer pointing to a host buffer that the
12529 * command's response data will be written. This can be either a host
12530 * physical address (HPA) or a guest physical address (GPA) and must
12531 * point to a physically contiguous block of memory.
12533 uint64_t resp_addr;
12534 /* Port ID of port that is to be queried. */
12536 uint8_t unused_0[6];
12537 } __attribute__((packed));
12539 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
12540 struct hwrm_port_phy_qcfg_output {
12541 /* The specific error status for the command. */
12542 uint16_t error_code;
12543 /* The HWRM command request type. */
12545 /* The sequence ID from the original command. */
12547 /* The length of the response data in number of bytes. */
12549 /* This value indicates the current link status. */
12551 /* There is no link or cable detected. */
12552 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
12553 /* There is no link, but a cable has been detected. */
12554 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
12555 /* There is a link. */
12556 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
12557 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
12558 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
12560 /* This value indicates the current link speed of the connection. */
12561 uint16_t link_speed;
12562 /* 100Mb link speed */
12563 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
12564 /* 1Gb link speed */
12565 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
12566 /* 2Gb link speed */
12567 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
12568 /* 25Gb link speed */
12569 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
12570 /* 10Gb link speed */
12571 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
12572 /* 20Mb link speed */
12573 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
12574 /* 25Gb link speed */
12575 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
12576 /* 40Gb link speed */
12577 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
12578 /* 50Gb link speed */
12579 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
12580 /* 100Gb link speed */
12581 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
12582 /* 200Gb link speed */
12583 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
12584 /* 10Mb link speed */
12585 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
12586 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
12587 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
12589 * This value is indicates the duplex of the current
12592 uint8_t duplex_cfg;
12593 /* Half Duplex connection. */
12594 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
12595 /* Full duplex connection. */
12596 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
12597 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
12598 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
12600 * This value is used to indicate the current
12601 * pause configuration. When autoneg is enabled, this value
12602 * represents the autoneg results of pause configuration.
12606 * When this bit is '1', Generation of tx pause messages
12607 * is supported. Disabled otherwise.
12609 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
12611 * When this bit is '1', Reception of rx pause messages
12612 * is supported. Disabled otherwise.
12614 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
12616 * The supported speeds for the port. This is a bit mask.
12617 * For each speed that is supported, the corrresponding
12618 * bit will be set to '1'.
12620 uint16_t support_speeds;
12621 /* 100Mb link speed (Half-duplex) */
12622 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
12624 /* 100Mb link speed (Full-duplex) */
12625 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
12627 /* 1Gb link speed (Half-duplex) */
12628 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
12630 /* 1Gb link speed (Full-duplex) */
12631 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
12633 /* 2Gb link speed */
12634 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
12636 /* 25Gb link speed */
12637 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
12639 /* 10Gb link speed */
12640 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
12642 /* 20Gb link speed */
12643 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
12645 /* 25Gb link speed */
12646 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
12648 /* 40Gb link speed */
12649 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
12651 /* 50Gb link speed */
12652 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
12654 /* 100Gb link speed */
12655 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
12657 /* 10Mb link speed (Half-duplex) */
12658 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
12660 /* 10Mb link speed (Full-duplex) */
12661 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
12663 /* 200Gb link speed */
12664 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
12667 * Current setting of forced link speed.
12668 * When the link speed is not being forced, this
12669 * value shall be set to 0.
12671 uint16_t force_link_speed;
12672 /* 100Mb link speed */
12673 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
12674 /* 1Gb link speed */
12675 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
12676 /* 2Gb link speed */
12677 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
12678 /* 25Gb link speed */
12679 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
12680 /* 10Gb link speed */
12681 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
12682 /* 20Mb link speed */
12683 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
12684 /* 25Gb link speed */
12685 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
12686 /* 40Gb link speed */
12687 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
12689 /* 50Gb link speed */
12690 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
12692 /* 100Gb link speed */
12693 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
12695 /* 200Gb link speed */
12696 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
12698 /* 10Mb link speed */
12699 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
12701 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
12702 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
12703 /* Current setting of auto negotiation mode. */
12705 /* Disable autoneg or autoneg disabled. No speeds are selected. */
12706 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
12707 /* Select all possible speeds for autoneg mode. */
12708 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
12710 * Select only the auto_link_speed speed for autoneg mode. This mode has
12711 * been DEPRECATED. An HWRM client should not use this mode.
12713 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
12715 * Select the auto_link_speed or any speed below that speed for autoneg.
12716 * This mode has been DEPRECATED. An HWRM client should not use this mode.
12718 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
12720 * Select the speeds based on the corresponding link speed mask value
12721 * that is provided.
12723 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
12724 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
12725 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
12727 * Current setting of pause autonegotiation.
12728 * Move autoneg_pause flag here.
12730 uint8_t auto_pause;
12732 * When this bit is '1', Generation of tx pause messages
12733 * has been requested. Disabled otherwise.
12735 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
12738 * When this bit is '1', Reception of rx pause messages
12739 * has been requested. Disabled otherwise.
12741 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
12744 * When set to 1, the advertisement of pause is enabled.
12746 * # When the auto_mode is not set to none and this flag is
12747 * set to 1, then the auto_pause bits on this port are being
12748 * advertised and autoneg pause results are being interpreted.
12749 * # When the auto_mode is not set to none and this
12750 * flag is set to 0, the pause is forced as indicated in
12751 * force_pause, and also advertised as auto_pause bits, but
12752 * the autoneg results are not interpreted since the pause
12753 * configuration is being forced.
12754 * # When the auto_mode is set to none and this flag is set to
12755 * 1, auto_pause bits should be ignored and should be set to 0.
12757 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
12760 * Current setting for auto_link_speed. This field is only
12761 * valid when auto_mode is set to "one_speed" or "one_or_below".
12763 uint16_t auto_link_speed;
12764 /* 100Mb link speed */
12765 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
12766 /* 1Gb link speed */
12767 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
12768 /* 2Gb link speed */
12769 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
12770 /* 25Gb link speed */
12771 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
12772 /* 10Gb link speed */
12773 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
12774 /* 20Mb link speed */
12775 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
12776 /* 25Gb link speed */
12777 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
12778 /* 40Gb link speed */
12779 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
12780 /* 50Gb link speed */
12781 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
12782 /* 100Gb link speed */
12783 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
12784 /* 200Gb link speed */
12785 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
12786 /* 10Mb link speed */
12787 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
12789 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
12790 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
12792 * Current setting for auto_link_speed_mask that is used to
12793 * advertise speeds during autonegotiation.
12794 * This field is only valid when auto_mode is set to "mask".
12795 * The speeds specified in this field shall be a subset of
12796 * supported speeds on this port.
12798 uint16_t auto_link_speed_mask;
12799 /* 100Mb link speed (Half-duplex) */
12800 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
12802 /* 100Mb link speed (Full-duplex) */
12803 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
12805 /* 1Gb link speed (Half-duplex) */
12806 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
12808 /* 1Gb link speed (Full-duplex) */
12809 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
12811 /* 2Gb link speed */
12812 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
12814 /* 25Gb link speed */
12815 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
12817 /* 10Gb link speed */
12818 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
12820 /* 20Gb link speed */
12821 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
12823 /* 25Gb link speed */
12824 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
12826 /* 40Gb link speed */
12827 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
12829 /* 50Gb link speed */
12830 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
12832 /* 100Gb link speed */
12833 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
12835 /* 10Mb link speed (Half-duplex) */
12836 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
12838 /* 10Mb link speed (Full-duplex) */
12839 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
12841 /* 200Gb link speed */
12842 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
12844 /* Current setting for wirespeed. */
12846 /* Wirespeed feature is disabled. */
12847 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
12848 /* Wirespeed feature is enabled. */
12849 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
12850 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
12851 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
12852 /* Current setting for loopback. */
12854 /* No loopback is selected. Normal operation. */
12855 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
12857 * The HW will be configured with local loopback such that
12858 * host data is sent back to the host without modification.
12860 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
12862 * The HW will be configured with remote loopback such that
12863 * port logic will send packets back out the transmitter that
12866 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
12868 * The HW will be configured with external loopback such that
12869 * host data is sent on the trasmitter and based on the external
12870 * loopback connection the data will be received without modification.
12872 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
12873 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
12874 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
12876 * Current setting of forced pause.
12877 * When the pause configuration is not being forced, then
12878 * this value shall be set to 0.
12880 uint8_t force_pause;
12882 * When this bit is '1', Generation of tx pause messages
12883 * is supported. Disabled otherwise.
12885 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
12887 * When this bit is '1', Reception of rx pause messages
12888 * is supported. Disabled otherwise.
12890 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
12892 * This value indicates the current status of the optics module on
12895 uint8_t module_status;
12896 /* Module is inserted and accepted */
12897 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
12899 /* Module is rejected and transmit side Laser is disabled. */
12900 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
12902 /* Module mismatch warning. */
12903 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
12905 /* Module is rejected and powered down. */
12906 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
12908 /* Module is not inserted. */
12909 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
12911 /* Module status is not applicable. */
12912 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
12914 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
12915 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
12916 /* Current setting for preemphasis. */
12917 uint32_t preemphasis;
12918 /* This field represents the major version of the PHY. */
12920 /* This field represents the minor version of the PHY. */
12922 /* This field represents the build version of the PHY. */
12924 /* This value represents a PHY type. */
12927 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
12930 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
12932 /* BASE-KR4 (Deprecated) */
12933 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
12936 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
12939 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
12941 /* BASE-KR2 (Deprecated) */
12942 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
12945 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
12948 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
12951 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
12953 /* EEE capable BASE-T */
12954 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
12956 /* SGMII connected external PHY */
12957 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
12959 /* 25G_BASECR_CA_L */
12960 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
12962 /* 25G_BASECR_CA_S */
12963 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
12965 /* 25G_BASECR_CA_N */
12966 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
12969 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
12972 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
12975 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
12978 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
12981 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
12983 /* 100G_BASESR10 */
12984 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
12987 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
12990 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
12993 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
12996 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
12998 /* 40G_ACTIVE_CABLE */
12999 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
13002 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
13005 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
13008 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
13011 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
13014 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
13017 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
13020 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
13022 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
13023 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
13024 /* This value represents a media type. */
13025 uint8_t media_type;
13027 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
13029 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
13030 /* Direct Attached Copper */
13031 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
13033 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
13034 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
13035 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
13036 /* This value represents a transceiver type. */
13037 uint8_t xcvr_pkg_type;
13038 /* PHY and MAC are in the same package */
13039 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
13041 /* PHY and MAC are in different packages */
13042 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
13044 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
13045 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
13046 uint8_t eee_config_phy_addr;
13047 /* This field represents PHY address. */
13048 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
13050 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
13052 * This field represents flags related to EEE configuration.
13053 * These EEE configuration flags are valid only when the
13054 * auto_mode is not set to none (in other words autonegotiation
13057 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
13059 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
13061 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
13062 * Speeds for autoneg with EEE mode enabled
13063 * are based on eee_link_speed_mask.
13065 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
13068 * This flag is valid only when eee_enabled is set to 1.
13070 * # If eee_enabled is set to 0, then EEE mode is disabled
13071 * and this flag shall be ignored.
13072 * # If eee_enabled is set to 1 and this flag is set to 1,
13073 * then Energy Efficient Ethernet (EEE) mode is enabled
13075 * # If eee_enabled is set to 1 and this flag is set to 0,
13076 * then Energy Efficient Ethernet (EEE) mode is enabled
13077 * but is currently not in use.
13079 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
13082 * This flag is valid only when eee_enabled is set to 1.
13084 * # If eee_enabled is set to 0, then EEE mode is disabled
13085 * and this flag shall be ignored.
13086 * # If eee_enabled is set to 1 and this flag is set to 1,
13087 * then Energy Efficient Ethernet (EEE) mode is enabled
13088 * and TX LPI is enabled.
13089 * # If eee_enabled is set to 1 and this flag is set to 0,
13090 * then Energy Efficient Ethernet (EEE) mode is enabled
13091 * but TX LPI is disabled.
13093 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
13096 * When set to 1, the parallel detection is used to determine
13097 * the speed of the link partner.
13099 * Parallel detection is used when a autonegotiation capable
13100 * device is connected to a link parter that is not capable
13101 * of autonegotiation.
13103 uint8_t parallel_detect;
13105 * When set to 1, the parallel detection is used to determine
13106 * the speed of the link partner.
13108 * Parallel detection is used when a autonegotiation capable
13109 * device is connected to a link parter that is not capable
13110 * of autonegotiation.
13112 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
13114 * The advertised speeds for the port by the link partner.
13115 * Each advertised speed will be set to '1'.
13117 uint16_t link_partner_adv_speeds;
13118 /* 100Mb link speed (Half-duplex) */
13119 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
13121 /* 100Mb link speed (Full-duplex) */
13122 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
13124 /* 1Gb link speed (Half-duplex) */
13125 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
13127 /* 1Gb link speed (Full-duplex) */
13128 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
13130 /* 2Gb link speed */
13131 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
13133 /* 25Gb link speed */
13134 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
13136 /* 10Gb link speed */
13137 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
13139 /* 20Gb link speed */
13140 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
13142 /* 25Gb link speed */
13143 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
13145 /* 40Gb link speed */
13146 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
13148 /* 50Gb link speed */
13149 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
13151 /* 100Gb link speed */
13152 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
13154 /* 10Mb link speed (Half-duplex) */
13155 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
13157 /* 10Mb link speed (Full-duplex) */
13158 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
13161 * The advertised autoneg for the port by the link partner.
13162 * This field is deprecated and should be set to 0.
13164 uint8_t link_partner_adv_auto_mode;
13165 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13166 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
13168 /* Select all possible speeds for autoneg mode. */
13169 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
13172 * Select only the auto_link_speed speed for autoneg mode. This mode has
13173 * been DEPRECATED. An HWRM client should not use this mode.
13175 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
13178 * Select the auto_link_speed or any speed below that speed for autoneg.
13179 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13181 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
13184 * Select the speeds based on the corresponding link speed mask value
13185 * that is provided.
13187 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
13189 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
13190 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
13191 /* The advertised pause settings on the port by the link partner. */
13192 uint8_t link_partner_adv_pause;
13194 * When this bit is '1', Generation of tx pause messages
13195 * is supported. Disabled otherwise.
13197 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
13200 * When this bit is '1', Reception of rx pause messages
13201 * is supported. Disabled otherwise.
13203 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
13206 * Current setting for link speed mask that is used to
13207 * advertise speeds during autonegotiation when EEE is enabled.
13208 * This field is valid only when eee_enabled flags is set to 1.
13209 * The speeds specified in this field shall be a subset of
13210 * speeds specified in auto_link_speed_mask.
13212 uint16_t adv_eee_link_speed_mask;
13214 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
13216 /* 100Mb link speed (Full-duplex) */
13217 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
13220 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
13222 /* 1Gb link speed (Full-duplex) */
13223 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
13226 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
13229 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
13231 /* 10Gb link speed */
13232 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
13235 * Current setting for link speed mask that is advertised by
13236 * the link partner when EEE is enabled.
13237 * This field is valid only when eee_enabled flags is set to 1.
13239 uint16_t link_partner_adv_eee_link_speed_mask;
13241 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
13243 /* 100Mb link speed (Full-duplex) */
13244 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
13247 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
13249 /* 1Gb link speed (Full-duplex) */
13250 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
13253 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
13256 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
13258 /* 10Gb link speed */
13259 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
13261 uint32_t xcvr_identifier_type_tx_lpi_timer;
13263 * Current setting of TX LPI timer in microseconds.
13264 * This field is valid only when_eee_enabled flag is set to 1
13265 * and tx_lpi_enabled is set to 1.
13267 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
13269 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
13270 /* This value represents transceiver identifier type. */
13271 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
13272 UINT32_C(0xff000000)
13273 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
13275 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
13276 (UINT32_C(0x0) << 24)
13277 /* SFP/SFP+/SFP28 */
13278 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
13279 (UINT32_C(0x3) << 24)
13281 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
13282 (UINT32_C(0xc) << 24)
13284 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
13285 (UINT32_C(0xd) << 24)
13287 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
13288 (UINT32_C(0x11) << 24)
13289 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
13290 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
13292 * This value represents the current configuration of
13293 * Forward Error Correction (FEC) on the port.
13297 * When set to 1, then FEC is not supported on this port. If this flag
13298 * is set to 1, then all other FEC configuration flags shall be ignored.
13299 * When set to 0, then FEC is supported as indicated by other
13300 * configuration flags.
13301 * If no cable is attached and the HWRM does not yet know the FEC
13302 * capability, then the HWRM shall set this flag to 1 when reporting
13305 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
13308 * When set to 1, then FEC autonegotiation is supported on this port.
13309 * When set to 0, then FEC autonegotiation is not supported on this port.
13311 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
13314 * When set to 1, then FEC autonegotiation is enabled on this port.
13315 * When set to 0, then FEC autonegotiation is disabled if supported.
13316 * This flag should be ignored if FEC autonegotiation is not supported on this port.
13318 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
13321 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
13322 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
13324 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
13327 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
13328 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
13329 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
13331 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
13334 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
13335 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
13337 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
13340 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
13341 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
13342 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
13344 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
13347 * This value is indicates the duplex of the current
13348 * connection state.
13350 uint8_t duplex_state;
13351 /* Half Duplex connection. */
13352 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
13353 /* Full duplex connection. */
13354 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
13355 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
13356 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
13357 /* Option flags fields. */
13358 uint8_t option_flags;
13359 /* When this bit is '1', Media auto detect is enabled. */
13360 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
13363 * Up to 16 bytes of null padded ASCII string representing
13365 * If the string is set to null, then the vendor name is not
13368 char phy_vendor_name[16];
13370 * Up to 16 bytes of null padded ASCII string that
13371 * identifies vendor specific part number of the PHY.
13372 * If the string is set to null, then the vendor specific
13373 * part number is not available.
13375 char phy_vendor_partnumber[16];
13376 uint8_t unused_2[7];
13378 * This field is used in Output records to indicate that the output
13379 * is completely written to RAM. This field should be read as '1'
13380 * to indicate that the output has been completely written.
13381 * When writing a command completion or response to an internal processor,
13382 * the order of writes has to be such that this field is written last.
13385 } __attribute__((packed));
13387 /*********************
13388 * hwrm_port_mac_cfg *
13389 *********************/
13392 /* hwrm_port_mac_cfg_input (size:320b/40B) */
13393 struct hwrm_port_mac_cfg_input {
13394 /* The HWRM command request type. */
13397 * The completion ring to send the completion event on. This should
13398 * be the NQ ID returned from the `nq_alloc` HWRM command.
13400 uint16_t cmpl_ring;
13402 * The sequence ID is used by the driver for tracking multiple
13403 * commands. This ID is treated as opaque data by the firmware and
13404 * the value is returned in the `hwrm_resp_hdr` upon completion.
13408 * The target ID of the command:
13409 * * 0x0-0xFFF8 - The function ID
13410 * * 0xFFF8-0xFFFE - Reserved for internal processors
13413 uint16_t target_id;
13415 * A physical address pointer pointing to a host buffer that the
13416 * command's response data will be written. This can be either a host
13417 * physical address (HPA) or a guest physical address (GPA) and must
13418 * point to a physically contiguous block of memory.
13420 uint64_t resp_addr;
13422 * In this field, there are a number of CoS mappings related flags
13423 * that are used to configure CoS mappings and their corresponding
13424 * priorities in the hardware.
13425 * For the priorities of CoS mappings, the HWRM uses the following
13426 * priority order (high to low) by default:
13429 * # tunnel_vlan_pri
13432 * A subset of CoS mappings can be enabled.
13433 * If a priority is not specified for an enabled CoS mapping, the
13434 * priority will be assigned in the above order for the enabled CoS
13435 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
13436 * enabled and their priorities are not specified, the following
13437 * priority order (high to low) will be used by the HWRM:
13442 * vlan_pri CoS mapping together with default CoS with lower priority
13443 * are enabled by default by the HWRM.
13447 * When this bit is '1', this command will configure
13448 * the MAC to match the current link state of the PHY.
13449 * If the link is not established on the PHY, then this
13450 * bit has no effect.
13452 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
13455 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
13456 * is requested to be enabled.
13458 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
13461 * When this bit is set to '1', tunnel VLAN PRI field to
13462 * CoS mapping is requested to be enabled.
13464 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
13467 * When this bit is set to '1', the IP DSCP to CoS mapping is
13468 * requested to be enabled.
13470 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
13473 * When this bit is '1', the HWRM is requested to
13474 * enable timestamp capture capability on the receive side
13477 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
13480 * When this bit is '1', the HWRM is requested to
13481 * disable timestamp capture capability on the receive side
13484 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
13487 * When this bit is '1', the HWRM is requested to
13488 * enable timestamp capture capability on the transmit side
13491 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
13494 * When this bit is '1', the HWRM is requested to
13495 * disable timestamp capture capability on the transmit side
13498 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
13501 * When this bit is '1', the Out-Of-Box WoL is requested to
13502 * be enabled on this port.
13504 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
13507 * When this bit is '1', the the Out-Of-Box WoL is requested to
13508 * be disabled on this port.
13510 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
13513 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
13514 * is requested to be disabled.
13516 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
13519 * When this bit is set to '1', tunnel VLAN PRI field to
13520 * CoS mapping is requested to be disabled.
13522 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
13525 * When this bit is set to '1', the IP DSCP to CoS mapping is
13526 * requested to be disabled.
13528 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
13532 * This bit must be '1' for the ipg field to be
13535 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
13538 * This bit must be '1' for the lpbk field to be
13541 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
13544 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
13547 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
13550 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
13553 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
13556 * This bit must be '1' for the dscp2cos_map_pri field to be
13559 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
13562 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
13565 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
13568 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
13571 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
13574 * This bit must be '1' for the cos_field_cfg field to be
13577 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
13579 /* Port ID of port that is to be configured. */
13582 * This value is used to configure the minimum IPG that will
13583 * be sent between packets by this port.
13586 /* This value controls the loopback setting for the MAC. */
13588 /* No loopback is selected. Normal operation. */
13589 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13591 * The HW will be configured with local loopback such that
13592 * host data is sent back to the host without modification.
13594 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13596 * The HW will be configured with remote loopback such that
13597 * port logic will send packets back out the transmitter that
13600 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13601 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
13602 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
13604 * This value controls the priority setting of VLAN PRI to CoS
13605 * mapping based on VLAN Tags of inner packet headers of
13606 * tunneled packets or packet headers of non-tunneled packets.
13608 * # Each XXX_pri variable shall have a unique priority value
13609 * when it is being specified.
13610 * # When comparing priorities of mappings, higher value
13611 * indicates higher priority.
13612 * For example, a value of 0-3 is returned where 0 is being
13613 * the lowest priority and 3 is being the highest priority.
13615 uint8_t vlan_pri2cos_map_pri;
13616 /* Reserved field. */
13619 * This value controls the priority setting of VLAN PRI to CoS
13620 * mapping based on VLAN Tags of tunneled header.
13621 * This mapping only applies when tunneled headers
13624 * # Each XXX_pri variable shall have a unique priority value
13625 * when it is being specified.
13626 * # When comparing priorities of mappings, higher value
13627 * indicates higher priority.
13628 * For example, a value of 0-3 is returned where 0 is being
13629 * the lowest priority and 3 is being the highest priority.
13631 uint8_t tunnel_pri2cos_map_pri;
13633 * This value controls the priority setting of IP DSCP to CoS
13634 * mapping based on inner IP header of tunneled packets or
13635 * IP header of non-tunneled packets.
13637 * # Each XXX_pri variable shall have a unique priority value
13638 * when it is being specified.
13639 * # When comparing priorities of mappings, higher value
13640 * indicates higher priority.
13641 * For example, a value of 0-3 is returned where 0 is being
13642 * the lowest priority and 3 is being the highest priority.
13644 uint8_t dscp2pri_map_pri;
13646 * This is a 16-bit bit mask that is used to request a
13647 * specific configuration of time stamp capture of PTP messages
13648 * on the receive side of this port.
13649 * This field shall be ignored if the ptp_rx_ts_capture_enable
13650 * flag is not set in this command.
13651 * Otherwise, if bit 'i' is set, then the HWRM is being
13652 * requested to configure the receive side of the port to
13653 * capture the time stamp of every received PTP message
13654 * with messageType field value set to i.
13656 uint16_t rx_ts_capture_ptp_msg_type;
13658 * This is a 16-bit bit mask that is used to request a
13659 * specific configuration of time stamp capture of PTP messages
13660 * on the transmit side of this port.
13661 * This field shall be ignored if the ptp_tx_ts_capture_enable
13662 * flag is not set in this command.
13663 * Otherwise, if bit 'i' is set, then the HWRM is being
13664 * requested to configure the transmit sied of the port to
13665 * capture the time stamp of every transmitted PTP message
13666 * with messageType field value set to i.
13668 uint16_t tx_ts_capture_ptp_msg_type;
13669 /* Configuration of CoS fields. */
13670 uint8_t cos_field_cfg;
13672 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
13675 * This field is used to specify selection of VLAN PRI value
13676 * based on whether one or two VLAN Tags are present in
13677 * the inner packet headers of tunneled packets or
13678 * non-tunneled packets.
13679 * This field is valid only if inner VLAN PRI to CoS mapping
13681 * If VLAN PRI to CoS mapping is not enabled, then this
13682 * field shall be ignored.
13684 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
13686 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
13689 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13690 * present in the inner packet headers
13692 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
13693 (UINT32_C(0x0) << 1)
13695 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13696 * present in the inner packet headers.
13697 * No VLAN PRI shall be selected for this configuration
13698 * if only one VLAN Tag is present in the inner
13701 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
13702 (UINT32_C(0x1) << 1)
13704 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13705 * are present in the inner packet headers
13707 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
13708 (UINT32_C(0x2) << 1)
13710 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
13711 (UINT32_C(0x3) << 1)
13712 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
13713 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
13715 * This field is used to specify selection of tunnel VLAN
13716 * PRI value based on whether one or two VLAN Tags are
13717 * present in tunnel headers.
13718 * This field is valid only if tunnel VLAN PRI to CoS mapping
13720 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
13721 * field shall be ignored.
13723 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
13725 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
13728 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
13729 * present in the tunnel packet headers
13731 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
13732 (UINT32_C(0x0) << 3)
13734 * Select outer VLAN Tag PRI when 2 VLAN Tags are
13735 * present in the tunnel packet headers.
13736 * No tunnel VLAN PRI shall be selected for this
13737 * configuration if only one VLAN Tag is present in
13738 * the tunnel packet headers.
13740 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
13741 (UINT32_C(0x1) << 3)
13743 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
13744 * are present in the tunnel packet headers
13746 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
13747 (UINT32_C(0x2) << 3)
13749 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
13750 (UINT32_C(0x3) << 3)
13751 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
13752 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
13754 * This field shall be used to provide default CoS value
13755 * that has been configured on this port.
13756 * This field is valid only if default CoS mapping
13758 * If default CoS mapping is not enabled, then this
13759 * field shall be ignored.
13761 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
13763 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
13765 uint8_t unused_0[3];
13766 } __attribute__((packed));
13768 /* hwrm_port_mac_cfg_output (size:128b/16B) */
13769 struct hwrm_port_mac_cfg_output {
13770 /* The specific error status for the command. */
13771 uint16_t error_code;
13772 /* The HWRM command request type. */
13774 /* The sequence ID from the original command. */
13776 /* The length of the response data in number of bytes. */
13779 * This is the configured maximum length of Ethernet packet
13780 * payload that is allowed to be received on the port.
13781 * This value does not include the number of bytes used by
13782 * Ethernet header and trailer (CRC).
13786 * This is the configured maximum length of Ethernet packet
13787 * payload that is allowed to be transmitted on the port.
13788 * This value does not include the number of bytes used by
13789 * Ethernet header and trailer (CRC).
13792 /* Current configuration of the IPG value. */
13794 /* Current value of the loopback value. */
13796 /* No loopback is selected. Normal operation. */
13797 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13799 * The HW will be configured with local loopback such that
13800 * host data is sent back to the host without modification.
13802 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13804 * The HW will be configured with remote loopback such that
13805 * port logic will send packets back out the transmitter that
13808 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13809 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
13810 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
13813 * This field is used in Output records to indicate that the output
13814 * is completely written to RAM. This field should be read as '1'
13815 * to indicate that the output has been completely written.
13816 * When writing a command completion or response to an internal processor,
13817 * the order of writes has to be such that this field is written last.
13820 } __attribute__((packed));
13822 /**********************
13823 * hwrm_port_mac_qcfg *
13824 **********************/
13827 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
13828 struct hwrm_port_mac_qcfg_input {
13829 /* The HWRM command request type. */
13832 * The completion ring to send the completion event on. This should
13833 * be the NQ ID returned from the `nq_alloc` HWRM command.
13835 uint16_t cmpl_ring;
13837 * The sequence ID is used by the driver for tracking multiple
13838 * commands. This ID is treated as opaque data by the firmware and
13839 * the value is returned in the `hwrm_resp_hdr` upon completion.
13843 * The target ID of the command:
13844 * * 0x0-0xFFF8 - The function ID
13845 * * 0xFFF8-0xFFFE - Reserved for internal processors
13848 uint16_t target_id;
13850 * A physical address pointer pointing to a host buffer that the
13851 * command's response data will be written. This can be either a host
13852 * physical address (HPA) or a guest physical address (GPA) and must
13853 * point to a physically contiguous block of memory.
13855 uint64_t resp_addr;
13856 /* Port ID of port that is to be configured. */
13858 uint8_t unused_0[6];
13859 } __attribute__((packed));
13861 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
13862 struct hwrm_port_mac_qcfg_output {
13863 /* The specific error status for the command. */
13864 uint16_t error_code;
13865 /* The HWRM command request type. */
13867 /* The sequence ID from the original command. */
13869 /* The length of the response data in number of bytes. */
13872 * This is the configured maximum length of Ethernet packet
13873 * payload that is allowed to be received on the port.
13874 * This value does not include the number of bytes used by the
13875 * Ethernet header and trailer (CRC).
13879 * This is the configured maximum length of Ethernet packet
13880 * payload that is allowed to be transmitted on the port.
13881 * This value does not include the number of bytes used by the
13882 * Ethernet header and trailer (CRC).
13886 * The minimum IPG that will
13887 * be sent between packets by this port.
13890 /* The loopback setting for the MAC. */
13892 /* No loopback is selected. Normal operation. */
13893 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13895 * The HW will be configured with local loopback such that
13896 * host data is sent back to the host without modification.
13898 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13900 * The HW will be configured with remote loopback such that
13901 * port logic will send packets back out the transmitter that
13904 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13905 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
13906 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
13908 * Priority setting for VLAN PRI to CoS mapping.
13909 * # Each XXX_pri variable shall have a unique priority value
13910 * when it is being used.
13911 * # When comparing priorities of mappings, higher value
13912 * indicates higher priority.
13913 * For example, a value of 0-3 is returned where 0 is being
13914 * the lowest priority and 3 is being the highest priority.
13915 * # If the correspoding CoS mapping is not enabled, then this
13916 * field should be ignored.
13917 * # This value indicates the normalized priority value retained
13920 uint8_t vlan_pri2cos_map_pri;
13922 * In this field, a number of CoS mappings related flags
13923 * are used to indicate configured CoS mappings.
13927 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
13930 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
13933 * When this bit is set to '1', tunnel VLAN PRI field to
13934 * CoS mapping is enabled.
13936 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
13939 * When this bit is set to '1', the IP DSCP to CoS mapping is
13942 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
13945 * When this bit is '1', the Out-Of-Box WoL is enabled on this
13948 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
13950 /* When this bit is '1', PTP is enabled for RX on this port. */
13951 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
13953 /* When this bit is '1', PTP is enabled for TX on this port. */
13954 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
13957 * Priority setting for tunnel VLAN PRI to CoS mapping.
13958 * # Each XXX_pri variable shall have a unique priority value
13959 * when it is being used.
13960 * # When comparing priorities of mappings, higher value
13961 * indicates higher priority.
13962 * For example, a value of 0-3 is returned where 0 is being
13963 * the lowest priority and 3 is being the highest priority.
13964 * # If the correspoding CoS mapping is not enabled, then this
13965 * field should be ignored.
13966 * # This value indicates the normalized priority value retained
13969 uint8_t tunnel_pri2cos_map_pri;
13971 * Priority setting for DSCP to PRI mapping.
13972 * # Each XXX_pri variable shall have a unique priority value
13973 * when it is being used.
13974 * # When comparing priorities of mappings, higher value
13975 * indicates higher priority.
13976 * For example, a value of 0-3 is returned where 0 is being
13977 * the lowest priority and 3 is being the highest priority.
13978 * # If the correspoding CoS mapping is not enabled, then this
13979 * field should be ignored.
13980 * # This value indicates the normalized priority value retained
13983 uint8_t dscp2pri_map_pri;
13985 * This is a 16-bit bit mask that represents the
13986 * current configuration of time stamp capture of PTP messages
13987 * on the receive side of this port.
13988 * If bit 'i' is set, then the receive side of the port
13989 * is configured to capture the time stamp of every
13990 * received PTP message with messageType field value set
13992 * If all bits are set to 0 (i.e. field value set 0),
13993 * then the receive side of the port is not configured
13994 * to capture timestamp for PTP messages.
13995 * If all bits are set to 1, then the receive side of the
13996 * port is configured to capture timestamp for all PTP
13999 uint16_t rx_ts_capture_ptp_msg_type;
14001 * This is a 16-bit bit mask that represents the
14002 * current configuration of time stamp capture of PTP messages
14003 * on the transmit side of this port.
14004 * If bit 'i' is set, then the transmit side of the port
14005 * is configured to capture the time stamp of every
14006 * received PTP message with messageType field value set
14008 * If all bits are set to 0 (i.e. field value set 0),
14009 * then the transmit side of the port is not configured
14010 * to capture timestamp for PTP messages.
14011 * If all bits are set to 1, then the transmit side of the
14012 * port is configured to capture timestamp for all PTP
14015 uint16_t tx_ts_capture_ptp_msg_type;
14016 /* Configuration of CoS fields. */
14017 uint8_t cos_field_cfg;
14019 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
14022 * This field is used for selecting VLAN PRI value
14023 * based on whether one or two VLAN Tags are present in
14024 * the inner packet headers of tunneled packets or
14025 * non-tunneled packets.
14027 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14029 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14032 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14033 * present in the inner packet headers
14035 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14036 (UINT32_C(0x0) << 1)
14038 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14039 * present in the inner packet headers.
14040 * No VLAN PRI is selected for this configuration
14041 * if only one VLAN Tag is present in the inner
14044 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14045 (UINT32_C(0x1) << 1)
14047 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14048 * are present in the inner packet headers
14050 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14051 (UINT32_C(0x2) << 1)
14053 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14054 (UINT32_C(0x3) << 1)
14055 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14056 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14058 * This field is used for selecting tunnel VLAN PRI value
14059 * based on whether one or two VLAN Tags are present in
14060 * the tunnel headers of tunneled packets. This selection
14061 * does not apply to non-tunneled packets.
14063 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14065 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14068 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14069 * present in the tunnel packet headers
14071 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14072 (UINT32_C(0x0) << 3)
14074 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14075 * present in the tunnel packet headers.
14076 * No VLAN PRI is selected for this configuration
14077 * if only one VLAN Tag is present in the tunnel
14080 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14081 (UINT32_C(0x1) << 3)
14083 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14084 * are present in the tunnel packet headers
14086 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14087 (UINT32_C(0x2) << 3)
14089 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14090 (UINT32_C(0x3) << 3)
14091 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14092 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14094 * This field is used to provide default CoS value that
14095 * has been configured on this port.
14097 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14099 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14102 * This field is used in Output records to indicate that the output
14103 * is completely written to RAM. This field should be read as '1'
14104 * to indicate that the output has been completely written.
14105 * When writing a command completion or response to an internal processor,
14106 * the order of writes has to be such that this field is written last.
14109 } __attribute__((packed));
14111 /**************************
14112 * hwrm_port_mac_ptp_qcfg *
14113 **************************/
14116 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
14117 struct hwrm_port_mac_ptp_qcfg_input {
14118 /* The HWRM command request type. */
14121 * The completion ring to send the completion event on. This should
14122 * be the NQ ID returned from the `nq_alloc` HWRM command.
14124 uint16_t cmpl_ring;
14126 * The sequence ID is used by the driver for tracking multiple
14127 * commands. This ID is treated as opaque data by the firmware and
14128 * the value is returned in the `hwrm_resp_hdr` upon completion.
14132 * The target ID of the command:
14133 * * 0x0-0xFFF8 - The function ID
14134 * * 0xFFF8-0xFFFE - Reserved for internal processors
14137 uint16_t target_id;
14139 * A physical address pointer pointing to a host buffer that the
14140 * command's response data will be written. This can be either a host
14141 * physical address (HPA) or a guest physical address (GPA) and must
14142 * point to a physically contiguous block of memory.
14144 uint64_t resp_addr;
14145 /* Port ID of port that is being queried. */
14147 uint8_t unused_0[6];
14148 } __attribute__((packed));
14150 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
14151 struct hwrm_port_mac_ptp_qcfg_output {
14152 /* The specific error status for the command. */
14153 uint16_t error_code;
14154 /* The HWRM command request type. */
14156 /* The sequence ID from the original command. */
14158 /* The length of the response data in number of bytes. */
14161 * In this field, a number of PTP related flags
14162 * are used to indicate configured PTP capabilities.
14166 * When this bit is set to '1', the PTP related registers are
14167 * directly accessible by the host.
14169 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
14172 * When this bit is set to '1', the PTP information is accessible
14173 * via HWRM commands.
14175 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
14177 uint8_t unused_0[3];
14178 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
14179 uint32_t rx_ts_reg_off_lower;
14180 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
14181 uint32_t rx_ts_reg_off_upper;
14182 /* Offset of the PTP register for the sequence ID for RX. */
14183 uint32_t rx_ts_reg_off_seq_id;
14184 /* Offset of the first PTP source ID for RX. */
14185 uint32_t rx_ts_reg_off_src_id_0;
14186 /* Offset of the second PTP source ID for RX. */
14187 uint32_t rx_ts_reg_off_src_id_1;
14188 /* Offset of the third PTP source ID for RX. */
14189 uint32_t rx_ts_reg_off_src_id_2;
14190 /* Offset of the domain ID for RX. */
14191 uint32_t rx_ts_reg_off_domain_id;
14192 /* Offset of the PTP FIFO register for RX. */
14193 uint32_t rx_ts_reg_off_fifo;
14194 /* Offset of the PTP advance FIFO register for RX. */
14195 uint32_t rx_ts_reg_off_fifo_adv;
14196 /* PTP timestamp granularity for RX. */
14197 uint32_t rx_ts_reg_off_granularity;
14198 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
14199 uint32_t tx_ts_reg_off_lower;
14200 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
14201 uint32_t tx_ts_reg_off_upper;
14202 /* Offset of the PTP register for the sequence ID for TX. */
14203 uint32_t tx_ts_reg_off_seq_id;
14204 /* Offset of the PTP FIFO register for TX. */
14205 uint32_t tx_ts_reg_off_fifo;
14206 /* PTP timestamp granularity for TX. */
14207 uint32_t tx_ts_reg_off_granularity;
14208 uint8_t unused_1[7];
14210 * This field is used in Output records to indicate that the output
14211 * is completely written to RAM. This field should be read as '1'
14212 * to indicate that the output has been completely written.
14213 * When writing a command completion or response to an internal processor,
14214 * the order of writes has to be such that this field is written last.
14217 } __attribute__((packed));
14219 /* Port Tx Statistics Formats */
14220 /* tx_port_stats (size:3264b/408B) */
14221 struct tx_port_stats {
14222 /* Total Number of 64 Bytes frames transmitted */
14223 uint64_t tx_64b_frames;
14224 /* Total Number of 65-127 Bytes frames transmitted */
14225 uint64_t tx_65b_127b_frames;
14226 /* Total Number of 128-255 Bytes frames transmitted */
14227 uint64_t tx_128b_255b_frames;
14228 /* Total Number of 256-511 Bytes frames transmitted */
14229 uint64_t tx_256b_511b_frames;
14230 /* Total Number of 512-1023 Bytes frames transmitted */
14231 uint64_t tx_512b_1023b_frames;
14232 /* Total Number of 1024-1518 Bytes frames transmitted */
14233 uint64_t tx_1024b_1518b_frames;
14235 * Total Number of each good VLAN (exludes FCS errors)
14236 * frame transmitted which is 1519 to 1522 bytes in length
14237 * inclusive (excluding framing bits but including FCS bytes).
14239 uint64_t tx_good_vlan_frames;
14240 /* Total Number of 1519-2047 Bytes frames transmitted */
14241 uint64_t tx_1519b_2047b_frames;
14242 /* Total Number of 2048-4095 Bytes frames transmitted */
14243 uint64_t tx_2048b_4095b_frames;
14244 /* Total Number of 4096-9216 Bytes frames transmitted */
14245 uint64_t tx_4096b_9216b_frames;
14246 /* Total Number of 9217-16383 Bytes frames transmitted */
14247 uint64_t tx_9217b_16383b_frames;
14248 /* Total Number of good frames transmitted */
14249 uint64_t tx_good_frames;
14250 /* Total Number of frames transmitted */
14251 uint64_t tx_total_frames;
14252 /* Total number of unicast frames transmitted */
14253 uint64_t tx_ucast_frames;
14254 /* Total number of multicast frames transmitted */
14255 uint64_t tx_mcast_frames;
14256 /* Total number of broadcast frames transmitted */
14257 uint64_t tx_bcast_frames;
14258 /* Total number of PAUSE control frames transmitted */
14259 uint64_t tx_pause_frames;
14261 * Total number of PFC/per-priority PAUSE
14262 * control frames transmitted
14264 uint64_t tx_pfc_frames;
14265 /* Total number of jabber frames transmitted */
14266 uint64_t tx_jabber_frames;
14267 /* Total number of frames transmitted with FCS error */
14268 uint64_t tx_fcs_err_frames;
14269 /* Total number of control frames transmitted */
14270 uint64_t tx_control_frames;
14271 /* Total number of over-sized frames transmitted */
14272 uint64_t tx_oversz_frames;
14273 /* Total number of frames with single deferral */
14274 uint64_t tx_single_dfrl_frames;
14275 /* Total number of frames with multiple deferrals */
14276 uint64_t tx_multi_dfrl_frames;
14277 /* Total number of frames with single collision */
14278 uint64_t tx_single_coll_frames;
14279 /* Total number of frames with multiple collisions */
14280 uint64_t tx_multi_coll_frames;
14281 /* Total number of frames with late collisions */
14282 uint64_t tx_late_coll_frames;
14283 /* Total number of frames with excessive collisions */
14284 uint64_t tx_excessive_coll_frames;
14285 /* Total number of fragmented frames transmitted */
14286 uint64_t tx_frag_frames;
14287 /* Total number of transmit errors */
14289 /* Total number of single VLAN tagged frames transmitted */
14290 uint64_t tx_tagged_frames;
14291 /* Total number of double VLAN tagged frames transmitted */
14292 uint64_t tx_dbl_tagged_frames;
14293 /* Total number of runt frames transmitted */
14294 uint64_t tx_runt_frames;
14295 /* Total number of TX FIFO under runs */
14296 uint64_t tx_fifo_underruns;
14298 * Total number of PFC frames with PFC enabled bit for
14299 * Pri 0 transmitted
14301 uint64_t tx_pfc_ena_frames_pri0;
14303 * Total number of PFC frames with PFC enabled bit for
14304 * Pri 1 transmitted
14306 uint64_t tx_pfc_ena_frames_pri1;
14308 * Total number of PFC frames with PFC enabled bit for
14309 * Pri 2 transmitted
14311 uint64_t tx_pfc_ena_frames_pri2;
14313 * Total number of PFC frames with PFC enabled bit for
14314 * Pri 3 transmitted
14316 uint64_t tx_pfc_ena_frames_pri3;
14318 * Total number of PFC frames with PFC enabled bit for
14319 * Pri 4 transmitted
14321 uint64_t tx_pfc_ena_frames_pri4;
14323 * Total number of PFC frames with PFC enabled bit for
14324 * Pri 5 transmitted
14326 uint64_t tx_pfc_ena_frames_pri5;
14328 * Total number of PFC frames with PFC enabled bit for
14329 * Pri 6 transmitted
14331 uint64_t tx_pfc_ena_frames_pri6;
14333 * Total number of PFC frames with PFC enabled bit for
14334 * Pri 7 transmitted
14336 uint64_t tx_pfc_ena_frames_pri7;
14337 /* Total number of EEE LPI Events on TX */
14338 uint64_t tx_eee_lpi_events;
14339 /* EEE LPI Duration Counter on TX */
14340 uint64_t tx_eee_lpi_duration;
14342 * Total number of Link Level Flow Control (LLFC) messages
14345 uint64_t tx_llfc_logical_msgs;
14346 /* Total number of HCFC messages transmitted */
14347 uint64_t tx_hcfc_msgs;
14348 /* Total number of TX collisions */
14349 uint64_t tx_total_collisions;
14350 /* Total number of transmitted bytes */
14352 /* Total number of end-to-end HOL frames */
14353 uint64_t tx_xthol_frames;
14354 /* Total Tx Drops per Port reported by STATS block */
14355 uint64_t tx_stat_discard;
14356 /* Total Tx Error Drops per Port reported by STATS block */
14357 uint64_t tx_stat_error;
14358 } __attribute__((packed));
14360 /* Port Rx Statistics Formats */
14361 /* rx_port_stats (size:4224b/528B) */
14362 struct rx_port_stats {
14363 /* Total Number of 64 Bytes frames received */
14364 uint64_t rx_64b_frames;
14365 /* Total Number of 65-127 Bytes frames received */
14366 uint64_t rx_65b_127b_frames;
14367 /* Total Number of 128-255 Bytes frames received */
14368 uint64_t rx_128b_255b_frames;
14369 /* Total Number of 256-511 Bytes frames received */
14370 uint64_t rx_256b_511b_frames;
14371 /* Total Number of 512-1023 Bytes frames received */
14372 uint64_t rx_512b_1023b_frames;
14373 /* Total Number of 1024-1518 Bytes frames received */
14374 uint64_t rx_1024b_1518b_frames;
14376 * Total Number of each good VLAN (exludes FCS errors)
14377 * frame received which is 1519 to 1522 bytes in length
14378 * inclusive (excluding framing bits but including FCS bytes).
14380 uint64_t rx_good_vlan_frames;
14381 /* Total Number of 1519-2047 Bytes frames received */
14382 uint64_t rx_1519b_2047b_frames;
14383 /* Total Number of 2048-4095 Bytes frames received */
14384 uint64_t rx_2048b_4095b_frames;
14385 /* Total Number of 4096-9216 Bytes frames received */
14386 uint64_t rx_4096b_9216b_frames;
14387 /* Total Number of 9217-16383 Bytes frames received */
14388 uint64_t rx_9217b_16383b_frames;
14389 /* Total number of frames received */
14390 uint64_t rx_total_frames;
14391 /* Total number of unicast frames received */
14392 uint64_t rx_ucast_frames;
14393 /* Total number of multicast frames received */
14394 uint64_t rx_mcast_frames;
14395 /* Total number of broadcast frames received */
14396 uint64_t rx_bcast_frames;
14397 /* Total number of received frames with FCS error */
14398 uint64_t rx_fcs_err_frames;
14399 /* Total number of control frames received */
14400 uint64_t rx_ctrl_frames;
14401 /* Total number of PAUSE frames received */
14402 uint64_t rx_pause_frames;
14403 /* Total number of PFC frames received */
14404 uint64_t rx_pfc_frames;
14406 * Total number of frames received with an unsupported
14409 uint64_t rx_unsupported_opcode_frames;
14411 * Total number of frames received with an unsupported
14412 * DA for pause and PFC
14414 uint64_t rx_unsupported_da_pausepfc_frames;
14415 /* Total number of frames received with an unsupported SA */
14416 uint64_t rx_wrong_sa_frames;
14417 /* Total number of received packets with alignment error */
14418 uint64_t rx_align_err_frames;
14419 /* Total number of received frames with out-of-range length */
14420 uint64_t rx_oor_len_frames;
14421 /* Total number of received frames with error termination */
14422 uint64_t rx_code_err_frames;
14424 * Total number of received frames with a false carrier is
14425 * detected during idle, as defined by RX_ER samples active
14426 * and RXD is 0xE. The event is reported along with the
14427 * statistics generated on the next received frame. Only
14428 * one false carrier condition can be detected and logged
14431 * Carrier event, valid for 10M/100M speed modes only.
14433 uint64_t rx_false_carrier_frames;
14434 /* Total number of over-sized frames received */
14435 uint64_t rx_ovrsz_frames;
14436 /* Total number of jabber packets received */
14437 uint64_t rx_jbr_frames;
14438 /* Total number of received frames with MTU error */
14439 uint64_t rx_mtu_err_frames;
14440 /* Total number of received frames with CRC match */
14441 uint64_t rx_match_crc_frames;
14442 /* Total number of frames received promiscuously */
14443 uint64_t rx_promiscuous_frames;
14445 * Total number of received frames with one or two VLAN
14448 uint64_t rx_tagged_frames;
14449 /* Total number of received frames with two VLAN tags */
14450 uint64_t rx_double_tagged_frames;
14451 /* Total number of truncated frames received */
14452 uint64_t rx_trunc_frames;
14453 /* Total number of good frames (without errors) received */
14454 uint64_t rx_good_frames;
14456 * Total number of received PFC frames with transition from
14457 * XON to XOFF on Pri 0
14459 uint64_t rx_pfc_xon2xoff_frames_pri0;
14461 * Total number of received PFC frames with transition from
14462 * XON to XOFF on Pri 1
14464 uint64_t rx_pfc_xon2xoff_frames_pri1;
14466 * Total number of received PFC frames with transition from
14467 * XON to XOFF on Pri 2
14469 uint64_t rx_pfc_xon2xoff_frames_pri2;
14471 * Total number of received PFC frames with transition from
14472 * XON to XOFF on Pri 3
14474 uint64_t rx_pfc_xon2xoff_frames_pri3;
14476 * Total number of received PFC frames with transition from
14477 * XON to XOFF on Pri 4
14479 uint64_t rx_pfc_xon2xoff_frames_pri4;
14481 * Total number of received PFC frames with transition from
14482 * XON to XOFF on Pri 5
14484 uint64_t rx_pfc_xon2xoff_frames_pri5;
14486 * Total number of received PFC frames with transition from
14487 * XON to XOFF on Pri 6
14489 uint64_t rx_pfc_xon2xoff_frames_pri6;
14491 * Total number of received PFC frames with transition from
14492 * XON to XOFF on Pri 7
14494 uint64_t rx_pfc_xon2xoff_frames_pri7;
14496 * Total number of received PFC frames with PFC enabled
14499 uint64_t rx_pfc_ena_frames_pri0;
14501 * Total number of received PFC frames with PFC enabled
14504 uint64_t rx_pfc_ena_frames_pri1;
14506 * Total number of received PFC frames with PFC enabled
14509 uint64_t rx_pfc_ena_frames_pri2;
14511 * Total number of received PFC frames with PFC enabled
14514 uint64_t rx_pfc_ena_frames_pri3;
14516 * Total number of received PFC frames with PFC enabled
14519 uint64_t rx_pfc_ena_frames_pri4;
14521 * Total number of received PFC frames with PFC enabled
14524 uint64_t rx_pfc_ena_frames_pri5;
14526 * Total number of received PFC frames with PFC enabled
14529 uint64_t rx_pfc_ena_frames_pri6;
14531 * Total number of received PFC frames with PFC enabled
14534 uint64_t rx_pfc_ena_frames_pri7;
14535 /* Total Number of frames received with SCH CRC error */
14536 uint64_t rx_sch_crc_err_frames;
14537 /* Total Number of under-sized frames received */
14538 uint64_t rx_undrsz_frames;
14539 /* Total Number of fragmented frames received */
14540 uint64_t rx_frag_frames;
14541 /* Total number of RX EEE LPI Events */
14542 uint64_t rx_eee_lpi_events;
14543 /* EEE LPI Duration Counter on RX */
14544 uint64_t rx_eee_lpi_duration;
14546 * Total number of physical type Link Level Flow Control
14547 * (LLFC) messages received
14549 uint64_t rx_llfc_physical_msgs;
14551 * Total number of logical type Link Level Flow Control
14552 * (LLFC) messages received
14554 uint64_t rx_llfc_logical_msgs;
14556 * Total number of logical type Link Level Flow Control
14557 * (LLFC) messages received with CRC error
14559 uint64_t rx_llfc_msgs_with_crc_err;
14560 /* Total number of HCFC messages received */
14561 uint64_t rx_hcfc_msgs;
14562 /* Total number of HCFC messages received with CRC error */
14563 uint64_t rx_hcfc_msgs_with_crc_err;
14564 /* Total number of received bytes */
14566 /* Total number of bytes received in runt frames */
14567 uint64_t rx_runt_bytes;
14568 /* Total number of runt frames received */
14569 uint64_t rx_runt_frames;
14570 /* Total Rx Discards per Port reported by STATS block */
14571 uint64_t rx_stat_discard;
14572 uint64_t rx_stat_err;
14573 } __attribute__((packed));
14575 /********************
14576 * hwrm_port_qstats *
14577 ********************/
14580 /* hwrm_port_qstats_input (size:320b/40B) */
14581 struct hwrm_port_qstats_input {
14582 /* The HWRM command request type. */
14585 * The completion ring to send the completion event on. This should
14586 * be the NQ ID returned from the `nq_alloc` HWRM command.
14588 uint16_t cmpl_ring;
14590 * The sequence ID is used by the driver for tracking multiple
14591 * commands. This ID is treated as opaque data by the firmware and
14592 * the value is returned in the `hwrm_resp_hdr` upon completion.
14596 * The target ID of the command:
14597 * * 0x0-0xFFF8 - The function ID
14598 * * 0xFFF8-0xFFFE - Reserved for internal processors
14601 uint16_t target_id;
14603 * A physical address pointer pointing to a host buffer that the
14604 * command's response data will be written. This can be either a host
14605 * physical address (HPA) or a guest physical address (GPA) and must
14606 * point to a physically contiguous block of memory.
14608 uint64_t resp_addr;
14609 /* Port ID of port that is being queried. */
14611 uint8_t unused_0[6];
14613 * This is the host address where
14614 * Tx port statistics will be stored
14616 uint64_t tx_stat_host_addr;
14618 * This is the host address where
14619 * Rx port statistics will be stored
14621 uint64_t rx_stat_host_addr;
14622 } __attribute__((packed));
14624 /* hwrm_port_qstats_output (size:128b/16B) */
14625 struct hwrm_port_qstats_output {
14626 /* The specific error status for the command. */
14627 uint16_t error_code;
14628 /* The HWRM command request type. */
14630 /* The sequence ID from the original command. */
14632 /* The length of the response data in number of bytes. */
14634 /* The size of TX port statistics block in bytes. */
14635 uint16_t tx_stat_size;
14636 /* The size of RX port statistics block in bytes. */
14637 uint16_t rx_stat_size;
14638 uint8_t unused_0[3];
14640 * This field is used in Output records to indicate that the output
14641 * is completely written to RAM. This field should be read as '1'
14642 * to indicate that the output has been completely written.
14643 * When writing a command completion or response to an internal processor,
14644 * the order of writes has to be such that this field is written last.
14647 } __attribute__((packed));
14649 /* Port Tx Statistics extended Formats */
14650 /* tx_port_stats_ext (size:2048b/256B) */
14651 struct tx_port_stats_ext {
14652 /* Total number of tx bytes count on cos queue 0 */
14653 uint64_t tx_bytes_cos0;
14654 /* Total number of tx bytes count on cos queue 1 */
14655 uint64_t tx_bytes_cos1;
14656 /* Total number of tx bytes count on cos queue 2 */
14657 uint64_t tx_bytes_cos2;
14658 /* Total number of tx bytes count on cos queue 3 */
14659 uint64_t tx_bytes_cos3;
14660 /* Total number of tx bytes count on cos queue 4 */
14661 uint64_t tx_bytes_cos4;
14662 /* Total number of tx bytes count on cos queue 5 */
14663 uint64_t tx_bytes_cos5;
14664 /* Total number of tx bytes count on cos queue 6 */
14665 uint64_t tx_bytes_cos6;
14666 /* Total number of tx bytes count on cos queue 7 */
14667 uint64_t tx_bytes_cos7;
14668 /* Total number of tx packets count on cos queue 0 */
14669 uint64_t tx_packets_cos0;
14670 /* Total number of tx packets count on cos queue 1 */
14671 uint64_t tx_packets_cos1;
14672 /* Total number of tx packets count on cos queue 2 */
14673 uint64_t tx_packets_cos2;
14674 /* Total number of tx packets count on cos queue 3 */
14675 uint64_t tx_packets_cos3;
14676 /* Total number of tx packets count on cos queue 4 */
14677 uint64_t tx_packets_cos4;
14678 /* Total number of tx packets count on cos queue 5 */
14679 uint64_t tx_packets_cos5;
14680 /* Total number of tx packets count on cos queue 6 */
14681 uint64_t tx_packets_cos6;
14682 /* Total number of tx packets count on cos queue 7 */
14683 uint64_t tx_packets_cos7;
14684 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
14685 uint64_t pfc_pri0_tx_duration_us;
14686 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
14687 uint64_t pfc_pri0_tx_transitions;
14688 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
14689 uint64_t pfc_pri1_tx_duration_us;
14690 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
14691 uint64_t pfc_pri1_tx_transitions;
14692 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
14693 uint64_t pfc_pri2_tx_duration_us;
14694 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
14695 uint64_t pfc_pri2_tx_transitions;
14696 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
14697 uint64_t pfc_pri3_tx_duration_us;
14698 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
14699 uint64_t pfc_pri3_tx_transitions;
14700 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
14701 uint64_t pfc_pri4_tx_duration_us;
14702 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
14703 uint64_t pfc_pri4_tx_transitions;
14704 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
14705 uint64_t pfc_pri5_tx_duration_us;
14706 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
14707 uint64_t pfc_pri5_tx_transitions;
14708 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
14709 uint64_t pfc_pri6_tx_duration_us;
14710 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
14711 uint64_t pfc_pri6_tx_transitions;
14712 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
14713 uint64_t pfc_pri7_tx_duration_us;
14714 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
14715 uint64_t pfc_pri7_tx_transitions;
14716 } __attribute__((packed));
14718 /* Port Rx Statistics extended Formats */
14719 /* rx_port_stats_ext (size:2368b/296B) */
14720 struct rx_port_stats_ext {
14721 /* Number of times link state changed to down */
14722 uint64_t link_down_events;
14723 /* Number of times the idle rings with pause bit are found */
14724 uint64_t continuous_pause_events;
14725 /* Number of times the active rings pause bit resumed back */
14726 uint64_t resume_pause_events;
14727 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
14728 uint64_t continuous_roce_pause_events;
14729 /* Number of times, the ROCE cos queue PFC is enabled back */
14730 uint64_t resume_roce_pause_events;
14731 /* Total number of rx bytes count on cos queue 0 */
14732 uint64_t rx_bytes_cos0;
14733 /* Total number of rx bytes count on cos queue 1 */
14734 uint64_t rx_bytes_cos1;
14735 /* Total number of rx bytes count on cos queue 2 */
14736 uint64_t rx_bytes_cos2;
14737 /* Total number of rx bytes count on cos queue 3 */
14738 uint64_t rx_bytes_cos3;
14739 /* Total number of rx bytes count on cos queue 4 */
14740 uint64_t rx_bytes_cos4;
14741 /* Total number of rx bytes count on cos queue 5 */
14742 uint64_t rx_bytes_cos5;
14743 /* Total number of rx bytes count on cos queue 6 */
14744 uint64_t rx_bytes_cos6;
14745 /* Total number of rx bytes count on cos queue 7 */
14746 uint64_t rx_bytes_cos7;
14747 /* Total number of rx packets count on cos queue 0 */
14748 uint64_t rx_packets_cos0;
14749 /* Total number of rx packets count on cos queue 1 */
14750 uint64_t rx_packets_cos1;
14751 /* Total number of rx packets count on cos queue 2 */
14752 uint64_t rx_packets_cos2;
14753 /* Total number of rx packets count on cos queue 3 */
14754 uint64_t rx_packets_cos3;
14755 /* Total number of rx packets count on cos queue 4 */
14756 uint64_t rx_packets_cos4;
14757 /* Total number of rx packets count on cos queue 5 */
14758 uint64_t rx_packets_cos5;
14759 /* Total number of rx packets count on cos queue 6 */
14760 uint64_t rx_packets_cos6;
14761 /* Total number of rx packets count on cos queue 7 */
14762 uint64_t rx_packets_cos7;
14763 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
14764 uint64_t pfc_pri0_rx_duration_us;
14765 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
14766 uint64_t pfc_pri0_rx_transitions;
14767 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
14768 uint64_t pfc_pri1_rx_duration_us;
14769 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
14770 uint64_t pfc_pri1_rx_transitions;
14771 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
14772 uint64_t pfc_pri2_rx_duration_us;
14773 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
14774 uint64_t pfc_pri2_rx_transitions;
14775 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
14776 uint64_t pfc_pri3_rx_duration_us;
14777 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
14778 uint64_t pfc_pri3_rx_transitions;
14779 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
14780 uint64_t pfc_pri4_rx_duration_us;
14781 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
14782 uint64_t pfc_pri4_rx_transitions;
14783 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
14784 uint64_t pfc_pri5_rx_duration_us;
14785 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
14786 uint64_t pfc_pri5_rx_transitions;
14787 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
14788 uint64_t pfc_pri6_rx_duration_us;
14789 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
14790 uint64_t pfc_pri6_rx_transitions;
14791 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
14792 uint64_t pfc_pri7_rx_duration_us;
14793 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
14794 uint64_t pfc_pri7_rx_transitions;
14795 } __attribute__((packed));
14797 /************************
14798 * hwrm_port_qstats_ext *
14799 ************************/
14802 /* hwrm_port_qstats_ext_input (size:320b/40B) */
14803 struct hwrm_port_qstats_ext_input {
14804 /* The HWRM command request type. */
14807 * The completion ring to send the completion event on. This should
14808 * be the NQ ID returned from the `nq_alloc` HWRM command.
14810 uint16_t cmpl_ring;
14812 * The sequence ID is used by the driver for tracking multiple
14813 * commands. This ID is treated as opaque data by the firmware and
14814 * the value is returned in the `hwrm_resp_hdr` upon completion.
14818 * The target ID of the command:
14819 * * 0x0-0xFFF8 - The function ID
14820 * * 0xFFF8-0xFFFE - Reserved for internal processors
14823 uint16_t target_id;
14825 * A physical address pointer pointing to a host buffer that the
14826 * command's response data will be written. This can be either a host
14827 * physical address (HPA) or a guest physical address (GPA) and must
14828 * point to a physically contiguous block of memory.
14830 uint64_t resp_addr;
14831 /* Port ID of port that is being queried. */
14834 * The size of TX port extended
14835 * statistics block in bytes.
14837 uint16_t tx_stat_size;
14839 * The size of RX port extended
14840 * statistics block in bytes
14842 uint16_t rx_stat_size;
14843 uint8_t unused_0[2];
14845 * This is the host address where
14846 * Tx port statistics will be stored
14848 uint64_t tx_stat_host_addr;
14850 * This is the host address where
14851 * Rx port statistics will be stored
14853 uint64_t rx_stat_host_addr;
14854 } __attribute__((packed));
14856 /* hwrm_port_qstats_ext_output (size:128b/16B) */
14857 struct hwrm_port_qstats_ext_output {
14858 /* The specific error status for the command. */
14859 uint16_t error_code;
14860 /* The HWRM command request type. */
14862 /* The sequence ID from the original command. */
14864 /* The length of the response data in number of bytes. */
14866 /* The size of TX port statistics block in bytes. */
14867 uint16_t tx_stat_size;
14868 /* The size of RX port statistics block in bytes. */
14869 uint16_t rx_stat_size;
14870 /* Total number of active cos queues available. */
14871 uint16_t total_active_cos_queues;
14874 * If set to 1, then this field indicates that clear
14875 * roce specific counters is supported.
14877 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
14880 * This field is used in Output records to indicate that the output
14881 * is completely written to RAM. This field should be read as '1'
14882 * to indicate that the output has been completely written.
14883 * When writing a command completion or response to an internal processor,
14884 * the order of writes has to be such that this field is written last.
14887 } __attribute__((packed));
14889 /*************************
14890 * hwrm_port_lpbk_qstats *
14891 *************************/
14894 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
14895 struct hwrm_port_lpbk_qstats_input {
14896 /* The HWRM command request type. */
14899 * The completion ring to send the completion event on. This should
14900 * be the NQ ID returned from the `nq_alloc` HWRM command.
14902 uint16_t cmpl_ring;
14904 * The sequence ID is used by the driver for tracking multiple
14905 * commands. This ID is treated as opaque data by the firmware and
14906 * the value is returned in the `hwrm_resp_hdr` upon completion.
14910 * The target ID of the command:
14911 * * 0x0-0xFFF8 - The function ID
14912 * * 0xFFF8-0xFFFE - Reserved for internal processors
14915 uint16_t target_id;
14917 * A physical address pointer pointing to a host buffer that the
14918 * command's response data will be written. This can be either a host
14919 * physical address (HPA) or a guest physical address (GPA) and must
14920 * point to a physically contiguous block of memory.
14922 uint64_t resp_addr;
14923 } __attribute__((packed));
14925 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
14926 struct hwrm_port_lpbk_qstats_output {
14927 /* The specific error status for the command. */
14928 uint16_t error_code;
14929 /* The HWRM command request type. */
14931 /* The sequence ID from the original command. */
14933 /* The length of the response data in number of bytes. */
14935 /* Number of transmitted unicast frames */
14936 uint64_t lpbk_ucast_frames;
14937 /* Number of transmitted multicast frames */
14938 uint64_t lpbk_mcast_frames;
14939 /* Number of transmitted broadcast frames */
14940 uint64_t lpbk_bcast_frames;
14941 /* Number of transmitted bytes for unicast traffic */
14942 uint64_t lpbk_ucast_bytes;
14943 /* Number of transmitted bytes for multicast traffic */
14944 uint64_t lpbk_mcast_bytes;
14945 /* Number of transmitted bytes for broadcast traffic */
14946 uint64_t lpbk_bcast_bytes;
14947 /* Total Tx Drops for loopback traffic reported by STATS block */
14948 uint64_t tx_stat_discard;
14949 /* Total Tx Error Drops for loopback traffic reported by STATS block */
14950 uint64_t tx_stat_error;
14951 /* Total Rx Drops for loopback traffic reported by STATS block */
14952 uint64_t rx_stat_discard;
14953 /* Total Rx Error Drops for loopback traffic reported by STATS block */
14954 uint64_t rx_stat_error;
14955 uint8_t unused_0[7];
14957 * This field is used in Output records to indicate that the output
14958 * is completely written to RAM. This field should be read as '1'
14959 * to indicate that the output has been completely written.
14960 * When writing a command completion or response to an internal processor,
14961 * the order of writes has to be such that this field is written last.
14964 } __attribute__((packed));
14966 /***********************
14967 * hwrm_port_clr_stats *
14968 ***********************/
14971 /* hwrm_port_clr_stats_input (size:192b/24B) */
14972 struct hwrm_port_clr_stats_input {
14973 /* The HWRM command request type. */
14976 * The completion ring to send the completion event on. This should
14977 * be the NQ ID returned from the `nq_alloc` HWRM command.
14979 uint16_t cmpl_ring;
14981 * The sequence ID is used by the driver for tracking multiple
14982 * commands. This ID is treated as opaque data by the firmware and
14983 * the value is returned in the `hwrm_resp_hdr` upon completion.
14987 * The target ID of the command:
14988 * * 0x0-0xFFF8 - The function ID
14989 * * 0xFFF8-0xFFFE - Reserved for internal processors
14992 uint16_t target_id;
14994 * A physical address pointer pointing to a host buffer that the
14995 * command's response data will be written. This can be either a host
14996 * physical address (HPA) or a guest physical address (GPA) and must
14997 * point to a physically contiguous block of memory.
14999 uint64_t resp_addr;
15000 /* Port ID of port that is being queried. */
15004 * If set to 1, then this field indicates clear the following RoCE
15005 * specific counters.
15006 * RoCE associated TX/RX cos counters
15007 * CNP associated TX/RX cos counters
15008 * RoCE/CNP specific TX/RX flow counters
15009 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
15010 * This flag is honored only when RoCE is enabled on that port.
15012 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
15013 uint8_t unused_0[5];
15014 } __attribute__((packed));
15016 /* hwrm_port_clr_stats_output (size:128b/16B) */
15017 struct hwrm_port_clr_stats_output {
15018 /* The specific error status for the command. */
15019 uint16_t error_code;
15020 /* The HWRM command request type. */
15022 /* The sequence ID from the original command. */
15024 /* The length of the response data in number of bytes. */
15026 uint8_t unused_0[7];
15028 * This field is used in Output records to indicate that the output
15029 * is completely written to RAM. This field should be read as '1'
15030 * to indicate that the output has been completely written.
15031 * When writing a command completion or response to an internal processor,
15032 * the order of writes has to be such that this field is written last.
15035 } __attribute__((packed));
15037 /***********************
15038 * hwrm_port_phy_qcaps *
15039 ***********************/
15042 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
15043 struct hwrm_port_phy_qcaps_input {
15044 /* The HWRM command request type. */
15047 * The completion ring to send the completion event on. This should
15048 * be the NQ ID returned from the `nq_alloc` HWRM command.
15050 uint16_t cmpl_ring;
15052 * The sequence ID is used by the driver for tracking multiple
15053 * commands. This ID is treated as opaque data by the firmware and
15054 * the value is returned in the `hwrm_resp_hdr` upon completion.
15058 * The target ID of the command:
15059 * * 0x0-0xFFF8 - The function ID
15060 * * 0xFFF8-0xFFFE - Reserved for internal processors
15063 uint16_t target_id;
15065 * A physical address pointer pointing to a host buffer that the
15066 * command's response data will be written. This can be either a host
15067 * physical address (HPA) or a guest physical address (GPA) and must
15068 * point to a physically contiguous block of memory.
15070 uint64_t resp_addr;
15071 /* Port ID of port that is being queried. */
15073 uint8_t unused_0[6];
15074 } __attribute__((packed));
15076 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
15077 struct hwrm_port_phy_qcaps_output {
15078 /* The specific error status for the command. */
15079 uint16_t error_code;
15080 /* The HWRM command request type. */
15082 /* The sequence ID from the original command. */
15084 /* The length of the response data in number of bytes. */
15086 /* PHY capability flags */
15089 * If set to 1, then this field indicates that the
15090 * link is capable of supporting EEE.
15092 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
15095 * If set to 1, then this field indicates that the
15096 * PHY is capable of supporting external loopback.
15098 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
15101 * Reserved field. The HWRM shall set this field to 0.
15102 * An HWRM client shall ignore this field.
15104 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
15106 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
15107 /* Number of front panel ports for this device. */
15109 /* Not supported or unknown */
15110 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
15111 /* single port device */
15112 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
15113 /* 2-port device */
15114 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
15115 /* 3-port device */
15116 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
15117 /* 4-port device */
15118 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
15119 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
15120 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
15122 * This is a bit mask to indicate what speeds are supported
15123 * as forced speeds on this link.
15124 * For each speed that can be forced on this link, the
15125 * corresponding mask bit shall be set to '1'.
15127 uint16_t supported_speeds_force_mode;
15128 /* 100Mb link speed (Half-duplex) */
15129 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
15131 /* 100Mb link speed (Full-duplex) */
15132 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
15134 /* 1Gb link speed (Half-duplex) */
15135 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
15137 /* 1Gb link speed (Full-duplex) */
15138 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
15140 /* 2Gb link speed */
15141 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
15143 /* 25Gb link speed */
15144 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
15146 /* 10Gb link speed */
15147 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
15149 /* 20Gb link speed */
15150 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
15152 /* 25Gb link speed */
15153 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
15155 /* 40Gb link speed */
15156 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
15158 /* 50Gb link speed */
15159 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
15161 /* 100Gb link speed */
15162 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
15164 /* 10Mb link speed (Half-duplex) */
15165 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
15167 /* 10Mb link speed (Full-duplex) */
15168 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
15170 /* 200Gb link speed */
15171 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
15174 * This is a bit mask to indicate what speeds are supported
15175 * for autonegotiation on this link.
15176 * For each speed that can be autonegotiated on this link, the
15177 * corresponding mask bit shall be set to '1'.
15179 uint16_t supported_speeds_auto_mode;
15180 /* 100Mb link speed (Half-duplex) */
15181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
15183 /* 100Mb link speed (Full-duplex) */
15184 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
15186 /* 1Gb link speed (Half-duplex) */
15187 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
15189 /* 1Gb link speed (Full-duplex) */
15190 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
15192 /* 2Gb link speed */
15193 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
15195 /* 25Gb link speed */
15196 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
15198 /* 10Gb link speed */
15199 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
15201 /* 20Gb link speed */
15202 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
15204 /* 25Gb link speed */
15205 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
15207 /* 40Gb link speed */
15208 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
15210 /* 50Gb link speed */
15211 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
15213 /* 100Gb link speed */
15214 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
15216 /* 10Mb link speed (Half-duplex) */
15217 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
15219 /* 10Mb link speed (Full-duplex) */
15220 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
15222 /* 200Gb link speed */
15223 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
15226 * This is a bit mask to indicate what speeds are supported
15227 * for EEE on this link.
15228 * For each speed that can be autonegotiated when EEE is enabled
15229 * on this link, the corresponding mask bit shall be set to '1'.
15230 * This field is only valid when the eee_suppotred is set to '1'.
15232 uint16_t supported_speeds_eee_mode;
15234 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
15236 /* 100Mb link speed (Full-duplex) */
15237 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
15240 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
15242 /* 1Gb link speed (Full-duplex) */
15243 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
15246 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
15249 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
15251 /* 10Gb link speed */
15252 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
15254 uint32_t tx_lpi_timer_low;
15256 * The lowest value of TX LPI timer that can be set on this link
15257 * when EEE is enabled. This value is in microseconds.
15258 * This field is valid only when_eee_supported is set to '1'.
15260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
15262 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
15264 * Reserved field. The HWRM shall set this field to 0.
15265 * An HWRM client shall ignore this field.
15267 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
15268 UINT32_C(0xff000000)
15269 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
15270 uint32_t valid_tx_lpi_timer_high;
15272 * The highest value of TX LPI timer that can be set on this link
15273 * when EEE is enabled. This value is in microseconds.
15274 * This field is valid only when_eee_supported is set to '1'.
15276 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
15278 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
15280 * This field is used in Output records to indicate that the output
15281 * is completely written to RAM. This field should be read as '1'
15282 * to indicate that the output has been completely written.
15283 * When writing a command completion or response to an internal processor,
15284 * the order of writes has to be such that this field is written last.
15286 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
15287 UINT32_C(0xff000000)
15288 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
15289 } __attribute__((packed));
15291 /****************************
15292 * hwrm_port_phy_mdio_write *
15293 ****************************/
15296 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
15297 struct hwrm_port_phy_mdio_write_input {
15298 /* The HWRM command request type. */
15301 * The completion ring to send the completion event on. This should
15302 * be the NQ ID returned from the `nq_alloc` HWRM command.
15304 uint16_t cmpl_ring;
15306 * The sequence ID is used by the driver for tracking multiple
15307 * commands. This ID is treated as opaque data by the firmware and
15308 * the value is returned in the `hwrm_resp_hdr` upon completion.
15312 * The target ID of the command:
15313 * * 0x0-0xFFF8 - The function ID
15314 * * 0xFFF8-0xFFFE - Reserved for internal processors
15317 uint16_t target_id;
15319 * A physical address pointer pointing to a host buffer that the
15320 * command's response data will be written. This can be either a host
15321 * physical address (HPA) or a guest physical address (GPA) and must
15322 * point to a physically contiguous block of memory.
15324 uint64_t resp_addr;
15325 /* Reserved for future use. */
15326 uint32_t unused_0[2];
15327 /* Port ID of port. */
15329 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
15331 /* 8-bit device address. */
15333 /* 16-bit register address. */
15335 /* 16-bit register data. */
15338 * When this bit is set to 1 a Clause 45 mdio access is done.
15339 * when this bit is set to 0 a Clause 22 mdio access is done.
15343 uint8_t unused_1[7];
15344 } __attribute__((packed));
15346 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
15347 struct hwrm_port_phy_mdio_write_output {
15348 /* The specific error status for the command. */
15349 uint16_t error_code;
15350 /* The HWRM command request type. */
15352 /* The sequence ID from the original command. */
15354 /* The length of the response data in number of bytes. */
15356 uint8_t unused_0[7];
15358 * This field is used in Output records to indicate that the output
15359 * is completely written to RAM. This field should be read as '1'
15360 * to indicate that the output has been completely written.
15361 * When writing a command completion or response to an internal processor,
15362 * the order of writes has to be such that this field is written last.
15365 } __attribute__((packed));
15367 /***************************
15368 * hwrm_port_phy_mdio_read *
15369 ***************************/
15372 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
15373 struct hwrm_port_phy_mdio_read_input {
15374 /* The HWRM command request type. */
15377 * The completion ring to send the completion event on. This should
15378 * be the NQ ID returned from the `nq_alloc` HWRM command.
15380 uint16_t cmpl_ring;
15382 * The sequence ID is used by the driver for tracking multiple
15383 * commands. This ID is treated as opaque data by the firmware and
15384 * the value is returned in the `hwrm_resp_hdr` upon completion.
15388 * The target ID of the command:
15389 * * 0x0-0xFFF8 - The function ID
15390 * * 0xFFF8-0xFFFE - Reserved for internal processors
15393 uint16_t target_id;
15395 * A physical address pointer pointing to a host buffer that the
15396 * command's response data will be written. This can be either a host
15397 * physical address (HPA) or a guest physical address (GPA) and must
15398 * point to a physically contiguous block of memory.
15400 uint64_t resp_addr;
15401 /* Reserved for future use. */
15402 uint32_t unused_0[2];
15403 /* Port ID of port. */
15405 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
15407 /* 8-bit device address. */
15409 /* 16-bit register address. */
15412 * When this bit is set to 1 a Clause 45 mdio access is done.
15413 * when this bit is set to 0 a Clause 22 mdio access is done.
15418 } __attribute__((packed));
15420 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
15421 struct hwrm_port_phy_mdio_read_output {
15422 /* The specific error status for the command. */
15423 uint16_t error_code;
15424 /* The HWRM command request type. */
15426 /* The sequence ID from the original command. */
15428 /* The length of the response data in number of bytes. */
15430 /* 16-bit register data. */
15432 uint8_t unused_0[5];
15434 * This field is used in Output records to indicate that the output
15435 * is completely written to RAM. This field should be read as '1'
15436 * to indicate that the output has been completely written.
15437 * When writing a command completion or response to an internal processor,
15438 * the order of writes has to be such that this field is written last.
15441 } __attribute__((packed));
15443 /*********************
15444 * hwrm_port_led_cfg *
15445 *********************/
15448 /* hwrm_port_led_cfg_input (size:512b/64B) */
15449 struct hwrm_port_led_cfg_input {
15450 /* The HWRM command request type. */
15453 * The completion ring to send the completion event on. This should
15454 * be the NQ ID returned from the `nq_alloc` HWRM command.
15456 uint16_t cmpl_ring;
15458 * The sequence ID is used by the driver for tracking multiple
15459 * commands. This ID is treated as opaque data by the firmware and
15460 * the value is returned in the `hwrm_resp_hdr` upon completion.
15464 * The target ID of the command:
15465 * * 0x0-0xFFF8 - The function ID
15466 * * 0xFFF8-0xFFFE - Reserved for internal processors
15469 uint16_t target_id;
15471 * A physical address pointer pointing to a host buffer that the
15472 * command's response data will be written. This can be either a host
15473 * physical address (HPA) or a guest physical address (GPA) and must
15474 * point to a physically contiguous block of memory.
15476 uint64_t resp_addr;
15479 * This bit must be '1' for the led0_id field to be
15482 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
15485 * This bit must be '1' for the led0_state field to be
15488 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
15491 * This bit must be '1' for the led0_color field to be
15494 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
15497 * This bit must be '1' for the led0_blink_on field to be
15500 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
15503 * This bit must be '1' for the led0_blink_off field to be
15506 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
15509 * This bit must be '1' for the led0_group_id field to be
15512 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
15515 * This bit must be '1' for the led1_id field to be
15518 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
15521 * This bit must be '1' for the led1_state field to be
15524 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
15527 * This bit must be '1' for the led1_color field to be
15530 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
15533 * This bit must be '1' for the led1_blink_on field to be
15536 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
15539 * This bit must be '1' for the led1_blink_off field to be
15542 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
15545 * This bit must be '1' for the led1_group_id field to be
15548 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
15551 * This bit must be '1' for the led2_id field to be
15554 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
15557 * This bit must be '1' for the led2_state field to be
15560 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
15563 * This bit must be '1' for the led2_color field to be
15566 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
15569 * This bit must be '1' for the led2_blink_on field to be
15572 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
15575 * This bit must be '1' for the led2_blink_off field to be
15578 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
15581 * This bit must be '1' for the led2_group_id field to be
15584 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
15587 * This bit must be '1' for the led3_id field to be
15590 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
15593 * This bit must be '1' for the led3_state field to be
15596 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
15599 * This bit must be '1' for the led3_color field to be
15602 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
15605 * This bit must be '1' for the led3_blink_on field to be
15608 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
15611 * This bit must be '1' for the led3_blink_off field to be
15614 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
15617 * This bit must be '1' for the led3_group_id field to be
15620 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
15622 /* Port ID of port whose LEDs are configured. */
15625 * The number of LEDs that are being configured.
15626 * Up to 4 LEDs can be configured with this command.
15629 /* Reserved field. */
15631 /* An identifier for the LED #0. */
15633 /* The requested state of the LED #0. */
15634 uint8_t led0_state;
15635 /* Default state of the LED */
15636 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
15638 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
15640 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
15642 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
15643 /* Blink Alternately */
15644 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
15645 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
15646 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
15647 /* The requested color of LED #0. */
15648 uint8_t led0_color;
15650 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
15652 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
15654 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
15655 /* Green or Amber */
15656 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
15657 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
15658 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
15661 * If the LED #0 state is "blink" or "blinkalt", then
15662 * this field represents the requested time in milliseconds
15663 * to keep LED on between cycles.
15665 uint16_t led0_blink_on;
15667 * If the LED #0 state is "blink" or "blinkalt", then
15668 * this field represents the requested time in milliseconds
15669 * to keep LED off between cycles.
15671 uint16_t led0_blink_off;
15673 * An identifier for the group of LEDs that LED #0 belongs
15675 * If set to 0, then the LED #0 shall not be grouped and
15676 * shall be treated as an individual resource.
15677 * For all other non-zero values of this field, LED #0 shall
15678 * be grouped together with the LEDs with the same group ID
15681 uint8_t led0_group_id;
15682 /* Reserved field. */
15684 /* An identifier for the LED #1. */
15686 /* The requested state of the LED #1. */
15687 uint8_t led1_state;
15688 /* Default state of the LED */
15689 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
15691 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
15693 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
15695 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
15696 /* Blink Alternately */
15697 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
15698 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
15699 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
15700 /* The requested color of LED #1. */
15701 uint8_t led1_color;
15703 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
15705 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
15707 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
15708 /* Green or Amber */
15709 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
15710 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
15711 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
15714 * If the LED #1 state is "blink" or "blinkalt", then
15715 * this field represents the requested time in milliseconds
15716 * to keep LED on between cycles.
15718 uint16_t led1_blink_on;
15720 * If the LED #1 state is "blink" or "blinkalt", then
15721 * this field represents the requested time in milliseconds
15722 * to keep LED off between cycles.
15724 uint16_t led1_blink_off;
15726 * An identifier for the group of LEDs that LED #1 belongs
15728 * If set to 0, then the LED #1 shall not be grouped and
15729 * shall be treated as an individual resource.
15730 * For all other non-zero values of this field, LED #1 shall
15731 * be grouped together with the LEDs with the same group ID
15734 uint8_t led1_group_id;
15735 /* Reserved field. */
15737 /* An identifier for the LED #2. */
15739 /* The requested state of the LED #2. */
15740 uint8_t led2_state;
15741 /* Default state of the LED */
15742 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
15744 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
15746 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
15748 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
15749 /* Blink Alternately */
15750 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
15751 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
15752 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
15753 /* The requested color of LED #2. */
15754 uint8_t led2_color;
15756 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
15758 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
15760 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
15761 /* Green or Amber */
15762 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
15763 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
15764 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
15767 * If the LED #2 state is "blink" or "blinkalt", then
15768 * this field represents the requested time in milliseconds
15769 * to keep LED on between cycles.
15771 uint16_t led2_blink_on;
15773 * If the LED #2 state is "blink" or "blinkalt", then
15774 * this field represents the requested time in milliseconds
15775 * to keep LED off between cycles.
15777 uint16_t led2_blink_off;
15779 * An identifier for the group of LEDs that LED #2 belongs
15781 * If set to 0, then the LED #2 shall not be grouped and
15782 * shall be treated as an individual resource.
15783 * For all other non-zero values of this field, LED #2 shall
15784 * be grouped together with the LEDs with the same group ID
15787 uint8_t led2_group_id;
15788 /* Reserved field. */
15790 /* An identifier for the LED #3. */
15792 /* The requested state of the LED #3. */
15793 uint8_t led3_state;
15794 /* Default state of the LED */
15795 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
15797 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
15799 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
15801 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
15802 /* Blink Alternately */
15803 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
15804 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
15805 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
15806 /* The requested color of LED #3. */
15807 uint8_t led3_color;
15809 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
15811 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
15813 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
15814 /* Green or Amber */
15815 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
15816 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
15817 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
15820 * If the LED #3 state is "blink" or "blinkalt", then
15821 * this field represents the requested time in milliseconds
15822 * to keep LED on between cycles.
15824 uint16_t led3_blink_on;
15826 * If the LED #3 state is "blink" or "blinkalt", then
15827 * this field represents the requested time in milliseconds
15828 * to keep LED off between cycles.
15830 uint16_t led3_blink_off;
15832 * An identifier for the group of LEDs that LED #3 belongs
15834 * If set to 0, then the LED #3 shall not be grouped and
15835 * shall be treated as an individual resource.
15836 * For all other non-zero values of this field, LED #3 shall
15837 * be grouped together with the LEDs with the same group ID
15840 uint8_t led3_group_id;
15841 /* Reserved field. */
15843 } __attribute__((packed));
15845 /* hwrm_port_led_cfg_output (size:128b/16B) */
15846 struct hwrm_port_led_cfg_output {
15847 /* The specific error status for the command. */
15848 uint16_t error_code;
15849 /* The HWRM command request type. */
15851 /* The sequence ID from the original command. */
15853 /* The length of the response data in number of bytes. */
15855 uint8_t unused_0[7];
15857 * This field is used in Output records to indicate that the output
15858 * is completely written to RAM. This field should be read as '1'
15859 * to indicate that the output has been completely written.
15860 * When writing a command completion or response to an internal processor,
15861 * the order of writes has to be such that this field is written last.
15864 } __attribute__((packed));
15866 /**********************
15867 * hwrm_port_led_qcfg *
15868 **********************/
15871 /* hwrm_port_led_qcfg_input (size:192b/24B) */
15872 struct hwrm_port_led_qcfg_input {
15873 /* The HWRM command request type. */
15876 * The completion ring to send the completion event on. This should
15877 * be the NQ ID returned from the `nq_alloc` HWRM command.
15879 uint16_t cmpl_ring;
15881 * The sequence ID is used by the driver for tracking multiple
15882 * commands. This ID is treated as opaque data by the firmware and
15883 * the value is returned in the `hwrm_resp_hdr` upon completion.
15887 * The target ID of the command:
15888 * * 0x0-0xFFF8 - The function ID
15889 * * 0xFFF8-0xFFFE - Reserved for internal processors
15892 uint16_t target_id;
15894 * A physical address pointer pointing to a host buffer that the
15895 * command's response data will be written. This can be either a host
15896 * physical address (HPA) or a guest physical address (GPA) and must
15897 * point to a physically contiguous block of memory.
15899 uint64_t resp_addr;
15900 /* Port ID of port whose LED configuration is being queried. */
15902 uint8_t unused_0[6];
15903 } __attribute__((packed));
15905 /* hwrm_port_led_qcfg_output (size:448b/56B) */
15906 struct hwrm_port_led_qcfg_output {
15907 /* The specific error status for the command. */
15908 uint16_t error_code;
15909 /* The HWRM command request type. */
15911 /* The sequence ID from the original command. */
15913 /* The length of the response data in number of bytes. */
15916 * The number of LEDs that are configured on this port.
15917 * Up to 4 LEDs can be returned in the response.
15920 /* An identifier for the LED #0. */
15922 /* The type of LED #0. */
15925 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
15927 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
15929 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
15930 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
15931 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
15932 /* The current state of the LED #0. */
15933 uint8_t led0_state;
15934 /* Default state of the LED */
15935 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
15937 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
15939 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
15941 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
15942 /* Blink Alternately */
15943 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
15944 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
15945 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
15946 /* The color of LED #0. */
15947 uint8_t led0_color;
15949 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
15951 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
15953 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
15954 /* Green or Amber */
15955 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
15956 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
15957 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
15960 * If the LED #0 state is "blink" or "blinkalt", then
15961 * this field represents the requested time in milliseconds
15962 * to keep LED on between cycles.
15964 uint16_t led0_blink_on;
15966 * If the LED #0 state is "blink" or "blinkalt", then
15967 * this field represents the requested time in milliseconds
15968 * to keep LED off between cycles.
15970 uint16_t led0_blink_off;
15972 * An identifier for the group of LEDs that LED #0 belongs
15974 * If set to 0, then the LED #0 is not grouped.
15975 * For all other non-zero values of this field, LED #0 is
15976 * grouped together with the LEDs with the same group ID
15979 uint8_t led0_group_id;
15980 /* An identifier for the LED #1. */
15982 /* The type of LED #1. */
15985 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
15987 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
15989 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
15990 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
15991 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
15992 /* The current state of the LED #1. */
15993 uint8_t led1_state;
15994 /* Default state of the LED */
15995 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
15997 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
15999 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
16001 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
16002 /* Blink Alternately */
16003 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16004 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
16005 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
16006 /* The color of LED #1. */
16007 uint8_t led1_color;
16009 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16011 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16013 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16014 /* Green or Amber */
16015 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16016 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
16017 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
16020 * If the LED #1 state is "blink" or "blinkalt", then
16021 * this field represents the requested time in milliseconds
16022 * to keep LED on between cycles.
16024 uint16_t led1_blink_on;
16026 * If the LED #1 state is "blink" or "blinkalt", then
16027 * this field represents the requested time in milliseconds
16028 * to keep LED off between cycles.
16030 uint16_t led1_blink_off;
16032 * An identifier for the group of LEDs that LED #1 belongs
16034 * If set to 0, then the LED #1 is not grouped.
16035 * For all other non-zero values of this field, LED #1 is
16036 * grouped together with the LEDs with the same group ID
16039 uint8_t led1_group_id;
16040 /* An identifier for the LED #2. */
16042 /* The type of LED #2. */
16045 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
16047 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
16049 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
16050 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
16051 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
16052 /* The current state of the LED #2. */
16053 uint8_t led2_state;
16054 /* Default state of the LED */
16055 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16057 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
16059 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
16061 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
16062 /* Blink Alternately */
16063 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16064 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
16065 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
16066 /* The color of LED #2. */
16067 uint8_t led2_color;
16069 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16071 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16073 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16074 /* Green or Amber */
16075 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16076 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
16077 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
16080 * If the LED #2 state is "blink" or "blinkalt", then
16081 * this field represents the requested time in milliseconds
16082 * to keep LED on between cycles.
16084 uint16_t led2_blink_on;
16086 * If the LED #2 state is "blink" or "blinkalt", then
16087 * this field represents the requested time in milliseconds
16088 * to keep LED off between cycles.
16090 uint16_t led2_blink_off;
16092 * An identifier for the group of LEDs that LED #2 belongs
16094 * If set to 0, then the LED #2 is not grouped.
16095 * For all other non-zero values of this field, LED #2 is
16096 * grouped together with the LEDs with the same group ID
16099 uint8_t led2_group_id;
16100 /* An identifier for the LED #3. */
16102 /* The type of LED #3. */
16105 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
16107 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
16109 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
16110 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
16111 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
16112 /* The current state of the LED #3. */
16113 uint8_t led3_state;
16114 /* Default state of the LED */
16115 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
16117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
16119 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
16121 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
16122 /* Blink Alternately */
16123 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
16124 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
16125 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
16126 /* The color of LED #3. */
16127 uint8_t led3_color;
16129 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
16131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
16133 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
16134 /* Green or Amber */
16135 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
16136 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
16137 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
16140 * If the LED #3 state is "blink" or "blinkalt", then
16141 * this field represents the requested time in milliseconds
16142 * to keep LED on between cycles.
16144 uint16_t led3_blink_on;
16146 * If the LED #3 state is "blink" or "blinkalt", then
16147 * this field represents the requested time in milliseconds
16148 * to keep LED off between cycles.
16150 uint16_t led3_blink_off;
16152 * An identifier for the group of LEDs that LED #3 belongs
16154 * If set to 0, then the LED #3 is not grouped.
16155 * For all other non-zero values of this field, LED #3 is
16156 * grouped together with the LEDs with the same group ID
16159 uint8_t led3_group_id;
16160 uint8_t unused_4[6];
16162 * This field is used in Output records to indicate that the output
16163 * is completely written to RAM. This field should be read as '1'
16164 * to indicate that the output has been completely written.
16165 * When writing a command completion or response to an internal processor,
16166 * the order of writes has to be such that this field is written last.
16169 } __attribute__((packed));
16171 /***********************
16172 * hwrm_port_led_qcaps *
16173 ***********************/
16176 /* hwrm_port_led_qcaps_input (size:192b/24B) */
16177 struct hwrm_port_led_qcaps_input {
16178 /* The HWRM command request type. */
16181 * The completion ring to send the completion event on. This should
16182 * be the NQ ID returned from the `nq_alloc` HWRM command.
16184 uint16_t cmpl_ring;
16186 * The sequence ID is used by the driver for tracking multiple
16187 * commands. This ID is treated as opaque data by the firmware and
16188 * the value is returned in the `hwrm_resp_hdr` upon completion.
16192 * The target ID of the command:
16193 * * 0x0-0xFFF8 - The function ID
16194 * * 0xFFF8-0xFFFE - Reserved for internal processors
16197 uint16_t target_id;
16199 * A physical address pointer pointing to a host buffer that the
16200 * command's response data will be written. This can be either a host
16201 * physical address (HPA) or a guest physical address (GPA) and must
16202 * point to a physically contiguous block of memory.
16204 uint64_t resp_addr;
16205 /* Port ID of port whose LED configuration is being queried. */
16207 uint8_t unused_0[6];
16208 } __attribute__((packed));
16210 /* hwrm_port_led_qcaps_output (size:384b/48B) */
16211 struct hwrm_port_led_qcaps_output {
16212 /* The specific error status for the command. */
16213 uint16_t error_code;
16214 /* The HWRM command request type. */
16216 /* The sequence ID from the original command. */
16218 /* The length of the response data in number of bytes. */
16221 * The number of LEDs that are configured on this port.
16222 * Up to 4 LEDs can be returned in the response.
16225 /* Reserved for future use. */
16227 /* An identifier for the LED #0. */
16229 /* The type of LED #0. */
16232 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
16234 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
16236 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
16237 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
16238 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
16240 * An identifier for the group of LEDs that LED #0 belongs
16242 * If set to 0, then the LED #0 cannot be grouped.
16243 * For all other non-zero values of this field, LED #0 is
16244 * grouped together with the LEDs with the same group ID
16247 uint8_t led0_group_id;
16249 /* The states supported by LED #0. */
16250 uint16_t led0_state_caps;
16252 * If set to 1, this LED is enabled.
16253 * If set to 0, this LED is disabled.
16255 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
16258 * If set to 1, off state is supported on this LED.
16259 * If set to 0, off state is not supported on this LED.
16261 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
16264 * If set to 1, on state is supported on this LED.
16265 * If set to 0, on state is not supported on this LED.
16267 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
16270 * If set to 1, blink state is supported on this LED.
16271 * If set to 0, blink state is not supported on this LED.
16273 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
16276 * If set to 1, blink_alt state is supported on this LED.
16277 * If set to 0, blink_alt state is not supported on this LED.
16279 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
16281 /* The colors supported by LED #0. */
16282 uint16_t led0_color_caps;
16284 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
16287 * If set to 1, Amber color is supported on this LED.
16288 * If set to 0, Amber color is not supported on this LED.
16290 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
16293 * If set to 1, Green color is supported on this LED.
16294 * If set to 0, Green color is not supported on this LED.
16296 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
16298 /* An identifier for the LED #1. */
16300 /* The type of LED #1. */
16303 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
16305 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
16307 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
16308 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
16309 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
16311 * An identifier for the group of LEDs that LED #1 belongs
16313 * If set to 0, then the LED #0 cannot be grouped.
16314 * For all other non-zero values of this field, LED #0 is
16315 * grouped together with the LEDs with the same group ID
16318 uint8_t led1_group_id;
16320 /* The states supported by LED #1. */
16321 uint16_t led1_state_caps;
16323 * If set to 1, this LED is enabled.
16324 * If set to 0, this LED is disabled.
16326 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
16329 * If set to 1, off state is supported on this LED.
16330 * If set to 0, off state is not supported on this LED.
16332 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
16335 * If set to 1, on state is supported on this LED.
16336 * If set to 0, on state is not supported on this LED.
16338 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
16341 * If set to 1, blink state is supported on this LED.
16342 * If set to 0, blink state is not supported on this LED.
16344 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
16347 * If set to 1, blink_alt state is supported on this LED.
16348 * If set to 0, blink_alt state is not supported on this LED.
16350 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
16352 /* The colors supported by LED #1. */
16353 uint16_t led1_color_caps;
16355 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
16358 * If set to 1, Amber color is supported on this LED.
16359 * If set to 0, Amber color is not supported on this LED.
16361 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
16364 * If set to 1, Green color is supported on this LED.
16365 * If set to 0, Green color is not supported on this LED.
16367 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
16369 /* An identifier for the LED #2. */
16371 /* The type of LED #2. */
16374 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
16376 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
16378 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
16379 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
16380 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
16382 * An identifier for the group of LEDs that LED #0 belongs
16384 * If set to 0, then the LED #0 cannot be grouped.
16385 * For all other non-zero values of this field, LED #0 is
16386 * grouped together with the LEDs with the same group ID
16389 uint8_t led2_group_id;
16391 /* The states supported by LED #2. */
16392 uint16_t led2_state_caps;
16394 * If set to 1, this LED is enabled.
16395 * If set to 0, this LED is disabled.
16397 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
16400 * If set to 1, off state is supported on this LED.
16401 * If set to 0, off state is not supported on this LED.
16403 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
16406 * If set to 1, on state is supported on this LED.
16407 * If set to 0, on state is not supported on this LED.
16409 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
16412 * If set to 1, blink state is supported on this LED.
16413 * If set to 0, blink state is not supported on this LED.
16415 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
16418 * If set to 1, blink_alt state is supported on this LED.
16419 * If set to 0, blink_alt state is not supported on this LED.
16421 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
16423 /* The colors supported by LED #2. */
16424 uint16_t led2_color_caps;
16426 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
16429 * If set to 1, Amber color is supported on this LED.
16430 * If set to 0, Amber color is not supported on this LED.
16432 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
16435 * If set to 1, Green color is supported on this LED.
16436 * If set to 0, Green color is not supported on this LED.
16438 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
16440 /* An identifier for the LED #3. */
16442 /* The type of LED #3. */
16445 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
16447 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
16449 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
16450 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
16451 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
16453 * An identifier for the group of LEDs that LED #3 belongs
16455 * If set to 0, then the LED #0 cannot be grouped.
16456 * For all other non-zero values of this field, LED #0 is
16457 * grouped together with the LEDs with the same group ID
16460 uint8_t led3_group_id;
16462 /* The states supported by LED #3. */
16463 uint16_t led3_state_caps;
16465 * If set to 1, this LED is enabled.
16466 * If set to 0, this LED is disabled.
16468 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
16471 * If set to 1, off state is supported on this LED.
16472 * If set to 0, off state is not supported on this LED.
16474 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
16477 * If set to 1, on state is supported on this LED.
16478 * If set to 0, on state is not supported on this LED.
16480 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
16483 * If set to 1, blink state is supported on this LED.
16484 * If set to 0, blink state is not supported on this LED.
16486 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
16489 * If set to 1, blink_alt state is supported on this LED.
16490 * If set to 0, blink_alt state is not supported on this LED.
16492 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
16494 /* The colors supported by LED #3. */
16495 uint16_t led3_color_caps;
16497 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
16500 * If set to 1, Amber color is supported on this LED.
16501 * If set to 0, Amber color is not supported on this LED.
16503 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
16506 * If set to 1, Green color is supported on this LED.
16507 * If set to 0, Green color is not supported on this LED.
16509 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
16511 uint8_t unused_4[3];
16513 * This field is used in Output records to indicate that the output
16514 * is completely written to RAM. This field should be read as '1'
16515 * to indicate that the output has been completely written.
16516 * When writing a command completion or response to an internal processor,
16517 * the order of writes has to be such that this field is written last.
16520 } __attribute__((packed));
16522 /***********************
16523 * hwrm_queue_qportcfg *
16524 ***********************/
16527 /* hwrm_queue_qportcfg_input (size:192b/24B) */
16528 struct hwrm_queue_qportcfg_input {
16529 /* The HWRM command request type. */
16532 * The completion ring to send the completion event on. This should
16533 * be the NQ ID returned from the `nq_alloc` HWRM command.
16535 uint16_t cmpl_ring;
16537 * The sequence ID is used by the driver for tracking multiple
16538 * commands. This ID is treated as opaque data by the firmware and
16539 * the value is returned in the `hwrm_resp_hdr` upon completion.
16543 * The target ID of the command:
16544 * * 0x0-0xFFF8 - The function ID
16545 * * 0xFFF8-0xFFFE - Reserved for internal processors
16548 uint16_t target_id;
16550 * A physical address pointer pointing to a host buffer that the
16551 * command's response data will be written. This can be either a host
16552 * physical address (HPA) or a guest physical address (GPA) and must
16553 * point to a physically contiguous block of memory.
16555 uint64_t resp_addr;
16558 * Enumeration denoting the RX, TX type of the resource.
16559 * This enumeration is used for resources that are similar for both
16560 * TX and RX paths of the chip.
16562 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
16564 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
16566 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
16567 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
16568 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
16570 * Port ID of port for which the queue configuration is being
16571 * queried. This field is only required when sent by IPC.
16575 * Drivers will set this capability when it can use
16576 * queue_idx_service_profile to map the queues to application.
16578 uint8_t drv_qmap_cap;
16580 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
16582 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
16583 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
16584 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
16586 } __attribute__((packed));
16588 /* hwrm_queue_qportcfg_output (size:256b/32B) */
16589 struct hwrm_queue_qportcfg_output {
16590 /* The specific error status for the command. */
16591 uint16_t error_code;
16592 /* The HWRM command request type. */
16594 /* The sequence ID from the original command. */
16596 /* The length of the response data in number of bytes. */
16599 * The maximum number of queues that can be configured on this
16601 * Valid values range from 1 through 8.
16603 uint8_t max_configurable_queues;
16605 * The maximum number of lossless queues that can be configured
16607 * Valid values range from 0 through 8.
16609 uint8_t max_configurable_lossless_queues;
16611 * Bitmask indicating which queues can be configured by the
16612 * hwrm_queue_cfg command.
16614 * Each bit represents a specific queue where bit 0 represents
16615 * queue 0 and bit 7 represents queue 7.
16616 * # A value of 0 indicates that the queue is not configurable
16617 * by the hwrm_queue_cfg command.
16618 * # A value of 1 indicates that the queue is configurable.
16619 * # A hwrm_queue_cfg command shall return error when trying to
16620 * configure a queue not configurable.
16622 uint8_t queue_cfg_allowed;
16623 /* Information about queue configuration. */
16624 uint8_t queue_cfg_info;
16626 * If this flag is set to '1', then the queues are
16627 * configured asymmetrically on TX and RX sides.
16628 * If this flag is set to '0', then the queues are
16629 * configured symmetrically on TX and RX sides. For
16630 * symmetric configuration, the queue configuration
16631 * including queue ids and service profiles on the
16632 * TX side is the same as the corresponding queue
16633 * configuration on the RX side.
16635 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
16638 * Bitmask indicating which queues can be configured by the
16639 * hwrm_queue_pfcenable_cfg command.
16641 * Each bit represents a specific priority where bit 0 represents
16642 * priority 0 and bit 7 represents priority 7.
16643 * # A value of 0 indicates that the priority is not configurable by
16644 * the hwrm_queue_pfcenable_cfg command.
16645 * # A value of 1 indicates that the priority is configurable.
16646 * # A hwrm_queue_pfcenable_cfg command shall return error when
16647 * trying to configure a priority that is not configurable.
16649 uint8_t queue_pfcenable_cfg_allowed;
16651 * Bitmask indicating which queues can be configured by the
16652 * hwrm_queue_pri2cos_cfg command.
16654 * Each bit represents a specific queue where bit 0 represents
16655 * queue 0 and bit 7 represents queue 7.
16656 * # A value of 0 indicates that the queue is not configurable
16657 * by the hwrm_queue_pri2cos_cfg command.
16658 * # A value of 1 indicates that the queue is configurable.
16659 * # A hwrm_queue_pri2cos_cfg command shall return error when
16660 * trying to configure a queue that is not configurable.
16662 uint8_t queue_pri2cos_cfg_allowed;
16664 * Bitmask indicating which queues can be configured by the
16665 * hwrm_queue_pri2cos_cfg command.
16667 * Each bit represents a specific queue where bit 0 represents
16668 * queue 0 and bit 7 represents queue 7.
16669 * # A value of 0 indicates that the queue is not configurable
16670 * by the hwrm_queue_pri2cos_cfg command.
16671 * # A value of 1 indicates that the queue is configurable.
16672 * # A hwrm_queue_pri2cos_cfg command shall return error when
16673 * trying to configure a queue not configurable.
16675 uint8_t queue_cos2bw_cfg_allowed;
16677 * ID of CoS Queue 0.
16680 * # This ID can be used on any subsequent call to an hwrm command
16681 * that takes a queue id.
16682 * # IDs must always be queried by this command before any use
16683 * by the driver or software.
16684 * # Any driver or software should not make any assumptions about
16686 * # A value of 0xff indicates that the queue is not available.
16687 * # Available queues may not be in sequential order.
16690 /* This value is applicable to CoS queues only. */
16691 uint8_t queue_id0_service_profile;
16692 /* Lossy (best-effort) */
16693 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
16695 /* Lossless (legacy) */
16696 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
16698 /* Lossless RoCE */
16699 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
16701 /* Lossy RoCE CNP */
16702 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16705 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
16707 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16708 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
16710 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
16711 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
16713 * ID of CoS Queue 1.
16716 * # This ID can be used on any subsequent call to an hwrm command
16717 * that takes a queue id.
16718 * # IDs must always be queried by this command before any use
16719 * by the driver or software.
16720 * # Any driver or software should not make any assumptions about
16722 * # A value of 0xff indicates that the queue is not available.
16723 * # Available queues may not be in sequential order.
16726 /* This value is applicable to CoS queues only. */
16727 uint8_t queue_id1_service_profile;
16728 /* Lossy (best-effort) */
16729 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
16731 /* Lossless (legacy) */
16732 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
16734 /* Lossless RoCE */
16735 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
16737 /* Lossy RoCE CNP */
16738 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16741 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
16743 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16744 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
16746 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
16747 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
16749 * ID of CoS Queue 2.
16752 * # This ID can be used on any subsequent call to an hwrm command
16753 * that takes a queue id.
16754 * # IDs must always be queried by this command before any use
16755 * by the driver or software.
16756 * # Any driver or software should not make any assumptions about
16758 * # A value of 0xff indicates that the queue is not available.
16759 * # Available queues may not be in sequential order.
16762 /* This value is applicable to CoS queues only. */
16763 uint8_t queue_id2_service_profile;
16764 /* Lossy (best-effort) */
16765 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
16767 /* Lossless (legacy) */
16768 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
16770 /* Lossless RoCE */
16771 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
16773 /* Lossy RoCE CNP */
16774 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16777 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
16779 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16780 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
16782 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
16783 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
16785 * ID of CoS Queue 3.
16788 * # This ID can be used on any subsequent call to an hwrm command
16789 * that takes a queue id.
16790 * # IDs must always be queried by this command before any use
16791 * by the driver or software.
16792 * # Any driver or software should not make any assumptions about
16794 * # A value of 0xff indicates that the queue is not available.
16795 * # Available queues may not be in sequential order.
16798 /* This value is applicable to CoS queues only. */
16799 uint8_t queue_id3_service_profile;
16800 /* Lossy (best-effort) */
16801 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
16803 /* Lossless (legacy) */
16804 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
16806 /* Lossless RoCE */
16807 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
16809 /* Lossy RoCE CNP */
16810 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16813 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
16815 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16816 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
16818 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
16819 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
16821 * ID of CoS Queue 4.
16824 * # This ID can be used on any subsequent call to an hwrm command
16825 * that takes a queue id.
16826 * # IDs must always be queried by this command before any use
16827 * by the driver or software.
16828 * # Any driver or software should not make any assumptions about
16830 * # A value of 0xff indicates that the queue is not available.
16831 * # Available queues may not be in sequential order.
16834 /* This value is applicable to CoS queues only. */
16835 uint8_t queue_id4_service_profile;
16836 /* Lossy (best-effort) */
16837 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
16839 /* Lossless (legacy) */
16840 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
16842 /* Lossless RoCE */
16843 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
16845 /* Lossy RoCE CNP */
16846 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16849 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
16851 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16852 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
16854 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
16855 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
16857 * ID of CoS Queue 5.
16860 * # This ID can be used on any subsequent call to an hwrm command
16861 * that takes a queue id.
16862 * # IDs must always be queried by this command before any use
16863 * by the driver or software.
16864 * # Any driver or software should not make any assumptions about
16866 * # A value of 0xff indicates that the queue is not available.
16867 * # Available queues may not be in sequential order.
16870 /* This value is applicable to CoS queues only. */
16871 uint8_t queue_id5_service_profile;
16872 /* Lossy (best-effort) */
16873 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
16875 /* Lossless (legacy) */
16876 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
16878 /* Lossless RoCE */
16879 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
16881 /* Lossy RoCE CNP */
16882 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16885 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
16887 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16888 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
16890 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
16891 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
16893 * ID of CoS Queue 6.
16896 * # This ID can be used on any subsequent call to an hwrm command
16897 * that takes a queue id.
16898 * # IDs must always be queried by this command before any use
16899 * by the driver or software.
16900 * # Any driver or software should not make any assumptions about
16902 * # A value of 0xff indicates that the queue is not available.
16903 * # Available queues may not be in sequential order.
16906 /* This value is applicable to CoS queues only. */
16907 uint8_t queue_id6_service_profile;
16908 /* Lossy (best-effort) */
16909 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
16911 /* Lossless (legacy) */
16912 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
16914 /* Lossless RoCE */
16915 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
16917 /* Lossy RoCE CNP */
16918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16921 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
16923 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16924 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
16926 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
16927 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
16929 * ID of CoS Queue 7.
16932 * # This ID can be used on any subsequent call to an hwrm command
16933 * that takes a queue id.
16934 * # IDs must always be queried by this command before any use
16935 * by the driver or software.
16936 * # Any driver or software should not make any assumptions about
16938 * # A value of 0xff indicates that the queue is not available.
16939 * # Available queues may not be in sequential order.
16942 /* This value is applicable to CoS queues only. */
16943 uint8_t queue_id7_service_profile;
16944 /* Lossy (best-effort) */
16945 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
16947 /* Lossless (legacy) */
16948 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
16950 /* Lossless RoCE */
16951 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
16953 /* Lossy RoCE CNP */
16954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
16957 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
16959 /* Set to 0xFF... (All Fs) if there is no service profile specified */
16960 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
16962 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
16963 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
16965 * This field is used in Output records to indicate that the output
16966 * is completely written to RAM. This field should be read as '1'
16967 * to indicate that the output has been completely written.
16968 * When writing a command completion or response to an internal processor,
16969 * the order of writes has to be such that this field is written last.
16972 } __attribute__((packed));
16974 /*******************
16975 * hwrm_queue_qcfg *
16976 *******************/
16979 /* hwrm_queue_qcfg_input (size:192b/24B) */
16980 struct hwrm_queue_qcfg_input {
16981 /* The HWRM command request type. */
16984 * The completion ring to send the completion event on. This should
16985 * be the NQ ID returned from the `nq_alloc` HWRM command.
16987 uint16_t cmpl_ring;
16989 * The sequence ID is used by the driver for tracking multiple
16990 * commands. This ID is treated as opaque data by the firmware and
16991 * the value is returned in the `hwrm_resp_hdr` upon completion.
16995 * The target ID of the command:
16996 * * 0x0-0xFFF8 - The function ID
16997 * * 0xFFF8-0xFFFE - Reserved for internal processors
17000 uint16_t target_id;
17002 * A physical address pointer pointing to a host buffer that the
17003 * command's response data will be written. This can be either a host
17004 * physical address (HPA) or a guest physical address (GPA) and must
17005 * point to a physically contiguous block of memory.
17007 uint64_t resp_addr;
17010 * Enumeration denoting the RX, TX type of the resource.
17011 * This enumeration is used for resources that are similar for both
17012 * TX and RX paths of the chip.
17014 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17016 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17018 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17019 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
17020 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
17021 /* Queue ID of the queue. */
17023 } __attribute__((packed));
17025 /* hwrm_queue_qcfg_output (size:128b/16B) */
17026 struct hwrm_queue_qcfg_output {
17027 /* The specific error status for the command. */
17028 uint16_t error_code;
17029 /* The HWRM command request type. */
17031 /* The sequence ID from the original command. */
17033 /* The length of the response data in number of bytes. */
17036 * This value is a the estimate packet length used in the
17039 uint32_t queue_len;
17040 /* This value is applicable to CoS queues only. */
17041 uint8_t service_profile;
17042 /* Lossy (best-effort) */
17043 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
17045 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
17046 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17047 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
17048 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
17049 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
17050 /* Information about queue configuration. */
17051 uint8_t queue_cfg_info;
17053 * If this flag is set to '1', then the queue is
17054 * configured asymmetrically on TX and RX sides.
17055 * If this flag is set to '0', then this queue is
17056 * configured symmetrically on TX and RX sides.
17058 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17062 * This field is used in Output records to indicate that the output
17063 * is completely written to RAM. This field should be read as '1'
17064 * to indicate that the output has been completely written.
17065 * When writing a command completion or response to an internal processor,
17066 * the order of writes has to be such that this field is written last.
17069 } __attribute__((packed));
17071 /******************
17073 ******************/
17076 /* hwrm_queue_cfg_input (size:320b/40B) */
17077 struct hwrm_queue_cfg_input {
17078 /* The HWRM command request type. */
17081 * The completion ring to send the completion event on. This should
17082 * be the NQ ID returned from the `nq_alloc` HWRM command.
17084 uint16_t cmpl_ring;
17086 * The sequence ID is used by the driver for tracking multiple
17087 * commands. This ID is treated as opaque data by the firmware and
17088 * the value is returned in the `hwrm_resp_hdr` upon completion.
17092 * The target ID of the command:
17093 * * 0x0-0xFFF8 - The function ID
17094 * * 0xFFF8-0xFFFE - Reserved for internal processors
17097 uint16_t target_id;
17099 * A physical address pointer pointing to a host buffer that the
17100 * command's response data will be written. This can be either a host
17101 * physical address (HPA) or a guest physical address (GPA) and must
17102 * point to a physically contiguous block of memory.
17104 uint64_t resp_addr;
17107 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
17108 * This enumeration is used for resources that are similar for both
17109 * TX and RX paths of the chip.
17111 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
17112 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
17114 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17116 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17117 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
17118 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
17119 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
17120 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
17123 * This bit must be '1' for the dflt_len field to be
17126 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
17128 * This bit must be '1' for the service_profile field to be
17131 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
17132 /* Queue ID of queue that is to be configured by this function. */
17135 * This value is a the estimate packet length used in the
17137 * Set to 0xFF... (All Fs) to not adjust this value.
17140 /* This value is applicable to CoS queues only. */
17141 uint8_t service_profile;
17142 /* Lossy (best-effort) */
17143 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
17145 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
17146 /* Set to 0xFF... (All Fs) if there is no service profile specified */
17147 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
17148 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
17149 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
17150 uint8_t unused_0[7];
17151 } __attribute__((packed));
17153 /* hwrm_queue_cfg_output (size:128b/16B) */
17154 struct hwrm_queue_cfg_output {
17155 /* The specific error status for the command. */
17156 uint16_t error_code;
17157 /* The HWRM command request type. */
17159 /* The sequence ID from the original command. */
17161 /* The length of the response data in number of bytes. */
17163 uint8_t unused_0[7];
17165 * This field is used in Output records to indicate that the output
17166 * is completely written to RAM. This field should be read as '1'
17167 * to indicate that the output has been completely written.
17168 * When writing a command completion or response to an internal processor,
17169 * the order of writes has to be such that this field is written last.
17172 } __attribute__((packed));
17174 /*****************************
17175 * hwrm_queue_pfcenable_qcfg *
17176 *****************************/
17179 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
17180 struct hwrm_queue_pfcenable_qcfg_input {
17181 /* The HWRM command request type. */
17184 * The completion ring to send the completion event on. This should
17185 * be the NQ ID returned from the `nq_alloc` HWRM command.
17187 uint16_t cmpl_ring;
17189 * The sequence ID is used by the driver for tracking multiple
17190 * commands. This ID is treated as opaque data by the firmware and
17191 * the value is returned in the `hwrm_resp_hdr` upon completion.
17195 * The target ID of the command:
17196 * * 0x0-0xFFF8 - The function ID
17197 * * 0xFFF8-0xFFFE - Reserved for internal processors
17200 uint16_t target_id;
17202 * A physical address pointer pointing to a host buffer that the
17203 * command's response data will be written. This can be either a host
17204 * physical address (HPA) or a guest physical address (GPA) and must
17205 * point to a physically contiguous block of memory.
17207 uint64_t resp_addr;
17209 * Port ID of port for which the table is being configured.
17210 * The HWRM needs to check whether this function is allowed
17211 * to configure pri2cos mapping on this port.
17214 uint8_t unused_0[6];
17215 } __attribute__((packed));
17217 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
17218 struct hwrm_queue_pfcenable_qcfg_output {
17219 /* The specific error status for the command. */
17220 uint16_t error_code;
17221 /* The HWRM command request type. */
17223 /* The sequence ID from the original command. */
17225 /* The length of the response data in number of bytes. */
17228 /* If set to 1, then PFC is enabled on PRI 0. */
17229 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
17231 /* If set to 1, then PFC is enabled on PRI 1. */
17232 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
17234 /* If set to 1, then PFC is enabled on PRI 2. */
17235 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
17237 /* If set to 1, then PFC is enabled on PRI 3. */
17238 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
17240 /* If set to 1, then PFC is enabled on PRI 4. */
17241 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
17243 /* If set to 1, then PFC is enabled on PRI 5. */
17244 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
17246 /* If set to 1, then PFC is enabled on PRI 6. */
17247 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
17249 /* If set to 1, then PFC is enabled on PRI 7. */
17250 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
17252 uint8_t unused_0[3];
17254 * This field is used in Output records to indicate that the output
17255 * is completely written to RAM. This field should be read as '1'
17256 * to indicate that the output has been completely written.
17257 * When writing a command completion or response to an internal processor,
17258 * the order of writes has to be such that this field is written last.
17261 } __attribute__((packed));
17263 /****************************
17264 * hwrm_queue_pfcenable_cfg *
17265 ****************************/
17268 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
17269 struct hwrm_queue_pfcenable_cfg_input {
17270 /* The HWRM command request type. */
17273 * The completion ring to send the completion event on. This should
17274 * be the NQ ID returned from the `nq_alloc` HWRM command.
17276 uint16_t cmpl_ring;
17278 * The sequence ID is used by the driver for tracking multiple
17279 * commands. This ID is treated as opaque data by the firmware and
17280 * the value is returned in the `hwrm_resp_hdr` upon completion.
17284 * The target ID of the command:
17285 * * 0x0-0xFFF8 - The function ID
17286 * * 0xFFF8-0xFFFE - Reserved for internal processors
17289 uint16_t target_id;
17291 * A physical address pointer pointing to a host buffer that the
17292 * command's response data will be written. This can be either a host
17293 * physical address (HPA) or a guest physical address (GPA) and must
17294 * point to a physically contiguous block of memory.
17296 uint64_t resp_addr;
17298 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
17299 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
17301 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
17302 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
17304 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
17305 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
17307 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
17308 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
17310 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
17311 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
17313 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
17314 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
17316 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
17317 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
17319 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
17320 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
17323 * Port ID of port for which the table is being configured.
17324 * The HWRM needs to check whether this function is allowed
17325 * to configure pri2cos mapping on this port.
17328 uint8_t unused_0[2];
17329 } __attribute__((packed));
17331 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
17332 struct hwrm_queue_pfcenable_cfg_output {
17333 /* The specific error status for the command. */
17334 uint16_t error_code;
17335 /* The HWRM command request type. */
17337 /* The sequence ID from the original command. */
17339 /* The length of the response data in number of bytes. */
17341 uint8_t unused_0[7];
17343 * This field is used in Output records to indicate that the output
17344 * is completely written to RAM. This field should be read as '1'
17345 * to indicate that the output has been completely written.
17346 * When writing a command completion or response to an internal processor,
17347 * the order of writes has to be such that this field is written last.
17350 } __attribute__((packed));
17352 /***************************
17353 * hwrm_queue_pri2cos_qcfg *
17354 ***************************/
17357 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
17358 struct hwrm_queue_pri2cos_qcfg_input {
17359 /* The HWRM command request type. */
17362 * The completion ring to send the completion event on. This should
17363 * be the NQ ID returned from the `nq_alloc` HWRM command.
17365 uint16_t cmpl_ring;
17367 * The sequence ID is used by the driver for tracking multiple
17368 * commands. This ID is treated as opaque data by the firmware and
17369 * the value is returned in the `hwrm_resp_hdr` upon completion.
17373 * The target ID of the command:
17374 * * 0x0-0xFFF8 - The function ID
17375 * * 0xFFF8-0xFFFE - Reserved for internal processors
17378 uint16_t target_id;
17380 * A physical address pointer pointing to a host buffer that the
17381 * command's response data will be written. This can be either a host
17382 * physical address (HPA) or a guest physical address (GPA) and must
17383 * point to a physically contiguous block of memory.
17385 uint64_t resp_addr;
17388 * Enumeration denoting the RX, TX type of the resource.
17389 * This enumeration is used for resources that are similar for both
17390 * TX and RX paths of the chip.
17392 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17394 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17396 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17397 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
17398 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
17400 * When this bit is set to '0', the query is
17401 * for VLAN PRI field in tunnel headers.
17402 * When this bit is set to '1', the query is
17403 * for VLAN PRI field in inner packet headers.
17405 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
17407 * Port ID of port for which the table is being configured.
17408 * The HWRM needs to check whether this function is allowed
17409 * to configure pri2cos mapping on this port.
17412 uint8_t unused_0[3];
17413 } __attribute__((packed));
17415 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
17416 struct hwrm_queue_pri2cos_qcfg_output {
17417 /* The specific error status for the command. */
17418 uint16_t error_code;
17419 /* The HWRM command request type. */
17421 /* The sequence ID from the original command. */
17423 /* The length of the response data in number of bytes. */
17426 * CoS Queue assigned to priority 0. This value can only
17427 * be changed before traffic has started.
17428 * A value of 0xff indicates that no CoS queue is assigned to the
17429 * specified priority.
17431 uint8_t pri0_cos_queue_id;
17433 * CoS Queue assigned to priority 1. This value can only
17434 * be changed before traffic has started.
17435 * A value of 0xff indicates that no CoS queue is assigned to the
17436 * specified priority.
17438 uint8_t pri1_cos_queue_id;
17440 * CoS Queue assigned to priority 2 This value can only
17441 * be changed before traffic has started.
17442 * A value of 0xff indicates that no CoS queue is assigned to the
17443 * specified priority.
17445 uint8_t pri2_cos_queue_id;
17447 * CoS Queue assigned to priority 3. This value can only
17448 * be changed before traffic has started.
17449 * A value of 0xff indicates that no CoS queue is assigned to the
17450 * specified priority.
17452 uint8_t pri3_cos_queue_id;
17454 * CoS Queue assigned to priority 4. This value can only
17455 * be changed before traffic has started.
17456 * A value of 0xff indicates that no CoS queue is assigned to the
17457 * specified priority.
17459 uint8_t pri4_cos_queue_id;
17461 * CoS Queue assigned to priority 5. This value can only
17462 * be changed before traffic has started.
17463 * A value of 0xff indicates that no CoS queue is assigned to the
17464 * specified priority.
17466 uint8_t pri5_cos_queue_id;
17468 * CoS Queue assigned to priority 6. This value can only
17469 * be changed before traffic has started.
17470 * A value of 0xff indicates that no CoS queue is assigned to the
17471 * specified priority.
17473 uint8_t pri6_cos_queue_id;
17475 * CoS Queue assigned to priority 7. This value can only
17476 * be changed before traffic has started.
17477 * A value of 0xff indicates that no CoS queue is assigned to the
17478 * specified priority.
17480 uint8_t pri7_cos_queue_id;
17481 /* Information about queue configuration. */
17482 uint8_t queue_cfg_info;
17484 * If this flag is set to '1', then the PRI to CoS
17485 * configuration is asymmetric on TX and RX sides.
17486 * If this flag is set to '0', then PRI to CoS configuration
17487 * is symmetric on TX and RX sides.
17489 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
17491 uint8_t unused_0[6];
17493 * This field is used in Output records to indicate that the output
17494 * is completely written to RAM. This field should be read as '1'
17495 * to indicate that the output has been completely written.
17496 * When writing a command completion or response to an internal processor,
17497 * the order of writes has to be such that this field is written last.
17500 } __attribute__((packed));
17502 /**************************
17503 * hwrm_queue_pri2cos_cfg *
17504 **************************/
17507 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
17508 struct hwrm_queue_pri2cos_cfg_input {
17509 /* The HWRM command request type. */
17512 * The completion ring to send the completion event on. This should
17513 * be the NQ ID returned from the `nq_alloc` HWRM command.
17515 uint16_t cmpl_ring;
17517 * The sequence ID is used by the driver for tracking multiple
17518 * commands. This ID is treated as opaque data by the firmware and
17519 * the value is returned in the `hwrm_resp_hdr` upon completion.
17523 * The target ID of the command:
17524 * * 0x0-0xFFF8 - The function ID
17525 * * 0xFFF8-0xFFFE - Reserved for internal processors
17528 uint16_t target_id;
17530 * A physical address pointer pointing to a host buffer that the
17531 * command's response data will be written. This can be either a host
17532 * physical address (HPA) or a guest physical address (GPA) and must
17533 * point to a physically contiguous block of memory.
17535 uint64_t resp_addr;
17538 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
17539 * This enumeration is used for resources that are similar for both
17540 * TX and RX paths of the chip.
17542 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
17543 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
17545 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
17547 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
17548 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
17549 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
17550 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
17551 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
17553 * When this bit is set to '0', the mapping is requested
17554 * for VLAN PRI field in tunnel headers.
17555 * When this bit is set to '1', the mapping is requested
17556 * for VLAN PRI field in inner packet headers.
17558 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
17561 * This bit must be '1' for the pri0_cos_queue_id field to be
17564 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
17567 * This bit must be '1' for the pri1_cos_queue_id field to be
17570 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
17573 * This bit must be '1' for the pri2_cos_queue_id field to be
17576 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
17579 * This bit must be '1' for the pri3_cos_queue_id field to be
17582 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
17585 * This bit must be '1' for the pri4_cos_queue_id field to be
17588 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
17591 * This bit must be '1' for the pri5_cos_queue_id field to be
17594 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
17597 * This bit must be '1' for the pri6_cos_queue_id field to be
17600 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
17603 * This bit must be '1' for the pri7_cos_queue_id field to be
17606 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
17609 * Port ID of port for which the table is being configured.
17610 * The HWRM needs to check whether this function is allowed
17611 * to configure pri2cos mapping on this port.
17615 * CoS Queue assigned to priority 0. This value can only
17616 * be changed before traffic has started.
17618 uint8_t pri0_cos_queue_id;
17620 * CoS Queue assigned to priority 1. This value can only
17621 * be changed before traffic has started.
17623 uint8_t pri1_cos_queue_id;
17625 * CoS Queue assigned to priority 2 This value can only
17626 * be changed before traffic has started.
17628 uint8_t pri2_cos_queue_id;
17630 * CoS Queue assigned to priority 3. This value can only
17631 * be changed before traffic has started.
17633 uint8_t pri3_cos_queue_id;
17635 * CoS Queue assigned to priority 4. This value can only
17636 * be changed before traffic has started.
17638 uint8_t pri4_cos_queue_id;
17640 * CoS Queue assigned to priority 5. This value can only
17641 * be changed before traffic has started.
17643 uint8_t pri5_cos_queue_id;
17645 * CoS Queue assigned to priority 6. This value can only
17646 * be changed before traffic has started.
17648 uint8_t pri6_cos_queue_id;
17650 * CoS Queue assigned to priority 7. This value can only
17651 * be changed before traffic has started.
17653 uint8_t pri7_cos_queue_id;
17654 uint8_t unused_0[7];
17655 } __attribute__((packed));
17657 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
17658 struct hwrm_queue_pri2cos_cfg_output {
17659 /* The specific error status for the command. */
17660 uint16_t error_code;
17661 /* The HWRM command request type. */
17663 /* The sequence ID from the original command. */
17665 /* The length of the response data in number of bytes. */
17667 uint8_t unused_0[7];
17669 * This field is used in Output records to indicate that the output
17670 * is completely written to RAM. This field should be read as '1'
17671 * to indicate that the output has been completely written.
17672 * When writing a command completion or response to an internal processor,
17673 * the order of writes has to be such that this field is written last.
17676 } __attribute__((packed));
17678 /**************************
17679 * hwrm_queue_cos2bw_qcfg *
17680 **************************/
17683 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
17684 struct hwrm_queue_cos2bw_qcfg_input {
17685 /* The HWRM command request type. */
17688 * The completion ring to send the completion event on. This should
17689 * be the NQ ID returned from the `nq_alloc` HWRM command.
17691 uint16_t cmpl_ring;
17693 * The sequence ID is used by the driver for tracking multiple
17694 * commands. This ID is treated as opaque data by the firmware and
17695 * the value is returned in the `hwrm_resp_hdr` upon completion.
17699 * The target ID of the command:
17700 * * 0x0-0xFFF8 - The function ID
17701 * * 0xFFF8-0xFFFE - Reserved for internal processors
17704 uint16_t target_id;
17706 * A physical address pointer pointing to a host buffer that the
17707 * command's response data will be written. This can be either a host
17708 * physical address (HPA) or a guest physical address (GPA) and must
17709 * point to a physically contiguous block of memory.
17711 uint64_t resp_addr;
17713 * Port ID of port for which the table is being configured.
17714 * The HWRM needs to check whether this function is allowed
17715 * to configure TC BW assignment on this port.
17718 uint8_t unused_0[6];
17719 } __attribute__((packed));
17721 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
17722 struct hwrm_queue_cos2bw_qcfg_output {
17723 /* The specific error status for the command. */
17724 uint16_t error_code;
17725 /* The HWRM command request type. */
17727 /* The sequence ID from the original command. */
17729 /* The length of the response data in number of bytes. */
17731 /* ID of CoS Queue 0. */
17736 * Minimum BW allocated to CoS Queue.
17737 * The HWRM will translate this value into byte counter and
17738 * time interval used for this COS inside the device.
17740 uint32_t queue_id0_min_bw;
17741 /* The bandwidth value. */
17742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
17743 UINT32_C(0xfffffff)
17744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
17746 /* The granularity of the value (bits or bytes). */
17747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
17748 UINT32_C(0x10000000)
17749 /* Value is in bits. */
17750 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
17751 (UINT32_C(0x0) << 28)
17752 /* Value is in bytes. */
17753 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
17754 (UINT32_C(0x1) << 28)
17755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
17756 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
17757 /* bw_value_unit is 3 b */
17758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
17759 UINT32_C(0xe0000000)
17760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
17762 /* Value is in Mb or MB (base 10). */
17763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
17764 (UINT32_C(0x0) << 29)
17765 /* Value is in Kb or KB (base 10). */
17766 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
17767 (UINT32_C(0x2) << 29)
17768 /* Value is in bits or bytes. */
17769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
17770 (UINT32_C(0x4) << 29)
17771 /* Value is in Gb or GB (base 10). */
17772 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
17773 (UINT32_C(0x6) << 29)
17774 /* Value is in 1/100th of a percentage of total bandwidth. */
17775 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17776 (UINT32_C(0x1) << 29)
17778 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
17779 (UINT32_C(0x7) << 29)
17780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
17781 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
17783 * Maximum BW allocated to CoS Queue.
17784 * The HWRM will translate this value into byte counter and
17785 * time interval used for this COS inside the device.
17787 uint32_t queue_id0_max_bw;
17788 /* The bandwidth value. */
17789 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
17790 UINT32_C(0xfffffff)
17791 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
17793 /* The granularity of the value (bits or bytes). */
17794 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
17795 UINT32_C(0x10000000)
17796 /* Value is in bits. */
17797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
17798 (UINT32_C(0x0) << 28)
17799 /* Value is in bytes. */
17800 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
17801 (UINT32_C(0x1) << 28)
17802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
17803 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
17804 /* bw_value_unit is 3 b */
17805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
17806 UINT32_C(0xe0000000)
17807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
17809 /* Value is in Mb or MB (base 10). */
17810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
17811 (UINT32_C(0x0) << 29)
17812 /* Value is in Kb or KB (base 10). */
17813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
17814 (UINT32_C(0x2) << 29)
17815 /* Value is in bits or bytes. */
17816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
17817 (UINT32_C(0x4) << 29)
17818 /* Value is in Gb or GB (base 10). */
17819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
17820 (UINT32_C(0x6) << 29)
17821 /* Value is in 1/100th of a percentage of total bandwidth. */
17822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17823 (UINT32_C(0x1) << 29)
17825 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
17826 (UINT32_C(0x7) << 29)
17827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
17828 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
17829 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17830 uint8_t queue_id0_tsa_assign;
17831 /* Strict Priority */
17832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
17834 /* Enhanced Transmission Selection */
17835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
17838 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
17841 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
17844 * Priority level for strict priority. Valid only when the
17845 * tsa_assign is 0 - Strict Priority (SP)
17846 * 0..7 - Valid values.
17847 * 8..255 - Reserved.
17849 uint8_t queue_id0_pri_lvl;
17851 * Weight used to allocate remaining BW for this COS after
17852 * servicing guaranteed bandwidths for all COS.
17854 uint8_t queue_id0_bw_weight;
17855 /* ID of CoS Queue 1. */
17858 * Minimum BW allocated to CoS Queue.
17859 * The HWRM will translate this value into byte counter and
17860 * time interval used for this COS inside the device.
17862 uint32_t queue_id1_min_bw;
17863 /* The bandwidth value. */
17864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
17865 UINT32_C(0xfffffff)
17866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
17868 /* The granularity of the value (bits or bytes). */
17869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
17870 UINT32_C(0x10000000)
17871 /* Value is in bits. */
17872 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
17873 (UINT32_C(0x0) << 28)
17874 /* Value is in bytes. */
17875 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
17876 (UINT32_C(0x1) << 28)
17877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
17878 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
17879 /* bw_value_unit is 3 b */
17880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
17881 UINT32_C(0xe0000000)
17882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
17884 /* Value is in Mb or MB (base 10). */
17885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
17886 (UINT32_C(0x0) << 29)
17887 /* Value is in Kb or KB (base 10). */
17888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
17889 (UINT32_C(0x2) << 29)
17890 /* Value is in bits or bytes. */
17891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
17892 (UINT32_C(0x4) << 29)
17893 /* Value is in Gb or GB (base 10). */
17894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
17895 (UINT32_C(0x6) << 29)
17896 /* Value is in 1/100th of a percentage of total bandwidth. */
17897 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17898 (UINT32_C(0x1) << 29)
17900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
17901 (UINT32_C(0x7) << 29)
17902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
17903 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
17905 * Maximum BW allocated to CoS queue.
17906 * The HWRM will translate this value into byte counter and
17907 * time interval used for this COS inside the device.
17909 uint32_t queue_id1_max_bw;
17910 /* The bandwidth value. */
17911 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
17912 UINT32_C(0xfffffff)
17913 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
17915 /* The granularity of the value (bits or bytes). */
17916 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
17917 UINT32_C(0x10000000)
17918 /* Value is in bits. */
17919 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
17920 (UINT32_C(0x0) << 28)
17921 /* Value is in bytes. */
17922 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
17923 (UINT32_C(0x1) << 28)
17924 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
17925 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
17926 /* bw_value_unit is 3 b */
17927 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
17928 UINT32_C(0xe0000000)
17929 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
17931 /* Value is in Mb or MB (base 10). */
17932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
17933 (UINT32_C(0x0) << 29)
17934 /* Value is in Kb or KB (base 10). */
17935 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
17936 (UINT32_C(0x2) << 29)
17937 /* Value is in bits or bytes. */
17938 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
17939 (UINT32_C(0x4) << 29)
17940 /* Value is in Gb or GB (base 10). */
17941 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
17942 (UINT32_C(0x6) << 29)
17943 /* Value is in 1/100th of a percentage of total bandwidth. */
17944 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17945 (UINT32_C(0x1) << 29)
17947 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
17948 (UINT32_C(0x7) << 29)
17949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
17950 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
17951 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17952 uint8_t queue_id1_tsa_assign;
17953 /* Strict Priority */
17954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
17956 /* Enhanced Transmission Selection */
17957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
17960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
17963 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
17966 * Priority level for strict priority. Valid only when the
17967 * tsa_assign is 0 - Strict Priority (SP)
17968 * 0..7 - Valid values.
17969 * 8..255 - Reserved.
17971 uint8_t queue_id1_pri_lvl;
17973 * Weight used to allocate remaining BW for this COS after
17974 * servicing guaranteed bandwidths for all COS.
17976 uint8_t queue_id1_bw_weight;
17977 /* ID of CoS Queue 2. */
17980 * Minimum BW allocated to CoS Queue.
17981 * The HWRM will translate this value into byte counter and
17982 * time interval used for this COS inside the device.
17984 uint32_t queue_id2_min_bw;
17985 /* The bandwidth value. */
17986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
17987 UINT32_C(0xfffffff)
17988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
17990 /* The granularity of the value (bits or bytes). */
17991 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
17992 UINT32_C(0x10000000)
17993 /* Value is in bits. */
17994 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
17995 (UINT32_C(0x0) << 28)
17996 /* Value is in bytes. */
17997 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
17998 (UINT32_C(0x1) << 28)
17999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
18000 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
18001 /* bw_value_unit is 3 b */
18002 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
18003 UINT32_C(0xe0000000)
18004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
18006 /* Value is in Mb or MB (base 10). */
18007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
18008 (UINT32_C(0x0) << 29)
18009 /* Value is in Kb or KB (base 10). */
18010 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
18011 (UINT32_C(0x2) << 29)
18012 /* Value is in bits or bytes. */
18013 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
18014 (UINT32_C(0x4) << 29)
18015 /* Value is in Gb or GB (base 10). */
18016 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
18017 (UINT32_C(0x6) << 29)
18018 /* Value is in 1/100th of a percentage of total bandwidth. */
18019 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18020 (UINT32_C(0x1) << 29)
18022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
18023 (UINT32_C(0x7) << 29)
18024 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
18025 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
18027 * Maximum BW allocated to CoS queue.
18028 * The HWRM will translate this value into byte counter and
18029 * time interval used for this COS inside the device.
18031 uint32_t queue_id2_max_bw;
18032 /* The bandwidth value. */
18033 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
18034 UINT32_C(0xfffffff)
18035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
18037 /* The granularity of the value (bits or bytes). */
18038 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
18039 UINT32_C(0x10000000)
18040 /* Value is in bits. */
18041 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
18042 (UINT32_C(0x0) << 28)
18043 /* Value is in bytes. */
18044 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
18045 (UINT32_C(0x1) << 28)
18046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
18047 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
18048 /* bw_value_unit is 3 b */
18049 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
18050 UINT32_C(0xe0000000)
18051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
18053 /* Value is in Mb or MB (base 10). */
18054 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
18055 (UINT32_C(0x0) << 29)
18056 /* Value is in Kb or KB (base 10). */
18057 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
18058 (UINT32_C(0x2) << 29)
18059 /* Value is in bits or bytes. */
18060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
18061 (UINT32_C(0x4) << 29)
18062 /* Value is in Gb or GB (base 10). */
18063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
18064 (UINT32_C(0x6) << 29)
18065 /* Value is in 1/100th of a percentage of total bandwidth. */
18066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18067 (UINT32_C(0x1) << 29)
18069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
18070 (UINT32_C(0x7) << 29)
18071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
18072 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
18073 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18074 uint8_t queue_id2_tsa_assign;
18075 /* Strict Priority */
18076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
18078 /* Enhanced Transmission Selection */
18079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
18082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
18085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
18088 * Priority level for strict priority. Valid only when the
18089 * tsa_assign is 0 - Strict Priority (SP)
18090 * 0..7 - Valid values.
18091 * 8..255 - Reserved.
18093 uint8_t queue_id2_pri_lvl;
18095 * Weight used to allocate remaining BW for this COS after
18096 * servicing guaranteed bandwidths for all COS.
18098 uint8_t queue_id2_bw_weight;
18099 /* ID of CoS Queue 3. */
18102 * Minimum BW allocated to CoS Queue.
18103 * The HWRM will translate this value into byte counter and
18104 * time interval used for this COS inside the device.
18106 uint32_t queue_id3_min_bw;
18107 /* The bandwidth value. */
18108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
18109 UINT32_C(0xfffffff)
18110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
18112 /* The granularity of the value (bits or bytes). */
18113 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
18114 UINT32_C(0x10000000)
18115 /* Value is in bits. */
18116 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
18117 (UINT32_C(0x0) << 28)
18118 /* Value is in bytes. */
18119 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
18120 (UINT32_C(0x1) << 28)
18121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
18122 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
18123 /* bw_value_unit is 3 b */
18124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
18125 UINT32_C(0xe0000000)
18126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
18128 /* Value is in Mb or MB (base 10). */
18129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
18130 (UINT32_C(0x0) << 29)
18131 /* Value is in Kb or KB (base 10). */
18132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
18133 (UINT32_C(0x2) << 29)
18134 /* Value is in bits or bytes. */
18135 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
18136 (UINT32_C(0x4) << 29)
18137 /* Value is in Gb or GB (base 10). */
18138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
18139 (UINT32_C(0x6) << 29)
18140 /* Value is in 1/100th of a percentage of total bandwidth. */
18141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18142 (UINT32_C(0x1) << 29)
18144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
18145 (UINT32_C(0x7) << 29)
18146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
18147 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
18149 * Maximum BW allocated to CoS queue.
18150 * The HWRM will translate this value into byte counter and
18151 * time interval used for this COS inside the device.
18153 uint32_t queue_id3_max_bw;
18154 /* The bandwidth value. */
18155 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
18156 UINT32_C(0xfffffff)
18157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
18159 /* The granularity of the value (bits or bytes). */
18160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
18161 UINT32_C(0x10000000)
18162 /* Value is in bits. */
18163 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
18164 (UINT32_C(0x0) << 28)
18165 /* Value is in bytes. */
18166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
18167 (UINT32_C(0x1) << 28)
18168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
18169 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
18170 /* bw_value_unit is 3 b */
18171 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
18172 UINT32_C(0xe0000000)
18173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
18175 /* Value is in Mb or MB (base 10). */
18176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
18177 (UINT32_C(0x0) << 29)
18178 /* Value is in Kb or KB (base 10). */
18179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
18180 (UINT32_C(0x2) << 29)
18181 /* Value is in bits or bytes. */
18182 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
18183 (UINT32_C(0x4) << 29)
18184 /* Value is in Gb or GB (base 10). */
18185 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
18186 (UINT32_C(0x6) << 29)
18187 /* Value is in 1/100th of a percentage of total bandwidth. */
18188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18189 (UINT32_C(0x1) << 29)
18191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
18192 (UINT32_C(0x7) << 29)
18193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
18194 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
18195 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18196 uint8_t queue_id3_tsa_assign;
18197 /* Strict Priority */
18198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
18200 /* Enhanced Transmission Selection */
18201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
18204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
18207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
18210 * Priority level for strict priority. Valid only when the
18211 * tsa_assign is 0 - Strict Priority (SP)
18212 * 0..7 - Valid values.
18213 * 8..255 - Reserved.
18215 uint8_t queue_id3_pri_lvl;
18217 * Weight used to allocate remaining BW for this COS after
18218 * servicing guaranteed bandwidths for all COS.
18220 uint8_t queue_id3_bw_weight;
18221 /* ID of CoS Queue 4. */
18224 * Minimum BW allocated to CoS Queue.
18225 * The HWRM will translate this value into byte counter and
18226 * time interval used for this COS inside the device.
18228 uint32_t queue_id4_min_bw;
18229 /* The bandwidth value. */
18230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
18231 UINT32_C(0xfffffff)
18232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
18234 /* The granularity of the value (bits or bytes). */
18235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
18236 UINT32_C(0x10000000)
18237 /* Value is in bits. */
18238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
18239 (UINT32_C(0x0) << 28)
18240 /* Value is in bytes. */
18241 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
18242 (UINT32_C(0x1) << 28)
18243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
18244 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
18245 /* bw_value_unit is 3 b */
18246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
18247 UINT32_C(0xe0000000)
18248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
18250 /* Value is in Mb or MB (base 10). */
18251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
18252 (UINT32_C(0x0) << 29)
18253 /* Value is in Kb or KB (base 10). */
18254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
18255 (UINT32_C(0x2) << 29)
18256 /* Value is in bits or bytes. */
18257 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
18258 (UINT32_C(0x4) << 29)
18259 /* Value is in Gb or GB (base 10). */
18260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
18261 (UINT32_C(0x6) << 29)
18262 /* Value is in 1/100th of a percentage of total bandwidth. */
18263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18264 (UINT32_C(0x1) << 29)
18266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
18267 (UINT32_C(0x7) << 29)
18268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
18269 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
18271 * Maximum BW allocated to CoS queue.
18272 * The HWRM will translate this value into byte counter and
18273 * time interval used for this COS inside the device.
18275 uint32_t queue_id4_max_bw;
18276 /* The bandwidth value. */
18277 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
18278 UINT32_C(0xfffffff)
18279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
18281 /* The granularity of the value (bits or bytes). */
18282 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
18283 UINT32_C(0x10000000)
18284 /* Value is in bits. */
18285 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
18286 (UINT32_C(0x0) << 28)
18287 /* Value is in bytes. */
18288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
18289 (UINT32_C(0x1) << 28)
18290 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
18291 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
18292 /* bw_value_unit is 3 b */
18293 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
18294 UINT32_C(0xe0000000)
18295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
18297 /* Value is in Mb or MB (base 10). */
18298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
18299 (UINT32_C(0x0) << 29)
18300 /* Value is in Kb or KB (base 10). */
18301 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
18302 (UINT32_C(0x2) << 29)
18303 /* Value is in bits or bytes. */
18304 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
18305 (UINT32_C(0x4) << 29)
18306 /* Value is in Gb or GB (base 10). */
18307 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
18308 (UINT32_C(0x6) << 29)
18309 /* Value is in 1/100th of a percentage of total bandwidth. */
18310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18311 (UINT32_C(0x1) << 29)
18313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
18314 (UINT32_C(0x7) << 29)
18315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
18316 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
18317 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18318 uint8_t queue_id4_tsa_assign;
18319 /* Strict Priority */
18320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
18322 /* Enhanced Transmission Selection */
18323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
18326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
18329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
18332 * Priority level for strict priority. Valid only when the
18333 * tsa_assign is 0 - Strict Priority (SP)
18334 * 0..7 - Valid values.
18335 * 8..255 - Reserved.
18337 uint8_t queue_id4_pri_lvl;
18339 * Weight used to allocate remaining BW for this COS after
18340 * servicing guaranteed bandwidths for all COS.
18342 uint8_t queue_id4_bw_weight;
18343 /* ID of CoS Queue 5. */
18346 * Minimum BW allocated to CoS Queue.
18347 * The HWRM will translate this value into byte counter and
18348 * time interval used for this COS inside the device.
18350 uint32_t queue_id5_min_bw;
18351 /* The bandwidth value. */
18352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
18353 UINT32_C(0xfffffff)
18354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
18356 /* The granularity of the value (bits or bytes). */
18357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
18358 UINT32_C(0x10000000)
18359 /* Value is in bits. */
18360 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
18361 (UINT32_C(0x0) << 28)
18362 /* Value is in bytes. */
18363 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
18364 (UINT32_C(0x1) << 28)
18365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
18366 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
18367 /* bw_value_unit is 3 b */
18368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
18369 UINT32_C(0xe0000000)
18370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
18372 /* Value is in Mb or MB (base 10). */
18373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
18374 (UINT32_C(0x0) << 29)
18375 /* Value is in Kb or KB (base 10). */
18376 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
18377 (UINT32_C(0x2) << 29)
18378 /* Value is in bits or bytes. */
18379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
18380 (UINT32_C(0x4) << 29)
18381 /* Value is in Gb or GB (base 10). */
18382 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
18383 (UINT32_C(0x6) << 29)
18384 /* Value is in 1/100th of a percentage of total bandwidth. */
18385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18386 (UINT32_C(0x1) << 29)
18388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
18389 (UINT32_C(0x7) << 29)
18390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
18391 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
18393 * Maximum BW allocated to CoS queue.
18394 * The HWRM will translate this value into byte counter and
18395 * time interval used for this COS inside the device.
18397 uint32_t queue_id5_max_bw;
18398 /* The bandwidth value. */
18399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
18400 UINT32_C(0xfffffff)
18401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
18403 /* The granularity of the value (bits or bytes). */
18404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
18405 UINT32_C(0x10000000)
18406 /* Value is in bits. */
18407 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
18408 (UINT32_C(0x0) << 28)
18409 /* Value is in bytes. */
18410 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
18411 (UINT32_C(0x1) << 28)
18412 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
18413 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
18414 /* bw_value_unit is 3 b */
18415 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
18416 UINT32_C(0xe0000000)
18417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
18419 /* Value is in Mb or MB (base 10). */
18420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
18421 (UINT32_C(0x0) << 29)
18422 /* Value is in Kb or KB (base 10). */
18423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
18424 (UINT32_C(0x2) << 29)
18425 /* Value is in bits or bytes. */
18426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
18427 (UINT32_C(0x4) << 29)
18428 /* Value is in Gb or GB (base 10). */
18429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
18430 (UINT32_C(0x6) << 29)
18431 /* Value is in 1/100th of a percentage of total bandwidth. */
18432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18433 (UINT32_C(0x1) << 29)
18435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
18436 (UINT32_C(0x7) << 29)
18437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
18438 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
18439 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18440 uint8_t queue_id5_tsa_assign;
18441 /* Strict Priority */
18442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
18444 /* Enhanced Transmission Selection */
18445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
18448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
18451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
18454 * Priority level for strict priority. Valid only when the
18455 * tsa_assign is 0 - Strict Priority (SP)
18456 * 0..7 - Valid values.
18457 * 8..255 - Reserved.
18459 uint8_t queue_id5_pri_lvl;
18461 * Weight used to allocate remaining BW for this COS after
18462 * servicing guaranteed bandwidths for all COS.
18464 uint8_t queue_id5_bw_weight;
18465 /* ID of CoS Queue 6. */
18468 * Minimum BW allocated to CoS Queue.
18469 * The HWRM will translate this value into byte counter and
18470 * time interval used for this COS inside the device.
18472 uint32_t queue_id6_min_bw;
18473 /* The bandwidth value. */
18474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
18475 UINT32_C(0xfffffff)
18476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
18478 /* The granularity of the value (bits or bytes). */
18479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
18480 UINT32_C(0x10000000)
18481 /* Value is in bits. */
18482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
18483 (UINT32_C(0x0) << 28)
18484 /* Value is in bytes. */
18485 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
18486 (UINT32_C(0x1) << 28)
18487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
18488 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
18489 /* bw_value_unit is 3 b */
18490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
18491 UINT32_C(0xe0000000)
18492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
18494 /* Value is in Mb or MB (base 10). */
18495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
18496 (UINT32_C(0x0) << 29)
18497 /* Value is in Kb or KB (base 10). */
18498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
18499 (UINT32_C(0x2) << 29)
18500 /* Value is in bits or bytes. */
18501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
18502 (UINT32_C(0x4) << 29)
18503 /* Value is in Gb or GB (base 10). */
18504 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
18505 (UINT32_C(0x6) << 29)
18506 /* Value is in 1/100th of a percentage of total bandwidth. */
18507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18508 (UINT32_C(0x1) << 29)
18510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
18511 (UINT32_C(0x7) << 29)
18512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
18513 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
18515 * Maximum BW allocated to CoS queue.
18516 * The HWRM will translate this value into byte counter and
18517 * time interval used for this COS inside the device.
18519 uint32_t queue_id6_max_bw;
18520 /* The bandwidth value. */
18521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
18522 UINT32_C(0xfffffff)
18523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
18525 /* The granularity of the value (bits or bytes). */
18526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
18527 UINT32_C(0x10000000)
18528 /* Value is in bits. */
18529 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
18530 (UINT32_C(0x0) << 28)
18531 /* Value is in bytes. */
18532 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
18533 (UINT32_C(0x1) << 28)
18534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
18535 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
18536 /* bw_value_unit is 3 b */
18537 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
18538 UINT32_C(0xe0000000)
18539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
18541 /* Value is in Mb or MB (base 10). */
18542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
18543 (UINT32_C(0x0) << 29)
18544 /* Value is in Kb or KB (base 10). */
18545 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
18546 (UINT32_C(0x2) << 29)
18547 /* Value is in bits or bytes. */
18548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
18549 (UINT32_C(0x4) << 29)
18550 /* Value is in Gb or GB (base 10). */
18551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
18552 (UINT32_C(0x6) << 29)
18553 /* Value is in 1/100th of a percentage of total bandwidth. */
18554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18555 (UINT32_C(0x1) << 29)
18557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
18558 (UINT32_C(0x7) << 29)
18559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
18560 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
18561 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18562 uint8_t queue_id6_tsa_assign;
18563 /* Strict Priority */
18564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
18566 /* Enhanced Transmission Selection */
18567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
18570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
18573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
18576 * Priority level for strict priority. Valid only when the
18577 * tsa_assign is 0 - Strict Priority (SP)
18578 * 0..7 - Valid values.
18579 * 8..255 - Reserved.
18581 uint8_t queue_id6_pri_lvl;
18583 * Weight used to allocate remaining BW for this COS after
18584 * servicing guaranteed bandwidths for all COS.
18586 uint8_t queue_id6_bw_weight;
18587 /* ID of CoS Queue 7. */
18590 * Minimum BW allocated to CoS Queue.
18591 * The HWRM will translate this value into byte counter and
18592 * time interval used for this COS inside the device.
18594 uint32_t queue_id7_min_bw;
18595 /* The bandwidth value. */
18596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
18597 UINT32_C(0xfffffff)
18598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
18600 /* The granularity of the value (bits or bytes). */
18601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
18602 UINT32_C(0x10000000)
18603 /* Value is in bits. */
18604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
18605 (UINT32_C(0x0) << 28)
18606 /* Value is in bytes. */
18607 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
18608 (UINT32_C(0x1) << 28)
18609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
18610 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
18611 /* bw_value_unit is 3 b */
18612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
18613 UINT32_C(0xe0000000)
18614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
18616 /* Value is in Mb or MB (base 10). */
18617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
18618 (UINT32_C(0x0) << 29)
18619 /* Value is in Kb or KB (base 10). */
18620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
18621 (UINT32_C(0x2) << 29)
18622 /* Value is in bits or bytes. */
18623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
18624 (UINT32_C(0x4) << 29)
18625 /* Value is in Gb or GB (base 10). */
18626 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
18627 (UINT32_C(0x6) << 29)
18628 /* Value is in 1/100th of a percentage of total bandwidth. */
18629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18630 (UINT32_C(0x1) << 29)
18632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
18633 (UINT32_C(0x7) << 29)
18634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
18635 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
18637 * Maximum BW allocated to CoS queue.
18638 * The HWRM will translate this value into byte counter and
18639 * time interval used for this COS inside the device.
18641 uint32_t queue_id7_max_bw;
18642 /* The bandwidth value. */
18643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
18644 UINT32_C(0xfffffff)
18645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
18647 /* The granularity of the value (bits or bytes). */
18648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
18649 UINT32_C(0x10000000)
18650 /* Value is in bits. */
18651 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
18652 (UINT32_C(0x0) << 28)
18653 /* Value is in bytes. */
18654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
18655 (UINT32_C(0x1) << 28)
18656 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
18657 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
18658 /* bw_value_unit is 3 b */
18659 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
18660 UINT32_C(0xe0000000)
18661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
18663 /* Value is in Mb or MB (base 10). */
18664 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
18665 (UINT32_C(0x0) << 29)
18666 /* Value is in Kb or KB (base 10). */
18667 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
18668 (UINT32_C(0x2) << 29)
18669 /* Value is in bits or bytes. */
18670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
18671 (UINT32_C(0x4) << 29)
18672 /* Value is in Gb or GB (base 10). */
18673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
18674 (UINT32_C(0x6) << 29)
18675 /* Value is in 1/100th of a percentage of total bandwidth. */
18676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18677 (UINT32_C(0x1) << 29)
18679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
18680 (UINT32_C(0x7) << 29)
18681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
18682 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
18683 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18684 uint8_t queue_id7_tsa_assign;
18685 /* Strict Priority */
18686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
18688 /* Enhanced Transmission Selection */
18689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
18692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
18695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
18698 * Priority level for strict priority. Valid only when the
18699 * tsa_assign is 0 - Strict Priority (SP)
18700 * 0..7 - Valid values.
18701 * 8..255 - Reserved.
18703 uint8_t queue_id7_pri_lvl;
18705 * Weight used to allocate remaining BW for this COS after
18706 * servicing guaranteed bandwidths for all COS.
18708 uint8_t queue_id7_bw_weight;
18709 uint8_t unused_2[4];
18711 * This field is used in Output records to indicate that the output
18712 * is completely written to RAM. This field should be read as '1'
18713 * to indicate that the output has been completely written.
18714 * When writing a command completion or response to an internal processor,
18715 * the order of writes has to be such that this field is written last.
18718 } __attribute__((packed));
18720 /*************************
18721 * hwrm_queue_cos2bw_cfg *
18722 *************************/
18725 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
18726 struct hwrm_queue_cos2bw_cfg_input {
18727 /* The HWRM command request type. */
18730 * The completion ring to send the completion event on. This should
18731 * be the NQ ID returned from the `nq_alloc` HWRM command.
18733 uint16_t cmpl_ring;
18735 * The sequence ID is used by the driver for tracking multiple
18736 * commands. This ID is treated as opaque data by the firmware and
18737 * the value is returned in the `hwrm_resp_hdr` upon completion.
18741 * The target ID of the command:
18742 * * 0x0-0xFFF8 - The function ID
18743 * * 0xFFF8-0xFFFE - Reserved for internal processors
18746 uint16_t target_id;
18748 * A physical address pointer pointing to a host buffer that the
18749 * command's response data will be written. This can be either a host
18750 * physical address (HPA) or a guest physical address (GPA) and must
18751 * point to a physically contiguous block of memory.
18753 uint64_t resp_addr;
18757 * If this bit is set to 1, then all queue_id0 related
18758 * parameters in this command are valid.
18760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
18763 * If this bit is set to 1, then all queue_id1 related
18764 * parameters in this command are valid.
18766 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
18769 * If this bit is set to 1, then all queue_id2 related
18770 * parameters in this command are valid.
18772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
18775 * If this bit is set to 1, then all queue_id3 related
18776 * parameters in this command are valid.
18778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
18781 * If this bit is set to 1, then all queue_id4 related
18782 * parameters in this command are valid.
18784 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
18787 * If this bit is set to 1, then all queue_id5 related
18788 * parameters in this command are valid.
18790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
18793 * If this bit is set to 1, then all queue_id6 related
18794 * parameters in this command are valid.
18796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
18799 * If this bit is set to 1, then all queue_id7 related
18800 * parameters in this command are valid.
18802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
18805 * Port ID of port for which the table is being configured.
18806 * The HWRM needs to check whether this function is allowed
18807 * to configure TC BW assignment on this port.
18810 /* ID of CoS Queue 0. */
18814 * Minimum BW allocated to CoS Queue.
18815 * The HWRM will translate this value into byte counter and
18816 * time interval used for this COS inside the device.
18818 uint32_t queue_id0_min_bw;
18819 /* The bandwidth value. */
18820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
18821 UINT32_C(0xfffffff)
18822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
18824 /* The granularity of the value (bits or bytes). */
18825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
18826 UINT32_C(0x10000000)
18827 /* Value is in bits. */
18828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
18829 (UINT32_C(0x0) << 28)
18830 /* Value is in bytes. */
18831 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
18832 (UINT32_C(0x1) << 28)
18833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
18834 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
18835 /* bw_value_unit is 3 b */
18836 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
18837 UINT32_C(0xe0000000)
18838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
18840 /* Value is in Mb or MB (base 10). */
18841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
18842 (UINT32_C(0x0) << 29)
18843 /* Value is in Kb or KB (base 10). */
18844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
18845 (UINT32_C(0x2) << 29)
18846 /* Value is in bits or bytes. */
18847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
18848 (UINT32_C(0x4) << 29)
18849 /* Value is in Gb or GB (base 10). */
18850 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
18851 (UINT32_C(0x6) << 29)
18852 /* Value is in 1/100th of a percentage of total bandwidth. */
18853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18854 (UINT32_C(0x1) << 29)
18856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
18857 (UINT32_C(0x7) << 29)
18858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
18859 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
18861 * Maximum BW allocated to CoS Queue.
18862 * The HWRM will translate this value into byte counter and
18863 * time interval used for this COS inside the device.
18865 uint32_t queue_id0_max_bw;
18866 /* The bandwidth value. */
18867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
18868 UINT32_C(0xfffffff)
18869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
18871 /* The granularity of the value (bits or bytes). */
18872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
18873 UINT32_C(0x10000000)
18874 /* Value is in bits. */
18875 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
18876 (UINT32_C(0x0) << 28)
18877 /* Value is in bytes. */
18878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
18879 (UINT32_C(0x1) << 28)
18880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
18881 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
18882 /* bw_value_unit is 3 b */
18883 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
18884 UINT32_C(0xe0000000)
18885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
18887 /* Value is in Mb or MB (base 10). */
18888 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
18889 (UINT32_C(0x0) << 29)
18890 /* Value is in Kb or KB (base 10). */
18891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
18892 (UINT32_C(0x2) << 29)
18893 /* Value is in bits or bytes. */
18894 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
18895 (UINT32_C(0x4) << 29)
18896 /* Value is in Gb or GB (base 10). */
18897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
18898 (UINT32_C(0x6) << 29)
18899 /* Value is in 1/100th of a percentage of total bandwidth. */
18900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18901 (UINT32_C(0x1) << 29)
18903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
18904 (UINT32_C(0x7) << 29)
18905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
18906 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
18907 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18908 uint8_t queue_id0_tsa_assign;
18909 /* Strict Priority */
18910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
18912 /* Enhanced Transmission Selection */
18913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
18916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
18919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
18922 * Priority level for strict priority. Valid only when the
18923 * tsa_assign is 0 - Strict Priority (SP)
18924 * 0..7 - Valid values.
18925 * 8..255 - Reserved.
18927 uint8_t queue_id0_pri_lvl;
18929 * Weight used to allocate remaining BW for this COS after
18930 * servicing guaranteed bandwidths for all COS.
18932 uint8_t queue_id0_bw_weight;
18933 /* ID of CoS Queue 1. */
18936 * Minimum BW allocated to CoS Queue.
18937 * The HWRM will translate this value into byte counter and
18938 * time interval used for this COS inside the device.
18940 uint32_t queue_id1_min_bw;
18941 /* The bandwidth value. */
18942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
18943 UINT32_C(0xfffffff)
18944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
18946 /* The granularity of the value (bits or bytes). */
18947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
18948 UINT32_C(0x10000000)
18949 /* Value is in bits. */
18950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
18951 (UINT32_C(0x0) << 28)
18952 /* Value is in bytes. */
18953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
18954 (UINT32_C(0x1) << 28)
18955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
18956 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
18957 /* bw_value_unit is 3 b */
18958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
18959 UINT32_C(0xe0000000)
18960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
18962 /* Value is in Mb or MB (base 10). */
18963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
18964 (UINT32_C(0x0) << 29)
18965 /* Value is in Kb or KB (base 10). */
18966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
18967 (UINT32_C(0x2) << 29)
18968 /* Value is in bits or bytes. */
18969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
18970 (UINT32_C(0x4) << 29)
18971 /* Value is in Gb or GB (base 10). */
18972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
18973 (UINT32_C(0x6) << 29)
18974 /* Value is in 1/100th of a percentage of total bandwidth. */
18975 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18976 (UINT32_C(0x1) << 29)
18978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
18979 (UINT32_C(0x7) << 29)
18980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
18981 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
18983 * Maximum BW allocated to CoS queue.
18984 * The HWRM will translate this value into byte counter and
18985 * time interval used for this COS inside the device.
18987 uint32_t queue_id1_max_bw;
18988 /* The bandwidth value. */
18989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
18990 UINT32_C(0xfffffff)
18991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
18993 /* The granularity of the value (bits or bytes). */
18994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
18995 UINT32_C(0x10000000)
18996 /* Value is in bits. */
18997 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
18998 (UINT32_C(0x0) << 28)
18999 /* Value is in bytes. */
19000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19001 (UINT32_C(0x1) << 28)
19002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19003 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19004 /* bw_value_unit is 3 b */
19005 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19006 UINT32_C(0xe0000000)
19007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19009 /* Value is in Mb or MB (base 10). */
19010 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19011 (UINT32_C(0x0) << 29)
19012 /* Value is in Kb or KB (base 10). */
19013 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19014 (UINT32_C(0x2) << 29)
19015 /* Value is in bits or bytes. */
19016 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19017 (UINT32_C(0x4) << 29)
19018 /* Value is in Gb or GB (base 10). */
19019 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19020 (UINT32_C(0x6) << 29)
19021 /* Value is in 1/100th of a percentage of total bandwidth. */
19022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19023 (UINT32_C(0x1) << 29)
19025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19026 (UINT32_C(0x7) << 29)
19027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19028 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19029 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19030 uint8_t queue_id1_tsa_assign;
19031 /* Strict Priority */
19032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19034 /* Enhanced Transmission Selection */
19035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19044 * Priority level for strict priority. Valid only when the
19045 * tsa_assign is 0 - Strict Priority (SP)
19046 * 0..7 - Valid values.
19047 * 8..255 - Reserved.
19049 uint8_t queue_id1_pri_lvl;
19051 * Weight used to allocate remaining BW for this COS after
19052 * servicing guaranteed bandwidths for all COS.
19054 uint8_t queue_id1_bw_weight;
19055 /* ID of CoS Queue 2. */
19058 * Minimum BW allocated to CoS Queue.
19059 * The HWRM will translate this value into byte counter and
19060 * time interval used for this COS inside the device.
19062 uint32_t queue_id2_min_bw;
19063 /* The bandwidth value. */
19064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19065 UINT32_C(0xfffffff)
19066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19068 /* The granularity of the value (bits or bytes). */
19069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
19070 UINT32_C(0x10000000)
19071 /* Value is in bits. */
19072 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19073 (UINT32_C(0x0) << 28)
19074 /* Value is in bytes. */
19075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19076 (UINT32_C(0x1) << 28)
19077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19078 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19079 /* bw_value_unit is 3 b */
19080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19081 UINT32_C(0xe0000000)
19082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19084 /* Value is in Mb or MB (base 10). */
19085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19086 (UINT32_C(0x0) << 29)
19087 /* Value is in Kb or KB (base 10). */
19088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19089 (UINT32_C(0x2) << 29)
19090 /* Value is in bits or bytes. */
19091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19092 (UINT32_C(0x4) << 29)
19093 /* Value is in Gb or GB (base 10). */
19094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19095 (UINT32_C(0x6) << 29)
19096 /* Value is in 1/100th of a percentage of total bandwidth. */
19097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19098 (UINT32_C(0x1) << 29)
19100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19101 (UINT32_C(0x7) << 29)
19102 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19103 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19105 * Maximum BW allocated to CoS queue.
19106 * The HWRM will translate this value into byte counter and
19107 * time interval used for this COS inside the device.
19109 uint32_t queue_id2_max_bw;
19110 /* The bandwidth value. */
19111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19112 UINT32_C(0xfffffff)
19113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19115 /* The granularity of the value (bits or bytes). */
19116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
19117 UINT32_C(0x10000000)
19118 /* Value is in bits. */
19119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19120 (UINT32_C(0x0) << 28)
19121 /* Value is in bytes. */
19122 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19123 (UINT32_C(0x1) << 28)
19124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19125 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19126 /* bw_value_unit is 3 b */
19127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19128 UINT32_C(0xe0000000)
19129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19131 /* Value is in Mb or MB (base 10). */
19132 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19133 (UINT32_C(0x0) << 29)
19134 /* Value is in Kb or KB (base 10). */
19135 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19136 (UINT32_C(0x2) << 29)
19137 /* Value is in bits or bytes. */
19138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19139 (UINT32_C(0x4) << 29)
19140 /* Value is in Gb or GB (base 10). */
19141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19142 (UINT32_C(0x6) << 29)
19143 /* Value is in 1/100th of a percentage of total bandwidth. */
19144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19145 (UINT32_C(0x1) << 29)
19147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19148 (UINT32_C(0x7) << 29)
19149 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19150 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19151 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19152 uint8_t queue_id2_tsa_assign;
19153 /* Strict Priority */
19154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19156 /* Enhanced Transmission Selection */
19157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
19166 * Priority level for strict priority. Valid only when the
19167 * tsa_assign is 0 - Strict Priority (SP)
19168 * 0..7 - Valid values.
19169 * 8..255 - Reserved.
19171 uint8_t queue_id2_pri_lvl;
19173 * Weight used to allocate remaining BW for this COS after
19174 * servicing guaranteed bandwidths for all COS.
19176 uint8_t queue_id2_bw_weight;
19177 /* ID of CoS Queue 3. */
19180 * Minimum BW allocated to CoS Queue.
19181 * The HWRM will translate this value into byte counter and
19182 * time interval used for this COS inside the device.
19184 uint32_t queue_id3_min_bw;
19185 /* The bandwidth value. */
19186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
19187 UINT32_C(0xfffffff)
19188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
19190 /* The granularity of the value (bits or bytes). */
19191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
19192 UINT32_C(0x10000000)
19193 /* Value is in bits. */
19194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
19195 (UINT32_C(0x0) << 28)
19196 /* Value is in bytes. */
19197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
19198 (UINT32_C(0x1) << 28)
19199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
19200 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
19201 /* bw_value_unit is 3 b */
19202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
19203 UINT32_C(0xe0000000)
19204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
19206 /* Value is in Mb or MB (base 10). */
19207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
19208 (UINT32_C(0x0) << 29)
19209 /* Value is in Kb or KB (base 10). */
19210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
19211 (UINT32_C(0x2) << 29)
19212 /* Value is in bits or bytes. */
19213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
19214 (UINT32_C(0x4) << 29)
19215 /* Value is in Gb or GB (base 10). */
19216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
19217 (UINT32_C(0x6) << 29)
19218 /* Value is in 1/100th of a percentage of total bandwidth. */
19219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19220 (UINT32_C(0x1) << 29)
19222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
19223 (UINT32_C(0x7) << 29)
19224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
19225 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
19227 * Maximum BW allocated to CoS queue.
19228 * The HWRM will translate this value into byte counter and
19229 * time interval used for this COS inside the device.
19231 uint32_t queue_id3_max_bw;
19232 /* The bandwidth value. */
19233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
19234 UINT32_C(0xfffffff)
19235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
19237 /* The granularity of the value (bits or bytes). */
19238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
19239 UINT32_C(0x10000000)
19240 /* Value is in bits. */
19241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
19242 (UINT32_C(0x0) << 28)
19243 /* Value is in bytes. */
19244 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
19245 (UINT32_C(0x1) << 28)
19246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
19247 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
19248 /* bw_value_unit is 3 b */
19249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
19250 UINT32_C(0xe0000000)
19251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
19253 /* Value is in Mb or MB (base 10). */
19254 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
19255 (UINT32_C(0x0) << 29)
19256 /* Value is in Kb or KB (base 10). */
19257 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
19258 (UINT32_C(0x2) << 29)
19259 /* Value is in bits or bytes. */
19260 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
19261 (UINT32_C(0x4) << 29)
19262 /* Value is in Gb or GB (base 10). */
19263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
19264 (UINT32_C(0x6) << 29)
19265 /* Value is in 1/100th of a percentage of total bandwidth. */
19266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19267 (UINT32_C(0x1) << 29)
19269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
19270 (UINT32_C(0x7) << 29)
19271 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
19272 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
19273 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19274 uint8_t queue_id3_tsa_assign;
19275 /* Strict Priority */
19276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
19278 /* Enhanced Transmission Selection */
19279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
19282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
19285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
19288 * Priority level for strict priority. Valid only when the
19289 * tsa_assign is 0 - Strict Priority (SP)
19290 * 0..7 - Valid values.
19291 * 8..255 - Reserved.
19293 uint8_t queue_id3_pri_lvl;
19295 * Weight used to allocate remaining BW for this COS after
19296 * servicing guaranteed bandwidths for all COS.
19298 uint8_t queue_id3_bw_weight;
19299 /* ID of CoS Queue 4. */
19302 * Minimum BW allocated to CoS Queue.
19303 * The HWRM will translate this value into byte counter and
19304 * time interval used for this COS inside the device.
19306 uint32_t queue_id4_min_bw;
19307 /* The bandwidth value. */
19308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
19309 UINT32_C(0xfffffff)
19310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
19312 /* The granularity of the value (bits or bytes). */
19313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
19314 UINT32_C(0x10000000)
19315 /* Value is in bits. */
19316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
19317 (UINT32_C(0x0) << 28)
19318 /* Value is in bytes. */
19319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
19320 (UINT32_C(0x1) << 28)
19321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
19322 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
19323 /* bw_value_unit is 3 b */
19324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
19325 UINT32_C(0xe0000000)
19326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
19328 /* Value is in Mb or MB (base 10). */
19329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
19330 (UINT32_C(0x0) << 29)
19331 /* Value is in Kb or KB (base 10). */
19332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
19333 (UINT32_C(0x2) << 29)
19334 /* Value is in bits or bytes. */
19335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
19336 (UINT32_C(0x4) << 29)
19337 /* Value is in Gb or GB (base 10). */
19338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
19339 (UINT32_C(0x6) << 29)
19340 /* Value is in 1/100th of a percentage of total bandwidth. */
19341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19342 (UINT32_C(0x1) << 29)
19344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
19345 (UINT32_C(0x7) << 29)
19346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
19347 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
19349 * Maximum BW allocated to CoS queue.
19350 * The HWRM will translate this value into byte counter and
19351 * time interval used for this COS inside the device.
19353 uint32_t queue_id4_max_bw;
19354 /* The bandwidth value. */
19355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
19356 UINT32_C(0xfffffff)
19357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
19359 /* The granularity of the value (bits or bytes). */
19360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
19361 UINT32_C(0x10000000)
19362 /* Value is in bits. */
19363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
19364 (UINT32_C(0x0) << 28)
19365 /* Value is in bytes. */
19366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
19367 (UINT32_C(0x1) << 28)
19368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
19369 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
19370 /* bw_value_unit is 3 b */
19371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
19372 UINT32_C(0xe0000000)
19373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
19375 /* Value is in Mb or MB (base 10). */
19376 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
19377 (UINT32_C(0x0) << 29)
19378 /* Value is in Kb or KB (base 10). */
19379 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
19380 (UINT32_C(0x2) << 29)
19381 /* Value is in bits or bytes. */
19382 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
19383 (UINT32_C(0x4) << 29)
19384 /* Value is in Gb or GB (base 10). */
19385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
19386 (UINT32_C(0x6) << 29)
19387 /* Value is in 1/100th of a percentage of total bandwidth. */
19388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19389 (UINT32_C(0x1) << 29)
19391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
19392 (UINT32_C(0x7) << 29)
19393 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
19394 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
19395 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19396 uint8_t queue_id4_tsa_assign;
19397 /* Strict Priority */
19398 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
19400 /* Enhanced Transmission Selection */
19401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
19404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
19407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
19410 * Priority level for strict priority. Valid only when the
19411 * tsa_assign is 0 - Strict Priority (SP)
19412 * 0..7 - Valid values.
19413 * 8..255 - Reserved.
19415 uint8_t queue_id4_pri_lvl;
19417 * Weight used to allocate remaining BW for this COS after
19418 * servicing guaranteed bandwidths for all COS.
19420 uint8_t queue_id4_bw_weight;
19421 /* ID of CoS Queue 5. */
19424 * Minimum BW allocated to CoS Queue.
19425 * The HWRM will translate this value into byte counter and
19426 * time interval used for this COS inside the device.
19428 uint32_t queue_id5_min_bw;
19429 /* The bandwidth value. */
19430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
19431 UINT32_C(0xfffffff)
19432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
19434 /* The granularity of the value (bits or bytes). */
19435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
19436 UINT32_C(0x10000000)
19437 /* Value is in bits. */
19438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
19439 (UINT32_C(0x0) << 28)
19440 /* Value is in bytes. */
19441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
19442 (UINT32_C(0x1) << 28)
19443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
19444 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
19445 /* bw_value_unit is 3 b */
19446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
19447 UINT32_C(0xe0000000)
19448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
19450 /* Value is in Mb or MB (base 10). */
19451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
19452 (UINT32_C(0x0) << 29)
19453 /* Value is in Kb or KB (base 10). */
19454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
19455 (UINT32_C(0x2) << 29)
19456 /* Value is in bits or bytes. */
19457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
19458 (UINT32_C(0x4) << 29)
19459 /* Value is in Gb or GB (base 10). */
19460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
19461 (UINT32_C(0x6) << 29)
19462 /* Value is in 1/100th of a percentage of total bandwidth. */
19463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19464 (UINT32_C(0x1) << 29)
19466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
19467 (UINT32_C(0x7) << 29)
19468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
19469 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
19471 * Maximum BW allocated to CoS queue.
19472 * The HWRM will translate this value into byte counter and
19473 * time interval used for this COS inside the device.
19475 uint32_t queue_id5_max_bw;
19476 /* The bandwidth value. */
19477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
19478 UINT32_C(0xfffffff)
19479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
19481 /* The granularity of the value (bits or bytes). */
19482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
19483 UINT32_C(0x10000000)
19484 /* Value is in bits. */
19485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
19486 (UINT32_C(0x0) << 28)
19487 /* Value is in bytes. */
19488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
19489 (UINT32_C(0x1) << 28)
19490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
19491 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
19492 /* bw_value_unit is 3 b */
19493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
19494 UINT32_C(0xe0000000)
19495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
19497 /* Value is in Mb or MB (base 10). */
19498 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
19499 (UINT32_C(0x0) << 29)
19500 /* Value is in Kb or KB (base 10). */
19501 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
19502 (UINT32_C(0x2) << 29)
19503 /* Value is in bits or bytes. */
19504 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
19505 (UINT32_C(0x4) << 29)
19506 /* Value is in Gb or GB (base 10). */
19507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
19508 (UINT32_C(0x6) << 29)
19509 /* Value is in 1/100th of a percentage of total bandwidth. */
19510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19511 (UINT32_C(0x1) << 29)
19513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
19514 (UINT32_C(0x7) << 29)
19515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
19516 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
19517 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19518 uint8_t queue_id5_tsa_assign;
19519 /* Strict Priority */
19520 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
19522 /* Enhanced Transmission Selection */
19523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
19526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
19529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
19532 * Priority level for strict priority. Valid only when the
19533 * tsa_assign is 0 - Strict Priority (SP)
19534 * 0..7 - Valid values.
19535 * 8..255 - Reserved.
19537 uint8_t queue_id5_pri_lvl;
19539 * Weight used to allocate remaining BW for this COS after
19540 * servicing guaranteed bandwidths for all COS.
19542 uint8_t queue_id5_bw_weight;
19543 /* ID of CoS Queue 6. */
19546 * Minimum BW allocated to CoS Queue.
19547 * The HWRM will translate this value into byte counter and
19548 * time interval used for this COS inside the device.
19550 uint32_t queue_id6_min_bw;
19551 /* The bandwidth value. */
19552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
19553 UINT32_C(0xfffffff)
19554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
19556 /* The granularity of the value (bits or bytes). */
19557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
19558 UINT32_C(0x10000000)
19559 /* Value is in bits. */
19560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
19561 (UINT32_C(0x0) << 28)
19562 /* Value is in bytes. */
19563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
19564 (UINT32_C(0x1) << 28)
19565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
19566 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
19567 /* bw_value_unit is 3 b */
19568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
19569 UINT32_C(0xe0000000)
19570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
19572 /* Value is in Mb or MB (base 10). */
19573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
19574 (UINT32_C(0x0) << 29)
19575 /* Value is in Kb or KB (base 10). */
19576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
19577 (UINT32_C(0x2) << 29)
19578 /* Value is in bits or bytes. */
19579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
19580 (UINT32_C(0x4) << 29)
19581 /* Value is in Gb or GB (base 10). */
19582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
19583 (UINT32_C(0x6) << 29)
19584 /* Value is in 1/100th of a percentage of total bandwidth. */
19585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19586 (UINT32_C(0x1) << 29)
19588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
19589 (UINT32_C(0x7) << 29)
19590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
19591 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
19593 * Maximum BW allocated to CoS queue.
19594 * The HWRM will translate this value into byte counter and
19595 * time interval used for this COS inside the device.
19597 uint32_t queue_id6_max_bw;
19598 /* The bandwidth value. */
19599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
19600 UINT32_C(0xfffffff)
19601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
19603 /* The granularity of the value (bits or bytes). */
19604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
19605 UINT32_C(0x10000000)
19606 /* Value is in bits. */
19607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
19608 (UINT32_C(0x0) << 28)
19609 /* Value is in bytes. */
19610 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
19611 (UINT32_C(0x1) << 28)
19612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
19613 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
19614 /* bw_value_unit is 3 b */
19615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
19616 UINT32_C(0xe0000000)
19617 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
19619 /* Value is in Mb or MB (base 10). */
19620 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
19621 (UINT32_C(0x0) << 29)
19622 /* Value is in Kb or KB (base 10). */
19623 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
19624 (UINT32_C(0x2) << 29)
19625 /* Value is in bits or bytes. */
19626 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
19627 (UINT32_C(0x4) << 29)
19628 /* Value is in Gb or GB (base 10). */
19629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
19630 (UINT32_C(0x6) << 29)
19631 /* Value is in 1/100th of a percentage of total bandwidth. */
19632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19633 (UINT32_C(0x1) << 29)
19635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
19636 (UINT32_C(0x7) << 29)
19637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
19638 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
19639 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19640 uint8_t queue_id6_tsa_assign;
19641 /* Strict Priority */
19642 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
19644 /* Enhanced Transmission Selection */
19645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
19648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
19651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
19654 * Priority level for strict priority. Valid only when the
19655 * tsa_assign is 0 - Strict Priority (SP)
19656 * 0..7 - Valid values.
19657 * 8..255 - Reserved.
19659 uint8_t queue_id6_pri_lvl;
19661 * Weight used to allocate remaining BW for this COS after
19662 * servicing guaranteed bandwidths for all COS.
19664 uint8_t queue_id6_bw_weight;
19665 /* ID of CoS Queue 7. */
19668 * Minimum BW allocated to CoS Queue.
19669 * The HWRM will translate this value into byte counter and
19670 * time interval used for this COS inside the device.
19672 uint32_t queue_id7_min_bw;
19673 /* The bandwidth value. */
19674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
19675 UINT32_C(0xfffffff)
19676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
19678 /* The granularity of the value (bits or bytes). */
19679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
19680 UINT32_C(0x10000000)
19681 /* Value is in bits. */
19682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
19683 (UINT32_C(0x0) << 28)
19684 /* Value is in bytes. */
19685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
19686 (UINT32_C(0x1) << 28)
19687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
19688 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
19689 /* bw_value_unit is 3 b */
19690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
19691 UINT32_C(0xe0000000)
19692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
19694 /* Value is in Mb or MB (base 10). */
19695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
19696 (UINT32_C(0x0) << 29)
19697 /* Value is in Kb or KB (base 10). */
19698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
19699 (UINT32_C(0x2) << 29)
19700 /* Value is in bits or bytes. */
19701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
19702 (UINT32_C(0x4) << 29)
19703 /* Value is in Gb or GB (base 10). */
19704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
19705 (UINT32_C(0x6) << 29)
19706 /* Value is in 1/100th of a percentage of total bandwidth. */
19707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19708 (UINT32_C(0x1) << 29)
19710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
19711 (UINT32_C(0x7) << 29)
19712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
19713 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
19715 * Maximum BW allocated to CoS queue.
19716 * The HWRM will translate this value into byte counter and
19717 * time interval used for this COS inside the device.
19719 uint32_t queue_id7_max_bw;
19720 /* The bandwidth value. */
19721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
19722 UINT32_C(0xfffffff)
19723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
19725 /* The granularity of the value (bits or bytes). */
19726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
19727 UINT32_C(0x10000000)
19728 /* Value is in bits. */
19729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
19730 (UINT32_C(0x0) << 28)
19731 /* Value is in bytes. */
19732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
19733 (UINT32_C(0x1) << 28)
19734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
19735 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
19736 /* bw_value_unit is 3 b */
19737 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
19738 UINT32_C(0xe0000000)
19739 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
19741 /* Value is in Mb or MB (base 10). */
19742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
19743 (UINT32_C(0x0) << 29)
19744 /* Value is in Kb or KB (base 10). */
19745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
19746 (UINT32_C(0x2) << 29)
19747 /* Value is in bits or bytes. */
19748 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
19749 (UINT32_C(0x4) << 29)
19750 /* Value is in Gb or GB (base 10). */
19751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
19752 (UINT32_C(0x6) << 29)
19753 /* Value is in 1/100th of a percentage of total bandwidth. */
19754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19755 (UINT32_C(0x1) << 29)
19757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
19758 (UINT32_C(0x7) << 29)
19759 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
19760 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
19761 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19762 uint8_t queue_id7_tsa_assign;
19763 /* Strict Priority */
19764 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
19766 /* Enhanced Transmission Selection */
19767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
19770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
19773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
19776 * Priority level for strict priority. Valid only when the
19777 * tsa_assign is 0 - Strict Priority (SP)
19778 * 0..7 - Valid values.
19779 * 8..255 - Reserved.
19781 uint8_t queue_id7_pri_lvl;
19783 * Weight used to allocate remaining BW for this COS after
19784 * servicing guaranteed bandwidths for all COS.
19786 uint8_t queue_id7_bw_weight;
19787 uint8_t unused_1[5];
19788 } __attribute__((packed));
19790 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
19791 struct hwrm_queue_cos2bw_cfg_output {
19792 /* The specific error status for the command. */
19793 uint16_t error_code;
19794 /* The HWRM command request type. */
19796 /* The sequence ID from the original command. */
19798 /* The length of the response data in number of bytes. */
19800 uint8_t unused_0[7];
19802 * This field is used in Output records to indicate that the output
19803 * is completely written to RAM. This field should be read as '1'
19804 * to indicate that the output has been completely written.
19805 * When writing a command completion or response to an internal processor,
19806 * the order of writes has to be such that this field is written last.
19809 } __attribute__((packed));
19811 /*******************
19812 * hwrm_vnic_alloc *
19813 *******************/
19816 /* hwrm_vnic_alloc_input (size:192b/24B) */
19817 struct hwrm_vnic_alloc_input {
19818 /* The HWRM command request type. */
19821 * The completion ring to send the completion event on. This should
19822 * be the NQ ID returned from the `nq_alloc` HWRM command.
19824 uint16_t cmpl_ring;
19826 * The sequence ID is used by the driver for tracking multiple
19827 * commands. This ID is treated as opaque data by the firmware and
19828 * the value is returned in the `hwrm_resp_hdr` upon completion.
19832 * The target ID of the command:
19833 * * 0x0-0xFFF8 - The function ID
19834 * * 0xFFF8-0xFFFE - Reserved for internal processors
19837 uint16_t target_id;
19839 * A physical address pointer pointing to a host buffer that the
19840 * command's response data will be written. This can be either a host
19841 * physical address (HPA) or a guest physical address (GPA) and must
19842 * point to a physically contiguous block of memory.
19844 uint64_t resp_addr;
19847 * When this bit is '1', this VNIC is requested to
19848 * be the default VNIC for this function.
19850 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
19851 uint8_t unused_0[4];
19852 } __attribute__((packed));
19854 /* hwrm_vnic_alloc_output (size:128b/16B) */
19855 struct hwrm_vnic_alloc_output {
19856 /* The specific error status for the command. */
19857 uint16_t error_code;
19858 /* The HWRM command request type. */
19860 /* The sequence ID from the original command. */
19862 /* The length of the response data in number of bytes. */
19864 /* Logical vnic ID */
19866 uint8_t unused_0[3];
19868 * This field is used in Output records to indicate that the output
19869 * is completely written to RAM. This field should be read as '1'
19870 * to indicate that the output has been completely written.
19871 * When writing a command completion or response to an internal processor,
19872 * the order of writes has to be such that this field is written last.
19875 } __attribute__((packed));
19877 /******************
19879 ******************/
19882 /* hwrm_vnic_free_input (size:192b/24B) */
19883 struct hwrm_vnic_free_input {
19884 /* The HWRM command request type. */
19887 * The completion ring to send the completion event on. This should
19888 * be the NQ ID returned from the `nq_alloc` HWRM command.
19890 uint16_t cmpl_ring;
19892 * The sequence ID is used by the driver for tracking multiple
19893 * commands. This ID is treated as opaque data by the firmware and
19894 * the value is returned in the `hwrm_resp_hdr` upon completion.
19898 * The target ID of the command:
19899 * * 0x0-0xFFF8 - The function ID
19900 * * 0xFFF8-0xFFFE - Reserved for internal processors
19903 uint16_t target_id;
19905 * A physical address pointer pointing to a host buffer that the
19906 * command's response data will be written. This can be either a host
19907 * physical address (HPA) or a guest physical address (GPA) and must
19908 * point to a physically contiguous block of memory.
19910 uint64_t resp_addr;
19911 /* Logical vnic ID */
19913 uint8_t unused_0[4];
19914 } __attribute__((packed));
19916 /* hwrm_vnic_free_output (size:128b/16B) */
19917 struct hwrm_vnic_free_output {
19918 /* The specific error status for the command. */
19919 uint16_t error_code;
19920 /* The HWRM command request type. */
19922 /* The sequence ID from the original command. */
19924 /* The length of the response data in number of bytes. */
19926 uint8_t unused_0[7];
19928 * This field is used in Output records to indicate that the output
19929 * is completely written to RAM. This field should be read as '1'
19930 * to indicate that the output has been completely written.
19931 * When writing a command completion or response to an internal processor,
19932 * the order of writes has to be such that this field is written last.
19935 } __attribute__((packed));
19942 /* hwrm_vnic_cfg_input (size:320b/40B) */
19943 struct hwrm_vnic_cfg_input {
19944 /* The HWRM command request type. */
19947 * The completion ring to send the completion event on. This should
19948 * be the NQ ID returned from the `nq_alloc` HWRM command.
19950 uint16_t cmpl_ring;
19952 * The sequence ID is used by the driver for tracking multiple
19953 * commands. This ID is treated as opaque data by the firmware and
19954 * the value is returned in the `hwrm_resp_hdr` upon completion.
19958 * The target ID of the command:
19959 * * 0x0-0xFFF8 - The function ID
19960 * * 0xFFF8-0xFFFE - Reserved for internal processors
19963 uint16_t target_id;
19965 * A physical address pointer pointing to a host buffer that the
19966 * command's response data will be written. This can be either a host
19967 * physical address (HPA) or a guest physical address (GPA) and must
19968 * point to a physically contiguous block of memory.
19970 uint64_t resp_addr;
19973 * When this bit is '1', the VNIC is requested to
19974 * be the default VNIC for the function.
19976 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
19979 * When this bit is '1', the VNIC is being configured to
19980 * strip VLAN in the RX path.
19981 * If set to '0', then VLAN stripping is disabled on
19984 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
19987 * When this bit is '1', the VNIC is being configured to
19988 * buffer receive packets in the hardware until the host
19989 * posts new receive buffers.
19990 * If set to '0', then bd_stall is being configured to be
19991 * disabled on this VNIC.
19993 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
19996 * When this bit is '1', the VNIC is being configured to
19997 * receive both RoCE and non-RoCE traffic.
19998 * If set to '0', then this VNIC is not configured to be
19999 * operating in dual VNIC mode.
20001 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
20004 * When this flag is set to '1', the VNIC is requested to
20005 * be configured to receive only RoCE traffic.
20006 * If this flag is set to '0', then this flag shall be
20007 * ignored by the HWRM.
20008 * If roce_dual_vnic_mode flag is set to '1'
20009 * or roce_mirroring_capable_vnic_mode flag to 1,
20010 * then the HWRM client shall not set this flag to '1'.
20012 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
20015 * When a VNIC uses one destination ring group for certain
20016 * application (e.g. Receive Flow Steering) where
20017 * exact match is used to direct packets to a VNIC with one
20018 * destination ring group only, there is no need to configure
20019 * RSS indirection table for that VNIC as only one destination
20020 * ring group is used.
20022 * This flag is used to enable a mode where
20023 * RSS is enabled in the VNIC using a RSS context
20024 * for computing RSS hash but the RSS indirection table is
20025 * not configured using hwrm_vnic_rss_cfg.
20027 * If this mode is enabled, then the driver should not program
20028 * RSS indirection table for the RSS context that is used for
20029 * computing RSS hash only.
20031 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
20034 * When this bit is '1', the VNIC is being configured to
20035 * receive both RoCE and non-RoCE traffic, but forward only the
20036 * RoCE traffic further. Also, RoCE traffic can be mirrored to
20039 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
20043 * This bit must be '1' for the dflt_ring_grp field to be
20046 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
20049 * This bit must be '1' for the rss_rule field to be
20052 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
20055 * This bit must be '1' for the cos_rule field to be
20058 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
20061 * This bit must be '1' for the lb_rule field to be
20064 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
20067 * This bit must be '1' for the mru field to be
20070 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
20073 * This bit must be '1' for the default_rx_ring_id field to be
20076 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
20079 * This bit must be '1' for the default_cmpl_ring_id field to be
20082 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
20084 /* Logical vnic ID */
20087 * Default Completion ring for the VNIC. This ring will
20088 * be chosen if packet does not match any RSS rules and if
20089 * there is no COS rule.
20091 uint16_t dflt_ring_grp;
20093 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
20094 * there is no RSS rule.
20098 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
20099 * there is no COS rule.
20103 * RSS ID for load balancing rule/table structure.
20104 * 0xFF... (All Fs) if there is no LB rule.
20108 * The maximum receive unit of the vnic.
20109 * Each vnic is associated with a function.
20110 * The vnic mru value overwrites the mru setting of the
20111 * associated function.
20112 * The HWRM shall make sure that vnic mru does not exceed
20113 * the mru of the port the function is associated with.
20117 * Default Rx ring for the VNIC. This ring will
20118 * be chosen if packet does not match any RSS rules.
20119 * The aggregation ring associated with the Rx ring is
20120 * implied based on the Rx ring specified when the
20121 * aggregation ring was allocated.
20123 uint16_t default_rx_ring_id;
20125 * Default completion ring for the VNIC. This ring will
20126 * be chosen if packet does not match any RSS rules.
20128 uint16_t default_cmpl_ring_id;
20129 } __attribute__((packed));
20131 /* hwrm_vnic_cfg_output (size:128b/16B) */
20132 struct hwrm_vnic_cfg_output {
20133 /* The specific error status for the command. */
20134 uint16_t error_code;
20135 /* The HWRM command request type. */
20137 /* The sequence ID from the original command. */
20139 /* The length of the response data in number of bytes. */
20141 uint8_t unused_0[7];
20143 * This field is used in Output records to indicate that the output
20144 * is completely written to RAM. This field should be read as '1'
20145 * to indicate that the output has been completely written.
20146 * When writing a command completion or response to an internal processor,
20147 * the order of writes has to be such that this field is written last.
20150 } __attribute__((packed));
20152 /******************
20154 ******************/
20157 /* hwrm_vnic_qcfg_input (size:256b/32B) */
20158 struct hwrm_vnic_qcfg_input {
20159 /* The HWRM command request type. */
20162 * The completion ring to send the completion event on. This should
20163 * be the NQ ID returned from the `nq_alloc` HWRM command.
20165 uint16_t cmpl_ring;
20167 * The sequence ID is used by the driver for tracking multiple
20168 * commands. This ID is treated as opaque data by the firmware and
20169 * the value is returned in the `hwrm_resp_hdr` upon completion.
20173 * The target ID of the command:
20174 * * 0x0-0xFFF8 - The function ID
20175 * * 0xFFF8-0xFFFE - Reserved for internal processors
20178 uint16_t target_id;
20180 * A physical address pointer pointing to a host buffer that the
20181 * command's response data will be written. This can be either a host
20182 * physical address (HPA) or a guest physical address (GPA) and must
20183 * point to a physically contiguous block of memory.
20185 uint64_t resp_addr;
20188 * This bit must be '1' for the vf_id_valid field to be
20191 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
20192 /* Logical vnic ID */
20194 /* ID of Virtual Function whose VNIC resource is being queried. */
20196 uint8_t unused_0[6];
20197 } __attribute__((packed));
20199 /* hwrm_vnic_qcfg_output (size:256b/32B) */
20200 struct hwrm_vnic_qcfg_output {
20201 /* The specific error status for the command. */
20202 uint16_t error_code;
20203 /* The HWRM command request type. */
20205 /* The sequence ID from the original command. */
20207 /* The length of the response data in number of bytes. */
20209 /* Default Completion ring for the VNIC. */
20210 uint16_t dflt_ring_grp;
20212 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
20213 * there is no RSS rule.
20217 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
20218 * there is no COS rule.
20222 * RSS ID for load balancing rule/table structure.
20223 * 0xFF... (All Fs) if there is no LB rule.
20226 /* The maximum receive unit of the vnic. */
20228 uint8_t unused_0[2];
20231 * When this bit is '1', the VNIC is the default VNIC for
20234 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
20237 * When this bit is '1', the VNIC is configured to
20238 * strip VLAN in the RX path.
20239 * If set to '0', then VLAN stripping is disabled on
20242 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
20245 * When this bit is '1', the VNIC is configured to
20246 * buffer receive packets in the hardware until the host
20247 * posts new receive buffers.
20248 * If set to '0', then bd_stall is disabled on
20251 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
20254 * When this bit is '1', the VNIC is configured to
20255 * receive both RoCE and non-RoCE traffic.
20256 * If set to '0', then this VNIC is not configured to
20257 * operate in dual VNIC mode.
20259 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
20262 * When this flag is set to '1', the VNIC is configured to
20263 * receive only RoCE traffic.
20264 * When this flag is set to '0', the VNIC is not configured
20265 * to receive only RoCE traffic.
20266 * If roce_dual_vnic_mode flag and this flag both are set
20267 * to '1', then it is an invalid configuration of the
20268 * VNIC. The HWRM should not allow that type of
20269 * mis-configuration by HWRM clients.
20271 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
20274 * When a VNIC uses one destination ring group for certain
20275 * application (e.g. Receive Flow Steering) where
20276 * exact match is used to direct packets to a VNIC with one
20277 * destination ring group only, there is no need to configure
20278 * RSS indirection table for that VNIC as only one destination
20279 * ring group is used.
20281 * When this bit is set to '1', then the VNIC is enabled in a
20282 * mode where RSS is enabled in the VNIC using a RSS context
20283 * for computing RSS hash but the RSS indirection table is
20286 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
20289 * When this bit is '1', the VNIC is configured to
20290 * receive both RoCE and non-RoCE traffic, but forward only
20291 * RoCE traffic further. Also RoCE traffic can be mirrored to
20294 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
20296 uint8_t unused_1[7];
20298 * This field is used in Output records to indicate that the output
20299 * is completely written to RAM. This field should be read as '1'
20300 * to indicate that the output has been completely written.
20301 * When writing a command completion or response to an internal processor,
20302 * the order of writes has to be such that this field is written last.
20305 } __attribute__((packed));
20307 /*******************
20308 * hwrm_vnic_qcaps *
20309 *******************/
20312 /* hwrm_vnic_qcaps_input (size:192b/24B) */
20313 struct hwrm_vnic_qcaps_input {
20314 /* The HWRM command request type. */
20317 * The completion ring to send the completion event on. This should
20318 * be the NQ ID returned from the `nq_alloc` HWRM command.
20320 uint16_t cmpl_ring;
20322 * The sequence ID is used by the driver for tracking multiple
20323 * commands. This ID is treated as opaque data by the firmware and
20324 * the value is returned in the `hwrm_resp_hdr` upon completion.
20328 * The target ID of the command:
20329 * * 0x0-0xFFF8 - The function ID
20330 * * 0xFFF8-0xFFFE - Reserved for internal processors
20333 uint16_t target_id;
20335 * A physical address pointer pointing to a host buffer that the
20336 * command's response data will be written. This can be either a host
20337 * physical address (HPA) or a guest physical address (GPA) and must
20338 * point to a physically contiguous block of memory.
20340 uint64_t resp_addr;
20342 uint8_t unused_0[4];
20343 } __attribute__((packed));
20345 /* hwrm_vnic_qcaps_output (size:192b/24B) */
20346 struct hwrm_vnic_qcaps_output {
20347 /* The specific error status for the command. */
20348 uint16_t error_code;
20349 /* The HWRM command request type. */
20351 /* The sequence ID from the original command. */
20353 /* The length of the response data in number of bytes. */
20355 /* The maximum receive unit that is settable on a vnic. */
20357 uint8_t unused_0[2];
20360 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
20363 * When this bit is '1', the capability of stripping VLAN in
20364 * the RX path is supported on VNIC(s).
20365 * If set to '0', then VLAN stripping capability is
20366 * not supported on VNIC(s).
20368 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
20371 * When this bit is '1', the capability to buffer receive
20372 * packets in the hardware until the host posts new receive buffers
20373 * is supported on VNIC(s).
20374 * If set to '0', then bd_stall capability is not supported
20377 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
20380 * When this bit is '1', the capability to
20381 * receive both RoCE and non-RoCE traffic on VNIC(s) is
20383 * If set to '0', then the capability to receive
20384 * both RoCE and non-RoCE traffic on VNIC(s) is
20387 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
20390 * When this bit is set to '1', the capability to configure
20391 * a VNIC to receive only RoCE traffic is supported.
20392 * When this flag is set to '0', the VNIC capability to
20393 * configure to receive only RoCE traffic is not supported.
20395 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
20398 * When this bit is set to '1', then the capability to enable
20399 * a VNIC in a mode where RSS context without configuring
20400 * RSS indirection table is supported (for RSS hash computation).
20401 * When this bit is set to '0', then a VNIC can not be configured
20402 * with a mode to enable RSS context without configuring RSS
20403 * indirection table.
20405 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
20408 * When this bit is '1', the capability to
20409 * mirror the the RoCE traffic is supported.
20410 * If set to '0', then the capability to mirror the
20411 * RoCE traffic is not supported.
20413 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
20416 * When this bit is '1', the outermost RSS hashing capability
20417 * is supported. If set to '0', then the outermost RSS hashing
20418 * capability is not supported.
20420 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
20422 uint8_t unused_1[7];
20424 * This field is used in Output records to indicate that the output
20425 * is completely written to RAM. This field should be read as '1'
20426 * to indicate that the output has been completely written.
20427 * When writing a command completion or response to an internal processor,
20428 * the order of writes has to be such that this field is written last.
20431 } __attribute__((packed));
20433 /*********************
20434 * hwrm_vnic_tpa_cfg *
20435 *********************/
20438 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
20439 struct hwrm_vnic_tpa_cfg_input {
20440 /* The HWRM command request type. */
20443 * The completion ring to send the completion event on. This should
20444 * be the NQ ID returned from the `nq_alloc` HWRM command.
20446 uint16_t cmpl_ring;
20448 * The sequence ID is used by the driver for tracking multiple
20449 * commands. This ID is treated as opaque data by the firmware and
20450 * the value is returned in the `hwrm_resp_hdr` upon completion.
20454 * The target ID of the command:
20455 * * 0x0-0xFFF8 - The function ID
20456 * * 0xFFF8-0xFFFE - Reserved for internal processors
20459 uint16_t target_id;
20461 * A physical address pointer pointing to a host buffer that the
20462 * command's response data will be written. This can be either a host
20463 * physical address (HPA) or a guest physical address (GPA) and must
20464 * point to a physically contiguous block of memory.
20466 uint64_t resp_addr;
20469 * When this bit is '1', the VNIC shall be configured to
20470 * perform transparent packet aggregation (TPA) of
20471 * non-tunneled TCP packets.
20473 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
20476 * When this bit is '1', the VNIC shall be configured to
20477 * perform transparent packet aggregation (TPA) of
20478 * tunneled TCP packets.
20480 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
20483 * When this bit is '1', the VNIC shall be configured to
20484 * perform transparent packet aggregation (TPA) according
20485 * to Windows Receive Segment Coalescing (RSC) rules.
20487 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
20490 * When this bit is '1', the VNIC shall be configured to
20491 * perform transparent packet aggregation (TPA) according
20492 * to Linux Generic Receive Offload (GRO) rules.
20494 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
20497 * When this bit is '1', the VNIC shall be configured to
20498 * perform transparent packet aggregation (TPA) for TCP
20499 * packets with IP ECN set to non-zero.
20501 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
20504 * When this bit is '1', the VNIC shall be configured to
20505 * perform transparent packet aggregation (TPA) for
20506 * GRE tunneled TCP packets only if all packets have the
20507 * same GRE sequence.
20509 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
20512 * When this bit is '1' and the GRO mode is enabled,
20513 * the VNIC shall be configured to
20514 * perform transparent packet aggregation (TPA) for
20515 * TCP/IPv4 packets with consecutively increasing IPIDs.
20516 * In other words, the last packet that is being
20517 * aggregated to an already existing aggregation context
20518 * shall have IPID 1 more than the IPID of the last packet
20519 * that was aggregated in that aggregation context.
20521 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
20524 * When this bit is '1' and the GRO mode is enabled,
20525 * the VNIC shall be configured to
20526 * perform transparent packet aggregation (TPA) for
20527 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
20530 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
20534 * This bit must be '1' for the max_agg_segs field to be
20537 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
20539 * This bit must be '1' for the max_aggs field to be
20542 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
20544 * This bit must be '1' for the max_agg_timer field to be
20547 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
20549 * This bit must be '1' for the min_agg_len field to be
20552 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
20553 /* Logical vnic ID */
20556 * This is the maximum number of TCP segments that can
20557 * be aggregated (unit is Log2). Max value is 31.
20559 uint16_t max_agg_segs;
20561 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
20563 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
20565 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
20567 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
20568 /* Any segment size larger than this is not valid */
20569 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
20570 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
20571 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
20573 * This is the maximum number of aggregations this VNIC is
20574 * allowed (unit is Log2). Max value is 7
20577 /* 1 aggregation */
20578 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
20579 /* 2 aggregations */
20580 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
20581 /* 4 aggregations */
20582 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
20583 /* 8 aggregations */
20584 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
20585 /* 16 aggregations */
20586 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
20587 /* Any aggregation size larger than this is not valid */
20588 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
20589 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
20590 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
20591 uint8_t unused_0[2];
20593 * This is the maximum amount of time allowed for
20594 * an aggregation context to complete after it was initiated.
20596 uint32_t max_agg_timer;
20598 * This is the minimum amount of payload length required to
20599 * start an aggregation context.
20601 uint32_t min_agg_len;
20602 } __attribute__((packed));
20604 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
20605 struct hwrm_vnic_tpa_cfg_output {
20606 /* The specific error status for the command. */
20607 uint16_t error_code;
20608 /* The HWRM command request type. */
20610 /* The sequence ID from the original command. */
20612 /* The length of the response data in number of bytes. */
20614 uint8_t unused_0[7];
20616 * This field is used in Output records to indicate that the output
20617 * is completely written to RAM. This field should be read as '1'
20618 * to indicate that the output has been completely written.
20619 * When writing a command completion or response to an internal processor,
20620 * the order of writes has to be such that this field is written last.
20623 } __attribute__((packed));
20625 /*********************
20626 * hwrm_vnic_rss_cfg *
20627 *********************/
20630 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
20631 struct hwrm_vnic_rss_cfg_input {
20632 /* The HWRM command request type. */
20635 * The completion ring to send the completion event on. This should
20636 * be the NQ ID returned from the `nq_alloc` HWRM command.
20638 uint16_t cmpl_ring;
20640 * The sequence ID is used by the driver for tracking multiple
20641 * commands. This ID is treated as opaque data by the firmware and
20642 * the value is returned in the `hwrm_resp_hdr` upon completion.
20646 * The target ID of the command:
20647 * * 0x0-0xFFF8 - The function ID
20648 * * 0xFFF8-0xFFFE - Reserved for internal processors
20651 uint16_t target_id;
20653 * A physical address pointer pointing to a host buffer that the
20654 * command's response data will be written. This can be either a host
20655 * physical address (HPA) or a guest physical address (GPA) and must
20656 * point to a physically contiguous block of memory.
20658 uint64_t resp_addr;
20659 uint32_t hash_type;
20661 * When this bit is '1', the RSS hash shall be computed
20662 * over source and destination IPv4 addresses of IPv4
20665 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
20667 * When this bit is '1', the RSS hash shall be computed
20668 * over source/destination IPv4 addresses and
20669 * source/destination ports of TCP/IPv4 packets.
20671 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
20673 * When this bit is '1', the RSS hash shall be computed
20674 * over source/destination IPv4 addresses and
20675 * source/destination ports of UDP/IPv4 packets.
20677 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
20679 * When this bit is '1', the RSS hash shall be computed
20680 * over source and destination IPv4 addresses of IPv6
20683 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
20685 * When this bit is '1', the RSS hash shall be computed
20686 * over source/destination IPv6 addresses and
20687 * source/destination ports of TCP/IPv6 packets.
20689 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
20691 * When this bit is '1', the RSS hash shall be computed
20692 * over source/destination IPv6 addresses and
20693 * source/destination ports of UDP/IPv6 packets.
20695 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
20696 /* VNIC ID of VNIC associated with RSS table being configured. */
20699 * Specifies which VNIC ring table pair to configure.
20700 * Valid values range from 0 to 7.
20702 uint8_t ring_table_pair_index;
20703 /* Flags to specify different RSS hash modes. */
20704 uint8_t hash_mode_flags;
20706 * When this bit is '1', it indicates using current RSS
20707 * hash mode setting configured in the device.
20709 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
20712 * When this bit is '1', it indicates requesting support of
20713 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
20714 * l4.src, l4.dest} for tunnel packets. For none-tunnel
20715 * packets, the RSS hash is computed over the normal
20716 * src/dest l3 and src/dest l4 headers.
20718 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
20721 * When this bit is '1', it indicates requesting support of
20722 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
20723 * tunnel packets. For none-tunnel packets, the RSS hash is
20724 * computed over the normal src/dest l3 headers.
20726 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
20729 * When this bit is '1', it indicates requesting support of
20730 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
20731 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
20732 * packets, the RSS hash is computed over the normal
20733 * src/dest l3 and src/dest l4 headers.
20735 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
20738 * When this bit is '1', it indicates requesting support of
20739 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
20740 * tunnel packets. For none-tunnel packets, the RSS hash is
20741 * computed over the normal src/dest l3 headers.
20743 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
20745 /* This is the address for rss ring group table */
20746 uint64_t ring_grp_tbl_addr;
20747 /* This is the address for rss hash key table */
20748 uint64_t hash_key_tbl_addr;
20749 /* Index to the rss indirection table. */
20750 uint16_t rss_ctx_idx;
20751 uint8_t unused_1[6];
20752 } __attribute__((packed));
20754 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
20755 struct hwrm_vnic_rss_cfg_output {
20756 /* The specific error status for the command. */
20757 uint16_t error_code;
20758 /* The HWRM command request type. */
20760 /* The sequence ID from the original command. */
20762 /* The length of the response data in number of bytes. */
20764 uint8_t unused_0[7];
20766 * This field is used in Output records to indicate that the output
20767 * is completely written to RAM. This field should be read as '1'
20768 * to indicate that the output has been completely written.
20769 * When writing a command completion or response to an internal processor,
20770 * the order of writes has to be such that this field is written last.
20773 } __attribute__((packed));
20775 /**********************
20776 * hwrm_vnic_rss_qcfg *
20777 **********************/
20780 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
20781 struct hwrm_vnic_rss_qcfg_input {
20782 /* The HWRM command request type. */
20785 * The completion ring to send the completion event on. This should
20786 * be the NQ ID returned from the `nq_alloc` HWRM command.
20788 uint16_t cmpl_ring;
20790 * The sequence ID is used by the driver for tracking multiple
20791 * commands. This ID is treated as opaque data by the firmware and
20792 * the value is returned in the `hwrm_resp_hdr` upon completion.
20796 * The target ID of the command:
20797 * * 0x0-0xFFF8 - The function ID
20798 * * 0xFFF8-0xFFFE - Reserved for internal processors
20801 uint16_t target_id;
20803 * A physical address pointer pointing to a host buffer that the
20804 * command's response data will be written. This can be either a host
20805 * physical address (HPA) or a guest physical address (GPA) and must
20806 * point to a physically contiguous block of memory.
20808 uint64_t resp_addr;
20809 /* Index to the rss indirection table. */
20810 uint16_t rss_ctx_idx;
20811 uint8_t unused_0[6];
20812 } __attribute__((packed));
20814 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
20815 struct hwrm_vnic_rss_qcfg_output {
20816 /* The specific error status for the command. */
20817 uint16_t error_code;
20818 /* The HWRM command request type. */
20820 /* The sequence ID from the original command. */
20822 /* The length of the response data in number of bytes. */
20824 uint32_t hash_type;
20826 * When this bit is '1', the RSS hash shall be computed
20827 * over source and destination IPv4 addresses of IPv4
20830 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
20832 * When this bit is '1', the RSS hash shall be computed
20833 * over source/destination IPv4 addresses and
20834 * source/destination ports of TCP/IPv4 packets.
20836 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
20838 * When this bit is '1', the RSS hash shall be computed
20839 * over source/destination IPv4 addresses and
20840 * source/destination ports of UDP/IPv4 packets.
20842 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
20844 * When this bit is '1', the RSS hash shall be computed
20845 * over source and destination IPv4 addresses of IPv6
20848 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
20850 * When this bit is '1', the RSS hash shall be computed
20851 * over source/destination IPv6 addresses and
20852 * source/destination ports of TCP/IPv6 packets.
20854 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
20856 * When this bit is '1', the RSS hash shall be computed
20857 * over source/destination IPv6 addresses and
20858 * source/destination ports of UDP/IPv6 packets.
20860 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
20861 uint8_t unused_0[4];
20862 /* This is the value of rss hash key */
20863 uint32_t hash_key[10];
20864 /* Flags to specify different RSS hash modes. */
20865 uint8_t hash_mode_flags;
20867 * When this bit is '1', it indicates using current RSS
20868 * hash mode setting configured in the device.
20870 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
20873 * When this bit is '1', it indicates requesting support of
20874 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
20875 * l4.src, l4.dest} for tunnel packets. For none-tunnel
20876 * packets, the RSS hash is computed over the normal
20877 * src/dest l3 and src/dest l4 headers.
20879 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
20882 * When this bit is '1', it indicates requesting support of
20883 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
20884 * tunnel packets. For none-tunnel packets, the RSS hash is
20885 * computed over the normal src/dest l3 headers.
20887 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
20890 * When this bit is '1', it indicates requesting support of
20891 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
20892 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
20893 * packets, the RSS hash is computed over the normal
20894 * src/dest l3 and src/dest l4 headers.
20896 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
20899 * When this bit is '1', it indicates requesting support of
20900 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
20901 * tunnel packets. For none-tunnel packets, the RSS hash is
20902 * computed over the normal src/dest l3 headers.
20904 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
20906 uint8_t unused_1[6];
20908 * This field is used in Output records to indicate that the output
20909 * is completely written to RAM. This field should be read as '1'
20910 * to indicate that the output has been completely written.
20911 * When writing a command completion or response to an internal processor,
20912 * the order of writes has to be such that this field is written last.
20915 } __attribute__((packed));
20917 /**************************
20918 * hwrm_vnic_plcmodes_cfg *
20919 **************************/
20922 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
20923 struct hwrm_vnic_plcmodes_cfg_input {
20924 /* The HWRM command request type. */
20927 * The completion ring to send the completion event on. This should
20928 * be the NQ ID returned from the `nq_alloc` HWRM command.
20930 uint16_t cmpl_ring;
20932 * The sequence ID is used by the driver for tracking multiple
20933 * commands. This ID is treated as opaque data by the firmware and
20934 * the value is returned in the `hwrm_resp_hdr` upon completion.
20938 * The target ID of the command:
20939 * * 0x0-0xFFF8 - The function ID
20940 * * 0xFFF8-0xFFFE - Reserved for internal processors
20943 uint16_t target_id;
20945 * A physical address pointer pointing to a host buffer that the
20946 * command's response data will be written. This can be either a host
20947 * physical address (HPA) or a guest physical address (GPA) and must
20948 * point to a physically contiguous block of memory.
20950 uint64_t resp_addr;
20953 * When this bit is '1', the VNIC shall be configured to
20954 * use regular placement algorithm.
20955 * By default, the regular placement algorithm shall be
20956 * enabled on the VNIC.
20958 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
20961 * When this bit is '1', the VNIC shall be configured
20962 * use the jumbo placement algorithm.
20964 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
20967 * When this bit is '1', the VNIC shall be configured
20968 * to enable Header-Data split for IPv4 packets according
20969 * to the following rules:
20970 * # If the packet is identified as TCP/IPv4, then the
20971 * packet is split at the beginning of the TCP payload.
20972 * # If the packet is identified as UDP/IPv4, then the
20973 * packet is split at the beginning of UDP payload.
20974 * # If the packet is identified as non-TCP and non-UDP
20975 * IPv4 packet, then the packet is split at the beginning
20976 * of the upper layer protocol header carried in the IPv4
20979 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
20982 * When this bit is '1', the VNIC shall be configured
20983 * to enable Header-Data split for IPv6 packets according
20984 * to the following rules:
20985 * # If the packet is identified as TCP/IPv6, then the
20986 * packet is split at the beginning of the TCP payload.
20987 * # If the packet is identified as UDP/IPv6, then the
20988 * packet is split at the beginning of UDP payload.
20989 * # If the packet is identified as non-TCP and non-UDP
20990 * IPv6 packet, then the packet is split at the beginning
20991 * of the upper layer protocol header carried in the IPv6
20994 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
20997 * When this bit is '1', the VNIC shall be configured
20998 * to enable Header-Data split for FCoE packets at the
20999 * beginning of FC payload.
21001 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
21004 * When this bit is '1', the VNIC shall be configured
21005 * to enable Header-Data split for RoCE packets at the
21006 * beginning of RoCE payload (after BTH/GRH headers).
21008 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
21012 * This bit must be '1' for the jumbo_thresh_valid field to be
21015 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
21018 * This bit must be '1' for the hds_offset_valid field to be
21021 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
21024 * This bit must be '1' for the hds_threshold_valid field to be
21027 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
21029 /* Logical vnic ID */
21032 * When jumbo placement algorithm is enabled, this value
21033 * is used to determine the threshold for jumbo placement.
21034 * Packets with length larger than this value will be
21035 * placed according to the jumbo placement algorithm.
21037 uint16_t jumbo_thresh;
21039 * This value is used to determine the offset into
21040 * packet buffer where the split data (payload) will be
21041 * placed according to one of of HDS placement algorithm.
21043 * The lengths of packet buffers provided for split data
21044 * shall be larger than this value.
21046 uint16_t hds_offset;
21048 * When one of the HDS placement algorithm is enabled, this
21049 * value is used to determine the threshold for HDS
21051 * Packets with length larger than this value will be
21052 * placed according to the HDS placement algorithm.
21053 * This value shall be in multiple of 4 bytes.
21055 uint16_t hds_threshold;
21056 uint8_t unused_0[6];
21057 } __attribute__((packed));
21059 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
21060 struct hwrm_vnic_plcmodes_cfg_output {
21061 /* The specific error status for the command. */
21062 uint16_t error_code;
21063 /* The HWRM command request type. */
21065 /* The sequence ID from the original command. */
21067 /* The length of the response data in number of bytes. */
21069 uint8_t unused_0[7];
21071 * This field is used in Output records to indicate that the output
21072 * is completely written to RAM. This field should be read as '1'
21073 * to indicate that the output has been completely written.
21074 * When writing a command completion or response to an internal processor,
21075 * the order of writes has to be such that this field is written last.
21078 } __attribute__((packed));
21080 /***************************
21081 * hwrm_vnic_plcmodes_qcfg *
21082 ***************************/
21085 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
21086 struct hwrm_vnic_plcmodes_qcfg_input {
21087 /* The HWRM command request type. */
21090 * The completion ring to send the completion event on. This should
21091 * be the NQ ID returned from the `nq_alloc` HWRM command.
21093 uint16_t cmpl_ring;
21095 * The sequence ID is used by the driver for tracking multiple
21096 * commands. This ID is treated as opaque data by the firmware and
21097 * the value is returned in the `hwrm_resp_hdr` upon completion.
21101 * The target ID of the command:
21102 * * 0x0-0xFFF8 - The function ID
21103 * * 0xFFF8-0xFFFE - Reserved for internal processors
21106 uint16_t target_id;
21108 * A physical address pointer pointing to a host buffer that the
21109 * command's response data will be written. This can be either a host
21110 * physical address (HPA) or a guest physical address (GPA) and must
21111 * point to a physically contiguous block of memory.
21113 uint64_t resp_addr;
21114 /* Logical vnic ID */
21116 uint8_t unused_0[4];
21117 } __attribute__((packed));
21119 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
21120 struct hwrm_vnic_plcmodes_qcfg_output {
21121 /* The specific error status for the command. */
21122 uint16_t error_code;
21123 /* The HWRM command request type. */
21125 /* The sequence ID from the original command. */
21127 /* The length of the response data in number of bytes. */
21131 * When this bit is '1', the VNIC is configured to
21132 * use regular placement algorithm.
21134 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
21137 * When this bit is '1', the VNIC is configured to
21138 * use the jumbo placement algorithm.
21140 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
21143 * When this bit is '1', the VNIC is configured
21144 * to enable Header-Data split for IPv4 packets.
21146 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
21149 * When this bit is '1', the VNIC is configured
21150 * to enable Header-Data split for IPv6 packets.
21152 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
21155 * When this bit is '1', the VNIC is configured
21156 * to enable Header-Data split for FCoE packets.
21158 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
21161 * When this bit is '1', the VNIC is configured
21162 * to enable Header-Data split for RoCE packets.
21164 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
21167 * When this bit is '1', the VNIC is configured
21168 * to be the default VNIC of the requesting function.
21170 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
21173 * When jumbo placement algorithm is enabled, this value
21174 * is used to determine the threshold for jumbo placement.
21175 * Packets with length larger than this value will be
21176 * placed according to the jumbo placement algorithm.
21178 uint16_t jumbo_thresh;
21180 * This value is used to determine the offset into
21181 * packet buffer where the split data (payload) will be
21182 * placed according to one of of HDS placement algorithm.
21184 * The lengths of packet buffers provided for split data
21185 * shall be larger than this value.
21187 uint16_t hds_offset;
21189 * When one of the HDS placement algorithm is enabled, this
21190 * value is used to determine the threshold for HDS
21192 * Packets with length larger than this value will be
21193 * placed according to the HDS placement algorithm.
21194 * This value shall be in multiple of 4 bytes.
21196 uint16_t hds_threshold;
21197 uint8_t unused_0[5];
21199 * This field is used in Output records to indicate that the output
21200 * is completely written to RAM. This field should be read as '1'
21201 * to indicate that the output has been completely written.
21202 * When writing a command completion or response to an internal processor,
21203 * the order of writes has to be such that this field is written last.
21206 } __attribute__((packed));
21208 /**********************************
21209 * hwrm_vnic_rss_cos_lb_ctx_alloc *
21210 **********************************/
21213 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
21214 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
21215 /* The HWRM command request type. */
21218 * The completion ring to send the completion event on. This should
21219 * be the NQ ID returned from the `nq_alloc` HWRM command.
21221 uint16_t cmpl_ring;
21223 * The sequence ID is used by the driver for tracking multiple
21224 * commands. This ID is treated as opaque data by the firmware and
21225 * the value is returned in the `hwrm_resp_hdr` upon completion.
21229 * The target ID of the command:
21230 * * 0x0-0xFFF8 - The function ID
21231 * * 0xFFF8-0xFFFE - Reserved for internal processors
21234 uint16_t target_id;
21236 * A physical address pointer pointing to a host buffer that the
21237 * command's response data will be written. This can be either a host
21238 * physical address (HPA) or a guest physical address (GPA) and must
21239 * point to a physically contiguous block of memory.
21241 uint64_t resp_addr;
21242 } __attribute__((packed));
21244 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
21245 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
21246 /* The specific error status for the command. */
21247 uint16_t error_code;
21248 /* The HWRM command request type. */
21250 /* The sequence ID from the original command. */
21252 /* The length of the response data in number of bytes. */
21254 /* rss_cos_lb_ctx_id is 16 b */
21255 uint16_t rss_cos_lb_ctx_id;
21256 uint8_t unused_0[5];
21258 * This field is used in Output records to indicate that the output
21259 * is completely written to RAM. This field should be read as '1'
21260 * to indicate that the output has been completely written.
21261 * When writing a command completion or response to an internal processor,
21262 * the order of writes has to be such that this field is written last.
21265 } __attribute__((packed));
21267 /*********************************
21268 * hwrm_vnic_rss_cos_lb_ctx_free *
21269 *********************************/
21272 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
21273 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
21274 /* The HWRM command request type. */
21277 * The completion ring to send the completion event on. This should
21278 * be the NQ ID returned from the `nq_alloc` HWRM command.
21280 uint16_t cmpl_ring;
21282 * The sequence ID is used by the driver for tracking multiple
21283 * commands. This ID is treated as opaque data by the firmware and
21284 * the value is returned in the `hwrm_resp_hdr` upon completion.
21288 * The target ID of the command:
21289 * * 0x0-0xFFF8 - The function ID
21290 * * 0xFFF8-0xFFFE - Reserved for internal processors
21293 uint16_t target_id;
21295 * A physical address pointer pointing to a host buffer that the
21296 * command's response data will be written. This can be either a host
21297 * physical address (HPA) or a guest physical address (GPA) and must
21298 * point to a physically contiguous block of memory.
21300 uint64_t resp_addr;
21301 /* rss_cos_lb_ctx_id is 16 b */
21302 uint16_t rss_cos_lb_ctx_id;
21303 uint8_t unused_0[6];
21304 } __attribute__((packed));
21306 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
21307 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
21308 /* The specific error status for the command. */
21309 uint16_t error_code;
21310 /* The HWRM command request type. */
21312 /* The sequence ID from the original command. */
21314 /* The length of the response data in number of bytes. */
21316 uint8_t unused_0[7];
21318 * This field is used in Output records to indicate that the output
21319 * is completely written to RAM. This field should be read as '1'
21320 * to indicate that the output has been completely written.
21321 * When writing a command completion or response to an internal processor,
21322 * the order of writes has to be such that this field is written last.
21325 } __attribute__((packed));
21327 /*******************
21328 * hwrm_ring_alloc *
21329 *******************/
21332 /* hwrm_ring_alloc_input (size:704b/88B) */
21333 struct hwrm_ring_alloc_input {
21334 /* The HWRM command request type. */
21337 * The completion ring to send the completion event on. This should
21338 * be the NQ ID returned from the `nq_alloc` HWRM command.
21340 uint16_t cmpl_ring;
21342 * The sequence ID is used by the driver for tracking multiple
21343 * commands. This ID is treated as opaque data by the firmware and
21344 * the value is returned in the `hwrm_resp_hdr` upon completion.
21348 * The target ID of the command:
21349 * * 0x0-0xFFF8 - The function ID
21350 * * 0xFFF8-0xFFFE - Reserved for internal processors
21353 uint16_t target_id;
21355 * A physical address pointer pointing to a host buffer that the
21356 * command's response data will be written. This can be either a host
21357 * physical address (HPA) or a guest physical address (GPA) and must
21358 * point to a physically contiguous block of memory.
21360 uint64_t resp_addr;
21363 * This bit must be '1' for the ring_arb_cfg field to be
21366 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
21369 * This bit must be '1' for the stat_ctx_id_valid field to be
21372 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
21375 * This bit must be '1' for the max_bw_valid field to be
21378 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
21381 * This bit must be '1' for the rx_ring_id field to be
21384 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
21387 * This bit must be '1' for the nq_ring_id field to be
21390 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
21393 * This bit must be '1' for the rx_buf_size field to be
21396 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
21400 /* L2 Completion Ring (CR) */
21401 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
21403 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
21405 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
21406 /* RoCE Notification Completion Ring (ROCE_CR) */
21407 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
21408 /* RX Aggregation Ring */
21409 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
21410 /* Notification Queue */
21411 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
21412 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
21413 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
21415 /* Ring allocation flags. */
21418 * For Rx rings, the incoming packet data can be placed at either
21419 * a 0B or 2B offset from the start of the Rx packet buffer. When
21420 * '1', the received packet will be padded with 2B of zeros at the
21421 * front of the packet. Note that this flag is only used for
21422 * Rx rings and is ignored for all other rings included Rx
21423 * Aggregation rings.
21425 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
21427 * This value is a pointer to the page table for the
21430 uint64_t page_tbl_addr;
21431 /* First Byte Offset of the first entry in the first page. */
21434 * Actual page size in 2^page_size. The supported range is increments
21435 * in powers of 2 from 16 bytes to 1GB.
21437 * Page size is 16 B.
21439 * Page size is 4 KB.
21441 * Page size is 8 KB.
21443 * Page size is 64 KB.
21445 * Page size is 2 MB.
21447 * Page size is 4 MB.
21449 * Page size is 1 GB.
21453 * This value indicates the depth of page table.
21454 * For this version of the specification, value other than 0 or
21455 * 1 shall be considered as an invalid value.
21456 * When the page_tbl_depth = 0, then it is treated as a
21457 * special case with the following.
21458 * 1. FBO and page size fields are not valid.
21459 * 2. page_tbl_addr is the physical address of the first
21460 * element of the ring.
21462 uint8_t page_tbl_depth;
21463 uint8_t unused_1[2];
21465 * Number of 16B units in the ring. Minimum size for
21466 * a ring is 16 16B entries.
21470 * Logical ring number for the ring to be allocated.
21471 * This value determines the position in the doorbell
21472 * area where the update to the ring will be made.
21474 * For completion rings, this value is also the MSI-X
21475 * vector number for the function the completion ring is
21478 uint16_t logical_id;
21480 * This field is used only when ring_type is a TX ring.
21481 * This value indicates what completion ring the TX ring
21482 * is associated with.
21484 uint16_t cmpl_ring_id;
21486 * This field is used only when ring_type is a TX ring.
21487 * This value indicates what CoS queue the TX ring
21488 * is associated with.
21492 * When allocating a Rx ring or Rx aggregation ring, this field
21493 * specifies the size of the buffer descriptors posted to the ring.
21495 uint16_t rx_buf_size;
21497 * When allocating an Rx aggregation ring, this field
21498 * specifies the associated Rx ring ID.
21500 uint16_t rx_ring_id;
21502 * When allocating a completion ring, this field
21503 * specifies the associated NQ ring ID.
21505 uint16_t nq_ring_id;
21507 * This field is used only when ring_type is a TX ring.
21508 * This field is used to configure arbitration related
21509 * parameters for a TX ring.
21511 uint16_t ring_arb_cfg;
21512 /* Arbitration policy used for the ring. */
21513 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
21515 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
21517 * Use strict priority for the TX ring.
21518 * Priority value is specified in arb_policy_param
21520 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
21523 * Use weighted fair queue arbitration for the TX ring.
21524 * Weight is specified in arb_policy_param
21526 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
21528 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
21529 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
21530 /* Reserved field. */
21531 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
21533 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
21535 * Arbitration policy specific parameter.
21536 * # For strict priority arbitration policy, this field
21537 * represents a priority value. If set to 0, then the priority
21538 * is not specified and the HWRM is allowed to select
21539 * any priority for this TX ring.
21540 * # For weighted fair queue arbitration policy, this field
21541 * represents a weight value. If set to 0, then the weight
21542 * is not specified and the HWRM is allowed to select
21543 * any weight for this TX ring.
21545 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
21547 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
21550 * This field is reserved for the future use.
21551 * It shall be set to 0.
21553 uint32_t reserved3;
21555 * This field is used only when ring_type is a TX ring.
21556 * This input indicates what statistics context this ring
21557 * should be associated with.
21559 uint32_t stat_ctx_id;
21561 * This field is reserved for the future use.
21562 * It shall be set to 0.
21564 uint32_t reserved4;
21566 * This field is used only when ring_type is a TX ring
21567 * to specify maximum BW allocated to the TX ring.
21568 * The HWRM will translate this value into byte counter and
21569 * time interval used for this ring inside the device.
21572 /* The bandwidth value. */
21573 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
21574 UINT32_C(0xfffffff)
21575 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
21576 /* The granularity of the value (bits or bytes). */
21577 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
21578 UINT32_C(0x10000000)
21579 /* Value is in bits. */
21580 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
21581 (UINT32_C(0x0) << 28)
21582 /* Value is in bytes. */
21583 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
21584 (UINT32_C(0x1) << 28)
21585 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
21586 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
21587 /* bw_value_unit is 3 b */
21588 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
21589 UINT32_C(0xe0000000)
21590 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
21591 /* Value is in Mb or MB (base 10). */
21592 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
21593 (UINT32_C(0x0) << 29)
21594 /* Value is in Kb or KB (base 10). */
21595 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
21596 (UINT32_C(0x2) << 29)
21597 /* Value is in bits or bytes. */
21598 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
21599 (UINT32_C(0x4) << 29)
21600 /* Value is in Gb or GB (base 10). */
21601 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
21602 (UINT32_C(0x6) << 29)
21603 /* Value is in 1/100th of a percentage of total bandwidth. */
21604 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21605 (UINT32_C(0x1) << 29)
21607 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
21608 (UINT32_C(0x7) << 29)
21609 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
21610 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
21612 * This field is used only when ring_type is a Completion ring.
21613 * This value indicates what interrupt mode should be used
21614 * on this completion ring.
21615 * Note: In the legacy interrupt mode, no more than 16
21616 * completion rings are allowed.
21620 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
21622 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
21624 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
21625 /* No Interrupt - Polled mode */
21626 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
21627 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
21628 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
21629 uint8_t unused_4[3];
21631 * The cq_handle is specified when allocating a completion ring. For
21632 * devices that support NQs, this cq_handle will be included in the
21633 * NQE to specify which CQ should be read to retrieve the completion
21636 uint64_t cq_handle;
21637 } __attribute__((packed));
21639 /* hwrm_ring_alloc_output (size:128b/16B) */
21640 struct hwrm_ring_alloc_output {
21641 /* The specific error status for the command. */
21642 uint16_t error_code;
21643 /* The HWRM command request type. */
21645 /* The sequence ID from the original command. */
21647 /* The length of the response data in number of bytes. */
21650 * Physical number of ring allocated.
21651 * This value shall be unique for a ring type.
21654 /* Logical number of ring allocated. */
21655 uint16_t logical_ring_id;
21656 uint8_t unused_0[3];
21658 * This field is used in Output records to indicate that the output
21659 * is completely written to RAM. This field should be read as '1'
21660 * to indicate that the output has been completely written.
21661 * When writing a command completion or response to an internal processor,
21662 * the order of writes has to be such that this field is written last.
21665 } __attribute__((packed));
21667 /******************
21669 ******************/
21672 /* hwrm_ring_free_input (size:192b/24B) */
21673 struct hwrm_ring_free_input {
21674 /* The HWRM command request type. */
21677 * The completion ring to send the completion event on. This should
21678 * be the NQ ID returned from the `nq_alloc` HWRM command.
21680 uint16_t cmpl_ring;
21682 * The sequence ID is used by the driver for tracking multiple
21683 * commands. This ID is treated as opaque data by the firmware and
21684 * the value is returned in the `hwrm_resp_hdr` upon completion.
21688 * The target ID of the command:
21689 * * 0x0-0xFFF8 - The function ID
21690 * * 0xFFF8-0xFFFE - Reserved for internal processors
21693 uint16_t target_id;
21695 * A physical address pointer pointing to a host buffer that the
21696 * command's response data will be written. This can be either a host
21697 * physical address (HPA) or a guest physical address (GPA) and must
21698 * point to a physically contiguous block of memory.
21700 uint64_t resp_addr;
21703 /* L2 Completion Ring (CR) */
21704 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
21706 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
21708 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
21709 /* RoCE Notification Completion Ring (ROCE_CR) */
21710 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
21711 /* RX Aggregation Ring */
21712 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
21713 /* Notification Queue */
21714 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
21715 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
21716 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
21718 /* Physical number of ring allocated. */
21720 uint8_t unused_1[4];
21721 } __attribute__((packed));
21723 /* hwrm_ring_free_output (size:128b/16B) */
21724 struct hwrm_ring_free_output {
21725 /* The specific error status for the command. */
21726 uint16_t error_code;
21727 /* The HWRM command request type. */
21729 /* The sequence ID from the original command. */
21731 /* The length of the response data in number of bytes. */
21733 uint8_t unused_0[7];
21735 * This field is used in Output records to indicate that the output
21736 * is completely written to RAM. This field should be read as '1'
21737 * to indicate that the output has been completely written.
21738 * When writing a command completion or response to an internal processor,
21739 * the order of writes has to be such that this field is written last.
21742 } __attribute__((packed));
21744 /*******************
21745 * hwrm_ring_reset *
21746 *******************/
21749 /* hwrm_ring_reset_input (size:192b/24B) */
21750 struct hwrm_ring_reset_input {
21751 /* The HWRM command request type. */
21754 * The completion ring to send the completion event on. This should
21755 * be the NQ ID returned from the `nq_alloc` HWRM command.
21757 uint16_t cmpl_ring;
21759 * The sequence ID is used by the driver for tracking multiple
21760 * commands. This ID is treated as opaque data by the firmware and
21761 * the value is returned in the `hwrm_resp_hdr` upon completion.
21765 * The target ID of the command:
21766 * * 0x0-0xFFF8 - The function ID
21767 * * 0xFFF8-0xFFFE - Reserved for internal processors
21770 uint16_t target_id;
21772 * A physical address pointer pointing to a host buffer that the
21773 * command's response data will be written. This can be either a host
21774 * physical address (HPA) or a guest physical address (GPA) and must
21775 * point to a physically contiguous block of memory.
21777 uint64_t resp_addr;
21780 /* L2 Completion Ring (CR) */
21781 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
21783 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
21785 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
21786 /* RoCE Notification Completion Ring (ROCE_CR) */
21787 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
21788 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
21789 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
21791 /* Physical number of the ring. */
21793 uint8_t unused_1[4];
21794 } __attribute__((packed));
21796 /* hwrm_ring_reset_output (size:128b/16B) */
21797 struct hwrm_ring_reset_output {
21798 /* The specific error status for the command. */
21799 uint16_t error_code;
21800 /* The HWRM command request type. */
21802 /* The sequence ID from the original command. */
21804 /* The length of the response data in number of bytes. */
21806 uint8_t unused_0[4];
21807 /* Position of consumer index after ring reset completes. */
21808 uint8_t consumer_idx[3];
21810 * This field is used in Output records to indicate that the output
21811 * is completely written to RAM. This field should be read as '1'
21812 * to indicate that the output has been completely written.
21813 * When writing a command completion or response to an internal processor,
21814 * the order of writes has to be such that this field is written last.
21817 } __attribute__((packed));
21819 /**************************
21820 * hwrm_ring_aggint_qcaps *
21821 **************************/
21824 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
21825 struct hwrm_ring_aggint_qcaps_input {
21826 /* The HWRM command request type. */
21829 * The completion ring to send the completion event on. This should
21830 * be the NQ ID returned from the `nq_alloc` HWRM command.
21832 uint16_t cmpl_ring;
21834 * The sequence ID is used by the driver for tracking multiple
21835 * commands. This ID is treated as opaque data by the firmware and
21836 * the value is returned in the `hwrm_resp_hdr` upon completion.
21840 * The target ID of the command:
21841 * * 0x0-0xFFF8 - The function ID
21842 * * 0xFFF8-0xFFFE - Reserved for internal processors
21845 uint16_t target_id;
21847 * A physical address pointer pointing to a host buffer that the
21848 * command's response data will be written. This can be either a host
21849 * physical address (HPA) or a guest physical address (GPA) and must
21850 * point to a physically contiguous block of memory.
21852 uint64_t resp_addr;
21853 } __attribute__((packed));
21855 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
21856 struct hwrm_ring_aggint_qcaps_output {
21857 /* The specific error status for the command. */
21858 uint16_t error_code;
21859 /* The HWRM command request type. */
21861 /* The sequence ID from the original command. */
21863 /* The length of the response data in number of bytes. */
21865 uint32_t cmpl_params;
21867 * When this bit is set to '1', int_lat_tmr_min can be configured
21868 * on completion rings.
21870 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
21873 * When this bit is set to '1', int_lat_tmr_max can be configured
21874 * on completion rings.
21876 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
21879 * When this bit is set to '1', timer_reset can be enabled
21880 * on completion rings.
21882 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
21885 * When this bit is set to '1', ring_idle can be enabled
21886 * on completion rings.
21888 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
21891 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
21892 * on completion rings.
21894 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
21897 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
21898 * on completion rings.
21900 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
21903 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
21904 * on completion rings.
21906 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
21909 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
21910 * on completion rings.
21912 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
21915 * When this bit is set to '1', num_cmpl_aggr_int can be configured
21916 * on completion rings.
21918 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
21920 uint32_t nq_params;
21922 * When this bit is set to '1', int_lat_tmr_min can be configured
21923 * on notification queues.
21925 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
21927 /* Minimum value for num_cmpl_dma_aggr */
21928 uint16_t num_cmpl_dma_aggr_min;
21929 /* Maximum value for num_cmpl_dma_aggr */
21930 uint16_t num_cmpl_dma_aggr_max;
21931 /* Minimum value for num_cmpl_dma_aggr_during_int */
21932 uint16_t num_cmpl_dma_aggr_during_int_min;
21933 /* Maximum value for num_cmpl_dma_aggr_during_int */
21934 uint16_t num_cmpl_dma_aggr_during_int_max;
21935 /* Minimum value for cmpl_aggr_dma_tmr */
21936 uint16_t cmpl_aggr_dma_tmr_min;
21937 /* Maximum value for cmpl_aggr_dma_tmr */
21938 uint16_t cmpl_aggr_dma_tmr_max;
21939 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
21940 uint16_t cmpl_aggr_dma_tmr_during_int_min;
21941 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
21942 uint16_t cmpl_aggr_dma_tmr_during_int_max;
21943 /* Minimum value for int_lat_tmr_min */
21944 uint16_t int_lat_tmr_min_min;
21945 /* Maximum value for int_lat_tmr_min */
21946 uint16_t int_lat_tmr_min_max;
21947 /* Minimum value for int_lat_tmr_max */
21948 uint16_t int_lat_tmr_max_min;
21949 /* Maximum value for int_lat_tmr_max */
21950 uint16_t int_lat_tmr_max_max;
21951 /* Minimum value for num_cmpl_aggr_int */
21952 uint16_t num_cmpl_aggr_int_min;
21953 /* Maximum value for num_cmpl_aggr_int */
21954 uint16_t num_cmpl_aggr_int_max;
21955 /* The units for timer parameters, in nanoseconds. */
21956 uint16_t timer_units;
21957 uint8_t unused_0[1];
21959 * This field is used in Output records to indicate that the output
21960 * is completely written to RAM. This field should be read as '1'
21961 * to indicate that the output has been completely written.
21962 * When writing a command completion or response to an internal processor,
21963 * the order of writes has to be such that this field is written last.
21966 } __attribute__((packed));
21968 /**************************************
21969 * hwrm_ring_cmpl_ring_qaggint_params *
21970 **************************************/
21973 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
21974 struct hwrm_ring_cmpl_ring_qaggint_params_input {
21975 /* The HWRM command request type. */
21978 * The completion ring to send the completion event on. This should
21979 * be the NQ ID returned from the `nq_alloc` HWRM command.
21981 uint16_t cmpl_ring;
21983 * The sequence ID is used by the driver for tracking multiple
21984 * commands. This ID is treated as opaque data by the firmware and
21985 * the value is returned in the `hwrm_resp_hdr` upon completion.
21989 * The target ID of the command:
21990 * * 0x0-0xFFF8 - The function ID
21991 * * 0xFFF8-0xFFFE - Reserved for internal processors
21994 uint16_t target_id;
21996 * A physical address pointer pointing to a host buffer that the
21997 * command's response data will be written. This can be either a host
21998 * physical address (HPA) or a guest physical address (GPA) and must
21999 * point to a physically contiguous block of memory.
22001 uint64_t resp_addr;
22002 /* Physical number of completion ring. */
22004 uint8_t unused_0[6];
22005 } __attribute__((packed));
22007 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
22008 struct hwrm_ring_cmpl_ring_qaggint_params_output {
22009 /* The specific error status for the command. */
22010 uint16_t error_code;
22011 /* The HWRM command request type. */
22013 /* The sequence ID from the original command. */
22015 /* The length of the response data in number of bytes. */
22019 * When this bit is set to '1', interrupt max
22020 * timer is reset whenever a completion is received.
22022 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
22025 * When this bit is set to '1', ring idle mode
22026 * aggregation will be enabled.
22028 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
22031 * Number of completions to aggregate before DMA
22032 * during the normal mode.
22034 uint16_t num_cmpl_dma_aggr;
22036 * Number of completions to aggregate before DMA
22037 * during the interrupt mode.
22039 uint16_t num_cmpl_dma_aggr_during_int;
22041 * Timer in unit of 80-nsec used to aggregate completions before
22042 * DMA during the normal mode (not in interrupt mode).
22044 uint16_t cmpl_aggr_dma_tmr;
22046 * Timer in unit of 80-nsec used to aggregate completions before
22047 * DMA during the interrupt mode.
22049 uint16_t cmpl_aggr_dma_tmr_during_int;
22050 /* Minimum time (in unit of 80-nsec) between two interrupts. */
22051 uint16_t int_lat_tmr_min;
22053 * Maximum wait time (in unit of 80-nsec) spent aggregating
22054 * completions before signaling the interrupt after the
22055 * interrupt is enabled.
22057 uint16_t int_lat_tmr_max;
22059 * Minimum number of completions aggregated before signaling
22062 uint16_t num_cmpl_aggr_int;
22063 uint8_t unused_0[7];
22065 * This field is used in Output records to indicate that the output
22066 * is completely written to RAM. This field should be read as '1'
22067 * to indicate that the output has been completely written.
22068 * When writing a command completion or response to an internal processor,
22069 * the order of writes has to be such that this field is written last.
22072 } __attribute__((packed));
22074 /*****************************************
22075 * hwrm_ring_cmpl_ring_cfg_aggint_params *
22076 *****************************************/
22079 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
22080 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
22081 /* The HWRM command request type. */
22084 * The completion ring to send the completion event on. This should
22085 * be the NQ ID returned from the `nq_alloc` HWRM command.
22087 uint16_t cmpl_ring;
22089 * The sequence ID is used by the driver for tracking multiple
22090 * commands. This ID is treated as opaque data by the firmware and
22091 * the value is returned in the `hwrm_resp_hdr` upon completion.
22095 * The target ID of the command:
22096 * * 0x0-0xFFF8 - The function ID
22097 * * 0xFFF8-0xFFFE - Reserved for internal processors
22100 uint16_t target_id;
22102 * A physical address pointer pointing to a host buffer that the
22103 * command's response data will be written. This can be either a host
22104 * physical address (HPA) or a guest physical address (GPA) and must
22105 * point to a physically contiguous block of memory.
22107 uint64_t resp_addr;
22108 /* Physical number of completion ring. */
22112 * When this bit is set to '1', interrupt latency max
22113 * timer is reset whenever a completion is received.
22115 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
22118 * When this bit is set to '1', ring idle mode
22119 * aggregation will be enabled.
22121 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
22124 * Set this flag to 1 when configuring parameters on a
22125 * notification queue. Set this flag to 0 when configuring
22126 * parameters on a completion queue.
22128 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
22131 * Number of completions to aggregate before DMA
22132 * during the normal mode.
22134 uint16_t num_cmpl_dma_aggr;
22136 * Number of completions to aggregate before DMA
22137 * during the interrupt mode.
22139 uint16_t num_cmpl_dma_aggr_during_int;
22141 * Timer in unit of 80-nsec used to aggregate completions before
22142 * DMA during the normal mode (not in interrupt mode).
22144 uint16_t cmpl_aggr_dma_tmr;
22146 * Timer in unit of 80-nsec used to aggregate completions before
22147 * DMA during the interrupt mode.
22149 uint16_t cmpl_aggr_dma_tmr_during_int;
22150 /* Minimum time (in unit of 80-nsec) between two interrupts. */
22151 uint16_t int_lat_tmr_min;
22153 * Maximum wait time (in unit of 80-nsec) spent aggregating
22154 * cmpls before signaling the interrupt after the
22155 * interrupt is enabled.
22157 uint16_t int_lat_tmr_max;
22159 * Minimum number of completions aggregated before signaling
22162 uint16_t num_cmpl_aggr_int;
22164 * Bitfield that indicates which parameters are to be applied. Only
22165 * required when configuring devices with notification queues, and
22166 * used in that case to set certain parameters on completion queues
22167 * and others on notification queues.
22171 * This bit must be '1' for the num_cmpl_dma_aggr field to be
22174 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
22177 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
22180 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
22183 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
22186 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
22189 * This bit must be '1' for the int_lat_tmr_min field to be
22192 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
22195 * This bit must be '1' for the int_lat_tmr_max field to be
22198 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
22201 * This bit must be '1' for the num_cmpl_aggr_int field to be
22204 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
22206 uint8_t unused_0[4];
22207 } __attribute__((packed));
22209 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
22210 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
22211 /* The specific error status for the command. */
22212 uint16_t error_code;
22213 /* The HWRM command request type. */
22215 /* The sequence ID from the original command. */
22217 /* The length of the response data in number of bytes. */
22219 uint8_t unused_0[7];
22221 * This field is used in Output records to indicate that the output
22222 * is completely written to RAM. This field should be read as '1'
22223 * to indicate that the output has been completely written.
22224 * When writing a command completion or response to an internal processor,
22225 * the order of writes has to be such that this field is written last.
22228 } __attribute__((packed));
22230 /***********************
22231 * hwrm_ring_grp_alloc *
22232 ***********************/
22235 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
22236 struct hwrm_ring_grp_alloc_input {
22237 /* The HWRM command request type. */
22240 * The completion ring to send the completion event on. This should
22241 * be the NQ ID returned from the `nq_alloc` HWRM command.
22243 uint16_t cmpl_ring;
22245 * The sequence ID is used by the driver for tracking multiple
22246 * commands. This ID is treated as opaque data by the firmware and
22247 * the value is returned in the `hwrm_resp_hdr` upon completion.
22251 * The target ID of the command:
22252 * * 0x0-0xFFF8 - The function ID
22253 * * 0xFFF8-0xFFFE - Reserved for internal processors
22256 uint16_t target_id;
22258 * A physical address pointer pointing to a host buffer that the
22259 * command's response data will be written. This can be either a host
22260 * physical address (HPA) or a guest physical address (GPA) and must
22261 * point to a physically contiguous block of memory.
22263 uint64_t resp_addr;
22265 * This value identifies the CR associated with the ring
22270 * This value identifies the main RR associated with the ring
22275 * This value identifies the aggregation RR associated with
22276 * the ring group. If this value is 0xFF... (All Fs), then no
22277 * Aggregation ring will be set.
22281 * This value identifies the statistics context associated
22282 * with the ring group.
22285 } __attribute__((packed));
22287 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
22288 struct hwrm_ring_grp_alloc_output {
22289 /* The specific error status for the command. */
22290 uint16_t error_code;
22291 /* The HWRM command request type. */
22293 /* The sequence ID from the original command. */
22295 /* The length of the response data in number of bytes. */
22298 * This is the ring group ID value. Use this value to program
22299 * the default ring group for the VNIC or as table entries
22300 * in an RSS/COS context.
22302 uint32_t ring_group_id;
22303 uint8_t unused_0[3];
22305 * This field is used in Output records to indicate that the output
22306 * is completely written to RAM. This field should be read as '1'
22307 * to indicate that the output has been completely written.
22308 * When writing a command completion or response to an internal processor,
22309 * the order of writes has to be such that this field is written last.
22312 } __attribute__((packed));
22314 /**********************
22315 * hwrm_ring_grp_free *
22316 **********************/
22319 /* hwrm_ring_grp_free_input (size:192b/24B) */
22320 struct hwrm_ring_grp_free_input {
22321 /* The HWRM command request type. */
22324 * The completion ring to send the completion event on. This should
22325 * be the NQ ID returned from the `nq_alloc` HWRM command.
22327 uint16_t cmpl_ring;
22329 * The sequence ID is used by the driver for tracking multiple
22330 * commands. This ID is treated as opaque data by the firmware and
22331 * the value is returned in the `hwrm_resp_hdr` upon completion.
22335 * The target ID of the command:
22336 * * 0x0-0xFFF8 - The function ID
22337 * * 0xFFF8-0xFFFE - Reserved for internal processors
22340 uint16_t target_id;
22342 * A physical address pointer pointing to a host buffer that the
22343 * command's response data will be written. This can be either a host
22344 * physical address (HPA) or a guest physical address (GPA) and must
22345 * point to a physically contiguous block of memory.
22347 uint64_t resp_addr;
22348 /* This is the ring group ID value. */
22349 uint32_t ring_group_id;
22350 uint8_t unused_0[4];
22351 } __attribute__((packed));
22353 /* hwrm_ring_grp_free_output (size:128b/16B) */
22354 struct hwrm_ring_grp_free_output {
22355 /* The specific error status for the command. */
22356 uint16_t error_code;
22357 /* The HWRM command request type. */
22359 /* The sequence ID from the original command. */
22361 /* The length of the response data in number of bytes. */
22363 uint8_t unused_0[7];
22365 * This field is used in Output records to indicate that the output
22366 * is completely written to RAM. This field should be read as '1'
22367 * to indicate that the output has been completely written.
22368 * When writing a command completion or response to an internal processor,
22369 * the order of writes has to be such that this field is written last.
22372 } __attribute__((packed));
22374 * special reserved flow ID to identify per function default
22375 * flows for vSwitch offload
22377 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
22379 * special reserved flow ID to identify per function RoCEv1
22382 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
22384 * special reserved flow ID to identify per function RoCEv2
22387 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
22389 * special reserved flow ID to identify per function RoCEv2
22392 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
22394 /****************************
22395 * hwrm_cfa_l2_filter_alloc *
22396 ****************************/
22399 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
22400 struct hwrm_cfa_l2_filter_alloc_input {
22401 /* The HWRM command request type. */
22404 * The completion ring to send the completion event on. This should
22405 * be the NQ ID returned from the `nq_alloc` HWRM command.
22407 uint16_t cmpl_ring;
22409 * The sequence ID is used by the driver for tracking multiple
22410 * commands. This ID is treated as opaque data by the firmware and
22411 * the value is returned in the `hwrm_resp_hdr` upon completion.
22415 * The target ID of the command:
22416 * * 0x0-0xFFF8 - The function ID
22417 * * 0xFFF8-0xFFFE - Reserved for internal processors
22420 uint16_t target_id;
22422 * A physical address pointer pointing to a host buffer that the
22423 * command's response data will be written. This can be either a host
22424 * physical address (HPA) or a guest physical address (GPA) and must
22425 * point to a physically contiguous block of memory.
22427 uint64_t resp_addr;
22430 * Enumeration denoting the RX, TX type of the resource.
22431 * This enumeration is used for resources that are similar for both
22432 * TX and RX paths of the chip.
22434 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
22437 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
22440 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
22442 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
22443 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
22444 /* Setting of this flag indicates the applicability to the loopback path. */
22445 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
22448 * Setting of this flag indicates drop action. If this flag is not set,
22449 * then it should be considered accept action.
22451 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
22454 * If this flag is set, all t_l2_* fields are invalid
22455 * and they should not be specified.
22456 * If this flag is set, then l2_* fields refer to
22457 * fields of outermost L2 header.
22459 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
22462 * Enumeration denoting NO_ROCE_L2 to support old drivers.
22463 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
22465 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
22467 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
22468 /* To support old drivers */
22469 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
22470 (UINT32_C(0x0) << 4)
22471 /* Only L2 traffic */
22472 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
22473 (UINT32_C(0x1) << 4)
22474 /* Roce & L2 traffic */
22475 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
22476 (UINT32_C(0x2) << 4)
22477 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
22478 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
22481 * This bit must be '1' for the l2_addr field to be
22484 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
22487 * This bit must be '1' for the l2_addr_mask field to be
22490 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
22493 * This bit must be '1' for the l2_ovlan field to be
22496 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
22499 * This bit must be '1' for the l2_ovlan_mask field to be
22502 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
22505 * This bit must be '1' for the l2_ivlan field to be
22508 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
22511 * This bit must be '1' for the l2_ivlan_mask field to be
22514 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
22517 * This bit must be '1' for the t_l2_addr field to be
22520 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
22523 * This bit must be '1' for the t_l2_addr_mask field to be
22526 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
22529 * This bit must be '1' for the t_l2_ovlan field to be
22532 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
22535 * This bit must be '1' for the t_l2_ovlan_mask field to be
22538 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
22541 * This bit must be '1' for the t_l2_ivlan field to be
22544 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
22547 * This bit must be '1' for the t_l2_ivlan_mask field to be
22550 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
22553 * This bit must be '1' for the src_type field to be
22556 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
22559 * This bit must be '1' for the src_id field to be
22562 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
22565 * This bit must be '1' for the tunnel_type field to be
22568 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
22571 * This bit must be '1' for the dst_id field to be
22574 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
22577 * This bit must be '1' for the mirror_vnic_id field to be
22580 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
22583 * This value sets the match value for the L2 MAC address.
22584 * Destination MAC address for RX path.
22585 * Source MAC address for TX path.
22587 uint8_t l2_addr[6];
22588 uint8_t unused_0[2];
22590 * This value sets the mask value for the L2 address.
22591 * A value of 0 will mask the corresponding bit from
22594 uint8_t l2_addr_mask[6];
22595 /* This value sets VLAN ID value for outer VLAN. */
22598 * This value sets the mask value for the ovlan id.
22599 * A value of 0 will mask the corresponding bit from
22602 uint16_t l2_ovlan_mask;
22603 /* This value sets VLAN ID value for inner VLAN. */
22606 * This value sets the mask value for the ivlan id.
22607 * A value of 0 will mask the corresponding bit from
22610 uint16_t l2_ivlan_mask;
22611 uint8_t unused_1[2];
22613 * This value sets the match value for the tunnel
22615 * Destination MAC address for RX path.
22616 * Source MAC address for TX path.
22618 uint8_t t_l2_addr[6];
22619 uint8_t unused_2[2];
22621 * This value sets the mask value for the tunnel L2
22623 * A value of 0 will mask the corresponding bit from
22626 uint8_t t_l2_addr_mask[6];
22627 /* This value sets VLAN ID value for tunnel outer VLAN. */
22628 uint16_t t_l2_ovlan;
22630 * This value sets the mask value for the tunnel ovlan id.
22631 * A value of 0 will mask the corresponding bit from
22634 uint16_t t_l2_ovlan_mask;
22635 /* This value sets VLAN ID value for tunnel inner VLAN. */
22636 uint16_t t_l2_ivlan;
22638 * This value sets the mask value for the tunnel ivlan id.
22639 * A value of 0 will mask the corresponding bit from
22642 uint16_t t_l2_ivlan_mask;
22643 /* This value identifies the type of source of the packet. */
22646 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
22647 /* Physical function */
22648 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
22649 /* Virtual function */
22650 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
22651 /* Virtual NIC of a function */
22652 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
22653 /* Embedded processor for CFA management */
22654 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
22655 /* Embedded processor for OOB management */
22656 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
22657 /* Embedded processor for RoCE */
22658 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
22659 /* Embedded processor for network proxy functions */
22660 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
22661 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
22662 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
22665 * This value is the id of the source.
22666 * For a network port, it represents port_id.
22667 * For a physical function, it represents fid.
22668 * For a virtual function, it represents vf_id.
22669 * For a vnic, it represents vnic_id.
22670 * For embedded processors, this id is not valid.
22673 * 1. The function ID is implied if it src_id is
22674 * not provided for a src_type that is either
22678 uint8_t tunnel_type;
22680 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22682 /* Virtual eXtensible Local Area Network (VXLAN) */
22683 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22685 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22686 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22688 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22689 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22692 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22694 /* Generic Network Virtualization Encapsulation (Geneve) */
22695 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22697 /* Multi-Protocol Lable Switching (MPLS) */
22698 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22700 /* Stateless Transport Tunnel (STT) */
22701 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
22703 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22704 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22706 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22707 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22709 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22710 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22712 /* Use fixed layer 2 ether type of 0xFFFF */
22713 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
22715 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
22716 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
22718 /* Any tunneled traffic */
22719 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22721 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22722 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22725 * If set, this value shall represent the
22726 * Logical VNIC ID of the destination VNIC for the RX
22727 * path and network port id of the destination port for
22732 * Logical VNIC ID of the VNIC where traffic is
22735 uint16_t mirror_vnic_id;
22737 * This hint is provided to help in placing
22738 * the filter in the filter table.
22741 /* No preference */
22742 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
22744 /* Above the given filter */
22745 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
22747 /* Below the given filter */
22748 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
22750 /* As high as possible */
22751 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
22753 /* As low as possible */
22754 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
22756 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
22757 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
22761 * This is the ID of the filter that goes along with
22764 * This field is valid only for the following values.
22765 * 1 - Above the given filter
22766 * 2 - Below the given filter
22768 uint64_t l2_filter_id_hint;
22769 } __attribute__((packed));
22771 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
22772 struct hwrm_cfa_l2_filter_alloc_output {
22773 /* The specific error status for the command. */
22774 uint16_t error_code;
22775 /* The HWRM command request type. */
22777 /* The sequence ID from the original command. */
22779 /* The length of the response data in number of bytes. */
22782 * This value identifies a set of CFA data structures used for an L2
22785 uint64_t l2_filter_id;
22787 * This is the ID of the flow associated with this
22789 * This value shall be used to match and associate the
22790 * flow identifier returned in completion records.
22791 * A value of 0xFFFFFFFF shall indicate no flow id.
22794 uint8_t unused_0[3];
22796 * This field is used in Output records to indicate that the output
22797 * is completely written to RAM. This field should be read as '1'
22798 * to indicate that the output has been completely written.
22799 * When writing a command completion or response to an internal processor,
22800 * the order of writes has to be such that this field is written last.
22803 } __attribute__((packed));
22805 /***************************
22806 * hwrm_cfa_l2_filter_free *
22807 ***************************/
22810 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
22811 struct hwrm_cfa_l2_filter_free_input {
22812 /* The HWRM command request type. */
22815 * The completion ring to send the completion event on. This should
22816 * be the NQ ID returned from the `nq_alloc` HWRM command.
22818 uint16_t cmpl_ring;
22820 * The sequence ID is used by the driver for tracking multiple
22821 * commands. This ID is treated as opaque data by the firmware and
22822 * the value is returned in the `hwrm_resp_hdr` upon completion.
22826 * The target ID of the command:
22827 * * 0x0-0xFFF8 - The function ID
22828 * * 0xFFF8-0xFFFE - Reserved for internal processors
22831 uint16_t target_id;
22833 * A physical address pointer pointing to a host buffer that the
22834 * command's response data will be written. This can be either a host
22835 * physical address (HPA) or a guest physical address (GPA) and must
22836 * point to a physically contiguous block of memory.
22838 uint64_t resp_addr;
22840 * This value identifies a set of CFA data structures used for an L2
22843 uint64_t l2_filter_id;
22844 } __attribute__((packed));
22846 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
22847 struct hwrm_cfa_l2_filter_free_output {
22848 /* The specific error status for the command. */
22849 uint16_t error_code;
22850 /* The HWRM command request type. */
22852 /* The sequence ID from the original command. */
22854 /* The length of the response data in number of bytes. */
22856 uint8_t unused_0[7];
22858 * This field is used in Output records to indicate that the output
22859 * is completely written to RAM. This field should be read as '1'
22860 * to indicate that the output has been completely written.
22861 * When writing a command completion or response to an internal processor,
22862 * the order of writes has to be such that this field is written last.
22865 } __attribute__((packed));
22867 /**************************
22868 * hwrm_cfa_l2_filter_cfg *
22869 **************************/
22872 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
22873 struct hwrm_cfa_l2_filter_cfg_input {
22874 /* The HWRM command request type. */
22877 * The completion ring to send the completion event on. This should
22878 * be the NQ ID returned from the `nq_alloc` HWRM command.
22880 uint16_t cmpl_ring;
22882 * The sequence ID is used by the driver for tracking multiple
22883 * commands. This ID is treated as opaque data by the firmware and
22884 * the value is returned in the `hwrm_resp_hdr` upon completion.
22888 * The target ID of the command:
22889 * * 0x0-0xFFF8 - The function ID
22890 * * 0xFFF8-0xFFFE - Reserved for internal processors
22893 uint16_t target_id;
22895 * A physical address pointer pointing to a host buffer that the
22896 * command's response data will be written. This can be either a host
22897 * physical address (HPA) or a guest physical address (GPA) and must
22898 * point to a physically contiguous block of memory.
22900 uint64_t resp_addr;
22903 * Enumeration denoting the RX, TX type of the resource.
22904 * This enumeration is used for resources that are similar for both
22905 * TX and RX paths of the chip.
22907 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
22910 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
22913 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
22915 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
22916 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
22918 * Setting of this flag indicates drop action. If this flag is not set,
22919 * then it should be considered accept action.
22921 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
22924 * Enumeration denoting NO_ROCE_L2 to support old drivers.
22925 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
22927 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
22929 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
22930 /* To support old drivers */
22931 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
22932 (UINT32_C(0x0) << 2)
22933 /* Only L2 traffic */
22934 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
22935 (UINT32_C(0x1) << 2)
22936 /* Roce & L2 traffic */
22937 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
22938 (UINT32_C(0x2) << 2)
22939 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
22940 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
22943 * This bit must be '1' for the dst_id field to be
22946 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
22949 * This bit must be '1' for the new_mirror_vnic_id field to be
22952 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
22955 * This value identifies a set of CFA data structures used for an L2
22958 uint64_t l2_filter_id;
22960 * If set, this value shall represent the
22961 * Logical VNIC ID of the destination VNIC for the RX
22962 * path and network port id of the destination port for
22967 * New Logical VNIC ID of the VNIC where traffic is
22970 uint32_t new_mirror_vnic_id;
22971 } __attribute__((packed));
22973 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
22974 struct hwrm_cfa_l2_filter_cfg_output {
22975 /* The specific error status for the command. */
22976 uint16_t error_code;
22977 /* The HWRM command request type. */
22979 /* The sequence ID from the original command. */
22981 /* The length of the response data in number of bytes. */
22983 uint8_t unused_0[7];
22985 * This field is used in Output records to indicate that the output
22986 * is completely written to RAM. This field should be read as '1'
22987 * to indicate that the output has been completely written.
22988 * When writing a command completion or response to an internal processor,
22989 * the order of writes has to be such that this field is written last.
22992 } __attribute__((packed));
22994 /***************************
22995 * hwrm_cfa_l2_set_rx_mask *
22996 ***************************/
22999 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
23000 struct hwrm_cfa_l2_set_rx_mask_input {
23001 /* The HWRM command request type. */
23004 * The completion ring to send the completion event on. This should
23005 * be the NQ ID returned from the `nq_alloc` HWRM command.
23007 uint16_t cmpl_ring;
23009 * The sequence ID is used by the driver for tracking multiple
23010 * commands. This ID is treated as opaque data by the firmware and
23011 * the value is returned in the `hwrm_resp_hdr` upon completion.
23015 * The target ID of the command:
23016 * * 0x0-0xFFF8 - The function ID
23017 * * 0xFFF8-0xFFFE - Reserved for internal processors
23020 uint16_t target_id;
23022 * A physical address pointer pointing to a host buffer that the
23023 * command's response data will be written. This can be either a host
23024 * physical address (HPA) or a guest physical address (GPA) and must
23025 * point to a physically contiguous block of memory.
23027 uint64_t resp_addr;
23032 * When this bit is '1', the function is requested to accept
23033 * multi-cast packets specified by the multicast addr table.
23035 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
23038 * When this bit is '1', the function is requested to accept
23039 * all multi-cast packets.
23041 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
23044 * When this bit is '1', the function is requested to accept
23045 * broadcast packets.
23047 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
23050 * When this bit is '1', the function is requested to be
23051 * put in the promiscuous mode.
23053 * The HWRM should accept any function to set up
23054 * promiscuous mode.
23056 * The HWRM shall follow the semantics below for the
23057 * promiscuous mode support.
23058 * # When partitioning is not enabled on a port
23059 * (i.e. single PF on the port), then the PF shall
23060 * be allowed to be in the promiscuous mode. When the
23061 * PF is in the promiscuous mode, then it shall
23062 * receive all host bound traffic on that port.
23063 * # When partitioning is enabled on a port
23064 * (i.e. multiple PFs per port) and a PF on that
23065 * port is in the promiscuous mode, then the PF
23066 * receives all traffic within that partition as
23067 * identified by a unique identifier for the
23068 * PF (e.g. S-Tag). If a unique outer VLAN
23069 * for the PF is specified, then the setting of
23070 * promiscuous mode on that PF shall result in the
23071 * PF receiving all host bound traffic with matching
23073 * # A VF shall can be set in the promiscuous mode.
23074 * In the promiscuous mode, the VF does not receive any
23075 * traffic unless a unique outer VLAN for the
23076 * VF is specified. If a unique outer VLAN
23077 * for the VF is specified, then the setting of
23078 * promiscuous mode on that VF shall result in the
23079 * VF receiving all host bound traffic with the
23080 * matching outer VLAN.
23081 * # The HWRM shall allow the setting of promiscuous
23082 * mode on a function independently from the
23083 * promiscuous mode settings on other functions.
23085 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
23088 * If this flag is set, the corresponding RX
23089 * filters shall be set up to cover multicast/broadcast
23090 * filters for the outermost Layer 2 destination MAC
23093 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
23096 * If this flag is set, the corresponding RX
23097 * filters shall be set up to cover multicast/broadcast
23098 * filters for the VLAN-tagged packets that match the
23099 * TPID and VID fields of VLAN tags in the VLAN tag
23100 * table specified in this command.
23102 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
23105 * If this flag is set, the corresponding RX
23106 * filters shall be set up to cover multicast/broadcast
23107 * filters for non-VLAN tagged packets and VLAN-tagged
23108 * packets that match the TPID and VID fields of VLAN
23109 * tags in the VLAN tag table specified in this command.
23111 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
23114 * If this flag is set, the corresponding RX
23115 * filters shall be set up to cover multicast/broadcast
23116 * filters for non-VLAN tagged packets and VLAN-tagged
23117 * packets matching any VLAN tag.
23119 * If this flag is set, then the HWRM shall ignore
23120 * VLAN tags specified in vlan_tag_tbl.
23122 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
23123 * flags is set, then the HWRM shall ignore
23124 * VLAN tags specified in vlan_tag_tbl.
23126 * The HWRM client shall set at most one flag out of
23127 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
23129 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
23131 /* This is the address for mcast address tbl. */
23132 uint64_t mc_tbl_addr;
23134 * This value indicates how many entries in mc_tbl are valid.
23135 * Each entry is 6 bytes.
23137 uint32_t num_mc_entries;
23138 uint8_t unused_0[4];
23140 * This is the address for VLAN tag table.
23141 * Each VLAN entry in the table is 4 bytes of a VLAN tag
23142 * including TPID, PCP, DEI, and VID fields in network byte
23145 uint64_t vlan_tag_tbl_addr;
23147 * This value indicates how many entries in vlan_tag_tbl are
23148 * valid. Each entry is 4 bytes.
23150 uint32_t num_vlan_tags;
23151 uint8_t unused_1[4];
23152 } __attribute__((packed));
23154 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
23155 struct hwrm_cfa_l2_set_rx_mask_output {
23156 /* The specific error status for the command. */
23157 uint16_t error_code;
23158 /* The HWRM command request type. */
23160 /* The sequence ID from the original command. */
23162 /* The length of the response data in number of bytes. */
23164 uint8_t unused_0[7];
23166 * This field is used in Output records to indicate that the output
23167 * is completely written to RAM. This field should be read as '1'
23168 * to indicate that the output has been completely written.
23169 * When writing a command completion or response to an internal processor,
23170 * the order of writes has to be such that this field is written last.
23173 } __attribute__((packed));
23175 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
23176 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
23178 * command specific error codes that goes to
23179 * the cmd_err field in Common HWRM Error Response.
23182 /* Unknown error */
23183 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
23185 /* Unable to complete operation due to conflict with Ntuple Filter */
23186 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
23188 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
23189 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
23190 uint8_t unused_0[7];
23191 } __attribute__((packed));
23193 /*******************************
23194 * hwrm_cfa_vlan_antispoof_cfg *
23195 *******************************/
23198 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
23199 struct hwrm_cfa_vlan_antispoof_cfg_input {
23200 /* The HWRM command request type. */
23203 * The completion ring to send the completion event on. This should
23204 * be the NQ ID returned from the `nq_alloc` HWRM command.
23206 uint16_t cmpl_ring;
23208 * The sequence ID is used by the driver for tracking multiple
23209 * commands. This ID is treated as opaque data by the firmware and
23210 * the value is returned in the `hwrm_resp_hdr` upon completion.
23214 * The target ID of the command:
23215 * * 0x0-0xFFF8 - The function ID
23216 * * 0xFFF8-0xFFFE - Reserved for internal processors
23219 uint16_t target_id;
23221 * A physical address pointer pointing to a host buffer that the
23222 * command's response data will be written. This can be either a host
23223 * physical address (HPA) or a guest physical address (GPA) and must
23224 * point to a physically contiguous block of memory.
23226 uint64_t resp_addr;
23228 * Function ID of the function that is being configured.
23229 * Only valid for a VF FID configured by the PF.
23232 uint8_t unused_0[2];
23233 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
23234 uint32_t num_vlan_entries;
23236 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
23237 * antispoof table. Each table entry contains the 16-bit TPID
23238 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
23239 * all in network order to match hwrm_cfa_l2_set_rx_mask.
23240 * For an individual VLAN entry, the mask value should be 0xfff
23241 * for the 12-bit VLAN ID.
23243 uint64_t vlan_tag_mask_tbl_addr;
23244 } __attribute__((packed));
23246 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
23247 struct hwrm_cfa_vlan_antispoof_cfg_output {
23248 /* The specific error status for the command. */
23249 uint16_t error_code;
23250 /* The HWRM command request type. */
23252 /* The sequence ID from the original command. */
23254 /* The length of the response data in number of bytes. */
23256 uint8_t unused_0[7];
23258 * This field is used in Output records to indicate that the output
23259 * is completely written to RAM. This field should be read as '1'
23260 * to indicate that the output has been completely written.
23261 * When writing a command completion or response to an internal processor,
23262 * the order of writes has to be such that this field is written last.
23265 } __attribute__((packed));
23267 /********************************
23268 * hwrm_cfa_vlan_antispoof_qcfg *
23269 ********************************/
23272 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
23273 struct hwrm_cfa_vlan_antispoof_qcfg_input {
23274 /* The HWRM command request type. */
23277 * The completion ring to send the completion event on. This should
23278 * be the NQ ID returned from the `nq_alloc` HWRM command.
23280 uint16_t cmpl_ring;
23282 * The sequence ID is used by the driver for tracking multiple
23283 * commands. This ID is treated as opaque data by the firmware and
23284 * the value is returned in the `hwrm_resp_hdr` upon completion.
23288 * The target ID of the command:
23289 * * 0x0-0xFFF8 - The function ID
23290 * * 0xFFF8-0xFFFE - Reserved for internal processors
23293 uint16_t target_id;
23295 * A physical address pointer pointing to a host buffer that the
23296 * command's response data will be written. This can be either a host
23297 * physical address (HPA) or a guest physical address (GPA) and must
23298 * point to a physically contiguous block of memory.
23300 uint64_t resp_addr;
23302 * Function ID of the function that is being queried.
23303 * Only valid for a VF FID queried by the PF.
23306 uint8_t unused_0[2];
23308 * Maximum number of VLAN entries the firmware is allowed to DMA
23309 * to vlan_tag_mask_tbl.
23311 uint32_t max_vlan_entries;
23313 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
23314 * antispoof table to which firmware will DMA to. Each table
23315 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
23316 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
23317 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
23318 * the mask value should be 0xfff for the 12-bit VLAN ID.
23320 uint64_t vlan_tag_mask_tbl_addr;
23321 } __attribute__((packed));
23323 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
23324 struct hwrm_cfa_vlan_antispoof_qcfg_output {
23325 /* The specific error status for the command. */
23326 uint16_t error_code;
23327 /* The HWRM command request type. */
23329 /* The sequence ID from the original command. */
23331 /* The length of the response data in number of bytes. */
23333 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
23334 uint32_t num_vlan_entries;
23335 uint8_t unused_0[3];
23337 * This field is used in Output records to indicate that the output
23338 * is completely written to RAM. This field should be read as '1'
23339 * to indicate that the output has been completely written.
23340 * When writing a command completion or response to an internal processor,
23341 * the order of writes has to be such that this field is written last.
23344 } __attribute__((packed));
23346 /********************************
23347 * hwrm_cfa_tunnel_filter_alloc *
23348 ********************************/
23351 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
23352 struct hwrm_cfa_tunnel_filter_alloc_input {
23353 /* The HWRM command request type. */
23356 * The completion ring to send the completion event on. This should
23357 * be the NQ ID returned from the `nq_alloc` HWRM command.
23359 uint16_t cmpl_ring;
23361 * The sequence ID is used by the driver for tracking multiple
23362 * commands. This ID is treated as opaque data by the firmware and
23363 * the value is returned in the `hwrm_resp_hdr` upon completion.
23367 * The target ID of the command:
23368 * * 0x0-0xFFF8 - The function ID
23369 * * 0xFFF8-0xFFFE - Reserved for internal processors
23372 uint16_t target_id;
23374 * A physical address pointer pointing to a host buffer that the
23375 * command's response data will be written. This can be either a host
23376 * physical address (HPA) or a guest physical address (GPA) and must
23377 * point to a physically contiguous block of memory.
23379 uint64_t resp_addr;
23381 /* Setting of this flag indicates the applicability to the loopback path. */
23382 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
23386 * This bit must be '1' for the l2_filter_id field to be
23389 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
23392 * This bit must be '1' for the l2_addr field to be
23395 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
23398 * This bit must be '1' for the l2_ivlan field to be
23401 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
23404 * This bit must be '1' for the l3_addr field to be
23407 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
23410 * This bit must be '1' for the l3_addr_type field to be
23413 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
23416 * This bit must be '1' for the t_l3_addr_type field to be
23419 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
23422 * This bit must be '1' for the t_l3_addr field to be
23425 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
23428 * This bit must be '1' for the tunnel_type field to be
23431 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23434 * This bit must be '1' for the vni field to be
23437 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
23440 * This bit must be '1' for the dst_vnic_id field to be
23443 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
23446 * This bit must be '1' for the mirror_vnic_id field to be
23449 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23452 * This value identifies a set of CFA data structures used for an L2
23455 uint64_t l2_filter_id;
23457 * This value sets the match value for the inner L2
23459 * Destination MAC address for RX path.
23460 * Source MAC address for TX path.
23462 uint8_t l2_addr[6];
23464 * This value sets VLAN ID value for inner VLAN.
23465 * Only 12-bits of VLAN ID are used in setting the filter.
23469 * The value of inner destination IP address to be used in filtering.
23470 * For IPv4, first four bytes represent the IP address.
23472 uint32_t l3_addr[4];
23474 * The value of tunnel destination IP address to be used in filtering.
23475 * For IPv4, first four bytes represent the IP address.
23477 uint32_t t_l3_addr[4];
23479 * This value indicates the type of inner IP address.
23482 * All others are invalid.
23484 uint8_t l3_addr_type;
23486 * This value indicates the type of tunnel IP address.
23489 * All others are invalid.
23491 uint8_t t_l3_addr_type;
23493 uint8_t tunnel_type;
23495 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23497 /* Virtual eXtensible Local Area Network (VXLAN) */
23498 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23500 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23501 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23503 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23504 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23507 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23509 /* Generic Network Virtualization Encapsulation (Geneve) */
23510 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23512 /* Multi-Protocol Lable Switching (MPLS) */
23513 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23515 /* Stateless Transport Tunnel (STT) */
23516 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23518 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23519 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23521 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23522 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23524 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23525 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23527 /* Use fixed layer 2 ether type of 0xFFFF */
23528 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23530 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23531 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23533 /* Any tunneled traffic */
23534 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23536 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23537 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23539 * tunnel_flags allows the user to indicate the tunnel tag detection
23540 * for the tunnel type specified in tunnel_type.
23542 uint8_t tunnel_flags;
23544 * If the tunnel_type is geneve, then this bit indicates if we
23545 * need to match the geneve OAM packet.
23546 * If the tunnel_type is nvgre or gre, then this bit indicates if
23547 * we need to detect checksum present bit in geneve header.
23548 * If the tunnel_type is mpls, then this bit indicates if we need
23549 * to match mpls packet with explicit IPV4/IPV6 null header.
23551 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
23554 * If the tunnel_type is geneve, then this bit indicates if we
23555 * need to detect the critical option bit set in the oam packet.
23556 * If the tunnel_type is nvgre or gre, then this bit indicates
23557 * if we need to match nvgre packets with key present bit set in
23559 * If the tunnel_type is mpls, then this bit indicates if we
23560 * need to match mpls packet with S bit from inner/second label.
23562 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
23565 * If the tunnel_type is geneve, then this bit indicates if we
23566 * need to match geneve packet with extended header bit set in
23568 * If the tunnel_type is nvgre or gre, then this bit indicates
23569 * if we need to match nvgre packets with sequence number
23570 * present bit set in gre header.
23571 * If the tunnel_type is mpls, then this bit indicates if we
23572 * need to match mpls packet with S bit from out/first label.
23574 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
23577 * Virtual Network Identifier (VNI). Only valid with
23578 * tunnel_types VXLAN, NVGRE, and Geneve.
23579 * Only lower 24-bits of VNI field are used
23580 * in setting up the filter.
23583 /* Logical VNIC ID of the destination VNIC. */
23584 uint32_t dst_vnic_id;
23586 * Logical VNIC ID of the VNIC where traffic is
23589 uint32_t mirror_vnic_id;
23590 } __attribute__((packed));
23592 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
23593 struct hwrm_cfa_tunnel_filter_alloc_output {
23594 /* The specific error status for the command. */
23595 uint16_t error_code;
23596 /* The HWRM command request type. */
23598 /* The sequence ID from the original command. */
23600 /* The length of the response data in number of bytes. */
23602 /* This value is an opaque id into CFA data structures. */
23603 uint64_t tunnel_filter_id;
23605 * This is the ID of the flow associated with this
23607 * This value shall be used to match and associate the
23608 * flow identifier returned in completion records.
23609 * A value of 0xFFFFFFFF shall indicate no flow id.
23612 uint8_t unused_0[3];
23614 * This field is used in Output records to indicate that the output
23615 * is completely written to RAM. This field should be read as '1'
23616 * to indicate that the output has been completely written.
23617 * When writing a command completion or response to an internal processor,
23618 * the order of writes has to be such that this field is written last.
23621 } __attribute__((packed));
23623 /*******************************
23624 * hwrm_cfa_tunnel_filter_free *
23625 *******************************/
23628 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
23629 struct hwrm_cfa_tunnel_filter_free_input {
23630 /* The HWRM command request type. */
23633 * The completion ring to send the completion event on. This should
23634 * be the NQ ID returned from the `nq_alloc` HWRM command.
23636 uint16_t cmpl_ring;
23638 * The sequence ID is used by the driver for tracking multiple
23639 * commands. This ID is treated as opaque data by the firmware and
23640 * the value is returned in the `hwrm_resp_hdr` upon completion.
23644 * The target ID of the command:
23645 * * 0x0-0xFFF8 - The function ID
23646 * * 0xFFF8-0xFFFE - Reserved for internal processors
23649 uint16_t target_id;
23651 * A physical address pointer pointing to a host buffer that the
23652 * command's response data will be written. This can be either a host
23653 * physical address (HPA) or a guest physical address (GPA) and must
23654 * point to a physically contiguous block of memory.
23656 uint64_t resp_addr;
23657 /* This value is an opaque id into CFA data structures. */
23658 uint64_t tunnel_filter_id;
23659 } __attribute__((packed));
23661 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
23662 struct hwrm_cfa_tunnel_filter_free_output {
23663 /* The specific error status for the command. */
23664 uint16_t error_code;
23665 /* The HWRM command request type. */
23667 /* The sequence ID from the original command. */
23669 /* The length of the response data in number of bytes. */
23671 uint8_t unused_0[7];
23673 * This field is used in Output records to indicate that the output
23674 * is completely written to RAM. This field should be read as '1'
23675 * to indicate that the output has been completely written.
23676 * When writing a command completion or response to an internal processor,
23677 * the order of writes has to be such that this field is written last.
23680 } __attribute__((packed));
23682 /***************************************
23683 * hwrm_cfa_redirect_tunnel_type_alloc *
23684 ***************************************/
23687 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
23688 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
23689 /* The HWRM command request type. */
23692 * The completion ring to send the completion event on. This should
23693 * be the NQ ID returned from the `nq_alloc` HWRM command.
23695 uint16_t cmpl_ring;
23697 * The sequence ID is used by the driver for tracking multiple
23698 * commands. This ID is treated as opaque data by the firmware and
23699 * the value is returned in the `hwrm_resp_hdr` upon completion.
23703 * The target ID of the command:
23704 * * 0x0-0xFFF8 - The function ID
23705 * * 0xFFF8-0xFFFE - Reserved for internal processors
23708 uint16_t target_id;
23710 * A physical address pointer pointing to a host buffer that the
23711 * command's response data will be written. This can be either a host
23712 * physical address (HPA) or a guest physical address (GPA) and must
23713 * point to a physically contiguous block of memory.
23715 uint64_t resp_addr;
23716 /* The destination function id, to whom the traffic is redirected. */
23719 uint8_t tunnel_type;
23721 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23723 /* Virtual eXtensible Local Area Network (VXLAN) */
23724 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23726 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23727 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23729 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23730 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23733 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23735 /* Generic Network Virtualization Encapsulation (Geneve) */
23736 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23738 /* Multi-Protocol Lable Switching (MPLS) */
23739 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23741 /* Stateless Transport Tunnel (STT) */
23742 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
23744 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23745 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23747 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23748 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23750 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23751 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23753 /* Use fixed layer 2 ether type of 0xFFFF */
23754 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
23756 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23757 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23759 /* Any tunneled traffic */
23760 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23762 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23763 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23764 /* Tunnel alloc flags. */
23766 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
23767 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
23769 uint8_t unused_0[4];
23770 } __attribute__((packed));
23772 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
23773 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
23774 /* The specific error status for the command. */
23775 uint16_t error_code;
23776 /* The HWRM command request type. */
23778 /* The sequence ID from the original command. */
23780 /* The length of the response data in number of bytes. */
23782 uint8_t unused_0[7];
23784 * This field is used in Output records to indicate that the output
23785 * is completely written to RAM. This field should be read as '1'
23786 * to indicate that the output has been completely written.
23787 * When writing a command completion or response to an internal processor,
23788 * the order of writes has to be such that this field is written last.
23791 } __attribute__((packed));
23793 /**************************************
23794 * hwrm_cfa_redirect_tunnel_type_free *
23795 **************************************/
23798 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
23799 struct hwrm_cfa_redirect_tunnel_type_free_input {
23800 /* The HWRM command request type. */
23803 * The completion ring to send the completion event on. This should
23804 * be the NQ ID returned from the `nq_alloc` HWRM command.
23806 uint16_t cmpl_ring;
23808 * The sequence ID is used by the driver for tracking multiple
23809 * commands. This ID is treated as opaque data by the firmware and
23810 * the value is returned in the `hwrm_resp_hdr` upon completion.
23814 * The target ID of the command:
23815 * * 0x0-0xFFF8 - The function ID
23816 * * 0xFFF8-0xFFFE - Reserved for internal processors
23819 uint16_t target_id;
23821 * A physical address pointer pointing to a host buffer that the
23822 * command's response data will be written. This can be either a host
23823 * physical address (HPA) or a guest physical address (GPA) and must
23824 * point to a physically contiguous block of memory.
23826 uint64_t resp_addr;
23827 /* The destination function id, to whom the traffic is redirected. */
23830 uint8_t tunnel_type;
23832 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
23834 /* Virtual eXtensible Local Area Network (VXLAN) */
23835 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
23837 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23838 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
23840 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23841 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
23844 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
23846 /* Generic Network Virtualization Encapsulation (Geneve) */
23847 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
23849 /* Multi-Protocol Lable Switching (MPLS) */
23850 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
23852 /* Stateless Transport Tunnel (STT) */
23853 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
23855 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23856 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
23858 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23859 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23861 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23862 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23864 /* Use fixed layer 2 ether type of 0xFFFF */
23865 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
23867 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23868 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23870 /* Any tunneled traffic */
23871 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23873 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
23874 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
23875 uint8_t unused_0[5];
23876 } __attribute__((packed));
23878 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
23879 struct hwrm_cfa_redirect_tunnel_type_free_output {
23880 /* The specific error status for the command. */
23881 uint16_t error_code;
23882 /* The HWRM command request type. */
23884 /* The sequence ID from the original command. */
23886 /* The length of the response data in number of bytes. */
23888 uint8_t unused_0[7];
23890 * This field is used in Output records to indicate that the output
23891 * is completely written to RAM. This field should be read as '1'
23892 * to indicate that the output has been completely written.
23893 * When writing a command completion or response to an internal processor,
23894 * the order of writes has to be such that this field is written last.
23897 } __attribute__((packed));
23899 /**************************************
23900 * hwrm_cfa_redirect_tunnel_type_info *
23901 **************************************/
23904 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
23905 struct hwrm_cfa_redirect_tunnel_type_info_input {
23906 /* The HWRM command request type. */
23909 * The completion ring to send the completion event on. This should
23910 * be the NQ ID returned from the `nq_alloc` HWRM command.
23912 uint16_t cmpl_ring;
23914 * The sequence ID is used by the driver for tracking multiple
23915 * commands. This ID is treated as opaque data by the firmware and
23916 * the value is returned in the `hwrm_resp_hdr` upon completion.
23920 * The target ID of the command:
23921 * * 0x0-0xFFF8 - The function ID
23922 * * 0xFFF8-0xFFFE - Reserved for internal processors
23925 uint16_t target_id;
23927 * A physical address pointer pointing to a host buffer that the
23928 * command's response data will be written. This can be either a host
23929 * physical address (HPA) or a guest physical address (GPA) and must
23930 * point to a physically contiguous block of memory.
23932 uint64_t resp_addr;
23933 /* The source function id. */
23936 uint8_t tunnel_type;
23938 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
23940 /* Virtual eXtensible Local Area Network (VXLAN) */
23941 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
23943 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23944 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
23946 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23947 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
23950 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
23952 /* Generic Network Virtualization Encapsulation (Geneve) */
23953 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
23955 /* Multi-Protocol Lable Switching (MPLS) */
23956 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
23958 /* Stateless Transport Tunnel (STT) */
23959 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
23961 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23962 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
23964 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23965 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23967 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
23968 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
23970 /* Use fixed layer 2 ether type of 0xFFFF */
23971 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
23973 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
23974 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
23976 /* Any tunneled traffic */
23977 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23979 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
23980 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
23981 uint8_t unused_0[5];
23982 } __attribute__((packed));
23984 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
23985 struct hwrm_cfa_redirect_tunnel_type_info_output {
23986 /* The specific error status for the command. */
23987 uint16_t error_code;
23988 /* The HWRM command request type. */
23990 /* The sequence ID from the original command. */
23992 /* The length of the response data in number of bytes. */
23994 /* The destination function id, to whom the traffic is redirected. */
23996 uint8_t unused_0[5];
23998 * This field is used in Output records to indicate that the output
23999 * is completely written to RAM. This field should be read as '1'
24000 * to indicate that the output has been completely written.
24001 * When writing a command completion or response to an internal processor,
24002 * the order of writes has to be such that this field is written last.
24005 } __attribute__((packed));
24007 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
24008 struct hwrm_vxlan_ipv4_hdr {
24009 /* IPv4 version and header length. */
24011 /* IPv4 header length */
24012 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
24013 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
24015 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
24016 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
24017 /* IPv4 type of service. */
24019 /* IPv4 identification. */
24021 /* IPv4 flags and offset. */
24022 uint16_t flags_frag_offset;
24025 /* IPv4 protocol. */
24027 /* IPv4 source address. */
24028 uint32_t src_ip_addr;
24029 /* IPv4 destination address. */
24030 uint32_t dest_ip_addr;
24031 } __attribute__((packed));
24033 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
24034 struct hwrm_vxlan_ipv6_hdr {
24035 /* IPv6 version, traffic class and flow label. */
24036 uint32_t ver_tc_flow_label;
24037 /* IPv6 version shift */
24038 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
24040 /* IPv6 version mask */
24041 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
24042 UINT32_C(0xf0000000)
24043 /* IPv6 TC shift */
24044 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
24047 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
24048 UINT32_C(0xff00000)
24049 /* IPv6 flow label shift */
24050 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
24052 /* IPv6 flow label mask */
24053 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
24055 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
24056 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
24057 /* IPv6 payload length. */
24058 uint16_t payload_len;
24059 /* IPv6 next header. */
24063 /* IPv6 source address. */
24064 uint32_t src_ip_addr[4];
24065 /* IPv6 destination address. */
24066 uint32_t dest_ip_addr[4];
24067 } __attribute__((packed));
24069 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
24070 struct hwrm_cfa_encap_data_vxlan {
24071 /* Source MAC address. */
24072 uint8_t src_mac_addr[6];
24075 /* Destination MAC address. */
24076 uint8_t dst_mac_addr[6];
24077 /* Number of VLAN tags. */
24078 uint8_t num_vlan_tags;
24081 /* Outer VLAN TPID. */
24082 uint16_t ovlan_tpid;
24083 /* Outer VLAN TCI. */
24084 uint16_t ovlan_tci;
24085 /* Inner VLAN TPID. */
24086 uint16_t ivlan_tpid;
24087 /* Inner VLAN TCI. */
24088 uint16_t ivlan_tci;
24089 /* L3 header fields. */
24091 /* IP version mask. */
24092 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
24093 /* IP version 4. */
24094 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
24095 /* IP version 6. */
24096 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
24097 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
24098 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
24099 /* UDP source port. */
24101 /* UDP destination port. */
24103 /* VXLAN Network Identifier. */
24105 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
24106 uint8_t hdr_rsvd0[3];
24107 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
24109 /* VXLAN header flags field. */
24112 } __attribute__((packed));
24114 /*******************************
24115 * hwrm_cfa_encap_record_alloc *
24116 *******************************/
24119 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
24120 struct hwrm_cfa_encap_record_alloc_input {
24121 /* The HWRM command request type. */
24124 * The completion ring to send the completion event on. This should
24125 * be the NQ ID returned from the `nq_alloc` HWRM command.
24127 uint16_t cmpl_ring;
24129 * The sequence ID is used by the driver for tracking multiple
24130 * commands. This ID is treated as opaque data by the firmware and
24131 * the value is returned in the `hwrm_resp_hdr` upon completion.
24135 * The target ID of the command:
24136 * * 0x0-0xFFF8 - The function ID
24137 * * 0xFFF8-0xFFFE - Reserved for internal processors
24140 uint16_t target_id;
24142 * A physical address pointer pointing to a host buffer that the
24143 * command's response data will be written. This can be either a host
24144 * physical address (HPA) or a guest physical address (GPA) and must
24145 * point to a physically contiguous block of memory.
24147 uint64_t resp_addr;
24149 /* Setting of this flag indicates the applicability to the loopback path. */
24150 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
24153 * Setting of this flag indicates this encap record is external encap record.
24154 * Resetting of this flag indicates this flag is internal encap record and
24155 * this is the default setting.
24157 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
24159 /* Encapsulation Type. */
24160 uint8_t encap_type;
24161 /* Virtual eXtensible Local Area Network (VXLAN) */
24162 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
24164 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24165 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
24167 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
24168 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
24171 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
24173 /* Generic Network Virtualization Encapsulation (Geneve) */
24174 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
24176 /* Multi-Protocol Lable Switching (MPLS) */
24177 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
24180 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
24182 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24183 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
24185 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24186 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
24188 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24189 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
24191 /* Use fixed layer 2 ether type of 0xFFFF */
24192 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
24194 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24195 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
24197 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
24198 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
24199 uint8_t unused_0[3];
24200 /* This value is encap data used for the given encap type. */
24201 uint32_t encap_data[20];
24202 } __attribute__((packed));
24204 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
24205 struct hwrm_cfa_encap_record_alloc_output {
24206 /* The specific error status for the command. */
24207 uint16_t error_code;
24208 /* The HWRM command request type. */
24210 /* The sequence ID from the original command. */
24212 /* The length of the response data in number of bytes. */
24214 /* This value is an opaque id into CFA data structures. */
24215 uint32_t encap_record_id;
24216 uint8_t unused_0[3];
24218 * This field is used in Output records to indicate that the output
24219 * is completely written to RAM. This field should be read as '1'
24220 * to indicate that the output has been completely written.
24221 * When writing a command completion or response to an internal processor,
24222 * the order of writes has to be such that this field is written last.
24225 } __attribute__((packed));
24227 /******************************
24228 * hwrm_cfa_encap_record_free *
24229 ******************************/
24232 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
24233 struct hwrm_cfa_encap_record_free_input {
24234 /* The HWRM command request type. */
24237 * The completion ring to send the completion event on. This should
24238 * be the NQ ID returned from the `nq_alloc` HWRM command.
24240 uint16_t cmpl_ring;
24242 * The sequence ID is used by the driver for tracking multiple
24243 * commands. This ID is treated as opaque data by the firmware and
24244 * the value is returned in the `hwrm_resp_hdr` upon completion.
24248 * The target ID of the command:
24249 * * 0x0-0xFFF8 - The function ID
24250 * * 0xFFF8-0xFFFE - Reserved for internal processors
24253 uint16_t target_id;
24255 * A physical address pointer pointing to a host buffer that the
24256 * command's response data will be written. This can be either a host
24257 * physical address (HPA) or a guest physical address (GPA) and must
24258 * point to a physically contiguous block of memory.
24260 uint64_t resp_addr;
24261 /* This value is an opaque id into CFA data structures. */
24262 uint32_t encap_record_id;
24263 uint8_t unused_0[4];
24264 } __attribute__((packed));
24266 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
24267 struct hwrm_cfa_encap_record_free_output {
24268 /* The specific error status for the command. */
24269 uint16_t error_code;
24270 /* The HWRM command request type. */
24272 /* The sequence ID from the original command. */
24274 /* The length of the response data in number of bytes. */
24276 uint8_t unused_0[7];
24278 * This field is used in Output records to indicate that the output
24279 * is completely written to RAM. This field should be read as '1'
24280 * to indicate that the output has been completely written.
24281 * When writing a command completion or response to an internal processor,
24282 * the order of writes has to be such that this field is written last.
24285 } __attribute__((packed));
24287 /********************************
24288 * hwrm_cfa_ntuple_filter_alloc *
24289 ********************************/
24292 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
24293 struct hwrm_cfa_ntuple_filter_alloc_input {
24294 /* The HWRM command request type. */
24297 * The completion ring to send the completion event on. This should
24298 * be the NQ ID returned from the `nq_alloc` HWRM command.
24300 uint16_t cmpl_ring;
24302 * The sequence ID is used by the driver for tracking multiple
24303 * commands. This ID is treated as opaque data by the firmware and
24304 * the value is returned in the `hwrm_resp_hdr` upon completion.
24308 * The target ID of the command:
24309 * * 0x0-0xFFF8 - The function ID
24310 * * 0xFFF8-0xFFFE - Reserved for internal processors
24313 uint16_t target_id;
24315 * A physical address pointer pointing to a host buffer that the
24316 * command's response data will be written. This can be either a host
24317 * physical address (HPA) or a guest physical address (GPA) and must
24318 * point to a physically contiguous block of memory.
24320 uint64_t resp_addr;
24322 /* Setting of this flag indicates the applicability to the loopback path. */
24323 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
24326 * Setting of this flag indicates drop action. If this flag is not set,
24327 * then it should be considered accept action.
24329 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
24332 * Setting of this flag indicates that a meter is expected to be attached
24333 * to this flow. This hint can be used when choosing the action record
24334 * format required for the flow.
24336 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
24339 * Setting of this flag indicates that the dest_id field contains function ID.
24340 * If this is not set it indicates dest_id is VNIC or VPORT.
24342 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
24346 * This bit must be '1' for the l2_filter_id field to be
24349 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24352 * This bit must be '1' for the ethertype field to be
24355 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
24358 * This bit must be '1' for the tunnel_type field to be
24361 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24364 * This bit must be '1' for the src_macaddr field to be
24367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
24370 * This bit must be '1' for the ipaddr_type field to be
24373 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
24376 * This bit must be '1' for the src_ipaddr field to be
24379 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
24382 * This bit must be '1' for the src_ipaddr_mask field to be
24385 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
24388 * This bit must be '1' for the dst_ipaddr field to be
24391 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
24394 * This bit must be '1' for the dst_ipaddr_mask field to be
24397 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
24400 * This bit must be '1' for the ip_protocol field to be
24403 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
24406 * This bit must be '1' for the src_port field to be
24409 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
24412 * This bit must be '1' for the src_port_mask field to be
24415 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
24418 * This bit must be '1' for the dst_port field to be
24421 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
24424 * This bit must be '1' for the dst_port_mask field to be
24427 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
24430 * This bit must be '1' for the pri_hint field to be
24433 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
24436 * This bit must be '1' for the ntuple_filter_id field to be
24439 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
24442 * This bit must be '1' for the dst_id field to be
24445 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
24448 * This bit must be '1' for the mirror_vnic_id field to be
24451 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
24454 * This bit must be '1' for the dst_macaddr field to be
24457 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
24460 * This value identifies a set of CFA data structures used for an L2
24463 uint64_t l2_filter_id;
24465 * This value indicates the source MAC address in
24466 * the Ethernet header.
24468 uint8_t src_macaddr[6];
24469 /* This value indicates the ethertype in the Ethernet header. */
24470 uint16_t ethertype;
24472 * This value indicates the type of IP address.
24475 * All others are invalid.
24477 uint8_t ip_addr_type;
24479 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
24482 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
24485 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
24487 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
24488 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
24490 * The value of protocol filed in IP header.
24491 * Applies to UDP and TCP traffic.
24495 uint8_t ip_protocol;
24497 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
24500 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
24503 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
24505 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
24506 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
24508 * If set, this value shall represent the
24509 * Logical VNIC ID of the destination VNIC for the RX
24510 * path and network port id of the destination port for
24515 * Logical VNIC ID of the VNIC where traffic is
24518 uint16_t mirror_vnic_id;
24520 * This value indicates the tunnel type for this filter.
24521 * If this field is not specified, then the filter shall
24522 * apply to both non-tunneled and tunneled packets.
24523 * If this field conflicts with the tunnel_type specified
24524 * in the l2_filter_id, then the HWRM shall return an
24525 * error for this command.
24527 uint8_t tunnel_type;
24529 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
24531 /* Virtual eXtensible Local Area Network (VXLAN) */
24532 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24534 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24535 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
24537 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24538 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
24541 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
24543 /* Generic Network Virtualization Encapsulation (Geneve) */
24544 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24546 /* Multi-Protocol Lable Switching (MPLS) */
24547 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
24549 /* Stateless Transport Tunnel (STT) */
24550 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
24552 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24553 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
24555 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24556 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24558 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24559 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24561 /* Use fixed layer 2 ether type of 0xFFFF */
24562 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
24564 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
24565 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
24567 /* Any tunneled traffic */
24568 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
24570 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24571 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24573 * This hint is provided to help in placing
24574 * the filter in the filter table.
24577 /* No preference */
24578 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
24580 /* Above the given filter */
24581 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
24583 /* Below the given filter */
24584 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
24586 /* As high as possible */
24587 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
24589 /* As low as possible */
24590 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
24592 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
24593 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
24595 * The value of source IP address to be used in filtering.
24596 * For IPv4, first four bytes represent the IP address.
24598 uint32_t src_ipaddr[4];
24600 * The value of source IP address mask to be used in
24602 * For IPv4, first four bytes represent the IP address mask.
24604 uint32_t src_ipaddr_mask[4];
24606 * The value of destination IP address to be used in filtering.
24607 * For IPv4, first four bytes represent the IP address.
24609 uint32_t dst_ipaddr[4];
24611 * The value of destination IP address mask to be used in
24613 * For IPv4, first four bytes represent the IP address mask.
24615 uint32_t dst_ipaddr_mask[4];
24617 * The value of source port to be used in filtering.
24618 * Applies to UDP and TCP traffic.
24622 * The value of source port mask to be used in filtering.
24623 * Applies to UDP and TCP traffic.
24625 uint16_t src_port_mask;
24627 * The value of destination port to be used in filtering.
24628 * Applies to UDP and TCP traffic.
24632 * The value of destination port mask to be used in
24634 * Applies to UDP and TCP traffic.
24636 uint16_t dst_port_mask;
24638 * This is the ID of the filter that goes along with
24641 uint64_t ntuple_filter_id_hint;
24642 } __attribute__((packed));
24644 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
24645 struct hwrm_cfa_ntuple_filter_alloc_output {
24646 /* The specific error status for the command. */
24647 uint16_t error_code;
24648 /* The HWRM command request type. */
24650 /* The sequence ID from the original command. */
24652 /* The length of the response data in number of bytes. */
24654 /* This value is an opaque id into CFA data structures. */
24655 uint64_t ntuple_filter_id;
24657 * This is the ID of the flow associated with this
24659 * This value shall be used to match and associate the
24660 * flow identifier returned in completion records.
24661 * A value of 0xFFFFFFFF shall indicate no flow id.
24664 uint8_t unused_0[3];
24666 * This field is used in Output records to indicate that the output
24667 * is completely written to RAM. This field should be read as '1'
24668 * to indicate that the output has been completely written.
24669 * When writing a command completion or response to an internal processor,
24670 * the order of writes has to be such that this field is written last.
24673 } __attribute__((packed));
24675 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
24676 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
24678 * command specific error codes that goes to
24679 * the cmd_err field in Common HWRM Error Response.
24682 /* Unknown error */
24683 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
24685 /* Unable to complete operation due to conflict with Rx Mask VLAN */
24686 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
24688 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
24689 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
24690 uint8_t unused_0[7];
24691 } __attribute__((packed));
24693 /*******************************
24694 * hwrm_cfa_ntuple_filter_free *
24695 *******************************/
24698 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
24699 struct hwrm_cfa_ntuple_filter_free_input {
24700 /* The HWRM command request type. */
24703 * The completion ring to send the completion event on. This should
24704 * be the NQ ID returned from the `nq_alloc` HWRM command.
24706 uint16_t cmpl_ring;
24708 * The sequence ID is used by the driver for tracking multiple
24709 * commands. This ID is treated as opaque data by the firmware and
24710 * the value is returned in the `hwrm_resp_hdr` upon completion.
24714 * The target ID of the command:
24715 * * 0x0-0xFFF8 - The function ID
24716 * * 0xFFF8-0xFFFE - Reserved for internal processors
24719 uint16_t target_id;
24721 * A physical address pointer pointing to a host buffer that the
24722 * command's response data will be written. This can be either a host
24723 * physical address (HPA) or a guest physical address (GPA) and must
24724 * point to a physically contiguous block of memory.
24726 uint64_t resp_addr;
24727 /* This value is an opaque id into CFA data structures. */
24728 uint64_t ntuple_filter_id;
24729 } __attribute__((packed));
24731 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
24732 struct hwrm_cfa_ntuple_filter_free_output {
24733 /* The specific error status for the command. */
24734 uint16_t error_code;
24735 /* The HWRM command request type. */
24737 /* The sequence ID from the original command. */
24739 /* The length of the response data in number of bytes. */
24741 uint8_t unused_0[7];
24743 * This field is used in Output records to indicate that the output
24744 * is completely written to RAM. This field should be read as '1'
24745 * to indicate that the output has been completely written.
24746 * When writing a command completion or response to an internal processor,
24747 * the order of writes has to be such that this field is written last.
24750 } __attribute__((packed));
24752 /******************************
24753 * hwrm_cfa_ntuple_filter_cfg *
24754 ******************************/
24757 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
24758 struct hwrm_cfa_ntuple_filter_cfg_input {
24759 /* The HWRM command request type. */
24762 * The completion ring to send the completion event on. This should
24763 * be the NQ ID returned from the `nq_alloc` HWRM command.
24765 uint16_t cmpl_ring;
24767 * The sequence ID is used by the driver for tracking multiple
24768 * commands. This ID is treated as opaque data by the firmware and
24769 * the value is returned in the `hwrm_resp_hdr` upon completion.
24773 * The target ID of the command:
24774 * * 0x0-0xFFF8 - The function ID
24775 * * 0xFFF8-0xFFFE - Reserved for internal processors
24778 uint16_t target_id;
24780 * A physical address pointer pointing to a host buffer that the
24781 * command's response data will be written. This can be either a host
24782 * physical address (HPA) or a guest physical address (GPA) and must
24783 * point to a physically contiguous block of memory.
24785 uint64_t resp_addr;
24788 * This bit must be '1' for the new_dst_id field to be
24791 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
24794 * This bit must be '1' for the new_mirror_vnic_id field to be
24797 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
24800 * This bit must be '1' for the new_meter_instance_id field to be
24803 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
24807 * Setting this bit to 1 indicates that dest_id field contains FID.
24808 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
24810 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
24812 /* This value is an opaque id into CFA data structures. */
24813 uint64_t ntuple_filter_id;
24815 * If set, this value shall represent the new
24816 * Logical VNIC ID of the destination VNIC for the RX
24817 * path and new network port id of the destination port for
24820 uint32_t new_dst_id;
24822 * New Logical VNIC ID of the VNIC where traffic is
24825 uint32_t new_mirror_vnic_id;
24827 * New meter to attach to the flow. Specifying the
24828 * invalid instance ID is used to remove any existing
24829 * meter from the flow.
24831 uint16_t new_meter_instance_id;
24833 * A value of 0xfff is considered invalid and implies the
24834 * instance is not configured.
24836 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
24838 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
24839 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
24840 uint8_t unused_1[6];
24841 } __attribute__((packed));
24843 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
24844 struct hwrm_cfa_ntuple_filter_cfg_output {
24845 /* The specific error status for the command. */
24846 uint16_t error_code;
24847 /* The HWRM command request type. */
24849 /* The sequence ID from the original command. */
24851 /* The length of the response data in number of bytes. */
24853 uint8_t unused_0[7];
24855 * This field is used in Output records to indicate that the output
24856 * is completely written to RAM. This field should be read as '1'
24857 * to indicate that the output has been completely written.
24858 * When writing a command completion or response to an internal processor,
24859 * the order of writes has to be such that this field is written last.
24862 } __attribute__((packed));
24864 /**************************
24865 * hwrm_cfa_em_flow_alloc *
24866 **************************/
24869 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
24870 struct hwrm_cfa_em_flow_alloc_input {
24871 /* The HWRM command request type. */
24874 * The completion ring to send the completion event on. This should
24875 * be the NQ ID returned from the `nq_alloc` HWRM command.
24877 uint16_t cmpl_ring;
24879 * The sequence ID is used by the driver for tracking multiple
24880 * commands. This ID is treated as opaque data by the firmware and
24881 * the value is returned in the `hwrm_resp_hdr` upon completion.
24885 * The target ID of the command:
24886 * * 0x0-0xFFF8 - The function ID
24887 * * 0xFFF8-0xFFFE - Reserved for internal processors
24890 uint16_t target_id;
24892 * A physical address pointer pointing to a host buffer that the
24893 * command's response data will be written. This can be either a host
24894 * physical address (HPA) or a guest physical address (GPA) and must
24895 * point to a physically contiguous block of memory.
24897 uint64_t resp_addr;
24900 * Enumeration denoting the RX, TX type of the resource.
24901 * This enumeration is used for resources that are similar for both
24902 * TX and RX paths of the chip.
24904 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
24906 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24908 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24909 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
24910 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
24912 * Setting of this flag indicates enabling of a byte counter for a given
24915 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
24917 * Setting of this flag indicates enabling of a packet counter for a given
24920 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
24921 /* Setting of this flag indicates de-capsulation action for the given flow. */
24922 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
24923 /* Setting of this flag indicates encapsulation action for the given flow. */
24924 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
24926 * Setting of this flag indicates drop action. If this flag is not set,
24927 * then it should be considered accept action.
24929 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
24931 * Setting of this flag indicates that a meter is expected to be attached
24932 * to this flow. This hint can be used when choosing the action record
24933 * format required for the flow.
24935 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
24938 * This bit must be '1' for the l2_filter_id field to be
24941 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
24944 * This bit must be '1' for the tunnel_type field to be
24947 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
24950 * This bit must be '1' for the tunnel_id field to be
24953 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
24956 * This bit must be '1' for the src_macaddr field to be
24959 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
24962 * This bit must be '1' for the dst_macaddr field to be
24965 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
24968 * This bit must be '1' for the ovlan_vid field to be
24971 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
24974 * This bit must be '1' for the ivlan_vid field to be
24977 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
24980 * This bit must be '1' for the ethertype field to be
24983 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
24986 * This bit must be '1' for the src_ipaddr field to be
24989 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
24992 * This bit must be '1' for the dst_ipaddr field to be
24995 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
24998 * This bit must be '1' for the ipaddr_type field to be
25001 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
25004 * This bit must be '1' for the ip_protocol field to be
25007 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
25010 * This bit must be '1' for the src_port field to be
25013 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
25016 * This bit must be '1' for the dst_port field to be
25019 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
25022 * This bit must be '1' for the dst_id field to be
25025 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
25028 * This bit must be '1' for the mirror_vnic_id field to be
25031 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25034 * This bit must be '1' for the encap_record_id field to be
25037 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
25040 * This bit must be '1' for the meter_instance_id field to be
25043 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
25046 * This value identifies a set of CFA data structures used for an L2
25049 uint64_t l2_filter_id;
25051 uint8_t tunnel_type;
25053 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25055 /* Virtual eXtensible Local Area Network (VXLAN) */
25056 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25058 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25059 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25061 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25062 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25065 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25067 /* Generic Network Virtualization Encapsulation (Geneve) */
25068 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25070 /* Multi-Protocol Lable Switching (MPLS) */
25071 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25073 /* Stateless Transport Tunnel (STT) */
25074 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
25076 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25077 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25079 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25080 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25082 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25083 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25085 /* Use fixed layer 2 ether type of 0xFFFF */
25086 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25088 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25089 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25091 /* Any tunneled traffic */
25092 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25094 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25095 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25096 uint8_t unused_0[3];
25098 * Tunnel identifier.
25099 * Virtual Network Identifier (VNI). Only valid with
25100 * tunnel_types VXLAN, NVGRE, and Geneve.
25101 * Only lower 24-bits of VNI field are used
25102 * in setting up the filter.
25104 uint32_t tunnel_id;
25106 * This value indicates the source MAC address in
25107 * the Ethernet header.
25109 uint8_t src_macaddr[6];
25110 /* The meter instance to attach to the flow. */
25111 uint16_t meter_instance_id;
25113 * A value of 0xfff is considered invalid and implies the
25114 * instance is not configured.
25116 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
25118 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
25119 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
25121 * This value indicates the destination MAC address in
25122 * the Ethernet header.
25124 uint8_t dst_macaddr[6];
25126 * This value indicates the VLAN ID of the outer VLAN tag
25127 * in the Ethernet header.
25129 uint16_t ovlan_vid;
25131 * This value indicates the VLAN ID of the inner VLAN tag
25132 * in the Ethernet header.
25134 uint16_t ivlan_vid;
25135 /* This value indicates the ethertype in the Ethernet header. */
25136 uint16_t ethertype;
25138 * This value indicates the type of IP address.
25141 * All others are invalid.
25143 uint8_t ip_addr_type;
25145 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
25147 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
25149 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
25150 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
25151 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
25153 * The value of protocol filed in IP header.
25154 * Applies to UDP and TCP traffic.
25158 uint8_t ip_protocol;
25160 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
25162 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
25164 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
25165 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
25166 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
25167 uint8_t unused_1[2];
25169 * The value of source IP address to be used in filtering.
25170 * For IPv4, first four bytes represent the IP address.
25172 uint32_t src_ipaddr[4];
25174 * big_endian = True
25175 * The value of destination IP address to be used in filtering.
25176 * For IPv4, first four bytes represent the IP address.
25178 uint32_t dst_ipaddr[4];
25180 * The value of source port to be used in filtering.
25181 * Applies to UDP and TCP traffic.
25185 * The value of destination port to be used in filtering.
25186 * Applies to UDP and TCP traffic.
25190 * If set, this value shall represent the
25191 * Logical VNIC ID of the destination VNIC for the RX
25192 * path and network port id of the destination port for
25197 * Logical VNIC ID of the VNIC where traffic is
25200 uint16_t mirror_vnic_id;
25201 /* Logical ID of the encapsulation record. */
25202 uint32_t encap_record_id;
25203 uint8_t unused_2[4];
25204 } __attribute__((packed));
25206 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
25207 struct hwrm_cfa_em_flow_alloc_output {
25208 /* The specific error status for the command. */
25209 uint16_t error_code;
25210 /* The HWRM command request type. */
25212 /* The sequence ID from the original command. */
25214 /* The length of the response data in number of bytes. */
25216 /* This value is an opaque id into CFA data structures. */
25217 uint64_t em_filter_id;
25219 * This is the ID of the flow associated with this
25221 * This value shall be used to match and associate the
25222 * flow identifier returned in completion records.
25223 * A value of 0xFFFFFFFF shall indicate no flow id.
25226 uint8_t unused_0[3];
25228 * This field is used in Output records to indicate that the output
25229 * is completely written to RAM. This field should be read as '1'
25230 * to indicate that the output has been completely written.
25231 * When writing a command completion or response to an internal processor,
25232 * the order of writes has to be such that this field is written last.
25235 } __attribute__((packed));
25237 /*************************
25238 * hwrm_cfa_em_flow_free *
25239 *************************/
25242 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
25243 struct hwrm_cfa_em_flow_free_input {
25244 /* The HWRM command request type. */
25247 * The completion ring to send the completion event on. This should
25248 * be the NQ ID returned from the `nq_alloc` HWRM command.
25250 uint16_t cmpl_ring;
25252 * The sequence ID is used by the driver for tracking multiple
25253 * commands. This ID is treated as opaque data by the firmware and
25254 * the value is returned in the `hwrm_resp_hdr` upon completion.
25258 * The target ID of the command:
25259 * * 0x0-0xFFF8 - The function ID
25260 * * 0xFFF8-0xFFFE - Reserved for internal processors
25263 uint16_t target_id;
25265 * A physical address pointer pointing to a host buffer that the
25266 * command's response data will be written. This can be either a host
25267 * physical address (HPA) or a guest physical address (GPA) and must
25268 * point to a physically contiguous block of memory.
25270 uint64_t resp_addr;
25271 /* This value is an opaque id into CFA data structures. */
25272 uint64_t em_filter_id;
25273 } __attribute__((packed));
25275 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
25276 struct hwrm_cfa_em_flow_free_output {
25277 /* The specific error status for the command. */
25278 uint16_t error_code;
25279 /* The HWRM command request type. */
25281 /* The sequence ID from the original command. */
25283 /* The length of the response data in number of bytes. */
25285 uint8_t unused_0[7];
25287 * This field is used in Output records to indicate that the output
25288 * is completely written to RAM. This field should be read as '1'
25289 * to indicate that the output has been completely written.
25290 * When writing a command completion or response to an internal processor,
25291 * the order of writes has to be such that this field is written last.
25294 } __attribute__((packed));
25296 /************************
25297 * hwrm_cfa_meter_qcaps *
25298 ************************/
25301 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
25302 struct hwrm_cfa_meter_qcaps_input {
25303 /* The HWRM command request type. */
25306 * The completion ring to send the completion event on. This should
25307 * be the NQ ID returned from the `nq_alloc` HWRM command.
25309 uint16_t cmpl_ring;
25311 * The sequence ID is used by the driver for tracking multiple
25312 * commands. This ID is treated as opaque data by the firmware and
25313 * the value is returned in the `hwrm_resp_hdr` upon completion.
25317 * The target ID of the command:
25318 * * 0x0-0xFFF8 - The function ID
25319 * * 0xFFF8-0xFFFE - Reserved for internal processors
25322 uint16_t target_id;
25324 * A physical address pointer pointing to a host buffer that the
25325 * command's response data will be written. This can be either a host
25326 * physical address (HPA) or a guest physical address (GPA) and must
25327 * point to a physically contiguous block of memory.
25329 uint64_t resp_addr;
25330 } __attribute__((packed));
25332 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
25333 struct hwrm_cfa_meter_qcaps_output {
25334 /* The specific error status for the command. */
25335 uint16_t error_code;
25336 /* The HWRM command request type. */
25338 /* The sequence ID from the original command. */
25340 /* The length of the response data in number of bytes. */
25344 * Enumeration denoting the clock at which the Meter is running with.
25345 * This enumeration is used for resources that are similar for both
25346 * TX and RX paths of the chip.
25348 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
25349 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
25351 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
25353 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
25354 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
25355 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
25356 uint8_t unused_0[4];
25358 * The minimum guaranteed number of tx meter profiles supported
25359 * for this function.
25361 uint16_t min_tx_profile;
25363 * The maximum non-guaranteed number of tx meter profiles supported
25364 * for this function.
25366 uint16_t max_tx_profile;
25368 * The minimum guaranteed number of rx meter profiles supported
25369 * for this function.
25371 uint16_t min_rx_profile;
25373 * The maximum non-guaranteed number of rx meter profiles supported
25374 * for this function.
25376 uint16_t max_rx_profile;
25378 * The minimum guaranteed number of tx meter instances supported
25379 * for this function.
25381 uint16_t min_tx_instance;
25383 * The maximum non-guaranteed number of tx meter instances supported
25384 * for this function.
25386 uint16_t max_tx_instance;
25388 * The minimum guaranteed number of rx meter instances supported
25389 * for this function.
25391 uint16_t min_rx_instance;
25393 * The maximum non-guaranteed number of rx meter instances supported
25394 * for this function.
25396 uint16_t max_rx_instance;
25397 uint8_t unused_1[7];
25399 * This field is used in Output records to indicate that the output
25400 * is completely written to RAM. This field should be read as '1'
25401 * to indicate that the output has been completely written.
25402 * When writing a command completion or response to an internal processor,
25403 * the order of writes has to be such that this field is written last.
25406 } __attribute__((packed));
25408 /********************************
25409 * hwrm_cfa_meter_profile_alloc *
25410 ********************************/
25413 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
25414 struct hwrm_cfa_meter_profile_alloc_input {
25415 /* The HWRM command request type. */
25418 * The completion ring to send the completion event on. This should
25419 * be the NQ ID returned from the `nq_alloc` HWRM command.
25421 uint16_t cmpl_ring;
25423 * The sequence ID is used by the driver for tracking multiple
25424 * commands. This ID is treated as opaque data by the firmware and
25425 * the value is returned in the `hwrm_resp_hdr` upon completion.
25429 * The target ID of the command:
25430 * * 0x0-0xFFF8 - The function ID
25431 * * 0xFFF8-0xFFFE - Reserved for internal processors
25434 uint16_t target_id;
25436 * A physical address pointer pointing to a host buffer that the
25437 * command's response data will be written. This can be either a host
25438 * physical address (HPA) or a guest physical address (GPA) and must
25439 * point to a physically contiguous block of memory.
25441 uint64_t resp_addr;
25444 * Enumeration denoting the RX, TX type of the resource.
25445 * This enumeration is used for resources that are similar for both
25446 * TX and RX paths of the chip.
25448 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
25450 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
25453 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
25455 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
25456 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
25457 /* The meter algorithm type. */
25458 uint8_t meter_type;
25459 /* RFC 2697 (srTCM) */
25460 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
25462 /* RFC 2698 (trTCM) */
25463 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
25465 /* RFC 4115 (trTCM) */
25466 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
25468 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
25469 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
25471 * This field is reserved for the future use.
25472 * It shall be set to 0.
25474 uint16_t reserved1;
25476 * This field is reserved for the future use.
25477 * It shall be set to 0.
25479 uint32_t reserved2;
25480 /* A meter rate specified in bytes-per-second. */
25481 uint32_t commit_rate;
25482 /* The bandwidth value. */
25483 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
25484 UINT32_C(0xfffffff)
25485 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
25487 /* The granularity of the value (bits or bytes). */
25488 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
25489 UINT32_C(0x10000000)
25490 /* Value is in bits. */
25491 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
25492 (UINT32_C(0x0) << 28)
25493 /* Value is in bytes. */
25494 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
25495 (UINT32_C(0x1) << 28)
25496 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
25497 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
25498 /* bw_value_unit is 3 b */
25499 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
25500 UINT32_C(0xe0000000)
25501 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
25503 /* Value is in Mb or MB (base 10). */
25504 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
25505 (UINT32_C(0x0) << 29)
25506 /* Value is in Kb or KB (base 10). */
25507 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
25508 (UINT32_C(0x2) << 29)
25509 /* Value is in bits or bytes. */
25510 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
25511 (UINT32_C(0x4) << 29)
25512 /* Value is in Gb or GB (base 10). */
25513 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
25514 (UINT32_C(0x6) << 29)
25515 /* Value is in 1/100th of a percentage of total bandwidth. */
25516 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
25517 (UINT32_C(0x1) << 29)
25519 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
25520 (UINT32_C(0x7) << 29)
25521 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
25522 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
25523 /* A meter burst size specified in bytes. */
25524 uint32_t commit_burst;
25525 /* The bandwidth value. */
25526 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
25527 UINT32_C(0xfffffff)
25528 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
25530 /* The granularity of the value (bits or bytes). */
25531 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
25532 UINT32_C(0x10000000)
25533 /* Value is in bits. */
25534 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
25535 (UINT32_C(0x0) << 28)
25536 /* Value is in bytes. */
25537 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
25538 (UINT32_C(0x1) << 28)
25539 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
25540 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
25541 /* bw_value_unit is 3 b */
25542 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
25543 UINT32_C(0xe0000000)
25544 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
25546 /* Value is in Mb or MB (base 10). */
25547 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
25548 (UINT32_C(0x0) << 29)
25549 /* Value is in Kb or KB (base 10). */
25550 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
25551 (UINT32_C(0x2) << 29)
25552 /* Value is in bits or bytes. */
25553 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
25554 (UINT32_C(0x4) << 29)
25555 /* Value is in Gb or GB (base 10). */
25556 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
25557 (UINT32_C(0x6) << 29)
25558 /* Value is in 1/100th of a percentage of total bandwidth. */
25559 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
25560 (UINT32_C(0x1) << 29)
25561 /* Invalid value */
25562 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
25563 (UINT32_C(0x7) << 29)
25564 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
25565 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
25566 /* A meter rate specified in bytes-per-second. */
25567 uint32_t excess_peak_rate;
25568 /* The bandwidth value. */
25569 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
25570 UINT32_C(0xfffffff)
25571 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
25573 /* The granularity of the value (bits or bytes). */
25574 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
25575 UINT32_C(0x10000000)
25576 /* Value is in bits. */
25577 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
25578 (UINT32_C(0x0) << 28)
25579 /* Value is in bytes. */
25580 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
25581 (UINT32_C(0x1) << 28)
25582 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
25583 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
25584 /* bw_value_unit is 3 b */
25585 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
25586 UINT32_C(0xe0000000)
25587 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
25589 /* Value is in Mb or MB (base 10). */
25590 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
25591 (UINT32_C(0x0) << 29)
25592 /* Value is in Kb or KB (base 10). */
25593 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
25594 (UINT32_C(0x2) << 29)
25595 /* Value is in bits or bytes. */
25596 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
25597 (UINT32_C(0x4) << 29)
25598 /* Value is in Gb or GB (base 10). */
25599 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
25600 (UINT32_C(0x6) << 29)
25601 /* Value is in 1/100th of a percentage of total bandwidth. */
25602 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
25603 (UINT32_C(0x1) << 29)
25605 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
25606 (UINT32_C(0x7) << 29)
25607 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
25608 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
25609 /* A meter burst size specified in bytes. */
25610 uint32_t excess_peak_burst;
25611 /* The bandwidth value. */
25612 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
25613 UINT32_C(0xfffffff)
25614 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
25616 /* The granularity of the value (bits or bytes). */
25617 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
25618 UINT32_C(0x10000000)
25619 /* Value is in bits. */
25620 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
25621 (UINT32_C(0x0) << 28)
25622 /* Value is in bytes. */
25623 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
25624 (UINT32_C(0x1) << 28)
25625 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
25626 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
25627 /* bw_value_unit is 3 b */
25628 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
25629 UINT32_C(0xe0000000)
25630 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
25632 /* Value is in Mb or MB (base 10). */
25633 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
25634 (UINT32_C(0x0) << 29)
25635 /* Value is in Kb or KB (base 10). */
25636 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
25637 (UINT32_C(0x2) << 29)
25638 /* Value is in bits or bytes. */
25639 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
25640 (UINT32_C(0x4) << 29)
25641 /* Value is in Gb or GB (base 10). */
25642 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
25643 (UINT32_C(0x6) << 29)
25644 /* Value is in 1/100th of a percentage of total bandwidth. */
25645 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
25646 (UINT32_C(0x1) << 29)
25648 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
25649 (UINT32_C(0x7) << 29)
25650 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
25651 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
25652 } __attribute__((packed));
25654 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
25655 struct hwrm_cfa_meter_profile_alloc_output {
25656 /* The specific error status for the command. */
25657 uint16_t error_code;
25658 /* The HWRM command request type. */
25660 /* The sequence ID from the original command. */
25662 /* The length of the response data in number of bytes. */
25664 /* This value identifies a meter profile in CFA. */
25665 uint16_t meter_profile_id;
25667 * A value of 0xfff is considered invalid and implies the
25668 * profile is not configured.
25670 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
25672 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
25673 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
25674 uint8_t unused_0[5];
25676 * This field is used in Output records to indicate that the output
25677 * is completely written to RAM. This field should be read as '1'
25678 * to indicate that the output has been completely written.
25679 * When writing a command completion or response to an internal processor,
25680 * the order of writes has to be such that this field is written last.
25683 } __attribute__((packed));
25685 /*******************************
25686 * hwrm_cfa_meter_profile_free *
25687 *******************************/
25690 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
25691 struct hwrm_cfa_meter_profile_free_input {
25692 /* The HWRM command request type. */
25695 * The completion ring to send the completion event on. This should
25696 * be the NQ ID returned from the `nq_alloc` HWRM command.
25698 uint16_t cmpl_ring;
25700 * The sequence ID is used by the driver for tracking multiple
25701 * commands. This ID is treated as opaque data by the firmware and
25702 * the value is returned in the `hwrm_resp_hdr` upon completion.
25706 * The target ID of the command:
25707 * * 0x0-0xFFF8 - The function ID
25708 * * 0xFFF8-0xFFFE - Reserved for internal processors
25711 uint16_t target_id;
25713 * A physical address pointer pointing to a host buffer that the
25714 * command's response data will be written. This can be either a host
25715 * physical address (HPA) or a guest physical address (GPA) and must
25716 * point to a physically contiguous block of memory.
25718 uint64_t resp_addr;
25721 * Enumeration denoting the RX, TX type of the resource.
25722 * This enumeration is used for resources that are similar for both
25723 * TX and RX paths of the chip.
25725 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
25727 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
25730 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
25732 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
25733 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
25735 /* This value identifies a meter profile in CFA. */
25736 uint16_t meter_profile_id;
25738 * A value of 0xfff is considered invalid and implies the
25739 * profile is not configured.
25741 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
25743 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
25744 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
25745 uint8_t unused_1[4];
25746 } __attribute__((packed));
25748 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
25749 struct hwrm_cfa_meter_profile_free_output {
25750 /* The specific error status for the command. */
25751 uint16_t error_code;
25752 /* The HWRM command request type. */
25754 /* The sequence ID from the original command. */
25756 /* The length of the response data in number of bytes. */
25758 uint8_t unused_0[7];
25760 * This field is used in Output records to indicate that the output
25761 * is completely written to RAM. This field should be read as '1'
25762 * to indicate that the output has been completely written.
25763 * When writing a command completion or response to an internal processor,
25764 * the order of writes has to be such that this field is written last.
25767 } __attribute__((packed));
25769 /******************************
25770 * hwrm_cfa_meter_profile_cfg *
25771 ******************************/
25774 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
25775 struct hwrm_cfa_meter_profile_cfg_input {
25776 /* The HWRM command request type. */
25779 * The completion ring to send the completion event on. This should
25780 * be the NQ ID returned from the `nq_alloc` HWRM command.
25782 uint16_t cmpl_ring;
25784 * The sequence ID is used by the driver for tracking multiple
25785 * commands. This ID is treated as opaque data by the firmware and
25786 * the value is returned in the `hwrm_resp_hdr` upon completion.
25790 * The target ID of the command:
25791 * * 0x0-0xFFF8 - The function ID
25792 * * 0xFFF8-0xFFFE - Reserved for internal processors
25795 uint16_t target_id;
25797 * A physical address pointer pointing to a host buffer that the
25798 * command's response data will be written. This can be either a host
25799 * physical address (HPA) or a guest physical address (GPA) and must
25800 * point to a physically contiguous block of memory.
25802 uint64_t resp_addr;
25805 * Enumeration denoting the RX, TX type of the resource.
25806 * This enumeration is used for resources that are similar for both
25807 * TX and RX paths of the chip.
25809 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
25811 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25813 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25814 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
25815 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
25816 /* The meter algorithm type. */
25817 uint8_t meter_type;
25818 /* RFC 2697 (srTCM) */
25819 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
25821 /* RFC 2698 (trTCM) */
25822 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
25824 /* RFC 4115 (trTCM) */
25825 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
25827 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
25828 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
25829 /* This value identifies a meter profile in CFA. */
25830 uint16_t meter_profile_id;
25832 * A value of 0xfff is considered invalid and implies the
25833 * profile is not configured.
25835 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
25837 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
25838 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
25840 * This field is reserved for the future use.
25841 * It shall be set to 0.
25844 /* A meter rate specified in bytes-per-second. */
25845 uint32_t commit_rate;
25846 /* The bandwidth value. */
25847 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
25848 UINT32_C(0xfffffff)
25849 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
25851 /* The granularity of the value (bits or bytes). */
25852 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
25853 UINT32_C(0x10000000)
25854 /* Value is in bits. */
25855 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
25856 (UINT32_C(0x0) << 28)
25857 /* Value is in bytes. */
25858 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
25859 (UINT32_C(0x1) << 28)
25860 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
25861 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
25862 /* bw_value_unit is 3 b */
25863 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
25864 UINT32_C(0xe0000000)
25865 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
25867 /* Value is in Mb or MB (base 10). */
25868 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
25869 (UINT32_C(0x0) << 29)
25870 /* Value is in Kb or KB (base 10). */
25871 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
25872 (UINT32_C(0x2) << 29)
25873 /* Value is in bits or bytes. */
25874 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
25875 (UINT32_C(0x4) << 29)
25876 /* Value is in Gb or GB (base 10). */
25877 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
25878 (UINT32_C(0x6) << 29)
25879 /* Value is in 1/100th of a percentage of total bandwidth. */
25880 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
25881 (UINT32_C(0x1) << 29)
25883 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
25884 (UINT32_C(0x7) << 29)
25885 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
25886 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
25887 /* A meter burst size specified in bytes. */
25888 uint32_t commit_burst;
25889 /* The bandwidth value. */
25890 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
25891 UINT32_C(0xfffffff)
25892 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
25894 /* The granularity of the value (bits or bytes). */
25895 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
25896 UINT32_C(0x10000000)
25897 /* Value is in bits. */
25898 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
25899 (UINT32_C(0x0) << 28)
25900 /* Value is in bytes. */
25901 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
25902 (UINT32_C(0x1) << 28)
25903 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
25904 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
25905 /* bw_value_unit is 3 b */
25906 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
25907 UINT32_C(0xe0000000)
25908 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
25910 /* Value is in Mb or MB (base 10). */
25911 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
25912 (UINT32_C(0x0) << 29)
25913 /* Value is in Kb or KB (base 10). */
25914 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
25915 (UINT32_C(0x2) << 29)
25916 /* Value is in bits or bytes. */
25917 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
25918 (UINT32_C(0x4) << 29)
25919 /* Value is in Gb or GB (base 10). */
25920 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
25921 (UINT32_C(0x6) << 29)
25922 /* Value is in 1/100th of a percentage of total bandwidth. */
25923 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
25924 (UINT32_C(0x1) << 29)
25925 /* Invalid value */
25926 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
25927 (UINT32_C(0x7) << 29)
25928 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
25929 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
25930 /* A meter rate specified in bytes-per-second. */
25931 uint32_t excess_peak_rate;
25932 /* The bandwidth value. */
25933 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
25934 UINT32_C(0xfffffff)
25935 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
25937 /* The granularity of the value (bits or bytes). */
25938 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
25939 UINT32_C(0x10000000)
25940 /* Value is in bits. */
25941 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
25942 (UINT32_C(0x0) << 28)
25943 /* Value is in bytes. */
25944 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
25945 (UINT32_C(0x1) << 28)
25946 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
25947 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
25948 /* bw_value_unit is 3 b */
25949 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
25950 UINT32_C(0xe0000000)
25951 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
25953 /* Value is in Mb or MB (base 10). */
25954 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
25955 (UINT32_C(0x0) << 29)
25956 /* Value is in Kb or KB (base 10). */
25957 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
25958 (UINT32_C(0x2) << 29)
25959 /* Value is in bits or bytes. */
25960 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
25961 (UINT32_C(0x4) << 29)
25962 /* Value is in Gb or GB (base 10). */
25963 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
25964 (UINT32_C(0x6) << 29)
25965 /* Value is in 1/100th of a percentage of total bandwidth. */
25966 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
25967 (UINT32_C(0x1) << 29)
25969 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
25970 (UINT32_C(0x7) << 29)
25971 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
25972 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
25973 /* A meter burst size specified in bytes. */
25974 uint32_t excess_peak_burst;
25975 /* The bandwidth value. */
25976 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
25977 UINT32_C(0xfffffff)
25978 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
25980 /* The granularity of the value (bits or bytes). */
25981 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
25982 UINT32_C(0x10000000)
25983 /* Value is in bits. */
25984 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
25985 (UINT32_C(0x0) << 28)
25986 /* Value is in bytes. */
25987 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
25988 (UINT32_C(0x1) << 28)
25989 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
25990 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
25991 /* bw_value_unit is 3 b */
25992 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
25993 UINT32_C(0xe0000000)
25994 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
25996 /* Value is in Mb or MB (base 10). */
25997 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
25998 (UINT32_C(0x0) << 29)
25999 /* Value is in Kb or KB (base 10). */
26000 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
26001 (UINT32_C(0x2) << 29)
26002 /* Value is in bits or bytes. */
26003 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
26004 (UINT32_C(0x4) << 29)
26005 /* Value is in Gb or GB (base 10). */
26006 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
26007 (UINT32_C(0x6) << 29)
26008 /* Value is in 1/100th of a percentage of total bandwidth. */
26009 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
26010 (UINT32_C(0x1) << 29)
26012 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
26013 (UINT32_C(0x7) << 29)
26014 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
26015 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
26016 } __attribute__((packed));
26018 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
26019 struct hwrm_cfa_meter_profile_cfg_output {
26020 /* The specific error status for the command. */
26021 uint16_t error_code;
26022 /* The HWRM command request type. */
26024 /* The sequence ID from the original command. */
26026 /* The length of the response data in number of bytes. */
26028 uint8_t unused_0[7];
26030 * This field is used in Output records to indicate that the output
26031 * is completely written to RAM. This field should be read as '1'
26032 * to indicate that the output has been completely written.
26033 * When writing a command completion or response to an internal processor,
26034 * the order of writes has to be such that this field is written last.
26037 } __attribute__((packed));
26039 /*********************************
26040 * hwrm_cfa_meter_instance_alloc *
26041 *********************************/
26044 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
26045 struct hwrm_cfa_meter_instance_alloc_input {
26046 /* The HWRM command request type. */
26049 * The completion ring to send the completion event on. This should
26050 * be the NQ ID returned from the `nq_alloc` HWRM command.
26052 uint16_t cmpl_ring;
26054 * The sequence ID is used by the driver for tracking multiple
26055 * commands. This ID is treated as opaque data by the firmware and
26056 * the value is returned in the `hwrm_resp_hdr` upon completion.
26060 * The target ID of the command:
26061 * * 0x0-0xFFF8 - The function ID
26062 * * 0xFFF8-0xFFFE - Reserved for internal processors
26065 uint16_t target_id;
26067 * A physical address pointer pointing to a host buffer that the
26068 * command's response data will be written. This can be either a host
26069 * physical address (HPA) or a guest physical address (GPA) and must
26070 * point to a physically contiguous block of memory.
26072 uint64_t resp_addr;
26075 * Enumeration denoting the RX, TX type of the resource.
26076 * This enumeration is used for resources that are similar for both
26077 * TX and RX paths of the chip.
26079 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
26082 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
26085 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
26087 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
26088 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
26090 /* This value identifies a meter profile in CFA. */
26091 uint16_t meter_profile_id;
26093 * A value of 0xffff is considered invalid and implies the
26094 * profile is not configured.
26096 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
26098 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
26099 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
26100 uint8_t unused_1[4];
26101 } __attribute__((packed));
26103 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
26104 struct hwrm_cfa_meter_instance_alloc_output {
26105 /* The specific error status for the command. */
26106 uint16_t error_code;
26107 /* The HWRM command request type. */
26109 /* The sequence ID from the original command. */
26111 /* The length of the response data in number of bytes. */
26113 /* This value identifies a meter instance in CFA. */
26114 uint16_t meter_instance_id;
26116 * A value of 0xffff is considered invalid and implies the
26117 * instance is not configured.
26119 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
26121 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
26122 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
26123 uint8_t unused_0[5];
26125 * This field is used in Output records to indicate that the output
26126 * is completely written to RAM. This field should be read as '1'
26127 * to indicate that the output has been completely written.
26128 * When writing a command completion or response to an internal processor,
26129 * the order of writes has to be such that this field is written last.
26132 } __attribute__((packed));
26134 /*******************************
26135 * hwrm_cfa_meter_instance_cfg *
26136 *******************************/
26139 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
26140 struct hwrm_cfa_meter_instance_cfg_input {
26141 /* The HWRM command request type. */
26144 * The completion ring to send the completion event on. This should
26145 * be the NQ ID returned from the `nq_alloc` HWRM command.
26147 uint16_t cmpl_ring;
26149 * The sequence ID is used by the driver for tracking multiple
26150 * commands. This ID is treated as opaque data by the firmware and
26151 * the value is returned in the `hwrm_resp_hdr` upon completion.
26155 * The target ID of the command:
26156 * * 0x0-0xFFF8 - The function ID
26157 * * 0xFFF8-0xFFFE - Reserved for internal processors
26160 uint16_t target_id;
26162 * A physical address pointer pointing to a host buffer that the
26163 * command's response data will be written. This can be either a host
26164 * physical address (HPA) or a guest physical address (GPA) and must
26165 * point to a physically contiguous block of memory.
26167 uint64_t resp_addr;
26170 * Enumeration denoting the RX, TX type of the resource.
26171 * This enumeration is used for resources that are similar for both
26172 * TX and RX paths of the chip.
26174 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
26176 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
26179 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
26181 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
26182 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
26185 * This value identifies a new meter profile to be associated with
26186 * the meter instance specified in this command.
26188 uint16_t meter_profile_id;
26190 * A value of 0xffff is considered invalid and implies the
26191 * profile is not configured.
26193 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
26195 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
26196 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
26198 * This value identifies the ID of a meter instance that needs to be updated with
26199 * a new meter profile specified in this command.
26201 uint16_t meter_instance_id;
26202 uint8_t unused_1[2];
26203 } __attribute__((packed));
26205 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
26206 struct hwrm_cfa_meter_instance_cfg_output {
26207 /* The specific error status for the command. */
26208 uint16_t error_code;
26209 /* The HWRM command request type. */
26211 /* The sequence ID from the original command. */
26213 /* The length of the response data in number of bytes. */
26215 uint8_t unused_0[7];
26217 * This field is used in Output records to indicate that the output
26218 * is completely written to RAM. This field should be read as '1'
26219 * to indicate that the output has been completely written.
26220 * When writing a command completion or response to an internal processor,
26221 * the order of writes has to be such that this field is written last.
26224 } __attribute__((packed));
26226 /********************************
26227 * hwrm_cfa_meter_instance_free *
26228 ********************************/
26231 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
26232 struct hwrm_cfa_meter_instance_free_input {
26233 /* The HWRM command request type. */
26236 * The completion ring to send the completion event on. This should
26237 * be the NQ ID returned from the `nq_alloc` HWRM command.
26239 uint16_t cmpl_ring;
26241 * The sequence ID is used by the driver for tracking multiple
26242 * commands. This ID is treated as opaque data by the firmware and
26243 * the value is returned in the `hwrm_resp_hdr` upon completion.
26247 * The target ID of the command:
26248 * * 0x0-0xFFF8 - The function ID
26249 * * 0xFFF8-0xFFFE - Reserved for internal processors
26252 uint16_t target_id;
26254 * A physical address pointer pointing to a host buffer that the
26255 * command's response data will be written. This can be either a host
26256 * physical address (HPA) or a guest physical address (GPA) and must
26257 * point to a physically contiguous block of memory.
26259 uint64_t resp_addr;
26262 * Enumeration denoting the RX, TX type of the resource.
26263 * This enumeration is used for resources that are similar for both
26264 * TX and RX paths of the chip.
26266 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
26268 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
26271 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
26273 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
26274 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
26276 /* This value identifies a meter instance in CFA. */
26277 uint16_t meter_instance_id;
26279 * A value of 0xfff is considered invalid and implies the
26280 * instance is not configured.
26282 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
26284 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
26285 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
26286 uint8_t unused_1[4];
26287 } __attribute__((packed));
26289 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
26290 struct hwrm_cfa_meter_instance_free_output {
26291 /* The specific error status for the command. */
26292 uint16_t error_code;
26293 /* The HWRM command request type. */
26295 /* The sequence ID from the original command. */
26297 /* The length of the response data in number of bytes. */
26299 uint8_t unused_0[7];
26301 * This field is used in Output records to indicate that the output
26302 * is completely written to RAM. This field should be read as '1'
26303 * to indicate that the output has been completely written.
26304 * When writing a command completion or response to an internal processor,
26305 * the order of writes has to be such that this field is written last.
26308 } __attribute__((packed));
26310 /*******************************
26311 * hwrm_cfa_decap_filter_alloc *
26312 *******************************/
26315 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
26316 struct hwrm_cfa_decap_filter_alloc_input {
26317 /* The HWRM command request type. */
26320 * The completion ring to send the completion event on. This should
26321 * be the NQ ID returned from the `nq_alloc` HWRM command.
26323 uint16_t cmpl_ring;
26325 * The sequence ID is used by the driver for tracking multiple
26326 * commands. This ID is treated as opaque data by the firmware and
26327 * the value is returned in the `hwrm_resp_hdr` upon completion.
26331 * The target ID of the command:
26332 * * 0x0-0xFFF8 - The function ID
26333 * * 0xFFF8-0xFFFE - Reserved for internal processors
26336 uint16_t target_id;
26338 * A physical address pointer pointing to a host buffer that the
26339 * command's response data will be written. This can be either a host
26340 * physical address (HPA) or a guest physical address (GPA) and must
26341 * point to a physically contiguous block of memory.
26343 uint64_t resp_addr;
26345 /* ovs_tunnel is 1 b */
26346 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
26350 * This bit must be '1' for the tunnel_type field to be
26353 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26356 * This bit must be '1' for the tunnel_id field to be
26359 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
26362 * This bit must be '1' for the src_macaddr field to be
26365 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
26368 * This bit must be '1' for the dst_macaddr field to be
26371 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
26374 * This bit must be '1' for the ovlan_vid field to be
26377 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
26380 * This bit must be '1' for the ivlan_vid field to be
26383 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
26386 * This bit must be '1' for the t_ovlan_vid field to be
26389 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
26392 * This bit must be '1' for the t_ivlan_vid field to be
26395 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
26398 * This bit must be '1' for the ethertype field to be
26401 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
26404 * This bit must be '1' for the src_ipaddr field to be
26407 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
26410 * This bit must be '1' for the dst_ipaddr field to be
26413 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
26416 * This bit must be '1' for the ipaddr_type field to be
26419 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
26422 * This bit must be '1' for the ip_protocol field to be
26425 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
26428 * This bit must be '1' for the src_port field to be
26431 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
26434 * This bit must be '1' for the dst_port field to be
26437 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
26440 * This bit must be '1' for the dst_id field to be
26443 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
26446 * This bit must be '1' for the mirror_vnic_id field to be
26449 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26452 * Tunnel identifier.
26453 * Virtual Network Identifier (VNI). Only valid with
26454 * tunnel_types VXLAN, NVGRE, and Geneve.
26455 * Only lower 24-bits of VNI field are used
26456 * in setting up the filter.
26458 uint32_t tunnel_id;
26460 uint8_t tunnel_type;
26462 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26464 /* Virtual eXtensible Local Area Network (VXLAN) */
26465 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26467 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26468 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26470 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26471 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26474 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26476 /* Generic Network Virtualization Encapsulation (Geneve) */
26477 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26479 /* Multi-Protocol Lable Switching (MPLS) */
26480 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26482 /* Stateless Transport Tunnel (STT) */
26483 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
26485 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26486 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26488 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26489 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26491 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26492 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26494 /* Use fixed layer 2 ether type of 0xFFFF */
26495 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26497 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26498 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26500 /* Any tunneled traffic */
26501 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26503 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26504 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26508 * This value indicates the source MAC address in
26509 * the Ethernet header.
26511 uint8_t src_macaddr[6];
26512 uint8_t unused_2[2];
26514 * This value indicates the destination MAC address in
26515 * the Ethernet header.
26517 uint8_t dst_macaddr[6];
26519 * This value indicates the VLAN ID of the outer VLAN tag
26520 * in the Ethernet header.
26522 uint16_t ovlan_vid;
26524 * This value indicates the VLAN ID of the inner VLAN tag
26525 * in the Ethernet header.
26527 uint16_t ivlan_vid;
26529 * This value indicates the VLAN ID of the outer VLAN tag
26530 * in the tunnel Ethernet header.
26532 uint16_t t_ovlan_vid;
26534 * This value indicates the VLAN ID of the inner VLAN tag
26535 * in the tunnel Ethernet header.
26537 uint16_t t_ivlan_vid;
26538 /* This value indicates the ethertype in the Ethernet header. */
26539 uint16_t ethertype;
26541 * This value indicates the type of IP address.
26544 * All others are invalid.
26546 uint8_t ip_addr_type;
26548 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
26551 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
26554 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
26556 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
26557 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
26559 * The value of protocol filed in IP header.
26560 * Applies to UDP and TCP traffic.
26564 uint8_t ip_protocol;
26566 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
26569 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
26572 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
26574 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
26575 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
26579 * The value of source IP address to be used in filtering.
26580 * For IPv4, first four bytes represent the IP address.
26582 uint32_t src_ipaddr[4];
26584 * The value of destination IP address to be used in filtering.
26585 * For IPv4, first four bytes represent the IP address.
26587 uint32_t dst_ipaddr[4];
26589 * The value of source port to be used in filtering.
26590 * Applies to UDP and TCP traffic.
26594 * The value of destination port to be used in filtering.
26595 * Applies to UDP and TCP traffic.
26599 * If set, this value shall represent the
26600 * Logical VNIC ID of the destination VNIC for the RX
26605 * If set, this value shall represent the L2 context that matches the L2
26606 * information of the decap filter.
26608 uint16_t l2_ctxt_ref_id;
26609 } __attribute__((packed));
26611 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
26612 struct hwrm_cfa_decap_filter_alloc_output {
26613 /* The specific error status for the command. */
26614 uint16_t error_code;
26615 /* The HWRM command request type. */
26617 /* The sequence ID from the original command. */
26619 /* The length of the response data in number of bytes. */
26621 /* This value is an opaque id into CFA data structures. */
26622 uint32_t decap_filter_id;
26623 uint8_t unused_0[3];
26625 * This field is used in Output records to indicate that the output
26626 * is completely written to RAM. This field should be read as '1'
26627 * to indicate that the output has been completely written.
26628 * When writing a command completion or response to an internal processor,
26629 * the order of writes has to be such that this field is written last.
26632 } __attribute__((packed));
26634 /******************************
26635 * hwrm_cfa_decap_filter_free *
26636 ******************************/
26639 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
26640 struct hwrm_cfa_decap_filter_free_input {
26641 /* The HWRM command request type. */
26644 * The completion ring to send the completion event on. This should
26645 * be the NQ ID returned from the `nq_alloc` HWRM command.
26647 uint16_t cmpl_ring;
26649 * The sequence ID is used by the driver for tracking multiple
26650 * commands. This ID is treated as opaque data by the firmware and
26651 * the value is returned in the `hwrm_resp_hdr` upon completion.
26655 * The target ID of the command:
26656 * * 0x0-0xFFF8 - The function ID
26657 * * 0xFFF8-0xFFFE - Reserved for internal processors
26660 uint16_t target_id;
26662 * A physical address pointer pointing to a host buffer that the
26663 * command's response data will be written. This can be either a host
26664 * physical address (HPA) or a guest physical address (GPA) and must
26665 * point to a physically contiguous block of memory.
26667 uint64_t resp_addr;
26668 /* This value is an opaque id into CFA data structures. */
26669 uint32_t decap_filter_id;
26670 uint8_t unused_0[4];
26671 } __attribute__((packed));
26673 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
26674 struct hwrm_cfa_decap_filter_free_output {
26675 /* The specific error status for the command. */
26676 uint16_t error_code;
26677 /* The HWRM command request type. */
26679 /* The sequence ID from the original command. */
26681 /* The length of the response data in number of bytes. */
26683 uint8_t unused_0[7];
26685 * This field is used in Output records to indicate that the output
26686 * is completely written to RAM. This field should be read as '1'
26687 * to indicate that the output has been completely written.
26688 * When writing a command completion or response to an internal processor,
26689 * the order of writes has to be such that this field is written last.
26692 } __attribute__((packed));
26694 /***********************
26695 * hwrm_cfa_flow_alloc *
26696 ***********************/
26699 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
26700 struct hwrm_cfa_flow_alloc_input {
26701 /* The HWRM command request type. */
26704 * The completion ring to send the completion event on. This should
26705 * be the NQ ID returned from the `nq_alloc` HWRM command.
26707 uint16_t cmpl_ring;
26709 * The sequence ID is used by the driver for tracking multiple
26710 * commands. This ID is treated as opaque data by the firmware and
26711 * the value is returned in the `hwrm_resp_hdr` upon completion.
26715 * The target ID of the command:
26716 * * 0x0-0xFFF8 - The function ID
26717 * * 0xFFF8-0xFFFE - Reserved for internal processors
26720 uint16_t target_id;
26722 * A physical address pointer pointing to a host buffer that the
26723 * command's response data will be written. This can be either a host
26724 * physical address (HPA) or a guest physical address (GPA) and must
26725 * point to a physically contiguous block of memory.
26727 uint64_t resp_addr;
26729 /* tunnel is 1 b */
26730 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
26732 /* num_vlan is 2 b */
26733 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
26735 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
26737 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
26738 (UINT32_C(0x0) << 1)
26740 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
26741 (UINT32_C(0x1) << 1)
26743 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
26744 (UINT32_C(0x2) << 1)
26745 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
26746 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
26747 /* Enumeration denoting the Flow Type. */
26748 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
26750 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
26752 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
26753 (UINT32_C(0x0) << 3)
26755 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
26756 (UINT32_C(0x1) << 3)
26758 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
26759 (UINT32_C(0x2) << 3)
26760 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
26761 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
26763 * when set to 1, indicates TX flow offload for function specified in src_fid and
26764 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
26765 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
26766 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
26767 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
26768 * belong to the children VFs of the same PF to indicate VM to VM flow.
26770 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
26773 * when set to 1, indicates RX flow offload for function specified in dst_fid and
26774 * the src_fid should be set to invalid value.
26776 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
26779 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
26780 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
26781 * This flag is only valid when the flow direction is RX.
26783 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
26785 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
26786 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
26793 /* Tunnel handle valid when tunnel flag is set. */
26794 uint32_t tunnel_handle;
26795 uint16_t action_flags;
26797 * Setting of this flag indicates drop action. If this flag is not set,
26798 * then it should be considered accept action.
26800 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
26802 /* recycle is 1 b */
26803 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
26806 * Setting of this flag indicates drop action. If this flag is not set,
26807 * then it should be considered accept action.
26809 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
26812 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
26814 /* tunnel is 1 b */
26815 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
26817 /* nat_src is 1 b */
26818 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
26820 /* nat_dest is 1 b */
26821 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
26823 /* nat_ipv4_address is 1 b */
26824 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
26826 /* l2_header_rewrite is 1 b */
26827 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
26829 /* ttl_decrement is 1 b */
26830 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
26833 * If set to 1 and flow direction is TX, it indicates decap of L2 header
26834 * and encap of tunnel header. If set to 1 and flow direction is RX, it
26835 * indicates decap of tunnel header and encap L2 header. The type of tunnel
26836 * is specified in the tunnel_type field.
26838 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
26840 /* If set to 1, flow aging is enabled for this flow. */
26841 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
26844 * If set to 1 an attempt will be made to try to offload this flow to the
26845 * most optimal flow table resource. If set to 0, the flow will be
26846 * placed to the default flow table resource.
26848 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
26851 * Tx Flow: pf or vf fid.
26855 /* VLAN tpid, valid when push_vlan flag is set. */
26856 uint16_t l2_rewrite_vlan_tpid;
26857 /* VLAN tci, valid when push_vlan flag is set. */
26858 uint16_t l2_rewrite_vlan_tci;
26859 /* Meter id, valid when meter flag is set. */
26860 uint16_t act_meter_id;
26861 /* Flow with the same l2 context tcam key. */
26862 uint16_t ref_flow_handle;
26863 /* This value sets the match value for the ethertype. */
26864 uint16_t ethertype;
26865 /* valid when num tags is 1 or 2. */
26866 uint16_t outer_vlan_tci;
26867 /* This value sets the match value for the Destination MAC address. */
26869 /* valid when num tags is 2. */
26870 uint16_t inner_vlan_tci;
26871 /* This value sets the match value for the Source MAC address. */
26873 /* The bit length of destination IP address mask. */
26874 uint8_t ip_dst_mask_len;
26875 /* The bit length of source IP address mask. */
26876 uint8_t ip_src_mask_len;
26877 /* The value of destination IPv4/IPv6 address. */
26878 uint32_t ip_dst[4];
26879 /* The source IPv4/IPv6 address. */
26880 uint32_t ip_src[4];
26882 * The value of source port.
26883 * Applies to UDP and TCP traffic.
26885 uint16_t l4_src_port;
26887 * The value of source port mask.
26888 * Applies to UDP and TCP traffic.
26890 uint16_t l4_src_port_mask;
26892 * The value of destination port.
26893 * Applies to UDP and TCP traffic.
26895 uint16_t l4_dst_port;
26897 * The value of destination port mask.
26898 * Applies to UDP and TCP traffic.
26900 uint16_t l4_dst_port_mask;
26902 * NAT IPv4/6 address based on address type flag.
26903 * 0 values are ignored.
26905 uint32_t nat_ip_address[4];
26906 /* L2 header re-write Destination MAC address. */
26907 uint16_t l2_rewrite_dmac[3];
26909 * The NAT source/destination port based on direction flag.
26910 * Applies to UDP and TCP traffic.
26911 * 0 values are ignored.
26914 /* L2 header re-write Source MAC address. */
26915 uint16_t l2_rewrite_smac[3];
26916 /* The value of ip protocol. */
26919 uint8_t tunnel_type;
26921 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26923 /* Virtual eXtensible Local Area Network (VXLAN) */
26924 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26926 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26927 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26929 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26930 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26933 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26935 /* Generic Network Virtualization Encapsulation (Geneve) */
26936 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26938 /* Multi-Protocol Lable Switching (MPLS) */
26939 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26941 /* Stateless Transport Tunnel (STT) */
26942 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
26944 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26945 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26947 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26948 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26950 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26951 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26953 /* Use fixed layer 2 ether type of 0xFFFF */
26954 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26956 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26957 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26959 /* Any tunneled traffic */
26960 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26962 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26963 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26964 } __attribute__((packed));
26966 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
26967 struct hwrm_cfa_flow_alloc_output {
26968 /* The specific error status for the command. */
26969 uint16_t error_code;
26970 /* The HWRM command request type. */
26972 /* The sequence ID from the original command. */
26974 /* The length of the response data in number of bytes. */
26976 /* Flow record index. */
26977 uint16_t flow_handle;
26978 uint8_t unused_0[2];
26980 * This is the ID of the flow associated with this
26982 * This value shall be used to match and associate the
26983 * flow identifier returned in completion records.
26984 * A value of 0xFFFFFFFF shall indicate no flow id.
26987 /* This value identifies a set of CFA data structures used for a flow. */
26988 uint64_t ext_flow_handle;
26989 uint32_t flow_counter_id;
26990 uint8_t unused_1[3];
26992 * This field is used in Output records to indicate that the output
26993 * is completely written to RAM. This field should be read as '1'
26994 * to indicate that the output has been completely written.
26995 * When writing a command completion or response to an internal processor,
26996 * the order of writes has to be such that this field is written last.
26999 } __attribute__((packed));
27001 /**********************
27002 * hwrm_cfa_flow_free *
27003 **********************/
27006 /* hwrm_cfa_flow_free_input (size:256b/32B) */
27007 struct hwrm_cfa_flow_free_input {
27008 /* The HWRM command request type. */
27011 * The completion ring to send the completion event on. This should
27012 * be the NQ ID returned from the `nq_alloc` HWRM command.
27014 uint16_t cmpl_ring;
27016 * The sequence ID is used by the driver for tracking multiple
27017 * commands. This ID is treated as opaque data by the firmware and
27018 * the value is returned in the `hwrm_resp_hdr` upon completion.
27022 * The target ID of the command:
27023 * * 0x0-0xFFF8 - The function ID
27024 * * 0xFFF8-0xFFFE - Reserved for internal processors
27027 uint16_t target_id;
27029 * A physical address pointer pointing to a host buffer that the
27030 * command's response data will be written. This can be either a host
27031 * physical address (HPA) or a guest physical address (GPA) and must
27032 * point to a physically contiguous block of memory.
27034 uint64_t resp_addr;
27035 /* Flow record index. */
27036 uint16_t flow_handle;
27037 uint8_t unused_0[6];
27038 /* This value identifies a set of CFA data structures used for a flow. */
27039 uint64_t ext_flow_handle;
27040 } __attribute__((packed));
27042 /* hwrm_cfa_flow_free_output (size:256b/32B) */
27043 struct hwrm_cfa_flow_free_output {
27044 /* The specific error status for the command. */
27045 uint16_t error_code;
27046 /* The HWRM command request type. */
27048 /* The sequence ID from the original command. */
27050 /* The length of the response data in number of bytes. */
27052 /* packet is 64 b */
27056 uint8_t unused_0[7];
27058 * This field is used in Output records to indicate that the output
27059 * is completely written to RAM. This field should be read as '1'
27060 * to indicate that the output has been completely written.
27061 * When writing a command completion or response to an internal processor,
27062 * the order of writes has to be such that this field is written last.
27065 } __attribute__((packed));
27067 /* hwrm_cfa_flow_action_data (size:960b/120B) */
27068 struct hwrm_cfa_flow_action_data {
27069 uint16_t action_flags;
27070 /* Setting of this flag indicates accept action. */
27071 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
27073 /* Setting of this flag indicates recycle action. */
27074 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
27076 /* Setting of this flag indicates drop action. */
27077 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
27079 /* Setting of this flag indicates meter action. */
27080 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
27082 /* Setting of this flag indicates tunnel action. */
27083 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
27086 * If set to 1 and flow direction is TX, it indicates decap of L2 header
27087 * and encap of tunnel header. If set to 1 and flow direction is RX, it
27088 * indicates decap of tunnel header and encap L2 header.
27090 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
27092 /* Setting of this flag indicates ttl decrement action. */
27093 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
27095 /* If set to 1, flow aging is enabled for this flow. */
27096 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
27098 /* Setting of this flag indicates encap action.. */
27099 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
27101 /* Setting of this flag indicates decap action.. */
27102 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
27105 uint16_t act_meter_id;
27108 /* vport number. */
27110 /* The NAT source/destination. */
27112 uint16_t unused_0[3];
27113 /* NAT IPv4/IPv6 address. */
27114 uint32_t nat_ip_address[4];
27115 /* Encapsulation Type. */
27116 uint8_t encap_type;
27117 /* Virtual eXtensible Local Area Network (VXLAN) */
27118 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
27119 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27120 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
27121 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
27122 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
27124 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
27125 /* Generic Network Virtualization Encapsulation (Geneve) */
27126 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
27127 /* Multi-Protocol Lable Switching (MPLS) */
27128 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
27130 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
27131 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27132 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
27133 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27134 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
27135 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27136 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
27137 /* Use fixed layer 2 ether type of 0xFFFF */
27138 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
27139 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27140 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
27141 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
27142 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
27144 /* This value is encap data for the associated encap type. */
27145 uint32_t encap_data[20];
27146 } __attribute__((packed));
27148 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
27149 struct hwrm_cfa_flow_tunnel_hdr_data {
27151 uint8_t tunnel_type;
27153 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
27155 /* Virtual eXtensible Local Area Network (VXLAN) */
27156 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
27158 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27159 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
27161 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27162 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
27165 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
27167 /* Generic Network Virtualization Encapsulation (Geneve) */
27168 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
27170 /* Multi-Protocol Lable Switching (MPLS) */
27171 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
27173 /* Stateless Transport Tunnel (STT) */
27174 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
27176 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27177 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
27179 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27180 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
27182 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27183 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
27185 /* Use fixed layer 2 ether type of 0xFFFF */
27186 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
27188 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27189 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
27191 /* Any tunneled traffic */
27192 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
27194 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
27195 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
27198 * Tunnel identifier.
27199 * Virtual Network Identifier (VNI).
27201 uint32_t tunnel_id;
27202 } __attribute__((packed));
27204 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
27205 struct hwrm_cfa_flow_l4_key_data {
27206 /* The value of source port. */
27207 uint16_t l4_src_port;
27208 /* The value of destination port. */
27209 uint16_t l4_dst_port;
27211 } __attribute__((packed));
27213 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
27214 struct hwrm_cfa_flow_l3_key_data {
27215 /* The value of ip protocol. */
27216 uint8_t ip_protocol;
27217 uint8_t unused_0[7];
27218 /* The value of destination IPv4/IPv6 address. */
27219 uint32_t ip_dst[4];
27220 /* The source IPv4/IPv6 address. */
27221 uint32_t ip_src[4];
27222 /* NAT IPv4/IPv6 address. */
27223 uint32_t nat_ip_address[4];
27224 uint32_t unused[2];
27225 } __attribute__((packed));
27227 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
27228 struct hwrm_cfa_flow_l2_key_data {
27229 /* Destination MAC address. */
27232 /* Source MAC address. */
27235 /* L2 header re-write Destination MAC address. */
27236 uint16_t l2_rewrite_dmac[3];
27238 /* L2 header re-write Source MAC address. */
27239 uint16_t l2_rewrite_smac[3];
27241 uint16_t ethertype;
27242 /* Number of VLAN tags. */
27243 uint16_t num_vlan_tags;
27245 uint16_t l2_rewrite_vlan_tpid;
27247 uint16_t l2_rewrite_vlan_tci;
27248 uint8_t unused_3[2];
27249 /* Outer VLAN TPID. */
27250 uint16_t ovlan_tpid;
27251 /* Outer VLAN TCI. */
27252 uint16_t ovlan_tci;
27253 /* Inner VLAN TPID. */
27254 uint16_t ivlan_tpid;
27255 /* Inner VLAN TCI. */
27256 uint16_t ivlan_tci;
27258 } __attribute__((packed));
27260 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
27261 struct hwrm_cfa_flow_key_data {
27262 /* Flow associated tunnel L2 header key info. */
27263 uint32_t t_l2_key_data[14];
27264 /* Flow associated tunnel L2 header mask info. */
27265 uint32_t t_l2_key_mask[14];
27266 /* Flow associated tunnel L3 header key info. */
27267 uint32_t t_l3_key_data[16];
27268 /* Flow associated tunnel L3 header mask info. */
27269 uint32_t t_l3_key_mask[16];
27270 /* Flow associated tunnel L4 header key info. */
27271 uint32_t t_l4_key_data[2];
27272 /* Flow associated tunnel L4 header mask info. */
27273 uint32_t t_l4_key_mask[2];
27274 /* Flow associated tunnel header info. */
27275 uint32_t tunnel_hdr[2];
27276 /* Flow associated L2 header key info. */
27277 uint32_t l2_key_data[14];
27278 /* Flow associated L2 header mask info. */
27279 uint32_t l2_key_mask[14];
27280 /* Flow associated L3 header key info. */
27281 uint32_t l3_key_data[16];
27282 /* Flow associated L3 header mask info. */
27283 uint32_t l3_key_mask[16];
27284 /* Flow associated L4 header key info. */
27285 uint32_t l4_key_data[2];
27286 /* Flow associated L4 header mask info. */
27287 uint32_t l4_key_mask[2];
27288 } __attribute__((packed));
27290 /**********************
27291 * hwrm_cfa_flow_info *
27292 **********************/
27295 /* hwrm_cfa_flow_info_input (size:256b/32B) */
27296 struct hwrm_cfa_flow_info_input {
27297 /* The HWRM command request type. */
27300 * The completion ring to send the completion event on. This should
27301 * be the NQ ID returned from the `nq_alloc` HWRM command.
27303 uint16_t cmpl_ring;
27305 * The sequence ID is used by the driver for tracking multiple
27306 * commands. This ID is treated as opaque data by the firmware and
27307 * the value is returned in the `hwrm_resp_hdr` upon completion.
27311 * The target ID of the command:
27312 * * 0x0-0xFFF8 - The function ID
27313 * * 0xFFF8-0xFFFE - Reserved for internal processors
27316 uint16_t target_id;
27318 * A physical address pointer pointing to a host buffer that the
27319 * command's response data will be written. This can be either a host
27320 * physical address (HPA) or a guest physical address (GPA) and must
27321 * point to a physically contiguous block of memory.
27323 uint64_t resp_addr;
27324 /* Flow record index. */
27325 uint16_t flow_handle;
27326 /* Max flow handle */
27327 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
27329 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
27330 /* CNP flow handle */
27331 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
27333 /* RoCEv1 flow handle */
27334 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
27336 /* RoCEv2 flow handle */
27337 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
27339 /* Direction rx = 1 */
27340 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
27342 uint8_t unused_0[6];
27343 /* This value identifies a set of CFA data structures used for a flow. */
27344 uint64_t ext_flow_handle;
27345 } __attribute__((packed));
27347 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
27348 struct hwrm_cfa_flow_info_output {
27349 /* The specific error status for the command. */
27350 uint16_t error_code;
27351 /* The HWRM command request type. */
27353 /* The sequence ID from the original command. */
27355 /* The length of the response data in number of bytes. */
27358 /* When set to 1, indicates the configuration is the TX flow. */
27359 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
27360 /* When set to 1, indicates the configuration is the RX flow. */
27361 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
27362 /* profile is 8 b */
27364 /* src_fid is 16 b */
27366 /* dst_fid is 16 b */
27368 /* l2_ctxt_id is 16 b */
27369 uint16_t l2_ctxt_id;
27370 /* em_info is 64 b */
27372 /* tcam_info is 64 b */
27373 uint64_t tcam_info;
27374 /* vfp_tcam_info is 64 b */
27375 uint64_t vfp_tcam_info;
27376 /* ar_id is 16 b */
27378 /* flow_handle is 16 b */
27379 uint16_t flow_handle;
27380 /* tunnel_handle is 32 b */
27381 uint32_t tunnel_handle;
27382 /* The flow aging timer for the flow, the unit is 100 milliseconds */
27383 uint16_t flow_timer;
27384 uint8_t unused_0[6];
27385 /* Flow associated L2, L3 and L4 headers info. */
27386 uint32_t flow_key_data[130];
27387 /* Flow associated action record info. */
27388 uint32_t flow_action_info[30];
27389 uint8_t unused_1[7];
27391 * This field is used in Output records to indicate that the output
27392 * is completely written to RAM. This field should be read as '1'
27393 * to indicate that the output has been completely written.
27394 * When writing a command completion or response to an internal processor,
27395 * the order of writes has to be such that this field is written last.
27398 } __attribute__((packed));
27400 /***********************
27401 * hwrm_cfa_flow_flush *
27402 ***********************/
27405 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
27406 struct hwrm_cfa_flow_flush_input {
27407 /* The HWRM command request type. */
27410 * The completion ring to send the completion event on. This should
27411 * be the NQ ID returned from the `nq_alloc` HWRM command.
27413 uint16_t cmpl_ring;
27415 * The sequence ID is used by the driver for tracking multiple
27416 * commands. This ID is treated as opaque data by the firmware and
27417 * the value is returned in the `hwrm_resp_hdr` upon completion.
27421 * The target ID of the command:
27422 * * 0x0-0xFFF8 - The function ID
27423 * * 0xFFF8-0xFFFE - Reserved for internal processors
27426 uint16_t target_id;
27428 * A physical address pointer pointing to a host buffer that the
27429 * command's response data will be written. This can be either a host
27430 * physical address (HPA) or a guest physical address (GPA) and must
27431 * point to a physically contiguous block of memory.
27433 uint64_t resp_addr;
27434 /* flags is 32 b */
27437 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
27438 * fields are valid. The flow flush operation should only flush the flows from the
27439 * flow table specified. This flag is set to 0 by older driver. For older firmware,
27440 * setting this flag has no effect.
27442 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
27445 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
27446 * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
27447 * setting this flag has no effect.
27449 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
27452 * This specifies the size of flow handle entries provided by the driver
27453 * in the flow table specified below. Only two flow handle size enums are defined.
27455 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
27456 UINT32_C(0xc0000000)
27457 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
27459 /* The flow handle is 16bit */
27460 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
27461 (UINT32_C(0x0) << 30)
27462 /* The flow handle is 64bit */
27463 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
27464 (UINT32_C(0x1) << 30)
27465 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
27466 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
27467 /* Specify page size of the flow table memory. */
27469 /* The page size is 4K */
27470 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
27471 /* The page size is 8K */
27472 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
27473 /* The page size is 64K */
27474 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
27475 /* The page size is 256K */
27476 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
27477 /* The page size is 1M */
27478 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
27479 /* The page size is 2M */
27480 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
27481 /* The page size is 4M */
27482 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
27483 /* The page size is 1G */
27484 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
27485 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
27486 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
27487 /* FLow table memory indirect levels. */
27488 uint8_t page_level;
27489 /* PBL pointer is physical start address. */
27490 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
27491 /* PBL pointer points to PTE table. */
27492 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
27493 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
27494 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
27495 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
27496 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
27497 /* number of flows in the flow table */
27498 uint16_t num_flows;
27499 /* Pointer to the PBL, or PDL depending on number of levels */
27501 } __attribute__((packed));
27503 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
27504 struct hwrm_cfa_flow_flush_output {
27505 /* The specific error status for the command. */
27506 uint16_t error_code;
27507 /* The HWRM command request type. */
27509 /* The sequence ID from the original command. */
27511 /* The length of the response data in number of bytes. */
27513 uint8_t unused_0[7];
27515 * This field is used in Output records to indicate that the output
27516 * is completely written to RAM. This field should be read as '1'
27517 * to indicate that the output has been completely written.
27518 * When writing a command completion or response to an internal processor,
27519 * the order of writes has to be such that this field is written last.
27522 } __attribute__((packed));
27524 /***********************
27525 * hwrm_cfa_flow_stats *
27526 ***********************/
27529 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
27530 struct hwrm_cfa_flow_stats_input {
27531 /* The HWRM command request type. */
27534 * The completion ring to send the completion event on. This should
27535 * be the NQ ID returned from the `nq_alloc` HWRM command.
27537 uint16_t cmpl_ring;
27539 * The sequence ID is used by the driver for tracking multiple
27540 * commands. This ID is treated as opaque data by the firmware and
27541 * the value is returned in the `hwrm_resp_hdr` upon completion.
27545 * The target ID of the command:
27546 * * 0x0-0xFFF8 - The function ID
27547 * * 0xFFF8-0xFFFE - Reserved for internal processors
27550 uint16_t target_id;
27552 * A physical address pointer pointing to a host buffer that the
27553 * command's response data will be written. This can be either a host
27554 * physical address (HPA) or a guest physical address (GPA) and must
27555 * point to a physically contiguous block of memory.
27557 uint64_t resp_addr;
27559 uint16_t num_flows;
27561 uint16_t flow_handle_0;
27563 uint16_t flow_handle_1;
27565 uint16_t flow_handle_2;
27567 uint16_t flow_handle_3;
27569 uint16_t flow_handle_4;
27571 uint16_t flow_handle_5;
27573 uint16_t flow_handle_6;
27575 uint16_t flow_handle_7;
27577 uint16_t flow_handle_8;
27579 uint16_t flow_handle_9;
27580 uint8_t unused_0[2];
27581 /* Flow ID of a flow. */
27582 uint32_t flow_id_0;
27583 /* Flow ID of a flow. */
27584 uint32_t flow_id_1;
27585 /* Flow ID of a flow. */
27586 uint32_t flow_id_2;
27587 /* Flow ID of a flow. */
27588 uint32_t flow_id_3;
27589 /* Flow ID of a flow. */
27590 uint32_t flow_id_4;
27591 /* Flow ID of a flow. */
27592 uint32_t flow_id_5;
27593 /* Flow ID of a flow. */
27594 uint32_t flow_id_6;
27595 /* Flow ID of a flow. */
27596 uint32_t flow_id_7;
27597 /* Flow ID of a flow. */
27598 uint32_t flow_id_8;
27599 /* Flow ID of a flow. */
27600 uint32_t flow_id_9;
27601 } __attribute__((packed));
27603 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
27604 struct hwrm_cfa_flow_stats_output {
27605 /* The specific error status for the command. */
27606 uint16_t error_code;
27607 /* The HWRM command request type. */
27609 /* The sequence ID from the original command. */
27611 /* The length of the response data in number of bytes. */
27613 /* packet_0 is 64 b */
27615 /* packet_1 is 64 b */
27617 /* packet_2 is 64 b */
27619 /* packet_3 is 64 b */
27621 /* packet_4 is 64 b */
27623 /* packet_5 is 64 b */
27625 /* packet_6 is 64 b */
27627 /* packet_7 is 64 b */
27629 /* packet_8 is 64 b */
27631 /* packet_9 is 64 b */
27633 /* byte_0 is 64 b */
27635 /* byte_1 is 64 b */
27637 /* byte_2 is 64 b */
27639 /* byte_3 is 64 b */
27641 /* byte_4 is 64 b */
27643 /* byte_5 is 64 b */
27645 /* byte_6 is 64 b */
27647 /* byte_7 is 64 b */
27649 /* byte_8 is 64 b */
27651 /* byte_9 is 64 b */
27653 uint8_t unused_0[7];
27655 * This field is used in Output records to indicate that the output
27656 * is completely written to RAM. This field should be read as '1'
27657 * to indicate that the output has been completely written.
27658 * When writing a command completion or response to an internal processor,
27659 * the order of writes has to be such that this field is written last.
27662 } __attribute__((packed));
27664 /***********************************
27665 * hwrm_cfa_flow_aging_timer_reset *
27666 ***********************************/
27669 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
27670 struct hwrm_cfa_flow_aging_timer_reset_input {
27671 /* The HWRM command request type. */
27674 * The completion ring to send the completion event on. This should
27675 * be the NQ ID returned from the `nq_alloc` HWRM command.
27677 uint16_t cmpl_ring;
27679 * The sequence ID is used by the driver for tracking multiple
27680 * commands. This ID is treated as opaque data by the firmware and
27681 * the value is returned in the `hwrm_resp_hdr` upon completion.
27685 * The target ID of the command:
27686 * * 0x0-0xFFF8 - The function ID
27687 * * 0xFFF8-0xFFFE - Reserved for internal processors
27690 uint16_t target_id;
27692 * A physical address pointer pointing to a host buffer that the
27693 * command's response data will be written. This can be either a host
27694 * physical address (HPA) or a guest physical address (GPA) and must
27695 * point to a physically contiguous block of memory.
27697 uint64_t resp_addr;
27698 /* Flow record index. */
27699 uint16_t flow_handle;
27700 uint8_t unused_0[2];
27702 * New flow timer value for the flow specified in the ext_flow_handle.
27703 * The flow timer unit is 100ms.
27705 uint32_t flow_timer;
27706 /* This value identifies a set of CFA data structures used for a flow. */
27707 uint64_t ext_flow_handle;
27708 } __attribute__((packed));
27710 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
27711 struct hwrm_cfa_flow_aging_timer_reset_output {
27712 /* The specific error status for the command. */
27713 uint16_t error_code;
27714 /* The HWRM command request type. */
27716 /* The sequence ID from the original command. */
27718 /* The length of the response data in number of bytes. */
27720 uint8_t unused_0[7];
27722 * This field is used in Output records to indicate that the output
27723 * is completely written to RAM. This field should be read as '1'
27724 * to indicate that the output has been completely written.
27725 * When writing a command completion or response to an internal processor,
27726 * the order of writes has to be such that this field is written last.
27729 } __attribute__((packed));
27731 /***************************
27732 * hwrm_cfa_flow_aging_cfg *
27733 ***************************/
27736 /* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
27737 struct hwrm_cfa_flow_aging_cfg_input {
27738 /* The HWRM command request type. */
27741 * The completion ring to send the completion event on. This should
27742 * be the NQ ID returned from the `nq_alloc` HWRM command.
27744 uint16_t cmpl_ring;
27746 * The sequence ID is used by the driver for tracking multiple
27747 * commands. This ID is treated as opaque data by the firmware and
27748 * the value is returned in the `hwrm_resp_hdr` upon completion.
27752 * The target ID of the command:
27753 * * 0x0-0xFFF8 - The function ID
27754 * * 0xFFF8-0xFFFE - Reserved for internal processors
27757 uint16_t target_id;
27759 * A physical address pointer pointing to a host buffer that the
27760 * command's response data will be written. This can be either a host
27761 * physical address (HPA) or a guest physical address (GPA) and must
27762 * point to a physically contiguous block of memory.
27764 uint64_t resp_addr;
27765 /* The bit field to enable per flow aging configuration. */
27767 /* This bit must be '1' for the tcp flow timer field to be configured */
27768 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
27770 /* This bit must be '1' for the tcp finish timer field to be configured */
27771 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
27773 /* This bit must be '1' for the udp flow timer field to be configured */
27774 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
27776 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
27778 /* Enumeration denoting the RX, TX type of the resource. */
27779 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27781 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27783 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27784 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
27785 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
27787 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
27788 uint32_t tcp_flow_timer;
27789 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
27790 uint32_t tcp_fin_timer;
27791 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
27792 uint32_t udp_flow_timer;
27793 } __attribute__((packed));
27795 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
27796 struct hwrm_cfa_flow_aging_cfg_output {
27797 /* The specific error status for the command. */
27798 uint16_t error_code;
27799 /* The HWRM command request type. */
27801 /* The sequence ID from the original command. */
27803 /* The length of the response data in number of bytes. */
27805 uint8_t unused_0[7];
27807 * This field is used in Output records to indicate that the output
27808 * is completely written to RAM. This field should be read as '1'
27809 * to indicate that the output has been completely written.
27810 * When writing a command completion or response to an internal processor,
27811 * the order of writes has to be such that this field is written last.
27814 } __attribute__((packed));
27816 /****************************
27817 * hwrm_cfa_flow_aging_qcfg *
27818 ****************************/
27821 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
27822 struct hwrm_cfa_flow_aging_qcfg_input {
27823 /* The HWRM command request type. */
27826 * The completion ring to send the completion event on. This should
27827 * be the NQ ID returned from the `nq_alloc` HWRM command.
27829 uint16_t cmpl_ring;
27831 * The sequence ID is used by the driver for tracking multiple
27832 * commands. This ID is treated as opaque data by the firmware and
27833 * the value is returned in the `hwrm_resp_hdr` upon completion.
27837 * The target ID of the command:
27838 * * 0x0-0xFFF8 - The function ID
27839 * * 0xFFF8-0xFFFE - Reserved for internal processors
27842 uint16_t target_id;
27844 * A physical address pointer pointing to a host buffer that the
27845 * command's response data will be written. This can be either a host
27846 * physical address (HPA) or a guest physical address (GPA) and must
27847 * point to a physically contiguous block of memory.
27849 uint64_t resp_addr;
27850 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
27852 /* Enumeration denoting the RX, TX type of the resource. */
27853 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
27855 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27857 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27858 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
27859 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
27860 uint8_t unused_0[7];
27861 } __attribute__((packed));
27863 /* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
27864 struct hwrm_cfa_flow_aging_qcfg_output {
27865 /* The specific error status for the command. */
27866 uint16_t error_code;
27867 /* The HWRM command request type. */
27869 /* The sequence ID from the original command. */
27871 /* The length of the response data in number of bytes. */
27873 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
27874 uint32_t tcp_flow_timer;
27875 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
27876 uint32_t tcp_fin_timer;
27877 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
27878 uint32_t udp_flow_timer;
27879 uint8_t unused_0[3];
27881 * This field is used in Output records to indicate that the output
27882 * is completely written to RAM. This field should be read as '1'
27883 * to indicate that the output has been completely written.
27884 * When writing a command completion or response to an internal processor,
27885 * the order of writes has to be such that this field is written last.
27888 } __attribute__((packed));
27890 /*****************************
27891 * hwrm_cfa_flow_aging_qcaps *
27892 *****************************/
27895 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
27896 struct hwrm_cfa_flow_aging_qcaps_input {
27897 /* The HWRM command request type. */
27900 * The completion ring to send the completion event on. This should
27901 * be the NQ ID returned from the `nq_alloc` HWRM command.
27903 uint16_t cmpl_ring;
27905 * The sequence ID is used by the driver for tracking multiple
27906 * commands. This ID is treated as opaque data by the firmware and
27907 * the value is returned in the `hwrm_resp_hdr` upon completion.
27911 * The target ID of the command:
27912 * * 0x0-0xFFF8 - The function ID
27913 * * 0xFFF8-0xFFFE - Reserved for internal processors
27916 uint16_t target_id;
27918 * A physical address pointer pointing to a host buffer that the
27919 * command's response data will be written. This can be either a host
27920 * physical address (HPA) or a guest physical address (GPA) and must
27921 * point to a physically contiguous block of memory.
27923 uint64_t resp_addr;
27924 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
27926 /* Enumeration denoting the RX, TX type of the resource. */
27927 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
27929 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27931 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27932 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
27933 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
27934 uint8_t unused_0[7];
27935 } __attribute__((packed));
27937 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
27938 struct hwrm_cfa_flow_aging_qcaps_output {
27939 /* The specific error status for the command. */
27940 uint16_t error_code;
27941 /* The HWRM command request type. */
27943 /* The sequence ID from the original command. */
27945 /* The length of the response data in number of bytes. */
27947 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
27948 uint32_t max_tcp_flow_timer;
27949 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
27950 uint32_t max_tcp_fin_timer;
27951 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
27952 uint32_t max_udp_flow_timer;
27953 /* The maximum aging flows that HW can support. */
27954 uint32_t max_aging_flows;
27955 uint8_t unused_0[7];
27957 * This field is used in Output records to indicate that the output
27958 * is completely written to RAM. This field should be read as '1'
27959 * to indicate that the output has been completely written.
27960 * When writing a command completion or response to an internal processor,
27961 * the order of writes has to be such that this field is written last.
27964 } __attribute__((packed));
27966 /**********************************
27967 * hwrm_cfa_tcp_flag_process_qcfg *
27968 **********************************/
27971 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
27972 struct hwrm_cfa_tcp_flag_process_qcfg_input {
27973 /* The HWRM command request type. */
27976 * The completion ring to send the completion event on. This should
27977 * be the NQ ID returned from the `nq_alloc` HWRM command.
27979 uint16_t cmpl_ring;
27981 * The sequence ID is used by the driver for tracking multiple
27982 * commands. This ID is treated as opaque data by the firmware and
27983 * the value is returned in the `hwrm_resp_hdr` upon completion.
27987 * The target ID of the command:
27988 * * 0x0-0xFFF8 - The function ID
27989 * * 0xFFF8-0xFFFE - Reserved for internal processors
27992 uint16_t target_id;
27994 * A physical address pointer pointing to a host buffer that the
27995 * command's response data will be written. This can be either a host
27996 * physical address (HPA) or a guest physical address (GPA) and must
27997 * point to a physically contiguous block of memory.
27999 uint64_t resp_addr;
28000 } __attribute__((packed));
28002 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
28003 struct hwrm_cfa_tcp_flag_process_qcfg_output {
28004 /* The specific error status for the command. */
28005 uint16_t error_code;
28006 /* The HWRM command request type. */
28008 /* The sequence ID from the original command. */
28010 /* The length of the response data in number of bytes. */
28012 /* The port 0 RX mirror action record ID. */
28013 uint16_t rx_ar_id_port0;
28014 /* The port 1 RX mirror action record ID. */
28015 uint16_t rx_ar_id_port1;
28016 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
28017 uint16_t tx_ar_id_port0;
28018 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
28019 uint16_t tx_ar_id_port1;
28020 uint8_t unused_0[7];
28022 * This field is used in Output records to indicate that the output
28023 * is completely written to RAM. This field should be read as '1'
28024 * to indicate that the output has been completely written.
28025 * When writing a command completion or response to an internal processor,
28026 * the order of writes has to be such that this field is written last.
28029 } __attribute__((packed));
28031 /**********************
28032 * hwrm_cfa_pair_info *
28033 **********************/
28036 /* hwrm_cfa_pair_info_input (size:448b/56B) */
28037 struct hwrm_cfa_pair_info_input {
28038 /* The HWRM command request type. */
28041 * The completion ring to send the completion event on. This should
28042 * be the NQ ID returned from the `nq_alloc` HWRM command.
28044 uint16_t cmpl_ring;
28046 * The sequence ID is used by the driver for tracking multiple
28047 * commands. This ID is treated as opaque data by the firmware and
28048 * the value is returned in the `hwrm_resp_hdr` upon completion.
28052 * The target ID of the command:
28053 * * 0x0-0xFFF8 - The function ID
28054 * * 0xFFF8-0xFFFE - Reserved for internal processors
28057 uint16_t target_id;
28059 * A physical address pointer pointing to a host buffer that the
28060 * command's response data will be written. This can be either a host
28061 * physical address (HPA) or a guest physical address (GPA) and must
28062 * point to a physically contiguous block of memory.
28064 uint64_t resp_addr;
28066 /* If this flag is set, lookup by name else lookup by index. */
28067 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
28068 /* If this flag is set, lookup by PF id and VF id. */
28069 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
28070 /* Pair table index. */
28071 uint16_t pair_index;
28072 /* Pair pf index. */
28074 /* Pair vf index. */
28076 /* Pair name (32 byte string). */
28077 char pair_name[32];
28078 } __attribute__((packed));
28080 /* hwrm_cfa_pair_info_output (size:576b/72B) */
28081 struct hwrm_cfa_pair_info_output {
28082 /* The specific error status for the command. */
28083 uint16_t error_code;
28084 /* The HWRM command request type. */
28086 /* The sequence ID from the original command. */
28088 /* The length of the response data in number of bytes. */
28090 /* Pair table index. */
28091 uint16_t next_pair_index;
28092 /* Pair member a's fid. */
28094 /* Logical host number. */
28095 uint8_t host_a_index;
28096 /* Logical PF number. */
28097 uint8_t pf_a_index;
28098 /* Pair member a's Linux logical VF number. */
28099 uint16_t vf_a_index;
28101 uint16_t rx_cfa_code_a;
28102 /* Tx CFA action. */
28103 uint16_t tx_cfa_action_a;
28104 /* Pair member b's fid. */
28106 /* Logical host number. */
28107 uint8_t host_b_index;
28108 /* Logical PF number. */
28109 uint8_t pf_b_index;
28110 /* Pair member a's Linux logical VF number. */
28111 uint16_t vf_b_index;
28113 uint16_t rx_cfa_code_b;
28114 /* Tx CFA action. */
28115 uint16_t tx_cfa_action_b;
28116 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
28118 /* Pair between VF on local host with PF or VF on specified host. */
28119 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
28120 /* Pair between REP on local host with PF or VF on specified host. */
28121 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
28122 /* Pair between REP on local host with REP on specified host. */
28123 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
28124 /* Pair for the proxy interface. */
28125 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
28126 /* Pair for the PF interface. */
28127 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
28128 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
28129 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
28131 uint8_t pair_state;
28132 /* Pair has been allocated */
28133 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
28134 /* Both pair members are active */
28135 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
28136 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
28137 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
28138 /* Pair name (32 byte string). */
28139 char pair_name[32];
28140 uint8_t unused_0[7];
28142 * This field is used in Output records to indicate that the output
28143 * is completely written to RAM. This field should be read as '1'
28144 * to indicate that the output has been completely written.
28145 * When writing a command completion or response to an internal processor,
28146 * the order of writes has to be such that this field is written last.
28149 } __attribute__((packed));
28151 /***************************************
28152 * hwrm_cfa_redirect_query_tunnel_type *
28153 ***************************************/
28156 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
28157 struct hwrm_cfa_redirect_query_tunnel_type_input {
28158 /* The HWRM command request type. */
28161 * The completion ring to send the completion event on. This should
28162 * be the NQ ID returned from the `nq_alloc` HWRM command.
28164 uint16_t cmpl_ring;
28166 * The sequence ID is used by the driver for tracking multiple
28167 * commands. This ID is treated as opaque data by the firmware and
28168 * the value is returned in the `hwrm_resp_hdr` upon completion.
28172 * The target ID of the command:
28173 * * 0x0-0xFFF8 - The function ID
28174 * * 0xFFF8-0xFFFE - Reserved for internal processors
28177 uint16_t target_id;
28179 * A physical address pointer pointing to a host buffer that the
28180 * command's response data will be written. This can be either a host
28181 * physical address (HPA) or a guest physical address (GPA) and must
28182 * point to a physically contiguous block of memory.
28184 uint64_t resp_addr;
28185 /* The source function id. */
28187 uint8_t unused_0[6];
28188 } __attribute__((packed));
28190 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
28191 struct hwrm_cfa_redirect_query_tunnel_type_output {
28192 /* The specific error status for the command. */
28193 uint16_t error_code;
28194 /* The HWRM command request type. */
28196 /* The sequence ID from the original command. */
28198 /* The length of the response data in number of bytes. */
28201 uint32_t tunnel_mask;
28203 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
28205 /* Virtual eXtensible Local Area Network (VXLAN) */
28206 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
28208 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
28209 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
28211 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
28212 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
28215 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
28217 /* Generic Network Virtualization Encapsulation (Geneve) */
28218 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
28220 /* Multi-Protocol Lable Switching (MPLS) */
28221 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
28223 /* Stateless Transport Tunnel (STT) */
28224 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
28226 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
28227 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
28229 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
28230 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
28232 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
28233 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
28235 /* Any tunneled traffic */
28236 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
28238 /* Use fixed layer 2 ether type of 0xFFFF */
28239 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
28241 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
28242 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
28244 uint8_t unused_0[3];
28246 * This field is used in Output records to indicate that the output
28247 * is completely written to RAM. This field should be read as '1'
28248 * to indicate that the output has been completely written.
28249 * When writing a command completion or response to an internal processor,
28250 * the order of writes has to be such that this field is written last.
28253 } __attribute__((packed));
28255 /*************************
28256 * hwrm_cfa_ctx_mem_rgtr *
28257 *************************/
28260 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
28261 struct hwrm_cfa_ctx_mem_rgtr_input {
28262 /* The HWRM command request type. */
28265 * The completion ring to send the completion event on. This should
28266 * be the NQ ID returned from the `nq_alloc` HWRM command.
28268 uint16_t cmpl_ring;
28270 * The sequence ID is used by the driver for tracking multiple
28271 * commands. This ID is treated as opaque data by the firmware and
28272 * the value is returned in the `hwrm_resp_hdr` upon completion.
28276 * The target ID of the command:
28277 * * 0x0-0xFFF8 - The function ID
28278 * * 0xFFF8-0xFFFE - Reserved for internal processors
28281 uint16_t target_id;
28283 * A physical address pointer pointing to a host buffer that the
28284 * command's response data will be written. This can be either a host
28285 * physical address (HPA) or a guest physical address (GPA) and must
28286 * point to a physically contiguous block of memory.
28288 uint64_t resp_addr;
28290 /* Counter PBL indirect levels. */
28291 uint8_t page_level;
28292 /* PBL pointer is physical start address. */
28293 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
28294 /* PBL pointer points to PTE table. */
28295 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
28296 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
28297 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
28298 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
28299 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
28302 /* 4KB page size. */
28303 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
28304 /* 8KB page size. */
28305 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
28306 /* 64KB page size. */
28307 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
28308 /* 256KB page size. */
28309 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
28310 /* 1MB page size. */
28311 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
28312 /* 2MB page size. */
28313 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
28314 /* 4MB page size. */
28315 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
28316 /* 1GB page size. */
28317 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
28318 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
28319 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
28321 /* Pointer to the PBL, or PDL depending on number of levels */
28323 } __attribute__((packed));
28325 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
28326 struct hwrm_cfa_ctx_mem_rgtr_output {
28327 /* The specific error status for the command. */
28328 uint16_t error_code;
28329 /* The HWRM command request type. */
28331 /* The sequence ID from the original command. */
28333 /* The length of the response data in number of bytes. */
28336 * Id/Handle to the recently register context memory. This handle is passed
28337 * to the CFA feature.
28340 uint8_t unused_0[5];
28342 * This field is used in Output records to indicate that the output
28343 * is completely written to RAM. This field should be read as '1'
28344 * to indicate that the output has been completely written.
28345 * When writing a command completion or response to an internal processor,
28346 * the order of writes has to be such that this field is written last.
28349 } __attribute__((packed));
28351 /***************************
28352 * hwrm_cfa_ctx_mem_unrgtr *
28353 ***************************/
28356 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
28357 struct hwrm_cfa_ctx_mem_unrgtr_input {
28358 /* The HWRM command request type. */
28361 * The completion ring to send the completion event on. This should
28362 * be the NQ ID returned from the `nq_alloc` HWRM command.
28364 uint16_t cmpl_ring;
28366 * The sequence ID is used by the driver for tracking multiple
28367 * commands. This ID is treated as opaque data by the firmware and
28368 * the value is returned in the `hwrm_resp_hdr` upon completion.
28372 * The target ID of the command:
28373 * * 0x0-0xFFF8 - The function ID
28374 * * 0xFFF8-0xFFFE - Reserved for internal processors
28377 uint16_t target_id;
28379 * A physical address pointer pointing to a host buffer that the
28380 * command's response data will be written. This can be either a host
28381 * physical address (HPA) or a guest physical address (GPA) and must
28382 * point to a physically contiguous block of memory.
28384 uint64_t resp_addr;
28386 * Id/Handle to the recently register context memory. This handle is passed
28387 * to the CFA feature.
28390 uint8_t unused_0[6];
28391 } __attribute__((packed));
28393 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
28394 struct hwrm_cfa_ctx_mem_unrgtr_output {
28395 /* The specific error status for the command. */
28396 uint16_t error_code;
28397 /* The HWRM command request type. */
28399 /* The sequence ID from the original command. */
28401 /* The length of the response data in number of bytes. */
28403 uint8_t unused_0[7];
28405 * This field is used in Output records to indicate that the output
28406 * is completely written to RAM. This field should be read as '1'
28407 * to indicate that the output has been completely written.
28408 * When writing a command completion or response to an internal processor,
28409 * the order of writes has to be such that this field is written last.
28412 } __attribute__((packed));
28414 /*************************
28415 * hwrm_cfa_ctx_mem_qctx *
28416 *************************/
28419 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
28420 struct hwrm_cfa_ctx_mem_qctx_input {
28421 /* The HWRM command request type. */
28424 * The completion ring to send the completion event on. This should
28425 * be the NQ ID returned from the `nq_alloc` HWRM command.
28427 uint16_t cmpl_ring;
28429 * The sequence ID is used by the driver for tracking multiple
28430 * commands. This ID is treated as opaque data by the firmware and
28431 * the value is returned in the `hwrm_resp_hdr` upon completion.
28435 * The target ID of the command:
28436 * * 0x0-0xFFF8 - The function ID
28437 * * 0xFFF8-0xFFFE - Reserved for internal processors
28440 uint16_t target_id;
28442 * A physical address pointer pointing to a host buffer that the
28443 * command's response data will be written. This can be either a host
28444 * physical address (HPA) or a guest physical address (GPA) and must
28445 * point to a physically contiguous block of memory.
28447 uint64_t resp_addr;
28449 * Id/Handle to the recently register context memory. This handle is passed
28450 * to the CFA feature.
28453 uint8_t unused_0[6];
28454 } __attribute__((packed));
28456 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
28457 struct hwrm_cfa_ctx_mem_qctx_output {
28458 /* The specific error status for the command. */
28459 uint16_t error_code;
28460 /* The HWRM command request type. */
28462 /* The sequence ID from the original command. */
28464 /* The length of the response data in number of bytes. */
28467 /* Counter PBL indirect levels. */
28468 uint8_t page_level;
28469 /* PBL pointer is physical start address. */
28470 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
28471 /* PBL pointer points to PTE table. */
28472 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
28473 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
28474 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
28475 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
28476 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
28479 /* 4KB page size. */
28480 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
28481 /* 8KB page size. */
28482 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
28483 /* 64KB page size. */
28484 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
28485 /* 256KB page size. */
28486 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
28487 /* 1MB page size. */
28488 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
28489 /* 2MB page size. */
28490 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
28491 /* 4MB page size. */
28492 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
28493 /* 1GB page size. */
28494 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
28495 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
28496 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
28497 uint8_t unused_0[4];
28498 /* Pointer to the PBL, or PDL depending on number of levels */
28500 uint8_t unused_1[7];
28502 * This field is used in Output records to indicate that the output
28503 * is completely written to RAM. This field should be read as '1'
28504 * to indicate that the output has been completely written.
28505 * When writing a command completion or response to an internal processor,
28506 * the order of writes has to be such that this field is written last.
28509 } __attribute__((packed));
28511 /**************************
28512 * hwrm_cfa_ctx_mem_qcaps *
28513 **************************/
28516 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
28517 struct hwrm_cfa_ctx_mem_qcaps_input {
28518 /* The HWRM command request type. */
28521 * The completion ring to send the completion event on. This should
28522 * be the NQ ID returned from the `nq_alloc` HWRM command.
28524 uint16_t cmpl_ring;
28526 * The sequence ID is used by the driver for tracking multiple
28527 * commands. This ID is treated as opaque data by the firmware and
28528 * the value is returned in the `hwrm_resp_hdr` upon completion.
28532 * The target ID of the command:
28533 * * 0x0-0xFFF8 - The function ID
28534 * * 0xFFF8-0xFFFE - Reserved for internal processors
28537 uint16_t target_id;
28539 * A physical address pointer pointing to a host buffer that the
28540 * command's response data will be written. This can be either a host
28541 * physical address (HPA) or a guest physical address (GPA) and must
28542 * point to a physically contiguous block of memory.
28544 uint64_t resp_addr;
28545 } __attribute__((packed));
28547 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
28548 struct hwrm_cfa_ctx_mem_qcaps_output {
28549 /* The specific error status for the command. */
28550 uint16_t error_code;
28551 /* The HWRM command request type. */
28553 /* The sequence ID from the original command. */
28555 /* The length of the response data in number of bytes. */
28557 /* Indicates the maximum number of context memory which can be registered. */
28558 uint16_t max_entries;
28559 uint8_t unused_0[6];
28560 } __attribute__((packed));
28562 /**********************
28563 * hwrm_cfa_eem_qcaps *
28564 **********************/
28567 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
28568 struct hwrm_cfa_eem_qcaps_input {
28569 /* The HWRM command request type. */
28572 * The completion ring to send the completion event on. This should
28573 * be the NQ ID returned from the `nq_alloc` HWRM command.
28575 uint16_t cmpl_ring;
28577 * The sequence ID is used by the driver for tracking multiple
28578 * commands. This ID is treated as opaque data by the firmware and
28579 * the value is returned in the `hwrm_resp_hdr` upon completion.
28583 * The target ID of the command:
28584 * * 0x0-0xFFF8 - The function ID
28585 * * 0xFFF8-0xFFFE - Reserved for internal processors
28588 uint16_t target_id;
28590 * A physical address pointer pointing to a host buffer that the
28591 * command's response data will be written. This can be either a host
28592 * physical address (HPA) or a guest physical address (GPA) and must
28593 * point to a physically contiguous block of memory.
28595 uint64_t resp_addr;
28598 * When set to 1, indicates the configuration will apply to TX flows
28599 * which are to be offloaded.
28600 * Note if this bit is set then the path_rx bit can't be set.
28602 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
28605 * When set to 1, indicates the configuration will apply to RX flows
28606 * which are to be offloaded.
28607 * Note if this bit is set then the path_tx bit can't be set.
28609 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
28611 /* When set to 1, all offloaded flows will be sent to EEM. */
28612 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
28615 } __attribute__((packed));
28617 /* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
28618 struct hwrm_cfa_eem_qcaps_output {
28619 /* The specific error status for the command. */
28620 uint16_t error_code;
28621 /* The HWRM command request type. */
28623 /* The sequence ID from the original command. */
28625 /* The length of the response data in number of bytes. */
28629 * When set to 1, indicates the configuration will apply to TX flows
28630 * which are to be offloaded.
28631 * Note if this bit is set then the path_rx bit can't be set.
28633 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
28635 * When set to 1, indicates the configuration will apply to RX flows
28636 * which are to be offloaded.
28637 * Note if this bit is set then the path_tx bit can't be set.
28639 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
28641 uint32_t supported;
28643 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
28644 * If set to 0 EEM KEY0 table is not supported.
28646 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
28649 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
28650 * If set to 0 EEM KEY1 table is not supported.
28652 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
28655 * If set to 1, then EEM External Record table is supported.
28656 * If set to 0 EEM External Record table is not supported.
28657 * (This table includes action record, EFC pointers, encap pointers)
28659 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
28662 * If set to 1, then EEM External Flow Counters table is supported.
28663 * If set to 0 EEM External Flow Counters table is not supported.
28665 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
28668 * The maximum number of entries supported by EEM. When configuring the host memory
28669 * the number of numbers of entries that can supported are -
28670 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
28671 * Any value that are not these values, the FW will round down to the closest support
28672 * number of entries.
28674 uint32_t max_entries_supported;
28675 /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
28676 uint16_t key_entry_size;
28677 /* The entry size in bytes of each entry in the RECORD EEM tables. */
28678 uint16_t record_entry_size;
28679 /* The entry size in bytes of each entry in the EFC EEM tables. */
28680 uint16_t efc_entry_size;
28683 * This field is used in Output records to indicate that the output
28684 * is completely written to RAM. This field should be read as '1'
28685 * to indicate that the output has been completely written.
28686 * When writing a command completion or response to an internal processor,
28687 * the order of writes has to be such that this field is written last.
28690 } __attribute__((packed));
28692 /********************
28693 * hwrm_cfa_eem_cfg *
28694 ********************/
28697 /* hwrm_cfa_eem_cfg_input (size:320b/40B) */
28698 struct hwrm_cfa_eem_cfg_input {
28699 /* The HWRM command request type. */
28702 * The completion ring to send the completion event on. This should
28703 * be the NQ ID returned from the `nq_alloc` HWRM command.
28705 uint16_t cmpl_ring;
28707 * The sequence ID is used by the driver for tracking multiple
28708 * commands. This ID is treated as opaque data by the firmware and
28709 * the value is returned in the `hwrm_resp_hdr` upon completion.
28713 * The target ID of the command:
28714 * * 0x0-0xFFF8 - The function ID
28715 * * 0xFFF8-0xFFFE - Reserved for internal processors
28718 uint16_t target_id;
28720 * A physical address pointer pointing to a host buffer that the
28721 * command's response data will be written. This can be either a host
28722 * physical address (HPA) or a guest physical address (GPA) and must
28723 * point to a physically contiguous block of memory.
28725 uint64_t resp_addr;
28728 * When set to 1, indicates the configuration will apply to TX flows
28729 * which are to be offloaded.
28730 * Note if this bit is set then the path_rx bit can't be set.
28732 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
28735 * When set to 1, indicates the configuration will apply to RX flows
28736 * which are to be offloaded.
28737 * Note if this bit is set then the path_tx bit can't be set.
28739 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
28741 /* When set to 1, all offloaded flows will be sent to EEM. */
28742 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
28746 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
28747 * RECORD, EFC all have the same number of entries and all tables will be configured
28748 * using this value. Current minimum value is 32k. Current maximum value is 128M.
28750 uint32_t num_entries;
28752 /* Configured EEM with the given context if for KEY0 table. */
28753 uint16_t key0_ctx_id;
28754 /* Configured EEM with the given context if for KEY1 table. */
28755 uint16_t key1_ctx_id;
28756 /* Configured EEM with the given context if for RECORD table. */
28757 uint16_t record_ctx_id;
28758 /* Configured EEM with the given context if for EFC table. */
28759 uint16_t efc_ctx_id;
28760 } __attribute__((packed));
28762 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
28763 struct hwrm_cfa_eem_cfg_output {
28764 /* The specific error status for the command. */
28765 uint16_t error_code;
28766 /* The HWRM command request type. */
28768 /* The sequence ID from the original command. */
28770 /* The length of the response data in number of bytes. */
28772 uint8_t unused_0[7];
28774 * This field is used in Output records to indicate that the output
28775 * is completely written to RAM. This field should be read as '1'
28776 * to indicate that the output has been completely written.
28777 * When writing a command completion or response to an internal processor,
28778 * the order of writes has to be such that this field is written last.
28781 } __attribute__((packed));
28783 /*********************
28784 * hwrm_cfa_eem_qcfg *
28785 *********************/
28788 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
28789 struct hwrm_cfa_eem_qcfg_input {
28790 /* The HWRM command request type. */
28793 * The completion ring to send the completion event on. This should
28794 * be the NQ ID returned from the `nq_alloc` HWRM command.
28796 uint16_t cmpl_ring;
28798 * The sequence ID is used by the driver for tracking multiple
28799 * commands. This ID is treated as opaque data by the firmware and
28800 * the value is returned in the `hwrm_resp_hdr` upon completion.
28804 * The target ID of the command:
28805 * * 0x0-0xFFF8 - The function ID
28806 * * 0xFFF8-0xFFFE - Reserved for internal processors
28809 uint16_t target_id;
28811 * A physical address pointer pointing to a host buffer that the
28812 * command's response data will be written. This can be either a host
28813 * physical address (HPA) or a guest physical address (GPA) and must
28814 * point to a physically contiguous block of memory.
28816 uint64_t resp_addr;
28818 /* When set to 1, indicates the configuration is the TX flow. */
28819 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
28820 /* When set to 1, indicates the configuration is the RX flow. */
28821 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
28823 } __attribute__((packed));
28825 /* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
28826 struct hwrm_cfa_eem_qcfg_output {
28827 /* The specific error status for the command. */
28828 uint16_t error_code;
28829 /* The HWRM command request type. */
28831 /* The sequence ID from the original command. */
28833 /* The length of the response data in number of bytes. */
28836 /* When set to 1, indicates the configuration is the TX flow. */
28837 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
28839 /* When set to 1, indicates the configuration is the RX flow. */
28840 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
28842 /* When set to 1, all offloaded flows will be sent to EEM. */
28843 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
28845 /* The number of entries the FW has configured for EEM. */
28846 uint32_t num_entries;
28847 uint8_t unused_0[7];
28849 * This field is used in Output records to indicate that the output
28850 * is completely written to RAM. This field should be read as '1'
28851 * to indicate that the output has been completely written.
28852 * When writing a command completion or response to an internal processor,
28853 * the order of writes has to be such that this field is written last.
28856 } __attribute__((packed));
28858 /*******************
28859 * hwrm_cfa_eem_op *
28860 *******************/
28863 /* hwrm_cfa_eem_op_input (size:192b/24B) */
28864 struct hwrm_cfa_eem_op_input {
28865 /* The HWRM command request type. */
28868 * The completion ring to send the completion event on. This should
28869 * be the NQ ID returned from the `nq_alloc` HWRM command.
28871 uint16_t cmpl_ring;
28873 * The sequence ID is used by the driver for tracking multiple
28874 * commands. This ID is treated as opaque data by the firmware and
28875 * the value is returned in the `hwrm_resp_hdr` upon completion.
28879 * The target ID of the command:
28880 * * 0x0-0xFFF8 - The function ID
28881 * * 0xFFF8-0xFFFE - Reserved for internal processors
28884 uint16_t target_id;
28886 * A physical address pointer pointing to a host buffer that the
28887 * command's response data will be written. This can be either a host
28888 * physical address (HPA) or a guest physical address (GPA) and must
28889 * point to a physically contiguous block of memory.
28891 uint64_t resp_addr;
28894 * When set to 1, indicates the host memory which is passed will be
28895 * used for the TX flow offload function specified in fid.
28896 * Note if this bit is set then the path_rx bit can't be set.
28898 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
28900 * When set to 1, indicates the host memory which is passed will be
28901 * used for the RX flow offload function specified in fid.
28902 * Note if this bit is set then the path_tx bit can't be set.
28904 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
28906 /* The number of EEM key table entries to be configured. */
28908 /* This value is reserved and should not be used. */
28909 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
28911 * To properly stop EEM and ensure there are no DMA's, the caller
28912 * must disable EEM for the given PF, using this call. This will
28913 * safely disable EEM and ensure that all DMA'ed to the
28914 * keys/records/efc have been completed.
28916 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
28918 * Once the EEM host memory has been configured, EEM options have
28919 * been configured. Then the caller should enable EEM for the given
28920 * PF. Note once this call has been made, then the EEM mechanism
28921 * will be active and DMA's will occur as packets are processed.
28923 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
28925 * Clear EEM settings for the given PF so that the register values
28926 * are reset back to there initial state.
28928 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
28929 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
28930 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
28931 } __attribute__((packed));
28933 /* hwrm_cfa_eem_op_output (size:128b/16B) */
28934 struct hwrm_cfa_eem_op_output {
28935 /* The specific error status for the command. */
28936 uint16_t error_code;
28937 /* The HWRM command request type. */
28939 /* The sequence ID from the original command. */
28941 /* The length of the response data in number of bytes. */
28943 uint8_t unused_0[7];
28945 * This field is used in Output records to indicate that the output
28946 * is completely written to RAM. This field should be read as '1'
28947 * to indicate that the output has been completely written.
28948 * When writing a command completion or response to an internal processor,
28949 * the order of writes has to be such that this field is written last.
28952 } __attribute__((packed));
28954 /********************************
28955 * hwrm_cfa_adv_flow_mgnt_qcaps *
28956 ********************************/
28959 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
28960 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
28961 /* The HWRM command request type. */
28964 * The completion ring to send the completion event on. This should
28965 * be the NQ ID returned from the `nq_alloc` HWRM command.
28967 uint16_t cmpl_ring;
28969 * The sequence ID is used by the driver for tracking multiple
28970 * commands. This ID is treated as opaque data by the firmware and
28971 * the value is returned in the `hwrm_resp_hdr` upon completion.
28975 * The target ID of the command:
28976 * * 0x0-0xFFF8 - The function ID
28977 * * 0xFFF8-0xFFFE - Reserved for internal processors
28980 uint16_t target_id;
28982 * A physical address pointer pointing to a host buffer that the
28983 * command's response data will be written. This can be either a host
28984 * physical address (HPA) or a guest physical address (GPA) and must
28985 * point to a physically contiguous block of memory.
28987 uint64_t resp_addr;
28988 uint32_t unused_0[4];
28989 } __attribute__((packed));
28991 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
28992 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
28993 /* The specific error status for the command. */
28994 uint16_t error_code;
28995 /* The HWRM command request type. */
28997 /* The sequence ID from the original command. */
28999 /* The length of the response data in number of bytes. */
29003 * Value of 1 to indicate firmware support 16-bit flow handle.
29004 * Value of 0 to indicate firmware not support 16-bit flow handle.
29006 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
29009 * Value of 1 to indicate firmware support 64-bit flow handle.
29010 * Value of 0 to indicate firmware not support 64-bit flow handle.
29012 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
29015 * Value of 1 to indicate firmware support flow batch delete operation through
29016 * HWRM_CFA_FLOW_FLUSH command.
29017 * Value of 0 to indicate that the firmware does not support flow batch delete
29020 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
29023 * Value of 1 to indicate that the firmware support flow reset all operation through
29024 * HWRM_CFA_FLOW_FLUSH command.
29025 * Value of 0 indicates firmware does not support flow reset all operation.
29027 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
29030 * Value of 1 to indicate that firmware supports use of FID as dest_id in
29031 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
29032 * Value of 0 indicates firmware does not support use of FID as dest_id.
29034 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
29037 * Value of 1 to indicate that firmware supports TX EEM flows.
29038 * Value of 0 indicates firmware does not support TX EEM flows.
29040 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
29043 * Value of 1 to indicate that firmware supports RX EEM flows.
29044 * Value of 0 indicates firmware does not support RX EEM flows.
29046 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
29048 uint8_t unused_0[3];
29050 * This field is used in Output records to indicate that the output
29051 * is completely written to RAM. This field should be read as '1'
29052 * to indicate that the output has been completely written.
29053 * When writing a command completion or response to an internal processor,
29054 * the order of writes has to be such that this field is written last.
29057 } __attribute__((packed));
29059 /******************************
29060 * hwrm_tunnel_dst_port_query *
29061 ******************************/
29064 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
29065 struct hwrm_tunnel_dst_port_query_input {
29066 /* The HWRM command request type. */
29069 * The completion ring to send the completion event on. This should
29070 * be the NQ ID returned from the `nq_alloc` HWRM command.
29072 uint16_t cmpl_ring;
29074 * The sequence ID is used by the driver for tracking multiple
29075 * commands. This ID is treated as opaque data by the firmware and
29076 * the value is returned in the `hwrm_resp_hdr` upon completion.
29080 * The target ID of the command:
29081 * * 0x0-0xFFF8 - The function ID
29082 * * 0xFFF8-0xFFFE - Reserved for internal processors
29085 uint16_t target_id;
29087 * A physical address pointer pointing to a host buffer that the
29088 * command's response data will be written. This can be either a host
29089 * physical address (HPA) or a guest physical address (GPA) and must
29090 * point to a physically contiguous block of memory.
29092 uint64_t resp_addr;
29094 uint8_t tunnel_type;
29095 /* Virtual eXtensible Local Area Network (VXLAN) */
29096 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
29098 /* Generic Network Virtualization Encapsulation (Geneve) */
29099 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
29101 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29102 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29104 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29105 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29107 /* Use fixed layer 2 ether type of 0xFFFF */
29108 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
29110 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29111 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29113 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
29114 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
29115 uint8_t unused_0[7];
29116 } __attribute__((packed));
29118 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
29119 struct hwrm_tunnel_dst_port_query_output {
29120 /* The specific error status for the command. */
29121 uint16_t error_code;
29122 /* The HWRM command request type. */
29124 /* The sequence ID from the original command. */
29126 /* The length of the response data in number of bytes. */
29129 * This field represents the identifier of L4 destination port
29130 * used for the given tunnel type. This field is valid for
29131 * specific tunnel types that use layer 4 (e.g. UDP)
29132 * transports for tunneling.
29134 uint16_t tunnel_dst_port_id;
29136 * This field represents the value of L4 destination port
29137 * identified by tunnel_dst_port_id. This field is valid for
29138 * specific tunnel types that use layer 4 (e.g. UDP)
29139 * transports for tunneling.
29140 * This field is in network byte order.
29142 * A value of 0 means that the destination port is not
29145 uint16_t tunnel_dst_port_val;
29146 uint8_t unused_0[3];
29148 * This field is used in Output records to indicate that the output
29149 * is completely written to RAM. This field should be read as '1'
29150 * to indicate that the output has been completely written.
29151 * When writing a command completion or response to an internal processor,
29152 * the order of writes has to be such that this field is written last.
29155 } __attribute__((packed));
29157 /******************************
29158 * hwrm_tunnel_dst_port_alloc *
29159 ******************************/
29162 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
29163 struct hwrm_tunnel_dst_port_alloc_input {
29164 /* The HWRM command request type. */
29167 * The completion ring to send the completion event on. This should
29168 * be the NQ ID returned from the `nq_alloc` HWRM command.
29170 uint16_t cmpl_ring;
29172 * The sequence ID is used by the driver for tracking multiple
29173 * commands. This ID is treated as opaque data by the firmware and
29174 * the value is returned in the `hwrm_resp_hdr` upon completion.
29178 * The target ID of the command:
29179 * * 0x0-0xFFF8 - The function ID
29180 * * 0xFFF8-0xFFFE - Reserved for internal processors
29183 uint16_t target_id;
29185 * A physical address pointer pointing to a host buffer that the
29186 * command's response data will be written. This can be either a host
29187 * physical address (HPA) or a guest physical address (GPA) and must
29188 * point to a physically contiguous block of memory.
29190 uint64_t resp_addr;
29192 uint8_t tunnel_type;
29193 /* Virtual eXtensible Local Area Network (VXLAN) */
29194 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29196 /* Generic Network Virtualization Encapsulation (Geneve) */
29197 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29199 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29200 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29202 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29203 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29205 /* Use fixed layer 2 ether type of 0xFFFF */
29206 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29208 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29209 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29211 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29212 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
29215 * This field represents the value of L4 destination port used
29216 * for the given tunnel type. This field is valid for
29217 * specific tunnel types that use layer 4 (e.g. UDP)
29218 * transports for tunneling.
29220 * This field is in network byte order.
29222 * A value of 0 shall fail the command.
29224 uint16_t tunnel_dst_port_val;
29225 uint8_t unused_1[4];
29226 } __attribute__((packed));
29228 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
29229 struct hwrm_tunnel_dst_port_alloc_output {
29230 /* The specific error status for the command. */
29231 uint16_t error_code;
29232 /* The HWRM command request type. */
29234 /* The sequence ID from the original command. */
29236 /* The length of the response data in number of bytes. */
29239 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
29240 * types that has l4 destination port parameters.
29242 uint16_t tunnel_dst_port_id;
29243 uint8_t unused_0[5];
29245 * This field is used in Output records to indicate that the output
29246 * is completely written to RAM. This field should be read as '1'
29247 * to indicate that the output has been completely written.
29248 * When writing a command completion or response to an internal processor,
29249 * the order of writes has to be such that this field is written last.
29252 } __attribute__((packed));
29254 /*****************************
29255 * hwrm_tunnel_dst_port_free *
29256 *****************************/
29259 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
29260 struct hwrm_tunnel_dst_port_free_input {
29261 /* The HWRM command request type. */
29264 * The completion ring to send the completion event on. This should
29265 * be the NQ ID returned from the `nq_alloc` HWRM command.
29267 uint16_t cmpl_ring;
29269 * The sequence ID is used by the driver for tracking multiple
29270 * commands. This ID is treated as opaque data by the firmware and
29271 * the value is returned in the `hwrm_resp_hdr` upon completion.
29275 * The target ID of the command:
29276 * * 0x0-0xFFF8 - The function ID
29277 * * 0xFFF8-0xFFFE - Reserved for internal processors
29280 uint16_t target_id;
29282 * A physical address pointer pointing to a host buffer that the
29283 * command's response data will be written. This can be either a host
29284 * physical address (HPA) or a guest physical address (GPA) and must
29285 * point to a physically contiguous block of memory.
29287 uint64_t resp_addr;
29289 uint8_t tunnel_type;
29290 /* Virtual eXtensible Local Area Network (VXLAN) */
29291 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
29293 /* Generic Network Virtualization Encapsulation (Geneve) */
29294 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
29296 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29297 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29299 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29300 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29302 /* Use fixed layer 2 ether type of 0xFFFF */
29303 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
29305 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29306 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29308 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
29309 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
29312 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
29313 * types that has l4 destination port parameters.
29315 uint16_t tunnel_dst_port_id;
29316 uint8_t unused_1[4];
29317 } __attribute__((packed));
29319 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
29320 struct hwrm_tunnel_dst_port_free_output {
29321 /* The specific error status for the command. */
29322 uint16_t error_code;
29323 /* The HWRM command request type. */
29325 /* The sequence ID from the original command. */
29327 /* The length of the response data in number of bytes. */
29329 uint8_t unused_1[7];
29331 * This field is used in Output records to indicate that the output
29332 * is completely written to RAM. This field should be read as '1'
29333 * to indicate that the output has been completely written.
29334 * When writing a command completion or response to an internal processor,
29335 * the order of writes has to be such that this field is written last.
29338 } __attribute__((packed));
29340 /* Periodic statistics context DMA to host. */
29341 /* ctx_hw_stats (size:1280b/160B) */
29342 struct ctx_hw_stats {
29343 /* Number of received unicast packets */
29344 uint64_t rx_ucast_pkts;
29345 /* Number of received multicast packets */
29346 uint64_t rx_mcast_pkts;
29347 /* Number of received broadcast packets */
29348 uint64_t rx_bcast_pkts;
29349 /* Number of discarded packets on received path */
29350 uint64_t rx_discard_pkts;
29351 /* Number of dropped packets on received path */
29352 uint64_t rx_drop_pkts;
29353 /* Number of received bytes for unicast traffic */
29354 uint64_t rx_ucast_bytes;
29355 /* Number of received bytes for multicast traffic */
29356 uint64_t rx_mcast_bytes;
29357 /* Number of received bytes for broadcast traffic */
29358 uint64_t rx_bcast_bytes;
29359 /* Number of transmitted unicast packets */
29360 uint64_t tx_ucast_pkts;
29361 /* Number of transmitted multicast packets */
29362 uint64_t tx_mcast_pkts;
29363 /* Number of transmitted broadcast packets */
29364 uint64_t tx_bcast_pkts;
29365 /* Number of discarded packets on transmit path */
29366 uint64_t tx_discard_pkts;
29367 /* Number of dropped packets on transmit path */
29368 uint64_t tx_drop_pkts;
29369 /* Number of transmitted bytes for unicast traffic */
29370 uint64_t tx_ucast_bytes;
29371 /* Number of transmitted bytes for multicast traffic */
29372 uint64_t tx_mcast_bytes;
29373 /* Number of transmitted bytes for broadcast traffic */
29374 uint64_t tx_bcast_bytes;
29375 /* Number of TPA packets */
29377 /* Number of TPA bytes */
29378 uint64_t tpa_bytes;
29379 /* Number of TPA events */
29380 uint64_t tpa_events;
29381 /* Number of TPA aborts */
29382 uint64_t tpa_aborts;
29383 } __attribute__((packed));
29385 /* Periodic Engine statistics context DMA to host. */
29386 /* ctx_eng_stats (size:512b/64B) */
29387 struct ctx_eng_stats {
29389 * Count of data bytes into the Engine.
29390 * This includes any user supplied prefix,
29391 * but does not include any predefined
29394 uint64_t eng_bytes_in;
29395 /* Count of data bytes out of the Engine. */
29396 uint64_t eng_bytes_out;
29398 * Count, in 4-byte (dword) units, of bytes
29399 * that are input as auxiliary data.
29400 * This includes the aux_cmd data.
29402 uint64_t aux_bytes_in;
29404 * Count, in 4-byte (dword) units, of bytes
29405 * that are output as auxiliary data.
29406 * This count is the buffer space for aux_data
29407 * output provided in the RQE, not the actual
29410 uint64_t aux_bytes_out;
29411 /* Count of number of commands executed. */
29414 * Count of number of error commands.
29415 * These are the commands with a
29416 * non-zero status value.
29418 uint64_t error_commands;
29420 * Compression/Encryption Engine usage,
29421 * the unit is count of clock cycles
29423 uint64_t cce_engine_usage;
29425 * De-Compression/De-cryption Engine usage,
29426 * the unit is count of clock cycles
29428 uint64_t cdd_engine_usage;
29429 } __attribute__((packed));
29431 /***********************
29432 * hwrm_stat_ctx_alloc *
29433 ***********************/
29436 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
29437 struct hwrm_stat_ctx_alloc_input {
29438 /* The HWRM command request type. */
29441 * The completion ring to send the completion event on. This should
29442 * be the NQ ID returned from the `nq_alloc` HWRM command.
29444 uint16_t cmpl_ring;
29446 * The sequence ID is used by the driver for tracking multiple
29447 * commands. This ID is treated as opaque data by the firmware and
29448 * the value is returned in the `hwrm_resp_hdr` upon completion.
29452 * The target ID of the command:
29453 * * 0x0-0xFFF8 - The function ID
29454 * * 0xFFF8-0xFFFE - Reserved for internal processors
29457 uint16_t target_id;
29459 * A physical address pointer pointing to a host buffer that the
29460 * command's response data will be written. This can be either a host
29461 * physical address (HPA) or a guest physical address (GPA) and must
29462 * point to a physically contiguous block of memory.
29464 uint64_t resp_addr;
29466 * This is the address for statistic block.
29467 * > For new versions of the chip, this address should be 128B
29470 uint64_t stats_dma_addr;
29472 * The statistic block update period in ms.
29473 * e.g. 250ms, 500ms, 750ms, 1000ms.
29474 * If update_period_ms is 0, then the stats update
29475 * shall be never done and the DMA address shall not be used.
29476 * In this case, the stat block can only be read by
29477 * hwrm_stat_ctx_query command.
29479 uint32_t update_period_ms;
29481 * This field is used to specify statistics context specific
29482 * configuration flags.
29484 uint8_t stat_ctx_flags;
29486 * When this bit is set to '1', the statistics context shall be
29487 * allocated for RoCE traffic only. In this case, traffic other
29488 * than offloaded RoCE traffic shall not be included in this
29489 * statistic context.
29490 * When this bit is set to '0', the statistics context shall be
29491 * used for network traffic or engine traffic.
29493 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
29494 uint8_t unused_0[3];
29495 } __attribute__((packed));
29497 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
29498 struct hwrm_stat_ctx_alloc_output {
29499 /* The specific error status for the command. */
29500 uint16_t error_code;
29501 /* The HWRM command request type. */
29503 /* The sequence ID from the original command. */
29505 /* The length of the response data in number of bytes. */
29507 /* This is the statistics context ID value. */
29508 uint32_t stat_ctx_id;
29509 uint8_t unused_0[3];
29511 * This field is used in Output records to indicate that the output
29512 * is completely written to RAM. This field should be read as '1'
29513 * to indicate that the output has been completely written.
29514 * When writing a command completion or response to an internal processor,
29515 * the order of writes has to be such that this field is written last.
29518 } __attribute__((packed));
29520 /**********************
29521 * hwrm_stat_ctx_free *
29522 **********************/
29525 /* hwrm_stat_ctx_free_input (size:192b/24B) */
29526 struct hwrm_stat_ctx_free_input {
29527 /* The HWRM command request type. */
29530 * The completion ring to send the completion event on. This should
29531 * be the NQ ID returned from the `nq_alloc` HWRM command.
29533 uint16_t cmpl_ring;
29535 * The sequence ID is used by the driver for tracking multiple
29536 * commands. This ID is treated as opaque data by the firmware and
29537 * the value is returned in the `hwrm_resp_hdr` upon completion.
29541 * The target ID of the command:
29542 * * 0x0-0xFFF8 - The function ID
29543 * * 0xFFF8-0xFFFE - Reserved for internal processors
29546 uint16_t target_id;
29548 * A physical address pointer pointing to a host buffer that the
29549 * command's response data will be written. This can be either a host
29550 * physical address (HPA) or a guest physical address (GPA) and must
29551 * point to a physically contiguous block of memory.
29553 uint64_t resp_addr;
29554 /* ID of the statistics context that is being queried. */
29555 uint32_t stat_ctx_id;
29556 uint8_t unused_0[4];
29557 } __attribute__((packed));
29559 /* hwrm_stat_ctx_free_output (size:128b/16B) */
29560 struct hwrm_stat_ctx_free_output {
29561 /* The specific error status for the command. */
29562 uint16_t error_code;
29563 /* The HWRM command request type. */
29565 /* The sequence ID from the original command. */
29567 /* The length of the response data in number of bytes. */
29569 /* This is the statistics context ID value. */
29570 uint32_t stat_ctx_id;
29571 uint8_t unused_0[3];
29573 * This field is used in Output records to indicate that the output
29574 * is completely written to RAM. This field should be read as '1'
29575 * to indicate that the output has been completely written.
29576 * When writing a command completion or response to an internal processor,
29577 * the order of writes has to be such that this field is written last.
29580 } __attribute__((packed));
29582 /***********************
29583 * hwrm_stat_ctx_query *
29584 ***********************/
29587 /* hwrm_stat_ctx_query_input (size:192b/24B) */
29588 struct hwrm_stat_ctx_query_input {
29589 /* The HWRM command request type. */
29592 * The completion ring to send the completion event on. This should
29593 * be the NQ ID returned from the `nq_alloc` HWRM command.
29595 uint16_t cmpl_ring;
29597 * The sequence ID is used by the driver for tracking multiple
29598 * commands. This ID is treated as opaque data by the firmware and
29599 * the value is returned in the `hwrm_resp_hdr` upon completion.
29603 * The target ID of the command:
29604 * * 0x0-0xFFF8 - The function ID
29605 * * 0xFFF8-0xFFFE - Reserved for internal processors
29608 uint16_t target_id;
29610 * A physical address pointer pointing to a host buffer that the
29611 * command's response data will be written. This can be either a host
29612 * physical address (HPA) or a guest physical address (GPA) and must
29613 * point to a physically contiguous block of memory.
29615 uint64_t resp_addr;
29616 /* ID of the statistics context that is being queried. */
29617 uint32_t stat_ctx_id;
29618 uint8_t unused_0[4];
29619 } __attribute__((packed));
29621 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
29622 struct hwrm_stat_ctx_query_output {
29623 /* The specific error status for the command. */
29624 uint16_t error_code;
29625 /* The HWRM command request type. */
29627 /* The sequence ID from the original command. */
29629 /* The length of the response data in number of bytes. */
29631 /* Number of transmitted unicast packets */
29632 uint64_t tx_ucast_pkts;
29633 /* Number of transmitted multicast packets */
29634 uint64_t tx_mcast_pkts;
29635 /* Number of transmitted broadcast packets */
29636 uint64_t tx_bcast_pkts;
29637 /* Number of transmitted packets with error */
29638 uint64_t tx_err_pkts;
29639 /* Number of dropped packets on transmit path */
29640 uint64_t tx_drop_pkts;
29641 /* Number of transmitted bytes for unicast traffic */
29642 uint64_t tx_ucast_bytes;
29643 /* Number of transmitted bytes for multicast traffic */
29644 uint64_t tx_mcast_bytes;
29645 /* Number of transmitted bytes for broadcast traffic */
29646 uint64_t tx_bcast_bytes;
29647 /* Number of received unicast packets */
29648 uint64_t rx_ucast_pkts;
29649 /* Number of received multicast packets */
29650 uint64_t rx_mcast_pkts;
29651 /* Number of received broadcast packets */
29652 uint64_t rx_bcast_pkts;
29653 /* Number of received packets with error */
29654 uint64_t rx_err_pkts;
29655 /* Number of dropped packets on received path */
29656 uint64_t rx_drop_pkts;
29657 /* Number of received bytes for unicast traffic */
29658 uint64_t rx_ucast_bytes;
29659 /* Number of received bytes for multicast traffic */
29660 uint64_t rx_mcast_bytes;
29661 /* Number of received bytes for broadcast traffic */
29662 uint64_t rx_bcast_bytes;
29663 /* Number of aggregated unicast packets */
29664 uint64_t rx_agg_pkts;
29665 /* Number of aggregated unicast bytes */
29666 uint64_t rx_agg_bytes;
29667 /* Number of aggregation events */
29668 uint64_t rx_agg_events;
29669 /* Number of aborted aggregations */
29670 uint64_t rx_agg_aborts;
29671 uint8_t unused_0[7];
29673 * This field is used in Output records to indicate that the output
29674 * is completely written to RAM. This field should be read as '1'
29675 * to indicate that the output has been completely written.
29676 * When writing a command completion or response to an internal processor,
29677 * the order of writes has to be such that this field is written last.
29680 } __attribute__((packed));
29682 /***************************
29683 * hwrm_stat_ctx_eng_query *
29684 ***************************/
29687 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
29688 struct hwrm_stat_ctx_eng_query_input {
29689 /* The HWRM command request type. */
29692 * The completion ring to send the completion event on. This should
29693 * be the NQ ID returned from the `nq_alloc` HWRM command.
29695 uint16_t cmpl_ring;
29697 * The sequence ID is used by the driver for tracking multiple
29698 * commands. This ID is treated as opaque data by the firmware and
29699 * the value is returned in the `hwrm_resp_hdr` upon completion.
29703 * The target ID of the command:
29704 * * 0x0-0xFFF8 - The function ID
29705 * * 0xFFF8-0xFFFE - Reserved for internal processors
29708 uint16_t target_id;
29710 * A physical address pointer pointing to a host buffer that the
29711 * command's response data will be written. This can be either a host
29712 * physical address (HPA) or a guest physical address (GPA) and must
29713 * point to a physically contiguous block of memory.
29715 uint64_t resp_addr;
29716 /* ID of the statistics context that is being queried. */
29717 uint32_t stat_ctx_id;
29718 uint8_t unused_0[4];
29719 } __attribute__((packed));
29721 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
29722 struct hwrm_stat_ctx_eng_query_output {
29723 /* The specific error status for the command. */
29724 uint16_t error_code;
29725 /* The HWRM command request type. */
29727 /* The sequence ID from the original command. */
29729 /* The length of the response data in number of bytes. */
29732 * Count of data bytes into the Engine.
29733 * This includes any user supplied prefix,
29734 * but does not include any predefined
29737 uint64_t eng_bytes_in;
29738 /* Count of data bytes out of the Engine. */
29739 uint64_t eng_bytes_out;
29741 * Count, in 4-byte (dword) units, of bytes
29742 * that are input as auxiliary data.
29743 * This includes the aux_cmd data.
29745 uint64_t aux_bytes_in;
29747 * Count, in 4-byte (dword) units, of bytes
29748 * that are output as auxiliary data.
29749 * This count is the buffer space for aux_data
29750 * output provided in the RQE, not the actual
29753 uint64_t aux_bytes_out;
29754 /* Count of number of commands executed. */
29757 * Count of number of error commands.
29758 * These are the commands with a
29759 * non-zero status value.
29761 uint64_t error_commands;
29763 * Compression/Encryption Engine usage,
29764 * the unit is count of clock cycles
29766 uint64_t cce_engine_usage;
29768 * De-Compression/De-cryption Engine usage,
29769 * the unit is count of clock cycles
29771 uint64_t cdd_engine_usage;
29772 uint8_t unused_0[7];
29774 * This field is used in Output records to indicate that the output
29775 * is completely written to RAM. This field should be read as '1'
29776 * to indicate that the output has been completely written.
29777 * When writing a command completion or response to an internal processor,
29778 * the order of writes has to be such that this field is written last.
29781 } __attribute__((packed));
29783 /***************************
29784 * hwrm_stat_ctx_clr_stats *
29785 ***************************/
29788 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
29789 struct hwrm_stat_ctx_clr_stats_input {
29790 /* The HWRM command request type. */
29793 * The completion ring to send the completion event on. This should
29794 * be the NQ ID returned from the `nq_alloc` HWRM command.
29796 uint16_t cmpl_ring;
29798 * The sequence ID is used by the driver for tracking multiple
29799 * commands. This ID is treated as opaque data by the firmware and
29800 * the value is returned in the `hwrm_resp_hdr` upon completion.
29804 * The target ID of the command:
29805 * * 0x0-0xFFF8 - The function ID
29806 * * 0xFFF8-0xFFFE - Reserved for internal processors
29809 uint16_t target_id;
29811 * A physical address pointer pointing to a host buffer that the
29812 * command's response data will be written. This can be either a host
29813 * physical address (HPA) or a guest physical address (GPA) and must
29814 * point to a physically contiguous block of memory.
29816 uint64_t resp_addr;
29817 /* ID of the statistics context that is being queried. */
29818 uint32_t stat_ctx_id;
29819 uint8_t unused_0[4];
29820 } __attribute__((packed));
29822 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
29823 struct hwrm_stat_ctx_clr_stats_output {
29824 /* The specific error status for the command. */
29825 uint16_t error_code;
29826 /* The HWRM command request type. */
29828 /* The sequence ID from the original command. */
29830 /* The length of the response data in number of bytes. */
29832 uint8_t unused_0[7];
29834 * This field is used in Output records to indicate that the output
29835 * is completely written to RAM. This field should be read as '1'
29836 * to indicate that the output has been completely written.
29837 * When writing a command completion or response to an internal processor,
29838 * the order of writes has to be such that this field is written last.
29841 } __attribute__((packed));
29843 /********************
29844 * hwrm_pcie_qstats *
29845 ********************/
29848 /* hwrm_pcie_qstats_input (size:256b/32B) */
29849 struct hwrm_pcie_qstats_input {
29850 /* The HWRM command request type. */
29853 * The completion ring to send the completion event on. This should
29854 * be the NQ ID returned from the `nq_alloc` HWRM command.
29856 uint16_t cmpl_ring;
29858 * The sequence ID is used by the driver for tracking multiple
29859 * commands. This ID is treated as opaque data by the firmware and
29860 * the value is returned in the `hwrm_resp_hdr` upon completion.
29864 * The target ID of the command:
29865 * * 0x0-0xFFF8 - The function ID
29866 * * 0xFFF8-0xFFFE - Reserved for internal processors
29869 uint16_t target_id;
29871 * A physical address pointer pointing to a host buffer that the
29872 * command's response data will be written. This can be either a host
29873 * physical address (HPA) or a guest physical address (GPA) and must
29874 * point to a physically contiguous block of memory.
29876 uint64_t resp_addr;
29878 * The size of PCIe statistics block in bytes.
29879 * Firmware will DMA the PCIe statistics to
29880 * the host with this field size in the response.
29882 uint16_t pcie_stat_size;
29883 uint8_t unused_0[6];
29885 * This is the host address where
29886 * PCIe statistics will be stored
29888 uint64_t pcie_stat_host_addr;
29889 } __attribute__((packed));
29891 /* hwrm_pcie_qstats_output (size:128b/16B) */
29892 struct hwrm_pcie_qstats_output {
29893 /* The specific error status for the command. */
29894 uint16_t error_code;
29895 /* The HWRM command request type. */
29897 /* The sequence ID from the original command. */
29899 /* The length of the response data in number of bytes. */
29901 /* The size of PCIe statistics block in bytes. */
29902 uint16_t pcie_stat_size;
29903 uint8_t unused_0[5];
29905 * This field is used in Output records to indicate that the output
29906 * is completely written to RAM. This field should be read as '1'
29907 * to indicate that the output has been completely written.
29908 * When writing a command completion or response to an internal processor,
29909 * the order of writes has to be such that this field is written last.
29912 } __attribute__((packed));
29914 /* PCIe Statistics Formats */
29915 /* pcie_ctx_hw_stats (size:768b/96B) */
29916 struct pcie_ctx_hw_stats {
29917 /* Number of physical layer receiver errors */
29918 uint64_t pcie_pl_signal_integrity;
29919 /* Number of DLLP CRC errors detected by Data Link Layer */
29920 uint64_t pcie_dl_signal_integrity;
29922 * Number of TLP LCRC and sequence number errors detected
29923 * by Data Link Layer
29925 uint64_t pcie_tl_signal_integrity;
29926 /* Number of times LTSSM entered Recovery state */
29927 uint64_t pcie_link_integrity;
29928 /* Number of TLP bytes that have been trasmitted */
29929 uint64_t pcie_tx_traffic_rate;
29930 /* Number of TLP bytes that have been received */
29931 uint64_t pcie_rx_traffic_rate;
29932 /* Number of DLLP bytes that have been trasmitted */
29933 uint64_t pcie_tx_dllp_statistics;
29934 /* Number of DLLP bytes that have been received */
29935 uint64_t pcie_rx_dllp_statistics;
29937 * Number of times spent in each phase of gen3
29940 uint64_t pcie_equalization_time;
29941 /* Records the last 16 transitions of the LTSSM */
29942 uint32_t pcie_ltssm_histogram[4];
29944 * Record the last 8 reasons on why LTSSM transitioned
29947 uint64_t pcie_recovery_histogram;
29948 } __attribute__((packed));
29950 /**********************
29951 * hwrm_exec_fwd_resp *
29952 **********************/
29955 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
29956 struct hwrm_exec_fwd_resp_input {
29957 /* The HWRM command request type. */
29960 * The completion ring to send the completion event on. This should
29961 * be the NQ ID returned from the `nq_alloc` HWRM command.
29963 uint16_t cmpl_ring;
29965 * The sequence ID is used by the driver for tracking multiple
29966 * commands. This ID is treated as opaque data by the firmware and
29967 * the value is returned in the `hwrm_resp_hdr` upon completion.
29971 * The target ID of the command:
29972 * * 0x0-0xFFF8 - The function ID
29973 * * 0xFFF8-0xFFFE - Reserved for internal processors
29976 uint16_t target_id;
29978 * A physical address pointer pointing to a host buffer that the
29979 * command's response data will be written. This can be either a host
29980 * physical address (HPA) or a guest physical address (GPA) and must
29981 * point to a physically contiguous block of memory.
29983 uint64_t resp_addr;
29985 * This is an encapsulated request. This request should
29986 * be executed by the HWRM and the response should be
29987 * provided in the response buffer inside the encapsulated
29990 uint32_t encap_request[26];
29992 * This value indicates the target id of the response to
29993 * the encapsulated request.
29994 * 0x0 - 0xFFF8 - Used for function ids
29995 * 0xFFF8 - 0xFFFE - Reserved for internal processors
29998 uint16_t encap_resp_target_id;
29999 uint8_t unused_0[6];
30000 } __attribute__((packed));
30002 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
30003 struct hwrm_exec_fwd_resp_output {
30004 /* The specific error status for the command. */
30005 uint16_t error_code;
30006 /* The HWRM command request type. */
30008 /* The sequence ID from the original command. */
30010 /* The length of the response data in number of bytes. */
30012 uint8_t unused_0[7];
30014 * This field is used in Output records to indicate that the output
30015 * is completely written to RAM. This field should be read as '1'
30016 * to indicate that the output has been completely written.
30017 * When writing a command completion or response to an internal processor,
30018 * the order of writes has to be such that this field is written last.
30021 } __attribute__((packed));
30023 /************************
30024 * hwrm_reject_fwd_resp *
30025 ************************/
30028 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
30029 struct hwrm_reject_fwd_resp_input {
30030 /* The HWRM command request type. */
30033 * The completion ring to send the completion event on. This should
30034 * be the NQ ID returned from the `nq_alloc` HWRM command.
30036 uint16_t cmpl_ring;
30038 * The sequence ID is used by the driver for tracking multiple
30039 * commands. This ID is treated as opaque data by the firmware and
30040 * the value is returned in the `hwrm_resp_hdr` upon completion.
30044 * The target ID of the command:
30045 * * 0x0-0xFFF8 - The function ID
30046 * * 0xFFF8-0xFFFE - Reserved for internal processors
30049 uint16_t target_id;
30051 * A physical address pointer pointing to a host buffer that the
30052 * command's response data will be written. This can be either a host
30053 * physical address (HPA) or a guest physical address (GPA) and must
30054 * point to a physically contiguous block of memory.
30056 uint64_t resp_addr;
30058 * This is an encapsulated request. This request should
30059 * be rejected by the HWRM and the error response should be
30060 * provided in the response buffer inside the encapsulated
30063 uint32_t encap_request[26];
30065 * This value indicates the target id of the response to
30066 * the encapsulated request.
30067 * 0x0 - 0xFFF8 - Used for function ids
30068 * 0xFFF8 - 0xFFFE - Reserved for internal processors
30071 uint16_t encap_resp_target_id;
30072 uint8_t unused_0[6];
30073 } __attribute__((packed));
30075 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
30076 struct hwrm_reject_fwd_resp_output {
30077 /* The specific error status for the command. */
30078 uint16_t error_code;
30079 /* The HWRM command request type. */
30081 /* The sequence ID from the original command. */
30083 /* The length of the response data in number of bytes. */
30085 uint8_t unused_0[7];
30087 * This field is used in Output records to indicate that the output
30088 * is completely written to RAM. This field should be read as '1'
30089 * to indicate that the output has been completely written.
30090 * When writing a command completion or response to an internal processor,
30091 * the order of writes has to be such that this field is written last.
30094 } __attribute__((packed));
30101 /* hwrm_fwd_resp_input (size:1024b/128B) */
30102 struct hwrm_fwd_resp_input {
30103 /* The HWRM command request type. */
30106 * The completion ring to send the completion event on. This should
30107 * be the NQ ID returned from the `nq_alloc` HWRM command.
30109 uint16_t cmpl_ring;
30111 * The sequence ID is used by the driver for tracking multiple
30112 * commands. This ID is treated as opaque data by the firmware and
30113 * the value is returned in the `hwrm_resp_hdr` upon completion.
30117 * The target ID of the command:
30118 * * 0x0-0xFFF8 - The function ID
30119 * * 0xFFF8-0xFFFE - Reserved for internal processors
30122 uint16_t target_id;
30124 * A physical address pointer pointing to a host buffer that the
30125 * command's response data will be written. This can be either a host
30126 * physical address (HPA) or a guest physical address (GPA) and must
30127 * point to a physically contiguous block of memory.
30129 uint64_t resp_addr;
30131 * This value indicates the target id of the encapsulated
30133 * 0x0 - 0xFFF8 - Used for function ids
30134 * 0xFFF8 - 0xFFFE - Reserved for internal processors
30137 uint16_t encap_resp_target_id;
30139 * This value indicates the completion ring the encapsulated
30140 * response will be optionally completed on. If the value is
30141 * -1, then no CR completion shall be generated for the
30142 * encapsulated response. Any other value must be a
30143 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
30144 * is provided, then a CR completion shall be generated for
30145 * the encapsulated response.
30147 uint16_t encap_resp_cmpl_ring;
30148 /* This field indicates the length of encapsulated response. */
30149 uint16_t encap_resp_len;
30153 * This is the host address where the encapsulated response
30155 * This area must be 16B aligned and must be cleared to zero
30156 * before the original request is made.
30158 uint64_t encap_resp_addr;
30159 /* This is an encapsulated response. */
30160 uint32_t encap_resp[24];
30161 } __attribute__((packed));
30163 /* hwrm_fwd_resp_output (size:128b/16B) */
30164 struct hwrm_fwd_resp_output {
30165 /* The specific error status for the command. */
30166 uint16_t error_code;
30167 /* The HWRM command request type. */
30169 /* The sequence ID from the original command. */
30171 /* The length of the response data in number of bytes. */
30173 uint8_t unused_0[7];
30175 * This field is used in Output records to indicate that the output
30176 * is completely written to RAM. This field should be read as '1'
30177 * to indicate that the output has been completely written.
30178 * When writing a command completion or response to an internal processor,
30179 * the order of writes has to be such that this field is written last.
30182 } __attribute__((packed));
30184 /*****************************
30185 * hwrm_fwd_async_event_cmpl *
30186 *****************************/
30189 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
30190 struct hwrm_fwd_async_event_cmpl_input {
30191 /* The HWRM command request type. */
30194 * The completion ring to send the completion event on. This should
30195 * be the NQ ID returned from the `nq_alloc` HWRM command.
30197 uint16_t cmpl_ring;
30199 * The sequence ID is used by the driver for tracking multiple
30200 * commands. This ID is treated as opaque data by the firmware and
30201 * the value is returned in the `hwrm_resp_hdr` upon completion.
30205 * The target ID of the command:
30206 * * 0x0-0xFFF8 - The function ID
30207 * * 0xFFF8-0xFFFE - Reserved for internal processors
30210 uint16_t target_id;
30212 * A physical address pointer pointing to a host buffer that the
30213 * command's response data will be written. This can be either a host
30214 * physical address (HPA) or a guest physical address (GPA) and must
30215 * point to a physically contiguous block of memory.
30217 uint64_t resp_addr;
30219 * This value indicates the target id of the encapsulated
30220 * asynchronous event.
30221 * 0x0 - 0xFFF8 - Used for function ids
30222 * 0xFFF8 - 0xFFFE - Reserved for internal processors
30223 * 0xFFFF - Broadcast to all children VFs (only applicable when
30224 * a PF is the requester)
30226 uint16_t encap_async_event_target_id;
30227 uint8_t unused_0[6];
30228 /* This is an encapsulated asynchronous event completion. */
30229 uint32_t encap_async_event_cmpl[4];
30230 } __attribute__((packed));
30232 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
30233 struct hwrm_fwd_async_event_cmpl_output {
30234 /* The specific error status for the command. */
30235 uint16_t error_code;
30236 /* The HWRM command request type. */
30238 /* The sequence ID from the original command. */
30240 /* The length of the response data in number of bytes. */
30242 uint8_t unused_0[7];
30244 * This field is used in Output records to indicate that the output
30245 * is completely written to RAM. This field should be read as '1'
30246 * to indicate that the output has been completely written.
30247 * When writing a command completion or response to an internal processor,
30248 * the order of writes has to be such that this field is written last.
30251 } __attribute__((packed));
30253 /**************************
30254 * hwrm_nvm_raw_write_blk *
30255 **************************/
30258 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
30259 struct hwrm_nvm_raw_write_blk_input {
30260 /* The HWRM command request type. */
30263 * The completion ring to send the completion event on. This should
30264 * be the NQ ID returned from the `nq_alloc` HWRM command.
30266 uint16_t cmpl_ring;
30268 * The sequence ID is used by the driver for tracking multiple
30269 * commands. This ID is treated as opaque data by the firmware and
30270 * the value is returned in the `hwrm_resp_hdr` upon completion.
30274 * The target ID of the command:
30275 * * 0x0-0xFFF8 - The function ID
30276 * * 0xFFF8-0xFFFE - Reserved for internal processors
30279 uint16_t target_id;
30281 * A physical address pointer pointing to a host buffer that the
30282 * command's response data will be written. This can be either a host
30283 * physical address (HPA) or a guest physical address (GPA) and must
30284 * point to a physically contiguous block of memory.
30286 uint64_t resp_addr;
30288 * 64-bit Host Source Address.
30289 * This is the loation of the source data to be written.
30291 uint64_t host_src_addr;
30293 * 32-bit Destination Address.
30294 * This is the NVRAM byte-offset where the source data will be written to.
30296 uint32_t dest_addr;
30297 /* Length of data to be written, in bytes. */
30299 } __attribute__((packed));
30301 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
30302 struct hwrm_nvm_raw_write_blk_output {
30303 /* The specific error status for the command. */
30304 uint16_t error_code;
30305 /* The HWRM command request type. */
30307 /* The sequence ID from the original command. */
30309 /* The length of the response data in number of bytes. */
30311 uint8_t unused_0[7];
30313 * This field is used in Output records to indicate that the output
30314 * is completely written to RAM. This field should be read as '1'
30315 * to indicate that the output has been completely written.
30316 * When writing a command completion or response to an internal processor,
30317 * the order of writes has to be such that this field is written last.
30320 } __attribute__((packed));
30327 /* hwrm_nvm_read_input (size:320b/40B) */
30328 struct hwrm_nvm_read_input {
30329 /* The HWRM command request type. */
30332 * The completion ring to send the completion event on. This should
30333 * be the NQ ID returned from the `nq_alloc` HWRM command.
30335 uint16_t cmpl_ring;
30337 * The sequence ID is used by the driver for tracking multiple
30338 * commands. This ID is treated as opaque data by the firmware and
30339 * the value is returned in the `hwrm_resp_hdr` upon completion.
30343 * The target ID of the command:
30344 * * 0x0-0xFFF8 - The function ID
30345 * * 0xFFF8-0xFFFE - Reserved for internal processors
30348 uint16_t target_id;
30350 * A physical address pointer pointing to a host buffer that the
30351 * command's response data will be written. This can be either a host
30352 * physical address (HPA) or a guest physical address (GPA) and must
30353 * point to a physically contiguous block of memory.
30355 uint64_t resp_addr;
30357 * 64-bit Host Destination Address.
30358 * This is the host address where the data will be written to.
30360 uint64_t host_dest_addr;
30361 /* The 0-based index of the directory entry. */
30363 uint8_t unused_0[2];
30364 /* The NVRAM byte-offset to read from. */
30366 /* The length of the data to be read, in bytes. */
30368 uint8_t unused_1[4];
30369 } __attribute__((packed));
30371 /* hwrm_nvm_read_output (size:128b/16B) */
30372 struct hwrm_nvm_read_output {
30373 /* The specific error status for the command. */
30374 uint16_t error_code;
30375 /* The HWRM command request type. */
30377 /* The sequence ID from the original command. */
30379 /* The length of the response data in number of bytes. */
30381 uint8_t unused_0[7];
30383 * This field is used in Output records to indicate that the output
30384 * is completely written to RAM. This field should be read as '1'
30385 * to indicate that the output has been completely written.
30386 * When writing a command completion or response to an internal processor,
30387 * the order of writes has to be such that this field is written last.
30390 } __attribute__((packed));
30392 /*********************
30393 * hwrm_nvm_raw_dump *
30394 *********************/
30397 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
30398 struct hwrm_nvm_raw_dump_input {
30399 /* The HWRM command request type. */
30402 * The completion ring to send the completion event on. This should
30403 * be the NQ ID returned from the `nq_alloc` HWRM command.
30405 uint16_t cmpl_ring;
30407 * The sequence ID is used by the driver for tracking multiple
30408 * commands. This ID is treated as opaque data by the firmware and
30409 * the value is returned in the `hwrm_resp_hdr` upon completion.
30413 * The target ID of the command:
30414 * * 0x0-0xFFF8 - The function ID
30415 * * 0xFFF8-0xFFFE - Reserved for internal processors
30418 uint16_t target_id;
30420 * A physical address pointer pointing to a host buffer that the
30421 * command's response data will be written. This can be either a host
30422 * physical address (HPA) or a guest physical address (GPA) and must
30423 * point to a physically contiguous block of memory.
30425 uint64_t resp_addr;
30427 * 64-bit Host Destination Address.
30428 * This is the host address where the data will be written to.
30430 uint64_t host_dest_addr;
30431 /* 32-bit NVRAM byte-offset to read from. */
30433 /* Total length of NVRAM contents to be read, in bytes. */
30435 } __attribute__((packed));
30437 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
30438 struct hwrm_nvm_raw_dump_output {
30439 /* The specific error status for the command. */
30440 uint16_t error_code;
30441 /* The HWRM command request type. */
30443 /* The sequence ID from the original command. */
30445 /* The length of the response data in number of bytes. */
30447 uint8_t unused_0[7];
30449 * This field is used in Output records to indicate that the output
30450 * is completely written to RAM. This field should be read as '1'
30451 * to indicate that the output has been completely written.
30452 * When writing a command completion or response to an internal processor,
30453 * the order of writes has to be such that this field is written last.
30456 } __attribute__((packed));
30458 /****************************
30459 * hwrm_nvm_get_dir_entries *
30460 ****************************/
30463 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
30464 struct hwrm_nvm_get_dir_entries_input {
30465 /* The HWRM command request type. */
30468 * The completion ring to send the completion event on. This should
30469 * be the NQ ID returned from the `nq_alloc` HWRM command.
30471 uint16_t cmpl_ring;
30473 * The sequence ID is used by the driver for tracking multiple
30474 * commands. This ID is treated as opaque data by the firmware and
30475 * the value is returned in the `hwrm_resp_hdr` upon completion.
30479 * The target ID of the command:
30480 * * 0x0-0xFFF8 - The function ID
30481 * * 0xFFF8-0xFFFE - Reserved for internal processors
30484 uint16_t target_id;
30486 * A physical address pointer pointing to a host buffer that the
30487 * command's response data will be written. This can be either a host
30488 * physical address (HPA) or a guest physical address (GPA) and must
30489 * point to a physically contiguous block of memory.
30491 uint64_t resp_addr;
30493 * 64-bit Host Destination Address.
30494 * This is the host address where the directory will be written.
30496 uint64_t host_dest_addr;
30497 } __attribute__((packed));
30499 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
30500 struct hwrm_nvm_get_dir_entries_output {
30501 /* The specific error status for the command. */
30502 uint16_t error_code;
30503 /* The HWRM command request type. */
30505 /* The sequence ID from the original command. */
30507 /* The length of the response data in number of bytes. */
30509 uint8_t unused_0[7];
30511 * This field is used in Output records to indicate that the output
30512 * is completely written to RAM. This field should be read as '1'
30513 * to indicate that the output has been completely written.
30514 * When writing a command completion or response to an internal processor,
30515 * the order of writes has to be such that this field is written last.
30518 } __attribute__((packed));
30520 /*************************
30521 * hwrm_nvm_get_dir_info *
30522 *************************/
30525 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
30526 struct hwrm_nvm_get_dir_info_input {
30527 /* The HWRM command request type. */
30530 * The completion ring to send the completion event on. This should
30531 * be the NQ ID returned from the `nq_alloc` HWRM command.
30533 uint16_t cmpl_ring;
30535 * The sequence ID is used by the driver for tracking multiple
30536 * commands. This ID is treated as opaque data by the firmware and
30537 * the value is returned in the `hwrm_resp_hdr` upon completion.
30541 * The target ID of the command:
30542 * * 0x0-0xFFF8 - The function ID
30543 * * 0xFFF8-0xFFFE - Reserved for internal processors
30546 uint16_t target_id;
30548 * A physical address pointer pointing to a host buffer that the
30549 * command's response data will be written. This can be either a host
30550 * physical address (HPA) or a guest physical address (GPA) and must
30551 * point to a physically contiguous block of memory.
30553 uint64_t resp_addr;
30554 } __attribute__((packed));
30556 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
30557 struct hwrm_nvm_get_dir_info_output {
30558 /* The specific error status for the command. */
30559 uint16_t error_code;
30560 /* The HWRM command request type. */
30562 /* The sequence ID from the original command. */
30564 /* The length of the response data in number of bytes. */
30566 /* Number of directory entries in the directory. */
30568 /* Size of each directory entry, in bytes. */
30569 uint32_t entry_length;
30570 uint8_t unused_0[7];
30572 * This field is used in Output records to indicate that the output
30573 * is completely written to RAM. This field should be read as '1'
30574 * to indicate that the output has been completely written.
30575 * When writing a command completion or response to an internal processor,
30576 * the order of writes has to be such that this field is written last.
30579 } __attribute__((packed));
30581 /******************
30583 ******************/
30586 /* hwrm_nvm_write_input (size:384b/48B) */
30587 struct hwrm_nvm_write_input {
30588 /* The HWRM command request type. */
30591 * The completion ring to send the completion event on. This should
30592 * be the NQ ID returned from the `nq_alloc` HWRM command.
30594 uint16_t cmpl_ring;
30596 * The sequence ID is used by the driver for tracking multiple
30597 * commands. This ID is treated as opaque data by the firmware and
30598 * the value is returned in the `hwrm_resp_hdr` upon completion.
30602 * The target ID of the command:
30603 * * 0x0-0xFFF8 - The function ID
30604 * * 0xFFF8-0xFFFE - Reserved for internal processors
30607 uint16_t target_id;
30609 * A physical address pointer pointing to a host buffer that the
30610 * command's response data will be written. This can be either a host
30611 * physical address (HPA) or a guest physical address (GPA) and must
30612 * point to a physically contiguous block of memory.
30614 uint64_t resp_addr;
30616 * 64-bit Host Source Address.
30617 * This is where the source data is.
30619 uint64_t host_src_addr;
30620 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
30623 * Directory ordinal.
30624 * The 0-based instance of the combined Directory Entry Type and Extension.
30626 uint16_t dir_ordinal;
30627 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
30629 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
30632 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
30633 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
30635 uint32_t dir_data_length;
30640 * When this bit is '1', the original active image
30641 * will not be removed. TBD: what purpose is this?
30643 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
30646 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
30647 * If this value is less than the specified data length, it will be ignored.
30648 * The response will contain the actual allocated item length, which may be greater than the requested item length.
30649 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
30650 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
30652 uint32_t dir_item_length;
30654 } __attribute__((packed));
30656 /* hwrm_nvm_write_output (size:128b/16B) */
30657 struct hwrm_nvm_write_output {
30658 /* The specific error status for the command. */
30659 uint16_t error_code;
30660 /* The HWRM command request type. */
30662 /* The sequence ID from the original command. */
30664 /* The length of the response data in number of bytes. */
30667 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
30668 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
30670 uint32_t dir_item_length;
30671 /* The directory index of the created or modified item. */
30675 * This field is used in Output records to indicate that the output
30676 * is completely written to RAM. This field should be read as '1'
30677 * to indicate that the output has been completely written.
30678 * When writing a command completion or response to an internal processor,
30679 * the order of writes has to be such that this field is written last.
30682 } __attribute__((packed));
30684 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
30685 struct hwrm_nvm_write_cmd_err {
30687 * command specific error codes that goes to
30688 * the cmd_err field in Common HWRM Error Response.
30691 /* Unknown error */
30692 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
30693 /* Unable to complete operation due to fragmentation */
30694 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
30695 /* nvm is completely full. */
30696 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
30697 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
30698 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
30699 uint8_t unused_0[7];
30700 } __attribute__((packed));
30702 /*******************
30703 * hwrm_nvm_modify *
30704 *******************/
30707 /* hwrm_nvm_modify_input (size:320b/40B) */
30708 struct hwrm_nvm_modify_input {
30709 /* The HWRM command request type. */
30712 * The completion ring to send the completion event on. This should
30713 * be the NQ ID returned from the `nq_alloc` HWRM command.
30715 uint16_t cmpl_ring;
30717 * The sequence ID is used by the driver for tracking multiple
30718 * commands. This ID is treated as opaque data by the firmware and
30719 * the value is returned in the `hwrm_resp_hdr` upon completion.
30723 * The target ID of the command:
30724 * * 0x0-0xFFF8 - The function ID
30725 * * 0xFFF8-0xFFFE - Reserved for internal processors
30728 uint16_t target_id;
30730 * A physical address pointer pointing to a host buffer that the
30731 * command's response data will be written. This can be either a host
30732 * physical address (HPA) or a guest physical address (GPA) and must
30733 * point to a physically contiguous block of memory.
30735 uint64_t resp_addr;
30737 * 64-bit Host Source Address.
30738 * This is where the modified data is.
30740 uint64_t host_src_addr;
30741 /* 16-bit directory entry index. */
30743 uint8_t unused_0[2];
30744 /* 32-bit NVRAM byte-offset to modify content from. */
30747 * Length of data to be modified, in bytes. The length shall
30751 uint8_t unused_1[4];
30752 } __attribute__((packed));
30754 /* hwrm_nvm_modify_output (size:128b/16B) */
30755 struct hwrm_nvm_modify_output {
30756 /* The specific error status for the command. */
30757 uint16_t error_code;
30758 /* The HWRM command request type. */
30760 /* The sequence ID from the original command. */
30762 /* The length of the response data in number of bytes. */
30764 uint8_t unused_0[7];
30766 * This field is used in Output records to indicate that the output
30767 * is completely written to RAM. This field should be read as '1'
30768 * to indicate that the output has been completely written.
30769 * When writing a command completion or response to an internal processor,
30770 * the order of writes has to be such that this field is written last.
30773 } __attribute__((packed));
30775 /***************************
30776 * hwrm_nvm_find_dir_entry *
30777 ***************************/
30780 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
30781 struct hwrm_nvm_find_dir_entry_input {
30782 /* The HWRM command request type. */
30785 * The completion ring to send the completion event on. This should
30786 * be the NQ ID returned from the `nq_alloc` HWRM command.
30788 uint16_t cmpl_ring;
30790 * The sequence ID is used by the driver for tracking multiple
30791 * commands. This ID is treated as opaque data by the firmware and
30792 * the value is returned in the `hwrm_resp_hdr` upon completion.
30796 * The target ID of the command:
30797 * * 0x0-0xFFF8 - The function ID
30798 * * 0xFFF8-0xFFFE - Reserved for internal processors
30801 uint16_t target_id;
30803 * A physical address pointer pointing to a host buffer that the
30804 * command's response data will be written. This can be either a host
30805 * physical address (HPA) or a guest physical address (GPA) and must
30806 * point to a physically contiguous block of memory.
30808 uint64_t resp_addr;
30811 * This bit must be '1' for the dir_idx_valid field to be
30814 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
30816 /* Directory Entry Index */
30818 /* Directory Entry (Image) Type */
30821 * Directory ordinal.
30822 * The instance of this Directory Type
30824 uint16_t dir_ordinal;
30825 /* The Directory Entry Extension flags. */
30827 /* This value indicates the search option using dir_ordinal. */
30828 uint8_t opt_ordinal;
30829 /* This value indicates the search option using dir_ordinal. */
30830 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
30831 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
30832 /* Equal to specified ordinal value. */
30833 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
30834 /* Greater than or equal to specified ordinal value */
30835 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
30836 /* Greater than specified ordinal value */
30837 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
30838 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
30839 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
30840 uint8_t unused_0[3];
30841 } __attribute__((packed));
30843 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
30844 struct hwrm_nvm_find_dir_entry_output {
30845 /* The specific error status for the command. */
30846 uint16_t error_code;
30847 /* The HWRM command request type. */
30849 /* The sequence ID from the original command. */
30851 /* The length of the response data in number of bytes. */
30853 /* Allocated NVRAM for this directory entry, in bytes. */
30854 uint32_t dir_item_length;
30855 /* Size of the stored data for this directory entry, in bytes. */
30856 uint32_t dir_data_length;
30858 * Firmware version.
30859 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
30862 /* Directory ordinal. */
30863 uint16_t dir_ordinal;
30864 /* Directory Entry Index */
30866 uint8_t unused_0[7];
30868 * This field is used in Output records to indicate that the output
30869 * is completely written to RAM. This field should be read as '1'
30870 * to indicate that the output has been completely written.
30871 * When writing a command completion or response to an internal processor,
30872 * the order of writes has to be such that this field is written last.
30875 } __attribute__((packed));
30877 /****************************
30878 * hwrm_nvm_erase_dir_entry *
30879 ****************************/
30882 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
30883 struct hwrm_nvm_erase_dir_entry_input {
30884 /* The HWRM command request type. */
30887 * The completion ring to send the completion event on. This should
30888 * be the NQ ID returned from the `nq_alloc` HWRM command.
30890 uint16_t cmpl_ring;
30892 * The sequence ID is used by the driver for tracking multiple
30893 * commands. This ID is treated as opaque data by the firmware and
30894 * the value is returned in the `hwrm_resp_hdr` upon completion.
30898 * The target ID of the command:
30899 * * 0x0-0xFFF8 - The function ID
30900 * * 0xFFF8-0xFFFE - Reserved for internal processors
30903 uint16_t target_id;
30905 * A physical address pointer pointing to a host buffer that the
30906 * command's response data will be written. This can be either a host
30907 * physical address (HPA) or a guest physical address (GPA) and must
30908 * point to a physically contiguous block of memory.
30910 uint64_t resp_addr;
30911 /* Directory Entry Index */
30913 uint8_t unused_0[6];
30914 } __attribute__((packed));
30916 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
30917 struct hwrm_nvm_erase_dir_entry_output {
30918 /* The specific error status for the command. */
30919 uint16_t error_code;
30920 /* The HWRM command request type. */
30922 /* The sequence ID from the original command. */
30924 /* The length of the response data in number of bytes. */
30926 uint8_t unused_0[7];
30928 * This field is used in Output records to indicate that the output
30929 * is completely written to RAM. This field should be read as '1'
30930 * to indicate that the output has been completely written.
30931 * When writing a command completion or response to an internal processor,
30932 * the order of writes has to be such that this field is written last.
30935 } __attribute__((packed));
30937 /*************************
30938 * hwrm_nvm_get_dev_info *
30939 *************************/
30942 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
30943 struct hwrm_nvm_get_dev_info_input {
30944 /* The HWRM command request type. */
30947 * The completion ring to send the completion event on. This should
30948 * be the NQ ID returned from the `nq_alloc` HWRM command.
30950 uint16_t cmpl_ring;
30952 * The sequence ID is used by the driver for tracking multiple
30953 * commands. This ID is treated as opaque data by the firmware and
30954 * the value is returned in the `hwrm_resp_hdr` upon completion.
30958 * The target ID of the command:
30959 * * 0x0-0xFFF8 - The function ID
30960 * * 0xFFF8-0xFFFE - Reserved for internal processors
30963 uint16_t target_id;
30965 * A physical address pointer pointing to a host buffer that the
30966 * command's response data will be written. This can be either a host
30967 * physical address (HPA) or a guest physical address (GPA) and must
30968 * point to a physically contiguous block of memory.
30970 uint64_t resp_addr;
30971 } __attribute__((packed));
30973 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
30974 struct hwrm_nvm_get_dev_info_output {
30975 /* The specific error status for the command. */
30976 uint16_t error_code;
30977 /* The HWRM command request type. */
30979 /* The sequence ID from the original command. */
30981 /* The length of the response data in number of bytes. */
30983 /* Manufacturer ID. */
30984 uint16_t manufacturer_id;
30986 uint16_t device_id;
30987 /* Sector size of the NVRAM device. */
30988 uint32_t sector_size;
30989 /* Total size, in bytes of the NVRAM device. */
30990 uint32_t nvram_size;
30991 uint32_t reserved_size;
30992 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
30993 uint32_t available_size;
30994 uint8_t unused_0[3];
30996 * This field is used in Output records to indicate that the output
30997 * is completely written to RAM. This field should be read as '1'
30998 * to indicate that the output has been completely written.
30999 * When writing a command completion or response to an internal processor,
31000 * the order of writes has to be such that this field is written last.
31003 } __attribute__((packed));
31005 /**************************
31006 * hwrm_nvm_mod_dir_entry *
31007 **************************/
31010 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
31011 struct hwrm_nvm_mod_dir_entry_input {
31012 /* The HWRM command request type. */
31015 * The completion ring to send the completion event on. This should
31016 * be the NQ ID returned from the `nq_alloc` HWRM command.
31018 uint16_t cmpl_ring;
31020 * The sequence ID is used by the driver for tracking multiple
31021 * commands. This ID is treated as opaque data by the firmware and
31022 * the value is returned in the `hwrm_resp_hdr` upon completion.
31026 * The target ID of the command:
31027 * * 0x0-0xFFF8 - The function ID
31028 * * 0xFFF8-0xFFFE - Reserved for internal processors
31031 uint16_t target_id;
31033 * A physical address pointer pointing to a host buffer that the
31034 * command's response data will be written. This can be either a host
31035 * physical address (HPA) or a guest physical address (GPA) and must
31036 * point to a physically contiguous block of memory.
31038 uint64_t resp_addr;
31041 * This bit must be '1' for the checksum field to be
31044 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
31045 /* Directory Entry Index */
31048 * Directory ordinal.
31049 * The (0-based) instance of this Directory Type.
31051 uint16_t dir_ordinal;
31052 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
31054 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
31057 * If valid, then this field updates the checksum
31058 * value of the content in the directory entry.
31061 } __attribute__((packed));
31063 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
31064 struct hwrm_nvm_mod_dir_entry_output {
31065 /* The specific error status for the command. */
31066 uint16_t error_code;
31067 /* The HWRM command request type. */
31069 /* The sequence ID from the original command. */
31071 /* The length of the response data in number of bytes. */
31073 uint8_t unused_0[7];
31075 * This field is used in Output records to indicate that the output
31076 * is completely written to RAM. This field should be read as '1'
31077 * to indicate that the output has been completely written.
31078 * When writing a command completion or response to an internal processor,
31079 * the order of writes has to be such that this field is written last.
31082 } __attribute__((packed));
31084 /**************************
31085 * hwrm_nvm_verify_update *
31086 **************************/
31089 /* hwrm_nvm_verify_update_input (size:192b/24B) */
31090 struct hwrm_nvm_verify_update_input {
31091 /* The HWRM command request type. */
31094 * The completion ring to send the completion event on. This should
31095 * be the NQ ID returned from the `nq_alloc` HWRM command.
31097 uint16_t cmpl_ring;
31099 * The sequence ID is used by the driver for tracking multiple
31100 * commands. This ID is treated as opaque data by the firmware and
31101 * the value is returned in the `hwrm_resp_hdr` upon completion.
31105 * The target ID of the command:
31106 * * 0x0-0xFFF8 - The function ID
31107 * * 0xFFF8-0xFFFE - Reserved for internal processors
31110 uint16_t target_id;
31112 * A physical address pointer pointing to a host buffer that the
31113 * command's response data will be written. This can be either a host
31114 * physical address (HPA) or a guest physical address (GPA) and must
31115 * point to a physically contiguous block of memory.
31117 uint64_t resp_addr;
31118 /* Directory Entry Type, to be verified. */
31121 * Directory ordinal.
31122 * The instance of the Directory Type to be verified.
31124 uint16_t dir_ordinal;
31126 * The Directory Entry Extension flags.
31127 * The "UPDATE" extension flag must be set in this value.
31128 * A corresponding directory entry with the same type and ordinal values but *without*
31129 * the "UPDATE" extension flag must also exist. The other flags of the extension must
31130 * be identical between the active and update entries.
31133 uint8_t unused_0[2];
31134 } __attribute__((packed));
31136 /* hwrm_nvm_verify_update_output (size:128b/16B) */
31137 struct hwrm_nvm_verify_update_output {
31138 /* The specific error status for the command. */
31139 uint16_t error_code;
31140 /* The HWRM command request type. */
31142 /* The sequence ID from the original command. */
31144 /* The length of the response data in number of bytes. */
31146 uint8_t unused_0[7];
31148 * This field is used in Output records to indicate that the output
31149 * is completely written to RAM. This field should be read as '1'
31150 * to indicate that the output has been completely written.
31151 * When writing a command completion or response to an internal processor,
31152 * the order of writes has to be such that this field is written last.
31155 } __attribute__((packed));
31157 /***************************
31158 * hwrm_nvm_install_update *
31159 ***************************/
31162 /* hwrm_nvm_install_update_input (size:192b/24B) */
31163 struct hwrm_nvm_install_update_input {
31164 /* The HWRM command request type. */
31167 * The completion ring to send the completion event on. This should
31168 * be the NQ ID returned from the `nq_alloc` HWRM command.
31170 uint16_t cmpl_ring;
31172 * The sequence ID is used by the driver for tracking multiple
31173 * commands. This ID is treated as opaque data by the firmware and
31174 * the value is returned in the `hwrm_resp_hdr` upon completion.
31178 * The target ID of the command:
31179 * * 0x0-0xFFF8 - The function ID
31180 * * 0xFFF8-0xFFFE - Reserved for internal processors
31183 uint16_t target_id;
31185 * A physical address pointer pointing to a host buffer that the
31186 * command's response data will be written. This can be either a host
31187 * physical address (HPA) or a guest physical address (GPA) and must
31188 * point to a physically contiguous block of memory.
31190 uint64_t resp_addr;
31192 * Installation type. If the value 3 through 0xffff is used,
31193 * only packaged items with that type value will be installed and
31194 * conditional installation directives for those packaged items
31195 * will be over-ridden (i.e. 'create' or 'replace' will be treated
31198 uint32_t install_type;
31200 * Perform a normal package installation. Conditional installation
31201 * directives (e.g. 'create' and 'replace') of packaged items
31202 * will be followed.
31204 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
31206 * Install all packaged items regardless of installation directive
31207 * (i.e. treat all packaged items as though they have an installation
31208 * directive of 'install').
31210 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
31211 UINT32_C(0xffffffff)
31212 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
31213 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
31215 /* If set to 1, then securely erase all unused locations in persistent storage. */
31216 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
31219 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
31220 * When combined with erase_unused_space then unspecified images will be securely erased.
31222 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
31225 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
31226 * Allow additional time for this command to complete if this bit is set to 1.
31228 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
31230 uint8_t unused_0[2];
31231 } __attribute__((packed));
31233 /* hwrm_nvm_install_update_output (size:192b/24B) */
31234 struct hwrm_nvm_install_update_output {
31235 /* The specific error status for the command. */
31236 uint16_t error_code;
31237 /* The HWRM command request type. */
31239 /* The sequence ID from the original command. */
31241 /* The length of the response data in number of bytes. */
31244 * Bit-mask of successfully installed items.
31245 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
31246 * A value of 0 indicates that no items were successfully installed.
31248 uint64_t installed_items;
31249 /* result is 8 b */
31251 /* There was no problem with the package installation. */
31252 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
31253 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
31254 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
31255 /* problem_item is 8 b */
31256 uint8_t problem_item;
31257 /* There was no problem with any packaged items. */
31258 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
31260 /* There was a problem with the NVM package itself. */
31261 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
31263 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
31264 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
31265 /* reset_required is 8 b */
31266 uint8_t reset_required;
31268 * No reset is required for installed/updated firmware or
31269 * microcode to take effect.
31271 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
31274 * A PCIe reset (e.g. system reboot) is
31275 * required for newly installed/updated firmware or
31276 * microcode to take effect.
31278 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
31281 * A controller power reset (e.g. system power-cycle) is
31282 * required for newly installed/updated firmware or
31283 * microcode to take effect. Some newly installed/updated
31284 * firmware or microcode may still take effect upon the
31287 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
31289 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
31290 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
31291 uint8_t unused_0[4];
31293 * This field is used in Output records to indicate that the output
31294 * is completely written to RAM. This field should be read as '1'
31295 * to indicate that the output has been completely written.
31296 * When writing a command completion or response to an internal processor,
31297 * the order of writes has to be such that this field is written last.
31300 } __attribute__((packed));
31302 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
31303 struct hwrm_nvm_install_update_cmd_err {
31305 * command specific error codes that goes to
31306 * the cmd_err field in Common HWRM Error Response.
31309 /* Unknown error */
31310 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31311 /* Unable to complete operation due to fragmentation */
31312 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
31313 /* nvm is completely full. */
31314 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
31315 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
31316 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
31317 uint8_t unused_0[7];
31318 } __attribute__((packed));
31320 /******************
31322 ******************/
31325 /* hwrm_nvm_flush_input (size:128b/16B) */
31326 struct hwrm_nvm_flush_input {
31327 /* The HWRM command request type. */
31330 * The completion ring to send the completion event on. This should
31331 * be the NQ ID returned from the `nq_alloc` HWRM command.
31333 uint16_t cmpl_ring;
31335 * The sequence ID is used by the driver for tracking multiple
31336 * commands. This ID is treated as opaque data by the firmware and
31337 * the value is returned in the `hwrm_resp_hdr` upon completion.
31341 * The target ID of the command:
31342 * * 0x0-0xFFF8 - The function ID
31343 * * 0xFFF8-0xFFFE - Reserved for internal processors
31346 uint16_t target_id;
31348 * A physical address pointer pointing to a host buffer that the
31349 * command's response data will be written. This can be either a host
31350 * physical address (HPA) or a guest physical address (GPA) and must
31351 * point to a physically contiguous block of memory.
31353 uint64_t resp_addr;
31354 } __attribute__((packed));
31356 /* hwrm_nvm_flush_output (size:128b/16B) */
31357 struct hwrm_nvm_flush_output {
31358 /* The specific error status for the command. */
31359 uint16_t error_code;
31360 /* The HWRM command request type. */
31362 /* The sequence ID from the original command. */
31364 /* The length of the response data in number of bytes. */
31366 uint8_t unused_0[7];
31368 * This field is used in Output records to indicate that the output
31369 * is completely written to RAM. This field should be read as '1'
31370 * to indicate that the output has been completely written.
31371 * When writing a command completion or response to an internal processor,
31372 * the order of writes has to be such that this field is written last.
31375 } __attribute__((packed));
31377 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
31378 struct hwrm_nvm_flush_cmd_err {
31380 * command specific error codes that goes to
31381 * the cmd_err field in Common HWRM Error Response.
31384 /* Unknown error */
31385 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31386 /* flush could not be performed */
31387 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
31388 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
31389 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
31390 uint8_t unused_0[7];
31391 } __attribute__((packed));
31393 /*************************
31394 * hwrm_nvm_get_variable *
31395 *************************/
31398 /* hwrm_nvm_get_variable_input (size:320b/40B) */
31399 struct hwrm_nvm_get_variable_input {
31400 /* The HWRM command request type. */
31403 * The completion ring to send the completion event on. This should
31404 * be the NQ ID returned from the `nq_alloc` HWRM command.
31406 uint16_t cmpl_ring;
31408 * The sequence ID is used by the driver for tracking multiple
31409 * commands. This ID is treated as opaque data by the firmware and
31410 * the value is returned in the `hwrm_resp_hdr` upon completion.
31414 * The target ID of the command:
31415 * * 0x0-0xFFF8 - The function ID
31416 * * 0xFFF8-0xFFFE - Reserved for internal processors
31419 uint16_t target_id;
31421 * A physical address pointer pointing to a host buffer that the
31422 * command's response data will be written. This can be either a host
31423 * physical address (HPA) or a guest physical address (GPA) and must
31424 * point to a physically contiguous block of memory.
31426 uint64_t resp_addr;
31428 * This is the host address where
31429 * nvm variable will be stored
31431 uint64_t dest_data_addr;
31432 /* size of data in bits */
31434 /* nvm cfg option number */
31435 uint16_t option_num;
31437 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
31439 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
31441 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
31442 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
31444 * Number of dimensions for this nvm configuration variable.
31445 * This value indicates how many of the indexN values to use.
31446 * A value of 0 means that none of the indexN values are valid.
31447 * A value of 1 requires at index0 is valued, a value of 2
31448 * requires that index0 and index1 are valid, and so forth
31450 uint16_t dimensions;
31451 /* index for the 1st dimensions */
31453 /* index for the 2nd dimensions */
31455 /* index for the 3rd dimensions */
31457 /* index for the 4th dimensions */
31461 * When this bit is set to 1, the factory default value will be returned,
31462 * 0 returns the operational value.
31464 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
31467 } __attribute__((packed));
31469 /* hwrm_nvm_get_variable_output (size:128b/16B) */
31470 struct hwrm_nvm_get_variable_output {
31471 /* The specific error status for the command. */
31472 uint16_t error_code;
31473 /* The HWRM command request type. */
31475 /* The sequence ID from the original command. */
31477 /* The length of the response data in number of bytes. */
31479 /* size of data of the actual variable retrieved in bits */
31482 * option_num is the option number for the data retrieved. It is possible in the
31483 * future that the option number returned would be different than requested. This
31484 * condition could occur if an option is deprecated and a new option id is defined
31485 * with similar characteristics, but has a slightly different definition. This
31486 * also makes it convenient for the caller to identify the variable result with
31487 * the option id from the response.
31489 uint16_t option_num;
31491 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
31493 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
31495 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
31496 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
31497 uint8_t unused_0[3];
31499 * This field is used in Output records to indicate that the output
31500 * is completely written to RAM. This field should be read as '1'
31501 * to indicate that the output has been completely written.
31502 * When writing a command completion or response to an internal processor,
31503 * the order of writes has to be such that this field is written last.
31506 } __attribute__((packed));
31508 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
31509 struct hwrm_nvm_get_variable_cmd_err {
31511 * command specific error codes that goes to
31512 * the cmd_err field in Common HWRM Error Response.
31515 /* Unknown error */
31516 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31517 /* variable does not exist */
31518 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
31519 /* configuration is corrupted and the variable cannot be saved */
31520 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
31521 /* length specified is too small */
31522 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
31523 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
31524 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
31525 uint8_t unused_0[7];
31526 } __attribute__((packed));
31528 /*************************
31529 * hwrm_nvm_set_variable *
31530 *************************/
31533 /* hwrm_nvm_set_variable_input (size:320b/40B) */
31534 struct hwrm_nvm_set_variable_input {
31535 /* The HWRM command request type. */
31538 * The completion ring to send the completion event on. This should
31539 * be the NQ ID returned from the `nq_alloc` HWRM command.
31541 uint16_t cmpl_ring;
31543 * The sequence ID is used by the driver for tracking multiple
31544 * commands. This ID is treated as opaque data by the firmware and
31545 * the value is returned in the `hwrm_resp_hdr` upon completion.
31549 * The target ID of the command:
31550 * * 0x0-0xFFF8 - The function ID
31551 * * 0xFFF8-0xFFFE - Reserved for internal processors
31554 uint16_t target_id;
31556 * A physical address pointer pointing to a host buffer that the
31557 * command's response data will be written. This can be either a host
31558 * physical address (HPA) or a guest physical address (GPA) and must
31559 * point to a physically contiguous block of memory.
31561 uint64_t resp_addr;
31563 * This is the host address where
31564 * nvm variable will be copied from
31566 uint64_t src_data_addr;
31567 /* size of data in bits */
31569 /* nvm cfg option number */
31570 uint16_t option_num;
31572 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
31574 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
31576 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
31577 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
31579 * Number of dimensions for this nvm configuration variable.
31580 * This value indicates how many of the indexN values to use.
31581 * A value of 0 means that none of the indexN values are valid.
31582 * A value of 1 requires at index0 is valued, a value of 2
31583 * requires that index0 and index1 are valid, and so forth
31585 uint16_t dimensions;
31586 /* index for the 1st dimensions */
31588 /* index for the 2nd dimensions */
31590 /* index for the 3rd dimensions */
31592 /* index for the 4th dimensions */
31595 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
31596 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
31598 /* encryption method */
31599 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
31601 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
31602 /* No encryption. */
31603 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
31604 (UINT32_C(0x0) << 1)
31605 /* one-way encryption. */
31606 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
31607 (UINT32_C(0x1) << 1)
31608 /* symmetric AES256 encryption. */
31609 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
31610 (UINT32_C(0x2) << 1)
31611 /* SHA1 digest appended to plaintext contents, for authentication */
31612 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
31613 (UINT32_C(0x3) << 1)
31614 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
31615 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
31617 } __attribute__((packed));
31619 /* hwrm_nvm_set_variable_output (size:128b/16B) */
31620 struct hwrm_nvm_set_variable_output {
31621 /* The specific error status for the command. */
31622 uint16_t error_code;
31623 /* The HWRM command request type. */
31625 /* The sequence ID from the original command. */
31627 /* The length of the response data in number of bytes. */
31629 uint8_t unused_0[7];
31631 * This field is used in Output records to indicate that the output
31632 * is completely written to RAM. This field should be read as '1'
31633 * to indicate that the output has been completely written.
31634 * When writing a command completion or response to an internal processor,
31635 * the order of writes has to be such that this field is written last.
31638 } __attribute__((packed));
31640 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
31641 struct hwrm_nvm_set_variable_cmd_err {
31643 * command specific error codes that goes to
31644 * the cmd_err field in Common HWRM Error Response.
31647 /* Unknown error */
31648 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31649 /* variable does not exist */
31650 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
31651 /* configuration is corrupted and the variable cannot be saved */
31652 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
31653 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
31654 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
31655 uint8_t unused_0[7];
31656 } __attribute__((packed));
31658 /****************************
31659 * hwrm_nvm_validate_option *
31660 ****************************/
31663 /* hwrm_nvm_validate_option_input (size:320b/40B) */
31664 struct hwrm_nvm_validate_option_input {
31665 /* The HWRM command request type. */
31668 * The completion ring to send the completion event on. This should
31669 * be the NQ ID returned from the `nq_alloc` HWRM command.
31671 uint16_t cmpl_ring;
31673 * The sequence ID is used by the driver for tracking multiple
31674 * commands. This ID is treated as opaque data by the firmware and
31675 * the value is returned in the `hwrm_resp_hdr` upon completion.
31679 * The target ID of the command:
31680 * * 0x0-0xFFF8 - The function ID
31681 * * 0xFFF8-0xFFFE - Reserved for internal processors
31684 uint16_t target_id;
31686 * A physical address pointer pointing to a host buffer that the
31687 * command's response data will be written. This can be either a host
31688 * physical address (HPA) or a guest physical address (GPA) and must
31689 * point to a physically contiguous block of memory.
31691 uint64_t resp_addr;
31693 * This is the host address where
31694 * nvm variable will be copied from
31696 uint64_t src_data_addr;
31697 /* size of data in bits */
31699 /* nvm cfg option number */
31700 uint16_t option_num;
31702 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
31705 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
31707 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
31708 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
31710 * Number of dimensions for this nvm configuration variable.
31711 * This value indicates how many of the indexN values to use.
31712 * A value of 0 means that none of the indexN values are valid.
31713 * A value of 1 requires at index0 is valued, a value of 2
31714 * requires that index0 and index1 are valid, and so forth
31716 uint16_t dimensions;
31717 /* index for the 1st dimensions */
31719 /* index for the 2nd dimensions */
31721 /* index for the 3rd dimensions */
31723 /* index for the 4th dimensions */
31725 uint8_t unused_0[2];
31726 } __attribute__((packed));
31728 /* hwrm_nvm_validate_option_output (size:128b/16B) */
31729 struct hwrm_nvm_validate_option_output {
31730 /* The specific error status for the command. */
31731 uint16_t error_code;
31732 /* The HWRM command request type. */
31734 /* The sequence ID from the original command. */
31736 /* The length of the response data in number of bytes. */
31739 /* indicates that the value provided for the option is not matching with the saved data. */
31740 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
31741 /* indicates that the value provided for the option is matching the saved data. */
31742 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
31743 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
31744 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
31745 uint8_t unused_0[6];
31747 * This field is used in Output records to indicate that the output
31748 * is completely written to RAM. This field should be read as '1'
31749 * to indicate that the output has been completely written.
31750 * When writing a command completion or response to an internal processor,
31751 * the order of writes has to be such that this field is written last.
31754 } __attribute__((packed));
31756 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
31757 struct hwrm_nvm_validate_option_cmd_err {
31759 * command specific error codes that goes to
31760 * the cmd_err field in Common HWRM Error Response.
31763 /* Unknown error */
31764 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
31765 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
31766 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
31767 uint8_t unused_0[7];
31768 } __attribute__((packed));
31770 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */