1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2019 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_RESET UINT32_C(0x5e)
345 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
346 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
347 /* Reserved for future use. */
348 #define HWRM_RESERVED5 UINT32_C(0x64)
349 /* Reserved for future use. */
350 #define HWRM_RESERVED6 UINT32_C(0x65)
351 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
352 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
353 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
354 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
355 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
356 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
357 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
358 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
359 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
360 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
361 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
362 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
364 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
366 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
367 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
368 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
369 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
371 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
373 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
375 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
376 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
377 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
378 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
379 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
380 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
381 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
382 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
383 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
384 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
385 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
386 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
387 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
388 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
389 #define HWRM_FW_RESET UINT32_C(0xc0)
390 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
391 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
392 #define HWRM_FW_SYNC UINT32_C(0xc3)
393 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
394 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
395 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
396 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
398 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
400 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
402 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
404 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
406 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
407 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
408 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
409 #define HWRM_FWD_RESP UINT32_C(0xd2)
410 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
411 #define HWRM_OEM_CMD UINT32_C(0xd4)
412 /* Tells the fw to run PRBS test on a given port and lane. */
413 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
414 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
415 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
416 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
417 /* Tells the fw to collect dsc dump on a given port and lane. */
418 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
419 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
420 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
421 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
422 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
423 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
424 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
425 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
427 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
429 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
431 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
433 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
435 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
437 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
439 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
441 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
443 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
445 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
447 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
449 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
451 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
453 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
455 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
457 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
459 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
461 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
463 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
464 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
465 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
466 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
468 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
470 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
472 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
474 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
476 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
478 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
480 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
482 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
484 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
486 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
488 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
490 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
492 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
494 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
496 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
498 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
500 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
502 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
504 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
506 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
508 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
510 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
512 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
514 #define HWRM_CFA_TFLIB UINT32_C(0x125)
515 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
516 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
517 /* Engine CKV - Add a new CKEK used to encrypt keys. */
518 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
519 /* Engine CKV - Delete a previously added CKEK. */
520 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
521 /* Engine CKV - Add a new key to the key vault. */
522 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
523 /* Engine CKV - Delete a key from the key vault. */
524 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
525 /* Engine CKV - Delete all keys from the key vault. */
526 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
527 /* Engine CKV - Get random data. */
528 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
529 /* Engine CKV - Generate and encrypt a new AES key. */
530 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
531 /* Engine CKV - Configure a label index with a label value. */
532 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
533 /* Engine CKV - Query a label */
534 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
535 /* Engine - Query the available queue groups configuration. */
536 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
537 /* Engine - Query the queue groups assigned to a function. */
538 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
539 /* Engine - Query the available queue group meter profile configuration. */
540 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
541 /* Engine - Query the configuration of a queue group meter profile. */
542 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
543 /* Engine - Allocate a queue group meter profile. */
544 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
545 /* Engine - Free a queue group meter profile. */
546 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
547 /* Engine - Query the meters assigned to a queue group. */
548 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
549 /* Engine - Bind a queue group meter profile to a queue group. */
550 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
551 /* Engine - Unbind a queue group meter profile from a queue group. */
552 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
553 /* Engine - Bind a queue group to a function. */
554 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
555 /* Engine - Query the scheduling group configuration. */
556 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
557 /* Engine - Query the queue groups assigned to a scheduling group. */
558 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
559 /* Engine - Query the configuration of a scheduling group's meter profiles. */
560 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
561 /* Engine - Configure a scheduling group's meter profiles. */
562 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
563 /* Engine - Bind a queue group to a scheduling group. */
564 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
565 /* Engine - Unbind a queue group from its scheduling group. */
566 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
567 /* Engine - Query the Engine configuration. */
568 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
569 /* Engine - Configure the statistics accumulator for an Engine. */
570 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
571 /* Engine - Clear the statistics accumulator for an Engine. */
572 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
573 /* Engine - Query the statistics accumulator for an Engine. */
574 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
575 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
576 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
577 /* Engine - Allocate an Engine RQ. */
578 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
579 /* Engine - Free an Engine RQ. */
580 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
581 /* Engine - Allocate an Engine CQ. */
582 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
583 /* Engine - Free an Engine CQ. */
584 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
585 /* Engine - Allocate an NQ. */
586 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
587 /* Engine - Free an NQ. */
588 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
589 /* Engine - Set the on-die RQE credit update location. */
590 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
591 /* Engine - Query the engine function configuration. */
592 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
594 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
596 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
598 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
600 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
602 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
603 /* Configures the BW of any VF */
604 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
605 /* Queries the BW of any VF */
606 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
607 /* Queries pf ids belong to specified host(s) */
608 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
610 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
612 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
614 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
616 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
618 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
620 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
621 /* Returns the current value of a free running counter from the device. */
622 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
624 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
626 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
628 * Tells the fw to run the DMA read from the host and DMA write
631 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
633 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
635 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
637 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
639 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
640 #define HWRM_DBG_DUMP UINT32_C(0xff14)
642 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
644 #define HWRM_DBG_CFG UINT32_C(0xff16)
646 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
648 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
650 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
652 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
654 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
656 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
658 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
660 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
662 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
663 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
664 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
665 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
666 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
667 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
668 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
669 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
670 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
671 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
672 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
673 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
674 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
675 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
676 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
677 #define HWRM_NVM_READ UINT32_C(0xfffd)
678 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
679 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
680 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
681 uint16_t unused_0[3];
685 /* ret_codes (size:64b/8B) */
688 /* Request was successfully executed by the HWRM. */
689 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
690 /* The HWRM failed to execute the request. */
691 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
693 * The request contains invalid argument(s) or input
696 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
698 * The requester is not allowed to access the requested
699 * resource. This error code shall be provided in a
700 * response to a request to query or modify an existing
701 * resource that is not accessible by the requester.
703 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
705 * The HWRM is unable to allocate the requested resource.
706 * This code only applies to requests for HWRM resource
709 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
711 * Invalid combination of flags is specified in the
714 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
716 * Invalid combination of enables fields is specified in
719 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
721 * Request contains a required TLV that is not supported by
722 * the installed version of firmware.
724 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
726 * No firmware buffer available to accept the request. Driver
727 * should retry the request.
729 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
731 * This error code is only reported by firmware when some
732 * sub-option of a supported HWRM command is unsupported.
734 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
736 * This error code is only reported by firmware when the specific
737 * request is not able to process when the HOT reset in progress.
739 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
741 * This error code is only reported by firmware when the registered
742 * driver instances are not capable of hot reset.
744 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
746 * This error code is only reported by the firmware when during
747 * flow allocation when a request for a flow counter fails because
748 * the number of flow counters are exhausted.
750 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
752 * This error code is only reported by firmware when the registered
753 * driver instances requested to offloaded a flow but was unable to because
754 * the requested key's hash collides with the installed keys.
756 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
758 * This error code is only reported by firmware when the registered
759 * driver instances requested to offloaded a flow but was unable to because
760 * the same key has already been installed.
762 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
764 * Generic HWRM execution error that represents an
767 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
769 * Firmware is unable to service the request at the present time. Caller
770 * may try again later.
772 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
774 * This value indicates that the HWRM response is in TLV format and
775 * should be interpreted as one or more TLVs starting with the
776 * hwrm_resp_hdr TLV. This value is not an indication of any error
777 * by itself, just an indication that the response should be parsed
778 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
780 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
782 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
783 /* Unsupported or invalid command */
784 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
785 #define HWRM_ERR_CODE_LAST \
786 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
787 uint16_t unused_0[3];
791 /* hwrm_err_output (size:128b/16B) */
792 struct hwrm_err_output {
794 * Pass/Fail or error type
796 * Note: receiver to verify the in parameters, and fail the call
797 * with an error when appropriate
800 /* This field returns the type of original request. */
802 /* This field provides original sequence number of the command. */
805 * This field is the length of the response in bytes. The
806 * last byte of the response is a valid flag that will read
807 * as '1' when the command has been completely written to
811 /* debug info for this error response. */
813 /* debug info for this error response. */
816 * In the case of an error response, command specific error
817 * code is returned in this field.
821 * This field is used in Output records to indicate that the output
822 * is completely written to RAM. This field should be read as '1'
823 * to indicate that the output has been completely written.
824 * When writing a command completion or response to an internal processor,
825 * the order of writes has to be such that this field is written last.
830 * Following is the signature for HWRM message field that indicates not
831 * applicable (All F's). Need to cast it the size of the field if needed.
833 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
834 /* hwrm_func_buf_rgtr */
835 #define HWRM_MAX_REQ_LEN 128
836 /* hwrm_cfa_flow_info */
837 #define HWRM_MAX_RESP_LEN 704
838 /* 7 bit indirection table index. */
839 #define HW_HASH_INDEX_SIZE 0x80
840 #define HW_HASH_KEY_SIZE 40
841 /* valid key for HWRM response */
842 #define HWRM_RESP_VALID_KEY 1
843 /* Reserved for BONO processor */
844 #define HWRM_TARGET_ID_BONO 0xFFF8
845 /* Reserved for KONG processor */
846 #define HWRM_TARGET_ID_KONG 0xFFF9
847 /* Reserved for APE processor */
848 #define HWRM_TARGET_ID_APE 0xFFFA
850 * This value will be used by tools for User-space HWRM Interface.
851 * When tool execute any HWRM command with this target_id, firmware
852 * will copy the response and/or data payload via register space instead
855 #define HWRM_TARGET_ID_TOOLS 0xFFFD
856 #define HWRM_VERSION_MAJOR 1
857 #define HWRM_VERSION_MINOR 10
858 #define HWRM_VERSION_UPDATE 1
859 /* non-zero means beta version */
860 #define HWRM_VERSION_RSVD 6
861 #define HWRM_VERSION_STR "1.10.1.6"
868 /* hwrm_ver_get_input (size:192b/24B) */
869 struct hwrm_ver_get_input {
870 /* The HWRM command request type. */
873 * The completion ring to send the completion event on. This should
874 * be the NQ ID returned from the `nq_alloc` HWRM command.
878 * The sequence ID is used by the driver for tracking multiple
879 * commands. This ID is treated as opaque data by the firmware and
880 * the value is returned in the `hwrm_resp_hdr` upon completion.
884 * The target ID of the command:
885 * * 0x0-0xFFF8 - The function ID
886 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
887 * * 0xFFFD - Reserved for user-space HWRM interface
892 * A physical address pointer pointing to a host buffer that the
893 * command's response data will be written. This can be either a host
894 * physical address (HPA) or a guest physical address (GPA) and must
895 * point to a physically contiguous block of memory.
899 * This field represents the major version of HWRM interface
900 * specification supported by the driver HWRM implementation.
901 * The interface major version is intended to change only when
902 * non backward compatible changes are made to the HWRM
903 * interface specification.
905 uint8_t hwrm_intf_maj;
907 * This field represents the minor version of HWRM interface
908 * specification supported by the driver HWRM implementation.
909 * A change in interface minor version is used to reflect
910 * significant backward compatible modification to HWRM
911 * interface specification.
912 * This can be due to addition or removal of functionality.
913 * HWRM interface specifications with the same major version
914 * but different minor versions are compatible.
916 uint8_t hwrm_intf_min;
918 * This field represents the update version of HWRM interface
919 * specification supported by the driver HWRM implementation.
920 * The interface update version is used to reflect minor
921 * changes or bug fixes to a released HWRM interface
924 uint8_t hwrm_intf_upd;
928 /* hwrm_ver_get_output (size:1408b/176B) */
929 struct hwrm_ver_get_output {
930 /* The specific error status for the command. */
932 /* The HWRM command request type. */
934 /* The sequence ID from the original command. */
936 /* The length of the response data in number of bytes. */
939 * This field represents the major version of HWRM interface
940 * specification supported by the HWRM implementation.
941 * The interface major version is intended to change only when
942 * non backward compatible changes are made to the HWRM
943 * interface specification.
944 * A HWRM implementation that is compliant with this
945 * specification shall provide value of 1 in this field.
947 uint8_t hwrm_intf_maj_8b;
949 * This field represents the minor version of HWRM interface
950 * specification supported by the HWRM implementation.
951 * A change in interface minor version is used to reflect
952 * significant backward compatible modification to HWRM
953 * interface specification.
954 * This can be due to addition or removal of functionality.
955 * HWRM interface specifications with the same major version
956 * but different minor versions are compatible.
957 * A HWRM implementation that is compliant with this
958 * specification shall provide value of 2 in this field.
960 uint8_t hwrm_intf_min_8b;
962 * This field represents the update version of HWRM interface
963 * specification supported by the HWRM implementation.
964 * The interface update version is used to reflect minor
965 * changes or bug fixes to a released HWRM interface
967 * A HWRM implementation that is compliant with this
968 * specification shall provide value of 2 in this field.
970 uint8_t hwrm_intf_upd_8b;
971 uint8_t hwrm_intf_rsvd_8b;
973 * This field represents the major version of HWRM firmware.
974 * A change in firmware major version represents a major
977 uint8_t hwrm_fw_maj_8b;
979 * This field represents the minor version of HWRM firmware.
980 * A change in firmware minor version represents significant
981 * firmware functionality changes.
983 uint8_t hwrm_fw_min_8b;
985 * This field represents the build version of HWRM firmware.
986 * A change in firmware build version represents bug fixes
987 * to a released firmware.
989 uint8_t hwrm_fw_bld_8b;
991 * This field is a reserved field. This field can be used to
992 * represent firmware branches or customer specific releases
993 * tied to a specific (major,minor,update) version of the
996 uint8_t hwrm_fw_rsvd_8b;
998 * This field represents the major version of mgmt firmware.
999 * A change in major version represents a major release.
1001 uint8_t mgmt_fw_maj_8b;
1003 * This field represents the minor version of mgmt firmware.
1004 * A change in minor version represents significant
1005 * functionality changes.
1007 uint8_t mgmt_fw_min_8b;
1009 * This field represents the build version of mgmt firmware.
1010 * A change in update version represents bug fixes.
1012 uint8_t mgmt_fw_bld_8b;
1014 * This field is a reserved field. This field can be used to
1015 * represent firmware branches or customer specific releases
1016 * tied to a specific (major,minor,update) version
1018 uint8_t mgmt_fw_rsvd_8b;
1020 * This field represents the major version of network
1022 * A change in major version represents a major release.
1024 uint8_t netctrl_fw_maj_8b;
1026 * This field represents the minor version of network
1028 * A change in minor version represents significant
1029 * functionality changes.
1031 uint8_t netctrl_fw_min_8b;
1033 * This field represents the build version of network
1035 * A change in update version represents bug fixes.
1037 uint8_t netctrl_fw_bld_8b;
1039 * This field is a reserved field. This field can be used to
1040 * represent firmware branches or customer specific releases
1041 * tied to a specific (major,minor,update) version
1043 uint8_t netctrl_fw_rsvd_8b;
1045 * This field is used to indicate device's capabilities and
1048 uint32_t dev_caps_cfg;
1050 * If set to 1, then secure firmware update behavior
1052 * If set to 0, then secure firmware update behavior is
1055 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1058 * If set to 1, then firmware based DCBX agent is supported.
1059 * If set to 0, then firmware based DCBX agent capability
1060 * is not supported on this device.
1062 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1065 * If set to 1, then HWRM short command format is supported.
1066 * If set to 0, then HWRM short command format is not supported.
1068 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1071 * If set to 1, then HWRM short command format is required.
1072 * If set to 0, then HWRM short command format is not required.
1074 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1077 * If set to 1, then the KONG host mailbox channel is supported.
1078 * If set to 0, then the KONG host mailbox channel is not supported.
1079 * By default, this flag should be 0 for older version of core firmware.
1081 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1084 * If set to 1, then the 64bit flow handle is supported in addition to the
1085 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1086 * supported. By default, this flag should be 0 for older version of core firmware.
1088 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1091 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1092 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1093 * If set to 0, then filter types not supported.
1094 * By default, this flag should be 0 for older version of core firmware.
1096 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1099 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1100 * If set to 0, firmware can't supported virtio vSwitch offload model.
1101 * By default, this flag should be 0 for older version of core firmware.
1103 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1106 * If set to 1, firmware is capable to support trusted VF.
1107 * If set to 0, firmware is not capable to support trusted VF.
1108 * By default, this flag should be 0 for older version of core firmware.
1110 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1113 * If set to 1, firmware is capable to support flow aging.
1114 * If set to 0, firmware is not capable to support flow aging.
1115 * By default, this flag should be 0 for older version of core firmware.
1117 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1120 * If set to 1, firmware is capable to support advanced flow counters like,
1121 * Meter drop counters and EEM counters.
1122 * If set to 0, firmware is not capable to support advanced flow counters.
1123 * By default, this flag should be 0 for older version of core firmware.
1125 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1128 * If set to 1, the firmware is able to support the use of the CFA
1129 * Extended Exact Match(EEM) feature.
1130 * If set to 0, firmware is not capable to support the use of the
1132 * By default, this flag should be 0 for older version of core firmware.
1134 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1137 * If set to 1, the firmware is able to support advance CFA flow management
1138 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1139 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1141 * By default, this flag should be 0 for older version of core firmware.
1143 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1146 * If set to 1, the firmware is able to support TFLIB features.
1147 * If set to 0, then the firmware doesn’t support TFLIB features.
1148 * By default, this flag should be 0 for older version of core firmware.
1150 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1153 * This field represents the major version of RoCE firmware.
1154 * A change in major version represents a major release.
1156 uint8_t roce_fw_maj_8b;
1158 * This field represents the minor version of RoCE firmware.
1159 * A change in minor version represents significant
1160 * functionality changes.
1162 uint8_t roce_fw_min_8b;
1164 * This field represents the build version of RoCE firmware.
1165 * A change in update version represents bug fixes.
1167 uint8_t roce_fw_bld_8b;
1169 * This field is a reserved field. This field can be used to
1170 * represent firmware branches or customer specific releases
1171 * tied to a specific (major,minor,update) version
1173 uint8_t roce_fw_rsvd_8b;
1175 * This field represents the name of HWRM FW (ASCII chars
1176 * with NULL at the end).
1178 char hwrm_fw_name[16];
1180 * This field represents the name of mgmt FW (ASCII chars
1181 * with NULL at the end).
1183 char mgmt_fw_name[16];
1185 * This field represents the name of network control
1186 * firmware (ASCII chars with NULL at the end).
1188 char netctrl_fw_name[16];
1189 /* This field represents the active board package name. */
1190 char active_pkg_name[16];
1192 * This field represents the name of RoCE FW (ASCII chars
1193 * with NULL at the end).
1195 char roce_fw_name[16];
1196 /* This field returns the chip number. */
1198 /* This field returns the revision of chip. */
1200 /* This field returns the chip metal number. */
1202 /* This field returns the bond id of the chip. */
1203 uint8_t chip_bond_id;
1204 /* This value indicates the type of platform used for chip implementation. */
1205 uint8_t chip_platform_type;
1207 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1208 /* FPGA platform of the chip. */
1209 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1210 /* Palladium platform of the chip. */
1211 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1212 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1213 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1215 * This field returns the maximum value of request window that
1216 * is supported by the HWRM. The request window is mapped
1217 * into device address space using MMIO.
1219 uint16_t max_req_win_len;
1221 * This field returns the maximum value of response buffer in
1224 uint16_t max_resp_len;
1226 * This field returns the default request timeout value in
1229 uint16_t def_req_timeout;
1231 * This field will indicate if any subsystems is not fully
1236 * If set to 1, it will indicate to host drivers that firmware is
1237 * not ready to start full blown HWRM commands. Host drivers should
1238 * re-try HWRM_VER_GET with some timeout period. The timeout period
1239 * can be selected up to 5 seconds.
1240 * For Example, PCIe hot-plug:
1241 * Hot plug timing is system dependent. It generally takes up to
1242 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1243 * If set to 0, device is ready to accept all HWRM commands.
1245 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1247 * If set to 1, external version present.
1248 * If set to 0, external version not present.
1250 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1251 uint8_t unused_0[2];
1253 * For backward compatibility this field must be set to 1.
1254 * Older drivers might look for this field to be 1 before
1255 * processing the message.
1259 * This field represents the major version of HWRM interface
1260 * specification supported by the HWRM implementation.
1261 * The interface major version is intended to change only when
1262 * non backward compatible changes are made to the HWRM
1263 * interface specification. A HWRM implementation that is
1264 * compliant with this specification shall provide value of 1
1267 uint16_t hwrm_intf_major;
1269 * This field represents the minor version of HWRM interface
1270 * specification supported by the HWRM implementation.
1271 * A change in interface minor version is used to reflect
1272 * significant backward compatible modification to HWRM
1273 * interface specification. This can be due to addition or
1274 * removal of functionality. HWRM interface specifications
1275 * with the same major version but different minor versions are
1276 * compatible. A HWRM implementation that is compliant with
1277 * this specification shall provide value of 2 in this field.
1279 uint16_t hwrm_intf_minor;
1281 * This field represents the update version of HWRM interface
1282 * specification supported by the HWRM implementation. The
1283 * interface update version is used to reflect minor changes or
1284 * bug fixes to a released HWRM interface specification.
1285 * A HWRM implementation that is compliant with this
1286 * specification shall provide value of 2 in this field.
1288 uint16_t hwrm_intf_build;
1290 * This field represents the patch version of HWRM interface
1291 * specification supported by the HWRM implementation.
1293 uint16_t hwrm_intf_patch;
1295 * This field represents the major version of HWRM firmware.
1296 * A change in firmware major version represents a major
1299 uint16_t hwrm_fw_major;
1301 * This field represents the minor version of HWRM firmware.
1302 * A change in firmware minor version represents significant
1303 * firmware functionality changes.
1305 uint16_t hwrm_fw_minor;
1307 * This field represents the build version of HWRM firmware.
1308 * A change in firmware build version represents bug fixes to
1309 * a released firmware.
1311 uint16_t hwrm_fw_build;
1313 * This field is a reserved field.
1314 * This field can be used to represent firmware branches or customer
1315 * specific releases tied to a specific (major,minor,update) version
1316 * of the HWRM firmware.
1318 uint16_t hwrm_fw_patch;
1320 * This field represents the major version of mgmt firmware.
1321 * A change in major version represents a major release.
1323 uint16_t mgmt_fw_major;
1325 * This field represents the minor version of HWRM firmware.
1326 * A change in firmware minor version represents significant
1327 * firmware functionality changes.
1329 uint16_t mgmt_fw_minor;
1331 * This field represents the build version of mgmt firmware.
1332 * A change in update version represents bug fixes.
1334 uint16_t mgmt_fw_build;
1336 * This field is a reserved field. This field can be used to
1337 * represent firmware branches or customer specific releases
1338 * tied to a specific (major,minor,update) version.
1340 uint16_t mgmt_fw_patch;
1342 * This field represents the major version of network control
1343 * firmware. A change in major version represents
1346 uint16_t netctrl_fw_major;
1348 * This field represents the minor version of network control
1349 * firmware. A change in minor version represents significant
1350 * functionality changes.
1352 uint16_t netctrl_fw_minor;
1354 * This field represents the build version of network control
1355 * firmware. A change in update version represents bug fixes.
1357 uint16_t netctrl_fw_build;
1359 * This field is a reserved field. This field can be used to
1360 * represent firmware branches or customer specific releases
1361 * tied to a specific (major,minor,update) version
1363 uint16_t netctrl_fw_patch;
1365 * This field represents the major version of RoCE firmware.
1366 * A change in major version represents a major release.
1368 uint16_t roce_fw_major;
1370 * This field represents the minor version of RoCE firmware.
1371 * A change in minor version represents significant
1372 * functionality changes.
1374 uint16_t roce_fw_minor;
1376 * This field represents the build version of RoCE firmware.
1377 * A change in update version represents bug fixes.
1379 uint16_t roce_fw_build;
1381 * This field is a reserved field. This field can be used to
1382 * represent firmware branches or customer specific releases
1383 * tied to a specific (major,minor,update) version
1385 uint16_t roce_fw_patch;
1387 * This field returns the maximum extended request length acceptable
1388 * by the device which allows requests greater than mailbox size when
1389 * used with the short cmd request format.
1391 uint16_t max_ext_req_len;
1392 uint8_t unused_1[5];
1394 * This field is used in Output records to indicate that the output
1395 * is completely written to RAM. This field should be read as '1'
1396 * to indicate that the output has been completely written.
1397 * When writing a command completion or response to an internal processor,
1398 * the order of writes has to be such that this field is written last.
1403 /* bd_base (size:64b/8B) */
1406 /* This value identifies the type of buffer descriptor. */
1407 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1408 #define BD_BASE_TYPE_SFT 0
1410 * Indicates that this BD is 16B long and is used for
1411 * normal L2 packet transmission.
1413 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1415 * Indicates that this BD is 1BB long and is an empty
1416 * TX BD. Not valid for use by the driver.
1418 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1420 * Indicates that this BD is 16B long and is an RX Producer
1421 * (i.e. empty) buffer descriptor.
1423 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1425 * Indicates that this BD is 16B long and is an RX
1426 * Producer Buffer BD.
1428 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1430 * Indicates that this BD is 16B long and is an
1431 * RX Producer Assembly Buffer Descriptor.
1433 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1435 * Indicates that this BD is 32B long and is used for
1436 * normal L2 packet transmission.
1438 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1440 * Indicates that this BD is 32B long and is used for
1441 * L2 packet transmission for small packets that require
1444 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1445 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1446 uint8_t unused_1[7];
1449 /* tx_bd_short (size:128b/16B) */
1450 struct tx_bd_short {
1452 * All bits in this field must be valid on the first BD of a packet.
1453 * Only the packet_end bit must be valid for the remaining BDs
1456 uint16_t flags_type;
1457 /* This value identifies the type of buffer descriptor. */
1458 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1459 #define TX_BD_SHORT_TYPE_SFT 0
1461 * Indicates that this BD is 16B long and is used for
1462 * normal L2 packet transmission.
1464 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1465 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1467 * All bits in this field must be valid on the first BD of a packet.
1468 * Only the packet_end bit must be valid for the remaining BDs
1471 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1472 #define TX_BD_SHORT_FLAGS_SFT 6
1474 * If set to 1, the packet ends with the data in the buffer
1475 * pointed to by this descriptor. This flag must be
1476 * valid on every BD.
1478 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1480 * If set to 1, the device will not generate a completion for
1481 * this transmit packet unless there is an error in it's
1484 * is set to 0, then the packet will be completed normally.
1486 * This bit must be valid only on the first BD of a packet.
1488 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1490 * This value indicates how many 16B BD locations are consumed
1491 * in the ring by this packet.
1492 * A value of 1 indicates that this BD is the only BD (and that
1493 * it is a short BD). A value
1494 * of 3 indicates either 3 short BDs or 1 long BD and one short
1495 * BD in the packet. A value of 0 indicates
1496 * that there are 32 BD locations in the packet (the maximum).
1498 * This field is valid only on the first BD of a packet.
1500 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1501 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1503 * This value is a hint for the length of the entire packet.
1504 * It is used by the chip to optimize internal processing.
1506 * The packet will be dropped if the hint is too short.
1508 * This field is valid only on the first BD of a packet.
1510 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1511 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1512 /* indicates packet length < 512B */
1513 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1514 /* indicates 512 <= packet length < 1KB */
1515 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1516 /* indicates 1KB <= packet length < 2KB */
1517 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1518 /* indicates packet length >= 2KB */
1519 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1520 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1521 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1523 * If set to 1, the device immediately updates the Send Consumer
1524 * Index after the buffer associated with this descriptor has
1525 * been transferred via DMA to NIC memory from host memory. An
1526 * interrupt may or may not be generated according to the state
1527 * of the interrupt avoidance mechanisms. If this bit
1528 * is set to 0, then the Consumer Index is only updated as soon
1529 * as one of the host interrupt coalescing conditions has been met.
1531 * This bit must be valid on the first BD of a packet.
1533 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1535 * This is the length of the host physical buffer this BD describes
1538 * This field must be valid on all BDs of a packet.
1542 * The opaque data field is pass through to the completion and can be
1543 * used for any data that the driver wants to associate with the
1546 * This field must be valid on the first BD of a packet.
1550 * This is the host physical address for the portion of the packet
1551 * described by this TX BD.
1553 * This value must be valid on all BDs of a packet.
1558 /* tx_bd_long (size:128b/16B) */
1560 /* This value identifies the type of buffer descriptor. */
1561 uint16_t flags_type;
1563 * This value indicates the type of buffer descriptor.
1566 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1567 #define TX_BD_LONG_TYPE_SFT 0
1569 * Indicates that this BD is 32B long and is used for
1570 * normal L2 packet transmission.
1572 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1573 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1575 * All bits in this field must be valid on the first BD of a packet.
1576 * Only the packet_end bit must be valid for the remaining BDs
1579 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1580 #define TX_BD_LONG_FLAGS_SFT 6
1582 * If set to 1, the packet ends with the data in the buffer
1583 * pointed to by this descriptor. This flag must be
1584 * valid on every BD.
1586 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1588 * If set to 1, the device will not generate a completion for
1589 * this transmit packet unless there is an error in it's
1592 * is set to 0, then the packet will be completed normally.
1594 * This bit must be valid only on the first BD of a packet.
1596 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1598 * This value indicates how many 16B BD locations are consumed
1599 * in the ring by this packet.
1600 * A value of 1 indicates that this BD is the only BD (and that
1601 * it is a short BD). A value
1602 * of 3 indicates either 3 short BDs or 1 long BD and one short
1603 * BD in the packet. A value of 0 indicates
1604 * that there are 32 BD locations in the packet (the maximum).
1606 * This field is valid only on the first BD of a packet.
1608 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1609 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1611 * This value is a hint for the length of the entire packet.
1612 * It is used by the chip to optimize internal processing.
1614 * The packet will be dropped if the hint is too short.
1616 * This field is valid only on the first BD of a packet.
1618 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1619 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1620 /* indicates packet length < 512B */
1621 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1622 /* indicates 512 <= packet length < 1KB */
1623 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1624 /* indicates 1KB <= packet length < 2KB */
1625 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1626 /* indicates packet length >= 2KB */
1627 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1628 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1630 * If set to 1, the device immediately updates the Send Consumer
1631 * Index after the buffer associated with this descriptor has
1632 * been transferred via DMA to NIC memory from host memory. An
1633 * interrupt may or may not be generated according to the state
1634 * of the interrupt avoidance mechanisms. If this bit
1635 * is set to 0, then the Consumer Index is only updated as soon
1636 * as one of the host interrupt coalescing conditions has been met.
1638 * This bit must be valid on the first BD of a packet.
1640 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1642 * This is the length of the host physical buffer this BD describes
1645 * This field must be valid on all BDs of a packet.
1649 * The opaque data field is pass through to the completion and can be
1650 * used for any data that the driver wants to associate with the
1653 * This field must be valid on the first BD of a packet.
1657 * This is the host physical address for the portion of the packet
1658 * described by this TX BD.
1660 * This value must be valid on all BDs of a packet.
1665 /* Last 16 bytes of tx_bd_long. */
1666 /* tx_bd_long_hi (size:128b/16B) */
1667 struct tx_bd_long_hi {
1669 * All bits in this field must be valid on the first BD of a packet.
1670 * Their value on other BDs of the packet will be ignored.
1674 * If set to 1, the controller replaces the TCP/UPD checksum
1675 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1676 * checksum field of the encapsulated TCP/UDP packets with the
1677 * hardware calculated TCP/UDP checksum for the packet associated
1678 * with this descriptor. The flag is ignored if the LSO flag is set.
1680 * This bit must be valid on the first BD of a packet.
1682 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1684 * If set to 1, the controller replaces the IP checksum of the
1685 * normal packets, or the inner IP checksum of the encapsulated
1686 * packets with the hardware calculated IP checksum for the
1687 * packet associated with this descriptor.
1689 * This bit must be valid on the first BD of a packet.
1691 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1693 * If set to 1, the controller will not append an Ethernet CRC
1694 * to the end of the frame.
1696 * This bit must be valid on the first BD of a packet.
1698 * Packet must be 64B or longer when this flag is set. It is not
1699 * useful to use this bit with any form of TX offload such as
1700 * CSO or LSO. The intent is that the packet from the host already
1701 * has a valid Ethernet CRC on the packet.
1703 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1705 * If set to 1, the device will record the time at which the packet
1706 * was actually transmitted at the TX MAC.
1708 * This bit must be valid on the first BD of a packet.
1710 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1712 * If set to 1, The controller replaces the tunnel IP checksum
1713 * field with hardware calculated IP checksum for the IP header
1714 * of the packet associated with this descriptor.
1716 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1717 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1718 * bit is set, outer UDP checksum will be calculated for the following
1720 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1721 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1722 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1723 * checksum will not be calculated.
1724 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1725 * as part of LSO operation.
1727 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1729 * If set to 1, the device will treat this packet with LSO(Large
1730 * Send Offload) processing for both normal or encapsulated
1731 * packets, which is a form of TCP segmentation. When this bit
1732 * is 1, the hdr_size and mss fields must be valid. The driver
1733 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1734 * flags since the controller will replace the appropriate
1735 * checksum fields for segmented packets.
1737 * When this bit is 1, the hdr_size and mss fields must be valid.
1739 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1741 * If set to zero when LSO is '1', then the IPID will be treated
1742 * as a 16b number and will be wrapped if it exceeds a value of
1745 * If set to one when LSO is '1', then the IPID will be treated
1746 * as a 15b number and will be wrapped if it exceeds a value 0f
1749 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1751 * If set to zero when LSO is '1', then the IPID of the tunnel
1752 * IP header will not be modified during LSO operations.
1754 * If set to one when LSO is '1', then the IPID of the tunnel
1755 * IP header will be incremented for each subsequent segment of an
1758 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1761 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1763 * If set to '1', then the RoCE ICRC will be appended to the
1764 * packet. Packet must be a valid RoCE format packet.
1766 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1768 * If set to '1', then the FCoE CRC will be appended to the
1769 * packet. Packet must be a valid FCoE format packet.
1771 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1774 * When LSO is '1', this field must contain the offset of the
1775 * TCP payload from the beginning of the packet in as
1776 * 16b words. In case of encapsulated/tunneling packet, this field
1777 * contains the offset of the inner TCP payload from beginning of the
1778 * packet as 16-bit words.
1780 * This value must be valid on the first BD of a packet.
1782 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1783 #define TX_BD_LONG_HDR_SIZE_SFT 0
1786 * This is the MSS value that will be used to do the LSO processing.
1787 * The value is the length in bytes of the TCP payload for each
1788 * segment generated by the LSO operation.
1790 * This value must be valid on the first BD of a packet.
1792 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1793 #define TX_BD_LONG_MSS_SFT 0
1796 * This value selects a CFA action to perform on the packet.
1797 * Set this value to zero if no CFA action is desired.
1799 * This value must be valid on the first BD of a packet.
1801 uint16_t cfa_action;
1803 * This value is action meta-data that defines CFA edit operations
1804 * that are done in addition to any action editing.
1807 /* When key=1, This is the VLAN tag VID value. */
1808 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1809 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1810 /* When key=1, This is the VLAN tag DE value. */
1811 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1812 /* When key=1, This is the VLAN tag PRI value. */
1813 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1814 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1815 /* When key=1, This is the VLAN tag TPID select value. */
1816 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1817 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1819 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1821 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1823 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1825 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1827 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1828 /* Value programmed in CFA VLANTPID register. */
1829 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1830 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1831 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1832 /* When key=1, This is the VLAN tag TPID select value. */
1833 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1834 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1836 * This field identifies the type of edit to be performed
1839 * This value must be valid on the first BD of a packet.
1841 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1842 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1844 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1846 * - meta[17:16] - TPID select value (0 = 0x8100).
1847 * - meta[15:12] - PRI/DE value.
1848 * - meta[11:0] - VID value.
1850 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1851 #define TX_BD_LONG_CFA_META_KEY_LAST \
1852 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1856 * This structure is used to inform the NIC of packet data that needs to be
1857 * transmitted with additional processing that requires extra data such as
1858 * VLAN insertion plus attached inline data. This BD type may be used to
1859 * improve latency for small packets needing the additional extended features
1860 * supported by long BDs.
1862 /* tx_bd_long_inline (size:256b/32B) */
1863 struct tx_bd_long_inline {
1864 uint16_t flags_type;
1865 /* This value identifies the type of buffer descriptor. */
1866 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1867 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1869 * This type of BD is 32B long and is used for inline L2 packet
1872 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1873 #define TX_BD_LONG_INLINE_TYPE_LAST \
1874 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1876 * All bits in this field may be set on the first BD of a packet.
1877 * Only the packet_end bit may be set in non-first BDs.
1879 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1880 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1882 * If set to 1, the packet ends with the data in the buffer
1883 * pointed to by this descriptor. This flag must be
1884 * valid on every BD.
1886 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1888 * If set to 1, the device will not generate a completion for
1889 * this transmit packet unless there is an error in its processing.
1890 * If this bit is set to 0, then the packet will be completed
1893 * This bit may be set only on the first BD of a packet.
1895 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1897 * This value indicates how many 16B BD locations are consumed
1898 * in the ring by this packet, including the BD and inline
1901 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1902 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1903 /* This field is deprecated. */
1904 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1905 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1907 * If set to 1, the device immediately updates the Send Consumer
1908 * Index after the buffer associated with this descriptor has
1909 * been transferred via DMA to NIC memory from host memory. An
1910 * interrupt may or may not be generated according to the state
1911 * of the interrupt avoidance mechanisms. If this bit
1912 * is set to 0, then the Consumer Index is only updated as soon
1913 * as one of the host interrupt coalescing conditions has been met.
1915 * This bit must be valid on the first BD of a packet.
1917 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1919 * This is the length of the inline data, not including BD length, in
1921 * The maximum value is 480.
1923 * This field must be valid on all BDs of a packet.
1927 * The opaque data field is passed through to the completion and can be
1928 * used for any data that the driver wants to associate with the transmit
1931 * This field must be valid on the first BD of a packet.
1936 * All bits in this field must be valid on the first BD of a packet.
1937 * Their value on other BDs of the packet is ignored.
1941 * If set to 1, the controller replaces the TCP/UPD checksum
1942 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1943 * checksum field of the encapsulated TCP/UDP packets with the
1944 * hardware calculated TCP/UDP checksum for the packet associated
1945 * with this descriptor. The flag is ignored if the LSO flag is set.
1947 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1949 * If set to 1, the controller replaces the IP checksum of the
1950 * normal packets, or the inner IP checksum of the encapsulated
1951 * packets with the hardware calculated IP checksum for the
1952 * packet associated with this descriptor.
1954 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1956 * If set to 1, the controller will not append an Ethernet CRC
1957 * to the end of the frame.
1959 * Packet must be 64B or longer when this flag is set. It is not
1960 * useful to use this bit with any form of TX offload such as
1961 * CSO or LSO. The intent is that the packet from the host already
1962 * has a valid Ethernet CRC on the packet.
1964 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1966 * If set to 1, the device will record the time at which the packet
1967 * was actually transmitted at the TX MAC.
1969 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1971 * If set to 1, the controller replaces the tunnel IP checksum
1972 * field with hardware calculated IP checksum for the IP header
1973 * of the packet associated with this descriptor. The hardware
1974 * updates an outer UDP checksum if it is non-zero.
1976 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1978 * This bit must be 0 for BDs of this type. LSO is not supported with
1981 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1982 /* Since LSO is not supported with inline BDs, this bit is not used. */
1983 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1984 /* Since LSO is not supported with inline BDs, this bit is not used. */
1985 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1987 * If set to '1', then the RoCE ICRC will be appended to the
1988 * packet. Packet must be a valid RoCE format packet.
1990 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1992 * If set to '1', then the FCoE CRC will be appended to the
1993 * packet. Packet must be a valid FCoE format packet.
1995 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2000 * This value selects a CFA action to perform on the packet.
2001 * Set this value to zero if no CFA action is desired.
2003 * This value must be valid on the first BD of a packet.
2005 uint16_t cfa_action;
2007 * This value is action meta-data that defines CFA edit operations
2008 * that are done in addition to any action editing.
2011 /* When key = 1, this is the VLAN tag VID value. */
2012 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2013 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2014 /* When key = 1, this is the VLAN tag DE value. */
2015 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2016 /* When key = 1, this is the VLAN tag PRI value. */
2017 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2018 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2019 /* When key = 1, this is the VLAN tag TPID select value. */
2020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2021 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2023 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2024 (UINT32_C(0x0) << 16)
2026 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2027 (UINT32_C(0x1) << 16)
2029 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2030 (UINT32_C(0x2) << 16)
2032 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2033 (UINT32_C(0x3) << 16)
2035 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2036 (UINT32_C(0x4) << 16)
2037 /* Value programmed in CFA VLANTPID register. */
2038 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2039 (UINT32_C(0x5) << 16)
2040 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2041 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2042 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2044 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2046 * This field identifies the type of edit to be performed
2049 * This value must be valid on the first BD of a packet.
2051 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2052 UINT32_C(0xf0000000)
2053 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2055 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2056 (UINT32_C(0x0) << 28)
2058 * - meta[17:16] - TPID select value (0 = 0x8100).
2059 * - meta[15:12] - PRI/DE value.
2060 * - meta[11:0] - VID value.
2062 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2063 (UINT32_C(0x1) << 28)
2064 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2065 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2068 /* tx_bd_empty (size:128b/16B) */
2069 struct tx_bd_empty {
2070 /* This value identifies the type of buffer descriptor. */
2072 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2073 #define TX_BD_EMPTY_TYPE_SFT 0
2075 * Indicates that this BD is 1BB long and is an empty
2076 * TX BD. Not valid for use by the driver.
2078 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2079 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2080 uint8_t unused_1[3];
2082 uint8_t unused_3[3];
2083 uint8_t unused_4[8];
2086 /* rx_prod_pkt_bd (size:128b/16B) */
2087 struct rx_prod_pkt_bd {
2088 /* This value identifies the type of buffer descriptor. */
2089 uint16_t flags_type;
2090 /* This value identifies the type of buffer descriptor. */
2091 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2092 #define RX_PROD_PKT_BD_TYPE_SFT 0
2094 * Indicates that this BD is 16B long and is an RX Producer
2095 * (i.e. empty) buffer descriptor.
2097 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2098 #define RX_PROD_PKT_BD_TYPE_LAST \
2099 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2100 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2101 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2103 * If set to 1, the packet will be placed at the address plus
2104 * 2B. The 2 Bytes of padding will be written as zero.
2106 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2108 * If set to 1, the packet write will be padded out to the
2109 * nearest cache-line with zero value padding.
2111 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2113 * This value is the number of additional buffers in the ring that
2114 * describe the buffer space to be consumed for this packet.
2115 * If the value is zero, then the packet must fit within the
2116 * space described by this BD. If this value is 1 or more, it
2117 * indicates how many additional "buffer" BDs are in the ring
2118 * immediately following this BD to be used for the same
2121 * Even if the packet to be placed does not need all the
2122 * additional buffers, they will be consumed anyway.
2124 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2125 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2127 * This is the length in Bytes of the host physical buffer where
2128 * data for the packet may be placed in host memory.
2132 * The opaque data field is pass through to the completion and can be
2133 * used for any data that the driver wants to associate with this
2134 * receive buffer set.
2138 * This is the host physical address where data for the packet may
2139 * be placed in host memory.
2144 /* rx_prod_bfr_bd (size:128b/16B) */
2145 struct rx_prod_bfr_bd {
2146 /* This value identifies the type of buffer descriptor. */
2147 uint16_t flags_type;
2148 /* This value identifies the type of buffer descriptor. */
2149 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2150 #define RX_PROD_BFR_BD_TYPE_SFT 0
2152 * Indicates that this BD is 16B long and is an RX
2153 * Producer Buffer BD.
2155 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2156 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2157 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2158 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2160 * This is the length in Bytes of the host physical buffer where
2161 * data for the packet may be placed in host memory.
2164 /* This field is not used. */
2167 * This is the host physical address where data for the packet may
2168 * be placed in host memory.
2173 /* rx_prod_agg_bd (size:128b/16B) */
2174 struct rx_prod_agg_bd {
2175 /* This value identifies the type of buffer descriptor. */
2176 uint16_t flags_type;
2177 /* This value identifies the type of buffer descriptor. */
2178 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2179 #define RX_PROD_AGG_BD_TYPE_SFT 0
2181 * Indicates that this BD is 16B long and is an
2182 * RX Producer Assembly Buffer Descriptor.
2184 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2185 #define RX_PROD_AGG_BD_TYPE_LAST \
2186 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2187 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2188 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2190 * If set to 1, the packet write will be padded out to the
2191 * nearest cache-line with zero value padding.
2193 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2195 * This is the length in Bytes of the host physical buffer where
2196 * data for the packet may be placed in host memory.
2200 * The opaque data field is pass through to the completion and can be
2201 * used for any data that the driver wants to associate with this
2202 * receive assembly buffer.
2206 * This is the host physical address where data for the packet may
2207 * be placed in host memory.
2212 /* cmpl_base (size:128b/16B) */
2216 * This field indicates the exact type of the completion.
2217 * By convention, the LSB identifies the length of the
2218 * record in 16B units. Even values indicate 16B
2219 * records. Odd values indicate 32B
2222 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2223 #define CMPL_BASE_TYPE_SFT 0
2226 * Completion of TX packet. Length = 16B
2228 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2231 * Completion of and L2 RX packet. Length = 32B
2233 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2235 * RX Aggregation Buffer completion :
2236 * Completion of an L2 aggregation buffer in support of
2237 * TPA, HDS, or Jumbo packet completion. Length = 16B
2239 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2241 * RX L2 TPA Start Completion:
2242 * Completion at the beginning of a TPA operation.
2245 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2247 * RX L2 TPA End Completion:
2248 * Completion at the end of a TPA operation.
2251 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2253 * Statistics Ejection Completion:
2254 * Completion of statistics data ejection buffer.
2257 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2259 * HWRM Command Completion:
2260 * Completion of an HWRM command.
2262 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2263 /* Forwarded HWRM Request */
2264 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2265 /* Forwarded HWRM Response */
2266 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2267 /* HWRM Asynchronous Event Information */
2268 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2269 /* CQ Notification */
2270 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2271 /* SRQ Threshold Event */
2272 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2273 /* DBQ Threshold Event */
2274 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2275 /* QP Async Notification */
2276 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2277 /* Function Async Notification */
2278 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2279 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2285 * This value is written by the NIC such that it will be different
2286 * for each pass through the completion queue. The even passes
2287 * will write 1. The odd passes will write 0.
2290 #define CMPL_BASE_V UINT32_C(0x1)
2291 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2292 #define CMPL_BASE_INFO3_SFT 1
2297 /* tx_cmpl (size:128b/16B) */
2299 uint16_t flags_type;
2301 * This field indicates the exact type of the completion.
2302 * By convention, the LSB identifies the length of the
2303 * record in 16B units. Even values indicate 16B
2304 * records. Odd values indicate 32B
2307 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2308 #define TX_CMPL_TYPE_SFT 0
2311 * Completion of TX packet. Length = 16B
2313 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2314 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2315 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2316 #define TX_CMPL_FLAGS_SFT 6
2318 * When this bit is '1', it indicates a packet that has an
2319 * error of some type. Type of error is indicated in
2322 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2324 * When this bit is '1', it indicates that the packet completed
2325 * was transmitted using the push acceleration data provided
2326 * by the driver. When this bit is '0', it indicates that the
2327 * packet had not push acceleration data written or was executed
2328 * as a normal packet even though push data was provided.
2330 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2331 /* unused1 is 16 b */
2334 * This is a copy of the opaque field from the first TX BD of this
2335 * transmitted packet.
2340 * This value is written by the NIC such that it will be different
2341 * for each pass through the completion queue. The even passes
2342 * will write 1. The odd passes will write 0.
2344 #define TX_CMPL_V UINT32_C(0x1)
2345 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2346 #define TX_CMPL_ERRORS_SFT 1
2348 * This error indicates that there was some sort of problem
2349 * with the BDs for the packet.
2351 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2352 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2354 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2357 * BDs were not formatted correctly.
2359 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2360 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2361 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2363 * When this bit is '1', it indicates that the length of
2364 * the packet was zero. No packet was transmitted.
2366 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2368 * When this bit is '1', it indicates that the packet
2369 * was longer than the programmed limit in TDI. No
2370 * packet was transmitted.
2372 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2374 * When this bit is '1', it indicates that one or more of the
2375 * BDs associated with this packet generated a PCI error.
2376 * This probably means the address was not valid.
2378 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2380 * When this bit is '1', it indicates that the packet was longer
2381 * than indicated by the hint. No packet was transmitted.
2383 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2385 * When this bit is '1', it indicates that the packet was
2386 * dropped due to Poison TLP error on one or more of the
2387 * TLPs in the PXP completion.
2389 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2390 /* unused2 is 16 b */
2392 /* unused3 is 32 b */
2396 /* rx_pkt_cmpl (size:128b/16B) */
2397 struct rx_pkt_cmpl {
2398 uint16_t flags_type;
2400 * This field indicates the exact type of the completion.
2401 * By convention, the LSB identifies the length of the
2402 * record in 16B units. Even values indicate 16B
2403 * records. Odd values indicate 32B
2406 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2407 #define RX_PKT_CMPL_TYPE_SFT 0
2410 * Completion of and L2 RX packet. Length = 32B
2412 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2413 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2414 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2415 #define RX_PKT_CMPL_FLAGS_SFT 6
2417 * When this bit is '1', it indicates a packet that has an
2418 * error of some type. Type of error is indicated in
2421 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2422 /* This field indicates how the packet was placed in the buffer. */
2423 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2424 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2427 * Packet was placed using normal algorithm.
2429 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2432 * Packet was placed using jumbo algorithm.
2434 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2436 * Header/Data Separation:
2437 * Packet was placed using Header/Data separation algorithm.
2438 * The separation location is indicated by the itype field.
2440 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2441 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2442 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2443 /* This bit is '1' if the RSS field in this completion is valid. */
2444 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2446 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2448 * This value indicates what the inner packet determined for the
2451 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2452 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2455 * Indicates that the packet type was not known.
2457 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2458 (UINT32_C(0x0) << 12)
2461 * Indicates that the packet was an IP packet, but further
2462 * classification was not possible.
2464 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2465 (UINT32_C(0x1) << 12)
2468 * Indicates that the packet was IP and TCP.
2469 * This indicates that the payload_offset field is valid.
2471 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2472 (UINT32_C(0x2) << 12)
2475 * Indicates that the packet was IP and UDP.
2476 * This indicates that the payload_offset field is valid.
2478 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2479 (UINT32_C(0x3) << 12)
2482 * Indicates that the packet was recognized as a FCoE.
2483 * This also indicates that the payload_offset field is valid.
2485 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2486 (UINT32_C(0x4) << 12)
2489 * Indicates that the packet was recognized as a RoCE.
2490 * This also indicates that the payload_offset field is valid.
2492 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2493 (UINT32_C(0x5) << 12)
2496 * Indicates that the packet was recognized as ICMP.
2497 * This indicates that the payload_offset field is valid.
2499 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2500 (UINT32_C(0x7) << 12)
2502 * PtP packet wo/timestamp:
2503 * Indicates that the packet was recognized as a PtP
2506 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2507 (UINT32_C(0x8) << 12)
2509 * PtP packet w/timestamp:
2510 * Indicates that the packet was recognized as a PtP
2511 * packet and that a timestamp was taken for the packet.
2513 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2514 (UINT32_C(0x9) << 12)
2515 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2516 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2518 * This is the length of the data for the packet stored in the
2519 * buffer(s) identified by the opaque value. This includes
2520 * the packet BD and any associated buffer BDs. This does not include
2521 * the length of any data places in aggregation BDs.
2525 * This is a copy of the opaque field from the RX BD this completion
2529 uint8_t agg_bufs_v1;
2531 * This value is written by the NIC such that it will be different
2532 * for each pass through the completion queue. The even passes
2533 * will write 1. The odd passes will write 0.
2535 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2537 * This value is the number of aggregation buffers that follow this
2538 * entry in the completion ring that are a part of this packet.
2539 * If the value is zero, then the packet is completely contained
2540 * in the buffer space provided for the packet in the RX ring.
2542 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2543 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2544 /* unused1 is 2 b */
2545 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2546 #define RX_PKT_CMPL_UNUSED1_SFT 6
2548 * This is the RSS hash type for the packet. The value is packed
2549 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2551 * The value of tuple_extrac_op provides the information about
2552 * what fields the hash was computed on.
2553 * * 0: The RSS hash was computed over source IP address,
2554 * destination IP address, source port, and destination port of inner
2555 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2556 * the packet headers are considered inner packet headers for the RSS
2557 * hash computation purpose.
2558 * * 1: The RSS hash was computed over source IP address and destination
2559 * IP address of inner IP header. Note: For non-tunneled packets,
2560 * the packet headers are considered inner packet headers for the RSS
2561 * hash computation purpose.
2562 * * 2: The RSS hash was computed over source IP address,
2563 * destination IP address, source port, and destination port of
2564 * IP and TCP or UDP headers of outer tunnel headers.
2565 * Note: For non-tunneled packets, this value is not applicable.
2566 * * 3: The RSS hash was computed over source IP address and
2567 * destination IP address of IP header of outer tunnel headers.
2568 * Note: For non-tunneled packets, this value is not applicable.
2570 * Note that 4-tuples values listed above are applicable
2571 * for layer 4 protocols supported and enabled for RSS in the hardware,
2572 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2573 * enabled for TCP traffic only, then the values of tuple_extract_op
2574 * corresponding to 4-tuples are only valid for TCP traffic.
2576 uint8_t rss_hash_type;
2578 * This value indicates the offset in bytes from the beginning of the packet
2579 * where the inner payload starts. This value is valid for TCP, UDP,
2580 * FCoE, and RoCE packets.
2582 * A value of zero indicates that header is 256B into the packet.
2584 uint8_t payload_offset;
2585 /* unused2 is 8 b */
2588 * This value is the RSS hash value calculated for the packet
2589 * based on the mode bits and key value in the VNIC.
2594 /* Last 16 bytes of rx_pkt_cmpl. */
2595 /* rx_pkt_cmpl_hi (size:128b/16B) */
2596 struct rx_pkt_cmpl_hi {
2599 * This indicates that the ip checksum was calculated for the
2600 * inner packet and that the ip_cs_error field indicates if there
2603 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2605 * This indicates that the TCP, UDP or ICMP checksum was
2606 * calculated for the inner packet and that the l4_cs_error field
2607 * indicates if there was an error.
2609 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2611 * This indicates that the ip checksum was calculated for the
2612 * tunnel header and that the t_ip_cs_error field indicates if there
2615 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2617 * This indicates that the UDP checksum was
2618 * calculated for the tunnel packet and that the t_l4_cs_error field
2619 * indicates if there was an error.
2621 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2622 /* This value indicates what format the metadata field is. */
2623 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2624 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2625 /* No metadata information. Value is zero. */
2626 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
2627 (UINT32_C(0x0) << 4)
2629 * The metadata field contains the VLAN tag and TPID value.
2630 * - metadata[11:0] contains the vlan VID value.
2631 * - metadata[12] contains the vlan DE value.
2632 * - metadata[15:13] contains the vlan PRI value.
2633 * - metadata[31:16] contains the vlan TPID value.
2635 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
2636 (UINT32_C(0x1) << 4)
2638 * If ext_meta_format is equal to 1, the metadata field
2639 * contains the lower 16b of the tunnel ID value, justified
2641 * - VXLAN = VNI[23:0] -> VXLAN Network ID
2642 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
2643 * - NVGRE = TNI[23:0] -> Tenant Network ID
2644 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
2645 * - IPV4 = 0 (not populated)
2646 * - IPV6 = Flow Label[19:0]
2647 * - PPPoE = sessionID[15:0]
2648 * - MPLs = Outer label[19:0]
2649 * - UPAR = Selected[31:0] with bit mask
2651 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
2652 (UINT32_C(0x2) << 4)
2654 * if ext_meta_format is equal to 1, metadata field contains
2655 * 16b metadata from the prepended header (chdr_data).
2657 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
2658 (UINT32_C(0x3) << 4)
2660 * If ext_meta_format is equal to 1, the metadata field contains
2661 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
2663 * - metadata[8:0] contains the outer_l3_offset.
2664 * - metadata[17:9] contains the inner_l2_offset.
2665 * - metadata[26:18] contains the inner_l3_offset.
2666 * - metadata[31:27] contains the inner_l4_size.
2668 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
2669 (UINT32_C(0x4) << 4)
2670 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2671 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
2673 * This field indicates the IP type for the inner-most IP header.
2674 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2675 * This value is only valid if itype indicates a packet
2676 * with an IP header.
2678 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2680 * This indicates that the complete 1's complement checksum was
2681 * calculated for the packet.
2683 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
2685 * The combination of this value and meta_format indicated what
2686 * format the metadata field is.
2688 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
2689 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
2691 * This value is the complete 1's complement checksum calculated from
2692 * the start of the outer L3 header to the end of the packet (not
2693 * including the ethernet crc). It is valid when the
2694 * 'complete_checksum_calc' flag is set.
2696 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
2697 UINT32_C(0xffff0000)
2698 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
2700 * This is data from the CFA block as indicated by the meta_format
2704 /* When meta_format=1, this value is the VLAN VID. */
2705 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2706 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2707 /* When meta_format=1, this value is the VLAN DE. */
2708 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2709 /* When meta_format=1, this value is the VLAN PRI. */
2710 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2711 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2712 /* When meta_format=1, this value is the VLAN TPID. */
2713 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2714 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2717 * This value is written by the NIC such that it will be different
2718 * for each pass through the completion queue. The even passes
2719 * will write 1. The odd passes will write 0.
2721 #define RX_PKT_CMPL_V2 \
2723 #define RX_PKT_CMPL_ERRORS_MASK \
2725 #define RX_PKT_CMPL_ERRORS_SFT 1
2727 * This error indicates that there was some sort of problem with
2728 * the BDs for the packet that was found after part of the
2729 * packet was already placed. The packet should be treated as
2732 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2734 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2735 /* No buffer error */
2736 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2737 (UINT32_C(0x0) << 1)
2740 * Packet did not fit into packet buffer provided.
2741 * For regular placement, this means the packet did not fit
2742 * in the buffer provided. For HDS and jumbo placement, this
2743 * means that the packet could not be placed into 7 physical
2746 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2747 (UINT32_C(0x1) << 1)
2750 * All BDs needed for the packet were not on-chip when
2751 * the packet arrived.
2753 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2754 (UINT32_C(0x2) << 1)
2757 * BDs were not formatted correctly.
2759 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2760 (UINT32_C(0x3) << 1)
2763 * There was a bad_format error on the previous operation
2765 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
2766 (UINT32_C(0x5) << 1)
2767 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2768 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
2770 * This indicates that there was an error in the IP header
2773 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2776 * This indicates that there was an error in the TCP, UDP
2779 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2782 * This indicates that there was an error in the tunnel
2783 * IP header checksum.
2785 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2788 * This indicates that there was an error in the tunnel
2791 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2794 * This indicates that there was a CRC error on either an FCoE
2795 * or RoCE packet. The itype indicates the packet type.
2797 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2800 * This indicates that there was an error in the tunnel
2801 * portion of the packet when this
2802 * field is non-zero.
2804 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2806 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2808 * No additional error occurred on the tunnel portion
2809 * or the packet of the packet does not have a tunnel.
2811 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2812 (UINT32_C(0x0) << 9)
2814 * Indicates that IP header version does not match
2815 * expectation from L2 Ethertype for IPv4 and IPv6
2816 * in the tunnel header.
2818 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2819 (UINT32_C(0x1) << 9)
2821 * Indicates that header length is out of range in the
2822 * tunnel header. Valid for
2825 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2826 (UINT32_C(0x2) << 9)
2828 * Indicates that the physical packet is shorter than that
2829 * claimed by the PPPoE header length for a tunnel PPPoE
2832 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2833 (UINT32_C(0x3) << 9)
2835 * Indicates that physical packet is shorter than that claimed
2836 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2837 * tunnel packet packets.
2839 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2840 (UINT32_C(0x4) << 9)
2842 * Indicates that the physical packet is shorter than that
2843 * claimed by the tunnel UDP header length for a tunnel
2844 * UDP packet that is not fragmented.
2846 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2847 (UINT32_C(0x5) << 9)
2849 * indicates that the IPv4 TTL or IPv6 hop limit check
2850 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2851 * for IPv4, and IPv6.
2853 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2854 (UINT32_C(0x6) << 9)
2855 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2856 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2858 * This indicates that there was an error in the inner
2859 * portion of the packet when this
2860 * field is non-zero.
2862 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2864 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2866 * No additional error occurred on the tunnel portion
2867 * or the packet of the packet does not have a tunnel.
2869 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2870 (UINT32_C(0x0) << 12)
2872 * Indicates that IP header version does not match
2873 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2874 * option other than VFT was parsed on
2877 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2878 (UINT32_C(0x1) << 12)
2880 * indicates that header length is out of range. Valid for
2883 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2884 (UINT32_C(0x2) << 12)
2886 * indicates that the IPv4 TTL or IPv6 hop limit check
2887 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2889 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2890 (UINT32_C(0x3) << 12)
2892 * Indicates that physical packet is shorter than that
2893 * claimed by the l3 header length. Valid for IPv4,
2894 * IPv6 packet or RoCE packets.
2896 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2897 (UINT32_C(0x4) << 12)
2899 * Indicates that the physical packet is shorter than that
2900 * claimed by the UDP header length for a UDP packet that is
2903 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2904 (UINT32_C(0x5) << 12)
2906 * Indicates that TCP header length > IP payload. Valid for
2909 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2910 (UINT32_C(0x6) << 12)
2911 /* Indicates that TCP header length < 5. Valid for TCP. */
2912 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2913 (UINT32_C(0x7) << 12)
2915 * Indicates that TCP option headers result in a TCP header
2916 * size that does not match data offset in TCP header. Valid
2919 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2920 (UINT32_C(0x8) << 12)
2921 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2922 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2924 * This field identifies the CFA action rule that was used for this
2930 * This value holds the reordering sequence number for the packet.
2931 * If the reordering sequence is not valid, then this value is zero.
2932 * The reordering domain for the packet is in the bottom 8 to 10b of
2933 * the rss_hash value. The bottom 20b of this value contain the
2934 * ordering domain value for the packet.
2936 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2937 #define RX_PKT_CMPL_REORDER_SFT 0
2941 * This TPA completion structure is used on devices where the
2942 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
2944 /* rx_tpa_start_cmpl (size:128b/16B) */
2945 struct rx_tpa_start_cmpl {
2946 uint16_t flags_type;
2948 * This field indicates the exact type of the completion.
2949 * By convention, the LSB identifies the length of the
2950 * record in 16B units. Even values indicate 16B
2951 * records. Odd values indicate 32B
2954 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2955 #define RX_TPA_START_CMPL_TYPE_SFT 0
2957 * RX L2 TPA Start Completion:
2958 * Completion at the beginning of a TPA operation.
2961 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2962 #define RX_TPA_START_CMPL_TYPE_LAST \
2963 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2964 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2965 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2966 /* This bit will always be '0' for TPA start completions. */
2967 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2968 /* This field indicates how the packet was placed in the buffer. */
2969 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2970 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2973 * TPA Packet was placed using jumbo algorithm. This means
2974 * that the first buffer will be filled with data before
2975 * moving to aggregation buffers. Each aggregation buffer
2976 * will be filled before moving to the next aggregation
2979 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2980 (UINT32_C(0x1) << 7)
2982 * Header/Data Separation:
2983 * Packet was placed using Header/Data separation algorithm.
2984 * The separation location is indicated by the itype field.
2986 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2987 (UINT32_C(0x2) << 7)
2990 * Packet will be placed using GRO/Jumbo where the first
2991 * packet is filled with data. Subsequent packets will be
2992 * placed such that any one packet does not span two
2993 * aggregation buffers unless it starts at the beginning of
2994 * an aggregation buffer.
2996 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2997 (UINT32_C(0x5) << 7)
2999 * GRO/Header-Data Separation:
3000 * Packet will be placed using GRO/HDS where the header
3001 * is in the first packet.
3002 * Payload of each packet will be
3003 * placed such that any one packet does not span two
3004 * aggregation buffers unless it starts at the beginning of
3005 * an aggregation buffer.
3007 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3008 (UINT32_C(0x6) << 7)
3009 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
3010 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3011 /* This bit is '1' if the RSS field in this completion is valid. */
3012 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3014 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
3016 * This value indicates what the inner packet determined for the
3019 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3020 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
3023 * Indicates that the packet was IP and TCP.
3025 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
3026 (UINT32_C(0x2) << 12)
3027 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
3028 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
3030 * This value indicates the amount of packet data written to the
3031 * buffer the opaque field in this completion corresponds to.
3035 * This is a copy of the opaque field from the RX BD this completion
3040 * This value is written by the NIC such that it will be different
3041 * for each pass through the completion queue. The even passes
3042 * will write 1. The odd passes will write 0.
3046 * This value is written by the NIC such that it will be different
3047 * for each pass through the completion queue. The even passes
3048 * will write 1. The odd passes will write 0.
3050 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
3051 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
3053 * This is the RSS hash type for the packet. The value is packed
3054 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3056 * The value of tuple_extrac_op provides the information about
3057 * what fields the hash was computed on.
3058 * * 0: The RSS hash was computed over source IP address,
3059 * destination IP address, source port, and destination port of inner
3060 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3061 * the packet headers are considered inner packet headers for the RSS
3062 * hash computation purpose.
3063 * * 1: The RSS hash was computed over source IP address and destination
3064 * IP address of inner IP header. Note: For non-tunneled packets,
3065 * the packet headers are considered inner packet headers for the RSS
3066 * hash computation purpose.
3067 * * 2: The RSS hash was computed over source IP address,
3068 * destination IP address, source port, and destination port of
3069 * IP and TCP or UDP headers of outer tunnel headers.
3070 * Note: For non-tunneled packets, this value is not applicable.
3071 * * 3: The RSS hash was computed over source IP address and
3072 * destination IP address of IP header of outer tunnel headers.
3073 * Note: For non-tunneled packets, this value is not applicable.
3075 * Note that 4-tuples values listed above are applicable
3076 * for layer 4 protocols supported and enabled for RSS in the hardware,
3077 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3078 * enabled for TCP traffic only, then the values of tuple_extract_op
3079 * corresponding to 4-tuples are only valid for TCP traffic.
3081 uint8_t rss_hash_type;
3083 * This is the aggregation ID that the completion is associated
3084 * with. Use this number to correlate the TPA start completion
3085 * with the TPA end completion.
3088 /* unused2 is 9 b */
3089 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
3090 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
3092 * This is the aggregation ID that the completion is associated
3093 * with. Use this number to correlate the TPA start completion
3094 * with the TPA end completion.
3096 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
3097 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
3099 * This value is the RSS hash value calculated for the packet
3100 * based on the mode bits and key value in the VNIC.
3106 * Last 16 bytes of rx_tpa_start_cmpl.
3108 * This TPA completion structure is used on devices where the
3109 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3111 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
3112 struct rx_tpa_start_cmpl_hi {
3115 * This indicates that the ip checksum was calculated for the
3116 * inner packet and that the sum passed for all segments
3117 * included in the aggregation.
3119 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3121 * This indicates that the TCP, UDP or ICMP checksum was
3122 * calculated for the inner packet and that the sum passed
3123 * for all segments included in the aggregation.
3125 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3127 * This indicates that the ip checksum was calculated for the
3128 * tunnel header and that the sum passed for all segments
3129 * included in the aggregation.
3131 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3133 * This indicates that the UDP checksum was
3134 * calculated for the tunnel packet and that the sum passed for
3135 * all segments included in the aggregation.
3137 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3138 /* This value indicates what format the metadata field is. */
3139 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3140 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3141 /* No metadata information. Value is zero. */
3142 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
3143 (UINT32_C(0x0) << 4)
3145 * The metadata field contains the VLAN tag and TPID value.
3146 * - metadata[11:0] contains the vlan VID value.
3147 * - metadata[12] contains the vlan DE value.
3148 * - metadata[15:13] contains the vlan PRI value.
3149 * - metadata[31:16] contains the vlan TPID value.
3151 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3152 (UINT32_C(0x1) << 4)
3153 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
3154 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
3156 * This field indicates the IP type for the inner-most IP header.
3157 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3159 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3161 * This is data from the CFA block as indicated by the meta_format
3165 /* When meta_format=1, this value is the VLAN VID. */
3166 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3167 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
3168 /* When meta_format=1, this value is the VLAN DE. */
3169 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
3170 /* When meta_format=1, this value is the VLAN PRI. */
3171 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3172 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
3173 /* When meta_format=1, this value is the VLAN TPID. */
3174 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3175 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
3178 * This value is written by the NIC such that it will be different
3179 * for each pass through the completion queue. The even passes
3180 * will write 1. The odd passes will write 0.
3182 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
3184 * This field identifies the CFA action rule that was used for this
3189 * This is the size in bytes of the inner most L4 header.
3190 * This can be subtracted from the payload_offset to determine
3191 * the start of the inner most L4 header.
3193 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3195 * This is the offset from the beginning of the packet in bytes for
3196 * the outer L3 header. If there is no outer L3 header, then this
3199 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3200 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
3202 * This is the offset from the beginning of the packet in bytes for
3203 * the inner most L2 header.
3205 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3206 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
3208 * This is the offset from the beginning of the packet in bytes for
3209 * the inner most L3 header.
3211 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3212 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
3214 * This is the size in bytes of the inner most L4 header.
3215 * This can be subtracted from the payload_offset to determine
3216 * the start of the inner most L4 header.
3218 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3219 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
3223 * This TPA completion structure is used on devices where the
3224 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3226 /* rx_tpa_end_cmpl (size:128b/16B) */
3227 struct rx_tpa_end_cmpl {
3228 uint16_t flags_type;
3230 * This field indicates the exact type of the completion.
3231 * By convention, the LSB identifies the length of the
3232 * record in 16B units. Even values indicate 16B
3233 * records. Odd values indicate 32B
3236 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3237 #define RX_TPA_END_CMPL_TYPE_SFT 0
3239 * RX L2 TPA End Completion:
3240 * Completion at the end of a TPA operation.
3243 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3244 #define RX_TPA_END_CMPL_TYPE_LAST \
3245 RX_TPA_END_CMPL_TYPE_RX_TPA_END
3246 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3247 #define RX_TPA_END_CMPL_FLAGS_SFT 6
3249 * When this bit is '1', it indicates a packet that has an
3250 * error of some type. Type of error is indicated in
3253 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3254 /* This field indicates how the packet was placed in the buffer. */
3255 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3256 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
3259 * TPA Packet was placed using jumbo algorithm. This means
3260 * that the first buffer will be filled with data before
3261 * moving to aggregation buffers. Each aggregation buffer
3262 * will be filled before moving to the next aggregation
3265 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3266 (UINT32_C(0x1) << 7)
3268 * Header/Data Separation:
3269 * Packet was placed using Header/Data separation algorithm.
3270 * The separation location is indicated by the itype field.
3272 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3273 (UINT32_C(0x2) << 7)
3276 * Packet will be placed using GRO/Jumbo where the first
3277 * packet is filled with data. Subsequent packets will be
3278 * placed such that any one packet does not span two
3279 * aggregation buffers unless it starts at the beginning of
3280 * an aggregation buffer.
3282 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3283 (UINT32_C(0x5) << 7)
3285 * GRO/Header-Data Separation:
3286 * Packet will be placed using GRO/HDS where the header
3287 * is in the first packet.
3288 * Payload of each packet will be
3289 * placed such that any one packet does not span two
3290 * aggregation buffers unless it starts at the beginning of
3291 * an aggregation buffer.
3293 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3294 (UINT32_C(0x6) << 7)
3295 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3296 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3298 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3299 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3301 * This value indicates what the inner packet determined for the
3304 * Indicates that the packet was IP and TCP. This indicates
3305 * that the ip_cs field is valid and that the tcp_udp_cs
3306 * field is valid and contains the TCP checksum.
3307 * This also indicates that the payload_offset field is valid.
3309 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3310 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3312 * This value is zero for TPA End completions.
3313 * There is no data in the buffer that corresponds to the opaque
3314 * value in this completion.
3318 * This is a copy of the opaque field from the RX BD this completion
3323 * This value is written by the NIC such that it will be different
3324 * for each pass through the completion queue. The even passes
3325 * will write 1. The odd passes will write 0.
3327 uint8_t agg_bufs_v1;
3329 * This value is written by the NIC such that it will be different
3330 * for each pass through the completion queue. The even passes
3331 * will write 1. The odd passes will write 0.
3333 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3335 * This value is the number of aggregation buffers that follow this
3336 * entry in the completion ring that are a part of this aggregation
3338 * If the value is zero, then the packet is completely contained
3339 * in the buffer space provided in the aggregation start completion.
3341 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3342 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3343 /* This value is the number of segments in the TPA operation. */
3346 * This value indicates the offset in bytes from the beginning of the packet
3347 * where the inner payload starts. This value is valid for TCP, UDP,
3348 * FCoE, and RoCE packets.
3350 * A value of zero indicates an offset of 256 bytes.
3352 uint8_t payload_offset;
3354 /* unused2 is 1 b */
3355 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3357 * This is the aggregation ID that the completion is associated
3358 * with. Use this number to correlate the TPA start completion
3359 * with the TPA end completion.
3361 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3362 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3364 * For non-GRO packets, this value is the
3365 * timestamp delta between earliest and latest timestamp values for
3366 * TPA packet. If packets were not time stamped, then delta will be
3369 * For GRO packets, this field is zero except for the following
3372 * Timestamp present indication. When '0', no Timestamp
3373 * option is in the packet. When '1', then a Timestamp
3374 * option is present in the packet.
3380 * Last 16 bytes of rx_tpa_end_cmpl.
3382 * This TPA completion structure is used on devices where the
3383 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
3385 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3386 struct rx_tpa_end_cmpl_hi {
3387 uint32_t tpa_dup_acks;
3389 * This value is the number of duplicate ACKs that have been
3390 * received as part of the TPA operation.
3392 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3393 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3395 * This value is the valid when TPA completion is active. It
3396 * indicates the length of the longest segment of the TPA operation
3397 * for LRO mode and the length of the first segment in GRO mode.
3399 * This value may be used by GRO software to re-construct the original
3400 * packet stream from the TPA packet. This is the length of all
3401 * but the last segment for GRO. In LRO mode this value may be used
3402 * to indicate MSS size to the stack.
3404 uint16_t tpa_seg_len;
3405 /* unused4 is 16 b */
3409 * This value is written by the NIC such that it will be different
3410 * for each pass through the completion queue. The even passes
3411 * will write 1. The odd passes will write 0.
3413 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3414 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3415 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3417 * This error indicates that there was some sort of problem with
3418 * the BDs for the packet that was found after part of the
3419 * packet was already placed. The packet should be treated as
3422 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3423 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3425 * This error occurs when there is a fatal HW problem in
3426 * the chip only. It indicates that there were not
3427 * BDs on chip but that there was adequate reservation.
3428 * provided by the TPA block.
3430 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3431 (UINT32_C(0x2) << 1)
3433 * This error occurs when TPA block was not configured to
3434 * reserve adequate BDs for TPA operations on this RX
3435 * ring. All data for the TPA operation was not placed.
3437 * This error can also be generated when the number of
3438 * segments is not programmed correctly in TPA and the
3439 * 33 total aggregation buffers allowed for the TPA
3440 * operation has been exceeded.
3442 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3443 (UINT32_C(0x4) << 1)
3444 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3445 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3446 /* unused5 is 16 b */
3449 * This is the opaque value that was completed for the TPA start
3450 * completion that corresponds to this TPA end completion.
3452 uint32_t start_opaque;
3456 * This TPA completion structure is used on devices where the
3457 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3459 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
3460 struct rx_tpa_v2_start_cmpl {
3461 uint16_t flags_type;
3463 * This field indicates the exact type of the completion.
3464 * By convention, the LSB identifies the length of the
3465 * record in 16B units. Even values indicate 16B
3466 * records. Odd values indicate 32B
3469 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
3471 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
3473 * RX L2 TPA Start Completion:
3474 * Completion at the beginning of a TPA operation.
3477 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
3479 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
3480 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
3481 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
3483 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
3484 /* This bit will always be '0' for TPA start completions. */
3485 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
3487 /* This field indicates how the packet was placed in the buffer. */
3488 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
3490 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
3493 * TPA Packet was placed using jumbo algorithm. This means
3494 * that the first buffer will be filled with data before
3495 * moving to aggregation buffers. Each aggregation buffer
3496 * will be filled before moving to the next aggregation
3499 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
3500 (UINT32_C(0x1) << 7)
3502 * Header/Data Separation:
3503 * Packet was placed using Header/Data separation algorithm.
3504 * The separation location is indicated by the itype field.
3506 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
3507 (UINT32_C(0x2) << 7)
3510 * Packet will be placed using GRO/Jumbo where the first
3511 * packet is filled with data. Subsequent packets will be
3512 * placed such that any one packet does not span two
3513 * aggregation buffers unless it starts at the beginning of
3514 * an aggregation buffer.
3516 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3517 (UINT32_C(0x5) << 7)
3519 * GRO/Header-Data Separation:
3520 * Packet will be placed using GRO/HDS where the header
3521 * is in the first packet.
3522 * Payload of each packet will be
3523 * placed such that any one packet does not span two
3524 * aggregation buffers unless it starts at the beginning of
3525 * an aggregation buffer.
3527 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3528 (UINT32_C(0x6) << 7)
3529 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
3530 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
3531 /* This bit is '1' if the RSS field in this completion is valid. */
3532 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
3535 * For devices that support timestamps, when this bit is cleared the
3536 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3537 * field contains the 32b timestamp for
3538 * the packet from the MAC. When this bit is set, the
3539 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
3540 * field contains the outer_l3_offset, inner_l2_offset,
3541 * inner_l3_offset, and inner_l4_size.
3543 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
3546 * This value indicates what the inner packet determined for the
3549 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
3551 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
3554 * Indicates that the packet was IP and TCP.
3556 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
3557 (UINT32_C(0x2) << 12)
3558 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
3559 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
3561 * This value indicates the amount of packet data written to the
3562 * buffer the opaque field in this completion corresponds to.
3566 * This is a copy of the opaque field from the RX BD this completion
3571 * This value is written by the NIC such that it will be different
3572 * for each pass through the completion queue. The even passes
3573 * will write 1. The odd passes will write 0.
3577 * This value is written by the NIC such that it will be different
3578 * for each pass through the completion queue. The even passes
3579 * will write 1. The odd passes will write 0.
3581 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
3582 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
3584 * This is the RSS hash type for the packet. The value is packed
3585 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3587 * The value of tuple_extrac_op provides the information about
3588 * what fields the hash was computed on.
3589 * * 0: The RSS hash was computed over source IP address,
3590 * destination IP address, source port, and destination port of inner
3591 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3592 * the packet headers are considered inner packet headers for the RSS
3593 * hash computation purpose.
3594 * * 1: The RSS hash was computed over source IP address and destination
3595 * IP address of inner IP header. Note: For non-tunneled packets,
3596 * the packet headers are considered inner packet headers for the RSS
3597 * hash computation purpose.
3598 * * 2: The RSS hash was computed over source IP address,
3599 * destination IP address, source port, and destination port of
3600 * IP and TCP or UDP headers of outer tunnel headers.
3601 * Note: For non-tunneled packets, this value is not applicable.
3602 * * 3: The RSS hash was computed over source IP address and
3603 * destination IP address of IP header of outer tunnel headers.
3604 * Note: For non-tunneled packets, this value is not applicable.
3606 * Note that 4-tuples values listed above are applicable
3607 * for layer 4 protocols supported and enabled for RSS in the hardware,
3608 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3609 * enabled for TCP traffic only, then the values of tuple_extract_op
3610 * corresponding to 4-tuples are only valid for TCP traffic.
3612 uint8_t rss_hash_type;
3614 * This is the aggregation ID that the completion is associated
3615 * with. Use this number to correlate the TPA start completion
3616 * with the TPA end completion.
3620 * This value is the RSS hash value calculated for the packet
3621 * based on the mode bits and key value in the VNIC.
3627 * Last 16 bytes of rx_tpa_v2_start_cmpl.
3629 * This TPA completion structure is used on devices where the
3630 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3632 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
3633 struct rx_tpa_v2_start_cmpl_hi {
3636 * This indicates that the ip checksum was calculated for the
3637 * inner packet and that the sum passed for all segments
3638 * included in the aggregation.
3640 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
3643 * This indicates that the TCP, UDP or ICMP checksum was
3644 * calculated for the inner packet and that the sum passed
3645 * for all segments included in the aggregation.
3647 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
3650 * This indicates that the ip checksum was calculated for the
3651 * tunnel header and that the sum passed for all segments
3652 * included in the aggregation.
3654 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
3657 * This indicates that the UDP checksum was
3658 * calculated for the tunnel packet and that the sum passed for
3659 * all segments included in the aggregation.
3661 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
3663 /* This value indicates what format the metadata field is. */
3664 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
3666 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
3667 /* No metadata informtaion. Value is zero. */
3668 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
3669 (UINT32_C(0x0) << 4)
3671 * The metadata field contains the VLAN tag and TPID value.
3672 * - metadata[11:0] contains the vlan VID value.
3673 * - metadata[12] contains the vlan DE value.
3674 * - metadata[15:13] contains the vlan PRI value.
3675 * - metadata[31:16] contains the vlan TPID value.
3677 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
3678 (UINT32_C(0x1) << 4)
3680 * If ext_meta_format is equal to 1, the metadata field
3681 * contains the lower 16b of the tunnel ID value, justified
3683 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3684 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3685 * - NVGRE = TNI[23:0] -> Tenant Network ID
3686 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
3687 * - IPV4 = 0 (not populated)
3688 * - IPV6 = Flow Label[19:0]
3689 * - PPPoE = sessionID[15:0]
3690 * - MPLs = Outer label[19:0]
3691 * - UPAR = Selected[31:0] with bit mask
3693 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3694 (UINT32_C(0x2) << 4)
3696 * if ext_meta_format is equal to 1, metadata field contains
3697 * 16b metadata from the prepended header (chdr_data).
3699 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3700 (UINT32_C(0x3) << 4)
3702 * If ext_meta_format is equal to 1, the metadata field contains
3703 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3705 * - metadata[8:0] contains the outer_l3_offset.
3706 * - metadata[17:9] contains the inner_l2_offset.
3707 * - metadata[26:18] contains the inner_l3_offset.
3708 * - metadata[31:27] contains the inner_l4_size.
3710 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3711 (UINT32_C(0x4) << 4)
3712 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
3713 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3715 * This field indicates the IP type for the inner-most IP header.
3716 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3718 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
3721 * This indicates that the complete 1's complement checksum was
3722 * calculated for the packet.
3724 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
3727 * The combination of this value and meta_format indicated what
3728 * format the metadata field is.
3730 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
3732 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3734 * This value is the complete 1's complement checksum calculated from
3735 * the start of the outer L3 header to the end of the packet (not
3736 * including the ethernet crc). It is valid when the
3737 * 'complete_checksum_calc' flag is set. For TPA Start completions,
3738 * the complete checksum is calculated for the first packet in the
3741 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3742 UINT32_C(0xffff0000)
3743 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3745 * This is data from the CFA block as indicated by the meta_format
3749 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
3750 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3751 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
3752 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
3753 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
3754 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
3755 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3756 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
3757 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
3758 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3759 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
3762 * This value is written by the NIC such that it will be different
3763 * for each pass through the completion queue. The even passes
3764 * will write 1. The odd passes will write 0.
3766 #define RX_TPA_V2_START_CMPL_V2 \
3768 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
3770 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
3772 * This error indicates that there was some sort of problem with
3773 * the BDs for the packet that was found after part of the
3774 * packet was already placed. The packet should be treated as
3777 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
3779 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3780 /* No buffer error */
3781 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3782 (UINT32_C(0x0) << 1)
3785 * BDs were not formatted correctly.
3787 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3788 (UINT32_C(0x3) << 1)
3791 * There was a bad_format error on the previous operation
3793 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3794 (UINT32_C(0x5) << 1)
3795 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
3796 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3798 * This field identifies the CFA action rule that was used for this
3803 * For devices that support timestamps this field is overridden
3804 * with the timestamp value. When `flags.timestamp_fld_format` is
3805 * cleared, this field contains the 32b timestamp for the packet from the
3808 * When `flags.timestamp_fld_format` is set, this field contains the
3809 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
3812 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
3814 * This is the offset from the beginning of the packet in bytes for
3815 * the outer L3 header. If there is no outer L3 header, then this
3818 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
3819 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
3821 * This is the offset from the beginning of the packet in bytes for
3822 * the inner most L2 header.
3824 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
3825 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
3827 * This is the offset from the beginning of the packet in bytes for
3828 * the inner most L3 header.
3830 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
3831 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
3833 * This is the size in bytes of the inner most L4 header.
3834 * This can be subtracted from the payload_offset to determine
3835 * the start of the inner most L4 header.
3837 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
3838 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
3842 * This TPA completion structure is used on devices where the
3843 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3845 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
3846 struct rx_tpa_v2_end_cmpl {
3847 uint16_t flags_type;
3849 * This field indicates the exact type of the completion.
3850 * By convention, the LSB identifies the length of the
3851 * record in 16B units. Even values indicate 16B
3852 * records. Odd values indicate 32B
3855 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
3856 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
3858 * RX L2 TPA End Completion:
3859 * Completion at the end of a TPA operation.
3862 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
3863 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
3864 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
3865 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3866 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
3868 * When this bit is '1', it indicates a packet that has an
3869 * error of some type. Type of error is indicated in
3872 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
3873 /* This field indicates how the packet was placed in the buffer. */
3874 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3875 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
3878 * TPA Packet was placed using jumbo algorithm. This means
3879 * that the first buffer will be filled with data before
3880 * moving to aggregation buffers. Each aggregation buffer
3881 * will be filled before moving to the next aggregation
3884 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3885 (UINT32_C(0x1) << 7)
3887 * Header/Data Separation:
3888 * Packet was placed using Header/Data separation algorithm.
3889 * The separation location is indicated by the itype field.
3891 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
3892 (UINT32_C(0x2) << 7)
3895 * Packet will be placed using GRO/Jumbo where the first
3896 * packet is filled with data. Subsequent packets will be
3897 * placed such that any one packet does not span two
3898 * aggregation buffers unless it starts at the beginning of
3899 * an aggregation buffer.
3901 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3902 (UINT32_C(0x5) << 7)
3904 * GRO/Header-Data Separation:
3905 * Packet will be placed using GRO/HDS where the header
3906 * is in the first packet.
3907 * Payload of each packet will be
3908 * placed such that any one packet does not span two
3909 * aggregation buffers unless it starts at the beginning of
3910 * an aggregation buffer.
3912 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3913 (UINT32_C(0x6) << 7)
3914 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
3915 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3917 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3918 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
3920 * This value indicates what the inner packet determined for the
3923 * Indicates that the packet was IP and TCP. This indicates
3924 * that the ip_cs field is valid and that the tcp_udp_cs
3925 * field is valid and contains the TCP checksum.
3926 * This also indicates that the payload_offset field is valid.
3928 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3929 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
3931 * This value is zero for TPA End completions.
3932 * There is no data in the buffer that corresponds to the opaque
3933 * value in this completion.
3937 * This is a copy of the opaque field from the RX BD this completion
3943 * This value is written by the NIC such that it will be different
3944 * for each pass through the completion queue. The even passes
3945 * will write 1. The odd passes will write 0.
3947 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
3948 /* This value is the number of segments in the TPA operation. */
3951 * This is the aggregation ID that the completion is associated
3952 * with. Use this number to correlate the TPA start completion
3953 * with the TPA end completion.
3957 * For non-GRO packets, this value is the
3958 * timestamp delta between earliest and latest timestamp values for
3959 * TPA packet. If packets were not time stamped, then delta will be
3962 * For GRO packets, this field is zero except for the following
3965 * Timestamp present indication. When '0', no Timestamp
3966 * option is in the packet. When '1', then a Timestamp
3967 * option is present in the packet.
3973 * Last 16 bytes of rx_tpa_v2_end_cmpl.
3975 * This TPA completion structure is used on devices where the
3976 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
3978 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
3979 struct rx_tpa_v2_end_cmpl_hi {
3981 * This value is the number of duplicate ACKs that have been
3982 * received as part of the TPA operation.
3984 uint16_t tpa_dup_acks;
3986 * This value is the number of duplicate ACKs that have been
3987 * received as part of the TPA operation.
3989 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3990 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
3992 * This value indicated the offset in bytes from the beginning of
3993 * the packet where the inner payload starts. This value is valid
3994 * for TCP, UDP, FCoE and RoCE packets
3996 uint8_t payload_offset;
3998 * The value is the total number of aggregation buffers that were
3999 * used in the TPA operation. All TPA aggregation buffer completions
4000 * precede the TPA End completion. If the value is zero, then the
4001 * aggregation is completely contained in the buffer space provided
4002 * in the aggregation start completion.
4003 * Note that the field is simply provided as a cross check.
4005 uint8_t tpa_agg_bufs;
4007 * This value is the valid when TPA completion is active. It
4008 * indicates the length of the longest segment of the TPA operation
4009 * for LRO mode and the length of the first segment in GRO mode.
4011 * This value may be used by GRO software to re-construct the original
4012 * packet stream from the TPA packet. This is the length of all
4013 * but the last segment for GRO. In LRO mode this value may be used
4014 * to indicate MSS size to the stack.
4016 uint16_t tpa_seg_len;
4020 * This value is written by the NIC such that it will be different
4021 * for each pass through the completion queue. The even passes
4022 * will write 1. The odd passes will write 0.
4024 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
4025 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
4027 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
4029 * This error indicates that there was some sort of problem with
4030 * the BDs for the packet that was found after part of the
4031 * packet was already placed. The packet should be treated as
4034 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
4036 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4037 /* No buffer error */
4038 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4039 (UINT32_C(0x0) << 1)
4041 * This error occurs when there is a fatal HW problem in
4042 * the chip only. It indicates that there were not
4043 * BDs on chip but that there was adequate reservation.
4044 * provided by the TPA block.
4046 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4047 (UINT32_C(0x2) << 1)
4050 * BDs were not formatted correctly.
4052 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4053 (UINT32_C(0x3) << 1)
4055 * This error occurs when TPA block was not configured to
4056 * reserve adequate BDs for TPA operations on this RX
4057 * ring. All data for the TPA operation was not placed.
4059 * This error can also be generated when the number of
4060 * segments is not programmed correctly in TPA and the
4061 * 33 total aggregation buffers allowed for the TPA
4062 * operation has been exceeded.
4064 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4065 (UINT32_C(0x4) << 1)
4068 * There was a bad_format error on the previous operation
4070 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4071 (UINT32_C(0x5) << 1)
4072 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4073 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4076 * This is the opaque value that was completed for the TPA start
4077 * completion that corresponds to this TPA end completion.
4079 uint32_t start_opaque;
4083 * This TPA completion structure is used on devices where the
4084 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4086 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
4087 struct rx_tpa_v2_abuf_cmpl {
4090 * This field indicates the exact type of the completion.
4091 * By convention, the LSB identifies the length of the
4092 * record in 16B units. Even values indicate 16B
4093 * records. Odd values indicate 32B
4096 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4097 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
4099 * RX TPA Aggregation Buffer completion :
4100 * Completion of an L2 aggregation buffer in support of
4101 * TPA packet completion. Length = 16B
4103 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
4104 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
4105 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
4107 * This is the length of the data for the packet stored in this
4108 * aggregation buffer identified by the opaque value. This does not
4109 * include the length of any
4110 * data placed in other aggregation BDs or in the packet or buffer
4111 * BDs. This length does not include any space added due to
4112 * hdr_offset register during HDS placement mode.
4116 * This is a copy of the opaque field from the RX BD this aggregation
4117 * buffer corresponds to.
4122 * This value is written by the NIC such that it will be different
4123 * for each pass through the completion queue. The even passes
4124 * will write 1. The odd passes will write 0.
4126 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
4128 * This is the aggregation ID that the completion is associated with. Use
4129 * this number to correlate the TPA agg completion with the TPA start
4130 * completion and the TPA end completion.
4136 /* rx_abuf_cmpl (size:128b/16B) */
4137 struct rx_abuf_cmpl {
4140 * This field indicates the exact type of the completion.
4141 * By convention, the LSB identifies the length of the
4142 * record in 16B units. Even values indicate 16B
4143 * records. Odd values indicate 32B
4146 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
4147 #define RX_ABUF_CMPL_TYPE_SFT 0
4149 * RX Aggregation Buffer completion :
4150 * Completion of an L2 aggregation buffer in support of
4151 * TPA, HDS, or Jumbo packet completion. Length = 16B
4153 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
4154 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
4156 * This is the length of the data for the packet stored in this
4157 * aggregation buffer identified by the opaque value. This does not
4158 * include the length of any
4159 * data placed in other aggregation BDs or in the packet or buffer
4160 * BDs. This length does not include any space added due to
4161 * hdr_offset register during HDS placement mode.
4165 * This is a copy of the opaque field from the RX BD this aggregation
4166 * buffer corresponds to.
4171 * This value is written by the NIC such that it will be different
4172 * for each pass through the completion queue. The even passes
4173 * will write 1. The odd passes will write 0.
4175 #define RX_ABUF_CMPL_V UINT32_C(0x1)
4176 /* unused3 is 32 b */
4180 /* eject_cmpl (size:128b/16B) */
4184 * This field indicates the exact type of the completion.
4185 * By convention, the LSB identifies the length of the
4186 * record in 16B units. Even values indicate 16B
4187 * records. Odd values indicate 32B
4190 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
4191 #define EJECT_CMPL_TYPE_SFT 0
4193 * Statistics Ejection Completion:
4194 * Completion of statistics data ejection buffer.
4197 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
4198 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
4199 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4200 #define EJECT_CMPL_FLAGS_SFT 6
4202 * When this bit is '1', it indicates a packet that has an
4203 * error of some type. Type of error is indicated in
4206 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4208 * This is the length of the statistics data stored in this
4213 * This is a copy of the opaque field from the RX BD this ejection
4214 * buffer corresponds to.
4219 * This value is written by the NIC such that it will be different
4220 * for each pass through the completion queue. The even passes
4221 * will write 1. The odd passes will write 0.
4223 #define EJECT_CMPL_V UINT32_C(0x1)
4224 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4225 #define EJECT_CMPL_ERRORS_SFT 1
4227 * This error indicates that there was some sort of problem with
4228 * the BDs for statistics ejection. The statistics ejection should
4229 * be treated as invalid
4231 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4232 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4233 /* No buffer error */
4234 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4235 (UINT32_C(0x0) << 1)
4238 * Statistics did not fit into aggregation buffer provided.
4240 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4241 (UINT32_C(0x1) << 1)
4244 * BDs were not formatted correctly.
4246 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4247 (UINT32_C(0x3) << 1)
4250 * There was a bad_format error on the previous operation
4252 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4253 (UINT32_C(0x5) << 1)
4254 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4255 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4256 /* reserved16 is 16 b */
4257 uint16_t reserved16;
4258 /* unused3 is 32 b */
4262 /* hwrm_cmpl (size:128b/16B) */
4266 * This field indicates the exact type of the completion.
4267 * By convention, the LSB identifies the length of the
4268 * record in 16B units. Even values indicate 16B
4269 * records. Odd values indicate 32B
4272 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
4273 #define HWRM_CMPL_TYPE_SFT 0
4275 * HWRM Command Completion:
4276 * Completion of an HWRM command.
4278 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
4279 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
4280 /* This is the sequence_id of the HWRM command that has completed. */
4281 uint16_t sequence_id;
4282 /* unused2 is 32 b */
4286 * This value is written by the NIC such that it will be different
4287 * for each pass through the completion queue. The even passes
4288 * will write 1. The odd passes will write 0.
4290 #define HWRM_CMPL_V UINT32_C(0x1)
4291 /* unused4 is 32 b */
4295 /* hwrm_fwd_req_cmpl (size:128b/16B) */
4296 struct hwrm_fwd_req_cmpl {
4298 * This field indicates the exact type of the completion.
4299 * By convention, the LSB identifies the length of the
4300 * record in 16B units. Even values indicate 16B
4301 * records. Odd values indicate 32B
4304 uint16_t req_len_type;
4306 * This field indicates the exact type of the completion.
4307 * By convention, the LSB identifies the length of the
4308 * record in 16B units. Even values indicate 16B
4309 * records. Odd values indicate 32B
4312 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
4313 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
4314 /* Forwarded HWRM Request */
4315 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4316 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
4317 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
4318 /* Length of forwarded request in bytes. */
4319 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
4320 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
4322 * Source ID of this request.
4323 * Typically used in forwarding requests and responses.
4324 * 0x0 - 0xFFF8 - Used for function ids
4325 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4329 /* unused1 is 32 b */
4331 /* Address of forwarded request. */
4332 uint32_t req_buf_addr_v[2];
4334 * This value is written by the NIC such that it will be different
4335 * for each pass through the completion queue. The even passes
4336 * will write 1. The odd passes will write 0.
4338 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
4339 /* Address of forwarded request. */
4340 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4341 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
4344 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
4345 struct hwrm_fwd_resp_cmpl {
4348 * This field indicates the exact type of the completion.
4349 * By convention, the LSB identifies the length of the
4350 * record in 16B units. Even values indicate 16B
4351 * records. Odd values indicate 32B
4354 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
4355 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
4356 /* Forwarded HWRM Response */
4357 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4358 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
4359 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
4361 * Source ID of this response.
4362 * Typically used in forwarding requests and responses.
4363 * 0x0 - 0xFFF8 - Used for function ids
4364 * 0xFFF8 - 0xFFFE - Reserved for internal processors
4368 /* Length of forwarded response in bytes. */
4370 /* unused2 is 16 b */
4372 /* Address of forwarded request. */
4373 uint32_t resp_buf_addr_v[2];
4375 * This value is written by the NIC such that it will be different
4376 * for each pass through the completion queue. The even passes
4377 * will write 1. The odd passes will write 0.
4379 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
4380 /* Address of forwarded request. */
4381 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
4382 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
4385 /* hwrm_async_event_cmpl (size:128b/16B) */
4386 struct hwrm_async_event_cmpl {
4389 * This field indicates the exact type of the completion.
4390 * By convention, the LSB identifies the length of the
4391 * record in 16B units. Even values indicate 16B
4392 * records. Odd values indicate 32B
4395 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
4396 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
4397 /* HWRM Asynchronous Event Information */
4398 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4399 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
4400 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
4401 /* Identifiers of events. */
4403 /* Link status changed */
4404 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
4406 /* Link MTU changed */
4407 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
4409 /* Link speed changed */
4410 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
4412 /* DCB Configuration changed */
4413 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
4415 /* Port connection not allowed */
4416 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4418 /* Link speed configuration was not allowed */
4419 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4421 /* Link speed configuration change */
4422 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
4424 /* Port PHY configuration change */
4425 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
4427 /* Reset notification to clients */
4428 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
4430 /* Master function selection event */
4431 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
4433 /* Function driver unloaded */
4434 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
4436 /* Function driver loaded */
4437 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
4439 /* Function FLR related processing has completed */
4440 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4442 /* PF driver unloaded */
4443 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
4445 /* PF driver loaded */
4446 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
4448 /* VF Function Level Reset (FLR) */
4449 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
4451 /* VF MAC Address Change */
4452 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
4454 /* PF-VF communication channel status change. */
4455 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4457 /* VF Configuration Change */
4458 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
4460 /* LLFC/PFC Configuration Change */
4461 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
4463 /* Default VNIC Configuration Change */
4464 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
4467 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
4470 * A debug notification being posted to the driver. These
4471 * notifications are purely for diagnostic purpose and should not be
4472 * used for functional purpose. The driver is not supposed to act
4473 * on these messages except to log/record it.
4475 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
4478 * An EEM flow cached memory flush for all flows request event being
4479 * posted to the PF driver.
4481 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
4484 * An EEM flow cache memory flush completion event being posted to the
4485 * firmware by the PF driver. This is indication that host EEM flush
4486 * has completed by the PF.
4488 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
4491 * A tcp flag action change event being posted to the PF or trusted VF
4492 * driver by the firmware. The PF or trusted VF driver should query
4493 * the firmware for the new TCP flag action update after receiving
4496 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
4499 * An EEM flow active event being posted to the PF or trusted VF driver
4500 * by the firmware. The PF or trusted VF driver should update the
4501 * flow's aging timer after receiving this async event.
4503 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
4506 * A eem cfg change event being posted to the trusted VF driver by the
4507 * firmware if the parent PF EEM configuration changed.
4509 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
4511 /* TFLIB unique default VNIC Configuration Change */
4512 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
4514 /* TFLIB unique link status changed */
4515 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
4518 * An event signifying completion for HWRM_FW_STATE_QUIESCE
4519 * (completion, timeout, or error)
4521 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
4524 * A trace log message. This contains firmware trace logs string
4525 * embedded in the asynchronous message. This is an experimental
4526 * event, not meant for production use at this time.
4528 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
4531 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
4533 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
4534 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
4535 /* Event specific data */
4536 uint32_t event_data2;
4539 * This value is written by the NIC such that it will be different
4540 * for each pass through the completion queue. The even passes
4541 * will write 1. The odd passes will write 0.
4543 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
4545 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
4546 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
4547 /* 8-lsb timestamp from POR (100-msec resolution) */
4548 uint8_t timestamp_lo;
4549 /* 16-lsb timestamp from POR (100-msec resolution) */
4550 uint16_t timestamp_hi;
4551 /* Event specific data */
4552 uint32_t event_data1;
4555 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
4556 struct hwrm_async_event_cmpl_link_status_change {
4559 * This field indicates the exact type of the completion.
4560 * By convention, the LSB identifies the length of the
4561 * record in 16B units. Even values indicate 16B
4562 * records. Odd values indicate 32B
4565 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
4567 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
4568 /* HWRM Asynchronous Event Information */
4569 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4571 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
4572 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4573 /* Identifiers of events. */
4575 /* Link status changed */
4576 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
4578 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
4579 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
4580 /* Event specific data */
4581 uint32_t event_data2;
4584 * This value is written by the NIC such that it will be different
4585 * for each pass through the completion queue. The even passes
4586 * will write 1. The odd passes will write 0.
4588 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
4591 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
4593 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
4594 /* 8-lsb timestamp from POR (100-msec resolution) */
4595 uint8_t timestamp_lo;
4596 /* 16-lsb timestamp from POR (100-msec resolution) */
4597 uint16_t timestamp_hi;
4598 /* Event specific data */
4599 uint32_t event_data1;
4600 /* Indicates link status change */
4601 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
4604 * If this bit set to 0, then it indicates that the link
4605 * was up and it went down.
4607 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
4610 * If this bit is set to 1, then it indicates that the link
4611 * was down and it went up.
4613 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
4615 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
4616 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
4617 /* Indicates the physical port this link status change occur */
4618 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
4620 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
4623 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4625 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4627 /* Indicates the physical function this event occurred on. */
4628 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
4630 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
4634 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
4635 struct hwrm_async_event_cmpl_link_mtu_change {
4638 * This field indicates the exact type of the completion.
4639 * By convention, the LSB identifies the length of the
4640 * record in 16B units. Even values indicate 16B
4641 * records. Odd values indicate 32B
4644 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
4646 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
4647 /* HWRM Asynchronous Event Information */
4648 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4650 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
4651 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
4652 /* Identifiers of events. */
4654 /* Link MTU changed */
4655 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
4657 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
4658 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
4659 /* Event specific data */
4660 uint32_t event_data2;
4663 * This value is written by the NIC such that it will be different
4664 * for each pass through the completion queue. The even passes
4665 * will write 1. The odd passes will write 0.
4667 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
4669 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
4671 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
4672 /* 8-lsb timestamp from POR (100-msec resolution) */
4673 uint8_t timestamp_lo;
4674 /* 16-lsb timestamp from POR (100-msec resolution) */
4675 uint16_t timestamp_hi;
4676 /* Event specific data */
4677 uint32_t event_data1;
4678 /* The new MTU of the link in bytes. */
4679 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
4681 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
4684 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
4685 struct hwrm_async_event_cmpl_link_speed_change {
4688 * This field indicates the exact type of the completion.
4689 * By convention, the LSB identifies the length of the
4690 * record in 16B units. Even values indicate 16B
4691 * records. Odd values indicate 32B
4694 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
4696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
4697 /* HWRM Asynchronous Event Information */
4698 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4700 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
4701 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
4702 /* Identifiers of events. */
4704 /* Link speed changed */
4705 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
4707 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
4708 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
4709 /* Event specific data */
4710 uint32_t event_data2;
4713 * This value is written by the NIC such that it will be different
4714 * for each pass through the completion queue. The even passes
4715 * will write 1. The odd passes will write 0.
4717 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
4720 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
4722 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
4723 /* 8-lsb timestamp from POR (100-msec resolution) */
4724 uint8_t timestamp_lo;
4725 /* 16-lsb timestamp from POR (100-msec resolution) */
4726 uint16_t timestamp_hi;
4727 /* Event specific data */
4728 uint32_t event_data1;
4730 * When this bit is '1', the link was forced to the
4731 * force_link_speed value.
4733 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
4735 /* The new link speed in 100 Mbps units. */
4736 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
4738 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
4740 /* 100Mb link speed */
4741 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
4742 (UINT32_C(0x1) << 1)
4743 /* 1Gb link speed */
4744 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
4745 (UINT32_C(0xa) << 1)
4746 /* 2Gb link speed */
4747 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
4748 (UINT32_C(0x14) << 1)
4749 /* 25Gb link speed */
4750 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
4751 (UINT32_C(0x19) << 1)
4752 /* 10Gb link speed */
4753 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
4754 (UINT32_C(0x64) << 1)
4755 /* 20Mb link speed */
4756 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
4757 (UINT32_C(0xc8) << 1)
4758 /* 25Gb link speed */
4759 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
4760 (UINT32_C(0xfa) << 1)
4761 /* 40Gb link speed */
4762 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
4763 (UINT32_C(0x190) << 1)
4764 /* 50Gb link speed */
4765 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
4766 (UINT32_C(0x1f4) << 1)
4767 /* 100Gb link speed */
4768 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
4769 (UINT32_C(0x3e8) << 1)
4770 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
4771 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
4773 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4774 UINT32_C(0xffff0000)
4775 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4779 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
4780 struct hwrm_async_event_cmpl_dcb_config_change {
4783 * This field indicates the exact type of the completion.
4784 * By convention, the LSB identifies the length of the
4785 * record in 16B units. Even values indicate 16B
4786 * records. Odd values indicate 32B
4789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
4791 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
4792 /* HWRM Asynchronous Event Information */
4793 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4795 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
4796 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4797 /* Identifiers of events. */
4799 /* DCB Configuration changed */
4800 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
4802 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
4803 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
4804 /* Event specific data */
4805 uint32_t event_data2;
4806 /* ETS configuration change */
4807 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
4809 /* PFC configuration change */
4810 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
4812 /* APP configuration change */
4813 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
4817 * This value is written by the NIC such that it will be different
4818 * for each pass through the completion queue. The even passes
4819 * will write 1. The odd passes will write 0.
4821 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
4824 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
4826 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
4827 /* 8-lsb timestamp from POR (100-msec resolution) */
4828 uint8_t timestamp_lo;
4829 /* 16-lsb timestamp from POR (100-msec resolution) */
4830 uint16_t timestamp_hi;
4831 /* Event specific data */
4832 uint32_t event_data1;
4834 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4836 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4838 /* Priority recommended for RoCE traffic */
4839 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
4841 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
4844 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
4845 (UINT32_C(0xff) << 16)
4846 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
4847 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
4848 /* Priority recommended for L2 traffic */
4849 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
4850 UINT32_C(0xff000000)
4851 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
4854 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
4855 (UINT32_C(0xff) << 24)
4856 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
4857 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
4860 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
4861 struct hwrm_async_event_cmpl_port_conn_not_allowed {
4864 * This field indicates the exact type of the completion.
4865 * By convention, the LSB identifies the length of the
4866 * record in 16B units. Even values indicate 16B
4867 * records. Odd values indicate 32B
4870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
4872 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
4874 /* HWRM Asynchronous Event Information */
4875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4877 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
4878 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4879 /* Identifiers of events. */
4881 /* Port connection not allowed */
4882 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
4884 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
4885 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
4886 /* Event specific data */
4887 uint32_t event_data2;
4890 * This value is written by the NIC such that it will be different
4891 * for each pass through the completion queue. The even passes
4892 * will write 1. The odd passes will write 0.
4894 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
4897 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
4899 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
4900 /* 8-lsb timestamp from POR (100-msec resolution) */
4901 uint8_t timestamp_lo;
4902 /* 16-lsb timestamp from POR (100-msec resolution) */
4903 uint16_t timestamp_hi;
4904 /* Event specific data */
4905 uint32_t event_data1;
4907 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4909 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4912 * This value indicates the current port level enforcement policy
4913 * for the optics module when there is an optical module mismatch
4914 * and port is not connected.
4916 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
4918 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
4920 /* No enforcement */
4921 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
4922 (UINT32_C(0x0) << 16)
4923 /* Disable Transmit side Laser. */
4924 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
4925 (UINT32_C(0x1) << 16)
4926 /* Raise a warning message. */
4927 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
4928 (UINT32_C(0x2) << 16)
4929 /* Power down the module. */
4930 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
4931 (UINT32_C(0x3) << 16)
4932 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
4933 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
4936 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
4937 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
4940 * This field indicates the exact type of the completion.
4941 * By convention, the LSB identifies the length of the
4942 * record in 16B units. Even values indicate 16B
4943 * records. Odd values indicate 32B
4946 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
4948 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
4950 /* HWRM Asynchronous Event Information */
4951 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
4953 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
4954 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
4955 /* Identifiers of events. */
4957 /* Link speed configuration was not allowed */
4958 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
4960 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
4961 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
4962 /* Event specific data */
4963 uint32_t event_data2;
4966 * This value is written by the NIC such that it will be different
4967 * for each pass through the completion queue. The even passes
4968 * will write 1. The odd passes will write 0.
4970 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
4973 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
4975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
4976 /* 8-lsb timestamp from POR (100-msec resolution) */
4977 uint8_t timestamp_lo;
4978 /* 16-lsb timestamp from POR (100-msec resolution) */
4979 uint16_t timestamp_hi;
4980 /* Event specific data */
4981 uint32_t event_data1;
4983 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
4985 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
4989 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
4990 struct hwrm_async_event_cmpl_link_speed_cfg_change {
4993 * This field indicates the exact type of the completion.
4994 * By convention, the LSB identifies the length of the
4995 * record in 16B units. Even values indicate 16B
4996 * records. Odd values indicate 32B
4999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
5001 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
5003 /* HWRM Asynchronous Event Information */
5004 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5006 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
5007 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5008 /* Identifiers of events. */
5010 /* Link speed configuration change */
5011 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
5013 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
5014 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
5015 /* Event specific data */
5016 uint32_t event_data2;
5019 * This value is written by the NIC such that it will be different
5020 * for each pass through the completion queue. The even passes
5021 * will write 1. The odd passes will write 0.
5023 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
5026 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
5028 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
5029 /* 8-lsb timestamp from POR (100-msec resolution) */
5030 uint8_t timestamp_lo;
5031 /* 16-lsb timestamp from POR (100-msec resolution) */
5032 uint16_t timestamp_hi;
5033 /* Event specific data */
5034 uint32_t event_data1;
5036 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5038 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5041 * If set to 1, it indicates that the supported link speeds
5042 * configuration on the port has changed.
5043 * If set to 0, then there is no change in supported link speeds
5046 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
5049 * If set to 1, it indicates that the link speed configuration
5050 * on the port has become illegal or invalid.
5051 * If set to 0, then the link speed configuration on the port is
5054 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
5058 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
5059 struct hwrm_async_event_cmpl_port_phy_cfg_change {
5062 * This field indicates the exact type of the completion.
5063 * By convention, the LSB identifies the length of the
5064 * record in 16B units. Even values indicate 16B
5065 * records. Odd values indicate 32B
5068 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
5070 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
5072 /* HWRM Asynchronous Event Information */
5073 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5075 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
5076 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5077 /* Identifiers of events. */
5079 /* Port PHY configuration change */
5080 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
5082 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
5083 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
5084 /* Event specific data */
5085 uint32_t event_data2;
5088 * This value is written by the NIC such that it will be different
5089 * for each pass through the completion queue. The even passes
5090 * will write 1. The odd passes will write 0.
5092 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
5095 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
5097 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
5098 /* 8-lsb timestamp from POR (100-msec resolution) */
5099 uint8_t timestamp_lo;
5100 /* 16-lsb timestamp from POR (100-msec resolution) */
5101 uint16_t timestamp_hi;
5102 /* Event specific data */
5103 uint32_t event_data1;
5105 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5107 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5110 * If set to 1, it indicates that the FEC
5111 * configuration on the port has changed.
5112 * If set to 0, then there is no change in FEC configuration.
5114 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
5117 * If set to 1, it indicates that the EEE configuration
5118 * on the port has changed.
5119 * If set to 0, then there is no change in EEE configuration
5122 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
5125 * If set to 1, it indicates that the pause configuration
5126 * on the PHY has changed.
5127 * If set to 0, then there is no change in the pause
5128 * configuration on the PHY.
5130 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
5134 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
5135 struct hwrm_async_event_cmpl_reset_notify {
5138 * This field indicates the exact type of the completion.
5139 * By convention, the LSB identifies the length of the
5140 * record in 16B units. Even values indicate 16B
5141 * records. Odd values indicate 32B
5144 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
5146 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
5147 /* HWRM Asynchronous Event Information */
5148 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
5150 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
5151 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
5152 /* Identifiers of events. */
5154 /* Notify clients of imminent reset. */
5155 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
5157 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
5158 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
5159 /* Event specific data */
5160 uint32_t event_data2;
5163 * This value is written by the NIC such that it will be different
5164 * for each pass through the completion queue. The even passes
5165 * will write 1. The odd passes will write 0.
5167 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
5169 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
5170 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
5172 * 8-lsb timestamp (100-msec resolution)
5173 * The Minimum time required for the Firmware readiness after sending this
5174 * notification to the driver instances.
5176 uint8_t timestamp_lo;
5178 * 16-lsb timestamp (100-msec resolution)
5179 * The Maximum Firmware Reset bail out value in the order of 100
5180 * milli seconds. The driver instances will use this value to re-initiate the
5181 * registration process again if the core firmware didn’t set the ready
5184 uint16_t timestamp_hi;
5185 /* Event specific data */
5186 uint32_t event_data1;
5187 /* Indicates driver action requested */
5188 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
5190 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
5193 * If set to 1, it indicates that the l2 client should
5194 * stop sending in band traffic to Nitro.
5195 * if set to 0, there is no change in L2 client behavior.
5197 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
5200 * If set to 1, it indicates that the L2 client should
5201 * bring down the interface.
5202 * If set to 0, then there is no change in L2 client behavior.
5204 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
5206 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
5207 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
5208 /* Indicates reason for reset. */
5209 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
5211 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
5213 /* A management client has requested reset. */
5214 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
5215 (UINT32_C(0x1) << 8)
5216 /* A fatal firmware exception has occurred. */
5217 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
5218 (UINT32_C(0x2) << 8)
5219 /* A non-fatal firmware exception has occurred. */
5220 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
5221 (UINT32_C(0x3) << 8)
5222 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
5223 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
5225 * Minimum time before driver should attempt access - units 100ms ticks.
5228 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
5229 UINT32_C(0xffff0000)
5230 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
5234 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
5235 struct hwrm_async_event_cmpl_error_recovery {
5238 * This field indicates the exact type of the completion.
5239 * By convention, the LSB identifies the length of the
5240 * record in 16B units. Even values indicate 16B
5241 * records. Odd values indicate 32B
5244 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
5246 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
5247 /* HWRM Asynchronous Event Information */
5248 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
5250 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
5251 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
5252 /* Identifiers of events. */
5255 * This async notification message can be used for selecting or
5256 * deselecting master function for error recovery,
5257 * and to communicate to all the functions whether error recovery
5258 * was enabled/disabled.
5260 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
5262 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
5263 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
5264 /* Event specific data */
5265 uint32_t event_data2;
5268 * This value is written by the NIC such that it will be different
5269 * for each pass through the completion queue. The even passes
5270 * will write 1. The odd passes will write 0.
5272 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
5274 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
5275 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
5276 /* 8-lsb timestamp (100-msec resolution) */
5277 uint8_t timestamp_lo;
5278 /* 16-lsb timestamp (100-msec resolution) */
5279 uint16_t timestamp_hi;
5280 /* Event specific data */
5281 uint32_t event_data1;
5282 /* Indicates driver action requested */
5283 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
5285 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
5288 * If set to 1, this function is selected as Master function.
5289 * This function has responsibility to do 'chip reset' when it
5290 * detects a fatal error. If set to 0, master function functionality
5291 * is disabled on this function.
5293 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
5296 * If set to 1, error recovery is enabled.
5297 * If set to 0, error recovery is disabled.
5299 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
5303 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
5304 struct hwrm_async_event_cmpl_func_drvr_unload {
5307 * This field indicates the exact type of the completion.
5308 * By convention, the LSB identifies the length of the
5309 * record in 16B units. Even values indicate 16B
5310 * records. Odd values indicate 32B
5313 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
5315 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
5316 /* HWRM Asynchronous Event Information */
5317 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5319 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
5320 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5321 /* Identifiers of events. */
5323 /* Function driver unloaded */
5324 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
5326 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
5327 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
5328 /* Event specific data */
5329 uint32_t event_data2;
5332 * This value is written by the NIC such that it will be different
5333 * for each pass through the completion queue. The even passes
5334 * will write 1. The odd passes will write 0.
5336 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
5338 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
5340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
5341 /* 8-lsb timestamp from POR (100-msec resolution) */
5342 uint8_t timestamp_lo;
5343 /* 16-lsb timestamp from POR (100-msec resolution) */
5344 uint16_t timestamp_hi;
5345 /* Event specific data */
5346 uint32_t event_data1;
5348 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5350 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
5354 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
5355 struct hwrm_async_event_cmpl_func_drvr_load {
5358 * This field indicates the exact type of the completion.
5359 * By convention, the LSB identifies the length of the
5360 * record in 16B units. Even values indicate 16B
5361 * records. Odd values indicate 32B
5364 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
5366 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
5367 /* HWRM Asynchronous Event Information */
5368 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5370 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
5371 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5372 /* Identifiers of events. */
5374 /* Function driver loaded */
5375 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
5377 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
5378 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
5379 /* Event specific data */
5380 uint32_t event_data2;
5383 * This value is written by the NIC such that it will be different
5384 * for each pass through the completion queue. The even passes
5385 * will write 1. The odd passes will write 0.
5387 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
5389 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5390 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
5391 /* 8-lsb timestamp from POR (100-msec resolution) */
5392 uint8_t timestamp_lo;
5393 /* 16-lsb timestamp from POR (100-msec resolution) */
5394 uint16_t timestamp_hi;
5395 /* Event specific data */
5396 uint32_t event_data1;
5398 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5400 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5403 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
5404 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
5407 * This field indicates the exact type of the completion.
5408 * By convention, the LSB identifies the length of the
5409 * record in 16B units. Even values indicate 16B
5410 * records. Odd values indicate 32B
5413 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
5415 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
5417 /* HWRM Asynchronous Event Information */
5418 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
5420 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
5421 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
5422 /* Identifiers of events. */
5424 /* Function FLR related processing has completed */
5425 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
5427 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
5428 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
5429 /* Event specific data */
5430 uint32_t event_data2;
5433 * This value is written by the NIC such that it will be different
5434 * for each pass through the completion queue. The even passes
5435 * will write 1. The odd passes will write 0.
5437 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
5440 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
5442 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
5443 /* 8-lsb timestamp from POR (100-msec resolution) */
5444 uint8_t timestamp_lo;
5445 /* 16-lsb timestamp from POR (100-msec resolution) */
5446 uint16_t timestamp_hi;
5447 /* Event specific data */
5448 uint32_t event_data1;
5450 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
5452 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
5456 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
5457 struct hwrm_async_event_cmpl_pf_drvr_unload {
5460 * This field indicates the exact type of the completion.
5461 * By convention, the LSB identifies the length of the
5462 * record in 16B units. Even values indicate 16B
5463 * records. Odd values indicate 32B
5466 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
5468 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
5469 /* HWRM Asynchronous Event Information */
5470 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
5472 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
5473 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
5474 /* Identifiers of events. */
5476 /* PF driver unloaded */
5477 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
5479 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
5480 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
5481 /* Event specific data */
5482 uint32_t event_data2;
5485 * This value is written by the NIC such that it will be different
5486 * for each pass through the completion queue. The even passes
5487 * will write 1. The odd passes will write 0.
5489 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
5491 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
5492 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
5493 /* 8-lsb timestamp from POR (100-msec resolution) */
5494 uint8_t timestamp_lo;
5495 /* 16-lsb timestamp from POR (100-msec resolution) */
5496 uint16_t timestamp_hi;
5497 /* Event specific data */
5498 uint32_t event_data1;
5500 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
5502 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
5503 /* Indicates the physical port this pf belongs to */
5504 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
5506 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
5509 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
5510 struct hwrm_async_event_cmpl_pf_drvr_load {
5513 * This field indicates the exact type of the completion.
5514 * By convention, the LSB identifies the length of the
5515 * record in 16B units. Even values indicate 16B
5516 * records. Odd values indicate 32B
5519 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
5521 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
5522 /* HWRM Asynchronous Event Information */
5523 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
5525 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
5526 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
5527 /* Identifiers of events. */
5529 /* PF driver loaded */
5530 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
5532 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
5533 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
5534 /* Event specific data */
5535 uint32_t event_data2;
5538 * This value is written by the NIC such that it will be different
5539 * for each pass through the completion queue. The even passes
5540 * will write 1. The odd passes will write 0.
5542 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
5544 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
5545 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
5546 /* 8-lsb timestamp from POR (100-msec resolution) */
5547 uint8_t timestamp_lo;
5548 /* 16-lsb timestamp from POR (100-msec resolution) */
5549 uint16_t timestamp_hi;
5550 /* Event specific data */
5551 uint32_t event_data1;
5553 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
5555 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
5556 /* Indicates the physical port this pf belongs to */
5557 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
5559 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
5562 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
5563 struct hwrm_async_event_cmpl_vf_flr {
5566 * This field indicates the exact type of the completion.
5567 * By convention, the LSB identifies the length of the
5568 * record in 16B units. Even values indicate 16B
5569 * records. Odd values indicate 32B
5572 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
5574 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
5575 /* HWRM Asynchronous Event Information */
5576 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
5578 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
5579 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
5580 /* Identifiers of events. */
5582 /* VF Function Level Reset (FLR) */
5583 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
5584 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
5585 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
5586 /* Event specific data */
5587 uint32_t event_data2;
5590 * This value is written by the NIC such that it will be different
5591 * for each pass through the completion queue. The even passes
5592 * will write 1. The odd passes will write 0.
5594 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
5596 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
5597 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
5598 /* 8-lsb timestamp from POR (100-msec resolution) */
5599 uint8_t timestamp_lo;
5600 /* 16-lsb timestamp from POR (100-msec resolution) */
5601 uint16_t timestamp_hi;
5602 /* Event specific data */
5603 uint32_t event_data1;
5605 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
5607 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
5608 /* Indicates the physical function this event occurred on. */
5609 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
5611 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
5614 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
5615 struct hwrm_async_event_cmpl_vf_mac_addr_change {
5618 * This field indicates the exact type of the completion.
5619 * By convention, the LSB identifies the length of the
5620 * record in 16B units. Even values indicate 16B
5621 * records. Odd values indicate 32B
5624 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
5626 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
5627 /* HWRM Asynchronous Event Information */
5628 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5630 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
5631 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
5632 /* Identifiers of events. */
5634 /* VF MAC Address Change */
5635 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
5637 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
5638 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
5639 /* Event specific data */
5640 uint32_t event_data2;
5643 * This value is written by the NIC such that it will be different
5644 * for each pass through the completion queue. The even passes
5645 * will write 1. The odd passes will write 0.
5647 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
5650 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
5652 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
5653 /* 8-lsb timestamp from POR (100-msec resolution) */
5654 uint8_t timestamp_lo;
5655 /* 16-lsb timestamp from POR (100-msec resolution) */
5656 uint16_t timestamp_hi;
5657 /* Event specific data */
5658 uint32_t event_data1;
5660 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
5662 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
5666 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
5667 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
5670 * This field indicates the exact type of the completion.
5671 * By convention, the LSB identifies the length of the
5672 * record in 16B units. Even values indicate 16B
5673 * records. Odd values indicate 32B
5676 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
5678 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
5680 /* HWRM Asynchronous Event Information */
5681 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5683 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
5684 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
5685 /* Identifiers of events. */
5687 /* PF-VF communication channel status change. */
5688 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
5690 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
5691 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
5692 /* Event specific data */
5693 uint32_t event_data2;
5696 * This value is written by the NIC such that it will be different
5697 * for each pass through the completion queue. The even passes
5698 * will write 1. The odd passes will write 0.
5700 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
5703 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
5705 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
5706 /* 8-lsb timestamp from POR (100-msec resolution) */
5707 uint8_t timestamp_lo;
5708 /* 16-lsb timestamp from POR (100-msec resolution) */
5709 uint16_t timestamp_hi;
5710 /* Event specific data */
5711 uint32_t event_data1;
5713 * If this bit is set to 1, then it indicates that the PF-VF
5714 * communication was lost and it is established.
5715 * If this bit set to 0, then it indicates that the PF-VF
5716 * communication was established and it is lost.
5718 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
5722 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
5723 struct hwrm_async_event_cmpl_vf_cfg_change {
5726 * This field indicates the exact type of the completion.
5727 * By convention, the LSB identifies the length of the
5728 * record in 16B units. Even values indicate 16B
5729 * records. Odd values indicate 32B
5732 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
5734 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
5735 /* HWRM Asynchronous Event Information */
5736 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5738 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
5739 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
5740 /* Identifiers of events. */
5742 /* VF Configuration Change */
5743 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
5745 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
5746 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
5747 /* Event specific data */
5748 uint32_t event_data2;
5751 * This value is written by the NIC such that it will be different
5752 * for each pass through the completion queue. The even passes
5753 * will write 1. The odd passes will write 0.
5755 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
5757 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
5758 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
5759 /* 8-lsb timestamp from POR (100-msec resolution) */
5760 uint8_t timestamp_lo;
5761 /* 16-lsb timestamp from POR (100-msec resolution) */
5762 uint16_t timestamp_hi;
5764 * Each flag provided in this field indicates a specific VF
5765 * configuration change. At least one of these flags shall be set to 1
5766 * when an asynchronous event completion of this type is provided
5769 uint32_t event_data1;
5771 * If this bit is set to 1, then the value of MTU
5772 * was changed on this VF.
5773 * If set to 0, then this bit should be ignored.
5775 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
5778 * If this bit is set to 1, then the value of MRU
5779 * was changed on this VF.
5780 * If set to 0, then this bit should be ignored.
5782 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
5785 * If this bit is set to 1, then the value of default MAC
5786 * address was changed on this VF.
5787 * If set to 0, then this bit should be ignored.
5789 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
5792 * If this bit is set to 1, then the value of default VLAN
5793 * was changed on this VF.
5794 * If set to 0, then this bit should be ignored.
5796 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
5799 * If this bit is set to 1, then the value of trusted VF enable
5800 * was changed on this VF.
5801 * If set to 0, then this bit should be ignored.
5803 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
5807 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
5808 struct hwrm_async_event_cmpl_llfc_pfc_change {
5811 * This field indicates the exact type of the completion.
5812 * By convention, the LSB identifies the length of the
5813 * record in 16B units. Even values indicate 16B
5814 * records. Odd values indicate 32B
5817 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
5819 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
5820 /* HWRM Asynchronous Event Information */
5821 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5823 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
5824 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5825 /* unused1 is 10 b */
5826 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
5828 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
5829 /* Identifiers of events. */
5831 /* LLFC/PFC Configuration Change */
5832 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
5834 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
5835 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
5836 /* Event specific data */
5837 uint32_t event_data2;
5840 * This value is written by the NIC such that it will be different
5841 * for each pass through the completion queue. The even passes
5842 * will write 1. The odd passes will write 0.
5844 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
5846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
5848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
5849 /* 8-lsb timestamp from POR (100-msec resolution) */
5850 uint8_t timestamp_lo;
5851 /* 16-lsb timestamp from POR (100-msec resolution) */
5852 uint16_t timestamp_hi;
5853 /* Event specific data */
5854 uint32_t event_data1;
5855 /* Indicates llfc pfc status change */
5856 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
5858 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
5861 * If this field set to 1, then it indicates that llfc is
5864 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
5867 * If this field is set to 2, then it indicates that pfc
5870 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
5872 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
5873 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
5874 /* Indicates the physical port this llfc pfc change occur */
5875 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
5877 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
5880 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
5882 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
5886 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
5887 struct hwrm_async_event_cmpl_default_vnic_change {
5890 * This field indicates the exact type of the completion.
5891 * By convention, the LSB identifies the length of the
5892 * record in 16B units. Even values indicate 16B
5893 * records. Odd values indicate 32B
5896 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
5898 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
5900 /* HWRM Asynchronous Event Information */
5901 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
5903 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
5904 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
5905 /* unused1 is 10 b */
5906 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
5908 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
5910 /* Identifiers of events. */
5912 /* Notification of a default vnic allocation or free */
5913 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
5915 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
5916 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
5917 /* Event specific data */
5918 uint32_t event_data2;
5921 * This value is written by the NIC such that it will be different
5922 * for each pass through the completion queue. The even passes
5923 * will write 1. The odd passes will write 0.
5925 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
5928 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
5930 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
5931 /* 8-lsb timestamp from POR (100-msec resolution) */
5932 uint8_t timestamp_lo;
5933 /* 16-lsb timestamp from POR (100-msec resolution) */
5934 uint16_t timestamp_hi;
5935 /* Event specific data */
5936 uint32_t event_data1;
5937 /* Indicates default vnic configuration change */
5938 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
5940 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
5943 * If this field is set to 1, then it indicates that
5944 * a default VNIC has been allocate.
5946 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
5949 * If this field is set to 2, then it indicates that
5950 * a default VNIC has been freed.
5952 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
5954 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
5955 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
5956 /* Indicates the physical function this event occurred on. */
5957 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
5959 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
5961 /* Indicates the virtual function this event occurred on */
5962 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
5964 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
5968 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
5969 struct hwrm_async_event_cmpl_hw_flow_aged {
5972 * This field indicates the exact type of the completion.
5973 * By convention, the LSB identifies the length of the
5974 * record in 16B units. Even values indicate 16B
5975 * records. Odd values indicate 32B
5978 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
5980 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
5981 /* HWRM Asynchronous Event Information */
5982 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
5984 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
5985 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
5986 /* Identifiers of events. */
5988 /* Notification of a hw flow aged */
5989 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
5991 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
5992 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
5993 /* Event specific data */
5994 uint32_t event_data2;
5997 * This value is written by the NIC such that it will be different
5998 * for each pass through the completion queue. The even passes
5999 * will write 1. The odd passes will write 0.
6001 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
6003 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
6004 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
6005 /* 8-lsb timestamp from POR (100-msec resolution) */
6006 uint8_t timestamp_lo;
6007 /* 16-lsb timestamp from POR (100-msec resolution) */
6008 uint16_t timestamp_hi;
6009 /* Event specific data */
6010 uint32_t event_data1;
6011 /* Indicates flow ID this event occurred on. */
6012 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
6013 UINT32_C(0x7fffffff)
6014 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
6016 /* Indicates flow direction this event occurred on. */
6017 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
6018 UINT32_C(0x80000000)
6020 * If this bit set to 0, then it indicates that the aged
6021 * event was rx flow.
6023 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
6024 (UINT32_C(0x0) << 31)
6026 * If this bit is set to 1, then it indicates that the aged
6027 * event was tx flow.
6029 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
6030 (UINT32_C(0x1) << 31)
6031 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
6032 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
6035 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
6036 struct hwrm_async_event_cmpl_eem_cache_flush_req {
6039 * This field indicates the exact type of the completion.
6040 * By convention, the LSB identifies the length of the
6041 * record in 16B units. Even values indicate 16B
6042 * records. Odd values indicate 32B
6045 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
6047 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
6049 /* HWRM Asynchronous Event Information */
6050 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
6052 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
6053 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
6054 /* Identifiers of events. */
6056 /* Notification of a eem_cache_flush request */
6057 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6059 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
6060 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
6061 /* Event specific data */
6062 uint32_t event_data2;
6065 * This value is written by the NIC such that it will be different
6066 * for each pass through the completion queue. The even passes
6067 * will write 1. The odd passes will write 0.
6069 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
6072 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
6074 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
6075 /* 8-lsb timestamp from POR (100-msec resolution) */
6076 uint8_t timestamp_lo;
6077 /* 16-lsb timestamp from POR (100-msec resolution) */
6078 uint16_t timestamp_hi;
6079 /* Event specific data */
6080 uint32_t event_data1;
6083 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
6084 struct hwrm_async_event_cmpl_eem_cache_flush_done {
6087 * This field indicates the exact type of the completion.
6088 * By convention, the LSB identifies the length of the
6089 * record in 16B units. Even values indicate 16B
6090 * records. Odd values indicate 32B
6093 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
6095 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
6097 /* HWRM Asynchronous Event Information */
6098 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
6100 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
6101 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
6102 /* Identifiers of events. */
6105 * Notification of a host eem_cache_flush has completed. This event
6106 * is generated by the host driver.
6108 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6110 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
6111 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
6112 /* Event specific data */
6113 uint32_t event_data2;
6116 * This value is written by the NIC such that it will be different
6117 * for each pass through the completion queue. The even passes
6118 * will write 1. The odd passes will write 0.
6120 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
6123 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
6125 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
6126 /* 8-lsb timestamp from POR (100-msec resolution) */
6127 uint8_t timestamp_lo;
6128 /* 16-lsb timestamp from POR (100-msec resolution) */
6129 uint16_t timestamp_hi;
6130 /* Event specific data */
6131 uint32_t event_data1;
6132 /* Indicates function ID that this event occurred on. */
6133 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
6135 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
6139 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
6140 struct hwrm_async_event_cmpl_tcp_flag_action_change {
6143 * This field indicates the exact type of the completion.
6144 * By convention, the LSB identifies the length of the
6145 * record in 16B units. Even values indicate 16B
6146 * records. Odd values indicate 32B
6149 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
6151 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
6153 /* HWRM Asynchronous Event Information */
6154 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6156 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
6157 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
6158 /* Identifiers of events. */
6160 /* Notification of tcp flag action change */
6161 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6163 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
6164 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
6165 /* Event specific data */
6166 uint32_t event_data2;
6169 * This value is written by the NIC such that it will be different
6170 * for each pass through the completion queue. The even passes
6171 * will write 1. The odd passes will write 0.
6173 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
6176 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
6178 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
6179 /* 8-lsb timestamp from POR (100-msec resolution) */
6180 uint8_t timestamp_lo;
6181 /* 16-lsb timestamp from POR (100-msec resolution) */
6182 uint16_t timestamp_hi;
6183 /* Event specific data */
6184 uint32_t event_data1;
6187 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
6188 struct hwrm_async_event_cmpl_eem_flow_active {
6191 * This field indicates the exact type of the completion.
6192 * By convention, the LSB identifies the length of the
6193 * record in 16B units. Even values indicate 16B
6194 * records. Odd values indicate 32B
6197 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
6199 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
6200 /* HWRM Asynchronous Event Information */
6201 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
6203 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
6204 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
6205 /* Identifiers of events. */
6207 /* Notification of an active eem flow */
6208 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
6210 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
6211 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
6212 /* Event specific data */
6213 uint32_t event_data2;
6214 /* Indicates the 2nd global id this event occurred on. */
6215 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
6216 UINT32_C(0x3fffffff)
6217 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
6220 * Indicates flow direction of the flow identified by
6223 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
6224 UINT32_C(0x40000000)
6225 /* If this bit is set to 0, then it indicates that this rx flow. */
6226 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
6227 (UINT32_C(0x0) << 30)
6228 /* If this bit is set to 1, then it indicates that this tx flow. */
6229 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
6230 (UINT32_C(0x1) << 30)
6231 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
6232 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
6235 * This value is written by the NIC such that it will be different
6236 * for each pass through the completion queue. The even passes
6237 * will write 1. The odd passes will write 0.
6239 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
6241 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
6243 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
6244 /* 8-lsb timestamp from POR (100-msec resolution) */
6245 uint8_t timestamp_lo;
6246 /* 16-lsb timestamp from POR (100-msec resolution) */
6247 uint16_t timestamp_hi;
6248 /* Event specific data */
6249 uint32_t event_data1;
6250 /* Indicates the 1st global id this event occurred on. */
6251 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
6252 UINT32_C(0x3fffffff)
6253 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
6256 * Indicates flow direction of the flow identified by the
6259 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
6260 UINT32_C(0x40000000)
6261 /* If this bit is set to 0, then it indicates that this is rx flow. */
6262 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
6263 (UINT32_C(0x0) << 30)
6264 /* If this bit is set to 1, then it indicates that this is tx flow. */
6265 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
6266 (UINT32_C(0x1) << 30)
6267 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
6268 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
6270 * Indicates EEM flow aging mode this event occurred on. If
6271 * this bit is set to 0, the event_data1 is the EEM global
6272 * ID. If this bit is set to 1, the event_data1 is the number
6273 * of global ID in the context memory.
6275 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
6276 UINT32_C(0x80000000)
6277 /* EEM flow aging mode 0. */
6278 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
6279 (UINT32_C(0x0) << 31)
6280 /* EEM flow aging mode 1. */
6281 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
6282 (UINT32_C(0x1) << 31)
6283 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
6284 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
6287 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
6288 struct hwrm_async_event_cmpl_eem_cfg_change {
6291 * This field indicates the exact type of the completion.
6292 * By convention, the LSB identifies the length of the
6293 * record in 16B units. Even values indicate 16B
6294 * records. Odd values indicate 32B
6297 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
6299 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
6300 /* HWRM Asynchronous Event Information */
6301 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6303 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
6304 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6305 /* Identifiers of events. */
6307 /* Notification of EEM configuration change */
6308 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
6310 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
6311 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
6312 /* Event specific data */
6313 uint32_t event_data2;
6316 * This value is written by the NIC such that it will be different
6317 * for each pass through the completion queue. The even passes
6318 * will write 1. The odd passes will write 0.
6320 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
6322 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
6323 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
6324 /* 8-lsb timestamp from POR (100-msec resolution) */
6325 uint8_t timestamp_lo;
6326 /* 16-lsb timestamp from POR (100-msec resolution) */
6327 uint16_t timestamp_hi;
6328 /* Event specific data */
6329 uint32_t event_data1;
6331 * Value of 1 to indicate EEM TX configuration is enabled. Value of
6332 * 0 to indicate the EEM TX configuration is disabled.
6334 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
6337 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
6338 * to indicate the EEM RX configuration is disabled.
6340 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
6344 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
6345 struct hwrm_async_event_cmpl_quiesce_done {
6348 * This field indicates the exact type of the completion.
6349 * By convention, the LSB identifies the length of the
6350 * record in 16B units. Even values indicate 16B
6351 * records. Odd values indicate 32B
6354 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
6356 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
6357 /* HWRM Asynchronous Event Information */
6358 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
6360 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
6361 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
6362 /* Identifiers of events. */
6364 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
6365 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
6367 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
6368 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
6369 /* Event specific data */
6370 uint32_t event_data2;
6371 /* Status of HWRM_FW_STATE_QUIESCE completion */
6372 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
6374 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
6377 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
6378 * completed successfully.
6380 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
6383 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
6386 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
6389 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
6390 * encountered an error.
6392 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
6394 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
6395 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
6398 * This value is written by the NIC such that it will be different
6399 * for each pass through the completion queue. The even passes
6400 * will write 1. The odd passes will write 0.
6402 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
6404 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
6405 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
6406 /* 8-lsb timestamp from POR (100-msec resolution) */
6407 uint8_t timestamp_lo;
6408 /* 16-lsb timestamp from POR (100-msec resolution) */
6409 uint16_t timestamp_hi;
6410 /* Event specific data */
6411 uint32_t event_data1;
6412 /* Time stamp for error event */
6413 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
6417 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
6418 struct hwrm_async_event_cmpl_fw_trace_msg {
6421 * This field indicates the exact type of the completion.
6422 * By convention, the LSB identifies the length of the
6423 * record in 16B units. Even values indicate 16B
6424 * records. Odd values indicate 32B
6427 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
6429 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
6430 /* HWRM Asynchronous Event Information */
6431 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
6433 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
6434 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
6435 /* Identifiers of events. */
6437 /* Firmware trace log message */
6438 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
6440 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
6441 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
6442 /* Trace byte 0 to 3 */
6443 uint32_t event_data2;
6445 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
6447 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
6449 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
6451 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
6453 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
6455 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
6457 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
6458 UINT32_C(0xff000000)
6459 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
6462 * This value is written by the NIC such that it will be different
6463 * for each pass through the completion queue. The even passes
6464 * will write 1. The odd passes will write 0.
6466 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
6468 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
6469 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
6471 uint8_t timestamp_lo;
6472 /* Indicates if the string is partial or complete. */
6473 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
6475 /* Complete string */
6476 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
6478 /* Partial string */
6479 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
6481 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
6482 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
6483 /* Indicates the firmware that sent the trace message. */
6484 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
6486 /* Primary firmware */
6487 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
6488 (UINT32_C(0x0) << 1)
6489 /* Secondary firmware */
6490 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
6491 (UINT32_C(0x1) << 1)
6492 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
6493 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
6494 /* Trace byte 4 to 5 */
6495 uint16_t timestamp_hi;
6497 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
6499 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
6501 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
6503 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
6504 /* Trace byte 6 to 9 */
6505 uint32_t event_data1;
6507 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
6509 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
6511 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
6513 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
6515 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
6517 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
6519 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
6520 UINT32_C(0xff000000)
6521 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
6524 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
6525 struct hwrm_async_event_cmpl_hwrm_error {
6528 * This field indicates the exact type of the completion.
6529 * By convention, the LSB identifies the length of the
6530 * record in 16B units. Even values indicate 16B
6531 * records. Odd values indicate 32B
6534 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
6536 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
6537 /* HWRM Asynchronous Event Information */
6538 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
6540 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
6541 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
6542 /* Identifiers of events. */
6545 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
6547 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
6548 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
6549 /* Event specific data */
6550 uint32_t event_data2;
6551 /* Severity of HWRM Error */
6552 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
6554 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
6556 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
6558 /* Non-fatal Error */
6559 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
6562 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
6564 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
6565 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
6568 * This value is written by the NIC such that it will be different
6569 * for each pass through the completion queue. The even passes
6570 * will write 1. The odd passes will write 0.
6572 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
6574 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
6575 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
6576 /* 8-lsb timestamp from POR (100-msec resolution) */
6577 uint8_t timestamp_lo;
6578 /* 16-lsb timestamp from POR (100-msec resolution) */
6579 uint16_t timestamp_hi;
6580 /* Event specific data */
6581 uint32_t event_data1;
6582 /* Time stamp for error event */
6583 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
6587 /*******************
6589 *******************/
6592 /* hwrm_func_reset_input (size:192b/24B) */
6593 struct hwrm_func_reset_input {
6594 /* The HWRM command request type. */
6597 * The completion ring to send the completion event on. This should
6598 * be the NQ ID returned from the `nq_alloc` HWRM command.
6602 * The sequence ID is used by the driver for tracking multiple
6603 * commands. This ID is treated as opaque data by the firmware and
6604 * the value is returned in the `hwrm_resp_hdr` upon completion.
6608 * The target ID of the command:
6609 * * 0x0-0xFFF8 - The function ID
6610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6611 * * 0xFFFD - Reserved for user-space HWRM interface
6616 * A physical address pointer pointing to a host buffer that the
6617 * command's response data will be written. This can be either a host
6618 * physical address (HPA) or a guest physical address (GPA) and must
6619 * point to a physically contiguous block of memory.
6624 * This bit must be '1' for the vf_id_valid field to be
6627 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
6629 * The ID of the VF that this PF is trying to reset.
6630 * Only the parent PF shall be allowed to reset a child VF.
6632 * A parent PF driver shall use this field only when a specific child VF
6633 * is requested to be reset.
6636 /* This value indicates the level of a function reset. */
6637 uint8_t func_reset_level;
6639 * Reset the caller function and its children VFs (if any). If no
6640 * children functions exist, then reset the caller function only.
6642 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
6644 /* Reset the caller function only */
6645 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
6648 * Reset all children VFs of the caller function driver if the
6649 * caller is a PF driver.
6650 * It is an error to specify this level by a VF driver.
6651 * It is an error to specify this level by a PF driver with
6654 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
6657 * Reset a specific VF of the caller function driver if the caller
6658 * is the parent PF driver.
6659 * It is an error to specify this level by a VF driver.
6660 * It is an error to specify this level by a PF driver that is not
6661 * the parent of the VF that is being requested to reset.
6663 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
6665 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
6666 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
6670 /* hwrm_func_reset_output (size:128b/16B) */
6671 struct hwrm_func_reset_output {
6672 /* The specific error status for the command. */
6673 uint16_t error_code;
6674 /* The HWRM command request type. */
6676 /* The sequence ID from the original command. */
6678 /* The length of the response data in number of bytes. */
6680 uint8_t unused_0[7];
6682 * This field is used in Output records to indicate that the output
6683 * is completely written to RAM. This field should be read as '1'
6684 * to indicate that the output has been completely written.
6685 * When writing a command completion or response to an internal processor,
6686 * the order of writes has to be such that this field is written last.
6691 /********************
6692 * hwrm_func_getfid *
6693 ********************/
6696 /* hwrm_func_getfid_input (size:192b/24B) */
6697 struct hwrm_func_getfid_input {
6698 /* The HWRM command request type. */
6701 * The completion ring to send the completion event on. This should
6702 * be the NQ ID returned from the `nq_alloc` HWRM command.
6706 * The sequence ID is used by the driver for tracking multiple
6707 * commands. This ID is treated as opaque data by the firmware and
6708 * the value is returned in the `hwrm_resp_hdr` upon completion.
6712 * The target ID of the command:
6713 * * 0x0-0xFFF8 - The function ID
6714 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6715 * * 0xFFFD - Reserved for user-space HWRM interface
6720 * A physical address pointer pointing to a host buffer that the
6721 * command's response data will be written. This can be either a host
6722 * physical address (HPA) or a guest physical address (GPA) and must
6723 * point to a physically contiguous block of memory.
6728 * This bit must be '1' for the pci_id field to be
6731 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
6733 * This value is the PCI ID of the queried function.
6734 * If ARI is enabled, then it is
6735 * Bus Number (8b):Function Number(8b). Otherwise, it is
6736 * Bus Number (8b):Device Number (5b):Function Number(3b).
6739 uint8_t unused_0[2];
6742 /* hwrm_func_getfid_output (size:128b/16B) */
6743 struct hwrm_func_getfid_output {
6744 /* The specific error status for the command. */
6745 uint16_t error_code;
6746 /* The HWRM command request type. */
6748 /* The sequence ID from the original command. */
6750 /* The length of the response data in number of bytes. */
6753 * FID value. This value is used to identify operations on the PCI
6754 * bus as belonging to a particular PCI function.
6757 uint8_t unused_0[5];
6759 * This field is used in Output records to indicate that the output
6760 * is completely written to RAM. This field should be read as '1'
6761 * to indicate that the output has been completely written.
6762 * When writing a command completion or response to an internal processor,
6763 * the order of writes has to be such that this field is written last.
6768 /**********************
6769 * hwrm_func_vf_alloc *
6770 **********************/
6773 /* hwrm_func_vf_alloc_input (size:192b/24B) */
6774 struct hwrm_func_vf_alloc_input {
6775 /* The HWRM command request type. */
6778 * The completion ring to send the completion event on. This should
6779 * be the NQ ID returned from the `nq_alloc` HWRM command.
6783 * The sequence ID is used by the driver for tracking multiple
6784 * commands. This ID is treated as opaque data by the firmware and
6785 * the value is returned in the `hwrm_resp_hdr` upon completion.
6789 * The target ID of the command:
6790 * * 0x0-0xFFF8 - The function ID
6791 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6792 * * 0xFFFD - Reserved for user-space HWRM interface
6797 * A physical address pointer pointing to a host buffer that the
6798 * command's response data will be written. This can be either a host
6799 * physical address (HPA) or a guest physical address (GPA) and must
6800 * point to a physically contiguous block of memory.
6805 * This bit must be '1' for the first_vf_id field to be
6808 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6810 * This value is used to identify a Virtual Function (VF).
6811 * The scope of VF ID is local within a PF.
6813 uint16_t first_vf_id;
6814 /* The number of virtual functions requested. */
6818 /* hwrm_func_vf_alloc_output (size:128b/16B) */
6819 struct hwrm_func_vf_alloc_output {
6820 /* The specific error status for the command. */
6821 uint16_t error_code;
6822 /* The HWRM command request type. */
6824 /* The sequence ID from the original command. */
6826 /* The length of the response data in number of bytes. */
6828 /* The ID of the first VF allocated. */
6829 uint16_t first_vf_id;
6830 uint8_t unused_0[5];
6832 * This field is used in Output records to indicate that the output
6833 * is completely written to RAM. This field should be read as '1'
6834 * to indicate that the output has been completely written.
6835 * When writing a command completion or response to an internal processor,
6836 * the order of writes has to be such that this field is written last.
6841 /*********************
6842 * hwrm_func_vf_free *
6843 *********************/
6846 /* hwrm_func_vf_free_input (size:192b/24B) */
6847 struct hwrm_func_vf_free_input {
6848 /* The HWRM command request type. */
6851 * The completion ring to send the completion event on. This should
6852 * be the NQ ID returned from the `nq_alloc` HWRM command.
6856 * The sequence ID is used by the driver for tracking multiple
6857 * commands. This ID is treated as opaque data by the firmware and
6858 * the value is returned in the `hwrm_resp_hdr` upon completion.
6862 * The target ID of the command:
6863 * * 0x0-0xFFF8 - The function ID
6864 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6865 * * 0xFFFD - Reserved for user-space HWRM interface
6870 * A physical address pointer pointing to a host buffer that the
6871 * command's response data will be written. This can be either a host
6872 * physical address (HPA) or a guest physical address (GPA) and must
6873 * point to a physically contiguous block of memory.
6878 * This bit must be '1' for the first_vf_id field to be
6881 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6883 * This value is used to identify a Virtual Function (VF).
6884 * The scope of VF ID is local within a PF.
6886 uint16_t first_vf_id;
6888 * The number of virtual functions requested.
6889 * 0xFFFF - Cleanup all children of this PF.
6894 /* hwrm_func_vf_free_output (size:128b/16B) */
6895 struct hwrm_func_vf_free_output {
6896 /* The specific error status for the command. */
6897 uint16_t error_code;
6898 /* The HWRM command request type. */
6900 /* The sequence ID from the original command. */
6902 /* The length of the response data in number of bytes. */
6904 uint8_t unused_0[7];
6906 * This field is used in Output records to indicate that the output
6907 * is completely written to RAM. This field should be read as '1'
6908 * to indicate that the output has been completely written.
6909 * When writing a command completion or response to an internal processor,
6910 * the order of writes has to be such that this field is written last.
6915 /********************
6916 * hwrm_func_vf_cfg *
6917 ********************/
6920 /* hwrm_func_vf_cfg_input (size:448b/56B) */
6921 struct hwrm_func_vf_cfg_input {
6922 /* The HWRM command request type. */
6925 * The completion ring to send the completion event on. This should
6926 * be the NQ ID returned from the `nq_alloc` HWRM command.
6930 * The sequence ID is used by the driver for tracking multiple
6931 * commands. This ID is treated as opaque data by the firmware and
6932 * the value is returned in the `hwrm_resp_hdr` upon completion.
6936 * The target ID of the command:
6937 * * 0x0-0xFFF8 - The function ID
6938 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
6939 * * 0xFFFD - Reserved for user-space HWRM interface
6944 * A physical address pointer pointing to a host buffer that the
6945 * command's response data will be written. This can be either a host
6946 * physical address (HPA) or a guest physical address (GPA) and must
6947 * point to a physically contiguous block of memory.
6952 * This bit must be '1' for the mtu field to be
6955 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
6958 * This bit must be '1' for the guest_vlan field to be
6961 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
6964 * This bit must be '1' for the async_event_cr field to be
6967 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6970 * This bit must be '1' for the dflt_mac_addr field to be
6973 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6976 * This bit must be '1' for the num_rsscos_ctxs field to be
6979 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6982 * This bit must be '1' for the num_cmpl_rings field to be
6985 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6988 * This bit must be '1' for the num_tx_rings field to be
6991 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6994 * This bit must be '1' for the num_rx_rings field to be
6997 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
7000 * This bit must be '1' for the num_l2_ctxs field to be
7003 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
7006 * This bit must be '1' for the num_vnics field to be
7009 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
7012 * This bit must be '1' for the num_stat_ctxs field to be
7015 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
7018 * This bit must be '1' for the num_hw_ring_grps field to be
7021 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
7024 * The maximum transmission unit requested on the function.
7025 * The HWRM should make sure that the mtu of
7026 * the function does not exceed the mtu of the physical
7027 * port that this function is associated with.
7029 * In addition to requesting mtu per function, it is
7030 * possible to configure mtu per transmit ring.
7031 * By default, the mtu of each transmit ring associated
7032 * with a function is equal to the mtu of the function.
7033 * The HWRM should make sure that the mtu of each transmit
7034 * ring that is assigned to a function has a valid mtu.
7038 * The guest VLAN for the function being configured.
7039 * This field's format is same as 802.1Q Tag's
7040 * Tag Control Information (TCI) format that includes both
7041 * Priority Code Point (PCP) and VLAN Identifier (VID).
7043 uint16_t guest_vlan;
7045 * ID of the target completion ring for receiving asynchronous
7046 * event completions. If this field is not valid, then the
7047 * HWRM shall use the default completion ring of the function
7048 * that is being configured as the target completion ring for
7049 * providing any asynchronous event completions for that
7051 * If this field is valid, then the HWRM shall use the
7052 * completion ring identified by this ID as the target
7053 * completion ring for providing any asynchronous event
7054 * completions for the function that is being configured.
7056 uint16_t async_event_cr;
7058 * This value is the current MAC address requested by the VF
7059 * driver to be configured on this VF. A value of
7060 * 00-00-00-00-00-00 indicates no MAC address configuration
7061 * is requested by the VF driver.
7062 * The parent PF driver may reject or overwrite this
7065 uint8_t dflt_mac_addr[6];
7068 * This bit requests that the firmware test to see if all the assets
7069 * requested in this command (i.e. number of TX rings) are available.
7070 * The firmware will return an error if the requested assets are
7071 * not available. The firwmare will NOT reserve the assets if they
7074 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
7077 * This bit requests that the firmware test to see if all the assets
7078 * requested in this command (i.e. number of RX rings) are available.
7079 * The firmware will return an error if the requested assets are
7080 * not available. The firwmare will NOT reserve the assets if they
7083 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
7086 * This bit requests that the firmware test to see if all the assets
7087 * requested in this command (i.e. number of CMPL rings) are available.
7088 * The firmware will return an error if the requested assets are
7089 * not available. The firwmare will NOT reserve the assets if they
7092 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
7095 * This bit requests that the firmware test to see if all the assets
7096 * requested in this command (i.e. number of RSS ctx) are available.
7097 * The firmware will return an error if the requested assets are
7098 * not available. The firwmare will NOT reserve the assets if they
7101 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
7104 * This bit requests that the firmware test to see if all the assets
7105 * requested in this command (i.e. number of ring groups) are available.
7106 * The firmware will return an error if the requested assets are
7107 * not available. The firwmare will NOT reserve the assets if they
7110 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
7113 * This bit requests that the firmware test to see if all the assets
7114 * requested in this command (i.e. number of stat ctx) are available.
7115 * The firmware will return an error if the requested assets are
7116 * not available. The firwmare will NOT reserve the assets if they
7119 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
7122 * This bit requests that the firmware test to see if all the assets
7123 * requested in this command (i.e. number of VNICs) are available.
7124 * The firmware will return an error if the requested assets are
7125 * not available. The firwmare will NOT reserve the assets if they
7128 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
7131 * This bit requests that the firmware test to see if all the assets
7132 * requested in this command (i.e. number of L2 ctx) are available.
7133 * The firmware will return an error if the requested assets are
7134 * not available. The firwmare will NOT reserve the assets if they
7137 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
7139 /* The number of RSS/COS contexts requested for the VF. */
7140 uint16_t num_rsscos_ctxs;
7141 /* The number of completion rings requested for the VF. */
7142 uint16_t num_cmpl_rings;
7143 /* The number of transmit rings requested for the VF. */
7144 uint16_t num_tx_rings;
7145 /* The number of receive rings requested for the VF. */
7146 uint16_t num_rx_rings;
7147 /* The number of L2 contexts requested for the VF. */
7148 uint16_t num_l2_ctxs;
7149 /* The number of vnics requested for the VF. */
7151 /* The number of statistic contexts requested for the VF. */
7152 uint16_t num_stat_ctxs;
7153 /* The number of HW ring groups requested for the VF. */
7154 uint16_t num_hw_ring_grps;
7155 uint8_t unused_0[4];
7158 /* hwrm_func_vf_cfg_output (size:128b/16B) */
7159 struct hwrm_func_vf_cfg_output {
7160 /* The specific error status for the command. */
7161 uint16_t error_code;
7162 /* The HWRM command request type. */
7164 /* The sequence ID from the original command. */
7166 /* The length of the response data in number of bytes. */
7168 uint8_t unused_0[7];
7170 * This field is used in Output records to indicate that the output
7171 * is completely written to RAM. This field should be read as '1'
7172 * to indicate that the output has been completely written.
7173 * When writing a command completion or response to an internal processor,
7174 * the order of writes has to be such that this field is written last.
7179 /*******************
7181 *******************/
7184 /* hwrm_func_qcaps_input (size:192b/24B) */
7185 struct hwrm_func_qcaps_input {
7186 /* The HWRM command request type. */
7189 * The completion ring to send the completion event on. This should
7190 * be the NQ ID returned from the `nq_alloc` HWRM command.
7194 * The sequence ID is used by the driver for tracking multiple
7195 * commands. This ID is treated as opaque data by the firmware and
7196 * the value is returned in the `hwrm_resp_hdr` upon completion.
7200 * The target ID of the command:
7201 * * 0x0-0xFFF8 - The function ID
7202 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7203 * * 0xFFFD - Reserved for user-space HWRM interface
7208 * A physical address pointer pointing to a host buffer that the
7209 * command's response data will be written. This can be either a host
7210 * physical address (HPA) or a guest physical address (GPA) and must
7211 * point to a physically contiguous block of memory.
7215 * Function ID of the function that is being queried.
7216 * 0xFF... (All Fs) if the query is for the requesting
7220 uint8_t unused_0[6];
7223 /* hwrm_func_qcaps_output (size:640b/80B) */
7224 struct hwrm_func_qcaps_output {
7225 /* The specific error status for the command. */
7226 uint16_t error_code;
7227 /* The HWRM command request type. */
7229 /* The sequence ID from the original command. */
7231 /* The length of the response data in number of bytes. */
7234 * FID value. This value is used to identify operations on the PCI
7235 * bus as belonging to a particular PCI function.
7239 * Port ID of port that this function is associated with.
7240 * Valid only for the PF.
7241 * 0xFF... (All Fs) if this function is not associated with
7243 * 0xFF... (All Fs) if this function is called from a VF.
7247 /* If 1, then Push mode is supported on this function. */
7248 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
7251 * If 1, then the global MSI-X auto-masking is enabled for the
7254 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
7257 * If 1, then the Precision Time Protocol (PTP) processing
7258 * is supported on this function.
7259 * The HWRM should enable PTP on only a single Physical
7260 * Function (PF) per port.
7262 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
7265 * If 1, then RDMA over Converged Ethernet (RoCE) v1
7266 * is supported on this function.
7268 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
7271 * If 1, then RDMA over Converged Ethernet (RoCE) v2
7272 * is supported on this function.
7274 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
7277 * If 1, then control and configuration of WoL magic packet
7278 * are supported on this function.
7280 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
7283 * If 1, then control and configuration of bitmap pattern
7284 * packet are supported on this function.
7286 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
7289 * If set to 1, then the control and configuration of rate limit
7290 * of an allocated TX ring on the queried function is supported.
7292 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
7295 * If 1, then control and configuration of minimum and
7296 * maximum bandwidths are supported on the queried function.
7298 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
7301 * If the query is for a VF, then this flag shall be ignored.
7302 * If this query is for a PF and this flag is set to 1,
7303 * then the PF has the capability to set the rate limits
7304 * on the TX rings of its children VFs.
7305 * If this query is for a PF and this flag is set to 0, then
7306 * the PF does not have the capability to set the rate limits
7307 * on the TX rings of its children VFs.
7309 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
7312 * If the query is for a VF, then this flag shall be ignored.
7313 * If this query is for a PF and this flag is set to 1,
7314 * then the PF has the capability to set the minimum and/or
7315 * maximum bandwidths for its children VFs.
7316 * If this query is for a PF and this flag is set to 0, then
7317 * the PF does not have the capability to set the minimum or
7318 * maximum bandwidths for its children VFs.
7320 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
7323 * Standard TX Ring mode is used for the allocation of TX ring
7324 * and underlying scheduling resources that allow bandwidth
7325 * reservation and limit settings on the queried function.
7326 * If set to 1, then standard TX ring mode is supported
7327 * on the queried function.
7328 * If set to 0, then standard TX ring mode is not available
7329 * on the queried function.
7331 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
7334 * If the query is for a VF, then this flag shall be ignored,
7335 * If this query is for a PF and this flag is set to 1,
7336 * then the PF has the capability to detect GENEVE tunnel
7339 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
7342 * If the query is for a VF, then this flag shall be ignored,
7343 * If this query is for a PF and this flag is set to 1,
7344 * then the PF has the capability to detect NVGRE tunnel
7347 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
7350 * If the query is for a VF, then this flag shall be ignored,
7351 * If this query is for a PF and this flag is set to 1,
7352 * then the PF has the capability to detect GRE tunnel
7355 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
7358 * If the query is for a VF, then this flag shall be ignored,
7359 * If this query is for a PF and this flag is set to 1,
7360 * then the PF has the capability to detect MPLS tunnel
7363 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
7366 * If the query is for a VF, then this flag shall be ignored,
7367 * If this query is for a PF and this flag is set to 1,
7368 * then the PF has the capability to support pcie stats.
7370 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
7373 * If the query is for a VF, then this flag shall be ignored,
7374 * If this query is for a PF and this flag is set to 1,
7375 * then the PF has the capability to adopt the VF's belonging
7378 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
7381 * If the query is for a VF, then this flag shall be ignored,
7382 * If this query is for a PF and this flag is set to 1,
7383 * then the PF has the administrative privilege to configure another PF
7385 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
7388 * If the query is for a VF, then this flag shall be ignored.
7389 * If this query is for a PF and this flag is set to 1, then
7390 * the PF will know that the firmware has the capability to track
7391 * the virtual link status.
7393 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
7396 * If 1, then this function supports the push mode that uses
7397 * write combine buffers and the long inline tx buffer descriptor.
7399 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
7402 * If 1, then FW has capability to allocate TX rings dynamically
7403 * in ring alloc even if PF reserved pool is zero.
7404 * This bit will be used only for PFs.
7406 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
7409 * When this bit is '1', it indicates that core firmware is
7410 * capable of Hot Reset.
7412 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
7415 * This flag will be set to 1 by the FW if FW supports adapter error
7418 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
7421 * If the query is for a VF, then this flag shall be ignored.
7422 * If this query is for a PF and this flag is set to 1, then
7423 * the PF has the capability to support extended stats.
7425 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
7428 * If the query is for a VF, then this flag shall be ignored.
7429 * If this query is for a PF and this flag is set to 1, then host
7430 * must initiate reset or reload (or fastboot) the firmware image
7431 * upon detection of device shutdown state.
7433 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
7436 * If the query is for a VF, then this flag (always set to 0) shall
7437 * be ignored. If this query is for a PF and this flag is set to 1,
7438 * host, when registered for the default vnic change async event,
7439 * receives async notification whenever a default vnic state is
7440 * changed for any of child or adopted VFs.
7442 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
7445 * This value is current MAC address configured for this
7446 * function. A value of 00-00-00-00-00-00 indicates no
7447 * MAC address is currently configured.
7449 uint8_t mac_address[6];
7451 * The maximum number of RSS/COS contexts that can be
7452 * allocated to the function.
7454 uint16_t max_rsscos_ctx;
7456 * The maximum number of completion rings that can be
7457 * allocated to the function.
7459 uint16_t max_cmpl_rings;
7461 * The maximum number of transmit rings that can be
7462 * allocated to the function.
7464 uint16_t max_tx_rings;
7466 * The maximum number of receive rings that can be
7467 * allocated to the function.
7469 uint16_t max_rx_rings;
7471 * The maximum number of L2 contexts that can be
7472 * allocated to the function.
7474 uint16_t max_l2_ctxs;
7476 * The maximum number of VNICs that can be
7477 * allocated to the function.
7481 * The identifier for the first VF enabled on a PF. This
7482 * is valid only on the PF with SR-IOV enabled.
7483 * 0xFF... (All Fs) if this command is called on a PF with
7484 * SR-IOV disabled or on a VF.
7486 uint16_t first_vf_id;
7488 * The maximum number of VFs that can be
7489 * allocated to the function. This is valid only on the
7490 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
7491 * command is called on a PF with SR-IOV disabled or
7496 * The maximum number of statistic contexts that can be
7497 * allocated to the function.
7499 uint16_t max_stat_ctx;
7501 * The maximum number of Encapsulation records that can be
7502 * offloaded by this function.
7504 uint32_t max_encap_records;
7506 * The maximum number of decapsulation records that can
7507 * be offloaded by this function.
7509 uint32_t max_decap_records;
7511 * The maximum number of Exact Match (EM) flows that can be
7512 * offloaded by this function on the TX side.
7514 uint32_t max_tx_em_flows;
7516 * The maximum number of Wildcard Match (WM) flows that can
7517 * be offloaded by this function on the TX side.
7519 uint32_t max_tx_wm_flows;
7521 * The maximum number of Exact Match (EM) flows that can be
7522 * offloaded by this function on the RX side.
7524 uint32_t max_rx_em_flows;
7526 * The maximum number of Wildcard Match (WM) flows that can
7527 * be offloaded by this function on the RX side.
7529 uint32_t max_rx_wm_flows;
7531 * The maximum number of multicast filters that can
7532 * be supported by this function on the RX side.
7534 uint32_t max_mcast_filters;
7536 * The maximum value of flow_id that can be supported
7537 * in completion records.
7539 uint32_t max_flow_id;
7541 * The maximum number of HW ring groups that can be
7542 * supported on this function.
7544 uint32_t max_hw_ring_grps;
7546 * The maximum number of strict priority transmit rings
7547 * that can be allocated to the function.
7548 * This number indicates the maximum number of TX rings
7549 * that can be assigned strict priorities out of the
7550 * maximum number of TX rings that can be allocated
7551 * (max_tx_rings) to the function.
7553 uint16_t max_sp_tx_rings;
7556 * This field is used in Output records to indicate that the output
7557 * is completely written to RAM. This field should be read as '1'
7558 * to indicate that the output has been completely written.
7559 * When writing a command completion or response to an internal processor,
7560 * the order of writes has to be such that this field is written last.
7570 /* hwrm_func_qcfg_input (size:192b/24B) */
7571 struct hwrm_func_qcfg_input {
7572 /* The HWRM command request type. */
7575 * The completion ring to send the completion event on. This should
7576 * be the NQ ID returned from the `nq_alloc` HWRM command.
7580 * The sequence ID is used by the driver for tracking multiple
7581 * commands. This ID is treated as opaque data by the firmware and
7582 * the value is returned in the `hwrm_resp_hdr` upon completion.
7586 * The target ID of the command:
7587 * * 0x0-0xFFF8 - The function ID
7588 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
7589 * * 0xFFFD - Reserved for user-space HWRM interface
7594 * A physical address pointer pointing to a host buffer that the
7595 * command's response data will be written. This can be either a host
7596 * physical address (HPA) or a guest physical address (GPA) and must
7597 * point to a physically contiguous block of memory.
7601 * Function ID of the function that is being queried.
7602 * 0xFF... (All Fs) if the query is for the requesting
7606 uint8_t unused_0[6];
7609 /* hwrm_func_qcfg_output (size:704b/88B) */
7610 struct hwrm_func_qcfg_output {
7611 /* The specific error status for the command. */
7612 uint16_t error_code;
7613 /* The HWRM command request type. */
7615 /* The sequence ID from the original command. */
7617 /* The length of the response data in number of bytes. */
7620 * FID value. This value is used to identify operations on the PCI
7621 * bus as belonging to a particular PCI function.
7625 * Port ID of port that this function is associated with.
7626 * 0xFF... (All Fs) if this function is not associated with
7631 * This value is the current VLAN setting for this
7632 * function. The value of 0 for this field indicates
7633 * no priority tagging or VLAN is used.
7634 * This field's format is same as 802.1Q Tag's
7635 * Tag Control Information (TCI) format that includes both
7636 * Priority Code Point (PCP) and VLAN Identifier (VID).
7641 * If 1, then magic packet based Out-Of-Box WoL is enabled on
7642 * the port associated with this function.
7644 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
7647 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
7648 * on the port associated with this function.
7650 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
7653 * If set to 1, then FW based DCBX agent is enabled and running on
7654 * the port associated with this function.
7655 * If set to 0, then DCBX agent is not running in the firmware.
7657 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
7660 * Standard TX Ring mode is used for the allocation of TX ring
7661 * and underlying scheduling resources that allow bandwidth
7662 * reservation and limit settings on the queried function.
7663 * If set to 1, then standard TX ring mode is enabled
7664 * on the queried function.
7665 * If set to 0, then the standard TX ring mode is disabled
7666 * on the queried function. In this extended TX ring resource
7667 * mode, the minimum and maximum bandwidth settings are not
7668 * supported to allow the allocation of TX rings to span multiple
7671 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
7674 * If set to 1 then FW based LLDP agent is enabled and running on
7675 * the port associated with this function.
7676 * If set to 0 then the LLDP agent is not running in the firmware.
7678 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
7681 * If set to 1, then multi-host mode is active for this function.
7682 * If set to 0, then multi-host mode is inactive for this function
7683 * or not applicable for this device.
7685 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
7688 * If the function that is being queried is a PF, then the HWRM shall
7689 * set this field to 0 and the HWRM client shall ignore this field.
7690 * If the function that is being queried is a VF, then the HWRM shall
7691 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
7692 * shall set this field to 0.
7694 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
7697 * If set to 1, then secure mode is enabled for this function or device.
7698 * If set to 0, then secure mode is disabled (or normal mode) for this
7699 * function or device.
7701 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
7704 * If set to 1, then this PF is enabled with a preboot driver that
7705 * requires access to the legacy L2 ring model and legacy 32b
7706 * doorbells. If set to 0, then this PF is not allowed to use
7707 * the legacy L2 rings. This feature is not allowed on VFs and
7708 * is only relevant for devices that require a context backing
7711 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
7714 * This value is current MAC address configured for this
7715 * function. A value of 00-00-00-00-00-00 indicates no
7716 * MAC address is currently configured.
7718 uint8_t mac_address[6];
7720 * This value is current PCI ID of this
7721 * function. If ARI is enabled, then it is
7722 * Bus Number (8b):Function Number(8b). Otherwise, it is
7723 * Bus Number (8b):Device Number (4b):Function Number(4b).
7724 * If multi-host mode is active, the 4 lsb will indicate
7725 * the PF index for this function.
7729 * The number of RSS/COS contexts currently
7730 * allocated to the function.
7732 uint16_t alloc_rsscos_ctx;
7734 * The number of completion rings currently allocated to
7735 * the function. This does not include the rings allocated
7736 * to any children functions if any.
7738 uint16_t alloc_cmpl_rings;
7740 * The number of transmit rings currently allocated to
7741 * the function. This does not include the rings allocated
7742 * to any children functions if any.
7744 uint16_t alloc_tx_rings;
7746 * The number of receive rings currently allocated to
7747 * the function. This does not include the rings allocated
7748 * to any children functions if any.
7750 uint16_t alloc_rx_rings;
7751 /* The allocated number of L2 contexts to the function. */
7752 uint16_t alloc_l2_ctx;
7753 /* The allocated number of vnics to the function. */
7754 uint16_t alloc_vnics;
7756 * The maximum transmission unit of the function.
7757 * If the reported mtu value is non-zero then it will used for the
7758 * rings allocated on this function. otherwise the default
7759 * value is used if ring MTU is not specified.
7763 * The maximum receive unit of the function.
7764 * For vnics allocated on this function, this default
7765 * value is used if vnic MRU is not specified.
7768 /* The statistics context assigned to a function. */
7769 uint16_t stat_ctx_id;
7771 * The HWRM shall return Unknown value for this field
7772 * when this command is used to query VF's configuration.
7774 uint8_t port_partition_type;
7775 /* Single physical function */
7776 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
7777 /* Multiple physical functions */
7778 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
7779 /* Network Partitioning 1.0 */
7780 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
7781 /* Network Partitioning 1.5 */
7782 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
7783 /* Network Partitioning 2.0 */
7784 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
7786 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
7788 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
7789 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
7791 * This field will indicate number of physical functions on this port_partition.
7792 * HWRM shall return unavail (i.e. value of 0) for this field
7793 * when this command is used to query VF's configuration or
7794 * from older firmware that doesn't support this field.
7796 uint8_t port_pf_cnt;
7797 /* number of PFs is not available */
7798 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
7799 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
7800 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
7802 * The default VNIC ID assigned to a function that is
7805 uint16_t dflt_vnic_id;
7806 uint16_t max_mtu_configured;
7808 * Minimum BW allocated for this function.
7809 * The HWRM will translate this value into byte counter and
7810 * time interval used for the scheduler inside the device.
7811 * A value of 0 indicates the minimum bandwidth is not
7815 /* The bandwidth value. */
7816 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
7818 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
7819 /* The granularity of the value (bits or bytes). */
7820 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
7821 UINT32_C(0x10000000)
7822 /* Value is in bits. */
7823 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
7824 (UINT32_C(0x0) << 28)
7825 /* Value is in bytes. */
7826 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
7827 (UINT32_C(0x1) << 28)
7828 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
7829 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
7830 /* bw_value_unit is 3 b */
7831 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
7832 UINT32_C(0xe0000000)
7833 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7834 /* Value is in Mb or MB (base 10). */
7835 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
7836 (UINT32_C(0x0) << 29)
7837 /* Value is in Kb or KB (base 10). */
7838 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
7839 (UINT32_C(0x2) << 29)
7840 /* Value is in bits or bytes. */
7841 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
7842 (UINT32_C(0x4) << 29)
7843 /* Value is in Gb or GB (base 10). */
7844 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
7845 (UINT32_C(0x6) << 29)
7846 /* Value is in 1/100th of a percentage of total bandwidth. */
7847 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
7848 (UINT32_C(0x1) << 29)
7850 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
7851 (UINT32_C(0x7) << 29)
7852 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
7853 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7855 * Maximum BW allocated for this function.
7856 * The HWRM will translate this value into byte counter and
7857 * time interval used for the scheduler inside the device.
7858 * A value of 0 indicates that the maximum bandwidth is not
7862 /* The bandwidth value. */
7863 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
7865 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
7866 /* The granularity of the value (bits or bytes). */
7867 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
7868 UINT32_C(0x10000000)
7869 /* Value is in bits. */
7870 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
7871 (UINT32_C(0x0) << 28)
7872 /* Value is in bytes. */
7873 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
7874 (UINT32_C(0x1) << 28)
7875 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
7876 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
7877 /* bw_value_unit is 3 b */
7878 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
7879 UINT32_C(0xe0000000)
7880 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7881 /* Value is in Mb or MB (base 10). */
7882 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
7883 (UINT32_C(0x0) << 29)
7884 /* Value is in Kb or KB (base 10). */
7885 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
7886 (UINT32_C(0x2) << 29)
7887 /* Value is in bits or bytes. */
7888 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
7889 (UINT32_C(0x4) << 29)
7890 /* Value is in Gb or GB (base 10). */
7891 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
7892 (UINT32_C(0x6) << 29)
7893 /* Value is in 1/100th of a percentage of total bandwidth. */
7894 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
7895 (UINT32_C(0x1) << 29)
7897 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
7898 (UINT32_C(0x7) << 29)
7899 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
7900 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7902 * This value indicates the Edge virtual bridge mode for the
7903 * domain that this function belongs to.
7906 /* No Edge Virtual Bridging (EVB) */
7907 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7908 /* Virtual Ethernet Bridge (VEB) */
7909 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
7910 /* Virtual Ethernet Port Aggregator (VEPA) */
7911 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
7912 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
7913 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
7916 * This value indicates the PCIE device cache line size.
7917 * The cache line size allows the DMA writes to terminate and
7918 * start at the cache boundary.
7920 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
7922 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
7923 /* Cache Line Size 64 bytes */
7924 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
7926 /* Cache Line Size 128 bytes */
7927 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
7929 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
7930 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
7931 /* This value is the virtual link admin state setting. */
7932 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
7934 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
7935 /* Admin link state is in forced down mode. */
7936 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
7937 (UINT32_C(0x0) << 2)
7938 /* Admin link state is in forced up mode. */
7939 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
7940 (UINT32_C(0x1) << 2)
7941 /* Admin link state is in auto mode - follows the physical link state. */
7942 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
7943 (UINT32_C(0x2) << 2)
7944 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
7945 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
7946 /* Reserved for future. */
7947 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
7949 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
7951 * The number of VFs that are allocated to the function.
7952 * This is valid only on the PF with SR-IOV enabled.
7953 * 0xFF... (All Fs) if this command is called on a PF with
7954 * SR-IOV disabled or on a VF.
7958 * The number of allocated multicast filters for this
7959 * function on the RX side.
7961 uint32_t alloc_mcast_filters;
7963 * The number of allocated HW ring groups for this
7966 uint32_t alloc_hw_ring_grps;
7968 * The number of strict priority transmit rings out of
7969 * currently allocated TX rings to the function
7972 uint16_t alloc_sp_tx_rings;
7974 * The number of statistics contexts
7975 * currently reserved for the function.
7977 uint16_t alloc_stat_ctx;
7979 * This field specifies how many NQs are reserved for the PF.
7980 * Remaining NQs that belong to the PF are available for VFs.
7981 * Once a PF has created VFs, it cannot change how many NQs are
7982 * reserved for itself (since the NQs must be contiguous in HW).
7984 uint16_t alloc_msix;
7986 * The number of registered VF’s associated with the PF. This field
7987 * should be ignored when the request received on the VF interface.
7988 * This field will be updated on the PF interface to initiate
7989 * the unregister request on PF in the HOT Reset Process.
7991 uint16_t registered_vfs;
7993 * The size of the doorbell BAR in KBytes reserved for L2 including
7994 * any area that is shared between L2 and RoCE. The L2 driver
7995 * should only map the L2 portion of the doorbell BAR. Any rounding
7996 * of the BAR size to the native CPU page size should be performed
7997 * by the driver. If the value is zero, no special partitioning
7998 * of the doorbell BAR between L2 and RoCE is required.
8000 uint16_t l2_doorbell_bar_size_kb;
8003 * For backward compatibility this field must be set to 1.
8004 * Older drivers might look for this field to be 1 before
8005 * processing the message.
8009 * This GRC address location is used by the Host driver interfaces to poll
8010 * the adapter ready state to re-initiate the registration process again
8011 * after receiving the RESET Notify event.
8013 uint32_t reset_addr_poll;
8015 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
8016 * this value to find out the doorbell page offset from the BAR.
8018 uint16_t legacy_l2_db_size_kb;
8019 uint8_t unused_2[1];
8021 * This field is used in Output records to indicate that the output
8022 * is completely written to RAM. This field should be read as '1'
8023 * to indicate that the output has been completely written.
8024 * When writing a command completion or response to an internal processor,
8025 * the order of writes has to be such that this field is written last.
8035 /* hwrm_func_cfg_input (size:704b/88B) */
8036 struct hwrm_func_cfg_input {
8037 /* The HWRM command request type. */
8040 * The completion ring to send the completion event on. This should
8041 * be the NQ ID returned from the `nq_alloc` HWRM command.
8045 * The sequence ID is used by the driver for tracking multiple
8046 * commands. This ID is treated as opaque data by the firmware and
8047 * the value is returned in the `hwrm_resp_hdr` upon completion.
8051 * The target ID of the command:
8052 * * 0x0-0xFFF8 - The function ID
8053 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8054 * * 0xFFFD - Reserved for user-space HWRM interface
8059 * A physical address pointer pointing to a host buffer that the
8060 * command's response data will be written. This can be either a host
8061 * physical address (HPA) or a guest physical address (GPA) and must
8062 * point to a physically contiguous block of memory.
8066 * Function ID of the function that is being
8068 * If set to 0xFF... (All Fs), then the the configuration is
8069 * for the requesting function.
8073 * This field specifies how many NQs will be reserved for the PF.
8074 * Remaining NQs that belong to the PF become available for VFs.
8075 * Once a PF has created VFs, it cannot change how many NQs are
8076 * reserved for itself (since the NQs must be contiguous in HW).
8081 * When this bit is '1', the function is disabled with
8082 * source MAC address check.
8083 * This is an anti-spoofing check. If this flag is set,
8084 * then the function shall be configured to disallow
8085 * transmission of frames with the source MAC address that
8086 * is configured for this function.
8088 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
8091 * When this bit is '1', the function is enabled with
8092 * source MAC address check.
8093 * This is an anti-spoofing check. If this flag is set,
8094 * then the function shall be configured to allow
8095 * transmission of frames with the source MAC address that
8096 * is configured for this function.
8098 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
8101 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
8103 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
8105 * Standard TX Ring mode is used for the allocation of TX ring
8106 * and underlying scheduling resources that allow bandwidth
8107 * reservation and limit settings on the queried function.
8108 * If set to 1, then standard TX ring mode is requested to be
8109 * enabled on the function being configured.
8111 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
8114 * Standard TX Ring mode is used for the allocation of TX ring
8115 * and underlying scheduling resources that allow bandwidth
8116 * reservation and limit settings on the queried function.
8117 * If set to 1, then the standard TX ring mode is requested to
8118 * be disabled on the function being configured. In this extended
8119 * TX ring resource mode, the minimum and maximum bandwidth settings
8120 * are not supported to allow the allocation of TX rings to
8121 * span multiple scheduler nodes.
8123 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
8126 * If this bit is set, virtual mac address configured
8127 * in this command will be persistent over warm boot.
8129 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
8132 * This bit only applies to the VF. If this bit is set, the statistic
8133 * context counters will not be cleared when the statistic context is freed
8134 * or a function reset is called on VF. This bit will be cleared when the PF
8135 * is unloaded or a function reset is called on the PF.
8137 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
8140 * This bit requests that the firmware test to see if all the assets
8141 * requested in this command (i.e. number of TX rings) are available.
8142 * The firmware will return an error if the requested assets are
8143 * not available. The firwmare will NOT reserve the assets if they
8146 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8149 * This bit requests that the firmware test to see if all the assets
8150 * requested in this command (i.e. number of RX rings) are available.
8151 * The firmware will return an error if the requested assets are
8152 * not available. The firwmare will NOT reserve the assets if they
8155 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8158 * This bit requests that the firmware test to see if all the assets
8159 * requested in this command (i.e. number of CMPL rings) are available.
8160 * The firmware will return an error if the requested assets are
8161 * not available. The firwmare will NOT reserve the assets if they
8164 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8167 * This bit requests that the firmware test to see if all the assets
8168 * requested in this command (i.e. number of RSS ctx) are available.
8169 * The firmware will return an error if the requested assets are
8170 * not available. The firwmare will NOT reserve the assets if they
8173 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8176 * This bit requests that the firmware test to see if all the assets
8177 * requested in this command (i.e. number of ring groups) are available.
8178 * The firmware will return an error if the requested assets are
8179 * not available. The firwmare will NOT reserve the assets if they
8182 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8185 * This bit requests that the firmware test to see if all the assets
8186 * requested in this command (i.e. number of stat ctx) are available.
8187 * The firmware will return an error if the requested assets are
8188 * not available. The firwmare will NOT reserve the assets if they
8191 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8194 * This bit requests that the firmware test to see if all the assets
8195 * requested in this command (i.e. number of VNICs) are available.
8196 * The firmware will return an error if the requested assets are
8197 * not available. The firwmare will NOT reserve the assets if they
8200 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8203 * This bit requests that the firmware test to see if all the assets
8204 * requested in this command (i.e. number of L2 ctx) are available.
8205 * The firmware will return an error if the requested assets are
8206 * not available. The firwmare will NOT reserve the assets if they
8209 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8212 * This configuration change can be initiated by a PF driver. This
8213 * configuration request shall be targeted to a VF. From local host
8214 * resident HWRM clients, only the parent PF driver shall be allowed
8215 * to initiate this change on one of its children VFs. If this bit is
8216 * set to 1, then the VF that is being configured is requested to be
8219 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
8222 * When this bit it set, even if PF reserved pool size is zero,
8223 * FW will allow driver to create TX rings in ring alloc,
8224 * by reserving TX ring, S3 node dynamically.
8226 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
8229 * This bit requests that the firmware test to see if all the assets
8230 * requested in this command (i.e. number of NQ rings) are available.
8231 * The firmware will return an error if the requested assets are
8232 * not available. The firwmare will NOT reserve the assets if they
8235 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
8238 * This configuration change can be initiated by a PF driver. This
8239 * configuration request shall be targeted to a VF. From local host
8240 * resident HWRM clients, only the parent PF driver shall be allowed
8241 * to initiate this change on one of its children VFs. If this bit is
8242 * set to 1, then the VF that is being configured is requested to be
8245 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
8248 * This bit is used by preboot drivers on a PF that require access
8249 * to the legacy L2 ring model and legacy 32b doorbells. This
8250 * feature is not allowed on VFs and is only relevant for devices
8251 * that require a context backing store.
8253 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
8257 * This bit must be '1' for the mtu field to be
8260 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
8263 * This bit must be '1' for the mru field to be
8266 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
8269 * This bit must be '1' for the num_rsscos_ctxs field to be
8272 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8275 * This bit must be '1' for the num_cmpl_rings field to be
8278 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8281 * This bit must be '1' for the num_tx_rings field to be
8284 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8287 * This bit must be '1' for the num_rx_rings field to be
8290 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8293 * This bit must be '1' for the num_l2_ctxs field to be
8296 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8299 * This bit must be '1' for the num_vnics field to be
8302 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
8305 * This bit must be '1' for the num_stat_ctxs field to be
8308 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8311 * This bit must be '1' for the dflt_mac_addr field to be
8314 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8317 * This bit must be '1' for the dflt_vlan field to be
8320 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
8323 * This bit must be '1' for the dflt_ip_addr field to be
8326 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
8329 * This bit must be '1' for the min_bw field to be
8332 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
8335 * This bit must be '1' for the max_bw field to be
8338 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
8341 * This bit must be '1' for the async_event_cr field to be
8344 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8347 * This bit must be '1' for the vlan_antispoof_mode field to be
8350 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
8353 * This bit must be '1' for the allowed_vlan_pris field to be
8356 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
8359 * This bit must be '1' for the evb_mode field to be
8362 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
8365 * This bit must be '1' for the num_mcast_filters field to be
8368 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
8371 * This bit must be '1' for the num_hw_ring_grps field to be
8374 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8377 * This bit must be '1' for the cache_linesize field to be
8380 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
8383 * This bit must be '1' for the num_msix field to be
8386 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
8389 * This bit must be '1' for the link admin state field to be
8392 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
8395 * The maximum transmission unit of the function.
8396 * The HWRM should make sure that the mtu of
8397 * the function does not exceed the mtu of the physical
8398 * port that this function is associated with.
8400 * In addition to configuring mtu per function, it is
8401 * possible to configure mtu per transmit ring.
8402 * By default, the mtu of each transmit ring associated
8403 * with a function is equal to the mtu of the function.
8404 * The HWRM should make sure that the mtu of each transmit
8405 * ring that is assigned to a function has a valid mtu.
8409 * The maximum receive unit of the function.
8410 * The HWRM should make sure that the mru of
8411 * the function does not exceed the mru of the physical
8412 * port that this function is associated with.
8414 * In addition to configuring mru per function, it is
8415 * possible to configure mru per vnic.
8416 * By default, the mru of each vnic associated
8417 * with a function is equal to the mru of the function.
8418 * The HWRM should make sure that the mru of each vnic
8419 * that is assigned to a function has a valid mru.
8423 * The number of RSS/COS contexts requested for the
8426 uint16_t num_rsscos_ctxs;
8428 * The number of completion rings requested for the
8429 * function. This does not include the rings allocated
8430 * to any children functions if any.
8432 uint16_t num_cmpl_rings;
8434 * The number of transmit rings requested for the function.
8435 * This does not include the rings allocated to any
8436 * children functions if any.
8438 uint16_t num_tx_rings;
8440 * The number of receive rings requested for the function.
8441 * This does not include the rings allocated
8442 * to any children functions if any.
8444 uint16_t num_rx_rings;
8445 /* The requested number of L2 contexts for the function. */
8446 uint16_t num_l2_ctxs;
8447 /* The requested number of vnics for the function. */
8449 /* The requested number of statistic contexts for the function. */
8450 uint16_t num_stat_ctxs;
8452 * The number of HW ring groups that should
8453 * be reserved for this function.
8455 uint16_t num_hw_ring_grps;
8456 /* The default MAC address for the function being configured. */
8457 uint8_t dflt_mac_addr[6];
8459 * The default VLAN for the function being configured.
8460 * This field's format is same as 802.1Q Tag's
8461 * Tag Control Information (TCI) format that includes both
8462 * Priority Code Point (PCP) and VLAN Identifier (VID).
8466 * The default IP address for the function being configured.
8467 * This address is only used in enabling source property check.
8469 uint32_t dflt_ip_addr[4];
8471 * Minimum BW allocated for this function.
8472 * The HWRM will translate this value into byte counter and
8473 * time interval used for the scheduler inside the device.
8476 /* The bandwidth value. */
8477 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
8479 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
8480 /* The granularity of the value (bits or bytes). */
8481 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
8482 UINT32_C(0x10000000)
8483 /* Value is in bits. */
8484 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
8485 (UINT32_C(0x0) << 28)
8486 /* Value is in bytes. */
8487 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
8488 (UINT32_C(0x1) << 28)
8489 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
8490 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
8491 /* bw_value_unit is 3 b */
8492 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
8493 UINT32_C(0xe0000000)
8494 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
8495 /* Value is in Mb or MB (base 10). */
8496 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
8497 (UINT32_C(0x0) << 29)
8498 /* Value is in Kb or KB (base 10). */
8499 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
8500 (UINT32_C(0x2) << 29)
8501 /* Value is in bits or bytes. */
8502 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
8503 (UINT32_C(0x4) << 29)
8504 /* Value is in Gb or GB (base 10). */
8505 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
8506 (UINT32_C(0x6) << 29)
8507 /* Value is in 1/100th of a percentage of total bandwidth. */
8508 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
8509 (UINT32_C(0x1) << 29)
8511 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
8512 (UINT32_C(0x7) << 29)
8513 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
8514 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
8516 * Maximum BW allocated for this function.
8517 * The HWRM will translate this value into byte counter and
8518 * time interval used for the scheduler inside the device.
8521 /* The bandwidth value. */
8522 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
8524 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
8525 /* The granularity of the value (bits or bytes). */
8526 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
8527 UINT32_C(0x10000000)
8528 /* Value is in bits. */
8529 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
8530 (UINT32_C(0x0) << 28)
8531 /* Value is in bytes. */
8532 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
8533 (UINT32_C(0x1) << 28)
8534 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
8535 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
8536 /* bw_value_unit is 3 b */
8537 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
8538 UINT32_C(0xe0000000)
8539 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
8540 /* Value is in Mb or MB (base 10). */
8541 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
8542 (UINT32_C(0x0) << 29)
8543 /* Value is in Kb or KB (base 10). */
8544 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
8545 (UINT32_C(0x2) << 29)
8546 /* Value is in bits or bytes. */
8547 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
8548 (UINT32_C(0x4) << 29)
8549 /* Value is in Gb or GB (base 10). */
8550 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
8551 (UINT32_C(0x6) << 29)
8552 /* Value is in 1/100th of a percentage of total bandwidth. */
8553 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
8554 (UINT32_C(0x1) << 29)
8556 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
8557 (UINT32_C(0x7) << 29)
8558 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
8559 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
8561 * ID of the target completion ring for receiving asynchronous
8562 * event completions. If this field is not valid, then the
8563 * HWRM shall use the default completion ring of the function
8564 * that is being configured as the target completion ring for
8565 * providing any asynchronous event completions for that
8567 * If this field is valid, then the HWRM shall use the
8568 * completion ring identified by this ID as the target
8569 * completion ring for providing any asynchronous event
8570 * completions for the function that is being configured.
8572 uint16_t async_event_cr;
8573 /* VLAN Anti-spoofing mode. */
8574 uint8_t vlan_antispoof_mode;
8575 /* No VLAN anti-spoofing checks are enabled */
8576 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
8578 /* Validate VLAN against the configured VLAN(s) */
8579 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
8581 /* Insert VLAN if it does not exist, otherwise discard */
8582 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
8584 /* Insert VLAN if it does not exist, override VLAN if it exists */
8585 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
8587 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
8588 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
8590 * This bit field defines VLAN PRIs that are allowed on
8592 * If nth bit is set, then VLAN PRI n is allowed on this
8595 uint8_t allowed_vlan_pris;
8597 * The HWRM shall allow a PF driver to change EVB mode for the
8598 * partition it belongs to.
8599 * The HWRM shall not allow a VF driver to change the EVB mode.
8600 * The HWRM shall take into account the switching of EVB mode
8601 * from one to another and reconfigure hardware resources as
8603 * The switching from VEB to VEPA mode requires
8604 * the disabling of the loopback traffic. Additionally,
8605 * source knock outs are handled differently in VEB and VEPA
8609 /* No Edge Virtual Bridging (EVB) */
8610 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
8611 /* Virtual Ethernet Bridge (VEB) */
8612 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
8613 /* Virtual Ethernet Port Aggregator (VEPA) */
8614 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
8615 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
8616 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
8619 * This value indicates the PCIE device cache line size.
8620 * The cache line size allows the DMA writes to terminate and
8621 * start at the cache boundary.
8623 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
8625 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
8626 /* Cache Line Size 64 bytes */
8627 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
8629 /* Cache Line Size 128 bytes */
8630 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
8632 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
8633 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
8634 /* This value is the virtual link admin state setting. */
8635 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
8637 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
8638 /* Admin state is forced down. */
8639 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
8640 (UINT32_C(0x0) << 2)
8641 /* Admin state is forced up. */
8642 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
8643 (UINT32_C(0x1) << 2)
8644 /* Admin state is in auto mode - is to follow the physical link state. */
8645 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
8646 (UINT32_C(0x2) << 2)
8647 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
8648 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
8649 /* Reserved for future. */
8650 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
8652 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
8654 * The number of multicast filters that should
8655 * be reserved for this function on the RX side.
8657 uint16_t num_mcast_filters;
8660 /* hwrm_func_cfg_output (size:128b/16B) */
8661 struct hwrm_func_cfg_output {
8662 /* The specific error status for the command. */
8663 uint16_t error_code;
8664 /* The HWRM command request type. */
8666 /* The sequence ID from the original command. */
8668 /* The length of the response data in number of bytes. */
8670 uint8_t unused_0[7];
8672 * This field is used in Output records to indicate that the output
8673 * is completely written to RAM. This field should be read as '1'
8674 * to indicate that the output has been completely written.
8675 * When writing a command completion or response to an internal processor,
8676 * the order of writes has to be such that this field is written last.
8681 /********************
8682 * hwrm_func_qstats *
8683 ********************/
8686 /* hwrm_func_qstats_input (size:192b/24B) */
8687 struct hwrm_func_qstats_input {
8688 /* The HWRM command request type. */
8691 * The completion ring to send the completion event on. This should
8692 * be the NQ ID returned from the `nq_alloc` HWRM command.
8696 * The sequence ID is used by the driver for tracking multiple
8697 * commands. This ID is treated as opaque data by the firmware and
8698 * the value is returned in the `hwrm_resp_hdr` upon completion.
8702 * The target ID of the command:
8703 * * 0x0-0xFFF8 - The function ID
8704 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8705 * * 0xFFFD - Reserved for user-space HWRM interface
8710 * A physical address pointer pointing to a host buffer that the
8711 * command's response data will be written. This can be either a host
8712 * physical address (HPA) or a guest physical address (GPA) and must
8713 * point to a physically contiguous block of memory.
8717 * Function ID of the function that is being queried.
8718 * 0xFF... (All Fs) if the query is for the requesting
8720 * A privileged PF can query for other function's statistics.
8723 /* This flags indicates the type of statistics request. */
8725 /* This value is not used to avoid backward compatibility issues. */
8726 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
8728 * flags should be set to 1 when request is for only RoCE statistics.
8729 * This will be honored only if the caller_fid is a privileged PF.
8730 * In all other cases FID and caller_fid should be the same.
8732 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
8733 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
8734 HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY
8735 uint8_t unused_0[5];
8738 /* hwrm_func_qstats_output (size:1408b/176B) */
8739 struct hwrm_func_qstats_output {
8740 /* The specific error status for the command. */
8741 uint16_t error_code;
8742 /* The HWRM command request type. */
8744 /* The sequence ID from the original command. */
8746 /* The length of the response data in number of bytes. */
8748 /* Number of transmitted unicast packets on the function. */
8749 uint64_t tx_ucast_pkts;
8750 /* Number of transmitted multicast packets on the function. */
8751 uint64_t tx_mcast_pkts;
8752 /* Number of transmitted broadcast packets on the function. */
8753 uint64_t tx_bcast_pkts;
8755 * Number of transmitted packets that were discarded due to
8756 * internal NIC resource problems. For transmit, this
8757 * can only happen if TMP is configured to allow dropping
8758 * in HOL blocking conditions, which is not a normal
8761 uint64_t tx_discard_pkts;
8763 * Number of dropped packets on transmit path on the function.
8764 * These are packets that have been marked for drop by
8765 * the TE CFA block or are packets that exceeded the
8766 * transmit MTU limit for the function.
8768 uint64_t tx_drop_pkts;
8769 /* Number of transmitted bytes for unicast traffic on the function. */
8770 uint64_t tx_ucast_bytes;
8771 /* Number of transmitted bytes for multicast traffic on the function. */
8772 uint64_t tx_mcast_bytes;
8773 /* Number of transmitted bytes for broadcast traffic on the function. */
8774 uint64_t tx_bcast_bytes;
8775 /* Number of received unicast packets on the function. */
8776 uint64_t rx_ucast_pkts;
8777 /* Number of received multicast packets on the function. */
8778 uint64_t rx_mcast_pkts;
8779 /* Number of received broadcast packets on the function. */
8780 uint64_t rx_bcast_pkts;
8782 * Number of received packets that were discarded on the function
8783 * due to resource limitations. This can happen for 3 reasons.
8784 * # The BD used for the packet has a bad format.
8785 * # There were no BDs available in the ring for the packet.
8786 * # There were no BDs available on-chip for the packet.
8788 uint64_t rx_discard_pkts;
8790 * Number of dropped packets on received path on the function.
8791 * These are packets that have been marked for drop by the
8794 uint64_t rx_drop_pkts;
8795 /* Number of received bytes for unicast traffic on the function. */
8796 uint64_t rx_ucast_bytes;
8797 /* Number of received bytes for multicast traffic on the function. */
8798 uint64_t rx_mcast_bytes;
8799 /* Number of received bytes for broadcast traffic on the function. */
8800 uint64_t rx_bcast_bytes;
8801 /* Number of aggregated unicast packets on the function. */
8802 uint64_t rx_agg_pkts;
8803 /* Number of aggregated unicast bytes on the function. */
8804 uint64_t rx_agg_bytes;
8805 /* Number of aggregation events on the function. */
8806 uint64_t rx_agg_events;
8807 /* Number of aborted aggregations on the function. */
8808 uint64_t rx_agg_aborts;
8809 uint8_t unused_0[7];
8811 * This field is used in Output records to indicate that the output
8812 * is completely written to RAM. This field should be read as '1'
8813 * to indicate that the output has been completely written.
8814 * When writing a command completion or response to an internal processor,
8815 * the order of writes has to be such that this field is written last.
8820 /***********************
8821 * hwrm_func_clr_stats *
8822 ***********************/
8825 /* hwrm_func_clr_stats_input (size:192b/24B) */
8826 struct hwrm_func_clr_stats_input {
8827 /* The HWRM command request type. */
8830 * The completion ring to send the completion event on. This should
8831 * be the NQ ID returned from the `nq_alloc` HWRM command.
8835 * The sequence ID is used by the driver for tracking multiple
8836 * commands. This ID is treated as opaque data by the firmware and
8837 * the value is returned in the `hwrm_resp_hdr` upon completion.
8841 * The target ID of the command:
8842 * * 0x0-0xFFF8 - The function ID
8843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8844 * * 0xFFFD - Reserved for user-space HWRM interface
8849 * A physical address pointer pointing to a host buffer that the
8850 * command's response data will be written. This can be either a host
8851 * physical address (HPA) or a guest physical address (GPA) and must
8852 * point to a physically contiguous block of memory.
8856 * Function ID of the function.
8857 * 0xFF... (All Fs) if the query is for the requesting
8861 uint8_t unused_0[6];
8864 /* hwrm_func_clr_stats_output (size:128b/16B) */
8865 struct hwrm_func_clr_stats_output {
8866 /* The specific error status for the command. */
8867 uint16_t error_code;
8868 /* The HWRM command request type. */
8870 /* The sequence ID from the original command. */
8872 /* The length of the response data in number of bytes. */
8874 uint8_t unused_0[7];
8876 * This field is used in Output records to indicate that the output
8877 * is completely written to RAM. This field should be read as '1'
8878 * to indicate that the output has been completely written.
8879 * When writing a command completion or response to an internal processor,
8880 * the order of writes has to be such that this field is written last.
8885 /**************************
8886 * hwrm_func_vf_resc_free *
8887 **************************/
8890 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
8891 struct hwrm_func_vf_resc_free_input {
8892 /* The HWRM command request type. */
8895 * The completion ring to send the completion event on. This should
8896 * be the NQ ID returned from the `nq_alloc` HWRM command.
8900 * The sequence ID is used by the driver for tracking multiple
8901 * commands. This ID is treated as opaque data by the firmware and
8902 * the value is returned in the `hwrm_resp_hdr` upon completion.
8906 * The target ID of the command:
8907 * * 0x0-0xFFF8 - The function ID
8908 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8909 * * 0xFFFD - Reserved for user-space HWRM interface
8914 * A physical address pointer pointing to a host buffer that the
8915 * command's response data will be written. This can be either a host
8916 * physical address (HPA) or a guest physical address (GPA) and must
8917 * point to a physically contiguous block of memory.
8921 * This value is used to identify a Virtual Function (VF).
8922 * The scope of VF ID is local within a PF.
8925 uint8_t unused_0[6];
8928 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
8929 struct hwrm_func_vf_resc_free_output {
8930 /* The specific error status for the command. */
8931 uint16_t error_code;
8932 /* The HWRM command request type. */
8934 /* The sequence ID from the original command. */
8936 /* The length of the response data in number of bytes. */
8938 uint8_t unused_0[7];
8940 * This field is used in Output records to indicate that the output
8941 * is completely written to RAM. This field should be read as '1'
8942 * to indicate that the output has been completely written.
8943 * When writing a command completion or response to an internal processor,
8944 * the order of writes has to be such that this field is written last.
8949 /**********************
8950 * hwrm_func_drv_rgtr *
8951 **********************/
8954 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
8955 struct hwrm_func_drv_rgtr_input {
8956 /* The HWRM command request type. */
8959 * The completion ring to send the completion event on. This should
8960 * be the NQ ID returned from the `nq_alloc` HWRM command.
8964 * The sequence ID is used by the driver for tracking multiple
8965 * commands. This ID is treated as opaque data by the firmware and
8966 * the value is returned in the `hwrm_resp_hdr` upon completion.
8970 * The target ID of the command:
8971 * * 0x0-0xFFF8 - The function ID
8972 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8973 * * 0xFFFD - Reserved for user-space HWRM interface
8978 * A physical address pointer pointing to a host buffer that the
8979 * command's response data will be written. This can be either a host
8980 * physical address (HPA) or a guest physical address (GPA) and must
8981 * point to a physically contiguous block of memory.
8986 * When this bit is '1', the function driver is requesting
8987 * all requests from its children VF drivers to be
8988 * forwarded to itself.
8989 * This flag can only be set by the PF driver.
8990 * If a VF driver sets this flag, it should be ignored
8993 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
8996 * When this bit is '1', the function is requesting none of
8997 * the requests from its children VF drivers to be
8998 * forwarded to itself.
8999 * This flag can only be set by the PF driver.
9000 * If a VF driver sets this flag, it should be ignored
9003 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
9006 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
9007 * fields shall be ignored and ver_maj, ver_min, ver_upd
9008 * and ver_patch shall be used for the driver version information.
9009 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
9010 * fields shall be used for the driver version information and
9011 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
9013 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
9016 * When this bit is '1', the function is indicating support of
9017 * 64bit flow handle. The firmware that only supports 64bit flow
9018 * handle should check this bit before allowing processing of
9019 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
9020 * with 64bit flow handle support can only be compatible with drivers
9021 * that support 64bit flow handle. The legacy drivers that don't support
9022 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
9023 * running with new firmware that only supports 64bit flow handle. The new
9024 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
9025 * status to the legacy driver when encounters these commands.
9027 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
9030 * When this bit is '1', the function is indicating support of
9031 * Hot Reset. The driver interface will destroy the resources,
9032 * unregister the function and register again up on receiving
9033 * the RESET_NOTIFY Async notification from the core firmware.
9034 * The core firmware will this use flag and trigger the Hot Reset
9035 * process only if all the registered driver instances are capable
9038 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
9041 * When this bit is 1, the function is indicating the support of the
9042 * error recovery capability. Error recovery support will be used by
9043 * firmware only if all the driver instances support error recovery
9044 * process. By setting this bit, driver is indicating support for
9045 * corresponding async event completion message. These will be
9046 * delivered to the driver even if they did not register for it.
9047 * If supported, after receiving reset notify async event with fatal
9048 * flag set in event data1, then all the drivers have to tear down
9049 * their resources without sending any HWRM commands to FW.
9051 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
9054 * When this bit is 1, the function is indicating the support of the
9055 * Master capability. The Firmware will use this capability to select the
9056 * Master function. The master function will be used to initiate
9057 * designated functionality like error recovery etc… If none of the
9058 * registered PF’s or trusted VF’s indicate this support, then
9059 * firmware will select the 1st registered PF as Master capable instance.
9061 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
9065 * This bit must be '1' for the os_type field to be
9068 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
9071 * This bit must be '1' for the ver field to be
9074 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
9077 * This bit must be '1' for the timestamp field to be
9080 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
9083 * This bit must be '1' for the vf_req_fwd field to be
9086 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
9089 * This bit must be '1' for the async_event_fwd field to be
9092 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
9094 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9097 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9098 /* Other OS not listed below. */
9099 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
9101 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9103 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9105 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9107 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
9109 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9110 /* VMware ESXi OS. */
9111 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
9112 /* Microsoft Windows 8 64-bit OS. */
9113 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9114 /* Microsoft Windows Server 2012 R2 OS. */
9115 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9117 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9118 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
9119 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
9120 /* This is the 8bit major version of the driver. */
9122 /* This is the 8bit minor version of the driver. */
9124 /* This is the 8bit update version of the driver. */
9126 uint8_t unused_0[3];
9128 * This is a 32-bit timestamp provided by the driver for
9130 * The timestamp is in multiples of 1ms.
9133 uint8_t unused_1[4];
9135 * This is a 256-bit bit mask provided by the PF driver for
9136 * letting the HWRM know what commands issued by the VF driver
9137 * to the HWRM should be forwarded to the PF driver.
9138 * Nth bit refers to the Nth req_type.
9140 * Setting Nth bit to 1 indicates that requests from the
9141 * VF driver with req_type equal to N shall be forwarded to
9142 * the parent PF driver.
9144 * This field is not valid for the VF driver.
9146 uint32_t vf_req_fwd[8];
9148 * This is a 256-bit bit mask provided by the function driver
9149 * (PF or VF driver) to indicate the list of asynchronous event
9150 * completions to be forwarded.
9152 * Nth bit refers to the Nth event_id.
9154 * Setting Nth bit to 1 by the function driver shall result in
9155 * the HWRM forwarding asynchronous event completion with
9156 * event_id equal to N.
9158 * If all bits are set to 0 (value of 0), then the HWRM shall
9159 * not forward any asynchronous event completion to this
9162 uint32_t async_event_fwd[8];
9163 /* This is the 16bit major version of the driver. */
9165 /* This is the 16bit minor version of the driver. */
9167 /* This is the 16bit update version of the driver. */
9169 /* This is the 16bit patch version of the driver. */
9173 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
9174 struct hwrm_func_drv_rgtr_output {
9175 /* The specific error status for the command. */
9176 uint16_t error_code;
9177 /* The HWRM command request type. */
9179 /* The sequence ID from the original command. */
9181 /* The length of the response data in number of bytes. */
9185 * When this bit is '1', it indicates that the
9186 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
9188 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
9190 uint8_t unused_0[3];
9192 * This field is used in Output records to indicate that the output
9193 * is completely written to RAM. This field should be read as '1'
9194 * to indicate that the output has been completely written.
9195 * When writing a command completion or response to an internal processor,
9196 * the order of writes has to be such that this field is written last.
9201 /************************
9202 * hwrm_func_drv_unrgtr *
9203 ************************/
9206 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
9207 struct hwrm_func_drv_unrgtr_input {
9208 /* The HWRM command request type. */
9211 * The completion ring to send the completion event on. This should
9212 * be the NQ ID returned from the `nq_alloc` HWRM command.
9216 * The sequence ID is used by the driver for tracking multiple
9217 * commands. This ID is treated as opaque data by the firmware and
9218 * the value is returned in the `hwrm_resp_hdr` upon completion.
9222 * The target ID of the command:
9223 * * 0x0-0xFFF8 - The function ID
9224 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9225 * * 0xFFFD - Reserved for user-space HWRM interface
9230 * A physical address pointer pointing to a host buffer that the
9231 * command's response data will be written. This can be either a host
9232 * physical address (HPA) or a guest physical address (GPA) and must
9233 * point to a physically contiguous block of memory.
9238 * When this bit is '1', the function driver is notifying
9239 * the HWRM to prepare for the shutdown.
9241 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
9243 uint8_t unused_0[4];
9246 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
9247 struct hwrm_func_drv_unrgtr_output {
9248 /* The specific error status for the command. */
9249 uint16_t error_code;
9250 /* The HWRM command request type. */
9252 /* The sequence ID from the original command. */
9254 /* The length of the response data in number of bytes. */
9256 uint8_t unused_0[7];
9258 * This field is used in Output records to indicate that the output
9259 * is completely written to RAM. This field should be read as '1'
9260 * to indicate that the output has been completely written.
9261 * When writing a command completion or response to an internal processor,
9262 * the order of writes has to be such that this field is written last.
9267 /**********************
9268 * hwrm_func_buf_rgtr *
9269 **********************/
9272 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
9273 struct hwrm_func_buf_rgtr_input {
9274 /* The HWRM command request type. */
9277 * The completion ring to send the completion event on. This should
9278 * be the NQ ID returned from the `nq_alloc` HWRM command.
9282 * The sequence ID is used by the driver for tracking multiple
9283 * commands. This ID is treated as opaque data by the firmware and
9284 * the value is returned in the `hwrm_resp_hdr` upon completion.
9288 * The target ID of the command:
9289 * * 0x0-0xFFF8 - The function ID
9290 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9291 * * 0xFFFD - Reserved for user-space HWRM interface
9296 * A physical address pointer pointing to a host buffer that the
9297 * command's response data will be written. This can be either a host
9298 * physical address (HPA) or a guest physical address (GPA) and must
9299 * point to a physically contiguous block of memory.
9304 * This bit must be '1' for the vf_id field to be
9307 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9309 * This bit must be '1' for the err_buf_addr field to be
9312 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
9314 * This value is used to identify a Virtual Function (VF).
9315 * The scope of VF ID is local within a PF.
9319 * This field represents the number of pages used for request
9322 uint16_t req_buf_num_pages;
9324 * This field represents the page size used for request
9327 uint16_t req_buf_page_size;
9329 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
9331 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
9333 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
9335 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
9337 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
9339 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
9341 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
9342 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
9343 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
9344 /* The length of the request buffer per VF in bytes. */
9345 uint16_t req_buf_len;
9346 /* The length of the response buffer in bytes. */
9347 uint16_t resp_buf_len;
9348 uint8_t unused_0[2];
9349 /* This field represents the page address of page #0. */
9350 uint64_t req_buf_page_addr0;
9351 /* This field represents the page address of page #1. */
9352 uint64_t req_buf_page_addr1;
9353 /* This field represents the page address of page #2. */
9354 uint64_t req_buf_page_addr2;
9355 /* This field represents the page address of page #3. */
9356 uint64_t req_buf_page_addr3;
9357 /* This field represents the page address of page #4. */
9358 uint64_t req_buf_page_addr4;
9359 /* This field represents the page address of page #5. */
9360 uint64_t req_buf_page_addr5;
9361 /* This field represents the page address of page #6. */
9362 uint64_t req_buf_page_addr6;
9363 /* This field represents the page address of page #7. */
9364 uint64_t req_buf_page_addr7;
9365 /* This field represents the page address of page #8. */
9366 uint64_t req_buf_page_addr8;
9367 /* This field represents the page address of page #9. */
9368 uint64_t req_buf_page_addr9;
9370 * This field is used to receive the error reporting from
9371 * the chipset. Only applicable for PFs.
9373 uint64_t error_buf_addr;
9375 * This field is used to receive the response forwarded by the
9378 uint64_t resp_buf_addr;
9381 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
9382 struct hwrm_func_buf_rgtr_output {
9383 /* The specific error status for the command. */
9384 uint16_t error_code;
9385 /* The HWRM command request type. */
9387 /* The sequence ID from the original command. */
9389 /* The length of the response data in number of bytes. */
9391 uint8_t unused_0[7];
9393 * This field is used in Output records to indicate that the output
9394 * is completely written to RAM. This field should be read as '1'
9395 * to indicate that the output has been completely written.
9396 * When writing a command completion or response to an internal processor,
9397 * the order of writes has to be such that this field is written last.
9402 /************************
9403 * hwrm_func_buf_unrgtr *
9404 ************************/
9407 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
9408 struct hwrm_func_buf_unrgtr_input {
9409 /* The HWRM command request type. */
9412 * The completion ring to send the completion event on. This should
9413 * be the NQ ID returned from the `nq_alloc` HWRM command.
9417 * The sequence ID is used by the driver for tracking multiple
9418 * commands. This ID is treated as opaque data by the firmware and
9419 * the value is returned in the `hwrm_resp_hdr` upon completion.
9423 * The target ID of the command:
9424 * * 0x0-0xFFF8 - The function ID
9425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9426 * * 0xFFFD - Reserved for user-space HWRM interface
9431 * A physical address pointer pointing to a host buffer that the
9432 * command's response data will be written. This can be either a host
9433 * physical address (HPA) or a guest physical address (GPA) and must
9434 * point to a physically contiguous block of memory.
9439 * This bit must be '1' for the vf_id field to be
9442 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
9444 * This value is used to identify a Virtual Function (VF).
9445 * The scope of VF ID is local within a PF.
9448 uint8_t unused_0[2];
9451 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
9452 struct hwrm_func_buf_unrgtr_output {
9453 /* The specific error status for the command. */
9454 uint16_t error_code;
9455 /* The HWRM command request type. */
9457 /* The sequence ID from the original command. */
9459 /* The length of the response data in number of bytes. */
9461 uint8_t unused_0[7];
9463 * This field is used in Output records to indicate that the output
9464 * is completely written to RAM. This field should be read as '1'
9465 * to indicate that the output has been completely written.
9466 * When writing a command completion or response to an internal processor,
9467 * the order of writes has to be such that this field is written last.
9472 /**********************
9473 * hwrm_func_drv_qver *
9474 **********************/
9477 /* hwrm_func_drv_qver_input (size:192b/24B) */
9478 struct hwrm_func_drv_qver_input {
9479 /* The HWRM command request type. */
9482 * The completion ring to send the completion event on. This should
9483 * be the NQ ID returned from the `nq_alloc` HWRM command.
9487 * The sequence ID is used by the driver for tracking multiple
9488 * commands. This ID is treated as opaque data by the firmware and
9489 * the value is returned in the `hwrm_resp_hdr` upon completion.
9493 * The target ID of the command:
9494 * * 0x0-0xFFF8 - The function ID
9495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9496 * * 0xFFFD - Reserved for user-space HWRM interface
9501 * A physical address pointer pointing to a host buffer that the
9502 * command's response data will be written. This can be either a host
9503 * physical address (HPA) or a guest physical address (GPA) and must
9504 * point to a physically contiguous block of memory.
9507 /* Reserved for future use. */
9510 * Function ID of the function that is being queried.
9511 * 0xFF... (All Fs) if the query is for the requesting
9515 uint8_t unused_0[2];
9518 /* hwrm_func_drv_qver_output (size:256b/32B) */
9519 struct hwrm_func_drv_qver_output {
9520 /* The specific error status for the command. */
9521 uint16_t error_code;
9522 /* The HWRM command request type. */
9524 /* The sequence ID from the original command. */
9526 /* The length of the response data in number of bytes. */
9528 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
9531 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
9532 /* Other OS not listed below. */
9533 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
9535 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
9537 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
9539 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
9541 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
9543 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
9544 /* VMware ESXi OS. */
9545 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
9546 /* Microsoft Windows 8 64-bit OS. */
9547 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
9548 /* Microsoft Windows Server 2012 R2 OS. */
9549 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
9551 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
9552 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
9553 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
9554 /* This is the 8bit major version of the driver. */
9556 /* This is the 8bit minor version of the driver. */
9558 /* This is the 8bit update version of the driver. */
9560 uint8_t unused_0[3];
9561 /* This is the 16bit major version of the driver. */
9563 /* This is the 16bit minor version of the driver. */
9565 /* This is the 16bit update version of the driver. */
9567 /* This is the 16bit patch version of the driver. */
9569 uint8_t unused_1[7];
9571 * This field is used in Output records to indicate that the output
9572 * is completely written to RAM. This field should be read as '1'
9573 * to indicate that the output has been completely written.
9574 * When writing a command completion or response to an internal processor,
9575 * the order of writes has to be such that this field is written last.
9580 /****************************
9581 * hwrm_func_resource_qcaps *
9582 ****************************/
9585 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
9586 struct hwrm_func_resource_qcaps_input {
9587 /* The HWRM command request type. */
9590 * The completion ring to send the completion event on. This should
9591 * be the NQ ID returned from the `nq_alloc` HWRM command.
9595 * The sequence ID is used by the driver for tracking multiple
9596 * commands. This ID is treated as opaque data by the firmware and
9597 * the value is returned in the `hwrm_resp_hdr` upon completion.
9601 * The target ID of the command:
9602 * * 0x0-0xFFF8 - The function ID
9603 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9604 * * 0xFFFD - Reserved for user-space HWRM interface
9609 * A physical address pointer pointing to a host buffer that the
9610 * command's response data will be written. This can be either a host
9611 * physical address (HPA) or a guest physical address (GPA) and must
9612 * point to a physically contiguous block of memory.
9616 * Function ID of the function that is being queried.
9617 * 0xFF... (All Fs) if the query is for the requesting
9621 uint8_t unused_0[6];
9624 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
9625 struct hwrm_func_resource_qcaps_output {
9626 /* The specific error status for the command. */
9627 uint16_t error_code;
9628 /* The HWRM command request type. */
9630 /* The sequence ID from the original command. */
9632 /* The length of the response data in number of bytes. */
9634 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
9636 /* Maximum guaranteed number of MSI-X vectors supported by function */
9638 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
9639 uint16_t vf_reservation_strategy;
9640 /* The PF driver should evenly divide its remaining resources among all VFs. */
9641 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
9643 /* The PF driver should only reserve minimal resources for each VF. */
9644 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
9647 * The PF driver should not reserve any resources for each VF until the
9648 * the VF interface is brought up.
9650 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
9652 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
9653 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
9654 /* Minimum guaranteed number of RSS/COS contexts */
9655 uint16_t min_rsscos_ctx;
9656 /* Maximum non-guaranteed number of RSS/COS contexts */
9657 uint16_t max_rsscos_ctx;
9658 /* Minimum guaranteed number of completion rings */
9659 uint16_t min_cmpl_rings;
9660 /* Maximum non-guaranteed number of completion rings */
9661 uint16_t max_cmpl_rings;
9662 /* Minimum guaranteed number of transmit rings */
9663 uint16_t min_tx_rings;
9664 /* Maximum non-guaranteed number of transmit rings */
9665 uint16_t max_tx_rings;
9666 /* Minimum guaranteed number of receive rings */
9667 uint16_t min_rx_rings;
9668 /* Maximum non-guaranteed number of receive rings */
9669 uint16_t max_rx_rings;
9670 /* Minimum guaranteed number of L2 contexts */
9671 uint16_t min_l2_ctxs;
9672 /* Maximum non-guaranteed number of L2 contexts */
9673 uint16_t max_l2_ctxs;
9674 /* Minimum guaranteed number of VNICs */
9676 /* Maximum non-guaranteed number of VNICs */
9678 /* Minimum guaranteed number of statistic contexts */
9679 uint16_t min_stat_ctx;
9680 /* Maximum non-guaranteed number of statistic contexts */
9681 uint16_t max_stat_ctx;
9682 /* Minimum guaranteed number of ring groups */
9683 uint16_t min_hw_ring_grps;
9684 /* Maximum non-guaranteed number of ring groups */
9685 uint16_t max_hw_ring_grps;
9687 * Maximum number of inputs into the transmit scheduler for this function.
9688 * The number of TX rings assigned to the function cannot exceed this value.
9690 uint16_t max_tx_scheduler_inputs;
9693 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
9694 * feature to reserve all minimum resources when minimum >= 1, otherwise
9697 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
9699 uint8_t unused_0[5];
9701 * This field is used in Output records to indicate that the output
9702 * is completely written to RAM. This field should be read as '1'
9703 * to indicate that the output has been completely written.
9704 * When writing a command completion or response to an internal processor,
9705 * the order of writes has to be such that this field is written last.
9710 /*********************************
9711 * hwrm_func_backing_store_qcaps *
9712 *********************************/
9715 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
9716 struct hwrm_func_backing_store_qcaps_input {
9717 /* The HWRM command request type. */
9720 * The completion ring to send the completion event on. This should
9721 * be the NQ ID returned from the `nq_alloc` HWRM command.
9725 * The sequence ID is used by the driver for tracking multiple
9726 * commands. This ID is treated as opaque data by the firmware and
9727 * the value is returned in the `hwrm_resp_hdr` upon completion.
9731 * The target ID of the command:
9732 * * 0x0-0xFFF8 - The function ID
9733 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9734 * * 0xFFFD - Reserved for user-space HWRM interface
9739 * A physical address pointer pointing to a host buffer that the
9740 * command's response data will be written. This can be either a host
9741 * physical address (HPA) or a guest physical address (GPA) and must
9742 * point to a physically contiguous block of memory.
9747 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
9748 struct hwrm_func_backing_store_qcaps_output {
9749 /* The specific error status for the command. */
9750 uint16_t error_code;
9751 /* The HWRM command request type. */
9753 /* The sequence ID from the original command. */
9755 /* The length of the response data in number of bytes. */
9757 /* Maximum number of QP context entries supported for this function. */
9758 uint32_t qp_max_entries;
9760 * Minimum number of QP context entries that are needed to be reserved
9761 * for QP1 for the PF and its VFs. PF drivers must allocate at least
9762 * this many QP context entries, even if RoCE will not be used.
9764 uint16_t qp_min_qp1_entries;
9765 /* Maximum number of QP context entries that can be used for L2. */
9766 uint16_t qp_max_l2_entries;
9767 /* Number of bytes that must be allocated for each context entry. */
9768 uint16_t qp_entry_size;
9769 /* Maximum number of SRQ context entries that can be used for L2. */
9770 uint16_t srq_max_l2_entries;
9771 /* Maximum number of SRQ context entries supported for this function. */
9772 uint32_t srq_max_entries;
9773 /* Number of bytes that must be allocated for each context entry. */
9774 uint16_t srq_entry_size;
9775 /* Maximum number of CQ context entries that can be used for L2. */
9776 uint16_t cq_max_l2_entries;
9777 /* Maximum number of CQ context entries supported for this function. */
9778 uint32_t cq_max_entries;
9779 /* Number of bytes that must be allocated for each context entry. */
9780 uint16_t cq_entry_size;
9781 /* Maximum number of VNIC context entries supported for this function. */
9782 uint16_t vnic_max_vnic_entries;
9783 /* Maximum number of Ring table context entries supported for this function. */
9784 uint16_t vnic_max_ring_table_entries;
9785 /* Number of bytes that must be allocated for each context entry. */
9786 uint16_t vnic_entry_size;
9787 /* Maximum number of statistic context entries supported for this function. */
9788 uint32_t stat_max_entries;
9789 /* Number of bytes that must be allocated for each context entry. */
9790 uint16_t stat_entry_size;
9791 /* Number of bytes that must be allocated for each context entry. */
9792 uint16_t tqm_entry_size;
9793 /* Minimum number of TQM context entries required per ring. */
9794 uint32_t tqm_min_entries_per_ring;
9796 * Maximum number of TQM context entries supported per ring. This is
9797 * actually a recommended TQM queue size based on worst case usage of
9800 * TQM fastpath rings should be sized large enough to accommodate the
9801 * maximum number of QPs (either L2 or RoCE, or both if shared)
9802 * that can be enqueued to the TQM ring.
9804 * TQM slowpath rings should be sized as follows:
9806 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
9809 * num_vnics is the number of VNICs allocated in the VNIC backing store
9810 * num_l2_tx_rings is the number of L2 rings in the QP backing store
9811 * num_roce_qps is the number of RoCE QPs in the QP backing store
9812 * tqm_min_size is tqm_min_entries_per_ring reported by
9813 * HWRM_FUNC_BACKING_STORE_QCAPS
9815 * Note that TQM ring sizes cannot be extended while the system is
9816 * operational. If a PF driver needs to extend a TQM ring, it needs
9817 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
9818 * the backing store.
9820 uint32_t tqm_max_entries_per_ring;
9822 * Maximum number of MR plus AV context entries supported for this
9825 uint32_t mrav_max_entries;
9826 /* Number of bytes that must be allocated for each context entry. */
9827 uint16_t mrav_entry_size;
9828 /* Number of bytes that must be allocated for each context entry. */
9829 uint16_t tim_entry_size;
9830 /* Maximum number of Timer context entries supported for this function. */
9831 uint32_t tim_max_entries;
9833 * When this field is zero, the 32b `mrav_num_entries` field in the
9834 * `backing_store_cfg` and `backing_store_qcfg` commands represents
9835 * the total number of MR plus AV entries allowed in the MR/AV backing
9838 * When this field is non-zero, the 32b `mrav_num_entries` field in
9839 * the `backing_store_cfg` and `backing_store_qcfg` commands is
9840 * logically divided into two 16b fields. Bits `[31:16]` represents
9841 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
9842 * Both of these values are represented in a unit granularity
9843 * specified by this field. For example, if this field is 16 and
9844 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
9845 * is 8192 and the number of AV entries is 4096.
9847 uint16_t mrav_num_entries_units;
9849 * The number of entries specified for any TQM ring must be a
9850 * multiple of this value to prevent any resource allocation
9853 uint8_t tqm_entries_multiple;
9855 * Initializer to be used by drivers
9856 * to initialize context memory to ensure
9857 * context subsystem flags an error for an attack
9858 * before the first time context load.
9860 uint8_t ctx_kind_initializer;
9861 /* Reserved for future. */
9863 /* Reserved for future. */
9865 /* Reserved for future. */
9868 * This field is used in Output records to indicate that the output
9869 * is completely written to RAM. This field should be read as '1'
9870 * to indicate that the output has been completely written.
9871 * When writing a command completion or response to an internal processor,
9872 * the order of writes has to be such that this field is written last.
9877 /*******************************
9878 * hwrm_func_backing_store_cfg *
9879 *******************************/
9882 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
9883 struct hwrm_func_backing_store_cfg_input {
9884 /* The HWRM command request type. */
9887 * The completion ring to send the completion event on. This should
9888 * be the NQ ID returned from the `nq_alloc` HWRM command.
9892 * The sequence ID is used by the driver for tracking multiple
9893 * commands. This ID is treated as opaque data by the firmware and
9894 * the value is returned in the `hwrm_resp_hdr` upon completion.
9898 * The target ID of the command:
9899 * * 0x0-0xFFF8 - The function ID
9900 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9901 * * 0xFFFD - Reserved for user-space HWRM interface
9906 * A physical address pointer pointing to a host buffer that the
9907 * command's response data will be written. This can be either a host
9908 * physical address (HPA) or a guest physical address (GPA) and must
9909 * point to a physically contiguous block of memory.
9914 * When set, the firmware only uses on-chip resources and does not
9915 * expect any backing store to be provided by the host driver. This
9916 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
9922 * When set, the 32b `mrav_num_entries` field is logically divided
9923 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
9925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
9929 * This bit must be '1' for the qp fields to be
9932 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
9935 * This bit must be '1' for the srq fields to be
9938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
9941 * This bit must be '1' for the cq fields to be
9944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
9947 * This bit must be '1' for the vnic fields to be
9950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
9953 * This bit must be '1' for the stat fields to be
9956 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
9959 * This bit must be '1' for the tqm_sp fields to be
9962 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
9965 * This bit must be '1' for the tqm_ring0 fields to be
9968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
9971 * This bit must be '1' for the tqm_ring1 fields to be
9974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
9977 * This bit must be '1' for the tqm_ring2 fields to be
9980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
9983 * This bit must be '1' for the tqm_ring3 fields to be
9986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
9989 * This bit must be '1' for the tqm_ring4 fields to be
9992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
9995 * This bit must be '1' for the tqm_ring5 fields to be
9998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
10001 * This bit must be '1' for the tqm_ring6 fields to be
10004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
10007 * This bit must be '1' for the tqm_ring7 fields to be
10010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
10013 * This bit must be '1' for the mrav fields to be
10016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
10019 * This bit must be '1' for the tim fields to be
10022 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
10024 /* QPC page size and level. */
10025 uint8_t qpc_pg_size_qpc_lvl;
10026 /* QPC PBL indirect levels. */
10027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
10029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
10030 /* PBL pointer is physical start address. */
10031 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
10033 /* PBL pointer points to PTE table. */
10034 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
10036 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
10039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
10040 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
10041 /* QPC page size. */
10042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
10044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
10046 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
10047 (UINT32_C(0x0) << 4)
10049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
10050 (UINT32_C(0x1) << 4)
10052 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
10053 (UINT32_C(0x2) << 4)
10055 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
10056 (UINT32_C(0x3) << 4)
10058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
10059 (UINT32_C(0x4) << 4)
10061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
10062 (UINT32_C(0x5) << 4)
10063 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
10064 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
10065 /* SRQ page size and level. */
10066 uint8_t srq_pg_size_srq_lvl;
10067 /* SRQ PBL indirect levels. */
10068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
10070 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
10071 /* PBL pointer is physical start address. */
10072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
10074 /* PBL pointer points to PTE table. */
10075 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
10077 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
10080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
10081 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
10082 /* SRQ page size. */
10083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
10085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
10087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
10088 (UINT32_C(0x0) << 4)
10090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
10091 (UINT32_C(0x1) << 4)
10093 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
10094 (UINT32_C(0x2) << 4)
10096 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
10097 (UINT32_C(0x3) << 4)
10099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
10100 (UINT32_C(0x4) << 4)
10102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
10103 (UINT32_C(0x5) << 4)
10104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
10105 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
10106 /* CQ page size and level. */
10107 uint8_t cq_pg_size_cq_lvl;
10108 /* CQ PBL indirect levels. */
10109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
10111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
10112 /* PBL pointer is physical start address. */
10113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
10115 /* PBL pointer points to PTE table. */
10116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
10118 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
10121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
10122 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
10123 /* CQ page size. */
10124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
10126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
10128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
10129 (UINT32_C(0x0) << 4)
10131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
10132 (UINT32_C(0x1) << 4)
10134 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
10135 (UINT32_C(0x2) << 4)
10137 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
10138 (UINT32_C(0x3) << 4)
10140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
10141 (UINT32_C(0x4) << 4)
10143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
10144 (UINT32_C(0x5) << 4)
10145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
10146 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
10147 /* VNIC page size and level. */
10148 uint8_t vnic_pg_size_vnic_lvl;
10149 /* VNIC PBL indirect levels. */
10150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
10152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
10153 /* PBL pointer is physical start address. */
10154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
10156 /* PBL pointer points to PTE table. */
10157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
10159 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
10162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
10163 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
10164 /* VNIC page size. */
10165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
10167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
10169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
10170 (UINT32_C(0x0) << 4)
10172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
10173 (UINT32_C(0x1) << 4)
10175 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
10176 (UINT32_C(0x2) << 4)
10178 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
10179 (UINT32_C(0x3) << 4)
10181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
10182 (UINT32_C(0x4) << 4)
10184 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
10185 (UINT32_C(0x5) << 4)
10186 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
10187 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
10188 /* Stat page size and level. */
10189 uint8_t stat_pg_size_stat_lvl;
10190 /* Stat PBL indirect levels. */
10191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
10193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
10194 /* PBL pointer is physical start address. */
10195 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
10197 /* PBL pointer points to PTE table. */
10198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
10200 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
10203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
10204 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
10205 /* Stat page size. */
10206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
10208 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
10210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
10211 (UINT32_C(0x0) << 4)
10213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
10214 (UINT32_C(0x1) << 4)
10216 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
10217 (UINT32_C(0x2) << 4)
10219 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
10220 (UINT32_C(0x3) << 4)
10222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
10223 (UINT32_C(0x4) << 4)
10225 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
10226 (UINT32_C(0x5) << 4)
10227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
10228 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
10229 /* TQM slow path page size and level. */
10230 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
10231 /* TQM slow path PBL indirect levels. */
10232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
10234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
10235 /* PBL pointer is physical start address. */
10236 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
10238 /* PBL pointer points to PTE table. */
10239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
10241 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
10244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
10245 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
10246 /* TQM slow path page size. */
10247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
10249 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
10251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
10252 (UINT32_C(0x0) << 4)
10254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
10255 (UINT32_C(0x1) << 4)
10257 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
10258 (UINT32_C(0x2) << 4)
10260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
10261 (UINT32_C(0x3) << 4)
10263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
10264 (UINT32_C(0x4) << 4)
10266 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
10267 (UINT32_C(0x5) << 4)
10268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
10269 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
10270 /* TQM ring 0 page size and level. */
10271 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
10272 /* TQM ring 0 PBL indirect levels. */
10273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
10275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
10276 /* PBL pointer is physical start address. */
10277 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
10279 /* PBL pointer points to PTE table. */
10280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
10282 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
10285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
10286 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
10287 /* TQM ring 0 page size. */
10288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
10290 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
10292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
10293 (UINT32_C(0x0) << 4)
10295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
10296 (UINT32_C(0x1) << 4)
10298 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
10299 (UINT32_C(0x2) << 4)
10301 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
10302 (UINT32_C(0x3) << 4)
10304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
10305 (UINT32_C(0x4) << 4)
10307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
10308 (UINT32_C(0x5) << 4)
10309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
10310 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
10311 /* TQM ring 1 page size and level. */
10312 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
10313 /* TQM ring 1 PBL indirect levels. */
10314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
10316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
10317 /* PBL pointer is physical start address. */
10318 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
10320 /* PBL pointer points to PTE table. */
10321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
10323 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
10326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
10327 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
10328 /* TQM ring 1 page size. */
10329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
10331 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
10333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
10334 (UINT32_C(0x0) << 4)
10336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
10337 (UINT32_C(0x1) << 4)
10339 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
10340 (UINT32_C(0x2) << 4)
10342 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
10343 (UINT32_C(0x3) << 4)
10345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
10346 (UINT32_C(0x4) << 4)
10348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
10349 (UINT32_C(0x5) << 4)
10350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
10351 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
10352 /* TQM ring 2 page size and level. */
10353 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
10354 /* TQM ring 2 PBL indirect levels. */
10355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
10357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
10358 /* PBL pointer is physical start address. */
10359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
10361 /* PBL pointer points to PTE table. */
10362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
10364 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
10367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
10368 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
10369 /* TQM ring 2 page size. */
10370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
10372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
10374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
10375 (UINT32_C(0x0) << 4)
10377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
10378 (UINT32_C(0x1) << 4)
10380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
10381 (UINT32_C(0x2) << 4)
10383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
10384 (UINT32_C(0x3) << 4)
10386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
10387 (UINT32_C(0x4) << 4)
10389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
10390 (UINT32_C(0x5) << 4)
10391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
10392 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
10393 /* TQM ring 3 page size and level. */
10394 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
10395 /* TQM ring 3 PBL indirect levels. */
10396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
10398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
10399 /* PBL pointer is physical start address. */
10400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
10402 /* PBL pointer points to PTE table. */
10403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
10405 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
10408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
10409 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
10410 /* TQM ring 3 page size. */
10411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
10413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
10415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
10416 (UINT32_C(0x0) << 4)
10418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
10419 (UINT32_C(0x1) << 4)
10421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
10422 (UINT32_C(0x2) << 4)
10424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
10425 (UINT32_C(0x3) << 4)
10427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
10428 (UINT32_C(0x4) << 4)
10430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
10431 (UINT32_C(0x5) << 4)
10432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
10433 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
10434 /* TQM ring 4 page size and level. */
10435 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
10436 /* TQM ring 4 PBL indirect levels. */
10437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
10439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
10440 /* PBL pointer is physical start address. */
10441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
10443 /* PBL pointer points to PTE table. */
10444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
10446 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
10449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
10450 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
10451 /* TQM ring 4 page size. */
10452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
10454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
10456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
10457 (UINT32_C(0x0) << 4)
10459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
10460 (UINT32_C(0x1) << 4)
10462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
10463 (UINT32_C(0x2) << 4)
10465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
10466 (UINT32_C(0x3) << 4)
10468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
10469 (UINT32_C(0x4) << 4)
10471 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
10472 (UINT32_C(0x5) << 4)
10473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
10474 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
10475 /* TQM ring 5 page size and level. */
10476 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
10477 /* TQM ring 5 PBL indirect levels. */
10478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
10480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
10481 /* PBL pointer is physical start address. */
10482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
10484 /* PBL pointer points to PTE table. */
10485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
10487 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
10490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
10491 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
10492 /* TQM ring 5 page size. */
10493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
10495 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
10497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
10498 (UINT32_C(0x0) << 4)
10500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
10501 (UINT32_C(0x1) << 4)
10503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
10504 (UINT32_C(0x2) << 4)
10506 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
10507 (UINT32_C(0x3) << 4)
10509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
10510 (UINT32_C(0x4) << 4)
10512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
10513 (UINT32_C(0x5) << 4)
10514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
10515 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
10516 /* TQM ring 6 page size and level. */
10517 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
10518 /* TQM ring 6 PBL indirect levels. */
10519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
10521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
10522 /* PBL pointer is physical start address. */
10523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
10525 /* PBL pointer points to PTE table. */
10526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
10528 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
10531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
10532 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
10533 /* TQM ring 6 page size. */
10534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
10536 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
10538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
10539 (UINT32_C(0x0) << 4)
10541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
10542 (UINT32_C(0x1) << 4)
10544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
10545 (UINT32_C(0x2) << 4)
10547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
10548 (UINT32_C(0x3) << 4)
10550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
10551 (UINT32_C(0x4) << 4)
10553 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
10554 (UINT32_C(0x5) << 4)
10555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
10556 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
10557 /* TQM ring 7 page size and level. */
10558 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
10559 /* TQM ring 7 PBL indirect levels. */
10560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
10562 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
10563 /* PBL pointer is physical start address. */
10564 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
10566 /* PBL pointer points to PTE table. */
10567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
10569 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
10572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
10573 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
10574 /* TQM ring 7 page size. */
10575 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
10577 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
10579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
10580 (UINT32_C(0x0) << 4)
10582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
10583 (UINT32_C(0x1) << 4)
10585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
10586 (UINT32_C(0x2) << 4)
10588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
10589 (UINT32_C(0x3) << 4)
10591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
10592 (UINT32_C(0x4) << 4)
10594 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
10595 (UINT32_C(0x5) << 4)
10596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
10597 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
10598 /* MR/AV page size and level. */
10599 uint8_t mrav_pg_size_mrav_lvl;
10600 /* MR/AV PBL indirect levels. */
10601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
10603 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
10604 /* PBL pointer is physical start address. */
10605 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
10607 /* PBL pointer points to PTE table. */
10608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
10610 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
10613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
10614 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
10615 /* MR/AV page size. */
10616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
10618 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
10620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
10621 (UINT32_C(0x0) << 4)
10623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
10624 (UINT32_C(0x1) << 4)
10626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
10627 (UINT32_C(0x2) << 4)
10629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
10630 (UINT32_C(0x3) << 4)
10632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
10633 (UINT32_C(0x4) << 4)
10635 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
10636 (UINT32_C(0x5) << 4)
10637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
10638 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
10639 /* Timer page size and level. */
10640 uint8_t tim_pg_size_tim_lvl;
10641 /* Timer PBL indirect levels. */
10642 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
10644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
10645 /* PBL pointer is physical start address. */
10646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
10648 /* PBL pointer points to PTE table. */
10649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
10651 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
10652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
10654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
10655 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
10656 /* Timer page size. */
10657 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
10659 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
10661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
10662 (UINT32_C(0x0) << 4)
10664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
10665 (UINT32_C(0x1) << 4)
10667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
10668 (UINT32_C(0x2) << 4)
10670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
10671 (UINT32_C(0x3) << 4)
10673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
10674 (UINT32_C(0x4) << 4)
10676 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
10677 (UINT32_C(0x5) << 4)
10678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
10679 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
10680 /* QP page directory. */
10681 uint64_t qpc_page_dir;
10682 /* SRQ page directory. */
10683 uint64_t srq_page_dir;
10684 /* CQ page directory. */
10685 uint64_t cq_page_dir;
10686 /* VNIC page directory. */
10687 uint64_t vnic_page_dir;
10688 /* Stat page directory. */
10689 uint64_t stat_page_dir;
10690 /* TQM slowpath page directory. */
10691 uint64_t tqm_sp_page_dir;
10692 /* TQM ring 0 page directory. */
10693 uint64_t tqm_ring0_page_dir;
10694 /* TQM ring 1 page directory. */
10695 uint64_t tqm_ring1_page_dir;
10696 /* TQM ring 2 page directory. */
10697 uint64_t tqm_ring2_page_dir;
10698 /* TQM ring 3 page directory. */
10699 uint64_t tqm_ring3_page_dir;
10700 /* TQM ring 4 page directory. */
10701 uint64_t tqm_ring4_page_dir;
10702 /* TQM ring 5 page directory. */
10703 uint64_t tqm_ring5_page_dir;
10704 /* TQM ring 6 page directory. */
10705 uint64_t tqm_ring6_page_dir;
10706 /* TQM ring 7 page directory. */
10707 uint64_t tqm_ring7_page_dir;
10708 /* MR/AV page directory. */
10709 uint64_t mrav_page_dir;
10710 /* Timer page directory. */
10711 uint64_t tim_page_dir;
10712 /* Number of QPs. */
10713 uint32_t qp_num_entries;
10714 /* Number of SRQs. */
10715 uint32_t srq_num_entries;
10716 /* Number of CQs. */
10717 uint32_t cq_num_entries;
10718 /* Number of Stats. */
10719 uint32_t stat_num_entries;
10721 * Number of TQM slowpath entries.
10723 * TQM slowpath rings should be sized as follows:
10725 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
10728 * num_vnics is the number of VNICs allocated in the VNIC backing store
10729 * num_l2_tx_rings is the number of L2 rings in the QP backing store
10730 * num_roce_qps is the number of RoCE QPs in the QP backing store
10731 * tqm_min_size is tqm_min_entries_per_ring reported by
10732 * HWRM_FUNC_BACKING_STORE_QCAPS
10734 * Note that TQM ring sizes cannot be extended while the system is
10735 * operational. If a PF driver needs to extend a TQM ring, it needs
10736 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10737 * the backing store.
10739 uint32_t tqm_sp_num_entries;
10741 * Number of TQM ring 0 entries.
10743 * TQM fastpath rings should be sized large enough to accommodate the
10744 * maximum number of QPs (either L2 or RoCE, or both if shared)
10745 * that can be enqueued to the TQM ring.
10747 * Note that TQM ring sizes cannot be extended while the system is
10748 * operational. If a PF driver needs to extend a TQM ring, it needs
10749 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10750 * the backing store.
10752 uint32_t tqm_ring0_num_entries;
10754 * Number of TQM ring 1 entries.
10756 * TQM fastpath rings should be sized large enough to accommodate the
10757 * maximum number of QPs (either L2 or RoCE, or both if shared)
10758 * that can be enqueued to the TQM ring.
10760 * Note that TQM ring sizes cannot be extended while the system is
10761 * operational. If a PF driver needs to extend a TQM ring, it needs
10762 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10763 * the backing store.
10765 uint32_t tqm_ring1_num_entries;
10767 * Number of TQM ring 2 entries.
10769 * TQM fastpath rings should be sized large enough to accommodate the
10770 * maximum number of QPs (either L2 or RoCE, or both if shared)
10771 * that can be enqueued to the TQM ring.
10773 * Note that TQM ring sizes cannot be extended while the system is
10774 * operational. If a PF driver needs to extend a TQM ring, it needs
10775 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10776 * the backing store.
10778 uint32_t tqm_ring2_num_entries;
10780 * Number of TQM ring 3 entries.
10782 * TQM fastpath rings should be sized large enough to accommodate the
10783 * maximum number of QPs (either L2 or RoCE, or both if shared)
10784 * that can be enqueued to the TQM ring.
10786 * Note that TQM ring sizes cannot be extended while the system is
10787 * operational. If a PF driver needs to extend a TQM ring, it needs
10788 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10789 * the backing store.
10791 uint32_t tqm_ring3_num_entries;
10793 * Number of TQM ring 4 entries.
10795 * TQM fastpath rings should be sized large enough to accommodate the
10796 * maximum number of QPs (either L2 or RoCE, or both if shared)
10797 * that can be enqueued to the TQM ring.
10799 * Note that TQM ring sizes cannot be extended while the system is
10800 * operational. If a PF driver needs to extend a TQM ring, it needs
10801 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10802 * the backing store.
10804 uint32_t tqm_ring4_num_entries;
10806 * Number of TQM ring 5 entries.
10808 * TQM fastpath rings should be sized large enough to accommodate the
10809 * maximum number of QPs (either L2 or RoCE, or both if shared)
10810 * that can be enqueued to the TQM ring.
10812 * Note that TQM ring sizes cannot be extended while the system is
10813 * operational. If a PF driver needs to extend a TQM ring, it needs
10814 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10815 * the backing store.
10817 uint32_t tqm_ring5_num_entries;
10819 * Number of TQM ring 6 entries.
10821 * TQM fastpath rings should be sized large enough to accommodate the
10822 * maximum number of QPs (either L2 or RoCE, or both if shared)
10823 * that can be enqueued to the TQM ring.
10825 * Note that TQM ring sizes cannot be extended while the system is
10826 * operational. If a PF driver needs to extend a TQM ring, it needs
10827 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10828 * the backing store.
10830 uint32_t tqm_ring6_num_entries;
10832 * Number of TQM ring 7 entries.
10834 * TQM fastpath rings should be sized large enough to accommodate the
10835 * maximum number of QPs (either L2 or RoCE, or both if shared)
10836 * that can be enqueued to the TQM ring.
10838 * Note that TQM ring sizes cannot be extended while the system is
10839 * operational. If a PF driver needs to extend a TQM ring, it needs
10840 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
10841 * the backing store.
10843 uint32_t tqm_ring7_num_entries;
10845 * If the MR/AV split reservation flag is not set, then this field
10846 * represents the total number of MR plus AV entries. For versions
10847 * of firmware that support the split reservation, when it is not
10848 * specified half of the entries will be reserved for MRs and the
10849 * other half for AVs.
10851 * If the MR/AV split reservation flag is set, then this
10852 * field is logically divided into two 16b fields. Bits `[31:16]`
10853 * represents the `mr_num_entries` and bits `[15:0]` represents
10854 * `av_num_entries`. The granularity of these values is defined by
10855 * the `mrav_num_entries_unit` field returned by the
10856 * `backing_store_qcaps` command.
10858 uint32_t mrav_num_entries;
10859 /* Number of Timer entries. */
10860 uint32_t tim_num_entries;
10861 /* Number of entries to reserve for QP1 */
10862 uint16_t qp_num_qp1_entries;
10863 /* Number of entries to reserve for L2 */
10864 uint16_t qp_num_l2_entries;
10865 /* Number of bytes that have been allocated for each context entry. */
10866 uint16_t qp_entry_size;
10867 /* Number of entries to reserve for L2 */
10868 uint16_t srq_num_l2_entries;
10869 /* Number of bytes that have been allocated for each context entry. */
10870 uint16_t srq_entry_size;
10871 /* Number of entries to reserve for L2 */
10872 uint16_t cq_num_l2_entries;
10873 /* Number of bytes that have been allocated for each context entry. */
10874 uint16_t cq_entry_size;
10875 /* Number of entries to reserve for VNIC entries */
10876 uint16_t vnic_num_vnic_entries;
10877 /* Number of entries to reserve for Ring table entries */
10878 uint16_t vnic_num_ring_table_entries;
10879 /* Number of bytes that have been allocated for each context entry. */
10880 uint16_t vnic_entry_size;
10881 /* Number of bytes that have been allocated for each context entry. */
10882 uint16_t stat_entry_size;
10883 /* Number of bytes that have been allocated for each context entry. */
10884 uint16_t tqm_entry_size;
10885 /* Number of bytes that have been allocated for each context entry. */
10886 uint16_t mrav_entry_size;
10887 /* Number of bytes that have been allocated for each context entry. */
10888 uint16_t tim_entry_size;
10891 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
10892 struct hwrm_func_backing_store_cfg_output {
10893 /* The specific error status for the command. */
10894 uint16_t error_code;
10895 /* The HWRM command request type. */
10897 /* The sequence ID from the original command. */
10899 /* The length of the response data in number of bytes. */
10901 uint8_t unused_0[7];
10903 * This field is used in Output records to indicate that the output
10904 * is completely written to RAM. This field should be read as '1'
10905 * to indicate that the output has been completely written.
10906 * When writing a command completion or response to an internal processor,
10907 * the order of writes has to be such that this field is written last.
10912 /********************************
10913 * hwrm_func_backing_store_qcfg *
10914 ********************************/
10917 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
10918 struct hwrm_func_backing_store_qcfg_input {
10919 /* The HWRM command request type. */
10922 * The completion ring to send the completion event on. This should
10923 * be the NQ ID returned from the `nq_alloc` HWRM command.
10925 uint16_t cmpl_ring;
10927 * The sequence ID is used by the driver for tracking multiple
10928 * commands. This ID is treated as opaque data by the firmware and
10929 * the value is returned in the `hwrm_resp_hdr` upon completion.
10933 * The target ID of the command:
10934 * * 0x0-0xFFF8 - The function ID
10935 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10936 * * 0xFFFD - Reserved for user-space HWRM interface
10939 uint16_t target_id;
10941 * A physical address pointer pointing to a host buffer that the
10942 * command's response data will be written. This can be either a host
10943 * physical address (HPA) or a guest physical address (GPA) and must
10944 * point to a physically contiguous block of memory.
10946 uint64_t resp_addr;
10949 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
10950 struct hwrm_func_backing_store_qcfg_output {
10951 /* The specific error status for the command. */
10952 uint16_t error_code;
10953 /* The HWRM command request type. */
10955 /* The sequence ID from the original command. */
10957 /* The length of the response data in number of bytes. */
10961 * When set, the firmware only uses on-chip resources and does not
10962 * expect any backing store to be provided by the host driver. This
10963 * mode provides minimal L2 functionality (e.g. limited L2 resources,
10966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
10969 * When set, the 32b `mrav_num_entries` field is logically divided
10970 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
10972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
10974 uint8_t unused_0[4];
10976 * This bit must be '1' for the qp fields to be
10979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
10982 * This bit must be '1' for the srq fields to be
10985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
10988 * This bit must be '1' for the cq fields to be
10991 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
10994 * This bit must be '1' for the vnic fields to be
10997 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
11000 * This bit must be '1' for the stat fields to be
11003 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
11006 * This bit must be '1' for the tqm_sp fields to be
11009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
11012 * This bit must be '1' for the tqm_ring0 fields to be
11015 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
11018 * This bit must be '1' for the tqm_ring1 fields to be
11021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
11024 * This bit must be '1' for the tqm_ring2 fields to be
11027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
11030 * This bit must be '1' for the tqm_ring3 fields to be
11033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
11036 * This bit must be '1' for the tqm_ring4 fields to be
11039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
11042 * This bit must be '1' for the tqm_ring5 fields to be
11045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
11048 * This bit must be '1' for the tqm_ring6 fields to be
11051 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
11054 * This bit must be '1' for the tqm_ring7 fields to be
11057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
11060 * This bit must be '1' for the mrav fields to be
11063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
11066 * This bit must be '1' for the tim fields to be
11069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
11071 /* QPC page size and level. */
11072 uint8_t qpc_pg_size_qpc_lvl;
11073 /* QPC PBL indirect levels. */
11074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
11076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
11077 /* PBL pointer is physical start address. */
11078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
11080 /* PBL pointer points to PTE table. */
11081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
11083 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
11086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
11087 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
11088 /* QPC page size. */
11089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
11091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
11093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
11094 (UINT32_C(0x0) << 4)
11096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
11097 (UINT32_C(0x1) << 4)
11099 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
11100 (UINT32_C(0x2) << 4)
11102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
11103 (UINT32_C(0x3) << 4)
11105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
11106 (UINT32_C(0x4) << 4)
11108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
11109 (UINT32_C(0x5) << 4)
11110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
11111 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
11112 /* SRQ page size and level. */
11113 uint8_t srq_pg_size_srq_lvl;
11114 /* SRQ PBL indirect levels. */
11115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
11117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
11118 /* PBL pointer is physical start address. */
11119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
11121 /* PBL pointer points to PTE table. */
11122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
11124 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
11127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
11128 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
11129 /* SRQ page size. */
11130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
11132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
11134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
11135 (UINT32_C(0x0) << 4)
11137 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
11138 (UINT32_C(0x1) << 4)
11140 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
11141 (UINT32_C(0x2) << 4)
11143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
11144 (UINT32_C(0x3) << 4)
11146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
11147 (UINT32_C(0x4) << 4)
11149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
11150 (UINT32_C(0x5) << 4)
11151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
11152 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
11153 /* CQ page size and level. */
11154 uint8_t cq_pg_size_cq_lvl;
11155 /* CQ PBL indirect levels. */
11156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
11158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
11159 /* PBL pointer is physical start address. */
11160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
11162 /* PBL pointer points to PTE table. */
11163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
11165 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
11168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
11169 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
11170 /* CQ page size. */
11171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
11173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
11175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
11176 (UINT32_C(0x0) << 4)
11178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
11179 (UINT32_C(0x1) << 4)
11181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
11182 (UINT32_C(0x2) << 4)
11184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
11185 (UINT32_C(0x3) << 4)
11187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
11188 (UINT32_C(0x4) << 4)
11190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
11191 (UINT32_C(0x5) << 4)
11192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
11193 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
11194 /* VNIC page size and level. */
11195 uint8_t vnic_pg_size_vnic_lvl;
11196 /* VNIC PBL indirect levels. */
11197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
11199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
11200 /* PBL pointer is physical start address. */
11201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
11203 /* PBL pointer points to PTE table. */
11204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
11206 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
11209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
11210 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
11211 /* VNIC page size. */
11212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
11214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
11216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
11217 (UINT32_C(0x0) << 4)
11219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
11220 (UINT32_C(0x1) << 4)
11222 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
11223 (UINT32_C(0x2) << 4)
11225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
11226 (UINT32_C(0x3) << 4)
11228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
11229 (UINT32_C(0x4) << 4)
11231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
11232 (UINT32_C(0x5) << 4)
11233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
11234 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
11235 /* Stat page size and level. */
11236 uint8_t stat_pg_size_stat_lvl;
11237 /* Stat PBL indirect levels. */
11238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
11240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
11241 /* PBL pointer is physical start address. */
11242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
11244 /* PBL pointer points to PTE table. */
11245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
11247 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
11250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
11251 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
11252 /* Stat page size. */
11253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
11255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
11257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
11258 (UINT32_C(0x0) << 4)
11260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
11261 (UINT32_C(0x1) << 4)
11263 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
11264 (UINT32_C(0x2) << 4)
11266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
11267 (UINT32_C(0x3) << 4)
11269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
11270 (UINT32_C(0x4) << 4)
11272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
11273 (UINT32_C(0x5) << 4)
11274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
11275 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
11276 /* TQM slow path page size and level. */
11277 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
11278 /* TQM slow path PBL indirect levels. */
11279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
11281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
11282 /* PBL pointer is physical start address. */
11283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
11285 /* PBL pointer points to PTE table. */
11286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
11288 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
11291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
11292 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
11293 /* TQM slow path page size. */
11294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
11296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
11298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
11299 (UINT32_C(0x0) << 4)
11301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
11302 (UINT32_C(0x1) << 4)
11304 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
11305 (UINT32_C(0x2) << 4)
11307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
11308 (UINT32_C(0x3) << 4)
11310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
11311 (UINT32_C(0x4) << 4)
11313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
11314 (UINT32_C(0x5) << 4)
11315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
11316 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
11317 /* TQM ring 0 page size and level. */
11318 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
11319 /* TQM ring 0 PBL indirect levels. */
11320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
11322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
11323 /* PBL pointer is physical start address. */
11324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
11326 /* PBL pointer points to PTE table. */
11327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
11329 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
11332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
11333 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
11334 /* TQM ring 0 page size. */
11335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
11337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
11339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
11340 (UINT32_C(0x0) << 4)
11342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
11343 (UINT32_C(0x1) << 4)
11345 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
11346 (UINT32_C(0x2) << 4)
11348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
11349 (UINT32_C(0x3) << 4)
11351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
11352 (UINT32_C(0x4) << 4)
11354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
11355 (UINT32_C(0x5) << 4)
11356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
11357 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
11358 /* TQM ring 1 page size and level. */
11359 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
11360 /* TQM ring 1 PBL indirect levels. */
11361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
11363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
11364 /* PBL pointer is physical start address. */
11365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
11367 /* PBL pointer points to PTE table. */
11368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
11370 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
11373 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
11374 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
11375 /* TQM ring 1 page size. */
11376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
11378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
11380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
11381 (UINT32_C(0x0) << 4)
11383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
11384 (UINT32_C(0x1) << 4)
11386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
11387 (UINT32_C(0x2) << 4)
11389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
11390 (UINT32_C(0x3) << 4)
11392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
11393 (UINT32_C(0x4) << 4)
11395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
11396 (UINT32_C(0x5) << 4)
11397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
11398 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
11399 /* TQM ring 2 page size and level. */
11400 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
11401 /* TQM ring 2 PBL indirect levels. */
11402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
11404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
11405 /* PBL pointer is physical start address. */
11406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
11408 /* PBL pointer points to PTE table. */
11409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
11411 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
11414 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
11415 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
11416 /* TQM ring 2 page size. */
11417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
11419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
11421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
11422 (UINT32_C(0x0) << 4)
11424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
11425 (UINT32_C(0x1) << 4)
11427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
11428 (UINT32_C(0x2) << 4)
11430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
11431 (UINT32_C(0x3) << 4)
11433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
11434 (UINT32_C(0x4) << 4)
11436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
11437 (UINT32_C(0x5) << 4)
11438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
11439 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
11440 /* TQM ring 3 page size and level. */
11441 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
11442 /* TQM ring 3 PBL indirect levels. */
11443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
11445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
11446 /* PBL pointer is physical start address. */
11447 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
11449 /* PBL pointer points to PTE table. */
11450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
11452 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
11455 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
11456 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
11457 /* TQM ring 3 page size. */
11458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
11460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
11462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
11463 (UINT32_C(0x0) << 4)
11465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
11466 (UINT32_C(0x1) << 4)
11468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
11469 (UINT32_C(0x2) << 4)
11471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
11472 (UINT32_C(0x3) << 4)
11474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
11475 (UINT32_C(0x4) << 4)
11477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
11478 (UINT32_C(0x5) << 4)
11479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
11480 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
11481 /* TQM ring 4 page size and level. */
11482 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
11483 /* TQM ring 4 PBL indirect levels. */
11484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
11486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
11487 /* PBL pointer is physical start address. */
11488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
11490 /* PBL pointer points to PTE table. */
11491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
11493 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
11496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
11497 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
11498 /* TQM ring 4 page size. */
11499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
11501 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
11503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
11504 (UINT32_C(0x0) << 4)
11506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
11507 (UINT32_C(0x1) << 4)
11509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
11510 (UINT32_C(0x2) << 4)
11512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
11513 (UINT32_C(0x3) << 4)
11515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
11516 (UINT32_C(0x4) << 4)
11518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
11519 (UINT32_C(0x5) << 4)
11520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
11521 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
11522 /* TQM ring 5 page size and level. */
11523 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
11524 /* TQM ring 5 PBL indirect levels. */
11525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
11527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
11528 /* PBL pointer is physical start address. */
11529 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
11531 /* PBL pointer points to PTE table. */
11532 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
11534 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
11537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
11538 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
11539 /* TQM ring 5 page size. */
11540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
11542 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
11544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
11545 (UINT32_C(0x0) << 4)
11547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
11548 (UINT32_C(0x1) << 4)
11550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
11551 (UINT32_C(0x2) << 4)
11553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
11554 (UINT32_C(0x3) << 4)
11556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
11557 (UINT32_C(0x4) << 4)
11559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
11560 (UINT32_C(0x5) << 4)
11561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
11562 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
11563 /* TQM ring 6 page size and level. */
11564 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
11565 /* TQM ring 6 PBL indirect levels. */
11566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
11568 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
11569 /* PBL pointer is physical start address. */
11570 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
11572 /* PBL pointer points to PTE table. */
11573 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
11575 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
11578 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
11579 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
11580 /* TQM ring 6 page size. */
11581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
11583 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
11585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
11586 (UINT32_C(0x0) << 4)
11588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
11589 (UINT32_C(0x1) << 4)
11591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
11592 (UINT32_C(0x2) << 4)
11594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
11595 (UINT32_C(0x3) << 4)
11597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
11598 (UINT32_C(0x4) << 4)
11600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
11601 (UINT32_C(0x5) << 4)
11602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
11603 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
11604 /* TQM ring 7 page size and level. */
11605 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
11606 /* TQM ring 7 PBL indirect levels. */
11607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
11609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
11610 /* PBL pointer is physical start address. */
11611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
11613 /* PBL pointer points to PTE table. */
11614 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
11616 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
11619 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
11620 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
11621 /* TQM ring 7 page size. */
11622 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
11624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
11626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
11627 (UINT32_C(0x0) << 4)
11629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
11630 (UINT32_C(0x1) << 4)
11632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
11633 (UINT32_C(0x2) << 4)
11635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
11636 (UINT32_C(0x3) << 4)
11638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
11639 (UINT32_C(0x4) << 4)
11641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
11642 (UINT32_C(0x5) << 4)
11643 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
11644 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
11645 /* MR/AV page size and level. */
11646 uint8_t mrav_pg_size_mrav_lvl;
11647 /* MR/AV PBL indirect levels. */
11648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
11650 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
11651 /* PBL pointer is physical start address. */
11652 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
11654 /* PBL pointer points to PTE table. */
11655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
11657 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
11660 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
11661 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
11662 /* MR/AV page size. */
11663 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
11665 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
11667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
11668 (UINT32_C(0x0) << 4)
11670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
11671 (UINT32_C(0x1) << 4)
11673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
11674 (UINT32_C(0x2) << 4)
11676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
11677 (UINT32_C(0x3) << 4)
11679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
11680 (UINT32_C(0x4) << 4)
11682 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
11683 (UINT32_C(0x5) << 4)
11684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
11685 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
11686 /* Timer page size and level. */
11687 uint8_t tim_pg_size_tim_lvl;
11688 /* Timer PBL indirect levels. */
11689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
11691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
11692 /* PBL pointer is physical start address. */
11693 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
11695 /* PBL pointer points to PTE table. */
11696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
11698 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
11699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
11701 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
11702 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
11703 /* Timer page size. */
11704 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
11706 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
11708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
11709 (UINT32_C(0x0) << 4)
11711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
11712 (UINT32_C(0x1) << 4)
11714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
11715 (UINT32_C(0x2) << 4)
11717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
11718 (UINT32_C(0x3) << 4)
11720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
11721 (UINT32_C(0x4) << 4)
11723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
11724 (UINT32_C(0x5) << 4)
11725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
11726 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
11727 /* QP page directory. */
11728 uint64_t qpc_page_dir;
11729 /* SRQ page directory. */
11730 uint64_t srq_page_dir;
11731 /* CQ page directory. */
11732 uint64_t cq_page_dir;
11733 /* VNIC page directory. */
11734 uint64_t vnic_page_dir;
11735 /* Stat page directory. */
11736 uint64_t stat_page_dir;
11737 /* TQM slowpath page directory. */
11738 uint64_t tqm_sp_page_dir;
11739 /* TQM ring 0 page directory. */
11740 uint64_t tqm_ring0_page_dir;
11741 /* TQM ring 1 page directory. */
11742 uint64_t tqm_ring1_page_dir;
11743 /* TQM ring 2 page directory. */
11744 uint64_t tqm_ring2_page_dir;
11745 /* TQM ring 3 page directory. */
11746 uint64_t tqm_ring3_page_dir;
11747 /* TQM ring 4 page directory. */
11748 uint64_t tqm_ring4_page_dir;
11749 /* TQM ring 5 page directory. */
11750 uint64_t tqm_ring5_page_dir;
11751 /* TQM ring 6 page directory. */
11752 uint64_t tqm_ring6_page_dir;
11753 /* TQM ring 7 page directory. */
11754 uint64_t tqm_ring7_page_dir;
11755 /* MR/AV page directory. */
11756 uint64_t mrav_page_dir;
11757 /* Timer page directory. */
11758 uint64_t tim_page_dir;
11759 /* Number of entries to reserve for QP1 */
11760 uint16_t qp_num_qp1_entries;
11761 /* Number of entries to reserve for L2 */
11762 uint16_t qp_num_l2_entries;
11763 /* Number of QPs. */
11764 uint32_t qp_num_entries;
11765 /* Number of SRQs. */
11766 uint32_t srq_num_entries;
11767 /* Number of entries to reserve for L2 */
11768 uint16_t srq_num_l2_entries;
11769 /* Number of entries to reserve for L2 */
11770 uint16_t cq_num_l2_entries;
11771 /* Number of CQs. */
11772 uint32_t cq_num_entries;
11773 /* Number of entries to reserve for VNIC entries */
11774 uint16_t vnic_num_vnic_entries;
11775 /* Number of entries to reserve for Ring table entries */
11776 uint16_t vnic_num_ring_table_entries;
11777 /* Number of Stats. */
11778 uint32_t stat_num_entries;
11779 /* Number of TQM slowpath entries. */
11780 uint32_t tqm_sp_num_entries;
11781 /* Number of TQM ring 0 entries. */
11782 uint32_t tqm_ring0_num_entries;
11783 /* Number of TQM ring 1 entries. */
11784 uint32_t tqm_ring1_num_entries;
11785 /* Number of TQM ring 2 entries. */
11786 uint32_t tqm_ring2_num_entries;
11787 /* Number of TQM ring 3 entries. */
11788 uint32_t tqm_ring3_num_entries;
11789 /* Number of TQM ring 4 entries. */
11790 uint32_t tqm_ring4_num_entries;
11791 /* Number of TQM ring 5 entries. */
11792 uint32_t tqm_ring5_num_entries;
11793 /* Number of TQM ring 6 entries. */
11794 uint32_t tqm_ring6_num_entries;
11795 /* Number of TQM ring 7 entries. */
11796 uint32_t tqm_ring7_num_entries;
11798 * If the MR/AV split reservation flag is not set, then this field
11799 * represents the total number of MR plus AV entries. For versions
11800 * of firmware that support the split reservation, when it is not
11801 * specified half of the entries will be reserved for MRs and the
11802 * other half for AVs.
11804 * If the MR/AV split reservation flag is set, then this
11805 * field is logically divided into two 16b fields. Bits `[31:16]`
11806 * represents the `mr_num_entries` and bits `[15:0]` represents
11807 * `av_num_entries`. The granularity of these values is defined by
11808 * the `mrav_num_entries_unit` field returned by the
11809 * `backing_store_qcaps` command.
11811 uint32_t mrav_num_entries;
11812 /* Number of Timer entries. */
11813 uint32_t tim_num_entries;
11814 uint8_t unused_1[7];
11816 * This field is used in Output records to indicate that the output
11817 * is completely written to RAM. This field should be read as 1
11818 * to indicate that the output has been completely written.
11819 * When writing a command completion or response to an internal
11820 * processor, the order of writes has to be such that this field
11826 /****************************
11827 * hwrm_error_recovery_qcfg *
11828 ****************************/
11831 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
11832 struct hwrm_error_recovery_qcfg_input {
11833 /* The HWRM command request type. */
11836 * The completion ring to send the completion event on. This should
11837 * be the NQ ID returned from the `nq_alloc` HWRM command.
11839 uint16_t cmpl_ring;
11841 * The sequence ID is used by the driver for tracking multiple
11842 * commands. This ID is treated as opaque data by the firmware and
11843 * the value is returned in the `hwrm_resp_hdr` upon completion.
11847 * The target ID of the command:
11848 * * 0x0-0xFFF8 - The function ID
11849 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11850 * * 0xFFFD - Reserved for user-space HWRM interface
11853 uint16_t target_id;
11855 * A physical address pointer pointing to a host buffer that the
11856 * command's response data will be written. This can be either a host
11857 * physical address (HPA) or a guest physical address (GPA) and must
11858 * point to a physically contiguous block of memory.
11860 uint64_t resp_addr;
11861 uint8_t unused_0[8];
11864 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
11865 struct hwrm_error_recovery_qcfg_output {
11866 /* The specific error status for the command. */
11867 uint16_t error_code;
11868 /* The HWRM command request type. */
11870 /* The sequence ID from the original command. */
11872 /* The length of the response data in number of bytes. */
11876 * When this flag is set to 1, error recovery will be initiated
11877 * through master function driver.
11879 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
11881 * When this flag is set to 1, error recovery will be performed
11882 * through Co processor.
11884 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
11886 * Driver Polling frequency. This value is in units of 100msec.
11887 * Typical value would be 10 to indicate 1sec.
11888 * Drivers can poll FW health status, Heartbeat, reset_counter with
11891 uint32_t driver_polling_freq;
11893 * This value is in units of 100msec.
11894 * Typical value would be 30 to indicate 3sec.
11895 * Master function wait period from detecting a fatal error to
11896 * initiating reset. In this time period Master PF expects every
11897 * active driver will detect fatal error.
11899 uint32_t master_func_wait_period;
11901 * This value is in units of 100msec.
11902 * Typical value would be 50 to indicate 5sec.
11903 * Normal function wait period from fatal error detection to
11904 * polling FW health status. In this time period, drivers should not
11905 * do any PCIe MMIO transaction and should not send any HWRM commands.
11907 uint32_t normal_func_wait_period;
11909 * This value is in units of 100msec.
11910 * Typical value would be 20 to indicate 2sec.
11911 * This field indicates that, master function wait period after chip
11912 * reset. After this time, master function should reinitialize with
11915 uint32_t master_func_wait_period_after_reset;
11917 * This value is in units of 100msec.
11918 * Typical value would be 60 to indicate 6sec.
11919 * This field is applicable to both master and normal functions.
11920 * Even after chip reset, if FW status not changed to ready,
11921 * then all the functions can poll for this much time and bailout.
11923 uint32_t max_bailout_time_after_reset;
11925 * FW health status register.
11926 * Lower 2 bits indicates address space location and upper 30 bits
11927 * indicates upper 30bits of the register address.
11928 * A value of 0xFFFF-FFFF indicates this register does not exist.
11930 uint32_t fw_health_status_reg;
11931 /* Lower 2 bits indicates address space location. */
11932 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
11934 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
11937 * If value is 0, this register is located in PCIe config space.
11938 * Drivers have to map appropriate window to access this
11941 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
11944 * If value is 1, this register is located in GRC address space.
11945 * Drivers have to map appropriate window to access this
11948 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
11951 * If value is 2, this register is located in first BAR address
11952 * space. Drivers have to map appropriate window to access this
11955 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
11958 * If value is 3, this register is located in second BAR address
11959 * space. Drivers have to map appropriate window to access this
11960 * Drivers have to map appropriate window to access this
11963 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
11965 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
11966 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
11967 /* Upper 30bits of the register address. */
11968 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
11969 UINT32_C(0xfffffffc)
11970 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
11973 * FW HeartBeat register.
11974 * Lower 2 bits indicates address space location and upper 30 bits
11975 * indicates actual address.
11976 * A value of 0xFFFF-FFFF indicates this register does not exist.
11978 uint32_t fw_heartbeat_reg;
11979 /* Lower 2 bits indicates address space location. */
11980 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
11982 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
11985 * If value is 0, this register is located in PCIe config space.
11986 * Drivers have to map appropriate window to access this
11989 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
11992 * If value is 1, this register is located in GRC address space.
11993 * Drivers have to map appropriate window to access this
11996 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
11999 * If value is 2, this register is located in first BAR address
12000 * space. Drivers have to map appropriate window to access this
12003 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
12006 * If value is 3, this register is located in second BAR address
12007 * space. Drivers have to map appropriate window to access this
12010 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
12012 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
12013 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
12014 /* Upper 30bits of the register address. */
12015 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
12016 UINT32_C(0xfffffffc)
12017 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
12020 * FW reset counter.
12021 * Lower 2 bits indicates address space location and upper 30 bits
12022 * indicates actual address.
12023 * A value of 0xFFFF-FFFF indicates this register does not exist.
12025 uint32_t fw_reset_cnt_reg;
12026 /* Lower 2 bits indicates address space location. */
12027 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
12029 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
12032 * If value is 0, this register is located in PCIe config space.
12033 * Drivers have to map appropriate window to access this
12036 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
12039 * If value is 1, this register is located in GRC address space.
12040 * Drivers have to map appropriate window to access this
12043 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
12046 * If value is 2, this register is located in first BAR address
12047 * space. Drivers have to map appropriate window to access this
12050 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
12053 * If value is 3, this register is located in second BAR address
12054 * space. Drivers have to map appropriate window to access this
12057 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
12059 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
12060 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
12061 /* Upper 30bits of the register address. */
12062 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
12063 UINT32_C(0xfffffffc)
12064 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
12067 * Reset Inprogress Register address for PFs.
12068 * Lower 2 bits indicates address space location and upper 30 bits
12069 * indicates actual address.
12070 * A value of 0xFFFF-FFFF indicates this register does not exist.
12072 uint32_t reset_inprogress_reg;
12073 /* Lower 2 bits indicates address space location. */
12074 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
12076 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
12079 * If value is 0, this register is located in PCIe config space.
12080 * Drivers have to map appropriate window to access this
12083 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
12086 * If value is 1, this register is located in GRC address space.
12087 * Drivers have to map appropriate window to access this
12090 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
12093 * If value is 2, this register is located in first BAR address
12094 * space. Drivers have to map appropriate window to access this
12097 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
12100 * If value is 3, this register is located in second BAR address
12101 * space. Drivers have to map appropriate window to access this
12104 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
12106 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
12107 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
12108 /* Upper 30bits of the register address. */
12109 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
12110 UINT32_C(0xfffffffc)
12111 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
12113 /* This field indicates the mask value for reset_inprogress_reg. */
12114 uint32_t reset_inprogress_reg_mask;
12115 uint8_t unused_0[3];
12117 * Array of registers and value count to reset the Chip
12118 * Each array count has reset_reg, reset_reg_val, delay_after_reset
12119 * in TLV format. Depending upon Chip type, number of reset registers
12120 * will vary. Drivers have to write reset_reg_val in the reset_reg
12121 * location in the same sequence in order to recover from a fatal
12124 uint8_t reg_array_cnt;
12127 * Lower 2 bits indicates address space location and upper 30 bits
12128 * indicates actual address.
12129 * A value of 0xFFFF-FFFF indicates this register does not exist.
12131 uint32_t reset_reg[16];
12132 /* Lower 2 bits indicates address space location. */
12133 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
12135 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
12137 * If value is 0, this register is located in PCIe config space.
12138 * Drivers have to map appropriate window to access this
12141 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
12144 * If value is 1, this register is located in GRC address space.
12145 * Drivers have to map appropriate window to access this
12148 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
12151 * If value is 2, this register is located in first BAR address
12152 * space. Drivers have to map appropriate window to access this
12155 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
12158 * If value is 3, this register is located in second BAR address
12159 * space. Drivers have to map appropriate window to access this
12162 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
12164 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
12165 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
12166 /* Upper 30bits of the register address. */
12167 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
12168 UINT32_C(0xfffffffc)
12169 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
12170 /* Value to be written in reset_reg to reset the controller. */
12171 uint32_t reset_reg_val[16];
12173 * This value is in units of 1msec.
12174 * Typical value would be 10 to indicate 10msec.
12175 * Some of the operations like Core reset require delay before
12176 * accessing PCIE MMIO register space.
12177 * If this value is non-zero, drivers have to wait for
12178 * this much time after writing reset_reg_val in reset_reg.
12180 uint8_t delay_after_reset[16];
12181 uint8_t unused_1[7];
12183 * This field is used in Output records to indicate that the output
12184 * is completely written to RAM. This field should be read as '1'
12185 * to indicate that the output has been completely written.
12186 * When writing a command completion or response to an internal
12187 * processor, the order of writes has to be such that this field
12193 /***********************
12194 * hwrm_func_vlan_qcfg *
12195 ***********************/
12198 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
12199 struct hwrm_func_vlan_qcfg_input {
12200 /* The HWRM command request type. */
12203 * The completion ring to send the completion event on. This should
12204 * be the NQ ID returned from the `nq_alloc` HWRM command.
12206 uint16_t cmpl_ring;
12208 * The sequence ID is used by the driver for tracking multiple
12209 * commands. This ID is treated as opaque data by the firmware and
12210 * the value is returned in the `hwrm_resp_hdr` upon completion.
12214 * The target ID of the command:
12215 * * 0x0-0xFFF8 - The function ID
12216 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12217 * * 0xFFFD - Reserved for user-space HWRM interface
12220 uint16_t target_id;
12222 * A physical address pointer pointing to a host buffer that the
12223 * command's response data will be written. This can be either a host
12224 * physical address (HPA) or a guest physical address (GPA) and must
12225 * point to a physically contiguous block of memory.
12227 uint64_t resp_addr;
12229 * Function ID of the function that is being
12231 * If set to 0xFF... (All Fs), then the configuration is
12232 * for the requesting function.
12235 uint8_t unused_0[6];
12238 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
12239 struct hwrm_func_vlan_qcfg_output {
12240 /* The specific error status for the command. */
12241 uint16_t error_code;
12242 /* The HWRM command request type. */
12244 /* The sequence ID from the original command. */
12246 /* The length of the response data in number of bytes. */
12249 /* S-TAG VLAN identifier configured for the function. */
12251 /* S-TAG PCP value configured for the function. */
12255 * S-TAG TPID value configured for the function. This field is specified in
12256 * network byte order.
12258 uint16_t stag_tpid;
12259 /* C-TAG VLAN identifier configured for the function. */
12261 /* C-TAG PCP value configured for the function. */
12265 * C-TAG TPID value configured for the function. This field is specified in
12266 * network byte order.
12268 uint16_t ctag_tpid;
12273 uint8_t unused_3[3];
12275 * This field is used in Output records to indicate that the output
12276 * is completely written to RAM. This field should be read as '1'
12277 * to indicate that the output has been completely written.
12278 * When writing a command completion or response to an internal processor,
12279 * the order of writes has to be such that this field is written last.
12284 /**********************
12285 * hwrm_func_vlan_cfg *
12286 **********************/
12289 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
12290 struct hwrm_func_vlan_cfg_input {
12291 /* The HWRM command request type. */
12294 * The completion ring to send the completion event on. This should
12295 * be the NQ ID returned from the `nq_alloc` HWRM command.
12297 uint16_t cmpl_ring;
12299 * The sequence ID is used by the driver for tracking multiple
12300 * commands. This ID is treated as opaque data by the firmware and
12301 * the value is returned in the `hwrm_resp_hdr` upon completion.
12305 * The target ID of the command:
12306 * * 0x0-0xFFF8 - The function ID
12307 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12308 * * 0xFFFD - Reserved for user-space HWRM interface
12311 uint16_t target_id;
12313 * A physical address pointer pointing to a host buffer that the
12314 * command's response data will be written. This can be either a host
12315 * physical address (HPA) or a guest physical address (GPA) and must
12316 * point to a physically contiguous block of memory.
12318 uint64_t resp_addr;
12320 * Function ID of the function that is being
12322 * If set to 0xFF... (All Fs), then the configuration is
12323 * for the requesting function.
12326 uint8_t unused_0[2];
12329 * This bit must be '1' for the stag_vid field to be
12332 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
12334 * This bit must be '1' for the ctag_vid field to be
12337 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
12339 * This bit must be '1' for the stag_pcp field to be
12342 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
12344 * This bit must be '1' for the ctag_pcp field to be
12347 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
12349 * This bit must be '1' for the stag_tpid field to be
12352 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
12354 * This bit must be '1' for the ctag_tpid field to be
12357 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
12358 /* S-TAG VLAN identifier configured for the function. */
12360 /* S-TAG PCP value configured for the function. */
12364 * S-TAG TPID value configured for the function. This field is specified in
12365 * network byte order.
12367 uint16_t stag_tpid;
12368 /* C-TAG VLAN identifier configured for the function. */
12370 /* C-TAG PCP value configured for the function. */
12374 * C-TAG TPID value configured for the function. This field is specified in
12375 * network byte order.
12377 uint16_t ctag_tpid;
12382 uint8_t unused_3[4];
12385 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
12386 struct hwrm_func_vlan_cfg_output {
12387 /* The specific error status for the command. */
12388 uint16_t error_code;
12389 /* The HWRM command request type. */
12391 /* The sequence ID from the original command. */
12393 /* The length of the response data in number of bytes. */
12395 uint8_t unused_0[7];
12397 * This field is used in Output records to indicate that the output
12398 * is completely written to RAM. This field should be read as '1'
12399 * to indicate that the output has been completely written.
12400 * When writing a command completion or response to an internal processor,
12401 * the order of writes has to be such that this field is written last.
12406 /*******************************
12407 * hwrm_func_vf_vnic_ids_query *
12408 *******************************/
12411 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
12412 struct hwrm_func_vf_vnic_ids_query_input {
12413 /* The HWRM command request type. */
12416 * The completion ring to send the completion event on. This should
12417 * be the NQ ID returned from the `nq_alloc` HWRM command.
12419 uint16_t cmpl_ring;
12421 * The sequence ID is used by the driver for tracking multiple
12422 * commands. This ID is treated as opaque data by the firmware and
12423 * the value is returned in the `hwrm_resp_hdr` upon completion.
12427 * The target ID of the command:
12428 * * 0x0-0xFFF8 - The function ID
12429 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12430 * * 0xFFFD - Reserved for user-space HWRM interface
12433 uint16_t target_id;
12435 * A physical address pointer pointing to a host buffer that the
12436 * command's response data will be written. This can be either a host
12437 * physical address (HPA) or a guest physical address (GPA) and must
12438 * point to a physically contiguous block of memory.
12440 uint64_t resp_addr;
12442 * This value is used to identify a Virtual Function (VF).
12443 * The scope of VF ID is local within a PF.
12446 uint8_t unused_0[2];
12447 /* Max number of vnic ids in vnic id table */
12448 uint32_t max_vnic_id_cnt;
12449 /* This is the address for VF VNIC ID table */
12450 uint64_t vnic_id_tbl_addr;
12453 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
12454 struct hwrm_func_vf_vnic_ids_query_output {
12455 /* The specific error status for the command. */
12456 uint16_t error_code;
12457 /* The HWRM command request type. */
12459 /* The sequence ID from the original command. */
12461 /* The length of the response data in number of bytes. */
12464 * Actual number of vnic ids
12466 * Each VNIC ID is written as a 32-bit number.
12468 uint32_t vnic_id_cnt;
12469 uint8_t unused_0[3];
12471 * This field is used in Output records to indicate that the output
12472 * is completely written to RAM. This field should be read as '1'
12473 * to indicate that the output has been completely written.
12474 * When writing a command completion or response to an internal processor,
12475 * the order of writes has to be such that this field is written last.
12480 /***********************
12481 * hwrm_func_vf_bw_cfg *
12482 ***********************/
12485 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
12486 struct hwrm_func_vf_bw_cfg_input {
12487 /* The HWRM command request type. */
12490 * The completion ring to send the completion event on. This should
12491 * be the NQ ID returned from the `nq_alloc` HWRM command.
12493 uint16_t cmpl_ring;
12495 * The sequence ID is used by the driver for tracking multiple
12496 * commands. This ID is treated as opaque data by the firmware and
12497 * the value is returned in the `hwrm_resp_hdr` upon completion.
12501 * The target ID of the command:
12502 * * 0x0-0xFFF8 - The function ID
12503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12504 * * 0xFFFD - Reserved for user-space HWRM interface
12507 uint16_t target_id;
12509 * A physical address pointer pointing to a host buffer that the
12510 * command's response data will be written. This can be either a host
12511 * physical address (HPA) or a guest physical address (GPA) and must
12512 * point to a physically contiguous block of memory.
12514 uint64_t resp_addr;
12516 * The number of VF functions that are being configured.
12517 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
12520 uint16_t unused[3];
12521 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12523 /* The physical VF id the adjustment will be made to. */
12524 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12525 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
12527 * This field configures the rate scale percentage of the VF as specified
12528 * by the physical VF id.
12530 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
12531 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
12532 /* 0% of the max tx rate */
12533 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
12534 (UINT32_C(0x0) << 12)
12535 /* 6.66% of the max tx rate */
12536 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
12537 (UINT32_C(0x1) << 12)
12538 /* 13.33% of the max tx rate */
12539 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
12540 (UINT32_C(0x2) << 12)
12541 /* 20% of the max tx rate */
12542 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
12543 (UINT32_C(0x3) << 12)
12544 /* 26.66% of the max tx rate */
12545 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
12546 (UINT32_C(0x4) << 12)
12547 /* 33% of the max tx rate */
12548 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
12549 (UINT32_C(0x5) << 12)
12550 /* 40% of the max tx rate */
12551 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
12552 (UINT32_C(0x6) << 12)
12553 /* 46.66% of the max tx rate */
12554 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
12555 (UINT32_C(0x7) << 12)
12556 /* 53.33% of the max tx rate */
12557 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
12558 (UINT32_C(0x8) << 12)
12559 /* 60% of the max tx rate */
12560 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
12561 (UINT32_C(0x9) << 12)
12562 /* 66.66% of the max tx rate */
12563 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
12564 (UINT32_C(0xa) << 12)
12565 /* 53.33% of the max tx rate */
12566 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
12567 (UINT32_C(0xb) << 12)
12568 /* 80% of the max tx rate */
12569 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
12570 (UINT32_C(0xc) << 12)
12571 /* 86.66% of the max tx rate */
12572 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
12573 (UINT32_C(0xd) << 12)
12574 /* 93.33% of the max tx rate */
12575 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
12576 (UINT32_C(0xe) << 12)
12577 /* 100% of the max tx rate */
12578 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
12579 (UINT32_C(0xf) << 12)
12580 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
12581 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
12584 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
12585 struct hwrm_func_vf_bw_cfg_output {
12586 /* The specific error status for the command. */
12587 uint16_t error_code;
12588 /* The HWRM command request type. */
12590 /* The sequence ID from the original command. */
12592 /* The length of the response data in number of bytes. */
12594 uint8_t unused_0[7];
12596 * This field is used in Output records to indicate that the output
12597 * is completely written to RAM. This field should be read as '1'
12598 * to indicate that the output has been completely written.
12599 * When writing a command completion or response to an internal processor,
12600 * the order of writes has to be such that this field is written last.
12605 /************************
12606 * hwrm_func_vf_bw_qcfg *
12607 ************************/
12610 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
12611 struct hwrm_func_vf_bw_qcfg_input {
12612 /* The HWRM command request type. */
12615 * The completion ring to send the completion event on. This should
12616 * be the NQ ID returned from the `nq_alloc` HWRM command.
12618 uint16_t cmpl_ring;
12620 * The sequence ID is used by the driver for tracking multiple
12621 * commands. This ID is treated as opaque data by the firmware and
12622 * the value is returned in the `hwrm_resp_hdr` upon completion.
12626 * The target ID of the command:
12627 * * 0x0-0xFFF8 - The function ID
12628 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12629 * * 0xFFFD - Reserved for user-space HWRM interface
12632 uint16_t target_id;
12634 * A physical address pointer pointing to a host buffer that the
12635 * command's response data will be written. This can be either a host
12636 * physical address (HPA) or a guest physical address (GPA) and must
12637 * point to a physically contiguous block of memory.
12639 uint64_t resp_addr;
12641 * The number of VF functions that are being queried.
12642 * The inline response space allows the host to query up to 50 VFs'
12643 * rate scale percentage
12646 uint16_t unused[3];
12647 /* These 16-bit fields contain the VF fid */
12649 /* The physical VF id of interest */
12650 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
12651 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
12654 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
12655 struct hwrm_func_vf_bw_qcfg_output {
12656 /* The specific error status for the command. */
12657 uint16_t error_code;
12658 /* The HWRM command request type. */
12660 /* The sequence ID from the original command. */
12662 /* The length of the response data in number of bytes. */
12665 * The number of VF functions that are being queried.
12666 * The inline response space allows the host to query up to 50 VFs' rate
12670 uint16_t unused[3];
12671 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
12673 /* The physical VF id the adjustment will be made to. */
12674 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
12675 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
12677 * This field configures the rate scale percentage of the VF as specified
12678 * by the physical VF id.
12680 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
12681 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
12682 /* 0% of the max tx rate */
12683 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
12684 (UINT32_C(0x0) << 12)
12685 /* 6.66% of the max tx rate */
12686 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
12687 (UINT32_C(0x1) << 12)
12688 /* 13.33% of the max tx rate */
12689 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
12690 (UINT32_C(0x2) << 12)
12691 /* 20% of the max tx rate */
12692 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
12693 (UINT32_C(0x3) << 12)
12694 /* 26.66% of the max tx rate */
12695 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
12696 (UINT32_C(0x4) << 12)
12697 /* 33% of the max tx rate */
12698 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
12699 (UINT32_C(0x5) << 12)
12700 /* 40% of the max tx rate */
12701 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
12702 (UINT32_C(0x6) << 12)
12703 /* 46.66% of the max tx rate */
12704 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
12705 (UINT32_C(0x7) << 12)
12706 /* 53.33% of the max tx rate */
12707 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
12708 (UINT32_C(0x8) << 12)
12709 /* 60% of the max tx rate */
12710 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
12711 (UINT32_C(0x9) << 12)
12712 /* 66.66% of the max tx rate */
12713 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
12714 (UINT32_C(0xa) << 12)
12715 /* 53.33% of the max tx rate */
12716 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
12717 (UINT32_C(0xb) << 12)
12718 /* 80% of the max tx rate */
12719 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
12720 (UINT32_C(0xc) << 12)
12721 /* 86.66% of the max tx rate */
12722 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
12723 (UINT32_C(0xd) << 12)
12724 /* 93.33% of the max tx rate */
12725 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
12726 (UINT32_C(0xe) << 12)
12727 /* 100% of the max tx rate */
12728 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
12729 (UINT32_C(0xf) << 12)
12730 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
12731 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
12732 uint8_t unused_0[7];
12734 * This field is used in Output records to indicate that the output
12735 * is completely written to RAM. This field should be read as '1'
12736 * to indicate that the output has been completely written.
12737 * When writing a command completion or response to an internal processor,
12738 * the order of writes has to be such that this field is written last.
12743 /***************************
12744 * hwrm_func_drv_if_change *
12745 ***************************/
12748 /* hwrm_func_drv_if_change_input (size:192b/24B) */
12749 struct hwrm_func_drv_if_change_input {
12750 /* The HWRM command request type. */
12753 * The completion ring to send the completion event on. This should
12754 * be the NQ ID returned from the `nq_alloc` HWRM command.
12756 uint16_t cmpl_ring;
12758 * The sequence ID is used by the driver for tracking multiple
12759 * commands. This ID is treated as opaque data by the firmware and
12760 * the value is returned in the `hwrm_resp_hdr` upon completion.
12764 * The target ID of the command:
12765 * * 0x0-0xFFF8 - The function ID
12766 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12767 * * 0xFFFD - Reserved for user-space HWRM interface
12770 uint16_t target_id;
12772 * A physical address pointer pointing to a host buffer that the
12773 * command's response data will be written. This can be either a host
12774 * physical address (HPA) or a guest physical address (GPA) and must
12775 * point to a physically contiguous block of memory.
12777 uint64_t resp_addr;
12780 * When this bit is '1', the function driver is indicating
12781 * that the IF state is changing to UP state. The call should
12782 * be made at the beginning of the driver's open call before
12783 * resources are allocated. After making the call, the driver
12784 * should check the response to see if any resources may have
12785 * changed (see the response below). If the driver fails
12786 * the open call, the driver should make this call again with
12787 * this bit cleared to indicate that the IF state is not UP.
12788 * During the driver's close call when the IF state is changing
12789 * to DOWN, the driver should make this call with the bit cleared
12790 * after all resources have been freed.
12792 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
12796 /* hwrm_func_drv_if_change_output (size:128b/16B) */
12797 struct hwrm_func_drv_if_change_output {
12798 /* The specific error status for the command. */
12799 uint16_t error_code;
12800 /* The HWRM command request type. */
12802 /* The sequence ID from the original command. */
12804 /* The length of the response data in number of bytes. */
12808 * When this bit is '1', it indicates that the resources reserved
12809 * for this function may have changed. The driver should check
12810 * resource capabilities and reserve resources again before
12811 * allocating resources.
12813 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
12816 * When this bit is '1', it indicates that the firmware got changed / reset.
12817 * The driver should do complete re-initialization when that bit is set.
12819 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
12821 uint8_t unused_0[3];
12823 * This field is used in Output records to indicate that the output
12824 * is completely written to RAM. This field should be read as '1'
12825 * to indicate that the output has been completely written.
12826 * When writing a command completion or response to an internal processor,
12827 * the order of writes has to be such that this field is written last.
12832 /*******************************
12833 * hwrm_func_host_pf_ids_query *
12834 *******************************/
12837 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
12838 struct hwrm_func_host_pf_ids_query_input {
12839 /* The HWRM command request type. */
12842 * The completion ring to send the completion event on. This should
12843 * be the NQ ID returned from the `nq_alloc` HWRM command.
12845 uint16_t cmpl_ring;
12847 * The sequence ID is used by the driver for tracking multiple
12848 * commands. This ID is treated as opaque data by the firmware and
12849 * the value is returned in the `hwrm_resp_hdr` upon completion.
12853 * The target ID of the command:
12854 * * 0x0-0xFFF8 - The function ID
12855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12856 * * 0xFFFD - Reserved for user-space HWRM interface
12859 uint16_t target_id;
12861 * A physical address pointer pointing to a host buffer that the
12862 * command's response data will be written. This can be either a host
12863 * physical address (HPA) or a guest physical address (GPA) and must
12864 * point to a physically contiguous block of memory.
12866 uint64_t resp_addr;
12869 * # If this bit is set to '1', the query will contain PF(s)
12870 * belongs to SOC host.
12872 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
12874 * # If this bit is set to '1', the query will contain PF(s)
12875 * belongs to EP0 host.
12877 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
12879 * # If this bit is set to '1', the query will contain PF(s)
12880 * belongs to EP1 host.
12882 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
12884 * # If this bit is set to '1', the query will contain PF(s)
12885 * belongs to EP2 host.
12887 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
12889 * # If this bit is set to '1', the query will contain PF(s)
12890 * belongs to EP3 host.
12892 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
12894 * This provides a filter of what PF(s) will be returned in the
12899 * all available PF(s) belong to the host(s) (defined in the
12900 * host field). This includes the hidden PFs.
12902 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
12904 * all available PF(s) belong to the host(s) (defined in the
12905 * host field) that is available for L2 traffic.
12907 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
12909 * all available PF(s) belong to the host(s) (defined in the
12910 * host field) that is available for ROCE traffic.
12912 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
12913 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
12914 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
12915 uint8_t unused_1[6];
12918 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
12919 struct hwrm_func_host_pf_ids_query_output {
12920 /* The specific error status for the command. */
12921 uint16_t error_code;
12922 /* The HWRM command request type. */
12924 /* The sequence ID from the original command. */
12926 /* The length of the response data in number of bytes. */
12928 /* This provides the first PF ID of the device. */
12929 uint16_t first_pf_id;
12930 uint16_t pf_ordinal_mask;
12932 * When this bit is '1', it indicates first PF belongs to one of
12933 * the hosts defined in the input request.
12935 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
12938 * When this bit is '1', it indicates 2nd PF belongs to one of the
12939 * hosts defined in the input request.
12941 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
12944 * When this bit is '1', it indicates 3rd PF belongs to one of the
12945 * hosts defined in the input request.
12947 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
12950 * When this bit is '1', it indicates 4th PF belongs to one of the
12951 * hosts defined in the input request.
12953 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
12956 * When this bit is '1', it indicates 5th PF belongs to one of the
12957 * hosts defined in the input request.
12959 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
12962 * When this bit is '1', it indicates 6th PF belongs to one of the
12963 * hosts defined in the input request.
12965 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
12968 * When this bit is '1', it indicates 7th PF belongs to one of the
12969 * hosts defined in the input request.
12971 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
12974 * When this bit is '1', it indicates 8th PF belongs to one of the
12975 * hosts defined in the input request.
12977 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
12980 * When this bit is '1', it indicates 9th PF belongs to one of the
12981 * hosts defined in the input request.
12983 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
12986 * When this bit is '1', it indicates 10th PF belongs to one of the
12987 * hosts defined in the input request.
12989 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
12992 * When this bit is '1', it indicates 11th PF belongs to one of the
12993 * hosts defined in the input request.
12995 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
12998 * When this bit is '1', it indicates 12th PF belongs to one of the
12999 * hosts defined in the input request.
13001 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
13004 * When this bit is '1', it indicates 13th PF belongs to one of the
13005 * hosts defined in the input request.
13007 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
13010 * When this bit is '1', it indicates 14th PF belongs to one of the
13011 * hosts defined in the input request.
13013 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
13016 * When this bit is '1', it indicates 15th PF belongs to one of the
13017 * hosts defined in the input request.
13019 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
13022 * When this bit is '1', it indicates 16th PF belongs to one of the
13023 * hosts defined in the input request.
13025 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
13027 uint8_t unused_1[3];
13029 * This field is used in Output records to indicate that the output
13030 * is completely written to RAM. This field should be read as '1'
13031 * to indicate that the output has been completely written.
13032 * When writing a command completion or response to an internal processor,
13033 * the order of writes has to be such that this field is written last.
13038 /*********************
13039 * hwrm_port_phy_cfg *
13040 *********************/
13043 /* hwrm_port_phy_cfg_input (size:448b/56B) */
13044 struct hwrm_port_phy_cfg_input {
13045 /* The HWRM command request type. */
13048 * The completion ring to send the completion event on. This should
13049 * be the NQ ID returned from the `nq_alloc` HWRM command.
13051 uint16_t cmpl_ring;
13053 * The sequence ID is used by the driver for tracking multiple
13054 * commands. This ID is treated as opaque data by the firmware and
13055 * the value is returned in the `hwrm_resp_hdr` upon completion.
13059 * The target ID of the command:
13060 * * 0x0-0xFFF8 - The function ID
13061 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13062 * * 0xFFFD - Reserved for user-space HWRM interface
13065 uint16_t target_id;
13067 * A physical address pointer pointing to a host buffer that the
13068 * command's response data will be written. This can be either a host
13069 * physical address (HPA) or a guest physical address (GPA) and must
13070 * point to a physically contiguous block of memory.
13072 uint64_t resp_addr;
13075 * When this bit is set to '1', the PHY for the port shall
13078 * # If this bit is set to 1, then the HWRM shall reset the
13079 * PHY after applying PHY configuration changes specified
13081 * # In order to guarantee that PHY configuration changes
13082 * specified in this command take effect, the HWRM
13083 * client should set this flag to 1.
13084 * # If this bit is not set to 1, then the HWRM may reset
13085 * the PHY depending on the current PHY configuration and
13086 * settings specified in this command.
13088 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
13090 /* deprecated bit. Do not use!!! */
13091 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
13094 * When this bit is set to '1', the link shall be forced to
13095 * the force_link_speed value.
13097 * When this bit is set to '1', the HWRM client should
13098 * not enable any of the auto negotiation related
13099 * fields represented by auto_XXX fields in this command.
13100 * When this bit is set to '1' and the HWRM client has
13101 * enabled a auto_XXX field in this command, then the
13102 * HWRM shall ignore the enabled auto_XXX field.
13104 * When this bit is set to zero, the link
13105 * shall be allowed to autoneg.
13107 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
13110 * When this bit is set to '1', the auto-negotiation process
13111 * shall be restarted on the link.
13113 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
13116 * When this bit is set to '1', Energy Efficient Ethernet
13117 * (EEE) is requested to be enabled on this link.
13118 * If EEE is not supported on this port, then this flag
13119 * shall be ignored by the HWRM.
13121 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
13124 * When this bit is set to '1', Energy Efficient Ethernet
13125 * (EEE) is requested to be disabled on this link.
13126 * If EEE is not supported on this port, then this flag
13127 * shall be ignored by the HWRM.
13129 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
13132 * When this bit is set to '1' and EEE is enabled on this
13133 * link, then TX LPI is requested to be enabled on the link.
13134 * If EEE is not supported on this port, then this flag
13135 * shall be ignored by the HWRM.
13136 * If EEE is disabled on this port, then this flag shall be
13137 * ignored by the HWRM.
13139 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
13142 * When this bit is set to '1' and EEE is enabled on this
13143 * link, then TX LPI is requested to be disabled on the link.
13144 * If EEE is not supported on this port, then this flag
13145 * shall be ignored by the HWRM.
13146 * If EEE is disabled on this port, then this flag shall be
13147 * ignored by the HWRM.
13149 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
13152 * When set to 1, then the HWRM shall enable FEC autonegotitation
13153 * on this port if supported.
13154 * When set to 0, then this flag shall be ignored.
13155 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13158 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
13161 * When set to 1, then the HWRM shall disable FEC autonegotiation
13162 * on this port if supported.
13163 * When set to 0, then this flag shall be ignored.
13164 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
13167 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
13170 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
13171 * on this port if supported.
13172 * When set to 0, then this flag shall be ignored.
13173 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13176 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
13179 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
13180 * on this port if supported.
13181 * When set to 0, then this flag shall be ignored.
13182 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
13185 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
13188 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
13189 * on this port if supported.
13190 * When set to 0, then this flag shall be ignored.
13191 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13194 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
13197 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
13198 * on this port if supported.
13199 * When set to 0, then this flag shall be ignored.
13200 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
13203 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
13206 * When this bit is set to '1', the link shall be forced to
13209 * # When this bit is set to '1", all other
13210 * command input settings related to the link speed shall
13212 * Once the link state is forced down, it can be
13213 * explicitly cleared from that state by setting this flag
13215 * # If this flag is set to '0', then the link shall be
13216 * cleared from forced down state if the link is in forced
13218 * There may be conditions (e.g. out-of-band or sideband
13219 * configuration changes for the link) outside the scope
13220 * of the HWRM implementation that may clear forced down
13223 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
13227 * This bit must be '1' for the auto_mode field to be
13230 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
13233 * This bit must be '1' for the auto_duplex field to be
13236 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
13239 * This bit must be '1' for the auto_pause field to be
13242 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
13245 * This bit must be '1' for the auto_link_speed field to be
13248 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
13251 * This bit must be '1' for the auto_link_speed_mask field to be
13254 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
13257 * This bit must be '1' for the wirespeed field to be
13260 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
13263 * This bit must be '1' for the lpbk field to be
13266 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
13269 * This bit must be '1' for the preemphasis field to be
13272 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
13275 * This bit must be '1' for the force_pause field to be
13278 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
13281 * This bit must be '1' for the eee_link_speed_mask field to be
13284 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
13287 * This bit must be '1' for the tx_lpi_timer field to be
13290 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
13292 /* Port ID of port that is to be configured. */
13295 * This is the speed that will be used if the force
13296 * bit is '1'. If unsupported speed is selected, an error
13297 * will be generated.
13299 uint16_t force_link_speed;
13300 /* 100Mb link speed */
13301 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13302 /* 1Gb link speed */
13303 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13304 /* 2Gb link speed */
13305 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13306 /* 25Gb link speed */
13307 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13308 /* 10Gb link speed */
13309 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13310 /* 20Mb link speed */
13311 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13312 /* 25Gb link speed */
13313 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13314 /* 40Gb link speed */
13315 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
13316 /* 50Gb link speed */
13317 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
13318 /* 100Gb link speed */
13319 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
13320 /* 200Gb link speed */
13321 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
13322 /* 10Mb link speed */
13323 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
13324 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
13325 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
13327 * This value is used to identify what autoneg mode is
13328 * used when the link speed is not being forced.
13331 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13332 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
13333 /* Select all possible speeds for autoneg mode. */
13334 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13336 * Select only the auto_link_speed speed for autoneg mode. This mode has
13337 * been DEPRECATED. An HWRM client should not use this mode.
13339 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13341 * Select the auto_link_speed or any speed below that speed for autoneg.
13342 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13344 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13346 * Select the speeds based on the corresponding link speed mask value
13347 * that is provided.
13349 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13350 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
13351 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
13353 * This is the duplex setting that will be used if the autoneg_mode
13354 * is "one_speed" or "one_or_below".
13356 uint8_t auto_duplex;
13357 /* Half Duplex will be requested. */
13358 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
13359 /* Full duplex will be requested. */
13360 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
13361 /* Both Half and Full dupex will be requested. */
13362 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
13363 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
13364 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
13366 * This value is used to configure the pause that will be
13367 * used for autonegotiation.
13368 * Add text on the usage of auto_pause and force_pause.
13370 uint8_t auto_pause;
13372 * When this bit is '1', Generation of tx pause messages
13373 * has been requested. Disabled otherwise.
13375 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
13378 * When this bit is '1', Reception of rx pause messages
13379 * has been requested. Disabled otherwise.
13381 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
13384 * When set to 1, the advertisement of pause is enabled.
13386 * # When the auto_mode is not set to none and this flag is
13387 * set to 1, then the auto_pause bits on this port are being
13388 * advertised and autoneg pause results are being interpreted.
13389 * # When the auto_mode is not set to none and this
13390 * flag is set to 0, the pause is forced as indicated in
13391 * force_pause, and also advertised as auto_pause bits, but
13392 * the autoneg results are not interpreted since the pause
13393 * configuration is being forced.
13394 * # When the auto_mode is set to none and this flag is set to
13395 * 1, auto_pause bits should be ignored and should be set to 0.
13397 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13401 * This is the speed that will be used if the autoneg_mode
13402 * is "one_speed" or "one_or_below". If an unsupported speed
13403 * is selected, an error will be generated.
13405 uint16_t auto_link_speed;
13406 /* 100Mb link speed */
13407 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13408 /* 1Gb link speed */
13409 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13410 /* 2Gb link speed */
13411 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13412 /* 25Gb link speed */
13413 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13414 /* 10Gb link speed */
13415 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13416 /* 20Mb link speed */
13417 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13418 /* 25Gb link speed */
13419 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13420 /* 40Gb link speed */
13421 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13422 /* 50Gb link speed */
13423 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13424 /* 100Gb link speed */
13425 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13426 /* 200Gb link speed */
13427 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13428 /* 10Mb link speed */
13429 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
13430 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
13431 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
13433 * This is a mask of link speeds that will be used if
13434 * autoneg_mode is "mask". If unsupported speed is enabled
13435 * an error will be generated.
13437 uint16_t auto_link_speed_mask;
13438 /* 100Mb link speed (Half-duplex) */
13439 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13441 /* 100Mb link speed (Full-duplex) */
13442 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
13444 /* 1Gb link speed (Half-duplex) */
13445 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13447 /* 1Gb link speed (Full-duplex) */
13448 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
13450 /* 2Gb link speed */
13451 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
13453 /* 25Gb link speed */
13454 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13456 /* 10Gb link speed */
13457 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
13459 /* 20Gb link speed */
13460 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
13462 /* 25Gb link speed */
13463 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
13465 /* 40Gb link speed */
13466 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
13468 /* 50Gb link speed */
13469 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
13471 /* 100Gb link speed */
13472 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
13474 /* 10Mb link speed (Half-duplex) */
13475 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13477 /* 10Mb link speed (Full-duplex) */
13478 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
13480 /* 200Gb link speed */
13481 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
13483 /* This value controls the wirespeed feature. */
13485 /* Wirespeed feature is disabled. */
13486 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
13487 /* Wirespeed feature is enabled. */
13488 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
13489 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
13490 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
13491 /* This value controls the loopback setting for the PHY. */
13493 /* No loopback is selected. Normal operation. */
13494 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
13496 * The HW will be configured with local loopback such that
13497 * host data is sent back to the host without modification.
13499 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
13501 * The HW will be configured with remote loopback such that
13502 * port logic will send packets back out the transmitter that
13505 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
13507 * The HW will be configured with external loopback such that
13508 * host data is sent on the transmitter and based on the external
13509 * loopback connection the data will be received without modification.
13511 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
13512 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
13513 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
13515 * This value is used to configure the pause that will be
13516 * used for force mode.
13518 uint8_t force_pause;
13520 * When this bit is '1', Generation of tx pause messages
13521 * is supported. Disabled otherwise.
13523 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
13525 * When this bit is '1', Reception of rx pause messages
13526 * is supported. Disabled otherwise.
13528 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
13531 * This value controls the pre-emphasis to be used for the
13532 * link. Driver should not set this value (use
13533 * enable.preemphasis = 0) unless driver is sure of setting.
13534 * Normally HWRM FW will determine proper pre-emphasis.
13536 uint32_t preemphasis;
13538 * Setting for link speed mask that is used to
13539 * advertise speeds during autonegotiation when EEE is enabled.
13540 * This field is valid only when EEE is enabled.
13541 * The speeds specified in this field shall be a subset of
13542 * speeds specified in auto_link_speed_mask.
13543 * If EEE is enabled,then at least one speed shall be provided
13546 uint16_t eee_link_speed_mask;
13548 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
13550 /* 100Mb link speed (Full-duplex) */
13551 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
13554 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
13556 /* 1Gb link speed (Full-duplex) */
13557 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
13560 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
13563 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
13565 /* 10Gb link speed */
13566 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
13568 uint8_t unused_2[2];
13570 * Requested setting of TX LPI timer in microseconds.
13571 * This field is valid only when EEE is enabled and TX LPI is
13574 uint32_t tx_lpi_timer;
13575 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
13576 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
13580 /* hwrm_port_phy_cfg_output (size:128b/16B) */
13581 struct hwrm_port_phy_cfg_output {
13582 /* The specific error status for the command. */
13583 uint16_t error_code;
13584 /* The HWRM command request type. */
13586 /* The sequence ID from the original command. */
13588 /* The length of the response data in number of bytes. */
13590 uint8_t unused_0[7];
13592 * This field is used in Output records to indicate that the output
13593 * is completely written to RAM. This field should be read as '1'
13594 * to indicate that the output has been completely written.
13595 * When writing a command completion or response to an internal processor,
13596 * the order of writes has to be such that this field is written last.
13601 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
13602 struct hwrm_port_phy_cfg_cmd_err {
13604 * command specific error codes that goes to
13605 * the cmd_err field in Common HWRM Error Response.
13608 /* Unknown error */
13609 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
13610 /* Unable to complete operation due to invalid speed */
13611 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
13613 * retry the command since the phy is not ready.
13614 * retry count is returned in opaque_0.
13615 * This is only valid for the first command and
13616 * this value will not change for successive calls.
13617 * but if a 0 is returned at any time then this should
13618 * be treated as an un recoverable failure,
13620 * retry interval in milli seconds is returned in opaque_1.
13621 * This specifies the time that user should wait before
13622 * issuing the next port_phy_cfg command.
13624 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
13625 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
13626 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
13627 uint8_t unused_0[7];
13630 /**********************
13631 * hwrm_port_phy_qcfg *
13632 **********************/
13635 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
13636 struct hwrm_port_phy_qcfg_input {
13637 /* The HWRM command request type. */
13640 * The completion ring to send the completion event on. This should
13641 * be the NQ ID returned from the `nq_alloc` HWRM command.
13643 uint16_t cmpl_ring;
13645 * The sequence ID is used by the driver for tracking multiple
13646 * commands. This ID is treated as opaque data by the firmware and
13647 * the value is returned in the `hwrm_resp_hdr` upon completion.
13651 * The target ID of the command:
13652 * * 0x0-0xFFF8 - The function ID
13653 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13654 * * 0xFFFD - Reserved for user-space HWRM interface
13657 uint16_t target_id;
13659 * A physical address pointer pointing to a host buffer that the
13660 * command's response data will be written. This can be either a host
13661 * physical address (HPA) or a guest physical address (GPA) and must
13662 * point to a physically contiguous block of memory.
13664 uint64_t resp_addr;
13665 /* Port ID of port that is to be queried. */
13667 uint8_t unused_0[6];
13670 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
13671 struct hwrm_port_phy_qcfg_output {
13672 /* The specific error status for the command. */
13673 uint16_t error_code;
13674 /* The HWRM command request type. */
13676 /* The sequence ID from the original command. */
13678 /* The length of the response data in number of bytes. */
13680 /* This value indicates the current link status. */
13682 /* There is no link or cable detected. */
13683 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
13684 /* There is no link, but a cable has been detected. */
13685 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
13686 /* There is a link. */
13687 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
13688 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
13689 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
13691 /* This value indicates the current link speed of the connection. */
13692 uint16_t link_speed;
13693 /* 100Mb link speed */
13694 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
13695 /* 1Gb link speed */
13696 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
13697 /* 2Gb link speed */
13698 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
13699 /* 25Gb link speed */
13700 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
13701 /* 10Gb link speed */
13702 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
13703 /* 20Mb link speed */
13704 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
13705 /* 25Gb link speed */
13706 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
13707 /* 40Gb link speed */
13708 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
13709 /* 50Gb link speed */
13710 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
13711 /* 100Gb link speed */
13712 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
13713 /* 200Gb link speed */
13714 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
13715 /* 10Mb link speed */
13716 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
13717 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
13718 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
13720 * This value is indicates the duplex of the current
13723 uint8_t duplex_cfg;
13724 /* Half Duplex connection. */
13725 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
13726 /* Full duplex connection. */
13727 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
13728 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
13729 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
13731 * This value is used to indicate the current
13732 * pause configuration. When autoneg is enabled, this value
13733 * represents the autoneg results of pause configuration.
13737 * When this bit is '1', Generation of tx pause messages
13738 * is supported. Disabled otherwise.
13740 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
13742 * When this bit is '1', Reception of rx pause messages
13743 * is supported. Disabled otherwise.
13745 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
13747 * The supported speeds for the port. This is a bit mask.
13748 * For each speed that is supported, the corrresponding
13749 * bit will be set to '1'.
13751 uint16_t support_speeds;
13752 /* 100Mb link speed (Half-duplex) */
13753 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
13755 /* 100Mb link speed (Full-duplex) */
13756 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
13758 /* 1Gb link speed (Half-duplex) */
13759 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
13761 /* 1Gb link speed (Full-duplex) */
13762 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
13764 /* 2Gb link speed */
13765 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
13767 /* 25Gb link speed */
13768 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
13770 /* 10Gb link speed */
13771 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
13773 /* 20Gb link speed */
13774 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
13776 /* 25Gb link speed */
13777 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
13779 /* 40Gb link speed */
13780 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
13782 /* 50Gb link speed */
13783 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
13785 /* 100Gb link speed */
13786 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
13788 /* 10Mb link speed (Half-duplex) */
13789 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
13791 /* 10Mb link speed (Full-duplex) */
13792 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
13794 /* 200Gb link speed */
13795 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
13798 * Current setting of forced link speed.
13799 * When the link speed is not being forced, this
13800 * value shall be set to 0.
13802 uint16_t force_link_speed;
13803 /* 100Mb link speed */
13804 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
13805 /* 1Gb link speed */
13806 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
13807 /* 2Gb link speed */
13808 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
13809 /* 25Gb link speed */
13810 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
13811 /* 10Gb link speed */
13812 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
13813 /* 20Mb link speed */
13814 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
13815 /* 25Gb link speed */
13816 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
13817 /* 40Gb link speed */
13818 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
13820 /* 50Gb link speed */
13821 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
13823 /* 100Gb link speed */
13824 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
13826 /* 200Gb link speed */
13827 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
13829 /* 10Mb link speed */
13830 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
13832 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
13833 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
13834 /* Current setting of auto negotiation mode. */
13836 /* Disable autoneg or autoneg disabled. No speeds are selected. */
13837 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
13838 /* Select all possible speeds for autoneg mode. */
13839 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
13841 * Select only the auto_link_speed speed for autoneg mode. This mode has
13842 * been DEPRECATED. An HWRM client should not use this mode.
13844 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
13846 * Select the auto_link_speed or any speed below that speed for autoneg.
13847 * This mode has been DEPRECATED. An HWRM client should not use this mode.
13849 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
13851 * Select the speeds based on the corresponding link speed mask value
13852 * that is provided.
13854 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
13855 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
13856 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
13858 * Current setting of pause autonegotiation.
13859 * Move autoneg_pause flag here.
13861 uint8_t auto_pause;
13863 * When this bit is '1', Generation of tx pause messages
13864 * has been requested. Disabled otherwise.
13866 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
13869 * When this bit is '1', Reception of rx pause messages
13870 * has been requested. Disabled otherwise.
13872 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
13875 * When set to 1, the advertisement of pause is enabled.
13877 * # When the auto_mode is not set to none and this flag is
13878 * set to 1, then the auto_pause bits on this port are being
13879 * advertised and autoneg pause results are being interpreted.
13880 * # When the auto_mode is not set to none and this
13881 * flag is set to 0, the pause is forced as indicated in
13882 * force_pause, and also advertised as auto_pause bits, but
13883 * the autoneg results are not interpreted since the pause
13884 * configuration is being forced.
13885 * # When the auto_mode is set to none and this flag is set to
13886 * 1, auto_pause bits should be ignored and should be set to 0.
13888 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
13891 * Current setting for auto_link_speed. This field is only
13892 * valid when auto_mode is set to "one_speed" or "one_or_below".
13894 uint16_t auto_link_speed;
13895 /* 100Mb link speed */
13896 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
13897 /* 1Gb link speed */
13898 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
13899 /* 2Gb link speed */
13900 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
13901 /* 25Gb link speed */
13902 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
13903 /* 10Gb link speed */
13904 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
13905 /* 20Mb link speed */
13906 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
13907 /* 25Gb link speed */
13908 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
13909 /* 40Gb link speed */
13910 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
13911 /* 50Gb link speed */
13912 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
13913 /* 100Gb link speed */
13914 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
13915 /* 200Gb link speed */
13916 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
13917 /* 10Mb link speed */
13918 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
13920 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
13921 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
13923 * Current setting for auto_link_speed_mask that is used to
13924 * advertise speeds during autonegotiation.
13925 * This field is only valid when auto_mode is set to "mask".
13926 * The speeds specified in this field shall be a subset of
13927 * supported speeds on this port.
13929 uint16_t auto_link_speed_mask;
13930 /* 100Mb link speed (Half-duplex) */
13931 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
13933 /* 100Mb link speed (Full-duplex) */
13934 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
13936 /* 1Gb link speed (Half-duplex) */
13937 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
13939 /* 1Gb link speed (Full-duplex) */
13940 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
13942 /* 2Gb link speed */
13943 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
13945 /* 25Gb link speed */
13946 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
13948 /* 10Gb link speed */
13949 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
13951 /* 20Gb link speed */
13952 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
13954 /* 25Gb link speed */
13955 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
13957 /* 40Gb link speed */
13958 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
13960 /* 50Gb link speed */
13961 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
13963 /* 100Gb link speed */
13964 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
13966 /* 10Mb link speed (Half-duplex) */
13967 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
13969 /* 10Mb link speed (Full-duplex) */
13970 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
13972 /* 200Gb link speed */
13973 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
13975 /* Current setting for wirespeed. */
13977 /* Wirespeed feature is disabled. */
13978 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
13979 /* Wirespeed feature is enabled. */
13980 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
13981 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
13982 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
13983 /* Current setting for loopback. */
13985 /* No loopback is selected. Normal operation. */
13986 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
13988 * The HW will be configured with local loopback such that
13989 * host data is sent back to the host without modification.
13991 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
13993 * The HW will be configured with remote loopback such that
13994 * port logic will send packets back out the transmitter that
13997 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
13999 * The HW will be configured with external loopback such that
14000 * host data is sent on the transmitter and based on the external
14001 * loopback connection the data will be received without modification.
14003 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
14004 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
14005 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
14007 * Current setting of forced pause.
14008 * When the pause configuration is not being forced, then
14009 * this value shall be set to 0.
14011 uint8_t force_pause;
14013 * When this bit is '1', Generation of tx pause messages
14014 * is supported. Disabled otherwise.
14016 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
14018 * When this bit is '1', Reception of rx pause messages
14019 * is supported. Disabled otherwise.
14021 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
14023 * This value indicates the current status of the optics module on
14026 uint8_t module_status;
14027 /* Module is inserted and accepted */
14028 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
14030 /* Module is rejected and transmit side Laser is disabled. */
14031 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
14033 /* Module mismatch warning. */
14034 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
14036 /* Module is rejected and powered down. */
14037 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
14039 /* Module is not inserted. */
14040 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
14042 /* Module status is not applicable. */
14043 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
14045 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
14046 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
14047 /* Current setting for preemphasis. */
14048 uint32_t preemphasis;
14049 /* This field represents the major version of the PHY. */
14051 /* This field represents the minor version of the PHY. */
14053 /* This field represents the build version of the PHY. */
14055 /* This value represents a PHY type. */
14058 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
14061 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
14063 /* BASE-KR4 (Deprecated) */
14064 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
14067 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
14070 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
14072 /* BASE-KR2 (Deprecated) */
14073 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
14076 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
14079 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
14082 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
14084 /* EEE capable BASE-T */
14085 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
14087 /* SGMII connected external PHY */
14088 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
14090 /* 25G_BASECR_CA_L */
14091 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
14093 /* 25G_BASECR_CA_S */
14094 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
14096 /* 25G_BASECR_CA_N */
14097 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
14100 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
14103 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
14106 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
14109 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
14112 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
14114 /* 100G_BASESR10 */
14115 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
14118 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
14121 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
14124 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
14127 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
14129 /* 40G_ACTIVE_CABLE */
14130 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
14133 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
14136 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
14139 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
14142 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
14145 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
14148 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
14151 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
14153 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
14154 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
14155 /* This value represents a media type. */
14156 uint8_t media_type;
14158 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
14160 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
14161 /* Direct Attached Copper */
14162 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
14164 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
14165 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
14166 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
14167 /* This value represents a transceiver type. */
14168 uint8_t xcvr_pkg_type;
14169 /* PHY and MAC are in the same package */
14170 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
14172 /* PHY and MAC are in different packages */
14173 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
14175 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
14176 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
14177 uint8_t eee_config_phy_addr;
14178 /* This field represents PHY address. */
14179 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
14181 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
14183 * This field represents flags related to EEE configuration.
14184 * These EEE configuration flags are valid only when the
14185 * auto_mode is not set to none (in other words autonegotiation
14188 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
14190 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
14192 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
14193 * Speeds for autoneg with EEE mode enabled
14194 * are based on eee_link_speed_mask.
14196 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
14199 * This flag is valid only when eee_enabled is set to 1.
14201 * # If eee_enabled is set to 0, then EEE mode is disabled
14202 * and this flag shall be ignored.
14203 * # If eee_enabled is set to 1 and this flag is set to 1,
14204 * then Energy Efficient Ethernet (EEE) mode is enabled
14206 * # If eee_enabled is set to 1 and this flag is set to 0,
14207 * then Energy Efficient Ethernet (EEE) mode is enabled
14208 * but is currently not in use.
14210 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
14213 * This flag is valid only when eee_enabled is set to 1.
14215 * # If eee_enabled is set to 0, then EEE mode is disabled
14216 * and this flag shall be ignored.
14217 * # If eee_enabled is set to 1 and this flag is set to 1,
14218 * then Energy Efficient Ethernet (EEE) mode is enabled
14219 * and TX LPI is enabled.
14220 * # If eee_enabled is set to 1 and this flag is set to 0,
14221 * then Energy Efficient Ethernet (EEE) mode is enabled
14222 * but TX LPI is disabled.
14224 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
14227 * When set to 1, the parallel detection is used to determine
14228 * the speed of the link partner.
14230 * Parallel detection is used when a autonegotiation capable
14231 * device is connected to a link parter that is not capable
14232 * of autonegotiation.
14234 uint8_t parallel_detect;
14236 * When set to 1, the parallel detection is used to determine
14237 * the speed of the link partner.
14239 * Parallel detection is used when a autonegotiation capable
14240 * device is connected to a link parter that is not capable
14241 * of autonegotiation.
14243 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
14245 * The advertised speeds for the port by the link partner.
14246 * Each advertised speed will be set to '1'.
14248 uint16_t link_partner_adv_speeds;
14249 /* 100Mb link speed (Half-duplex) */
14250 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
14252 /* 100Mb link speed (Full-duplex) */
14253 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
14255 /* 1Gb link speed (Half-duplex) */
14256 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
14258 /* 1Gb link speed (Full-duplex) */
14259 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
14261 /* 2Gb link speed */
14262 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
14264 /* 25Gb link speed */
14265 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
14267 /* 10Gb link speed */
14268 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
14270 /* 20Gb link speed */
14271 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
14273 /* 25Gb link speed */
14274 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
14276 /* 40Gb link speed */
14277 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
14279 /* 50Gb link speed */
14280 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
14282 /* 100Gb link speed */
14283 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
14285 /* 10Mb link speed (Half-duplex) */
14286 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
14288 /* 10Mb link speed (Full-duplex) */
14289 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
14292 * The advertised autoneg for the port by the link partner.
14293 * This field is deprecated and should be set to 0.
14295 uint8_t link_partner_adv_auto_mode;
14296 /* Disable autoneg or autoneg disabled. No speeds are selected. */
14297 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
14299 /* Select all possible speeds for autoneg mode. */
14300 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
14303 * Select only the auto_link_speed speed for autoneg mode. This mode has
14304 * been DEPRECATED. An HWRM client should not use this mode.
14306 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
14309 * Select the auto_link_speed or any speed below that speed for autoneg.
14310 * This mode has been DEPRECATED. An HWRM client should not use this mode.
14312 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
14315 * Select the speeds based on the corresponding link speed mask value
14316 * that is provided.
14318 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
14320 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
14321 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
14322 /* The advertised pause settings on the port by the link partner. */
14323 uint8_t link_partner_adv_pause;
14325 * When this bit is '1', Generation of tx pause messages
14326 * is supported. Disabled otherwise.
14328 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
14331 * When this bit is '1', Reception of rx pause messages
14332 * is supported. Disabled otherwise.
14334 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
14337 * Current setting for link speed mask that is used to
14338 * advertise speeds during autonegotiation when EEE is enabled.
14339 * This field is valid only when eee_enabled flags is set to 1.
14340 * The speeds specified in this field shall be a subset of
14341 * speeds specified in auto_link_speed_mask.
14343 uint16_t adv_eee_link_speed_mask;
14345 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14347 /* 100Mb link speed (Full-duplex) */
14348 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
14351 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14353 /* 1Gb link speed (Full-duplex) */
14354 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
14357 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14360 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14362 /* 10Gb link speed */
14363 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
14366 * Current setting for link speed mask that is advertised by
14367 * the link partner when EEE is enabled.
14368 * This field is valid only when eee_enabled flags is set to 1.
14370 uint16_t link_partner_adv_eee_link_speed_mask;
14372 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
14374 /* 100Mb link speed (Full-duplex) */
14375 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
14378 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
14380 /* 1Gb link speed (Full-duplex) */
14381 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
14384 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
14387 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
14389 /* 10Gb link speed */
14390 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
14392 uint32_t xcvr_identifier_type_tx_lpi_timer;
14394 * Current setting of TX LPI timer in microseconds.
14395 * This field is valid only when_eee_enabled flag is set to 1
14396 * and tx_lpi_enabled is set to 1.
14398 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
14400 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
14401 /* This value represents transceiver identifier type. */
14402 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
14403 UINT32_C(0xff000000)
14404 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
14406 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
14407 (UINT32_C(0x0) << 24)
14408 /* SFP/SFP+/SFP28 */
14409 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
14410 (UINT32_C(0x3) << 24)
14412 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
14413 (UINT32_C(0xc) << 24)
14415 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
14416 (UINT32_C(0xd) << 24)
14418 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
14419 (UINT32_C(0x11) << 24)
14420 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
14421 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
14423 * This value represents the current configuration of
14424 * Forward Error Correction (FEC) on the port.
14428 * When set to 1, then FEC is not supported on this port. If this flag
14429 * is set to 1, then all other FEC configuration flags shall be ignored.
14430 * When set to 0, then FEC is supported as indicated by other
14431 * configuration flags.
14432 * If no cable is attached and the HWRM does not yet know the FEC
14433 * capability, then the HWRM shall set this flag to 1 when reporting
14436 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
14439 * When set to 1, then FEC autonegotiation is supported on this port.
14440 * When set to 0, then FEC autonegotiation is not supported on this port.
14442 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
14445 * When set to 1, then FEC autonegotiation is enabled on this port.
14446 * When set to 0, then FEC autonegotiation is disabled if supported.
14447 * This flag should be ignored if FEC autonegotiation is not supported on this port.
14449 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
14452 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
14453 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
14455 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
14458 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
14459 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
14460 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
14462 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
14465 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
14466 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
14468 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
14471 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
14472 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
14473 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
14475 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
14478 * This value is indicates the duplex of the current
14479 * connection state.
14481 uint8_t duplex_state;
14482 /* Half Duplex connection. */
14483 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
14484 /* Full duplex connection. */
14485 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
14486 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
14487 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
14488 /* Option flags fields. */
14489 uint8_t option_flags;
14490 /* When this bit is '1', Media auto detect is enabled. */
14491 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
14494 * Up to 16 bytes of null padded ASCII string representing
14496 * If the string is set to null, then the vendor name is not
14499 char phy_vendor_name[16];
14501 * Up to 16 bytes of null padded ASCII string that
14502 * identifies vendor specific part number of the PHY.
14503 * If the string is set to null, then the vendor specific
14504 * part number is not available.
14506 char phy_vendor_partnumber[16];
14507 uint8_t unused_2[7];
14509 * This field is used in Output records to indicate that the output
14510 * is completely written to RAM. This field should be read as '1'
14511 * to indicate that the output has been completely written.
14512 * When writing a command completion or response to an internal processor,
14513 * the order of writes has to be such that this field is written last.
14518 /*********************
14519 * hwrm_port_mac_cfg *
14520 *********************/
14523 /* hwrm_port_mac_cfg_input (size:384b/48B) */
14524 struct hwrm_port_mac_cfg_input {
14525 /* The HWRM command request type. */
14528 * The completion ring to send the completion event on. This should
14529 * be the NQ ID returned from the `nq_alloc` HWRM command.
14531 uint16_t cmpl_ring;
14533 * The sequence ID is used by the driver for tracking multiple
14534 * commands. This ID is treated as opaque data by the firmware and
14535 * the value is returned in the `hwrm_resp_hdr` upon completion.
14539 * The target ID of the command:
14540 * * 0x0-0xFFF8 - The function ID
14541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14542 * * 0xFFFD - Reserved for user-space HWRM interface
14545 uint16_t target_id;
14547 * A physical address pointer pointing to a host buffer that the
14548 * command's response data will be written. This can be either a host
14549 * physical address (HPA) or a guest physical address (GPA) and must
14550 * point to a physically contiguous block of memory.
14552 uint64_t resp_addr;
14554 * In this field, there are a number of CoS mappings related flags
14555 * that are used to configure CoS mappings and their corresponding
14556 * priorities in the hardware.
14557 * For the priorities of CoS mappings, the HWRM uses the following
14558 * priority order (high to low) by default:
14561 * # tunnel_vlan_pri
14564 * A subset of CoS mappings can be enabled.
14565 * If a priority is not specified for an enabled CoS mapping, the
14566 * priority will be assigned in the above order for the enabled CoS
14567 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
14568 * enabled and their priorities are not specified, the following
14569 * priority order (high to low) will be used by the HWRM:
14574 * vlan_pri CoS mapping together with default CoS with lower priority
14575 * are enabled by default by the HWRM.
14579 * When this bit is '1', this command will configure
14580 * the MAC to match the current link state of the PHY.
14581 * If the link is not established on the PHY, then this
14582 * bit has no effect.
14584 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
14587 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14588 * is requested to be enabled.
14590 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
14593 * When this bit is set to '1', tunnel VLAN PRI field to
14594 * CoS mapping is requested to be enabled.
14596 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
14599 * When this bit is set to '1', the IP DSCP to CoS mapping is
14600 * requested to be enabled.
14602 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
14605 * When this bit is '1', the HWRM is requested to
14606 * enable timestamp capture capability on the receive side
14609 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
14612 * When this bit is '1', the HWRM is requested to
14613 * disable timestamp capture capability on the receive side
14616 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
14619 * When this bit is '1', the HWRM is requested to
14620 * enable timestamp capture capability on the transmit side
14623 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
14626 * When this bit is '1', the HWRM is requested to
14627 * disable timestamp capture capability on the transmit side
14630 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
14633 * When this bit is '1', the Out-Of-Box WoL is requested to
14634 * be enabled on this port.
14636 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
14639 * When this bit is '1', the Out-Of-Box WoL is requested to
14640 * be disabled on this port.
14642 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
14645 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
14646 * is requested to be disabled.
14648 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
14651 * When this bit is set to '1', tunnel VLAN PRI field to
14652 * CoS mapping is requested to be disabled.
14654 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
14657 * When this bit is set to '1', the IP DSCP to CoS mapping is
14658 * requested to be disabled.
14660 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
14663 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
14664 * bit is set, then the device uses one step Tx timestamping.
14665 * This bit is temporary and used for experimental purposes.
14667 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
14671 * This bit must be '1' for the ipg field to be
14674 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
14677 * This bit must be '1' for the lpbk field to be
14680 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
14683 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
14686 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
14689 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
14692 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
14695 * This bit must be '1' for the dscp2cos_map_pri field to be
14698 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
14701 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
14704 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
14707 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
14710 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
14713 * This bit must be '1' for the cos_field_cfg field to be
14716 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
14719 * This bit must be '1' for the ptp_freq_adj_ppb field to be
14722 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
14724 /* Port ID of port that is to be configured. */
14727 * This value is used to configure the minimum IPG that will
14728 * be sent between packets by this port.
14731 /* This value controls the loopback setting for the MAC. */
14733 /* No loopback is selected. Normal operation. */
14734 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
14736 * The HW will be configured with local loopback such that
14737 * host data is sent back to the host without modification.
14739 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
14741 * The HW will be configured with remote loopback such that
14742 * port logic will send packets back out the transmitter that
14745 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
14746 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
14747 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
14749 * This value controls the priority setting of VLAN PRI to CoS
14750 * mapping based on VLAN Tags of inner packet headers of
14751 * tunneled packets or packet headers of non-tunneled packets.
14753 * # Each XXX_pri variable shall have a unique priority value
14754 * when it is being specified.
14755 * # When comparing priorities of mappings, higher value
14756 * indicates higher priority.
14757 * For example, a value of 0-3 is returned where 0 is being
14758 * the lowest priority and 3 is being the highest priority.
14760 uint8_t vlan_pri2cos_map_pri;
14761 /* Reserved field. */
14764 * This value controls the priority setting of VLAN PRI to CoS
14765 * mapping based on VLAN Tags of tunneled header.
14766 * This mapping only applies when tunneled headers
14769 * # Each XXX_pri variable shall have a unique priority value
14770 * when it is being specified.
14771 * # When comparing priorities of mappings, higher value
14772 * indicates higher priority.
14773 * For example, a value of 0-3 is returned where 0 is being
14774 * the lowest priority and 3 is being the highest priority.
14776 uint8_t tunnel_pri2cos_map_pri;
14778 * This value controls the priority setting of IP DSCP to CoS
14779 * mapping based on inner IP header of tunneled packets or
14780 * IP header of non-tunneled packets.
14782 * # Each XXX_pri variable shall have a unique priority value
14783 * when it is being specified.
14784 * # When comparing priorities of mappings, higher value
14785 * indicates higher priority.
14786 * For example, a value of 0-3 is returned where 0 is being
14787 * the lowest priority and 3 is being the highest priority.
14789 uint8_t dscp2pri_map_pri;
14791 * This is a 16-bit bit mask that is used to request a
14792 * specific configuration of time stamp capture of PTP messages
14793 * on the receive side of this port.
14794 * This field shall be ignored if the ptp_rx_ts_capture_enable
14795 * flag is not set in this command.
14796 * Otherwise, if bit 'i' is set, then the HWRM is being
14797 * requested to configure the receive side of the port to
14798 * capture the time stamp of every received PTP message
14799 * with messageType field value set to i.
14801 uint16_t rx_ts_capture_ptp_msg_type;
14803 * This is a 16-bit bit mask that is used to request a
14804 * specific configuration of time stamp capture of PTP messages
14805 * on the transmit side of this port.
14806 * This field shall be ignored if the ptp_tx_ts_capture_enable
14807 * flag is not set in this command.
14808 * Otherwise, if bit 'i' is set, then the HWRM is being
14809 * requested to configure the transmit side of the port to
14810 * capture the time stamp of every transmitted PTP message
14811 * with messageType field value set to i.
14813 uint16_t tx_ts_capture_ptp_msg_type;
14814 /* Configuration of CoS fields. */
14815 uint8_t cos_field_cfg;
14817 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
14820 * This field is used to specify selection of VLAN PRI value
14821 * based on whether one or two VLAN Tags are present in
14822 * the inner packet headers of tunneled packets or
14823 * non-tunneled packets.
14824 * This field is valid only if inner VLAN PRI to CoS mapping
14826 * If VLAN PRI to CoS mapping is not enabled, then this
14827 * field shall be ignored.
14829 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
14831 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
14834 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14835 * present in the inner packet headers
14837 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
14838 (UINT32_C(0x0) << 1)
14840 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14841 * present in the inner packet headers.
14842 * No VLAN PRI shall be selected for this configuration
14843 * if only one VLAN Tag is present in the inner
14846 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
14847 (UINT32_C(0x1) << 1)
14849 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14850 * are present in the inner packet headers
14852 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
14853 (UINT32_C(0x2) << 1)
14855 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
14856 (UINT32_C(0x3) << 1)
14857 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
14858 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
14860 * This field is used to specify selection of tunnel VLAN
14861 * PRI value based on whether one or two VLAN Tags are
14862 * present in tunnel headers.
14863 * This field is valid only if tunnel VLAN PRI to CoS mapping
14865 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
14866 * field shall be ignored.
14868 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
14870 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
14873 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
14874 * present in the tunnel packet headers
14876 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
14877 (UINT32_C(0x0) << 3)
14879 * Select outer VLAN Tag PRI when 2 VLAN Tags are
14880 * present in the tunnel packet headers.
14881 * No tunnel VLAN PRI shall be selected for this
14882 * configuration if only one VLAN Tag is present in
14883 * the tunnel packet headers.
14885 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
14886 (UINT32_C(0x1) << 3)
14888 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
14889 * are present in the tunnel packet headers
14891 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
14892 (UINT32_C(0x2) << 3)
14894 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
14895 (UINT32_C(0x3) << 3)
14896 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
14897 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
14899 * This field shall be used to provide default CoS value
14900 * that has been configured on this port.
14901 * This field is valid only if default CoS mapping
14903 * If default CoS mapping is not enabled, then this
14904 * field shall be ignored.
14906 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
14908 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
14910 uint8_t unused_0[3];
14912 * This signed field specifies by how much to adjust the frequency
14913 * of sync timer updates (measured in parts per billion).
14915 int32_t ptp_freq_adj_ppb;
14916 uint8_t unused_1[4];
14919 /* hwrm_port_mac_cfg_output (size:128b/16B) */
14920 struct hwrm_port_mac_cfg_output {
14921 /* The specific error status for the command. */
14922 uint16_t error_code;
14923 /* The HWRM command request type. */
14925 /* The sequence ID from the original command. */
14927 /* The length of the response data in number of bytes. */
14930 * This is the configured maximum length of Ethernet packet
14931 * payload that is allowed to be received on the port.
14932 * This value does not include the number of bytes used by
14933 * Ethernet header and trailer (CRC).
14937 * This is the configured maximum length of Ethernet packet
14938 * payload that is allowed to be transmitted on the port.
14939 * This value does not include the number of bytes used by
14940 * Ethernet header and trailer (CRC).
14943 /* Current configuration of the IPG value. */
14945 /* Current value of the loopback value. */
14947 /* No loopback is selected. Normal operation. */
14948 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
14950 * The HW will be configured with local loopback such that
14951 * host data is sent back to the host without modification.
14953 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
14955 * The HW will be configured with remote loopback such that
14956 * port logic will send packets back out the transmitter that
14959 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
14960 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
14961 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
14964 * This field is used in Output records to indicate that the output
14965 * is completely written to RAM. This field should be read as '1'
14966 * to indicate that the output has been completely written.
14967 * When writing a command completion or response to an internal processor,
14968 * the order of writes has to be such that this field is written last.
14973 /**********************
14974 * hwrm_port_mac_qcfg *
14975 **********************/
14978 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
14979 struct hwrm_port_mac_qcfg_input {
14980 /* The HWRM command request type. */
14983 * The completion ring to send the completion event on. This should
14984 * be the NQ ID returned from the `nq_alloc` HWRM command.
14986 uint16_t cmpl_ring;
14988 * The sequence ID is used by the driver for tracking multiple
14989 * commands. This ID is treated as opaque data by the firmware and
14990 * the value is returned in the `hwrm_resp_hdr` upon completion.
14994 * The target ID of the command:
14995 * * 0x0-0xFFF8 - The function ID
14996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14997 * * 0xFFFD - Reserved for user-space HWRM interface
15000 uint16_t target_id;
15002 * A physical address pointer pointing to a host buffer that the
15003 * command's response data will be written. This can be either a host
15004 * physical address (HPA) or a guest physical address (GPA) and must
15005 * point to a physically contiguous block of memory.
15007 uint64_t resp_addr;
15008 /* Port ID of port that is to be configured. */
15010 uint8_t unused_0[6];
15013 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
15014 struct hwrm_port_mac_qcfg_output {
15015 /* The specific error status for the command. */
15016 uint16_t error_code;
15017 /* The HWRM command request type. */
15019 /* The sequence ID from the original command. */
15021 /* The length of the response data in number of bytes. */
15024 * This is the configured maximum length of Ethernet packet
15025 * payload that is allowed to be received on the port.
15026 * This value does not include the number of bytes used by the
15027 * Ethernet header and trailer (CRC).
15031 * This is the configured maximum length of Ethernet packet
15032 * payload that is allowed to be transmitted on the port.
15033 * This value does not include the number of bytes used by the
15034 * Ethernet header and trailer (CRC).
15038 * The minimum IPG that will
15039 * be sent between packets by this port.
15042 /* The loopback setting for the MAC. */
15044 /* No loopback is selected. Normal operation. */
15045 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
15047 * The HW will be configured with local loopback such that
15048 * host data is sent back to the host without modification.
15050 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
15052 * The HW will be configured with remote loopback such that
15053 * port logic will send packets back out the transmitter that
15056 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
15057 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
15058 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
15060 * Priority setting for VLAN PRI to CoS mapping.
15061 * # Each XXX_pri variable shall have a unique priority value
15062 * when it is being used.
15063 * # When comparing priorities of mappings, higher value
15064 * indicates higher priority.
15065 * For example, a value of 0-3 is returned where 0 is being
15066 * the lowest priority and 3 is being the highest priority.
15067 * # If the correspoding CoS mapping is not enabled, then this
15068 * field should be ignored.
15069 * # This value indicates the normalized priority value retained
15072 uint8_t vlan_pri2cos_map_pri;
15074 * In this field, a number of CoS mappings related flags
15075 * are used to indicate configured CoS mappings.
15079 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
15082 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
15085 * When this bit is set to '1', tunnel VLAN PRI field to
15086 * CoS mapping is enabled.
15088 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
15091 * When this bit is set to '1', the IP DSCP to CoS mapping is
15094 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
15097 * When this bit is '1', the Out-Of-Box WoL is enabled on this
15100 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
15102 /* When this bit is '1', PTP is enabled for RX on this port. */
15103 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
15105 /* When this bit is '1', PTP is enabled for TX on this port. */
15106 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
15109 * Priority setting for tunnel VLAN PRI to CoS mapping.
15110 * # Each XXX_pri variable shall have a unique priority value
15111 * when it is being used.
15112 * # When comparing priorities of mappings, higher value
15113 * indicates higher priority.
15114 * For example, a value of 0-3 is returned where 0 is being
15115 * the lowest priority and 3 is being the highest priority.
15116 * # If the correspoding CoS mapping is not enabled, then this
15117 * field should be ignored.
15118 * # This value indicates the normalized priority value retained
15121 uint8_t tunnel_pri2cos_map_pri;
15123 * Priority setting for DSCP to PRI mapping.
15124 * # Each XXX_pri variable shall have a unique priority value
15125 * when it is being used.
15126 * # When comparing priorities of mappings, higher value
15127 * indicates higher priority.
15128 * For example, a value of 0-3 is returned where 0 is being
15129 * the lowest priority and 3 is being the highest priority.
15130 * # If the correspoding CoS mapping is not enabled, then this
15131 * field should be ignored.
15132 * # This value indicates the normalized priority value retained
15135 uint8_t dscp2pri_map_pri;
15137 * This is a 16-bit bit mask that represents the
15138 * current configuration of time stamp capture of PTP messages
15139 * on the receive side of this port.
15140 * If bit 'i' is set, then the receive side of the port
15141 * is configured to capture the time stamp of every
15142 * received PTP message with messageType field value set
15144 * If all bits are set to 0 (i.e. field value set 0),
15145 * then the receive side of the port is not configured
15146 * to capture timestamp for PTP messages.
15147 * If all bits are set to 1, then the receive side of the
15148 * port is configured to capture timestamp for all PTP
15151 uint16_t rx_ts_capture_ptp_msg_type;
15153 * This is a 16-bit bit mask that represents the
15154 * current configuration of time stamp capture of PTP messages
15155 * on the transmit side of this port.
15156 * If bit 'i' is set, then the transmit side of the port
15157 * is configured to capture the time stamp of every
15158 * received PTP message with messageType field value set
15160 * If all bits are set to 0 (i.e. field value set 0),
15161 * then the transmit side of the port is not configured
15162 * to capture timestamp for PTP messages.
15163 * If all bits are set to 1, then the transmit side of the
15164 * port is configured to capture timestamp for all PTP
15167 uint16_t tx_ts_capture_ptp_msg_type;
15168 /* Configuration of CoS fields. */
15169 uint8_t cos_field_cfg;
15171 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
15174 * This field is used for selecting VLAN PRI value
15175 * based on whether one or two VLAN Tags are present in
15176 * the inner packet headers of tunneled packets or
15177 * non-tunneled packets.
15179 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
15181 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
15184 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15185 * present in the inner packet headers
15187 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
15188 (UINT32_C(0x0) << 1)
15190 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15191 * present in the inner packet headers.
15192 * No VLAN PRI is selected for this configuration
15193 * if only one VLAN Tag is present in the inner
15196 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
15197 (UINT32_C(0x1) << 1)
15199 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15200 * are present in the inner packet headers
15202 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
15203 (UINT32_C(0x2) << 1)
15205 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
15206 (UINT32_C(0x3) << 1)
15207 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
15208 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
15210 * This field is used for selecting tunnel VLAN PRI value
15211 * based on whether one or two VLAN Tags are present in
15212 * the tunnel headers of tunneled packets. This selection
15213 * does not apply to non-tunneled packets.
15215 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
15217 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
15220 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
15221 * present in the tunnel packet headers
15223 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
15224 (UINT32_C(0x0) << 3)
15226 * Select outer VLAN Tag PRI when 2 VLAN Tags are
15227 * present in the tunnel packet headers.
15228 * No VLAN PRI is selected for this configuration
15229 * if only one VLAN Tag is present in the tunnel
15232 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
15233 (UINT32_C(0x1) << 3)
15235 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
15236 * are present in the tunnel packet headers
15238 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
15239 (UINT32_C(0x2) << 3)
15241 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
15242 (UINT32_C(0x3) << 3)
15243 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
15244 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
15246 * This field is used to provide default CoS value that
15247 * has been configured on this port.
15249 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
15251 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
15254 * This field is used in Output records to indicate that the output
15255 * is completely written to RAM. This field should be read as '1'
15256 * to indicate that the output has been completely written.
15257 * When writing a command completion or response to an internal processor,
15258 * the order of writes has to be such that this field is written last.
15263 /**************************
15264 * hwrm_port_mac_ptp_qcfg *
15265 **************************/
15268 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
15269 struct hwrm_port_mac_ptp_qcfg_input {
15270 /* The HWRM command request type. */
15273 * The completion ring to send the completion event on. This should
15274 * be the NQ ID returned from the `nq_alloc` HWRM command.
15276 uint16_t cmpl_ring;
15278 * The sequence ID is used by the driver for tracking multiple
15279 * commands. This ID is treated as opaque data by the firmware and
15280 * the value is returned in the `hwrm_resp_hdr` upon completion.
15284 * The target ID of the command:
15285 * * 0x0-0xFFF8 - The function ID
15286 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15287 * * 0xFFFD - Reserved for user-space HWRM interface
15290 uint16_t target_id;
15292 * A physical address pointer pointing to a host buffer that the
15293 * command's response data will be written. This can be either a host
15294 * physical address (HPA) or a guest physical address (GPA) and must
15295 * point to a physically contiguous block of memory.
15297 uint64_t resp_addr;
15298 /* Port ID of port that is being queried. */
15300 uint8_t unused_0[6];
15303 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
15304 struct hwrm_port_mac_ptp_qcfg_output {
15305 /* The specific error status for the command. */
15306 uint16_t error_code;
15307 /* The HWRM command request type. */
15309 /* The sequence ID from the original command. */
15311 /* The length of the response data in number of bytes. */
15314 * In this field, a number of PTP related flags
15315 * are used to indicate configured PTP capabilities.
15319 * When this bit is set to '1', the PTP related registers are
15320 * directly accessible by the host.
15322 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
15325 * When this bit is set to '1', the PTP information is accessible
15326 * via HWRM commands.
15328 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
15331 * When this bit is set to '1', the device supports one-step
15334 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
15336 uint8_t unused_0[3];
15337 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
15338 uint32_t rx_ts_reg_off_lower;
15339 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
15340 uint32_t rx_ts_reg_off_upper;
15341 /* Offset of the PTP register for the sequence ID for RX. */
15342 uint32_t rx_ts_reg_off_seq_id;
15343 /* Offset of the first PTP source ID for RX. */
15344 uint32_t rx_ts_reg_off_src_id_0;
15345 /* Offset of the second PTP source ID for RX. */
15346 uint32_t rx_ts_reg_off_src_id_1;
15347 /* Offset of the third PTP source ID for RX. */
15348 uint32_t rx_ts_reg_off_src_id_2;
15349 /* Offset of the domain ID for RX. */
15350 uint32_t rx_ts_reg_off_domain_id;
15351 /* Offset of the PTP FIFO register for RX. */
15352 uint32_t rx_ts_reg_off_fifo;
15353 /* Offset of the PTP advance FIFO register for RX. */
15354 uint32_t rx_ts_reg_off_fifo_adv;
15355 /* PTP timestamp granularity for RX. */
15356 uint32_t rx_ts_reg_off_granularity;
15357 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
15358 uint32_t tx_ts_reg_off_lower;
15359 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
15360 uint32_t tx_ts_reg_off_upper;
15361 /* Offset of the PTP register for the sequence ID for TX. */
15362 uint32_t tx_ts_reg_off_seq_id;
15363 /* Offset of the PTP FIFO register for TX. */
15364 uint32_t tx_ts_reg_off_fifo;
15365 /* PTP timestamp granularity for TX. */
15366 uint32_t tx_ts_reg_off_granularity;
15367 uint8_t unused_1[7];
15369 * This field is used in Output records to indicate that the output
15370 * is completely written to RAM. This field should be read as '1'
15371 * to indicate that the output has been completely written.
15372 * When writing a command completion or response to an internal processor,
15373 * the order of writes has to be such that this field is written last.
15378 /* Port Tx Statistics Formats */
15379 /* tx_port_stats (size:3264b/408B) */
15380 struct tx_port_stats {
15381 /* Total Number of 64 Bytes frames transmitted */
15382 uint64_t tx_64b_frames;
15383 /* Total Number of 65-127 Bytes frames transmitted */
15384 uint64_t tx_65b_127b_frames;
15385 /* Total Number of 128-255 Bytes frames transmitted */
15386 uint64_t tx_128b_255b_frames;
15387 /* Total Number of 256-511 Bytes frames transmitted */
15388 uint64_t tx_256b_511b_frames;
15389 /* Total Number of 512-1023 Bytes frames transmitted */
15390 uint64_t tx_512b_1023b_frames;
15391 /* Total Number of 1024-1518 Bytes frames transmitted */
15392 uint64_t tx_1024b_1518b_frames;
15394 * Total Number of each good VLAN (exludes FCS errors)
15395 * frame transmitted which is 1519 to 1522 bytes in length
15396 * inclusive (excluding framing bits but including FCS bytes).
15398 uint64_t tx_good_vlan_frames;
15399 /* Total Number of 1519-2047 Bytes frames transmitted */
15400 uint64_t tx_1519b_2047b_frames;
15401 /* Total Number of 2048-4095 Bytes frames transmitted */
15402 uint64_t tx_2048b_4095b_frames;
15403 /* Total Number of 4096-9216 Bytes frames transmitted */
15404 uint64_t tx_4096b_9216b_frames;
15405 /* Total Number of 9217-16383 Bytes frames transmitted */
15406 uint64_t tx_9217b_16383b_frames;
15407 /* Total Number of good frames transmitted */
15408 uint64_t tx_good_frames;
15409 /* Total Number of frames transmitted */
15410 uint64_t tx_total_frames;
15411 /* Total number of unicast frames transmitted */
15412 uint64_t tx_ucast_frames;
15413 /* Total number of multicast frames transmitted */
15414 uint64_t tx_mcast_frames;
15415 /* Total number of broadcast frames transmitted */
15416 uint64_t tx_bcast_frames;
15417 /* Total number of PAUSE control frames transmitted */
15418 uint64_t tx_pause_frames;
15420 * Total number of PFC/per-priority PAUSE
15421 * control frames transmitted
15423 uint64_t tx_pfc_frames;
15424 /* Total number of jabber frames transmitted */
15425 uint64_t tx_jabber_frames;
15426 /* Total number of frames transmitted with FCS error */
15427 uint64_t tx_fcs_err_frames;
15428 /* Total number of control frames transmitted */
15429 uint64_t tx_control_frames;
15430 /* Total number of over-sized frames transmitted */
15431 uint64_t tx_oversz_frames;
15432 /* Total number of frames with single deferral */
15433 uint64_t tx_single_dfrl_frames;
15434 /* Total number of frames with multiple deferrals */
15435 uint64_t tx_multi_dfrl_frames;
15436 /* Total number of frames with single collision */
15437 uint64_t tx_single_coll_frames;
15438 /* Total number of frames with multiple collisions */
15439 uint64_t tx_multi_coll_frames;
15440 /* Total number of frames with late collisions */
15441 uint64_t tx_late_coll_frames;
15442 /* Total number of frames with excessive collisions */
15443 uint64_t tx_excessive_coll_frames;
15444 /* Total number of fragmented frames transmitted */
15445 uint64_t tx_frag_frames;
15446 /* Total number of transmit errors */
15448 /* Total number of single VLAN tagged frames transmitted */
15449 uint64_t tx_tagged_frames;
15450 /* Total number of double VLAN tagged frames transmitted */
15451 uint64_t tx_dbl_tagged_frames;
15452 /* Total number of runt frames transmitted */
15453 uint64_t tx_runt_frames;
15454 /* Total number of TX FIFO under runs */
15455 uint64_t tx_fifo_underruns;
15457 * Total number of PFC frames with PFC enabled bit for
15458 * Pri 0 transmitted
15460 uint64_t tx_pfc_ena_frames_pri0;
15462 * Total number of PFC frames with PFC enabled bit for
15463 * Pri 1 transmitted
15465 uint64_t tx_pfc_ena_frames_pri1;
15467 * Total number of PFC frames with PFC enabled bit for
15468 * Pri 2 transmitted
15470 uint64_t tx_pfc_ena_frames_pri2;
15472 * Total number of PFC frames with PFC enabled bit for
15473 * Pri 3 transmitted
15475 uint64_t tx_pfc_ena_frames_pri3;
15477 * Total number of PFC frames with PFC enabled bit for
15478 * Pri 4 transmitted
15480 uint64_t tx_pfc_ena_frames_pri4;
15482 * Total number of PFC frames with PFC enabled bit for
15483 * Pri 5 transmitted
15485 uint64_t tx_pfc_ena_frames_pri5;
15487 * Total number of PFC frames with PFC enabled bit for
15488 * Pri 6 transmitted
15490 uint64_t tx_pfc_ena_frames_pri6;
15492 * Total number of PFC frames with PFC enabled bit for
15493 * Pri 7 transmitted
15495 uint64_t tx_pfc_ena_frames_pri7;
15496 /* Total number of EEE LPI Events on TX */
15497 uint64_t tx_eee_lpi_events;
15498 /* EEE LPI Duration Counter on TX */
15499 uint64_t tx_eee_lpi_duration;
15501 * Total number of Link Level Flow Control (LLFC) messages
15504 uint64_t tx_llfc_logical_msgs;
15505 /* Total number of HCFC messages transmitted */
15506 uint64_t tx_hcfc_msgs;
15507 /* Total number of TX collisions */
15508 uint64_t tx_total_collisions;
15509 /* Total number of transmitted bytes */
15511 /* Total number of end-to-end HOL frames */
15512 uint64_t tx_xthol_frames;
15513 /* Total Tx Drops per Port reported by STATS block */
15514 uint64_t tx_stat_discard;
15515 /* Total Tx Error Drops per Port reported by STATS block */
15516 uint64_t tx_stat_error;
15519 /* Port Rx Statistics Formats */
15520 /* rx_port_stats (size:4224b/528B) */
15521 struct rx_port_stats {
15522 /* Total Number of 64 Bytes frames received */
15523 uint64_t rx_64b_frames;
15524 /* Total Number of 65-127 Bytes frames received */
15525 uint64_t rx_65b_127b_frames;
15526 /* Total Number of 128-255 Bytes frames received */
15527 uint64_t rx_128b_255b_frames;
15528 /* Total Number of 256-511 Bytes frames received */
15529 uint64_t rx_256b_511b_frames;
15530 /* Total Number of 512-1023 Bytes frames received */
15531 uint64_t rx_512b_1023b_frames;
15532 /* Total Number of 1024-1518 Bytes frames received */
15533 uint64_t rx_1024b_1518b_frames;
15535 * Total Number of each good VLAN (exludes FCS errors)
15536 * frame received which is 1519 to 1522 bytes in length
15537 * inclusive (excluding framing bits but including FCS bytes).
15539 uint64_t rx_good_vlan_frames;
15540 /* Total Number of 1519-2047 Bytes frames received */
15541 uint64_t rx_1519b_2047b_frames;
15542 /* Total Number of 2048-4095 Bytes frames received */
15543 uint64_t rx_2048b_4095b_frames;
15544 /* Total Number of 4096-9216 Bytes frames received */
15545 uint64_t rx_4096b_9216b_frames;
15546 /* Total Number of 9217-16383 Bytes frames received */
15547 uint64_t rx_9217b_16383b_frames;
15548 /* Total number of frames received */
15549 uint64_t rx_total_frames;
15550 /* Total number of unicast frames received */
15551 uint64_t rx_ucast_frames;
15552 /* Total number of multicast frames received */
15553 uint64_t rx_mcast_frames;
15554 /* Total number of broadcast frames received */
15555 uint64_t rx_bcast_frames;
15556 /* Total number of received frames with FCS error */
15557 uint64_t rx_fcs_err_frames;
15558 /* Total number of control frames received */
15559 uint64_t rx_ctrl_frames;
15560 /* Total number of PAUSE frames received */
15561 uint64_t rx_pause_frames;
15562 /* Total number of PFC frames received */
15563 uint64_t rx_pfc_frames;
15565 * Total number of frames received with an unsupported
15568 uint64_t rx_unsupported_opcode_frames;
15570 * Total number of frames received with an unsupported
15571 * DA for pause and PFC
15573 uint64_t rx_unsupported_da_pausepfc_frames;
15574 /* Total number of frames received with an unsupported SA */
15575 uint64_t rx_wrong_sa_frames;
15576 /* Total number of received packets with alignment error */
15577 uint64_t rx_align_err_frames;
15578 /* Total number of received frames with out-of-range length */
15579 uint64_t rx_oor_len_frames;
15580 /* Total number of received frames with error termination */
15581 uint64_t rx_code_err_frames;
15583 * Total number of received frames with a false carrier is
15584 * detected during idle, as defined by RX_ER samples active
15585 * and RXD is 0xE. The event is reported along with the
15586 * statistics generated on the next received frame. Only
15587 * one false carrier condition can be detected and logged
15590 * Carrier event, valid for 10M/100M speed modes only.
15592 uint64_t rx_false_carrier_frames;
15593 /* Total number of over-sized frames received */
15594 uint64_t rx_ovrsz_frames;
15595 /* Total number of jabber packets received */
15596 uint64_t rx_jbr_frames;
15597 /* Total number of received frames with MTU error */
15598 uint64_t rx_mtu_err_frames;
15599 /* Total number of received frames with CRC match */
15600 uint64_t rx_match_crc_frames;
15601 /* Total number of frames received promiscuously */
15602 uint64_t rx_promiscuous_frames;
15604 * Total number of received frames with one or two VLAN
15607 uint64_t rx_tagged_frames;
15608 /* Total number of received frames with two VLAN tags */
15609 uint64_t rx_double_tagged_frames;
15610 /* Total number of truncated frames received */
15611 uint64_t rx_trunc_frames;
15612 /* Total number of good frames (without errors) received */
15613 uint64_t rx_good_frames;
15615 * Total number of received PFC frames with transition from
15616 * XON to XOFF on Pri 0
15618 uint64_t rx_pfc_xon2xoff_frames_pri0;
15620 * Total number of received PFC frames with transition from
15621 * XON to XOFF on Pri 1
15623 uint64_t rx_pfc_xon2xoff_frames_pri1;
15625 * Total number of received PFC frames with transition from
15626 * XON to XOFF on Pri 2
15628 uint64_t rx_pfc_xon2xoff_frames_pri2;
15630 * Total number of received PFC frames with transition from
15631 * XON to XOFF on Pri 3
15633 uint64_t rx_pfc_xon2xoff_frames_pri3;
15635 * Total number of received PFC frames with transition from
15636 * XON to XOFF on Pri 4
15638 uint64_t rx_pfc_xon2xoff_frames_pri4;
15640 * Total number of received PFC frames with transition from
15641 * XON to XOFF on Pri 5
15643 uint64_t rx_pfc_xon2xoff_frames_pri5;
15645 * Total number of received PFC frames with transition from
15646 * XON to XOFF on Pri 6
15648 uint64_t rx_pfc_xon2xoff_frames_pri6;
15650 * Total number of received PFC frames with transition from
15651 * XON to XOFF on Pri 7
15653 uint64_t rx_pfc_xon2xoff_frames_pri7;
15655 * Total number of received PFC frames with PFC enabled
15658 uint64_t rx_pfc_ena_frames_pri0;
15660 * Total number of received PFC frames with PFC enabled
15663 uint64_t rx_pfc_ena_frames_pri1;
15665 * Total number of received PFC frames with PFC enabled
15668 uint64_t rx_pfc_ena_frames_pri2;
15670 * Total number of received PFC frames with PFC enabled
15673 uint64_t rx_pfc_ena_frames_pri3;
15675 * Total number of received PFC frames with PFC enabled
15678 uint64_t rx_pfc_ena_frames_pri4;
15680 * Total number of received PFC frames with PFC enabled
15683 uint64_t rx_pfc_ena_frames_pri5;
15685 * Total number of received PFC frames with PFC enabled
15688 uint64_t rx_pfc_ena_frames_pri6;
15690 * Total number of received PFC frames with PFC enabled
15693 uint64_t rx_pfc_ena_frames_pri7;
15694 /* Total Number of frames received with SCH CRC error */
15695 uint64_t rx_sch_crc_err_frames;
15696 /* Total Number of under-sized frames received */
15697 uint64_t rx_undrsz_frames;
15698 /* Total Number of fragmented frames received */
15699 uint64_t rx_frag_frames;
15700 /* Total number of RX EEE LPI Events */
15701 uint64_t rx_eee_lpi_events;
15702 /* EEE LPI Duration Counter on RX */
15703 uint64_t rx_eee_lpi_duration;
15705 * Total number of physical type Link Level Flow Control
15706 * (LLFC) messages received
15708 uint64_t rx_llfc_physical_msgs;
15710 * Total number of logical type Link Level Flow Control
15711 * (LLFC) messages received
15713 uint64_t rx_llfc_logical_msgs;
15715 * Total number of logical type Link Level Flow Control
15716 * (LLFC) messages received with CRC error
15718 uint64_t rx_llfc_msgs_with_crc_err;
15719 /* Total number of HCFC messages received */
15720 uint64_t rx_hcfc_msgs;
15721 /* Total number of HCFC messages received with CRC error */
15722 uint64_t rx_hcfc_msgs_with_crc_err;
15723 /* Total number of received bytes */
15725 /* Total number of bytes received in runt frames */
15726 uint64_t rx_runt_bytes;
15727 /* Total number of runt frames received */
15728 uint64_t rx_runt_frames;
15729 /* Total Rx Discards per Port reported by STATS block */
15730 uint64_t rx_stat_discard;
15731 uint64_t rx_stat_err;
15734 /********************
15735 * hwrm_port_qstats *
15736 ********************/
15739 /* hwrm_port_qstats_input (size:320b/40B) */
15740 struct hwrm_port_qstats_input {
15741 /* The HWRM command request type. */
15744 * The completion ring to send the completion event on. This should
15745 * be the NQ ID returned from the `nq_alloc` HWRM command.
15747 uint16_t cmpl_ring;
15749 * The sequence ID is used by the driver for tracking multiple
15750 * commands. This ID is treated as opaque data by the firmware and
15751 * the value is returned in the `hwrm_resp_hdr` upon completion.
15755 * The target ID of the command:
15756 * * 0x0-0xFFF8 - The function ID
15757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15758 * * 0xFFFD - Reserved for user-space HWRM interface
15761 uint16_t target_id;
15763 * A physical address pointer pointing to a host buffer that the
15764 * command's response data will be written. This can be either a host
15765 * physical address (HPA) or a guest physical address (GPA) and must
15766 * point to a physically contiguous block of memory.
15768 uint64_t resp_addr;
15769 /* Port ID of port that is being queried. */
15771 uint8_t unused_0[6];
15773 * This is the host address where
15774 * Tx port statistics will be stored
15776 uint64_t tx_stat_host_addr;
15778 * This is the host address where
15779 * Rx port statistics will be stored
15781 uint64_t rx_stat_host_addr;
15784 /* hwrm_port_qstats_output (size:128b/16B) */
15785 struct hwrm_port_qstats_output {
15786 /* The specific error status for the command. */
15787 uint16_t error_code;
15788 /* The HWRM command request type. */
15790 /* The sequence ID from the original command. */
15792 /* The length of the response data in number of bytes. */
15794 /* The size of TX port statistics block in bytes. */
15795 uint16_t tx_stat_size;
15796 /* The size of RX port statistics block in bytes. */
15797 uint16_t rx_stat_size;
15798 uint8_t unused_0[3];
15800 * This field is used in Output records to indicate that the output
15801 * is completely written to RAM. This field should be read as '1'
15802 * to indicate that the output has been completely written.
15803 * When writing a command completion or response to an internal processor,
15804 * the order of writes has to be such that this field is written last.
15809 /* Port Tx Statistics extended Formats */
15810 /* tx_port_stats_ext (size:2048b/256B) */
15811 struct tx_port_stats_ext {
15812 /* Total number of tx bytes count on cos queue 0 */
15813 uint64_t tx_bytes_cos0;
15814 /* Total number of tx bytes count on cos queue 1 */
15815 uint64_t tx_bytes_cos1;
15816 /* Total number of tx bytes count on cos queue 2 */
15817 uint64_t tx_bytes_cos2;
15818 /* Total number of tx bytes count on cos queue 3 */
15819 uint64_t tx_bytes_cos3;
15820 /* Total number of tx bytes count on cos queue 4 */
15821 uint64_t tx_bytes_cos4;
15822 /* Total number of tx bytes count on cos queue 5 */
15823 uint64_t tx_bytes_cos5;
15824 /* Total number of tx bytes count on cos queue 6 */
15825 uint64_t tx_bytes_cos6;
15826 /* Total number of tx bytes count on cos queue 7 */
15827 uint64_t tx_bytes_cos7;
15828 /* Total number of tx packets count on cos queue 0 */
15829 uint64_t tx_packets_cos0;
15830 /* Total number of tx packets count on cos queue 1 */
15831 uint64_t tx_packets_cos1;
15832 /* Total number of tx packets count on cos queue 2 */
15833 uint64_t tx_packets_cos2;
15834 /* Total number of tx packets count on cos queue 3 */
15835 uint64_t tx_packets_cos3;
15836 /* Total number of tx packets count on cos queue 4 */
15837 uint64_t tx_packets_cos4;
15838 /* Total number of tx packets count on cos queue 5 */
15839 uint64_t tx_packets_cos5;
15840 /* Total number of tx packets count on cos queue 6 */
15841 uint64_t tx_packets_cos6;
15842 /* Total number of tx packets count on cos queue 7 */
15843 uint64_t tx_packets_cos7;
15844 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15845 uint64_t pfc_pri0_tx_duration_us;
15846 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15847 uint64_t pfc_pri0_tx_transitions;
15848 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15849 uint64_t pfc_pri1_tx_duration_us;
15850 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15851 uint64_t pfc_pri1_tx_transitions;
15852 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15853 uint64_t pfc_pri2_tx_duration_us;
15854 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15855 uint64_t pfc_pri2_tx_transitions;
15856 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15857 uint64_t pfc_pri3_tx_duration_us;
15858 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15859 uint64_t pfc_pri3_tx_transitions;
15860 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15861 uint64_t pfc_pri4_tx_duration_us;
15862 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15863 uint64_t pfc_pri4_tx_transitions;
15864 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15865 uint64_t pfc_pri5_tx_duration_us;
15866 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15867 uint64_t pfc_pri5_tx_transitions;
15868 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15869 uint64_t pfc_pri6_tx_duration_us;
15870 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15871 uint64_t pfc_pri6_tx_transitions;
15872 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15873 uint64_t pfc_pri7_tx_duration_us;
15874 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15875 uint64_t pfc_pri7_tx_transitions;
15878 /* Port Rx Statistics extended Formats */
15879 /* rx_port_stats_ext (size:3648b/456B) */
15880 struct rx_port_stats_ext {
15881 /* Number of times link state changed to down */
15882 uint64_t link_down_events;
15883 /* Number of times the idle rings with pause bit are found */
15884 uint64_t continuous_pause_events;
15885 /* Number of times the active rings pause bit resumed back */
15886 uint64_t resume_pause_events;
15887 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
15888 uint64_t continuous_roce_pause_events;
15889 /* Number of times, the ROCE cos queue PFC is enabled back */
15890 uint64_t resume_roce_pause_events;
15891 /* Total number of rx bytes count on cos queue 0 */
15892 uint64_t rx_bytes_cos0;
15893 /* Total number of rx bytes count on cos queue 1 */
15894 uint64_t rx_bytes_cos1;
15895 /* Total number of rx bytes count on cos queue 2 */
15896 uint64_t rx_bytes_cos2;
15897 /* Total number of rx bytes count on cos queue 3 */
15898 uint64_t rx_bytes_cos3;
15899 /* Total number of rx bytes count on cos queue 4 */
15900 uint64_t rx_bytes_cos4;
15901 /* Total number of rx bytes count on cos queue 5 */
15902 uint64_t rx_bytes_cos5;
15903 /* Total number of rx bytes count on cos queue 6 */
15904 uint64_t rx_bytes_cos6;
15905 /* Total number of rx bytes count on cos queue 7 */
15906 uint64_t rx_bytes_cos7;
15907 /* Total number of rx packets count on cos queue 0 */
15908 uint64_t rx_packets_cos0;
15909 /* Total number of rx packets count on cos queue 1 */
15910 uint64_t rx_packets_cos1;
15911 /* Total number of rx packets count on cos queue 2 */
15912 uint64_t rx_packets_cos2;
15913 /* Total number of rx packets count on cos queue 3 */
15914 uint64_t rx_packets_cos3;
15915 /* Total number of rx packets count on cos queue 4 */
15916 uint64_t rx_packets_cos4;
15917 /* Total number of rx packets count on cos queue 5 */
15918 uint64_t rx_packets_cos5;
15919 /* Total number of rx packets count on cos queue 6 */
15920 uint64_t rx_packets_cos6;
15921 /* Total number of rx packets count on cos queue 7 */
15922 uint64_t rx_packets_cos7;
15923 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
15924 uint64_t pfc_pri0_rx_duration_us;
15925 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
15926 uint64_t pfc_pri0_rx_transitions;
15927 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
15928 uint64_t pfc_pri1_rx_duration_us;
15929 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
15930 uint64_t pfc_pri1_rx_transitions;
15931 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
15932 uint64_t pfc_pri2_rx_duration_us;
15933 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
15934 uint64_t pfc_pri2_rx_transitions;
15935 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
15936 uint64_t pfc_pri3_rx_duration_us;
15937 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
15938 uint64_t pfc_pri3_rx_transitions;
15939 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
15940 uint64_t pfc_pri4_rx_duration_us;
15941 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
15942 uint64_t pfc_pri4_rx_transitions;
15943 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
15944 uint64_t pfc_pri5_rx_duration_us;
15945 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
15946 uint64_t pfc_pri5_rx_transitions;
15947 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
15948 uint64_t pfc_pri6_rx_duration_us;
15949 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
15950 uint64_t pfc_pri6_rx_transitions;
15951 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
15952 uint64_t pfc_pri7_rx_duration_us;
15953 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
15954 uint64_t pfc_pri7_rx_transitions;
15955 /* Total number of received bits */
15957 /* The number of events where the port receive buffer was over 85% full */
15958 uint64_t rx_buffer_passed_threshold;
15960 * The number of symbol errors that wasn't corrected by FEC correction
15963 uint64_t rx_pcs_symbol_err;
15964 /* The number of corrected bits on the port according to active FEC */
15965 uint64_t rx_corrected_bits;
15966 /* Total number of rx discard bytes count on cos queue 0 */
15967 uint64_t rx_discard_bytes_cos0;
15968 /* Total number of rx discard bytes count on cos queue 1 */
15969 uint64_t rx_discard_bytes_cos1;
15970 /* Total number of rx discard bytes count on cos queue 2 */
15971 uint64_t rx_discard_bytes_cos2;
15972 /* Total number of rx discard bytes count on cos queue 3 */
15973 uint64_t rx_discard_bytes_cos3;
15974 /* Total number of rx discard bytes count on cos queue 4 */
15975 uint64_t rx_discard_bytes_cos4;
15976 /* Total number of rx discard bytes count on cos queue 5 */
15977 uint64_t rx_discard_bytes_cos5;
15978 /* Total number of rx discard bytes count on cos queue 6 */
15979 uint64_t rx_discard_bytes_cos6;
15980 /* Total number of rx discard bytes count on cos queue 7 */
15981 uint64_t rx_discard_bytes_cos7;
15982 /* Total number of rx discard packets count on cos queue 0 */
15983 uint64_t rx_discard_packets_cos0;
15984 /* Total number of rx discard packets count on cos queue 1 */
15985 uint64_t rx_discard_packets_cos1;
15986 /* Total number of rx discard packets count on cos queue 2 */
15987 uint64_t rx_discard_packets_cos2;
15988 /* Total number of rx discard packets count on cos queue 3 */
15989 uint64_t rx_discard_packets_cos3;
15990 /* Total number of rx discard packets count on cos queue 4 */
15991 uint64_t rx_discard_packets_cos4;
15992 /* Total number of rx discard packets count on cos queue 5 */
15993 uint64_t rx_discard_packets_cos5;
15994 /* Total number of rx discard packets count on cos queue 6 */
15995 uint64_t rx_discard_packets_cos6;
15996 /* Total number of rx discard packets count on cos queue 7 */
15997 uint64_t rx_discard_packets_cos7;
16000 /************************
16001 * hwrm_port_qstats_ext *
16002 ************************/
16005 /* hwrm_port_qstats_ext_input (size:320b/40B) */
16006 struct hwrm_port_qstats_ext_input {
16007 /* The HWRM command request type. */
16010 * The completion ring to send the completion event on. This should
16011 * be the NQ ID returned from the `nq_alloc` HWRM command.
16013 uint16_t cmpl_ring;
16015 * The sequence ID is used by the driver for tracking multiple
16016 * commands. This ID is treated as opaque data by the firmware and
16017 * the value is returned in the `hwrm_resp_hdr` upon completion.
16021 * The target ID of the command:
16022 * * 0x0-0xFFF8 - The function ID
16023 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16024 * * 0xFFFD - Reserved for user-space HWRM interface
16027 uint16_t target_id;
16029 * A physical address pointer pointing to a host buffer that the
16030 * command's response data will be written. This can be either a host
16031 * physical address (HPA) or a guest physical address (GPA) and must
16032 * point to a physically contiguous block of memory.
16034 uint64_t resp_addr;
16035 /* Port ID of port that is being queried. */
16038 * The size of TX port extended
16039 * statistics block in bytes.
16041 uint16_t tx_stat_size;
16043 * The size of RX port extended
16044 * statistics block in bytes
16046 uint16_t rx_stat_size;
16047 uint8_t unused_0[2];
16049 * This is the host address where
16050 * Tx port statistics will be stored
16052 uint64_t tx_stat_host_addr;
16054 * This is the host address where
16055 * Rx port statistics will be stored
16057 uint64_t rx_stat_host_addr;
16060 /* hwrm_port_qstats_ext_output (size:128b/16B) */
16061 struct hwrm_port_qstats_ext_output {
16062 /* The specific error status for the command. */
16063 uint16_t error_code;
16064 /* The HWRM command request type. */
16066 /* The sequence ID from the original command. */
16068 /* The length of the response data in number of bytes. */
16070 /* The size of TX port statistics block in bytes. */
16071 uint16_t tx_stat_size;
16072 /* The size of RX port statistics block in bytes. */
16073 uint16_t rx_stat_size;
16074 /* Total number of active cos queues available. */
16075 uint16_t total_active_cos_queues;
16078 * If set to 1, then this field indicates that clear
16079 * roce specific counters is supported.
16081 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
16084 * This field is used in Output records to indicate that the output
16085 * is completely written to RAM. This field should be read as '1'
16086 * to indicate that the output has been completely written.
16087 * When writing a command completion or response to an internal processor,
16088 * the order of writes has to be such that this field is written last.
16093 /*************************
16094 * hwrm_port_lpbk_qstats *
16095 *************************/
16098 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
16099 struct hwrm_port_lpbk_qstats_input {
16100 /* The HWRM command request type. */
16103 * The completion ring to send the completion event on. This should
16104 * be the NQ ID returned from the `nq_alloc` HWRM command.
16106 uint16_t cmpl_ring;
16108 * The sequence ID is used by the driver for tracking multiple
16109 * commands. This ID is treated as opaque data by the firmware and
16110 * the value is returned in the `hwrm_resp_hdr` upon completion.
16114 * The target ID of the command:
16115 * * 0x0-0xFFF8 - The function ID
16116 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16117 * * 0xFFFD - Reserved for user-space HWRM interface
16120 uint16_t target_id;
16122 * A physical address pointer pointing to a host buffer that the
16123 * command's response data will be written. This can be either a host
16124 * physical address (HPA) or a guest physical address (GPA) and must
16125 * point to a physically contiguous block of memory.
16127 uint64_t resp_addr;
16130 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
16131 struct hwrm_port_lpbk_qstats_output {
16132 /* The specific error status for the command. */
16133 uint16_t error_code;
16134 /* The HWRM command request type. */
16136 /* The sequence ID from the original command. */
16138 /* The length of the response data in number of bytes. */
16140 /* Number of transmitted unicast frames */
16141 uint64_t lpbk_ucast_frames;
16142 /* Number of transmitted multicast frames */
16143 uint64_t lpbk_mcast_frames;
16144 /* Number of transmitted broadcast frames */
16145 uint64_t lpbk_bcast_frames;
16146 /* Number of transmitted bytes for unicast traffic */
16147 uint64_t lpbk_ucast_bytes;
16148 /* Number of transmitted bytes for multicast traffic */
16149 uint64_t lpbk_mcast_bytes;
16150 /* Number of transmitted bytes for broadcast traffic */
16151 uint64_t lpbk_bcast_bytes;
16152 /* Total Tx Drops for loopback traffic reported by STATS block */
16153 uint64_t tx_stat_discard;
16154 /* Total Tx Error Drops for loopback traffic reported by STATS block */
16155 uint64_t tx_stat_error;
16156 /* Total Rx Drops for loopback traffic reported by STATS block */
16157 uint64_t rx_stat_discard;
16158 /* Total Rx Error Drops for loopback traffic reported by STATS block */
16159 uint64_t rx_stat_error;
16160 uint8_t unused_0[7];
16162 * This field is used in Output records to indicate that the output
16163 * is completely written to RAM. This field should be read as '1'
16164 * to indicate that the output has been completely written.
16165 * When writing a command completion or response to an internal processor,
16166 * the order of writes has to be such that this field is written last.
16171 /***********************
16172 * hwrm_port_clr_stats *
16173 ***********************/
16176 /* hwrm_port_clr_stats_input (size:192b/24B) */
16177 struct hwrm_port_clr_stats_input {
16178 /* The HWRM command request type. */
16181 * The completion ring to send the completion event on. This should
16182 * be the NQ ID returned from the `nq_alloc` HWRM command.
16184 uint16_t cmpl_ring;
16186 * The sequence ID is used by the driver for tracking multiple
16187 * commands. This ID is treated as opaque data by the firmware and
16188 * the value is returned in the `hwrm_resp_hdr` upon completion.
16192 * The target ID of the command:
16193 * * 0x0-0xFFF8 - The function ID
16194 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16195 * * 0xFFFD - Reserved for user-space HWRM interface
16198 uint16_t target_id;
16200 * A physical address pointer pointing to a host buffer that the
16201 * command's response data will be written. This can be either a host
16202 * physical address (HPA) or a guest physical address (GPA) and must
16203 * point to a physically contiguous block of memory.
16205 uint64_t resp_addr;
16206 /* Port ID of port that is being queried. */
16210 * If set to 1, then this field indicates clear the following RoCE
16211 * specific counters.
16212 * RoCE associated TX/RX cos counters
16213 * CNP associated TX/RX cos counters
16214 * RoCE/CNP specific TX/RX flow counters
16215 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
16216 * This flag is honored only when RoCE is enabled on that port.
16218 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
16219 uint8_t unused_0[5];
16222 /* hwrm_port_clr_stats_output (size:128b/16B) */
16223 struct hwrm_port_clr_stats_output {
16224 /* The specific error status for the command. */
16225 uint16_t error_code;
16226 /* The HWRM command request type. */
16228 /* The sequence ID from the original command. */
16230 /* The length of the response data in number of bytes. */
16232 uint8_t unused_0[7];
16234 * This field is used in Output records to indicate that the output
16235 * is completely written to RAM. This field should be read as '1'
16236 * to indicate that the output has been completely written.
16237 * When writing a command completion or response to an internal processor,
16238 * the order of writes has to be such that this field is written last.
16243 /***********************
16244 * hwrm_port_phy_qcaps *
16245 ***********************/
16248 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
16249 struct hwrm_port_phy_qcaps_input {
16250 /* The HWRM command request type. */
16253 * The completion ring to send the completion event on. This should
16254 * be the NQ ID returned from the `nq_alloc` HWRM command.
16256 uint16_t cmpl_ring;
16258 * The sequence ID is used by the driver for tracking multiple
16259 * commands. This ID is treated as opaque data by the firmware and
16260 * the value is returned in the `hwrm_resp_hdr` upon completion.
16264 * The target ID of the command:
16265 * * 0x0-0xFFF8 - The function ID
16266 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16267 * * 0xFFFD - Reserved for user-space HWRM interface
16270 uint16_t target_id;
16272 * A physical address pointer pointing to a host buffer that the
16273 * command's response data will be written. This can be either a host
16274 * physical address (HPA) or a guest physical address (GPA) and must
16275 * point to a physically contiguous block of memory.
16277 uint64_t resp_addr;
16278 /* Port ID of port that is being queried. */
16280 uint8_t unused_0[6];
16283 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
16284 struct hwrm_port_phy_qcaps_output {
16285 /* The specific error status for the command. */
16286 uint16_t error_code;
16287 /* The HWRM command request type. */
16289 /* The sequence ID from the original command. */
16291 /* The length of the response data in number of bytes. */
16293 /* PHY capability flags */
16296 * If set to 1, then this field indicates that the
16297 * link is capable of supporting EEE.
16299 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
16302 * If set to 1, then this field indicates that the
16303 * PHY is capable of supporting external loopback.
16305 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
16308 * If set to 1, then this field indicates that the
16309 * PHY is capable of supporting loopback in autoneg mode.
16311 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
16314 * Indicates if the configuration of shared PHY settings is supported.
16315 * In cases where a physical port is shared by multiple functions
16316 * (e.g. NPAR, multihost, etc), the configuration of PHY
16317 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
16318 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
16320 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
16323 * Reserved field. The HWRM shall set this field to 0.
16324 * An HWRM client shall ignore this field.
16326 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
16328 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
16329 /* Number of front panel ports for this device. */
16331 /* Not supported or unknown */
16332 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
16333 /* single port device */
16334 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
16335 /* 2-port device */
16336 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
16337 /* 3-port device */
16338 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
16339 /* 4-port device */
16340 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
16341 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
16342 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
16344 * This is a bit mask to indicate what speeds are supported
16345 * as forced speeds on this link.
16346 * For each speed that can be forced on this link, the
16347 * corresponding mask bit shall be set to '1'.
16349 uint16_t supported_speeds_force_mode;
16350 /* 100Mb link speed (Half-duplex) */
16351 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
16353 /* 100Mb link speed (Full-duplex) */
16354 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
16356 /* 1Gb link speed (Half-duplex) */
16357 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
16359 /* 1Gb link speed (Full-duplex) */
16360 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
16362 /* 2Gb link speed */
16363 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
16365 /* 25Gb link speed */
16366 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
16368 /* 10Gb link speed */
16369 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
16371 /* 20Gb link speed */
16372 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
16374 /* 25Gb link speed */
16375 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
16377 /* 40Gb link speed */
16378 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
16380 /* 50Gb link speed */
16381 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
16383 /* 100Gb link speed */
16384 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
16386 /* 10Mb link speed (Half-duplex) */
16387 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
16389 /* 10Mb link speed (Full-duplex) */
16390 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
16392 /* 200Gb link speed */
16393 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
16396 * This is a bit mask to indicate what speeds are supported
16397 * for autonegotiation on this link.
16398 * For each speed that can be autonegotiated on this link, the
16399 * corresponding mask bit shall be set to '1'.
16401 uint16_t supported_speeds_auto_mode;
16402 /* 100Mb link speed (Half-duplex) */
16403 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
16405 /* 100Mb link speed (Full-duplex) */
16406 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
16408 /* 1Gb link speed (Half-duplex) */
16409 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
16411 /* 1Gb link speed (Full-duplex) */
16412 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
16414 /* 2Gb link speed */
16415 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
16417 /* 25Gb link speed */
16418 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
16420 /* 10Gb link speed */
16421 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
16423 /* 20Gb link speed */
16424 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
16426 /* 25Gb link speed */
16427 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
16429 /* 40Gb link speed */
16430 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
16432 /* 50Gb link speed */
16433 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
16435 /* 100Gb link speed */
16436 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
16438 /* 10Mb link speed (Half-duplex) */
16439 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
16441 /* 10Mb link speed (Full-duplex) */
16442 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
16444 /* 200Gb link speed */
16445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
16448 * This is a bit mask to indicate what speeds are supported
16449 * for EEE on this link.
16450 * For each speed that can be autonegotiated when EEE is enabled
16451 * on this link, the corresponding mask bit shall be set to '1'.
16452 * This field is only valid when the eee_suppotred is set to '1'.
16454 uint16_t supported_speeds_eee_mode;
16456 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
16458 /* 100Mb link speed (Full-duplex) */
16459 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
16462 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
16464 /* 1Gb link speed (Full-duplex) */
16465 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
16468 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
16471 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
16473 /* 10Gb link speed */
16474 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
16476 uint32_t tx_lpi_timer_low;
16478 * The lowest value of TX LPI timer that can be set on this link
16479 * when EEE is enabled. This value is in microseconds.
16480 * This field is valid only when_eee_supported is set to '1'.
16482 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
16484 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
16486 * Reserved field. The HWRM shall set this field to 0.
16487 * An HWRM client shall ignore this field.
16489 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
16490 UINT32_C(0xff000000)
16491 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
16492 uint32_t valid_tx_lpi_timer_high;
16494 * The highest value of TX LPI timer that can be set on this link
16495 * when EEE is enabled. This value is in microseconds.
16496 * This field is valid only when_eee_supported is set to '1'.
16498 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
16500 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
16502 * This field is used in Output records to indicate that the output
16503 * is completely written to RAM. This field should be read as '1'
16504 * to indicate that the output has been completely written.
16505 * When writing a command completion or response to an internal processor,
16506 * the order of writes has to be such that this field is written last.
16508 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
16509 UINT32_C(0xff000000)
16510 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
16513 /****************************
16514 * hwrm_port_phy_mdio_write *
16515 ****************************/
16518 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
16519 struct hwrm_port_phy_mdio_write_input {
16520 /* The HWRM command request type. */
16523 * The completion ring to send the completion event on. This should
16524 * be the NQ ID returned from the `nq_alloc` HWRM command.
16526 uint16_t cmpl_ring;
16528 * The sequence ID is used by the driver for tracking multiple
16529 * commands. This ID is treated as opaque data by the firmware and
16530 * the value is returned in the `hwrm_resp_hdr` upon completion.
16534 * The target ID of the command:
16535 * * 0x0-0xFFF8 - The function ID
16536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16537 * * 0xFFFD - Reserved for user-space HWRM interface
16540 uint16_t target_id;
16542 * A physical address pointer pointing to a host buffer that the
16543 * command's response data will be written. This can be either a host
16544 * physical address (HPA) or a guest physical address (GPA) and must
16545 * point to a physically contiguous block of memory.
16547 uint64_t resp_addr;
16548 /* Reserved for future use. */
16549 uint32_t unused_0[2];
16550 /* Port ID of port. */
16552 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16554 /* 8-bit device address. */
16556 /* 16-bit register address. */
16558 /* 16-bit register data. */
16561 * When this bit is set to 1 a Clause 45 mdio access is done.
16562 * when this bit is set to 0 a Clause 22 mdio access is done.
16566 uint8_t unused_1[7];
16569 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
16570 struct hwrm_port_phy_mdio_write_output {
16571 /* The specific error status for the command. */
16572 uint16_t error_code;
16573 /* The HWRM command request type. */
16575 /* The sequence ID from the original command. */
16577 /* The length of the response data in number of bytes. */
16579 uint8_t unused_0[7];
16581 * This field is used in Output records to indicate that the output
16582 * is completely written to RAM. This field should be read as '1'
16583 * to indicate that the output has been completely written.
16584 * When writing a command completion or response to an internal processor,
16585 * the order of writes has to be such that this field is written last.
16590 /***************************
16591 * hwrm_port_phy_mdio_read *
16592 ***************************/
16595 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
16596 struct hwrm_port_phy_mdio_read_input {
16597 /* The HWRM command request type. */
16600 * The completion ring to send the completion event on. This should
16601 * be the NQ ID returned from the `nq_alloc` HWRM command.
16603 uint16_t cmpl_ring;
16605 * The sequence ID is used by the driver for tracking multiple
16606 * commands. This ID is treated as opaque data by the firmware and
16607 * the value is returned in the `hwrm_resp_hdr` upon completion.
16611 * The target ID of the command:
16612 * * 0x0-0xFFF8 - The function ID
16613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16614 * * 0xFFFD - Reserved for user-space HWRM interface
16617 uint16_t target_id;
16619 * A physical address pointer pointing to a host buffer that the
16620 * command's response data will be written. This can be either a host
16621 * physical address (HPA) or a guest physical address (GPA) and must
16622 * point to a physically contiguous block of memory.
16624 uint64_t resp_addr;
16625 /* Reserved for future use. */
16626 uint32_t unused_0[2];
16627 /* Port ID of port. */
16629 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
16631 /* 8-bit device address. */
16633 /* 16-bit register address. */
16636 * When this bit is set to 1 a Clause 45 mdio access is done.
16637 * when this bit is set to 0 a Clause 22 mdio access is done.
16644 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
16645 struct hwrm_port_phy_mdio_read_output {
16646 /* The specific error status for the command. */
16647 uint16_t error_code;
16648 /* The HWRM command request type. */
16650 /* The sequence ID from the original command. */
16652 /* The length of the response data in number of bytes. */
16654 /* 16-bit register data. */
16656 uint8_t unused_0[5];
16658 * This field is used in Output records to indicate that the output
16659 * is completely written to RAM. This field should be read as '1'
16660 * to indicate that the output has been completely written.
16661 * When writing a command completion or response to an internal processor,
16662 * the order of writes has to be such that this field is written last.
16667 /*********************
16668 * hwrm_port_led_cfg *
16669 *********************/
16672 /* hwrm_port_led_cfg_input (size:512b/64B) */
16673 struct hwrm_port_led_cfg_input {
16674 /* The HWRM command request type. */
16677 * The completion ring to send the completion event on. This should
16678 * be the NQ ID returned from the `nq_alloc` HWRM command.
16680 uint16_t cmpl_ring;
16682 * The sequence ID is used by the driver for tracking multiple
16683 * commands. This ID is treated as opaque data by the firmware and
16684 * the value is returned in the `hwrm_resp_hdr` upon completion.
16688 * The target ID of the command:
16689 * * 0x0-0xFFF8 - The function ID
16690 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16691 * * 0xFFFD - Reserved for user-space HWRM interface
16694 uint16_t target_id;
16696 * A physical address pointer pointing to a host buffer that the
16697 * command's response data will be written. This can be either a host
16698 * physical address (HPA) or a guest physical address (GPA) and must
16699 * point to a physically contiguous block of memory.
16701 uint64_t resp_addr;
16704 * This bit must be '1' for the led0_id field to be
16707 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
16710 * This bit must be '1' for the led0_state field to be
16713 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
16716 * This bit must be '1' for the led0_color field to be
16719 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
16722 * This bit must be '1' for the led0_blink_on field to be
16725 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
16728 * This bit must be '1' for the led0_blink_off field to be
16731 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
16734 * This bit must be '1' for the led0_group_id field to be
16737 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
16740 * This bit must be '1' for the led1_id field to be
16743 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
16746 * This bit must be '1' for the led1_state field to be
16749 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
16752 * This bit must be '1' for the led1_color field to be
16755 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
16758 * This bit must be '1' for the led1_blink_on field to be
16761 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
16764 * This bit must be '1' for the led1_blink_off field to be
16767 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
16770 * This bit must be '1' for the led1_group_id field to be
16773 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
16776 * This bit must be '1' for the led2_id field to be
16779 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
16782 * This bit must be '1' for the led2_state field to be
16785 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
16788 * This bit must be '1' for the led2_color field to be
16791 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
16794 * This bit must be '1' for the led2_blink_on field to be
16797 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
16800 * This bit must be '1' for the led2_blink_off field to be
16803 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
16806 * This bit must be '1' for the led2_group_id field to be
16809 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
16812 * This bit must be '1' for the led3_id field to be
16815 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
16818 * This bit must be '1' for the led3_state field to be
16821 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
16824 * This bit must be '1' for the led3_color field to be
16827 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
16830 * This bit must be '1' for the led3_blink_on field to be
16833 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
16836 * This bit must be '1' for the led3_blink_off field to be
16839 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
16842 * This bit must be '1' for the led3_group_id field to be
16845 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
16847 /* Port ID of port whose LEDs are configured. */
16850 * The number of LEDs that are being configured.
16851 * Up to 4 LEDs can be configured with this command.
16854 /* Reserved field. */
16856 /* An identifier for the LED #0. */
16858 /* The requested state of the LED #0. */
16859 uint8_t led0_state;
16860 /* Default state of the LED */
16861 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
16863 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
16865 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
16867 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
16868 /* Blink Alternately */
16869 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
16870 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
16871 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
16872 /* The requested color of LED #0. */
16873 uint8_t led0_color;
16875 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
16877 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
16879 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
16880 /* Green or Amber */
16881 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
16882 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
16883 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
16886 * If the LED #0 state is "blink" or "blinkalt", then
16887 * this field represents the requested time in milliseconds
16888 * to keep LED on between cycles.
16890 uint16_t led0_blink_on;
16892 * If the LED #0 state is "blink" or "blinkalt", then
16893 * this field represents the requested time in milliseconds
16894 * to keep LED off between cycles.
16896 uint16_t led0_blink_off;
16898 * An identifier for the group of LEDs that LED #0 belongs
16900 * If set to 0, then the LED #0 shall not be grouped and
16901 * shall be treated as an individual resource.
16902 * For all other non-zero values of this field, LED #0 shall
16903 * be grouped together with the LEDs with the same group ID
16906 uint8_t led0_group_id;
16907 /* Reserved field. */
16909 /* An identifier for the LED #1. */
16911 /* The requested state of the LED #1. */
16912 uint8_t led1_state;
16913 /* Default state of the LED */
16914 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
16916 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
16918 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
16920 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
16921 /* Blink Alternately */
16922 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
16923 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
16924 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
16925 /* The requested color of LED #1. */
16926 uint8_t led1_color;
16928 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
16930 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
16932 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
16933 /* Green or Amber */
16934 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
16935 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
16936 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
16939 * If the LED #1 state is "blink" or "blinkalt", then
16940 * this field represents the requested time in milliseconds
16941 * to keep LED on between cycles.
16943 uint16_t led1_blink_on;
16945 * If the LED #1 state is "blink" or "blinkalt", then
16946 * this field represents the requested time in milliseconds
16947 * to keep LED off between cycles.
16949 uint16_t led1_blink_off;
16951 * An identifier for the group of LEDs that LED #1 belongs
16953 * If set to 0, then the LED #1 shall not be grouped and
16954 * shall be treated as an individual resource.
16955 * For all other non-zero values of this field, LED #1 shall
16956 * be grouped together with the LEDs with the same group ID
16959 uint8_t led1_group_id;
16960 /* Reserved field. */
16962 /* An identifier for the LED #2. */
16964 /* The requested state of the LED #2. */
16965 uint8_t led2_state;
16966 /* Default state of the LED */
16967 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
16969 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
16971 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
16973 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
16974 /* Blink Alternately */
16975 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
16976 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
16977 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
16978 /* The requested color of LED #2. */
16979 uint8_t led2_color;
16981 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
16983 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
16985 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
16986 /* Green or Amber */
16987 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
16988 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
16989 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
16992 * If the LED #2 state is "blink" or "blinkalt", then
16993 * this field represents the requested time in milliseconds
16994 * to keep LED on between cycles.
16996 uint16_t led2_blink_on;
16998 * If the LED #2 state is "blink" or "blinkalt", then
16999 * this field represents the requested time in milliseconds
17000 * to keep LED off between cycles.
17002 uint16_t led2_blink_off;
17004 * An identifier for the group of LEDs that LED #2 belongs
17006 * If set to 0, then the LED #2 shall not be grouped and
17007 * shall be treated as an individual resource.
17008 * For all other non-zero values of this field, LED #2 shall
17009 * be grouped together with the LEDs with the same group ID
17012 uint8_t led2_group_id;
17013 /* Reserved field. */
17015 /* An identifier for the LED #3. */
17017 /* The requested state of the LED #3. */
17018 uint8_t led3_state;
17019 /* Default state of the LED */
17020 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17022 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
17024 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
17026 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
17027 /* Blink Alternately */
17028 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17029 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
17030 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
17031 /* The requested color of LED #3. */
17032 uint8_t led3_color;
17034 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17036 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17038 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
17039 /* Green or Amber */
17040 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
17041 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
17042 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
17045 * If the LED #3 state is "blink" or "blinkalt", then
17046 * this field represents the requested time in milliseconds
17047 * to keep LED on between cycles.
17049 uint16_t led3_blink_on;
17051 * If the LED #3 state is "blink" or "blinkalt", then
17052 * this field represents the requested time in milliseconds
17053 * to keep LED off between cycles.
17055 uint16_t led3_blink_off;
17057 * An identifier for the group of LEDs that LED #3 belongs
17059 * If set to 0, then the LED #3 shall not be grouped and
17060 * shall be treated as an individual resource.
17061 * For all other non-zero values of this field, LED #3 shall
17062 * be grouped together with the LEDs with the same group ID
17065 uint8_t led3_group_id;
17066 /* Reserved field. */
17070 /* hwrm_port_led_cfg_output (size:128b/16B) */
17071 struct hwrm_port_led_cfg_output {
17072 /* The specific error status for the command. */
17073 uint16_t error_code;
17074 /* The HWRM command request type. */
17076 /* The sequence ID from the original command. */
17078 /* The length of the response data in number of bytes. */
17080 uint8_t unused_0[7];
17082 * This field is used in Output records to indicate that the output
17083 * is completely written to RAM. This field should be read as '1'
17084 * to indicate that the output has been completely written.
17085 * When writing a command completion or response to an internal processor,
17086 * the order of writes has to be such that this field is written last.
17091 /**********************
17092 * hwrm_port_led_qcfg *
17093 **********************/
17096 /* hwrm_port_led_qcfg_input (size:192b/24B) */
17097 struct hwrm_port_led_qcfg_input {
17098 /* The HWRM command request type. */
17101 * The completion ring to send the completion event on. This should
17102 * be the NQ ID returned from the `nq_alloc` HWRM command.
17104 uint16_t cmpl_ring;
17106 * The sequence ID is used by the driver for tracking multiple
17107 * commands. This ID is treated as opaque data by the firmware and
17108 * the value is returned in the `hwrm_resp_hdr` upon completion.
17112 * The target ID of the command:
17113 * * 0x0-0xFFF8 - The function ID
17114 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17115 * * 0xFFFD - Reserved for user-space HWRM interface
17118 uint16_t target_id;
17120 * A physical address pointer pointing to a host buffer that the
17121 * command's response data will be written. This can be either a host
17122 * physical address (HPA) or a guest physical address (GPA) and must
17123 * point to a physically contiguous block of memory.
17125 uint64_t resp_addr;
17126 /* Port ID of port whose LED configuration is being queried. */
17128 uint8_t unused_0[6];
17131 /* hwrm_port_led_qcfg_output (size:448b/56B) */
17132 struct hwrm_port_led_qcfg_output {
17133 /* The specific error status for the command. */
17134 uint16_t error_code;
17135 /* The HWRM command request type. */
17137 /* The sequence ID from the original command. */
17139 /* The length of the response data in number of bytes. */
17142 * The number of LEDs that are configured on this port.
17143 * Up to 4 LEDs can be returned in the response.
17146 /* An identifier for the LED #0. */
17148 /* The type of LED #0. */
17151 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17153 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17155 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17156 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
17157 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
17158 /* The current state of the LED #0. */
17159 uint8_t led0_state;
17160 /* Default state of the LED */
17161 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
17163 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
17165 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
17167 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
17168 /* Blink Alternately */
17169 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
17170 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
17171 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
17172 /* The color of LED #0. */
17173 uint8_t led0_color;
17175 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
17177 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
17179 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
17180 /* Green or Amber */
17181 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
17182 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
17183 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
17186 * If the LED #0 state is "blink" or "blinkalt", then
17187 * this field represents the requested time in milliseconds
17188 * to keep LED on between cycles.
17190 uint16_t led0_blink_on;
17192 * If the LED #0 state is "blink" or "blinkalt", then
17193 * this field represents the requested time in milliseconds
17194 * to keep LED off between cycles.
17196 uint16_t led0_blink_off;
17198 * An identifier for the group of LEDs that LED #0 belongs
17200 * If set to 0, then the LED #0 is not grouped.
17201 * For all other non-zero values of this field, LED #0 is
17202 * grouped together with the LEDs with the same group ID
17205 uint8_t led0_group_id;
17206 /* An identifier for the LED #1. */
17208 /* The type of LED #1. */
17211 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17213 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17215 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17216 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
17217 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
17218 /* The current state of the LED #1. */
17219 uint8_t led1_state;
17220 /* Default state of the LED */
17221 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
17223 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
17225 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
17227 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
17228 /* Blink Alternately */
17229 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
17230 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
17231 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
17232 /* The color of LED #1. */
17233 uint8_t led1_color;
17235 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
17237 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
17239 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
17240 /* Green or Amber */
17241 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
17242 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
17243 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
17246 * If the LED #1 state is "blink" or "blinkalt", then
17247 * this field represents the requested time in milliseconds
17248 * to keep LED on between cycles.
17250 uint16_t led1_blink_on;
17252 * If the LED #1 state is "blink" or "blinkalt", then
17253 * this field represents the requested time in milliseconds
17254 * to keep LED off between cycles.
17256 uint16_t led1_blink_off;
17258 * An identifier for the group of LEDs that LED #1 belongs
17260 * If set to 0, then the LED #1 is not grouped.
17261 * For all other non-zero values of this field, LED #1 is
17262 * grouped together with the LEDs with the same group ID
17265 uint8_t led1_group_id;
17266 /* An identifier for the LED #2. */
17268 /* The type of LED #2. */
17271 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17273 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17275 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17276 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
17277 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
17278 /* The current state of the LED #2. */
17279 uint8_t led2_state;
17280 /* Default state of the LED */
17281 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
17283 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
17285 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
17287 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
17288 /* Blink Alternately */
17289 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
17290 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
17291 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
17292 /* The color of LED #2. */
17293 uint8_t led2_color;
17295 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
17297 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
17299 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
17300 /* Green or Amber */
17301 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
17302 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
17303 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
17306 * If the LED #2 state is "blink" or "blinkalt", then
17307 * this field represents the requested time in milliseconds
17308 * to keep LED on between cycles.
17310 uint16_t led2_blink_on;
17312 * If the LED #2 state is "blink" or "blinkalt", then
17313 * this field represents the requested time in milliseconds
17314 * to keep LED off between cycles.
17316 uint16_t led2_blink_off;
17318 * An identifier for the group of LEDs that LED #2 belongs
17320 * If set to 0, then the LED #2 is not grouped.
17321 * For all other non-zero values of this field, LED #2 is
17322 * grouped together with the LEDs with the same group ID
17325 uint8_t led2_group_id;
17326 /* An identifier for the LED #3. */
17328 /* The type of LED #3. */
17331 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17333 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17335 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17336 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
17337 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
17338 /* The current state of the LED #3. */
17339 uint8_t led3_state;
17340 /* Default state of the LED */
17341 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
17343 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
17345 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
17347 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
17348 /* Blink Alternately */
17349 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
17350 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
17351 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
17352 /* The color of LED #3. */
17353 uint8_t led3_color;
17355 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
17357 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
17359 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
17360 /* Green or Amber */
17361 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
17362 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
17363 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
17366 * If the LED #3 state is "blink" or "blinkalt", then
17367 * this field represents the requested time in milliseconds
17368 * to keep LED on between cycles.
17370 uint16_t led3_blink_on;
17372 * If the LED #3 state is "blink" or "blinkalt", then
17373 * this field represents the requested time in milliseconds
17374 * to keep LED off between cycles.
17376 uint16_t led3_blink_off;
17378 * An identifier for the group of LEDs that LED #3 belongs
17380 * If set to 0, then the LED #3 is not grouped.
17381 * For all other non-zero values of this field, LED #3 is
17382 * grouped together with the LEDs with the same group ID
17385 uint8_t led3_group_id;
17386 uint8_t unused_4[6];
17388 * This field is used in Output records to indicate that the output
17389 * is completely written to RAM. This field should be read as '1'
17390 * to indicate that the output has been completely written.
17391 * When writing a command completion or response to an internal processor,
17392 * the order of writes has to be such that this field is written last.
17397 /***********************
17398 * hwrm_port_led_qcaps *
17399 ***********************/
17402 /* hwrm_port_led_qcaps_input (size:192b/24B) */
17403 struct hwrm_port_led_qcaps_input {
17404 /* The HWRM command request type. */
17407 * The completion ring to send the completion event on. This should
17408 * be the NQ ID returned from the `nq_alloc` HWRM command.
17410 uint16_t cmpl_ring;
17412 * The sequence ID is used by the driver for tracking multiple
17413 * commands. This ID is treated as opaque data by the firmware and
17414 * the value is returned in the `hwrm_resp_hdr` upon completion.
17418 * The target ID of the command:
17419 * * 0x0-0xFFF8 - The function ID
17420 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17421 * * 0xFFFD - Reserved for user-space HWRM interface
17424 uint16_t target_id;
17426 * A physical address pointer pointing to a host buffer that the
17427 * command's response data will be written. This can be either a host
17428 * physical address (HPA) or a guest physical address (GPA) and must
17429 * point to a physically contiguous block of memory.
17431 uint64_t resp_addr;
17432 /* Port ID of port whose LED configuration is being queried. */
17434 uint8_t unused_0[6];
17437 /* hwrm_port_led_qcaps_output (size:384b/48B) */
17438 struct hwrm_port_led_qcaps_output {
17439 /* The specific error status for the command. */
17440 uint16_t error_code;
17441 /* The HWRM command request type. */
17443 /* The sequence ID from the original command. */
17445 /* The length of the response data in number of bytes. */
17448 * The number of LEDs that are configured on this port.
17449 * Up to 4 LEDs can be returned in the response.
17452 /* Reserved for future use. */
17454 /* An identifier for the LED #0. */
17456 /* The type of LED #0. */
17459 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
17461 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
17463 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
17464 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
17465 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
17467 * An identifier for the group of LEDs that LED #0 belongs
17469 * If set to 0, then the LED #0 cannot be grouped.
17470 * For all other non-zero values of this field, LED #0 is
17471 * grouped together with the LEDs with the same group ID
17474 uint8_t led0_group_id;
17476 /* The states supported by LED #0. */
17477 uint16_t led0_state_caps;
17479 * If set to 1, this LED is enabled.
17480 * If set to 0, this LED is disabled.
17482 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
17485 * If set to 1, off state is supported on this LED.
17486 * If set to 0, off state is not supported on this LED.
17488 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
17491 * If set to 1, on state is supported on this LED.
17492 * If set to 0, on state is not supported on this LED.
17494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
17497 * If set to 1, blink state is supported on this LED.
17498 * If set to 0, blink state is not supported on this LED.
17500 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
17503 * If set to 1, blink_alt state is supported on this LED.
17504 * If set to 0, blink_alt state is not supported on this LED.
17506 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
17508 /* The colors supported by LED #0. */
17509 uint16_t led0_color_caps;
17511 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
17514 * If set to 1, Amber color is supported on this LED.
17515 * If set to 0, Amber color is not supported on this LED.
17517 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
17520 * If set to 1, Green color is supported on this LED.
17521 * If set to 0, Green color is not supported on this LED.
17523 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
17525 /* An identifier for the LED #1. */
17527 /* The type of LED #1. */
17530 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
17532 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
17534 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
17535 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
17536 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
17538 * An identifier for the group of LEDs that LED #1 belongs
17540 * If set to 0, then the LED #0 cannot be grouped.
17541 * For all other non-zero values of this field, LED #0 is
17542 * grouped together with the LEDs with the same group ID
17545 uint8_t led1_group_id;
17547 /* The states supported by LED #1. */
17548 uint16_t led1_state_caps;
17550 * If set to 1, this LED is enabled.
17551 * If set to 0, this LED is disabled.
17553 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
17556 * If set to 1, off state is supported on this LED.
17557 * If set to 0, off state is not supported on this LED.
17559 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
17562 * If set to 1, on state is supported on this LED.
17563 * If set to 0, on state is not supported on this LED.
17565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
17568 * If set to 1, blink state is supported on this LED.
17569 * If set to 0, blink state is not supported on this LED.
17571 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
17574 * If set to 1, blink_alt state is supported on this LED.
17575 * If set to 0, blink_alt state is not supported on this LED.
17577 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
17579 /* The colors supported by LED #1. */
17580 uint16_t led1_color_caps;
17582 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
17585 * If set to 1, Amber color is supported on this LED.
17586 * If set to 0, Amber color is not supported on this LED.
17588 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
17591 * If set to 1, Green color is supported on this LED.
17592 * If set to 0, Green color is not supported on this LED.
17594 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
17596 /* An identifier for the LED #2. */
17598 /* The type of LED #2. */
17601 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
17603 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
17605 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
17606 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
17607 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
17609 * An identifier for the group of LEDs that LED #0 belongs
17611 * If set to 0, then the LED #0 cannot be grouped.
17612 * For all other non-zero values of this field, LED #0 is
17613 * grouped together with the LEDs with the same group ID
17616 uint8_t led2_group_id;
17618 /* The states supported by LED #2. */
17619 uint16_t led2_state_caps;
17621 * If set to 1, this LED is enabled.
17622 * If set to 0, this LED is disabled.
17624 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
17627 * If set to 1, off state is supported on this LED.
17628 * If set to 0, off state is not supported on this LED.
17630 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
17633 * If set to 1, on state is supported on this LED.
17634 * If set to 0, on state is not supported on this LED.
17636 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
17639 * If set to 1, blink state is supported on this LED.
17640 * If set to 0, blink state is not supported on this LED.
17642 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
17645 * If set to 1, blink_alt state is supported on this LED.
17646 * If set to 0, blink_alt state is not supported on this LED.
17648 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
17650 /* The colors supported by LED #2. */
17651 uint16_t led2_color_caps;
17653 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
17656 * If set to 1, Amber color is supported on this LED.
17657 * If set to 0, Amber color is not supported on this LED.
17659 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
17662 * If set to 1, Green color is supported on this LED.
17663 * If set to 0, Green color is not supported on this LED.
17665 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
17667 /* An identifier for the LED #3. */
17669 /* The type of LED #3. */
17672 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
17674 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
17676 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
17677 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
17678 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
17680 * An identifier for the group of LEDs that LED #3 belongs
17682 * If set to 0, then the LED #0 cannot be grouped.
17683 * For all other non-zero values of this field, LED #0 is
17684 * grouped together with the LEDs with the same group ID
17687 uint8_t led3_group_id;
17689 /* The states supported by LED #3. */
17690 uint16_t led3_state_caps;
17692 * If set to 1, this LED is enabled.
17693 * If set to 0, this LED is disabled.
17695 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
17698 * If set to 1, off state is supported on this LED.
17699 * If set to 0, off state is not supported on this LED.
17701 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
17704 * If set to 1, on state is supported on this LED.
17705 * If set to 0, on state is not supported on this LED.
17707 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
17710 * If set to 1, blink state is supported on this LED.
17711 * If set to 0, blink state is not supported on this LED.
17713 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
17716 * If set to 1, blink_alt state is supported on this LED.
17717 * If set to 0, blink_alt state is not supported on this LED.
17719 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
17721 /* The colors supported by LED #3. */
17722 uint16_t led3_color_caps;
17724 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
17727 * If set to 1, Amber color is supported on this LED.
17728 * If set to 0, Amber color is not supported on this LED.
17730 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
17733 * If set to 1, Green color is supported on this LED.
17734 * If set to 0, Green color is not supported on this LED.
17736 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
17738 uint8_t unused_4[3];
17740 * This field is used in Output records to indicate that the output
17741 * is completely written to RAM. This field should be read as '1'
17742 * to indicate that the output has been completely written.
17743 * When writing a command completion or response to an internal processor,
17744 * the order of writes has to be such that this field is written last.
17749 /***********************
17750 * hwrm_port_prbs_test *
17751 ***********************/
17754 /* hwrm_port_prbs_test_input (size:384b/48B) */
17755 struct hwrm_port_prbs_test_input {
17756 /* The HWRM command request type. */
17759 * The completion ring to send the completion event on. This should
17760 * be the NQ ID returned from the `nq_alloc` HWRM command.
17762 uint16_t cmpl_ring;
17764 * The sequence ID is used by the driver for tracking multiple
17765 * commands. This ID is treated as opaque data by the firmware and
17766 * the value is returned in the `hwrm_resp_hdr` upon completion.
17770 * The target ID of the command:
17771 * * 0x0-0xFFF8 - The function ID
17772 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17773 * * 0xFFFD - Reserved for user-space HWRM interface
17776 uint16_t target_id;
17778 * A physical address pointer pointing to a host buffer that the
17779 * command's response data will be written. This can be either a host
17780 * physical address (HPA) or a guest physical address (GPA) and must
17781 * point to a physically contiguous block of memory.
17783 uint64_t resp_addr;
17784 /* Host address data is to DMA'd to. */
17785 uint64_t resp_data_addr;
17787 * Size of the buffer pointed to by resp_data_addr. The firmware may
17788 * use this entire buffer or less than the entire buffer, but never more.
17793 /* Port ID of port where PRBS test to be run. */
17795 /* Polynomial selection for PRBS test. */
17798 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
17800 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
17802 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
17804 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
17806 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
17808 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
17810 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
17812 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
17813 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
17814 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
17816 * Configuration bits for PRBS test.
17817 * Use enable bit to start/stop test.
17818 * Use tx/rx lane map bits to run test on specific lanes,
17819 * if set to 0 test will be run on all lanes.
17821 uint16_t prbs_config;
17823 * Set 0 to stop test currently in progress
17824 * Set 1 to start test with configuration provided.
17826 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
17829 * If set to 1, tx_lane_map bitmap should have lane bits set.
17830 * If set to 0, test will be run on all lanes for this port.
17832 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
17835 * If set to 1, rx_lane_map bitmap should have lane bits set.
17836 * If set to 0, test will be run on all lanes for this port.
17838 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
17840 /* Duration in seconds to run the PRBS test. */
17843 * If tx_lane_map_valid is set to 1, this field is a bitmap
17844 * of tx lanes to run PRBS test. bit0 = lane0,
17845 * bit1 = lane1 ..bit31 = lane31
17847 uint32_t tx_lane_map;
17849 * If rx_lane_map_valid is set to 1, this field is a bitmap
17850 * of rx lanes to run PRBS test. bit0 = lane0,
17851 * bit1 = lane1 ..bit31 = lane31
17853 uint32_t rx_lane_map;
17856 /* hwrm_port_prbs_test_output (size:128b/16B) */
17857 struct hwrm_port_prbs_test_output {
17858 /* The specific error status for the command. */
17859 uint16_t error_code;
17860 /* The HWRM command request type. */
17862 /* The sequence ID from the original command. */
17864 /* The length of the response data in number of bytes. */
17866 /* Total length of stored data. */
17867 uint16_t total_data_len;
17869 uint8_t unused_1[3];
17871 * This field is used in Output records to indicate that the output
17872 * is completely written to RAM. This field should be read as '1'
17873 * to indicate that the output has been completely written.
17874 * When writing a command completion or response to an internal processor,
17875 * the order of writes has to be such that this field is written last.
17880 /**********************
17881 * hwrm_port_dsc_dump *
17882 **********************/
17885 /* hwrm_port_dsc_dump_input (size:320b/40B) */
17886 struct hwrm_port_dsc_dump_input {
17887 /* The HWRM command request type. */
17890 * The completion ring to send the completion event on. This should
17891 * be the NQ ID returned from the `nq_alloc` HWRM command.
17893 uint16_t cmpl_ring;
17895 * The sequence ID is used by the driver for tracking multiple
17896 * commands. This ID is treated as opaque data by the firmware and
17897 * the value is returned in the `hwrm_resp_hdr` upon completion.
17901 * The target ID of the command:
17902 * * 0x0-0xFFF8 - The function ID
17903 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17904 * * 0xFFFD - Reserved for user-space HWRM interface
17907 uint16_t target_id;
17909 * A physical address pointer pointing to a host buffer that the
17910 * command's response data will be written. This can be either a host
17911 * physical address (HPA) or a guest physical address (GPA) and must
17912 * point to a physically contiguous block of memory.
17914 uint64_t resp_addr;
17915 /* Host address where response diagnostic data is returned. */
17916 uint64_t resp_data_addr;
17918 * Size of the buffer pointed to by resp_data_addr. The firmware
17919 * may use this entire buffer or less than the entire buffer, but
17925 /* Port ID of port where dsc dump to be collected. */
17927 /* Diag level specified by the user */
17928 uint16_t diag_level;
17929 /* SRDS_DIAG_LANE */
17930 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
17932 /* SRDS_DIAG_CORE */
17933 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
17935 /* SRDS_DIAG_EVENT */
17936 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
17938 /* SRDS_DIAG_EYE */
17939 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
17941 /* SRDS_DIAG_REG_CORE */
17942 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
17944 /* SRDS_DIAG_REG_LANE */
17945 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
17947 /* SRDS_DIAG_UC_CORE */
17948 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
17950 /* SRDS_DIAG_UC_LANE */
17951 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
17953 /* SRDS_DIAG_LANE_DEBUG */
17954 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
17956 /* SRDS_DIAG_BER_VERT */
17957 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
17959 /* SRDS_DIAG_BER_HORZ */
17960 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
17962 /* SRDS_DIAG_EVENT_SAFE */
17963 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
17965 /* SRDS_DIAG_TIMESTAMP */
17966 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
17968 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
17969 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
17971 * This field is a lane number
17972 * on which to collect the dsc dump
17974 uint16_t lane_number;
17976 * Configuration bits.
17977 * Use enable bit to start dsc dump or retrieve dump
17979 uint16_t dsc_dump_config;
17981 * Set 0 to retrieve the dsc dump
17982 * Set 1 to start the dsc dump
17984 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
17988 /* hwrm_port_dsc_dump_output (size:128b/16B) */
17989 struct hwrm_port_dsc_dump_output {
17990 /* The specific error status for the command. */
17991 uint16_t error_code;
17992 /* The HWRM command request type. */
17994 /* The sequence ID from the original command. */
17996 /* The length of the response data in number of bytes. */
17998 /* Total length of stored data. */
17999 uint16_t total_data_len;
18001 uint8_t unused_1[3];
18003 * This field is used in Output records to indicate that the output
18004 * is completely written to RAM. This field should be read as '1'
18005 * to indicate that the output has been completely written.
18006 * When writing a command completion or response to an internal processor,
18007 * the order of writes has to be such that this field is written last.
18012 /******************************
18013 * hwrm_port_sfp_sideband_cfg *
18014 ******************************/
18017 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
18018 struct hwrm_port_sfp_sideband_cfg_input {
18019 /* The HWRM command request type. */
18022 * The completion ring to send the completion event on. This should
18023 * be the NQ ID returned from the `nq_alloc` HWRM command.
18025 uint16_t cmpl_ring;
18027 * The sequence ID is used by the driver for tracking multiple
18028 * commands. This ID is treated as opaque data by the firmware and
18029 * the value is returned in the `hwrm_resp_hdr` upon completion.
18033 * The target ID of the command:
18034 * * 0x0-0xFFF8 - The function ID
18035 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18036 * * 0xFFFD - Reserved for user-space HWRM interface
18039 uint16_t target_id;
18041 * A physical address pointer pointing to a host buffer that the
18042 * command's response data will be written. This can be either a host
18043 * physical address (HPA) or a guest physical address (GPA) and must
18044 * point to a physically contiguous block of memory.
18046 uint64_t resp_addr;
18047 /* Port ID of port that is to be queried. */
18049 uint8_t unused_0[6];
18051 * This bitfield is used to specify which bits from the 'flags'
18052 * fields are being configured by the caller.
18055 /* This bit must be '1' for rs0 to be configured. */
18056 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
18058 /* This bit must be '1' for rs1 to be configured. */
18059 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
18061 /* This bit must be '1' for tx_disable to be configured. */
18062 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
18065 * This bit must be '1' for mod_sel to be configured.
18066 * Valid only on QSFP modules
18068 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
18070 /* This bit must be '1' for reset_l to be configured. */
18071 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
18073 /* This bit must be '1' for lp_mode to be configured. */
18074 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
18076 /* This bit must be '1' for pwr_disable to be configured. */
18077 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
18080 * Only bits that have corresponding bits in the 'enables'
18081 * bitfield are processed by the firmware, all other bits
18082 * of 'flags' are ignored.
18086 * This bit along with rs1 configures the current speed of the dual
18087 * rate module. If these pins are GNDed then the speed can be changed
18088 * by driectly writing to EEPROM.
18090 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
18093 * This bit along with rs0 configures the current speed of the dual
18094 * rate module. If these pins are GNDed then the speed can be changed
18095 * by driectly writing to EEPROM.
18097 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
18100 * When this bit is set to '1', tx_disable is set.
18101 * On a 1G BASE-T module, if this bit is set,
18102 * module PHY registers will not be accessible.
18104 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
18107 * When this bit is set to '1', this module is selected.
18108 * Valid only on QSFP modules
18110 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
18113 * If reset_l is set to 0, Module will be taken out of reset
18114 * and other signals will be set to their requested state once
18115 * the module is out of reset.
18116 * Valid only on QSFP modules
18118 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
18121 * When this bit is set to '1', the module will be configured
18122 * in low power mode.
18123 * Valid only on QSFP modules
18125 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
18127 /* When this bit is set to '1', the module will be powered down. */
18128 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
18132 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
18133 struct hwrm_port_sfp_sideband_cfg_output {
18134 /* The specific error status for the command. */
18135 uint16_t error_code;
18136 /* The HWRM command request type. */
18138 /* The sequence ID from the original command. */
18140 /* The length of the response data in number of bytes. */
18144 * This field is used in Output records to indicate that the output
18145 * is completely written to RAM. This field should be read as '1'
18146 * to indicate that the output has been completely written. When
18147 * writing a command completion or response to an internal processor,
18148 * the order of writes has to be such that this field is written last.
18153 /*******************************
18154 * hwrm_port_sfp_sideband_qcfg *
18155 *******************************/
18158 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
18159 struct hwrm_port_sfp_sideband_qcfg_input {
18160 /* The HWRM command request type. */
18163 * The completion ring to send the completion event on. This should
18164 * be the NQ ID returned from the `nq_alloc` HWRM command.
18166 uint16_t cmpl_ring;
18168 * The sequence ID is used by the driver for tracking multiple
18169 * commands. This ID is treated as opaque data by the firmware and
18170 * the value is returned in the `hwrm_resp_hdr` upon completion.
18174 * The target ID of the command:
18175 * * 0x0-0xFFF8 - The function ID
18176 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18177 * * 0xFFFD - Reserved for user-space HWRM interface
18180 uint16_t target_id;
18182 * A physical address pointer pointing to a host buffer that the
18183 * command's response data will be written. This can be either a host
18184 * physical address (HPA) or a guest physical address (GPA) and must
18185 * point to a physically contiguous block of memory.
18187 uint64_t resp_addr;
18188 /* Port ID of port that is to be queried. */
18190 uint8_t unused_0[6];
18193 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
18194 struct hwrm_port_sfp_sideband_qcfg_output {
18195 /* The specific error status for the command. */
18196 uint16_t error_code;
18197 /* The HWRM command request type. */
18199 /* The sequence ID from the original command. */
18201 /* The length of the response data in number of bytes. */
18204 * Bitmask indicating which sideband signals are valid.
18205 * This is based on the board and nvm cfg that is present on the board.
18207 uint32_t supported_mask;
18208 uint32_t sideband_signals;
18209 /* When this bit is set to '1', the Module is absent. */
18210 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
18213 * When this bit is set to '1', there is no valid signal on RX.
18214 * This signal is a filtered version of Signal Detect.
18216 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
18219 * This bit along with rs1 indiactes the current speed of the dual
18220 * rate module.If these pins are grounded then the speed can be
18221 * changed by driectky writing to EEPROM.
18223 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
18226 * This bit along with rs0 indiactes the current speed of the dual
18227 * rate module.If these pins are grounded then the speed can be
18228 * changed by driectky writing to EEPROM.
18230 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
18233 * When this bit is set to '1', tx_disable is set.
18234 * On a 1G BASE-T module, if this bit is set, module PHY
18235 * registers will not be accessible.
18237 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
18239 /* When this bit is set to '1', tx_fault is set. */
18240 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
18243 * When this bit is set to '1', module is selected.
18244 * Valid only on QSFP modules
18246 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
18249 * When this bit is set to '0', the module is held in reset.
18250 * if reset_l is set to 1,first module is taken out of reset
18251 * and other signals will be set to their requested state.
18252 * Valid only on QSFP modules.
18254 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
18257 * When this bit is set to '1', the module is in low power mode.
18258 * Valid only on QSFP modules
18260 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
18262 /* When this bit is set to '1', module is in power down state. */
18263 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
18267 * This field is used in Output records to indicate that the output
18268 * is completely written to RAM. This field should be read as '1'
18269 * to indicate that the output has been completely written. When
18270 * writing a command completion or response to an internal processor,
18271 * the order of writes has to be such that this field is written last.
18276 /**********************************
18277 * hwrm_port_phy_mdio_bus_acquire *
18278 **********************************/
18281 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
18282 struct hwrm_port_phy_mdio_bus_acquire_input {
18283 /* The HWRM command request type. */
18286 * The completion ring to send the completion event on. This should
18287 * be the NQ ID returned from the `nq_alloc` HWRM command.
18289 uint16_t cmpl_ring;
18291 * The sequence ID is used by the driver for tracking multiple
18292 * commands. This ID is treated as opaque data by the firmware and
18293 * the value is returned in the `hwrm_resp_hdr` upon completion.
18297 * The target ID of the command:
18298 * * 0x0-0xFFF8 - The function ID
18299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18300 * * 0xFFFD - Reserved for user-space HWRM interface
18303 uint16_t target_id;
18305 * A physical address pointer pointing to a host buffer that the
18306 * command's response data will be written. This can be either a host
18307 * physical address (HPA) or a guest physical address (GPA) and must
18308 * point to a physically contiguous block of memory.
18310 uint64_t resp_addr;
18311 /* Port ID of the port. */
18314 * client_id of the client requesting BUS access.
18315 * Any value from 0x10 to 0xFFFF can be used.
18316 * Client should make sure that the returned client_id
18317 * in response matches the client_id in request.
18318 * 0-0xF are reserved for internal use.
18320 uint16_t client_id;
18322 * Timeout in milli seconds, MDIO BUS will be released automatically
18323 * after this time, if another mdio acquire command is not received
18324 * within the timeout window from the same client.
18325 * A 0xFFFF will hold the bus until this bus is released.
18327 uint16_t mdio_bus_timeout;
18328 uint8_t unused_0[2];
18331 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
18332 struct hwrm_port_phy_mdio_bus_acquire_output {
18333 /* The specific error status for the command. */
18334 uint16_t error_code;
18335 /* The HWRM command request type. */
18337 /* The sequence ID from the original command. */
18339 /* The length of the response data in number of bytes. */
18343 * client_id of the module holding the BUS.
18344 * 0-0xF are reserved for internal use.
18346 uint16_t client_id;
18347 uint8_t unused_1[3];
18349 * This field is used in Output records to indicate that the output
18350 * is completely written to RAM. This field should be read as '1'
18351 * to indicate that the output has been completely written.
18352 * When writing a command completion or response to an internal processor,
18353 * the order of writes has to be such that this field is written last.
18358 /**********************************
18359 * hwrm_port_phy_mdio_bus_release *
18360 **********************************/
18363 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
18364 struct hwrm_port_phy_mdio_bus_release_input {
18365 /* The HWRM command request type. */
18368 * The completion ring to send the completion event on. This should
18369 * be the NQ ID returned from the `nq_alloc` HWRM command.
18371 uint16_t cmpl_ring;
18373 * The sequence ID is used by the driver for tracking multiple
18374 * commands. This ID is treated as opaque data by the firmware and
18375 * the value is returned in the `hwrm_resp_hdr` upon completion.
18379 * The target ID of the command:
18380 * * 0x0-0xFFF8 - The function ID
18381 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18382 * * 0xFFFD - Reserved for user-space HWRM interface
18385 uint16_t target_id;
18387 * A physical address pointer pointing to a host buffer that the
18388 * command's response data will be written. This can be either a host
18389 * physical address (HPA) or a guest physical address (GPA) and must
18390 * point to a physically contiguous block of memory.
18392 uint64_t resp_addr;
18393 /* Port ID of the port. */
18396 * client_id of the client requesting BUS release.
18397 * A client should not release any other clients BUS.
18399 uint16_t client_id;
18400 uint8_t unused_0[4];
18403 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
18404 struct hwrm_port_phy_mdio_bus_release_output {
18405 /* The specific error status for the command. */
18406 uint16_t error_code;
18407 /* The HWRM command request type. */
18409 /* The sequence ID from the original command. */
18411 /* The length of the response data in number of bytes. */
18414 /* The BUS is released if client_id matches the client_id in request. */
18415 uint16_t clients_id;
18416 uint8_t unused_1[3];
18418 * This field is used in Output records to indicate that the output
18419 * is completely written to RAM. This field should be read as '1'
18420 * to indicate that the output has been completely written.
18421 * When writing a command completion or response to an internal processor,
18422 * the order of writes has to be such that this field is written last.
18427 /***********************
18428 * hwrm_queue_qportcfg *
18429 ***********************/
18432 /* hwrm_queue_qportcfg_input (size:192b/24B) */
18433 struct hwrm_queue_qportcfg_input {
18434 /* The HWRM command request type. */
18437 * The completion ring to send the completion event on. This should
18438 * be the NQ ID returned from the `nq_alloc` HWRM command.
18440 uint16_t cmpl_ring;
18442 * The sequence ID is used by the driver for tracking multiple
18443 * commands. This ID is treated as opaque data by the firmware and
18444 * the value is returned in the `hwrm_resp_hdr` upon completion.
18448 * The target ID of the command:
18449 * * 0x0-0xFFF8 - The function ID
18450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18451 * * 0xFFFD - Reserved for user-space HWRM interface
18454 uint16_t target_id;
18456 * A physical address pointer pointing to a host buffer that the
18457 * command's response data will be written. This can be either a host
18458 * physical address (HPA) or a guest physical address (GPA) and must
18459 * point to a physically contiguous block of memory.
18461 uint64_t resp_addr;
18464 * Enumeration denoting the RX, TX type of the resource.
18465 * This enumeration is used for resources that are similar for both
18466 * TX and RX paths of the chip.
18468 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18470 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18472 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18473 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
18474 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
18476 * Port ID of port for which the queue configuration is being
18477 * queried. This field is only required when sent by IPC.
18481 * Drivers will set this capability when it can use
18482 * queue_idx_service_profile to map the queues to application.
18484 uint8_t drv_qmap_cap;
18486 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
18488 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
18489 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
18490 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
18494 /* hwrm_queue_qportcfg_output (size:256b/32B) */
18495 struct hwrm_queue_qportcfg_output {
18496 /* The specific error status for the command. */
18497 uint16_t error_code;
18498 /* The HWRM command request type. */
18500 /* The sequence ID from the original command. */
18502 /* The length of the response data in number of bytes. */
18505 * The maximum number of queues that can be configured on this
18507 * Valid values range from 1 through 8.
18509 uint8_t max_configurable_queues;
18511 * The maximum number of lossless queues that can be configured
18513 * Valid values range from 0 through 8.
18515 uint8_t max_configurable_lossless_queues;
18517 * Bitmask indicating which queues can be configured by the
18518 * hwrm_queue_cfg command.
18520 * Each bit represents a specific queue where bit 0 represents
18521 * queue 0 and bit 7 represents queue 7.
18522 * # A value of 0 indicates that the queue is not configurable
18523 * by the hwrm_queue_cfg command.
18524 * # A value of 1 indicates that the queue is configurable.
18525 * # A hwrm_queue_cfg command shall return error when trying to
18526 * configure a queue not configurable.
18528 uint8_t queue_cfg_allowed;
18529 /* Information about queue configuration. */
18530 uint8_t queue_cfg_info;
18532 * If this flag is set to '1', then the queues are
18533 * configured asymmetrically on TX and RX sides.
18534 * If this flag is set to '0', then the queues are
18535 * configured symmetrically on TX and RX sides. For
18536 * symmetric configuration, the queue configuration
18537 * including queue ids and service profiles on the
18538 * TX side is the same as the corresponding queue
18539 * configuration on the RX side.
18541 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18544 * Bitmask indicating which queues can be configured by the
18545 * hwrm_queue_pfcenable_cfg command.
18547 * Each bit represents a specific priority where bit 0 represents
18548 * priority 0 and bit 7 represents priority 7.
18549 * # A value of 0 indicates that the priority is not configurable by
18550 * the hwrm_queue_pfcenable_cfg command.
18551 * # A value of 1 indicates that the priority is configurable.
18552 * # A hwrm_queue_pfcenable_cfg command shall return error when
18553 * trying to configure a priority that is not configurable.
18555 uint8_t queue_pfcenable_cfg_allowed;
18557 * Bitmask indicating which queues can be configured by the
18558 * hwrm_queue_pri2cos_cfg command.
18560 * Each bit represents a specific queue where bit 0 represents
18561 * queue 0 and bit 7 represents queue 7.
18562 * # A value of 0 indicates that the queue is not configurable
18563 * by the hwrm_queue_pri2cos_cfg command.
18564 * # A value of 1 indicates that the queue is configurable.
18565 * # A hwrm_queue_pri2cos_cfg command shall return error when
18566 * trying to configure a queue that is not configurable.
18568 uint8_t queue_pri2cos_cfg_allowed;
18570 * Bitmask indicating which queues can be configured by the
18571 * hwrm_queue_pri2cos_cfg command.
18573 * Each bit represents a specific queue where bit 0 represents
18574 * queue 0 and bit 7 represents queue 7.
18575 * # A value of 0 indicates that the queue is not configurable
18576 * by the hwrm_queue_pri2cos_cfg command.
18577 * # A value of 1 indicates that the queue is configurable.
18578 * # A hwrm_queue_pri2cos_cfg command shall return error when
18579 * trying to configure a queue not configurable.
18581 uint8_t queue_cos2bw_cfg_allowed;
18583 * ID of CoS Queue 0.
18586 * # This ID can be used on any subsequent call to an hwrm command
18587 * that takes a queue id.
18588 * # IDs must always be queried by this command before any use
18589 * by the driver or software.
18590 * # Any driver or software should not make any assumptions about
18592 * # A value of 0xff indicates that the queue is not available.
18593 * # Available queues may not be in sequential order.
18596 /* This value is applicable to CoS queues only. */
18597 uint8_t queue_id0_service_profile;
18598 /* Lossy (best-effort) */
18599 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
18601 /* Lossless (legacy) */
18602 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
18604 /* Lossless RoCE */
18605 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
18607 /* Lossy RoCE CNP */
18608 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18611 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
18613 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18614 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
18616 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
18617 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
18619 * ID of CoS Queue 1.
18622 * # This ID can be used on any subsequent call to an hwrm command
18623 * that takes a queue id.
18624 * # IDs must always be queried by this command before any use
18625 * by the driver or software.
18626 * # Any driver or software should not make any assumptions about
18628 * # A value of 0xff indicates that the queue is not available.
18629 * # Available queues may not be in sequential order.
18632 /* This value is applicable to CoS queues only. */
18633 uint8_t queue_id1_service_profile;
18634 /* Lossy (best-effort) */
18635 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
18637 /* Lossless (legacy) */
18638 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
18640 /* Lossless RoCE */
18641 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
18643 /* Lossy RoCE CNP */
18644 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18647 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
18649 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18650 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
18652 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
18653 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
18655 * ID of CoS Queue 2.
18658 * # This ID can be used on any subsequent call to an hwrm command
18659 * that takes a queue id.
18660 * # IDs must always be queried by this command before any use
18661 * by the driver or software.
18662 * # Any driver or software should not make any assumptions about
18664 * # A value of 0xff indicates that the queue is not available.
18665 * # Available queues may not be in sequential order.
18668 /* This value is applicable to CoS queues only. */
18669 uint8_t queue_id2_service_profile;
18670 /* Lossy (best-effort) */
18671 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
18673 /* Lossless (legacy) */
18674 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
18676 /* Lossless RoCE */
18677 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
18679 /* Lossy RoCE CNP */
18680 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18683 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
18685 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18686 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
18688 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
18689 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
18691 * ID of CoS Queue 3.
18694 * # This ID can be used on any subsequent call to an hwrm command
18695 * that takes a queue id.
18696 * # IDs must always be queried by this command before any use
18697 * by the driver or software.
18698 * # Any driver or software should not make any assumptions about
18700 * # A value of 0xff indicates that the queue is not available.
18701 * # Available queues may not be in sequential order.
18704 /* This value is applicable to CoS queues only. */
18705 uint8_t queue_id3_service_profile;
18706 /* Lossy (best-effort) */
18707 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
18709 /* Lossless (legacy) */
18710 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
18712 /* Lossless RoCE */
18713 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
18715 /* Lossy RoCE CNP */
18716 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18719 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
18721 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18722 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
18724 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
18725 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
18727 * ID of CoS Queue 4.
18730 * # This ID can be used on any subsequent call to an hwrm command
18731 * that takes a queue id.
18732 * # IDs must always be queried by this command before any use
18733 * by the driver or software.
18734 * # Any driver or software should not make any assumptions about
18736 * # A value of 0xff indicates that the queue is not available.
18737 * # Available queues may not be in sequential order.
18740 /* This value is applicable to CoS queues only. */
18741 uint8_t queue_id4_service_profile;
18742 /* Lossy (best-effort) */
18743 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
18745 /* Lossless (legacy) */
18746 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
18748 /* Lossless RoCE */
18749 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
18751 /* Lossy RoCE CNP */
18752 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18755 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
18757 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18758 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
18760 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
18761 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
18763 * ID of CoS Queue 5.
18766 * # This ID can be used on any subsequent call to an hwrm command
18767 * that takes a queue id.
18768 * # IDs must always be queried by this command before any use
18769 * by the driver or software.
18770 * # Any driver or software should not make any assumptions about
18772 * # A value of 0xff indicates that the queue is not available.
18773 * # Available queues may not be in sequential order.
18776 /* This value is applicable to CoS queues only. */
18777 uint8_t queue_id5_service_profile;
18778 /* Lossy (best-effort) */
18779 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
18781 /* Lossless (legacy) */
18782 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
18784 /* Lossless RoCE */
18785 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
18787 /* Lossy RoCE CNP */
18788 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18791 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
18793 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18794 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
18796 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
18797 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
18799 * ID of CoS Queue 6.
18802 * # This ID can be used on any subsequent call to an hwrm command
18803 * that takes a queue id.
18804 * # IDs must always be queried by this command before any use
18805 * by the driver or software.
18806 * # Any driver or software should not make any assumptions about
18808 * # A value of 0xff indicates that the queue is not available.
18809 * # Available queues may not be in sequential order.
18812 /* This value is applicable to CoS queues only. */
18813 uint8_t queue_id6_service_profile;
18814 /* Lossy (best-effort) */
18815 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
18817 /* Lossless (legacy) */
18818 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
18820 /* Lossless RoCE */
18821 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
18823 /* Lossy RoCE CNP */
18824 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18827 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
18829 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18830 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
18832 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
18833 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
18835 * ID of CoS Queue 7.
18838 * # This ID can be used on any subsequent call to an hwrm command
18839 * that takes a queue id.
18840 * # IDs must always be queried by this command before any use
18841 * by the driver or software.
18842 * # Any driver or software should not make any assumptions about
18844 * # A value of 0xff indicates that the queue is not available.
18845 * # Available queues may not be in sequential order.
18848 /* This value is applicable to CoS queues only. */
18849 uint8_t queue_id7_service_profile;
18850 /* Lossy (best-effort) */
18851 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
18853 /* Lossless (legacy) */
18854 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
18856 /* Lossless RoCE */
18857 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
18859 /* Lossy RoCE CNP */
18860 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
18863 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
18865 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18866 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
18868 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
18869 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
18871 * This field is used in Output records to indicate that the output
18872 * is completely written to RAM. This field should be read as '1'
18873 * to indicate that the output has been completely written.
18874 * When writing a command completion or response to an internal processor,
18875 * the order of writes has to be such that this field is written last.
18880 /*******************
18881 * hwrm_queue_qcfg *
18882 *******************/
18885 /* hwrm_queue_qcfg_input (size:192b/24B) */
18886 struct hwrm_queue_qcfg_input {
18887 /* The HWRM command request type. */
18890 * The completion ring to send the completion event on. This should
18891 * be the NQ ID returned from the `nq_alloc` HWRM command.
18893 uint16_t cmpl_ring;
18895 * The sequence ID is used by the driver for tracking multiple
18896 * commands. This ID is treated as opaque data by the firmware and
18897 * the value is returned in the `hwrm_resp_hdr` upon completion.
18901 * The target ID of the command:
18902 * * 0x0-0xFFF8 - The function ID
18903 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18904 * * 0xFFFD - Reserved for user-space HWRM interface
18907 uint16_t target_id;
18909 * A physical address pointer pointing to a host buffer that the
18910 * command's response data will be written. This can be either a host
18911 * physical address (HPA) or a guest physical address (GPA) and must
18912 * point to a physically contiguous block of memory.
18914 uint64_t resp_addr;
18917 * Enumeration denoting the RX, TX type of the resource.
18918 * This enumeration is used for resources that are similar for both
18919 * TX and RX paths of the chip.
18921 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
18923 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
18925 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
18926 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
18927 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
18928 /* Queue ID of the queue. */
18932 /* hwrm_queue_qcfg_output (size:128b/16B) */
18933 struct hwrm_queue_qcfg_output {
18934 /* The specific error status for the command. */
18935 uint16_t error_code;
18936 /* The HWRM command request type. */
18938 /* The sequence ID from the original command. */
18940 /* The length of the response data in number of bytes. */
18943 * This value is the estimate packet length used in the
18946 uint32_t queue_len;
18947 /* This value is applicable to CoS queues only. */
18948 uint8_t service_profile;
18949 /* Lossy (best-effort) */
18950 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
18952 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
18953 /* Set to 0xFF... (All Fs) if there is no service profile specified */
18954 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
18955 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
18956 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
18957 /* Information about queue configuration. */
18958 uint8_t queue_cfg_info;
18960 * If this flag is set to '1', then the queue is
18961 * configured asymmetrically on TX and RX sides.
18962 * If this flag is set to '0', then this queue is
18963 * configured symmetrically on TX and RX sides.
18965 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
18969 * This field is used in Output records to indicate that the output
18970 * is completely written to RAM. This field should be read as '1'
18971 * to indicate that the output has been completely written.
18972 * When writing a command completion or response to an internal processor,
18973 * the order of writes has to be such that this field is written last.
18978 /******************
18980 ******************/
18983 /* hwrm_queue_cfg_input (size:320b/40B) */
18984 struct hwrm_queue_cfg_input {
18985 /* The HWRM command request type. */
18988 * The completion ring to send the completion event on. This should
18989 * be the NQ ID returned from the `nq_alloc` HWRM command.
18991 uint16_t cmpl_ring;
18993 * The sequence ID is used by the driver for tracking multiple
18994 * commands. This ID is treated as opaque data by the firmware and
18995 * the value is returned in the `hwrm_resp_hdr` upon completion.
18999 * The target ID of the command:
19000 * * 0x0-0xFFF8 - The function ID
19001 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19002 * * 0xFFFD - Reserved for user-space HWRM interface
19005 uint16_t target_id;
19007 * A physical address pointer pointing to a host buffer that the
19008 * command's response data will be written. This can be either a host
19009 * physical address (HPA) or a guest physical address (GPA) and must
19010 * point to a physically contiguous block of memory.
19012 uint64_t resp_addr;
19015 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
19016 * This enumeration is used for resources that are similar for both
19017 * TX and RX paths of the chip.
19019 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
19020 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
19022 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19024 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19025 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
19026 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
19027 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
19028 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
19031 * This bit must be '1' for the dflt_len field to be
19034 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
19036 * This bit must be '1' for the service_profile field to be
19039 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
19040 /* Queue ID of queue that is to be configured by this function. */
19043 * This value is a the estimate packet length used in the
19045 * Set to 0xFF... (All Fs) to not adjust this value.
19048 /* This value is applicable to CoS queues only. */
19049 uint8_t service_profile;
19050 /* Lossy (best-effort) */
19051 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
19053 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
19054 /* Set to 0xFF... (All Fs) if there is no service profile specified */
19055 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
19056 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
19057 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
19058 uint8_t unused_0[7];
19061 /* hwrm_queue_cfg_output (size:128b/16B) */
19062 struct hwrm_queue_cfg_output {
19063 /* The specific error status for the command. */
19064 uint16_t error_code;
19065 /* The HWRM command request type. */
19067 /* The sequence ID from the original command. */
19069 /* The length of the response data in number of bytes. */
19071 uint8_t unused_0[7];
19073 * This field is used in Output records to indicate that the output
19074 * is completely written to RAM. This field should be read as '1'
19075 * to indicate that the output has been completely written.
19076 * When writing a command completion or response to an internal processor,
19077 * the order of writes has to be such that this field is written last.
19082 /*****************************
19083 * hwrm_queue_pfcenable_qcfg *
19084 *****************************/
19087 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
19088 struct hwrm_queue_pfcenable_qcfg_input {
19089 /* The HWRM command request type. */
19092 * The completion ring to send the completion event on. This should
19093 * be the NQ ID returned from the `nq_alloc` HWRM command.
19095 uint16_t cmpl_ring;
19097 * The sequence ID is used by the driver for tracking multiple
19098 * commands. This ID is treated as opaque data by the firmware and
19099 * the value is returned in the `hwrm_resp_hdr` upon completion.
19103 * The target ID of the command:
19104 * * 0x0-0xFFF8 - The function ID
19105 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19106 * * 0xFFFD - Reserved for user-space HWRM interface
19109 uint16_t target_id;
19111 * A physical address pointer pointing to a host buffer that the
19112 * command's response data will be written. This can be either a host
19113 * physical address (HPA) or a guest physical address (GPA) and must
19114 * point to a physically contiguous block of memory.
19116 uint64_t resp_addr;
19118 * Port ID of port for which the table is being configured.
19119 * The HWRM needs to check whether this function is allowed
19120 * to configure pri2cos mapping on this port.
19123 uint8_t unused_0[6];
19126 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
19127 struct hwrm_queue_pfcenable_qcfg_output {
19128 /* The specific error status for the command. */
19129 uint16_t error_code;
19130 /* The HWRM command request type. */
19132 /* The sequence ID from the original command. */
19134 /* The length of the response data in number of bytes. */
19137 /* If set to 1, then PFC is enabled on PRI 0. */
19138 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
19140 /* If set to 1, then PFC is enabled on PRI 1. */
19141 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
19143 /* If set to 1, then PFC is enabled on PRI 2. */
19144 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
19146 /* If set to 1, then PFC is enabled on PRI 3. */
19147 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
19149 /* If set to 1, then PFC is enabled on PRI 4. */
19150 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
19152 /* If set to 1, then PFC is enabled on PRI 5. */
19153 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
19155 /* If set to 1, then PFC is enabled on PRI 6. */
19156 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
19158 /* If set to 1, then PFC is enabled on PRI 7. */
19159 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
19161 uint8_t unused_0[3];
19163 * This field is used in Output records to indicate that the output
19164 * is completely written to RAM. This field should be read as '1'
19165 * to indicate that the output has been completely written.
19166 * When writing a command completion or response to an internal processor,
19167 * the order of writes has to be such that this field is written last.
19172 /****************************
19173 * hwrm_queue_pfcenable_cfg *
19174 ****************************/
19177 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
19178 struct hwrm_queue_pfcenable_cfg_input {
19179 /* The HWRM command request type. */
19182 * The completion ring to send the completion event on. This should
19183 * be the NQ ID returned from the `nq_alloc` HWRM command.
19185 uint16_t cmpl_ring;
19187 * The sequence ID is used by the driver for tracking multiple
19188 * commands. This ID is treated as opaque data by the firmware and
19189 * the value is returned in the `hwrm_resp_hdr` upon completion.
19193 * The target ID of the command:
19194 * * 0x0-0xFFF8 - The function ID
19195 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19196 * * 0xFFFD - Reserved for user-space HWRM interface
19199 uint16_t target_id;
19201 * A physical address pointer pointing to a host buffer that the
19202 * command's response data will be written. This can be either a host
19203 * physical address (HPA) or a guest physical address (GPA) and must
19204 * point to a physically contiguous block of memory.
19206 uint64_t resp_addr;
19208 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
19209 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
19211 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
19212 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
19214 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
19215 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
19217 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
19218 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
19220 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
19221 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
19223 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
19224 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
19226 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
19227 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
19229 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
19230 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
19233 * Port ID of port for which the table is being configured.
19234 * The HWRM needs to check whether this function is allowed
19235 * to configure pri2cos mapping on this port.
19238 uint8_t unused_0[2];
19241 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
19242 struct hwrm_queue_pfcenable_cfg_output {
19243 /* The specific error status for the command. */
19244 uint16_t error_code;
19245 /* The HWRM command request type. */
19247 /* The sequence ID from the original command. */
19249 /* The length of the response data in number of bytes. */
19251 uint8_t unused_0[7];
19253 * This field is used in Output records to indicate that the output
19254 * is completely written to RAM. This field should be read as '1'
19255 * to indicate that the output has been completely written.
19256 * When writing a command completion or response to an internal processor,
19257 * the order of writes has to be such that this field is written last.
19262 /***************************
19263 * hwrm_queue_pri2cos_qcfg *
19264 ***************************/
19267 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
19268 struct hwrm_queue_pri2cos_qcfg_input {
19269 /* The HWRM command request type. */
19272 * The completion ring to send the completion event on. This should
19273 * be the NQ ID returned from the `nq_alloc` HWRM command.
19275 uint16_t cmpl_ring;
19277 * The sequence ID is used by the driver for tracking multiple
19278 * commands. This ID is treated as opaque data by the firmware and
19279 * the value is returned in the `hwrm_resp_hdr` upon completion.
19283 * The target ID of the command:
19284 * * 0x0-0xFFF8 - The function ID
19285 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19286 * * 0xFFFD - Reserved for user-space HWRM interface
19289 uint16_t target_id;
19291 * A physical address pointer pointing to a host buffer that the
19292 * command's response data will be written. This can be either a host
19293 * physical address (HPA) or a guest physical address (GPA) and must
19294 * point to a physically contiguous block of memory.
19296 uint64_t resp_addr;
19299 * Enumeration denoting the RX, TX type of the resource.
19300 * This enumeration is used for resources that are similar for both
19301 * TX and RX paths of the chip.
19303 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
19305 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19307 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19308 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
19309 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
19311 * When this bit is set to '0', the query is
19312 * for PRI from tunnel headers.
19313 * When this bit is set to '1', the query is
19314 * for PRI from inner packet headers.
19316 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
19318 * Port ID of port for which the table is being configured.
19319 * The HWRM needs to check whether this function is allowed
19320 * to configure pri2cos mapping on this port.
19323 uint8_t unused_0[3];
19326 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
19327 struct hwrm_queue_pri2cos_qcfg_output {
19328 /* The specific error status for the command. */
19329 uint16_t error_code;
19330 /* The HWRM command request type. */
19332 /* The sequence ID from the original command. */
19334 /* The length of the response data in number of bytes. */
19337 * CoS Queue assigned to priority 0. This value can only
19338 * be changed before traffic has started.
19339 * A value of 0xff indicates that no CoS queue is assigned to the
19340 * specified priority.
19342 uint8_t pri0_cos_queue_id;
19344 * CoS Queue assigned to priority 1. This value can only
19345 * be changed before traffic has started.
19346 * A value of 0xff indicates that no CoS queue is assigned to the
19347 * specified priority.
19349 uint8_t pri1_cos_queue_id;
19351 * CoS Queue assigned to priority 2. This value can only
19352 * be changed before traffic has started.
19353 * A value of 0xff indicates that no CoS queue is assigned to the
19354 * specified priority.
19356 uint8_t pri2_cos_queue_id;
19358 * CoS Queue assigned to priority 3. This value can only
19359 * be changed before traffic has started.
19360 * A value of 0xff indicates that no CoS queue is assigned to the
19361 * specified priority.
19363 uint8_t pri3_cos_queue_id;
19365 * CoS Queue assigned to priority 4. This value can only
19366 * be changed before traffic has started.
19367 * A value of 0xff indicates that no CoS queue is assigned to the
19368 * specified priority.
19370 uint8_t pri4_cos_queue_id;
19372 * CoS Queue assigned to priority 5. This value can only
19373 * be changed before traffic has started.
19374 * A value of 0xff indicates that no CoS queue is assigned to the
19375 * specified priority.
19377 uint8_t pri5_cos_queue_id;
19379 * CoS Queue assigned to priority 6. This value can only
19380 * be changed before traffic has started.
19381 * A value of 0xff indicates that no CoS queue is assigned to the
19382 * specified priority.
19384 uint8_t pri6_cos_queue_id;
19386 * CoS Queue assigned to priority 7. This value can only
19387 * be changed before traffic has started.
19388 * A value of 0xff indicates that no CoS queue is assigned to the
19389 * specified priority.
19391 uint8_t pri7_cos_queue_id;
19392 /* Information about queue configuration. */
19393 uint8_t queue_cfg_info;
19395 * If this flag is set to '1', then the PRI to CoS
19396 * configuration is asymmetric on TX and RX sides.
19397 * If this flag is set to '0', then PRI to CoS configuration
19398 * is symmetric on TX and RX sides.
19400 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
19402 uint8_t unused_0[6];
19404 * This field is used in Output records to indicate that the output
19405 * is completely written to RAM. This field should be read as '1'
19406 * to indicate that the output has been completely written.
19407 * When writing a command completion or response to an internal processor,
19408 * the order of writes has to be such that this field is written last.
19413 /**************************
19414 * hwrm_queue_pri2cos_cfg *
19415 **************************/
19418 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
19419 struct hwrm_queue_pri2cos_cfg_input {
19420 /* The HWRM command request type. */
19423 * The completion ring to send the completion event on. This should
19424 * be the NQ ID returned from the `nq_alloc` HWRM command.
19426 uint16_t cmpl_ring;
19428 * The sequence ID is used by the driver for tracking multiple
19429 * commands. This ID is treated as opaque data by the firmware and
19430 * the value is returned in the `hwrm_resp_hdr` upon completion.
19434 * The target ID of the command:
19435 * * 0x0-0xFFF8 - The function ID
19436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19437 * * 0xFFFD - Reserved for user-space HWRM interface
19440 uint16_t target_id;
19442 * A physical address pointer pointing to a host buffer that the
19443 * command's response data will be written. This can be either a host
19444 * physical address (HPA) or a guest physical address (GPA) and must
19445 * point to a physically contiguous block of memory.
19447 uint64_t resp_addr;
19450 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
19451 * This enumeration is used for resources that are similar for both
19452 * TX and RX paths of the chip.
19454 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
19455 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
19457 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19459 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19460 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
19461 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
19462 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
19463 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
19465 * When this bit is set to '0', the mapping is requested
19466 * for PRI from tunnel headers.
19467 * When this bit is set to '1', the mapping is requested
19468 * for PRI from inner packet headers.
19470 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
19473 * This bit must be '1' for the pri0_cos_queue_id field to be
19476 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
19479 * This bit must be '1' for the pri1_cos_queue_id field to be
19482 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
19485 * This bit must be '1' for the pri2_cos_queue_id field to be
19488 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
19491 * This bit must be '1' for the pri3_cos_queue_id field to be
19494 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
19497 * This bit must be '1' for the pri4_cos_queue_id field to be
19500 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
19503 * This bit must be '1' for the pri5_cos_queue_id field to be
19506 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
19509 * This bit must be '1' for the pri6_cos_queue_id field to be
19512 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
19515 * This bit must be '1' for the pri7_cos_queue_id field to be
19518 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
19521 * Port ID of port for which the table is being configured.
19522 * The HWRM needs to check whether this function is allowed
19523 * to configure pri2cos mapping on this port.
19527 * CoS Queue assigned to priority 0. This value can only
19528 * be changed before traffic has started.
19530 uint8_t pri0_cos_queue_id;
19532 * CoS Queue assigned to priority 1. This value can only
19533 * be changed before traffic has started.
19535 uint8_t pri1_cos_queue_id;
19537 * CoS Queue assigned to priority 2 This value can only
19538 * be changed before traffic has started.
19540 uint8_t pri2_cos_queue_id;
19542 * CoS Queue assigned to priority 3. This value can only
19543 * be changed before traffic has started.
19545 uint8_t pri3_cos_queue_id;
19547 * CoS Queue assigned to priority 4. This value can only
19548 * be changed before traffic has started.
19550 uint8_t pri4_cos_queue_id;
19552 * CoS Queue assigned to priority 5. This value can only
19553 * be changed before traffic has started.
19555 uint8_t pri5_cos_queue_id;
19557 * CoS Queue assigned to priority 6. This value can only
19558 * be changed before traffic has started.
19560 uint8_t pri6_cos_queue_id;
19562 * CoS Queue assigned to priority 7. This value can only
19563 * be changed before traffic has started.
19565 uint8_t pri7_cos_queue_id;
19566 uint8_t unused_0[7];
19569 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
19570 struct hwrm_queue_pri2cos_cfg_output {
19571 /* The specific error status for the command. */
19572 uint16_t error_code;
19573 /* The HWRM command request type. */
19575 /* The sequence ID from the original command. */
19577 /* The length of the response data in number of bytes. */
19579 uint8_t unused_0[7];
19581 * This field is used in Output records to indicate that the output
19582 * is completely written to RAM. This field should be read as '1'
19583 * to indicate that the output has been completely written.
19584 * When writing a command completion or response to an internal processor,
19585 * the order of writes has to be such that this field is written last.
19590 /**************************
19591 * hwrm_queue_cos2bw_qcfg *
19592 **************************/
19595 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
19596 struct hwrm_queue_cos2bw_qcfg_input {
19597 /* The HWRM command request type. */
19600 * The completion ring to send the completion event on. This should
19601 * be the NQ ID returned from the `nq_alloc` HWRM command.
19603 uint16_t cmpl_ring;
19605 * The sequence ID is used by the driver for tracking multiple
19606 * commands. This ID is treated as opaque data by the firmware and
19607 * the value is returned in the `hwrm_resp_hdr` upon completion.
19611 * The target ID of the command:
19612 * * 0x0-0xFFF8 - The function ID
19613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19614 * * 0xFFFD - Reserved for user-space HWRM interface
19617 uint16_t target_id;
19619 * A physical address pointer pointing to a host buffer that the
19620 * command's response data will be written. This can be either a host
19621 * physical address (HPA) or a guest physical address (GPA) and must
19622 * point to a physically contiguous block of memory.
19624 uint64_t resp_addr;
19626 * Port ID of port for which the table is being configured.
19627 * The HWRM needs to check whether this function is allowed
19628 * to configure TC BW assignment on this port.
19631 uint8_t unused_0[6];
19634 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
19635 struct hwrm_queue_cos2bw_qcfg_output {
19636 /* The specific error status for the command. */
19637 uint16_t error_code;
19638 /* The HWRM command request type. */
19640 /* The sequence ID from the original command. */
19642 /* The length of the response data in number of bytes. */
19644 /* ID of CoS Queue 0. */
19649 * Minimum BW allocated to CoS Queue.
19650 * The HWRM will translate this value into byte counter and
19651 * time interval used for this COS inside the device.
19653 uint32_t queue_id0_min_bw;
19654 /* The bandwidth value. */
19655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
19656 UINT32_C(0xfffffff)
19657 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
19659 /* The granularity of the value (bits or bytes). */
19660 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
19661 UINT32_C(0x10000000)
19662 /* Value is in bits. */
19663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
19664 (UINT32_C(0x0) << 28)
19665 /* Value is in bytes. */
19666 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
19667 (UINT32_C(0x1) << 28)
19668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
19669 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
19670 /* bw_value_unit is 3 b */
19671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
19672 UINT32_C(0xe0000000)
19673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
19675 /* Value is in Mb or MB (base 10). */
19676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
19677 (UINT32_C(0x0) << 29)
19678 /* Value is in Kb or KB (base 10). */
19679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
19680 (UINT32_C(0x2) << 29)
19681 /* Value is in bits or bytes. */
19682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
19683 (UINT32_C(0x4) << 29)
19684 /* Value is in Gb or GB (base 10). */
19685 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
19686 (UINT32_C(0x6) << 29)
19687 /* Value is in 1/100th of a percentage of total bandwidth. */
19688 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19689 (UINT32_C(0x1) << 29)
19691 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
19692 (UINT32_C(0x7) << 29)
19693 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
19694 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
19696 * Maximum BW allocated to CoS Queue.
19697 * The HWRM will translate this value into byte counter and
19698 * time interval used for this COS inside the device.
19700 uint32_t queue_id0_max_bw;
19701 /* The bandwidth value. */
19702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
19703 UINT32_C(0xfffffff)
19704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
19706 /* The granularity of the value (bits or bytes). */
19707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
19708 UINT32_C(0x10000000)
19709 /* Value is in bits. */
19710 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
19711 (UINT32_C(0x0) << 28)
19712 /* Value is in bytes. */
19713 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
19714 (UINT32_C(0x1) << 28)
19715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
19716 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
19717 /* bw_value_unit is 3 b */
19718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
19719 UINT32_C(0xe0000000)
19720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
19722 /* Value is in Mb or MB (base 10). */
19723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
19724 (UINT32_C(0x0) << 29)
19725 /* Value is in Kb or KB (base 10). */
19726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
19727 (UINT32_C(0x2) << 29)
19728 /* Value is in bits or bytes. */
19729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
19730 (UINT32_C(0x4) << 29)
19731 /* Value is in Gb or GB (base 10). */
19732 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
19733 (UINT32_C(0x6) << 29)
19734 /* Value is in 1/100th of a percentage of total bandwidth. */
19735 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19736 (UINT32_C(0x1) << 29)
19738 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
19739 (UINT32_C(0x7) << 29)
19740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
19741 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
19742 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19743 uint8_t queue_id0_tsa_assign;
19744 /* Strict Priority */
19745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
19747 /* Enhanced Transmission Selection */
19748 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
19751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
19754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
19757 * Priority level for strict priority. Valid only when the
19758 * tsa_assign is 0 - Strict Priority (SP)
19759 * 0..7 - Valid values.
19760 * 8..255 - Reserved.
19762 uint8_t queue_id0_pri_lvl;
19764 * Weight used to allocate remaining BW for this COS after
19765 * servicing guaranteed bandwidths for all COS.
19767 uint8_t queue_id0_bw_weight;
19768 /* ID of CoS Queue 1. */
19771 * Minimum BW allocated to CoS Queue.
19772 * The HWRM will translate this value into byte counter and
19773 * time interval used for this COS inside the device.
19775 uint32_t queue_id1_min_bw;
19776 /* The bandwidth value. */
19777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
19778 UINT32_C(0xfffffff)
19779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
19781 /* The granularity of the value (bits or bytes). */
19782 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
19783 UINT32_C(0x10000000)
19784 /* Value is in bits. */
19785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
19786 (UINT32_C(0x0) << 28)
19787 /* Value is in bytes. */
19788 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
19789 (UINT32_C(0x1) << 28)
19790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
19791 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
19792 /* bw_value_unit is 3 b */
19793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
19794 UINT32_C(0xe0000000)
19795 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
19797 /* Value is in Mb or MB (base 10). */
19798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
19799 (UINT32_C(0x0) << 29)
19800 /* Value is in Kb or KB (base 10). */
19801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
19802 (UINT32_C(0x2) << 29)
19803 /* Value is in bits or bytes. */
19804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
19805 (UINT32_C(0x4) << 29)
19806 /* Value is in Gb or GB (base 10). */
19807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
19808 (UINT32_C(0x6) << 29)
19809 /* Value is in 1/100th of a percentage of total bandwidth. */
19810 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19811 (UINT32_C(0x1) << 29)
19813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
19814 (UINT32_C(0x7) << 29)
19815 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
19816 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
19818 * Maximum BW allocated to CoS queue.
19819 * The HWRM will translate this value into byte counter and
19820 * time interval used for this COS inside the device.
19822 uint32_t queue_id1_max_bw;
19823 /* The bandwidth value. */
19824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
19825 UINT32_C(0xfffffff)
19826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
19828 /* The granularity of the value (bits or bytes). */
19829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
19830 UINT32_C(0x10000000)
19831 /* Value is in bits. */
19832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
19833 (UINT32_C(0x0) << 28)
19834 /* Value is in bytes. */
19835 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
19836 (UINT32_C(0x1) << 28)
19837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
19838 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
19839 /* bw_value_unit is 3 b */
19840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
19841 UINT32_C(0xe0000000)
19842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
19844 /* Value is in Mb or MB (base 10). */
19845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
19846 (UINT32_C(0x0) << 29)
19847 /* Value is in Kb or KB (base 10). */
19848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
19849 (UINT32_C(0x2) << 29)
19850 /* Value is in bits or bytes. */
19851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
19852 (UINT32_C(0x4) << 29)
19853 /* Value is in Gb or GB (base 10). */
19854 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
19855 (UINT32_C(0x6) << 29)
19856 /* Value is in 1/100th of a percentage of total bandwidth. */
19857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19858 (UINT32_C(0x1) << 29)
19860 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
19861 (UINT32_C(0x7) << 29)
19862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
19863 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
19864 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19865 uint8_t queue_id1_tsa_assign;
19866 /* Strict Priority */
19867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
19869 /* Enhanced Transmission Selection */
19870 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
19873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
19876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
19879 * Priority level for strict priority. Valid only when the
19880 * tsa_assign is 0 - Strict Priority (SP)
19881 * 0..7 - Valid values.
19882 * 8..255 - Reserved.
19884 uint8_t queue_id1_pri_lvl;
19886 * Weight used to allocate remaining BW for this COS after
19887 * servicing guaranteed bandwidths for all COS.
19889 uint8_t queue_id1_bw_weight;
19890 /* ID of CoS Queue 2. */
19893 * Minimum BW allocated to CoS Queue.
19894 * The HWRM will translate this value into byte counter and
19895 * time interval used for this COS inside the device.
19897 uint32_t queue_id2_min_bw;
19898 /* The bandwidth value. */
19899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
19900 UINT32_C(0xfffffff)
19901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
19903 /* The granularity of the value (bits or bytes). */
19904 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
19905 UINT32_C(0x10000000)
19906 /* Value is in bits. */
19907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
19908 (UINT32_C(0x0) << 28)
19909 /* Value is in bytes. */
19910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
19911 (UINT32_C(0x1) << 28)
19912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
19913 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
19914 /* bw_value_unit is 3 b */
19915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
19916 UINT32_C(0xe0000000)
19917 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
19919 /* Value is in Mb or MB (base 10). */
19920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
19921 (UINT32_C(0x0) << 29)
19922 /* Value is in Kb or KB (base 10). */
19923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
19924 (UINT32_C(0x2) << 29)
19925 /* Value is in bits or bytes. */
19926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
19927 (UINT32_C(0x4) << 29)
19928 /* Value is in Gb or GB (base 10). */
19929 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
19930 (UINT32_C(0x6) << 29)
19931 /* Value is in 1/100th of a percentage of total bandwidth. */
19932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
19933 (UINT32_C(0x1) << 29)
19935 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
19936 (UINT32_C(0x7) << 29)
19937 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
19938 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
19940 * Maximum BW allocated to CoS queue.
19941 * The HWRM will translate this value into byte counter and
19942 * time interval used for this COS inside the device.
19944 uint32_t queue_id2_max_bw;
19945 /* The bandwidth value. */
19946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
19947 UINT32_C(0xfffffff)
19948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
19950 /* The granularity of the value (bits or bytes). */
19951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
19952 UINT32_C(0x10000000)
19953 /* Value is in bits. */
19954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
19955 (UINT32_C(0x0) << 28)
19956 /* Value is in bytes. */
19957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
19958 (UINT32_C(0x1) << 28)
19959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
19960 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
19961 /* bw_value_unit is 3 b */
19962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
19963 UINT32_C(0xe0000000)
19964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
19966 /* Value is in Mb or MB (base 10). */
19967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
19968 (UINT32_C(0x0) << 29)
19969 /* Value is in Kb or KB (base 10). */
19970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
19971 (UINT32_C(0x2) << 29)
19972 /* Value is in bits or bytes. */
19973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
19974 (UINT32_C(0x4) << 29)
19975 /* Value is in Gb or GB (base 10). */
19976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
19977 (UINT32_C(0x6) << 29)
19978 /* Value is in 1/100th of a percentage of total bandwidth. */
19979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19980 (UINT32_C(0x1) << 29)
19982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
19983 (UINT32_C(0x7) << 29)
19984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
19985 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
19986 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
19987 uint8_t queue_id2_tsa_assign;
19988 /* Strict Priority */
19989 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
19991 /* Enhanced Transmission Selection */
19992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
19995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
19998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
20001 * Priority level for strict priority. Valid only when the
20002 * tsa_assign is 0 - Strict Priority (SP)
20003 * 0..7 - Valid values.
20004 * 8..255 - Reserved.
20006 uint8_t queue_id2_pri_lvl;
20008 * Weight used to allocate remaining BW for this COS after
20009 * servicing guaranteed bandwidths for all COS.
20011 uint8_t queue_id2_bw_weight;
20012 /* ID of CoS Queue 3. */
20015 * Minimum BW allocated to CoS Queue.
20016 * The HWRM will translate this value into byte counter and
20017 * time interval used for this COS inside the device.
20019 uint32_t queue_id3_min_bw;
20020 /* The bandwidth value. */
20021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
20022 UINT32_C(0xfffffff)
20023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
20025 /* The granularity of the value (bits or bytes). */
20026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
20027 UINT32_C(0x10000000)
20028 /* Value is in bits. */
20029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
20030 (UINT32_C(0x0) << 28)
20031 /* Value is in bytes. */
20032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
20033 (UINT32_C(0x1) << 28)
20034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
20035 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
20036 /* bw_value_unit is 3 b */
20037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
20038 UINT32_C(0xe0000000)
20039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
20041 /* Value is in Mb or MB (base 10). */
20042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
20043 (UINT32_C(0x0) << 29)
20044 /* Value is in Kb or KB (base 10). */
20045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
20046 (UINT32_C(0x2) << 29)
20047 /* Value is in bits or bytes. */
20048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
20049 (UINT32_C(0x4) << 29)
20050 /* Value is in Gb or GB (base 10). */
20051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
20052 (UINT32_C(0x6) << 29)
20053 /* Value is in 1/100th of a percentage of total bandwidth. */
20054 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20055 (UINT32_C(0x1) << 29)
20057 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
20058 (UINT32_C(0x7) << 29)
20059 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
20060 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
20062 * Maximum BW allocated to CoS queue.
20063 * The HWRM will translate this value into byte counter and
20064 * time interval used for this COS inside the device.
20066 uint32_t queue_id3_max_bw;
20067 /* The bandwidth value. */
20068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
20069 UINT32_C(0xfffffff)
20070 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
20072 /* The granularity of the value (bits or bytes). */
20073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
20074 UINT32_C(0x10000000)
20075 /* Value is in bits. */
20076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
20077 (UINT32_C(0x0) << 28)
20078 /* Value is in bytes. */
20079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
20080 (UINT32_C(0x1) << 28)
20081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
20082 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
20083 /* bw_value_unit is 3 b */
20084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
20085 UINT32_C(0xe0000000)
20086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
20088 /* Value is in Mb or MB (base 10). */
20089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
20090 (UINT32_C(0x0) << 29)
20091 /* Value is in Kb or KB (base 10). */
20092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
20093 (UINT32_C(0x2) << 29)
20094 /* Value is in bits or bytes. */
20095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
20096 (UINT32_C(0x4) << 29)
20097 /* Value is in Gb or GB (base 10). */
20098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
20099 (UINT32_C(0x6) << 29)
20100 /* Value is in 1/100th of a percentage of total bandwidth. */
20101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20102 (UINT32_C(0x1) << 29)
20104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
20105 (UINT32_C(0x7) << 29)
20106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
20107 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
20108 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20109 uint8_t queue_id3_tsa_assign;
20110 /* Strict Priority */
20111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
20113 /* Enhanced Transmission Selection */
20114 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
20117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
20120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
20123 * Priority level for strict priority. Valid only when the
20124 * tsa_assign is 0 - Strict Priority (SP)
20125 * 0..7 - Valid values.
20126 * 8..255 - Reserved.
20128 uint8_t queue_id3_pri_lvl;
20130 * Weight used to allocate remaining BW for this COS after
20131 * servicing guaranteed bandwidths for all COS.
20133 uint8_t queue_id3_bw_weight;
20134 /* ID of CoS Queue 4. */
20137 * Minimum BW allocated to CoS Queue.
20138 * The HWRM will translate this value into byte counter and
20139 * time interval used for this COS inside the device.
20141 uint32_t queue_id4_min_bw;
20142 /* The bandwidth value. */
20143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
20144 UINT32_C(0xfffffff)
20145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
20147 /* The granularity of the value (bits or bytes). */
20148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
20149 UINT32_C(0x10000000)
20150 /* Value is in bits. */
20151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
20152 (UINT32_C(0x0) << 28)
20153 /* Value is in bytes. */
20154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
20155 (UINT32_C(0x1) << 28)
20156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
20157 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
20158 /* bw_value_unit is 3 b */
20159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
20160 UINT32_C(0xe0000000)
20161 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
20163 /* Value is in Mb or MB (base 10). */
20164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
20165 (UINT32_C(0x0) << 29)
20166 /* Value is in Kb or KB (base 10). */
20167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
20168 (UINT32_C(0x2) << 29)
20169 /* Value is in bits or bytes. */
20170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
20171 (UINT32_C(0x4) << 29)
20172 /* Value is in Gb or GB (base 10). */
20173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
20174 (UINT32_C(0x6) << 29)
20175 /* Value is in 1/100th of a percentage of total bandwidth. */
20176 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20177 (UINT32_C(0x1) << 29)
20179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
20180 (UINT32_C(0x7) << 29)
20181 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
20182 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
20184 * Maximum BW allocated to CoS queue.
20185 * The HWRM will translate this value into byte counter and
20186 * time interval used for this COS inside the device.
20188 uint32_t queue_id4_max_bw;
20189 /* The bandwidth value. */
20190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
20191 UINT32_C(0xfffffff)
20192 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
20194 /* The granularity of the value (bits or bytes). */
20195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
20196 UINT32_C(0x10000000)
20197 /* Value is in bits. */
20198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
20199 (UINT32_C(0x0) << 28)
20200 /* Value is in bytes. */
20201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
20202 (UINT32_C(0x1) << 28)
20203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
20204 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
20205 /* bw_value_unit is 3 b */
20206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
20207 UINT32_C(0xe0000000)
20208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
20210 /* Value is in Mb or MB (base 10). */
20211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
20212 (UINT32_C(0x0) << 29)
20213 /* Value is in Kb or KB (base 10). */
20214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
20215 (UINT32_C(0x2) << 29)
20216 /* Value is in bits or bytes. */
20217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
20218 (UINT32_C(0x4) << 29)
20219 /* Value is in Gb or GB (base 10). */
20220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
20221 (UINT32_C(0x6) << 29)
20222 /* Value is in 1/100th of a percentage of total bandwidth. */
20223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20224 (UINT32_C(0x1) << 29)
20226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
20227 (UINT32_C(0x7) << 29)
20228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
20229 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
20230 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20231 uint8_t queue_id4_tsa_assign;
20232 /* Strict Priority */
20233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
20235 /* Enhanced Transmission Selection */
20236 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
20239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
20242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
20245 * Priority level for strict priority. Valid only when the
20246 * tsa_assign is 0 - Strict Priority (SP)
20247 * 0..7 - Valid values.
20248 * 8..255 - Reserved.
20250 uint8_t queue_id4_pri_lvl;
20252 * Weight used to allocate remaining BW for this COS after
20253 * servicing guaranteed bandwidths for all COS.
20255 uint8_t queue_id4_bw_weight;
20256 /* ID of CoS Queue 5. */
20259 * Minimum BW allocated to CoS Queue.
20260 * The HWRM will translate this value into byte counter and
20261 * time interval used for this COS inside the device.
20263 uint32_t queue_id5_min_bw;
20264 /* The bandwidth value. */
20265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
20266 UINT32_C(0xfffffff)
20267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
20269 /* The granularity of the value (bits or bytes). */
20270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
20271 UINT32_C(0x10000000)
20272 /* Value is in bits. */
20273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
20274 (UINT32_C(0x0) << 28)
20275 /* Value is in bytes. */
20276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
20277 (UINT32_C(0x1) << 28)
20278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
20279 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
20280 /* bw_value_unit is 3 b */
20281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
20282 UINT32_C(0xe0000000)
20283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
20285 /* Value is in Mb or MB (base 10). */
20286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
20287 (UINT32_C(0x0) << 29)
20288 /* Value is in Kb or KB (base 10). */
20289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
20290 (UINT32_C(0x2) << 29)
20291 /* Value is in bits or bytes. */
20292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
20293 (UINT32_C(0x4) << 29)
20294 /* Value is in Gb or GB (base 10). */
20295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
20296 (UINT32_C(0x6) << 29)
20297 /* Value is in 1/100th of a percentage of total bandwidth. */
20298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20299 (UINT32_C(0x1) << 29)
20301 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
20302 (UINT32_C(0x7) << 29)
20303 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
20304 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
20306 * Maximum BW allocated to CoS queue.
20307 * The HWRM will translate this value into byte counter and
20308 * time interval used for this COS inside the device.
20310 uint32_t queue_id5_max_bw;
20311 /* The bandwidth value. */
20312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
20313 UINT32_C(0xfffffff)
20314 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
20316 /* The granularity of the value (bits or bytes). */
20317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
20318 UINT32_C(0x10000000)
20319 /* Value is in bits. */
20320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
20321 (UINT32_C(0x0) << 28)
20322 /* Value is in bytes. */
20323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
20324 (UINT32_C(0x1) << 28)
20325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
20326 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
20327 /* bw_value_unit is 3 b */
20328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
20329 UINT32_C(0xe0000000)
20330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
20332 /* Value is in Mb or MB (base 10). */
20333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
20334 (UINT32_C(0x0) << 29)
20335 /* Value is in Kb or KB (base 10). */
20336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
20337 (UINT32_C(0x2) << 29)
20338 /* Value is in bits or bytes. */
20339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
20340 (UINT32_C(0x4) << 29)
20341 /* Value is in Gb or GB (base 10). */
20342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
20343 (UINT32_C(0x6) << 29)
20344 /* Value is in 1/100th of a percentage of total bandwidth. */
20345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20346 (UINT32_C(0x1) << 29)
20348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
20349 (UINT32_C(0x7) << 29)
20350 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
20351 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
20352 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20353 uint8_t queue_id5_tsa_assign;
20354 /* Strict Priority */
20355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
20357 /* Enhanced Transmission Selection */
20358 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
20361 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
20364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
20367 * Priority level for strict priority. Valid only when the
20368 * tsa_assign is 0 - Strict Priority (SP)
20369 * 0..7 - Valid values.
20370 * 8..255 - Reserved.
20372 uint8_t queue_id5_pri_lvl;
20374 * Weight used to allocate remaining BW for this COS after
20375 * servicing guaranteed bandwidths for all COS.
20377 uint8_t queue_id5_bw_weight;
20378 /* ID of CoS Queue 6. */
20381 * Minimum BW allocated to CoS Queue.
20382 * The HWRM will translate this value into byte counter and
20383 * time interval used for this COS inside the device.
20385 uint32_t queue_id6_min_bw;
20386 /* The bandwidth value. */
20387 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
20388 UINT32_C(0xfffffff)
20389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
20391 /* The granularity of the value (bits or bytes). */
20392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
20393 UINT32_C(0x10000000)
20394 /* Value is in bits. */
20395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
20396 (UINT32_C(0x0) << 28)
20397 /* Value is in bytes. */
20398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
20399 (UINT32_C(0x1) << 28)
20400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
20401 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
20402 /* bw_value_unit is 3 b */
20403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
20404 UINT32_C(0xe0000000)
20405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
20407 /* Value is in Mb or MB (base 10). */
20408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
20409 (UINT32_C(0x0) << 29)
20410 /* Value is in Kb or KB (base 10). */
20411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
20412 (UINT32_C(0x2) << 29)
20413 /* Value is in bits or bytes. */
20414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
20415 (UINT32_C(0x4) << 29)
20416 /* Value is in Gb or GB (base 10). */
20417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
20418 (UINT32_C(0x6) << 29)
20419 /* Value is in 1/100th of a percentage of total bandwidth. */
20420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20421 (UINT32_C(0x1) << 29)
20423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
20424 (UINT32_C(0x7) << 29)
20425 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
20426 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
20428 * Maximum BW allocated to CoS queue.
20429 * The HWRM will translate this value into byte counter and
20430 * time interval used for this COS inside the device.
20432 uint32_t queue_id6_max_bw;
20433 /* The bandwidth value. */
20434 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
20435 UINT32_C(0xfffffff)
20436 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
20438 /* The granularity of the value (bits or bytes). */
20439 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
20440 UINT32_C(0x10000000)
20441 /* Value is in bits. */
20442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
20443 (UINT32_C(0x0) << 28)
20444 /* Value is in bytes. */
20445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
20446 (UINT32_C(0x1) << 28)
20447 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
20448 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
20449 /* bw_value_unit is 3 b */
20450 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
20451 UINT32_C(0xe0000000)
20452 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
20454 /* Value is in Mb or MB (base 10). */
20455 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
20456 (UINT32_C(0x0) << 29)
20457 /* Value is in Kb or KB (base 10). */
20458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
20459 (UINT32_C(0x2) << 29)
20460 /* Value is in bits or bytes. */
20461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
20462 (UINT32_C(0x4) << 29)
20463 /* Value is in Gb or GB (base 10). */
20464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
20465 (UINT32_C(0x6) << 29)
20466 /* Value is in 1/100th of a percentage of total bandwidth. */
20467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20468 (UINT32_C(0x1) << 29)
20470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
20471 (UINT32_C(0x7) << 29)
20472 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
20473 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
20474 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20475 uint8_t queue_id6_tsa_assign;
20476 /* Strict Priority */
20477 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
20479 /* Enhanced Transmission Selection */
20480 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
20483 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
20486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
20489 * Priority level for strict priority. Valid only when the
20490 * tsa_assign is 0 - Strict Priority (SP)
20491 * 0..7 - Valid values.
20492 * 8..255 - Reserved.
20494 uint8_t queue_id6_pri_lvl;
20496 * Weight used to allocate remaining BW for this COS after
20497 * servicing guaranteed bandwidths for all COS.
20499 uint8_t queue_id6_bw_weight;
20500 /* ID of CoS Queue 7. */
20503 * Minimum BW allocated to CoS Queue.
20504 * The HWRM will translate this value into byte counter and
20505 * time interval used for this COS inside the device.
20507 uint32_t queue_id7_min_bw;
20508 /* The bandwidth value. */
20509 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
20510 UINT32_C(0xfffffff)
20511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
20513 /* The granularity of the value (bits or bytes). */
20514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
20515 UINT32_C(0x10000000)
20516 /* Value is in bits. */
20517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
20518 (UINT32_C(0x0) << 28)
20519 /* Value is in bytes. */
20520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
20521 (UINT32_C(0x1) << 28)
20522 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
20523 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
20524 /* bw_value_unit is 3 b */
20525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
20526 UINT32_C(0xe0000000)
20527 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
20529 /* Value is in Mb or MB (base 10). */
20530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
20531 (UINT32_C(0x0) << 29)
20532 /* Value is in Kb or KB (base 10). */
20533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
20534 (UINT32_C(0x2) << 29)
20535 /* Value is in bits or bytes. */
20536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
20537 (UINT32_C(0x4) << 29)
20538 /* Value is in Gb or GB (base 10). */
20539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
20540 (UINT32_C(0x6) << 29)
20541 /* Value is in 1/100th of a percentage of total bandwidth. */
20542 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20543 (UINT32_C(0x1) << 29)
20545 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
20546 (UINT32_C(0x7) << 29)
20547 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
20548 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
20550 * Maximum BW allocated to CoS queue.
20551 * The HWRM will translate this value into byte counter and
20552 * time interval used for this COS inside the device.
20554 uint32_t queue_id7_max_bw;
20555 /* The bandwidth value. */
20556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
20557 UINT32_C(0xfffffff)
20558 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
20560 /* The granularity of the value (bits or bytes). */
20561 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
20562 UINT32_C(0x10000000)
20563 /* Value is in bits. */
20564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
20565 (UINT32_C(0x0) << 28)
20566 /* Value is in bytes. */
20567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
20568 (UINT32_C(0x1) << 28)
20569 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
20570 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
20571 /* bw_value_unit is 3 b */
20572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
20573 UINT32_C(0xe0000000)
20574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
20576 /* Value is in Mb or MB (base 10). */
20577 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
20578 (UINT32_C(0x0) << 29)
20579 /* Value is in Kb or KB (base 10). */
20580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
20581 (UINT32_C(0x2) << 29)
20582 /* Value is in bits or bytes. */
20583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
20584 (UINT32_C(0x4) << 29)
20585 /* Value is in Gb or GB (base 10). */
20586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
20587 (UINT32_C(0x6) << 29)
20588 /* Value is in 1/100th of a percentage of total bandwidth. */
20589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20590 (UINT32_C(0x1) << 29)
20592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
20593 (UINT32_C(0x7) << 29)
20594 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
20595 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
20596 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20597 uint8_t queue_id7_tsa_assign;
20598 /* Strict Priority */
20599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
20601 /* Enhanced Transmission Selection */
20602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
20605 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
20608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
20611 * Priority level for strict priority. Valid only when the
20612 * tsa_assign is 0 - Strict Priority (SP)
20613 * 0..7 - Valid values.
20614 * 8..255 - Reserved.
20616 uint8_t queue_id7_pri_lvl;
20618 * Weight used to allocate remaining BW for this COS after
20619 * servicing guaranteed bandwidths for all COS.
20621 uint8_t queue_id7_bw_weight;
20622 uint8_t unused_2[4];
20624 * This field is used in Output records to indicate that the output
20625 * is completely written to RAM. This field should be read as '1'
20626 * to indicate that the output has been completely written.
20627 * When writing a command completion or response to an internal processor,
20628 * the order of writes has to be such that this field is written last.
20633 /*************************
20634 * hwrm_queue_cos2bw_cfg *
20635 *************************/
20638 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
20639 struct hwrm_queue_cos2bw_cfg_input {
20640 /* The HWRM command request type. */
20643 * The completion ring to send the completion event on. This should
20644 * be the NQ ID returned from the `nq_alloc` HWRM command.
20646 uint16_t cmpl_ring;
20648 * The sequence ID is used by the driver for tracking multiple
20649 * commands. This ID is treated as opaque data by the firmware and
20650 * the value is returned in the `hwrm_resp_hdr` upon completion.
20654 * The target ID of the command:
20655 * * 0x0-0xFFF8 - The function ID
20656 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20657 * * 0xFFFD - Reserved for user-space HWRM interface
20660 uint16_t target_id;
20662 * A physical address pointer pointing to a host buffer that the
20663 * command's response data will be written. This can be either a host
20664 * physical address (HPA) or a guest physical address (GPA) and must
20665 * point to a physically contiguous block of memory.
20667 uint64_t resp_addr;
20671 * If this bit is set to 1, then all queue_id0 related
20672 * parameters in this command are valid.
20674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
20677 * If this bit is set to 1, then all queue_id1 related
20678 * parameters in this command are valid.
20680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
20683 * If this bit is set to 1, then all queue_id2 related
20684 * parameters in this command are valid.
20686 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
20689 * If this bit is set to 1, then all queue_id3 related
20690 * parameters in this command are valid.
20692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
20695 * If this bit is set to 1, then all queue_id4 related
20696 * parameters in this command are valid.
20698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
20701 * If this bit is set to 1, then all queue_id5 related
20702 * parameters in this command are valid.
20704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
20707 * If this bit is set to 1, then all queue_id6 related
20708 * parameters in this command are valid.
20710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
20713 * If this bit is set to 1, then all queue_id7 related
20714 * parameters in this command are valid.
20716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
20719 * Port ID of port for which the table is being configured.
20720 * The HWRM needs to check whether this function is allowed
20721 * to configure TC BW assignment on this port.
20724 /* ID of CoS Queue 0. */
20728 * Minimum BW allocated to CoS Queue.
20729 * The HWRM will translate this value into byte counter and
20730 * time interval used for this COS inside the device.
20732 uint32_t queue_id0_min_bw;
20733 /* The bandwidth value. */
20734 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
20735 UINT32_C(0xfffffff)
20736 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
20738 /* The granularity of the value (bits or bytes). */
20739 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
20740 UINT32_C(0x10000000)
20741 /* Value is in bits. */
20742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
20743 (UINT32_C(0x0) << 28)
20744 /* Value is in bytes. */
20745 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
20746 (UINT32_C(0x1) << 28)
20747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
20748 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
20749 /* bw_value_unit is 3 b */
20750 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
20751 UINT32_C(0xe0000000)
20752 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
20754 /* Value is in Mb or MB (base 10). */
20755 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
20756 (UINT32_C(0x0) << 29)
20757 /* Value is in Kb or KB (base 10). */
20758 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
20759 (UINT32_C(0x2) << 29)
20760 /* Value is in bits or bytes. */
20761 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
20762 (UINT32_C(0x4) << 29)
20763 /* Value is in Gb or GB (base 10). */
20764 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
20765 (UINT32_C(0x6) << 29)
20766 /* Value is in 1/100th of a percentage of total bandwidth. */
20767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20768 (UINT32_C(0x1) << 29)
20770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
20771 (UINT32_C(0x7) << 29)
20772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
20773 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
20775 * Maximum BW allocated to CoS Queue.
20776 * The HWRM will translate this value into byte counter and
20777 * time interval used for this COS inside the device.
20779 uint32_t queue_id0_max_bw;
20780 /* The bandwidth value. */
20781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
20782 UINT32_C(0xfffffff)
20783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
20785 /* The granularity of the value (bits or bytes). */
20786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
20787 UINT32_C(0x10000000)
20788 /* Value is in bits. */
20789 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
20790 (UINT32_C(0x0) << 28)
20791 /* Value is in bytes. */
20792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
20793 (UINT32_C(0x1) << 28)
20794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
20795 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
20796 /* bw_value_unit is 3 b */
20797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
20798 UINT32_C(0xe0000000)
20799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
20801 /* Value is in Mb or MB (base 10). */
20802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
20803 (UINT32_C(0x0) << 29)
20804 /* Value is in Kb or KB (base 10). */
20805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
20806 (UINT32_C(0x2) << 29)
20807 /* Value is in bits or bytes. */
20808 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
20809 (UINT32_C(0x4) << 29)
20810 /* Value is in Gb or GB (base 10). */
20811 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
20812 (UINT32_C(0x6) << 29)
20813 /* Value is in 1/100th of a percentage of total bandwidth. */
20814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20815 (UINT32_C(0x1) << 29)
20817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
20818 (UINT32_C(0x7) << 29)
20819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
20820 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
20821 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20822 uint8_t queue_id0_tsa_assign;
20823 /* Strict Priority */
20824 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
20826 /* Enhanced Transmission Selection */
20827 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
20830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
20833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
20836 * Priority level for strict priority. Valid only when the
20837 * tsa_assign is 0 - Strict Priority (SP)
20838 * 0..7 - Valid values.
20839 * 8..255 - Reserved.
20841 uint8_t queue_id0_pri_lvl;
20843 * Weight used to allocate remaining BW for this COS after
20844 * servicing guaranteed bandwidths for all COS.
20846 uint8_t queue_id0_bw_weight;
20847 /* ID of CoS Queue 1. */
20850 * Minimum BW allocated to CoS Queue.
20851 * The HWRM will translate this value into byte counter and
20852 * time interval used for this COS inside the device.
20854 uint32_t queue_id1_min_bw;
20855 /* The bandwidth value. */
20856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
20857 UINT32_C(0xfffffff)
20858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
20860 /* The granularity of the value (bits or bytes). */
20861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
20862 UINT32_C(0x10000000)
20863 /* Value is in bits. */
20864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
20865 (UINT32_C(0x0) << 28)
20866 /* Value is in bytes. */
20867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
20868 (UINT32_C(0x1) << 28)
20869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
20870 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
20871 /* bw_value_unit is 3 b */
20872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
20873 UINT32_C(0xe0000000)
20874 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
20876 /* Value is in Mb or MB (base 10). */
20877 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
20878 (UINT32_C(0x0) << 29)
20879 /* Value is in Kb or KB (base 10). */
20880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
20881 (UINT32_C(0x2) << 29)
20882 /* Value is in bits or bytes. */
20883 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
20884 (UINT32_C(0x4) << 29)
20885 /* Value is in Gb or GB (base 10). */
20886 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
20887 (UINT32_C(0x6) << 29)
20888 /* Value is in 1/100th of a percentage of total bandwidth. */
20889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
20890 (UINT32_C(0x1) << 29)
20892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
20893 (UINT32_C(0x7) << 29)
20894 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
20895 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
20897 * Maximum BW allocated to CoS queue.
20898 * The HWRM will translate this value into byte counter and
20899 * time interval used for this COS inside the device.
20901 uint32_t queue_id1_max_bw;
20902 /* The bandwidth value. */
20903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
20904 UINT32_C(0xfffffff)
20905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
20907 /* The granularity of the value (bits or bytes). */
20908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
20909 UINT32_C(0x10000000)
20910 /* Value is in bits. */
20911 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
20912 (UINT32_C(0x0) << 28)
20913 /* Value is in bytes. */
20914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
20915 (UINT32_C(0x1) << 28)
20916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
20917 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
20918 /* bw_value_unit is 3 b */
20919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
20920 UINT32_C(0xe0000000)
20921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
20923 /* Value is in Mb or MB (base 10). */
20924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
20925 (UINT32_C(0x0) << 29)
20926 /* Value is in Kb or KB (base 10). */
20927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
20928 (UINT32_C(0x2) << 29)
20929 /* Value is in bits or bytes. */
20930 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
20931 (UINT32_C(0x4) << 29)
20932 /* Value is in Gb or GB (base 10). */
20933 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
20934 (UINT32_C(0x6) << 29)
20935 /* Value is in 1/100th of a percentage of total bandwidth. */
20936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20937 (UINT32_C(0x1) << 29)
20939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
20940 (UINT32_C(0x7) << 29)
20941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
20942 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
20943 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
20944 uint8_t queue_id1_tsa_assign;
20945 /* Strict Priority */
20946 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
20948 /* Enhanced Transmission Selection */
20949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
20952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
20955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
20958 * Priority level for strict priority. Valid only when the
20959 * tsa_assign is 0 - Strict Priority (SP)
20960 * 0..7 - Valid values.
20961 * 8..255 - Reserved.
20963 uint8_t queue_id1_pri_lvl;
20965 * Weight used to allocate remaining BW for this COS after
20966 * servicing guaranteed bandwidths for all COS.
20968 uint8_t queue_id1_bw_weight;
20969 /* ID of CoS Queue 2. */
20972 * Minimum BW allocated to CoS Queue.
20973 * The HWRM will translate this value into byte counter and
20974 * time interval used for this COS inside the device.
20976 uint32_t queue_id2_min_bw;
20977 /* The bandwidth value. */
20978 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
20979 UINT32_C(0xfffffff)
20980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
20982 /* The granularity of the value (bits or bytes). */
20983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
20984 UINT32_C(0x10000000)
20985 /* Value is in bits. */
20986 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
20987 (UINT32_C(0x0) << 28)
20988 /* Value is in bytes. */
20989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
20990 (UINT32_C(0x1) << 28)
20991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
20992 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
20993 /* bw_value_unit is 3 b */
20994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
20995 UINT32_C(0xe0000000)
20996 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
20998 /* Value is in Mb or MB (base 10). */
20999 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
21000 (UINT32_C(0x0) << 29)
21001 /* Value is in Kb or KB (base 10). */
21002 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
21003 (UINT32_C(0x2) << 29)
21004 /* Value is in bits or bytes. */
21005 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
21006 (UINT32_C(0x4) << 29)
21007 /* Value is in Gb or GB (base 10). */
21008 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
21009 (UINT32_C(0x6) << 29)
21010 /* Value is in 1/100th of a percentage of total bandwidth. */
21011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21012 (UINT32_C(0x1) << 29)
21014 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
21015 (UINT32_C(0x7) << 29)
21016 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
21017 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
21019 * Maximum BW allocated to CoS queue.
21020 * The HWRM will translate this value into byte counter and
21021 * time interval used for this COS inside the device.
21023 uint32_t queue_id2_max_bw;
21024 /* The bandwidth value. */
21025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
21026 UINT32_C(0xfffffff)
21027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
21029 /* The granularity of the value (bits or bytes). */
21030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
21031 UINT32_C(0x10000000)
21032 /* Value is in bits. */
21033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
21034 (UINT32_C(0x0) << 28)
21035 /* Value is in bytes. */
21036 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
21037 (UINT32_C(0x1) << 28)
21038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
21039 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
21040 /* bw_value_unit is 3 b */
21041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
21042 UINT32_C(0xe0000000)
21043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
21045 /* Value is in Mb or MB (base 10). */
21046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
21047 (UINT32_C(0x0) << 29)
21048 /* Value is in Kb or KB (base 10). */
21049 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
21050 (UINT32_C(0x2) << 29)
21051 /* Value is in bits or bytes. */
21052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
21053 (UINT32_C(0x4) << 29)
21054 /* Value is in Gb or GB (base 10). */
21055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
21056 (UINT32_C(0x6) << 29)
21057 /* Value is in 1/100th of a percentage of total bandwidth. */
21058 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21059 (UINT32_C(0x1) << 29)
21061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
21062 (UINT32_C(0x7) << 29)
21063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
21064 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
21065 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21066 uint8_t queue_id2_tsa_assign;
21067 /* Strict Priority */
21068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
21070 /* Enhanced Transmission Selection */
21071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
21074 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
21077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
21080 * Priority level for strict priority. Valid only when the
21081 * tsa_assign is 0 - Strict Priority (SP)
21082 * 0..7 - Valid values.
21083 * 8..255 - Reserved.
21085 uint8_t queue_id2_pri_lvl;
21087 * Weight used to allocate remaining BW for this COS after
21088 * servicing guaranteed bandwidths for all COS.
21090 uint8_t queue_id2_bw_weight;
21091 /* ID of CoS Queue 3. */
21094 * Minimum BW allocated to CoS Queue.
21095 * The HWRM will translate this value into byte counter and
21096 * time interval used for this COS inside the device.
21098 uint32_t queue_id3_min_bw;
21099 /* The bandwidth value. */
21100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
21101 UINT32_C(0xfffffff)
21102 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
21104 /* The granularity of the value (bits or bytes). */
21105 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
21106 UINT32_C(0x10000000)
21107 /* Value is in bits. */
21108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
21109 (UINT32_C(0x0) << 28)
21110 /* Value is in bytes. */
21111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
21112 (UINT32_C(0x1) << 28)
21113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
21114 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
21115 /* bw_value_unit is 3 b */
21116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
21117 UINT32_C(0xe0000000)
21118 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
21120 /* Value is in Mb or MB (base 10). */
21121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
21122 (UINT32_C(0x0) << 29)
21123 /* Value is in Kb or KB (base 10). */
21124 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
21125 (UINT32_C(0x2) << 29)
21126 /* Value is in bits or bytes. */
21127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
21128 (UINT32_C(0x4) << 29)
21129 /* Value is in Gb or GB (base 10). */
21130 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
21131 (UINT32_C(0x6) << 29)
21132 /* Value is in 1/100th of a percentage of total bandwidth. */
21133 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21134 (UINT32_C(0x1) << 29)
21136 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
21137 (UINT32_C(0x7) << 29)
21138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
21139 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
21141 * Maximum BW allocated to CoS queue.
21142 * The HWRM will translate this value into byte counter and
21143 * time interval used for this COS inside the device.
21145 uint32_t queue_id3_max_bw;
21146 /* The bandwidth value. */
21147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
21148 UINT32_C(0xfffffff)
21149 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
21151 /* The granularity of the value (bits or bytes). */
21152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
21153 UINT32_C(0x10000000)
21154 /* Value is in bits. */
21155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
21156 (UINT32_C(0x0) << 28)
21157 /* Value is in bytes. */
21158 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
21159 (UINT32_C(0x1) << 28)
21160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
21161 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
21162 /* bw_value_unit is 3 b */
21163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
21164 UINT32_C(0xe0000000)
21165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
21167 /* Value is in Mb or MB (base 10). */
21168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
21169 (UINT32_C(0x0) << 29)
21170 /* Value is in Kb or KB (base 10). */
21171 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
21172 (UINT32_C(0x2) << 29)
21173 /* Value is in bits or bytes. */
21174 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
21175 (UINT32_C(0x4) << 29)
21176 /* Value is in Gb or GB (base 10). */
21177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
21178 (UINT32_C(0x6) << 29)
21179 /* Value is in 1/100th of a percentage of total bandwidth. */
21180 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21181 (UINT32_C(0x1) << 29)
21183 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
21184 (UINT32_C(0x7) << 29)
21185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
21186 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
21187 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21188 uint8_t queue_id3_tsa_assign;
21189 /* Strict Priority */
21190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
21192 /* Enhanced Transmission Selection */
21193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
21196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
21199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
21202 * Priority level for strict priority. Valid only when the
21203 * tsa_assign is 0 - Strict Priority (SP)
21204 * 0..7 - Valid values.
21205 * 8..255 - Reserved.
21207 uint8_t queue_id3_pri_lvl;
21209 * Weight used to allocate remaining BW for this COS after
21210 * servicing guaranteed bandwidths for all COS.
21212 uint8_t queue_id3_bw_weight;
21213 /* ID of CoS Queue 4. */
21216 * Minimum BW allocated to CoS Queue.
21217 * The HWRM will translate this value into byte counter and
21218 * time interval used for this COS inside the device.
21220 uint32_t queue_id4_min_bw;
21221 /* The bandwidth value. */
21222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
21223 UINT32_C(0xfffffff)
21224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
21226 /* The granularity of the value (bits or bytes). */
21227 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
21228 UINT32_C(0x10000000)
21229 /* Value is in bits. */
21230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
21231 (UINT32_C(0x0) << 28)
21232 /* Value is in bytes. */
21233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
21234 (UINT32_C(0x1) << 28)
21235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
21236 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
21237 /* bw_value_unit is 3 b */
21238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
21239 UINT32_C(0xe0000000)
21240 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
21242 /* Value is in Mb or MB (base 10). */
21243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
21244 (UINT32_C(0x0) << 29)
21245 /* Value is in Kb or KB (base 10). */
21246 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
21247 (UINT32_C(0x2) << 29)
21248 /* Value is in bits or bytes. */
21249 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
21250 (UINT32_C(0x4) << 29)
21251 /* Value is in Gb or GB (base 10). */
21252 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
21253 (UINT32_C(0x6) << 29)
21254 /* Value is in 1/100th of a percentage of total bandwidth. */
21255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21256 (UINT32_C(0x1) << 29)
21258 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
21259 (UINT32_C(0x7) << 29)
21260 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
21261 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
21263 * Maximum BW allocated to CoS queue.
21264 * The HWRM will translate this value into byte counter and
21265 * time interval used for this COS inside the device.
21267 uint32_t queue_id4_max_bw;
21268 /* The bandwidth value. */
21269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
21270 UINT32_C(0xfffffff)
21271 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
21273 /* The granularity of the value (bits or bytes). */
21274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
21275 UINT32_C(0x10000000)
21276 /* Value is in bits. */
21277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
21278 (UINT32_C(0x0) << 28)
21279 /* Value is in bytes. */
21280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
21281 (UINT32_C(0x1) << 28)
21282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
21283 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
21284 /* bw_value_unit is 3 b */
21285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
21286 UINT32_C(0xe0000000)
21287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
21289 /* Value is in Mb or MB (base 10). */
21290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
21291 (UINT32_C(0x0) << 29)
21292 /* Value is in Kb or KB (base 10). */
21293 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
21294 (UINT32_C(0x2) << 29)
21295 /* Value is in bits or bytes. */
21296 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
21297 (UINT32_C(0x4) << 29)
21298 /* Value is in Gb or GB (base 10). */
21299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
21300 (UINT32_C(0x6) << 29)
21301 /* Value is in 1/100th of a percentage of total bandwidth. */
21302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21303 (UINT32_C(0x1) << 29)
21305 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
21306 (UINT32_C(0x7) << 29)
21307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
21308 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
21309 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21310 uint8_t queue_id4_tsa_assign;
21311 /* Strict Priority */
21312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
21314 /* Enhanced Transmission Selection */
21315 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
21318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
21321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
21324 * Priority level for strict priority. Valid only when the
21325 * tsa_assign is 0 - Strict Priority (SP)
21326 * 0..7 - Valid values.
21327 * 8..255 - Reserved.
21329 uint8_t queue_id4_pri_lvl;
21331 * Weight used to allocate remaining BW for this COS after
21332 * servicing guaranteed bandwidths for all COS.
21334 uint8_t queue_id4_bw_weight;
21335 /* ID of CoS Queue 5. */
21338 * Minimum BW allocated to CoS Queue.
21339 * The HWRM will translate this value into byte counter and
21340 * time interval used for this COS inside the device.
21342 uint32_t queue_id5_min_bw;
21343 /* The bandwidth value. */
21344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
21345 UINT32_C(0xfffffff)
21346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
21348 /* The granularity of the value (bits or bytes). */
21349 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
21350 UINT32_C(0x10000000)
21351 /* Value is in bits. */
21352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
21353 (UINT32_C(0x0) << 28)
21354 /* Value is in bytes. */
21355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
21356 (UINT32_C(0x1) << 28)
21357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
21358 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
21359 /* bw_value_unit is 3 b */
21360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
21361 UINT32_C(0xe0000000)
21362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
21364 /* Value is in Mb or MB (base 10). */
21365 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
21366 (UINT32_C(0x0) << 29)
21367 /* Value is in Kb or KB (base 10). */
21368 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
21369 (UINT32_C(0x2) << 29)
21370 /* Value is in bits or bytes. */
21371 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
21372 (UINT32_C(0x4) << 29)
21373 /* Value is in Gb or GB (base 10). */
21374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
21375 (UINT32_C(0x6) << 29)
21376 /* Value is in 1/100th of a percentage of total bandwidth. */
21377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21378 (UINT32_C(0x1) << 29)
21380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
21381 (UINT32_C(0x7) << 29)
21382 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
21383 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
21385 * Maximum BW allocated to CoS queue.
21386 * The HWRM will translate this value into byte counter and
21387 * time interval used for this COS inside the device.
21389 uint32_t queue_id5_max_bw;
21390 /* The bandwidth value. */
21391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
21392 UINT32_C(0xfffffff)
21393 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
21395 /* The granularity of the value (bits or bytes). */
21396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
21397 UINT32_C(0x10000000)
21398 /* Value is in bits. */
21399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
21400 (UINT32_C(0x0) << 28)
21401 /* Value is in bytes. */
21402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
21403 (UINT32_C(0x1) << 28)
21404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
21405 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
21406 /* bw_value_unit is 3 b */
21407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
21408 UINT32_C(0xe0000000)
21409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
21411 /* Value is in Mb or MB (base 10). */
21412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
21413 (UINT32_C(0x0) << 29)
21414 /* Value is in Kb or KB (base 10). */
21415 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
21416 (UINT32_C(0x2) << 29)
21417 /* Value is in bits or bytes. */
21418 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
21419 (UINT32_C(0x4) << 29)
21420 /* Value is in Gb or GB (base 10). */
21421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
21422 (UINT32_C(0x6) << 29)
21423 /* Value is in 1/100th of a percentage of total bandwidth. */
21424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21425 (UINT32_C(0x1) << 29)
21427 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
21428 (UINT32_C(0x7) << 29)
21429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
21430 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
21431 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21432 uint8_t queue_id5_tsa_assign;
21433 /* Strict Priority */
21434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
21436 /* Enhanced Transmission Selection */
21437 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
21440 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
21443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
21446 * Priority level for strict priority. Valid only when the
21447 * tsa_assign is 0 - Strict Priority (SP)
21448 * 0..7 - Valid values.
21449 * 8..255 - Reserved.
21451 uint8_t queue_id5_pri_lvl;
21453 * Weight used to allocate remaining BW for this COS after
21454 * servicing guaranteed bandwidths for all COS.
21456 uint8_t queue_id5_bw_weight;
21457 /* ID of CoS Queue 6. */
21460 * Minimum BW allocated to CoS Queue.
21461 * The HWRM will translate this value into byte counter and
21462 * time interval used for this COS inside the device.
21464 uint32_t queue_id6_min_bw;
21465 /* The bandwidth value. */
21466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
21467 UINT32_C(0xfffffff)
21468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
21470 /* The granularity of the value (bits or bytes). */
21471 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
21472 UINT32_C(0x10000000)
21473 /* Value is in bits. */
21474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
21475 (UINT32_C(0x0) << 28)
21476 /* Value is in bytes. */
21477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
21478 (UINT32_C(0x1) << 28)
21479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
21480 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
21481 /* bw_value_unit is 3 b */
21482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
21483 UINT32_C(0xe0000000)
21484 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
21486 /* Value is in Mb or MB (base 10). */
21487 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
21488 (UINT32_C(0x0) << 29)
21489 /* Value is in Kb or KB (base 10). */
21490 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
21491 (UINT32_C(0x2) << 29)
21492 /* Value is in bits or bytes. */
21493 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
21494 (UINT32_C(0x4) << 29)
21495 /* Value is in Gb or GB (base 10). */
21496 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
21497 (UINT32_C(0x6) << 29)
21498 /* Value is in 1/100th of a percentage of total bandwidth. */
21499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21500 (UINT32_C(0x1) << 29)
21502 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
21503 (UINT32_C(0x7) << 29)
21504 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
21505 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
21507 * Maximum BW allocated to CoS queue.
21508 * The HWRM will translate this value into byte counter and
21509 * time interval used for this COS inside the device.
21511 uint32_t queue_id6_max_bw;
21512 /* The bandwidth value. */
21513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
21514 UINT32_C(0xfffffff)
21515 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
21517 /* The granularity of the value (bits or bytes). */
21518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
21519 UINT32_C(0x10000000)
21520 /* Value is in bits. */
21521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
21522 (UINT32_C(0x0) << 28)
21523 /* Value is in bytes. */
21524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
21525 (UINT32_C(0x1) << 28)
21526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
21527 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
21528 /* bw_value_unit is 3 b */
21529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
21530 UINT32_C(0xe0000000)
21531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
21533 /* Value is in Mb or MB (base 10). */
21534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
21535 (UINT32_C(0x0) << 29)
21536 /* Value is in Kb or KB (base 10). */
21537 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
21538 (UINT32_C(0x2) << 29)
21539 /* Value is in bits or bytes. */
21540 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
21541 (UINT32_C(0x4) << 29)
21542 /* Value is in Gb or GB (base 10). */
21543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
21544 (UINT32_C(0x6) << 29)
21545 /* Value is in 1/100th of a percentage of total bandwidth. */
21546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21547 (UINT32_C(0x1) << 29)
21549 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
21550 (UINT32_C(0x7) << 29)
21551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
21552 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
21553 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21554 uint8_t queue_id6_tsa_assign;
21555 /* Strict Priority */
21556 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
21558 /* Enhanced Transmission Selection */
21559 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
21562 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
21565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
21568 * Priority level for strict priority. Valid only when the
21569 * tsa_assign is 0 - Strict Priority (SP)
21570 * 0..7 - Valid values.
21571 * 8..255 - Reserved.
21573 uint8_t queue_id6_pri_lvl;
21575 * Weight used to allocate remaining BW for this COS after
21576 * servicing guaranteed bandwidths for all COS.
21578 uint8_t queue_id6_bw_weight;
21579 /* ID of CoS Queue 7. */
21582 * Minimum BW allocated to CoS Queue.
21583 * The HWRM will translate this value into byte counter and
21584 * time interval used for this COS inside the device.
21586 uint32_t queue_id7_min_bw;
21587 /* The bandwidth value. */
21588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
21589 UINT32_C(0xfffffff)
21590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
21592 /* The granularity of the value (bits or bytes). */
21593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
21594 UINT32_C(0x10000000)
21595 /* Value is in bits. */
21596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
21597 (UINT32_C(0x0) << 28)
21598 /* Value is in bytes. */
21599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
21600 (UINT32_C(0x1) << 28)
21601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
21602 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
21603 /* bw_value_unit is 3 b */
21604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
21605 UINT32_C(0xe0000000)
21606 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
21608 /* Value is in Mb or MB (base 10). */
21609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
21610 (UINT32_C(0x0) << 29)
21611 /* Value is in Kb or KB (base 10). */
21612 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
21613 (UINT32_C(0x2) << 29)
21614 /* Value is in bits or bytes. */
21615 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
21616 (UINT32_C(0x4) << 29)
21617 /* Value is in Gb or GB (base 10). */
21618 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
21619 (UINT32_C(0x6) << 29)
21620 /* Value is in 1/100th of a percentage of total bandwidth. */
21621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
21622 (UINT32_C(0x1) << 29)
21624 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
21625 (UINT32_C(0x7) << 29)
21626 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
21627 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
21629 * Maximum BW allocated to CoS queue.
21630 * The HWRM will translate this value into byte counter and
21631 * time interval used for this COS inside the device.
21633 uint32_t queue_id7_max_bw;
21634 /* The bandwidth value. */
21635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
21636 UINT32_C(0xfffffff)
21637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
21639 /* The granularity of the value (bits or bytes). */
21640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
21641 UINT32_C(0x10000000)
21642 /* Value is in bits. */
21643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
21644 (UINT32_C(0x0) << 28)
21645 /* Value is in bytes. */
21646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
21647 (UINT32_C(0x1) << 28)
21648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
21649 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
21650 /* bw_value_unit is 3 b */
21651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
21652 UINT32_C(0xe0000000)
21653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
21655 /* Value is in Mb or MB (base 10). */
21656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
21657 (UINT32_C(0x0) << 29)
21658 /* Value is in Kb or KB (base 10). */
21659 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
21660 (UINT32_C(0x2) << 29)
21661 /* Value is in bits or bytes. */
21662 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
21663 (UINT32_C(0x4) << 29)
21664 /* Value is in Gb or GB (base 10). */
21665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
21666 (UINT32_C(0x6) << 29)
21667 /* Value is in 1/100th of a percentage of total bandwidth. */
21668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
21669 (UINT32_C(0x1) << 29)
21671 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
21672 (UINT32_C(0x7) << 29)
21673 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
21674 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
21675 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
21676 uint8_t queue_id7_tsa_assign;
21677 /* Strict Priority */
21678 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
21680 /* Enhanced Transmission Selection */
21681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
21684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
21687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
21690 * Priority level for strict priority. Valid only when the
21691 * tsa_assign is 0 - Strict Priority (SP)
21692 * 0..7 - Valid values.
21693 * 8..255 - Reserved.
21695 uint8_t queue_id7_pri_lvl;
21697 * Weight used to allocate remaining BW for this COS after
21698 * servicing guaranteed bandwidths for all COS.
21700 uint8_t queue_id7_bw_weight;
21701 uint8_t unused_1[5];
21704 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
21705 struct hwrm_queue_cos2bw_cfg_output {
21706 /* The specific error status for the command. */
21707 uint16_t error_code;
21708 /* The HWRM command request type. */
21710 /* The sequence ID from the original command. */
21712 /* The length of the response data in number of bytes. */
21714 uint8_t unused_0[7];
21716 * This field is used in Output records to indicate that the output
21717 * is completely written to RAM. This field should be read as '1'
21718 * to indicate that the output has been completely written.
21719 * When writing a command completion or response to an internal processor,
21720 * the order of writes has to be such that this field is written last.
21725 /*************************
21726 * hwrm_queue_dscp_qcaps *
21727 *************************/
21730 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
21731 struct hwrm_queue_dscp_qcaps_input {
21732 /* The HWRM command request type. */
21735 * The completion ring to send the completion event on. This should
21736 * be the NQ ID returned from the `nq_alloc` HWRM command.
21738 uint16_t cmpl_ring;
21740 * The sequence ID is used by the driver for tracking multiple
21741 * commands. This ID is treated as opaque data by the firmware and
21742 * the value is returned in the `hwrm_resp_hdr` upon completion.
21746 * The target ID of the command:
21747 * * 0x0-0xFFF8 - The function ID
21748 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21749 * * 0xFFFD - Reserved for user-space HWRM interface
21752 uint16_t target_id;
21754 * A physical address pointer pointing to a host buffer that the
21755 * command's response data will be written. This can be either a host
21756 * physical address (HPA) or a guest physical address (GPA) and must
21757 * point to a physically contiguous block of memory.
21759 uint64_t resp_addr;
21761 * Port ID of port for which the table is being configured.
21762 * The HWRM needs to check whether this function is allowed
21763 * to configure pri2cos mapping on this port.
21766 uint8_t unused_0[7];
21769 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
21770 struct hwrm_queue_dscp_qcaps_output {
21771 /* The specific error status for the command. */
21772 uint16_t error_code;
21773 /* The HWRM command request type. */
21775 /* The sequence ID from the original command. */
21777 /* The length of the response data in number of bytes. */
21779 /* The number of bits provided by the hardware for the DSCP value. */
21780 uint8_t num_dscp_bits;
21782 /* Max number of DSCP-MASK-PRI entries supported. */
21783 uint16_t max_entries;
21784 uint8_t unused_1[3];
21786 * This field is used in Output records to indicate that the output
21787 * is completely written to RAM. This field should be read as '1'
21788 * to indicate that the output has been completely written.
21789 * When writing a command completion or response to an internal processor,
21790 * the order of writes has to be such that this field is written last.
21795 /****************************
21796 * hwrm_queue_dscp2pri_qcfg *
21797 ****************************/
21800 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
21801 struct hwrm_queue_dscp2pri_qcfg_input {
21802 /* The HWRM command request type. */
21805 * The completion ring to send the completion event on. This should
21806 * be the NQ ID returned from the `nq_alloc` HWRM command.
21808 uint16_t cmpl_ring;
21810 * The sequence ID is used by the driver for tracking multiple
21811 * commands. This ID is treated as opaque data by the firmware and
21812 * the value is returned in the `hwrm_resp_hdr` upon completion.
21816 * The target ID of the command:
21817 * * 0x0-0xFFF8 - The function ID
21818 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21819 * * 0xFFFD - Reserved for user-space HWRM interface
21822 uint16_t target_id;
21824 * A physical address pointer pointing to a host buffer that the
21825 * command's response data will be written. This can be either a host
21826 * physical address (HPA) or a guest physical address (GPA) and must
21827 * point to a physically contiguous block of memory.
21829 uint64_t resp_addr;
21831 * This is the host address where the 24-bits DSCP-MASK-PRI
21832 * tuple(s) will be copied to.
21834 uint64_t dest_data_addr;
21836 * Port ID of port for which the table is being configured.
21837 * The HWRM needs to check whether this function is allowed
21838 * to configure pri2cos mapping on this port.
21842 /* Size of the buffer pointed to by dest_data_addr. */
21843 uint16_t dest_data_buffer_size;
21844 uint8_t unused_1[4];
21847 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
21848 struct hwrm_queue_dscp2pri_qcfg_output {
21849 /* The specific error status for the command. */
21850 uint16_t error_code;
21851 /* The HWRM command request type. */
21853 /* The sequence ID from the original command. */
21855 /* The length of the response data in number of bytes. */
21858 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
21859 * by the dest_data_addr.
21861 uint16_t entry_cnt;
21863 * This is the default PRI which un-initialized DSCP values are
21866 uint8_t default_pri;
21867 uint8_t unused_0[4];
21869 * This field is used in Output records to indicate that the output
21870 * is completely written to RAM. This field should be read as '1'
21871 * to indicate that the output has been completely written.
21872 * When writing a command completion or response to an internal processor,
21873 * the order of writes has to be such that this field is written last.
21878 /***************************
21879 * hwrm_queue_dscp2pri_cfg *
21880 ***************************/
21883 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
21884 struct hwrm_queue_dscp2pri_cfg_input {
21885 /* The HWRM command request type. */
21888 * The completion ring to send the completion event on. This should
21889 * be the NQ ID returned from the `nq_alloc` HWRM command.
21891 uint16_t cmpl_ring;
21893 * The sequence ID is used by the driver for tracking multiple
21894 * commands. This ID is treated as opaque data by the firmware and
21895 * the value is returned in the `hwrm_resp_hdr` upon completion.
21899 * The target ID of the command:
21900 * * 0x0-0xFFF8 - The function ID
21901 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21902 * * 0xFFFD - Reserved for user-space HWRM interface
21905 uint16_t target_id;
21907 * A physical address pointer pointing to a host buffer that the
21908 * command's response data will be written. This can be either a host
21909 * physical address (HPA) or a guest physical address (GPA) and must
21910 * point to a physically contiguous block of memory.
21912 uint64_t resp_addr;
21914 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
21915 * will be copied from.
21917 uint64_t src_data_addr;
21919 /* use_hw_default_pri is 1 b */
21920 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
21924 * This bit must be '1' for the default_pri field to be
21927 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
21930 * Port ID of port for which the table is being configured.
21931 * The HWRM needs to check whether this function is allowed
21932 * to configure pri2cos mapping on this port.
21936 * This is the default PRI which un-initialized DSCP values will be
21939 uint8_t default_pri;
21941 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
21942 * to by src_data_addr.
21944 uint16_t entry_cnt;
21945 uint8_t unused_0[4];
21948 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
21949 struct hwrm_queue_dscp2pri_cfg_output {
21950 /* The specific error status for the command. */
21951 uint16_t error_code;
21952 /* The HWRM command request type. */
21954 /* The sequence ID from the original command. */
21956 /* The length of the response data in number of bytes. */
21958 uint8_t unused_0[7];
21960 * This field is used in Output records to indicate that the output
21961 * is completely written to RAM. This field should be read as '1'
21962 * to indicate that the output has been completely written.
21963 * When writing a command completion or response to an internal processor,
21964 * the order of writes has to be such that this field is written last.
21969 /*************************
21970 * hwrm_queue_mpls_qcaps *
21971 *************************/
21974 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
21975 struct hwrm_queue_mpls_qcaps_input {
21976 /* The HWRM command request type. */
21979 * The completion ring to send the completion event on. This should
21980 * be the NQ ID returned from the `nq_alloc` HWRM command.
21982 uint16_t cmpl_ring;
21984 * The sequence ID is used by the driver for tracking multiple
21985 * commands. This ID is treated as opaque data by the firmware and
21986 * the value is returned in the `hwrm_resp_hdr` upon completion.
21990 * The target ID of the command:
21991 * * 0x0-0xFFF8 - The function ID
21992 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21993 * * 0xFFFD - Reserved for user-space HWRM interface
21996 uint16_t target_id;
21998 * A physical address pointer pointing to a host buffer that the
21999 * command's response data will be written. This can be either a host
22000 * physical address (HPA) or a guest physical address (GPA) and must
22001 * point to a physically contiguous block of memory.
22003 uint64_t resp_addr;
22005 * Port ID of port for which the table is being configured.
22006 * The HWRM needs to check whether this function is allowed
22007 * to configure MPLS TC(EXP) to pri mapping on this port.
22010 uint8_t unused_0[7];
22013 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
22014 struct hwrm_queue_mpls_qcaps_output {
22015 /* The specific error status for the command. */
22016 uint16_t error_code;
22017 /* The HWRM command request type. */
22019 /* The sequence ID from the original command. */
22021 /* The length of the response data in number of bytes. */
22024 * Bitmask indicating which queues can be configured by the
22025 * hwrm_queue_mplstc2pri_cfg command.
22027 * Each bit represents a specific pri where bit 0 represents
22028 * pri 0 and bit 7 represents pri 7.
22029 * # A value of 0 indicates that the pri is not configurable
22030 * by the hwrm_queue_mplstc2pri_cfg command.
22031 * # A value of 1 indicates that the pri is configurable.
22032 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
22033 * trying to configure a pri that is not configurable.
22035 uint8_t queue_mplstc2pri_cfg_allowed;
22037 * This is the default PRI which un-initialized MPLS values will be
22040 uint8_t hw_default_pri;
22041 uint8_t unused_0[5];
22043 * This field is used in Output records to indicate that the output
22044 * is completely written to RAM. This field should be read as '1'
22045 * to indicate that the output has been completely written.
22046 * When writing a command completion or response to an internal processor,
22047 * the order of writes has to be such that this field is written last.
22052 /******************************
22053 * hwrm_queue_mplstc2pri_qcfg *
22054 ******************************/
22057 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
22058 struct hwrm_queue_mplstc2pri_qcfg_input {
22059 /* The HWRM command request type. */
22062 * The completion ring to send the completion event on. This should
22063 * be the NQ ID returned from the `nq_alloc` HWRM command.
22065 uint16_t cmpl_ring;
22067 * The sequence ID is used by the driver for tracking multiple
22068 * commands. This ID is treated as opaque data by the firmware and
22069 * the value is returned in the `hwrm_resp_hdr` upon completion.
22073 * The target ID of the command:
22074 * * 0x0-0xFFF8 - The function ID
22075 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22076 * * 0xFFFD - Reserved for user-space HWRM interface
22079 uint16_t target_id;
22081 * A physical address pointer pointing to a host buffer that the
22082 * command's response data will be written. This can be either a host
22083 * physical address (HPA) or a guest physical address (GPA) and must
22084 * point to a physically contiguous block of memory.
22086 uint64_t resp_addr;
22088 * Port ID of port for which the table is being configured.
22089 * The HWRM needs to check whether this function is allowed
22090 * to configure MPLS TC(EXP) to pri mapping on this port.
22093 uint8_t unused_0[7];
22096 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
22097 struct hwrm_queue_mplstc2pri_qcfg_output {
22098 /* The specific error status for the command. */
22099 uint16_t error_code;
22100 /* The HWRM command request type. */
22102 /* The sequence ID from the original command. */
22104 /* The length of the response data in number of bytes. */
22107 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
22108 * before traffic has started.
22109 * A value of 0xff indicates that no pri is assigned to the
22112 uint8_t tc0_pri_queue_id;
22114 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
22115 * before traffic has started.
22116 * A value of 0xff indicates that no pri is assigned to the
22119 uint8_t tc1_pri_queue_id;
22121 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
22122 * before traffic has started.
22123 * A value of 0xff indicates that no pri is assigned to the
22126 uint8_t tc2_pri_queue_id;
22128 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
22129 * before traffic has started.
22130 * A value of 0xff indicates that no pri is assigned to the
22133 uint8_t tc3_pri_queue_id;
22135 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
22136 * before traffic has started.
22137 * A value of 0xff indicates that no pri is assigned to the
22140 uint8_t tc4_pri_queue_id;
22142 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
22143 * before traffic has started.
22144 * A value of 0xff indicates that no pri is assigned to the
22147 uint8_t tc5_pri_queue_id;
22149 * pri assigned to MPLS TC(EXP) 6. This value can only
22150 * be changed before traffic has started.
22151 * A value of 0xff indicates that no pri is assigned to the
22154 uint8_t tc6_pri_queue_id;
22156 * pri assigned to MPLS TC(EXP) 7. This value can only
22157 * be changed before traffic has started.
22158 * A value of 0xff indicates that no pri is assigned to the
22161 uint8_t tc7_pri_queue_id;
22162 uint8_t unused_0[7];
22164 * This field is used in Output records to indicate that the output
22165 * is completely written to RAM. This field should be read as '1'
22166 * to indicate that the output has been completely written.
22167 * When writing a command completion or response to an internal processor,
22168 * the order of writes has to be such that this field is written last.
22173 /*****************************
22174 * hwrm_queue_mplstc2pri_cfg *
22175 *****************************/
22178 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
22179 struct hwrm_queue_mplstc2pri_cfg_input {
22180 /* The HWRM command request type. */
22183 * The completion ring to send the completion event on. This should
22184 * be the NQ ID returned from the `nq_alloc` HWRM command.
22186 uint16_t cmpl_ring;
22188 * The sequence ID is used by the driver for tracking multiple
22189 * commands. This ID is treated as opaque data by the firmware and
22190 * the value is returned in the `hwrm_resp_hdr` upon completion.
22194 * The target ID of the command:
22195 * * 0x0-0xFFF8 - The function ID
22196 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22197 * * 0xFFFD - Reserved for user-space HWRM interface
22200 uint16_t target_id;
22202 * A physical address pointer pointing to a host buffer that the
22203 * command's response data will be written. This can be either a host
22204 * physical address (HPA) or a guest physical address (GPA) and must
22205 * point to a physically contiguous block of memory.
22207 uint64_t resp_addr;
22210 * This bit must be '1' for the mplstc0_pri_queue_id field to be
22213 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
22216 * This bit must be '1' for the mplstc1_pri_queue_id field to be
22219 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
22222 * This bit must be '1' for the mplstc2_pri_queue_id field to be
22225 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
22228 * This bit must be '1' for the mplstc3_pri_queue_id field to be
22231 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
22234 * This bit must be '1' for the mplstc4_pri_queue_id field to be
22237 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
22240 * This bit must be '1' for the mplstc5_pri_queue_id field to be
22243 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
22246 * This bit must be '1' for the mplstc6_pri_queue_id field to be
22249 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
22252 * This bit must be '1' for the mplstc7_pri_queue_id field to be
22255 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
22258 * Port ID of port for which the table is being configured.
22259 * The HWRM needs to check whether this function is allowed
22260 * to configure MPLS TC(EXP)to pri mapping on this port.
22263 uint8_t unused_0[3];
22265 * pri assigned to MPLS TC(EXP) 0. This value can only
22266 * be changed before traffic has started.
22268 uint8_t tc0_pri_queue_id;
22270 * pri assigned to MPLS TC(EXP) 1. This value can only
22271 * be changed before traffic has started.
22273 uint8_t tc1_pri_queue_id;
22275 * pri assigned to MPLS TC(EXP) 2 This value can only
22276 * be changed before traffic has started.
22278 uint8_t tc2_pri_queue_id;
22280 * pri assigned to MPLS TC(EXP) 3. This value can only
22281 * be changed before traffic has started.
22283 uint8_t tc3_pri_queue_id;
22285 * pri assigned to MPLS TC(EXP) 4. This value can only
22286 * be changed before traffic has started.
22288 uint8_t tc4_pri_queue_id;
22290 * pri assigned to MPLS TC(EXP) 5. This value can only
22291 * be changed before traffic has started.
22293 uint8_t tc5_pri_queue_id;
22295 * pri assigned to MPLS TC(EXP) 6. This value can only
22296 * be changed before traffic has started.
22298 uint8_t tc6_pri_queue_id;
22300 * pri assigned to MPLS TC(EXP) 7. This value can only
22301 * be changed before traffic has started.
22303 uint8_t tc7_pri_queue_id;
22306 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
22307 struct hwrm_queue_mplstc2pri_cfg_output {
22308 /* The specific error status for the command. */
22309 uint16_t error_code;
22310 /* The HWRM command request type. */
22312 /* The sequence ID from the original command. */
22314 /* The length of the response data in number of bytes. */
22316 uint8_t unused_0[7];
22318 * This field is used in Output records to indicate that the output
22319 * is completely written to RAM. This field should be read as '1'
22320 * to indicate that the output has been completely written.
22321 * When writing a command completion or response to an internal processor,
22322 * the order of writes has to be such that this field is written last.
22327 /*******************
22328 * hwrm_vnic_alloc *
22329 *******************/
22332 /* hwrm_vnic_alloc_input (size:192b/24B) */
22333 struct hwrm_vnic_alloc_input {
22334 /* The HWRM command request type. */
22337 * The completion ring to send the completion event on. This should
22338 * be the NQ ID returned from the `nq_alloc` HWRM command.
22340 uint16_t cmpl_ring;
22342 * The sequence ID is used by the driver for tracking multiple
22343 * commands. This ID is treated as opaque data by the firmware and
22344 * the value is returned in the `hwrm_resp_hdr` upon completion.
22348 * The target ID of the command:
22349 * * 0x0-0xFFF8 - The function ID
22350 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22351 * * 0xFFFD - Reserved for user-space HWRM interface
22354 uint16_t target_id;
22356 * A physical address pointer pointing to a host buffer that the
22357 * command's response data will be written. This can be either a host
22358 * physical address (HPA) or a guest physical address (GPA) and must
22359 * point to a physically contiguous block of memory.
22361 uint64_t resp_addr;
22364 * When this bit is '1', this VNIC is requested to
22365 * be the default VNIC for this function.
22367 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
22368 uint8_t unused_0[4];
22371 /* hwrm_vnic_alloc_output (size:128b/16B) */
22372 struct hwrm_vnic_alloc_output {
22373 /* The specific error status for the command. */
22374 uint16_t error_code;
22375 /* The HWRM command request type. */
22377 /* The sequence ID from the original command. */
22379 /* The length of the response data in number of bytes. */
22381 /* Logical vnic ID */
22383 uint8_t unused_0[3];
22385 * This field is used in Output records to indicate that the output
22386 * is completely written to RAM. This field should be read as '1'
22387 * to indicate that the output has been completely written.
22388 * When writing a command completion or response to an internal processor,
22389 * the order of writes has to be such that this field is written last.
22394 /******************
22396 ******************/
22399 /* hwrm_vnic_free_input (size:192b/24B) */
22400 struct hwrm_vnic_free_input {
22401 /* The HWRM command request type. */
22404 * The completion ring to send the completion event on. This should
22405 * be the NQ ID returned from the `nq_alloc` HWRM command.
22407 uint16_t cmpl_ring;
22409 * The sequence ID is used by the driver for tracking multiple
22410 * commands. This ID is treated as opaque data by the firmware and
22411 * the value is returned in the `hwrm_resp_hdr` upon completion.
22415 * The target ID of the command:
22416 * * 0x0-0xFFF8 - The function ID
22417 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22418 * * 0xFFFD - Reserved for user-space HWRM interface
22421 uint16_t target_id;
22423 * A physical address pointer pointing to a host buffer that the
22424 * command's response data will be written. This can be either a host
22425 * physical address (HPA) or a guest physical address (GPA) and must
22426 * point to a physically contiguous block of memory.
22428 uint64_t resp_addr;
22429 /* Logical vnic ID */
22431 uint8_t unused_0[4];
22434 /* hwrm_vnic_free_output (size:128b/16B) */
22435 struct hwrm_vnic_free_output {
22436 /* The specific error status for the command. */
22437 uint16_t error_code;
22438 /* The HWRM command request type. */
22440 /* The sequence ID from the original command. */
22442 /* The length of the response data in number of bytes. */
22444 uint8_t unused_0[7];
22446 * This field is used in Output records to indicate that the output
22447 * is completely written to RAM. This field should be read as '1'
22448 * to indicate that the output has been completely written.
22449 * When writing a command completion or response to an internal processor,
22450 * the order of writes has to be such that this field is written last.
22460 /* hwrm_vnic_cfg_input (size:384b/48B) */
22461 struct hwrm_vnic_cfg_input {
22462 /* The HWRM command request type. */
22465 * The completion ring to send the completion event on. This should
22466 * be the NQ ID returned from the `nq_alloc` HWRM command.
22468 uint16_t cmpl_ring;
22470 * The sequence ID is used by the driver for tracking multiple
22471 * commands. This ID is treated as opaque data by the firmware and
22472 * the value is returned in the `hwrm_resp_hdr` upon completion.
22476 * The target ID of the command:
22477 * * 0x0-0xFFF8 - The function ID
22478 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22479 * * 0xFFFD - Reserved for user-space HWRM interface
22482 uint16_t target_id;
22484 * A physical address pointer pointing to a host buffer that the
22485 * command's response data will be written. This can be either a host
22486 * physical address (HPA) or a guest physical address (GPA) and must
22487 * point to a physically contiguous block of memory.
22489 uint64_t resp_addr;
22492 * When this bit is '1', the VNIC is requested to
22493 * be the default VNIC for the function.
22495 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
22498 * When this bit is '1', the VNIC is being configured to
22499 * strip VLAN in the RX path.
22500 * If set to '0', then VLAN stripping is disabled on
22503 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
22506 * When this bit is '1', the VNIC is being configured to
22507 * buffer receive packets in the hardware until the host
22508 * posts new receive buffers.
22509 * If set to '0', then bd_stall is being configured to be
22510 * disabled on this VNIC.
22512 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
22515 * When this bit is '1', the VNIC is being configured to
22516 * receive both RoCE and non-RoCE traffic.
22517 * If set to '0', then this VNIC is not configured to be
22518 * operating in dual VNIC mode.
22520 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
22523 * When this flag is set to '1', the VNIC is requested to
22524 * be configured to receive only RoCE traffic.
22525 * If this flag is set to '0', then this flag shall be
22526 * ignored by the HWRM.
22527 * If roce_dual_vnic_mode flag is set to '1'
22528 * or roce_mirroring_capable_vnic_mode flag to 1,
22529 * then the HWRM client shall not set this flag to '1'.
22531 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
22534 * When a VNIC uses one destination ring group for certain
22535 * application (e.g. Receive Flow Steering) where
22536 * exact match is used to direct packets to a VNIC with one
22537 * destination ring group only, there is no need to configure
22538 * RSS indirection table for that VNIC as only one destination
22539 * ring group is used.
22541 * This flag is used to enable a mode where
22542 * RSS is enabled in the VNIC using a RSS context
22543 * for computing RSS hash but the RSS indirection table is
22544 * not configured using hwrm_vnic_rss_cfg.
22546 * If this mode is enabled, then the driver should not program
22547 * RSS indirection table for the RSS context that is used for
22548 * computing RSS hash only.
22550 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
22553 * When this bit is '1', the VNIC is being configured to
22554 * receive both RoCE and non-RoCE traffic, but forward only the
22555 * RoCE traffic further. Also, RoCE traffic can be mirrored to
22558 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
22562 * This bit must be '1' for the dflt_ring_grp field to be
22565 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
22568 * This bit must be '1' for the rss_rule field to be
22571 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
22574 * This bit must be '1' for the cos_rule field to be
22577 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
22580 * This bit must be '1' for the lb_rule field to be
22583 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
22586 * This bit must be '1' for the mru field to be
22589 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
22592 * This bit must be '1' for the default_rx_ring_id field to be
22595 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
22598 * This bit must be '1' for the default_cmpl_ring_id field to be
22601 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
22603 /* This bit must be '1' for the queue_id field to be configured. */
22604 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
22606 /* Logical vnic ID */
22609 * Default Completion ring for the VNIC. This ring will
22610 * be chosen if packet does not match any RSS rules and if
22611 * there is no COS rule.
22613 uint16_t dflt_ring_grp;
22615 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
22616 * there is no RSS rule.
22620 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
22621 * there is no COS rule.
22625 * RSS ID for load balancing rule/table structure.
22626 * 0xFF... (All Fs) if there is no LB rule.
22630 * The maximum receive unit of the vnic.
22631 * Each vnic is associated with a function.
22632 * The vnic mru value overwrites the mru setting of the
22633 * associated function.
22634 * The HWRM shall make sure that vnic mru does not exceed
22635 * the mru of the port the function is associated with.
22639 * Default Rx ring for the VNIC. This ring will
22640 * be chosen if packet does not match any RSS rules.
22641 * The aggregation ring associated with the Rx ring is
22642 * implied based on the Rx ring specified when the
22643 * aggregation ring was allocated.
22645 uint16_t default_rx_ring_id;
22647 * Default completion ring for the VNIC. This ring will
22648 * be chosen if packet does not match any RSS rules.
22650 uint16_t default_cmpl_ring_id;
22652 * When specified, only incoming packets classified to the specified CoS
22653 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
22654 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
22655 * ntuple filters with VNIC destination specified are invalid since they
22656 * conflict with the the CoS to VNIC steering rules in this mode.
22658 * If this field is not specified, packet to VNIC steering will be
22659 * subject to the standard L2 filter rules and any additional ntuple
22660 * filter rules with destination VNIC specified.
22663 uint8_t unused0[6];
22666 /* hwrm_vnic_cfg_output (size:128b/16B) */
22667 struct hwrm_vnic_cfg_output {
22668 /* The specific error status for the command. */
22669 uint16_t error_code;
22670 /* The HWRM command request type. */
22672 /* The sequence ID from the original command. */
22674 /* The length of the response data in number of bytes. */
22676 uint8_t unused_0[7];
22678 * This field is used in Output records to indicate that the output
22679 * is completely written to RAM. This field should be read as '1'
22680 * to indicate that the output has been completely written.
22681 * When writing a command completion or response to an internal processor,
22682 * the order of writes has to be such that this field is written last.
22687 /******************
22689 ******************/
22692 /* hwrm_vnic_qcfg_input (size:256b/32B) */
22693 struct hwrm_vnic_qcfg_input {
22694 /* The HWRM command request type. */
22697 * The completion ring to send the completion event on. This should
22698 * be the NQ ID returned from the `nq_alloc` HWRM command.
22700 uint16_t cmpl_ring;
22702 * The sequence ID is used by the driver for tracking multiple
22703 * commands. This ID is treated as opaque data by the firmware and
22704 * the value is returned in the `hwrm_resp_hdr` upon completion.
22708 * The target ID of the command:
22709 * * 0x0-0xFFF8 - The function ID
22710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22711 * * 0xFFFD - Reserved for user-space HWRM interface
22714 uint16_t target_id;
22716 * A physical address pointer pointing to a host buffer that the
22717 * command's response data will be written. This can be either a host
22718 * physical address (HPA) or a guest physical address (GPA) and must
22719 * point to a physically contiguous block of memory.
22721 uint64_t resp_addr;
22724 * This bit must be '1' for the vf_id_valid field to be
22727 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
22728 /* Logical vnic ID */
22730 /* ID of Virtual Function whose VNIC resource is being queried. */
22732 uint8_t unused_0[6];
22735 /* hwrm_vnic_qcfg_output (size:256b/32B) */
22736 struct hwrm_vnic_qcfg_output {
22737 /* The specific error status for the command. */
22738 uint16_t error_code;
22739 /* The HWRM command request type. */
22741 /* The sequence ID from the original command. */
22743 /* The length of the response data in number of bytes. */
22745 /* Default Completion ring for the VNIC. */
22746 uint16_t dflt_ring_grp;
22748 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
22749 * there is no RSS rule.
22753 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
22754 * there is no COS rule.
22758 * RSS ID for load balancing rule/table structure.
22759 * 0xFF... (All Fs) if there is no LB rule.
22762 /* The maximum receive unit of the vnic. */
22764 uint8_t unused_0[2];
22767 * When this bit is '1', the VNIC is the default VNIC for
22770 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
22773 * When this bit is '1', the VNIC is configured to
22774 * strip VLAN in the RX path.
22775 * If set to '0', then VLAN stripping is disabled on
22778 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
22781 * When this bit is '1', the VNIC is configured to
22782 * buffer receive packets in the hardware until the host
22783 * posts new receive buffers.
22784 * If set to '0', then bd_stall is disabled on
22787 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
22790 * When this bit is '1', the VNIC is configured to
22791 * receive both RoCE and non-RoCE traffic.
22792 * If set to '0', then this VNIC is not configured to
22793 * operate in dual VNIC mode.
22795 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
22798 * When this flag is set to '1', the VNIC is configured to
22799 * receive only RoCE traffic.
22800 * When this flag is set to '0', the VNIC is not configured
22801 * to receive only RoCE traffic.
22802 * If roce_dual_vnic_mode flag and this flag both are set
22803 * to '1', then it is an invalid configuration of the
22804 * VNIC. The HWRM should not allow that type of
22805 * mis-configuration by HWRM clients.
22807 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
22810 * When a VNIC uses one destination ring group for certain
22811 * application (e.g. Receive Flow Steering) where
22812 * exact match is used to direct packets to a VNIC with one
22813 * destination ring group only, there is no need to configure
22814 * RSS indirection table for that VNIC as only one destination
22815 * ring group is used.
22817 * When this bit is set to '1', then the VNIC is enabled in a
22818 * mode where RSS is enabled in the VNIC using a RSS context
22819 * for computing RSS hash but the RSS indirection table is
22822 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
22825 * When this bit is '1', the VNIC is configured to
22826 * receive both RoCE and non-RoCE traffic, but forward only
22827 * RoCE traffic further. Also RoCE traffic can be mirrored to
22830 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
22833 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
22834 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
22835 * queue association.
22838 uint8_t unused_1[5];
22840 * This field is used in Output records to indicate that the output
22841 * is completely written to RAM. This field should be read as '1'
22842 * to indicate that the output has been completely written.
22843 * When writing a command completion or response to an internal processor,
22844 * the order of writes has to be such that this field is written last.
22849 /*******************
22850 * hwrm_vnic_qcaps *
22851 *******************/
22854 /* hwrm_vnic_qcaps_input (size:192b/24B) */
22855 struct hwrm_vnic_qcaps_input {
22856 /* The HWRM command request type. */
22859 * The completion ring to send the completion event on. This should
22860 * be the NQ ID returned from the `nq_alloc` HWRM command.
22862 uint16_t cmpl_ring;
22864 * The sequence ID is used by the driver for tracking multiple
22865 * commands. This ID is treated as opaque data by the firmware and
22866 * the value is returned in the `hwrm_resp_hdr` upon completion.
22870 * The target ID of the command:
22871 * * 0x0-0xFFF8 - The function ID
22872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22873 * * 0xFFFD - Reserved for user-space HWRM interface
22876 uint16_t target_id;
22878 * A physical address pointer pointing to a host buffer that the
22879 * command's response data will be written. This can be either a host
22880 * physical address (HPA) or a guest physical address (GPA) and must
22881 * point to a physically contiguous block of memory.
22883 uint64_t resp_addr;
22885 uint8_t unused_0[4];
22888 /* hwrm_vnic_qcaps_output (size:192b/24B) */
22889 struct hwrm_vnic_qcaps_output {
22890 /* The specific error status for the command. */
22891 uint16_t error_code;
22892 /* The HWRM command request type. */
22894 /* The sequence ID from the original command. */
22896 /* The length of the response data in number of bytes. */
22898 /* The maximum receive unit that is settable on a vnic. */
22900 uint8_t unused_0[2];
22903 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
22906 * When this bit is '1', the capability of stripping VLAN in
22907 * the RX path is supported on VNIC(s).
22908 * If set to '0', then VLAN stripping capability is
22909 * not supported on VNIC(s).
22911 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
22914 * When this bit is '1', the capability to buffer receive
22915 * packets in the hardware until the host posts new receive buffers
22916 * is supported on VNIC(s).
22917 * If set to '0', then bd_stall capability is not supported
22920 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
22923 * When this bit is '1', the capability to
22924 * receive both RoCE and non-RoCE traffic on VNIC(s) is
22926 * If set to '0', then the capability to receive
22927 * both RoCE and non-RoCE traffic on VNIC(s) is
22930 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
22933 * When this bit is set to '1', the capability to configure
22934 * a VNIC to receive only RoCE traffic is supported.
22935 * When this flag is set to '0', the VNIC capability to
22936 * configure to receive only RoCE traffic is not supported.
22938 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
22941 * When this bit is set to '1', then the capability to enable
22942 * a VNIC in a mode where RSS context without configuring
22943 * RSS indirection table is supported (for RSS hash computation).
22944 * When this bit is set to '0', then a VNIC can not be configured
22945 * with a mode to enable RSS context without configuring RSS
22946 * indirection table.
22948 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
22951 * When this bit is '1', the capability to
22952 * mirror the the RoCE traffic is supported.
22953 * If set to '0', then the capability to mirror the
22954 * RoCE traffic is not supported.
22956 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
22959 * When this bit is '1', the outermost RSS hashing capability
22960 * is supported. If set to '0', then the outermost RSS hashing
22961 * capability is not supported.
22963 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
22966 * When this bit is '1', it indicates that firmware supports the
22967 * ability to steer incoming packets from one CoS queue to one
22968 * VNIC. This optional feature can then be enabled
22969 * using HWRM_VNIC_CFG on any VNIC. This feature is only
22970 * available when NVM option “enable_cos_classfication” is set
22971 * to 1. If set to '0', firmware does not support this feature.
22973 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
22976 * This field advertises the maximum concurrent TPA aggregations
22977 * supported by the VNIC on new devices that support TPA v2.
22978 * '0' means that TPA v2 is not supported.
22980 uint16_t max_aggs_supported;
22981 uint8_t unused_1[5];
22983 * This field is used in Output records to indicate that the output
22984 * is completely written to RAM. This field should be read as '1'
22985 * to indicate that the output has been completely written.
22986 * When writing a command completion or response to an internal processor,
22987 * the order of writes has to be such that this field is written last.
22992 /*********************
22993 * hwrm_vnic_tpa_cfg *
22994 *********************/
22997 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
22998 struct hwrm_vnic_tpa_cfg_input {
22999 /* The HWRM command request type. */
23002 * The completion ring to send the completion event on. This should
23003 * be the NQ ID returned from the `nq_alloc` HWRM command.
23005 uint16_t cmpl_ring;
23007 * The sequence ID is used by the driver for tracking multiple
23008 * commands. This ID is treated as opaque data by the firmware and
23009 * the value is returned in the `hwrm_resp_hdr` upon completion.
23013 * The target ID of the command:
23014 * * 0x0-0xFFF8 - The function ID
23015 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23016 * * 0xFFFD - Reserved for user-space HWRM interface
23019 uint16_t target_id;
23021 * A physical address pointer pointing to a host buffer that the
23022 * command's response data will be written. This can be either a host
23023 * physical address (HPA) or a guest physical address (GPA) and must
23024 * point to a physically contiguous block of memory.
23026 uint64_t resp_addr;
23029 * When this bit is '1', the VNIC shall be configured to
23030 * perform transparent packet aggregation (TPA) of
23031 * non-tunneled TCP packets.
23033 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
23036 * When this bit is '1', the VNIC shall be configured to
23037 * perform transparent packet aggregation (TPA) of
23038 * tunneled TCP packets.
23040 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
23043 * When this bit is '1', the VNIC shall be configured to
23044 * perform transparent packet aggregation (TPA) according
23045 * to Windows Receive Segment Coalescing (RSC) rules.
23047 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
23050 * When this bit is '1', the VNIC shall be configured to
23051 * perform transparent packet aggregation (TPA) according
23052 * to Linux Generic Receive Offload (GRO) rules.
23054 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
23057 * When this bit is '1', the VNIC shall be configured to
23058 * perform transparent packet aggregation (TPA) for TCP
23059 * packets with IP ECN set to non-zero.
23061 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
23064 * When this bit is '1', the VNIC shall be configured to
23065 * perform transparent packet aggregation (TPA) for
23066 * GRE tunneled TCP packets only if all packets have the
23067 * same GRE sequence.
23069 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
23072 * When this bit is '1' and the GRO mode is enabled,
23073 * the VNIC shall be configured to
23074 * perform transparent packet aggregation (TPA) for
23075 * TCP/IPv4 packets with consecutively increasing IPIDs.
23076 * In other words, the last packet that is being
23077 * aggregated to an already existing aggregation context
23078 * shall have IPID 1 more than the IPID of the last packet
23079 * that was aggregated in that aggregation context.
23081 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
23084 * When this bit is '1' and the GRO mode is enabled,
23085 * the VNIC shall be configured to
23086 * perform transparent packet aggregation (TPA) for
23087 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
23090 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
23093 * When this bit is '1' and the GRO mode is enabled,
23094 * the VNIC shall DMA payload data using GRO rules.
23095 * When this bit is '0', the VNIC shall DMA payload data
23096 * using the more efficient LRO rules of filling all
23097 * aggregation buffers.
23099 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
23103 * This bit must be '1' for the max_agg_segs field to be
23106 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
23108 * This bit must be '1' for the max_aggs field to be
23111 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
23113 * This bit must be '1' for the max_agg_timer field to be
23116 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
23117 /* deprecated bit. Do not use!!! */
23118 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
23119 /* Logical vnic ID */
23122 * This is the maximum number of TCP segments that can
23123 * be aggregated (unit is Log2). Max value is 31. On new
23124 * devices supporting TPA v2, the unit is multiples of 4 and
23125 * valid values are > 0 and <= 63.
23127 uint16_t max_agg_segs;
23129 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
23131 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
23133 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
23135 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
23136 /* Any segment size larger than this is not valid */
23137 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
23138 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
23139 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
23141 * This is the maximum number of aggregations this VNIC is
23142 * allowed (unit is Log2). Max value is 7. On new devices
23143 * supporting TPA v2, this is in unit of 1 and must be > 0
23144 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
23145 * to enable TPA v2.
23148 /* 1 aggregation */
23149 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
23150 /* 2 aggregations */
23151 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
23152 /* 4 aggregations */
23153 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
23154 /* 8 aggregations */
23155 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
23156 /* 16 aggregations */
23157 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
23158 /* Any aggregation size larger than this is not valid */
23159 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
23160 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
23161 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
23162 uint8_t unused_0[2];
23164 * This is the maximum amount of time allowed for
23165 * an aggregation context to complete after it was initiated.
23167 uint32_t max_agg_timer;
23169 * This is the minimum amount of payload length required to
23170 * start an aggregation context. This field is deprecated and
23171 * should be set to 0. The minimum length is set by firmware
23172 * and can be queried using hwrm_vnic_tpa_qcfg.
23174 uint32_t min_agg_len;
23177 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
23178 struct hwrm_vnic_tpa_cfg_output {
23179 /* The specific error status for the command. */
23180 uint16_t error_code;
23181 /* The HWRM command request type. */
23183 /* The sequence ID from the original command. */
23185 /* The length of the response data in number of bytes. */
23187 uint8_t unused_0[7];
23189 * This field is used in Output records to indicate that the output
23190 * is completely written to RAM. This field should be read as '1'
23191 * to indicate that the output has been completely written.
23192 * When writing a command completion or response to an internal processor,
23193 * the order of writes has to be such that this field is written last.
23198 /*********************
23199 * hwrm_vnic_rss_cfg *
23200 *********************/
23203 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
23204 struct hwrm_vnic_rss_cfg_input {
23205 /* The HWRM command request type. */
23208 * The completion ring to send the completion event on. This should
23209 * be the NQ ID returned from the `nq_alloc` HWRM command.
23211 uint16_t cmpl_ring;
23213 * The sequence ID is used by the driver for tracking multiple
23214 * commands. This ID is treated as opaque data by the firmware and
23215 * the value is returned in the `hwrm_resp_hdr` upon completion.
23219 * The target ID of the command:
23220 * * 0x0-0xFFF8 - The function ID
23221 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23222 * * 0xFFFD - Reserved for user-space HWRM interface
23225 uint16_t target_id;
23227 * A physical address pointer pointing to a host buffer that the
23228 * command's response data will be written. This can be either a host
23229 * physical address (HPA) or a guest physical address (GPA) and must
23230 * point to a physically contiguous block of memory.
23232 uint64_t resp_addr;
23233 uint32_t hash_type;
23235 * When this bit is '1', the RSS hash shall be computed
23236 * over source and destination IPv4 addresses of IPv4
23239 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
23241 * When this bit is '1', the RSS hash shall be computed
23242 * over source/destination IPv4 addresses and
23243 * source/destination ports of TCP/IPv4 packets.
23245 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
23247 * When this bit is '1', the RSS hash shall be computed
23248 * over source/destination IPv4 addresses and
23249 * source/destination ports of UDP/IPv4 packets.
23251 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
23253 * When this bit is '1', the RSS hash shall be computed
23254 * over source and destination IPv4 addresses of IPv6
23257 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
23259 * When this bit is '1', the RSS hash shall be computed
23260 * over source/destination IPv6 addresses and
23261 * source/destination ports of TCP/IPv6 packets.
23263 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
23265 * When this bit is '1', the RSS hash shall be computed
23266 * over source/destination IPv6 addresses and
23267 * source/destination ports of UDP/IPv6 packets.
23269 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
23270 /* VNIC ID of VNIC associated with RSS table being configured. */
23273 * Specifies which VNIC ring table pair to configure.
23274 * Valid values range from 0 to 7.
23276 uint8_t ring_table_pair_index;
23277 /* Flags to specify different RSS hash modes. */
23278 uint8_t hash_mode_flags;
23280 * When this bit is '1', it indicates using current RSS
23281 * hash mode setting configured in the device.
23283 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
23286 * When this bit is '1', it indicates requesting support of
23287 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
23288 * l4.src, l4.dest} for tunnel packets. For none-tunnel
23289 * packets, the RSS hash is computed over the normal
23290 * src/dest l3 and src/dest l4 headers.
23292 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
23295 * When this bit is '1', it indicates requesting support of
23296 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
23297 * tunnel packets. For none-tunnel packets, the RSS hash is
23298 * computed over the normal src/dest l3 headers.
23300 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
23303 * When this bit is '1', it indicates requesting support of
23304 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
23305 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
23306 * packets, the RSS hash is computed over the normal
23307 * src/dest l3 and src/dest l4 headers.
23309 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
23312 * When this bit is '1', it indicates requesting support of
23313 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
23314 * tunnel packets. For none-tunnel packets, the RSS hash is
23315 * computed over the normal src/dest l3 headers.
23317 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
23319 /* This is the address for rss ring group table */
23320 uint64_t ring_grp_tbl_addr;
23321 /* This is the address for rss hash key table */
23322 uint64_t hash_key_tbl_addr;
23323 /* Index to the rss indirection table. */
23324 uint16_t rss_ctx_idx;
23325 uint8_t unused_1[6];
23328 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
23329 struct hwrm_vnic_rss_cfg_output {
23330 /* The specific error status for the command. */
23331 uint16_t error_code;
23332 /* The HWRM command request type. */
23334 /* The sequence ID from the original command. */
23336 /* The length of the response data in number of bytes. */
23338 uint8_t unused_0[7];
23340 * This field is used in Output records to indicate that the output
23341 * is completely written to RAM. This field should be read as '1'
23342 * to indicate that the output has been completely written.
23343 * When writing a command completion or response to an internal processor,
23344 * the order of writes has to be such that this field is written last.
23349 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
23350 struct hwrm_vnic_rss_cfg_cmd_err {
23352 * command specific error codes that goes to
23353 * the cmd_err field in Common HWRM Error Response.
23356 /* Unknown error */
23357 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
23360 * Unable to change global RSS mode to outer due to all active
23361 * interfaces are not ready to support outer RSS hashing.
23363 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
23365 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
23366 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
23367 uint8_t unused_0[7];
23370 /**********************
23371 * hwrm_vnic_rss_qcfg *
23372 **********************/
23375 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
23376 struct hwrm_vnic_rss_qcfg_input {
23377 /* The HWRM command request type. */
23380 * The completion ring to send the completion event on. This should
23381 * be the NQ ID returned from the `nq_alloc` HWRM command.
23383 uint16_t cmpl_ring;
23385 * The sequence ID is used by the driver for tracking multiple
23386 * commands. This ID is treated as opaque data by the firmware and
23387 * the value is returned in the `hwrm_resp_hdr` upon completion.
23391 * The target ID of the command:
23392 * * 0x0-0xFFF8 - The function ID
23393 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23394 * * 0xFFFD - Reserved for user-space HWRM interface
23397 uint16_t target_id;
23399 * A physical address pointer pointing to a host buffer that the
23400 * command's response data will be written. This can be either a host
23401 * physical address (HPA) or a guest physical address (GPA) and must
23402 * point to a physically contiguous block of memory.
23404 uint64_t resp_addr;
23405 /* Index to the rss indirection table. */
23406 uint16_t rss_ctx_idx;
23407 uint8_t unused_0[6];
23410 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
23411 struct hwrm_vnic_rss_qcfg_output {
23412 /* The specific error status for the command. */
23413 uint16_t error_code;
23414 /* The HWRM command request type. */
23416 /* The sequence ID from the original command. */
23418 /* The length of the response data in number of bytes. */
23420 uint32_t hash_type;
23422 * When this bit is '1', the RSS hash shall be computed
23423 * over source and destination IPv4 addresses of IPv4
23426 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
23428 * When this bit is '1', the RSS hash shall be computed
23429 * over source/destination IPv4 addresses and
23430 * source/destination ports of TCP/IPv4 packets.
23432 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
23434 * When this bit is '1', the RSS hash shall be computed
23435 * over source/destination IPv4 addresses and
23436 * source/destination ports of UDP/IPv4 packets.
23438 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
23440 * When this bit is '1', the RSS hash shall be computed
23441 * over source and destination IPv4 addresses of IPv6
23444 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
23446 * When this bit is '1', the RSS hash shall be computed
23447 * over source/destination IPv6 addresses and
23448 * source/destination ports of TCP/IPv6 packets.
23450 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
23452 * When this bit is '1', the RSS hash shall be computed
23453 * over source/destination IPv6 addresses and
23454 * source/destination ports of UDP/IPv6 packets.
23456 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
23457 uint8_t unused_0[4];
23458 /* This is the value of rss hash key */
23459 uint32_t hash_key[10];
23460 /* Flags to specify different RSS hash modes. */
23461 uint8_t hash_mode_flags;
23463 * When this bit is '1', it indicates using current RSS
23464 * hash mode setting configured in the device.
23466 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
23469 * When this bit is '1', it indicates requesting support of
23470 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
23471 * l4.src, l4.dest} for tunnel packets. For none-tunnel
23472 * packets, the RSS hash is computed over the normal
23473 * src/dest l3 and src/dest l4 headers.
23475 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
23478 * When this bit is '1', it indicates requesting support of
23479 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
23480 * tunnel packets. For none-tunnel packets, the RSS hash is
23481 * computed over the normal src/dest l3 headers.
23483 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
23486 * When this bit is '1', it indicates requesting support of
23487 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
23488 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
23489 * packets, the RSS hash is computed over the normal
23490 * src/dest l3 and src/dest l4 headers.
23492 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
23495 * When this bit is '1', it indicates requesting support of
23496 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
23497 * tunnel packets. For none-tunnel packets, the RSS hash is
23498 * computed over the normal src/dest l3 headers.
23500 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
23502 uint8_t unused_1[6];
23504 * This field is used in Output records to indicate that the output
23505 * is completely written to RAM. This field should be read as '1'
23506 * to indicate that the output has been completely written.
23507 * When writing a command completion or response to an internal processor,
23508 * the order of writes has to be such that this field is written last.
23513 /**************************
23514 * hwrm_vnic_plcmodes_cfg *
23515 **************************/
23518 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
23519 struct hwrm_vnic_plcmodes_cfg_input {
23520 /* The HWRM command request type. */
23523 * The completion ring to send the completion event on. This should
23524 * be the NQ ID returned from the `nq_alloc` HWRM command.
23526 uint16_t cmpl_ring;
23528 * The sequence ID is used by the driver for tracking multiple
23529 * commands. This ID is treated as opaque data by the firmware and
23530 * the value is returned in the `hwrm_resp_hdr` upon completion.
23534 * The target ID of the command:
23535 * * 0x0-0xFFF8 - The function ID
23536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23537 * * 0xFFFD - Reserved for user-space HWRM interface
23540 uint16_t target_id;
23542 * A physical address pointer pointing to a host buffer that the
23543 * command's response data will be written. This can be either a host
23544 * physical address (HPA) or a guest physical address (GPA) and must
23545 * point to a physically contiguous block of memory.
23547 uint64_t resp_addr;
23550 * When this bit is '1', the VNIC shall be configured to
23551 * use regular placement algorithm.
23552 * By default, the regular placement algorithm shall be
23553 * enabled on the VNIC.
23555 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
23558 * When this bit is '1', the VNIC shall be configured
23559 * use the jumbo placement algorithm.
23561 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
23564 * When this bit is '1', the VNIC shall be configured
23565 * to enable Header-Data split for IPv4 packets according
23566 * to the following rules:
23567 * # If the packet is identified as TCP/IPv4, then the
23568 * packet is split at the beginning of the TCP payload.
23569 * # If the packet is identified as UDP/IPv4, then the
23570 * packet is split at the beginning of UDP payload.
23571 * # If the packet is identified as non-TCP and non-UDP
23572 * IPv4 packet, then the packet is split at the beginning
23573 * of the upper layer protocol header carried in the IPv4
23576 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
23579 * When this bit is '1', the VNIC shall be configured
23580 * to enable Header-Data split for IPv6 packets according
23581 * to the following rules:
23582 * # If the packet is identified as TCP/IPv6, then the
23583 * packet is split at the beginning of the TCP payload.
23584 * # If the packet is identified as UDP/IPv6, then the
23585 * packet is split at the beginning of UDP payload.
23586 * # If the packet is identified as non-TCP and non-UDP
23587 * IPv6 packet, then the packet is split at the beginning
23588 * of the upper layer protocol header carried in the IPv6
23591 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
23594 * When this bit is '1', the VNIC shall be configured
23595 * to enable Header-Data split for FCoE packets at the
23596 * beginning of FC payload.
23598 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
23601 * When this bit is '1', the VNIC shall be configured
23602 * to enable Header-Data split for RoCE packets at the
23603 * beginning of RoCE payload (after BTH/GRH headers).
23605 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
23609 * This bit must be '1' for the jumbo_thresh_valid field to be
23612 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
23615 * This bit must be '1' for the hds_offset_valid field to be
23618 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
23621 * This bit must be '1' for the hds_threshold_valid field to be
23624 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
23626 /* Logical vnic ID */
23629 * When jumbo placement algorithm is enabled, this value
23630 * is used to determine the threshold for jumbo placement.
23631 * Packets with length larger than this value will be
23632 * placed according to the jumbo placement algorithm.
23634 uint16_t jumbo_thresh;
23636 * This value is used to determine the offset into
23637 * packet buffer where the split data (payload) will be
23638 * placed according to one of HDS placement algorithm.
23640 * The lengths of packet buffers provided for split data
23641 * shall be larger than this value.
23643 uint16_t hds_offset;
23645 * When one of the HDS placement algorithm is enabled, this
23646 * value is used to determine the threshold for HDS
23648 * Packets with length larger than this value will be
23649 * placed according to the HDS placement algorithm.
23650 * This value shall be in multiple of 4 bytes.
23652 uint16_t hds_threshold;
23653 uint8_t unused_0[6];
23656 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
23657 struct hwrm_vnic_plcmodes_cfg_output {
23658 /* The specific error status for the command. */
23659 uint16_t error_code;
23660 /* The HWRM command request type. */
23662 /* The sequence ID from the original command. */
23664 /* The length of the response data in number of bytes. */
23666 uint8_t unused_0[7];
23668 * This field is used in Output records to indicate that the output
23669 * is completely written to RAM. This field should be read as '1'
23670 * to indicate that the output has been completely written.
23671 * When writing a command completion or response to an internal processor,
23672 * the order of writes has to be such that this field is written last.
23677 /***************************
23678 * hwrm_vnic_plcmodes_qcfg *
23679 ***************************/
23682 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
23683 struct hwrm_vnic_plcmodes_qcfg_input {
23684 /* The HWRM command request type. */
23687 * The completion ring to send the completion event on. This should
23688 * be the NQ ID returned from the `nq_alloc` HWRM command.
23690 uint16_t cmpl_ring;
23692 * The sequence ID is used by the driver for tracking multiple
23693 * commands. This ID is treated as opaque data by the firmware and
23694 * the value is returned in the `hwrm_resp_hdr` upon completion.
23698 * The target ID of the command:
23699 * * 0x0-0xFFF8 - The function ID
23700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23701 * * 0xFFFD - Reserved for user-space HWRM interface
23704 uint16_t target_id;
23706 * A physical address pointer pointing to a host buffer that the
23707 * command's response data will be written. This can be either a host
23708 * physical address (HPA) or a guest physical address (GPA) and must
23709 * point to a physically contiguous block of memory.
23711 uint64_t resp_addr;
23712 /* Logical vnic ID */
23714 uint8_t unused_0[4];
23717 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
23718 struct hwrm_vnic_plcmodes_qcfg_output {
23719 /* The specific error status for the command. */
23720 uint16_t error_code;
23721 /* The HWRM command request type. */
23723 /* The sequence ID from the original command. */
23725 /* The length of the response data in number of bytes. */
23729 * When this bit is '1', the VNIC is configured to
23730 * use regular placement algorithm.
23732 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
23735 * When this bit is '1', the VNIC is configured to
23736 * use the jumbo placement algorithm.
23738 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
23741 * When this bit is '1', the VNIC is configured
23742 * to enable Header-Data split for IPv4 packets.
23744 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
23747 * When this bit is '1', the VNIC is configured
23748 * to enable Header-Data split for IPv6 packets.
23750 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
23753 * When this bit is '1', the VNIC is configured
23754 * to enable Header-Data split for FCoE packets.
23756 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
23759 * When this bit is '1', the VNIC is configured
23760 * to enable Header-Data split for RoCE packets.
23762 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
23765 * When this bit is '1', the VNIC is configured
23766 * to be the default VNIC of the requesting function.
23768 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
23771 * When jumbo placement algorithm is enabled, this value
23772 * is used to determine the threshold for jumbo placement.
23773 * Packets with length larger than this value will be
23774 * placed according to the jumbo placement algorithm.
23776 uint16_t jumbo_thresh;
23778 * This value is used to determine the offset into
23779 * packet buffer where the split data (payload) will be
23780 * placed according to one of HDS placement algorithm.
23782 * The lengths of packet buffers provided for split data
23783 * shall be larger than this value.
23785 uint16_t hds_offset;
23787 * When one of the HDS placement algorithm is enabled, this
23788 * value is used to determine the threshold for HDS
23790 * Packets with length larger than this value will be
23791 * placed according to the HDS placement algorithm.
23792 * This value shall be in multiple of 4 bytes.
23794 uint16_t hds_threshold;
23795 uint8_t unused_0[5];
23797 * This field is used in Output records to indicate that the output
23798 * is completely written to RAM. This field should be read as '1'
23799 * to indicate that the output has been completely written.
23800 * When writing a command completion or response to an internal processor,
23801 * the order of writes has to be such that this field is written last.
23806 /**********************************
23807 * hwrm_vnic_rss_cos_lb_ctx_alloc *
23808 **********************************/
23811 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
23812 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
23813 /* The HWRM command request type. */
23816 * The completion ring to send the completion event on. This should
23817 * be the NQ ID returned from the `nq_alloc` HWRM command.
23819 uint16_t cmpl_ring;
23821 * The sequence ID is used by the driver for tracking multiple
23822 * commands. This ID is treated as opaque data by the firmware and
23823 * the value is returned in the `hwrm_resp_hdr` upon completion.
23827 * The target ID of the command:
23828 * * 0x0-0xFFF8 - The function ID
23829 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23830 * * 0xFFFD - Reserved for user-space HWRM interface
23833 uint16_t target_id;
23835 * A physical address pointer pointing to a host buffer that the
23836 * command's response data will be written. This can be either a host
23837 * physical address (HPA) or a guest physical address (GPA) and must
23838 * point to a physically contiguous block of memory.
23840 uint64_t resp_addr;
23843 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
23844 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
23845 /* The specific error status for the command. */
23846 uint16_t error_code;
23847 /* The HWRM command request type. */
23849 /* The sequence ID from the original command. */
23851 /* The length of the response data in number of bytes. */
23853 /* rss_cos_lb_ctx_id is 16 b */
23854 uint16_t rss_cos_lb_ctx_id;
23855 uint8_t unused_0[5];
23857 * This field is used in Output records to indicate that the output
23858 * is completely written to RAM. This field should be read as '1'
23859 * to indicate that the output has been completely written.
23860 * When writing a command completion or response to an internal processor,
23861 * the order of writes has to be such that this field is written last.
23866 /*********************************
23867 * hwrm_vnic_rss_cos_lb_ctx_free *
23868 *********************************/
23871 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
23872 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
23873 /* The HWRM command request type. */
23876 * The completion ring to send the completion event on. This should
23877 * be the NQ ID returned from the `nq_alloc` HWRM command.
23879 uint16_t cmpl_ring;
23881 * The sequence ID is used by the driver for tracking multiple
23882 * commands. This ID is treated as opaque data by the firmware and
23883 * the value is returned in the `hwrm_resp_hdr` upon completion.
23887 * The target ID of the command:
23888 * * 0x0-0xFFF8 - The function ID
23889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23890 * * 0xFFFD - Reserved for user-space HWRM interface
23893 uint16_t target_id;
23895 * A physical address pointer pointing to a host buffer that the
23896 * command's response data will be written. This can be either a host
23897 * physical address (HPA) or a guest physical address (GPA) and must
23898 * point to a physically contiguous block of memory.
23900 uint64_t resp_addr;
23901 /* rss_cos_lb_ctx_id is 16 b */
23902 uint16_t rss_cos_lb_ctx_id;
23903 uint8_t unused_0[6];
23906 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
23907 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
23908 /* The specific error status for the command. */
23909 uint16_t error_code;
23910 /* The HWRM command request type. */
23912 /* The sequence ID from the original command. */
23914 /* The length of the response data in number of bytes. */
23916 uint8_t unused_0[7];
23918 * This field is used in Output records to indicate that the output
23919 * is completely written to RAM. This field should be read as '1'
23920 * to indicate that the output has been completely written.
23921 * When writing a command completion or response to an internal processor,
23922 * the order of writes has to be such that this field is written last.
23927 /*******************
23928 * hwrm_ring_alloc *
23929 *******************/
23932 /* hwrm_ring_alloc_input (size:704b/88B) */
23933 struct hwrm_ring_alloc_input {
23934 /* The HWRM command request type. */
23937 * The completion ring to send the completion event on. This should
23938 * be the NQ ID returned from the `nq_alloc` HWRM command.
23940 uint16_t cmpl_ring;
23942 * The sequence ID is used by the driver for tracking multiple
23943 * commands. This ID is treated as opaque data by the firmware and
23944 * the value is returned in the `hwrm_resp_hdr` upon completion.
23948 * The target ID of the command:
23949 * * 0x0-0xFFF8 - The function ID
23950 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23951 * * 0xFFFD - Reserved for user-space HWRM interface
23954 uint16_t target_id;
23956 * A physical address pointer pointing to a host buffer that the
23957 * command's response data will be written. This can be either a host
23958 * physical address (HPA) or a guest physical address (GPA) and must
23959 * point to a physically contiguous block of memory.
23961 uint64_t resp_addr;
23964 * This bit must be '1' for the ring_arb_cfg field to be
23967 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
23970 * This bit must be '1' for the stat_ctx_id_valid field to be
23973 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
23976 * This bit must be '1' for the max_bw_valid field to be
23979 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
23982 * This bit must be '1' for the rx_ring_id field to be
23985 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
23988 * This bit must be '1' for the nq_ring_id field to be
23991 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
23994 * This bit must be '1' for the rx_buf_size field to be
23997 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
24001 /* L2 Completion Ring (CR) */
24002 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
24004 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
24006 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
24007 /* RoCE Notification Completion Ring (ROCE_CR) */
24008 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
24009 /* RX Aggregation Ring */
24010 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
24011 /* Notification Queue */
24012 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
24013 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
24014 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
24016 /* Ring allocation flags. */
24019 * For Rx rings, the incoming packet data can be placed at either
24020 * a 0B or 2B offset from the start of the Rx packet buffer. When
24021 * '1', the received packet will be padded with 2B of zeros at the
24022 * front of the packet. Note that this flag is only used for
24023 * Rx rings and is ignored for all other rings included Rx
24024 * Aggregation rings.
24026 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
24028 * This value is a pointer to the page table for the
24031 uint64_t page_tbl_addr;
24032 /* First Byte Offset of the first entry in the first page. */
24035 * Actual page size in 2^page_size. The supported range is increments
24036 * in powers of 2 from 16 bytes to 1GB.
24038 * Page size is 16 B.
24040 * Page size is 4 KB.
24042 * Page size is 8 KB.
24044 * Page size is 64 KB.
24046 * Page size is 2 MB.
24048 * Page size is 4 MB.
24050 * Page size is 1 GB.
24054 * This value indicates the depth of page table.
24055 * For this version of the specification, value other than 0 or
24056 * 1 shall be considered as an invalid value.
24057 * When the page_tbl_depth = 0, then it is treated as a
24058 * special case with the following.
24059 * 1. FBO and page size fields are not valid.
24060 * 2. page_tbl_addr is the physical address of the first
24061 * element of the ring.
24063 uint8_t page_tbl_depth;
24064 uint8_t unused_1[2];
24066 * Number of 16B units in the ring. Minimum size for
24067 * a ring is 16 16B entries.
24071 * Logical ring number for the ring to be allocated.
24072 * This value determines the position in the doorbell
24073 * area where the update to the ring will be made.
24075 * For completion rings, this value is also the MSI-X
24076 * vector number for the function the completion ring is
24079 uint16_t logical_id;
24081 * This field is used only when ring_type is a TX ring.
24082 * This value indicates what completion ring the TX ring
24083 * is associated with.
24085 uint16_t cmpl_ring_id;
24087 * This field is used only when ring_type is a TX ring.
24088 * This value indicates what CoS queue the TX ring
24089 * is associated with.
24093 * When allocating a Rx ring or Rx aggregation ring, this field
24094 * specifies the size of the buffer descriptors posted to the ring.
24096 uint16_t rx_buf_size;
24098 * When allocating an Rx aggregation ring, this field
24099 * specifies the associated Rx ring ID.
24101 uint16_t rx_ring_id;
24103 * When allocating a completion ring, this field
24104 * specifies the associated NQ ring ID.
24106 uint16_t nq_ring_id;
24108 * This field is used only when ring_type is a TX ring.
24109 * This field is used to configure arbitration related
24110 * parameters for a TX ring.
24112 uint16_t ring_arb_cfg;
24113 /* Arbitration policy used for the ring. */
24114 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
24116 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
24118 * Use strict priority for the TX ring.
24119 * Priority value is specified in arb_policy_param
24121 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
24124 * Use weighted fair queue arbitration for the TX ring.
24125 * Weight is specified in arb_policy_param
24127 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
24129 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
24130 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
24131 /* Reserved field. */
24132 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
24134 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
24136 * Arbitration policy specific parameter.
24137 * # For strict priority arbitration policy, this field
24138 * represents a priority value. If set to 0, then the priority
24139 * is not specified and the HWRM is allowed to select
24140 * any priority for this TX ring.
24141 * # For weighted fair queue arbitration policy, this field
24142 * represents a weight value. If set to 0, then the weight
24143 * is not specified and the HWRM is allowed to select
24144 * any weight for this TX ring.
24146 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
24148 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
24151 * This field is reserved for the future use.
24152 * It shall be set to 0.
24154 uint32_t reserved3;
24156 * This field is used only when ring_type is a TX ring.
24157 * This input indicates what statistics context this ring
24158 * should be associated with.
24160 uint32_t stat_ctx_id;
24162 * This field is reserved for the future use.
24163 * It shall be set to 0.
24165 uint32_t reserved4;
24167 * This field is used only when ring_type is a TX ring
24168 * to specify maximum BW allocated to the TX ring.
24169 * The HWRM will translate this value into byte counter and
24170 * time interval used for this ring inside the device.
24173 /* The bandwidth value. */
24174 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
24175 UINT32_C(0xfffffff)
24176 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
24177 /* The granularity of the value (bits or bytes). */
24178 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
24179 UINT32_C(0x10000000)
24180 /* Value is in bits. */
24181 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
24182 (UINT32_C(0x0) << 28)
24183 /* Value is in bytes. */
24184 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
24185 (UINT32_C(0x1) << 28)
24186 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
24187 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
24188 /* bw_value_unit is 3 b */
24189 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
24190 UINT32_C(0xe0000000)
24191 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
24192 /* Value is in Mb or MB (base 10). */
24193 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
24194 (UINT32_C(0x0) << 29)
24195 /* Value is in Kb or KB (base 10). */
24196 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
24197 (UINT32_C(0x2) << 29)
24198 /* Value is in bits or bytes. */
24199 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
24200 (UINT32_C(0x4) << 29)
24201 /* Value is in Gb or GB (base 10). */
24202 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
24203 (UINT32_C(0x6) << 29)
24204 /* Value is in 1/100th of a percentage of total bandwidth. */
24205 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24206 (UINT32_C(0x1) << 29)
24208 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
24209 (UINT32_C(0x7) << 29)
24210 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
24211 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
24213 * This field is used only when ring_type is a Completion ring.
24214 * This value indicates what interrupt mode should be used
24215 * on this completion ring.
24216 * Note: In the legacy interrupt mode, no more than 16
24217 * completion rings are allowed.
24221 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
24223 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
24225 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
24226 /* No Interrupt - Polled mode */
24227 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
24228 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
24229 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
24230 uint8_t unused_4[3];
24232 * The cq_handle is specified when allocating a completion ring. For
24233 * devices that support NQs, this cq_handle will be included in the
24234 * NQE to specify which CQ should be read to retrieve the completion
24237 uint64_t cq_handle;
24240 /* hwrm_ring_alloc_output (size:128b/16B) */
24241 struct hwrm_ring_alloc_output {
24242 /* The specific error status for the command. */
24243 uint16_t error_code;
24244 /* The HWRM command request type. */
24246 /* The sequence ID from the original command. */
24248 /* The length of the response data in number of bytes. */
24251 * Physical number of ring allocated.
24252 * This value shall be unique for a ring type.
24255 /* Logical number of ring allocated. */
24256 uint16_t logical_ring_id;
24257 uint8_t unused_0[3];
24259 * This field is used in Output records to indicate that the output
24260 * is completely written to RAM. This field should be read as '1'
24261 * to indicate that the output has been completely written.
24262 * When writing a command completion or response to an internal processor,
24263 * the order of writes has to be such that this field is written last.
24268 /******************
24270 ******************/
24273 /* hwrm_ring_free_input (size:192b/24B) */
24274 struct hwrm_ring_free_input {
24275 /* The HWRM command request type. */
24278 * The completion ring to send the completion event on. This should
24279 * be the NQ ID returned from the `nq_alloc` HWRM command.
24281 uint16_t cmpl_ring;
24283 * The sequence ID is used by the driver for tracking multiple
24284 * commands. This ID is treated as opaque data by the firmware and
24285 * the value is returned in the `hwrm_resp_hdr` upon completion.
24289 * The target ID of the command:
24290 * * 0x0-0xFFF8 - The function ID
24291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24292 * * 0xFFFD - Reserved for user-space HWRM interface
24295 uint16_t target_id;
24297 * A physical address pointer pointing to a host buffer that the
24298 * command's response data will be written. This can be either a host
24299 * physical address (HPA) or a guest physical address (GPA) and must
24300 * point to a physically contiguous block of memory.
24302 uint64_t resp_addr;
24305 /* L2 Completion Ring (CR) */
24306 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
24308 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
24310 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
24311 /* RoCE Notification Completion Ring (ROCE_CR) */
24312 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
24313 /* RX Aggregation Ring */
24314 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
24315 /* Notification Queue */
24316 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
24317 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
24318 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
24320 /* Physical number of ring allocated. */
24322 uint8_t unused_1[4];
24325 /* hwrm_ring_free_output (size:128b/16B) */
24326 struct hwrm_ring_free_output {
24327 /* The specific error status for the command. */
24328 uint16_t error_code;
24329 /* The HWRM command request type. */
24331 /* The sequence ID from the original command. */
24333 /* The length of the response data in number of bytes. */
24335 uint8_t unused_0[7];
24337 * This field is used in Output records to indicate that the output
24338 * is completely written to RAM. This field should be read as '1'
24339 * to indicate that the output has been completely written.
24340 * When writing a command completion or response to an internal processor,
24341 * the order of writes has to be such that this field is written last.
24346 /*******************
24347 * hwrm_ring_reset *
24348 *******************/
24351 /* hwrm_ring_reset_input (size:192b/24B) */
24352 struct hwrm_ring_reset_input {
24353 /* The HWRM command request type. */
24356 * The completion ring to send the completion event on. This should
24357 * be the NQ ID returned from the `nq_alloc` HWRM command.
24359 uint16_t cmpl_ring;
24361 * The sequence ID is used by the driver for tracking multiple
24362 * commands. This ID is treated as opaque data by the firmware and
24363 * the value is returned in the `hwrm_resp_hdr` upon completion.
24367 * The target ID of the command:
24368 * * 0x0-0xFFF8 - The function ID
24369 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24370 * * 0xFFFD - Reserved for user-space HWRM interface
24373 uint16_t target_id;
24375 * A physical address pointer pointing to a host buffer that the
24376 * command's response data will be written. This can be either a host
24377 * physical address (HPA) or a guest physical address (GPA) and must
24378 * point to a physically contiguous block of memory.
24380 uint64_t resp_addr;
24383 /* L2 Completion Ring (CR) */
24384 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
24386 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
24388 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
24389 /* RoCE Notification Completion Ring (ROCE_CR) */
24390 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
24391 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
24392 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
24394 /* Physical number of the ring. */
24396 uint8_t unused_1[4];
24399 /* hwrm_ring_reset_output (size:128b/16B) */
24400 struct hwrm_ring_reset_output {
24401 /* The specific error status for the command. */
24402 uint16_t error_code;
24403 /* The HWRM command request type. */
24405 /* The sequence ID from the original command. */
24407 /* The length of the response data in number of bytes. */
24409 uint8_t unused_0[4];
24410 /* Position of consumer index after ring reset completes. */
24411 uint8_t consumer_idx[3];
24413 * This field is used in Output records to indicate that the output
24414 * is completely written to RAM. This field should be read as '1'
24415 * to indicate that the output has been completely written.
24416 * When writing a command completion or response to an internal processor,
24417 * the order of writes has to be such that this field is written last.
24422 /**************************
24423 * hwrm_ring_aggint_qcaps *
24424 **************************/
24427 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
24428 struct hwrm_ring_aggint_qcaps_input {
24429 /* The HWRM command request type. */
24432 * The completion ring to send the completion event on. This should
24433 * be the NQ ID returned from the `nq_alloc` HWRM command.
24435 uint16_t cmpl_ring;
24437 * The sequence ID is used by the driver for tracking multiple
24438 * commands. This ID is treated as opaque data by the firmware and
24439 * the value is returned in the `hwrm_resp_hdr` upon completion.
24443 * The target ID of the command:
24444 * * 0x0-0xFFF8 - The function ID
24445 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24446 * * 0xFFFD - Reserved for user-space HWRM interface
24449 uint16_t target_id;
24451 * A physical address pointer pointing to a host buffer that the
24452 * command's response data will be written. This can be either a host
24453 * physical address (HPA) or a guest physical address (GPA) and must
24454 * point to a physically contiguous block of memory.
24456 uint64_t resp_addr;
24459 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
24460 struct hwrm_ring_aggint_qcaps_output {
24461 /* The specific error status for the command. */
24462 uint16_t error_code;
24463 /* The HWRM command request type. */
24465 /* The sequence ID from the original command. */
24467 /* The length of the response data in number of bytes. */
24469 uint32_t cmpl_params;
24471 * When this bit is set to '1', int_lat_tmr_min can be configured
24472 * on completion rings.
24474 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
24477 * When this bit is set to '1', int_lat_tmr_max can be configured
24478 * on completion rings.
24480 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
24483 * When this bit is set to '1', timer_reset can be enabled
24484 * on completion rings.
24486 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
24489 * When this bit is set to '1', ring_idle can be enabled
24490 * on completion rings.
24492 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
24495 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
24496 * on completion rings.
24498 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
24501 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
24502 * on completion rings.
24504 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
24507 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
24508 * on completion rings.
24510 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
24513 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
24514 * on completion rings.
24516 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
24519 * When this bit is set to '1', num_cmpl_aggr_int can be configured
24520 * on completion rings.
24522 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
24524 uint32_t nq_params;
24526 * When this bit is set to '1', int_lat_tmr_min can be configured
24527 * on notification queues.
24529 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
24531 /* Minimum value for num_cmpl_dma_aggr */
24532 uint16_t num_cmpl_dma_aggr_min;
24533 /* Maximum value for num_cmpl_dma_aggr */
24534 uint16_t num_cmpl_dma_aggr_max;
24535 /* Minimum value for num_cmpl_dma_aggr_during_int */
24536 uint16_t num_cmpl_dma_aggr_during_int_min;
24537 /* Maximum value for num_cmpl_dma_aggr_during_int */
24538 uint16_t num_cmpl_dma_aggr_during_int_max;
24539 /* Minimum value for cmpl_aggr_dma_tmr */
24540 uint16_t cmpl_aggr_dma_tmr_min;
24541 /* Maximum value for cmpl_aggr_dma_tmr */
24542 uint16_t cmpl_aggr_dma_tmr_max;
24543 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
24544 uint16_t cmpl_aggr_dma_tmr_during_int_min;
24545 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
24546 uint16_t cmpl_aggr_dma_tmr_during_int_max;
24547 /* Minimum value for int_lat_tmr_min */
24548 uint16_t int_lat_tmr_min_min;
24549 /* Maximum value for int_lat_tmr_min */
24550 uint16_t int_lat_tmr_min_max;
24551 /* Minimum value for int_lat_tmr_max */
24552 uint16_t int_lat_tmr_max_min;
24553 /* Maximum value for int_lat_tmr_max */
24554 uint16_t int_lat_tmr_max_max;
24555 /* Minimum value for num_cmpl_aggr_int */
24556 uint16_t num_cmpl_aggr_int_min;
24557 /* Maximum value for num_cmpl_aggr_int */
24558 uint16_t num_cmpl_aggr_int_max;
24559 /* The units for timer parameters, in nanoseconds. */
24560 uint16_t timer_units;
24561 uint8_t unused_0[1];
24563 * This field is used in Output records to indicate that the output
24564 * is completely written to RAM. This field should be read as '1'
24565 * to indicate that the output has been completely written.
24566 * When writing a command completion or response to an internal processor,
24567 * the order of writes has to be such that this field is written last.
24572 /**************************************
24573 * hwrm_ring_cmpl_ring_qaggint_params *
24574 **************************************/
24577 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
24578 struct hwrm_ring_cmpl_ring_qaggint_params_input {
24579 /* The HWRM command request type. */
24582 * The completion ring to send the completion event on. This should
24583 * be the NQ ID returned from the `nq_alloc` HWRM command.
24585 uint16_t cmpl_ring;
24587 * The sequence ID is used by the driver for tracking multiple
24588 * commands. This ID is treated as opaque data by the firmware and
24589 * the value is returned in the `hwrm_resp_hdr` upon completion.
24593 * The target ID of the command:
24594 * * 0x0-0xFFF8 - The function ID
24595 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24596 * * 0xFFFD - Reserved for user-space HWRM interface
24599 uint16_t target_id;
24601 * A physical address pointer pointing to a host buffer that the
24602 * command's response data will be written. This can be either a host
24603 * physical address (HPA) or a guest physical address (GPA) and must
24604 * point to a physically contiguous block of memory.
24606 uint64_t resp_addr;
24607 /* Physical number of completion ring. */
24609 uint8_t unused_0[6];
24612 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
24613 struct hwrm_ring_cmpl_ring_qaggint_params_output {
24614 /* The specific error status for the command. */
24615 uint16_t error_code;
24616 /* The HWRM command request type. */
24618 /* The sequence ID from the original command. */
24620 /* The length of the response data in number of bytes. */
24624 * When this bit is set to '1', interrupt max
24625 * timer is reset whenever a completion is received.
24627 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
24630 * When this bit is set to '1', ring idle mode
24631 * aggregation will be enabled.
24633 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
24636 * Number of completions to aggregate before DMA
24637 * during the normal mode.
24639 uint16_t num_cmpl_dma_aggr;
24641 * Number of completions to aggregate before DMA
24642 * during the interrupt mode.
24644 uint16_t num_cmpl_dma_aggr_during_int;
24646 * Timer in unit of 80-nsec used to aggregate completions before
24647 * DMA during the normal mode (not in interrupt mode).
24649 uint16_t cmpl_aggr_dma_tmr;
24651 * Timer in unit of 80-nsec used to aggregate completions before
24652 * DMA during the interrupt mode.
24654 uint16_t cmpl_aggr_dma_tmr_during_int;
24655 /* Minimum time (in unit of 80-nsec) between two interrupts. */
24656 uint16_t int_lat_tmr_min;
24658 * Maximum wait time (in unit of 80-nsec) spent aggregating
24659 * completions before signaling the interrupt after the
24660 * interrupt is enabled.
24662 uint16_t int_lat_tmr_max;
24664 * Minimum number of completions aggregated before signaling
24667 uint16_t num_cmpl_aggr_int;
24668 uint8_t unused_0[7];
24670 * This field is used in Output records to indicate that the output
24671 * is completely written to RAM. This field should be read as '1'
24672 * to indicate that the output has been completely written.
24673 * When writing a command completion or response to an internal processor,
24674 * the order of writes has to be such that this field is written last.
24679 /*****************************************
24680 * hwrm_ring_cmpl_ring_cfg_aggint_params *
24681 *****************************************/
24684 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
24685 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
24686 /* The HWRM command request type. */
24689 * The completion ring to send the completion event on. This should
24690 * be the NQ ID returned from the `nq_alloc` HWRM command.
24692 uint16_t cmpl_ring;
24694 * The sequence ID is used by the driver for tracking multiple
24695 * commands. This ID is treated as opaque data by the firmware and
24696 * the value is returned in the `hwrm_resp_hdr` upon completion.
24700 * The target ID of the command:
24701 * * 0x0-0xFFF8 - The function ID
24702 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24703 * * 0xFFFD - Reserved for user-space HWRM interface
24706 uint16_t target_id;
24708 * A physical address pointer pointing to a host buffer that the
24709 * command's response data will be written. This can be either a host
24710 * physical address (HPA) or a guest physical address (GPA) and must
24711 * point to a physically contiguous block of memory.
24713 uint64_t resp_addr;
24714 /* Physical number of completion ring. */
24718 * When this bit is set to '1', interrupt latency max
24719 * timer is reset whenever a completion is received.
24721 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
24724 * When this bit is set to '1', ring idle mode
24725 * aggregation will be enabled.
24727 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
24730 * Set this flag to 1 when configuring parameters on a
24731 * notification queue. Set this flag to 0 when configuring
24732 * parameters on a completion queue.
24734 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
24737 * Number of completions to aggregate before DMA
24738 * during the normal mode.
24740 uint16_t num_cmpl_dma_aggr;
24742 * Number of completions to aggregate before DMA
24743 * during the interrupt mode.
24745 uint16_t num_cmpl_dma_aggr_during_int;
24747 * Timer in unit of 80-nsec used to aggregate completions before
24748 * DMA during the normal mode (not in interrupt mode).
24750 uint16_t cmpl_aggr_dma_tmr;
24752 * Timer in unit of 80-nsec used to aggregate completions before
24753 * DMA during the interrupt mode.
24755 uint16_t cmpl_aggr_dma_tmr_during_int;
24756 /* Minimum time (in unit of 80-nsec) between two interrupts. */
24757 uint16_t int_lat_tmr_min;
24759 * Maximum wait time (in unit of 80-nsec) spent aggregating
24760 * cmpls before signaling the interrupt after the
24761 * interrupt is enabled.
24763 uint16_t int_lat_tmr_max;
24765 * Minimum number of completions aggregated before signaling
24768 uint16_t num_cmpl_aggr_int;
24770 * Bitfield that indicates which parameters are to be applied. Only
24771 * required when configuring devices with notification queues, and
24772 * used in that case to set certain parameters on completion queues
24773 * and others on notification queues.
24777 * This bit must be '1' for the num_cmpl_dma_aggr field to be
24780 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
24783 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
24786 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
24789 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
24792 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
24795 * This bit must be '1' for the int_lat_tmr_min field to be
24798 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
24801 * This bit must be '1' for the int_lat_tmr_max field to be
24804 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
24807 * This bit must be '1' for the num_cmpl_aggr_int field to be
24810 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
24812 uint8_t unused_0[4];
24815 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
24816 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
24817 /* The specific error status for the command. */
24818 uint16_t error_code;
24819 /* The HWRM command request type. */
24821 /* The sequence ID from the original command. */
24823 /* The length of the response data in number of bytes. */
24825 uint8_t unused_0[7];
24827 * This field is used in Output records to indicate that the output
24828 * is completely written to RAM. This field should be read as '1'
24829 * to indicate that the output has been completely written.
24830 * When writing a command completion or response to an internal processor,
24831 * the order of writes has to be such that this field is written last.
24836 /***********************
24837 * hwrm_ring_grp_alloc *
24838 ***********************/
24841 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
24842 struct hwrm_ring_grp_alloc_input {
24843 /* The HWRM command request type. */
24846 * The completion ring to send the completion event on. This should
24847 * be the NQ ID returned from the `nq_alloc` HWRM command.
24849 uint16_t cmpl_ring;
24851 * The sequence ID is used by the driver for tracking multiple
24852 * commands. This ID is treated as opaque data by the firmware and
24853 * the value is returned in the `hwrm_resp_hdr` upon completion.
24857 * The target ID of the command:
24858 * * 0x0-0xFFF8 - The function ID
24859 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24860 * * 0xFFFD - Reserved for user-space HWRM interface
24863 uint16_t target_id;
24865 * A physical address pointer pointing to a host buffer that the
24866 * command's response data will be written. This can be either a host
24867 * physical address (HPA) or a guest physical address (GPA) and must
24868 * point to a physically contiguous block of memory.
24870 uint64_t resp_addr;
24872 * This value identifies the CR associated with the ring
24877 * This value identifies the main RR associated with the ring
24882 * This value identifies the aggregation RR associated with
24883 * the ring group. If this value is 0xFF... (All Fs), then no
24884 * Aggregation ring will be set.
24888 * This value identifies the statistics context associated
24889 * with the ring group.
24894 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
24895 struct hwrm_ring_grp_alloc_output {
24896 /* The specific error status for the command. */
24897 uint16_t error_code;
24898 /* The HWRM command request type. */
24900 /* The sequence ID from the original command. */
24902 /* The length of the response data in number of bytes. */
24905 * This is the ring group ID value. Use this value to program
24906 * the default ring group for the VNIC or as table entries
24907 * in an RSS/COS context.
24909 uint32_t ring_group_id;
24910 uint8_t unused_0[3];
24912 * This field is used in Output records to indicate that the output
24913 * is completely written to RAM. This field should be read as '1'
24914 * to indicate that the output has been completely written.
24915 * When writing a command completion or response to an internal processor,
24916 * the order of writes has to be such that this field is written last.
24921 /**********************
24922 * hwrm_ring_grp_free *
24923 **********************/
24926 /* hwrm_ring_grp_free_input (size:192b/24B) */
24927 struct hwrm_ring_grp_free_input {
24928 /* The HWRM command request type. */
24931 * The completion ring to send the completion event on. This should
24932 * be the NQ ID returned from the `nq_alloc` HWRM command.
24934 uint16_t cmpl_ring;
24936 * The sequence ID is used by the driver for tracking multiple
24937 * commands. This ID is treated as opaque data by the firmware and
24938 * the value is returned in the `hwrm_resp_hdr` upon completion.
24942 * The target ID of the command:
24943 * * 0x0-0xFFF8 - The function ID
24944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24945 * * 0xFFFD - Reserved for user-space HWRM interface
24948 uint16_t target_id;
24950 * A physical address pointer pointing to a host buffer that the
24951 * command's response data will be written. This can be either a host
24952 * physical address (HPA) or a guest physical address (GPA) and must
24953 * point to a physically contiguous block of memory.
24955 uint64_t resp_addr;
24956 /* This is the ring group ID value. */
24957 uint32_t ring_group_id;
24958 uint8_t unused_0[4];
24961 /* hwrm_ring_grp_free_output (size:128b/16B) */
24962 struct hwrm_ring_grp_free_output {
24963 /* The specific error status for the command. */
24964 uint16_t error_code;
24965 /* The HWRM command request type. */
24967 /* The sequence ID from the original command. */
24969 /* The length of the response data in number of bytes. */
24971 uint8_t unused_0[7];
24973 * This field is used in Output records to indicate that the output
24974 * is completely written to RAM. This field should be read as '1'
24975 * to indicate that the output has been completely written.
24976 * When writing a command completion or response to an internal processor,
24977 * the order of writes has to be such that this field is written last.
24982 * special reserved flow ID to identify per function default
24983 * flows for vSwitch offload
24985 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
24987 * special reserved flow ID to identify per function RoCEv1
24990 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
24992 * special reserved flow ID to identify per function RoCEv2
24995 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
24997 * special reserved flow ID to identify per function RoCEv2
25000 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
25002 /****************************
25003 * hwrm_cfa_l2_filter_alloc *
25004 ****************************/
25007 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
25008 struct hwrm_cfa_l2_filter_alloc_input {
25009 /* The HWRM command request type. */
25012 * The completion ring to send the completion event on. This should
25013 * be the NQ ID returned from the `nq_alloc` HWRM command.
25015 uint16_t cmpl_ring;
25017 * The sequence ID is used by the driver for tracking multiple
25018 * commands. This ID is treated as opaque data by the firmware and
25019 * the value is returned in the `hwrm_resp_hdr` upon completion.
25023 * The target ID of the command:
25024 * * 0x0-0xFFF8 - The function ID
25025 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25026 * * 0xFFFD - Reserved for user-space HWRM interface
25029 uint16_t target_id;
25031 * A physical address pointer pointing to a host buffer that the
25032 * command's response data will be written. This can be either a host
25033 * physical address (HPA) or a guest physical address (GPA) and must
25034 * point to a physically contiguous block of memory.
25036 uint64_t resp_addr;
25039 * Enumeration denoting the RX, TX type of the resource.
25040 * This enumeration is used for resources that are similar for both
25041 * TX and RX paths of the chip.
25043 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
25046 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
25049 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
25051 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
25052 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
25053 /* Setting of this flag indicates the applicability to the loopback path. */
25054 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
25057 * Setting of this flag indicates drop action. If this flag is not set,
25058 * then it should be considered accept action.
25060 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
25063 * If this flag is set, all t_l2_* fields are invalid
25064 * and they should not be specified.
25065 * If this flag is set, then l2_* fields refer to
25066 * fields of outermost L2 header.
25068 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
25071 * Enumeration denoting NO_ROCE_L2 to support old drivers.
25072 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
25074 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
25076 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
25077 /* To support old drivers */
25078 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
25079 (UINT32_C(0x0) << 4)
25080 /* Only L2 traffic */
25081 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
25082 (UINT32_C(0x1) << 4)
25083 /* Roce & L2 traffic */
25084 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
25085 (UINT32_C(0x2) << 4)
25086 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
25087 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
25089 * Setting of this flag indicates that no XDP filter is created with
25091 * 0 - legacy behavior, XDP filter is created with L2 filter
25092 * 1 - XDP filter won't be created with L2 filter
25094 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
25097 * Setting this flag to 1 indicate the L2 fields in this command
25098 * pertain to source fields. Setting this flag to 0 indicate the
25099 * L2 fields in this command pertain to the destination fields
25100 * and this is the default/legacy behavior.
25102 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
25106 * This bit must be '1' for the l2_addr field to be
25109 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
25112 * This bit must be '1' for the l2_addr_mask field to be
25115 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
25118 * This bit must be '1' for the l2_ovlan field to be
25121 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
25124 * This bit must be '1' for the l2_ovlan_mask field to be
25127 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
25130 * This bit must be '1' for the l2_ivlan field to be
25133 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
25136 * This bit must be '1' for the l2_ivlan_mask field to be
25139 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
25142 * This bit must be '1' for the t_l2_addr field to be
25145 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
25148 * This bit must be '1' for the t_l2_addr_mask field to be
25151 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
25154 * This bit must be '1' for the t_l2_ovlan field to be
25157 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
25160 * This bit must be '1' for the t_l2_ovlan_mask field to be
25163 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
25166 * This bit must be '1' for the t_l2_ivlan field to be
25169 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
25172 * This bit must be '1' for the t_l2_ivlan_mask field to be
25175 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
25178 * This bit must be '1' for the src_type field to be
25181 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
25184 * This bit must be '1' for the src_id field to be
25187 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
25190 * This bit must be '1' for the tunnel_type field to be
25193 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
25196 * This bit must be '1' for the dst_id field to be
25199 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
25202 * This bit must be '1' for the mirror_vnic_id field to be
25205 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
25208 * This bit must be '1' for the num_vlans field to be
25211 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
25214 * This bit must be '1' for the t_num_vlans field to be
25217 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
25220 * This value sets the match value for the L2 MAC address.
25221 * Destination MAC address for RX path.
25222 * Source MAC address for TX path.
25224 uint8_t l2_addr[6];
25225 /* This value sets the match value for the number of VLANs. */
25228 * This value sets the match value for the number of VLANs
25229 * in the tunnel headers.
25231 uint8_t t_num_vlans;
25233 * This value sets the mask value for the L2 address.
25234 * A value of 0 will mask the corresponding bit from
25237 uint8_t l2_addr_mask[6];
25238 /* This value sets VLAN ID value for outer VLAN. */
25241 * This value sets the mask value for the ovlan id.
25242 * A value of 0 will mask the corresponding bit from
25245 uint16_t l2_ovlan_mask;
25246 /* This value sets VLAN ID value for inner VLAN. */
25249 * This value sets the mask value for the ivlan id.
25250 * A value of 0 will mask the corresponding bit from
25253 uint16_t l2_ivlan_mask;
25254 uint8_t unused_1[2];
25256 * This value sets the match value for the tunnel
25258 * Destination MAC address for RX path.
25259 * Source MAC address for TX path.
25261 uint8_t t_l2_addr[6];
25262 uint8_t unused_2[2];
25264 * This value sets the mask value for the tunnel L2
25266 * A value of 0 will mask the corresponding bit from
25269 uint8_t t_l2_addr_mask[6];
25270 /* This value sets VLAN ID value for tunnel outer VLAN. */
25271 uint16_t t_l2_ovlan;
25273 * This value sets the mask value for the tunnel ovlan id.
25274 * A value of 0 will mask the corresponding bit from
25277 uint16_t t_l2_ovlan_mask;
25278 /* This value sets VLAN ID value for tunnel inner VLAN. */
25279 uint16_t t_l2_ivlan;
25281 * This value sets the mask value for the tunnel ivlan id.
25282 * A value of 0 will mask the corresponding bit from
25285 uint16_t t_l2_ivlan_mask;
25286 /* This value identifies the type of source of the packet. */
25289 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
25290 /* Physical function */
25291 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
25292 /* Virtual function */
25293 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
25294 /* Virtual NIC of a function */
25295 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
25296 /* Embedded processor for CFA management */
25297 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
25298 /* Embedded processor for OOB management */
25299 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
25300 /* Embedded processor for RoCE */
25301 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
25302 /* Embedded processor for network proxy functions */
25303 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
25304 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
25305 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
25308 * This value is the id of the source.
25309 * For a network port, it represents port_id.
25310 * For a physical function, it represents fid.
25311 * For a virtual function, it represents vf_id.
25312 * For a vnic, it represents vnic_id.
25313 * For embedded processors, this id is not valid.
25316 * 1. The function ID is implied if it src_id is
25317 * not provided for a src_type that is either
25321 uint8_t tunnel_type;
25323 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
25325 /* Virtual eXtensible Local Area Network (VXLAN) */
25326 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25328 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
25329 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
25331 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
25332 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
25335 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
25337 /* Generic Network Virtualization Encapsulation (Geneve) */
25338 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25340 /* Multi-Protocol Label Switching (MPLS) */
25341 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
25343 /* Stateless Transport Tunnel (STT) */
25344 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
25346 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
25347 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
25349 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25350 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25352 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25353 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25355 /* Use fixed layer 2 ether type of 0xFFFF */
25356 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
25358 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
25359 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
25361 /* Any tunneled traffic */
25362 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
25364 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25365 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
25368 * If set, this value shall represent the
25369 * Logical VNIC ID of the destination VNIC for the RX
25370 * path and network port id of the destination port for
25375 * Logical VNIC ID of the VNIC where traffic is
25378 uint16_t mirror_vnic_id;
25380 * This hint is provided to help in placing
25381 * the filter in the filter table.
25384 /* No preference */
25385 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
25387 /* Above the given filter */
25388 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
25390 /* Below the given filter */
25391 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
25393 /* As high as possible */
25394 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
25396 /* As low as possible */
25397 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
25399 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
25400 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
25404 * This is the ID of the filter that goes along with
25407 * This field is valid only for the following values.
25408 * 1 - Above the given filter
25409 * 2 - Below the given filter
25411 uint64_t l2_filter_id_hint;
25414 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
25415 struct hwrm_cfa_l2_filter_alloc_output {
25416 /* The specific error status for the command. */
25417 uint16_t error_code;
25418 /* The HWRM command request type. */
25420 /* The sequence ID from the original command. */
25422 /* The length of the response data in number of bytes. */
25425 * This value identifies a set of CFA data structures used for an L2
25428 uint64_t l2_filter_id;
25430 * The flow id value in bit 0-29 is the actual ID of the flow
25431 * associated with this filter and it shall be used to match
25432 * and associate the flow identifier returned in completion
25433 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
25434 * shall indicate no valid flow id.
25437 /* Indicate the flow id value. */
25438 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
25439 UINT32_C(0x3fffffff)
25440 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
25441 /* Indicate type of the flow. */
25442 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
25443 UINT32_C(0x40000000)
25445 * If this bit set to 0, then it indicates that the flow is
25448 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
25449 (UINT32_C(0x0) << 30)
25451 * If this bit is set to 1, then it indicates that the flow is
25454 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
25455 (UINT32_C(0x1) << 30)
25456 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
25457 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
25458 /* Indicate the flow direction. */
25459 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
25460 UINT32_C(0x80000000)
25461 /* If this bit set to 0, then it indicates rx flow. */
25462 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
25463 (UINT32_C(0x0) << 31)
25464 /* If this bit is set to 1, then it indicates that tx flow. */
25465 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
25466 (UINT32_C(0x1) << 31)
25467 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
25468 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
25469 uint8_t unused_0[3];
25471 * This field is used in Output records to indicate that the output
25472 * is completely written to RAM. This field should be read as '1'
25473 * to indicate that the output has been completely written.
25474 * When writing a command completion or response to an internal processor,
25475 * the order of writes has to be such that this field is written last.
25480 /***************************
25481 * hwrm_cfa_l2_filter_free *
25482 ***************************/
25485 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
25486 struct hwrm_cfa_l2_filter_free_input {
25487 /* The HWRM command request type. */
25490 * The completion ring to send the completion event on. This should
25491 * be the NQ ID returned from the `nq_alloc` HWRM command.
25493 uint16_t cmpl_ring;
25495 * The sequence ID is used by the driver for tracking multiple
25496 * commands. This ID is treated as opaque data by the firmware and
25497 * the value is returned in the `hwrm_resp_hdr` upon completion.
25501 * The target ID of the command:
25502 * * 0x0-0xFFF8 - The function ID
25503 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25504 * * 0xFFFD - Reserved for user-space HWRM interface
25507 uint16_t target_id;
25509 * A physical address pointer pointing to a host buffer that the
25510 * command's response data will be written. This can be either a host
25511 * physical address (HPA) or a guest physical address (GPA) and must
25512 * point to a physically contiguous block of memory.
25514 uint64_t resp_addr;
25516 * This value identifies a set of CFA data structures used for an L2
25519 uint64_t l2_filter_id;
25522 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
25523 struct hwrm_cfa_l2_filter_free_output {
25524 /* The specific error status for the command. */
25525 uint16_t error_code;
25526 /* The HWRM command request type. */
25528 /* The sequence ID from the original command. */
25530 /* The length of the response data in number of bytes. */
25532 uint8_t unused_0[7];
25534 * This field is used in Output records to indicate that the output
25535 * is completely written to RAM. This field should be read as '1'
25536 * to indicate that the output has been completely written.
25537 * When writing a command completion or response to an internal processor,
25538 * the order of writes has to be such that this field is written last.
25543 /**************************
25544 * hwrm_cfa_l2_filter_cfg *
25545 **************************/
25548 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
25549 struct hwrm_cfa_l2_filter_cfg_input {
25550 /* The HWRM command request type. */
25553 * The completion ring to send the completion event on. This should
25554 * be the NQ ID returned from the `nq_alloc` HWRM command.
25556 uint16_t cmpl_ring;
25558 * The sequence ID is used by the driver for tracking multiple
25559 * commands. This ID is treated as opaque data by the firmware and
25560 * the value is returned in the `hwrm_resp_hdr` upon completion.
25564 * The target ID of the command:
25565 * * 0x0-0xFFF8 - The function ID
25566 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25567 * * 0xFFFD - Reserved for user-space HWRM interface
25570 uint16_t target_id;
25572 * A physical address pointer pointing to a host buffer that the
25573 * command's response data will be written. This can be either a host
25574 * physical address (HPA) or a guest physical address (GPA) and must
25575 * point to a physically contiguous block of memory.
25577 uint64_t resp_addr;
25580 * Enumeration denoting the RX, TX type of the resource.
25581 * This enumeration is used for resources that are similar for both
25582 * TX and RX paths of the chip.
25584 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
25587 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
25590 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
25592 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
25593 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
25595 * Setting of this flag indicates drop action. If this flag is not set,
25596 * then it should be considered accept action.
25598 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
25601 * Enumeration denoting NO_ROCE_L2 to support old drivers.
25602 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
25604 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
25606 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
25607 /* To support old drivers */
25608 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
25609 (UINT32_C(0x0) << 2)
25610 /* Only L2 traffic */
25611 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
25612 (UINT32_C(0x1) << 2)
25613 /* Roce & L2 traffic */
25614 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
25615 (UINT32_C(0x2) << 2)
25616 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
25617 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
25620 * This bit must be '1' for the dst_id field to be
25623 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
25626 * This bit must be '1' for the new_mirror_vnic_id field to be
25629 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
25632 * This value identifies a set of CFA data structures used for an L2
25635 uint64_t l2_filter_id;
25637 * If set, this value shall represent the
25638 * Logical VNIC ID of the destination VNIC for the RX
25639 * path and network port id of the destination port for
25644 * New Logical VNIC ID of the VNIC where traffic is
25647 uint32_t new_mirror_vnic_id;
25650 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
25651 struct hwrm_cfa_l2_filter_cfg_output {
25652 /* The specific error status for the command. */
25653 uint16_t error_code;
25654 /* The HWRM command request type. */
25656 /* The sequence ID from the original command. */
25658 /* The length of the response data in number of bytes. */
25660 uint8_t unused_0[7];
25662 * This field is used in Output records to indicate that the output
25663 * is completely written to RAM. This field should be read as '1'
25664 * to indicate that the output has been completely written.
25665 * When writing a command completion or response to an internal processor,
25666 * the order of writes has to be such that this field is written last.
25671 /***************************
25672 * hwrm_cfa_l2_set_rx_mask *
25673 ***************************/
25676 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
25677 struct hwrm_cfa_l2_set_rx_mask_input {
25678 /* The HWRM command request type. */
25681 * The completion ring to send the completion event on. This should
25682 * be the NQ ID returned from the `nq_alloc` HWRM command.
25684 uint16_t cmpl_ring;
25686 * The sequence ID is used by the driver for tracking multiple
25687 * commands. This ID is treated as opaque data by the firmware and
25688 * the value is returned in the `hwrm_resp_hdr` upon completion.
25692 * The target ID of the command:
25693 * * 0x0-0xFFF8 - The function ID
25694 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25695 * * 0xFFFD - Reserved for user-space HWRM interface
25698 uint16_t target_id;
25700 * A physical address pointer pointing to a host buffer that the
25701 * command's response data will be written. This can be either a host
25702 * physical address (HPA) or a guest physical address (GPA) and must
25703 * point to a physically contiguous block of memory.
25705 uint64_t resp_addr;
25710 * When this bit is '1', the function is requested to accept
25711 * multi-cast packets specified by the multicast addr table.
25713 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
25716 * When this bit is '1', the function is requested to accept
25717 * all multi-cast packets.
25719 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
25722 * When this bit is '1', the function is requested to accept
25723 * broadcast packets.
25725 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
25728 * When this bit is '1', the function is requested to be
25729 * put in the promiscuous mode.
25731 * The HWRM should accept any function to set up
25732 * promiscuous mode.
25734 * The HWRM shall follow the semantics below for the
25735 * promiscuous mode support.
25736 * # When partitioning is not enabled on a port
25737 * (i.e. single PF on the port), then the PF shall
25738 * be allowed to be in the promiscuous mode. When the
25739 * PF is in the promiscuous mode, then it shall
25740 * receive all host bound traffic on that port.
25741 * # When partitioning is enabled on a port
25742 * (i.e. multiple PFs per port) and a PF on that
25743 * port is in the promiscuous mode, then the PF
25744 * receives all traffic within that partition as
25745 * identified by a unique identifier for the
25746 * PF (e.g. S-Tag). If a unique outer VLAN
25747 * for the PF is specified, then the setting of
25748 * promiscuous mode on that PF shall result in the
25749 * PF receiving all host bound traffic with matching
25751 * # A VF shall can be set in the promiscuous mode.
25752 * In the promiscuous mode, the VF does not receive any
25753 * traffic unless a unique outer VLAN for the
25754 * VF is specified. If a unique outer VLAN
25755 * for the VF is specified, then the setting of
25756 * promiscuous mode on that VF shall result in the
25757 * VF receiving all host bound traffic with the
25758 * matching outer VLAN.
25759 * # The HWRM shall allow the setting of promiscuous
25760 * mode on a function independently from the
25761 * promiscuous mode settings on other functions.
25763 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
25766 * If this flag is set, the corresponding RX
25767 * filters shall be set up to cover multicast/broadcast
25768 * filters for the outermost Layer 2 destination MAC
25771 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
25774 * If this flag is set, the corresponding RX
25775 * filters shall be set up to cover multicast/broadcast
25776 * filters for the VLAN-tagged packets that match the
25777 * TPID and VID fields of VLAN tags in the VLAN tag
25778 * table specified in this command.
25780 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
25783 * If this flag is set, the corresponding RX
25784 * filters shall be set up to cover multicast/broadcast
25785 * filters for non-VLAN tagged packets and VLAN-tagged
25786 * packets that match the TPID and VID fields of VLAN
25787 * tags in the VLAN tag table specified in this command.
25789 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
25792 * If this flag is set, the corresponding RX
25793 * filters shall be set up to cover multicast/broadcast
25794 * filters for non-VLAN tagged packets and VLAN-tagged
25795 * packets matching any VLAN tag.
25797 * If this flag is set, then the HWRM shall ignore
25798 * VLAN tags specified in vlan_tag_tbl.
25800 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
25801 * flags is set, then the HWRM shall ignore
25802 * VLAN tags specified in vlan_tag_tbl.
25804 * The HWRM client shall set at most one flag out of
25805 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
25807 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
25809 /* This is the address for mcast address tbl. */
25810 uint64_t mc_tbl_addr;
25812 * This value indicates how many entries in mc_tbl are valid.
25813 * Each entry is 6 bytes.
25815 uint32_t num_mc_entries;
25816 uint8_t unused_0[4];
25818 * This is the address for VLAN tag table.
25819 * Each VLAN entry in the table is 4 bytes of a VLAN tag
25820 * including TPID, PCP, DEI, and VID fields in network byte
25823 uint64_t vlan_tag_tbl_addr;
25825 * This value indicates how many entries in vlan_tag_tbl are
25826 * valid. Each entry is 4 bytes.
25828 uint32_t num_vlan_tags;
25829 uint8_t unused_1[4];
25832 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
25833 struct hwrm_cfa_l2_set_rx_mask_output {
25834 /* The specific error status for the command. */
25835 uint16_t error_code;
25836 /* The HWRM command request type. */
25838 /* The sequence ID from the original command. */
25840 /* The length of the response data in number of bytes. */
25842 uint8_t unused_0[7];
25844 * This field is used in Output records to indicate that the output
25845 * is completely written to RAM. This field should be read as '1'
25846 * to indicate that the output has been completely written.
25847 * When writing a command completion or response to an internal processor,
25848 * the order of writes has to be such that this field is written last.
25853 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
25854 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
25856 * command specific error codes that goes to
25857 * the cmd_err field in Common HWRM Error Response.
25860 /* Unknown error */
25861 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
25863 /* Unable to complete operation due to conflict with Ntuple Filter */
25864 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
25866 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
25867 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
25868 uint8_t unused_0[7];
25871 /*******************************
25872 * hwrm_cfa_vlan_antispoof_cfg *
25873 *******************************/
25876 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
25877 struct hwrm_cfa_vlan_antispoof_cfg_input {
25878 /* The HWRM command request type. */
25881 * The completion ring to send the completion event on. This should
25882 * be the NQ ID returned from the `nq_alloc` HWRM command.
25884 uint16_t cmpl_ring;
25886 * The sequence ID is used by the driver for tracking multiple
25887 * commands. This ID is treated as opaque data by the firmware and
25888 * the value is returned in the `hwrm_resp_hdr` upon completion.
25892 * The target ID of the command:
25893 * * 0x0-0xFFF8 - The function ID
25894 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25895 * * 0xFFFD - Reserved for user-space HWRM interface
25898 uint16_t target_id;
25900 * A physical address pointer pointing to a host buffer that the
25901 * command's response data will be written. This can be either a host
25902 * physical address (HPA) or a guest physical address (GPA) and must
25903 * point to a physically contiguous block of memory.
25905 uint64_t resp_addr;
25907 * Function ID of the function that is being configured.
25908 * Only valid for a VF FID configured by the PF.
25911 uint8_t unused_0[2];
25912 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
25913 uint32_t num_vlan_entries;
25915 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
25916 * antispoof table. Each table entry contains the 16-bit TPID
25917 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
25918 * all in network order to match hwrm_cfa_l2_set_rx_mask.
25919 * For an individual VLAN entry, the mask value should be 0xfff
25920 * for the 12-bit VLAN ID.
25922 uint64_t vlan_tag_mask_tbl_addr;
25925 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
25926 struct hwrm_cfa_vlan_antispoof_cfg_output {
25927 /* The specific error status for the command. */
25928 uint16_t error_code;
25929 /* The HWRM command request type. */
25931 /* The sequence ID from the original command. */
25933 /* The length of the response data in number of bytes. */
25935 uint8_t unused_0[7];
25937 * This field is used in Output records to indicate that the output
25938 * is completely written to RAM. This field should be read as '1'
25939 * to indicate that the output has been completely written.
25940 * When writing a command completion or response to an internal processor,
25941 * the order of writes has to be such that this field is written last.
25946 /********************************
25947 * hwrm_cfa_vlan_antispoof_qcfg *
25948 ********************************/
25951 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
25952 struct hwrm_cfa_vlan_antispoof_qcfg_input {
25953 /* The HWRM command request type. */
25956 * The completion ring to send the completion event on. This should
25957 * be the NQ ID returned from the `nq_alloc` HWRM command.
25959 uint16_t cmpl_ring;
25961 * The sequence ID is used by the driver for tracking multiple
25962 * commands. This ID is treated as opaque data by the firmware and
25963 * the value is returned in the `hwrm_resp_hdr` upon completion.
25967 * The target ID of the command:
25968 * * 0x0-0xFFF8 - The function ID
25969 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25970 * * 0xFFFD - Reserved for user-space HWRM interface
25973 uint16_t target_id;
25975 * A physical address pointer pointing to a host buffer that the
25976 * command's response data will be written. This can be either a host
25977 * physical address (HPA) or a guest physical address (GPA) and must
25978 * point to a physically contiguous block of memory.
25980 uint64_t resp_addr;
25982 * Function ID of the function that is being queried.
25983 * Only valid for a VF FID queried by the PF.
25986 uint8_t unused_0[2];
25988 * Maximum number of VLAN entries the firmware is allowed to DMA
25989 * to vlan_tag_mask_tbl.
25991 uint32_t max_vlan_entries;
25993 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
25994 * antispoof table to which firmware will DMA to. Each table
25995 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
25996 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
25997 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
25998 * the mask value should be 0xfff for the 12-bit VLAN ID.
26000 uint64_t vlan_tag_mask_tbl_addr;
26003 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
26004 struct hwrm_cfa_vlan_antispoof_qcfg_output {
26005 /* The specific error status for the command. */
26006 uint16_t error_code;
26007 /* The HWRM command request type. */
26009 /* The sequence ID from the original command. */
26011 /* The length of the response data in number of bytes. */
26013 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
26014 uint32_t num_vlan_entries;
26015 uint8_t unused_0[3];
26017 * This field is used in Output records to indicate that the output
26018 * is completely written to RAM. This field should be read as '1'
26019 * to indicate that the output has been completely written.
26020 * When writing a command completion or response to an internal processor,
26021 * the order of writes has to be such that this field is written last.
26026 /********************************
26027 * hwrm_cfa_tunnel_filter_alloc *
26028 ********************************/
26031 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
26032 struct hwrm_cfa_tunnel_filter_alloc_input {
26033 /* The HWRM command request type. */
26036 * The completion ring to send the completion event on. This should
26037 * be the NQ ID returned from the `nq_alloc` HWRM command.
26039 uint16_t cmpl_ring;
26041 * The sequence ID is used by the driver for tracking multiple
26042 * commands. This ID is treated as opaque data by the firmware and
26043 * the value is returned in the `hwrm_resp_hdr` upon completion.
26047 * The target ID of the command:
26048 * * 0x0-0xFFF8 - The function ID
26049 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26050 * * 0xFFFD - Reserved for user-space HWRM interface
26053 uint16_t target_id;
26055 * A physical address pointer pointing to a host buffer that the
26056 * command's response data will be written. This can be either a host
26057 * physical address (HPA) or a guest physical address (GPA) and must
26058 * point to a physically contiguous block of memory.
26060 uint64_t resp_addr;
26062 /* Setting of this flag indicates the applicability to the loopback path. */
26063 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
26067 * This bit must be '1' for the l2_filter_id field to be
26070 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
26073 * This bit must be '1' for the l2_addr field to be
26076 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
26079 * This bit must be '1' for the l2_ivlan field to be
26082 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
26085 * This bit must be '1' for the l3_addr field to be
26088 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
26091 * This bit must be '1' for the l3_addr_type field to be
26094 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
26097 * This bit must be '1' for the t_l3_addr_type field to be
26100 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
26103 * This bit must be '1' for the t_l3_addr field to be
26106 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
26109 * This bit must be '1' for the tunnel_type field to be
26112 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
26115 * This bit must be '1' for the vni field to be
26118 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
26121 * This bit must be '1' for the dst_vnic_id field to be
26124 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
26127 * This bit must be '1' for the mirror_vnic_id field to be
26130 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
26133 * This value identifies a set of CFA data structures used for an L2
26136 uint64_t l2_filter_id;
26138 * This value sets the match value for the inner L2
26140 * Destination MAC address for RX path.
26141 * Source MAC address for TX path.
26143 uint8_t l2_addr[6];
26145 * This value sets VLAN ID value for inner VLAN.
26146 * Only 12-bits of VLAN ID are used in setting the filter.
26150 * The value of inner destination IP address to be used in filtering.
26151 * For IPv4, first four bytes represent the IP address.
26153 uint32_t l3_addr[4];
26155 * The value of tunnel destination IP address to be used in filtering.
26156 * For IPv4, first four bytes represent the IP address.
26158 uint32_t t_l3_addr[4];
26160 * This value indicates the type of inner IP address.
26163 * All others are invalid.
26165 uint8_t l3_addr_type;
26167 * This value indicates the type of tunnel IP address.
26170 * All others are invalid.
26172 uint8_t t_l3_addr_type;
26174 uint8_t tunnel_type;
26176 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26178 /* Virtual eXtensible Local Area Network (VXLAN) */
26179 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26181 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26182 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26184 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26185 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26188 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26190 /* Generic Network Virtualization Encapsulation (Geneve) */
26191 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26193 /* Multi-Protocol Label Switching (MPLS) */
26194 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26196 /* Stateless Transport Tunnel (STT) */
26197 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
26199 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26200 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26202 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26203 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26205 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26206 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26208 /* Use fixed layer 2 ether type of 0xFFFF */
26209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26211 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26212 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26214 /* Any tunneled traffic */
26215 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26217 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26218 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26220 * tunnel_flags allows the user to indicate the tunnel tag detection
26221 * for the tunnel type specified in tunnel_type.
26223 uint8_t tunnel_flags;
26225 * If the tunnel_type is geneve, then this bit indicates if we
26226 * need to match the geneve OAM packet.
26227 * If the tunnel_type is nvgre or gre, then this bit indicates if
26228 * we need to detect checksum present bit in geneve header.
26229 * If the tunnel_type is mpls, then this bit indicates if we need
26230 * to match mpls packet with explicit IPV4/IPV6 null header.
26232 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
26235 * If the tunnel_type is geneve, then this bit indicates if we
26236 * need to detect the critical option bit set in the oam packet.
26237 * If the tunnel_type is nvgre or gre, then this bit indicates
26238 * if we need to match nvgre packets with key present bit set in
26240 * If the tunnel_type is mpls, then this bit indicates if we
26241 * need to match mpls packet with S bit from inner/second label.
26243 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
26246 * If the tunnel_type is geneve, then this bit indicates if we
26247 * need to match geneve packet with extended header bit set in
26249 * If the tunnel_type is nvgre or gre, then this bit indicates
26250 * if we need to match nvgre packets with sequence number
26251 * present bit set in gre header.
26252 * If the tunnel_type is mpls, then this bit indicates if we
26253 * need to match mpls packet with S bit from out/first label.
26255 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
26258 * Virtual Network Identifier (VNI). Only valid with
26259 * tunnel_types VXLAN, NVGRE, and Geneve.
26260 * Only lower 24-bits of VNI field are used
26261 * in setting up the filter.
26264 /* Logical VNIC ID of the destination VNIC. */
26265 uint32_t dst_vnic_id;
26267 * Logical VNIC ID of the VNIC where traffic is
26270 uint32_t mirror_vnic_id;
26273 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
26274 struct hwrm_cfa_tunnel_filter_alloc_output {
26275 /* The specific error status for the command. */
26276 uint16_t error_code;
26277 /* The HWRM command request type. */
26279 /* The sequence ID from the original command. */
26281 /* The length of the response data in number of bytes. */
26283 /* This value is an opaque id into CFA data structures. */
26284 uint64_t tunnel_filter_id;
26286 * The flow id value in bit 0-29 is the actual ID of the flow
26287 * associated with this filter and it shall be used to match
26288 * and associate the flow identifier returned in completion
26289 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
26290 * shall indicate no valid flow id.
26293 /* Indicate the flow id value. */
26294 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
26295 UINT32_C(0x3fffffff)
26296 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
26297 /* Indicate type of the flow. */
26298 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
26299 UINT32_C(0x40000000)
26301 * If this bit set to 0, then it indicates that the flow is
26304 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
26305 (UINT32_C(0x0) << 30)
26307 * If this bit is set to 1, then it indicates that the flow is
26310 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
26311 (UINT32_C(0x1) << 30)
26312 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
26313 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
26314 /* Indicate the flow direction. */
26315 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
26316 UINT32_C(0x80000000)
26317 /* If this bit set to 0, then it indicates rx flow. */
26318 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
26319 (UINT32_C(0x0) << 31)
26320 /* If this bit is set to 1, then it indicates that tx flow. */
26321 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
26322 (UINT32_C(0x1) << 31)
26323 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
26324 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
26325 uint8_t unused_0[3];
26327 * This field is used in Output records to indicate that the output
26328 * is completely written to RAM. This field should be read as '1'
26329 * to indicate that the output has been completely written.
26330 * When writing a command completion or response to an internal processor,
26331 * the order of writes has to be such that this field is written last.
26336 /*******************************
26337 * hwrm_cfa_tunnel_filter_free *
26338 *******************************/
26341 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
26342 struct hwrm_cfa_tunnel_filter_free_input {
26343 /* The HWRM command request type. */
26346 * The completion ring to send the completion event on. This should
26347 * be the NQ ID returned from the `nq_alloc` HWRM command.
26349 uint16_t cmpl_ring;
26351 * The sequence ID is used by the driver for tracking multiple
26352 * commands. This ID is treated as opaque data by the firmware and
26353 * the value is returned in the `hwrm_resp_hdr` upon completion.
26357 * The target ID of the command:
26358 * * 0x0-0xFFF8 - The function ID
26359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26360 * * 0xFFFD - Reserved for user-space HWRM interface
26363 uint16_t target_id;
26365 * A physical address pointer pointing to a host buffer that the
26366 * command's response data will be written. This can be either a host
26367 * physical address (HPA) or a guest physical address (GPA) and must
26368 * point to a physically contiguous block of memory.
26370 uint64_t resp_addr;
26371 /* This value is an opaque id into CFA data structures. */
26372 uint64_t tunnel_filter_id;
26375 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
26376 struct hwrm_cfa_tunnel_filter_free_output {
26377 /* The specific error status for the command. */
26378 uint16_t error_code;
26379 /* The HWRM command request type. */
26381 /* The sequence ID from the original command. */
26383 /* The length of the response data in number of bytes. */
26385 uint8_t unused_0[7];
26387 * This field is used in Output records to indicate that the output
26388 * is completely written to RAM. This field should be read as '1'
26389 * to indicate that the output has been completely written.
26390 * When writing a command completion or response to an internal processor,
26391 * the order of writes has to be such that this field is written last.
26396 /***************************************
26397 * hwrm_cfa_redirect_tunnel_type_alloc *
26398 ***************************************/
26401 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
26402 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
26403 /* The HWRM command request type. */
26406 * The completion ring to send the completion event on. This should
26407 * be the NQ ID returned from the `nq_alloc` HWRM command.
26409 uint16_t cmpl_ring;
26411 * The sequence ID is used by the driver for tracking multiple
26412 * commands. This ID is treated as opaque data by the firmware and
26413 * the value is returned in the `hwrm_resp_hdr` upon completion.
26417 * The target ID of the command:
26418 * * 0x0-0xFFF8 - The function ID
26419 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26420 * * 0xFFFD - Reserved for user-space HWRM interface
26423 uint16_t target_id;
26425 * A physical address pointer pointing to a host buffer that the
26426 * command's response data will be written. This can be either a host
26427 * physical address (HPA) or a guest physical address (GPA) and must
26428 * point to a physically contiguous block of memory.
26430 uint64_t resp_addr;
26431 /* The destination function id, to whom the traffic is redirected. */
26434 uint8_t tunnel_type;
26436 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
26438 /* Virtual eXtensible Local Area Network (VXLAN) */
26439 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
26441 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26442 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
26444 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26445 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
26448 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
26450 /* Generic Network Virtualization Encapsulation (Geneve) */
26451 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
26453 /* Multi-Protocol Label Switching (MPLS) */
26454 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
26456 /* Stateless Transport Tunnel (STT) */
26457 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
26459 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26460 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
26462 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26463 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26465 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26466 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26468 /* Use fixed layer 2 ether type of 0xFFFF */
26469 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
26471 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26472 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26474 /* Any tunneled traffic */
26475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26477 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
26478 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
26479 /* Tunnel alloc flags. */
26481 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
26482 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
26484 uint8_t unused_0[4];
26487 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
26488 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
26489 /* The specific error status for the command. */
26490 uint16_t error_code;
26491 /* The HWRM command request type. */
26493 /* The sequence ID from the original command. */
26495 /* The length of the response data in number of bytes. */
26497 uint8_t unused_0[7];
26499 * This field is used in Output records to indicate that the output
26500 * is completely written to RAM. This field should be read as '1'
26501 * to indicate that the output has been completely written.
26502 * When writing a command completion or response to an internal processor,
26503 * the order of writes has to be such that this field is written last.
26508 /**************************************
26509 * hwrm_cfa_redirect_tunnel_type_free *
26510 **************************************/
26513 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
26514 struct hwrm_cfa_redirect_tunnel_type_free_input {
26515 /* The HWRM command request type. */
26518 * The completion ring to send the completion event on. This should
26519 * be the NQ ID returned from the `nq_alloc` HWRM command.
26521 uint16_t cmpl_ring;
26523 * The sequence ID is used by the driver for tracking multiple
26524 * commands. This ID is treated as opaque data by the firmware and
26525 * the value is returned in the `hwrm_resp_hdr` upon completion.
26529 * The target ID of the command:
26530 * * 0x0-0xFFF8 - The function ID
26531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26532 * * 0xFFFD - Reserved for user-space HWRM interface
26535 uint16_t target_id;
26537 * A physical address pointer pointing to a host buffer that the
26538 * command's response data will be written. This can be either a host
26539 * physical address (HPA) or a guest physical address (GPA) and must
26540 * point to a physically contiguous block of memory.
26542 uint64_t resp_addr;
26543 /* The destination function id, to whom the traffic is redirected. */
26546 uint8_t tunnel_type;
26548 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
26550 /* Virtual eXtensible Local Area Network (VXLAN) */
26551 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
26553 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26554 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
26556 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26557 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
26560 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
26562 /* Generic Network Virtualization Encapsulation (Geneve) */
26563 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
26565 /* Multi-Protocol Label Switching (MPLS) */
26566 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
26568 /* Stateless Transport Tunnel (STT) */
26569 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
26571 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26572 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
26574 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26575 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26577 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26578 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26580 /* Use fixed layer 2 ether type of 0xFFFF */
26581 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
26583 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26584 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26586 /* Any tunneled traffic */
26587 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26589 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
26590 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
26591 uint8_t unused_0[5];
26594 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
26595 struct hwrm_cfa_redirect_tunnel_type_free_output {
26596 /* The specific error status for the command. */
26597 uint16_t error_code;
26598 /* The HWRM command request type. */
26600 /* The sequence ID from the original command. */
26602 /* The length of the response data in number of bytes. */
26604 uint8_t unused_0[7];
26606 * This field is used in Output records to indicate that the output
26607 * is completely written to RAM. This field should be read as '1'
26608 * to indicate that the output has been completely written.
26609 * When writing a command completion or response to an internal processor,
26610 * the order of writes has to be such that this field is written last.
26615 /**************************************
26616 * hwrm_cfa_redirect_tunnel_type_info *
26617 **************************************/
26620 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
26621 struct hwrm_cfa_redirect_tunnel_type_info_input {
26622 /* The HWRM command request type. */
26625 * The completion ring to send the completion event on. This should
26626 * be the NQ ID returned from the `nq_alloc` HWRM command.
26628 uint16_t cmpl_ring;
26630 * The sequence ID is used by the driver for tracking multiple
26631 * commands. This ID is treated as opaque data by the firmware and
26632 * the value is returned in the `hwrm_resp_hdr` upon completion.
26636 * The target ID of the command:
26637 * * 0x0-0xFFF8 - The function ID
26638 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26639 * * 0xFFFD - Reserved for user-space HWRM interface
26642 uint16_t target_id;
26644 * A physical address pointer pointing to a host buffer that the
26645 * command's response data will be written. This can be either a host
26646 * physical address (HPA) or a guest physical address (GPA) and must
26647 * point to a physically contiguous block of memory.
26649 uint64_t resp_addr;
26650 /* The source function id. */
26653 uint8_t tunnel_type;
26655 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
26657 /* Virtual eXtensible Local Area Network (VXLAN) */
26658 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
26660 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26661 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
26663 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
26664 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
26667 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
26669 /* Generic Network Virtualization Encapsulation (Geneve) */
26670 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
26672 /* Multi-Protocol Label Switching (MPLS) */
26673 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
26675 /* Stateless Transport Tunnel (STT) */
26676 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
26678 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26679 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
26681 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26682 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
26684 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26685 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
26687 /* Use fixed layer 2 ether type of 0xFFFF */
26688 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
26690 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26691 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
26693 /* Any tunneled traffic */
26694 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
26696 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
26697 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
26698 uint8_t unused_0[5];
26701 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
26702 struct hwrm_cfa_redirect_tunnel_type_info_output {
26703 /* The specific error status for the command. */
26704 uint16_t error_code;
26705 /* The HWRM command request type. */
26707 /* The sequence ID from the original command. */
26709 /* The length of the response data in number of bytes. */
26711 /* The destination function id, to whom the traffic is redirected. */
26713 uint8_t unused_0[5];
26715 * This field is used in Output records to indicate that the output
26716 * is completely written to RAM. This field should be read as '1'
26717 * to indicate that the output has been completely written.
26718 * When writing a command completion or response to an internal processor,
26719 * the order of writes has to be such that this field is written last.
26724 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
26725 struct hwrm_vxlan_ipv4_hdr {
26726 /* IPv4 version and header length. */
26728 /* IPv4 header length */
26729 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
26730 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
26732 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
26733 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
26734 /* IPv4 type of service. */
26736 /* IPv4 identification. */
26738 /* IPv4 flags and offset. */
26739 uint16_t flags_frag_offset;
26742 /* IPv4 protocol. */
26744 /* IPv4 source address. */
26745 uint32_t src_ip_addr;
26746 /* IPv4 destination address. */
26747 uint32_t dest_ip_addr;
26750 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
26751 struct hwrm_vxlan_ipv6_hdr {
26752 /* IPv6 version, traffic class and flow label. */
26753 uint32_t ver_tc_flow_label;
26754 /* IPv6 version shift */
26755 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
26757 /* IPv6 version mask */
26758 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
26759 UINT32_C(0xf0000000)
26760 /* IPv6 TC shift */
26761 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
26764 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
26765 UINT32_C(0xff00000)
26766 /* IPv6 flow label shift */
26767 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
26769 /* IPv6 flow label mask */
26770 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
26772 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
26773 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
26774 /* IPv6 payload length. */
26775 uint16_t payload_len;
26776 /* IPv6 next header. */
26780 /* IPv6 source address. */
26781 uint32_t src_ip_addr[4];
26782 /* IPv6 destination address. */
26783 uint32_t dest_ip_addr[4];
26786 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
26787 struct hwrm_cfa_encap_data_vxlan {
26788 /* Source MAC address. */
26789 uint8_t src_mac_addr[6];
26792 /* Destination MAC address. */
26793 uint8_t dst_mac_addr[6];
26794 /* Number of VLAN tags. */
26795 uint8_t num_vlan_tags;
26798 /* Outer VLAN TPID. */
26799 uint16_t ovlan_tpid;
26800 /* Outer VLAN TCI. */
26801 uint16_t ovlan_tci;
26802 /* Inner VLAN TPID. */
26803 uint16_t ivlan_tpid;
26804 /* Inner VLAN TCI. */
26805 uint16_t ivlan_tci;
26806 /* L3 header fields. */
26808 /* IP version mask. */
26809 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
26810 /* IP version 4. */
26811 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
26812 /* IP version 6. */
26813 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
26814 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
26815 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
26816 /* UDP source port. */
26818 /* UDP destination port. */
26820 /* VXLAN Network Identifier. */
26822 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
26823 uint8_t hdr_rsvd0[3];
26824 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
26826 /* VXLAN header flags field. */
26831 /*******************************
26832 * hwrm_cfa_encap_record_alloc *
26833 *******************************/
26836 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
26837 struct hwrm_cfa_encap_record_alloc_input {
26838 /* The HWRM command request type. */
26841 * The completion ring to send the completion event on. This should
26842 * be the NQ ID returned from the `nq_alloc` HWRM command.
26844 uint16_t cmpl_ring;
26846 * The sequence ID is used by the driver for tracking multiple
26847 * commands. This ID is treated as opaque data by the firmware and
26848 * the value is returned in the `hwrm_resp_hdr` upon completion.
26852 * The target ID of the command:
26853 * * 0x0-0xFFF8 - The function ID
26854 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26855 * * 0xFFFD - Reserved for user-space HWRM interface
26858 uint16_t target_id;
26860 * A physical address pointer pointing to a host buffer that the
26861 * command's response data will be written. This can be either a host
26862 * physical address (HPA) or a guest physical address (GPA) and must
26863 * point to a physically contiguous block of memory.
26865 uint64_t resp_addr;
26867 /* Setting of this flag indicates the applicability to the loopback path. */
26868 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
26871 * Setting of this flag indicates this encap record is external encap record.
26872 * Resetting of this flag indicates this flag is internal encap record and
26873 * this is the default setting.
26875 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
26877 /* Encapsulation Type. */
26878 uint8_t encap_type;
26879 /* Virtual eXtensible Local Area Network (VXLAN) */
26880 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
26882 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
26883 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
26885 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
26886 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
26889 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
26891 /* Generic Network Virtualization Encapsulation (Geneve) */
26892 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
26894 /* Multi-Protocol Label Switching (MPLS) */
26895 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
26898 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
26900 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
26901 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
26903 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
26904 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
26906 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
26907 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
26909 /* Use fixed layer 2 ether type of 0xFFFF */
26910 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
26912 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
26913 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
26915 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
26916 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
26917 uint8_t unused_0[3];
26918 /* This value is encap data used for the given encap type. */
26919 uint32_t encap_data[20];
26922 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
26923 struct hwrm_cfa_encap_record_alloc_output {
26924 /* The specific error status for the command. */
26925 uint16_t error_code;
26926 /* The HWRM command request type. */
26928 /* The sequence ID from the original command. */
26930 /* The length of the response data in number of bytes. */
26932 /* This value is an opaque id into CFA data structures. */
26933 uint32_t encap_record_id;
26934 uint8_t unused_0[3];
26936 * This field is used in Output records to indicate that the output
26937 * is completely written to RAM. This field should be read as '1'
26938 * to indicate that the output has been completely written.
26939 * When writing a command completion or response to an internal processor,
26940 * the order of writes has to be such that this field is written last.
26945 /******************************
26946 * hwrm_cfa_encap_record_free *
26947 ******************************/
26950 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
26951 struct hwrm_cfa_encap_record_free_input {
26952 /* The HWRM command request type. */
26955 * The completion ring to send the completion event on. This should
26956 * be the NQ ID returned from the `nq_alloc` HWRM command.
26958 uint16_t cmpl_ring;
26960 * The sequence ID is used by the driver for tracking multiple
26961 * commands. This ID is treated as opaque data by the firmware and
26962 * the value is returned in the `hwrm_resp_hdr` upon completion.
26966 * The target ID of the command:
26967 * * 0x0-0xFFF8 - The function ID
26968 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26969 * * 0xFFFD - Reserved for user-space HWRM interface
26972 uint16_t target_id;
26974 * A physical address pointer pointing to a host buffer that the
26975 * command's response data will be written. This can be either a host
26976 * physical address (HPA) or a guest physical address (GPA) and must
26977 * point to a physically contiguous block of memory.
26979 uint64_t resp_addr;
26980 /* This value is an opaque id into CFA data structures. */
26981 uint32_t encap_record_id;
26982 uint8_t unused_0[4];
26985 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
26986 struct hwrm_cfa_encap_record_free_output {
26987 /* The specific error status for the command. */
26988 uint16_t error_code;
26989 /* The HWRM command request type. */
26991 /* The sequence ID from the original command. */
26993 /* The length of the response data in number of bytes. */
26995 uint8_t unused_0[7];
26997 * This field is used in Output records to indicate that the output
26998 * is completely written to RAM. This field should be read as '1'
26999 * to indicate that the output has been completely written.
27000 * When writing a command completion or response to an internal processor,
27001 * the order of writes has to be such that this field is written last.
27006 /********************************
27007 * hwrm_cfa_ntuple_filter_alloc *
27008 ********************************/
27011 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
27012 struct hwrm_cfa_ntuple_filter_alloc_input {
27013 /* The HWRM command request type. */
27016 * The completion ring to send the completion event on. This should
27017 * be the NQ ID returned from the `nq_alloc` HWRM command.
27019 uint16_t cmpl_ring;
27021 * The sequence ID is used by the driver for tracking multiple
27022 * commands. This ID is treated as opaque data by the firmware and
27023 * the value is returned in the `hwrm_resp_hdr` upon completion.
27027 * The target ID of the command:
27028 * * 0x0-0xFFF8 - The function ID
27029 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27030 * * 0xFFFD - Reserved for user-space HWRM interface
27033 uint16_t target_id;
27035 * A physical address pointer pointing to a host buffer that the
27036 * command's response data will be written. This can be either a host
27037 * physical address (HPA) or a guest physical address (GPA) and must
27038 * point to a physically contiguous block of memory.
27040 uint64_t resp_addr;
27042 /* Setting of this flag indicates the applicability to the loopback path. */
27043 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
27046 * Setting of this flag indicates drop action. If this flag is not set,
27047 * then it should be considered accept action.
27049 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
27052 * Setting of this flag indicates that a meter is expected to be attached
27053 * to this flow. This hint can be used when choosing the action record
27054 * format required for the flow.
27056 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
27059 * Setting of this flag indicates that the dst_id field contains function ID.
27060 * If this is not set it indicates dest_id is VNIC or VPORT.
27062 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
27065 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
27066 * If this is not set it indicates no specific arp opcode matching.
27068 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
27071 * Setting of this flag indicates that the dst_id field contains RFS ring
27072 * table index. If this is not set it indicates dst_id is VNIC or VPORT
27073 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
27076 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
27080 * This bit must be '1' for the l2_filter_id field to be
27083 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
27086 * This bit must be '1' for the ethertype field to be
27089 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
27092 * This bit must be '1' for the tunnel_type field to be
27095 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27098 * This bit must be '1' for the src_macaddr field to be
27101 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
27104 * This bit must be '1' for the ipaddr_type field to be
27107 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27110 * This bit must be '1' for the src_ipaddr field to be
27113 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27116 * This bit must be '1' for the src_ipaddr_mask field to be
27119 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
27122 * This bit must be '1' for the dst_ipaddr field to be
27125 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
27128 * This bit must be '1' for the dst_ipaddr_mask field to be
27131 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
27134 * This bit must be '1' for the ip_protocol field to be
27137 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27140 * This bit must be '1' for the src_port field to be
27143 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
27146 * This bit must be '1' for the src_port_mask field to be
27149 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
27152 * This bit must be '1' for the dst_port field to be
27155 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
27158 * This bit must be '1' for the dst_port_mask field to be
27161 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
27164 * This bit must be '1' for the pri_hint field to be
27167 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
27170 * This bit must be '1' for the ntuple_filter_id field to be
27173 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
27176 * This bit must be '1' for the dst_id field to be
27179 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
27182 * This bit must be '1' for the mirror_vnic_id field to be
27185 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27188 * This bit must be '1' for the dst_macaddr field to be
27191 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
27193 /* This flag is deprecated. */
27194 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
27197 * This value identifies a set of CFA data structures used for an L2
27200 uint64_t l2_filter_id;
27202 * This value indicates the source MAC address in
27203 * the Ethernet header.
27205 uint8_t src_macaddr[6];
27206 /* This value indicates the ethertype in the Ethernet header. */
27207 uint16_t ethertype;
27209 * This value indicates the type of IP address.
27212 * All others are invalid.
27214 uint8_t ip_addr_type;
27216 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
27219 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
27222 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
27224 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
27225 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
27227 * The value of protocol filed in IP header.
27228 * Applies to UDP and TCP traffic.
27232 uint8_t ip_protocol;
27234 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
27237 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
27240 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
27242 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
27243 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
27245 * If set, this value shall represent the
27246 * Logical VNIC ID of the destination VNIC for the RX
27247 * path and network port id of the destination port for
27252 * Logical VNIC ID of the VNIC where traffic is
27255 uint16_t mirror_vnic_id;
27257 * This value indicates the tunnel type for this filter.
27258 * If this field is not specified, then the filter shall
27259 * apply to both non-tunneled and tunneled packets.
27260 * If this field conflicts with the tunnel_type specified
27261 * in the l2_filter_id, then the HWRM shall return an
27262 * error for this command.
27264 uint8_t tunnel_type;
27266 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27268 /* Virtual eXtensible Local Area Network (VXLAN) */
27269 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27271 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27272 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27274 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27275 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27278 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27280 /* Generic Network Virtualization Encapsulation (Geneve) */
27281 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27283 /* Multi-Protocol Label Switching (MPLS) */
27284 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27286 /* Stateless Transport Tunnel (STT) */
27287 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
27289 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27290 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27292 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27293 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27295 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27296 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27298 /* Use fixed layer 2 ether type of 0xFFFF */
27299 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27301 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27302 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27304 /* Any tunneled traffic */
27305 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27307 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27308 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27310 * This hint is provided to help in placing
27311 * the filter in the filter table.
27314 /* No preference */
27315 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
27317 /* Above the given filter */
27318 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
27320 /* Below the given filter */
27321 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
27323 /* As high as possible */
27324 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
27326 /* As low as possible */
27327 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
27329 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
27330 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
27332 * The value of source IP address to be used in filtering.
27333 * For IPv4, first four bytes represent the IP address.
27335 uint32_t src_ipaddr[4];
27337 * The value of source IP address mask to be used in
27339 * For IPv4, first four bytes represent the IP address mask.
27341 uint32_t src_ipaddr_mask[4];
27343 * The value of destination IP address to be used in filtering.
27344 * For IPv4, first four bytes represent the IP address.
27346 uint32_t dst_ipaddr[4];
27348 * The value of destination IP address mask to be used in
27350 * For IPv4, first four bytes represent the IP address mask.
27352 uint32_t dst_ipaddr_mask[4];
27354 * The value of source port to be used in filtering.
27355 * Applies to UDP and TCP traffic.
27359 * The value of source port mask to be used in filtering.
27360 * Applies to UDP and TCP traffic.
27362 uint16_t src_port_mask;
27364 * The value of destination port to be used in filtering.
27365 * Applies to UDP and TCP traffic.
27369 * The value of destination port mask to be used in
27371 * Applies to UDP and TCP traffic.
27373 uint16_t dst_port_mask;
27375 * This is the ID of the filter that goes along with
27378 uint64_t ntuple_filter_id_hint;
27381 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
27382 struct hwrm_cfa_ntuple_filter_alloc_output {
27383 /* The specific error status for the command. */
27384 uint16_t error_code;
27385 /* The HWRM command request type. */
27387 /* The sequence ID from the original command. */
27389 /* The length of the response data in number of bytes. */
27391 /* This value is an opaque id into CFA data structures. */
27392 uint64_t ntuple_filter_id;
27394 * The flow id value in bit 0-29 is the actual ID of the flow
27395 * associated with this filter and it shall be used to match
27396 * and associate the flow identifier returned in completion
27397 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
27398 * shall indicate no valid flow id.
27401 /* Indicate the flow id value. */
27402 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
27403 UINT32_C(0x3fffffff)
27404 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
27405 /* Indicate type of the flow. */
27406 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
27407 UINT32_C(0x40000000)
27409 * If this bit set to 0, then it indicates that the flow is
27412 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
27413 (UINT32_C(0x0) << 30)
27415 * If this bit is set to 1, then it indicates that the flow is
27418 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
27419 (UINT32_C(0x1) << 30)
27420 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
27421 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
27422 /* Indicate the flow direction. */
27423 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
27424 UINT32_C(0x80000000)
27425 /* If this bit set to 0, then it indicates rx flow. */
27426 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
27427 (UINT32_C(0x0) << 31)
27428 /* If this bit is set to 1, then it indicates that tx flow. */
27429 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
27430 (UINT32_C(0x1) << 31)
27431 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
27432 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
27433 uint8_t unused_0[3];
27435 * This field is used in Output records to indicate that the output
27436 * is completely written to RAM. This field should be read as '1'
27437 * to indicate that the output has been completely written.
27438 * When writing a command completion or response to an internal processor,
27439 * the order of writes has to be such that this field is written last.
27444 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
27445 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
27447 * command specific error codes that goes to
27448 * the cmd_err field in Common HWRM Error Response.
27451 /* Unknown error */
27452 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
27454 /* Unable to complete operation due to conflict with Rx Mask VLAN */
27455 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
27457 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
27458 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
27459 uint8_t unused_0[7];
27462 /*******************************
27463 * hwrm_cfa_ntuple_filter_free *
27464 *******************************/
27467 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
27468 struct hwrm_cfa_ntuple_filter_free_input {
27469 /* The HWRM command request type. */
27472 * The completion ring to send the completion event on. This should
27473 * be the NQ ID returned from the `nq_alloc` HWRM command.
27475 uint16_t cmpl_ring;
27477 * The sequence ID is used by the driver for tracking multiple
27478 * commands. This ID is treated as opaque data by the firmware and
27479 * the value is returned in the `hwrm_resp_hdr` upon completion.
27483 * The target ID of the command:
27484 * * 0x0-0xFFF8 - The function ID
27485 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27486 * * 0xFFFD - Reserved for user-space HWRM interface
27489 uint16_t target_id;
27491 * A physical address pointer pointing to a host buffer that the
27492 * command's response data will be written. This can be either a host
27493 * physical address (HPA) or a guest physical address (GPA) and must
27494 * point to a physically contiguous block of memory.
27496 uint64_t resp_addr;
27497 /* This value is an opaque id into CFA data structures. */
27498 uint64_t ntuple_filter_id;
27501 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
27502 struct hwrm_cfa_ntuple_filter_free_output {
27503 /* The specific error status for the command. */
27504 uint16_t error_code;
27505 /* The HWRM command request type. */
27507 /* The sequence ID from the original command. */
27509 /* The length of the response data in number of bytes. */
27511 uint8_t unused_0[7];
27513 * This field is used in Output records to indicate that the output
27514 * is completely written to RAM. This field should be read as '1'
27515 * to indicate that the output has been completely written.
27516 * When writing a command completion or response to an internal processor,
27517 * the order of writes has to be such that this field is written last.
27522 /******************************
27523 * hwrm_cfa_ntuple_filter_cfg *
27524 ******************************/
27527 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
27528 struct hwrm_cfa_ntuple_filter_cfg_input {
27529 /* The HWRM command request type. */
27532 * The completion ring to send the completion event on. This should
27533 * be the NQ ID returned from the `nq_alloc` HWRM command.
27535 uint16_t cmpl_ring;
27537 * The sequence ID is used by the driver for tracking multiple
27538 * commands. This ID is treated as opaque data by the firmware and
27539 * the value is returned in the `hwrm_resp_hdr` upon completion.
27543 * The target ID of the command:
27544 * * 0x0-0xFFF8 - The function ID
27545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27546 * * 0xFFFD - Reserved for user-space HWRM interface
27549 uint16_t target_id;
27551 * A physical address pointer pointing to a host buffer that the
27552 * command's response data will be written. This can be either a host
27553 * physical address (HPA) or a guest physical address (GPA) and must
27554 * point to a physically contiguous block of memory.
27556 uint64_t resp_addr;
27559 * This bit must be '1' for the new_dst_id field to be
27562 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
27565 * This bit must be '1' for the new_mirror_vnic_id field to be
27568 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
27571 * This bit must be '1' for the new_meter_instance_id field to be
27574 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
27578 * Setting this bit to 1 indicates that dest_id field contains FID.
27579 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
27581 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
27584 * Setting of this flag indicates that the new_dst_id field contains
27585 * RFS ring table index. If this is not set it indicates new_dst_id is
27586 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
27587 * can’t be set at the same time.
27589 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
27591 /* This value is an opaque id into CFA data structures. */
27592 uint64_t ntuple_filter_id;
27594 * If set, this value shall represent the new
27595 * Logical VNIC ID of the destination VNIC for the RX
27596 * path and new network port id of the destination port for
27599 uint32_t new_dst_id;
27601 * New Logical VNIC ID of the VNIC where traffic is
27604 uint32_t new_mirror_vnic_id;
27606 * New meter to attach to the flow. Specifying the
27607 * invalid instance ID is used to remove any existing
27608 * meter from the flow.
27610 uint16_t new_meter_instance_id;
27612 * A value of 0xfff is considered invalid and implies the
27613 * instance is not configured.
27615 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
27617 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
27618 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
27619 uint8_t unused_1[6];
27622 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
27623 struct hwrm_cfa_ntuple_filter_cfg_output {
27624 /* The specific error status for the command. */
27625 uint16_t error_code;
27626 /* The HWRM command request type. */
27628 /* The sequence ID from the original command. */
27630 /* The length of the response data in number of bytes. */
27632 uint8_t unused_0[7];
27634 * This field is used in Output records to indicate that the output
27635 * is completely written to RAM. This field should be read as '1'
27636 * to indicate that the output has been completely written.
27637 * When writing a command completion or response to an internal processor,
27638 * the order of writes has to be such that this field is written last.
27643 /**************************
27644 * hwrm_cfa_em_flow_alloc *
27645 **************************/
27648 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
27649 struct hwrm_cfa_em_flow_alloc_input {
27650 /* The HWRM command request type. */
27653 * The completion ring to send the completion event on. This should
27654 * be the NQ ID returned from the `nq_alloc` HWRM command.
27656 uint16_t cmpl_ring;
27658 * The sequence ID is used by the driver for tracking multiple
27659 * commands. This ID is treated as opaque data by the firmware and
27660 * the value is returned in the `hwrm_resp_hdr` upon completion.
27664 * The target ID of the command:
27665 * * 0x0-0xFFF8 - The function ID
27666 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27667 * * 0xFFFD - Reserved for user-space HWRM interface
27670 uint16_t target_id;
27672 * A physical address pointer pointing to a host buffer that the
27673 * command's response data will be written. This can be either a host
27674 * physical address (HPA) or a guest physical address (GPA) and must
27675 * point to a physically contiguous block of memory.
27677 uint64_t resp_addr;
27680 * Enumeration denoting the RX, TX type of the resource.
27681 * This enumeration is used for resources that are similar for both
27682 * TX and RX paths of the chip.
27684 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
27686 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
27688 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
27689 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
27690 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
27692 * Setting of this flag indicates enabling of a byte counter for a given
27695 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
27697 * Setting of this flag indicates enabling of a packet counter for a given
27700 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
27701 /* Setting of this flag indicates de-capsulation action for the given flow. */
27702 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
27703 /* Setting of this flag indicates encapsulation action for the given flow. */
27704 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
27706 * Setting of this flag indicates drop action. If this flag is not set,
27707 * then it should be considered accept action.
27709 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
27711 * Setting of this flag indicates that a meter is expected to be attached
27712 * to this flow. This hint can be used when choosing the action record
27713 * format required for the flow.
27715 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
27718 * This bit must be '1' for the l2_filter_id field to be
27721 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
27724 * This bit must be '1' for the tunnel_type field to be
27727 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
27730 * This bit must be '1' for the tunnel_id field to be
27733 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
27736 * This bit must be '1' for the src_macaddr field to be
27739 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
27742 * This bit must be '1' for the dst_macaddr field to be
27745 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
27748 * This bit must be '1' for the ovlan_vid field to be
27751 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
27754 * This bit must be '1' for the ivlan_vid field to be
27757 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
27760 * This bit must be '1' for the ethertype field to be
27763 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
27766 * This bit must be '1' for the src_ipaddr field to be
27769 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
27772 * This bit must be '1' for the dst_ipaddr field to be
27775 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
27778 * This bit must be '1' for the ipaddr_type field to be
27781 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
27784 * This bit must be '1' for the ip_protocol field to be
27787 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
27790 * This bit must be '1' for the src_port field to be
27793 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
27796 * This bit must be '1' for the dst_port field to be
27799 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
27802 * This bit must be '1' for the dst_id field to be
27805 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
27808 * This bit must be '1' for the mirror_vnic_id field to be
27811 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
27814 * This bit must be '1' for the encap_record_id field to be
27817 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
27820 * This bit must be '1' for the meter_instance_id field to be
27823 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
27826 * This value identifies a set of CFA data structures used for an L2
27829 uint64_t l2_filter_id;
27831 uint8_t tunnel_type;
27833 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
27835 /* Virtual eXtensible Local Area Network (VXLAN) */
27836 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
27838 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
27839 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
27841 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
27842 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
27845 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
27847 /* Generic Network Virtualization Encapsulation (Geneve) */
27848 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
27850 /* Multi-Protocol Label Switching (MPLS) */
27851 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
27853 /* Stateless Transport Tunnel (STT) */
27854 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
27856 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
27857 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
27859 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
27860 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
27862 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
27863 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
27865 /* Use fixed layer 2 ether type of 0xFFFF */
27866 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
27868 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
27869 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
27871 /* Any tunneled traffic */
27872 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
27874 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
27875 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
27876 uint8_t unused_0[3];
27878 * Tunnel identifier.
27879 * Virtual Network Identifier (VNI). Only valid with
27880 * tunnel_types VXLAN, NVGRE, and Geneve.
27881 * Only lower 24-bits of VNI field are used
27882 * in setting up the filter.
27884 uint32_t tunnel_id;
27886 * This value indicates the source MAC address in
27887 * the Ethernet header.
27889 uint8_t src_macaddr[6];
27890 /* The meter instance to attach to the flow. */
27891 uint16_t meter_instance_id;
27893 * A value of 0xfff is considered invalid and implies the
27894 * instance is not configured.
27896 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
27898 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
27899 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
27901 * This value indicates the destination MAC address in
27902 * the Ethernet header.
27904 uint8_t dst_macaddr[6];
27906 * This value indicates the VLAN ID of the outer VLAN tag
27907 * in the Ethernet header.
27909 uint16_t ovlan_vid;
27911 * This value indicates the VLAN ID of the inner VLAN tag
27912 * in the Ethernet header.
27914 uint16_t ivlan_vid;
27915 /* This value indicates the ethertype in the Ethernet header. */
27916 uint16_t ethertype;
27918 * This value indicates the type of IP address.
27921 * All others are invalid.
27923 uint8_t ip_addr_type;
27925 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
27927 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
27929 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
27930 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
27931 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
27933 * The value of protocol filed in IP header.
27934 * Applies to UDP and TCP traffic.
27938 uint8_t ip_protocol;
27940 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
27942 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
27944 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
27945 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
27946 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
27947 uint8_t unused_1[2];
27949 * The value of source IP address to be used in filtering.
27950 * For IPv4, first four bytes represent the IP address.
27952 uint32_t src_ipaddr[4];
27954 * big_endian = True
27955 * The value of destination IP address to be used in filtering.
27956 * For IPv4, first four bytes represent the IP address.
27958 uint32_t dst_ipaddr[4];
27960 * The value of source port to be used in filtering.
27961 * Applies to UDP and TCP traffic.
27965 * The value of destination port to be used in filtering.
27966 * Applies to UDP and TCP traffic.
27970 * If set, this value shall represent the
27971 * Logical VNIC ID of the destination VNIC for the RX
27972 * path and network port id of the destination port for
27977 * Logical VNIC ID of the VNIC where traffic is
27980 uint16_t mirror_vnic_id;
27981 /* Logical ID of the encapsulation record. */
27982 uint32_t encap_record_id;
27983 uint8_t unused_2[4];
27986 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
27987 struct hwrm_cfa_em_flow_alloc_output {
27988 /* The specific error status for the command. */
27989 uint16_t error_code;
27990 /* The HWRM command request type. */
27992 /* The sequence ID from the original command. */
27994 /* The length of the response data in number of bytes. */
27996 /* This value is an opaque id into CFA data structures. */
27997 uint64_t em_filter_id;
27999 * The flow id value in bit 0-29 is the actual ID of the flow
28000 * associated with this filter and it shall be used to match
28001 * and associate the flow identifier returned in completion
28002 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
28003 * shall indicate no valid flow id.
28006 /* Indicate the flow id value. */
28007 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
28008 UINT32_C(0x3fffffff)
28009 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
28010 /* Indicate type of the flow. */
28011 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
28012 UINT32_C(0x40000000)
28014 * If this bit set to 0, then it indicates that the flow is
28017 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
28018 (UINT32_C(0x0) << 30)
28020 * If this bit is set to 1, then it indicates that the flow is
28023 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
28024 (UINT32_C(0x1) << 30)
28025 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
28026 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
28027 /* Indicate the flow direction. */
28028 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
28029 UINT32_C(0x80000000)
28030 /* If this bit set to 0, then it indicates rx flow. */
28031 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
28032 (UINT32_C(0x0) << 31)
28033 /* If this bit is set to 1, then it indicates that tx flow. */
28034 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
28035 (UINT32_C(0x1) << 31)
28036 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
28037 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
28038 uint8_t unused_0[3];
28040 * This field is used in Output records to indicate that the output
28041 * is completely written to RAM. This field should be read as '1'
28042 * to indicate that the output has been completely written.
28043 * When writing a command completion or response to an internal processor,
28044 * the order of writes has to be such that this field is written last.
28049 /*************************
28050 * hwrm_cfa_em_flow_free *
28051 *************************/
28054 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
28055 struct hwrm_cfa_em_flow_free_input {
28056 /* The HWRM command request type. */
28059 * The completion ring to send the completion event on. This should
28060 * be the NQ ID returned from the `nq_alloc` HWRM command.
28062 uint16_t cmpl_ring;
28064 * The sequence ID is used by the driver for tracking multiple
28065 * commands. This ID is treated as opaque data by the firmware and
28066 * the value is returned in the `hwrm_resp_hdr` upon completion.
28070 * The target ID of the command:
28071 * * 0x0-0xFFF8 - The function ID
28072 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28073 * * 0xFFFD - Reserved for user-space HWRM interface
28076 uint16_t target_id;
28078 * A physical address pointer pointing to a host buffer that the
28079 * command's response data will be written. This can be either a host
28080 * physical address (HPA) or a guest physical address (GPA) and must
28081 * point to a physically contiguous block of memory.
28083 uint64_t resp_addr;
28084 /* This value is an opaque id into CFA data structures. */
28085 uint64_t em_filter_id;
28088 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
28089 struct hwrm_cfa_em_flow_free_output {
28090 /* The specific error status for the command. */
28091 uint16_t error_code;
28092 /* The HWRM command request type. */
28094 /* The sequence ID from the original command. */
28096 /* The length of the response data in number of bytes. */
28098 uint8_t unused_0[7];
28100 * This field is used in Output records to indicate that the output
28101 * is completely written to RAM. This field should be read as '1'
28102 * to indicate that the output has been completely written.
28103 * When writing a command completion or response to an internal processor,
28104 * the order of writes has to be such that this field is written last.
28109 /************************
28110 * hwrm_cfa_meter_qcaps *
28111 ************************/
28114 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
28115 struct hwrm_cfa_meter_qcaps_input {
28116 /* The HWRM command request type. */
28119 * The completion ring to send the completion event on. This should
28120 * be the NQ ID returned from the `nq_alloc` HWRM command.
28122 uint16_t cmpl_ring;
28124 * The sequence ID is used by the driver for tracking multiple
28125 * commands. This ID is treated as opaque data by the firmware and
28126 * the value is returned in the `hwrm_resp_hdr` upon completion.
28130 * The target ID of the command:
28131 * * 0x0-0xFFF8 - The function ID
28132 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28133 * * 0xFFFD - Reserved for user-space HWRM interface
28136 uint16_t target_id;
28138 * A physical address pointer pointing to a host buffer that the
28139 * command's response data will be written. This can be either a host
28140 * physical address (HPA) or a guest physical address (GPA) and must
28141 * point to a physically contiguous block of memory.
28143 uint64_t resp_addr;
28146 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
28147 struct hwrm_cfa_meter_qcaps_output {
28148 /* The specific error status for the command. */
28149 uint16_t error_code;
28150 /* The HWRM command request type. */
28152 /* The sequence ID from the original command. */
28154 /* The length of the response data in number of bytes. */
28158 * Enumeration denoting the clock at which the Meter is running with.
28159 * This enumeration is used for resources that are similar for both
28160 * TX and RX paths of the chip.
28162 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
28163 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
28165 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
28167 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
28168 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
28169 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
28170 uint8_t unused_0[4];
28172 * The minimum guaranteed number of tx meter profiles supported
28173 * for this function.
28175 uint16_t min_tx_profile;
28177 * The maximum non-guaranteed number of tx meter profiles supported
28178 * for this function.
28180 uint16_t max_tx_profile;
28182 * The minimum guaranteed number of rx meter profiles supported
28183 * for this function.
28185 uint16_t min_rx_profile;
28187 * The maximum non-guaranteed number of rx meter profiles supported
28188 * for this function.
28190 uint16_t max_rx_profile;
28192 * The minimum guaranteed number of tx meter instances supported
28193 * for this function.
28195 uint16_t min_tx_instance;
28197 * The maximum non-guaranteed number of tx meter instances supported
28198 * for this function.
28200 uint16_t max_tx_instance;
28202 * The minimum guaranteed number of rx meter instances supported
28203 * for this function.
28205 uint16_t min_rx_instance;
28207 * The maximum non-guaranteed number of rx meter instances supported
28208 * for this function.
28210 uint16_t max_rx_instance;
28211 uint8_t unused_1[7];
28213 * This field is used in Output records to indicate that the output
28214 * is completely written to RAM. This field should be read as '1'
28215 * to indicate that the output has been completely written.
28216 * When writing a command completion or response to an internal processor,
28217 * the order of writes has to be such that this field is written last.
28222 /********************************
28223 * hwrm_cfa_meter_profile_alloc *
28224 ********************************/
28227 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
28228 struct hwrm_cfa_meter_profile_alloc_input {
28229 /* The HWRM command request type. */
28232 * The completion ring to send the completion event on. This should
28233 * be the NQ ID returned from the `nq_alloc` HWRM command.
28235 uint16_t cmpl_ring;
28237 * The sequence ID is used by the driver for tracking multiple
28238 * commands. This ID is treated as opaque data by the firmware and
28239 * the value is returned in the `hwrm_resp_hdr` upon completion.
28243 * The target ID of the command:
28244 * * 0x0-0xFFF8 - The function ID
28245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28246 * * 0xFFFD - Reserved for user-space HWRM interface
28249 uint16_t target_id;
28251 * A physical address pointer pointing to a host buffer that the
28252 * command's response data will be written. This can be either a host
28253 * physical address (HPA) or a guest physical address (GPA) and must
28254 * point to a physically contiguous block of memory.
28256 uint64_t resp_addr;
28259 * Enumeration denoting the RX, TX type of the resource.
28260 * This enumeration is used for resources that are similar for both
28261 * TX and RX paths of the chip.
28263 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
28265 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
28268 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
28270 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
28271 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
28272 /* The meter algorithm type. */
28273 uint8_t meter_type;
28274 /* RFC 2697 (srTCM) */
28275 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
28277 /* RFC 2698 (trTCM) */
28278 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
28280 /* RFC 4115 (trTCM) */
28281 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
28283 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
28284 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
28286 * This field is reserved for the future use.
28287 * It shall be set to 0.
28289 uint16_t reserved1;
28291 * This field is reserved for the future use.
28292 * It shall be set to 0.
28294 uint32_t reserved2;
28295 /* A meter rate specified in bytes-per-second. */
28296 uint32_t commit_rate;
28297 /* The bandwidth value. */
28298 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
28299 UINT32_C(0xfffffff)
28300 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
28302 /* The granularity of the value (bits or bytes). */
28303 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
28304 UINT32_C(0x10000000)
28305 /* Value is in bits. */
28306 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
28307 (UINT32_C(0x0) << 28)
28308 /* Value is in bytes. */
28309 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
28310 (UINT32_C(0x1) << 28)
28311 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
28312 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
28313 /* bw_value_unit is 3 b */
28314 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
28315 UINT32_C(0xe0000000)
28316 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
28318 /* Value is in Mb or MB (base 10). */
28319 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
28320 (UINT32_C(0x0) << 29)
28321 /* Value is in Kb or KB (base 10). */
28322 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
28323 (UINT32_C(0x2) << 29)
28324 /* Value is in bits or bytes. */
28325 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
28326 (UINT32_C(0x4) << 29)
28327 /* Value is in Gb or GB (base 10). */
28328 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
28329 (UINT32_C(0x6) << 29)
28330 /* Value is in 1/100th of a percentage of total bandwidth. */
28331 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
28332 (UINT32_C(0x1) << 29)
28334 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
28335 (UINT32_C(0x7) << 29)
28336 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
28337 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
28338 /* A meter burst size specified in bytes. */
28339 uint32_t commit_burst;
28340 /* The bandwidth value. */
28341 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
28342 UINT32_C(0xfffffff)
28343 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
28345 /* The granularity of the value (bits or bytes). */
28346 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
28347 UINT32_C(0x10000000)
28348 /* Value is in bits. */
28349 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
28350 (UINT32_C(0x0) << 28)
28351 /* Value is in bytes. */
28352 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
28353 (UINT32_C(0x1) << 28)
28354 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
28355 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
28356 /* bw_value_unit is 3 b */
28357 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
28358 UINT32_C(0xe0000000)
28359 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
28361 /* Value is in Mb or MB (base 10). */
28362 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
28363 (UINT32_C(0x0) << 29)
28364 /* Value is in Kb or KB (base 10). */
28365 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
28366 (UINT32_C(0x2) << 29)
28367 /* Value is in bits or bytes. */
28368 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
28369 (UINT32_C(0x4) << 29)
28370 /* Value is in Gb or GB (base 10). */
28371 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
28372 (UINT32_C(0x6) << 29)
28373 /* Value is in 1/100th of a percentage of total bandwidth. */
28374 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
28375 (UINT32_C(0x1) << 29)
28376 /* Invalid value */
28377 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
28378 (UINT32_C(0x7) << 29)
28379 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
28380 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
28381 /* A meter rate specified in bytes-per-second. */
28382 uint32_t excess_peak_rate;
28383 /* The bandwidth value. */
28384 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
28385 UINT32_C(0xfffffff)
28386 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
28388 /* The granularity of the value (bits or bytes). */
28389 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
28390 UINT32_C(0x10000000)
28391 /* Value is in bits. */
28392 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
28393 (UINT32_C(0x0) << 28)
28394 /* Value is in bytes. */
28395 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
28396 (UINT32_C(0x1) << 28)
28397 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
28398 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
28399 /* bw_value_unit is 3 b */
28400 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
28401 UINT32_C(0xe0000000)
28402 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
28404 /* Value is in Mb or MB (base 10). */
28405 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
28406 (UINT32_C(0x0) << 29)
28407 /* Value is in Kb or KB (base 10). */
28408 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
28409 (UINT32_C(0x2) << 29)
28410 /* Value is in bits or bytes. */
28411 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
28412 (UINT32_C(0x4) << 29)
28413 /* Value is in Gb or GB (base 10). */
28414 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
28415 (UINT32_C(0x6) << 29)
28416 /* Value is in 1/100th of a percentage of total bandwidth. */
28417 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
28418 (UINT32_C(0x1) << 29)
28420 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
28421 (UINT32_C(0x7) << 29)
28422 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
28423 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
28424 /* A meter burst size specified in bytes. */
28425 uint32_t excess_peak_burst;
28426 /* The bandwidth value. */
28427 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
28428 UINT32_C(0xfffffff)
28429 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
28431 /* The granularity of the value (bits or bytes). */
28432 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
28433 UINT32_C(0x10000000)
28434 /* Value is in bits. */
28435 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
28436 (UINT32_C(0x0) << 28)
28437 /* Value is in bytes. */
28438 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
28439 (UINT32_C(0x1) << 28)
28440 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
28441 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
28442 /* bw_value_unit is 3 b */
28443 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
28444 UINT32_C(0xe0000000)
28445 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
28447 /* Value is in Mb or MB (base 10). */
28448 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
28449 (UINT32_C(0x0) << 29)
28450 /* Value is in Kb or KB (base 10). */
28451 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
28452 (UINT32_C(0x2) << 29)
28453 /* Value is in bits or bytes. */
28454 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
28455 (UINT32_C(0x4) << 29)
28456 /* Value is in Gb or GB (base 10). */
28457 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
28458 (UINT32_C(0x6) << 29)
28459 /* Value is in 1/100th of a percentage of total bandwidth. */
28460 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
28461 (UINT32_C(0x1) << 29)
28463 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
28464 (UINT32_C(0x7) << 29)
28465 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
28466 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
28469 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
28470 struct hwrm_cfa_meter_profile_alloc_output {
28471 /* The specific error status for the command. */
28472 uint16_t error_code;
28473 /* The HWRM command request type. */
28475 /* The sequence ID from the original command. */
28477 /* The length of the response data in number of bytes. */
28479 /* This value identifies a meter profile in CFA. */
28480 uint16_t meter_profile_id;
28482 * A value of 0xfff is considered invalid and implies the
28483 * profile is not configured.
28485 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
28487 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
28488 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
28489 uint8_t unused_0[5];
28491 * This field is used in Output records to indicate that the output
28492 * is completely written to RAM. This field should be read as '1'
28493 * to indicate that the output has been completely written.
28494 * When writing a command completion or response to an internal processor,
28495 * the order of writes has to be such that this field is written last.
28500 /*******************************
28501 * hwrm_cfa_meter_profile_free *
28502 *******************************/
28505 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
28506 struct hwrm_cfa_meter_profile_free_input {
28507 /* The HWRM command request type. */
28510 * The completion ring to send the completion event on. This should
28511 * be the NQ ID returned from the `nq_alloc` HWRM command.
28513 uint16_t cmpl_ring;
28515 * The sequence ID is used by the driver for tracking multiple
28516 * commands. This ID is treated as opaque data by the firmware and
28517 * the value is returned in the `hwrm_resp_hdr` upon completion.
28521 * The target ID of the command:
28522 * * 0x0-0xFFF8 - The function ID
28523 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28524 * * 0xFFFD - Reserved for user-space HWRM interface
28527 uint16_t target_id;
28529 * A physical address pointer pointing to a host buffer that the
28530 * command's response data will be written. This can be either a host
28531 * physical address (HPA) or a guest physical address (GPA) and must
28532 * point to a physically contiguous block of memory.
28534 uint64_t resp_addr;
28537 * Enumeration denoting the RX, TX type of the resource.
28538 * This enumeration is used for resources that are similar for both
28539 * TX and RX paths of the chip.
28541 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
28543 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
28546 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
28548 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
28549 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
28551 /* This value identifies a meter profile in CFA. */
28552 uint16_t meter_profile_id;
28554 * A value of 0xfff is considered invalid and implies the
28555 * profile is not configured.
28557 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
28559 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
28560 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
28561 uint8_t unused_1[4];
28564 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
28565 struct hwrm_cfa_meter_profile_free_output {
28566 /* The specific error status for the command. */
28567 uint16_t error_code;
28568 /* The HWRM command request type. */
28570 /* The sequence ID from the original command. */
28572 /* The length of the response data in number of bytes. */
28574 uint8_t unused_0[7];
28576 * This field is used in Output records to indicate that the output
28577 * is completely written to RAM. This field should be read as '1'
28578 * to indicate that the output has been completely written.
28579 * When writing a command completion or response to an internal processor,
28580 * the order of writes has to be such that this field is written last.
28585 /******************************
28586 * hwrm_cfa_meter_profile_cfg *
28587 ******************************/
28590 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
28591 struct hwrm_cfa_meter_profile_cfg_input {
28592 /* The HWRM command request type. */
28595 * The completion ring to send the completion event on. This should
28596 * be the NQ ID returned from the `nq_alloc` HWRM command.
28598 uint16_t cmpl_ring;
28600 * The sequence ID is used by the driver for tracking multiple
28601 * commands. This ID is treated as opaque data by the firmware and
28602 * the value is returned in the `hwrm_resp_hdr` upon completion.
28606 * The target ID of the command:
28607 * * 0x0-0xFFF8 - The function ID
28608 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28609 * * 0xFFFD - Reserved for user-space HWRM interface
28612 uint16_t target_id;
28614 * A physical address pointer pointing to a host buffer that the
28615 * command's response data will be written. This can be either a host
28616 * physical address (HPA) or a guest physical address (GPA) and must
28617 * point to a physically contiguous block of memory.
28619 uint64_t resp_addr;
28622 * Enumeration denoting the RX, TX type of the resource.
28623 * This enumeration is used for resources that are similar for both
28624 * TX and RX paths of the chip.
28626 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28628 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
28630 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
28631 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
28632 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
28633 /* The meter algorithm type. */
28634 uint8_t meter_type;
28635 /* RFC 2697 (srTCM) */
28636 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
28638 /* RFC 2698 (trTCM) */
28639 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
28641 /* RFC 4115 (trTCM) */
28642 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
28644 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
28645 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
28646 /* This value identifies a meter profile in CFA. */
28647 uint16_t meter_profile_id;
28649 * A value of 0xfff is considered invalid and implies the
28650 * profile is not configured.
28652 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
28654 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
28655 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
28657 * This field is reserved for the future use.
28658 * It shall be set to 0.
28661 /* A meter rate specified in bytes-per-second. */
28662 uint32_t commit_rate;
28663 /* The bandwidth value. */
28664 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
28665 UINT32_C(0xfffffff)
28666 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
28668 /* The granularity of the value (bits or bytes). */
28669 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
28670 UINT32_C(0x10000000)
28671 /* Value is in bits. */
28672 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
28673 (UINT32_C(0x0) << 28)
28674 /* Value is in bytes. */
28675 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
28676 (UINT32_C(0x1) << 28)
28677 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
28678 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
28679 /* bw_value_unit is 3 b */
28680 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
28681 UINT32_C(0xe0000000)
28682 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
28684 /* Value is in Mb or MB (base 10). */
28685 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
28686 (UINT32_C(0x0) << 29)
28687 /* Value is in Kb or KB (base 10). */
28688 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
28689 (UINT32_C(0x2) << 29)
28690 /* Value is in bits or bytes. */
28691 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
28692 (UINT32_C(0x4) << 29)
28693 /* Value is in Gb or GB (base 10). */
28694 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
28695 (UINT32_C(0x6) << 29)
28696 /* Value is in 1/100th of a percentage of total bandwidth. */
28697 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
28698 (UINT32_C(0x1) << 29)
28700 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
28701 (UINT32_C(0x7) << 29)
28702 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
28703 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
28704 /* A meter burst size specified in bytes. */
28705 uint32_t commit_burst;
28706 /* The bandwidth value. */
28707 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
28708 UINT32_C(0xfffffff)
28709 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
28711 /* The granularity of the value (bits or bytes). */
28712 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
28713 UINT32_C(0x10000000)
28714 /* Value is in bits. */
28715 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
28716 (UINT32_C(0x0) << 28)
28717 /* Value is in bytes. */
28718 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
28719 (UINT32_C(0x1) << 28)
28720 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
28721 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
28722 /* bw_value_unit is 3 b */
28723 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
28724 UINT32_C(0xe0000000)
28725 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
28727 /* Value is in Mb or MB (base 10). */
28728 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
28729 (UINT32_C(0x0) << 29)
28730 /* Value is in Kb or KB (base 10). */
28731 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
28732 (UINT32_C(0x2) << 29)
28733 /* Value is in bits or bytes. */
28734 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
28735 (UINT32_C(0x4) << 29)
28736 /* Value is in Gb or GB (base 10). */
28737 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
28738 (UINT32_C(0x6) << 29)
28739 /* Value is in 1/100th of a percentage of total bandwidth. */
28740 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
28741 (UINT32_C(0x1) << 29)
28742 /* Invalid value */
28743 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
28744 (UINT32_C(0x7) << 29)
28745 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
28746 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
28747 /* A meter rate specified in bytes-per-second. */
28748 uint32_t excess_peak_rate;
28749 /* The bandwidth value. */
28750 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
28751 UINT32_C(0xfffffff)
28752 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
28754 /* The granularity of the value (bits or bytes). */
28755 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
28756 UINT32_C(0x10000000)
28757 /* Value is in bits. */
28758 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
28759 (UINT32_C(0x0) << 28)
28760 /* Value is in bytes. */
28761 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
28762 (UINT32_C(0x1) << 28)
28763 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
28764 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
28765 /* bw_value_unit is 3 b */
28766 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
28767 UINT32_C(0xe0000000)
28768 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
28770 /* Value is in Mb or MB (base 10). */
28771 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
28772 (UINT32_C(0x0) << 29)
28773 /* Value is in Kb or KB (base 10). */
28774 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
28775 (UINT32_C(0x2) << 29)
28776 /* Value is in bits or bytes. */
28777 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
28778 (UINT32_C(0x4) << 29)
28779 /* Value is in Gb or GB (base 10). */
28780 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
28781 (UINT32_C(0x6) << 29)
28782 /* Value is in 1/100th of a percentage of total bandwidth. */
28783 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
28784 (UINT32_C(0x1) << 29)
28786 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
28787 (UINT32_C(0x7) << 29)
28788 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
28789 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
28790 /* A meter burst size specified in bytes. */
28791 uint32_t excess_peak_burst;
28792 /* The bandwidth value. */
28793 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
28794 UINT32_C(0xfffffff)
28795 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
28797 /* The granularity of the value (bits or bytes). */
28798 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
28799 UINT32_C(0x10000000)
28800 /* Value is in bits. */
28801 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
28802 (UINT32_C(0x0) << 28)
28803 /* Value is in bytes. */
28804 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
28805 (UINT32_C(0x1) << 28)
28806 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
28807 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
28808 /* bw_value_unit is 3 b */
28809 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
28810 UINT32_C(0xe0000000)
28811 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
28813 /* Value is in Mb or MB (base 10). */
28814 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
28815 (UINT32_C(0x0) << 29)
28816 /* Value is in Kb or KB (base 10). */
28817 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
28818 (UINT32_C(0x2) << 29)
28819 /* Value is in bits or bytes. */
28820 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
28821 (UINT32_C(0x4) << 29)
28822 /* Value is in Gb or GB (base 10). */
28823 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
28824 (UINT32_C(0x6) << 29)
28825 /* Value is in 1/100th of a percentage of total bandwidth. */
28826 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
28827 (UINT32_C(0x1) << 29)
28829 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
28830 (UINT32_C(0x7) << 29)
28831 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
28832 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
28835 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
28836 struct hwrm_cfa_meter_profile_cfg_output {
28837 /* The specific error status for the command. */
28838 uint16_t error_code;
28839 /* The HWRM command request type. */
28841 /* The sequence ID from the original command. */
28843 /* The length of the response data in number of bytes. */
28845 uint8_t unused_0[7];
28847 * This field is used in Output records to indicate that the output
28848 * is completely written to RAM. This field should be read as '1'
28849 * to indicate that the output has been completely written.
28850 * When writing a command completion or response to an internal processor,
28851 * the order of writes has to be such that this field is written last.
28856 /*********************************
28857 * hwrm_cfa_meter_instance_alloc *
28858 *********************************/
28861 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
28862 struct hwrm_cfa_meter_instance_alloc_input {
28863 /* The HWRM command request type. */
28866 * The completion ring to send the completion event on. This should
28867 * be the NQ ID returned from the `nq_alloc` HWRM command.
28869 uint16_t cmpl_ring;
28871 * The sequence ID is used by the driver for tracking multiple
28872 * commands. This ID is treated as opaque data by the firmware and
28873 * the value is returned in the `hwrm_resp_hdr` upon completion.
28877 * The target ID of the command:
28878 * * 0x0-0xFFF8 - The function ID
28879 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28880 * * 0xFFFD - Reserved for user-space HWRM interface
28883 uint16_t target_id;
28885 * A physical address pointer pointing to a host buffer that the
28886 * command's response data will be written. This can be either a host
28887 * physical address (HPA) or a guest physical address (GPA) and must
28888 * point to a physically contiguous block of memory.
28890 uint64_t resp_addr;
28893 * Enumeration denoting the RX, TX type of the resource.
28894 * This enumeration is used for resources that are similar for both
28895 * TX and RX paths of the chip.
28897 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
28900 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
28903 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
28905 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
28906 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
28908 /* This value identifies a meter profile in CFA. */
28909 uint16_t meter_profile_id;
28911 * A value of 0xffff is considered invalid and implies the
28912 * profile is not configured.
28914 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
28916 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
28917 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
28918 uint8_t unused_1[4];
28921 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
28922 struct hwrm_cfa_meter_instance_alloc_output {
28923 /* The specific error status for the command. */
28924 uint16_t error_code;
28925 /* The HWRM command request type. */
28927 /* The sequence ID from the original command. */
28929 /* The length of the response data in number of bytes. */
28931 /* This value identifies a meter instance in CFA. */
28932 uint16_t meter_instance_id;
28934 * A value of 0xffff is considered invalid and implies the
28935 * instance is not configured.
28937 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
28939 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
28940 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
28941 uint8_t unused_0[5];
28943 * This field is used in Output records to indicate that the output
28944 * is completely written to RAM. This field should be read as '1'
28945 * to indicate that the output has been completely written.
28946 * When writing a command completion or response to an internal processor,
28947 * the order of writes has to be such that this field is written last.
28952 /*******************************
28953 * hwrm_cfa_meter_instance_cfg *
28954 *******************************/
28957 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
28958 struct hwrm_cfa_meter_instance_cfg_input {
28959 /* The HWRM command request type. */
28962 * The completion ring to send the completion event on. This should
28963 * be the NQ ID returned from the `nq_alloc` HWRM command.
28965 uint16_t cmpl_ring;
28967 * The sequence ID is used by the driver for tracking multiple
28968 * commands. This ID is treated as opaque data by the firmware and
28969 * the value is returned in the `hwrm_resp_hdr` upon completion.
28973 * The target ID of the command:
28974 * * 0x0-0xFFF8 - The function ID
28975 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28976 * * 0xFFFD - Reserved for user-space HWRM interface
28979 uint16_t target_id;
28981 * A physical address pointer pointing to a host buffer that the
28982 * command's response data will be written. This can be either a host
28983 * physical address (HPA) or a guest physical address (GPA) and must
28984 * point to a physically contiguous block of memory.
28986 uint64_t resp_addr;
28989 * Enumeration denoting the RX, TX type of the resource.
28990 * This enumeration is used for resources that are similar for both
28991 * TX and RX paths of the chip.
28993 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
28995 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
28998 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
29000 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
29001 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
29004 * This value identifies a new meter profile to be associated with
29005 * the meter instance specified in this command.
29007 uint16_t meter_profile_id;
29009 * A value of 0xffff is considered invalid and implies the
29010 * profile is not configured.
29012 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
29014 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
29015 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
29017 * This value identifies the ID of a meter instance that needs to be updated with
29018 * a new meter profile specified in this command.
29020 uint16_t meter_instance_id;
29021 uint8_t unused_1[2];
29024 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
29025 struct hwrm_cfa_meter_instance_cfg_output {
29026 /* The specific error status for the command. */
29027 uint16_t error_code;
29028 /* The HWRM command request type. */
29030 /* The sequence ID from the original command. */
29032 /* The length of the response data in number of bytes. */
29034 uint8_t unused_0[7];
29036 * This field is used in Output records to indicate that the output
29037 * is completely written to RAM. This field should be read as '1'
29038 * to indicate that the output has been completely written.
29039 * When writing a command completion or response to an internal processor,
29040 * the order of writes has to be such that this field is written last.
29045 /********************************
29046 * hwrm_cfa_meter_instance_free *
29047 ********************************/
29050 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
29051 struct hwrm_cfa_meter_instance_free_input {
29052 /* The HWRM command request type. */
29055 * The completion ring to send the completion event on. This should
29056 * be the NQ ID returned from the `nq_alloc` HWRM command.
29058 uint16_t cmpl_ring;
29060 * The sequence ID is used by the driver for tracking multiple
29061 * commands. This ID is treated as opaque data by the firmware and
29062 * the value is returned in the `hwrm_resp_hdr` upon completion.
29066 * The target ID of the command:
29067 * * 0x0-0xFFF8 - The function ID
29068 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29069 * * 0xFFFD - Reserved for user-space HWRM interface
29072 uint16_t target_id;
29074 * A physical address pointer pointing to a host buffer that the
29075 * command's response data will be written. This can be either a host
29076 * physical address (HPA) or a guest physical address (GPA) and must
29077 * point to a physically contiguous block of memory.
29079 uint64_t resp_addr;
29082 * Enumeration denoting the RX, TX type of the resource.
29083 * This enumeration is used for resources that are similar for both
29084 * TX and RX paths of the chip.
29086 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
29088 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
29091 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
29093 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
29094 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
29096 /* This value identifies a meter instance in CFA. */
29097 uint16_t meter_instance_id;
29099 * A value of 0xfff is considered invalid and implies the
29100 * instance is not configured.
29102 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
29104 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
29105 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
29106 uint8_t unused_1[4];
29109 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
29110 struct hwrm_cfa_meter_instance_free_output {
29111 /* The specific error status for the command. */
29112 uint16_t error_code;
29113 /* The HWRM command request type. */
29115 /* The sequence ID from the original command. */
29117 /* The length of the response data in number of bytes. */
29119 uint8_t unused_0[7];
29121 * This field is used in Output records to indicate that the output
29122 * is completely written to RAM. This field should be read as '1'
29123 * to indicate that the output has been completely written.
29124 * When writing a command completion or response to an internal processor,
29125 * the order of writes has to be such that this field is written last.
29130 /*******************************
29131 * hwrm_cfa_decap_filter_alloc *
29132 *******************************/
29135 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
29136 struct hwrm_cfa_decap_filter_alloc_input {
29137 /* The HWRM command request type. */
29140 * The completion ring to send the completion event on. This should
29141 * be the NQ ID returned from the `nq_alloc` HWRM command.
29143 uint16_t cmpl_ring;
29145 * The sequence ID is used by the driver for tracking multiple
29146 * commands. This ID is treated as opaque data by the firmware and
29147 * the value is returned in the `hwrm_resp_hdr` upon completion.
29151 * The target ID of the command:
29152 * * 0x0-0xFFF8 - The function ID
29153 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29154 * * 0xFFFD - Reserved for user-space HWRM interface
29157 uint16_t target_id;
29159 * A physical address pointer pointing to a host buffer that the
29160 * command's response data will be written. This can be either a host
29161 * physical address (HPA) or a guest physical address (GPA) and must
29162 * point to a physically contiguous block of memory.
29164 uint64_t resp_addr;
29166 /* ovs_tunnel is 1 b */
29167 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
29171 * This bit must be '1' for the tunnel_type field to be
29174 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
29177 * This bit must be '1' for the tunnel_id field to be
29180 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
29183 * This bit must be '1' for the src_macaddr field to be
29186 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
29189 * This bit must be '1' for the dst_macaddr field to be
29192 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
29195 * This bit must be '1' for the ovlan_vid field to be
29198 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
29201 * This bit must be '1' for the ivlan_vid field to be
29204 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
29207 * This bit must be '1' for the t_ovlan_vid field to be
29210 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
29213 * This bit must be '1' for the t_ivlan_vid field to be
29216 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
29219 * This bit must be '1' for the ethertype field to be
29222 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
29225 * This bit must be '1' for the src_ipaddr field to be
29228 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
29231 * This bit must be '1' for the dst_ipaddr field to be
29234 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
29237 * This bit must be '1' for the ipaddr_type field to be
29240 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
29243 * This bit must be '1' for the ip_protocol field to be
29246 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
29249 * This bit must be '1' for the src_port field to be
29252 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
29255 * This bit must be '1' for the dst_port field to be
29258 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
29261 * This bit must be '1' for the dst_id field to be
29264 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
29267 * This bit must be '1' for the mirror_vnic_id field to be
29270 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
29273 * Tunnel identifier.
29274 * Virtual Network Identifier (VNI). Only valid with
29275 * tunnel_types VXLAN, NVGRE, and Geneve.
29276 * Only lower 24-bits of VNI field are used
29277 * in setting up the filter.
29279 uint32_t tunnel_id;
29281 uint8_t tunnel_type;
29283 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29285 /* Virtual eXtensible Local Area Network (VXLAN) */
29286 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29288 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29289 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29291 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29292 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29295 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29297 /* Generic Network Virtualization Encapsulation (Geneve) */
29298 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29300 /* Multi-Protocol Label Switching (MPLS) */
29301 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29303 /* Stateless Transport Tunnel (STT) */
29304 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
29306 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29307 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29309 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29310 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29312 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29313 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29315 /* Use fixed layer 2 ether type of 0xFFFF */
29316 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29318 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29319 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29321 /* Any tunneled traffic */
29322 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29324 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29325 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29329 * This value indicates the source MAC address in
29330 * the Ethernet header.
29332 uint8_t src_macaddr[6];
29333 uint8_t unused_2[2];
29335 * This value indicates the destination MAC address in
29336 * the Ethernet header.
29338 uint8_t dst_macaddr[6];
29340 * This value indicates the VLAN ID of the outer VLAN tag
29341 * in the Ethernet header.
29343 uint16_t ovlan_vid;
29345 * This value indicates the VLAN ID of the inner VLAN tag
29346 * in the Ethernet header.
29348 uint16_t ivlan_vid;
29350 * This value indicates the VLAN ID of the outer VLAN tag
29351 * in the tunnel Ethernet header.
29353 uint16_t t_ovlan_vid;
29355 * This value indicates the VLAN ID of the inner VLAN tag
29356 * in the tunnel Ethernet header.
29358 uint16_t t_ivlan_vid;
29359 /* This value indicates the ethertype in the Ethernet header. */
29360 uint16_t ethertype;
29362 * This value indicates the type of IP address.
29365 * All others are invalid.
29367 uint8_t ip_addr_type;
29369 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
29372 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
29375 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
29377 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
29378 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
29380 * The value of protocol filed in IP header.
29381 * Applies to UDP and TCP traffic.
29385 uint8_t ip_protocol;
29387 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
29390 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
29393 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
29395 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
29396 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
29400 * The value of source IP address to be used in filtering.
29401 * For IPv4, first four bytes represent the IP address.
29403 uint32_t src_ipaddr[4];
29405 * The value of destination IP address to be used in filtering.
29406 * For IPv4, first four bytes represent the IP address.
29408 uint32_t dst_ipaddr[4];
29410 * The value of source port to be used in filtering.
29411 * Applies to UDP and TCP traffic.
29415 * The value of destination port to be used in filtering.
29416 * Applies to UDP and TCP traffic.
29420 * If set, this value shall represent the
29421 * Logical VNIC ID of the destination VNIC for the RX
29426 * If set, this value shall represent the L2 context that matches the L2
29427 * information of the decap filter.
29429 uint16_t l2_ctxt_ref_id;
29432 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
29433 struct hwrm_cfa_decap_filter_alloc_output {
29434 /* The specific error status for the command. */
29435 uint16_t error_code;
29436 /* The HWRM command request type. */
29438 /* The sequence ID from the original command. */
29440 /* The length of the response data in number of bytes. */
29442 /* This value is an opaque id into CFA data structures. */
29443 uint32_t decap_filter_id;
29444 uint8_t unused_0[3];
29446 * This field is used in Output records to indicate that the output
29447 * is completely written to RAM. This field should be read as '1'
29448 * to indicate that the output has been completely written.
29449 * When writing a command completion or response to an internal processor,
29450 * the order of writes has to be such that this field is written last.
29455 /******************************
29456 * hwrm_cfa_decap_filter_free *
29457 ******************************/
29460 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
29461 struct hwrm_cfa_decap_filter_free_input {
29462 /* The HWRM command request type. */
29465 * The completion ring to send the completion event on. This should
29466 * be the NQ ID returned from the `nq_alloc` HWRM command.
29468 uint16_t cmpl_ring;
29470 * The sequence ID is used by the driver for tracking multiple
29471 * commands. This ID is treated as opaque data by the firmware and
29472 * the value is returned in the `hwrm_resp_hdr` upon completion.
29476 * The target ID of the command:
29477 * * 0x0-0xFFF8 - The function ID
29478 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29479 * * 0xFFFD - Reserved for user-space HWRM interface
29482 uint16_t target_id;
29484 * A physical address pointer pointing to a host buffer that the
29485 * command's response data will be written. This can be either a host
29486 * physical address (HPA) or a guest physical address (GPA) and must
29487 * point to a physically contiguous block of memory.
29489 uint64_t resp_addr;
29490 /* This value is an opaque id into CFA data structures. */
29491 uint32_t decap_filter_id;
29492 uint8_t unused_0[4];
29495 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
29496 struct hwrm_cfa_decap_filter_free_output {
29497 /* The specific error status for the command. */
29498 uint16_t error_code;
29499 /* The HWRM command request type. */
29501 /* The sequence ID from the original command. */
29503 /* The length of the response data in number of bytes. */
29505 uint8_t unused_0[7];
29507 * This field is used in Output records to indicate that the output
29508 * is completely written to RAM. This field should be read as '1'
29509 * to indicate that the output has been completely written.
29510 * When writing a command completion or response to an internal processor,
29511 * the order of writes has to be such that this field is written last.
29516 /***********************
29517 * hwrm_cfa_flow_alloc *
29518 ***********************/
29521 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
29522 struct hwrm_cfa_flow_alloc_input {
29523 /* The HWRM command request type. */
29526 * The completion ring to send the completion event on. This should
29527 * be the NQ ID returned from the `nq_alloc` HWRM command.
29529 uint16_t cmpl_ring;
29531 * The sequence ID is used by the driver for tracking multiple
29532 * commands. This ID is treated as opaque data by the firmware and
29533 * the value is returned in the `hwrm_resp_hdr` upon completion.
29537 * The target ID of the command:
29538 * * 0x0-0xFFF8 - The function ID
29539 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29540 * * 0xFFFD - Reserved for user-space HWRM interface
29543 uint16_t target_id;
29545 * A physical address pointer pointing to a host buffer that the
29546 * command's response data will be written. This can be either a host
29547 * physical address (HPA) or a guest physical address (GPA) and must
29548 * point to a physically contiguous block of memory.
29550 uint64_t resp_addr;
29552 /* tunnel is 1 b */
29553 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
29555 /* num_vlan is 2 b */
29556 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
29558 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
29560 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
29561 (UINT32_C(0x0) << 1)
29563 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
29564 (UINT32_C(0x1) << 1)
29566 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
29567 (UINT32_C(0x2) << 1)
29568 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
29569 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
29570 /* Enumeration denoting the Flow Type. */
29571 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
29573 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
29575 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
29576 (UINT32_C(0x0) << 3)
29578 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
29579 (UINT32_C(0x1) << 3)
29581 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
29582 (UINT32_C(0x2) << 3)
29583 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
29584 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
29586 * when set to 1, indicates TX flow offload for function specified in src_fid and
29587 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
29588 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
29589 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
29590 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
29591 * belong to the children VFs of the same PF to indicate VM to VM flow.
29593 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
29596 * when set to 1, indicates RX flow offload for function specified in dst_fid and
29597 * the src_fid should be set to invalid value.
29599 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
29602 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
29603 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
29604 * This flag is only valid when the flow direction is RX.
29606 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
29608 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
29609 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
29616 /* Tunnel handle valid when tunnel flag is set. */
29617 uint32_t tunnel_handle;
29618 uint16_t action_flags;
29620 * Setting of this flag indicates drop action. If this flag is not set,
29621 * then it should be considered accept action.
29623 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
29625 /* recycle is 1 b */
29626 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
29629 * Setting of this flag indicates drop action. If this flag is not set,
29630 * then it should be considered accept action.
29632 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
29635 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
29637 /* tunnel is 1 b */
29638 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
29640 /* nat_src is 1 b */
29641 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
29643 /* nat_dest is 1 b */
29644 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
29646 /* nat_ipv4_address is 1 b */
29647 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
29649 /* l2_header_rewrite is 1 b */
29650 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
29652 /* ttl_decrement is 1 b */
29653 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
29656 * If set to 1 and flow direction is TX, it indicates decap of L2 header
29657 * and encap of tunnel header. If set to 1 and flow direction is RX, it
29658 * indicates decap of tunnel header and encap L2 header. The type of tunnel
29659 * is specified in the tunnel_type field.
29661 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
29663 /* If set to 1, flow aging is enabled for this flow. */
29664 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
29667 * If set to 1 an attempt will be made to try to offload this flow to the
29668 * most optimal flow table resource. If set to 0, the flow will be
29669 * placed to the default flow table resource.
29671 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
29674 * If set to 1 there will be no attempt to allocate an on-chip try to
29675 * offload this flow. If set to 0, which will keep compatibility with the
29676 * older drivers, will cause the FW to attempt to allocate an on-chip flow
29677 * counter for the newly created flow. This will keep the existing behavior
29678 * with EM flows which always had an associated flow counter.
29680 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
29683 * Tx Flow: pf or vf fid.
29687 /* VLAN tpid, valid when push_vlan flag is set. */
29688 uint16_t l2_rewrite_vlan_tpid;
29689 /* VLAN tci, valid when push_vlan flag is set. */
29690 uint16_t l2_rewrite_vlan_tci;
29691 /* Meter id, valid when meter flag is set. */
29692 uint16_t act_meter_id;
29693 /* Flow with the same l2 context tcam key. */
29694 uint16_t ref_flow_handle;
29695 /* This value sets the match value for the ethertype. */
29696 uint16_t ethertype;
29697 /* valid when num tags is 1 or 2. */
29698 uint16_t outer_vlan_tci;
29699 /* This value sets the match value for the Destination MAC address. */
29701 /* valid when num tags is 2. */
29702 uint16_t inner_vlan_tci;
29703 /* This value sets the match value for the Source MAC address. */
29705 /* The bit length of destination IP address mask. */
29706 uint8_t ip_dst_mask_len;
29707 /* The bit length of source IP address mask. */
29708 uint8_t ip_src_mask_len;
29709 /* The value of destination IPv4/IPv6 address. */
29710 uint32_t ip_dst[4];
29711 /* The source IPv4/IPv6 address. */
29712 uint32_t ip_src[4];
29714 * The value of source port.
29715 * Applies to UDP and TCP traffic.
29717 uint16_t l4_src_port;
29719 * The value of source port mask.
29720 * Applies to UDP and TCP traffic.
29722 uint16_t l4_src_port_mask;
29724 * The value of destination port.
29725 * Applies to UDP and TCP traffic.
29727 uint16_t l4_dst_port;
29729 * The value of destination port mask.
29730 * Applies to UDP and TCP traffic.
29732 uint16_t l4_dst_port_mask;
29734 * NAT IPv4/6 address based on address type flag.
29735 * 0 values are ignored.
29737 uint32_t nat_ip_address[4];
29738 /* L2 header re-write Destination MAC address. */
29739 uint16_t l2_rewrite_dmac[3];
29741 * The NAT source/destination port based on direction flag.
29742 * Applies to UDP and TCP traffic.
29743 * 0 values are ignored.
29746 /* L2 header re-write Source MAC address. */
29747 uint16_t l2_rewrite_smac[3];
29748 /* The value of ip protocol. */
29751 uint8_t tunnel_type;
29753 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29755 /* Virtual eXtensible Local Area Network (VXLAN) */
29756 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29758 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29759 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29761 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29762 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29765 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29767 /* Generic Network Virtualization Encapsulation (Geneve) */
29768 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29770 /* Multi-Protocol Label Switching (MPLS) */
29771 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29773 /* Stateless Transport Tunnel (STT) */
29774 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
29776 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29777 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29779 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29780 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29782 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29783 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29785 /* Use fixed layer 2 ether type of 0xFFFF */
29786 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29788 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29789 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29791 /* Any tunneled traffic */
29792 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29794 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29795 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29798 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
29799 struct hwrm_cfa_flow_alloc_output {
29800 /* The specific error status for the command. */
29801 uint16_t error_code;
29802 /* The HWRM command request type. */
29804 /* The sequence ID from the original command. */
29806 /* The length of the response data in number of bytes. */
29808 /* Flow record index. */
29809 uint16_t flow_handle;
29810 uint8_t unused_0[2];
29812 * The flow id value in bit 0-29 is the actual ID of the flow
29813 * associated with this filter and it shall be used to match
29814 * and associate the flow identifier returned in completion
29815 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29816 * shall indicate no valid flow id.
29819 /* Indicate the flow id value. */
29820 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29821 UINT32_C(0x3fffffff)
29822 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29823 /* Indicate type of the flow. */
29824 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
29825 UINT32_C(0x40000000)
29827 * If this bit set to 0, then it indicates that the flow is
29830 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29831 (UINT32_C(0x0) << 30)
29833 * If this bit is set to 1, then it indicates that the flow is
29836 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29837 (UINT32_C(0x1) << 30)
29838 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29839 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29840 /* Indicate the flow direction. */
29841 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
29842 UINT32_C(0x80000000)
29843 /* If this bit set to 0, then it indicates rx flow. */
29844 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29845 (UINT32_C(0x0) << 31)
29846 /* If this bit is set to 1, then it indicates that tx flow. */
29847 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29848 (UINT32_C(0x1) << 31)
29849 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29850 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29851 /* This value identifies a set of CFA data structures used for a flow. */
29852 uint64_t ext_flow_handle;
29853 uint32_t flow_counter_id;
29854 uint8_t unused_1[3];
29856 * This field is used in Output records to indicate that the output
29857 * is completely written to RAM. This field should be read as '1'
29858 * to indicate that the output has been completely written.
29859 * When writing a command completion or response to an internal processor,
29860 * the order of writes has to be such that this field is written last.
29865 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
29866 struct hwrm_cfa_flow_alloc_cmd_err {
29868 * command specific error codes that goes to
29869 * the cmd_err field in Common HWRM Error Response.
29872 /* Unknown error */
29873 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
29874 /* No more L2 Context TCAM */
29875 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
29876 /* No more action records */
29877 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
29878 /* No more flow counters */
29879 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
29880 /* No more wild-card TCAM */
29881 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
29882 /* Hash collsion in exact match tables */
29883 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
29884 /* Key is already installed */
29885 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
29886 /* Flow Context DB is out of resource */
29887 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
29888 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
29889 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
29890 uint8_t unused_0[7];
29893 /**********************
29894 * hwrm_cfa_flow_free *
29895 **********************/
29898 /* hwrm_cfa_flow_free_input (size:256b/32B) */
29899 struct hwrm_cfa_flow_free_input {
29900 /* The HWRM command request type. */
29903 * The completion ring to send the completion event on. This should
29904 * be the NQ ID returned from the `nq_alloc` HWRM command.
29906 uint16_t cmpl_ring;
29908 * The sequence ID is used by the driver for tracking multiple
29909 * commands. This ID is treated as opaque data by the firmware and
29910 * the value is returned in the `hwrm_resp_hdr` upon completion.
29914 * The target ID of the command:
29915 * * 0x0-0xFFF8 - The function ID
29916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29917 * * 0xFFFD - Reserved for user-space HWRM interface
29920 uint16_t target_id;
29922 * A physical address pointer pointing to a host buffer that the
29923 * command's response data will be written. This can be either a host
29924 * physical address (HPA) or a guest physical address (GPA) and must
29925 * point to a physically contiguous block of memory.
29927 uint64_t resp_addr;
29928 /* Flow record index. */
29929 uint16_t flow_handle;
29931 /* Flow counter id to be freed. */
29932 uint32_t flow_counter_id;
29933 /* This value identifies a set of CFA data structures used for a flow. */
29934 uint64_t ext_flow_handle;
29937 /* hwrm_cfa_flow_free_output (size:256b/32B) */
29938 struct hwrm_cfa_flow_free_output {
29939 /* The specific error status for the command. */
29940 uint16_t error_code;
29941 /* The HWRM command request type. */
29943 /* The sequence ID from the original command. */
29945 /* The length of the response data in number of bytes. */
29947 /* packet is 64 b */
29951 uint8_t unused_0[7];
29953 * This field is used in Output records to indicate that the output
29954 * is completely written to RAM. This field should be read as '1'
29955 * to indicate that the output has been completely written.
29956 * When writing a command completion or response to an internal processor,
29957 * the order of writes has to be such that this field is written last.
29962 /* hwrm_cfa_flow_action_data (size:960b/120B) */
29963 struct hwrm_cfa_flow_action_data {
29964 uint16_t action_flags;
29965 /* Setting of this flag indicates accept action. */
29966 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
29968 /* Setting of this flag indicates recycle action. */
29969 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
29971 /* Setting of this flag indicates drop action. */
29972 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
29974 /* Setting of this flag indicates meter action. */
29975 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
29977 /* Setting of this flag indicates tunnel action. */
29978 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
29981 * If set to 1 and flow direction is TX, it indicates decap of L2 header
29982 * and encap of tunnel header. If set to 1 and flow direction is RX, it
29983 * indicates decap of tunnel header and encap L2 header.
29985 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
29987 /* Setting of this flag indicates ttl decrement action. */
29988 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
29990 /* If set to 1, flow aging is enabled for this flow. */
29991 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
29993 /* Setting of this flag indicates encap action. */
29994 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
29996 /* Setting of this flag indicates decap action. */
29997 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
30000 uint16_t act_meter_id;
30003 /* vport number. */
30005 /* The NAT source/destination. */
30007 uint16_t unused_0[3];
30008 /* NAT IPv4/IPv6 address. */
30009 uint32_t nat_ip_address[4];
30010 /* Encapsulation Type. */
30011 uint8_t encap_type;
30012 /* Virtual eXtensible Local Area Network (VXLAN) */
30013 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
30014 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30015 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
30016 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
30017 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
30019 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
30020 /* Generic Network Virtualization Encapsulation (Geneve) */
30021 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
30022 /* Multi-Protocol Label Switching (MPLS) */
30023 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
30025 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
30026 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30027 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
30028 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30029 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
30030 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30031 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
30032 /* Use fixed layer 2 ether type of 0xFFFF */
30033 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
30034 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30035 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
30036 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
30037 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
30039 /* This value is encap data for the associated encap type. */
30040 uint32_t encap_data[20];
30043 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
30044 struct hwrm_cfa_flow_tunnel_hdr_data {
30046 uint8_t tunnel_type;
30048 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
30050 /* Virtual eXtensible Local Area Network (VXLAN) */
30051 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
30053 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30054 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
30056 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30057 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
30060 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
30062 /* Generic Network Virtualization Encapsulation (Geneve) */
30063 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
30065 /* Multi-Protocol Label Switching (MPLS) */
30066 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
30068 /* Stateless Transport Tunnel (STT) */
30069 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
30071 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30072 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
30074 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30075 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
30077 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30078 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
30080 /* Use fixed layer 2 ether type of 0xFFFF */
30081 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
30083 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30084 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
30086 /* Any tunneled traffic */
30087 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
30089 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
30090 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
30093 * Tunnel identifier.
30094 * Virtual Network Identifier (VNI).
30096 uint32_t tunnel_id;
30099 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
30100 struct hwrm_cfa_flow_l4_key_data {
30101 /* The value of source port. */
30102 uint16_t l4_src_port;
30103 /* The value of destination port. */
30104 uint16_t l4_dst_port;
30108 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
30109 struct hwrm_cfa_flow_l3_key_data {
30110 /* The value of ip protocol. */
30111 uint8_t ip_protocol;
30112 uint8_t unused_0[7];
30113 /* The value of destination IPv4/IPv6 address. */
30114 uint32_t ip_dst[4];
30115 /* The source IPv4/IPv6 address. */
30116 uint32_t ip_src[4];
30117 /* NAT IPv4/IPv6 address. */
30118 uint32_t nat_ip_address[4];
30119 uint32_t unused[2];
30122 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
30123 struct hwrm_cfa_flow_l2_key_data {
30124 /* Destination MAC address. */
30127 /* Source MAC address. */
30130 /* L2 header re-write Destination MAC address. */
30131 uint16_t l2_rewrite_dmac[3];
30133 /* L2 header re-write Source MAC address. */
30134 uint16_t l2_rewrite_smac[3];
30136 uint16_t ethertype;
30137 /* Number of VLAN tags. */
30138 uint16_t num_vlan_tags;
30140 uint16_t l2_rewrite_vlan_tpid;
30142 uint16_t l2_rewrite_vlan_tci;
30143 uint8_t unused_3[2];
30144 /* Outer VLAN TPID. */
30145 uint16_t ovlan_tpid;
30146 /* Outer VLAN TCI. */
30147 uint16_t ovlan_tci;
30148 /* Inner VLAN TPID. */
30149 uint16_t ivlan_tpid;
30150 /* Inner VLAN TCI. */
30151 uint16_t ivlan_tci;
30155 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
30156 struct hwrm_cfa_flow_key_data {
30157 /* Flow associated tunnel L2 header key info. */
30158 uint32_t t_l2_key_data[14];
30159 /* Flow associated tunnel L2 header mask info. */
30160 uint32_t t_l2_key_mask[14];
30161 /* Flow associated tunnel L3 header key info. */
30162 uint32_t t_l3_key_data[16];
30163 /* Flow associated tunnel L3 header mask info. */
30164 uint32_t t_l3_key_mask[16];
30165 /* Flow associated tunnel L4 header key info. */
30166 uint32_t t_l4_key_data[2];
30167 /* Flow associated tunnel L4 header mask info. */
30168 uint32_t t_l4_key_mask[2];
30169 /* Flow associated tunnel header info. */
30170 uint32_t tunnel_hdr[2];
30171 /* Flow associated L2 header key info. */
30172 uint32_t l2_key_data[14];
30173 /* Flow associated L2 header mask info. */
30174 uint32_t l2_key_mask[14];
30175 /* Flow associated L3 header key info. */
30176 uint32_t l3_key_data[16];
30177 /* Flow associated L3 header mask info. */
30178 uint32_t l3_key_mask[16];
30179 /* Flow associated L4 header key info. */
30180 uint32_t l4_key_data[2];
30181 /* Flow associated L4 header mask info. */
30182 uint32_t l4_key_mask[2];
30185 /**********************
30186 * hwrm_cfa_flow_info *
30187 **********************/
30190 /* hwrm_cfa_flow_info_input (size:256b/32B) */
30191 struct hwrm_cfa_flow_info_input {
30192 /* The HWRM command request type. */
30195 * The completion ring to send the completion event on. This should
30196 * be the NQ ID returned from the `nq_alloc` HWRM command.
30198 uint16_t cmpl_ring;
30200 * The sequence ID is used by the driver for tracking multiple
30201 * commands. This ID is treated as opaque data by the firmware and
30202 * the value is returned in the `hwrm_resp_hdr` upon completion.
30206 * The target ID of the command:
30207 * * 0x0-0xFFF8 - The function ID
30208 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30209 * * 0xFFFD - Reserved for user-space HWRM interface
30212 uint16_t target_id;
30214 * A physical address pointer pointing to a host buffer that the
30215 * command's response data will be written. This can be either a host
30216 * physical address (HPA) or a guest physical address (GPA) and must
30217 * point to a physically contiguous block of memory.
30219 uint64_t resp_addr;
30220 /* Flow record index. */
30221 uint16_t flow_handle;
30222 /* Max flow handle */
30223 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
30225 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
30226 /* CNP flow handle */
30227 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
30229 /* RoCEv1 flow handle */
30230 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
30232 /* RoCEv2 flow handle */
30233 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
30235 /* Direction rx = 1 */
30236 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
30238 uint8_t unused_0[6];
30239 /* This value identifies a set of CFA data structures used for a flow. */
30240 uint64_t ext_flow_handle;
30243 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
30244 struct hwrm_cfa_flow_info_output {
30245 /* The specific error status for the command. */
30246 uint16_t error_code;
30247 /* The HWRM command request type. */
30249 /* The sequence ID from the original command. */
30251 /* The length of the response data in number of bytes. */
30254 /* When set to 1, indicates the configuration is the TX flow. */
30255 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
30256 /* When set to 1, indicates the configuration is the RX flow. */
30257 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
30258 /* profile is 8 b */
30260 /* src_fid is 16 b */
30262 /* dst_fid is 16 b */
30264 /* l2_ctxt_id is 16 b */
30265 uint16_t l2_ctxt_id;
30266 /* em_info is 64 b */
30268 /* tcam_info is 64 b */
30269 uint64_t tcam_info;
30270 /* vfp_tcam_info is 64 b */
30271 uint64_t vfp_tcam_info;
30272 /* ar_id is 16 b */
30274 /* flow_handle is 16 b */
30275 uint16_t flow_handle;
30276 /* tunnel_handle is 32 b */
30277 uint32_t tunnel_handle;
30278 /* The flow aging timer for the flow, the unit is 100 milliseconds */
30279 uint16_t flow_timer;
30280 uint8_t unused_0[6];
30281 /* Flow associated L2, L3 and L4 headers info. */
30282 uint32_t flow_key_data[130];
30283 /* Flow associated action record info. */
30284 uint32_t flow_action_info[30];
30285 uint8_t unused_1[7];
30287 * This field is used in Output records to indicate that the output
30288 * is completely written to RAM. This field should be read as '1'
30289 * to indicate that the output has been completely written.
30290 * When writing a command completion or response to an internal processor,
30291 * the order of writes has to be such that this field is written last.
30296 /***********************
30297 * hwrm_cfa_flow_flush *
30298 ***********************/
30301 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
30302 struct hwrm_cfa_flow_flush_input {
30303 /* The HWRM command request type. */
30306 * The completion ring to send the completion event on. This should
30307 * be the NQ ID returned from the `nq_alloc` HWRM command.
30309 uint16_t cmpl_ring;
30311 * The sequence ID is used by the driver for tracking multiple
30312 * commands. This ID is treated as opaque data by the firmware and
30313 * the value is returned in the `hwrm_resp_hdr` upon completion.
30317 * The target ID of the command:
30318 * * 0x0-0xFFF8 - The function ID
30319 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30320 * * 0xFFFD - Reserved for user-space HWRM interface
30323 uint16_t target_id;
30325 * A physical address pointer pointing to a host buffer that the
30326 * command's response data will be written. This can be either a host
30327 * physical address (HPA) or a guest physical address (GPA) and must
30328 * point to a physically contiguous block of memory.
30330 uint64_t resp_addr;
30331 /* flags is 32 b */
30334 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
30335 * fields are valid. The flow flush operation should only flush the flows from the
30336 * flow table specified. This flag is set to 0 by older driver. For older firmware,
30337 * setting this flag has no effect.
30339 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
30342 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
30343 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
30344 * setting this flag has no effect.
30346 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
30349 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
30350 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
30352 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
30354 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
30355 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
30356 UINT32_C(0x8000000)
30358 * This specifies the size of flow handle entries provided by the driver
30359 * in the flow table specified below. Only two flow handle size enums are defined.
30361 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
30362 UINT32_C(0xc0000000)
30363 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
30365 /* The flow handle is 16bit */
30366 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
30367 (UINT32_C(0x0) << 30)
30368 /* The flow handle is 64bit */
30369 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
30370 (UINT32_C(0x1) << 30)
30371 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
30372 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
30373 /* Specify page size of the flow table memory. */
30375 /* The page size is 4K */
30376 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
30377 /* The page size is 8K */
30378 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
30379 /* The page size is 64K */
30380 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
30381 /* The page size is 256K */
30382 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
30383 /* The page size is 1M */
30384 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
30385 /* The page size is 2M */
30386 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
30387 /* The page size is 4M */
30388 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
30389 /* The page size is 1G */
30390 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
30391 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
30392 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
30393 /* FLow table memory indirect levels. */
30394 uint8_t page_level;
30395 /* PBL pointer is physical start address. */
30396 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
30397 /* PBL pointer points to PTE table. */
30398 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
30399 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
30400 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
30401 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
30402 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
30403 /* number of flows in the flow table */
30404 uint16_t num_flows;
30405 /* Pointer to the PBL, or PDL depending on number of levels */
30409 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
30410 struct hwrm_cfa_flow_flush_output {
30411 /* The specific error status for the command. */
30412 uint16_t error_code;
30413 /* The HWRM command request type. */
30415 /* The sequence ID from the original command. */
30417 /* The length of the response data in number of bytes. */
30419 uint8_t unused_0[7];
30421 * This field is used in Output records to indicate that the output
30422 * is completely written to RAM. This field should be read as '1'
30423 * to indicate that the output has been completely written.
30424 * When writing a command completion or response to an internal processor,
30425 * the order of writes has to be such that this field is written last.
30430 /***********************
30431 * hwrm_cfa_flow_stats *
30432 ***********************/
30435 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
30436 struct hwrm_cfa_flow_stats_input {
30437 /* The HWRM command request type. */
30440 * The completion ring to send the completion event on. This should
30441 * be the NQ ID returned from the `nq_alloc` HWRM command.
30443 uint16_t cmpl_ring;
30445 * The sequence ID is used by the driver for tracking multiple
30446 * commands. This ID is treated as opaque data by the firmware and
30447 * the value is returned in the `hwrm_resp_hdr` upon completion.
30451 * The target ID of the command:
30452 * * 0x0-0xFFF8 - The function ID
30453 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30454 * * 0xFFFD - Reserved for user-space HWRM interface
30457 uint16_t target_id;
30459 * A physical address pointer pointing to a host buffer that the
30460 * command's response data will be written. This can be either a host
30461 * physical address (HPA) or a guest physical address (GPA) and must
30462 * point to a physically contiguous block of memory.
30464 uint64_t resp_addr;
30466 uint16_t num_flows;
30468 uint16_t flow_handle_0;
30470 uint16_t flow_handle_1;
30472 uint16_t flow_handle_2;
30474 uint16_t flow_handle_3;
30476 uint16_t flow_handle_4;
30478 uint16_t flow_handle_5;
30480 uint16_t flow_handle_6;
30482 uint16_t flow_handle_7;
30484 uint16_t flow_handle_8;
30486 uint16_t flow_handle_9;
30487 uint8_t unused_0[2];
30488 /* Flow ID of a flow. */
30489 uint32_t flow_id_0;
30490 /* Flow ID of a flow. */
30491 uint32_t flow_id_1;
30492 /* Flow ID of a flow. */
30493 uint32_t flow_id_2;
30494 /* Flow ID of a flow. */
30495 uint32_t flow_id_3;
30496 /* Flow ID of a flow. */
30497 uint32_t flow_id_4;
30498 /* Flow ID of a flow. */
30499 uint32_t flow_id_5;
30500 /* Flow ID of a flow. */
30501 uint32_t flow_id_6;
30502 /* Flow ID of a flow. */
30503 uint32_t flow_id_7;
30504 /* Flow ID of a flow. */
30505 uint32_t flow_id_8;
30506 /* Flow ID of a flow. */
30507 uint32_t flow_id_9;
30510 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
30511 struct hwrm_cfa_flow_stats_output {
30512 /* The specific error status for the command. */
30513 uint16_t error_code;
30514 /* The HWRM command request type. */
30516 /* The sequence ID from the original command. */
30518 /* The length of the response data in number of bytes. */
30520 /* packet_0 is 64 b */
30522 /* packet_1 is 64 b */
30524 /* packet_2 is 64 b */
30526 /* packet_3 is 64 b */
30528 /* packet_4 is 64 b */
30530 /* packet_5 is 64 b */
30532 /* packet_6 is 64 b */
30534 /* packet_7 is 64 b */
30536 /* packet_8 is 64 b */
30538 /* packet_9 is 64 b */
30540 /* byte_0 is 64 b */
30542 /* byte_1 is 64 b */
30544 /* byte_2 is 64 b */
30546 /* byte_3 is 64 b */
30548 /* byte_4 is 64 b */
30550 /* byte_5 is 64 b */
30552 /* byte_6 is 64 b */
30554 /* byte_7 is 64 b */
30556 /* byte_8 is 64 b */
30558 /* byte_9 is 64 b */
30560 uint8_t unused_0[7];
30562 * This field is used in Output records to indicate that the output
30563 * is completely written to RAM. This field should be read as '1'
30564 * to indicate that the output has been completely written.
30565 * When writing a command completion or response to an internal processor,
30566 * the order of writes has to be such that this field is written last.
30571 /***********************************
30572 * hwrm_cfa_flow_aging_timer_reset *
30573 ***********************************/
30576 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
30577 struct hwrm_cfa_flow_aging_timer_reset_input {
30578 /* The HWRM command request type. */
30581 * The completion ring to send the completion event on. This should
30582 * be the NQ ID returned from the `nq_alloc` HWRM command.
30584 uint16_t cmpl_ring;
30586 * The sequence ID is used by the driver for tracking multiple
30587 * commands. This ID is treated as opaque data by the firmware and
30588 * the value is returned in the `hwrm_resp_hdr` upon completion.
30592 * The target ID of the command:
30593 * * 0x0-0xFFF8 - The function ID
30594 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30595 * * 0xFFFD - Reserved for user-space HWRM interface
30598 uint16_t target_id;
30600 * A physical address pointer pointing to a host buffer that the
30601 * command's response data will be written. This can be either a host
30602 * physical address (HPA) or a guest physical address (GPA) and must
30603 * point to a physically contiguous block of memory.
30605 uint64_t resp_addr;
30606 /* Flow record index. */
30607 uint16_t flow_handle;
30608 uint8_t unused_0[2];
30610 * New flow timer value for the flow specified in the ext_flow_handle.
30611 * The flow timer unit is 100ms.
30613 uint32_t flow_timer;
30614 /* This value identifies a set of CFA data structures used for a flow. */
30615 uint64_t ext_flow_handle;
30618 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
30619 struct hwrm_cfa_flow_aging_timer_reset_output {
30620 /* The specific error status for the command. */
30621 uint16_t error_code;
30622 /* The HWRM command request type. */
30624 /* The sequence ID from the original command. */
30626 /* The length of the response data in number of bytes. */
30628 uint8_t unused_0[7];
30630 * This field is used in Output records to indicate that the output
30631 * is completely written to RAM. This field should be read as '1'
30632 * to indicate that the output has been completely written.
30633 * When writing a command completion or response to an internal processor,
30634 * the order of writes has to be such that this field is written last.
30639 /***************************
30640 * hwrm_cfa_flow_aging_cfg *
30641 ***************************/
30644 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
30645 struct hwrm_cfa_flow_aging_cfg_input {
30646 /* The HWRM command request type. */
30649 * The completion ring to send the completion event on. This should
30650 * be the NQ ID returned from the `nq_alloc` HWRM command.
30652 uint16_t cmpl_ring;
30654 * The sequence ID is used by the driver for tracking multiple
30655 * commands. This ID is treated as opaque data by the firmware and
30656 * the value is returned in the `hwrm_resp_hdr` upon completion.
30660 * The target ID of the command:
30661 * * 0x0-0xFFF8 - The function ID
30662 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30663 * * 0xFFFD - Reserved for user-space HWRM interface
30666 uint16_t target_id;
30668 * A physical address pointer pointing to a host buffer that the
30669 * command's response data will be written. This can be either a host
30670 * physical address (HPA) or a guest physical address (GPA) and must
30671 * point to a physically contiguous block of memory.
30673 uint64_t resp_addr;
30674 /* The bit field to enable per flow aging configuration. */
30676 /* This bit must be '1' for the tcp flow timer field to be configured */
30677 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
30679 /* This bit must be '1' for the tcp finish timer field to be configured */
30680 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
30682 /* This bit must be '1' for the udp flow timer field to be configured */
30683 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
30685 /* This bit must be '1' for the eem dma interval field to be configured */
30686 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
30688 /* This bit must be '1' for the eem notice interval field to be configured */
30689 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
30691 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
30692 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
30694 /* This bit must be '1' for the eem context memory ID field to be configured */
30695 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
30697 /* This bit must be '1' for the eem context memory type field to be configured */
30698 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
30701 /* Enumeration denoting the RX, TX type of the resource. */
30702 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
30704 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30706 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30707 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
30708 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
30709 /* Enumeration denoting the enable, disable eem flow aging configuration. */
30710 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
30712 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
30713 (UINT32_C(0x0) << 1)
30715 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
30716 (UINT32_C(0x1) << 1)
30717 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
30718 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
30720 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
30721 uint32_t tcp_flow_timer;
30722 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
30723 uint32_t tcp_fin_timer;
30724 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
30725 uint32_t udp_flow_timer;
30726 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
30727 uint16_t eem_dma_interval;
30728 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
30729 uint16_t eem_notice_interval;
30730 /* The maximum entries number in the eem context memory. */
30731 uint32_t eem_ctx_max_entries;
30732 /* The context memory ID for eem flow aging. */
30733 uint16_t eem_ctx_id;
30734 uint16_t eem_ctx_mem_type;
30735 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
30736 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
30738 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
30739 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
30740 uint8_t unused_1[4];
30743 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
30744 struct hwrm_cfa_flow_aging_cfg_output {
30745 /* The specific error status for the command. */
30746 uint16_t error_code;
30747 /* The HWRM command request type. */
30749 /* The sequence ID from the original command. */
30751 /* The length of the response data in number of bytes. */
30753 uint8_t unused_0[7];
30755 * This field is used in Output records to indicate that the output
30756 * is completely written to RAM. This field should be read as '1'
30757 * to indicate that the output has been completely written.
30758 * When writing a command completion or response to an internal processor,
30759 * the order of writes has to be such that this field is written last.
30764 /****************************
30765 * hwrm_cfa_flow_aging_qcfg *
30766 ****************************/
30769 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
30770 struct hwrm_cfa_flow_aging_qcfg_input {
30771 /* The HWRM command request type. */
30774 * The completion ring to send the completion event on. This should
30775 * be the NQ ID returned from the `nq_alloc` HWRM command.
30777 uint16_t cmpl_ring;
30779 * The sequence ID is used by the driver for tracking multiple
30780 * commands. This ID is treated as opaque data by the firmware and
30781 * the value is returned in the `hwrm_resp_hdr` upon completion.
30785 * The target ID of the command:
30786 * * 0x0-0xFFF8 - The function ID
30787 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30788 * * 0xFFFD - Reserved for user-space HWRM interface
30791 uint16_t target_id;
30793 * A physical address pointer pointing to a host buffer that the
30794 * command's response data will be written. This can be either a host
30795 * physical address (HPA) or a guest physical address (GPA) and must
30796 * point to a physically contiguous block of memory.
30798 uint64_t resp_addr;
30799 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
30801 /* Enumeration denoting the RX, TX type of the resource. */
30802 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
30804 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30806 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30807 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
30808 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
30809 uint8_t unused_0[7];
30812 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
30813 struct hwrm_cfa_flow_aging_qcfg_output {
30814 /* The specific error status for the command. */
30815 uint16_t error_code;
30816 /* The HWRM command request type. */
30818 /* The sequence ID from the original command. */
30820 /* The length of the response data in number of bytes. */
30822 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
30823 uint32_t tcp_flow_timer;
30824 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
30825 uint32_t tcp_fin_timer;
30826 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
30827 uint32_t udp_flow_timer;
30828 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
30829 uint16_t eem_dma_interval;
30830 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
30831 uint16_t eem_notice_interval;
30832 /* The maximum entries number in the eem context memory. */
30833 uint32_t eem_ctx_max_entries;
30834 /* The context memory ID for eem flow aging. */
30835 uint16_t eem_ctx_id;
30836 /* The context memory type for eem flow aging. */
30837 uint16_t eem_ctx_mem_type;
30838 uint8_t unused_0[7];
30840 * This field is used in Output records to indicate that the output
30841 * is completely written to RAM. This field should be read as '1'
30842 * to indicate that the output has been completely written.
30843 * When writing a command completion or response to an internal processor,
30844 * the order of writes has to be such that this field is written last.
30849 /*****************************
30850 * hwrm_cfa_flow_aging_qcaps *
30851 *****************************/
30854 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
30855 struct hwrm_cfa_flow_aging_qcaps_input {
30856 /* The HWRM command request type. */
30859 * The completion ring to send the completion event on. This should
30860 * be the NQ ID returned from the `nq_alloc` HWRM command.
30862 uint16_t cmpl_ring;
30864 * The sequence ID is used by the driver for tracking multiple
30865 * commands. This ID is treated as opaque data by the firmware and
30866 * the value is returned in the `hwrm_resp_hdr` upon completion.
30870 * The target ID of the command:
30871 * * 0x0-0xFFF8 - The function ID
30872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30873 * * 0xFFFD - Reserved for user-space HWRM interface
30876 uint16_t target_id;
30878 * A physical address pointer pointing to a host buffer that the
30879 * command's response data will be written. This can be either a host
30880 * physical address (HPA) or a guest physical address (GPA) and must
30881 * point to a physically contiguous block of memory.
30883 uint64_t resp_addr;
30884 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
30886 /* Enumeration denoting the RX, TX type of the resource. */
30887 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
30889 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30891 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30892 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
30893 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
30894 uint8_t unused_0[7];
30897 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
30898 struct hwrm_cfa_flow_aging_qcaps_output {
30899 /* The specific error status for the command. */
30900 uint16_t error_code;
30901 /* The HWRM command request type. */
30903 /* The sequence ID from the original command. */
30905 /* The length of the response data in number of bytes. */
30907 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
30908 uint32_t max_tcp_flow_timer;
30909 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
30910 uint32_t max_tcp_fin_timer;
30911 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
30912 uint32_t max_udp_flow_timer;
30913 /* The maximum aging flows that HW can support. */
30914 uint32_t max_aging_flows;
30915 uint8_t unused_0[7];
30917 * This field is used in Output records to indicate that the output
30918 * is completely written to RAM. This field should be read as '1'
30919 * to indicate that the output has been completely written.
30920 * When writing a command completion or response to an internal processor,
30921 * the order of writes has to be such that this field is written last.
30926 /**********************************
30927 * hwrm_cfa_tcp_flag_process_qcfg *
30928 **********************************/
30931 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
30932 struct hwrm_cfa_tcp_flag_process_qcfg_input {
30933 /* The HWRM command request type. */
30936 * The completion ring to send the completion event on. This should
30937 * be the NQ ID returned from the `nq_alloc` HWRM command.
30939 uint16_t cmpl_ring;
30941 * The sequence ID is used by the driver for tracking multiple
30942 * commands. This ID is treated as opaque data by the firmware and
30943 * the value is returned in the `hwrm_resp_hdr` upon completion.
30947 * The target ID of the command:
30948 * * 0x0-0xFFF8 - The function ID
30949 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30950 * * 0xFFFD - Reserved for user-space HWRM interface
30953 uint16_t target_id;
30955 * A physical address pointer pointing to a host buffer that the
30956 * command's response data will be written. This can be either a host
30957 * physical address (HPA) or a guest physical address (GPA) and must
30958 * point to a physically contiguous block of memory.
30960 uint64_t resp_addr;
30963 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
30964 struct hwrm_cfa_tcp_flag_process_qcfg_output {
30965 /* The specific error status for the command. */
30966 uint16_t error_code;
30967 /* The HWRM command request type. */
30969 /* The sequence ID from the original command. */
30971 /* The length of the response data in number of bytes. */
30973 /* The port 0 RX mirror action record ID. */
30974 uint16_t rx_ar_id_port0;
30975 /* The port 1 RX mirror action record ID. */
30976 uint16_t rx_ar_id_port1;
30977 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
30978 uint16_t tx_ar_id_port0;
30979 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
30980 uint16_t tx_ar_id_port1;
30981 uint8_t unused_0[7];
30983 * This field is used in Output records to indicate that the output
30984 * is completely written to RAM. This field should be read as '1'
30985 * to indicate that the output has been completely written.
30986 * When writing a command completion or response to an internal processor,
30987 * the order of writes has to be such that this field is written last.
30992 /**********************
30993 * hwrm_cfa_pair_info *
30994 **********************/
30997 /* hwrm_cfa_pair_info_input (size:448b/56B) */
30998 struct hwrm_cfa_pair_info_input {
30999 /* The HWRM command request type. */
31002 * The completion ring to send the completion event on. This should
31003 * be the NQ ID returned from the `nq_alloc` HWRM command.
31005 uint16_t cmpl_ring;
31007 * The sequence ID is used by the driver for tracking multiple
31008 * commands. This ID is treated as opaque data by the firmware and
31009 * the value is returned in the `hwrm_resp_hdr` upon completion.
31013 * The target ID of the command:
31014 * * 0x0-0xFFF8 - The function ID
31015 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31016 * * 0xFFFD - Reserved for user-space HWRM interface
31019 uint16_t target_id;
31021 * A physical address pointer pointing to a host buffer that the
31022 * command's response data will be written. This can be either a host
31023 * physical address (HPA) or a guest physical address (GPA) and must
31024 * point to a physically contiguous block of memory.
31026 uint64_t resp_addr;
31028 /* If this flag is set, lookup by name else lookup by index. */
31029 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
31030 /* If this flag is set, lookup by PF id and VF id. */
31031 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
31032 /* Pair table index. */
31033 uint16_t pair_index;
31034 /* Pair pf index. */
31036 /* Pair vf index. */
31038 /* Pair name (32 byte string). */
31039 char pair_name[32];
31042 /* hwrm_cfa_pair_info_output (size:576b/72B) */
31043 struct hwrm_cfa_pair_info_output {
31044 /* The specific error status for the command. */
31045 uint16_t error_code;
31046 /* The HWRM command request type. */
31048 /* The sequence ID from the original command. */
31050 /* The length of the response data in number of bytes. */
31052 /* Pair table index. */
31053 uint16_t next_pair_index;
31054 /* Pair member a's fid. */
31056 /* Logical host number. */
31057 uint8_t host_a_index;
31058 /* Logical PF number. */
31059 uint8_t pf_a_index;
31060 /* Pair member a's Linux logical VF number. */
31061 uint16_t vf_a_index;
31063 uint16_t rx_cfa_code_a;
31064 /* Tx CFA action. */
31065 uint16_t tx_cfa_action_a;
31066 /* Pair member b's fid. */
31068 /* Logical host number. */
31069 uint8_t host_b_index;
31070 /* Logical PF number. */
31071 uint8_t pf_b_index;
31072 /* Pair member a's Linux logical VF number. */
31073 uint16_t vf_b_index;
31075 uint16_t rx_cfa_code_b;
31076 /* Tx CFA action. */
31077 uint16_t tx_cfa_action_b;
31078 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
31080 /* Pair between VF on local host with PF or VF on specified host. */
31081 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
31082 /* Pair between REP on local host with PF or VF on specified host. */
31083 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
31084 /* Pair between REP on local host with REP on specified host. */
31085 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
31086 /* Pair for the proxy interface. */
31087 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
31088 /* Pair for the PF interface. */
31089 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
31090 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
31091 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
31093 uint8_t pair_state;
31094 /* Pair has been allocated */
31095 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
31096 /* Both pair members are active */
31097 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
31098 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
31099 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
31100 /* Pair name (32 byte string). */
31101 char pair_name[32];
31102 uint8_t unused_0[7];
31104 * This field is used in Output records to indicate that the output
31105 * is completely written to RAM. This field should be read as '1'
31106 * to indicate that the output has been completely written.
31107 * When writing a command completion or response to an internal processor,
31108 * the order of writes has to be such that this field is written last.
31113 /***************************************
31114 * hwrm_cfa_redirect_query_tunnel_type *
31115 ***************************************/
31118 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
31119 struct hwrm_cfa_redirect_query_tunnel_type_input {
31120 /* The HWRM command request type. */
31123 * The completion ring to send the completion event on. This should
31124 * be the NQ ID returned from the `nq_alloc` HWRM command.
31126 uint16_t cmpl_ring;
31128 * The sequence ID is used by the driver for tracking multiple
31129 * commands. This ID is treated as opaque data by the firmware and
31130 * the value is returned in the `hwrm_resp_hdr` upon completion.
31134 * The target ID of the command:
31135 * * 0x0-0xFFF8 - The function ID
31136 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31137 * * 0xFFFD - Reserved for user-space HWRM interface
31140 uint16_t target_id;
31142 * A physical address pointer pointing to a host buffer that the
31143 * command's response data will be written. This can be either a host
31144 * physical address (HPA) or a guest physical address (GPA) and must
31145 * point to a physically contiguous block of memory.
31147 uint64_t resp_addr;
31148 /* The source function id. */
31150 uint8_t unused_0[6];
31153 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
31154 struct hwrm_cfa_redirect_query_tunnel_type_output {
31155 /* The specific error status for the command. */
31156 uint16_t error_code;
31157 /* The HWRM command request type. */
31159 /* The sequence ID from the original command. */
31161 /* The length of the response data in number of bytes. */
31164 uint32_t tunnel_mask;
31166 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
31168 /* Virtual eXtensible Local Area Network (VXLAN) */
31169 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
31171 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31172 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
31174 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31175 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
31178 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
31180 /* Generic Network Virtualization Encapsulation (Geneve) */
31181 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
31183 /* Multi-Protocol Label Switching (MPLS) */
31184 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
31186 /* Stateless Transport Tunnel (STT) */
31187 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
31189 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31190 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
31192 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31193 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
31195 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31196 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
31198 /* Any tunneled traffic */
31199 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
31201 /* Use fixed layer 2 ether type of 0xFFFF */
31202 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
31204 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31205 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
31207 uint8_t unused_0[3];
31209 * This field is used in Output records to indicate that the output
31210 * is completely written to RAM. This field should be read as '1'
31211 * to indicate that the output has been completely written.
31212 * When writing a command completion or response to an internal processor,
31213 * the order of writes has to be such that this field is written last.
31218 /*************************
31219 * hwrm_cfa_ctx_mem_rgtr *
31220 *************************/
31223 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
31224 struct hwrm_cfa_ctx_mem_rgtr_input {
31225 /* The HWRM command request type. */
31228 * The completion ring to send the completion event on. This should
31229 * be the NQ ID returned from the `nq_alloc` HWRM command.
31231 uint16_t cmpl_ring;
31233 * The sequence ID is used by the driver for tracking multiple
31234 * commands. This ID is treated as opaque data by the firmware and
31235 * the value is returned in the `hwrm_resp_hdr` upon completion.
31239 * The target ID of the command:
31240 * * 0x0-0xFFF8 - The function ID
31241 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31242 * * 0xFFFD - Reserved for user-space HWRM interface
31245 uint16_t target_id;
31247 * A physical address pointer pointing to a host buffer that the
31248 * command's response data will be written. This can be either a host
31249 * physical address (HPA) or a guest physical address (GPA) and must
31250 * point to a physically contiguous block of memory.
31252 uint64_t resp_addr;
31254 /* Counter PBL indirect levels. */
31255 uint8_t page_level;
31256 /* PBL pointer is physical start address. */
31257 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
31258 /* PBL pointer points to PTE table. */
31259 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
31260 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
31261 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
31262 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
31263 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
31266 /* 4KB page size. */
31267 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
31268 /* 8KB page size. */
31269 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
31270 /* 64KB page size. */
31271 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
31272 /* 256KB page size. */
31273 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
31274 /* 1MB page size. */
31275 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
31276 /* 2MB page size. */
31277 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
31278 /* 4MB page size. */
31279 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
31280 /* 1GB page size. */
31281 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
31282 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
31283 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
31285 /* Pointer to the PBL, or PDL depending on number of levels */
31289 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
31290 struct hwrm_cfa_ctx_mem_rgtr_output {
31291 /* The specific error status for the command. */
31292 uint16_t error_code;
31293 /* The HWRM command request type. */
31295 /* The sequence ID from the original command. */
31297 /* The length of the response data in number of bytes. */
31300 * Id/Handle to the recently register context memory. This handle is passed
31301 * to the CFA feature.
31304 uint8_t unused_0[5];
31306 * This field is used in Output records to indicate that the output
31307 * is completely written to RAM. This field should be read as '1'
31308 * to indicate that the output has been completely written.
31309 * When writing a command completion or response to an internal processor,
31310 * the order of writes has to be such that this field is written last.
31315 /***************************
31316 * hwrm_cfa_ctx_mem_unrgtr *
31317 ***************************/
31320 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
31321 struct hwrm_cfa_ctx_mem_unrgtr_input {
31322 /* The HWRM command request type. */
31325 * The completion ring to send the completion event on. This should
31326 * be the NQ ID returned from the `nq_alloc` HWRM command.
31328 uint16_t cmpl_ring;
31330 * The sequence ID is used by the driver for tracking multiple
31331 * commands. This ID is treated as opaque data by the firmware and
31332 * the value is returned in the `hwrm_resp_hdr` upon completion.
31336 * The target ID of the command:
31337 * * 0x0-0xFFF8 - The function ID
31338 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31339 * * 0xFFFD - Reserved for user-space HWRM interface
31342 uint16_t target_id;
31344 * A physical address pointer pointing to a host buffer that the
31345 * command's response data will be written. This can be either a host
31346 * physical address (HPA) or a guest physical address (GPA) and must
31347 * point to a physically contiguous block of memory.
31349 uint64_t resp_addr;
31351 * Id/Handle to the recently register context memory. This handle is passed
31352 * to the CFA feature.
31355 uint8_t unused_0[6];
31358 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
31359 struct hwrm_cfa_ctx_mem_unrgtr_output {
31360 /* The specific error status for the command. */
31361 uint16_t error_code;
31362 /* The HWRM command request type. */
31364 /* The sequence ID from the original command. */
31366 /* The length of the response data in number of bytes. */
31368 uint8_t unused_0[7];
31370 * This field is used in Output records to indicate that the output
31371 * is completely written to RAM. This field should be read as '1'
31372 * to indicate that the output has been completely written.
31373 * When writing a command completion or response to an internal processor,
31374 * the order of writes has to be such that this field is written last.
31379 /*************************
31380 * hwrm_cfa_ctx_mem_qctx *
31381 *************************/
31384 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
31385 struct hwrm_cfa_ctx_mem_qctx_input {
31386 /* The HWRM command request type. */
31389 * The completion ring to send the completion event on. This should
31390 * be the NQ ID returned from the `nq_alloc` HWRM command.
31392 uint16_t cmpl_ring;
31394 * The sequence ID is used by the driver for tracking multiple
31395 * commands. This ID is treated as opaque data by the firmware and
31396 * the value is returned in the `hwrm_resp_hdr` upon completion.
31400 * The target ID of the command:
31401 * * 0x0-0xFFF8 - The function ID
31402 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31403 * * 0xFFFD - Reserved for user-space HWRM interface
31406 uint16_t target_id;
31408 * A physical address pointer pointing to a host buffer that the
31409 * command's response data will be written. This can be either a host
31410 * physical address (HPA) or a guest physical address (GPA) and must
31411 * point to a physically contiguous block of memory.
31413 uint64_t resp_addr;
31415 * Id/Handle to the recently register context memory. This handle is passed
31416 * to the CFA feature.
31419 uint8_t unused_0[6];
31422 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
31423 struct hwrm_cfa_ctx_mem_qctx_output {
31424 /* The specific error status for the command. */
31425 uint16_t error_code;
31426 /* The HWRM command request type. */
31428 /* The sequence ID from the original command. */
31430 /* The length of the response data in number of bytes. */
31433 /* Counter PBL indirect levels. */
31434 uint8_t page_level;
31435 /* PBL pointer is physical start address. */
31436 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
31437 /* PBL pointer points to PTE table. */
31438 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
31439 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
31440 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
31441 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
31442 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
31445 /* 4KB page size. */
31446 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
31447 /* 8KB page size. */
31448 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
31449 /* 64KB page size. */
31450 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
31451 /* 256KB page size. */
31452 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
31453 /* 1MB page size. */
31454 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
31455 /* 2MB page size. */
31456 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
31457 /* 4MB page size. */
31458 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
31459 /* 1GB page size. */
31460 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
31461 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
31462 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
31463 uint8_t unused_0[4];
31464 /* Pointer to the PBL, or PDL depending on number of levels */
31466 uint8_t unused_1[7];
31468 * This field is used in Output records to indicate that the output
31469 * is completely written to RAM. This field should be read as '1'
31470 * to indicate that the output has been completely written.
31471 * When writing a command completion or response to an internal processor,
31472 * the order of writes has to be such that this field is written last.
31477 /**************************
31478 * hwrm_cfa_ctx_mem_qcaps *
31479 **************************/
31482 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
31483 struct hwrm_cfa_ctx_mem_qcaps_input {
31484 /* The HWRM command request type. */
31487 * The completion ring to send the completion event on. This should
31488 * be the NQ ID returned from the `nq_alloc` HWRM command.
31490 uint16_t cmpl_ring;
31492 * The sequence ID is used by the driver for tracking multiple
31493 * commands. This ID is treated as opaque data by the firmware and
31494 * the value is returned in the `hwrm_resp_hdr` upon completion.
31498 * The target ID of the command:
31499 * * 0x0-0xFFF8 - The function ID
31500 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31501 * * 0xFFFD - Reserved for user-space HWRM interface
31504 uint16_t target_id;
31506 * A physical address pointer pointing to a host buffer that the
31507 * command's response data will be written. This can be either a host
31508 * physical address (HPA) or a guest physical address (GPA) and must
31509 * point to a physically contiguous block of memory.
31511 uint64_t resp_addr;
31514 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
31515 struct hwrm_cfa_ctx_mem_qcaps_output {
31516 /* The specific error status for the command. */
31517 uint16_t error_code;
31518 /* The HWRM command request type. */
31520 /* The sequence ID from the original command. */
31522 /* The length of the response data in number of bytes. */
31524 /* Indicates the maximum number of context memory which can be registered. */
31525 uint16_t max_entries;
31526 uint8_t unused_0[5];
31528 * This field is used in Output records to indicate that the output
31529 * is completely written to RAM. This field should be read as '1'
31530 * to indicate that the output has been completely written.
31531 * When writing a command completion or response to an internal processor,
31532 * the order of writes has to be such that this field is written last.
31537 /**********************
31538 * hwrm_cfa_eem_qcaps *
31539 **********************/
31542 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
31543 struct hwrm_cfa_eem_qcaps_input {
31544 /* The HWRM command request type. */
31547 * The completion ring to send the completion event on. This should
31548 * be the NQ ID returned from the `nq_alloc` HWRM command.
31550 uint16_t cmpl_ring;
31552 * The sequence ID is used by the driver for tracking multiple
31553 * commands. This ID is treated as opaque data by the firmware and
31554 * the value is returned in the `hwrm_resp_hdr` upon completion.
31558 * The target ID of the command:
31559 * * 0x0-0xFFF8 - The function ID
31560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31561 * * 0xFFFD - Reserved for user-space HWRM interface
31564 uint16_t target_id;
31566 * A physical address pointer pointing to a host buffer that the
31567 * command's response data will be written. This can be either a host
31568 * physical address (HPA) or a guest physical address (GPA) and must
31569 * point to a physically contiguous block of memory.
31571 uint64_t resp_addr;
31574 * When set to 1, indicates the configuration will apply to TX flows
31575 * which are to be offloaded.
31576 * Note if this bit is set then the path_rx bit can't be set.
31578 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
31581 * When set to 1, indicates the configuration will apply to RX flows
31582 * which are to be offloaded.
31583 * Note if this bit is set then the path_tx bit can't be set.
31585 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
31587 /* When set to 1, all offloaded flows will be sent to EEM. */
31588 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
31593 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
31594 struct hwrm_cfa_eem_qcaps_output {
31595 /* The specific error status for the command. */
31596 uint16_t error_code;
31597 /* The HWRM command request type. */
31599 /* The sequence ID from the original command. */
31601 /* The length of the response data in number of bytes. */
31605 * When set to 1, indicates the configuration will apply to TX flows
31606 * which are to be offloaded.
31607 * Note if this bit is set then the path_rx bit can't be set.
31609 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
31612 * When set to 1, indicates the configuration will apply to RX flows
31613 * which are to be offloaded.
31614 * Note if this bit is set then the path_tx bit can't be set.
31616 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
31619 * When set to 1, indicates the the FW supports the Centralized
31620 * Memory Model. The concept designates one entity for the
31621 * memory allocation while all others ‘subscribe’ to it.
31623 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
31626 * When set to 1, indicates the the FW supports the Detached
31627 * Centralized Memory Model. The memory is allocated and managed
31628 * as a separate entity. All PFs and VFs will be granted direct
31629 * or semi-direct access to the allocated memory while none of
31630 * which can interfere with the management of the memory.
31632 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
31635 uint32_t supported;
31637 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
31638 * If set to 0, EEM KEY0 table is not supported.
31640 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
31643 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
31644 * If set to 0, EEM KEY1 table is not supported.
31646 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
31649 * If set to 1, then EEM External Record table is supported.
31650 * If set to 0, EEM External Record table is not supported.
31651 * (This table includes action record, EFC pointers, encap pointers)
31653 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
31656 * If set to 1, then EEM External Flow Counters table is supported.
31657 * If set to 0, EEM External Flow Counters table is not supported.
31659 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
31662 * If set to 1, then FID table used for implicit flow flush is supported.
31663 * If set to 0, then FID table used for implicit flow flush is not supported.
31665 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
31668 * The maximum number of entries supported by EEM. When configuring the host memory
31669 * the number of numbers of entries that can supported are -
31670 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
31671 * Any value that are not these values, the FW will round down to the closest support
31672 * number of entries.
31674 uint32_t max_entries_supported;
31675 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
31676 uint16_t key_entry_size;
31677 /* The entry size in bytes of each entry in the EEM RECORD tables. */
31678 uint16_t record_entry_size;
31679 /* The entry size in bytes of each entry in the EEM EFC tables. */
31680 uint16_t efc_entry_size;
31681 /* The FID size in bytes of each entry in the EEM FID tables. */
31682 uint16_t fid_entry_size;
31683 uint8_t unused_1[7];
31685 * This field is used in Output records to indicate that the output
31686 * is completely written to RAM. This field should be read as '1'
31687 * to indicate that the output has been completely written.
31688 * When writing a command completion or response to an internal processor,
31689 * the order of writes has to be such that this field is written last.
31694 /********************
31695 * hwrm_cfa_eem_cfg *
31696 ********************/
31699 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
31700 struct hwrm_cfa_eem_cfg_input {
31701 /* The HWRM command request type. */
31704 * The completion ring to send the completion event on. This should
31705 * be the NQ ID returned from the `nq_alloc` HWRM command.
31707 uint16_t cmpl_ring;
31709 * The sequence ID is used by the driver for tracking multiple
31710 * commands. This ID is treated as opaque data by the firmware and
31711 * the value is returned in the `hwrm_resp_hdr` upon completion.
31715 * The target ID of the command:
31716 * * 0x0-0xFFF8 - The function ID
31717 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31718 * * 0xFFFD - Reserved for user-space HWRM interface
31721 uint16_t target_id;
31723 * A physical address pointer pointing to a host buffer that the
31724 * command's response data will be written. This can be either a host
31725 * physical address (HPA) or a guest physical address (GPA) and must
31726 * point to a physically contiguous block of memory.
31728 uint64_t resp_addr;
31731 * When set to 1, indicates the configuration will apply to TX flows
31732 * which are to be offloaded.
31733 * Note if this bit is set then the path_rx bit can't be set.
31735 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
31738 * When set to 1, indicates the configuration will apply to RX flows
31739 * which are to be offloaded.
31740 * Note if this bit is set then the path_tx bit can't be set.
31742 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
31744 /* When set to 1, all offloaded flows will be sent to EEM. */
31745 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
31747 /* When set to 1, secondary, 0 means primary. */
31748 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
31751 * Group_id which used by Firmware to identify memory pools belonging
31752 * to certain group.
31757 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
31758 * RECORD, EFC all have the same number of entries and all tables will be configured
31759 * using this value. Current minimum value is 32k. Current maximum value is 128M.
31761 uint32_t num_entries;
31763 /* Configured EEM with the given context if for KEY0 table. */
31764 uint16_t key0_ctx_id;
31765 /* Configured EEM with the given context if for KEY1 table. */
31766 uint16_t key1_ctx_id;
31767 /* Configured EEM with the given context if for RECORD table. */
31768 uint16_t record_ctx_id;
31769 /* Configured EEM with the given context if for EFC table. */
31770 uint16_t efc_ctx_id;
31771 /* Configured EEM with the given context if for EFC table. */
31772 uint16_t fid_ctx_id;
31777 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
31778 struct hwrm_cfa_eem_cfg_output {
31779 /* The specific error status for the command. */
31780 uint16_t error_code;
31781 /* The HWRM command request type. */
31783 /* The sequence ID from the original command. */
31785 /* The length of the response data in number of bytes. */
31787 uint8_t unused_0[7];
31789 * This field is used in Output records to indicate that the output
31790 * is completely written to RAM. This field should be read as '1'
31791 * to indicate that the output has been completely written.
31792 * When writing a command completion or response to an internal processor,
31793 * the order of writes has to be such that this field is written last.
31798 /*********************
31799 * hwrm_cfa_eem_qcfg *
31800 *********************/
31803 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
31804 struct hwrm_cfa_eem_qcfg_input {
31805 /* The HWRM command request type. */
31808 * The completion ring to send the completion event on. This should
31809 * be the NQ ID returned from the `nq_alloc` HWRM command.
31811 uint16_t cmpl_ring;
31813 * The sequence ID is used by the driver for tracking multiple
31814 * commands. This ID is treated as opaque data by the firmware and
31815 * the value is returned in the `hwrm_resp_hdr` upon completion.
31819 * The target ID of the command:
31820 * * 0x0-0xFFF8 - The function ID
31821 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31822 * * 0xFFFD - Reserved for user-space HWRM interface
31825 uint16_t target_id;
31827 * A physical address pointer pointing to a host buffer that the
31828 * command's response data will be written. This can be either a host
31829 * physical address (HPA) or a guest physical address (GPA) and must
31830 * point to a physically contiguous block of memory.
31832 uint64_t resp_addr;
31834 /* When set to 1, indicates the configuration is the TX flow. */
31835 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
31836 /* When set to 1, indicates the configuration is the RX flow. */
31837 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
31841 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
31842 struct hwrm_cfa_eem_qcfg_output {
31843 /* The specific error status for the command. */
31844 uint16_t error_code;
31845 /* The HWRM command request type. */
31847 /* The sequence ID from the original command. */
31849 /* The length of the response data in number of bytes. */
31852 /* When set to 1, indicates the configuration is the TX flow. */
31853 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
31855 /* When set to 1, indicates the configuration is the RX flow. */
31856 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
31858 /* When set to 1, all offloaded flows will be sent to EEM. */
31859 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
31861 /* The number of entries the FW has configured for EEM. */
31862 uint32_t num_entries;
31863 /* Configured EEM with the given context if for KEY0 table. */
31864 uint16_t key0_ctx_id;
31865 /* Configured EEM with the given context if for KEY1 table. */
31866 uint16_t key1_ctx_id;
31867 /* Configured EEM with the given context if for RECORD table. */
31868 uint16_t record_ctx_id;
31869 /* Configured EEM with the given context if for EFC table. */
31870 uint16_t efc_ctx_id;
31871 /* Configured EEM with the given context if for EFC table. */
31872 uint16_t fid_ctx_id;
31873 uint8_t unused_2[5];
31875 * This field is used in Output records to indicate that the output
31876 * is completely written to RAM. This field should be read as '1'
31877 * to indicate that the output has been completely written.
31878 * When writing a command completion or response to an internal processor,
31879 * the order of writes has to be such that this field is written last.
31884 /*******************
31885 * hwrm_cfa_eem_op *
31886 *******************/
31889 /* hwrm_cfa_eem_op_input (size:192b/24B) */
31890 struct hwrm_cfa_eem_op_input {
31891 /* The HWRM command request type. */
31894 * The completion ring to send the completion event on. This should
31895 * be the NQ ID returned from the `nq_alloc` HWRM command.
31897 uint16_t cmpl_ring;
31899 * The sequence ID is used by the driver for tracking multiple
31900 * commands. This ID is treated as opaque data by the firmware and
31901 * the value is returned in the `hwrm_resp_hdr` upon completion.
31905 * The target ID of the command:
31906 * * 0x0-0xFFF8 - The function ID
31907 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31908 * * 0xFFFD - Reserved for user-space HWRM interface
31911 uint16_t target_id;
31913 * A physical address pointer pointing to a host buffer that the
31914 * command's response data will be written. This can be either a host
31915 * physical address (HPA) or a guest physical address (GPA) and must
31916 * point to a physically contiguous block of memory.
31918 uint64_t resp_addr;
31921 * When set to 1, indicates the host memory which is passed will be
31922 * used for the TX flow offload function specified in fid.
31923 * Note if this bit is set then the path_rx bit can't be set.
31925 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
31927 * When set to 1, indicates the host memory which is passed will be
31928 * used for the RX flow offload function specified in fid.
31929 * Note if this bit is set then the path_tx bit can't be set.
31931 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
31933 /* The number of EEM key table entries to be configured. */
31935 /* This value is reserved and should not be used. */
31936 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
31938 * To properly stop EEM and ensure there are no DMA's, the caller
31939 * must disable EEM for the given PF, using this call. This will
31940 * safely disable EEM and ensure that all DMA'ed to the
31941 * keys/records/efc have been completed.
31943 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
31945 * Once the EEM host memory has been configured, EEM options have
31946 * been configured. Then the caller should enable EEM for the given
31947 * PF. Note once this call has been made, then the EEM mechanism
31948 * will be active and DMA's will occur as packets are processed.
31950 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
31952 * Clear EEM settings for the given PF so that the register values
31953 * are reset back to there initial state.
31955 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
31956 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
31957 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
31960 /* hwrm_cfa_eem_op_output (size:128b/16B) */
31961 struct hwrm_cfa_eem_op_output {
31962 /* The specific error status for the command. */
31963 uint16_t error_code;
31964 /* The HWRM command request type. */
31966 /* The sequence ID from the original command. */
31968 /* The length of the response data in number of bytes. */
31970 uint8_t unused_0[7];
31972 * This field is used in Output records to indicate that the output
31973 * is completely written to RAM. This field should be read as '1'
31974 * to indicate that the output has been completely written.
31975 * When writing a command completion or response to an internal processor,
31976 * the order of writes has to be such that this field is written last.
31981 /********************************
31982 * hwrm_cfa_adv_flow_mgnt_qcaps *
31983 ********************************/
31986 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
31987 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
31988 /* The HWRM command request type. */
31991 * The completion ring to send the completion event on. This should
31992 * be the NQ ID returned from the `nq_alloc` HWRM command.
31994 uint16_t cmpl_ring;
31996 * The sequence ID is used by the driver for tracking multiple
31997 * commands. This ID is treated as opaque data by the firmware and
31998 * the value is returned in the `hwrm_resp_hdr` upon completion.
32002 * The target ID of the command:
32003 * * 0x0-0xFFF8 - The function ID
32004 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32005 * * 0xFFFD - Reserved for user-space HWRM interface
32008 uint16_t target_id;
32010 * A physical address pointer pointing to a host buffer that the
32011 * command's response data will be written. This can be either a host
32012 * physical address (HPA) or a guest physical address (GPA) and must
32013 * point to a physically contiguous block of memory.
32015 uint64_t resp_addr;
32016 uint32_t unused_0[4];
32019 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
32020 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
32021 /* The specific error status for the command. */
32022 uint16_t error_code;
32023 /* The HWRM command request type. */
32025 /* The sequence ID from the original command. */
32027 /* The length of the response data in number of bytes. */
32031 * Value of 1 to indicate firmware support 16-bit flow handle.
32032 * Value of 0 to indicate firmware not support 16-bit flow handle.
32034 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
32037 * Value of 1 to indicate firmware support 64-bit flow handle.
32038 * Value of 0 to indicate firmware not support 64-bit flow handle.
32040 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
32043 * Value of 1 to indicate firmware support flow batch delete operation through
32044 * HWRM_CFA_FLOW_FLUSH command.
32045 * Value of 0 to indicate that the firmware does not support flow batch delete
32048 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
32051 * Value of 1 to indicate that the firmware support flow reset all operation through
32052 * HWRM_CFA_FLOW_FLUSH command.
32053 * Value of 0 indicates firmware does not support flow reset all operation.
32055 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
32058 * Value of 1 to indicate that firmware supports use of FID as dest_id in
32059 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
32060 * Value of 0 indicates firmware does not support use of FID as dest_id.
32062 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
32065 * Value of 1 to indicate that firmware supports TX EEM flows.
32066 * Value of 0 indicates firmware does not support TX EEM flows.
32068 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
32071 * Value of 1 to indicate that firmware supports RX EEM flows.
32072 * Value of 0 indicates firmware does not support RX EEM flows.
32074 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
32077 * Value of 1 to indicate that firmware supports the dynamic allocation of an
32078 * on-chip flow counter which can be used for EEM flows.
32079 * Value of 0 indicates firmware does not support the dynamic allocation of an
32080 * on-chip flow counter.
32082 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
32085 * Value of 1 to indicate that firmware supports setting of
32086 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
32087 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
32089 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
32092 * Value of 1 to indicate that firmware supports untagged matching
32093 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
32094 * indicates firmware does not support untagged matching.
32096 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
32099 * Value of 1 to indicate that firmware supports XDP filter. Value
32100 * of 0 indicates firmware does not support XDP filter.
32102 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
32105 * Value of 1 to indicate that the firmware support L2 header source
32106 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
32107 * Value of 0 indicates firmware does not support L2 header source
32110 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
32113 * If set to 1, firmware is capable of supporting ARP ethertype as
32114 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
32115 * RX direction. By default, this flag should be 0 for older version
32118 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
32121 * Value of 1 to indicate that firmware supports setting of
32122 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
32123 * command. Value of 0 indicates firmware does not support
32124 * rfs_ring_tbl_idx in dst_id field.
32126 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
32129 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
32130 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
32131 * direction. By default, this flag should be 0 for older version
32134 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
32136 uint8_t unused_0[3];
32138 * This field is used in Output records to indicate that the output
32139 * is completely written to RAM. This field should be read as '1'
32140 * to indicate that the output has been completely written.
32141 * When writing a command completion or response to an internal processor,
32142 * the order of writes has to be such that this field is written last.
32147 /******************
32149 ******************/
32152 /* hwrm_cfa_tflib_input (size:1024b/128B) */
32153 struct hwrm_cfa_tflib_input {
32154 /* The HWRM command request type. */
32157 * The completion ring to send the completion event on. This should
32158 * be the NQ ID returned from the `nq_alloc` HWRM command.
32160 uint16_t cmpl_ring;
32162 * The sequence ID is used by the driver for tracking multiple
32163 * commands. This ID is treated as opaque data by the firmware and
32164 * the value is returned in the `hwrm_resp_hdr` upon completion.
32168 * The target ID of the command:
32169 * * 0x0-0xFFF8 - The function ID
32170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32171 * * 0xFFFD - Reserved for user-space HWRM interface
32174 uint16_t target_id;
32176 * A physical address pointer pointing to a host buffer that the
32177 * command's response data will be written. This can be either a host
32178 * physical address (HPA) or a guest physical address (GPA) and must
32179 * point to a physically contiguous block of memory.
32181 uint64_t resp_addr;
32182 /* TFLIB message type. */
32184 /* TFLIB message subtype. */
32185 uint16_t tf_subtype;
32187 uint8_t unused0[4];
32188 /* TFLIB request data. */
32189 uint32_t tf_req[26];
32192 /* hwrm_cfa_tflib_output (size:5632b/704B) */
32193 struct hwrm_cfa_tflib_output {
32194 /* The specific error status for the command. */
32195 uint16_t error_code;
32196 /* The HWRM command request type. */
32198 /* The sequence ID from the original command. */
32200 /* The length of the response data in number of bytes. */
32202 /* TFLIB message type. */
32204 /* TFLIB message subtype. */
32205 uint16_t tf_subtype;
32206 /* TFLIB response code */
32207 uint32_t tf_resp_code;
32208 /* TFLIB response data. */
32209 uint32_t tf_resp[170];
32211 uint8_t unused1[7];
32213 * This field is used in Output records to indicate that the output
32214 * is completely written to RAM. This field should be read as '1'
32215 * to indicate that the output has been completely written.
32216 * When writing a command completion or response to an internal processor,
32217 * the order of writes has to be such that this field is written last.
32222 /******************************
32223 * hwrm_tunnel_dst_port_query *
32224 ******************************/
32227 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
32228 struct hwrm_tunnel_dst_port_query_input {
32229 /* The HWRM command request type. */
32232 * The completion ring to send the completion event on. This should
32233 * be the NQ ID returned from the `nq_alloc` HWRM command.
32235 uint16_t cmpl_ring;
32237 * The sequence ID is used by the driver for tracking multiple
32238 * commands. This ID is treated as opaque data by the firmware and
32239 * the value is returned in the `hwrm_resp_hdr` upon completion.
32243 * The target ID of the command:
32244 * * 0x0-0xFFF8 - The function ID
32245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32246 * * 0xFFFD - Reserved for user-space HWRM interface
32249 uint16_t target_id;
32251 * A physical address pointer pointing to a host buffer that the
32252 * command's response data will be written. This can be either a host
32253 * physical address (HPA) or a guest physical address (GPA) and must
32254 * point to a physically contiguous block of memory.
32256 uint64_t resp_addr;
32258 uint8_t tunnel_type;
32259 /* Virtual eXtensible Local Area Network (VXLAN) */
32260 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
32262 /* Generic Network Virtualization Encapsulation (Geneve) */
32263 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
32265 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32266 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32268 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32269 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32271 /* Use fixed layer 2 ether type of 0xFFFF */
32272 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
32274 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32275 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32277 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
32278 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
32279 uint8_t unused_0[7];
32282 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
32283 struct hwrm_tunnel_dst_port_query_output {
32284 /* The specific error status for the command. */
32285 uint16_t error_code;
32286 /* The HWRM command request type. */
32288 /* The sequence ID from the original command. */
32290 /* The length of the response data in number of bytes. */
32293 * This field represents the identifier of L4 destination port
32294 * used for the given tunnel type. This field is valid for
32295 * specific tunnel types that use layer 4 (e.g. UDP)
32296 * transports for tunneling.
32298 uint16_t tunnel_dst_port_id;
32300 * This field represents the value of L4 destination port
32301 * identified by tunnel_dst_port_id. This field is valid for
32302 * specific tunnel types that use layer 4 (e.g. UDP)
32303 * transports for tunneling.
32304 * This field is in network byte order.
32306 * A value of 0 means that the destination port is not
32309 uint16_t tunnel_dst_port_val;
32310 uint8_t unused_0[3];
32312 * This field is used in Output records to indicate that the output
32313 * is completely written to RAM. This field should be read as '1'
32314 * to indicate that the output has been completely written.
32315 * When writing a command completion or response to an internal processor,
32316 * the order of writes has to be such that this field is written last.
32321 /******************************
32322 * hwrm_tunnel_dst_port_alloc *
32323 ******************************/
32326 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
32327 struct hwrm_tunnel_dst_port_alloc_input {
32328 /* The HWRM command request type. */
32331 * The completion ring to send the completion event on. This should
32332 * be the NQ ID returned from the `nq_alloc` HWRM command.
32334 uint16_t cmpl_ring;
32336 * The sequence ID is used by the driver for tracking multiple
32337 * commands. This ID is treated as opaque data by the firmware and
32338 * the value is returned in the `hwrm_resp_hdr` upon completion.
32342 * The target ID of the command:
32343 * * 0x0-0xFFF8 - The function ID
32344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32345 * * 0xFFFD - Reserved for user-space HWRM interface
32348 uint16_t target_id;
32350 * A physical address pointer pointing to a host buffer that the
32351 * command's response data will be written. This can be either a host
32352 * physical address (HPA) or a guest physical address (GPA) and must
32353 * point to a physically contiguous block of memory.
32355 uint64_t resp_addr;
32357 uint8_t tunnel_type;
32358 /* Virtual eXtensible Local Area Network (VXLAN) */
32359 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
32361 /* Generic Network Virtualization Encapsulation (Geneve) */
32362 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
32364 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32365 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32367 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32368 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32370 /* Use fixed layer 2 ether type of 0xFFFF */
32371 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
32373 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32374 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32376 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
32377 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
32380 * This field represents the value of L4 destination port used
32381 * for the given tunnel type. This field is valid for
32382 * specific tunnel types that use layer 4 (e.g. UDP)
32383 * transports for tunneling.
32385 * This field is in network byte order.
32387 * A value of 0 shall fail the command.
32389 uint16_t tunnel_dst_port_val;
32390 uint8_t unused_1[4];
32393 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
32394 struct hwrm_tunnel_dst_port_alloc_output {
32395 /* The specific error status for the command. */
32396 uint16_t error_code;
32397 /* The HWRM command request type. */
32399 /* The sequence ID from the original command. */
32401 /* The length of the response data in number of bytes. */
32404 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
32405 * types that has l4 destination port parameters.
32407 uint16_t tunnel_dst_port_id;
32408 uint8_t unused_0[5];
32410 * This field is used in Output records to indicate that the output
32411 * is completely written to RAM. This field should be read as '1'
32412 * to indicate that the output has been completely written.
32413 * When writing a command completion or response to an internal processor,
32414 * the order of writes has to be such that this field is written last.
32419 /*****************************
32420 * hwrm_tunnel_dst_port_free *
32421 *****************************/
32424 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
32425 struct hwrm_tunnel_dst_port_free_input {
32426 /* The HWRM command request type. */
32429 * The completion ring to send the completion event on. This should
32430 * be the NQ ID returned from the `nq_alloc` HWRM command.
32432 uint16_t cmpl_ring;
32434 * The sequence ID is used by the driver for tracking multiple
32435 * commands. This ID is treated as opaque data by the firmware and
32436 * the value is returned in the `hwrm_resp_hdr` upon completion.
32440 * The target ID of the command:
32441 * * 0x0-0xFFF8 - The function ID
32442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32443 * * 0xFFFD - Reserved for user-space HWRM interface
32446 uint16_t target_id;
32448 * A physical address pointer pointing to a host buffer that the
32449 * command's response data will be written. This can be either a host
32450 * physical address (HPA) or a guest physical address (GPA) and must
32451 * point to a physically contiguous block of memory.
32453 uint64_t resp_addr;
32455 uint8_t tunnel_type;
32456 /* Virtual eXtensible Local Area Network (VXLAN) */
32457 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
32459 /* Generic Network Virtualization Encapsulation (Geneve) */
32460 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
32462 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
32463 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
32465 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
32466 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
32468 /* Use fixed layer 2 ether type of 0xFFFF */
32469 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
32471 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
32472 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
32474 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
32475 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
32478 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
32479 * types that has l4 destination port parameters.
32481 uint16_t tunnel_dst_port_id;
32482 uint8_t unused_1[4];
32485 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
32486 struct hwrm_tunnel_dst_port_free_output {
32487 /* The specific error status for the command. */
32488 uint16_t error_code;
32489 /* The HWRM command request type. */
32491 /* The sequence ID from the original command. */
32493 /* The length of the response data in number of bytes. */
32495 uint8_t unused_1[7];
32497 * This field is used in Output records to indicate that the output
32498 * is completely written to RAM. This field should be read as '1'
32499 * to indicate that the output has been completely written.
32500 * When writing a command completion or response to an internal processor,
32501 * the order of writes has to be such that this field is written last.
32506 /* Periodic statistics context DMA to host. */
32507 /* ctx_hw_stats (size:1280b/160B) */
32508 struct ctx_hw_stats {
32509 /* Number of received unicast packets */
32510 uint64_t rx_ucast_pkts;
32511 /* Number of received multicast packets */
32512 uint64_t rx_mcast_pkts;
32513 /* Number of received broadcast packets */
32514 uint64_t rx_bcast_pkts;
32515 /* Number of discarded packets on received path */
32516 uint64_t rx_discard_pkts;
32517 /* Number of dropped packets on received path */
32518 uint64_t rx_drop_pkts;
32519 /* Number of received bytes for unicast traffic */
32520 uint64_t rx_ucast_bytes;
32521 /* Number of received bytes for multicast traffic */
32522 uint64_t rx_mcast_bytes;
32523 /* Number of received bytes for broadcast traffic */
32524 uint64_t rx_bcast_bytes;
32525 /* Number of transmitted unicast packets */
32526 uint64_t tx_ucast_pkts;
32527 /* Number of transmitted multicast packets */
32528 uint64_t tx_mcast_pkts;
32529 /* Number of transmitted broadcast packets */
32530 uint64_t tx_bcast_pkts;
32531 /* Number of discarded packets on transmit path */
32532 uint64_t tx_discard_pkts;
32533 /* Number of dropped packets on transmit path */
32534 uint64_t tx_drop_pkts;
32535 /* Number of transmitted bytes for unicast traffic */
32536 uint64_t tx_ucast_bytes;
32537 /* Number of transmitted bytes for multicast traffic */
32538 uint64_t tx_mcast_bytes;
32539 /* Number of transmitted bytes for broadcast traffic */
32540 uint64_t tx_bcast_bytes;
32541 /* Number of TPA packets */
32543 /* Number of TPA bytes */
32544 uint64_t tpa_bytes;
32545 /* Number of TPA events */
32546 uint64_t tpa_events;
32547 /* Number of TPA aborts */
32548 uint64_t tpa_aborts;
32551 /* Periodic statistics context DMA to host. */
32552 /* ctx_hw_stats_ext (size:1344b/168B) */
32553 struct ctx_hw_stats_ext {
32554 /* Number of received unicast packets */
32555 uint64_t rx_ucast_pkts;
32556 /* Number of received multicast packets */
32557 uint64_t rx_mcast_pkts;
32558 /* Number of received broadcast packets */
32559 uint64_t rx_bcast_pkts;
32560 /* Number of discarded packets on received path */
32561 uint64_t rx_discard_pkts;
32562 /* Number of dropped packets on received path */
32563 uint64_t rx_drop_pkts;
32564 /* Number of received bytes for unicast traffic */
32565 uint64_t rx_ucast_bytes;
32566 /* Number of received bytes for multicast traffic */
32567 uint64_t rx_mcast_bytes;
32568 /* Number of received bytes for broadcast traffic */
32569 uint64_t rx_bcast_bytes;
32570 /* Number of transmitted unicast packets */
32571 uint64_t tx_ucast_pkts;
32572 /* Number of transmitted multicast packets */
32573 uint64_t tx_mcast_pkts;
32574 /* Number of transmitted broadcast packets */
32575 uint64_t tx_bcast_pkts;
32576 /* Number of discarded packets on transmit path */
32577 uint64_t tx_discard_pkts;
32578 /* Number of dropped packets on transmit path */
32579 uint64_t tx_drop_pkts;
32580 /* Number of transmitted bytes for unicast traffic */
32581 uint64_t tx_ucast_bytes;
32582 /* Number of transmitted bytes for multicast traffic */
32583 uint64_t tx_mcast_bytes;
32584 /* Number of transmitted bytes for broadcast traffic */
32585 uint64_t tx_bcast_bytes;
32586 /* Number of TPA eligible packets */
32587 uint64_t rx_tpa_eligible_pkt;
32588 /* Number of TPA eligible bytes */
32589 uint64_t rx_tpa_eligible_bytes;
32590 /* Number of TPA packets */
32591 uint64_t rx_tpa_pkt;
32592 /* Number of TPA bytes */
32593 uint64_t rx_tpa_bytes;
32594 /* Number of TPA errors */
32595 uint64_t rx_tpa_errors;
32598 /* Periodic Engine statistics context DMA to host. */
32599 /* ctx_eng_stats (size:512b/64B) */
32600 struct ctx_eng_stats {
32602 * Count of data bytes into the Engine.
32603 * This includes any user supplied prefix,
32604 * but does not include any predefined
32607 uint64_t eng_bytes_in;
32608 /* Count of data bytes out of the Engine. */
32609 uint64_t eng_bytes_out;
32611 * Count, in 4-byte (dword) units, of bytes
32612 * that are input as auxiliary data.
32613 * This includes the aux_cmd data.
32615 uint64_t aux_bytes_in;
32617 * Count, in 4-byte (dword) units, of bytes
32618 * that are output as auxiliary data.
32619 * This count is the buffer space for aux_data
32620 * output provided in the RQE, not the actual
32623 uint64_t aux_bytes_out;
32624 /* Count of number of commands executed. */
32627 * Count of number of error commands.
32628 * These are the commands with a
32629 * non-zero status value.
32631 uint64_t error_commands;
32633 * Compression/Encryption Engine usage,
32634 * the unit is count of clock cycles
32636 uint64_t cce_engine_usage;
32638 * De-Compression/De-cryption Engine usage,
32639 * the unit is count of clock cycles
32641 uint64_t cdd_engine_usage;
32644 /***********************
32645 * hwrm_stat_ctx_alloc *
32646 ***********************/
32649 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
32650 struct hwrm_stat_ctx_alloc_input {
32651 /* The HWRM command request type. */
32654 * The completion ring to send the completion event on. This should
32655 * be the NQ ID returned from the `nq_alloc` HWRM command.
32657 uint16_t cmpl_ring;
32659 * The sequence ID is used by the driver for tracking multiple
32660 * commands. This ID is treated as opaque data by the firmware and
32661 * the value is returned in the `hwrm_resp_hdr` upon completion.
32665 * The target ID of the command:
32666 * * 0x0-0xFFF8 - The function ID
32667 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32668 * * 0xFFFD - Reserved for user-space HWRM interface
32671 uint16_t target_id;
32673 * A physical address pointer pointing to a host buffer that the
32674 * command's response data will be written. This can be either a host
32675 * physical address (HPA) or a guest physical address (GPA) and must
32676 * point to a physically contiguous block of memory.
32678 uint64_t resp_addr;
32680 * This is the address for statistic block.
32681 * > For new versions of the chip, this address should be 128B
32684 uint64_t stats_dma_addr;
32686 * The statistic block update period in ms.
32687 * e.g. 250ms, 500ms, 750ms, 1000ms.
32688 * If update_period_ms is 0, then the stats update
32689 * shall be never done and the DMA address shall not be used.
32690 * In this case, the stat block can only be read by
32691 * hwrm_stat_ctx_query command.
32692 * On Ethernet/L2 based devices:
32693 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
32694 * ctx_hw_stats_ext is used for DMA,
32696 * ctx_hw_stats is used for DMA.
32698 uint32_t update_period_ms;
32700 * This field is used to specify statistics context specific
32701 * configuration flags.
32703 uint8_t stat_ctx_flags;
32705 * When this bit is set to '1', the statistics context shall be
32706 * allocated for RoCE traffic only. In this case, traffic other
32707 * than offloaded RoCE traffic shall not be included in this
32708 * statistic context.
32709 * When this bit is set to '0', the statistics context shall be
32710 * used for network traffic or engine traffic.
32712 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
32715 * This is the size of the structure (ctx_hw_stats or
32716 * ctx_hw_stats_ext) that the driver has allocated to be used
32717 * for the periodic DMA updates.
32719 uint16_t stats_dma_length;
32722 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
32723 struct hwrm_stat_ctx_alloc_output {
32724 /* The specific error status for the command. */
32725 uint16_t error_code;
32726 /* The HWRM command request type. */
32728 /* The sequence ID from the original command. */
32730 /* The length of the response data in number of bytes. */
32732 /* This is the statistics context ID value. */
32733 uint32_t stat_ctx_id;
32734 uint8_t unused_0[3];
32736 * This field is used in Output records to indicate that the output
32737 * is completely written to RAM. This field should be read as '1'
32738 * to indicate that the output has been completely written.
32739 * When writing a command completion or response to an internal processor,
32740 * the order of writes has to be such that this field is written last.
32745 /**********************
32746 * hwrm_stat_ctx_free *
32747 **********************/
32750 /* hwrm_stat_ctx_free_input (size:192b/24B) */
32751 struct hwrm_stat_ctx_free_input {
32752 /* The HWRM command request type. */
32755 * The completion ring to send the completion event on. This should
32756 * be the NQ ID returned from the `nq_alloc` HWRM command.
32758 uint16_t cmpl_ring;
32760 * The sequence ID is used by the driver for tracking multiple
32761 * commands. This ID is treated as opaque data by the firmware and
32762 * the value is returned in the `hwrm_resp_hdr` upon completion.
32766 * The target ID of the command:
32767 * * 0x0-0xFFF8 - The function ID
32768 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32769 * * 0xFFFD - Reserved for user-space HWRM interface
32772 uint16_t target_id;
32774 * A physical address pointer pointing to a host buffer that the
32775 * command's response data will be written. This can be either a host
32776 * physical address (HPA) or a guest physical address (GPA) and must
32777 * point to a physically contiguous block of memory.
32779 uint64_t resp_addr;
32780 /* ID of the statistics context that is being queried. */
32781 uint32_t stat_ctx_id;
32782 uint8_t unused_0[4];
32785 /* hwrm_stat_ctx_free_output (size:128b/16B) */
32786 struct hwrm_stat_ctx_free_output {
32787 /* The specific error status for the command. */
32788 uint16_t error_code;
32789 /* The HWRM command request type. */
32791 /* The sequence ID from the original command. */
32793 /* The length of the response data in number of bytes. */
32795 /* This is the statistics context ID value. */
32796 uint32_t stat_ctx_id;
32797 uint8_t unused_0[3];
32799 * This field is used in Output records to indicate that the output
32800 * is completely written to RAM. This field should be read as '1'
32801 * to indicate that the output has been completely written.
32802 * When writing a command completion or response to an internal processor,
32803 * the order of writes has to be such that this field is written last.
32808 /***********************
32809 * hwrm_stat_ctx_query *
32810 ***********************/
32813 /* hwrm_stat_ctx_query_input (size:192b/24B) */
32814 struct hwrm_stat_ctx_query_input {
32815 /* The HWRM command request type. */
32818 * The completion ring to send the completion event on. This should
32819 * be the NQ ID returned from the `nq_alloc` HWRM command.
32821 uint16_t cmpl_ring;
32823 * The sequence ID is used by the driver for tracking multiple
32824 * commands. This ID is treated as opaque data by the firmware and
32825 * the value is returned in the `hwrm_resp_hdr` upon completion.
32829 * The target ID of the command:
32830 * * 0x0-0xFFF8 - The function ID
32831 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32832 * * 0xFFFD - Reserved for user-space HWRM interface
32835 uint16_t target_id;
32837 * A physical address pointer pointing to a host buffer that the
32838 * command's response data will be written. This can be either a host
32839 * physical address (HPA) or a guest physical address (GPA) and must
32840 * point to a physically contiguous block of memory.
32842 uint64_t resp_addr;
32843 /* ID of the statistics context that is being queried. */
32844 uint32_t stat_ctx_id;
32845 uint8_t unused_0[4];
32848 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
32849 struct hwrm_stat_ctx_query_output {
32850 /* The specific error status for the command. */
32851 uint16_t error_code;
32852 /* The HWRM command request type. */
32854 /* The sequence ID from the original command. */
32856 /* The length of the response data in number of bytes. */
32858 /* Number of transmitted unicast packets */
32859 uint64_t tx_ucast_pkts;
32860 /* Number of transmitted multicast packets */
32861 uint64_t tx_mcast_pkts;
32862 /* Number of transmitted broadcast packets */
32863 uint64_t tx_bcast_pkts;
32864 /* Number of transmitted packets with error */
32865 uint64_t tx_err_pkts;
32866 /* Number of dropped packets on transmit path */
32867 uint64_t tx_drop_pkts;
32868 /* Number of transmitted bytes for unicast traffic */
32869 uint64_t tx_ucast_bytes;
32870 /* Number of transmitted bytes for multicast traffic */
32871 uint64_t tx_mcast_bytes;
32872 /* Number of transmitted bytes for broadcast traffic */
32873 uint64_t tx_bcast_bytes;
32874 /* Number of received unicast packets */
32875 uint64_t rx_ucast_pkts;
32876 /* Number of received multicast packets */
32877 uint64_t rx_mcast_pkts;
32878 /* Number of received broadcast packets */
32879 uint64_t rx_bcast_pkts;
32880 /* Number of received packets with error */
32881 uint64_t rx_err_pkts;
32882 /* Number of dropped packets on received path */
32883 uint64_t rx_drop_pkts;
32884 /* Number of received bytes for unicast traffic */
32885 uint64_t rx_ucast_bytes;
32886 /* Number of received bytes for multicast traffic */
32887 uint64_t rx_mcast_bytes;
32888 /* Number of received bytes for broadcast traffic */
32889 uint64_t rx_bcast_bytes;
32890 /* Number of aggregated unicast packets */
32891 uint64_t rx_agg_pkts;
32892 /* Number of aggregated unicast bytes */
32893 uint64_t rx_agg_bytes;
32894 /* Number of aggregation events */
32895 uint64_t rx_agg_events;
32896 /* Number of aborted aggregations */
32897 uint64_t rx_agg_aborts;
32898 uint8_t unused_0[7];
32900 * This field is used in Output records to indicate that the output
32901 * is completely written to RAM. This field should be read as '1'
32902 * to indicate that the output has been completely written.
32903 * When writing a command completion or response to an internal processor,
32904 * the order of writes has to be such that this field is written last.
32909 /***************************
32910 * hwrm_stat_ctx_eng_query *
32911 ***************************/
32914 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
32915 struct hwrm_stat_ctx_eng_query_input {
32916 /* The HWRM command request type. */
32919 * The completion ring to send the completion event on. This should
32920 * be the NQ ID returned from the `nq_alloc` HWRM command.
32922 uint16_t cmpl_ring;
32924 * The sequence ID is used by the driver for tracking multiple
32925 * commands. This ID is treated as opaque data by the firmware and
32926 * the value is returned in the `hwrm_resp_hdr` upon completion.
32930 * The target ID of the command:
32931 * * 0x0-0xFFF8 - The function ID
32932 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32933 * * 0xFFFD - Reserved for user-space HWRM interface
32936 uint16_t target_id;
32938 * A physical address pointer pointing to a host buffer that the
32939 * command's response data will be written. This can be either a host
32940 * physical address (HPA) or a guest physical address (GPA) and must
32941 * point to a physically contiguous block of memory.
32943 uint64_t resp_addr;
32944 /* ID of the statistics context that is being queried. */
32945 uint32_t stat_ctx_id;
32946 uint8_t unused_0[4];
32949 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
32950 struct hwrm_stat_ctx_eng_query_output {
32951 /* The specific error status for the command. */
32952 uint16_t error_code;
32953 /* The HWRM command request type. */
32955 /* The sequence ID from the original command. */
32957 /* The length of the response data in number of bytes. */
32960 * Count of data bytes into the Engine.
32961 * This includes any user supplied prefix,
32962 * but does not include any predefined
32965 uint64_t eng_bytes_in;
32966 /* Count of data bytes out of the Engine. */
32967 uint64_t eng_bytes_out;
32969 * Count, in 4-byte (dword) units, of bytes
32970 * that are input as auxiliary data.
32971 * This includes the aux_cmd data.
32973 uint64_t aux_bytes_in;
32975 * Count, in 4-byte (dword) units, of bytes
32976 * that are output as auxiliary data.
32977 * This count is the buffer space for aux_data
32978 * output provided in the RQE, not the actual
32981 uint64_t aux_bytes_out;
32982 /* Count of number of commands executed. */
32985 * Count of number of error commands.
32986 * These are the commands with a
32987 * non-zero status value.
32989 uint64_t error_commands;
32991 * Compression/Encryption Engine usage,
32992 * the unit is count of clock cycles
32994 uint64_t cce_engine_usage;
32996 * De-Compression/De-cryption Engine usage,
32997 * the unit is count of clock cycles
32999 uint64_t cdd_engine_usage;
33000 uint8_t unused_0[7];
33002 * This field is used in Output records to indicate that the output
33003 * is completely written to RAM. This field should be read as '1'
33004 * to indicate that the output has been completely written.
33005 * When writing a command completion or response to an internal processor,
33006 * the order of writes has to be such that this field is written last.
33011 /***************************
33012 * hwrm_stat_ctx_clr_stats *
33013 ***************************/
33016 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
33017 struct hwrm_stat_ctx_clr_stats_input {
33018 /* The HWRM command request type. */
33021 * The completion ring to send the completion event on. This should
33022 * be the NQ ID returned from the `nq_alloc` HWRM command.
33024 uint16_t cmpl_ring;
33026 * The sequence ID is used by the driver for tracking multiple
33027 * commands. This ID is treated as opaque data by the firmware and
33028 * the value is returned in the `hwrm_resp_hdr` upon completion.
33032 * The target ID of the command:
33033 * * 0x0-0xFFF8 - The function ID
33034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33035 * * 0xFFFD - Reserved for user-space HWRM interface
33038 uint16_t target_id;
33040 * A physical address pointer pointing to a host buffer that the
33041 * command's response data will be written. This can be either a host
33042 * physical address (HPA) or a guest physical address (GPA) and must
33043 * point to a physically contiguous block of memory.
33045 uint64_t resp_addr;
33046 /* ID of the statistics context that is being queried. */
33047 uint32_t stat_ctx_id;
33048 uint8_t unused_0[4];
33051 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
33052 struct hwrm_stat_ctx_clr_stats_output {
33053 /* The specific error status for the command. */
33054 uint16_t error_code;
33055 /* The HWRM command request type. */
33057 /* The sequence ID from the original command. */
33059 /* The length of the response data in number of bytes. */
33061 uint8_t unused_0[7];
33063 * This field is used in Output records to indicate that the output
33064 * is completely written to RAM. This field should be read as '1'
33065 * to indicate that the output has been completely written.
33066 * When writing a command completion or response to an internal processor,
33067 * the order of writes has to be such that this field is written last.
33072 /********************
33073 * hwrm_pcie_qstats *
33074 ********************/
33077 /* hwrm_pcie_qstats_input (size:256b/32B) */
33078 struct hwrm_pcie_qstats_input {
33079 /* The HWRM command request type. */
33082 * The completion ring to send the completion event on. This should
33083 * be the NQ ID returned from the `nq_alloc` HWRM command.
33085 uint16_t cmpl_ring;
33087 * The sequence ID is used by the driver for tracking multiple
33088 * commands. This ID is treated as opaque data by the firmware and
33089 * the value is returned in the `hwrm_resp_hdr` upon completion.
33093 * The target ID of the command:
33094 * * 0x0-0xFFF8 - The function ID
33095 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33096 * * 0xFFFD - Reserved for user-space HWRM interface
33099 uint16_t target_id;
33101 * A physical address pointer pointing to a host buffer that the
33102 * command's response data will be written. This can be either a host
33103 * physical address (HPA) or a guest physical address (GPA) and must
33104 * point to a physically contiguous block of memory.
33106 uint64_t resp_addr;
33108 * The size of PCIe statistics block in bytes.
33109 * Firmware will DMA the PCIe statistics to
33110 * the host with this field size in the response.
33112 uint16_t pcie_stat_size;
33113 uint8_t unused_0[6];
33115 * This is the host address where
33116 * PCIe statistics will be stored
33118 uint64_t pcie_stat_host_addr;
33121 /* hwrm_pcie_qstats_output (size:128b/16B) */
33122 struct hwrm_pcie_qstats_output {
33123 /* The specific error status for the command. */
33124 uint16_t error_code;
33125 /* The HWRM command request type. */
33127 /* The sequence ID from the original command. */
33129 /* The length of the response data in number of bytes. */
33131 /* The size of PCIe statistics block in bytes. */
33132 uint16_t pcie_stat_size;
33133 uint8_t unused_0[5];
33135 * This field is used in Output records to indicate that the output
33136 * is completely written to RAM. This field should be read as '1'
33137 * to indicate that the output has been completely written.
33138 * When writing a command completion or response to an internal processor,
33139 * the order of writes has to be such that this field is written last.
33144 /* PCIe Statistics Formats */
33145 /* pcie_ctx_hw_stats (size:768b/96B) */
33146 struct pcie_ctx_hw_stats {
33147 /* Number of physical layer receiver errors */
33148 uint64_t pcie_pl_signal_integrity;
33149 /* Number of DLLP CRC errors detected by Data Link Layer */
33150 uint64_t pcie_dl_signal_integrity;
33152 * Number of TLP LCRC and sequence number errors detected
33153 * by Data Link Layer
33155 uint64_t pcie_tl_signal_integrity;
33156 /* Number of times LTSSM entered Recovery state */
33157 uint64_t pcie_link_integrity;
33158 /* Number of TLP bytes that have been transmitted */
33159 uint64_t pcie_tx_traffic_rate;
33160 /* Number of TLP bytes that have been received */
33161 uint64_t pcie_rx_traffic_rate;
33162 /* Number of DLLP bytes that have been transmitted */
33163 uint64_t pcie_tx_dllp_statistics;
33164 /* Number of DLLP bytes that have been received */
33165 uint64_t pcie_rx_dllp_statistics;
33167 * Number of times spent in each phase of gen3
33170 uint64_t pcie_equalization_time;
33171 /* Records the last 16 transitions of the LTSSM */
33172 uint32_t pcie_ltssm_histogram[4];
33174 * Record the last 8 reasons on why LTSSM transitioned
33177 uint64_t pcie_recovery_histogram;
33180 /**********************
33181 * hwrm_exec_fwd_resp *
33182 **********************/
33185 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
33186 struct hwrm_exec_fwd_resp_input {
33187 /* The HWRM command request type. */
33190 * The completion ring to send the completion event on. This should
33191 * be the NQ ID returned from the `nq_alloc` HWRM command.
33193 uint16_t cmpl_ring;
33195 * The sequence ID is used by the driver for tracking multiple
33196 * commands. This ID is treated as opaque data by the firmware and
33197 * the value is returned in the `hwrm_resp_hdr` upon completion.
33201 * The target ID of the command:
33202 * * 0x0-0xFFF8 - The function ID
33203 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33204 * * 0xFFFD - Reserved for user-space HWRM interface
33207 uint16_t target_id;
33209 * A physical address pointer pointing to a host buffer that the
33210 * command's response data will be written. This can be either a host
33211 * physical address (HPA) or a guest physical address (GPA) and must
33212 * point to a physically contiguous block of memory.
33214 uint64_t resp_addr;
33216 * This is an encapsulated request. This request should
33217 * be executed by the HWRM and the response should be
33218 * provided in the response buffer inside the encapsulated
33221 uint32_t encap_request[26];
33223 * This value indicates the target id of the response to
33224 * the encapsulated request.
33225 * 0x0 - 0xFFF8 - Used for function ids
33226 * 0xFFF8 - 0xFFFE - Reserved for internal processors
33229 uint16_t encap_resp_target_id;
33230 uint8_t unused_0[6];
33233 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
33234 struct hwrm_exec_fwd_resp_output {
33235 /* The specific error status for the command. */
33236 uint16_t error_code;
33237 /* The HWRM command request type. */
33239 /* The sequence ID from the original command. */
33241 /* The length of the response data in number of bytes. */
33243 uint8_t unused_0[7];
33245 * This field is used in Output records to indicate that the output
33246 * is completely written to RAM. This field should be read as '1'
33247 * to indicate that the output has been completely written.
33248 * When writing a command completion or response to an internal processor,
33249 * the order of writes has to be such that this field is written last.
33254 /************************
33255 * hwrm_reject_fwd_resp *
33256 ************************/
33259 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
33260 struct hwrm_reject_fwd_resp_input {
33261 /* The HWRM command request type. */
33264 * The completion ring to send the completion event on. This should
33265 * be the NQ ID returned from the `nq_alloc` HWRM command.
33267 uint16_t cmpl_ring;
33269 * The sequence ID is used by the driver for tracking multiple
33270 * commands. This ID is treated as opaque data by the firmware and
33271 * the value is returned in the `hwrm_resp_hdr` upon completion.
33275 * The target ID of the command:
33276 * * 0x0-0xFFF8 - The function ID
33277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33278 * * 0xFFFD - Reserved for user-space HWRM interface
33281 uint16_t target_id;
33283 * A physical address pointer pointing to a host buffer that the
33284 * command's response data will be written. This can be either a host
33285 * physical address (HPA) or a guest physical address (GPA) and must
33286 * point to a physically contiguous block of memory.
33288 uint64_t resp_addr;
33290 * This is an encapsulated request. This request should
33291 * be rejected by the HWRM and the error response should be
33292 * provided in the response buffer inside the encapsulated
33295 uint32_t encap_request[26];
33297 * This value indicates the target id of the response to
33298 * the encapsulated request.
33299 * 0x0 - 0xFFF8 - Used for function ids
33300 * 0xFFF8 - 0xFFFE - Reserved for internal processors
33303 uint16_t encap_resp_target_id;
33304 uint8_t unused_0[6];
33307 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
33308 struct hwrm_reject_fwd_resp_output {
33309 /* The specific error status for the command. */
33310 uint16_t error_code;
33311 /* The HWRM command request type. */
33313 /* The sequence ID from the original command. */
33315 /* The length of the response data in number of bytes. */
33317 uint8_t unused_0[7];
33319 * This field is used in Output records to indicate that the output
33320 * is completely written to RAM. This field should be read as '1'
33321 * to indicate that the output has been completely written.
33322 * When writing a command completion or response to an internal processor,
33323 * the order of writes has to be such that this field is written last.
33333 /* hwrm_fwd_resp_input (size:1024b/128B) */
33334 struct hwrm_fwd_resp_input {
33335 /* The HWRM command request type. */
33338 * The completion ring to send the completion event on. This should
33339 * be the NQ ID returned from the `nq_alloc` HWRM command.
33341 uint16_t cmpl_ring;
33343 * The sequence ID is used by the driver for tracking multiple
33344 * commands. This ID is treated as opaque data by the firmware and
33345 * the value is returned in the `hwrm_resp_hdr` upon completion.
33349 * The target ID of the command:
33350 * * 0x0-0xFFF8 - The function ID
33351 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33352 * * 0xFFFD - Reserved for user-space HWRM interface
33355 uint16_t target_id;
33357 * A physical address pointer pointing to a host buffer that the
33358 * command's response data will be written. This can be either a host
33359 * physical address (HPA) or a guest physical address (GPA) and must
33360 * point to a physically contiguous block of memory.
33362 uint64_t resp_addr;
33364 * This value indicates the target id of the encapsulated
33366 * 0x0 - 0xFFF8 - Used for function ids
33367 * 0xFFF8 - 0xFFFE - Reserved for internal processors
33370 uint16_t encap_resp_target_id;
33372 * This value indicates the completion ring the encapsulated
33373 * response will be optionally completed on. If the value is
33374 * -1, then no CR completion shall be generated for the
33375 * encapsulated response. Any other value must be a
33376 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
33377 * is provided, then a CR completion shall be generated for
33378 * the encapsulated response.
33380 uint16_t encap_resp_cmpl_ring;
33381 /* This field indicates the length of encapsulated response. */
33382 uint16_t encap_resp_len;
33386 * This is the host address where the encapsulated response
33388 * This area must be 16B aligned and must be cleared to zero
33389 * before the original request is made.
33391 uint64_t encap_resp_addr;
33392 /* This is an encapsulated response. */
33393 uint32_t encap_resp[24];
33396 /* hwrm_fwd_resp_output (size:128b/16B) */
33397 struct hwrm_fwd_resp_output {
33398 /* The specific error status for the command. */
33399 uint16_t error_code;
33400 /* The HWRM command request type. */
33402 /* The sequence ID from the original command. */
33404 /* The length of the response data in number of bytes. */
33406 uint8_t unused_0[7];
33408 * This field is used in Output records to indicate that the output
33409 * is completely written to RAM. This field should be read as '1'
33410 * to indicate that the output has been completely written.
33411 * When writing a command completion or response to an internal processor,
33412 * the order of writes has to be such that this field is written last.
33417 /*****************************
33418 * hwrm_fwd_async_event_cmpl *
33419 *****************************/
33422 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
33423 struct hwrm_fwd_async_event_cmpl_input {
33424 /* The HWRM command request type. */
33427 * The completion ring to send the completion event on. This should
33428 * be the NQ ID returned from the `nq_alloc` HWRM command.
33430 uint16_t cmpl_ring;
33432 * The sequence ID is used by the driver for tracking multiple
33433 * commands. This ID is treated as opaque data by the firmware and
33434 * the value is returned in the `hwrm_resp_hdr` upon completion.
33438 * The target ID of the command:
33439 * * 0x0-0xFFF8 - The function ID
33440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33441 * * 0xFFFD - Reserved for user-space HWRM interface
33444 uint16_t target_id;
33446 * A physical address pointer pointing to a host buffer that the
33447 * command's response data will be written. This can be either a host
33448 * physical address (HPA) or a guest physical address (GPA) and must
33449 * point to a physically contiguous block of memory.
33451 uint64_t resp_addr;
33453 * This value indicates the target id of the encapsulated
33454 * asynchronous event.
33455 * 0x0 - 0xFFF8 - Used for function ids
33456 * 0xFFF8 - 0xFFFE - Reserved for internal processors
33457 * 0xFFFF - Broadcast to all children VFs (only applicable when
33458 * a PF is the requester)
33460 uint16_t encap_async_event_target_id;
33461 uint8_t unused_0[6];
33462 /* This is an encapsulated asynchronous event completion. */
33463 uint32_t encap_async_event_cmpl[4];
33466 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
33467 struct hwrm_fwd_async_event_cmpl_output {
33468 /* The specific error status for the command. */
33469 uint16_t error_code;
33470 /* The HWRM command request type. */
33472 /* The sequence ID from the original command. */
33474 /* The length of the response data in number of bytes. */
33476 uint8_t unused_0[7];
33478 * This field is used in Output records to indicate that the output
33479 * is completely written to RAM. This field should be read as '1'
33480 * to indicate that the output has been completely written.
33481 * When writing a command completion or response to an internal processor,
33482 * the order of writes has to be such that this field is written last.
33487 /**************************
33488 * hwrm_nvm_raw_write_blk *
33489 **************************/
33492 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
33493 struct hwrm_nvm_raw_write_blk_input {
33494 /* The HWRM command request type. */
33497 * The completion ring to send the completion event on. This should
33498 * be the NQ ID returned from the `nq_alloc` HWRM command.
33500 uint16_t cmpl_ring;
33502 * The sequence ID is used by the driver for tracking multiple
33503 * commands. This ID is treated as opaque data by the firmware and
33504 * the value is returned in the `hwrm_resp_hdr` upon completion.
33508 * The target ID of the command:
33509 * * 0x0-0xFFF8 - The function ID
33510 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33511 * * 0xFFFD - Reserved for user-space HWRM interface
33514 uint16_t target_id;
33516 * A physical address pointer pointing to a host buffer that the
33517 * command's response data will be written. This can be either a host
33518 * physical address (HPA) or a guest physical address (GPA) and must
33519 * point to a physically contiguous block of memory.
33521 uint64_t resp_addr;
33523 * 64-bit Host Source Address.
33524 * This is the location of the source data to be written.
33526 uint64_t host_src_addr;
33528 * 32-bit Destination Address.
33529 * This is the NVRAM byte-offset where the source data will be written to.
33531 uint32_t dest_addr;
33532 /* Length of data to be written, in bytes. */
33536 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
33537 struct hwrm_nvm_raw_write_blk_output {
33538 /* The specific error status for the command. */
33539 uint16_t error_code;
33540 /* The HWRM command request type. */
33542 /* The sequence ID from the original command. */
33544 /* The length of the response data in number of bytes. */
33546 uint8_t unused_0[7];
33548 * This field is used in Output records to indicate that the output
33549 * is completely written to RAM. This field should be read as '1'
33550 * to indicate that the output has been completely written.
33551 * When writing a command completion or response to an internal processor,
33552 * the order of writes has to be such that this field is written last.
33562 /* hwrm_nvm_read_input (size:320b/40B) */
33563 struct hwrm_nvm_read_input {
33564 /* The HWRM command request type. */
33567 * The completion ring to send the completion event on. This should
33568 * be the NQ ID returned from the `nq_alloc` HWRM command.
33570 uint16_t cmpl_ring;
33572 * The sequence ID is used by the driver for tracking multiple
33573 * commands. This ID is treated as opaque data by the firmware and
33574 * the value is returned in the `hwrm_resp_hdr` upon completion.
33578 * The target ID of the command:
33579 * * 0x0-0xFFF8 - The function ID
33580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33581 * * 0xFFFD - Reserved for user-space HWRM interface
33584 uint16_t target_id;
33586 * A physical address pointer pointing to a host buffer that the
33587 * command's response data will be written. This can be either a host
33588 * physical address (HPA) or a guest physical address (GPA) and must
33589 * point to a physically contiguous block of memory.
33591 uint64_t resp_addr;
33593 * 64-bit Host Destination Address.
33594 * This is the host address where the data will be written to.
33596 uint64_t host_dest_addr;
33597 /* The 0-based index of the directory entry. */
33599 uint8_t unused_0[2];
33600 /* The NVRAM byte-offset to read from. */
33602 /* The length of the data to be read, in bytes. */
33604 uint8_t unused_1[4];
33607 /* hwrm_nvm_read_output (size:128b/16B) */
33608 struct hwrm_nvm_read_output {
33609 /* The specific error status for the command. */
33610 uint16_t error_code;
33611 /* The HWRM command request type. */
33613 /* The sequence ID from the original command. */
33615 /* The length of the response data in number of bytes. */
33617 uint8_t unused_0[7];
33619 * This field is used in Output records to indicate that the output
33620 * is completely written to RAM. This field should be read as '1'
33621 * to indicate that the output has been completely written.
33622 * When writing a command completion or response to an internal processor,
33623 * the order of writes has to be such that this field is written last.
33628 /*********************
33629 * hwrm_nvm_raw_dump *
33630 *********************/
33633 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
33634 struct hwrm_nvm_raw_dump_input {
33635 /* The HWRM command request type. */
33638 * The completion ring to send the completion event on. This should
33639 * be the NQ ID returned from the `nq_alloc` HWRM command.
33641 uint16_t cmpl_ring;
33643 * The sequence ID is used by the driver for tracking multiple
33644 * commands. This ID is treated as opaque data by the firmware and
33645 * the value is returned in the `hwrm_resp_hdr` upon completion.
33649 * The target ID of the command:
33650 * * 0x0-0xFFF8 - The function ID
33651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33652 * * 0xFFFD - Reserved for user-space HWRM interface
33655 uint16_t target_id;
33657 * A physical address pointer pointing to a host buffer that the
33658 * command's response data will be written. This can be either a host
33659 * physical address (HPA) or a guest physical address (GPA) and must
33660 * point to a physically contiguous block of memory.
33662 uint64_t resp_addr;
33664 * 64-bit Host Destination Address.
33665 * This is the host address where the data will be written to.
33667 uint64_t host_dest_addr;
33668 /* 32-bit NVRAM byte-offset to read from. */
33670 /* Total length of NVRAM contents to be read, in bytes. */
33674 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
33675 struct hwrm_nvm_raw_dump_output {
33676 /* The specific error status for the command. */
33677 uint16_t error_code;
33678 /* The HWRM command request type. */
33680 /* The sequence ID from the original command. */
33682 /* The length of the response data in number of bytes. */
33684 uint8_t unused_0[7];
33686 * This field is used in Output records to indicate that the output
33687 * is completely written to RAM. This field should be read as '1'
33688 * to indicate that the output has been completely written.
33689 * When writing a command completion or response to an internal processor,
33690 * the order of writes has to be such that this field is written last.
33695 /****************************
33696 * hwrm_nvm_get_dir_entries *
33697 ****************************/
33700 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
33701 struct hwrm_nvm_get_dir_entries_input {
33702 /* The HWRM command request type. */
33705 * The completion ring to send the completion event on. This should
33706 * be the NQ ID returned from the `nq_alloc` HWRM command.
33708 uint16_t cmpl_ring;
33710 * The sequence ID is used by the driver for tracking multiple
33711 * commands. This ID is treated as opaque data by the firmware and
33712 * the value is returned in the `hwrm_resp_hdr` upon completion.
33716 * The target ID of the command:
33717 * * 0x0-0xFFF8 - The function ID
33718 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33719 * * 0xFFFD - Reserved for user-space HWRM interface
33722 uint16_t target_id;
33724 * A physical address pointer pointing to a host buffer that the
33725 * command's response data will be written. This can be either a host
33726 * physical address (HPA) or a guest physical address (GPA) and must
33727 * point to a physically contiguous block of memory.
33729 uint64_t resp_addr;
33731 * 64-bit Host Destination Address.
33732 * This is the host address where the directory will be written.
33734 uint64_t host_dest_addr;
33737 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
33738 struct hwrm_nvm_get_dir_entries_output {
33739 /* The specific error status for the command. */
33740 uint16_t error_code;
33741 /* The HWRM command request type. */
33743 /* The sequence ID from the original command. */
33745 /* The length of the response data in number of bytes. */
33747 uint8_t unused_0[7];
33749 * This field is used in Output records to indicate that the output
33750 * is completely written to RAM. This field should be read as '1'
33751 * to indicate that the output has been completely written.
33752 * When writing a command completion or response to an internal processor,
33753 * the order of writes has to be such that this field is written last.
33758 /*************************
33759 * hwrm_nvm_get_dir_info *
33760 *************************/
33763 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
33764 struct hwrm_nvm_get_dir_info_input {
33765 /* The HWRM command request type. */
33768 * The completion ring to send the completion event on. This should
33769 * be the NQ ID returned from the `nq_alloc` HWRM command.
33771 uint16_t cmpl_ring;
33773 * The sequence ID is used by the driver for tracking multiple
33774 * commands. This ID is treated as opaque data by the firmware and
33775 * the value is returned in the `hwrm_resp_hdr` upon completion.
33779 * The target ID of the command:
33780 * * 0x0-0xFFF8 - The function ID
33781 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33782 * * 0xFFFD - Reserved for user-space HWRM interface
33785 uint16_t target_id;
33787 * A physical address pointer pointing to a host buffer that the
33788 * command's response data will be written. This can be either a host
33789 * physical address (HPA) or a guest physical address (GPA) and must
33790 * point to a physically contiguous block of memory.
33792 uint64_t resp_addr;
33795 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
33796 struct hwrm_nvm_get_dir_info_output {
33797 /* The specific error status for the command. */
33798 uint16_t error_code;
33799 /* The HWRM command request type. */
33801 /* The sequence ID from the original command. */
33803 /* The length of the response data in number of bytes. */
33805 /* Number of directory entries in the directory. */
33807 /* Size of each directory entry, in bytes. */
33808 uint32_t entry_length;
33809 uint8_t unused_0[7];
33811 * This field is used in Output records to indicate that the output
33812 * is completely written to RAM. This field should be read as '1'
33813 * to indicate that the output has been completely written.
33814 * When writing a command completion or response to an internal processor,
33815 * the order of writes has to be such that this field is written last.
33820 /******************
33822 ******************/
33825 /* hwrm_nvm_write_input (size:384b/48B) */
33826 struct hwrm_nvm_write_input {
33827 /* The HWRM command request type. */
33830 * The completion ring to send the completion event on. This should
33831 * be the NQ ID returned from the `nq_alloc` HWRM command.
33833 uint16_t cmpl_ring;
33835 * The sequence ID is used by the driver for tracking multiple
33836 * commands. This ID is treated as opaque data by the firmware and
33837 * the value is returned in the `hwrm_resp_hdr` upon completion.
33841 * The target ID of the command:
33842 * * 0x0-0xFFF8 - The function ID
33843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33844 * * 0xFFFD - Reserved for user-space HWRM interface
33847 uint16_t target_id;
33849 * A physical address pointer pointing to a host buffer that the
33850 * command's response data will be written. This can be either a host
33851 * physical address (HPA) or a guest physical address (GPA) and must
33852 * point to a physically contiguous block of memory.
33854 uint64_t resp_addr;
33856 * 64-bit Host Source Address.
33857 * This is where the source data is.
33859 uint64_t host_src_addr;
33860 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
33863 * Directory ordinal.
33864 * The 0-based instance of the combined Directory Entry Type and Extension.
33866 uint16_t dir_ordinal;
33867 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
33869 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
33872 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
33873 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
33875 uint32_t dir_data_length;
33880 * When this bit is '1', the original active image
33881 * will not be removed. TBD: what purpose is this?
33883 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
33886 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
33887 * If this value is less than the specified data length, it will be ignored.
33888 * The response will contain the actual allocated item length, which may be greater than the requested item length.
33889 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
33890 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
33892 uint32_t dir_item_length;
33896 /* hwrm_nvm_write_output (size:128b/16B) */
33897 struct hwrm_nvm_write_output {
33898 /* The specific error status for the command. */
33899 uint16_t error_code;
33900 /* The HWRM command request type. */
33902 /* The sequence ID from the original command. */
33904 /* The length of the response data in number of bytes. */
33907 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
33908 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
33910 uint32_t dir_item_length;
33911 /* The directory index of the created or modified item. */
33915 * This field is used in Output records to indicate that the output
33916 * is completely written to RAM. This field should be read as '1'
33917 * to indicate that the output has been completely written.
33918 * When writing a command completion or response to an internal processor,
33919 * the order of writes has to be such that this field is written last.
33924 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
33925 struct hwrm_nvm_write_cmd_err {
33927 * command specific error codes that goes to
33928 * the cmd_err field in Common HWRM Error Response.
33931 /* Unknown error */
33932 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33933 /* Unable to complete operation due to fragmentation */
33934 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
33935 /* nvm is completely full. */
33936 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
33937 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
33938 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
33939 uint8_t unused_0[7];
33942 /*******************
33943 * hwrm_nvm_modify *
33944 *******************/
33947 /* hwrm_nvm_modify_input (size:320b/40B) */
33948 struct hwrm_nvm_modify_input {
33949 /* The HWRM command request type. */
33952 * The completion ring to send the completion event on. This should
33953 * be the NQ ID returned from the `nq_alloc` HWRM command.
33955 uint16_t cmpl_ring;
33957 * The sequence ID is used by the driver for tracking multiple
33958 * commands. This ID is treated as opaque data by the firmware and
33959 * the value is returned in the `hwrm_resp_hdr` upon completion.
33963 * The target ID of the command:
33964 * * 0x0-0xFFF8 - The function ID
33965 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33966 * * 0xFFFD - Reserved for user-space HWRM interface
33969 uint16_t target_id;
33971 * A physical address pointer pointing to a host buffer that the
33972 * command's response data will be written. This can be either a host
33973 * physical address (HPA) or a guest physical address (GPA) and must
33974 * point to a physically contiguous block of memory.
33976 uint64_t resp_addr;
33978 * 64-bit Host Source Address.
33979 * This is where the modified data is.
33981 uint64_t host_src_addr;
33982 /* 16-bit directory entry index. */
33984 uint8_t unused_0[2];
33985 /* 32-bit NVRAM byte-offset to modify content from. */
33988 * Length of data to be modified, in bytes. The length shall
33992 uint8_t unused_1[4];
33995 /* hwrm_nvm_modify_output (size:128b/16B) */
33996 struct hwrm_nvm_modify_output {
33997 /* The specific error status for the command. */
33998 uint16_t error_code;
33999 /* The HWRM command request type. */
34001 /* The sequence ID from the original command. */
34003 /* The length of the response data in number of bytes. */
34005 uint8_t unused_0[7];
34007 * This field is used in Output records to indicate that the output
34008 * is completely written to RAM. This field should be read as '1'
34009 * to indicate that the output has been completely written.
34010 * When writing a command completion or response to an internal processor,
34011 * the order of writes has to be such that this field is written last.
34016 /***************************
34017 * hwrm_nvm_find_dir_entry *
34018 ***************************/
34021 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
34022 struct hwrm_nvm_find_dir_entry_input {
34023 /* The HWRM command request type. */
34026 * The completion ring to send the completion event on. This should
34027 * be the NQ ID returned from the `nq_alloc` HWRM command.
34029 uint16_t cmpl_ring;
34031 * The sequence ID is used by the driver for tracking multiple
34032 * commands. This ID is treated as opaque data by the firmware and
34033 * the value is returned in the `hwrm_resp_hdr` upon completion.
34037 * The target ID of the command:
34038 * * 0x0-0xFFF8 - The function ID
34039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34040 * * 0xFFFD - Reserved for user-space HWRM interface
34043 uint16_t target_id;
34045 * A physical address pointer pointing to a host buffer that the
34046 * command's response data will be written. This can be either a host
34047 * physical address (HPA) or a guest physical address (GPA) and must
34048 * point to a physically contiguous block of memory.
34050 uint64_t resp_addr;
34053 * This bit must be '1' for the dir_idx_valid field to be
34056 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
34058 /* Directory Entry Index */
34060 /* Directory Entry (Image) Type */
34063 * Directory ordinal.
34064 * The instance of this Directory Type
34066 uint16_t dir_ordinal;
34067 /* The Directory Entry Extension flags. */
34069 /* This value indicates the search option using dir_ordinal. */
34070 uint8_t opt_ordinal;
34071 /* This value indicates the search option using dir_ordinal. */
34072 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
34073 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
34074 /* Equal to specified ordinal value. */
34075 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
34076 /* Greater than or equal to specified ordinal value */
34077 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
34078 /* Greater than specified ordinal value */
34079 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
34080 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
34081 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
34082 uint8_t unused_0[3];
34085 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
34086 struct hwrm_nvm_find_dir_entry_output {
34087 /* The specific error status for the command. */
34088 uint16_t error_code;
34089 /* The HWRM command request type. */
34091 /* The sequence ID from the original command. */
34093 /* The length of the response data in number of bytes. */
34095 /* Allocated NVRAM for this directory entry, in bytes. */
34096 uint32_t dir_item_length;
34097 /* Size of the stored data for this directory entry, in bytes. */
34098 uint32_t dir_data_length;
34100 * Firmware version.
34101 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
34104 /* Directory ordinal. */
34105 uint16_t dir_ordinal;
34106 /* Directory Entry Index */
34108 uint8_t unused_0[7];
34110 * This field is used in Output records to indicate that the output
34111 * is completely written to RAM. This field should be read as '1'
34112 * to indicate that the output has been completely written.
34113 * When writing a command completion or response to an internal processor,
34114 * the order of writes has to be such that this field is written last.
34119 /****************************
34120 * hwrm_nvm_erase_dir_entry *
34121 ****************************/
34124 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
34125 struct hwrm_nvm_erase_dir_entry_input {
34126 /* The HWRM command request type. */
34129 * The completion ring to send the completion event on. This should
34130 * be the NQ ID returned from the `nq_alloc` HWRM command.
34132 uint16_t cmpl_ring;
34134 * The sequence ID is used by the driver for tracking multiple
34135 * commands. This ID is treated as opaque data by the firmware and
34136 * the value is returned in the `hwrm_resp_hdr` upon completion.
34140 * The target ID of the command:
34141 * * 0x0-0xFFF8 - The function ID
34142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34143 * * 0xFFFD - Reserved for user-space HWRM interface
34146 uint16_t target_id;
34148 * A physical address pointer pointing to a host buffer that the
34149 * command's response data will be written. This can be either a host
34150 * physical address (HPA) or a guest physical address (GPA) and must
34151 * point to a physically contiguous block of memory.
34153 uint64_t resp_addr;
34154 /* Directory Entry Index */
34156 uint8_t unused_0[6];
34159 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
34160 struct hwrm_nvm_erase_dir_entry_output {
34161 /* The specific error status for the command. */
34162 uint16_t error_code;
34163 /* The HWRM command request type. */
34165 /* The sequence ID from the original command. */
34167 /* The length of the response data in number of bytes. */
34169 uint8_t unused_0[7];
34171 * This field is used in Output records to indicate that the output
34172 * is completely written to RAM. This field should be read as '1'
34173 * to indicate that the output has been completely written.
34174 * When writing a command completion or response to an internal processor,
34175 * the order of writes has to be such that this field is written last.
34180 /*************************
34181 * hwrm_nvm_get_dev_info *
34182 *************************/
34185 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
34186 struct hwrm_nvm_get_dev_info_input {
34187 /* The HWRM command request type. */
34190 * The completion ring to send the completion event on. This should
34191 * be the NQ ID returned from the `nq_alloc` HWRM command.
34193 uint16_t cmpl_ring;
34195 * The sequence ID is used by the driver for tracking multiple
34196 * commands. This ID is treated as opaque data by the firmware and
34197 * the value is returned in the `hwrm_resp_hdr` upon completion.
34201 * The target ID of the command:
34202 * * 0x0-0xFFF8 - The function ID
34203 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34204 * * 0xFFFD - Reserved for user-space HWRM interface
34207 uint16_t target_id;
34209 * A physical address pointer pointing to a host buffer that the
34210 * command's response data will be written. This can be either a host
34211 * physical address (HPA) or a guest physical address (GPA) and must
34212 * point to a physically contiguous block of memory.
34214 uint64_t resp_addr;
34217 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
34218 struct hwrm_nvm_get_dev_info_output {
34219 /* The specific error status for the command. */
34220 uint16_t error_code;
34221 /* The HWRM command request type. */
34223 /* The sequence ID from the original command. */
34225 /* The length of the response data in number of bytes. */
34227 /* Manufacturer ID. */
34228 uint16_t manufacturer_id;
34230 uint16_t device_id;
34231 /* Sector size of the NVRAM device. */
34232 uint32_t sector_size;
34233 /* Total size, in bytes of the NVRAM device. */
34234 uint32_t nvram_size;
34235 uint32_t reserved_size;
34236 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
34237 uint32_t available_size;
34238 /* This field represents the major version of NVM cfg */
34239 uint8_t nvm_cfg_ver_maj;
34240 /* This field represents the minor version of NVM cfg */
34241 uint8_t nvm_cfg_ver_min;
34242 /* This field represents the update version of NVM cfg */
34243 uint8_t nvm_cfg_ver_upd;
34245 * This field is used in Output records to indicate that the output
34246 * is completely written to RAM. This field should be read as '1'
34247 * to indicate that the output has been completely written.
34248 * When writing a command completion or response to an internal processor,
34249 * the order of writes has to be such that this field is written last.
34254 /**************************
34255 * hwrm_nvm_mod_dir_entry *
34256 **************************/
34259 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
34260 struct hwrm_nvm_mod_dir_entry_input {
34261 /* The HWRM command request type. */
34264 * The completion ring to send the completion event on. This should
34265 * be the NQ ID returned from the `nq_alloc` HWRM command.
34267 uint16_t cmpl_ring;
34269 * The sequence ID is used by the driver for tracking multiple
34270 * commands. This ID is treated as opaque data by the firmware and
34271 * the value is returned in the `hwrm_resp_hdr` upon completion.
34275 * The target ID of the command:
34276 * * 0x0-0xFFF8 - The function ID
34277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34278 * * 0xFFFD - Reserved for user-space HWRM interface
34281 uint16_t target_id;
34283 * A physical address pointer pointing to a host buffer that the
34284 * command's response data will be written. This can be either a host
34285 * physical address (HPA) or a guest physical address (GPA) and must
34286 * point to a physically contiguous block of memory.
34288 uint64_t resp_addr;
34291 * This bit must be '1' for the checksum field to be
34294 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
34295 /* Directory Entry Index */
34298 * Directory ordinal.
34299 * The (0-based) instance of this Directory Type.
34301 uint16_t dir_ordinal;
34302 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
34304 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
34307 * If valid, then this field updates the checksum
34308 * value of the content in the directory entry.
34313 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
34314 struct hwrm_nvm_mod_dir_entry_output {
34315 /* The specific error status for the command. */
34316 uint16_t error_code;
34317 /* The HWRM command request type. */
34319 /* The sequence ID from the original command. */
34321 /* The length of the response data in number of bytes. */
34323 uint8_t unused_0[7];
34325 * This field is used in Output records to indicate that the output
34326 * is completely written to RAM. This field should be read as '1'
34327 * to indicate that the output has been completely written.
34328 * When writing a command completion or response to an internal processor,
34329 * the order of writes has to be such that this field is written last.
34334 /**************************
34335 * hwrm_nvm_verify_update *
34336 **************************/
34339 /* hwrm_nvm_verify_update_input (size:192b/24B) */
34340 struct hwrm_nvm_verify_update_input {
34341 /* The HWRM command request type. */
34344 * The completion ring to send the completion event on. This should
34345 * be the NQ ID returned from the `nq_alloc` HWRM command.
34347 uint16_t cmpl_ring;
34349 * The sequence ID is used by the driver for tracking multiple
34350 * commands. This ID is treated as opaque data by the firmware and
34351 * the value is returned in the `hwrm_resp_hdr` upon completion.
34355 * The target ID of the command:
34356 * * 0x0-0xFFF8 - The function ID
34357 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34358 * * 0xFFFD - Reserved for user-space HWRM interface
34361 uint16_t target_id;
34363 * A physical address pointer pointing to a host buffer that the
34364 * command's response data will be written. This can be either a host
34365 * physical address (HPA) or a guest physical address (GPA) and must
34366 * point to a physically contiguous block of memory.
34368 uint64_t resp_addr;
34369 /* Directory Entry Type, to be verified. */
34372 * Directory ordinal.
34373 * The instance of the Directory Type to be verified.
34375 uint16_t dir_ordinal;
34377 * The Directory Entry Extension flags.
34378 * The "UPDATE" extension flag must be set in this value.
34379 * A corresponding directory entry with the same type and ordinal values but *without*
34380 * the "UPDATE" extension flag must also exist. The other flags of the extension must
34381 * be identical between the active and update entries.
34384 uint8_t unused_0[2];
34387 /* hwrm_nvm_verify_update_output (size:128b/16B) */
34388 struct hwrm_nvm_verify_update_output {
34389 /* The specific error status for the command. */
34390 uint16_t error_code;
34391 /* The HWRM command request type. */
34393 /* The sequence ID from the original command. */
34395 /* The length of the response data in number of bytes. */
34397 uint8_t unused_0[7];
34399 * This field is used in Output records to indicate that the output
34400 * is completely written to RAM. This field should be read as '1'
34401 * to indicate that the output has been completely written.
34402 * When writing a command completion or response to an internal processor,
34403 * the order of writes has to be such that this field is written last.
34408 /***************************
34409 * hwrm_nvm_install_update *
34410 ***************************/
34413 /* hwrm_nvm_install_update_input (size:192b/24B) */
34414 struct hwrm_nvm_install_update_input {
34415 /* The HWRM command request type. */
34418 * The completion ring to send the completion event on. This should
34419 * be the NQ ID returned from the `nq_alloc` HWRM command.
34421 uint16_t cmpl_ring;
34423 * The sequence ID is used by the driver for tracking multiple
34424 * commands. This ID is treated as opaque data by the firmware and
34425 * the value is returned in the `hwrm_resp_hdr` upon completion.
34429 * The target ID of the command:
34430 * * 0x0-0xFFF8 - The function ID
34431 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34432 * * 0xFFFD - Reserved for user-space HWRM interface
34435 uint16_t target_id;
34437 * A physical address pointer pointing to a host buffer that the
34438 * command's response data will be written. This can be either a host
34439 * physical address (HPA) or a guest physical address (GPA) and must
34440 * point to a physically contiguous block of memory.
34442 uint64_t resp_addr;
34444 * Installation type. If the value 3 through 0xffff is used,
34445 * only packaged items with that type value will be installed and
34446 * conditional installation directives for those packaged items
34447 * will be over-ridden (i.e. 'create' or 'replace' will be treated
34450 uint32_t install_type;
34452 * Perform a normal package installation. Conditional installation
34453 * directives (e.g. 'create' and 'replace') of packaged items
34454 * will be followed.
34456 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
34458 * Install all packaged items regardless of installation directive
34459 * (i.e. treat all packaged items as though they have an installation
34460 * directive of 'install').
34462 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
34463 UINT32_C(0xffffffff)
34464 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
34465 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
34467 /* If set to 1, then securely erase all unused locations in persistent storage. */
34468 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
34471 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
34472 * When combined with erase_unused_space then unspecified images will be securely erased.
34474 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
34477 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
34478 * Allow additional time for this command to complete if this bit is set to 1.
34480 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
34482 uint8_t unused_0[2];
34485 /* hwrm_nvm_install_update_output (size:192b/24B) */
34486 struct hwrm_nvm_install_update_output {
34487 /* The specific error status for the command. */
34488 uint16_t error_code;
34489 /* The HWRM command request type. */
34491 /* The sequence ID from the original command. */
34493 /* The length of the response data in number of bytes. */
34496 * Bit-mask of successfully installed items.
34497 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
34498 * A value of 0 indicates that no items were successfully installed.
34500 uint64_t installed_items;
34501 /* result is 8 b */
34503 /* There was no problem with the package installation. */
34504 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
34505 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
34506 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
34507 /* problem_item is 8 b */
34508 uint8_t problem_item;
34509 /* There was no problem with any packaged items. */
34510 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
34512 /* There was a problem with the NVM package itself. */
34513 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
34515 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
34516 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
34517 /* reset_required is 8 b */
34518 uint8_t reset_required;
34520 * No reset is required for installed/updated firmware or
34521 * microcode to take effect.
34523 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
34526 * A PCIe reset (e.g. system reboot) is
34527 * required for newly installed/updated firmware or
34528 * microcode to take effect.
34530 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
34533 * A controller power reset (e.g. system power-cycle) is
34534 * required for newly installed/updated firmware or
34535 * microcode to take effect. Some newly installed/updated
34536 * firmware or microcode may still take effect upon the
34539 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
34541 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
34542 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
34543 uint8_t unused_0[4];
34545 * This field is used in Output records to indicate that the output
34546 * is completely written to RAM. This field should be read as '1'
34547 * to indicate that the output has been completely written.
34548 * When writing a command completion or response to an internal processor,
34549 * the order of writes has to be such that this field is written last.
34554 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
34555 struct hwrm_nvm_install_update_cmd_err {
34557 * command specific error codes that goes to
34558 * the cmd_err field in Common HWRM Error Response.
34561 /* Unknown error */
34562 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34563 /* Unable to complete operation due to fragmentation */
34564 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
34565 /* nvm is completely full. */
34566 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
34567 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
34568 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
34569 uint8_t unused_0[7];
34572 /******************
34574 ******************/
34577 /* hwrm_nvm_flush_input (size:128b/16B) */
34578 struct hwrm_nvm_flush_input {
34579 /* The HWRM command request type. */
34582 * The completion ring to send the completion event on. This should
34583 * be the NQ ID returned from the `nq_alloc` HWRM command.
34585 uint16_t cmpl_ring;
34587 * The sequence ID is used by the driver for tracking multiple
34588 * commands. This ID is treated as opaque data by the firmware and
34589 * the value is returned in the `hwrm_resp_hdr` upon completion.
34593 * The target ID of the command:
34594 * * 0x0-0xFFF8 - The function ID
34595 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34596 * * 0xFFFD - Reserved for user-space HWRM interface
34599 uint16_t target_id;
34601 * A physical address pointer pointing to a host buffer that the
34602 * command's response data will be written. This can be either a host
34603 * physical address (HPA) or a guest physical address (GPA) and must
34604 * point to a physically contiguous block of memory.
34606 uint64_t resp_addr;
34609 /* hwrm_nvm_flush_output (size:128b/16B) */
34610 struct hwrm_nvm_flush_output {
34611 /* The specific error status for the command. */
34612 uint16_t error_code;
34613 /* The HWRM command request type. */
34615 /* The sequence ID from the original command. */
34617 /* The length of the response data in number of bytes. */
34619 uint8_t unused_0[7];
34621 * This field is used in Output records to indicate that the output
34622 * is completely written to RAM. This field should be read as '1'
34623 * to indicate that the output has been completely written.
34624 * When writing a command completion or response to an internal processor,
34625 * the order of writes has to be such that this field is written last.
34630 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
34631 struct hwrm_nvm_flush_cmd_err {
34633 * command specific error codes that goes to
34634 * the cmd_err field in Common HWRM Error Response.
34637 /* Unknown error */
34638 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34639 /* flush could not be performed */
34640 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
34641 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
34642 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
34643 uint8_t unused_0[7];
34646 /*************************
34647 * hwrm_nvm_get_variable *
34648 *************************/
34651 /* hwrm_nvm_get_variable_input (size:320b/40B) */
34652 struct hwrm_nvm_get_variable_input {
34653 /* The HWRM command request type. */
34656 * The completion ring to send the completion event on. This should
34657 * be the NQ ID returned from the `nq_alloc` HWRM command.
34659 uint16_t cmpl_ring;
34661 * The sequence ID is used by the driver for tracking multiple
34662 * commands. This ID is treated as opaque data by the firmware and
34663 * the value is returned in the `hwrm_resp_hdr` upon completion.
34667 * The target ID of the command:
34668 * * 0x0-0xFFF8 - The function ID
34669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34670 * * 0xFFFD - Reserved for user-space HWRM interface
34673 uint16_t target_id;
34675 * A physical address pointer pointing to a host buffer that the
34676 * command's response data will be written. This can be either a host
34677 * physical address (HPA) or a guest physical address (GPA) and must
34678 * point to a physically contiguous block of memory.
34680 uint64_t resp_addr;
34682 * This is the host address where
34683 * nvm variable will be stored
34685 uint64_t dest_data_addr;
34686 /* size of data in bits */
34688 /* nvm cfg option number */
34689 uint16_t option_num;
34691 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
34693 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
34695 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
34696 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
34698 * Number of dimensions for this nvm configuration variable.
34699 * This value indicates how many of the indexN values to use.
34700 * A value of 0 means that none of the indexN values are valid.
34701 * A value of 1 requires at index0 is valued, a value of 2
34702 * requires that index0 and index1 are valid, and so forth
34704 uint16_t dimensions;
34705 /* index for the 1st dimensions */
34707 /* index for the 2nd dimensions */
34709 /* index for the 3rd dimensions */
34711 /* index for the 4th dimensions */
34715 * When this bit is set to 1, the factory default value will be returned,
34716 * 0 returns the operational value.
34718 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
34723 /* hwrm_nvm_get_variable_output (size:128b/16B) */
34724 struct hwrm_nvm_get_variable_output {
34725 /* The specific error status for the command. */
34726 uint16_t error_code;
34727 /* The HWRM command request type. */
34729 /* The sequence ID from the original command. */
34731 /* The length of the response data in number of bytes. */
34733 /* size of data of the actual variable retrieved in bits */
34736 * option_num is the option number for the data retrieved. It is possible in the
34737 * future that the option number returned would be different than requested. This
34738 * condition could occur if an option is deprecated and a new option id is defined
34739 * with similar characteristics, but has a slightly different definition. This
34740 * also makes it convenient for the caller to identify the variable result with
34741 * the option id from the response.
34743 uint16_t option_num;
34745 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
34747 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
34749 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
34750 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
34751 uint8_t unused_0[3];
34753 * This field is used in Output records to indicate that the output
34754 * is completely written to RAM. This field should be read as '1'
34755 * to indicate that the output has been completely written.
34756 * When writing a command completion or response to an internal processor,
34757 * the order of writes has to be such that this field is written last.
34762 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
34763 struct hwrm_nvm_get_variable_cmd_err {
34765 * command specific error codes that goes to
34766 * the cmd_err field in Common HWRM Error Response.
34769 /* Unknown error */
34770 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34771 /* variable does not exist */
34772 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
34773 /* configuration is corrupted and the variable cannot be saved */
34774 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
34775 /* length specified is too small */
34776 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
34777 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
34778 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
34779 uint8_t unused_0[7];
34782 /*************************
34783 * hwrm_nvm_set_variable *
34784 *************************/
34787 /* hwrm_nvm_set_variable_input (size:320b/40B) */
34788 struct hwrm_nvm_set_variable_input {
34789 /* The HWRM command request type. */
34792 * The completion ring to send the completion event on. This should
34793 * be the NQ ID returned from the `nq_alloc` HWRM command.
34795 uint16_t cmpl_ring;
34797 * The sequence ID is used by the driver for tracking multiple
34798 * commands. This ID is treated as opaque data by the firmware and
34799 * the value is returned in the `hwrm_resp_hdr` upon completion.
34803 * The target ID of the command:
34804 * * 0x0-0xFFF8 - The function ID
34805 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34806 * * 0xFFFD - Reserved for user-space HWRM interface
34809 uint16_t target_id;
34811 * A physical address pointer pointing to a host buffer that the
34812 * command's response data will be written. This can be either a host
34813 * physical address (HPA) or a guest physical address (GPA) and must
34814 * point to a physically contiguous block of memory.
34816 uint64_t resp_addr;
34818 * This is the host address where
34819 * nvm variable will be copied from
34821 uint64_t src_data_addr;
34822 /* size of data in bits */
34824 /* nvm cfg option number */
34825 uint16_t option_num;
34827 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
34829 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
34831 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
34832 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
34834 * Number of dimensions for this nvm configuration variable.
34835 * This value indicates how many of the indexN values to use.
34836 * A value of 0 means that none of the indexN values are valid.
34837 * A value of 1 requires at index0 is valued, a value of 2
34838 * requires that index0 and index1 are valid, and so forth
34840 uint16_t dimensions;
34841 /* index for the 1st dimensions */
34843 /* index for the 2nd dimensions */
34845 /* index for the 3rd dimensions */
34847 /* index for the 4th dimensions */
34850 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
34851 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
34853 /* encryption method */
34854 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
34856 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
34857 /* No encryption. */
34858 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
34859 (UINT32_C(0x0) << 1)
34860 /* one-way encryption. */
34861 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
34862 (UINT32_C(0x1) << 1)
34863 /* symmetric AES256 encryption. */
34864 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
34865 (UINT32_C(0x2) << 1)
34866 /* SHA1 digest appended to plaintext contents, for authentication */
34867 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
34868 (UINT32_C(0x3) << 1)
34869 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
34870 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
34871 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
34873 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
34874 /* When this bit is 1, update the factory default region */
34875 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
34880 /* hwrm_nvm_set_variable_output (size:128b/16B) */
34881 struct hwrm_nvm_set_variable_output {
34882 /* The specific error status for the command. */
34883 uint16_t error_code;
34884 /* The HWRM command request type. */
34886 /* The sequence ID from the original command. */
34888 /* The length of the response data in number of bytes. */
34890 uint8_t unused_0[7];
34892 * This field is used in Output records to indicate that the output
34893 * is completely written to RAM. This field should be read as '1'
34894 * to indicate that the output has been completely written.
34895 * When writing a command completion or response to an internal processor,
34896 * the order of writes has to be such that this field is written last.
34901 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
34902 struct hwrm_nvm_set_variable_cmd_err {
34904 * command specific error codes that goes to
34905 * the cmd_err field in Common HWRM Error Response.
34908 /* Unknown error */
34909 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
34910 /* variable does not exist */
34911 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
34912 /* configuration is corrupted and the variable cannot be saved */
34913 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
34914 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
34915 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
34916 uint8_t unused_0[7];
34919 /****************************
34920 * hwrm_nvm_validate_option *
34921 ****************************/
34924 /* hwrm_nvm_validate_option_input (size:320b/40B) */
34925 struct hwrm_nvm_validate_option_input {
34926 /* The HWRM command request type. */
34929 * The completion ring to send the completion event on. This should
34930 * be the NQ ID returned from the `nq_alloc` HWRM command.
34932 uint16_t cmpl_ring;
34934 * The sequence ID is used by the driver for tracking multiple
34935 * commands. This ID is treated as opaque data by the firmware and
34936 * the value is returned in the `hwrm_resp_hdr` upon completion.
34940 * The target ID of the command:
34941 * * 0x0-0xFFF8 - The function ID
34942 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34943 * * 0xFFFD - Reserved for user-space HWRM interface
34946 uint16_t target_id;
34948 * A physical address pointer pointing to a host buffer that the
34949 * command's response data will be written. This can be either a host
34950 * physical address (HPA) or a guest physical address (GPA) and must
34951 * point to a physically contiguous block of memory.
34953 uint64_t resp_addr;
34955 * This is the host address where
34956 * nvm variable will be copied from
34958 uint64_t src_data_addr;
34959 /* size of data in bits */
34961 /* nvm cfg option number */
34962 uint16_t option_num;
34964 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
34967 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
34969 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
34970 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
34972 * Number of dimensions for this nvm configuration variable.
34973 * This value indicates how many of the indexN values to use.
34974 * A value of 0 means that none of the indexN values are valid.
34975 * A value of 1 requires at index0 is valued, a value of 2
34976 * requires that index0 and index1 are valid, and so forth
34978 uint16_t dimensions;
34979 /* index for the 1st dimensions */
34981 /* index for the 2nd dimensions */
34983 /* index for the 3rd dimensions */
34985 /* index for the 4th dimensions */
34987 uint8_t unused_0[2];
34990 /* hwrm_nvm_validate_option_output (size:128b/16B) */
34991 struct hwrm_nvm_validate_option_output {
34992 /* The specific error status for the command. */
34993 uint16_t error_code;
34994 /* The HWRM command request type. */
34996 /* The sequence ID from the original command. */
34998 /* The length of the response data in number of bytes. */
35001 /* indicates that the value provided for the option is not matching with the saved data. */
35002 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
35003 /* indicates that the value provided for the option is matching the saved data. */
35004 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
35005 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
35006 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
35007 uint8_t unused_0[6];
35009 * This field is used in Output records to indicate that the output
35010 * is completely written to RAM. This field should be read as '1'
35011 * to indicate that the output has been completely written.
35012 * When writing a command completion or response to an internal processor,
35013 * the order of writes has to be such that this field is written last.
35018 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
35019 struct hwrm_nvm_validate_option_cmd_err {
35021 * command specific error codes that goes to
35022 * the cmd_err field in Common HWRM Error Response.
35025 /* Unknown error */
35026 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
35027 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
35028 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
35029 uint8_t unused_0[7];
35034 ******************/
35037 /* hwrm_fw_reset_input (size:192b/24B) */
35038 struct hwrm_fw_reset_input {
35039 /* The HWRM command request type. */
35042 * The completion ring to send the completion event on. This should
35043 * be the NQ ID returned from the `nq_alloc` HWRM command.
35045 uint16_t cmpl_ring;
35047 * The sequence ID is used by the driver for tracking multiple
35048 * commands. This ID is treated as opaque data by the firmware and
35049 * the value is returned in the `hwrm_resp_hdr` upon completion.
35053 * The target ID of the command:
35054 * * 0x0-0xFFF8 - The function ID
35055 * * 0xFFF8-0xFFFE - Reserved for internal processors
35058 uint16_t target_id;
35060 * A physical address pointer pointing to a host buffer that the
35061 * command's response data will be written. This can be either a host
35062 * physical address (HPA) or a guest physical address (GPA) and must
35063 * point to a physically contiguous block of memory.
35065 uint64_t resp_addr;
35066 /* Type of embedded processor. */
35067 uint8_t embedded_proc_type;
35068 /* Boot Processor */
35069 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
35071 /* Management Processor */
35072 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
35074 /* Network control processor */
35075 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
35077 /* RoCE control processor */
35078 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
35081 * Host (in multi-host environment): This is only valid if requester is IPC.
35082 * Reinit host hardware resources and PCIe.
35084 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
35086 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
35087 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
35089 /* Reset all blocks of the chip (including all processors) */
35090 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
35093 * Host (in multi-host environment): This is only valid if requester is IPC.
35094 * Reinit host hardware resources.
35096 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
35098 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
35099 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
35100 /* Type of self reset. */
35101 uint8_t selfrst_status;
35102 /* No Self Reset */
35103 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
35105 /* Self Reset as soon as possible to do so safely */
35106 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
35108 /* Self Reset on PCIe Reset */
35109 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
35111 /* Self Reset immediately after notification to all clients. */
35112 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
35114 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
35115 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
35117 * Indicate which host is being reset. 0 means first host.
35118 * Only valid when embedded_proc_type is host in multihost
35124 * When this bit is '1', then the core firmware initiates
35125 * the reset only after graceful shut down of all registered instances.
35126 * If not, the device will continue with the existing firmware.
35128 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
35129 uint8_t unused_0[4];
35132 /* hwrm_fw_reset_output (size:128b/16B) */
35133 struct hwrm_fw_reset_output {
35134 /* The specific error status for the command. */
35135 uint16_t error_code;
35136 /* The HWRM command request type. */
35138 /* The sequence ID from the original command. */
35140 /* The length of the response data in number of bytes. */
35142 /* Type of self reset. */
35143 uint8_t selfrst_status;
35144 /* No Self Reset */
35145 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
35147 /* Self Reset as soon as possible to do so safely */
35148 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
35150 /* Self Reset on PCIe Reset */
35151 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
35153 /* Self Reset immediately after notification to all clients. */
35154 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
35156 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
35157 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
35158 uint8_t unused_0[6];
35160 * This field is used in Output records to indicate that the output
35161 * is completely written to RAM. This field should be read as '1'
35162 * to indicate that the output has been completely written.
35163 * When writing a command completion or response to an internal processor,
35164 * the order of writes has to be such that this field is written last.
35169 /**********************
35170 * hwrm_port_ts_query *
35171 ***********************/
35174 /* hwrm_port_ts_query_input (size:192b/24B) */
35175 struct hwrm_port_ts_query_input {
35176 /* The HWRM command request type. */
35179 * The completion ring to send the completion event on. This should
35180 * be the NQ ID returned from the `nq_alloc` HWRM command.
35182 uint16_t cmpl_ring;
35184 * The sequence ID is used by the driver for tracking multiple
35185 * commands. This ID is treated as opaque data by the firmware and
35186 * the value is returned in the `hwrm_resp_hdr` upon completion.
35190 * The target ID of the command:
35191 * * 0x0-0xFFF8 - The function ID
35192 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35193 * * 0xFFFD - Reserved for user-space HWRM interface
35196 uint16_t target_id;
35198 * A physical address pointer pointing to a host buffer that the
35199 * command's response data will be written. This can be either a host
35200 * physical address (HPA) or a guest physical address (GPA) and must
35201 * point to a physically contiguous block of memory.
35203 uint64_t resp_addr;
35206 * Enumeration denoting the RX, TX type of the resource.
35207 * This enumeration is used for resources that are similar for both
35208 * TX and RX paths of the chip.
35210 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
35212 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
35214 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
35215 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
35216 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
35218 * If set, the response includes the current value of the free
35221 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
35222 /* Port ID of port that is being queried. */
35224 uint8_t unused_0[2];
35227 /* hwrm_port_ts_query_output (size:192b/24B) */
35228 struct hwrm_port_ts_query_output {
35229 /* The specific error status for the command. */
35230 uint16_t error_code;
35231 /* The HWRM command request type. */
35233 /* The sequence ID from the original command. */
35235 /* The length of the response data in number of bytes. */
35238 * Timestamp value of PTP message captured, or current value of
35239 * free running timer.
35241 uint32_t ptp_msg_ts[2];
35242 /* Sequence ID of the PTP message captured. */
35243 uint16_t ptp_msg_seqid;
35244 uint8_t unused_0[5];
35246 * This field is used in Output records to indicate that the output
35247 * is completely written to RAM. This field should be read as '1'
35248 * to indicate that the output has been completely written.
35249 * When writing a command completion or response to an internal processor,
35250 * the order of writes has to be such that this field is written last.
35255 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */