1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* RoCE slow path command to query CC Gen1 support. */
71 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
72 /* RoCE slow path command to modify CC Gen1 support. */
73 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
74 /* Engine CKV - The device's serial number. */
75 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
76 /* Engine CKV - Per-function random nonce data. */
77 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
78 /* Engine CKV - Initialization vector. */
79 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
80 /* Engine CKV - Authentication tag. */
81 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
82 /* Engine CKV - The encrypted data. */
83 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
84 /* Engine CKV - Supported algorithms. */
85 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
86 /* Engine CKV - The EC curve name and ECC public key information. */
87 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
88 /* Engine CKV - The ECDSA signature. */
89 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
90 #define TLV_TYPE_LAST \
91 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
94 /* tlv (size:64b/8B) */
97 * The command discriminator is used to differentiate between various
98 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
99 * command messages as well as newer TLV encapsulated HWRM commands.
101 * For TLV encapsulated messages this field must be 0x8000.
107 * Indicates the presence of additional TLV encapsulated data
110 #define TLV_FLAGS_MORE UINT32_C(0x1)
111 /* Last TLV in a sequence of TLVs. */
112 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
113 /* More TLVs follow this TLV. */
114 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
116 * When an HWRM receiver detects a TLV type that it does not
117 * support with the TLV required flag set, the receiver must
118 * reject the HWRM message with an error code indicating an
119 * unsupported TLV type.
121 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
123 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
125 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
126 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
128 * This field defines the TLV type value which is divided into
129 * two ranges to differentiate between global and local TLV types.
130 * Global TLV types must be unique across all defined TLV types.
131 * Local TLV types are valid only for extensions to a given
132 * HWRM message and may be repeated across different HWRM message
133 * types. There is a direct correlation of each HWRM message type
134 * to a single global TLV type value.
136 * Global TLV range: `0 - (63k-1)`
138 * Local TLV range: `63k - (64k-1)`
142 * Length of the message data encapsulated by this TLV in bytes.
143 * This length does not include the size of the TLV header itself
144 * and it must be an integer multiple of 8B.
147 } __attribute__((packed));
150 /* input (size:128b/16B) */
153 * This value indicates what type of request this is. The format
154 * for the rest of the command is determined by this field.
158 * This value indicates the what completion ring the request will
159 * be optionally completed on. If the value is -1, then no
160 * CR completion will be generated. Any other value must be a
161 * valid CR ring_id value for this function.
164 /* This value indicates the command sequence number. */
167 * Target ID of this command.
169 * 0x0 - 0xFFF8 - Used for function ids
170 * 0xFFF8 - 0xFFFE - Reserved for internal processors
175 * This is the host address where the response will be written
176 * when the request is complete. This area must be 16B aligned
177 * and must be cleared to zero before the request is made.
180 } __attribute__((packed));
183 /* output (size:64b/8B) */
186 * Pass/Fail or error type
188 * Note: receiver to verify the in parameters, and fail the call
189 * with an error when appropriate
192 /* This field returns the type of original request. */
194 /* This field provides original sequence number of the command. */
197 * This field is the length of the response in bytes. The
198 * last byte of the response is a valid flag that will read
199 * as '1' when the command has been completely written to
203 } __attribute__((packed));
205 /* Short Command Structure */
206 /* hwrm_short_input (size:128b/16B) */
207 struct hwrm_short_input {
209 * This field indicates the type of request in the request buffer.
210 * The format for the rest of the command (request) is determined
215 * This field indicates a signature that is used to identify short
216 * form of the command listed here. This field shall be set to
220 /* Signature indicating this is a short form of HWRM command */
221 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
222 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
223 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
224 /* Reserved for future use. */
226 /* This value indicates the length of the request. */
229 * This is the host address where the request was written.
230 * This area must be 16B aligned.
233 } __attribute__((packed));
237 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
238 * # So only structure definition is provided here.
240 /* cmd_nums (size:64b/8B) */
243 * This version of the specification defines the commands listed in
244 * the table below. The following are general implementation
245 * requirements for these commands:
247 * # All commands listed below that are marked neither
248 * reserved nor experimental shall be implemented by the HWRM.
249 * # A HWRM client compliant to this specification should not use
250 * commands outside of the list below.
251 * # A HWRM client compliant to this specification should not use
252 * command numbers marked reserved below.
253 * # A command marked experimental below may not be implemented
255 * # A command marked experimental may change in the
256 * future version of the HWRM specification.
257 * # A command not listed below may be implemented by the HWRM.
258 * The behavior of commands that are not listed below is outside
259 * the scope of this specification.
262 #define HWRM_VER_GET UINT32_C(0x0)
263 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
264 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
265 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
266 /* Reserved for future use. */
267 #define HWRM_RESERVED1 UINT32_C(0x10)
268 #define HWRM_FUNC_RESET UINT32_C(0x11)
269 #define HWRM_FUNC_GETFID UINT32_C(0x12)
270 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
271 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
272 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
273 #define HWRM_FUNC_QCFG UINT32_C(0x16)
274 #define HWRM_FUNC_CFG UINT32_C(0x17)
275 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
276 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
277 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
278 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
279 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
280 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
281 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
282 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
283 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
284 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
286 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
287 #define HWRM_PORT_QSTATS UINT32_C(0x23)
288 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
290 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
292 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
293 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
294 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
296 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
297 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
298 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
299 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
300 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
301 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
302 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
303 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
304 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
305 #define HWRM_QUEUE_CFG UINT32_C(0x32)
306 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
307 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
308 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
309 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
310 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
311 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
312 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
313 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
315 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
317 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
319 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
320 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
321 #define HWRM_VNIC_FREE UINT32_C(0x41)
322 #define HWRM_VNIC_CFG UINT32_C(0x42)
323 #define HWRM_VNIC_QCFG UINT32_C(0x43)
324 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
326 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
327 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
328 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
329 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
330 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
331 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
332 #define HWRM_RING_ALLOC UINT32_C(0x50)
333 #define HWRM_RING_FREE UINT32_C(0x51)
334 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
335 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
336 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
337 #define HWRM_RING_RESET UINT32_C(0x5e)
338 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
339 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
340 /* Reserved for future use. */
341 #define HWRM_RESERVED5 UINT32_C(0x64)
342 /* Reserved for future use. */
343 #define HWRM_RESERVED6 UINT32_C(0x65)
344 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
345 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
346 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
347 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
348 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
349 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
350 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
351 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
352 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
354 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
356 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
357 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
358 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
359 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
361 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
363 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
365 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
366 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
367 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
368 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
369 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
370 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
371 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
372 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
373 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
374 #define HWRM_FW_RESET UINT32_C(0xc0)
375 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
376 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
377 #define HWRM_FW_SYNC UINT32_C(0xc3)
379 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
381 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
383 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
385 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
387 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
388 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
389 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
390 #define HWRM_FWD_RESP UINT32_C(0xd2)
391 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
392 #define HWRM_OEM_CMD UINT32_C(0xd4)
393 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
394 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
395 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
396 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
397 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
399 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
401 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
403 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
405 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
407 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
409 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
411 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
413 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
415 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
417 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
419 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
421 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
423 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
425 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
427 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
429 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
431 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
432 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
433 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
434 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
436 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
438 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
440 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
442 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
443 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
444 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
445 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
446 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
447 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
448 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
449 /* Engine CKV - Add a new CKEK used to encrypt keys. */
450 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
451 /* Engine CKV - Delete a previously added CKEK. */
452 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
453 /* Engine CKV - Add a new key to the key vault. */
454 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
455 /* Engine CKV - Delete a key from the key vault. */
456 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
457 /* Engine CKV - Delete all keys from the key vault. */
458 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
459 /* Engine CKV - Get random data. */
460 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
461 /* Engine CKV - Generate and encrypt a new AES key. */
462 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
463 /* Engine - Query the available queue groups configuration. */
464 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
465 /* Engine - Query the queue groups assigned to a function. */
466 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
467 /* Engine - Query the available queue group meter profile configuration. */
468 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
469 /* Engine - Query the configuration of a queue group meter profile. */
470 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
471 /* Engine - Allocate a queue group meter profile. */
472 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
473 /* Engine - Free a queue group meter profile. */
474 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
475 /* Engine - Query the meters assigned to a queue group. */
476 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
477 /* Engine - Bind a queue group meter profile to a queue group. */
478 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
479 /* Engine - Unbind a queue group meter profile from a queue group. */
480 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
481 /* Engine - Bind a queue group to a function. */
482 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
483 /* Engine - Query the scheduling group configuration. */
484 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
485 /* Engine - Query the queue groups assigned to a scheduling group. */
486 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
487 /* Engine - Query the configuration of a scheduling group's meter profiles. */
488 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
489 /* Engine - Configure a scheduling group's meter profiles. */
490 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
491 /* Engine - Bind a queue group to a scheduling group. */
492 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
493 /* Engine - Unbind a queue group from its scheduling group. */
494 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
495 /* Engine - Query the Engine configuration. */
496 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
497 /* Engine - Configure the statistics accumulator for an Engine. */
498 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
499 /* Engine - Clear the statistics accumulator for an Engine. */
500 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
501 /* Engine - Query the statistics accumulator for an Engine. */
502 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
503 /* Engine - Allocate an Engine RQ. */
504 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
505 /* Engine - Free an Engine RQ. */
506 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
507 /* Engine - Allocate an Engine CQ. */
508 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
509 /* Engine - Free an Engine CQ. */
510 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
511 /* Engine - Allocate an NQ. */
512 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
513 /* Engine - Free an NQ. */
514 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
515 /* Engine - Set the on-die RQE credit update location. */
516 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
518 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
520 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
522 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
524 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
526 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
527 /* Configures the BW of any VF */
528 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
529 /* Queries the BW of any VF */
530 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
532 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
534 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
536 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
538 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
540 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
542 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
544 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
546 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
548 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
549 #define HWRM_DBG_DUMP UINT32_C(0xff14)
551 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
553 #define HWRM_DBG_CFG UINT32_C(0xff16)
555 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
557 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
559 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
561 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
563 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
565 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
567 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
568 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
569 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
570 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
571 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
572 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
573 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
574 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
575 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
576 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
577 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
578 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
579 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
580 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
581 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
582 #define HWRM_NVM_READ UINT32_C(0xfffd)
583 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
584 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
585 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
586 uint16_t unused_0[3];
587 } __attribute__((packed));
590 /* ret_codes (size:64b/8B) */
593 /* Request was successfully executed by the HWRM. */
594 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
595 /* The HWRM failed to execute the request. */
596 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
598 * The request contains invalid argument(s) or input
601 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
603 * The requester is not allowed to access the requested
604 * resource. This error code shall be provided in a
605 * response to a request to query or modify an existing
606 * resource that is not accessible by the requester.
608 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
610 * The HWRM is unable to allocate the requested resource.
611 * This code only applies to requests for HWRM resource
614 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
616 * Invalid combination of flags is specified in the
619 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
621 * Invalid combination of enables fields is specified in
624 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
626 * Request contains a required TLV that is not supported by
627 * the installed version of firmware.
629 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
631 * No firmware buffer available to accept the request. Driver
632 * should retry the request.
634 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
636 * This error code is only reported by firmware when some
637 * sub-option of a supported HWRM command is unsupported.
639 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
641 * Generic HWRM execution error that represents an
644 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
646 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
647 /* Unsupported or invalid command */
648 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
649 #define HWRM_ERR_CODE_LAST \
650 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
651 uint16_t unused_0[3];
652 } __attribute__((packed));
655 /* hwrm_err_output (size:128b/16B) */
656 struct hwrm_err_output {
658 * Pass/Fail or error type
660 * Note: receiver to verify the in parameters, and fail the call
661 * with an error when appropriate
664 /* This field returns the type of original request. */
666 /* This field provides original sequence number of the command. */
669 * This field is the length of the response in bytes. The
670 * last byte of the response is a valid flag that will read
671 * as '1' when the command has been completely written to
675 /* debug info for this error response. */
677 /* debug info for this error response. */
680 * In the case of an error response, command specific error
681 * code is returned in this field.
685 * This field is used in Output records to indicate that the output
686 * is completely written to RAM. This field should be read as '1'
687 * to indicate that the output has been completely written.
688 * When writing a command completion or response to an internal processor,
689 * the order of writes has to be such that this field is written last.
692 } __attribute__((packed));
694 * Following is the signature for HWRM message field that indicates not
695 * applicable (All F's). Need to cast it the size of the field if needed.
697 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
698 /* hwrm_func_buf_rgtr */
699 #define HWRM_MAX_REQ_LEN 128
700 /* hwrm_selftest_qlist */
701 #define HWRM_MAX_RESP_LEN 280
702 /* 7 bit indirection table index. */
703 #define HW_HASH_INDEX_SIZE 0x80
704 #define HW_HASH_KEY_SIZE 40
705 /* valid key for HWRM response */
706 #define HWRM_RESP_VALID_KEY 1
707 #define HWRM_VERSION_MAJOR 1
708 #define HWRM_VERSION_MINOR 9
709 #define HWRM_VERSION_UPDATE 2
710 /* non-zero means beta version */
711 #define HWRM_VERSION_RSVD 53
712 #define HWRM_VERSION_STR "1.9.2.53"
719 /* hwrm_ver_get_input (size:192b/24B) */
720 struct hwrm_ver_get_input {
721 /* The HWRM command request type. */
724 * The completion ring to send the completion event on. This should
725 * be the NQ ID returned from the `nq_alloc` HWRM command.
729 * The sequence ID is used by the driver for tracking multiple
730 * commands. This ID is treated as opaque data by the firmware and
731 * the value is returned in the `hwrm_resp_hdr` upon completion.
735 * The target ID of the command:
736 * * 0x0-0xFFF8 - The function ID
737 * * 0xFFF8-0xFFFE - Reserved for internal processors
742 * A physical address pointer pointing to a host buffer that the
743 * command's response data will be written. This can be either a host
744 * physical address (HPA) or a guest physical address (GPA) and must
745 * point to a physically contiguous block of memory.
749 * This field represents the major version of HWRM interface
750 * specification supported by the driver HWRM implementation.
751 * The interface major version is intended to change only when
752 * non backward compatible changes are made to the HWRM
753 * interface specification.
755 uint8_t hwrm_intf_maj;
757 * This field represents the minor version of HWRM interface
758 * specification supported by the driver HWRM implementation.
759 * A change in interface minor version is used to reflect
760 * significant backward compatible modification to HWRM
761 * interface specification.
762 * This can be due to addition or removal of functionality.
763 * HWRM interface specifications with the same major version
764 * but different minor versions are compatible.
766 uint8_t hwrm_intf_min;
768 * This field represents the update version of HWRM interface
769 * specification supported by the driver HWRM implementation.
770 * The interface update version is used to reflect minor
771 * changes or bug fixes to a released HWRM interface
774 uint8_t hwrm_intf_upd;
776 } __attribute__((packed));
778 /* hwrm_ver_get_output (size:1408b/176B) */
779 struct hwrm_ver_get_output {
780 /* The specific error status for the command. */
782 /* The HWRM command request type. */
784 /* The sequence ID from the original command. */
786 /* The length of the response data in number of bytes. */
789 * This field represents the major version of HWRM interface
790 * specification supported by the HWRM implementation.
791 * The interface major version is intended to change only when
792 * non backward compatible changes are made to the HWRM
793 * interface specification.
794 * A HWRM implementation that is compliant with this
795 * specification shall provide value of 1 in this field.
797 uint8_t hwrm_intf_maj_8b;
799 * This field represents the minor version of HWRM interface
800 * specification supported by the HWRM implementation.
801 * A change in interface minor version is used to reflect
802 * significant backward compatible modification to HWRM
803 * interface specification.
804 * This can be due to addition or removal of functionality.
805 * HWRM interface specifications with the same major version
806 * but different minor versions are compatible.
807 * A HWRM implementation that is compliant with this
808 * specification shall provide value of 2 in this field.
810 uint8_t hwrm_intf_min_8b;
812 * This field represents the update version of HWRM interface
813 * specification supported by the HWRM implementation.
814 * The interface update version is used to reflect minor
815 * changes or bug fixes to a released HWRM interface
817 * A HWRM implementation that is compliant with this
818 * specification shall provide value of 2 in this field.
820 uint8_t hwrm_intf_upd_8b;
821 uint8_t hwrm_intf_rsvd_8b;
823 * This field represents the major version of HWRM firmware.
824 * A change in firmware major version represents a major
827 uint8_t hwrm_fw_maj_8b;
829 * This field represents the minor version of HWRM firmware.
830 * A change in firmware minor version represents significant
831 * firmware functionality changes.
833 uint8_t hwrm_fw_min_8b;
835 * This field represents the build version of HWRM firmware.
836 * A change in firmware build version represents bug fixes
837 * to a released firmware.
839 uint8_t hwrm_fw_bld_8b;
841 * This field is a reserved field. This field can be used to
842 * represent firmware branches or customer specific releases
843 * tied to a specific (major,minor,update) version of the
846 uint8_t hwrm_fw_rsvd_8b;
848 * This field represents the major version of mgmt firmware.
849 * A change in major version represents a major release.
851 uint8_t mgmt_fw_maj_8b;
853 * This field represents the minor version of mgmt firmware.
854 * A change in minor version represents significant
855 * functionality changes.
857 uint8_t mgmt_fw_min_8b;
859 * This field represents the build version of mgmt firmware.
860 * A change in update version represents bug fixes.
862 uint8_t mgmt_fw_bld_8b;
864 * This field is a reserved field. This field can be used to
865 * represent firmware branches or customer specific releases
866 * tied to a specific (major,minor,update) version
868 uint8_t mgmt_fw_rsvd_8b;
870 * This field represents the major version of network
872 * A change in major version represents a major release.
874 uint8_t netctrl_fw_maj_8b;
876 * This field represents the minor version of network
878 * A change in minor version represents significant
879 * functionality changes.
881 uint8_t netctrl_fw_min_8b;
883 * This field represents the build version of network
885 * A change in update version represents bug fixes.
887 uint8_t netctrl_fw_bld_8b;
889 * This field is a reserved field. This field can be used to
890 * represent firmware branches or customer specific releases
891 * tied to a specific (major,minor,update) version
893 uint8_t netctrl_fw_rsvd_8b;
895 * This field is used to indicate device's capabilities and
898 uint32_t dev_caps_cfg;
900 * If set to 1, then secure firmware update behavior
902 * If set to 0, then secure firmware update behavior is
905 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
908 * If set to 1, then firmware based DCBX agent is supported.
909 * If set to 0, then firmware based DCBX agent capability
910 * is not supported on this device.
912 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
915 * If set to 1, then HWRM short command format is supported.
916 * If set to 0, then HWRM short command format is not supported.
918 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
921 * If set to 1, then HWRM short command format is required.
922 * If set to 0, then HWRM short command format is not required.
924 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
927 * If set to 1, then the KONG host mailbox channel is supported.
928 * If set to 0, then the KONG host mailbox channel is not supported.
929 * By default, this flag should be 0 for older version of core firmware.
931 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
934 * If set to 1, then the 64bit flow handle is supported in addition to the
935 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
936 * supported. By default, this flag should be 0 for older version of core firmware.
938 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
941 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
942 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
943 * If set to 0, then filter types not supported.
944 * By default, this flag should be 0 for older version of core firmware.
946 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
949 * If set to 1, firmware is capable to support virtio vSwitch offload model.
950 * If set to 0, firmware can't supported virtio vSwitch offload model.
951 * By default, this flag should be 0 for older version of core firmware.
953 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
956 * If set to 1, firmware is capable to support trusted VF.
957 * If set to 0, firmware is not capable to support trusted VF.
958 * By default, this flag should be 0 for older version of core firmware.
960 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
963 * This field represents the major version of RoCE firmware.
964 * A change in major version represents a major release.
966 uint8_t roce_fw_maj_8b;
968 * This field represents the minor version of RoCE firmware.
969 * A change in minor version represents significant
970 * functionality changes.
972 uint8_t roce_fw_min_8b;
974 * This field represents the build version of RoCE firmware.
975 * A change in update version represents bug fixes.
977 uint8_t roce_fw_bld_8b;
979 * This field is a reserved field. This field can be used to
980 * represent firmware branches or customer specific releases
981 * tied to a specific (major,minor,update) version
983 uint8_t roce_fw_rsvd_8b;
985 * This field represents the name of HWRM FW (ASCII chars
986 * with NULL at the end).
988 char hwrm_fw_name[16];
990 * This field represents the name of mgmt FW (ASCII chars
991 * with NULL at the end).
993 char mgmt_fw_name[16];
995 * This field represents the name of network control
996 * firmware (ASCII chars with NULL at the end).
998 char netctrl_fw_name[16];
1000 * This field is reserved for future use.
1001 * The responder should set it to 0.
1002 * The requester should ignore this field.
1004 uint8_t reserved2[16];
1006 * This field represents the name of RoCE FW (ASCII chars
1007 * with NULL at the end).
1009 char roce_fw_name[16];
1010 /* This field returns the chip number. */
1012 /* This field returns the revision of chip. */
1014 /* This field returns the chip metal number. */
1016 /* This field returns the bond id of the chip. */
1017 uint8_t chip_bond_id;
1018 /* This value indicates the type of platform used for chip implementation. */
1019 uint8_t chip_platform_type;
1021 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1022 /* FPGA platform of the chip. */
1023 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1024 /* Palladium platform of the chip. */
1025 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1026 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1027 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1029 * This field returns the maximum value of request window that
1030 * is supported by the HWRM. The request window is mapped
1031 * into device address space using MMIO.
1033 uint16_t max_req_win_len;
1035 * This field returns the maximum value of response buffer in
1038 uint16_t max_resp_len;
1040 * This field returns the default request timeout value in
1043 uint16_t def_req_timeout;
1045 * This field will indicate if any subsystems is not fully
1050 * If set to 1, device is not ready.
1051 * If set to 0, device is ready to accept all HWRM commands.
1053 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1055 * If set to 1, external version present.
1056 * If set to 0, external version not present.
1058 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1059 uint8_t unused_0[2];
1061 * For backward compatibility this field must be set to 1.
1062 * Older drivers might look for this field to be 1 before
1063 * processing the message.
1067 * This field represents the major version of HWRM interface
1068 * specification supported by the HWRM implementation.
1069 * The interface major version is intended to change only when
1070 * non backward compatible changes are made to the HWRM
1071 * interface specification. A HWRM implementation that is
1072 * compliant with this specification shall provide value of 1
1075 uint16_t hwrm_intf_major;
1077 * This field represents the minor version of HWRM interface
1078 * specification supported by the HWRM implementation.
1079 * A change in interface minor version is used to reflect
1080 * significant backward compatible modification to HWRM
1081 * interface specification. This can be due to addition or
1082 * removal of functionality. HWRM interface specifications
1083 * with the same major version but different minor versions are
1084 * compatible. A HWRM implementation that is compliant with
1085 * this specification shall provide value of 2 in this field.
1087 uint16_t hwrm_intf_minor;
1089 * This field represents the update version of HWRM interface
1090 * specification supported by the HWRM implementation. The
1091 * interface update version is used to reflect minor changes or
1092 * bug fixes to a released HWRM interface specification.
1093 * A HWRM implementation that is compliant with this
1094 * specification shall provide value of 2 in this field.
1096 uint16_t hwrm_intf_build;
1098 * This field represents the patch version of HWRM interface
1099 * specification supported by the HWRM implementation.
1101 uint16_t hwrm_intf_patch;
1103 * This field represents the major version of HWRM firmware.
1104 * A change in firmware major version represents a major
1107 uint16_t hwrm_fw_major;
1109 * This field represents the minor version of HWRM firmware.
1110 * A change in firmware minor version represents significant
1111 * firmware functionality changes.
1113 uint16_t hwrm_fw_minor;
1115 * This field represents the build version of HWRM firmware.
1116 * A change in firmware build version represents bug fixes to
1117 * a released firmware.
1119 uint16_t hwrm_fw_build;
1121 * This field is a reserved field.
1122 * This field can be used to represent firmware branches or customer
1123 * specific releases tied to a specific (major,minor,update) version
1124 * of the HWRM firmware.
1126 uint16_t hwrm_fw_patch;
1128 * This field represents the major version of mgmt firmware.
1129 * A change in major version represents a major release.
1131 uint16_t mgmt_fw_major;
1133 * This field represents the minor version of HWRM firmware.
1134 * A change in firmware minor version represents significant
1135 * firmware functionality changes.
1137 uint16_t mgmt_fw_minor;
1139 * This field represents the build version of mgmt firmware.
1140 * A change in update version represents bug fixes.
1142 uint16_t mgmt_fw_build;
1144 * This field is a reserved field. This field can be used to
1145 * represent firmware branches or customer specific releases
1146 * tied to a specific (major,minor,update) version.
1148 uint16_t mgmt_fw_patch;
1150 * This field represents the major version of network control
1151 * firmware. A change in major version represents
1154 uint16_t netctrl_fw_major;
1156 * This field represents the minor version of network control
1157 * firmware. A change in minor version represents significant
1158 * functionality changes.
1160 uint16_t netctrl_fw_minor;
1162 * This field represents the build version of network control
1163 * firmware. A change in update version represents bug fixes.
1165 uint16_t netctrl_fw_build;
1167 * This field is a reserved field. This field can be used to
1168 * represent firmware branches or customer specific releases
1169 * tied to a specific (major,minor,update) version
1171 uint16_t netctrl_fw_patch;
1173 * This field represents the major version of RoCE firmware.
1174 * A change in major version represents a major release.
1176 uint16_t roce_fw_major;
1178 * This field represents the minor version of RoCE firmware.
1179 * A change in minor version represents significant
1180 * functionality changes.
1182 uint16_t roce_fw_minor;
1184 * This field represents the build version of RoCE firmware.
1185 * A change in update version represents bug fixes.
1187 uint16_t roce_fw_build;
1189 * This field is a reserved field. This field can be used to
1190 * represent firmware branches or customer specific releases
1191 * tied to a specific (major,minor,update) version
1193 uint16_t roce_fw_patch;
1195 * This field returns the maximum extended request length acceptable
1196 * by the device which allows requests greater than mailbox size when
1197 * used with the short cmd request format.
1199 uint16_t max_ext_req_len;
1200 uint8_t unused_1[5];
1202 * This field is used in Output records to indicate that the output
1203 * is completely written to RAM. This field should be read as '1'
1204 * to indicate that the output has been completely written.
1205 * When writing a command completion or response to an internal processor,
1206 * the order of writes has to be such that this field is written last.
1209 } __attribute__((packed));
1211 /* bd_base (size:64b/8B) */
1214 /* This value identifies the type of buffer descriptor. */
1215 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1216 #define BD_BASE_TYPE_SFT 0
1218 * Indicates that this BD is 16B long and is used for
1219 * normal L2 packet transmission.
1221 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1223 * Indicates that this BD is 1BB long and is an empty
1224 * TX BD. Not valid for use by the driver.
1226 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1228 * Indicates that this BD is 16B long and is an RX Producer
1229 * (ie. empty) buffer descriptor.
1231 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1233 * Indicates that this BD is 16B long and is an RX
1234 * Producer Buffer BD.
1236 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1238 * Indicates that this BD is 16B long and is an
1239 * RX Producer Assembly Buffer Descriptor.
1241 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1243 * Indicates that this BD is 32B long and is used for
1244 * normal L2 packet transmission.
1246 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1248 * Indicates that this BD is 32B long and is used for
1249 * L2 packet transmission for small packets that require
1252 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1253 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1254 uint8_t unused_1[7];
1255 } __attribute__((packed));
1257 /* tx_bd_short (size:128b/16B) */
1258 struct tx_bd_short {
1260 * All bits in this field must be valid on the first BD of a packet.
1261 * Only the packet_end bit must be valid for the remaining BDs
1264 uint16_t flags_type;
1265 /* This value identifies the type of buffer descriptor. */
1266 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1267 #define TX_BD_SHORT_TYPE_SFT 0
1269 * Indicates that this BD is 16B long and is used for
1270 * normal L2 packet transmission.
1272 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1273 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1275 * All bits in this field must be valid on the first BD of a packet.
1276 * Only the packet_end bit must be valid for the remaining BDs
1279 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1280 #define TX_BD_SHORT_FLAGS_SFT 6
1282 * If set to 1, the packet ends with the data in the buffer
1283 * pointed to by this descriptor. This flag must be
1284 * valid on every BD.
1286 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1288 * If set to 1, the device will not generate a completion for
1289 * this transmit packet unless there is an error in it's
1292 * is set to 0, then the packet will be completed normally.
1294 * This bit must be valid only on the first BD of a packet.
1296 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1298 * This value indicates how many 16B BD locations are consumed
1299 * in the ring by this packet.
1300 * A value of 1 indicates that this BD is the only BD (and that
1301 * the it is a short BD). A value
1302 * of 3 indicates either 3 short BDs or 1 long BD and one short
1303 * BD in the packet. A value of 0 indicates
1304 * that there are 32 BD locations in the packet (the maximum).
1306 * This field is valid only on the first BD of a packet.
1308 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1309 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1311 * This value is a hint for the length of the entire packet.
1312 * It is used by the chip to optimize internal processing.
1314 * The packet will be dropped if the hint is too short.
1316 * This field is valid only on the first BD of a packet.
1318 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1319 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1320 /* indicates packet length < 512B */
1321 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1322 /* indicates 512 <= packet length < 1KB */
1323 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1324 /* indicates 1KB <= packet length < 2KB */
1325 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1326 /* indicates packet length >= 2KB */
1327 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1328 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1329 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1331 * If set to 1, the device immediately updates the Send Consumer
1332 * Index after the buffer associated with this descriptor has
1333 * been transferred via DMA to NIC memory from host memory. An
1334 * interrupt may or may not be generated according to the state
1335 * of the interrupt avoidance mechanisms. If this bit
1336 * is set to 0, then the Consumer Index is only updated as soon
1337 * as one of the host interrupt coalescing conditions has been met.
1339 * This bit must be valid on the first BD of a packet.
1341 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1343 * This is the length of the host physical buffer this BD describes
1346 * This field must be valid on all BDs of a packet.
1350 * The opaque data field is pass through to the completion and can be
1351 * used for any data that the driver wants to associate with the
1354 * This field must be valid on the first BD of a packet.
1358 * This is the host physical address for the portion of the packet
1359 * described by this TX BD.
1361 * This value must be valid on all BDs of a packet.
1364 } __attribute__((packed));
1366 /* tx_bd_long (size:128b/16B) */
1368 /* This value identifies the type of buffer descriptor. */
1369 uint16_t flags_type;
1371 * This value indicates the type of buffer descriptor.
1374 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1375 #define TX_BD_LONG_TYPE_SFT 0
1377 * Indicates that this BD is 32B long and is used for
1378 * normal L2 packet transmission.
1380 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1381 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1383 * All bits in this field must be valid on the first BD of a packet.
1384 * Only the packet_end bit must be valid for the remaining BDs
1387 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1388 #define TX_BD_LONG_FLAGS_SFT 6
1390 * If set to 1, the packet ends with the data in the buffer
1391 * pointed to by this descriptor. This flag must be
1392 * valid on every BD.
1394 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1396 * If set to 1, the device will not generate a completion for
1397 * this transmit packet unless there is an error in it's
1400 * is set to 0, then the packet will be completed normally.
1402 * This bit must be valid only on the first BD of a packet.
1404 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1406 * This value indicates how many 16B BD locations are consumed
1407 * in the ring by this packet.
1408 * A value of 1 indicates that this BD is the only BD (and that
1409 * the it is a short BD). A value
1410 * of 3 indicates either 3 short BDs or 1 long BD and one short
1411 * BD in the packet. A value of 0 indicates
1412 * that there are 32 BD locations in the packet (the maximum).
1414 * This field is valid only on the first BD of a packet.
1416 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1417 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1419 * This value is a hint for the length of the entire packet.
1420 * It is used by the chip to optimize internal processing.
1422 * The packet will be dropped if the hint is too short.
1424 * This field is valid only on the first BD of a packet.
1426 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1427 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1428 /* indicates packet length < 512B */
1429 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1430 /* indicates 512 <= packet length < 1KB */
1431 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1432 /* indicates 1KB <= packet length < 2KB */
1433 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1434 /* indicates packet length >= 2KB */
1435 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1436 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1438 * If set to 1, the device immediately updates the Send Consumer
1439 * Index after the buffer associated with this descriptor has
1440 * been transferred via DMA to NIC memory from host memory. An
1441 * interrupt may or may not be generated according to the state
1442 * of the interrupt avoidance mechanisms. If this bit
1443 * is set to 0, then the Consumer Index is only updated as soon
1444 * as one of the host interrupt coalescing conditions has been met.
1446 * This bit must be valid on the first BD of a packet.
1448 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1450 * This is the length of the host physical buffer this BD describes
1453 * This field must be valid on all BDs of a packet.
1457 * The opaque data field is pass through to the completion and can be
1458 * used for any data that the driver wants to associate with the
1461 * This field must be valid on the first BD of a packet.
1465 * This is the host physical address for the portion of the packet
1466 * described by this TX BD.
1468 * This value must be valid on all BDs of a packet.
1471 } __attribute__((packed));
1473 /* Last 16 bytes of tx_bd_long. */
1474 /* tx_bd_long_hi (size:128b/16B) */
1475 struct tx_bd_long_hi {
1477 * All bits in this field must be valid on the first BD of a packet.
1478 * Their value on other BDs of the packet will be ignored.
1482 * If set to 1, the controller replaces the TCP/UPD checksum
1483 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1484 * checksum field of the encapsulated TCP/UDP packets with the
1485 * hardware calculated TCP/UDP checksum for the packet associated
1486 * with this descriptor. The flag is ignored if the LSO flag is set.
1488 * This bit must be valid on the first BD of a packet.
1490 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1492 * If set to 1, the controller replaces the IP checksum of the
1493 * normal packets, or the inner IP checksum of the encapsulated
1494 * packets with the hardware calculated IP checksum for the
1495 * packet associated with this descriptor.
1497 * This bit must be valid on the first BD of a packet.
1499 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1501 * If set to 1, the controller will not append an Ethernet CRC
1502 * to the end of the frame.
1504 * This bit must be valid on the first BD of a packet.
1506 * Packet must be 64B or longer when this flag is set. It is not
1507 * useful to use this bit with any form of TX offload such as
1508 * CSO or LSO. The intent is that the packet from the host already
1509 * has a valid Ethernet CRC on the packet.
1511 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1513 * If set to 1, the device will record the time at which the packet
1514 * was actually transmitted at the TX MAC.
1516 * This bit must be valid on the first BD of a packet.
1518 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1520 * If set to 1, The controller replaces the tunnel IP checksum
1521 * field with hardware calculated IP checksum for the IP header
1522 * of the packet associated with this descriptor.
1524 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1525 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1526 * bit is set, outer UDP checksum will be calculated for the following
1528 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1529 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1530 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1531 * checksum will not be calculated.
1532 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1533 * as part of LSO operation.
1535 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1537 * If set to 1, the device will treat this packet with LSO(Large
1538 * Send Offload) processing for both normal or encapsulated
1539 * packets, which is a form of TCP segmentation. When this bit
1540 * is 1, the hdr_size and mss fields must be valid. The driver
1541 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1542 * flags since the controller will replace the appropriate
1543 * checksum fields for segmented packets.
1545 * When this bit is 1, the hdr_size and mss fields must be valid.
1547 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1549 * If set to zero when LSO is '1', then the IPID will be treated
1550 * as a 16b number and will be wrapped if it exceeds a value of
1553 * If set to one when LSO is '1', then the IPID will be treated
1554 * as a 15b number and will be wrapped if it exceeds a value 0f
1557 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1559 * If set to zero when LSO is '1', then the IPID of the tunnel
1560 * IP header will not be modified during LSO operations.
1562 * If set to one when LSO is '1', then the IPID of the tunnel
1563 * IP header will be incremented for each subsequent segment of an
1566 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1569 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1571 * If set to '1', then the RoCE ICRC will be appended to the
1572 * packet. Packet must be a valid RoCE format packet.
1574 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1576 * If set to '1', then the FCoE CRC will be appended to the
1577 * packet. Packet must be a valid FCoE format packet.
1579 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1582 * When LSO is '1', this field must contain the offset of the
1583 * TCP payload from the beginning of the packet in as
1584 * 16b words. In case of encapsulated/tunneling packet, this field
1585 * contains the offset of the inner TCP payload from beginning of the
1586 * packet as 16-bit words.
1588 * This value must be valid on the first BD of a packet.
1590 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1591 #define TX_BD_LONG_HDR_SIZE_SFT 0
1594 * This is the MSS value that will be used to do the LSO processing.
1595 * The value is the length in bytes of the TCP payload for each
1596 * segment generated by the LSO operation.
1598 * This value must be valid on the first BD of a packet.
1600 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1601 #define TX_BD_LONG_MSS_SFT 0
1604 * This value selects a CFA action to perform on the packet.
1605 * Set this value to zero if no CFA action is desired.
1607 * This value must be valid on the first BD of a packet.
1609 uint16_t cfa_action;
1611 * This value is action meta-data that defines CFA edit operations
1612 * that are done in addition to any action editing.
1615 /* When key=1, This is the VLAN tag VID value. */
1616 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1617 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1618 /* When key=1, This is the VLAN tag DE value. */
1619 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1620 /* When key=1, This is the VLAN tag PRI value. */
1621 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1622 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1623 /* When key=1, This is the VLAN tag TPID select value. */
1624 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1625 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1627 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1629 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1631 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1633 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1635 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1636 /* Value programmed in CFA VLANTPID register. */
1637 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1638 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1639 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1640 /* When key=1, This is the VLAN tag TPID select value. */
1641 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1642 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1644 * This field identifies the type of edit to be performed
1647 * This value must be valid on the first BD of a packet.
1649 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1650 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1652 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1654 * - meta[17:16] - TPID select value (0 = 0x8100).
1655 * - meta[15:12] - PRI/DE value.
1656 * - meta[11:0] - VID value.
1658 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1659 #define TX_BD_LONG_CFA_META_KEY_LAST \
1660 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1661 } __attribute__((packed));
1664 * This structure is used to inform the NIC of packet data that needs to be
1665 * transmitted with additional processing that requires extra data such as
1666 * VLAN insertion plus attached inline data. This BD type may be used to
1667 * improve latency for small packets needing the additional extended features
1668 * supported by long BDs.
1670 /* tx_bd_long_inline (size:256b/32B) */
1671 struct tx_bd_long_inline {
1672 uint16_t flags_type;
1673 /* This value identifies the type of buffer descriptor. */
1674 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1675 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1677 * This type of BD is 32B long and is used for inline L2 packet
1680 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1681 #define TX_BD_LONG_INLINE_TYPE_LAST \
1682 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1684 * All bits in this field may be set on the first BD of a packet.
1685 * Only the packet_end bit may be set in non-first BDs.
1687 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1688 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1690 * If set to 1, the packet ends with the data in the buffer
1691 * pointed to by this descriptor. This flag must be
1692 * valid on every BD.
1694 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1696 * If set to 1, the device will not generate a completion for
1697 * this transmit packet unless there is an error in its processing.
1698 * If this bit is set to 0, then the packet will be completed
1701 * This bit may be set only on the first BD of a packet.
1703 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1705 * This value indicates how many 16B BD locations are consumed
1706 * in the ring by this packet, including the BD and inline
1709 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1710 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1711 /* This field is deprecated. */
1712 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1713 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
1715 * If set to 1, the device immediately updates the Send Consumer
1716 * Index after the buffer associated with this descriptor has
1717 * been transferred via DMA to NIC memory from host memory. An
1718 * interrupt may or may not be generated according to the state
1719 * of the interrupt avoidance mechanisms. If this bit
1720 * is set to 0, then the Consumer Index is only updated as soon
1721 * as one of the host interrupt coalescing conditions has been met.
1723 * This bit must be valid on the first BD of a packet.
1725 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
1727 * This is the length of the inline data, not including BD length, in
1729 * The maximum value is 480.
1731 * This field must be valid on all BDs of a packet.
1735 * The opaque data field is passed through to the completion and can be
1736 * used for any data that the driver wants to associate with the transmit
1739 * This field must be valid on the first BD of a packet.
1744 * All bits in this field must be valid on the first BD of a packet.
1745 * Their value on other BDs of the packet is ignored.
1749 * If set to 1, the controller replaces the TCP/UPD checksum
1750 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1751 * checksum field of the encapsulated TCP/UDP packets with the
1752 * hardware calculated TCP/UDP checksum for the packet associated
1753 * with this descriptor. The flag is ignored if the LSO flag is set.
1755 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1757 * If set to 1, the controller replaces the IP checksum of the
1758 * normal packets, or the inner IP checksum of the encapsulated
1759 * packets with the hardware calculated IP checksum for the
1760 * packet associated with this descriptor.
1762 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1764 * If set to 1, the controller will not append an Ethernet CRC
1765 * to the end of the frame.
1767 * Packet must be 64B or longer when this flag is set. It is not
1768 * useful to use this bit with any form of TX offload such as
1769 * CSO or LSO. The intent is that the packet from the host already
1770 * has a valid Ethernet CRC on the packet.
1772 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
1774 * If set to 1, the device will record the time at which the packet
1775 * was actually transmitted at the TX MAC.
1777 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
1779 * If set to 1, the controller replaces the tunnel IP checksum
1780 * field with hardware calculated IP checksum for the IP header
1781 * of the packet associated with this descriptor. The hardware
1782 * updates an outer UDP checksum if it is non-zero.
1784 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1786 * This bit must be 0 for BDs of this type. LSO is not supported with
1789 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
1790 /* Since LSO is not supported with inline BDs, this bit is not used. */
1791 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
1792 /* Since LSO is not supported with inline BDs, this bit is not used. */
1793 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
1795 * If set to '1', then the RoCE ICRC will be appended to the
1796 * packet. Packet must be a valid RoCE format packet.
1798 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
1800 * If set to '1', then the FCoE CRC will be appended to the
1801 * packet. Packet must be a valid FCoE format packet.
1803 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
1808 * This value selects a CFA action to perform on the packet.
1809 * Set this value to zero if no CFA action is desired.
1811 * This value must be valid on the first BD of a packet.
1813 uint16_t cfa_action;
1815 * This value is action meta-data that defines CFA edit operations
1816 * that are done in addition to any action editing.
1819 /* When key = 1, this is the VLAN tag VID value. */
1820 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1821 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
1822 /* When key = 1, this is the VLAN tag DE value. */
1823 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
1824 /* When key = 1, this is the VLAN tag PRI value. */
1825 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1826 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
1827 /* When key = 1, this is the VLAN tag TPID select value. */
1828 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1829 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
1831 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
1832 (UINT32_C(0x0) << 16)
1834 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
1835 (UINT32_C(0x1) << 16)
1837 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
1838 (UINT32_C(0x2) << 16)
1840 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
1841 (UINT32_C(0x3) << 16)
1843 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
1844 (UINT32_C(0x4) << 16)
1845 /* Value programmed in CFA VLANTPID register. */
1846 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
1847 (UINT32_C(0x5) << 16)
1848 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
1849 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
1850 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
1852 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
1854 * This field identifies the type of edit to be performed
1857 * This value must be valid on the first BD of a packet.
1859 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
1860 UINT32_C(0xf0000000)
1861 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
1863 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
1864 (UINT32_C(0x0) << 28)
1866 * - meta[17:16] - TPID select value (0 = 0x8100).
1867 * - meta[15:12] - PRI/DE value.
1868 * - meta[11:0] - VID value.
1870 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
1871 (UINT32_C(0x1) << 28)
1872 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
1873 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
1874 } __attribute__((packed));
1876 /* tx_bd_empty (size:128b/16B) */
1877 struct tx_bd_empty {
1878 /* This value identifies the type of buffer descriptor. */
1880 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1881 #define TX_BD_EMPTY_TYPE_SFT 0
1883 * Indicates that this BD is 1BB long and is an empty
1884 * TX BD. Not valid for use by the driver.
1886 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1887 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1888 uint8_t unused_1[3];
1890 uint8_t unused_3[3];
1891 uint8_t unused_4[8];
1892 } __attribute__((packed));
1894 /* rx_prod_pkt_bd (size:128b/16B) */
1895 struct rx_prod_pkt_bd {
1896 /* This value identifies the type of buffer descriptor. */
1897 uint16_t flags_type;
1898 /* This value identifies the type of buffer descriptor. */
1899 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
1900 #define RX_PROD_PKT_BD_TYPE_SFT 0
1902 * Indicates that this BD is 16B long and is an RX Producer
1903 * (ie. empty) buffer descriptor.
1905 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
1906 #define RX_PROD_PKT_BD_TYPE_LAST \
1907 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
1908 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
1909 #define RX_PROD_PKT_BD_FLAGS_SFT 6
1911 * If set to 1, the packet will be placed at the address plus
1912 * 2B. The 2 Bytes of padding will be written as zero.
1914 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
1916 * If set to 1, the packet write will be padded out to the
1917 * nearest cache-line with zero value padding.
1919 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
1921 * This value is the number of additional buffers in the ring that
1922 * describe the buffer space to be consumed for the this packet.
1923 * If the value is zero, then the packet must fit within the
1924 * space described by this BD. If this value is 1 or more, it
1925 * indicates how many additional "buffer" BDs are in the ring
1926 * immediately following this BD to be used for the same
1929 * Even if the packet to be placed does not need all the
1930 * additional buffers, they will be consumed anyway.
1932 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
1933 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
1935 * This is the length in Bytes of the host physical buffer where
1936 * data for the packet may be placed in host memory.
1940 * The opaque data field is pass through to the completion and can be
1941 * used for any data that the driver wants to associate with this
1942 * receive buffer set.
1946 * This is the host physical address where data for the packet may
1947 * by placed in host memory.
1950 } __attribute__((packed));
1952 /* rx_prod_bfr_bd (size:128b/16B) */
1953 struct rx_prod_bfr_bd {
1954 /* This value identifies the type of buffer descriptor. */
1955 uint16_t flags_type;
1956 /* This value identifies the type of buffer descriptor. */
1957 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
1958 #define RX_PROD_BFR_BD_TYPE_SFT 0
1960 * Indicates that this BD is 16B long and is an RX
1961 * Producer Buffer BD.
1963 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
1964 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
1965 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
1966 #define RX_PROD_BFR_BD_FLAGS_SFT 6
1968 * This is the length in Bytes of the host physical buffer where
1969 * data for the packet may be placed in host memory.
1972 /* This field is not used. */
1975 * This is the host physical address where data for the packet may
1976 * by placed in host memory.
1979 } __attribute__((packed));
1981 /* rx_prod_agg_bd (size:128b/16B) */
1982 struct rx_prod_agg_bd {
1983 /* This value identifies the type of buffer descriptor. */
1984 uint16_t flags_type;
1985 /* This value identifies the type of buffer descriptor. */
1986 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
1987 #define RX_PROD_AGG_BD_TYPE_SFT 0
1989 * Indicates that this BD is 16B long and is an
1990 * RX Producer Assembly Buffer Descriptor.
1992 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
1993 #define RX_PROD_AGG_BD_TYPE_LAST \
1994 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
1995 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
1996 #define RX_PROD_AGG_BD_FLAGS_SFT 6
1998 * If set to 1, the packet write will be padded out to the
1999 * nearest cache-line with zero value padding.
2001 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2003 * This is the length in Bytes of the host physical buffer where
2004 * data for the packet may be placed in host memory.
2008 * The opaque data field is pass through to the completion and can be
2009 * used for any data that the driver wants to associate with this
2010 * receive assembly buffer.
2014 * This is the host physical address where data for the packet may
2015 * by placed in host memory.
2018 } __attribute__((packed));
2020 /* cmpl_base (size:128b/16B) */
2024 * This field indicates the exact type of the completion.
2025 * By convention, the LSB identifies the length of the
2026 * record in 16B units. Even values indicate 16B
2027 * records. Odd values indicate 32B
2030 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2031 #define CMPL_BASE_TYPE_SFT 0
2034 * Completion of TX packet. Length = 16B
2036 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2039 * Completion of and L2 RX packet. Length = 32B
2041 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2043 * RX Aggregation Buffer completion :
2044 * Completion of an L2 aggregation buffer in support of
2045 * TPA, HDS, or Jumbo packet completion. Length = 16B
2047 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2049 * RX L2 TPA Start Completion:
2050 * Completion at the beginning of a TPA operation.
2053 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2055 * RX L2 TPA End Completion:
2056 * Completion at the end of a TPA operation.
2059 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2061 * Statistics Ejection Completion:
2062 * Completion of statistics data ejection buffer.
2065 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2067 * HWRM Command Completion:
2068 * Completion of an HWRM command.
2070 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2071 /* Forwarded HWRM Request */
2072 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2073 /* Forwarded HWRM Response */
2074 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2075 /* HWRM Asynchronous Event Information */
2076 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2077 /* CQ Notification */
2078 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2079 /* SRQ Threshold Event */
2080 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2081 /* DBQ Threshold Event */
2082 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2083 /* QP Async Notification */
2084 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2085 /* Function Async Notification */
2086 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2087 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2093 * This value is written by the NIC such that it will be different
2094 * for each pass through the completion queue. The even passes
2095 * will write 1. The odd passes will write 0.
2098 #define CMPL_BASE_V UINT32_C(0x1)
2099 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2100 #define CMPL_BASE_INFO3_SFT 1
2103 } __attribute__((packed));
2105 /* tx_cmpl (size:128b/16B) */
2107 uint16_t flags_type;
2109 * This field indicates the exact type of the completion.
2110 * By convention, the LSB identifies the length of the
2111 * record in 16B units. Even values indicate 16B
2112 * records. Odd values indicate 32B
2115 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2116 #define TX_CMPL_TYPE_SFT 0
2119 * Completion of TX packet. Length = 16B
2121 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2122 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2123 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2124 #define TX_CMPL_FLAGS_SFT 6
2126 * When this bit is '1', it indicates a packet that has an
2127 * error of some type. Type of error is indicated in
2130 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2132 * When this bit is '1', it indicates that the packet completed
2133 * was transmitted using the push acceleration data provided
2134 * by the driver. When this bit is '0', it indicates that the
2135 * packet had not push acceleration data written or was executed
2136 * as a normal packet even though push data was provided.
2138 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2139 /* unused1 is 16 b */
2142 * This is a copy of the opaque field from the first TX BD of this
2143 * transmitted packet.
2148 * This value is written by the NIC such that it will be different
2149 * for each pass through the completion queue. The even passes
2150 * will write 1. The odd passes will write 0.
2152 #define TX_CMPL_V UINT32_C(0x1)
2153 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2154 #define TX_CMPL_ERRORS_SFT 1
2156 * This error indicates that there was some sort of problem
2157 * with the BDs for the packet.
2159 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2160 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2162 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
2165 * BDs were not formatted correctly.
2167 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
2168 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2169 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2171 * When this bit is '1', it indicates that the length of
2172 * the packet was zero. No packet was transmitted.
2174 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2176 * When this bit is '1', it indicates that the packet
2177 * was longer than the programmed limit in TDI. No
2178 * packet was transmitted.
2180 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2182 * When this bit is '1', it indicates that one or more of the
2183 * BDs associated with this packet generated a PCI error.
2184 * This probably means the address was not valid.
2186 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2188 * When this bit is '1', it indicates that the packet was longer
2189 * than indicated by the hint. No packet was transmitted.
2191 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2193 * When this bit is '1', it indicates that the packet was
2194 * dropped due to Poison TLP error on one or more of the
2195 * TLPs in the PXP completion.
2197 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2198 /* unused2 is 16 b */
2200 /* unused3 is 32 b */
2202 } __attribute__((packed));
2204 /* rx_pkt_cmpl (size:128b/16B) */
2205 struct rx_pkt_cmpl {
2206 uint16_t flags_type;
2208 * This field indicates the exact type of the completion.
2209 * By convention, the LSB identifies the length of the
2210 * record in 16B units. Even values indicate 16B
2211 * records. Odd values indicate 32B
2214 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2215 #define RX_PKT_CMPL_TYPE_SFT 0
2218 * Completion of and L2 RX packet. Length = 32B
2220 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2221 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2222 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2223 #define RX_PKT_CMPL_FLAGS_SFT 6
2225 * When this bit is '1', it indicates a packet that has an
2226 * error of some type. Type of error is indicated in
2229 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2230 /* This field indicates how the packet was placed in the buffer. */
2231 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2232 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2235 * Packet was placed using normal algorithm.
2237 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2240 * Packet was placed using jumbo algorithm.
2242 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2244 * Header/Data Separation:
2245 * Packet was placed using Header/Data separation algorithm.
2246 * The separation location is indicated by the itype field.
2248 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2249 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2250 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2251 /* This bit is '1' if the RSS field in this completion is valid. */
2252 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2254 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2256 * This value indicates what the inner packet determined for the
2259 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2260 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2263 * Indicates that the packet type was not known.
2265 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2266 (UINT32_C(0x0) << 12)
2269 * Indicates that the packet was an IP packet, but further
2270 * classification was not possible.
2272 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2273 (UINT32_C(0x1) << 12)
2276 * Indicates that the packet was IP and TCP.
2277 * This indicates that the payload_offset field is valid.
2279 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2280 (UINT32_C(0x2) << 12)
2283 * Indicates that the packet was IP and UDP.
2284 * This indicates that the payload_offset field is valid.
2286 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2287 (UINT32_C(0x3) << 12)
2290 * Indicates that the packet was recognized as a FCoE.
2291 * This also indicates that the payload_offset field is valid.
2293 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2294 (UINT32_C(0x4) << 12)
2297 * Indicates that the packet was recognized as a RoCE.
2298 * This also indicates that the payload_offset field is valid.
2300 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2301 (UINT32_C(0x5) << 12)
2304 * Indicates that the packet was recognized as ICMP.
2305 * This indicates that the payload_offset field is valid.
2307 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2308 (UINT32_C(0x7) << 12)
2310 * PtP packet wo/timestamp:
2311 * Indicates that the packet was recognized as a PtP
2314 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2315 (UINT32_C(0x8) << 12)
2317 * PtP packet w/timestamp:
2318 * Indicates that the packet was recognized as a PtP
2319 * packet and that a timestamp was taken for the packet.
2321 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2322 (UINT32_C(0x9) << 12)
2323 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2324 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2326 * This is the length of the data for the packet stored in the
2327 * buffer(s) identified by the opaque value. This includes
2328 * the packet BD and any associated buffer BDs. This does not include
2329 * the the length of any data places in aggregation BDs.
2333 * This is a copy of the opaque field from the RX BD this completion
2337 uint8_t agg_bufs_v1;
2339 * This value is written by the NIC such that it will be different
2340 * for each pass through the completion queue. The even passes
2341 * will write 1. The odd passes will write 0.
2343 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2345 * This value is the number of aggregation buffers that follow this
2346 * entry in the completion ring that are a part of this packet.
2347 * If the value is zero, then the packet is completely contained
2348 * in the buffer space provided for the packet in the RX ring.
2350 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2351 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2352 /* unused1 is 2 b */
2353 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2354 #define RX_PKT_CMPL_UNUSED1_SFT 6
2356 * This is the RSS hash type for the packet. The value is packed
2357 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2359 * The value of tuple_extrac_op provides the information about
2360 * what fields the hash was computed on.
2361 * * 0: The RSS hash was computed over source IP address,
2362 * destination IP address, source port, and destination port of inner
2363 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2364 * the packet headers are considered inner packet headers for the RSS
2365 * hash computation purpose.
2366 * * 1: The RSS hash was computed over source IP address and destination
2367 * IP address of inner IP header. Note: For non-tunneled packets,
2368 * the packet headers are considered inner packet headers for the RSS
2369 * hash computation purpose.
2370 * * 2: The RSS hash was computed over source IP address,
2371 * destination IP address, source port, and destination port of
2372 * IP and TCP or UDP headers of outer tunnel headers.
2373 * Note: For non-tunneled packets, this value is not applicable.
2374 * * 3: The RSS hash was computed over source IP address and
2375 * destination IP address of IP header of outer tunnel headers.
2376 * Note: For non-tunneled packets, this value is not applicable.
2378 * Note that 4-tuples values listed above are applicable
2379 * for layer 4 protocols supported and enabled for RSS in the hardware,
2380 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2381 * enabled for TCP traffic only, then the values of tuple_extract_op
2382 * corresponding to 4-tuples are only valid for TCP traffic.
2384 uint8_t rss_hash_type;
2386 * This value indicates the offset in bytes from the beginning of the packet
2387 * where the inner payload starts. This value is valid for TCP, UDP,
2388 * FCoE, and RoCE packets.
2390 * A value of zero indicates that header is 256B into the packet.
2392 uint8_t payload_offset;
2393 /* unused2 is 8 b */
2396 * This value is the RSS hash value calculated for the packet
2397 * based on the mode bits and key value in the VNIC.
2400 } __attribute__((packed));
2402 /* Last 16 bytes of rx_pkt_cmpl. */
2403 /* rx_pkt_cmpl_hi (size:128b/16B) */
2404 struct rx_pkt_cmpl_hi {
2407 * This indicates that the ip checksum was calculated for the
2408 * inner packet and that the ip_cs_error field indicates if there
2411 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2413 * This indicates that the TCP, UDP or ICMP checksum was
2414 * calculated for the inner packet and that the l4_cs_error field
2415 * indicates if there was an error.
2417 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2419 * This indicates that the ip checksum was calculated for the
2420 * tunnel header and that the t_ip_cs_error field indicates if there
2423 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2425 * This indicates that the UDP checksum was
2426 * calculated for the tunnel packet and that the t_l4_cs_error field
2427 * indicates if there was an error.
2429 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2430 /* This value indicates what format the metadata field is. */
2431 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2432 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2433 /* No metadata informtaion. Value is zero. */
2434 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
2436 * The metadata field contains the VLAN tag and TPID value.
2437 * - metadata[11:0] contains the vlan VID value.
2438 * - metadata[12] contains the vlan DE value.
2439 * - metadata[15:13] contains the vlan PRI value.
2440 * - metadata[31:16] contains the vlan TPID value.
2442 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
2443 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2444 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
2446 * This field indicates the IP type for the inner-most IP header.
2447 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2448 * This value is only valid if itype indicates a packet
2449 * with an IP header.
2451 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2453 * This is data from the CFA block as indicated by the meta_format
2457 /* When meta_format=1, this value is the VLAN VID. */
2458 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2459 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2460 /* When meta_format=1, this value is the VLAN DE. */
2461 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2462 /* When meta_format=1, this value is the VLAN PRI. */
2463 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2464 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2465 /* When meta_format=1, this value is the VLAN TPID. */
2466 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2467 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2470 * This value is written by the NIC such that it will be different
2471 * for each pass through the completion queue. The even passes
2472 * will write 1. The odd passes will write 0.
2474 #define RX_PKT_CMPL_V2 \
2476 #define RX_PKT_CMPL_ERRORS_MASK \
2478 #define RX_PKT_CMPL_ERRORS_SFT 1
2480 * This error indicates that there was some sort of problem with
2481 * the BDs for the packet that was found after part of the
2482 * packet was already placed. The packet should be treated as
2485 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2487 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2488 /* No buffer error */
2489 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2490 (UINT32_C(0x0) << 1)
2493 * Packet did not fit into packet buffer provided.
2494 * For regular placement, this means the packet did not fit
2495 * in the buffer provided. For HDS and jumbo placement, this
2496 * means that the packet could not be placed into 7 physical
2499 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2500 (UINT32_C(0x1) << 1)
2503 * All BDs needed for the packet were not on-chip when
2504 * the packet arrived.
2506 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2507 (UINT32_C(0x2) << 1)
2510 * BDs were not formatted correctly.
2512 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2513 (UINT32_C(0x3) << 1)
2514 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2515 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
2517 * This indicates that there was an error in the IP header
2520 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2523 * This indicates that there was an error in the TCP, UDP
2526 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2529 * This indicates that there was an error in the tunnel
2530 * IP header checksum.
2532 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2535 * This indicates that there was an error in the tunnel
2538 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2541 * This indicates that there was a CRC error on either an FCoE
2542 * or RoCE packet. The itype indicates the packet type.
2544 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2547 * This indicates that there was an error in the tunnel
2548 * portion of the packet when this
2549 * field is non-zero.
2551 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2553 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2555 * No additional error occurred on the tunnel portion
2556 * of the packet of the packet does not have a tunnel.
2558 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2559 (UINT32_C(0x0) << 9)
2561 * Indicates that IP header version does not match
2562 * expectation from L2 Ethertype for IPv4 and IPv6
2563 * in the tunnel header.
2565 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2566 (UINT32_C(0x1) << 9)
2568 * Indicates that header length is out of range in the
2569 * tunnel header. Valid for
2572 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2573 (UINT32_C(0x2) << 9)
2575 * Indicates that the physical packet is shorter than that
2576 * claimed by the PPPoE header length for a tunnel PPPoE
2579 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2580 (UINT32_C(0x3) << 9)
2582 * Indicates that physical packet is shorter than that claimed
2583 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2584 * tunnel packet packets.
2586 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2587 (UINT32_C(0x4) << 9)
2589 * Indicates that the physical packet is shorter than that
2590 * claimed by the tunnel UDP header length for a tunnel
2591 * UDP packet that is not fragmented.
2593 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2594 (UINT32_C(0x5) << 9)
2596 * indicates that the IPv4 TTL or IPv6 hop limit check
2597 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2598 * for IPv4, and IPv6.
2600 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2601 (UINT32_C(0x6) << 9)
2602 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2603 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2605 * This indicates that there was an error in the inner
2606 * portion of the packet when this
2607 * field is non-zero.
2609 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2611 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2613 * No additional error occurred on the tunnel portion
2614 * of the packet of the packet does not have a tunnel.
2616 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2617 (UINT32_C(0x0) << 12)
2619 * Indicates that IP header version does not match
2620 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2621 * option other than VFT was parsed on
2624 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2625 (UINT32_C(0x1) << 12)
2627 * indicates that header length is out of range. Valid for
2630 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2631 (UINT32_C(0x2) << 12)
2633 * indicates that the IPv4 TTL or IPv6 hop limit check
2634 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2636 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2637 (UINT32_C(0x3) << 12)
2639 * Indicates that physical packet is shorter than that
2640 * claimed by the l3 header length. Valid for IPv4,
2641 * IPv6 packet or RoCE packets.
2643 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2644 (UINT32_C(0x4) << 12)
2646 * Indicates that the physical packet is shorter than that
2647 * claimed by the UDP header length for a UDP packet that is
2650 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2651 (UINT32_C(0x5) << 12)
2653 * Indicates that TCP header length > IP payload. Valid for
2656 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2657 (UINT32_C(0x6) << 12)
2658 /* Indicates that TCP header length < 5. Valid for TCP. */
2659 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2660 (UINT32_C(0x7) << 12)
2662 * Indicates that TCP option headers result in a TCP header
2663 * size that does not match data offset in TCP header. Valid
2666 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2667 (UINT32_C(0x8) << 12)
2668 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2669 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2671 * This field identifies the CFA action rule that was used for this
2677 * This value holds the reordering sequence number for the packet.
2678 * If the reordering sequence is not valid, then this value is zero.
2679 * The reordering domain for the packet is in the bottom 8 to 10b of
2680 * the rss_hash value. The bottom 20b of this value contain the
2681 * ordering domain value for the packet.
2683 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2684 #define RX_PKT_CMPL_REORDER_SFT 0
2685 } __attribute__((packed));
2687 /* rx_tpa_start_cmpl (size:128b/16B) */
2688 struct rx_tpa_start_cmpl {
2689 uint16_t flags_type;
2691 * This field indicates the exact type of the completion.
2692 * By convention, the LSB identifies the length of the
2693 * record in 16B units. Even values indicate 16B
2694 * records. Odd values indicate 32B
2697 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2698 #define RX_TPA_START_CMPL_TYPE_SFT 0
2700 * RX L2 TPA Start Completion:
2701 * Completion at the beginning of a TPA operation.
2704 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2705 #define RX_TPA_START_CMPL_TYPE_LAST \
2706 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2707 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2708 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2709 /* This bit will always be '0' for TPA start completions. */
2710 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2711 /* This field indicates how the packet was placed in the buffer. */
2712 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2713 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2716 * TPA Packet was placed using jumbo algorithm. This means
2717 * that the first buffer will be filled with data before
2718 * moving to aggregation buffers. Each aggregation buffer
2719 * will be filled before moving to the next aggregation
2722 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2723 (UINT32_C(0x1) << 7)
2725 * Header/Data Separation:
2726 * Packet was placed using Header/Data separation algorithm.
2727 * The separation location is indicated by the itype field.
2729 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2730 (UINT32_C(0x2) << 7)
2733 * Packet will be placed using GRO/Jumbo where the first
2734 * packet is filled with data. Subsequent packets will be
2735 * placed such that any one packet does not span two
2736 * aggregation buffers unless it starts at the beginning of
2737 * an aggregation buffer.
2739 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2740 (UINT32_C(0x5) << 7)
2742 * GRO/Header-Data Separation:
2743 * Packet will be placed using GRO/HDS where the header
2744 * is in the first packet.
2745 * Payload of each packet will be
2746 * placed such that any one packet does not span two
2747 * aggregation buffers unless it starts at the beginning of
2748 * an aggregation buffer.
2750 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2751 (UINT32_C(0x6) << 7)
2752 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2753 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2754 /* This bit is '1' if the RSS field in this completion is valid. */
2755 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2757 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2759 * This value indicates what the inner packet determined for the
2762 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2763 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2766 * Indicates that the packet was IP and TCP.
2768 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2769 (UINT32_C(0x2) << 12)
2770 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2771 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2773 * This value indicates the amount of packet data written to the
2774 * buffer the opaque field in this completion corresponds to.
2778 * This is a copy of the opaque field from the RX BD this completion
2783 * This value is written by the NIC such that it will be different
2784 * for each pass through the completion queue. The even passes
2785 * will write 1. The odd passes will write 0.
2789 * This value is written by the NIC such that it will be different
2790 * for each pass through the completion queue. The even passes
2791 * will write 1. The odd passes will write 0.
2793 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2794 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2796 * This is the RSS hash type for the packet. The value is packed
2797 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2799 * The value of tuple_extrac_op provides the information about
2800 * what fields the hash was computed on.
2801 * * 0: The RSS hash was computed over source IP address,
2802 * destination IP address, source port, and destination port of inner
2803 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2804 * the packet headers are considered inner packet headers for the RSS
2805 * hash computation purpose.
2806 * * 1: The RSS hash was computed over source IP address and destination
2807 * IP address of inner IP header. Note: For non-tunneled packets,
2808 * the packet headers are considered inner packet headers for the RSS
2809 * hash computation purpose.
2810 * * 2: The RSS hash was computed over source IP address,
2811 * destination IP address, source port, and destination port of
2812 * IP and TCP or UDP headers of outer tunnel headers.
2813 * Note: For non-tunneled packets, this value is not applicable.
2814 * * 3: The RSS hash was computed over source IP address and
2815 * destination IP address of IP header of outer tunnel headers.
2816 * Note: For non-tunneled packets, this value is not applicable.
2818 * Note that 4-tuples values listed above are applicable
2819 * for layer 4 protocols supported and enabled for RSS in the hardware,
2820 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2821 * enabled for TCP traffic only, then the values of tuple_extract_op
2822 * corresponding to 4-tuples are only valid for TCP traffic.
2824 uint8_t rss_hash_type;
2826 * This is the aggregation ID that the completion is associated
2827 * with. Use this number to correlate the TPA start completion
2828 * with the TPA end completion.
2831 /* unused2 is 9 b */
2832 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2833 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2835 * This is the aggregation ID that the completion is associated
2836 * with. Use this number to correlate the TPA start completion
2837 * with the TPA end completion.
2839 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
2840 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
2842 * This value is the RSS hash value calculated for the packet
2843 * based on the mode bits and key value in the VNIC.
2846 } __attribute__((packed));
2848 /* Last 16 bytes of rx_tpq_start_cmpl. */
2849 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
2850 struct rx_tpa_start_cmpl_hi {
2853 * This indicates that the ip checksum was calculated for the
2854 * inner packet and that the sum passed for all segments
2855 * included in the aggregation.
2857 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2859 * This indicates that the TCP, UDP or ICMP checksum was
2860 * calculated for the inner packet and that the sum passed
2861 * for all segments included in the aggregation.
2863 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2865 * This indicates that the ip checksum was calculated for the
2866 * tunnel header and that the sum passed for all segments
2867 * included in the aggregation.
2869 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2871 * This indicates that the UDP checksum was
2872 * calculated for the tunnel packet and that the sum passed for
2873 * all segments included in the aggregation.
2875 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2876 /* This value indicates what format the metadata field is. */
2877 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2878 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
2879 /* No metadata informtaion. Value is zero. */
2880 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
2881 (UINT32_C(0x0) << 4)
2883 * The metadata field contains the VLAN tag and TPID value.
2884 * - metadata[11:0] contains the vlan VID value.
2885 * - metadata[12] contains the vlan DE value.
2886 * - metadata[15:13] contains the vlan PRI value.
2887 * - metadata[31:16] contains the vlan TPID value.
2889 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
2890 (UINT32_C(0x1) << 4)
2891 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
2892 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
2894 * This field indicates the IP type for the inner-most IP header.
2895 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2897 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2899 * This is data from the CFA block as indicated by the meta_format
2903 /* When meta_format=1, this value is the VLAN VID. */
2904 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2905 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
2906 /* When meta_format=1, this value is the VLAN DE. */
2907 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
2908 /* When meta_format=1, this value is the VLAN PRI. */
2909 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2910 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
2911 /* When meta_format=1, this value is the VLAN TPID. */
2912 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2913 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
2916 * This value is written by the NIC such that it will be different
2917 * for each pass through the completion queue. The even passes
2918 * will write 1. The odd passes will write 0.
2920 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
2922 * This field identifies the CFA action rule that was used for this
2927 * This is the size in bytes of the inner most L4 header.
2928 * This can be subtracted from the payload_offset to determine
2929 * the start of the inner most L4 header.
2931 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
2933 * This is the offset from the beginning of the packet in bytes for
2934 * the outer L3 header. If there is no outer L3 header, then this
2937 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
2938 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
2940 * This is the offset from the beginning of the packet in bytes for
2941 * the inner most L2 header.
2943 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
2944 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
2946 * This is the offset from the beginning of the packet in bytes for
2947 * the inner most L3 header.
2949 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
2950 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
2952 * This is the size in bytes of the inner most L4 header.
2953 * This can be subtracted from the payload_offset to determine
2954 * the start of the inner most L4 header.
2956 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
2957 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
2958 } __attribute__((packed));
2960 /* rx_tpa_end_cmpl (size:128b/16B) */
2961 struct rx_tpa_end_cmpl {
2962 uint16_t flags_type;
2964 * This field indicates the exact type of the completion.
2965 * By convention, the LSB identifies the length of the
2966 * record in 16B units. Even values indicate 16B
2967 * records. Odd values indicate 32B
2970 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
2971 #define RX_TPA_END_CMPL_TYPE_SFT 0
2973 * RX L2 TPA End Completion:
2974 * Completion at the end of a TPA operation.
2977 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
2978 #define RX_TPA_END_CMPL_TYPE_LAST \
2979 RX_TPA_END_CMPL_TYPE_RX_TPA_END
2980 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2981 #define RX_TPA_END_CMPL_FLAGS_SFT 6
2983 * When this bit is '1', it indicates a packet that has an
2984 * error of some type. Type of error is indicated in
2987 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
2988 /* This field indicates how the packet was placed in the buffer. */
2989 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2990 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
2993 * TPA Packet was placed using jumbo algorithm. This means
2994 * that the first buffer will be filled with data before
2995 * moving to aggregation buffers. Each aggregation buffer
2996 * will be filled before moving to the next aggregation
2999 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
3000 (UINT32_C(0x1) << 7)
3002 * Header/Data Separation:
3003 * Packet was placed using Header/Data separation algorithm.
3004 * The separation location is indicated by the itype field.
3006 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
3007 (UINT32_C(0x2) << 7)
3010 * Packet will be placed using GRO/Jumbo where the first
3011 * packet is filled with data. Subsequent packets will be
3012 * placed such that any one packet does not span two
3013 * aggregation buffers unless it starts at the beginning of
3014 * an aggregation buffer.
3016 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
3017 (UINT32_C(0x5) << 7)
3019 * GRO/Header-Data Separation:
3020 * Packet will be placed using GRO/HDS where the header
3021 * is in the first packet.
3022 * Payload of each packet will be
3023 * placed such that any one packet does not span two
3024 * aggregation buffers unless it starts at the beginning of
3025 * an aggregation buffer.
3027 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
3028 (UINT32_C(0x6) << 7)
3029 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
3030 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
3032 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
3033 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
3035 * This value indicates what the inner packet determined for the
3038 * Indicates that the packet was IP and TCP. This indicates
3039 * that the ip_cs field is valid and that the tcp_udp_cs
3040 * field is valid and contains the TCP checksum.
3041 * This also indicates that the payload_offset field is valid.
3043 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3044 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
3046 * This value is zero for TPA End completions.
3047 * There is no data in the buffer that corresponds to the opaque
3048 * value in this completion.
3052 * This is a copy of the opaque field from the RX BD this completion
3057 * This value is written by the NIC such that it will be different
3058 * for each pass through the completion queue. The even passes
3059 * will write 1. The odd passes will write 0.
3061 uint8_t agg_bufs_v1;
3063 * This value is written by the NIC such that it will be different
3064 * for each pass through the completion queue. The even passes
3065 * will write 1. The odd passes will write 0.
3067 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
3069 * This value is the number of aggregation buffers that follow this
3070 * entry in the completion ring that are a part of this aggregation
3072 * If the value is zero, then the packet is completely contained
3073 * in the buffer space provided in the aggregation start completion.
3075 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
3076 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
3077 /* This value is the number of segments in the TPA operation. */
3080 * This value indicates the offset in bytes from the beginning of the packet
3081 * where the inner payload starts. This value is valid for TCP, UDP,
3082 * FCoE, and RoCE packets.
3084 * A value of zero indicates an offset of 256 bytes.
3086 uint8_t payload_offset;
3088 /* unused2 is 1 b */
3089 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
3091 * This is the aggregation ID that the completion is associated
3092 * with. Use this number to correlate the TPA start completion
3093 * with the TPA end completion.
3095 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
3096 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
3098 * For non-GRO packets, this value is the
3099 * timestamp delta between earliest and latest timestamp values for
3100 * TPA packet. If packets were not time stamped, then delta will be
3103 * For GRO packets, this field is zero except for the following
3106 * Timestamp present indication. When '0', no Timestamp
3107 * option is in the packet. When '1', then a Timestamp
3108 * option is present in the packet.
3111 } __attribute__((packed));
3113 /* Last 16 bytes of rx_tpa_end_cmpl. */
3114 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
3115 struct rx_tpa_end_cmpl_hi {
3117 * This value is the number of duplicate ACKs that have been
3118 * received as part of the TPA operation.
3120 uint32_t tpa_dup_acks;
3122 * This value is the number of duplicate ACKs that have been
3123 * received as part of the TPA operation.
3125 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
3126 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
3128 * This value is the valid when TPA completion is active. It
3129 * indicates the length of the longest segment of the TPA operation
3130 * for LRO mode and the length of the first segment in GRO mode.
3132 * This value may be used by GRO software to re-construct the original
3133 * packet stream from the TPA packet. This is the length of all
3134 * but the last segment for GRO. In LRO mode this value may be used
3135 * to indicate MSS size to the stack.
3137 uint16_t tpa_seg_len;
3138 /* unused4 is 16 b */
3142 * This value is written by the NIC such that it will be different
3143 * for each pass through the completion queue. The even passes
3144 * will write 1. The odd passes will write 0.
3146 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
3147 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3148 #define RX_TPA_END_CMPL_ERRORS_SFT 1
3150 * This error indicates that there was some sort of problem with
3151 * the BDs for the packet that was found after part of the
3152 * packet was already placed. The packet should be treated as
3155 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3156 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3158 * This error occurs when there is a fatal HW problem in
3159 * the chip only. It indicates that there were not
3160 * BDs on chip but that there was adequate reservation.
3161 * provided by the TPA block.
3163 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3164 (UINT32_C(0x2) << 1)
3166 * This error occurs when TPA block was not configured to
3167 * reserve adequate BDs for TPA operations on this RX
3168 * ring. All data for the TPA operation was not placed.
3170 * This error can also be generated when the number of
3171 * segments is not programmed correctly in TPA and the
3172 * 33 total aggregation buffers allowed for the TPA
3173 * operation has been exceeded.
3175 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
3176 (UINT32_C(0x4) << 1)
3177 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
3178 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
3179 /* unused5 is 16 b */
3182 * This is the opaque value that was completed for the TPA start
3183 * completion that corresponds to this TPA end completion.
3185 uint32_t start_opaque;
3186 } __attribute__((packed));
3188 /* rx_abuf_cmpl (size:128b/16B) */
3189 struct rx_abuf_cmpl {
3192 * This field indicates the exact type of the completion.
3193 * By convention, the LSB identifies the length of the
3194 * record in 16B units. Even values indicate 16B
3195 * records. Odd values indicate 32B
3198 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
3199 #define RX_ABUF_CMPL_TYPE_SFT 0
3201 * RX Aggregation Buffer completion :
3202 * Completion of an L2 aggregation buffer in support of
3203 * TPA, HDS, or Jumbo packet completion. Length = 16B
3205 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
3206 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
3208 * This is the length of the data for the packet stored in this
3209 * aggregation buffer identified by the opaque value. This does not
3210 * include the length of any
3211 * data placed in other aggregation BDs or in the packet or buffer
3212 * BDs. This length does not include any space added due to
3213 * hdr_offset register during HDS placement mode.
3217 * This is a copy of the opaque field from the RX BD this aggregation
3218 * buffer corresponds to.
3223 * This value is written by the NIC such that it will be different
3224 * for each pass through the completion queue. The even passes
3225 * will write 1. The odd passes will write 0.
3227 #define RX_ABUF_CMPL_V UINT32_C(0x1)
3228 /* unused3 is 32 b */
3230 } __attribute__((packed));
3232 /* eject_cmpl (size:128b/16B) */
3236 * This field indicates the exact type of the completion.
3237 * By convention, the LSB identifies the length of the
3238 * record in 16B units. Even values indicate 16B
3239 * records. Odd values indicate 32B
3242 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
3243 #define EJECT_CMPL_TYPE_SFT 0
3245 * Statistics Ejection Completion:
3246 * Completion of statistics data ejection buffer.
3249 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
3250 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
3252 * This is the length of the statistics data stored in this
3257 * This is a copy of the opaque field from the RX BD this ejection
3258 * buffer corresponds to.
3263 * This value is written by the NIC such that it will be different
3264 * for each pass through the completion queue. The even passes
3265 * will write 1. The odd passes will write 0.
3267 #define EJECT_CMPL_V UINT32_C(0x1)
3268 /* unused3 is 32 b */
3270 } __attribute__((packed));
3272 /* hwrm_cmpl (size:128b/16B) */
3276 * This field indicates the exact type of the completion.
3277 * By convention, the LSB identifies the length of the
3278 * record in 16B units. Even values indicate 16B
3279 * records. Odd values indicate 32B
3282 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3283 #define HWRM_CMPL_TYPE_SFT 0
3285 * HWRM Command Completion:
3286 * Completion of an HWRM command.
3288 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3289 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3290 /* This is the sequence_id of the HWRM command that has completed. */
3291 uint16_t sequence_id;
3292 /* unused2 is 32 b */
3296 * This value is written by the NIC such that it will be different
3297 * for each pass through the completion queue. The even passes
3298 * will write 1. The odd passes will write 0.
3300 #define HWRM_CMPL_V UINT32_C(0x1)
3301 /* unused4 is 32 b */
3303 } __attribute__((packed));
3305 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3306 struct hwrm_fwd_req_cmpl {
3308 * This field indicates the exact type of the completion.
3309 * By convention, the LSB identifies the length of the
3310 * record in 16B units. Even values indicate 16B
3311 * records. Odd values indicate 32B
3314 uint16_t req_len_type;
3316 * This field indicates the exact type of the completion.
3317 * By convention, the LSB identifies the length of the
3318 * record in 16B units. Even values indicate 16B
3319 * records. Odd values indicate 32B
3322 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3323 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3324 /* Forwarded HWRM Request */
3325 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3326 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3327 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3328 /* Length of forwarded request in bytes. */
3329 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3330 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3332 * Source ID of this request.
3333 * Typically used in forwarding requests and responses.
3334 * 0x0 - 0xFFF8 - Used for function ids
3335 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3339 /* unused1 is 32 b */
3341 /* Address of forwarded request. */
3342 uint32_t req_buf_addr_v[2];
3344 * This value is written by the NIC such that it will be different
3345 * for each pass through the completion queue. The even passes
3346 * will write 1. The odd passes will write 0.
3348 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3349 /* Address of forwarded request. */
3350 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3351 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3352 } __attribute__((packed));
3354 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3355 struct hwrm_fwd_resp_cmpl {
3358 * This field indicates the exact type of the completion.
3359 * By convention, the LSB identifies the length of the
3360 * record in 16B units. Even values indicate 16B
3361 * records. Odd values indicate 32B
3364 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3365 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3366 /* Forwarded HWRM Response */
3367 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3368 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3369 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3371 * Source ID of this response.
3372 * Typically used in forwarding requests and responses.
3373 * 0x0 - 0xFFF8 - Used for function ids
3374 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3378 /* Length of forwarded response in bytes. */
3380 /* unused2 is 16 b */
3382 /* Address of forwarded request. */
3383 uint32_t resp_buf_addr_v[2];
3385 * This value is written by the NIC such that it will be different
3386 * for each pass through the completion queue. The even passes
3387 * will write 1. The odd passes will write 0.
3389 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3390 /* Address of forwarded request. */
3391 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3392 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3393 } __attribute__((packed));
3395 /* hwrm_async_event_cmpl (size:128b/16B) */
3396 struct hwrm_async_event_cmpl {
3399 * This field indicates the exact type of the completion.
3400 * By convention, the LSB identifies the length of the
3401 * record in 16B units. Even values indicate 16B
3402 * records. Odd values indicate 32B
3405 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3406 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3407 /* HWRM Asynchronous Event Information */
3408 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3409 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3410 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3411 /* Identifiers of events. */
3413 /* Link status changed */
3414 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3416 /* Link MTU changed */
3417 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3419 /* Link speed changed */
3420 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3422 /* DCB Configuration changed */
3423 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3425 /* Port connection not allowed */
3426 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3428 /* Link speed configuration was not allowed */
3429 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3431 /* Link speed configuration change */
3432 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3434 /* Port PHY configuration change */
3435 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3437 /* Reset notification to clients */
3438 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
3440 /* Function driver unloaded */
3441 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3443 /* Function driver loaded */
3444 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3446 /* Function FLR related processing has completed */
3447 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3449 /* PF driver unloaded */
3450 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3452 /* PF driver loaded */
3453 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3455 /* VF Function Level Reset (FLR) */
3456 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3458 /* VF MAC Address Change */
3459 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3461 /* PF-VF communication channel status change. */
3462 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3464 /* VF Configuration Change */
3465 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3467 /* LLFC/PFC Configuration Change */
3468 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3470 /* Default VNIC Configuration Change */
3471 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
3474 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3476 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3477 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3478 /* Event specific data */
3479 uint32_t event_data2;
3482 * This value is written by the NIC such that it will be different
3483 * for each pass through the completion queue. The even passes
3484 * will write 1. The odd passes will write 0.
3486 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3488 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3489 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3490 /* 8-lsb timestamp from POR (100-msec resolution) */
3491 uint8_t timestamp_lo;
3492 /* 16-lsb timestamp from POR (100-msec resolution) */
3493 uint16_t timestamp_hi;
3494 /* Event specific data */
3495 uint32_t event_data1;
3496 } __attribute__((packed));
3498 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3499 struct hwrm_async_event_cmpl_link_status_change {
3502 * This field indicates the exact type of the completion.
3503 * By convention, the LSB identifies the length of the
3504 * record in 16B units. Even values indicate 16B
3505 * records. Odd values indicate 32B
3508 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3510 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3511 /* HWRM Asynchronous Event Information */
3512 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3514 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3515 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3516 /* Identifiers of events. */
3518 /* Link status changed */
3519 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3521 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3522 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3523 /* Event specific data */
3524 uint32_t event_data2;
3527 * This value is written by the NIC such that it will be different
3528 * for each pass through the completion queue. The even passes
3529 * will write 1. The odd passes will write 0.
3531 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3534 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3536 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3537 /* 8-lsb timestamp from POR (100-msec resolution) */
3538 uint8_t timestamp_lo;
3539 /* 16-lsb timestamp from POR (100-msec resolution) */
3540 uint16_t timestamp_hi;
3541 /* Event specific data */
3542 uint32_t event_data1;
3543 /* Indicates link status change */
3544 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3547 * If this bit set to 0, then it indicates that the link
3548 * was up and it went down.
3550 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3553 * If this bit is set to 1, then it indicates that the link
3554 * was down and it went up.
3556 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3558 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3559 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3560 /* Indicates the physical port this link status change occur */
3561 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3563 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3566 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3568 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3570 /* Indicates the physical function this event occured on. */
3571 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
3573 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
3575 } __attribute__((packed));
3577 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
3578 struct hwrm_async_event_cmpl_link_mtu_change {
3581 * This field indicates the exact type of the completion.
3582 * By convention, the LSB identifies the length of the
3583 * record in 16B units. Even values indicate 16B
3584 * records. Odd values indicate 32B
3587 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
3589 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
3590 /* HWRM Asynchronous Event Information */
3591 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3593 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
3594 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
3595 /* Identifiers of events. */
3597 /* Link MTU changed */
3598 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
3600 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
3601 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
3602 /* Event specific data */
3603 uint32_t event_data2;
3606 * This value is written by the NIC such that it will be different
3607 * for each pass through the completion queue. The even passes
3608 * will write 1. The odd passes will write 0.
3610 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
3612 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
3614 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
3615 /* 8-lsb timestamp from POR (100-msec resolution) */
3616 uint8_t timestamp_lo;
3617 /* 16-lsb timestamp from POR (100-msec resolution) */
3618 uint16_t timestamp_hi;
3619 /* Event specific data */
3620 uint32_t event_data1;
3621 /* The new MTU of the link in bytes. */
3622 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
3624 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
3625 } __attribute__((packed));
3627 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
3628 struct hwrm_async_event_cmpl_link_speed_change {
3631 * This field indicates the exact type of the completion.
3632 * By convention, the LSB identifies the length of the
3633 * record in 16B units. Even values indicate 16B
3634 * records. Odd values indicate 32B
3637 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
3639 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
3640 /* HWRM Asynchronous Event Information */
3641 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3643 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
3644 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
3645 /* Identifiers of events. */
3647 /* Link speed changed */
3648 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
3650 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
3651 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
3652 /* Event specific data */
3653 uint32_t event_data2;
3656 * This value is written by the NIC such that it will be different
3657 * for each pass through the completion queue. The even passes
3658 * will write 1. The odd passes will write 0.
3660 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
3663 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
3665 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
3666 /* 8-lsb timestamp from POR (100-msec resolution) */
3667 uint8_t timestamp_lo;
3668 /* 16-lsb timestamp from POR (100-msec resolution) */
3669 uint16_t timestamp_hi;
3670 /* Event specific data */
3671 uint32_t event_data1;
3673 * When this bit is '1', the link was forced to the
3674 * force_link_speed value.
3676 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
3678 /* The new link speed in 100 Mbps units. */
3679 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
3681 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
3683 /* 100Mb link speed */
3684 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
3685 (UINT32_C(0x1) << 1)
3686 /* 1Gb link speed */
3687 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
3688 (UINT32_C(0xa) << 1)
3689 /* 2Gb link speed */
3690 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
3691 (UINT32_C(0x14) << 1)
3692 /* 25Gb link speed */
3693 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
3694 (UINT32_C(0x19) << 1)
3695 /* 10Gb link speed */
3696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
3697 (UINT32_C(0x64) << 1)
3698 /* 20Mb link speed */
3699 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
3700 (UINT32_C(0xc8) << 1)
3701 /* 25Gb link speed */
3702 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
3703 (UINT32_C(0xfa) << 1)
3704 /* 40Gb link speed */
3705 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
3706 (UINT32_C(0x190) << 1)
3707 /* 50Gb link speed */
3708 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
3709 (UINT32_C(0x1f4) << 1)
3710 /* 100Gb link speed */
3711 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
3712 (UINT32_C(0x3e8) << 1)
3713 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
3714 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
3716 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3717 UINT32_C(0xffff0000)
3718 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3720 } __attribute__((packed));
3722 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
3723 struct hwrm_async_event_cmpl_dcb_config_change {
3726 * This field indicates the exact type of the completion.
3727 * By convention, the LSB identifies the length of the
3728 * record in 16B units. Even values indicate 16B
3729 * records. Odd values indicate 32B
3732 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
3734 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
3735 /* HWRM Asynchronous Event Information */
3736 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3738 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
3739 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3740 /* Identifiers of events. */
3742 /* DCB Configuration changed */
3743 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
3745 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
3746 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
3747 /* Event specific data */
3748 uint32_t event_data2;
3749 /* ETS configuration change */
3750 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
3752 /* PFC configuration change */
3753 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
3755 /* APP configuration change */
3756 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
3760 * This value is written by the NIC such that it will be different
3761 * for each pass through the completion queue. The even passes
3762 * will write 1. The odd passes will write 0.
3764 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
3767 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
3769 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
3770 /* 8-lsb timestamp from POR (100-msec resolution) */
3771 uint8_t timestamp_lo;
3772 /* 16-lsb timestamp from POR (100-msec resolution) */
3773 uint16_t timestamp_hi;
3774 /* Event specific data */
3775 uint32_t event_data1;
3777 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3779 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3781 /* Priority recommended for RoCE traffic */
3782 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
3784 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
3787 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
3788 (UINT32_C(0xff) << 16)
3789 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
3790 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
3791 /* Priority recommended for L2 traffic */
3792 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
3793 UINT32_C(0xff000000)
3794 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
3797 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
3798 (UINT32_C(0xff) << 24)
3799 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
3800 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
3801 } __attribute__((packed));
3803 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
3804 struct hwrm_async_event_cmpl_port_conn_not_allowed {
3807 * This field indicates the exact type of the completion.
3808 * By convention, the LSB identifies the length of the
3809 * record in 16B units. Even values indicate 16B
3810 * records. Odd values indicate 32B
3813 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
3815 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
3817 /* HWRM Asynchronous Event Information */
3818 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3820 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
3821 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3822 /* Identifiers of events. */
3824 /* Port connection not allowed */
3825 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3827 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
3828 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
3829 /* Event specific data */
3830 uint32_t event_data2;
3833 * This value is written by the NIC such that it will be different
3834 * for each pass through the completion queue. The even passes
3835 * will write 1. The odd passes will write 0.
3837 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
3840 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
3842 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
3843 /* 8-lsb timestamp from POR (100-msec resolution) */
3844 uint8_t timestamp_lo;
3845 /* 16-lsb timestamp from POR (100-msec resolution) */
3846 uint16_t timestamp_hi;
3847 /* Event specific data */
3848 uint32_t event_data1;
3850 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3852 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3855 * This value indicates the current port level enforcement policy
3856 * for the optics module when there is an optical module mismatch
3857 * and port is not connected.
3859 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
3861 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
3863 /* No enforcement */
3864 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
3865 (UINT32_C(0x0) << 16)
3866 /* Disable Transmit side Laser. */
3867 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
3868 (UINT32_C(0x1) << 16)
3869 /* Raise a warning message. */
3870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
3871 (UINT32_C(0x2) << 16)
3872 /* Power down the module. */
3873 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
3874 (UINT32_C(0x3) << 16)
3875 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
3876 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
3877 } __attribute__((packed));
3879 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
3880 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
3883 * This field indicates the exact type of the completion.
3884 * By convention, the LSB identifies the length of the
3885 * record in 16B units. Even values indicate 16B
3886 * records. Odd values indicate 32B
3889 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
3891 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
3893 /* HWRM Asynchronous Event Information */
3894 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3896 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
3897 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3898 /* Identifiers of events. */
3900 /* Link speed configuration was not allowed */
3901 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3903 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
3904 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
3905 /* Event specific data */
3906 uint32_t event_data2;
3909 * This value is written by the NIC such that it will be different
3910 * for each pass through the completion queue. The even passes
3911 * will write 1. The odd passes will write 0.
3913 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
3916 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
3918 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
3919 /* 8-lsb timestamp from POR (100-msec resolution) */
3920 uint8_t timestamp_lo;
3921 /* 16-lsb timestamp from POR (100-msec resolution) */
3922 uint16_t timestamp_hi;
3923 /* Event specific data */
3924 uint32_t event_data1;
3926 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3928 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3930 } __attribute__((packed));
3932 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
3933 struct hwrm_async_event_cmpl_link_speed_cfg_change {
3936 * This field indicates the exact type of the completion.
3937 * By convention, the LSB identifies the length of the
3938 * record in 16B units. Even values indicate 16B
3939 * records. Odd values indicate 32B
3942 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
3944 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
3946 /* HWRM Asynchronous Event Information */
3947 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3949 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
3950 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3951 /* Identifiers of events. */
3953 /* Link speed configuration change */
3954 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3956 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
3957 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
3958 /* Event specific data */
3959 uint32_t event_data2;
3962 * This value is written by the NIC such that it will be different
3963 * for each pass through the completion queue. The even passes
3964 * will write 1. The odd passes will write 0.
3966 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
3969 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
3971 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
3972 /* 8-lsb timestamp from POR (100-msec resolution) */
3973 uint8_t timestamp_lo;
3974 /* 16-lsb timestamp from POR (100-msec resolution) */
3975 uint16_t timestamp_hi;
3976 /* Event specific data */
3977 uint32_t event_data1;
3979 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3981 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3984 * If set to 1, it indicates that the supported link speeds
3985 * configuration on the port has changed.
3986 * If set to 0, then there is no change in supported link speeds
3989 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
3992 * If set to 1, it indicates that the link speed configuration
3993 * on the port has become illegal or invalid.
3994 * If set to 0, then the link speed configuration on the port is
3997 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
3999 } __attribute__((packed));
4001 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
4002 struct hwrm_async_event_cmpl_port_phy_cfg_change {
4005 * This field indicates the exact type of the completion.
4006 * By convention, the LSB identifies the length of the
4007 * record in 16B units. Even values indicate 16B
4008 * records. Odd values indicate 32B
4011 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
4013 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
4015 /* HWRM Asynchronous Event Information */
4016 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4018 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
4019 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4020 /* Identifiers of events. */
4022 /* Port PHY configuration change */
4023 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
4025 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
4026 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
4027 /* Event specific data */
4028 uint32_t event_data2;
4031 * This value is written by the NIC such that it will be different
4032 * for each pass through the completion queue. The even passes
4033 * will write 1. The odd passes will write 0.
4035 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
4038 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
4040 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
4041 /* 8-lsb timestamp from POR (100-msec resolution) */
4042 uint8_t timestamp_lo;
4043 /* 16-lsb timestamp from POR (100-msec resolution) */
4044 uint16_t timestamp_hi;
4045 /* Event specific data */
4046 uint32_t event_data1;
4048 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4050 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4053 * If set to 1, it indicates that the FEC
4054 * configuration on the port has changed.
4055 * If set to 0, then there is no change in FEC configuration.
4057 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
4060 * If set to 1, it indicates that the EEE configuration
4061 * on the port has changed.
4062 * If set to 0, then there is no change in EEE configuration
4065 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
4068 * If set to 1, it indicates that the pause configuration
4069 * on the PHY has changed.
4070 * If set to 0, then there is no change in the pause
4071 * configuration on the PHY.
4073 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
4075 } __attribute__((packed));
4077 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
4078 struct hwrm_async_event_cmpl_reset_notify {
4081 * This field indicates the exact type of the completion.
4082 * By convention, the LSB identifies the length of the
4083 * record in 16B units. Even values indicate 16B
4084 * records. Odd values indicate 32B
4087 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
4089 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
4090 /* HWRM Asynchronous Event Information */
4091 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
4093 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
4094 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
4095 /* Identifiers of events. */
4097 /* Notify clients of imminent reset. */
4098 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
4100 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
4101 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
4102 /* Event specific data */
4103 uint32_t event_data2;
4106 * This value is written by the NIC such that it will be different
4107 * for each pass through the completion queue. The even passes
4108 * will write 1. The odd passes will write 0.
4110 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
4112 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
4113 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
4114 /* 8-lsb timestamp from POR (100-msec resolution) */
4115 uint8_t timestamp_lo;
4116 /* 16-lsb timestamp from POR (100-msec resolution) */
4117 uint16_t timestamp_hi;
4118 /* Event specific data */
4119 uint32_t event_data1;
4120 /* Indicates driver action requested */
4121 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
4123 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
4126 * If set to 1, it indicates that the l2 client should
4127 * stop sending in band traffic to Nitro.
4128 * if set to 0, there is no change in L2 client behavior.
4130 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
4133 * If set to 1, it indicates that the L2 client should
4134 * bring down the interface.
4135 * If set to 0, then there is no change in L2 client behavior.
4137 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
4139 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
4140 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
4141 /* Indicates reason for reset. */
4142 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
4144 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
4146 /* A management client has requested reset. */
4147 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
4148 (UINT32_C(0x1) << 8)
4149 /* A fatal firmware exception has occurred. */
4150 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
4151 (UINT32_C(0x2) << 8)
4152 /* A non-fatal firmware exception has occurred. */
4153 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
4154 (UINT32_C(0x3) << 8)
4155 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
4156 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
4158 * Minimum time before driver should attempt access - units 100ms ticks.
4161 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
4162 UINT32_C(0xffff0000)
4163 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
4165 } __attribute__((packed));
4167 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
4168 struct hwrm_async_event_cmpl_func_drvr_unload {
4171 * This field indicates the exact type of the completion.
4172 * By convention, the LSB identifies the length of the
4173 * record in 16B units. Even values indicate 16B
4174 * records. Odd values indicate 32B
4177 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
4179 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
4180 /* HWRM Asynchronous Event Information */
4181 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4183 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
4184 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4185 /* Identifiers of events. */
4187 /* Function driver unloaded */
4188 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
4190 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
4191 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
4192 /* Event specific data */
4193 uint32_t event_data2;
4196 * This value is written by the NIC such that it will be different
4197 * for each pass through the completion queue. The even passes
4198 * will write 1. The odd passes will write 0.
4200 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
4202 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
4204 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
4205 /* 8-lsb timestamp from POR (100-msec resolution) */
4206 uint8_t timestamp_lo;
4207 /* 16-lsb timestamp from POR (100-msec resolution) */
4208 uint16_t timestamp_hi;
4209 /* Event specific data */
4210 uint32_t event_data1;
4212 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4214 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
4216 } __attribute__((packed));
4218 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
4219 struct hwrm_async_event_cmpl_func_drvr_load {
4222 * This field indicates the exact type of the completion.
4223 * By convention, the LSB identifies the length of the
4224 * record in 16B units. Even values indicate 16B
4225 * records. Odd values indicate 32B
4228 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
4230 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
4231 /* HWRM Asynchronous Event Information */
4232 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4234 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
4235 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4236 /* Identifiers of events. */
4238 /* Function driver loaded */
4239 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
4241 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
4242 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
4243 /* Event specific data */
4244 uint32_t event_data2;
4247 * This value is written by the NIC such that it will be different
4248 * for each pass through the completion queue. The even passes
4249 * will write 1. The odd passes will write 0.
4251 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
4253 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4254 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
4255 /* 8-lsb timestamp from POR (100-msec resolution) */
4256 uint8_t timestamp_lo;
4257 /* 16-lsb timestamp from POR (100-msec resolution) */
4258 uint16_t timestamp_hi;
4259 /* Event specific data */
4260 uint32_t event_data1;
4262 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4264 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4265 } __attribute__((packed));
4267 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
4268 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
4271 * This field indicates the exact type of the completion.
4272 * By convention, the LSB identifies the length of the
4273 * record in 16B units. Even values indicate 16B
4274 * records. Odd values indicate 32B
4277 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
4279 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
4281 /* HWRM Asynchronous Event Information */
4282 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
4284 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
4285 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
4286 /* Identifiers of events. */
4288 /* Function FLR related processing has completed */
4289 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
4291 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
4292 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
4293 /* Event specific data */
4294 uint32_t event_data2;
4297 * This value is written by the NIC such that it will be different
4298 * for each pass through the completion queue. The even passes
4299 * will write 1. The odd passes will write 0.
4301 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
4304 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
4306 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
4307 /* 8-lsb timestamp from POR (100-msec resolution) */
4308 uint8_t timestamp_lo;
4309 /* 16-lsb timestamp from POR (100-msec resolution) */
4310 uint16_t timestamp_hi;
4311 /* Event specific data */
4312 uint32_t event_data1;
4314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
4316 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
4318 } __attribute__((packed));
4320 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
4321 struct hwrm_async_event_cmpl_pf_drvr_unload {
4324 * This field indicates the exact type of the completion.
4325 * By convention, the LSB identifies the length of the
4326 * record in 16B units. Even values indicate 16B
4327 * records. Odd values indicate 32B
4330 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
4332 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
4333 /* HWRM Asynchronous Event Information */
4334 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
4336 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
4337 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
4338 /* Identifiers of events. */
4340 /* PF driver unloaded */
4341 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
4343 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
4344 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
4345 /* Event specific data */
4346 uint32_t event_data2;
4349 * This value is written by the NIC such that it will be different
4350 * for each pass through the completion queue. The even passes
4351 * will write 1. The odd passes will write 0.
4353 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
4355 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
4356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
4357 /* 8-lsb timestamp from POR (100-msec resolution) */
4358 uint8_t timestamp_lo;
4359 /* 16-lsb timestamp from POR (100-msec resolution) */
4360 uint16_t timestamp_hi;
4361 /* Event specific data */
4362 uint32_t event_data1;
4364 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
4366 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
4367 /* Indicates the physical port this pf belongs to */
4368 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
4370 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
4371 } __attribute__((packed));
4373 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
4374 struct hwrm_async_event_cmpl_pf_drvr_load {
4377 * This field indicates the exact type of the completion.
4378 * By convention, the LSB identifies the length of the
4379 * record in 16B units. Even values indicate 16B
4380 * records. Odd values indicate 32B
4383 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4385 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4386 /* HWRM Asynchronous Event Information */
4387 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4389 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4390 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4391 /* Identifiers of events. */
4393 /* PF driver loaded */
4394 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4396 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4397 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4398 /* Event specific data */
4399 uint32_t event_data2;
4402 * This value is written by the NIC such that it will be different
4403 * for each pass through the completion queue. The even passes
4404 * will write 1. The odd passes will write 0.
4406 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4408 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4409 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4410 /* 8-lsb timestamp from POR (100-msec resolution) */
4411 uint8_t timestamp_lo;
4412 /* 16-lsb timestamp from POR (100-msec resolution) */
4413 uint16_t timestamp_hi;
4414 /* Event specific data */
4415 uint32_t event_data1;
4417 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4419 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4420 /* Indicates the physical port this pf belongs to */
4421 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4423 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4424 } __attribute__((packed));
4426 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4427 struct hwrm_async_event_cmpl_vf_flr {
4430 * This field indicates the exact type of the completion.
4431 * By convention, the LSB identifies the length of the
4432 * record in 16B units. Even values indicate 16B
4433 * records. Odd values indicate 32B
4436 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4438 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4439 /* HWRM Asynchronous Event Information */
4440 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4442 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4443 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4444 /* Identifiers of events. */
4446 /* VF Function Level Reset (FLR) */
4447 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4448 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4449 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4450 /* Event specific data */
4451 uint32_t event_data2;
4454 * This value is written by the NIC such that it will be different
4455 * for each pass through the completion queue. The even passes
4456 * will write 1. The odd passes will write 0.
4458 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4460 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4461 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4462 /* 8-lsb timestamp from POR (100-msec resolution) */
4463 uint8_t timestamp_lo;
4464 /* 16-lsb timestamp from POR (100-msec resolution) */
4465 uint16_t timestamp_hi;
4466 /* Event specific data */
4467 uint32_t event_data1;
4469 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4471 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
4472 /* Indicates the physical function this event occured on. */
4473 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
4475 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
4476 } __attribute__((packed));
4478 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
4479 struct hwrm_async_event_cmpl_vf_mac_addr_change {
4482 * This field indicates the exact type of the completion.
4483 * By convention, the LSB identifies the length of the
4484 * record in 16B units. Even values indicate 16B
4485 * records. Odd values indicate 32B
4488 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
4490 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
4491 /* HWRM Asynchronous Event Information */
4492 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4494 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
4495 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
4496 /* Identifiers of events. */
4498 /* VF MAC Address Change */
4499 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
4501 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
4502 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
4503 /* Event specific data */
4504 uint32_t event_data2;
4507 * This value is written by the NIC such that it will be different
4508 * for each pass through the completion queue. The even passes
4509 * will write 1. The odd passes will write 0.
4511 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
4514 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
4516 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
4517 /* 8-lsb timestamp from POR (100-msec resolution) */
4518 uint8_t timestamp_lo;
4519 /* 16-lsb timestamp from POR (100-msec resolution) */
4520 uint16_t timestamp_hi;
4521 /* Event specific data */
4522 uint32_t event_data1;
4524 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
4526 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
4528 } __attribute__((packed));
4530 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
4531 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
4534 * This field indicates the exact type of the completion.
4535 * By convention, the LSB identifies the length of the
4536 * record in 16B units. Even values indicate 16B
4537 * records. Odd values indicate 32B
4540 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
4542 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
4544 /* HWRM Asynchronous Event Information */
4545 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4547 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
4548 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4549 /* Identifiers of events. */
4551 /* PF-VF communication channel status change. */
4552 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4554 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
4555 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
4556 /* Event specific data */
4557 uint32_t event_data2;
4560 * This value is written by the NIC such that it will be different
4561 * for each pass through the completion queue. The even passes
4562 * will write 1. The odd passes will write 0.
4564 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
4567 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
4569 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
4570 /* 8-lsb timestamp from POR (100-msec resolution) */
4571 uint8_t timestamp_lo;
4572 /* 16-lsb timestamp from POR (100-msec resolution) */
4573 uint16_t timestamp_hi;
4574 /* Event specific data */
4575 uint32_t event_data1;
4577 * If this bit is set to 1, then it indicates that the PF-VF
4578 * communication was lost and it is established.
4579 * If this bit set to 0, then it indicates that the PF-VF
4580 * communication was established and it is lost.
4582 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
4584 } __attribute__((packed));
4586 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
4587 struct hwrm_async_event_cmpl_vf_cfg_change {
4590 * This field indicates the exact type of the completion.
4591 * By convention, the LSB identifies the length of the
4592 * record in 16B units. Even values indicate 16B
4593 * records. Odd values indicate 32B
4596 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
4598 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
4599 /* HWRM Asynchronous Event Information */
4600 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4602 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
4603 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4604 /* Identifiers of events. */
4606 /* VF Configuration Change */
4607 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
4609 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
4610 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
4611 /* Event specific data */
4612 uint32_t event_data2;
4615 * This value is written by the NIC such that it will be different
4616 * for each pass through the completion queue. The even passes
4617 * will write 1. The odd passes will write 0.
4619 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
4621 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
4622 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
4623 /* 8-lsb timestamp from POR (100-msec resolution) */
4624 uint8_t timestamp_lo;
4625 /* 16-lsb timestamp from POR (100-msec resolution) */
4626 uint16_t timestamp_hi;
4628 * Each flag provided in this field indicates a specific VF
4629 * configuration change. At least one of these flags shall be set to 1
4630 * when an asynchronous event completion of this type is provided
4633 uint32_t event_data1;
4635 * If this bit is set to 1, then the value of MTU
4636 * was changed on this VF.
4637 * If set to 0, then this bit should be ignored.
4639 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
4642 * If this bit is set to 1, then the value of MRU
4643 * was changed on this VF.
4644 * If set to 0, then this bit should be ignored.
4646 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
4649 * If this bit is set to 1, then the value of default MAC
4650 * address was changed on this VF.
4651 * If set to 0, then this bit should be ignored.
4653 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
4656 * If this bit is set to 1, then the value of default VLAN
4657 * was changed on this VF.
4658 * If set to 0, then this bit should be ignored.
4660 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
4663 * If this bit is set to 1, then the value of trusted VF enable
4664 * was changed on this VF.
4665 * If set to 0, then this bit should be ignored.
4667 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
4669 } __attribute__((packed));
4671 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
4672 struct hwrm_async_event_cmpl_llfc_pfc_change {
4675 * This field indicates the exact type of the completion.
4676 * By convention, the LSB identifies the length of the
4677 * record in 16B units. Even values indicate 16B
4678 * records. Odd values indicate 32B
4681 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
4683 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
4684 /* HWRM Asynchronous Event Information */
4685 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4687 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
4688 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4689 /* unused1 is 10 b */
4690 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
4692 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
4693 /* Identifiers of events. */
4695 /* LLFC/PFC Configuration Change */
4696 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
4698 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
4699 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
4700 /* Event specific data */
4701 uint32_t event_data2;
4704 * This value is written by the NIC such that it will be different
4705 * for each pass through the completion queue. The even passes
4706 * will write 1. The odd passes will write 0.
4708 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
4710 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
4712 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
4713 /* 8-lsb timestamp from POR (100-msec resolution) */
4714 uint8_t timestamp_lo;
4715 /* 16-lsb timestamp from POR (100-msec resolution) */
4716 uint16_t timestamp_hi;
4717 /* Event specific data */
4718 uint32_t event_data1;
4719 /* Indicates llfc pfc status change */
4720 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
4722 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
4725 * If this field set to 1, then it indicates that llfc is
4728 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
4731 * If this field is set to 2, then it indicates that pfc
4734 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
4736 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
4737 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
4738 /* Indicates the physical port this llfc pfc change occur */
4739 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
4741 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
4744 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4746 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4748 } __attribute__((packed));
4750 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
4751 struct hwrm_async_event_cmpl_default_vnic_change {
4754 * This field indicates the exact type of the completion.
4755 * By convention, the LSB identifies the length of the
4756 * record in 16B units. Even values indicate 16B
4757 * records. Odd values indicate 32B
4760 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
4762 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
4764 /* HWRM Asynchronous Event Information */
4765 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4767 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
4768 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4769 /* unused1 is 10 b */
4770 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
4772 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
4774 /* Identifiers of events. */
4776 /* Notification of a default vnic allocaiton or free */
4777 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
4779 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
4780 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
4781 /* Event specific data */
4782 uint32_t event_data2;
4785 * This value is written by the NIC such that it will be different
4786 * for each pass through the completion queue. The even passes
4787 * will write 1. The odd passes will write 0.
4789 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
4792 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
4794 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
4795 /* 8-lsb timestamp from POR (100-msec resolution) */
4796 uint8_t timestamp_lo;
4797 /* 16-lsb timestamp from POR (100-msec resolution) */
4798 uint16_t timestamp_hi;
4799 /* Event specific data */
4800 uint32_t event_data1;
4801 /* Indicates default vnic configuration change */
4802 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
4804 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
4807 * If this field is set to 1, then it indicates that
4808 * a default VNIC has been allocate.
4810 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
4813 * If this field is set to 2, then it indicates that
4814 * a default VNIC has been freed.
4816 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
4818 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
4819 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
4820 /* Indicates the physical function this event occured on. */
4821 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
4823 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
4825 /* Indicates the virtual function this event occured on */
4826 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
4828 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
4830 } __attribute__((packed));
4832 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
4833 struct hwrm_async_event_cmpl_hwrm_error {
4836 * This field indicates the exact type of the completion.
4837 * By convention, the LSB identifies the length of the
4838 * record in 16B units. Even values indicate 16B
4839 * records. Odd values indicate 32B
4842 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
4844 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
4845 /* HWRM Asynchronous Event Information */
4846 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
4848 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
4849 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
4850 /* Identifiers of events. */
4853 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
4855 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
4856 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
4857 /* Event specific data */
4858 uint32_t event_data2;
4859 /* Severity of HWRM Error */
4860 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
4862 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
4864 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
4866 /* Non-fatal Error */
4867 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
4870 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
4872 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
4873 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
4876 * This value is written by the NIC such that it will be different
4877 * for each pass through the completion queue. The even passes
4878 * will write 1. The odd passes will write 0.
4880 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
4882 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
4883 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
4884 /* 8-lsb timestamp from POR (100-msec resolution) */
4885 uint8_t timestamp_lo;
4886 /* 16-lsb timestamp from POR (100-msec resolution) */
4887 uint16_t timestamp_hi;
4888 /* Event specific data */
4889 uint32_t event_data1;
4890 /* Time stamp for error event */
4891 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
4893 } __attribute__((packed));
4895 /*******************
4897 *******************/
4900 /* hwrm_func_reset_input (size:192b/24B) */
4901 struct hwrm_func_reset_input {
4902 /* The HWRM command request type. */
4905 * The completion ring to send the completion event on. This should
4906 * be the NQ ID returned from the `nq_alloc` HWRM command.
4910 * The sequence ID is used by the driver for tracking multiple
4911 * commands. This ID is treated as opaque data by the firmware and
4912 * the value is returned in the `hwrm_resp_hdr` upon completion.
4916 * The target ID of the command:
4917 * * 0x0-0xFFF8 - The function ID
4918 * * 0xFFF8-0xFFFE - Reserved for internal processors
4923 * A physical address pointer pointing to a host buffer that the
4924 * command's response data will be written. This can be either a host
4925 * physical address (HPA) or a guest physical address (GPA) and must
4926 * point to a physically contiguous block of memory.
4931 * This bit must be '1' for the vf_id_valid field to be
4934 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
4936 * The ID of the VF that this PF is trying to reset.
4937 * Only the parent PF shall be allowed to reset a child VF.
4939 * A parent PF driver shall use this field only when a specific child VF
4940 * is requested to be reset.
4943 /* This value indicates the level of a function reset. */
4944 uint8_t func_reset_level;
4946 * Reset the caller function and its children VFs (if any). If no
4947 * children functions exist, then reset the caller function only.
4949 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
4951 /* Reset the caller function only */
4952 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
4955 * Reset all children VFs of the caller function driver if the
4956 * caller is a PF driver.
4957 * It is an error to specify this level by a VF driver.
4958 * It is an error to specify this level by a PF driver with
4961 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
4964 * Reset a specific VF of the caller function driver if the caller
4965 * is the parent PF driver.
4966 * It is an error to specify this level by a VF driver.
4967 * It is an error to specify this level by a PF driver that is not
4968 * the parent of the VF that is being requested to reset.
4970 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
4972 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
4973 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
4975 } __attribute__((packed));
4977 /* hwrm_func_reset_output (size:128b/16B) */
4978 struct hwrm_func_reset_output {
4979 /* The specific error status for the command. */
4980 uint16_t error_code;
4981 /* The HWRM command request type. */
4983 /* The sequence ID from the original command. */
4985 /* The length of the response data in number of bytes. */
4987 uint8_t unused_0[7];
4989 * This field is used in Output records to indicate that the output
4990 * is completely written to RAM. This field should be read as '1'
4991 * to indicate that the output has been completely written.
4992 * When writing a command completion or response to an internal processor,
4993 * the order of writes has to be such that this field is written last.
4996 } __attribute__((packed));
4998 /********************
4999 * hwrm_func_getfid *
5000 ********************/
5003 /* hwrm_func_getfid_input (size:192b/24B) */
5004 struct hwrm_func_getfid_input {
5005 /* The HWRM command request type. */
5008 * The completion ring to send the completion event on. This should
5009 * be the NQ ID returned from the `nq_alloc` HWRM command.
5013 * The sequence ID is used by the driver for tracking multiple
5014 * commands. This ID is treated as opaque data by the firmware and
5015 * the value is returned in the `hwrm_resp_hdr` upon completion.
5019 * The target ID of the command:
5020 * * 0x0-0xFFF8 - The function ID
5021 * * 0xFFF8-0xFFFE - Reserved for internal processors
5026 * A physical address pointer pointing to a host buffer that the
5027 * command's response data will be written. This can be either a host
5028 * physical address (HPA) or a guest physical address (GPA) and must
5029 * point to a physically contiguous block of memory.
5034 * This bit must be '1' for the pci_id field to be
5037 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
5039 * This value is the PCI ID of the queried function.
5040 * If ARI is enabled, then it is
5041 * Bus Number (8b):Function Number(8b). Otherwise, it is
5042 * Bus Number (8b):Device Number (5b):Function Number(3b).
5045 uint8_t unused_0[2];
5046 } __attribute__((packed));
5048 /* hwrm_func_getfid_output (size:128b/16B) */
5049 struct hwrm_func_getfid_output {
5050 /* The specific error status for the command. */
5051 uint16_t error_code;
5052 /* The HWRM command request type. */
5054 /* The sequence ID from the original command. */
5056 /* The length of the response data in number of bytes. */
5059 * FID value. This value is used to identify operations on the PCI
5060 * bus as belonging to a particular PCI function.
5063 uint8_t unused_0[5];
5065 * This field is used in Output records to indicate that the output
5066 * is completely written to RAM. This field should be read as '1'
5067 * to indicate that the output has been completely written.
5068 * When writing a command completion or response to an internal processor,
5069 * the order of writes has to be such that this field is written last.
5072 } __attribute__((packed));
5074 /**********************
5075 * hwrm_func_vf_alloc *
5076 **********************/
5079 /* hwrm_func_vf_alloc_input (size:192b/24B) */
5080 struct hwrm_func_vf_alloc_input {
5081 /* The HWRM command request type. */
5084 * The completion ring to send the completion event on. This should
5085 * be the NQ ID returned from the `nq_alloc` HWRM command.
5089 * The sequence ID is used by the driver for tracking multiple
5090 * commands. This ID is treated as opaque data by the firmware and
5091 * the value is returned in the `hwrm_resp_hdr` upon completion.
5095 * The target ID of the command:
5096 * * 0x0-0xFFF8 - The function ID
5097 * * 0xFFF8-0xFFFE - Reserved for internal processors
5102 * A physical address pointer pointing to a host buffer that the
5103 * command's response data will be written. This can be either a host
5104 * physical address (HPA) or a guest physical address (GPA) and must
5105 * point to a physically contiguous block of memory.
5110 * This bit must be '1' for the first_vf_id field to be
5113 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
5115 * This value is used to identify a Virtual Function (VF).
5116 * The scope of VF ID is local within a PF.
5118 uint16_t first_vf_id;
5119 /* The number of virtual functions requested. */
5121 } __attribute__((packed));
5123 /* hwrm_func_vf_alloc_output (size:128b/16B) */
5124 struct hwrm_func_vf_alloc_output {
5125 /* The specific error status for the command. */
5126 uint16_t error_code;
5127 /* The HWRM command request type. */
5129 /* The sequence ID from the original command. */
5131 /* The length of the response data in number of bytes. */
5133 /* The ID of the first VF allocated. */
5134 uint16_t first_vf_id;
5135 uint8_t unused_0[5];
5137 * This field is used in Output records to indicate that the output
5138 * is completely written to RAM. This field should be read as '1'
5139 * to indicate that the output has been completely written.
5140 * When writing a command completion or response to an internal processor,
5141 * the order of writes has to be such that this field is written last.
5144 } __attribute__((packed));
5146 /*********************
5147 * hwrm_func_vf_free *
5148 *********************/
5151 /* hwrm_func_vf_free_input (size:192b/24B) */
5152 struct hwrm_func_vf_free_input {
5153 /* The HWRM command request type. */
5156 * The completion ring to send the completion event on. This should
5157 * be the NQ ID returned from the `nq_alloc` HWRM command.
5161 * The sequence ID is used by the driver for tracking multiple
5162 * commands. This ID is treated as opaque data by the firmware and
5163 * the value is returned in the `hwrm_resp_hdr` upon completion.
5167 * The target ID of the command:
5168 * * 0x0-0xFFF8 - The function ID
5169 * * 0xFFF8-0xFFFE - Reserved for internal processors
5174 * A physical address pointer pointing to a host buffer that the
5175 * command's response data will be written. This can be either a host
5176 * physical address (HPA) or a guest physical address (GPA) and must
5177 * point to a physically contiguous block of memory.
5182 * This bit must be '1' for the first_vf_id field to be
5185 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
5187 * This value is used to identify a Virtual Function (VF).
5188 * The scope of VF ID is local within a PF.
5190 uint16_t first_vf_id;
5192 * The number of virtual functions requested.
5193 * 0xFFFF - Cleanup all children of this PF.
5196 } __attribute__((packed));
5198 /* hwrm_func_vf_free_output (size:128b/16B) */
5199 struct hwrm_func_vf_free_output {
5200 /* The specific error status for the command. */
5201 uint16_t error_code;
5202 /* The HWRM command request type. */
5204 /* The sequence ID from the original command. */
5206 /* The length of the response data in number of bytes. */
5208 uint8_t unused_0[7];
5210 * This field is used in Output records to indicate that the output
5211 * is completely written to RAM. This field should be read as '1'
5212 * to indicate that the output has been completely written.
5213 * When writing a command completion or response to an internal processor,
5214 * the order of writes has to be such that this field is written last.
5217 } __attribute__((packed));
5219 /********************
5220 * hwrm_func_vf_cfg *
5221 ********************/
5224 /* hwrm_func_vf_cfg_input (size:448b/56B) */
5225 struct hwrm_func_vf_cfg_input {
5226 /* The HWRM command request type. */
5229 * The completion ring to send the completion event on. This should
5230 * be the NQ ID returned from the `nq_alloc` HWRM command.
5234 * The sequence ID is used by the driver for tracking multiple
5235 * commands. This ID is treated as opaque data by the firmware and
5236 * the value is returned in the `hwrm_resp_hdr` upon completion.
5240 * The target ID of the command:
5241 * * 0x0-0xFFF8 - The function ID
5242 * * 0xFFF8-0xFFFE - Reserved for internal processors
5247 * A physical address pointer pointing to a host buffer that the
5248 * command's response data will be written. This can be either a host
5249 * physical address (HPA) or a guest physical address (GPA) and must
5250 * point to a physically contiguous block of memory.
5255 * This bit must be '1' for the mtu field to be
5258 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
5261 * This bit must be '1' for the guest_vlan field to be
5264 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
5267 * This bit must be '1' for the async_event_cr field to be
5270 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
5273 * This bit must be '1' for the dflt_mac_addr field to be
5276 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
5279 * This bit must be '1' for the num_rsscos_ctxs field to be
5282 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
5285 * This bit must be '1' for the num_cmpl_rings field to be
5288 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
5291 * This bit must be '1' for the num_tx_rings field to be
5294 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
5297 * This bit must be '1' for the num_rx_rings field to be
5300 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
5303 * This bit must be '1' for the num_l2_ctxs field to be
5306 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
5309 * This bit must be '1' for the num_vnics field to be
5312 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
5315 * This bit must be '1' for the num_stat_ctxs field to be
5318 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
5321 * This bit must be '1' for the num_hw_ring_grps field to be
5324 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
5327 * The maximum transmission unit requested on the function.
5328 * The HWRM should make sure that the mtu of
5329 * the function does not exceed the mtu of the physical
5330 * port that this function is associated with.
5332 * In addition to requesting mtu per function, it is
5333 * possible to configure mtu per transmit ring.
5334 * By default, the mtu of each transmit ring associated
5335 * with a function is equal to the mtu of the function.
5336 * The HWRM should make sure that the mtu of each transmit
5337 * ring that is assigned to a function has a valid mtu.
5341 * The guest VLAN for the function being configured.
5342 * This field's format is same as 802.1Q Tag's
5343 * Tag Control Information (TCI) format that includes both
5344 * Priority Code Point (PCP) and VLAN Identifier (VID).
5346 uint16_t guest_vlan;
5348 * ID of the target completion ring for receiving asynchronous
5349 * event completions. If this field is not valid, then the
5350 * HWRM shall use the default completion ring of the function
5351 * that is being configured as the target completion ring for
5352 * providing any asynchronous event completions for that
5354 * If this field is valid, then the HWRM shall use the
5355 * completion ring identified by this ID as the target
5356 * completion ring for providing any asynchronous event
5357 * completions for the function that is being configured.
5359 uint16_t async_event_cr;
5361 * This value is the current MAC address requested by the VF
5362 * driver to be configured on this VF. A value of
5363 * 00-00-00-00-00-00 indicates no MAC address configuration
5364 * is requested by the VF driver.
5365 * The parent PF driver may reject or overwrite this
5368 uint8_t dflt_mac_addr[6];
5371 * This bit requests that the firmware test to see if all the assets
5372 * requested in this command (i.e. number of TX rings) are available.
5373 * The firmware will return an error if the requested assets are
5374 * not available. The firwmare will NOT reserve the assets if they
5377 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
5380 * This bit requests that the firmware test to see if all the assets
5381 * requested in this command (i.e. number of RX rings) are available.
5382 * The firmware will return an error if the requested assets are
5383 * not available. The firwmare will NOT reserve the assets if they
5386 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
5389 * This bit requests that the firmware test to see if all the assets
5390 * requested in this command (i.e. number of CMPL rings) are available.
5391 * The firmware will return an error if the requested assets are
5392 * not available. The firwmare will NOT reserve the assets if they
5395 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
5398 * This bit requests that the firmware test to see if all the assets
5399 * requested in this command (i.e. number of RSS ctx) are available.
5400 * The firmware will return an error if the requested assets are
5401 * not available. The firwmare will NOT reserve the assets if they
5404 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
5407 * This bit requests that the firmware test to see if all the assets
5408 * requested in this command (i.e. number of ring groups) are available.
5409 * The firmware will return an error if the requested assets are
5410 * not available. The firwmare will NOT reserve the assets if they
5413 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
5416 * This bit requests that the firmware test to see if all the assets
5417 * requested in this command (i.e. number of stat ctx) are available.
5418 * The firmware will return an error if the requested assets are
5419 * not available. The firwmare will NOT reserve the assets if they
5422 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
5425 * This bit requests that the firmware test to see if all the assets
5426 * requested in this command (i.e. number of VNICs) are available.
5427 * The firmware will return an error if the requested assets are
5428 * not available. The firwmare will NOT reserve the assets if they
5431 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
5434 * This bit requests that the firmware test to see if all the assets
5435 * requested in this command (i.e. number of L2 ctx) are available.
5436 * The firmware will return an error if the requested assets are
5437 * not available. The firwmare will NOT reserve the assets if they
5440 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
5442 /* The number of RSS/COS contexts requested for the VF. */
5443 uint16_t num_rsscos_ctxs;
5444 /* The number of completion rings requested for the VF. */
5445 uint16_t num_cmpl_rings;
5446 /* The number of transmit rings requested for the VF. */
5447 uint16_t num_tx_rings;
5448 /* The number of receive rings requested for the VF. */
5449 uint16_t num_rx_rings;
5450 /* The number of L2 contexts requested for the VF. */
5451 uint16_t num_l2_ctxs;
5452 /* The number of vnics requested for the VF. */
5454 /* The number of statistic contexts requested for the VF. */
5455 uint16_t num_stat_ctxs;
5456 /* The number of HW ring groups requested for the VF. */
5457 uint16_t num_hw_ring_grps;
5458 uint8_t unused_0[4];
5459 } __attribute__((packed));
5461 /* hwrm_func_vf_cfg_output (size:128b/16B) */
5462 struct hwrm_func_vf_cfg_output {
5463 /* The specific error status for the command. */
5464 uint16_t error_code;
5465 /* The HWRM command request type. */
5467 /* The sequence ID from the original command. */
5469 /* The length of the response data in number of bytes. */
5471 uint8_t unused_0[7];
5473 * This field is used in Output records to indicate that the output
5474 * is completely written to RAM. This field should be read as '1'
5475 * to indicate that the output has been completely written.
5476 * When writing a command completion or response to an internal processor,
5477 * the order of writes has to be such that this field is written last.
5480 } __attribute__((packed));
5482 /*******************
5484 *******************/
5487 /* hwrm_func_qcaps_input (size:192b/24B) */
5488 struct hwrm_func_qcaps_input {
5489 /* The HWRM command request type. */
5492 * The completion ring to send the completion event on. This should
5493 * be the NQ ID returned from the `nq_alloc` HWRM command.
5497 * The sequence ID is used by the driver for tracking multiple
5498 * commands. This ID is treated as opaque data by the firmware and
5499 * the value is returned in the `hwrm_resp_hdr` upon completion.
5503 * The target ID of the command:
5504 * * 0x0-0xFFF8 - The function ID
5505 * * 0xFFF8-0xFFFE - Reserved for internal processors
5510 * A physical address pointer pointing to a host buffer that the
5511 * command's response data will be written. This can be either a host
5512 * physical address (HPA) or a guest physical address (GPA) and must
5513 * point to a physically contiguous block of memory.
5517 * Function ID of the function that is being queried.
5518 * 0xFF... (All Fs) if the query is for the requesting
5522 uint8_t unused_0[6];
5523 } __attribute__((packed));
5525 /* hwrm_func_qcaps_output (size:640b/80B) */
5526 struct hwrm_func_qcaps_output {
5527 /* The specific error status for the command. */
5528 uint16_t error_code;
5529 /* The HWRM command request type. */
5531 /* The sequence ID from the original command. */
5533 /* The length of the response data in number of bytes. */
5536 * FID value. This value is used to identify operations on the PCI
5537 * bus as belonging to a particular PCI function.
5541 * Port ID of port that this function is associated with.
5542 * Valid only for the PF.
5543 * 0xFF... (All Fs) if this function is not associated with
5545 * 0xFF... (All Fs) if this function is called from a VF.
5549 /* If 1, then Push mode is supported on this function. */
5550 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
5553 * If 1, then the global MSI-X auto-masking is enabled for the
5556 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
5559 * If 1, then the Precision Time Protocol (PTP) processing
5560 * is supported on this function.
5561 * The HWRM should enable PTP on only a single Physical
5562 * Function (PF) per port.
5564 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
5567 * If 1, then RDMA over Converged Ethernet (RoCE) v1
5568 * is supported on this function.
5570 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
5573 * If 1, then RDMA over Converged Ethernet (RoCE) v2
5574 * is supported on this function.
5576 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
5579 * If 1, then control and configuration of WoL magic packet
5580 * are supported on this function.
5582 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
5585 * If 1, then control and configuration of bitmap pattern
5586 * packet are supported on this function.
5588 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
5591 * If set to 1, then the control and configuration of rate limit
5592 * of an allocated TX ring on the queried function is supported.
5594 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
5597 * If 1, then control and configuration of minimum and
5598 * maximum bandwidths are supported on the queried function.
5600 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
5603 * If the query is for a VF, then this flag shall be ignored.
5604 * If this query is for a PF and this flag is set to 1,
5605 * then the PF has the capability to set the rate limits
5606 * on the TX rings of its children VFs.
5607 * If this query is for a PF and this flag is set to 0, then
5608 * the PF does not have the capability to set the rate limits
5609 * on the TX rings of its children VFs.
5611 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
5614 * If the query is for a VF, then this flag shall be ignored.
5615 * If this query is for a PF and this flag is set to 1,
5616 * then the PF has the capability to set the minimum and/or
5617 * maximum bandwidths for its children VFs.
5618 * If this query is for a PF and this flag is set to 0, then
5619 * the PF does not have the capability to set the minimum or
5620 * maximum bandwidths for its children VFs.
5622 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
5625 * Standard TX Ring mode is used for the allocation of TX ring
5626 * and underlying scheduling resources that allow bandwidth
5627 * reservation and limit settings on the queried function.
5628 * If set to 1, then standard TX ring mode is supported
5629 * on the queried function.
5630 * If set to 0, then standard TX ring mode is not available
5631 * on the queried function.
5633 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
5636 * If the query is for a VF, then this flag shall be ignored,
5637 * If this query is for a PF and this flag is set to 1,
5638 * then the PF has the capability to detect GENEVE tunnel
5641 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
5644 * If the query is for a VF, then this flag shall be ignored,
5645 * If this query is for a PF and this flag is set to 1,
5646 * then the PF has the capability to detect NVGRE tunnel
5649 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
5652 * If the query is for a VF, then this flag shall be ignored,
5653 * If this query is for a PF and this flag is set to 1,
5654 * then the PF has the capability to detect GRE tunnel
5657 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
5660 * If the query is for a VF, then this flag shall be ignored,
5661 * If this query is for a PF and this flag is set to 1,
5662 * then the PF has the capability to detect MPLS tunnel
5665 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
5668 * If the query is for a VF, then this flag shall be ignored,
5669 * If this query is for a PF and this flag is set to 1,
5670 * then the PF has the capability to support pcie stats.
5672 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
5675 * If the query is for a VF, then this flag shall be ignored,
5676 * If this query is for a PF and this flag is set to 1,
5677 * then the PF has the capability to adopt the VF's belonging
5680 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
5683 * If the query is for a VF, then this flag shall be ignored,
5684 * If this query is for a PF and this flag is set to 1,
5685 * then the PF has the capability to administer another PF.
5687 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
5690 * If the query is for a VF, then this flag shall be ignored.
5691 * If this query is for a PF and this flag is set to 1, then
5692 * the PF will know that the firmware has the capability to track
5693 * the virtual link status.
5695 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
5698 * If 1, then this function supports the push mode that uses
5699 * write combine buffers and the long inline tx buffer descriptor.
5701 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
5704 * This value is current MAC address configured for this
5705 * function. A value of 00-00-00-00-00-00 indicates no
5706 * MAC address is currently configured.
5708 uint8_t mac_address[6];
5710 * The maximum number of RSS/COS contexts that can be
5711 * allocated to the function.
5713 uint16_t max_rsscos_ctx;
5715 * The maximum number of completion rings that can be
5716 * allocated to the function.
5718 uint16_t max_cmpl_rings;
5720 * The maximum number of transmit rings that can be
5721 * allocated to the function.
5723 uint16_t max_tx_rings;
5725 * The maximum number of receive rings that can be
5726 * allocated to the function.
5728 uint16_t max_rx_rings;
5730 * The maximum number of L2 contexts that can be
5731 * allocated to the function.
5733 uint16_t max_l2_ctxs;
5735 * The maximum number of VNICs that can be
5736 * allocated to the function.
5740 * The identifier for the first VF enabled on a PF. This
5741 * is valid only on the PF with SR-IOV enabled.
5742 * 0xFF... (All Fs) if this command is called on a PF with
5743 * SR-IOV disabled or on a VF.
5745 uint16_t first_vf_id;
5747 * The maximum number of VFs that can be
5748 * allocated to the function. This is valid only on the
5749 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
5750 * command is called on a PF with SR-IOV disabled or
5755 * The maximum number of statistic contexts that can be
5756 * allocated to the function.
5758 uint16_t max_stat_ctx;
5760 * The maximum number of Encapsulation records that can be
5761 * offloaded by this function.
5763 uint32_t max_encap_records;
5765 * The maximum number of decapsulation records that can
5766 * be offloaded by this function.
5768 uint32_t max_decap_records;
5770 * The maximum number of Exact Match (EM) flows that can be
5771 * offloaded by this function on the TX side.
5773 uint32_t max_tx_em_flows;
5775 * The maximum number of Wildcard Match (WM) flows that can
5776 * be offloaded by this function on the TX side.
5778 uint32_t max_tx_wm_flows;
5780 * The maximum number of Exact Match (EM) flows that can be
5781 * offloaded by this function on the RX side.
5783 uint32_t max_rx_em_flows;
5785 * The maximum number of Wildcard Match (WM) flows that can
5786 * be offloaded by this function on the RX side.
5788 uint32_t max_rx_wm_flows;
5790 * The maximum number of multicast filters that can
5791 * be supported by this function on the RX side.
5793 uint32_t max_mcast_filters;
5795 * The maximum value of flow_id that can be supported
5796 * in completion records.
5798 uint32_t max_flow_id;
5800 * The maximum number of HW ring groups that can be
5801 * supported on this function.
5803 uint32_t max_hw_ring_grps;
5805 * The maximum number of strict priority transmit rings
5806 * that can be allocated to the function.
5807 * This number indicates the maximum number of TX rings
5808 * that can be assigned strict priorities out of the
5809 * maximum number of TX rings that can be allocated
5810 * (max_tx_rings) to the function.
5812 uint16_t max_sp_tx_rings;
5815 * This field is used in Output records to indicate that the output
5816 * is completely written to RAM. This field should be read as '1'
5817 * to indicate that the output has been completely written.
5818 * When writing a command completion or response to an internal processor,
5819 * the order of writes has to be such that this field is written last.
5822 } __attribute__((packed));
5829 /* hwrm_func_qcfg_input (size:192b/24B) */
5830 struct hwrm_func_qcfg_input {
5831 /* The HWRM command request type. */
5834 * The completion ring to send the completion event on. This should
5835 * be the NQ ID returned from the `nq_alloc` HWRM command.
5839 * The sequence ID is used by the driver for tracking multiple
5840 * commands. This ID is treated as opaque data by the firmware and
5841 * the value is returned in the `hwrm_resp_hdr` upon completion.
5845 * The target ID of the command:
5846 * * 0x0-0xFFF8 - The function ID
5847 * * 0xFFF8-0xFFFE - Reserved for internal processors
5852 * A physical address pointer pointing to a host buffer that the
5853 * command's response data will be written. This can be either a host
5854 * physical address (HPA) or a guest physical address (GPA) and must
5855 * point to a physically contiguous block of memory.
5859 * Function ID of the function that is being queried.
5860 * 0xFF... (All Fs) if the query is for the requesting
5864 uint8_t unused_0[6];
5865 } __attribute__((packed));
5867 /* hwrm_func_qcfg_output (size:640b/80B) */
5868 struct hwrm_func_qcfg_output {
5869 /* The specific error status for the command. */
5870 uint16_t error_code;
5871 /* The HWRM command request type. */
5873 /* The sequence ID from the original command. */
5875 /* The length of the response data in number of bytes. */
5878 * FID value. This value is used to identify operations on the PCI
5879 * bus as belonging to a particular PCI function.
5883 * Port ID of port that this function is associated with.
5884 * 0xFF... (All Fs) if this function is not associated with
5889 * This value is the current VLAN setting for this
5890 * function. The value of 0 for this field indicates
5891 * no priority tagging or VLAN is used.
5892 * This field's format is same as 802.1Q Tag's
5893 * Tag Control Information (TCI) format that includes both
5894 * Priority Code Point (PCP) and VLAN Identifier (VID).
5899 * If 1, then magic packet based Out-Of-Box WoL is enabled on
5900 * the port associated with this function.
5902 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
5905 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
5906 * on the port associated with this function.
5908 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
5911 * If set to 1, then FW based DCBX agent is enabled and running on
5912 * the port associated with this function.
5913 * If set to 0, then DCBX agent is not running in the firmware.
5915 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
5918 * Standard TX Ring mode is used for the allocation of TX ring
5919 * and underlying scheduling resources that allow bandwidth
5920 * reservation and limit settings on the queried function.
5921 * If set to 1, then standard TX ring mode is enabled
5922 * on the queried function.
5923 * If set to 0, then the standard TX ring mode is disabled
5924 * on the queried function. In this extended TX ring resource
5925 * mode, the minimum and maximum bandwidth settings are not
5926 * supported to allow the allocation of TX rings to span multiple
5929 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
5932 * If set to 1 then FW based LLDP agent is enabled and running on
5933 * the port associated with this function.
5934 * If set to 0 then the LLDP agent is not running in the firmware.
5936 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
5939 * If set to 1, then multi-host mode is active for this function.
5940 * If set to 0, then multi-host mode is inactive for this function
5941 * or not applicable for this device.
5943 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
5946 * If the function that is being queried is a PF, then the HWRM shall
5947 * set this field to 0 and the HWRM client shall ignore this field.
5948 * If the function that is being queried is a VF, then the HWRM shall
5949 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
5950 * shall set this field to 0.
5952 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
5955 * This value is current MAC address configured for this
5956 * function. A value of 00-00-00-00-00-00 indicates no
5957 * MAC address is currently configured.
5959 uint8_t mac_address[6];
5961 * This value is current PCI ID of this
5962 * function. If ARI is enabled, then it is
5963 * Bus Number (8b):Function Number(8b). Otherwise, it is
5964 * Bus Number (8b):Device Number (4b):Function Number(4b).
5965 * If multi-host mode is active, the 4 lsb will indicate
5966 * the PF index for this function.
5970 * The number of RSS/COS contexts currently
5971 * allocated to the function.
5973 uint16_t alloc_rsscos_ctx;
5975 * The number of completion rings currently allocated to
5976 * the function. This does not include the rings allocated
5977 * to any children functions if any.
5979 uint16_t alloc_cmpl_rings;
5981 * The number of transmit rings currently allocated to
5982 * the function. This does not include the rings allocated
5983 * to any children functions if any.
5985 uint16_t alloc_tx_rings;
5987 * The number of receive rings currently allocated to
5988 * the function. This does not include the rings allocated
5989 * to any children functions if any.
5991 uint16_t alloc_rx_rings;
5992 /* The allocated number of L2 contexts to the function. */
5993 uint16_t alloc_l2_ctx;
5994 /* The allocated number of vnics to the function. */
5995 uint16_t alloc_vnics;
5997 * The maximum transmission unit of the function.
5998 * For rings allocated on this function, this default
5999 * value is used if ring MTU is not specified.
6003 * The maximum receive unit of the function.
6004 * For vnics allocated on this function, this default
6005 * value is used if vnic MRU is not specified.
6008 /* The statistics context assigned to a function. */
6009 uint16_t stat_ctx_id;
6011 * The HWRM shall return Unknown value for this field
6012 * when this command is used to query VF's configuration.
6014 uint8_t port_partition_type;
6015 /* Single physical function */
6016 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
6017 /* Multiple physical functions */
6018 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
6019 /* Network Partitioning 1.0 */
6020 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
6021 /* Network Partitioning 1.5 */
6022 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
6023 /* Network Partitioning 2.0 */
6024 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
6026 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
6028 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
6029 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
6031 * This field will indicate number of physical functions on this port_partition.
6032 * HWRM shall return unavail (i.e. value of 0) for this field
6033 * when this command is used to query VF's configuration or
6034 * from older firmware that doesn't support this field.
6036 uint8_t port_pf_cnt;
6037 /* number of PFs is not available */
6038 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
6039 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
6040 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
6042 * The default VNIC ID assigned to a function that is
6045 uint16_t dflt_vnic_id;
6046 uint16_t max_mtu_configured;
6048 * Minimum BW allocated for this function.
6049 * The HWRM will translate this value into byte counter and
6050 * time interval used for the scheduler inside the device.
6051 * A value of 0 indicates the minimum bandwidth is not
6055 /* The bandwidth value. */
6056 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
6058 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
6059 /* The granularity of the value (bits or bytes). */
6060 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
6061 UINT32_C(0x10000000)
6062 /* Value is in bits. */
6063 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
6064 (UINT32_C(0x0) << 28)
6065 /* Value is in bytes. */
6066 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
6067 (UINT32_C(0x1) << 28)
6068 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
6069 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
6070 /* bw_value_unit is 3 b */
6071 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
6072 UINT32_C(0xe0000000)
6073 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6074 /* Value is in Mb or MB (base 10). */
6075 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
6076 (UINT32_C(0x0) << 29)
6077 /* Value is in Kb or KB (base 10). */
6078 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
6079 (UINT32_C(0x2) << 29)
6080 /* Value is in bits or bytes. */
6081 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
6082 (UINT32_C(0x4) << 29)
6083 /* Value is in Gb or GB (base 10). */
6084 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
6085 (UINT32_C(0x6) << 29)
6086 /* Value is in 1/100th of a percentage of total bandwidth. */
6087 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
6088 (UINT32_C(0x1) << 29)
6090 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
6091 (UINT32_C(0x7) << 29)
6092 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
6093 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6095 * Maximum BW allocated for this function.
6096 * The HWRM will translate this value into byte counter and
6097 * time interval used for the scheduler inside the device.
6098 * A value of 0 indicates that the maximum bandwidth is not
6102 /* The bandwidth value. */
6103 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
6105 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
6106 /* The granularity of the value (bits or bytes). */
6107 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
6108 UINT32_C(0x10000000)
6109 /* Value is in bits. */
6110 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
6111 (UINT32_C(0x0) << 28)
6112 /* Value is in bytes. */
6113 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
6114 (UINT32_C(0x1) << 28)
6115 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
6116 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
6117 /* bw_value_unit is 3 b */
6118 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
6119 UINT32_C(0xe0000000)
6120 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6121 /* Value is in Mb or MB (base 10). */
6122 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
6123 (UINT32_C(0x0) << 29)
6124 /* Value is in Kb or KB (base 10). */
6125 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
6126 (UINT32_C(0x2) << 29)
6127 /* Value is in bits or bytes. */
6128 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
6129 (UINT32_C(0x4) << 29)
6130 /* Value is in Gb or GB (base 10). */
6131 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
6132 (UINT32_C(0x6) << 29)
6133 /* Value is in 1/100th of a percentage of total bandwidth. */
6134 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
6135 (UINT32_C(0x1) << 29)
6137 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
6138 (UINT32_C(0x7) << 29)
6139 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
6140 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6142 * This value indicates the Edge virtual bridge mode for the
6143 * domain that this function belongs to.
6146 /* No Edge Virtual Bridging (EVB) */
6147 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6148 /* Virtual Ethernet Bridge (VEB) */
6149 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
6150 /* Virtual Ethernet Port Aggregator (VEPA) */
6151 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
6152 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
6153 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
6156 * This value indicates the PCIE device cache line size.
6157 * The cache line size allows the DMA writes to terminate and
6158 * start at the cache boundary.
6160 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
6162 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
6163 /* Cache Line Size 64 bytes */
6164 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
6166 /* Cache Line Size 128 bytes */
6167 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
6169 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
6170 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
6171 /* This value is the virtual link admin state setting. */
6172 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
6174 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
6175 /* Admin link state is in forced down mode. */
6176 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
6177 (UINT32_C(0x0) << 2)
6178 /* Admin link state is in forced up mode. */
6179 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
6180 (UINT32_C(0x1) << 2)
6181 /* Admin link state is in auto mode - follows the physical link state. */
6182 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
6183 (UINT32_C(0x2) << 2)
6184 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
6185 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
6186 /* Reserved for future. */
6187 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
6189 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
6191 * The number of VFs that are allocated to the function.
6192 * This is valid only on the PF with SR-IOV enabled.
6193 * 0xFF... (All Fs) if this command is called on a PF with
6194 * SR-IOV disabled or on a VF.
6198 * The number of allocated multicast filters for this
6199 * function on the RX side.
6201 uint32_t alloc_mcast_filters;
6203 * The number of allocated HW ring groups for this
6206 uint32_t alloc_hw_ring_grps;
6208 * The number of strict priority transmit rings out of
6209 * currently allocated TX rings to the function
6212 uint16_t alloc_sp_tx_rings;
6214 * The number of statistics contexts
6215 * currently reserved for the function.
6217 uint16_t alloc_stat_ctx;
6219 * This field specifies how many NQs are reserved for the PF.
6220 * Remaining NQs that belong to the PF are available for VFs.
6221 * Once a PF has created VFs, it cannot change how many NQs are
6222 * reserved for itself (since the NQs must be contiguous in HW).
6224 uint16_t alloc_msix;
6225 uint8_t unused_2[5];
6227 * This field is used in Output records to indicate that the output
6228 * is completely written to RAM. This field should be read as '1'
6229 * to indicate that the output has been completely written.
6230 * When writing a command completion or response to an internal processor,
6231 * the order of writes has to be such that this field is written last.
6234 } __attribute__((packed));
6241 /* hwrm_func_cfg_input (size:704b/88B) */
6242 struct hwrm_func_cfg_input {
6243 /* The HWRM command request type. */
6246 * The completion ring to send the completion event on. This should
6247 * be the NQ ID returned from the `nq_alloc` HWRM command.
6251 * The sequence ID is used by the driver for tracking multiple
6252 * commands. This ID is treated as opaque data by the firmware and
6253 * the value is returned in the `hwrm_resp_hdr` upon completion.
6257 * The target ID of the command:
6258 * * 0x0-0xFFF8 - The function ID
6259 * * 0xFFF8-0xFFFE - Reserved for internal processors
6264 * A physical address pointer pointing to a host buffer that the
6265 * command's response data will be written. This can be either a host
6266 * physical address (HPA) or a guest physical address (GPA) and must
6267 * point to a physically contiguous block of memory.
6271 * Function ID of the function that is being
6273 * If set to 0xFF... (All Fs), then the the configuration is
6274 * for the requesting function.
6278 * This field specifies how many NQs will be reserved for the PF.
6279 * Remaining NQs that belong to the PF become available for VFs.
6280 * Once a PF has created VFs, it cannot change how many NQs are
6281 * reserved for itself (since the NQs must be contiguous in HW).
6286 * When this bit is '1', the function is disabled with
6287 * source MAC address check.
6288 * This is an anti-spoofing check. If this flag is set,
6289 * then the function shall be configured to disallow
6290 * transmission of frames with the source MAC address that
6291 * is configured for this function.
6293 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
6296 * When this bit is '1', the function is enabled with
6297 * source MAC address check.
6298 * This is an anti-spoofing check. If this flag is set,
6299 * then the function shall be configured to allow
6300 * transmission of frames with the source MAC address that
6301 * is configured for this function.
6303 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
6306 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
6308 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
6310 * Standard TX Ring mode is used for the allocation of TX ring
6311 * and underlying scheduling resources that allow bandwidth
6312 * reservation and limit settings on the queried function.
6313 * If set to 1, then standard TX ring mode is requested to be
6314 * enabled on the function being configured.
6316 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
6319 * Standard TX Ring mode is used for the allocation of TX ring
6320 * and underlying scheduling resources that allow bandwidth
6321 * reservation and limit settings on the queried function.
6322 * If set to 1, then the standard TX ring mode is requested to
6323 * be disabled on the function being configured. In this extended
6324 * TX ring resource mode, the minimum and maximum bandwidth settings
6325 * are not supported to allow the allocation of TX rings to
6326 * span multiple scheduler nodes.
6328 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
6331 * If this bit is set, virtual mac address configured
6332 * in this command will be persistent over warm boot.
6334 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
6337 * This bit only applies to the VF. If this bit is set, the statistic
6338 * context counters will not be cleared when the statistic context is freed
6339 * or a function reset is called on VF. This bit will be cleared when the PF
6340 * is unloaded or a function reset is called on the PF.
6342 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
6345 * This bit requests that the firmware test to see if all the assets
6346 * requested in this command (i.e. number of TX rings) are available.
6347 * The firmware will return an error if the requested assets are
6348 * not available. The firwmare will NOT reserve the assets if they
6351 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6354 * This bit requests that the firmware test to see if all the assets
6355 * requested in this command (i.e. number of RX rings) are available.
6356 * The firmware will return an error if the requested assets are
6357 * not available. The firwmare will NOT reserve the assets if they
6360 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6363 * This bit requests that the firmware test to see if all the assets
6364 * requested in this command (i.e. number of CMPL rings) are available.
6365 * The firmware will return an error if the requested assets are
6366 * not available. The firwmare will NOT reserve the assets if they
6369 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6372 * This bit requests that the firmware test to see if all the assets
6373 * requested in this command (i.e. number of RSS ctx) are available.
6374 * The firmware will return an error if the requested assets are
6375 * not available. The firwmare will NOT reserve the assets if they
6378 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6381 * This bit requests that the firmware test to see if all the assets
6382 * requested in this command (i.e. number of ring groups) are available.
6383 * The firmware will return an error if the requested assets are
6384 * not available. The firwmare will NOT reserve the assets if they
6387 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6390 * This bit requests that the firmware test to see if all the assets
6391 * requested in this command (i.e. number of stat ctx) are available.
6392 * The firmware will return an error if the requested assets are
6393 * not available. The firwmare will NOT reserve the assets if they
6396 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6399 * This bit requests that the firmware test to see if all the assets
6400 * requested in this command (i.e. number of VNICs) are available.
6401 * The firmware will return an error if the requested assets are
6402 * not available. The firwmare will NOT reserve the assets if they
6405 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6408 * This bit requests that the firmware test to see if all the assets
6409 * requested in this command (i.e. number of L2 ctx) are available.
6410 * The firmware will return an error if the requested assets are
6411 * not available. The firwmare will NOT reserve the assets if they
6414 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6417 * This configuration change can be initiated by a PF driver. This
6418 * configuration request shall be targeted to a VF. From local host
6419 * resident HWRM clients, only the parent PF driver shall be allowed
6420 * to initiate this change on one of its children VFs. If this bit is
6421 * set to 1, then the VF that is being configured is requested to be
6422 * trusted. If this bit is set to 0, then the VF that is being configured
6423 * is requested to be not trusted.
6425 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
6429 * This bit must be '1' for the mtu field to be
6432 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
6435 * This bit must be '1' for the mru field to be
6438 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
6441 * This bit must be '1' for the num_rsscos_ctxs field to be
6444 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6447 * This bit must be '1' for the num_cmpl_rings field to be
6450 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6453 * This bit must be '1' for the num_tx_rings field to be
6456 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6459 * This bit must be '1' for the num_rx_rings field to be
6462 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6465 * This bit must be '1' for the num_l2_ctxs field to be
6468 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6471 * This bit must be '1' for the num_vnics field to be
6474 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
6477 * This bit must be '1' for the num_stat_ctxs field to be
6480 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6483 * This bit must be '1' for the dflt_mac_addr field to be
6486 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6489 * This bit must be '1' for the dflt_vlan field to be
6492 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
6495 * This bit must be '1' for the dflt_ip_addr field to be
6498 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
6501 * This bit must be '1' for the min_bw field to be
6504 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
6507 * This bit must be '1' for the max_bw field to be
6510 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
6513 * This bit must be '1' for the async_event_cr field to be
6516 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6519 * This bit must be '1' for the vlan_antispoof_mode field to be
6522 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
6525 * This bit must be '1' for the allowed_vlan_pris field to be
6528 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
6531 * This bit must be '1' for the evb_mode field to be
6534 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
6537 * This bit must be '1' for the num_mcast_filters field to be
6540 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
6543 * This bit must be '1' for the num_hw_ring_grps field to be
6546 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6549 * This bit must be '1' for the cache_linesize field to be
6552 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
6555 * This bit must be '1' for the num_msix field to be
6558 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
6561 * This bit must be '1' for the link admin state field to be
6564 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
6567 * The maximum transmission unit of the function.
6568 * The HWRM should make sure that the mtu of
6569 * the function does not exceed the mtu of the physical
6570 * port that this function is associated with.
6572 * In addition to configuring mtu per function, it is
6573 * possible to configure mtu per transmit ring.
6574 * By default, the mtu of each transmit ring associated
6575 * with a function is equal to the mtu of the function.
6576 * The HWRM should make sure that the mtu of each transmit
6577 * ring that is assigned to a function has a valid mtu.
6581 * The maximum receive unit of the function.
6582 * The HWRM should make sure that the mru of
6583 * the function does not exceed the mru of the physical
6584 * port that this function is associated with.
6586 * In addition to configuring mru per function, it is
6587 * possible to configure mru per vnic.
6588 * By default, the mru of each vnic associated
6589 * with a function is equal to the mru of the function.
6590 * The HWRM should make sure that the mru of each vnic
6591 * that is assigned to a function has a valid mru.
6595 * The number of RSS/COS contexts requested for the
6598 uint16_t num_rsscos_ctxs;
6600 * The number of completion rings requested for the
6601 * function. This does not include the rings allocated
6602 * to any children functions if any.
6604 uint16_t num_cmpl_rings;
6606 * The number of transmit rings requested for the function.
6607 * This does not include the rings allocated to any
6608 * children functions if any.
6610 uint16_t num_tx_rings;
6612 * The number of receive rings requested for the function.
6613 * This does not include the rings allocated
6614 * to any children functions if any.
6616 uint16_t num_rx_rings;
6617 /* The requested number of L2 contexts for the function. */
6618 uint16_t num_l2_ctxs;
6619 /* The requested number of vnics for the function. */
6621 /* The requested number of statistic contexts for the function. */
6622 uint16_t num_stat_ctxs;
6624 * The number of HW ring groups that should
6625 * be reserved for this function.
6627 uint16_t num_hw_ring_grps;
6628 /* The default MAC address for the function being configured. */
6629 uint8_t dflt_mac_addr[6];
6631 * The default VLAN for the function being configured.
6632 * This field's format is same as 802.1Q Tag's
6633 * Tag Control Information (TCI) format that includes both
6634 * Priority Code Point (PCP) and VLAN Identifier (VID).
6638 * The default IP address for the function being configured.
6639 * This address is only used in enabling source property check.
6641 uint32_t dflt_ip_addr[4];
6643 * Minimum BW allocated for this function.
6644 * The HWRM will translate this value into byte counter and
6645 * time interval used for the scheduler inside the device.
6648 /* The bandwidth value. */
6649 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
6651 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
6652 /* The granularity of the value (bits or bytes). */
6653 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
6654 UINT32_C(0x10000000)
6655 /* Value is in bits. */
6656 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
6657 (UINT32_C(0x0) << 28)
6658 /* Value is in bytes. */
6659 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
6660 (UINT32_C(0x1) << 28)
6661 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
6662 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
6663 /* bw_value_unit is 3 b */
6664 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
6665 UINT32_C(0xe0000000)
6666 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6667 /* Value is in Mb or MB (base 10). */
6668 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
6669 (UINT32_C(0x0) << 29)
6670 /* Value is in Kb or KB (base 10). */
6671 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
6672 (UINT32_C(0x2) << 29)
6673 /* Value is in bits or bytes. */
6674 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
6675 (UINT32_C(0x4) << 29)
6676 /* Value is in Gb or GB (base 10). */
6677 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
6678 (UINT32_C(0x6) << 29)
6679 /* Value is in 1/100th of a percentage of total bandwidth. */
6680 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
6681 (UINT32_C(0x1) << 29)
6683 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
6684 (UINT32_C(0x7) << 29)
6685 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
6686 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6688 * Maximum BW allocated for this function.
6689 * The HWRM will translate this value into byte counter and
6690 * time interval used for the scheduler inside the device.
6693 /* The bandwidth value. */
6694 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
6696 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
6697 /* The granularity of the value (bits or bytes). */
6698 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
6699 UINT32_C(0x10000000)
6700 /* Value is in bits. */
6701 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
6702 (UINT32_C(0x0) << 28)
6703 /* Value is in bytes. */
6704 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
6705 (UINT32_C(0x1) << 28)
6706 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
6707 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
6708 /* bw_value_unit is 3 b */
6709 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
6710 UINT32_C(0xe0000000)
6711 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6712 /* Value is in Mb or MB (base 10). */
6713 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
6714 (UINT32_C(0x0) << 29)
6715 /* Value is in Kb or KB (base 10). */
6716 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
6717 (UINT32_C(0x2) << 29)
6718 /* Value is in bits or bytes. */
6719 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
6720 (UINT32_C(0x4) << 29)
6721 /* Value is in Gb or GB (base 10). */
6722 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
6723 (UINT32_C(0x6) << 29)
6724 /* Value is in 1/100th of a percentage of total bandwidth. */
6725 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
6726 (UINT32_C(0x1) << 29)
6728 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
6729 (UINT32_C(0x7) << 29)
6730 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
6731 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6733 * ID of the target completion ring for receiving asynchronous
6734 * event completions. If this field is not valid, then the
6735 * HWRM shall use the default completion ring of the function
6736 * that is being configured as the target completion ring for
6737 * providing any asynchronous event completions for that
6739 * If this field is valid, then the HWRM shall use the
6740 * completion ring identified by this ID as the target
6741 * completion ring for providing any asynchronous event
6742 * completions for the function that is being configured.
6744 uint16_t async_event_cr;
6745 /* VLAN Anti-spoofing mode. */
6746 uint8_t vlan_antispoof_mode;
6747 /* No VLAN anti-spoofing checks are enabled */
6748 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
6750 /* Validate VLAN against the configured VLAN(s) */
6751 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
6753 /* Insert VLAN if it does not exist, otherwise discard */
6754 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
6756 /* Insert VLAN if it does not exist, override VLAN if it exists */
6757 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
6759 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
6760 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
6762 * This bit field defines VLAN PRIs that are allowed on
6764 * If nth bit is set, then VLAN PRI n is allowed on this
6767 uint8_t allowed_vlan_pris;
6769 * The HWRM shall allow a PF driver to change EVB mode for the
6770 * partition it belongs to.
6771 * The HWRM shall not allow a VF driver to change the EVB mode.
6772 * The HWRM shall take into account the switching of EVB mode
6773 * from one to another and reconfigure hardware resources as
6775 * The switching from VEB to VEPA mode requires
6776 * the disabling of the loopback traffic. Additionally,
6777 * source knock outs are handled differently in VEB and VEPA
6781 /* No Edge Virtual Bridging (EVB) */
6782 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6783 /* Virtual Ethernet Bridge (VEB) */
6784 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
6785 /* Virtual Ethernet Port Aggregator (VEPA) */
6786 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
6787 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
6788 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
6791 * This value indicates the PCIE device cache line size.
6792 * The cache line size allows the DMA writes to terminate and
6793 * start at the cache boundary.
6795 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
6797 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
6798 /* Cache Line Size 64 bytes */
6799 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
6801 /* Cache Line Size 128 bytes */
6802 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
6804 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
6805 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
6806 /* This value is the virtual link admin state setting. */
6807 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
6809 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
6810 /* Admin state is forced down. */
6811 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
6812 (UINT32_C(0x0) << 2)
6813 /* Admin state is forced up. */
6814 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
6815 (UINT32_C(0x1) << 2)
6816 /* Admin state is in auto mode - is to follow the physical link state. */
6817 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
6818 (UINT32_C(0x2) << 2)
6819 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
6820 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
6821 /* Reserved for future. */
6822 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
6824 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
6826 * The number of multicast filters that should
6827 * be reserved for this function on the RX side.
6829 uint16_t num_mcast_filters;
6830 } __attribute__((packed));
6832 /* hwrm_func_cfg_output (size:128b/16B) */
6833 struct hwrm_func_cfg_output {
6834 /* The specific error status for the command. */
6835 uint16_t error_code;
6836 /* The HWRM command request type. */
6838 /* The sequence ID from the original command. */
6840 /* The length of the response data in number of bytes. */
6842 uint8_t unused_0[7];
6844 * This field is used in Output records to indicate that the output
6845 * is completely written to RAM. This field should be read as '1'
6846 * to indicate that the output has been completely written.
6847 * When writing a command completion or response to an internal processor,
6848 * the order of writes has to be such that this field is written last.
6851 } __attribute__((packed));
6853 /********************
6854 * hwrm_func_qstats *
6855 ********************/
6858 /* hwrm_func_qstats_input (size:192b/24B) */
6859 struct hwrm_func_qstats_input {
6860 /* The HWRM command request type. */
6863 * The completion ring to send the completion event on. This should
6864 * be the NQ ID returned from the `nq_alloc` HWRM command.
6868 * The sequence ID is used by the driver for tracking multiple
6869 * commands. This ID is treated as opaque data by the firmware and
6870 * the value is returned in the `hwrm_resp_hdr` upon completion.
6874 * The target ID of the command:
6875 * * 0x0-0xFFF8 - The function ID
6876 * * 0xFFF8-0xFFFE - Reserved for internal processors
6881 * A physical address pointer pointing to a host buffer that the
6882 * command's response data will be written. This can be either a host
6883 * physical address (HPA) or a guest physical address (GPA) and must
6884 * point to a physically contiguous block of memory.
6888 * Function ID of the function that is being queried.
6889 * 0xFF... (All Fs) if the query is for the requesting
6893 uint8_t unused_0[6];
6894 } __attribute__((packed));
6896 /* hwrm_func_qstats_output (size:1408b/176B) */
6897 struct hwrm_func_qstats_output {
6898 /* The specific error status for the command. */
6899 uint16_t error_code;
6900 /* The HWRM command request type. */
6902 /* The sequence ID from the original command. */
6904 /* The length of the response data in number of bytes. */
6906 /* Number of transmitted unicast packets on the function. */
6907 uint64_t tx_ucast_pkts;
6908 /* Number of transmitted multicast packets on the function. */
6909 uint64_t tx_mcast_pkts;
6910 /* Number of transmitted broadcast packets on the function. */
6911 uint64_t tx_bcast_pkts;
6913 * Number of transmitted packets that were discarded due to
6914 * internal NIC resource problems. For transmit, this
6915 * can only happen if TMP is configured to allow dropping
6916 * in HOL blocking conditions, which is not a normal
6919 uint64_t tx_discard_pkts;
6921 * Number of dropped packets on transmit path on the function.
6922 * These are packets that have been marked for drop by
6923 * the TE CFA block or are packets that exceeded the
6924 * transmit MTU limit for the function.
6926 uint64_t tx_drop_pkts;
6927 /* Number of transmitted bytes for unicast traffic on the function. */
6928 uint64_t tx_ucast_bytes;
6929 /* Number of transmitted bytes for multicast traffic on the function. */
6930 uint64_t tx_mcast_bytes;
6931 /* Number of transmitted bytes for broadcast traffic on the function. */
6932 uint64_t tx_bcast_bytes;
6933 /* Number of received unicast packets on the function. */
6934 uint64_t rx_ucast_pkts;
6935 /* Number of received multicast packets on the function. */
6936 uint64_t rx_mcast_pkts;
6937 /* Number of received broadcast packets on the function. */
6938 uint64_t rx_bcast_pkts;
6940 * Number of received packets that were discarded on the function
6941 * due to resource limitations. This can happen for 3 reasons.
6942 * # The BD used for the packet has a bad format.
6943 * # There were no BDs available in the ring for the packet.
6944 * # There were no BDs available on-chip for the packet.
6946 uint64_t rx_discard_pkts;
6948 * Number of dropped packets on received path on the function.
6949 * These are packets that have been marked for drop by the
6952 uint64_t rx_drop_pkts;
6953 /* Number of received bytes for unicast traffic on the function. */
6954 uint64_t rx_ucast_bytes;
6955 /* Number of received bytes for multicast traffic on the function. */
6956 uint64_t rx_mcast_bytes;
6957 /* Number of received bytes for broadcast traffic on the function. */
6958 uint64_t rx_bcast_bytes;
6959 /* Number of aggregated unicast packets on the function. */
6960 uint64_t rx_agg_pkts;
6961 /* Number of aggregated unicast bytes on the function. */
6962 uint64_t rx_agg_bytes;
6963 /* Number of aggregation events on the function. */
6964 uint64_t rx_agg_events;
6965 /* Number of aborted aggregations on the function. */
6966 uint64_t rx_agg_aborts;
6967 uint8_t unused_0[7];
6969 * This field is used in Output records to indicate that the output
6970 * is completely written to RAM. This field should be read as '1'
6971 * to indicate that the output has been completely written.
6972 * When writing a command completion or response to an internal processor,
6973 * the order of writes has to be such that this field is written last.
6976 } __attribute__((packed));
6978 /***********************
6979 * hwrm_func_clr_stats *
6980 ***********************/
6983 /* hwrm_func_clr_stats_input (size:192b/24B) */
6984 struct hwrm_func_clr_stats_input {
6985 /* The HWRM command request type. */
6988 * The completion ring to send the completion event on. This should
6989 * be the NQ ID returned from the `nq_alloc` HWRM command.
6993 * The sequence ID is used by the driver for tracking multiple
6994 * commands. This ID is treated as opaque data by the firmware and
6995 * the value is returned in the `hwrm_resp_hdr` upon completion.
6999 * The target ID of the command:
7000 * * 0x0-0xFFF8 - The function ID
7001 * * 0xFFF8-0xFFFE - Reserved for internal processors
7006 * A physical address pointer pointing to a host buffer that the
7007 * command's response data will be written. This can be either a host
7008 * physical address (HPA) or a guest physical address (GPA) and must
7009 * point to a physically contiguous block of memory.
7013 * Function ID of the function.
7014 * 0xFF... (All Fs) if the query is for the requesting
7018 uint8_t unused_0[6];
7019 } __attribute__((packed));
7021 /* hwrm_func_clr_stats_output (size:128b/16B) */
7022 struct hwrm_func_clr_stats_output {
7023 /* The specific error status for the command. */
7024 uint16_t error_code;
7025 /* The HWRM command request type. */
7027 /* The sequence ID from the original command. */
7029 /* The length of the response data in number of bytes. */
7031 uint8_t unused_0[7];
7033 * This field is used in Output records to indicate that the output
7034 * is completely written to RAM. This field should be read as '1'
7035 * to indicate that the output has been completely written.
7036 * When writing a command completion or response to an internal processor,
7037 * the order of writes has to be such that this field is written last.
7040 } __attribute__((packed));
7042 /**************************
7043 * hwrm_func_vf_resc_free *
7044 **************************/
7047 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
7048 struct hwrm_func_vf_resc_free_input {
7049 /* The HWRM command request type. */
7052 * The completion ring to send the completion event on. This should
7053 * be the NQ ID returned from the `nq_alloc` HWRM command.
7057 * The sequence ID is used by the driver for tracking multiple
7058 * commands. This ID is treated as opaque data by the firmware and
7059 * the value is returned in the `hwrm_resp_hdr` upon completion.
7063 * The target ID of the command:
7064 * * 0x0-0xFFF8 - The function ID
7065 * * 0xFFF8-0xFFFE - Reserved for internal processors
7070 * A physical address pointer pointing to a host buffer that the
7071 * command's response data will be written. This can be either a host
7072 * physical address (HPA) or a guest physical address (GPA) and must
7073 * point to a physically contiguous block of memory.
7077 * This value is used to identify a Virtual Function (VF).
7078 * The scope of VF ID is local within a PF.
7081 uint8_t unused_0[6];
7082 } __attribute__((packed));
7084 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
7085 struct hwrm_func_vf_resc_free_output {
7086 /* The specific error status for the command. */
7087 uint16_t error_code;
7088 /* The HWRM command request type. */
7090 /* The sequence ID from the original command. */
7092 /* The length of the response data in number of bytes. */
7094 uint8_t unused_0[7];
7096 * This field is used in Output records to indicate that the output
7097 * is completely written to RAM. This field should be read as '1'
7098 * to indicate that the output has been completely written.
7099 * When writing a command completion or response to an internal processor,
7100 * the order of writes has to be such that this field is written last.
7103 } __attribute__((packed));
7105 /**********************
7106 * hwrm_func_drv_rgtr *
7107 **********************/
7110 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
7111 struct hwrm_func_drv_rgtr_input {
7112 /* The HWRM command request type. */
7115 * The completion ring to send the completion event on. This should
7116 * be the NQ ID returned from the `nq_alloc` HWRM command.
7120 * The sequence ID is used by the driver for tracking multiple
7121 * commands. This ID is treated as opaque data by the firmware and
7122 * the value is returned in the `hwrm_resp_hdr` upon completion.
7126 * The target ID of the command:
7127 * * 0x0-0xFFF8 - The function ID
7128 * * 0xFFF8-0xFFFE - Reserved for internal processors
7133 * A physical address pointer pointing to a host buffer that the
7134 * command's response data will be written. This can be either a host
7135 * physical address (HPA) or a guest physical address (GPA) and must
7136 * point to a physically contiguous block of memory.
7141 * When this bit is '1', the function driver is requesting
7142 * all requests from its children VF drivers to be
7143 * forwarded to itself.
7144 * This flag can only be set by the PF driver.
7145 * If a VF driver sets this flag, it should be ignored
7148 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
7151 * When this bit is '1', the function is requesting none of
7152 * the requests from its children VF drivers to be
7153 * forwarded to itself.
7154 * This flag can only be set by the PF driver.
7155 * If a VF driver sets this flag, it should be ignored
7158 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
7161 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
7162 * fields shall be ignored and ver_maj, ver_min, ver_upd
7163 * and ver_patch shall be used for the driver version information.
7164 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
7165 * fields shall be used for the driver version information and
7166 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
7168 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
7171 * When this bit is '1', the function is indicating support of
7172 * 64bit flow handle. The firmware that only supports 64bit flow
7173 * handle should check this bit before allowing processing of
7174 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
7175 * with 64bit flow handle support can only be compatible with drivers
7176 * that support 64bit flow handle. The legacy drivers that don't support
7177 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
7178 * running with new firmware that only supports 64bit flow handle. The new
7179 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
7180 * status to the legacy driver when encounters these commands.
7182 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
7186 * This bit must be '1' for the os_type field to be
7189 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
7192 * This bit must be '1' for the ver field to be
7195 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
7198 * This bit must be '1' for the timestamp field to be
7201 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
7204 * This bit must be '1' for the vf_req_fwd field to be
7207 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
7210 * This bit must be '1' for the async_event_fwd field to be
7213 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
7215 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7218 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7219 /* Other OS not listed below. */
7220 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
7222 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7224 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7226 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7228 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
7230 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7231 /* VMware ESXi OS. */
7232 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
7233 /* Microsoft Windows 8 64-bit OS. */
7234 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7235 /* Microsoft Windows Server 2012 R2 OS. */
7236 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7238 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7239 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
7240 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
7241 /* This is the 8bit major version of the driver. */
7243 /* This is the 8bit minor version of the driver. */
7245 /* This is the 8bit update version of the driver. */
7247 uint8_t unused_0[3];
7249 * This is a 32-bit timestamp provided by the driver for
7251 * The timestamp is in multiples of 1ms.
7254 uint8_t unused_1[4];
7256 * This is a 256-bit bit mask provided by the PF driver for
7257 * letting the HWRM know what commands issued by the VF driver
7258 * to the HWRM should be forwarded to the PF driver.
7259 * Nth bit refers to the Nth req_type.
7261 * Setting Nth bit to 1 indicates that requests from the
7262 * VF driver with req_type equal to N shall be forwarded to
7263 * the parent PF driver.
7265 * This field is not valid for the VF driver.
7267 uint32_t vf_req_fwd[8];
7269 * This is a 256-bit bit mask provided by the function driver
7270 * (PF or VF driver) to indicate the list of asynchronous event
7271 * completions to be forwarded.
7273 * Nth bit refers to the Nth event_id.
7275 * Setting Nth bit to 1 by the function driver shall result in
7276 * the HWRM forwarding asynchronous event completion with
7277 * event_id equal to N.
7279 * If all bits are set to 0 (value of 0), then the HWRM shall
7280 * not forward any asynchronous event completion to this
7283 uint32_t async_event_fwd[8];
7284 /* This is the 16bit major version of the driver. */
7286 /* This is the 16bit minor version of the driver. */
7288 /* This is the 16bit update version of the driver. */
7290 /* This is the 16bit patch version of the driver. */
7292 } __attribute__((packed));
7294 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
7295 struct hwrm_func_drv_rgtr_output {
7296 /* The specific error status for the command. */
7297 uint16_t error_code;
7298 /* The HWRM command request type. */
7300 /* The sequence ID from the original command. */
7302 /* The length of the response data in number of bytes. */
7306 * When this bit is '1', it indicates that the
7307 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
7309 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
7311 uint8_t unused_0[3];
7313 * This field is used in Output records to indicate that the output
7314 * is completely written to RAM. This field should be read as '1'
7315 * to indicate that the output has been completely written.
7316 * When writing a command completion or response to an internal processor,
7317 * the order of writes has to be such that this field is written last.
7320 } __attribute__((packed));
7322 /************************
7323 * hwrm_func_drv_unrgtr *
7324 ************************/
7327 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
7328 struct hwrm_func_drv_unrgtr_input {
7329 /* The HWRM command request type. */
7332 * The completion ring to send the completion event on. This should
7333 * be the NQ ID returned from the `nq_alloc` HWRM command.
7337 * The sequence ID is used by the driver for tracking multiple
7338 * commands. This ID is treated as opaque data by the firmware and
7339 * the value is returned in the `hwrm_resp_hdr` upon completion.
7343 * The target ID of the command:
7344 * * 0x0-0xFFF8 - The function ID
7345 * * 0xFFF8-0xFFFE - Reserved for internal processors
7350 * A physical address pointer pointing to a host buffer that the
7351 * command's response data will be written. This can be either a host
7352 * physical address (HPA) or a guest physical address (GPA) and must
7353 * point to a physically contiguous block of memory.
7358 * When this bit is '1', the function driver is notifying
7359 * the HWRM to prepare for the shutdown.
7361 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
7363 uint8_t unused_0[4];
7364 } __attribute__((packed));
7366 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
7367 struct hwrm_func_drv_unrgtr_output {
7368 /* The specific error status for the command. */
7369 uint16_t error_code;
7370 /* The HWRM command request type. */
7372 /* The sequence ID from the original command. */
7374 /* The length of the response data in number of bytes. */
7376 uint8_t unused_0[7];
7378 * This field is used in Output records to indicate that the output
7379 * is completely written to RAM. This field should be read as '1'
7380 * to indicate that the output has been completely written.
7381 * When writing a command completion or response to an internal processor,
7382 * the order of writes has to be such that this field is written last.
7385 } __attribute__((packed));
7387 /**********************
7388 * hwrm_func_buf_rgtr *
7389 **********************/
7392 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
7393 struct hwrm_func_buf_rgtr_input {
7394 /* The HWRM command request type. */
7397 * The completion ring to send the completion event on. This should
7398 * be the NQ ID returned from the `nq_alloc` HWRM command.
7402 * The sequence ID is used by the driver for tracking multiple
7403 * commands. This ID is treated as opaque data by the firmware and
7404 * the value is returned in the `hwrm_resp_hdr` upon completion.
7408 * The target ID of the command:
7409 * * 0x0-0xFFF8 - The function ID
7410 * * 0xFFF8-0xFFFE - Reserved for internal processors
7415 * A physical address pointer pointing to a host buffer that the
7416 * command's response data will be written. This can be either a host
7417 * physical address (HPA) or a guest physical address (GPA) and must
7418 * point to a physically contiguous block of memory.
7423 * This bit must be '1' for the vf_id field to be
7426 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7428 * This bit must be '1' for the err_buf_addr field to be
7431 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
7433 * This value is used to identify a Virtual Function (VF).
7434 * The scope of VF ID is local within a PF.
7438 * This field represents the number of pages used for request
7441 uint16_t req_buf_num_pages;
7443 * This field represents the page size used for request
7446 uint16_t req_buf_page_size;
7448 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
7450 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
7452 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
7454 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
7456 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
7458 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
7460 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
7461 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
7462 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
7463 /* The length of the request buffer per VF in bytes. */
7464 uint16_t req_buf_len;
7465 /* The length of the response buffer in bytes. */
7466 uint16_t resp_buf_len;
7467 uint8_t unused_0[2];
7468 /* This field represents the page address of page #0. */
7469 uint64_t req_buf_page_addr0;
7470 /* This field represents the page address of page #1. */
7471 uint64_t req_buf_page_addr1;
7472 /* This field represents the page address of page #2. */
7473 uint64_t req_buf_page_addr2;
7474 /* This field represents the page address of page #3. */
7475 uint64_t req_buf_page_addr3;
7476 /* This field represents the page address of page #4. */
7477 uint64_t req_buf_page_addr4;
7478 /* This field represents the page address of page #5. */
7479 uint64_t req_buf_page_addr5;
7480 /* This field represents the page address of page #6. */
7481 uint64_t req_buf_page_addr6;
7482 /* This field represents the page address of page #7. */
7483 uint64_t req_buf_page_addr7;
7484 /* This field represents the page address of page #8. */
7485 uint64_t req_buf_page_addr8;
7486 /* This field represents the page address of page #9. */
7487 uint64_t req_buf_page_addr9;
7489 * This field is used to receive the error reporting from
7490 * the chipset. Only applicable for PFs.
7492 uint64_t error_buf_addr;
7494 * This field is used to receive the response forwarded by the
7497 uint64_t resp_buf_addr;
7498 } __attribute__((packed));
7500 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
7501 struct hwrm_func_buf_rgtr_output {
7502 /* The specific error status for the command. */
7503 uint16_t error_code;
7504 /* The HWRM command request type. */
7506 /* The sequence ID from the original command. */
7508 /* The length of the response data in number of bytes. */
7510 uint8_t unused_0[7];
7512 * This field is used in Output records to indicate that the output
7513 * is completely written to RAM. This field should be read as '1'
7514 * to indicate that the output has been completely written.
7515 * When writing a command completion or response to an internal processor,
7516 * the order of writes has to be such that this field is written last.
7519 } __attribute__((packed));
7521 /************************
7522 * hwrm_func_buf_unrgtr *
7523 ************************/
7526 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
7527 struct hwrm_func_buf_unrgtr_input {
7528 /* The HWRM command request type. */
7531 * The completion ring to send the completion event on. This should
7532 * be the NQ ID returned from the `nq_alloc` HWRM command.
7536 * The sequence ID is used by the driver for tracking multiple
7537 * commands. This ID is treated as opaque data by the firmware and
7538 * the value is returned in the `hwrm_resp_hdr` upon completion.
7542 * The target ID of the command:
7543 * * 0x0-0xFFF8 - The function ID
7544 * * 0xFFF8-0xFFFE - Reserved for internal processors
7549 * A physical address pointer pointing to a host buffer that the
7550 * command's response data will be written. This can be either a host
7551 * physical address (HPA) or a guest physical address (GPA) and must
7552 * point to a physically contiguous block of memory.
7557 * This bit must be '1' for the vf_id field to be
7560 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7562 * This value is used to identify a Virtual Function (VF).
7563 * The scope of VF ID is local within a PF.
7566 uint8_t unused_0[2];
7567 } __attribute__((packed));
7569 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
7570 struct hwrm_func_buf_unrgtr_output {
7571 /* The specific error status for the command. */
7572 uint16_t error_code;
7573 /* The HWRM command request type. */
7575 /* The sequence ID from the original command. */
7577 /* The length of the response data in number of bytes. */
7579 uint8_t unused_0[7];
7581 * This field is used in Output records to indicate that the output
7582 * is completely written to RAM. This field should be read as '1'
7583 * to indicate that the output has been completely written.
7584 * When writing a command completion or response to an internal processor,
7585 * the order of writes has to be such that this field is written last.
7588 } __attribute__((packed));
7590 /**********************
7591 * hwrm_func_drv_qver *
7592 **********************/
7595 /* hwrm_func_drv_qver_input (size:192b/24B) */
7596 struct hwrm_func_drv_qver_input {
7597 /* The HWRM command request type. */
7600 * The completion ring to send the completion event on. This should
7601 * be the NQ ID returned from the `nq_alloc` HWRM command.
7605 * The sequence ID is used by the driver for tracking multiple
7606 * commands. This ID is treated as opaque data by the firmware and
7607 * the value is returned in the `hwrm_resp_hdr` upon completion.
7611 * The target ID of the command:
7612 * * 0x0-0xFFF8 - The function ID
7613 * * 0xFFF8-0xFFFE - Reserved for internal processors
7618 * A physical address pointer pointing to a host buffer that the
7619 * command's response data will be written. This can be either a host
7620 * physical address (HPA) or a guest physical address (GPA) and must
7621 * point to a physically contiguous block of memory.
7624 /* Reserved for future use. */
7627 * Function ID of the function that is being queried.
7628 * 0xFF... (All Fs) if the query is for the requesting
7632 uint8_t unused_0[2];
7633 } __attribute__((packed));
7635 /* hwrm_func_drv_qver_output (size:256b/32B) */
7636 struct hwrm_func_drv_qver_output {
7637 /* The specific error status for the command. */
7638 uint16_t error_code;
7639 /* The HWRM command request type. */
7641 /* The sequence ID from the original command. */
7643 /* The length of the response data in number of bytes. */
7645 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7648 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7649 /* Other OS not listed below. */
7650 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
7652 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7654 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7656 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7658 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
7660 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7661 /* VMware ESXi OS. */
7662 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
7663 /* Microsoft Windows 8 64-bit OS. */
7664 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7665 /* Microsoft Windows Server 2012 R2 OS. */
7666 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7668 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7669 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
7670 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
7671 /* This is the 8bit major version of the driver. */
7673 /* This is the 8bit minor version of the driver. */
7675 /* This is the 8bit update version of the driver. */
7677 uint8_t unused_0[3];
7678 /* This is the 16bit major version of the driver. */
7680 /* This is the 16bit minor version of the driver. */
7682 /* This is the 16bit update version of the driver. */
7684 /* This is the 16bit patch version of the driver. */
7686 uint8_t unused_1[7];
7688 * This field is used in Output records to indicate that the output
7689 * is completely written to RAM. This field should be read as '1'
7690 * to indicate that the output has been completely written.
7691 * When writing a command completion or response to an internal processor,
7692 * the order of writes has to be such that this field is written last.
7695 } __attribute__((packed));
7697 /****************************
7698 * hwrm_func_resource_qcaps *
7699 ****************************/
7702 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
7703 struct hwrm_func_resource_qcaps_input {
7704 /* The HWRM command request type. */
7707 * The completion ring to send the completion event on. This should
7708 * be the NQ ID returned from the `nq_alloc` HWRM command.
7712 * The sequence ID is used by the driver for tracking multiple
7713 * commands. This ID is treated as opaque data by the firmware and
7714 * the value is returned in the `hwrm_resp_hdr` upon completion.
7718 * The target ID of the command:
7719 * * 0x0-0xFFF8 - The function ID
7720 * * 0xFFF8-0xFFFE - Reserved for internal processors
7725 * A physical address pointer pointing to a host buffer that the
7726 * command's response data will be written. This can be either a host
7727 * physical address (HPA) or a guest physical address (GPA) and must
7728 * point to a physically contiguous block of memory.
7732 * Function ID of the function that is being queried.
7733 * 0xFF... (All Fs) if the query is for the requesting
7737 uint8_t unused_0[6];
7738 } __attribute__((packed));
7740 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
7741 struct hwrm_func_resource_qcaps_output {
7742 /* The specific error status for the command. */
7743 uint16_t error_code;
7744 /* The HWRM command request type. */
7746 /* The sequence ID from the original command. */
7748 /* The length of the response data in number of bytes. */
7750 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
7752 /* Maximum guaranteed number of MSI-X vectors supported by function */
7754 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
7755 uint16_t vf_reservation_strategy;
7756 /* The PF driver should evenly divide its remaining resources among all VFs. */
7757 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
7759 /* The PF driver should only reserve minimal resources for each VF. */
7760 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
7763 * The PF driver should not reserve any resources for each VF until the
7764 * the VF interface is brought up.
7766 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
7768 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
7769 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
7770 /* Minimum guaranteed number of RSS/COS contexts */
7771 uint16_t min_rsscos_ctx;
7772 /* Maximum non-guaranteed number of RSS/COS contexts */
7773 uint16_t max_rsscos_ctx;
7774 /* Minimum guaranteed number of completion rings */
7775 uint16_t min_cmpl_rings;
7776 /* Maximum non-guaranteed number of completion rings */
7777 uint16_t max_cmpl_rings;
7778 /* Minimum guaranteed number of transmit rings */
7779 uint16_t min_tx_rings;
7780 /* Maximum non-guaranteed number of transmit rings */
7781 uint16_t max_tx_rings;
7782 /* Minimum guaranteed number of receive rings */
7783 uint16_t min_rx_rings;
7784 /* Maximum non-guaranteed number of receive rings */
7785 uint16_t max_rx_rings;
7786 /* Minimum guaranteed number of L2 contexts */
7787 uint16_t min_l2_ctxs;
7788 /* Maximum non-guaranteed number of L2 contexts */
7789 uint16_t max_l2_ctxs;
7790 /* Minimum guaranteed number of VNICs */
7792 /* Maximum non-guaranteed number of VNICs */
7794 /* Minimum guaranteed number of statistic contexts */
7795 uint16_t min_stat_ctx;
7796 /* Maximum non-guaranteed number of statistic contexts */
7797 uint16_t max_stat_ctx;
7798 /* Minimum guaranteed number of ring groups */
7799 uint16_t min_hw_ring_grps;
7800 /* Maximum non-guaranteed number of ring groups */
7801 uint16_t max_hw_ring_grps;
7803 * Maximum number of inputs into the transmit scheduler for this function.
7804 * The number of TX rings assigned to the function cannot exceed this value.
7806 uint16_t max_tx_scheduler_inputs;
7809 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
7810 * feature to reserve all minimum resources when minimum >= 1, otherwise
7813 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
7815 uint8_t unused_0[5];
7817 * This field is used in Output records to indicate that the output
7818 * is completely written to RAM. This field should be read as '1'
7819 * to indicate that the output has been completely written.
7820 * When writing a command completion or response to an internal processor,
7821 * the order of writes has to be such that this field is written last.
7824 } __attribute__((packed));
7826 /*********************************
7827 * hwrm_func_backing_store_qcaps *
7828 *********************************/
7831 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
7832 struct hwrm_func_backing_store_qcaps_input {
7833 /* The HWRM command request type. */
7836 * The completion ring to send the completion event on. This should
7837 * be the NQ ID returned from the `nq_alloc` HWRM command.
7841 * The sequence ID is used by the driver for tracking multiple
7842 * commands. This ID is treated as opaque data by the firmware and
7843 * the value is returned in the `hwrm_resp_hdr` upon completion.
7847 * The target ID of the command:
7848 * * 0x0-0xFFF8 - The function ID
7849 * * 0xFFF8-0xFFFE - Reserved for internal processors
7854 * A physical address pointer pointing to a host buffer that the
7855 * command's response data will be written. This can be either a host
7856 * physical address (HPA) or a guest physical address (GPA) and must
7857 * point to a physically contiguous block of memory.
7860 } __attribute__((packed));
7862 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */
7863 struct hwrm_func_backing_store_qcaps_output {
7864 /* The specific error status for the command. */
7865 uint16_t error_code;
7866 /* The HWRM command request type. */
7868 /* The sequence ID from the original command. */
7870 /* The length of the response data in number of bytes. */
7872 /* Maximum number of QP context entries supported for this function. */
7873 uint32_t qp_max_entries;
7875 * Minimum number of QP context entries that are needed to be reserved
7876 * for QP1 for the PF and its VFs. PF drivers must allocate at least
7877 * this many QP context entries, even if RoCE will not be used.
7879 uint16_t qp_min_qp1_entries;
7880 /* Maximum number of QP context entries that can be used for L2. */
7881 uint16_t qp_max_l2_entries;
7882 /* Number of bytes that must be allocated for each context entry. */
7883 uint16_t qp_entry_size;
7884 /* Maximum number of SRQ context entries that can be used for L2. */
7885 uint16_t srq_max_l2_entries;
7886 /* Maximum number of SRQ context entries supported for this function. */
7887 uint32_t srq_max_entries;
7888 /* Number of bytes that must be allocated for each context entry. */
7889 uint16_t srq_entry_size;
7890 /* Maximum number of CQ context entries that can be used for L2. */
7891 uint16_t cq_max_l2_entries;
7892 /* Maximum number of CQ context entries supported for this function. */
7893 uint32_t cq_max_entries;
7894 /* Number of bytes that must be allocated for each context entry. */
7895 uint16_t cq_entry_size;
7896 /* Maximum number of VNIC context entries supported for this function. */
7897 uint16_t vnic_max_vnic_entries;
7898 /* Maximum number of Ring table context entries supported for this function. */
7899 uint16_t vnic_max_ring_table_entries;
7900 /* Number of bytes that must be allocated for each context entry. */
7901 uint16_t vnic_entry_size;
7902 /* Maximum number of statistic context entries supported for this function. */
7903 uint32_t stat_max_entries;
7904 /* Number of bytes that must be allocated for each context entry. */
7905 uint16_t stat_entry_size;
7906 /* Number of bytes that must be allocated for each context entry. */
7907 uint16_t tqm_entry_size;
7908 /* Minimum number of TQM context entries required per ring. */
7909 uint32_t tqm_min_entries_per_ring;
7911 * Maximum number of TQM context entries supported per ring. This is
7912 * actually a recommended TQM queue size based on worst case usage of
7915 * TQM fastpath rings should be sized large enough to accommodate the
7916 * maximum number of QPs (either L2 or RoCE, or both if shared)
7917 * that can be enqueued to the TQM ring.
7919 * TQM slowpath rings should be sized as follows:
7921 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
7924 * num_vnics is the number of VNICs allocated in the VNIC backing store
7925 * num_l2_tx_rings is the number of L2 rings in the QP backing store
7926 * num_roce_qps is the number of RoCE QPs in the QP backing store
7927 * tqm_min_size is tqm_min_entries_per_ring reported by
7928 * HWRM_FUNC_BACKING_STORE_QCAPS
7930 * Note that TQM ring sizes cannot be extended while the system is
7931 * operational. If a PF driver needs to extend a TQM ring, it needs
7932 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
7933 * the backing store.
7935 uint32_t tqm_max_entries_per_ring;
7936 /* Maximum number of MR/AV context entries supported for this function. */
7937 uint32_t mrav_max_entries;
7938 /* Number of bytes that must be allocated for each context entry. */
7939 uint16_t mrav_entry_size;
7940 /* Number of bytes that must be allocated for each context entry. */
7941 uint16_t tim_entry_size;
7942 /* Maximum number of Timer context entries supported for this function. */
7943 uint32_t tim_max_entries;
7944 uint8_t unused_0[2];
7946 * The number of entries specified for any TQM ring must be a
7947 * multiple of this value to prevent any resource allocation
7950 uint8_t tqm_entries_multiple;
7952 * This field is used in Output records to indicate that the output
7953 * is completely written to RAM. This field should be read as '1'
7954 * to indicate that the output has been completely written.
7955 * When writing a command completion or response to an internal processor,
7956 * the order of writes has to be such that this field is written last.
7959 } __attribute__((packed));
7961 /*******************************
7962 * hwrm_func_backing_store_cfg *
7963 *******************************/
7966 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
7967 struct hwrm_func_backing_store_cfg_input {
7968 /* The HWRM command request type. */
7971 * The completion ring to send the completion event on. This should
7972 * be the NQ ID returned from the `nq_alloc` HWRM command.
7976 * The sequence ID is used by the driver for tracking multiple
7977 * commands. This ID is treated as opaque data by the firmware and
7978 * the value is returned in the `hwrm_resp_hdr` upon completion.
7982 * The target ID of the command:
7983 * * 0x0-0xFFF8 - The function ID
7984 * * 0xFFF8-0xFFFE - Reserved for internal processors
7989 * A physical address pointer pointing to a host buffer that the
7990 * command's response data will be written. This can be either a host
7991 * physical address (HPA) or a guest physical address (GPA) and must
7992 * point to a physically contiguous block of memory.
7997 * When set, the firmware only uses on-chip resources and does not
7998 * expect any backing store to be provided by the host driver. This
7999 * mode provides minimal L2 functionality (e.g. limited L2 resources,
8002 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
8006 * This bit must be '1' for the qp fields to be
8009 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
8012 * This bit must be '1' for the srq fields to be
8015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
8018 * This bit must be '1' for the cq fields to be
8021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
8024 * This bit must be '1' for the vnic fields to be
8027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
8030 * This bit must be '1' for the stat fields to be
8033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
8036 * This bit must be '1' for the tqm_sp fields to be
8039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
8042 * This bit must be '1' for the tqm_ring0 fields to be
8045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
8048 * This bit must be '1' for the tqm_ring1 fields to be
8051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
8054 * This bit must be '1' for the tqm_ring2 fields to be
8057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
8060 * This bit must be '1' for the tqm_ring3 fields to be
8063 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
8066 * This bit must be '1' for the tqm_ring4 fields to be
8069 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
8072 * This bit must be '1' for the tqm_ring5 fields to be
8075 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
8078 * This bit must be '1' for the tqm_ring6 fields to be
8081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
8084 * This bit must be '1' for the tqm_ring7 fields to be
8087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
8090 * This bit must be '1' for the mrav fields to be
8093 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
8096 * This bit must be '1' for the tim fields to be
8099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
8101 /* QPC page size and level. */
8102 uint8_t qpc_pg_size_qpc_lvl;
8103 /* QPC PBL indirect levels. */
8104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
8106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
8107 /* PBL pointer is physical start address. */
8108 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
8110 /* PBL pointer points to PTE table. */
8111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
8113 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
8116 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
8117 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
8118 /* QPC page size. */
8119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
8121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
8123 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
8124 (UINT32_C(0x0) << 4)
8126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
8127 (UINT32_C(0x1) << 4)
8129 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
8130 (UINT32_C(0x2) << 4)
8132 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
8133 (UINT32_C(0x3) << 4)
8135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
8136 (UINT32_C(0x4) << 4)
8138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
8139 (UINT32_C(0x5) << 4)
8140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
8141 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
8142 /* SRQ page size and level. */
8143 uint8_t srq_pg_size_srq_lvl;
8144 /* SRQ PBL indirect levels. */
8145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
8147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
8148 /* PBL pointer is physical start address. */
8149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
8151 /* PBL pointer points to PTE table. */
8152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
8154 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
8157 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
8158 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
8159 /* SRQ page size. */
8160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
8162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
8164 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
8165 (UINT32_C(0x0) << 4)
8167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
8168 (UINT32_C(0x1) << 4)
8170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
8171 (UINT32_C(0x2) << 4)
8173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
8174 (UINT32_C(0x3) << 4)
8176 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
8177 (UINT32_C(0x4) << 4)
8179 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
8180 (UINT32_C(0x5) << 4)
8181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
8182 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
8183 /* CQ page size and level. */
8184 uint8_t cq_pg_size_cq_lvl;
8185 /* CQ PBL indirect levels. */
8186 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
8188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
8189 /* PBL pointer is physical start address. */
8190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
8192 /* PBL pointer points to PTE table. */
8193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
8195 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
8198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
8199 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
8201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
8203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
8205 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
8206 (UINT32_C(0x0) << 4)
8208 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
8209 (UINT32_C(0x1) << 4)
8211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
8212 (UINT32_C(0x2) << 4)
8214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
8215 (UINT32_C(0x3) << 4)
8217 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
8218 (UINT32_C(0x4) << 4)
8220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
8221 (UINT32_C(0x5) << 4)
8222 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
8223 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
8224 /* VNIC page size and level. */
8225 uint8_t vnic_pg_size_vnic_lvl;
8226 /* VNIC PBL indirect levels. */
8227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
8229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
8230 /* PBL pointer is physical start address. */
8231 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
8233 /* PBL pointer points to PTE table. */
8234 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
8236 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
8239 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
8240 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
8241 /* VNIC page size. */
8242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
8244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
8246 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
8247 (UINT32_C(0x0) << 4)
8249 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
8250 (UINT32_C(0x1) << 4)
8252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
8253 (UINT32_C(0x2) << 4)
8255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
8256 (UINT32_C(0x3) << 4)
8258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
8259 (UINT32_C(0x4) << 4)
8261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
8262 (UINT32_C(0x5) << 4)
8263 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
8264 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
8265 /* Stat page size and level. */
8266 uint8_t stat_pg_size_stat_lvl;
8267 /* Stat PBL indirect levels. */
8268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
8270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
8271 /* PBL pointer is physical start address. */
8272 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
8274 /* PBL pointer points to PTE table. */
8275 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
8277 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
8280 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
8281 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
8282 /* Stat page size. */
8283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
8285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
8287 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
8288 (UINT32_C(0x0) << 4)
8290 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
8291 (UINT32_C(0x1) << 4)
8293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
8294 (UINT32_C(0x2) << 4)
8296 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
8297 (UINT32_C(0x3) << 4)
8299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
8300 (UINT32_C(0x4) << 4)
8302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
8303 (UINT32_C(0x5) << 4)
8304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
8305 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
8306 /* TQM slow path page size and level. */
8307 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
8308 /* TQM slow path PBL indirect levels. */
8309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
8311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
8312 /* PBL pointer is physical start address. */
8313 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
8315 /* PBL pointer points to PTE table. */
8316 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
8318 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
8321 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
8322 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
8323 /* TQM slow path page size. */
8324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
8326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
8328 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
8329 (UINT32_C(0x0) << 4)
8331 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
8332 (UINT32_C(0x1) << 4)
8334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
8335 (UINT32_C(0x2) << 4)
8337 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
8338 (UINT32_C(0x3) << 4)
8340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
8341 (UINT32_C(0x4) << 4)
8343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
8344 (UINT32_C(0x5) << 4)
8345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
8346 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
8347 /* TQM ring 0 page size and level. */
8348 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
8349 /* TQM ring 0 PBL indirect levels. */
8350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
8352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
8353 /* PBL pointer is physical start address. */
8354 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
8356 /* PBL pointer points to PTE table. */
8357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
8359 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
8362 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
8363 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
8364 /* TQM ring 0 page size. */
8365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
8367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
8369 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
8370 (UINT32_C(0x0) << 4)
8372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
8373 (UINT32_C(0x1) << 4)
8375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
8376 (UINT32_C(0x2) << 4)
8378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
8379 (UINT32_C(0x3) << 4)
8381 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
8382 (UINT32_C(0x4) << 4)
8384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
8385 (UINT32_C(0x5) << 4)
8386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
8387 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
8388 /* TQM ring 1 page size and level. */
8389 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
8390 /* TQM ring 1 PBL indirect levels. */
8391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
8393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
8394 /* PBL pointer is physical start address. */
8395 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
8397 /* PBL pointer points to PTE table. */
8398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
8400 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
8403 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
8404 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
8405 /* TQM ring 1 page size. */
8406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
8408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
8410 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
8411 (UINT32_C(0x0) << 4)
8413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
8414 (UINT32_C(0x1) << 4)
8416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
8417 (UINT32_C(0x2) << 4)
8419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
8420 (UINT32_C(0x3) << 4)
8422 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
8423 (UINT32_C(0x4) << 4)
8425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
8426 (UINT32_C(0x5) << 4)
8427 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
8428 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
8429 /* TQM ring 2 page size and level. */
8430 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
8431 /* TQM ring 2 PBL indirect levels. */
8432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
8434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
8435 /* PBL pointer is physical start address. */
8436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
8438 /* PBL pointer points to PTE table. */
8439 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
8441 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
8444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
8445 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
8446 /* TQM ring 2 page size. */
8447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
8449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
8451 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
8452 (UINT32_C(0x0) << 4)
8454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
8455 (UINT32_C(0x1) << 4)
8457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
8458 (UINT32_C(0x2) << 4)
8460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
8461 (UINT32_C(0x3) << 4)
8463 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
8464 (UINT32_C(0x4) << 4)
8466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
8467 (UINT32_C(0x5) << 4)
8468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
8469 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
8470 /* TQM ring 3 page size and level. */
8471 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
8472 /* TQM ring 3 PBL indirect levels. */
8473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
8475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
8476 /* PBL pointer is physical start address. */
8477 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
8479 /* PBL pointer points to PTE table. */
8480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
8482 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
8485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
8486 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
8487 /* TQM ring 3 page size. */
8488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
8490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
8492 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
8493 (UINT32_C(0x0) << 4)
8495 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
8496 (UINT32_C(0x1) << 4)
8498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
8499 (UINT32_C(0x2) << 4)
8501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
8502 (UINT32_C(0x3) << 4)
8504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
8505 (UINT32_C(0x4) << 4)
8507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
8508 (UINT32_C(0x5) << 4)
8509 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
8510 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
8511 /* TQM ring 4 page size and level. */
8512 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
8513 /* TQM ring 4 PBL indirect levels. */
8514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
8516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
8517 /* PBL pointer is physical start address. */
8518 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
8520 /* PBL pointer points to PTE table. */
8521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
8523 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
8526 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
8527 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
8528 /* TQM ring 4 page size. */
8529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
8531 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
8533 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
8534 (UINT32_C(0x0) << 4)
8536 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
8537 (UINT32_C(0x1) << 4)
8539 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
8540 (UINT32_C(0x2) << 4)
8542 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
8543 (UINT32_C(0x3) << 4)
8545 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
8546 (UINT32_C(0x4) << 4)
8548 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
8549 (UINT32_C(0x5) << 4)
8550 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
8551 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
8552 /* TQM ring 5 page size and level. */
8553 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
8554 /* TQM ring 5 PBL indirect levels. */
8555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
8557 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
8558 /* PBL pointer is physical start address. */
8559 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
8561 /* PBL pointer points to PTE table. */
8562 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
8564 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8565 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
8567 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
8568 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
8569 /* TQM ring 5 page size. */
8570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
8572 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
8574 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
8575 (UINT32_C(0x0) << 4)
8577 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
8578 (UINT32_C(0x1) << 4)
8580 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
8581 (UINT32_C(0x2) << 4)
8583 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
8584 (UINT32_C(0x3) << 4)
8586 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
8587 (UINT32_C(0x4) << 4)
8589 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
8590 (UINT32_C(0x5) << 4)
8591 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
8592 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
8593 /* TQM ring 6 page size and level. */
8594 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
8595 /* TQM ring 6 PBL indirect levels. */
8596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
8598 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
8599 /* PBL pointer is physical start address. */
8600 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
8602 /* PBL pointer points to PTE table. */
8603 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
8605 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8606 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
8608 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
8609 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
8610 /* TQM ring 6 page size. */
8611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
8613 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
8615 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
8616 (UINT32_C(0x0) << 4)
8618 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
8619 (UINT32_C(0x1) << 4)
8621 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
8622 (UINT32_C(0x2) << 4)
8624 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
8625 (UINT32_C(0x3) << 4)
8627 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
8628 (UINT32_C(0x4) << 4)
8630 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
8631 (UINT32_C(0x5) << 4)
8632 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
8633 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
8634 /* TQM ring 7 page size and level. */
8635 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
8636 /* TQM ring 7 PBL indirect levels. */
8637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
8639 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
8640 /* PBL pointer is physical start address. */
8641 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
8643 /* PBL pointer points to PTE table. */
8644 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
8646 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8647 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
8649 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
8650 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
8651 /* TQM ring 7 page size. */
8652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
8654 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
8656 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
8657 (UINT32_C(0x0) << 4)
8659 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
8660 (UINT32_C(0x1) << 4)
8662 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
8663 (UINT32_C(0x2) << 4)
8665 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
8666 (UINT32_C(0x3) << 4)
8668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
8669 (UINT32_C(0x4) << 4)
8671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
8672 (UINT32_C(0x5) << 4)
8673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
8674 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
8675 /* MR/AV page size and level. */
8676 uint8_t mrav_pg_size_mrav_lvl;
8677 /* MR/AV PBL indirect levels. */
8678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
8680 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
8681 /* PBL pointer is physical start address. */
8682 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
8684 /* PBL pointer points to PTE table. */
8685 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
8687 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
8690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
8691 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
8692 /* MR/AV page size. */
8693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
8695 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
8697 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
8698 (UINT32_C(0x0) << 4)
8700 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
8701 (UINT32_C(0x1) << 4)
8703 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
8704 (UINT32_C(0x2) << 4)
8706 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
8707 (UINT32_C(0x3) << 4)
8709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
8710 (UINT32_C(0x4) << 4)
8712 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
8713 (UINT32_C(0x5) << 4)
8714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
8715 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
8716 /* Timer page size and level. */
8717 uint8_t tim_pg_size_tim_lvl;
8718 /* Timer PBL indirect levels. */
8719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
8721 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
8722 /* PBL pointer is physical start address. */
8723 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
8725 /* PBL pointer points to PTE table. */
8726 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
8728 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8729 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
8731 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
8732 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
8733 /* Timer page size. */
8734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
8736 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
8738 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
8739 (UINT32_C(0x0) << 4)
8741 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
8742 (UINT32_C(0x1) << 4)
8744 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
8745 (UINT32_C(0x2) << 4)
8747 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
8748 (UINT32_C(0x3) << 4)
8750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
8751 (UINT32_C(0x4) << 4)
8753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
8754 (UINT32_C(0x5) << 4)
8755 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
8756 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
8757 /* QP page directory. */
8758 uint64_t qpc_page_dir;
8759 /* SRQ page directory. */
8760 uint64_t srq_page_dir;
8761 /* CQ page directory. */
8762 uint64_t cq_page_dir;
8763 /* VNIC page directory. */
8764 uint64_t vnic_page_dir;
8765 /* Stat page directory. */
8766 uint64_t stat_page_dir;
8767 /* TQM slowpath page directory. */
8768 uint64_t tqm_sp_page_dir;
8769 /* TQM ring 0 page directory. */
8770 uint64_t tqm_ring0_page_dir;
8771 /* TQM ring 1 page directory. */
8772 uint64_t tqm_ring1_page_dir;
8773 /* TQM ring 2 page directory. */
8774 uint64_t tqm_ring2_page_dir;
8775 /* TQM ring 3 page directory. */
8776 uint64_t tqm_ring3_page_dir;
8777 /* TQM ring 4 page directory. */
8778 uint64_t tqm_ring4_page_dir;
8779 /* TQM ring 5 page directory. */
8780 uint64_t tqm_ring5_page_dir;
8781 /* TQM ring 6 page directory. */
8782 uint64_t tqm_ring6_page_dir;
8783 /* TQM ring 7 page directory. */
8784 uint64_t tqm_ring7_page_dir;
8785 /* MR/AV page directory. */
8786 uint64_t mrav_page_dir;
8787 /* Timer page directory. */
8788 uint64_t tim_page_dir;
8789 /* Number of QPs. */
8790 uint32_t qp_num_entries;
8791 /* Number of SRQs. */
8792 uint32_t srq_num_entries;
8793 /* Number of CQs. */
8794 uint32_t cq_num_entries;
8795 /* Number of Stats. */
8796 uint32_t stat_num_entries;
8798 * Number of TQM slowpath entries.
8800 * TQM slowpath rings should be sized as follows:
8802 * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size
8805 * num_vnics is the number of VNICs allocated in the VNIC backing store
8806 * num_l2_tx_rings is the number of L2 rings in the QP backing store
8807 * num_roce_qps is the number of RoCE QPs in the QP backing store
8808 * tqm_min_size is tqm_min_entries_per_ring reported by
8809 * HWRM_FUNC_BACKING_STORE_QCAPS
8811 * Note that TQM ring sizes cannot be extended while the system is
8812 * operational. If a PF driver needs to extend a TQM ring, it needs
8813 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8814 * the backing store.
8816 uint32_t tqm_sp_num_entries;
8818 * Number of TQM ring 0 entries.
8820 * TQM fastpath rings should be sized large enough to accommodate the
8821 * maximum number of QPs (either L2 or RoCE, or both if shared)
8822 * that can be enqueued to the TQM ring.
8824 * Note that TQM ring sizes cannot be extended while the system is
8825 * operational. If a PF driver needs to extend a TQM ring, it needs
8826 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8827 * the backing store.
8829 uint32_t tqm_ring0_num_entries;
8831 * Number of TQM ring 1 entries.
8833 * TQM fastpath rings should be sized large enough to accommodate the
8834 * maximum number of QPs (either L2 or RoCE, or both if shared)
8835 * that can be enqueued to the TQM ring.
8837 * Note that TQM ring sizes cannot be extended while the system is
8838 * operational. If a PF driver needs to extend a TQM ring, it needs
8839 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8840 * the backing store.
8842 uint32_t tqm_ring1_num_entries;
8844 * Number of TQM ring 2 entries.
8846 * TQM fastpath rings should be sized large enough to accommodate the
8847 * maximum number of QPs (either L2 or RoCE, or both if shared)
8848 * that can be enqueued to the TQM ring.
8850 * Note that TQM ring sizes cannot be extended while the system is
8851 * operational. If a PF driver needs to extend a TQM ring, it needs
8852 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8853 * the backing store.
8855 uint32_t tqm_ring2_num_entries;
8857 * Number of TQM ring 3 entries.
8859 * TQM fastpath rings should be sized large enough to accommodate the
8860 * maximum number of QPs (either L2 or RoCE, or both if shared)
8861 * that can be enqueued to the TQM ring.
8863 * Note that TQM ring sizes cannot be extended while the system is
8864 * operational. If a PF driver needs to extend a TQM ring, it needs
8865 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8866 * the backing store.
8868 uint32_t tqm_ring3_num_entries;
8870 * Number of TQM ring 4 entries.
8872 * TQM fastpath rings should be sized large enough to accommodate the
8873 * maximum number of QPs (either L2 or RoCE, or both if shared)
8874 * that can be enqueued to the TQM ring.
8876 * Note that TQM ring sizes cannot be extended while the system is
8877 * operational. If a PF driver needs to extend a TQM ring, it needs
8878 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8879 * the backing store.
8881 uint32_t tqm_ring4_num_entries;
8883 * Number of TQM ring 5 entries.
8885 * TQM fastpath rings should be sized large enough to accommodate the
8886 * maximum number of QPs (either L2 or RoCE, or both if shared)
8887 * that can be enqueued to the TQM ring.
8889 * Note that TQM ring sizes cannot be extended while the system is
8890 * operational. If a PF driver needs to extend a TQM ring, it needs
8891 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8892 * the backing store.
8894 uint32_t tqm_ring5_num_entries;
8896 * Number of TQM ring 6 entries.
8898 * TQM fastpath rings should be sized large enough to accommodate the
8899 * maximum number of QPs (either L2 or RoCE, or both if shared)
8900 * that can be enqueued to the TQM ring.
8902 * Note that TQM ring sizes cannot be extended while the system is
8903 * operational. If a PF driver needs to extend a TQM ring, it needs
8904 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8905 * the backing store.
8907 uint32_t tqm_ring6_num_entries;
8909 * Number of TQM ring 7 entries.
8911 * TQM fastpath rings should be sized large enough to accommodate the
8912 * maximum number of QPs (either L2 or RoCE, or both if shared)
8913 * that can be enqueued to the TQM ring.
8915 * Note that TQM ring sizes cannot be extended while the system is
8916 * operational. If a PF driver needs to extend a TQM ring, it needs
8917 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
8918 * the backing store.
8920 uint32_t tqm_ring7_num_entries;
8921 /* Number of MR/AV entries. */
8922 uint32_t mrav_num_entries;
8923 /* Number of Timer entries. */
8924 uint32_t tim_num_entries;
8925 /* Number of entries to reserve for QP1 */
8926 uint16_t qp_num_qp1_entries;
8927 /* Number of entries to reserve for L2 */
8928 uint16_t qp_num_l2_entries;
8929 /* Number of bytes that have been allocated for each context entry. */
8930 uint16_t qp_entry_size;
8931 /* Number of entries to reserve for L2 */
8932 uint16_t srq_num_l2_entries;
8933 /* Number of bytes that have been allocated for each context entry. */
8934 uint16_t srq_entry_size;
8935 /* Number of entries to reserve for L2 */
8936 uint16_t cq_num_l2_entries;
8937 /* Number of bytes that have been allocated for each context entry. */
8938 uint16_t cq_entry_size;
8939 /* Number of entries to reserve for VNIC entries */
8940 uint16_t vnic_num_vnic_entries;
8941 /* Number of entries to reserve for Ring table entries */
8942 uint16_t vnic_num_ring_table_entries;
8943 /* Number of bytes that have been allocated for each context entry. */
8944 uint16_t vnic_entry_size;
8945 /* Number of bytes that have been allocated for each context entry. */
8946 uint16_t stat_entry_size;
8947 /* Number of bytes that have been allocated for each context entry. */
8948 uint16_t tqm_entry_size;
8949 /* Number of bytes that have been allocated for each context entry. */
8950 uint16_t mrav_entry_size;
8951 /* Number of bytes that have been allocated for each context entry. */
8952 uint16_t tim_entry_size;
8953 } __attribute__((packed));
8955 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
8956 struct hwrm_func_backing_store_cfg_output {
8957 /* The specific error status for the command. */
8958 uint16_t error_code;
8959 /* The HWRM command request type. */
8961 /* The sequence ID from the original command. */
8963 /* The length of the response data in number of bytes. */
8965 uint8_t unused_0[7];
8967 * This field is used in Output records to indicate that the output
8968 * is completely written to RAM. This field should be read as '1'
8969 * to indicate that the output has been completely written.
8970 * When writing a command completion or response to an internal processor,
8971 * the order of writes has to be such that this field is written last.
8974 } __attribute__((packed));
8976 /********************************
8977 * hwrm_func_backing_store_qcfg *
8978 ********************************/
8981 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
8982 struct hwrm_func_backing_store_qcfg_input {
8983 /* The HWRM command request type. */
8986 * The completion ring to send the completion event on. This should
8987 * be the NQ ID returned from the `nq_alloc` HWRM command.
8991 * The sequence ID is used by the driver for tracking multiple
8992 * commands. This ID is treated as opaque data by the firmware and
8993 * the value is returned in the `hwrm_resp_hdr` upon completion.
8997 * The target ID of the command:
8998 * * 0x0-0xFFF8 - The function ID
8999 * * 0xFFF8-0xFFFE - Reserved for internal processors
9004 * A physical address pointer pointing to a host buffer that the
9005 * command's response data will be written. This can be either a host
9006 * physical address (HPA) or a guest physical address (GPA) and must
9007 * point to a physically contiguous block of memory.
9010 } __attribute__((packed));
9012 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
9013 struct hwrm_func_backing_store_qcfg_output {
9014 /* The specific error status for the command. */
9015 uint16_t error_code;
9016 /* The HWRM command request type. */
9018 /* The sequence ID from the original command. */
9020 /* The length of the response data in number of bytes. */
9024 * When set, the firmware only uses on-chip resources and does not
9025 * expect any backing store to be provided by the host driver. This
9026 * mode provides minimal L2 functionality (e.g. limited L2 resources,
9029 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
9031 uint8_t unused_0[4];
9033 * This bit must be '1' for the qp fields to be
9036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
9039 * This bit must be '1' for the srq fields to be
9042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
9045 * This bit must be '1' for the cq fields to be
9048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
9051 * This bit must be '1' for the vnic fields to be
9054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
9057 * This bit must be '1' for the stat fields to be
9060 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
9063 * This bit must be '1' for the tqm_sp fields to be
9066 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
9069 * This bit must be '1' for the tqm_ring0 fields to be
9072 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
9075 * This bit must be '1' for the tqm_ring1 fields to be
9078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
9081 * This bit must be '1' for the tqm_ring2 fields to be
9084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
9087 * This bit must be '1' for the tqm_ring3 fields to be
9090 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
9093 * This bit must be '1' for the tqm_ring4 fields to be
9096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
9099 * This bit must be '1' for the tqm_ring5 fields to be
9102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
9105 * This bit must be '1' for the tqm_ring6 fields to be
9108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
9111 * This bit must be '1' for the tqm_ring7 fields to be
9114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
9117 * This bit must be '1' for the mrav fields to be
9120 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
9123 * This bit must be '1' for the tim fields to be
9126 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
9128 /* QPC page size and level. */
9129 uint8_t qpc_pg_size_qpc_lvl;
9130 /* QPC PBL indirect levels. */
9131 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
9133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
9134 /* PBL pointer is physical start address. */
9135 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
9137 /* PBL pointer points to PTE table. */
9138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
9140 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
9143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
9144 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
9145 /* QPC page size. */
9146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
9148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
9150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
9151 (UINT32_C(0x0) << 4)
9153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
9154 (UINT32_C(0x1) << 4)
9156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
9157 (UINT32_C(0x2) << 4)
9159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
9160 (UINT32_C(0x3) << 4)
9162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
9163 (UINT32_C(0x4) << 4)
9165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
9166 (UINT32_C(0x5) << 4)
9167 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
9168 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
9169 /* SRQ page size and level. */
9170 uint8_t srq_pg_size_srq_lvl;
9171 /* SRQ PBL indirect levels. */
9172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
9174 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
9175 /* PBL pointer is physical start address. */
9176 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
9178 /* PBL pointer points to PTE table. */
9179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
9181 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
9184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
9185 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
9186 /* SRQ page size. */
9187 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
9189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
9191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
9192 (UINT32_C(0x0) << 4)
9194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
9195 (UINT32_C(0x1) << 4)
9197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
9198 (UINT32_C(0x2) << 4)
9200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
9201 (UINT32_C(0x3) << 4)
9203 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
9204 (UINT32_C(0x4) << 4)
9206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
9207 (UINT32_C(0x5) << 4)
9208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
9209 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
9210 /* CQ page size and level. */
9211 uint8_t cq_pg_size_cq_lvl;
9212 /* CQ PBL indirect levels. */
9213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
9215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
9216 /* PBL pointer is physical start address. */
9217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
9219 /* PBL pointer points to PTE table. */
9220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
9222 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
9225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
9226 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
9228 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
9230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
9232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
9233 (UINT32_C(0x0) << 4)
9235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
9236 (UINT32_C(0x1) << 4)
9238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
9239 (UINT32_C(0x2) << 4)
9241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
9242 (UINT32_C(0x3) << 4)
9244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
9245 (UINT32_C(0x4) << 4)
9247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
9248 (UINT32_C(0x5) << 4)
9249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
9250 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
9251 /* VNIC page size and level. */
9252 uint8_t vnic_pg_size_vnic_lvl;
9253 /* VNIC PBL indirect levels. */
9254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
9256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
9257 /* PBL pointer is physical start address. */
9258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
9260 /* PBL pointer points to PTE table. */
9261 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
9263 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
9266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
9267 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
9268 /* VNIC page size. */
9269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
9271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
9273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
9274 (UINT32_C(0x0) << 4)
9276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
9277 (UINT32_C(0x1) << 4)
9279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
9280 (UINT32_C(0x2) << 4)
9282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
9283 (UINT32_C(0x3) << 4)
9285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
9286 (UINT32_C(0x4) << 4)
9288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
9289 (UINT32_C(0x5) << 4)
9290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
9291 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
9292 /* Stat page size and level. */
9293 uint8_t stat_pg_size_stat_lvl;
9294 /* Stat PBL indirect levels. */
9295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
9297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
9298 /* PBL pointer is physical start address. */
9299 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
9301 /* PBL pointer points to PTE table. */
9302 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
9304 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
9307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
9308 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
9309 /* Stat page size. */
9310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
9312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
9314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
9315 (UINT32_C(0x0) << 4)
9317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
9318 (UINT32_C(0x1) << 4)
9320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
9321 (UINT32_C(0x2) << 4)
9323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
9324 (UINT32_C(0x3) << 4)
9326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
9327 (UINT32_C(0x4) << 4)
9329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
9330 (UINT32_C(0x5) << 4)
9331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
9332 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
9333 /* TQM slow path page size and level. */
9334 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
9335 /* TQM slow path PBL indirect levels. */
9336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
9338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
9339 /* PBL pointer is physical start address. */
9340 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
9342 /* PBL pointer points to PTE table. */
9343 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
9345 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
9348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
9349 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
9350 /* TQM slow path page size. */
9351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
9353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
9355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
9356 (UINT32_C(0x0) << 4)
9358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
9359 (UINT32_C(0x1) << 4)
9361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
9362 (UINT32_C(0x2) << 4)
9364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
9365 (UINT32_C(0x3) << 4)
9367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
9368 (UINT32_C(0x4) << 4)
9370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
9371 (UINT32_C(0x5) << 4)
9372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
9373 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
9374 /* TQM ring 0 page size and level. */
9375 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9376 /* TQM ring 0 PBL indirect levels. */
9377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
9379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
9380 /* PBL pointer is physical start address. */
9381 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
9383 /* PBL pointer points to PTE table. */
9384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
9386 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
9389 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
9390 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
9391 /* TQM ring 0 page size. */
9392 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
9394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
9396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
9397 (UINT32_C(0x0) << 4)
9399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
9400 (UINT32_C(0x1) << 4)
9402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
9403 (UINT32_C(0x2) << 4)
9405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
9406 (UINT32_C(0x3) << 4)
9408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
9409 (UINT32_C(0x4) << 4)
9411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
9412 (UINT32_C(0x5) << 4)
9413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
9414 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
9415 /* TQM ring 1 page size and level. */
9416 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9417 /* TQM ring 1 PBL indirect levels. */
9418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
9420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
9421 /* PBL pointer is physical start address. */
9422 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
9424 /* PBL pointer points to PTE table. */
9425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
9427 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
9430 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
9431 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
9432 /* TQM ring 1 page size. */
9433 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
9435 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
9437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
9438 (UINT32_C(0x0) << 4)
9440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
9441 (UINT32_C(0x1) << 4)
9443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
9444 (UINT32_C(0x2) << 4)
9446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
9447 (UINT32_C(0x3) << 4)
9449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
9450 (UINT32_C(0x4) << 4)
9452 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
9453 (UINT32_C(0x5) << 4)
9454 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
9455 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
9456 /* TQM ring 2 page size and level. */
9457 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9458 /* TQM ring 2 PBL indirect levels. */
9459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
9461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
9462 /* PBL pointer is physical start address. */
9463 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
9465 /* PBL pointer points to PTE table. */
9466 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
9468 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9469 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
9471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
9472 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
9473 /* TQM ring 2 page size. */
9474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
9476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
9478 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
9479 (UINT32_C(0x0) << 4)
9481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
9482 (UINT32_C(0x1) << 4)
9484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
9485 (UINT32_C(0x2) << 4)
9487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
9488 (UINT32_C(0x3) << 4)
9490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
9491 (UINT32_C(0x4) << 4)
9493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
9494 (UINT32_C(0x5) << 4)
9495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
9496 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
9497 /* TQM ring 3 page size and level. */
9498 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9499 /* TQM ring 3 PBL indirect levels. */
9500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
9502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
9503 /* PBL pointer is physical start address. */
9504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
9506 /* PBL pointer points to PTE table. */
9507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
9509 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
9512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
9513 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
9514 /* TQM ring 3 page size. */
9515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
9517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
9519 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
9520 (UINT32_C(0x0) << 4)
9522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
9523 (UINT32_C(0x1) << 4)
9525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
9526 (UINT32_C(0x2) << 4)
9528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
9529 (UINT32_C(0x3) << 4)
9531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
9532 (UINT32_C(0x4) << 4)
9534 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
9535 (UINT32_C(0x5) << 4)
9536 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
9537 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
9538 /* TQM ring 4 page size and level. */
9539 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9540 /* TQM ring 4 PBL indirect levels. */
9541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
9543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
9544 /* PBL pointer is physical start address. */
9545 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
9547 /* PBL pointer points to PTE table. */
9548 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
9550 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9551 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
9553 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
9554 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
9555 /* TQM ring 4 page size. */
9556 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
9558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
9560 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
9561 (UINT32_C(0x0) << 4)
9563 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
9564 (UINT32_C(0x1) << 4)
9566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
9567 (UINT32_C(0x2) << 4)
9569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
9570 (UINT32_C(0x3) << 4)
9572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
9573 (UINT32_C(0x4) << 4)
9575 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
9576 (UINT32_C(0x5) << 4)
9577 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
9578 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
9579 /* TQM ring 5 page size and level. */
9580 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9581 /* TQM ring 5 PBL indirect levels. */
9582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
9584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
9585 /* PBL pointer is physical start address. */
9586 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
9588 /* PBL pointer points to PTE table. */
9589 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
9591 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
9594 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
9595 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
9596 /* TQM ring 5 page size. */
9597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
9599 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
9601 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
9602 (UINT32_C(0x0) << 4)
9604 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
9605 (UINT32_C(0x1) << 4)
9607 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
9608 (UINT32_C(0x2) << 4)
9610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
9611 (UINT32_C(0x3) << 4)
9613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
9614 (UINT32_C(0x4) << 4)
9616 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
9617 (UINT32_C(0x5) << 4)
9618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
9619 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
9620 /* TQM ring 6 page size and level. */
9621 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9622 /* TQM ring 6 PBL indirect levels. */
9623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
9625 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
9626 /* PBL pointer is physical start address. */
9627 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
9629 /* PBL pointer points to PTE table. */
9630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
9632 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9633 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
9635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
9636 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
9637 /* TQM ring 6 page size. */
9638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
9640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
9642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
9643 (UINT32_C(0x0) << 4)
9645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
9646 (UINT32_C(0x1) << 4)
9648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
9649 (UINT32_C(0x2) << 4)
9651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
9652 (UINT32_C(0x3) << 4)
9654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
9655 (UINT32_C(0x4) << 4)
9657 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
9658 (UINT32_C(0x5) << 4)
9659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
9660 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
9661 /* TQM ring 7 page size and level. */
9662 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9663 /* TQM ring 7 PBL indirect levels. */
9664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
9666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
9667 /* PBL pointer is physical start address. */
9668 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
9670 /* PBL pointer points to PTE table. */
9671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
9673 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
9676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
9677 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
9678 /* TQM ring 7 page size. */
9679 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
9681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
9683 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
9684 (UINT32_C(0x0) << 4)
9686 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
9687 (UINT32_C(0x1) << 4)
9689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
9690 (UINT32_C(0x2) << 4)
9692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
9693 (UINT32_C(0x3) << 4)
9695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
9696 (UINT32_C(0x4) << 4)
9698 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
9699 (UINT32_C(0x5) << 4)
9700 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
9701 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
9702 /* MR/AV page size and level. */
9703 uint8_t mrav_pg_size_mrav_lvl;
9704 /* MR/AV PBL indirect levels. */
9705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
9707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
9708 /* PBL pointer is physical start address. */
9709 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
9711 /* PBL pointer points to PTE table. */
9712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
9714 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9715 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
9717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
9718 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
9719 /* MR/AV page size. */
9720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
9722 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
9724 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
9725 (UINT32_C(0x0) << 4)
9727 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
9728 (UINT32_C(0x1) << 4)
9730 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
9731 (UINT32_C(0x2) << 4)
9733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
9734 (UINT32_C(0x3) << 4)
9736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
9737 (UINT32_C(0x4) << 4)
9739 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
9740 (UINT32_C(0x5) << 4)
9741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
9742 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
9743 /* Timer page size and level. */
9744 uint8_t tim_pg_size_tim_lvl;
9745 /* Timer PBL indirect levels. */
9746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
9748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
9749 /* PBL pointer is physical start address. */
9750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
9752 /* PBL pointer points to PTE table. */
9753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
9755 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
9758 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
9759 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
9760 /* Timer page size. */
9761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
9763 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
9765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
9766 (UINT32_C(0x0) << 4)
9768 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
9769 (UINT32_C(0x1) << 4)
9771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
9772 (UINT32_C(0x2) << 4)
9774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
9775 (UINT32_C(0x3) << 4)
9777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
9778 (UINT32_C(0x4) << 4)
9780 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
9781 (UINT32_C(0x5) << 4)
9782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
9783 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
9784 /* QP page directory. */
9785 uint64_t qpc_page_dir;
9786 /* SRQ page directory. */
9787 uint64_t srq_page_dir;
9788 /* CQ page directory. */
9789 uint64_t cq_page_dir;
9790 /* VNIC page directory. */
9791 uint64_t vnic_page_dir;
9792 /* Stat page directory. */
9793 uint64_t stat_page_dir;
9794 /* TQM slowpath page directory. */
9795 uint64_t tqm_sp_page_dir;
9796 /* TQM ring 0 page directory. */
9797 uint64_t tqm_ring0_page_dir;
9798 /* TQM ring 1 page directory. */
9799 uint64_t tqm_ring1_page_dir;
9800 /* TQM ring 2 page directory. */
9801 uint64_t tqm_ring2_page_dir;
9802 /* TQM ring 3 page directory. */
9803 uint64_t tqm_ring3_page_dir;
9804 /* TQM ring 4 page directory. */
9805 uint64_t tqm_ring4_page_dir;
9806 /* TQM ring 5 page directory. */
9807 uint64_t tqm_ring5_page_dir;
9808 /* TQM ring 6 page directory. */
9809 uint64_t tqm_ring6_page_dir;
9810 /* TQM ring 7 page directory. */
9811 uint64_t tqm_ring7_page_dir;
9812 /* MR/AV page directory. */
9813 uint64_t mrav_page_dir;
9814 /* Timer page directory. */
9815 uint64_t tim_page_dir;
9816 /* Number of entries to reserve for QP1 */
9817 uint16_t qp_num_qp1_entries;
9818 /* Number of entries to reserve for L2 */
9819 uint16_t qp_num_l2_entries;
9820 /* Number of QPs. */
9821 uint32_t qp_num_entries;
9822 /* Number of SRQs. */
9823 uint32_t srq_num_entries;
9824 /* Number of entries to reserve for L2 */
9825 uint16_t srq_num_l2_entries;
9826 /* Number of entries to reserve for L2 */
9827 uint16_t cq_num_l2_entries;
9828 /* Number of CQs. */
9829 uint32_t cq_num_entries;
9830 /* Number of entries to reserve for VNIC entries */
9831 uint16_t vnic_num_vnic_entries;
9832 /* Number of entries to reserve for Ring table entries */
9833 uint16_t vnic_num_ring_table_entries;
9834 /* Number of Stats. */
9835 uint32_t stat_num_entries;
9836 /* Number of TQM slowpath entries. */
9837 uint32_t tqm_sp_num_entries;
9838 /* Number of TQM ring 0 entries. */
9839 uint32_t tqm_ring0_num_entries;
9840 /* Number of TQM ring 1 entries. */
9841 uint32_t tqm_ring1_num_entries;
9842 /* Number of TQM ring 2 entries. */
9843 uint32_t tqm_ring2_num_entries;
9844 /* Number of TQM ring 3 entries. */
9845 uint32_t tqm_ring3_num_entries;
9846 /* Number of TQM ring 4 entries. */
9847 uint32_t tqm_ring4_num_entries;
9848 /* Number of TQM ring 5 entries. */
9849 uint32_t tqm_ring5_num_entries;
9850 /* Number of TQM ring 6 entries. */
9851 uint32_t tqm_ring6_num_entries;
9852 /* Number of TQM ring 7 entries. */
9853 uint32_t tqm_ring7_num_entries;
9854 /* Number of MR/AV entries. */
9855 uint32_t mrav_num_entries;
9856 /* Number of Timer entries. */
9857 uint32_t tim_num_entries;
9858 uint8_t unused_1[7];
9860 * This field is used in Output records to indicate that the output
9861 * is completely written to RAM. This field should be read as '1'
9862 * to indicate that the output has been completely written.
9863 * When writing a command completion or response to an internal processor,
9864 * the order of writes has to be such that this field is written last.
9867 } __attribute__((packed));
9869 /***********************
9870 * hwrm_func_vlan_qcfg *
9871 ***********************/
9874 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
9875 struct hwrm_func_vlan_qcfg_input {
9876 /* The HWRM command request type. */
9879 * The completion ring to send the completion event on. This should
9880 * be the NQ ID returned from the `nq_alloc` HWRM command.
9884 * The sequence ID is used by the driver for tracking multiple
9885 * commands. This ID is treated as opaque data by the firmware and
9886 * the value is returned in the `hwrm_resp_hdr` upon completion.
9890 * The target ID of the command:
9891 * * 0x0-0xFFF8 - The function ID
9892 * * 0xFFF8-0xFFFE - Reserved for internal processors
9897 * A physical address pointer pointing to a host buffer that the
9898 * command's response data will be written. This can be either a host
9899 * physical address (HPA) or a guest physical address (GPA) and must
9900 * point to a physically contiguous block of memory.
9904 * Function ID of the function that is being
9906 * If set to 0xFF... (All Fs), then the configuration is
9907 * for the requesting function.
9910 uint8_t unused_0[6];
9911 } __attribute__((packed));
9913 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
9914 struct hwrm_func_vlan_qcfg_output {
9915 /* The specific error status for the command. */
9916 uint16_t error_code;
9917 /* The HWRM command request type. */
9919 /* The sequence ID from the original command. */
9921 /* The length of the response data in number of bytes. */
9924 /* S-TAG VLAN identifier configured for the function. */
9926 /* S-TAG PCP value configured for the function. */
9930 * S-TAG TPID value configured for the function. This field is specified in
9931 * network byte order.
9934 /* C-TAG VLAN identifier configured for the function. */
9936 /* C-TAG PCP value configured for the function. */
9940 * C-TAG TPID value configured for the function. This field is specified in
9941 * network byte order.
9948 uint8_t unused_3[3];
9950 * This field is used in Output records to indicate that the output
9951 * is completely written to RAM. This field should be read as '1'
9952 * to indicate that the output has been completely written.
9953 * When writing a command completion or response to an internal processor,
9954 * the order of writes has to be such that this field is written last.
9957 } __attribute__((packed));
9959 /**********************
9960 * hwrm_func_vlan_cfg *
9961 **********************/
9964 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
9965 struct hwrm_func_vlan_cfg_input {
9966 /* The HWRM command request type. */
9969 * The completion ring to send the completion event on. This should
9970 * be the NQ ID returned from the `nq_alloc` HWRM command.
9974 * The sequence ID is used by the driver for tracking multiple
9975 * commands. This ID is treated as opaque data by the firmware and
9976 * the value is returned in the `hwrm_resp_hdr` upon completion.
9980 * The target ID of the command:
9981 * * 0x0-0xFFF8 - The function ID
9982 * * 0xFFF8-0xFFFE - Reserved for internal processors
9987 * A physical address pointer pointing to a host buffer that the
9988 * command's response data will be written. This can be either a host
9989 * physical address (HPA) or a guest physical address (GPA) and must
9990 * point to a physically contiguous block of memory.
9994 * Function ID of the function that is being
9996 * If set to 0xFF... (All Fs), then the configuration is
9997 * for the requesting function.
10000 uint8_t unused_0[2];
10003 * This bit must be '1' for the stag_vid field to be
10006 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
10008 * This bit must be '1' for the ctag_vid field to be
10011 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
10013 * This bit must be '1' for the stag_pcp field to be
10016 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
10018 * This bit must be '1' for the ctag_pcp field to be
10021 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
10023 * This bit must be '1' for the stag_tpid field to be
10026 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
10028 * This bit must be '1' for the ctag_tpid field to be
10031 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
10032 /* S-TAG VLAN identifier configured for the function. */
10034 /* S-TAG PCP value configured for the function. */
10038 * S-TAG TPID value configured for the function. This field is specified in
10039 * network byte order.
10041 uint16_t stag_tpid;
10042 /* C-TAG VLAN identifier configured for the function. */
10044 /* C-TAG PCP value configured for the function. */
10048 * C-TAG TPID value configured for the function. This field is specified in
10049 * network byte order.
10051 uint16_t ctag_tpid;
10056 uint8_t unused_3[4];
10057 } __attribute__((packed));
10059 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
10060 struct hwrm_func_vlan_cfg_output {
10061 /* The specific error status for the command. */
10062 uint16_t error_code;
10063 /* The HWRM command request type. */
10065 /* The sequence ID from the original command. */
10067 /* The length of the response data in number of bytes. */
10069 uint8_t unused_0[7];
10071 * This field is used in Output records to indicate that the output
10072 * is completely written to RAM. This field should be read as '1'
10073 * to indicate that the output has been completely written.
10074 * When writing a command completion or response to an internal processor,
10075 * the order of writes has to be such that this field is written last.
10078 } __attribute__((packed));
10080 /*******************************
10081 * hwrm_func_vf_vnic_ids_query *
10082 *******************************/
10085 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
10086 struct hwrm_func_vf_vnic_ids_query_input {
10087 /* The HWRM command request type. */
10090 * The completion ring to send the completion event on. This should
10091 * be the NQ ID returned from the `nq_alloc` HWRM command.
10093 uint16_t cmpl_ring;
10095 * The sequence ID is used by the driver for tracking multiple
10096 * commands. This ID is treated as opaque data by the firmware and
10097 * the value is returned in the `hwrm_resp_hdr` upon completion.
10101 * The target ID of the command:
10102 * * 0x0-0xFFF8 - The function ID
10103 * * 0xFFF8-0xFFFE - Reserved for internal processors
10106 uint16_t target_id;
10108 * A physical address pointer pointing to a host buffer that the
10109 * command's response data will be written. This can be either a host
10110 * physical address (HPA) or a guest physical address (GPA) and must
10111 * point to a physically contiguous block of memory.
10113 uint64_t resp_addr;
10115 * This value is used to identify a Virtual Function (VF).
10116 * The scope of VF ID is local within a PF.
10119 uint8_t unused_0[2];
10120 /* Max number of vnic ids in vnic id table */
10121 uint32_t max_vnic_id_cnt;
10122 /* This is the address for VF VNIC ID table */
10123 uint64_t vnic_id_tbl_addr;
10124 } __attribute__((packed));
10126 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
10127 struct hwrm_func_vf_vnic_ids_query_output {
10128 /* The specific error status for the command. */
10129 uint16_t error_code;
10130 /* The HWRM command request type. */
10132 /* The sequence ID from the original command. */
10134 /* The length of the response data in number of bytes. */
10137 * Actual number of vnic ids
10139 * Each VNIC ID is written as a 32-bit number.
10141 uint32_t vnic_id_cnt;
10142 uint8_t unused_0[3];
10144 * This field is used in Output records to indicate that the output
10145 * is completely written to RAM. This field should be read as '1'
10146 * to indicate that the output has been completely written.
10147 * When writing a command completion or response to an internal processor,
10148 * the order of writes has to be such that this field is written last.
10151 } __attribute__((packed));
10153 /***********************
10154 * hwrm_func_vf_bw_cfg *
10155 ***********************/
10158 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
10159 struct hwrm_func_vf_bw_cfg_input {
10160 /* The HWRM command request type. */
10163 * The completion ring to send the completion event on. This should
10164 * be the NQ ID returned from the `nq_alloc` HWRM command.
10166 uint16_t cmpl_ring;
10168 * The sequence ID is used by the driver for tracking multiple
10169 * commands. This ID is treated as opaque data by the firmware and
10170 * the value is returned in the `hwrm_resp_hdr` upon completion.
10174 * The target ID of the command:
10175 * * 0x0-0xFFF8 - The function ID
10176 * * 0xFFF8-0xFFFE - Reserved for internal processors
10179 uint16_t target_id;
10181 * A physical address pointer pointing to a host buffer that the
10182 * command's response data will be written. This can be either a host
10183 * physical address (HPA) or a guest physical address (GPA) and must
10184 * point to a physically contiguous block of memory.
10186 uint64_t resp_addr;
10188 * The number of VF functions that are being configured.
10189 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
10192 uint16_t unused[3];
10193 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
10195 /* The physical VF id the adjustment will be made to. */
10196 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
10197 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
10199 * This field configures the rate scale percentage of the VF as specified
10200 * by the physical VF id.
10202 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
10203 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
10204 /* 0% of the max tx rate */
10205 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
10206 (UINT32_C(0x0) << 12)
10207 /* 6.66% of the max tx rate */
10208 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
10209 (UINT32_C(0x1) << 12)
10210 /* 13.33% of the max tx rate */
10211 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
10212 (UINT32_C(0x2) << 12)
10213 /* 20% of the max tx rate */
10214 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
10215 (UINT32_C(0x3) << 12)
10216 /* 26.66% of the max tx rate */
10217 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
10218 (UINT32_C(0x4) << 12)
10219 /* 33% of the max tx rate */
10220 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
10221 (UINT32_C(0x5) << 12)
10222 /* 40% of the max tx rate */
10223 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
10224 (UINT32_C(0x6) << 12)
10225 /* 46.66% of the max tx rate */
10226 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
10227 (UINT32_C(0x7) << 12)
10228 /* 53.33% of the max tx rate */
10229 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
10230 (UINT32_C(0x8) << 12)
10231 /* 60% of the max tx rate */
10232 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
10233 (UINT32_C(0x9) << 12)
10234 /* 66.66% of the max tx rate */
10235 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
10236 (UINT32_C(0xa) << 12)
10237 /* 53.33% of the max tx rate */
10238 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
10239 (UINT32_C(0xb) << 12)
10240 /* 80% of the max tx rate */
10241 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
10242 (UINT32_C(0xc) << 12)
10243 /* 86.66% of the max tx rate */
10244 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
10245 (UINT32_C(0xd) << 12)
10246 /* 93.33% of the max tx rate */
10247 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
10248 (UINT32_C(0xe) << 12)
10249 /* 100% of the max tx rate */
10250 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
10251 (UINT32_C(0xf) << 12)
10252 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
10253 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
10254 } __attribute__((packed));
10256 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
10257 struct hwrm_func_vf_bw_cfg_output {
10258 /* The specific error status for the command. */
10259 uint16_t error_code;
10260 /* The HWRM command request type. */
10262 /* The sequence ID from the original command. */
10264 /* The length of the response data in number of bytes. */
10266 uint8_t unused_0[7];
10268 * This field is used in Output records to indicate that the output
10269 * is completely written to RAM. This field should be read as '1'
10270 * to indicate that the output has been completely written.
10271 * When writing a command completion or response to an internal processor,
10272 * the order of writes has to be such that this field is written last.
10275 } __attribute__((packed));
10277 /************************
10278 * hwrm_func_vf_bw_qcfg *
10279 ************************/
10282 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
10283 struct hwrm_func_vf_bw_qcfg_input {
10284 /* The HWRM command request type. */
10287 * The completion ring to send the completion event on. This should
10288 * be the NQ ID returned from the `nq_alloc` HWRM command.
10290 uint16_t cmpl_ring;
10292 * The sequence ID is used by the driver for tracking multiple
10293 * commands. This ID is treated as opaque data by the firmware and
10294 * the value is returned in the `hwrm_resp_hdr` upon completion.
10298 * The target ID of the command:
10299 * * 0x0-0xFFF8 - The function ID
10300 * * 0xFFF8-0xFFFE - Reserved for internal processors
10303 uint16_t target_id;
10305 * A physical address pointer pointing to a host buffer that the
10306 * command's response data will be written. This can be either a host
10307 * physical address (HPA) or a guest physical address (GPA) and must
10308 * point to a physically contiguous block of memory.
10310 uint64_t resp_addr;
10312 * The number of VF functions that are being queried.
10313 * The inline response space allows the host to query up to 50 VFs'
10314 * rate scale percentage
10317 uint16_t unused[3];
10318 /* These 16-bit fields contain the VF fid */
10320 /* The physical VF id of interest */
10321 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
10322 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
10323 } __attribute__((packed));
10325 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
10326 struct hwrm_func_vf_bw_qcfg_output {
10327 /* The specific error status for the command. */
10328 uint16_t error_code;
10329 /* The HWRM command request type. */
10331 /* The sequence ID from the original command. */
10333 /* The length of the response data in number of bytes. */
10336 * The number of VF functions that are being queried.
10337 * The inline response space allows the host to query up to 50 VFs' rate
10341 uint16_t unused[3];
10342 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
10344 /* The physical VF id the adjustment will be made to. */
10345 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
10346 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
10348 * This field configures the rate scale percentage of the VF as specified
10349 * by the physical VF id.
10351 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
10352 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
10353 /* 0% of the max tx rate */
10354 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
10355 (UINT32_C(0x0) << 12)
10356 /* 6.66% of the max tx rate */
10357 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
10358 (UINT32_C(0x1) << 12)
10359 /* 13.33% of the max tx rate */
10360 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
10361 (UINT32_C(0x2) << 12)
10362 /* 20% of the max tx rate */
10363 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
10364 (UINT32_C(0x3) << 12)
10365 /* 26.66% of the max tx rate */
10366 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
10367 (UINT32_C(0x4) << 12)
10368 /* 33% of the max tx rate */
10369 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
10370 (UINT32_C(0x5) << 12)
10371 /* 40% of the max tx rate */
10372 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
10373 (UINT32_C(0x6) << 12)
10374 /* 46.66% of the max tx rate */
10375 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
10376 (UINT32_C(0x7) << 12)
10377 /* 53.33% of the max tx rate */
10378 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
10379 (UINT32_C(0x8) << 12)
10380 /* 60% of the max tx rate */
10381 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
10382 (UINT32_C(0x9) << 12)
10383 /* 66.66% of the max tx rate */
10384 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
10385 (UINT32_C(0xa) << 12)
10386 /* 53.33% of the max tx rate */
10387 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
10388 (UINT32_C(0xb) << 12)
10389 /* 80% of the max tx rate */
10390 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
10391 (UINT32_C(0xc) << 12)
10392 /* 86.66% of the max tx rate */
10393 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
10394 (UINT32_C(0xd) << 12)
10395 /* 93.33% of the max tx rate */
10396 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
10397 (UINT32_C(0xe) << 12)
10398 /* 100% of the max tx rate */
10399 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
10400 (UINT32_C(0xf) << 12)
10401 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
10402 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
10403 uint8_t unused_0[7];
10405 * This field is used in Output records to indicate that the output
10406 * is completely written to RAM. This field should be read as '1'
10407 * to indicate that the output has been completely written.
10408 * When writing a command completion or response to an internal processor,
10409 * the order of writes has to be such that this field is written last.
10412 } __attribute__((packed));
10414 /***************************
10415 * hwrm_func_drv_if_change *
10416 ***************************/
10419 /* hwrm_func_drv_if_change_input (size:192b/24B) */
10420 struct hwrm_func_drv_if_change_input {
10421 /* The HWRM command request type. */
10424 * The completion ring to send the completion event on. This should
10425 * be the NQ ID returned from the `nq_alloc` HWRM command.
10427 uint16_t cmpl_ring;
10429 * The sequence ID is used by the driver for tracking multiple
10430 * commands. This ID is treated as opaque data by the firmware and
10431 * the value is returned in the `hwrm_resp_hdr` upon completion.
10435 * The target ID of the command:
10436 * * 0x0-0xFFF8 - The function ID
10437 * * 0xFFF8-0xFFFE - Reserved for internal processors
10440 uint16_t target_id;
10442 * A physical address pointer pointing to a host buffer that the
10443 * command's response data will be written. This can be either a host
10444 * physical address (HPA) or a guest physical address (GPA) and must
10445 * point to a physically contiguous block of memory.
10447 uint64_t resp_addr;
10450 * When this bit is '1', the function driver is indicating
10451 * that the IF state is changing to UP state. The call should
10452 * be made at the beginning of the driver's open call before
10453 * resources are allocated. After making the call, the driver
10454 * should check the response to see if any resources may have
10455 * changed (see the response below). If the driver fails
10456 * the open call, the driver should make this call again with
10457 * this bit cleared to indicate that the IF state is not UP.
10458 * During the driver's close call when the IF state is changing
10459 * to DOWN, the driver should make this call with the bit cleared
10460 * after all resources have been freed.
10462 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
10464 } __attribute__((packed));
10466 /* hwrm_func_drv_if_change_output (size:128b/16B) */
10467 struct hwrm_func_drv_if_change_output {
10468 /* The specific error status for the command. */
10469 uint16_t error_code;
10470 /* The HWRM command request type. */
10472 /* The sequence ID from the original command. */
10474 /* The length of the response data in number of bytes. */
10478 * When this bit is '1', it indicates that the resources reserved
10479 * for this function may have changed. The driver should check
10480 * resource capabilities and reserve resources again before
10481 * allocating resources.
10483 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
10485 uint8_t unused_0[3];
10487 * This field is used in Output records to indicate that the output
10488 * is completely written to RAM. This field should be read as '1'
10489 * to indicate that the output has been completely written.
10490 * When writing a command completion or response to an internal processor,
10491 * the order of writes has to be such that this field is written last.
10494 } __attribute__((packed));
10496 /*********************
10497 * hwrm_port_phy_cfg *
10498 *********************/
10501 /* hwrm_port_phy_cfg_input (size:448b/56B) */
10502 struct hwrm_port_phy_cfg_input {
10503 /* The HWRM command request type. */
10506 * The completion ring to send the completion event on. This should
10507 * be the NQ ID returned from the `nq_alloc` HWRM command.
10509 uint16_t cmpl_ring;
10511 * The sequence ID is used by the driver for tracking multiple
10512 * commands. This ID is treated as opaque data by the firmware and
10513 * the value is returned in the `hwrm_resp_hdr` upon completion.
10517 * The target ID of the command:
10518 * * 0x0-0xFFF8 - The function ID
10519 * * 0xFFF8-0xFFFE - Reserved for internal processors
10522 uint16_t target_id;
10524 * A physical address pointer pointing to a host buffer that the
10525 * command's response data will be written. This can be either a host
10526 * physical address (HPA) or a guest physical address (GPA) and must
10527 * point to a physically contiguous block of memory.
10529 uint64_t resp_addr;
10532 * When this bit is set to '1', the PHY for the port shall
10535 * # If this bit is set to 1, then the HWRM shall reset the
10536 * PHY after applying PHY configuration changes specified
10538 * # In order to guarantee that PHY configuration changes
10539 * specified in this command take effect, the HWRM
10540 * client should set this flag to 1.
10541 * # If this bit is not set to 1, then the HWRM may reset
10542 * the PHY depending on the current PHY configuration and
10543 * settings specified in this command.
10545 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
10547 /* deprecated bit. Do not use!!! */
10548 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
10551 * When this bit is set to '1', the link shall be forced to
10552 * the force_link_speed value.
10554 * When this bit is set to '1', the HWRM client should
10555 * not enable any of the auto negotiation related
10556 * fields represented by auto_XXX fields in this command.
10557 * When this bit is set to '1' and the HWRM client has
10558 * enabled a auto_XXX field in this command, then the
10559 * HWRM shall ignore the enabled auto_XXX field.
10561 * When this bit is set to zero, the link
10562 * shall be allowed to autoneg.
10564 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
10567 * When this bit is set to '1', the auto-negotiation process
10568 * shall be restarted on the link.
10570 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
10573 * When this bit is set to '1', Energy Efficient Ethernet
10574 * (EEE) is requested to be enabled on this link.
10575 * If EEE is not supported on this port, then this flag
10576 * shall be ignored by the HWRM.
10578 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
10581 * When this bit is set to '1', Energy Efficient Ethernet
10582 * (EEE) is requested to be disabled on this link.
10583 * If EEE is not supported on this port, then this flag
10584 * shall be ignored by the HWRM.
10586 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
10589 * When this bit is set to '1' and EEE is enabled on this
10590 * link, then TX LPI is requested to be enabled on the link.
10591 * If EEE is not supported on this port, then this flag
10592 * shall be ignored by the HWRM.
10593 * If EEE is disabled on this port, then this flag shall be
10594 * ignored by the HWRM.
10596 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
10599 * When this bit is set to '1' and EEE is enabled on this
10600 * link, then TX LPI is requested to be disabled on the link.
10601 * If EEE is not supported on this port, then this flag
10602 * shall be ignored by the HWRM.
10603 * If EEE is disabled on this port, then this flag shall be
10604 * ignored by the HWRM.
10606 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
10609 * When set to 1, then the HWRM shall enable FEC autonegotitation
10610 * on this port if supported.
10611 * When set to 0, then this flag shall be ignored.
10612 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
10615 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
10618 * When set to 1, then the HWRM shall disable FEC autonegotiation
10619 * on this port if supported.
10620 * When set to 0, then this flag shall be ignored.
10621 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
10624 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
10627 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
10628 * on this port if supported.
10629 * When set to 0, then this flag shall be ignored.
10630 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
10633 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
10636 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
10637 * on this port if supported.
10638 * When set to 0, then this flag shall be ignored.
10639 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
10642 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
10645 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
10646 * on this port if supported.
10647 * When set to 0, then this flag shall be ignored.
10648 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
10651 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
10654 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
10655 * on this port if supported.
10656 * When set to 0, then this flag shall be ignored.
10657 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
10660 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
10663 * When this bit is set to '1', the link shall be forced to
10666 * # When this bit is set to '1", all other
10667 * command input settings related to the link speed shall
10669 * Once the link state is forced down, it can be
10670 * explicitly cleared from that state by setting this flag
10672 * # If this flag is set to '0', then the link shall be
10673 * cleared from forced down state if the link is in forced
10675 * There may be conditions (e.g. out-of-band or sideband
10676 * configuration changes for the link) outside the scope
10677 * of the HWRM implementation that may clear forced down
10680 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
10684 * This bit must be '1' for the auto_mode field to be
10687 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
10690 * This bit must be '1' for the auto_duplex field to be
10693 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
10696 * This bit must be '1' for the auto_pause field to be
10699 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
10702 * This bit must be '1' for the auto_link_speed field to be
10705 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
10708 * This bit must be '1' for the auto_link_speed_mask field to be
10711 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
10714 * This bit must be '1' for the wirespeed field to be
10717 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
10720 * This bit must be '1' for the lpbk field to be
10723 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
10726 * This bit must be '1' for the preemphasis field to be
10729 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
10732 * This bit must be '1' for the force_pause field to be
10735 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
10738 * This bit must be '1' for the eee_link_speed_mask field to be
10741 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
10744 * This bit must be '1' for the tx_lpi_timer field to be
10747 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
10749 /* Port ID of port that is to be configured. */
10752 * This is the speed that will be used if the force
10753 * bit is '1'. If unsupported speed is selected, an error
10754 * will be generated.
10756 uint16_t force_link_speed;
10757 /* 100Mb link speed */
10758 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
10759 /* 1Gb link speed */
10760 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
10761 /* 2Gb link speed */
10762 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
10763 /* 25Gb link speed */
10764 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
10765 /* 10Gb link speed */
10766 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
10767 /* 20Mb link speed */
10768 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
10769 /* 25Gb link speed */
10770 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
10771 /* 40Gb link speed */
10772 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
10773 /* 50Gb link speed */
10774 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
10775 /* 100Gb link speed */
10776 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
10777 /* 10Mb link speed */
10778 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
10779 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
10780 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
10782 * This value is used to identify what autoneg mode is
10783 * used when the link speed is not being forced.
10786 /* Disable autoneg or autoneg disabled. No speeds are selected. */
10787 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
10788 /* Select all possible speeds for autoneg mode. */
10789 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
10791 * Select only the auto_link_speed speed for autoneg mode. This mode has
10792 * been DEPRECATED. An HWRM client should not use this mode.
10794 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
10796 * Select the auto_link_speed or any speed below that speed for autoneg.
10797 * This mode has been DEPRECATED. An HWRM client should not use this mode.
10799 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
10801 * Select the speeds based on the corresponding link speed mask value
10802 * that is provided.
10804 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
10805 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
10806 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
10808 * This is the duplex setting that will be used if the autoneg_mode
10809 * is "one_speed" or "one_or_below".
10811 uint8_t auto_duplex;
10812 /* Half Duplex will be requested. */
10813 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
10814 /* Full duplex will be requested. */
10815 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
10816 /* Both Half and Full dupex will be requested. */
10817 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
10818 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
10819 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
10821 * This value is used to configure the pause that will be
10822 * used for autonegotiation.
10823 * Add text on the usage of auto_pause and force_pause.
10825 uint8_t auto_pause;
10827 * When this bit is '1', Generation of tx pause messages
10828 * has been requested. Disabled otherwise.
10830 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
10833 * When this bit is '1', Reception of rx pause messages
10834 * has been requested. Disabled otherwise.
10836 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
10839 * When set to 1, the advertisement of pause is enabled.
10841 * # When the auto_mode is not set to none and this flag is
10842 * set to 1, then the auto_pause bits on this port are being
10843 * advertised and autoneg pause results are being interpreted.
10844 * # When the auto_mode is not set to none and this
10845 * flag is set to 0, the pause is forced as indicated in
10846 * force_pause, and also advertised as auto_pause bits, but
10847 * the autoneg results are not interpreted since the pause
10848 * configuration is being forced.
10849 * # When the auto_mode is set to none and this flag is set to
10850 * 1, auto_pause bits should be ignored and should be set to 0.
10852 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
10856 * This is the speed that will be used if the autoneg_mode
10857 * is "one_speed" or "one_or_below". If an unsupported speed
10858 * is selected, an error will be generated.
10860 uint16_t auto_link_speed;
10861 /* 100Mb link speed */
10862 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
10863 /* 1Gb link speed */
10864 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
10865 /* 2Gb link speed */
10866 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
10867 /* 25Gb link speed */
10868 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
10869 /* 10Gb link speed */
10870 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
10871 /* 20Mb link speed */
10872 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
10873 /* 25Gb link speed */
10874 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
10875 /* 40Gb link speed */
10876 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
10877 /* 50Gb link speed */
10878 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
10879 /* 100Gb link speed */
10880 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
10881 /* 10Mb link speed */
10882 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
10883 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
10884 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
10886 * This is a mask of link speeds that will be used if
10887 * autoneg_mode is "mask". If unsupported speed is enabled
10888 * an error will be generated.
10890 uint16_t auto_link_speed_mask;
10891 /* 100Mb link speed (Half-duplex) */
10892 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
10894 /* 100Mb link speed (Full-duplex) */
10895 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
10897 /* 1Gb link speed (Half-duplex) */
10898 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
10900 /* 1Gb link speed (Full-duplex) */
10901 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
10903 /* 2Gb link speed */
10904 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
10906 /* 25Gb link speed */
10907 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
10909 /* 10Gb link speed */
10910 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
10912 /* 20Gb link speed */
10913 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
10915 /* 25Gb link speed */
10916 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
10918 /* 40Gb link speed */
10919 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
10921 /* 50Gb link speed */
10922 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
10924 /* 100Gb link speed */
10925 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
10927 /* 10Mb link speed (Half-duplex) */
10928 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
10930 /* 10Mb link speed (Full-duplex) */
10931 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
10933 /* This value controls the wirespeed feature. */
10935 /* Wirespeed feature is disabled. */
10936 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
10937 /* Wirespeed feature is enabled. */
10938 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
10939 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
10940 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
10941 /* This value controls the loopback setting for the PHY. */
10943 /* No loopback is selected. Normal operation. */
10944 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
10946 * The HW will be configured with local loopback such that
10947 * host data is sent back to the host without modification.
10949 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
10951 * The HW will be configured with remote loopback such that
10952 * port logic will send packets back out the transmitter that
10955 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
10957 * The HW will be configured with external loopback such that
10958 * host data is sent on the trasmitter and based on the external
10959 * loopback connection the data will be received without modification.
10961 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
10962 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
10963 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
10965 * This value is used to configure the pause that will be
10966 * used for force mode.
10968 uint8_t force_pause;
10970 * When this bit is '1', Generation of tx pause messages
10971 * is supported. Disabled otherwise.
10973 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
10975 * When this bit is '1', Reception of rx pause messages
10976 * is supported. Disabled otherwise.
10978 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
10981 * This value controls the pre-emphasis to be used for the
10982 * link. Driver should not set this value (use
10983 * enable.preemphasis = 0) unless driver is sure of setting.
10984 * Normally HWRM FW will determine proper pre-emphasis.
10986 uint32_t preemphasis;
10988 * Setting for link speed mask that is used to
10989 * advertise speeds during autonegotiation when EEE is enabled.
10990 * This field is valid only when EEE is enabled.
10991 * The speeds specified in this field shall be a subset of
10992 * speeds specified in auto_link_speed_mask.
10993 * If EEE is enabled,then at least one speed shall be provided
10996 uint16_t eee_link_speed_mask;
10998 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
11000 /* 100Mb link speed (Full-duplex) */
11001 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
11004 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
11006 /* 1Gb link speed (Full-duplex) */
11007 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
11010 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
11013 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
11015 /* 10Gb link speed */
11016 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
11018 uint8_t unused_2[2];
11020 * Reuested setting of TX LPI timer in microseconds.
11021 * This field is valid only when EEE is enabled and TX LPI is
11024 uint32_t tx_lpi_timer;
11025 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
11026 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
11028 } __attribute__((packed));
11030 /* hwrm_port_phy_cfg_output (size:128b/16B) */
11031 struct hwrm_port_phy_cfg_output {
11032 /* The specific error status for the command. */
11033 uint16_t error_code;
11034 /* The HWRM command request type. */
11036 /* The sequence ID from the original command. */
11038 /* The length of the response data in number of bytes. */
11040 uint8_t unused_0[7];
11042 * This field is used in Output records to indicate that the output
11043 * is completely written to RAM. This field should be read as '1'
11044 * to indicate that the output has been completely written.
11045 * When writing a command completion or response to an internal processor,
11046 * the order of writes has to be such that this field is written last.
11049 } __attribute__((packed));
11051 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
11052 struct hwrm_port_phy_cfg_cmd_err {
11054 * command specific error codes that goes to
11055 * the cmd_err field in Common HWRM Error Response.
11058 /* Unknown error */
11059 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
11060 /* Unable to complete operation due to invalid speed */
11061 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
11063 * retry the command since the phy is not ready.
11064 * retry count is returned in opaque_0.
11065 * This is only valid for the first command and
11066 * this value will not change for successive calls.
11067 * but if a 0 is returned at any time then this should
11068 * be treated as an un recoverable failure,
11070 * retry interval in milli seconds is returned in opaque_1.
11071 * This specifies the time that user should wait before
11072 * issuing the next port_phy_cfg command.
11074 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
11075 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
11076 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
11077 uint8_t unused_0[7];
11078 } __attribute__((packed));
11080 /**********************
11081 * hwrm_port_phy_qcfg *
11082 **********************/
11085 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
11086 struct hwrm_port_phy_qcfg_input {
11087 /* The HWRM command request type. */
11090 * The completion ring to send the completion event on. This should
11091 * be the NQ ID returned from the `nq_alloc` HWRM command.
11093 uint16_t cmpl_ring;
11095 * The sequence ID is used by the driver for tracking multiple
11096 * commands. This ID is treated as opaque data by the firmware and
11097 * the value is returned in the `hwrm_resp_hdr` upon completion.
11101 * The target ID of the command:
11102 * * 0x0-0xFFF8 - The function ID
11103 * * 0xFFF8-0xFFFE - Reserved for internal processors
11106 uint16_t target_id;
11108 * A physical address pointer pointing to a host buffer that the
11109 * command's response data will be written. This can be either a host
11110 * physical address (HPA) or a guest physical address (GPA) and must
11111 * point to a physically contiguous block of memory.
11113 uint64_t resp_addr;
11114 /* Port ID of port that is to be queried. */
11116 uint8_t unused_0[6];
11117 } __attribute__((packed));
11119 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
11120 struct hwrm_port_phy_qcfg_output {
11121 /* The specific error status for the command. */
11122 uint16_t error_code;
11123 /* The HWRM command request type. */
11125 /* The sequence ID from the original command. */
11127 /* The length of the response data in number of bytes. */
11129 /* This value indicates the current link status. */
11131 /* There is no link or cable detected. */
11132 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
11133 /* There is no link, but a cable has been detected. */
11134 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
11135 /* There is a link. */
11136 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
11137 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
11138 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
11140 /* This value indicates the current link speed of the connection. */
11141 uint16_t link_speed;
11142 /* 100Mb link speed */
11143 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
11144 /* 1Gb link speed */
11145 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
11146 /* 2Gb link speed */
11147 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
11148 /* 25Gb link speed */
11149 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
11150 /* 10Gb link speed */
11151 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
11152 /* 20Mb link speed */
11153 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
11154 /* 25Gb link speed */
11155 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
11156 /* 40Gb link speed */
11157 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
11158 /* 50Gb link speed */
11159 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
11160 /* 100Gb link speed */
11161 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
11162 /* 10Mb link speed */
11163 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
11164 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
11165 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
11167 * This value is indicates the duplex of the current
11170 uint8_t duplex_cfg;
11171 /* Half Duplex connection. */
11172 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
11173 /* Full duplex connection. */
11174 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
11175 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
11176 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
11178 * This value is used to indicate the current
11179 * pause configuration. When autoneg is enabled, this value
11180 * represents the autoneg results of pause configuration.
11184 * When this bit is '1', Generation of tx pause messages
11185 * is supported. Disabled otherwise.
11187 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
11189 * When this bit is '1', Reception of rx pause messages
11190 * is supported. Disabled otherwise.
11192 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
11194 * The supported speeds for the port. This is a bit mask.
11195 * For each speed that is supported, the corrresponding
11196 * bit will be set to '1'.
11198 uint16_t support_speeds;
11199 /* 100Mb link speed (Half-duplex) */
11200 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
11202 /* 100Mb link speed (Full-duplex) */
11203 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
11205 /* 1Gb link speed (Half-duplex) */
11206 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
11208 /* 1Gb link speed (Full-duplex) */
11209 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
11211 /* 2Gb link speed */
11212 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
11214 /* 25Gb link speed */
11215 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
11217 /* 10Gb link speed */
11218 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
11220 /* 20Gb link speed */
11221 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
11223 /* 25Gb link speed */
11224 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
11226 /* 40Gb link speed */
11227 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
11229 /* 50Gb link speed */
11230 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
11232 /* 100Gb link speed */
11233 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
11235 /* 10Mb link speed (Half-duplex) */
11236 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
11238 /* 10Mb link speed (Full-duplex) */
11239 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
11242 * Current setting of forced link speed.
11243 * When the link speed is not being forced, this
11244 * value shall be set to 0.
11246 uint16_t force_link_speed;
11247 /* 100Mb link speed */
11248 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
11249 /* 1Gb link speed */
11250 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
11251 /* 2Gb link speed */
11252 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
11253 /* 25Gb link speed */
11254 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
11255 /* 10Gb link speed */
11256 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
11257 /* 20Mb link speed */
11258 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
11259 /* 25Gb link speed */
11260 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
11261 /* 40Gb link speed */
11262 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
11264 /* 50Gb link speed */
11265 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
11267 /* 100Gb link speed */
11268 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
11270 /* 10Mb link speed */
11271 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
11273 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
11274 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
11275 /* Current setting of auto negotiation mode. */
11277 /* Disable autoneg or autoneg disabled. No speeds are selected. */
11278 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
11279 /* Select all possible speeds for autoneg mode. */
11280 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
11282 * Select only the auto_link_speed speed for autoneg mode. This mode has
11283 * been DEPRECATED. An HWRM client should not use this mode.
11285 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
11287 * Select the auto_link_speed or any speed below that speed for autoneg.
11288 * This mode has been DEPRECATED. An HWRM client should not use this mode.
11290 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
11292 * Select the speeds based on the corresponding link speed mask value
11293 * that is provided.
11295 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
11296 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
11297 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
11299 * Current setting of pause autonegotiation.
11300 * Move autoneg_pause flag here.
11302 uint8_t auto_pause;
11304 * When this bit is '1', Generation of tx pause messages
11305 * has been requested. Disabled otherwise.
11307 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
11310 * When this bit is '1', Reception of rx pause messages
11311 * has been requested. Disabled otherwise.
11313 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
11316 * When set to 1, the advertisement of pause is enabled.
11318 * # When the auto_mode is not set to none and this flag is
11319 * set to 1, then the auto_pause bits on this port are being
11320 * advertised and autoneg pause results are being interpreted.
11321 * # When the auto_mode is not set to none and this
11322 * flag is set to 0, the pause is forced as indicated in
11323 * force_pause, and also advertised as auto_pause bits, but
11324 * the autoneg results are not interpreted since the pause
11325 * configuration is being forced.
11326 * # When the auto_mode is set to none and this flag is set to
11327 * 1, auto_pause bits should be ignored and should be set to 0.
11329 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
11332 * Current setting for auto_link_speed. This field is only
11333 * valid when auto_mode is set to "one_speed" or "one_or_below".
11335 uint16_t auto_link_speed;
11336 /* 100Mb link speed */
11337 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
11338 /* 1Gb link speed */
11339 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
11340 /* 2Gb link speed */
11341 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
11342 /* 25Gb link speed */
11343 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
11344 /* 10Gb link speed */
11345 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
11346 /* 20Mb link speed */
11347 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
11348 /* 25Gb link speed */
11349 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
11350 /* 40Gb link speed */
11351 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
11352 /* 50Gb link speed */
11353 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
11354 /* 100Gb link speed */
11355 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
11356 /* 10Mb link speed */
11357 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
11359 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
11360 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
11362 * Current setting for auto_link_speed_mask that is used to
11363 * advertise speeds during autonegotiation.
11364 * This field is only valid when auto_mode is set to "mask".
11365 * The speeds specified in this field shall be a subset of
11366 * supported speeds on this port.
11368 uint16_t auto_link_speed_mask;
11369 /* 100Mb link speed (Half-duplex) */
11370 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
11372 /* 100Mb link speed (Full-duplex) */
11373 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
11375 /* 1Gb link speed (Half-duplex) */
11376 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
11378 /* 1Gb link speed (Full-duplex) */
11379 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
11381 /* 2Gb link speed */
11382 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
11384 /* 25Gb link speed */
11385 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
11387 /* 10Gb link speed */
11388 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
11390 /* 20Gb link speed */
11391 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
11393 /* 25Gb link speed */
11394 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
11396 /* 40Gb link speed */
11397 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
11399 /* 50Gb link speed */
11400 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
11402 /* 100Gb link speed */
11403 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
11405 /* 10Mb link speed (Half-duplex) */
11406 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
11408 /* 10Mb link speed (Full-duplex) */
11409 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
11411 /* Current setting for wirespeed. */
11413 /* Wirespeed feature is disabled. */
11414 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
11415 /* Wirespeed feature is enabled. */
11416 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
11417 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
11418 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
11419 /* Current setting for loopback. */
11421 /* No loopback is selected. Normal operation. */
11422 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11424 * The HW will be configured with local loopback such that
11425 * host data is sent back to the host without modification.
11427 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11429 * The HW will be configured with remote loopback such that
11430 * port logic will send packets back out the transmitter that
11433 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11435 * The HW will be configured with external loopback such that
11436 * host data is sent on the trasmitter and based on the external
11437 * loopback connection the data will be received without modification.
11439 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
11440 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
11441 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
11443 * Current setting of forced pause.
11444 * When the pause configuration is not being forced, then
11445 * this value shall be set to 0.
11447 uint8_t force_pause;
11449 * When this bit is '1', Generation of tx pause messages
11450 * is supported. Disabled otherwise.
11452 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
11454 * When this bit is '1', Reception of rx pause messages
11455 * is supported. Disabled otherwise.
11457 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
11459 * This value indicates the current status of the optics module on
11462 uint8_t module_status;
11463 /* Module is inserted and accepted */
11464 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
11466 /* Module is rejected and transmit side Laser is disabled. */
11467 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
11469 /* Module mismatch warning. */
11470 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
11472 /* Module is rejected and powered down. */
11473 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
11475 /* Module is not inserted. */
11476 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
11478 /* Module status is not applicable. */
11479 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
11481 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
11482 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
11483 /* Current setting for preemphasis. */
11484 uint32_t preemphasis;
11485 /* This field represents the major version of the PHY. */
11487 /* This field represents the minor version of the PHY. */
11489 /* This field represents the build version of the PHY. */
11491 /* This value represents a PHY type. */
11494 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
11497 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
11499 /* BASE-KR4 (Deprecated) */
11500 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
11503 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
11506 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
11508 /* BASE-KR2 (Deprecated) */
11509 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
11512 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
11515 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
11518 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
11520 /* EEE capable BASE-T */
11521 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
11523 /* SGMII connected external PHY */
11524 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
11526 /* 25G_BASECR_CA_L */
11527 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
11529 /* 25G_BASECR_CA_S */
11530 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
11532 /* 25G_BASECR_CA_N */
11533 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
11536 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
11539 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
11542 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
11545 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
11548 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
11550 /* 100G_BASESR10 */
11551 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
11554 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
11557 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
11560 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
11563 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
11565 /* 40G_ACTIVE_CABLE */
11566 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
11569 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
11572 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
11575 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
11577 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
11578 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
11579 /* This value represents a media type. */
11580 uint8_t media_type;
11582 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
11584 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
11585 /* Direct Attached Copper */
11586 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
11588 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
11589 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
11590 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
11591 /* This value represents a transceiver type. */
11592 uint8_t xcvr_pkg_type;
11593 /* PHY and MAC are in the same package */
11594 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
11596 /* PHY and MAC are in different packages */
11597 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
11599 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
11600 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
11601 uint8_t eee_config_phy_addr;
11602 /* This field represents PHY address. */
11603 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
11605 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
11607 * This field represents flags related to EEE configuration.
11608 * These EEE configuration flags are valid only when the
11609 * auto_mode is not set to none (in other words autonegotiation
11612 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
11614 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
11616 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
11617 * Speeds for autoneg with EEE mode enabled
11618 * are based on eee_link_speed_mask.
11620 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
11623 * This flag is valid only when eee_enabled is set to 1.
11625 * # If eee_enabled is set to 0, then EEE mode is disabled
11626 * and this flag shall be ignored.
11627 * # If eee_enabled is set to 1 and this flag is set to 1,
11628 * then Energy Efficient Ethernet (EEE) mode is enabled
11630 * # If eee_enabled is set to 1 and this flag is set to 0,
11631 * then Energy Efficient Ethernet (EEE) mode is enabled
11632 * but is currently not in use.
11634 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
11637 * This flag is valid only when eee_enabled is set to 1.
11639 * # If eee_enabled is set to 0, then EEE mode is disabled
11640 * and this flag shall be ignored.
11641 * # If eee_enabled is set to 1 and this flag is set to 1,
11642 * then Energy Efficient Ethernet (EEE) mode is enabled
11643 * and TX LPI is enabled.
11644 * # If eee_enabled is set to 1 and this flag is set to 0,
11645 * then Energy Efficient Ethernet (EEE) mode is enabled
11646 * but TX LPI is disabled.
11648 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
11651 * When set to 1, the parallel detection is used to determine
11652 * the speed of the link partner.
11654 * Parallel detection is used when a autonegotiation capable
11655 * device is connected to a link parter that is not capable
11656 * of autonegotiation.
11658 uint8_t parallel_detect;
11660 * When set to 1, the parallel detection is used to determine
11661 * the speed of the link partner.
11663 * Parallel detection is used when a autonegotiation capable
11664 * device is connected to a link parter that is not capable
11665 * of autonegotiation.
11667 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
11669 * The advertised speeds for the port by the link partner.
11670 * Each advertised speed will be set to '1'.
11672 uint16_t link_partner_adv_speeds;
11673 /* 100Mb link speed (Half-duplex) */
11674 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
11676 /* 100Mb link speed (Full-duplex) */
11677 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
11679 /* 1Gb link speed (Half-duplex) */
11680 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
11682 /* 1Gb link speed (Full-duplex) */
11683 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
11685 /* 2Gb link speed */
11686 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
11688 /* 25Gb link speed */
11689 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
11691 /* 10Gb link speed */
11692 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
11694 /* 20Gb link speed */
11695 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
11697 /* 25Gb link speed */
11698 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
11700 /* 40Gb link speed */
11701 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
11703 /* 50Gb link speed */
11704 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
11706 /* 100Gb link speed */
11707 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
11709 /* 10Mb link speed (Half-duplex) */
11710 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
11712 /* 10Mb link speed (Full-duplex) */
11713 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
11716 * The advertised autoneg for the port by the link partner.
11717 * This field is deprecated and should be set to 0.
11719 uint8_t link_partner_adv_auto_mode;
11720 /* Disable autoneg or autoneg disabled. No speeds are selected. */
11721 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
11723 /* Select all possible speeds for autoneg mode. */
11724 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
11727 * Select only the auto_link_speed speed for autoneg mode. This mode has
11728 * been DEPRECATED. An HWRM client should not use this mode.
11730 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
11733 * Select the auto_link_speed or any speed below that speed for autoneg.
11734 * This mode has been DEPRECATED. An HWRM client should not use this mode.
11736 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
11739 * Select the speeds based on the corresponding link speed mask value
11740 * that is provided.
11742 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
11744 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
11745 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
11746 /* The advertised pause settings on the port by the link partner. */
11747 uint8_t link_partner_adv_pause;
11749 * When this bit is '1', Generation of tx pause messages
11750 * is supported. Disabled otherwise.
11752 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
11755 * When this bit is '1', Reception of rx pause messages
11756 * is supported. Disabled otherwise.
11758 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
11761 * Current setting for link speed mask that is used to
11762 * advertise speeds during autonegotiation when EEE is enabled.
11763 * This field is valid only when eee_enabled flags is set to 1.
11764 * The speeds specified in this field shall be a subset of
11765 * speeds specified in auto_link_speed_mask.
11767 uint16_t adv_eee_link_speed_mask;
11769 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
11771 /* 100Mb link speed (Full-duplex) */
11772 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
11775 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
11777 /* 1Gb link speed (Full-duplex) */
11778 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
11781 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
11784 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
11786 /* 10Gb link speed */
11787 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
11790 * Current setting for link speed mask that is advertised by
11791 * the link partner when EEE is enabled.
11792 * This field is valid only when eee_enabled flags is set to 1.
11794 uint16_t link_partner_adv_eee_link_speed_mask;
11796 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
11798 /* 100Mb link speed (Full-duplex) */
11799 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
11802 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
11804 /* 1Gb link speed (Full-duplex) */
11805 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
11808 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
11811 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
11813 /* 10Gb link speed */
11814 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
11816 uint32_t xcvr_identifier_type_tx_lpi_timer;
11818 * Current setting of TX LPI timer in microseconds.
11819 * This field is valid only when_eee_enabled flag is set to 1
11820 * and tx_lpi_enabled is set to 1.
11822 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
11824 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
11825 /* This value represents transceiver identifier type. */
11826 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
11827 UINT32_C(0xff000000)
11828 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
11830 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
11831 (UINT32_C(0x0) << 24)
11832 /* SFP/SFP+/SFP28 */
11833 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
11834 (UINT32_C(0x3) << 24)
11836 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
11837 (UINT32_C(0xc) << 24)
11839 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
11840 (UINT32_C(0xd) << 24)
11842 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
11843 (UINT32_C(0x11) << 24)
11844 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
11845 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
11847 * This value represents the current configuration of
11848 * Forward Error Correction (FEC) on the port.
11852 * When set to 1, then FEC is not supported on this port. If this flag
11853 * is set to 1, then all other FEC configuration flags shall be ignored.
11854 * When set to 0, then FEC is supported as indicated by other
11855 * configuration flags.
11856 * If no cable is attached and the HWRM does not yet know the FEC
11857 * capability, then the HWRM shall set this flag to 1 when reporting
11860 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
11863 * When set to 1, then FEC autonegotiation is supported on this port.
11864 * When set to 0, then FEC autonegotiation is not supported on this port.
11866 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
11869 * When set to 1, then FEC autonegotiation is enabled on this port.
11870 * When set to 0, then FEC autonegotiation is disabled if supported.
11871 * This flag should be ignored if FEC autonegotiation is not supported on this port.
11873 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
11876 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
11877 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
11879 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
11882 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
11883 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
11884 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
11886 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
11889 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
11890 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
11892 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
11895 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
11896 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
11897 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
11899 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
11902 * This value is indicates the duplex of the current
11903 * connection state.
11905 uint8_t duplex_state;
11906 /* Half Duplex connection. */
11907 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
11908 /* Full duplex connection. */
11909 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
11910 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
11911 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
11912 /* Option flags fields. */
11913 uint8_t option_flags;
11914 /* When this bit is '1', Media auto detect is enabled. */
11915 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
11918 * Up to 16 bytes of null padded ASCII string representing
11920 * If the string is set to null, then the vendor name is not
11923 char phy_vendor_name[16];
11925 * Up to 16 bytes of null padded ASCII string that
11926 * identifies vendor specific part number of the PHY.
11927 * If the string is set to null, then the vendor specific
11928 * part number is not available.
11930 char phy_vendor_partnumber[16];
11931 uint8_t unused_2[7];
11933 * This field is used in Output records to indicate that the output
11934 * is completely written to RAM. This field should be read as '1'
11935 * to indicate that the output has been completely written.
11936 * When writing a command completion or response to an internal processor,
11937 * the order of writes has to be such that this field is written last.
11940 } __attribute__((packed));
11942 /*********************
11943 * hwrm_port_mac_cfg *
11944 *********************/
11947 /* hwrm_port_mac_cfg_input (size:320b/40B) */
11948 struct hwrm_port_mac_cfg_input {
11949 /* The HWRM command request type. */
11952 * The completion ring to send the completion event on. This should
11953 * be the NQ ID returned from the `nq_alloc` HWRM command.
11955 uint16_t cmpl_ring;
11957 * The sequence ID is used by the driver for tracking multiple
11958 * commands. This ID is treated as opaque data by the firmware and
11959 * the value is returned in the `hwrm_resp_hdr` upon completion.
11963 * The target ID of the command:
11964 * * 0x0-0xFFF8 - The function ID
11965 * * 0xFFF8-0xFFFE - Reserved for internal processors
11968 uint16_t target_id;
11970 * A physical address pointer pointing to a host buffer that the
11971 * command's response data will be written. This can be either a host
11972 * physical address (HPA) or a guest physical address (GPA) and must
11973 * point to a physically contiguous block of memory.
11975 uint64_t resp_addr;
11977 * In this field, there are a number of CoS mappings related flags
11978 * that are used to configure CoS mappings and their corresponding
11979 * priorities in the hardware.
11980 * For the priorities of CoS mappings, the HWRM uses the following
11981 * priority order (high to low) by default:
11984 * # tunnel_vlan_pri
11987 * A subset of CoS mappings can be enabled.
11988 * If a priority is not specified for an enabled CoS mapping, the
11989 * priority will be assigned in the above order for the enabled CoS
11990 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
11991 * enabled and their priorities are not specified, the following
11992 * priority order (high to low) will be used by the HWRM:
11997 * vlan_pri CoS mapping together with default CoS with lower priority
11998 * are enabled by default by the HWRM.
12002 * When this bit is '1', this command will configure
12003 * the MAC to match the current link state of the PHY.
12004 * If the link is not established on the PHY, then this
12005 * bit has no effect.
12007 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
12010 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12011 * is requested to be enabled.
12013 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
12016 * When this bit is set to '1', tunnel VLAN PRI field to
12017 * CoS mapping is requested to be enabled.
12019 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
12022 * When this bit is set to '1', the IP DSCP to CoS mapping is
12023 * requested to be enabled.
12025 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
12028 * When this bit is '1', the HWRM is requested to
12029 * enable timestamp capture capability on the receive side
12032 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
12035 * When this bit is '1', the HWRM is requested to
12036 * disable timestamp capture capability on the receive side
12039 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
12042 * When this bit is '1', the HWRM is requested to
12043 * enable timestamp capture capability on the transmit side
12046 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
12049 * When this bit is '1', the HWRM is requested to
12050 * disable timestamp capture capability on the transmit side
12053 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
12056 * When this bit is '1', the Out-Of-Box WoL is requested to
12057 * be enabled on this port.
12059 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
12062 * When this bit is '1', the the Out-Of-Box WoL is requested to
12063 * be disabled on this port.
12065 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
12068 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12069 * is requested to be disabled.
12071 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
12074 * When this bit is set to '1', tunnel VLAN PRI field to
12075 * CoS mapping is requested to be disabled.
12077 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
12080 * When this bit is set to '1', the IP DSCP to CoS mapping is
12081 * requested to be disabled.
12083 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
12087 * This bit must be '1' for the ipg field to be
12090 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
12093 * This bit must be '1' for the lpbk field to be
12096 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
12099 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
12102 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
12105 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
12108 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
12111 * This bit must be '1' for the dscp2cos_map_pri field to be
12114 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
12117 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
12120 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
12123 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
12126 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
12129 * This bit must be '1' for the cos_field_cfg field to be
12132 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
12134 /* Port ID of port that is to be configured. */
12137 * This value is used to configure the minimum IPG that will
12138 * be sent between packets by this port.
12141 /* This value controls the loopback setting for the MAC. */
12143 /* No loopback is selected. Normal operation. */
12144 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
12146 * The HW will be configured with local loopback such that
12147 * host data is sent back to the host without modification.
12149 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
12151 * The HW will be configured with remote loopback such that
12152 * port logic will send packets back out the transmitter that
12155 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
12156 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
12157 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
12159 * This value controls the priority setting of VLAN PRI to CoS
12160 * mapping based on VLAN Tags of inner packet headers of
12161 * tunneled packets or packet headers of non-tunneled packets.
12163 * # Each XXX_pri variable shall have a unique priority value
12164 * when it is being specified.
12165 * # When comparing priorities of mappings, higher value
12166 * indicates higher priority.
12167 * For example, a value of 0-3 is returned where 0 is being
12168 * the lowest priority and 3 is being the highest priority.
12170 uint8_t vlan_pri2cos_map_pri;
12171 /* Reserved field. */
12174 * This value controls the priority setting of VLAN PRI to CoS
12175 * mapping based on VLAN Tags of tunneled header.
12176 * This mapping only applies when tunneled headers
12179 * # Each XXX_pri variable shall have a unique priority value
12180 * when it is being specified.
12181 * # When comparing priorities of mappings, higher value
12182 * indicates higher priority.
12183 * For example, a value of 0-3 is returned where 0 is being
12184 * the lowest priority and 3 is being the highest priority.
12186 uint8_t tunnel_pri2cos_map_pri;
12188 * This value controls the priority setting of IP DSCP to CoS
12189 * mapping based on inner IP header of tunneled packets or
12190 * IP header of non-tunneled packets.
12192 * # Each XXX_pri variable shall have a unique priority value
12193 * when it is being specified.
12194 * # When comparing priorities of mappings, higher value
12195 * indicates higher priority.
12196 * For example, a value of 0-3 is returned where 0 is being
12197 * the lowest priority and 3 is being the highest priority.
12199 uint8_t dscp2pri_map_pri;
12201 * This is a 16-bit bit mask that is used to request a
12202 * specific configuration of time stamp capture of PTP messages
12203 * on the receive side of this port.
12204 * This field shall be ignored if the ptp_rx_ts_capture_enable
12205 * flag is not set in this command.
12206 * Otherwise, if bit 'i' is set, then the HWRM is being
12207 * requested to configure the receive side of the port to
12208 * capture the time stamp of every received PTP message
12209 * with messageType field value set to i.
12211 uint16_t rx_ts_capture_ptp_msg_type;
12213 * This is a 16-bit bit mask that is used to request a
12214 * specific configuration of time stamp capture of PTP messages
12215 * on the transmit side of this port.
12216 * This field shall be ignored if the ptp_tx_ts_capture_enable
12217 * flag is not set in this command.
12218 * Otherwise, if bit 'i' is set, then the HWRM is being
12219 * requested to configure the transmit sied of the port to
12220 * capture the time stamp of every transmitted PTP message
12221 * with messageType field value set to i.
12223 uint16_t tx_ts_capture_ptp_msg_type;
12224 /* Configuration of CoS fields. */
12225 uint8_t cos_field_cfg;
12227 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
12230 * This field is used to specify selection of VLAN PRI value
12231 * based on whether one or two VLAN Tags are present in
12232 * the inner packet headers of tunneled packets or
12233 * non-tunneled packets.
12234 * This field is valid only if inner VLAN PRI to CoS mapping
12236 * If VLAN PRI to CoS mapping is not enabled, then this
12237 * field shall be ignored.
12239 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
12241 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
12244 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12245 * present in the inner packet headers
12247 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
12248 (UINT32_C(0x0) << 1)
12250 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12251 * present in the inner packet headers.
12252 * No VLAN PRI shall be selected for this configuration
12253 * if only one VLAN Tag is present in the inner
12256 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
12257 (UINT32_C(0x1) << 1)
12259 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12260 * are present in the inner packet headers
12262 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
12263 (UINT32_C(0x2) << 1)
12265 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
12266 (UINT32_C(0x3) << 1)
12267 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
12268 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
12270 * This field is used to specify selection of tunnel VLAN
12271 * PRI value based on whether one or two VLAN Tags are
12272 * present in tunnel headers.
12273 * This field is valid only if tunnel VLAN PRI to CoS mapping
12275 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
12276 * field shall be ignored.
12278 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
12280 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
12283 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12284 * present in the tunnel packet headers
12286 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
12287 (UINT32_C(0x0) << 3)
12289 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12290 * present in the tunnel packet headers.
12291 * No tunnel VLAN PRI shall be selected for this
12292 * configuration if only one VLAN Tag is present in
12293 * the tunnel packet headers.
12295 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
12296 (UINT32_C(0x1) << 3)
12298 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12299 * are present in the tunnel packet headers
12301 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
12302 (UINT32_C(0x2) << 3)
12304 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
12305 (UINT32_C(0x3) << 3)
12306 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
12307 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
12309 * This field shall be used to provide default CoS value
12310 * that has been configured on this port.
12311 * This field is valid only if default CoS mapping
12313 * If default CoS mapping is not enabled, then this
12314 * field shall be ignored.
12316 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
12318 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
12320 uint8_t unused_0[3];
12321 } __attribute__((packed));
12323 /* hwrm_port_mac_cfg_output (size:128b/16B) */
12324 struct hwrm_port_mac_cfg_output {
12325 /* The specific error status for the command. */
12326 uint16_t error_code;
12327 /* The HWRM command request type. */
12329 /* The sequence ID from the original command. */
12331 /* The length of the response data in number of bytes. */
12334 * This is the configured maximum length of Ethernet packet
12335 * payload that is allowed to be received on the port.
12336 * This value does not include the number of bytes used by
12337 * Ethernet header and trailer (CRC).
12341 * This is the configured maximum length of Ethernet packet
12342 * payload that is allowed to be transmitted on the port.
12343 * This value does not include the number of bytes used by
12344 * Ethernet header and trailer (CRC).
12347 /* Current configuration of the IPG value. */
12349 /* Current value of the loopback value. */
12351 /* No loopback is selected. Normal operation. */
12352 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
12354 * The HW will be configured with local loopback such that
12355 * host data is sent back to the host without modification.
12357 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
12359 * The HW will be configured with remote loopback such that
12360 * port logic will send packets back out the transmitter that
12363 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
12364 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
12365 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
12368 * This field is used in Output records to indicate that the output
12369 * is completely written to RAM. This field should be read as '1'
12370 * to indicate that the output has been completely written.
12371 * When writing a command completion or response to an internal processor,
12372 * the order of writes has to be such that this field is written last.
12375 } __attribute__((packed));
12377 /**********************
12378 * hwrm_port_mac_qcfg *
12379 **********************/
12382 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
12383 struct hwrm_port_mac_qcfg_input {
12384 /* The HWRM command request type. */
12387 * The completion ring to send the completion event on. This should
12388 * be the NQ ID returned from the `nq_alloc` HWRM command.
12390 uint16_t cmpl_ring;
12392 * The sequence ID is used by the driver for tracking multiple
12393 * commands. This ID is treated as opaque data by the firmware and
12394 * the value is returned in the `hwrm_resp_hdr` upon completion.
12398 * The target ID of the command:
12399 * * 0x0-0xFFF8 - The function ID
12400 * * 0xFFF8-0xFFFE - Reserved for internal processors
12403 uint16_t target_id;
12405 * A physical address pointer pointing to a host buffer that the
12406 * command's response data will be written. This can be either a host
12407 * physical address (HPA) or a guest physical address (GPA) and must
12408 * point to a physically contiguous block of memory.
12410 uint64_t resp_addr;
12411 /* Port ID of port that is to be configured. */
12413 uint8_t unused_0[6];
12414 } __attribute__((packed));
12416 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
12417 struct hwrm_port_mac_qcfg_output {
12418 /* The specific error status for the command. */
12419 uint16_t error_code;
12420 /* The HWRM command request type. */
12422 /* The sequence ID from the original command. */
12424 /* The length of the response data in number of bytes. */
12427 * This is the configured maximum length of Ethernet packet
12428 * payload that is allowed to be received on the port.
12429 * This value does not include the number of bytes used by the
12430 * Ethernet header and trailer (CRC).
12434 * This is the configured maximum length of Ethernet packet
12435 * payload that is allowed to be transmitted on the port.
12436 * This value does not include the number of bytes used by the
12437 * Ethernet header and trailer (CRC).
12441 * The minimum IPG that will
12442 * be sent between packets by this port.
12445 /* The loopback setting for the MAC. */
12447 /* No loopback is selected. Normal operation. */
12448 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
12450 * The HW will be configured with local loopback such that
12451 * host data is sent back to the host without modification.
12453 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
12455 * The HW will be configured with remote loopback such that
12456 * port logic will send packets back out the transmitter that
12459 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
12460 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
12461 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
12463 * Priority setting for VLAN PRI to CoS mapping.
12464 * # Each XXX_pri variable shall have a unique priority value
12465 * when it is being used.
12466 * # When comparing priorities of mappings, higher value
12467 * indicates higher priority.
12468 * For example, a value of 0-3 is returned where 0 is being
12469 * the lowest priority and 3 is being the highest priority.
12470 * # If the correspoding CoS mapping is not enabled, then this
12471 * field should be ignored.
12472 * # This value indicates the normalized priority value retained
12475 uint8_t vlan_pri2cos_map_pri;
12477 * In this field, a number of CoS mappings related flags
12478 * are used to indicate configured CoS mappings.
12482 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
12485 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
12488 * When this bit is set to '1', tunnel VLAN PRI field to
12489 * CoS mapping is enabled.
12491 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
12494 * When this bit is set to '1', the IP DSCP to CoS mapping is
12497 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
12500 * When this bit is '1', the Out-Of-Box WoL is enabled on this
12503 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
12505 /* When this bit is '1', PTP is enabled for RX on this port. */
12506 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
12508 /* When this bit is '1', PTP is enabled for TX on this port. */
12509 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
12512 * Priority setting for tunnel VLAN PRI to CoS mapping.
12513 * # Each XXX_pri variable shall have a unique priority value
12514 * when it is being used.
12515 * # When comparing priorities of mappings, higher value
12516 * indicates higher priority.
12517 * For example, a value of 0-3 is returned where 0 is being
12518 * the lowest priority and 3 is being the highest priority.
12519 * # If the correspoding CoS mapping is not enabled, then this
12520 * field should be ignored.
12521 * # This value indicates the normalized priority value retained
12524 uint8_t tunnel_pri2cos_map_pri;
12526 * Priority setting for DSCP to PRI mapping.
12527 * # Each XXX_pri variable shall have a unique priority value
12528 * when it is being used.
12529 * # When comparing priorities of mappings, higher value
12530 * indicates higher priority.
12531 * For example, a value of 0-3 is returned where 0 is being
12532 * the lowest priority and 3 is being the highest priority.
12533 * # If the correspoding CoS mapping is not enabled, then this
12534 * field should be ignored.
12535 * # This value indicates the normalized priority value retained
12538 uint8_t dscp2pri_map_pri;
12540 * This is a 16-bit bit mask that represents the
12541 * current configuration of time stamp capture of PTP messages
12542 * on the receive side of this port.
12543 * If bit 'i' is set, then the receive side of the port
12544 * is configured to capture the time stamp of every
12545 * received PTP message with messageType field value set
12547 * If all bits are set to 0 (i.e. field value set 0),
12548 * then the receive side of the port is not configured
12549 * to capture timestamp for PTP messages.
12550 * If all bits are set to 1, then the receive side of the
12551 * port is configured to capture timestamp for all PTP
12554 uint16_t rx_ts_capture_ptp_msg_type;
12556 * This is a 16-bit bit mask that represents the
12557 * current configuration of time stamp capture of PTP messages
12558 * on the transmit side of this port.
12559 * If bit 'i' is set, then the transmit side of the port
12560 * is configured to capture the time stamp of every
12561 * received PTP message with messageType field value set
12563 * If all bits are set to 0 (i.e. field value set 0),
12564 * then the transmit side of the port is not configured
12565 * to capture timestamp for PTP messages.
12566 * If all bits are set to 1, then the transmit side of the
12567 * port is configured to capture timestamp for all PTP
12570 uint16_t tx_ts_capture_ptp_msg_type;
12571 /* Configuration of CoS fields. */
12572 uint8_t cos_field_cfg;
12574 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
12577 * This field is used for selecting VLAN PRI value
12578 * based on whether one or two VLAN Tags are present in
12579 * the inner packet headers of tunneled packets or
12580 * non-tunneled packets.
12582 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
12584 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
12587 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12588 * present in the inner packet headers
12590 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
12591 (UINT32_C(0x0) << 1)
12593 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12594 * present in the inner packet headers.
12595 * No VLAN PRI is selected for this configuration
12596 * if only one VLAN Tag is present in the inner
12599 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
12600 (UINT32_C(0x1) << 1)
12602 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12603 * are present in the inner packet headers
12605 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
12606 (UINT32_C(0x2) << 1)
12608 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
12609 (UINT32_C(0x3) << 1)
12610 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
12611 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
12613 * This field is used for selecting tunnel VLAN PRI value
12614 * based on whether one or two VLAN Tags are present in
12615 * the tunnel headers of tunneled packets. This selection
12616 * does not apply to non-tunneled packets.
12618 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
12620 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
12623 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
12624 * present in the tunnel packet headers
12626 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
12627 (UINT32_C(0x0) << 3)
12629 * Select outer VLAN Tag PRI when 2 VLAN Tags are
12630 * present in the tunnel packet headers.
12631 * No VLAN PRI is selected for this configuration
12632 * if only one VLAN Tag is present in the tunnel
12635 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
12636 (UINT32_C(0x1) << 3)
12638 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
12639 * are present in the tunnel packet headers
12641 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
12642 (UINT32_C(0x2) << 3)
12644 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
12645 (UINT32_C(0x3) << 3)
12646 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
12647 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
12649 * This field is used to provide default CoS value that
12650 * has been configured on this port.
12652 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
12654 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
12657 * This field is used in Output records to indicate that the output
12658 * is completely written to RAM. This field should be read as '1'
12659 * to indicate that the output has been completely written.
12660 * When writing a command completion or response to an internal processor,
12661 * the order of writes has to be such that this field is written last.
12664 } __attribute__((packed));
12666 /**************************
12667 * hwrm_port_mac_ptp_qcfg *
12668 **************************/
12671 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
12672 struct hwrm_port_mac_ptp_qcfg_input {
12673 /* The HWRM command request type. */
12676 * The completion ring to send the completion event on. This should
12677 * be the NQ ID returned from the `nq_alloc` HWRM command.
12679 uint16_t cmpl_ring;
12681 * The sequence ID is used by the driver for tracking multiple
12682 * commands. This ID is treated as opaque data by the firmware and
12683 * the value is returned in the `hwrm_resp_hdr` upon completion.
12687 * The target ID of the command:
12688 * * 0x0-0xFFF8 - The function ID
12689 * * 0xFFF8-0xFFFE - Reserved for internal processors
12692 uint16_t target_id;
12694 * A physical address pointer pointing to a host buffer that the
12695 * command's response data will be written. This can be either a host
12696 * physical address (HPA) or a guest physical address (GPA) and must
12697 * point to a physically contiguous block of memory.
12699 uint64_t resp_addr;
12700 /* Port ID of port that is being queried. */
12702 uint8_t unused_0[6];
12703 } __attribute__((packed));
12705 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
12706 struct hwrm_port_mac_ptp_qcfg_output {
12707 /* The specific error status for the command. */
12708 uint16_t error_code;
12709 /* The HWRM command request type. */
12711 /* The sequence ID from the original command. */
12713 /* The length of the response data in number of bytes. */
12716 * In this field, a number of PTP related flags
12717 * are used to indicate configured PTP capabilities.
12721 * When this bit is set to '1', the PTP related registers are
12722 * directly accessible by the host.
12724 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
12727 * When this bit is set to '1', the PTP information is accessible
12728 * via HWRM commands.
12730 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
12732 uint8_t unused_0[3];
12733 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
12734 uint32_t rx_ts_reg_off_lower;
12735 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
12736 uint32_t rx_ts_reg_off_upper;
12737 /* Offset of the PTP register for the sequence ID for RX. */
12738 uint32_t rx_ts_reg_off_seq_id;
12739 /* Offset of the first PTP source ID for RX. */
12740 uint32_t rx_ts_reg_off_src_id_0;
12741 /* Offset of the second PTP source ID for RX. */
12742 uint32_t rx_ts_reg_off_src_id_1;
12743 /* Offset of the third PTP source ID for RX. */
12744 uint32_t rx_ts_reg_off_src_id_2;
12745 /* Offset of the domain ID for RX. */
12746 uint32_t rx_ts_reg_off_domain_id;
12747 /* Offset of the PTP FIFO register for RX. */
12748 uint32_t rx_ts_reg_off_fifo;
12749 /* Offset of the PTP advance FIFO register for RX. */
12750 uint32_t rx_ts_reg_off_fifo_adv;
12751 /* PTP timestamp granularity for RX. */
12752 uint32_t rx_ts_reg_off_granularity;
12753 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
12754 uint32_t tx_ts_reg_off_lower;
12755 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
12756 uint32_t tx_ts_reg_off_upper;
12757 /* Offset of the PTP register for the sequence ID for TX. */
12758 uint32_t tx_ts_reg_off_seq_id;
12759 /* Offset of the PTP FIFO register for TX. */
12760 uint32_t tx_ts_reg_off_fifo;
12761 /* PTP timestamp granularity for TX. */
12762 uint32_t tx_ts_reg_off_granularity;
12763 uint8_t unused_1[7];
12765 * This field is used in Output records to indicate that the output
12766 * is completely written to RAM. This field should be read as '1'
12767 * to indicate that the output has been completely written.
12768 * When writing a command completion or response to an internal processor,
12769 * the order of writes has to be such that this field is written last.
12772 } __attribute__((packed));
12774 /* Port Tx Statistics Formats */
12775 /* tx_port_stats (size:3264b/408B) */
12776 struct tx_port_stats {
12777 /* Total Number of 64 Bytes frames transmitted */
12778 uint64_t tx_64b_frames;
12779 /* Total Number of 65-127 Bytes frames transmitted */
12780 uint64_t tx_65b_127b_frames;
12781 /* Total Number of 128-255 Bytes frames transmitted */
12782 uint64_t tx_128b_255b_frames;
12783 /* Total Number of 256-511 Bytes frames transmitted */
12784 uint64_t tx_256b_511b_frames;
12785 /* Total Number of 512-1023 Bytes frames transmitted */
12786 uint64_t tx_512b_1023b_frames;
12787 /* Total Number of 1024-1518 Bytes frames transmitted */
12788 uint64_t tx_1024b_1518b_frames;
12790 * Total Number of each good VLAN (exludes FCS errors)
12791 * frame transmitted which is 1519 to 1522 bytes in length
12792 * inclusive (excluding framing bits but including FCS bytes).
12794 uint64_t tx_good_vlan_frames;
12795 /* Total Number of 1519-2047 Bytes frames transmitted */
12796 uint64_t tx_1519b_2047b_frames;
12797 /* Total Number of 2048-4095 Bytes frames transmitted */
12798 uint64_t tx_2048b_4095b_frames;
12799 /* Total Number of 4096-9216 Bytes frames transmitted */
12800 uint64_t tx_4096b_9216b_frames;
12801 /* Total Number of 9217-16383 Bytes frames transmitted */
12802 uint64_t tx_9217b_16383b_frames;
12803 /* Total Number of good frames transmitted */
12804 uint64_t tx_good_frames;
12805 /* Total Number of frames transmitted */
12806 uint64_t tx_total_frames;
12807 /* Total number of unicast frames transmitted */
12808 uint64_t tx_ucast_frames;
12809 /* Total number of multicast frames transmitted */
12810 uint64_t tx_mcast_frames;
12811 /* Total number of broadcast frames transmitted */
12812 uint64_t tx_bcast_frames;
12813 /* Total number of PAUSE control frames transmitted */
12814 uint64_t tx_pause_frames;
12816 * Total number of PFC/per-priority PAUSE
12817 * control frames transmitted
12819 uint64_t tx_pfc_frames;
12820 /* Total number of jabber frames transmitted */
12821 uint64_t tx_jabber_frames;
12822 /* Total number of frames transmitted with FCS error */
12823 uint64_t tx_fcs_err_frames;
12824 /* Total number of control frames transmitted */
12825 uint64_t tx_control_frames;
12826 /* Total number of over-sized frames transmitted */
12827 uint64_t tx_oversz_frames;
12828 /* Total number of frames with single deferral */
12829 uint64_t tx_single_dfrl_frames;
12830 /* Total number of frames with multiple deferrals */
12831 uint64_t tx_multi_dfrl_frames;
12832 /* Total number of frames with single collision */
12833 uint64_t tx_single_coll_frames;
12834 /* Total number of frames with multiple collisions */
12835 uint64_t tx_multi_coll_frames;
12836 /* Total number of frames with late collisions */
12837 uint64_t tx_late_coll_frames;
12838 /* Total number of frames with excessive collisions */
12839 uint64_t tx_excessive_coll_frames;
12840 /* Total number of fragmented frames transmitted */
12841 uint64_t tx_frag_frames;
12842 /* Total number of transmit errors */
12844 /* Total number of single VLAN tagged frames transmitted */
12845 uint64_t tx_tagged_frames;
12846 /* Total number of double VLAN tagged frames transmitted */
12847 uint64_t tx_dbl_tagged_frames;
12848 /* Total number of runt frames transmitted */
12849 uint64_t tx_runt_frames;
12850 /* Total number of TX FIFO under runs */
12851 uint64_t tx_fifo_underruns;
12853 * Total number of PFC frames with PFC enabled bit for
12854 * Pri 0 transmitted
12856 uint64_t tx_pfc_ena_frames_pri0;
12858 * Total number of PFC frames with PFC enabled bit for
12859 * Pri 1 transmitted
12861 uint64_t tx_pfc_ena_frames_pri1;
12863 * Total number of PFC frames with PFC enabled bit for
12864 * Pri 2 transmitted
12866 uint64_t tx_pfc_ena_frames_pri2;
12868 * Total number of PFC frames with PFC enabled bit for
12869 * Pri 3 transmitted
12871 uint64_t tx_pfc_ena_frames_pri3;
12873 * Total number of PFC frames with PFC enabled bit for
12874 * Pri 4 transmitted
12876 uint64_t tx_pfc_ena_frames_pri4;
12878 * Total number of PFC frames with PFC enabled bit for
12879 * Pri 5 transmitted
12881 uint64_t tx_pfc_ena_frames_pri5;
12883 * Total number of PFC frames with PFC enabled bit for
12884 * Pri 6 transmitted
12886 uint64_t tx_pfc_ena_frames_pri6;
12888 * Total number of PFC frames with PFC enabled bit for
12889 * Pri 7 transmitted
12891 uint64_t tx_pfc_ena_frames_pri7;
12892 /* Total number of EEE LPI Events on TX */
12893 uint64_t tx_eee_lpi_events;
12894 /* EEE LPI Duration Counter on TX */
12895 uint64_t tx_eee_lpi_duration;
12897 * Total number of Link Level Flow Control (LLFC) messages
12900 uint64_t tx_llfc_logical_msgs;
12901 /* Total number of HCFC messages transmitted */
12902 uint64_t tx_hcfc_msgs;
12903 /* Total number of TX collisions */
12904 uint64_t tx_total_collisions;
12905 /* Total number of transmitted bytes */
12907 /* Total number of end-to-end HOL frames */
12908 uint64_t tx_xthol_frames;
12909 /* Total Tx Drops per Port reported by STATS block */
12910 uint64_t tx_stat_discard;
12911 /* Total Tx Error Drops per Port reported by STATS block */
12912 uint64_t tx_stat_error;
12913 } __attribute__((packed));
12915 /* Port Rx Statistics Formats */
12916 /* rx_port_stats (size:4224b/528B) */
12917 struct rx_port_stats {
12918 /* Total Number of 64 Bytes frames received */
12919 uint64_t rx_64b_frames;
12920 /* Total Number of 65-127 Bytes frames received */
12921 uint64_t rx_65b_127b_frames;
12922 /* Total Number of 128-255 Bytes frames received */
12923 uint64_t rx_128b_255b_frames;
12924 /* Total Number of 256-511 Bytes frames received */
12925 uint64_t rx_256b_511b_frames;
12926 /* Total Number of 512-1023 Bytes frames received */
12927 uint64_t rx_512b_1023b_frames;
12928 /* Total Number of 1024-1518 Bytes frames received */
12929 uint64_t rx_1024b_1518b_frames;
12931 * Total Number of each good VLAN (exludes FCS errors)
12932 * frame received which is 1519 to 1522 bytes in length
12933 * inclusive (excluding framing bits but including FCS bytes).
12935 uint64_t rx_good_vlan_frames;
12936 /* Total Number of 1519-2047 Bytes frames received */
12937 uint64_t rx_1519b_2047b_frames;
12938 /* Total Number of 2048-4095 Bytes frames received */
12939 uint64_t rx_2048b_4095b_frames;
12940 /* Total Number of 4096-9216 Bytes frames received */
12941 uint64_t rx_4096b_9216b_frames;
12942 /* Total Number of 9217-16383 Bytes frames received */
12943 uint64_t rx_9217b_16383b_frames;
12944 /* Total number of frames received */
12945 uint64_t rx_total_frames;
12946 /* Total number of unicast frames received */
12947 uint64_t rx_ucast_frames;
12948 /* Total number of multicast frames received */
12949 uint64_t rx_mcast_frames;
12950 /* Total number of broadcast frames received */
12951 uint64_t rx_bcast_frames;
12952 /* Total number of received frames with FCS error */
12953 uint64_t rx_fcs_err_frames;
12954 /* Total number of control frames received */
12955 uint64_t rx_ctrl_frames;
12956 /* Total number of PAUSE frames received */
12957 uint64_t rx_pause_frames;
12958 /* Total number of PFC frames received */
12959 uint64_t rx_pfc_frames;
12961 * Total number of frames received with an unsupported
12964 uint64_t rx_unsupported_opcode_frames;
12966 * Total number of frames received with an unsupported
12967 * DA for pause and PFC
12969 uint64_t rx_unsupported_da_pausepfc_frames;
12970 /* Total number of frames received with an unsupported SA */
12971 uint64_t rx_wrong_sa_frames;
12972 /* Total number of received packets with alignment error */
12973 uint64_t rx_align_err_frames;
12974 /* Total number of received frames with out-of-range length */
12975 uint64_t rx_oor_len_frames;
12976 /* Total number of received frames with error termination */
12977 uint64_t rx_code_err_frames;
12979 * Total number of received frames with a false carrier is
12980 * detected during idle, as defined by RX_ER samples active
12981 * and RXD is 0xE. The event is reported along with the
12982 * statistics generated on the next received frame. Only
12983 * one false carrier condition can be detected and logged
12986 * Carrier event, valid for 10M/100M speed modes only.
12988 uint64_t rx_false_carrier_frames;
12989 /* Total number of over-sized frames received */
12990 uint64_t rx_ovrsz_frames;
12991 /* Total number of jabber packets received */
12992 uint64_t rx_jbr_frames;
12993 /* Total number of received frames with MTU error */
12994 uint64_t rx_mtu_err_frames;
12995 /* Total number of received frames with CRC match */
12996 uint64_t rx_match_crc_frames;
12997 /* Total number of frames received promiscuously */
12998 uint64_t rx_promiscuous_frames;
13000 * Total number of received frames with one or two VLAN
13003 uint64_t rx_tagged_frames;
13004 /* Total number of received frames with two VLAN tags */
13005 uint64_t rx_double_tagged_frames;
13006 /* Total number of truncated frames received */
13007 uint64_t rx_trunc_frames;
13008 /* Total number of good frames (without errors) received */
13009 uint64_t rx_good_frames;
13011 * Total number of received PFC frames with transition from
13012 * XON to XOFF on Pri 0
13014 uint64_t rx_pfc_xon2xoff_frames_pri0;
13016 * Total number of received PFC frames with transition from
13017 * XON to XOFF on Pri 1
13019 uint64_t rx_pfc_xon2xoff_frames_pri1;
13021 * Total number of received PFC frames with transition from
13022 * XON to XOFF on Pri 2
13024 uint64_t rx_pfc_xon2xoff_frames_pri2;
13026 * Total number of received PFC frames with transition from
13027 * XON to XOFF on Pri 3
13029 uint64_t rx_pfc_xon2xoff_frames_pri3;
13031 * Total number of received PFC frames with transition from
13032 * XON to XOFF on Pri 4
13034 uint64_t rx_pfc_xon2xoff_frames_pri4;
13036 * Total number of received PFC frames with transition from
13037 * XON to XOFF on Pri 5
13039 uint64_t rx_pfc_xon2xoff_frames_pri5;
13041 * Total number of received PFC frames with transition from
13042 * XON to XOFF on Pri 6
13044 uint64_t rx_pfc_xon2xoff_frames_pri6;
13046 * Total number of received PFC frames with transition from
13047 * XON to XOFF on Pri 7
13049 uint64_t rx_pfc_xon2xoff_frames_pri7;
13051 * Total number of received PFC frames with PFC enabled
13054 uint64_t rx_pfc_ena_frames_pri0;
13056 * Total number of received PFC frames with PFC enabled
13059 uint64_t rx_pfc_ena_frames_pri1;
13061 * Total number of received PFC frames with PFC enabled
13064 uint64_t rx_pfc_ena_frames_pri2;
13066 * Total number of received PFC frames with PFC enabled
13069 uint64_t rx_pfc_ena_frames_pri3;
13071 * Total number of received PFC frames with PFC enabled
13074 uint64_t rx_pfc_ena_frames_pri4;
13076 * Total number of received PFC frames with PFC enabled
13079 uint64_t rx_pfc_ena_frames_pri5;
13081 * Total number of received PFC frames with PFC enabled
13084 uint64_t rx_pfc_ena_frames_pri6;
13086 * Total number of received PFC frames with PFC enabled
13089 uint64_t rx_pfc_ena_frames_pri7;
13090 /* Total Number of frames received with SCH CRC error */
13091 uint64_t rx_sch_crc_err_frames;
13092 /* Total Number of under-sized frames received */
13093 uint64_t rx_undrsz_frames;
13094 /* Total Number of fragmented frames received */
13095 uint64_t rx_frag_frames;
13096 /* Total number of RX EEE LPI Events */
13097 uint64_t rx_eee_lpi_events;
13098 /* EEE LPI Duration Counter on RX */
13099 uint64_t rx_eee_lpi_duration;
13101 * Total number of physical type Link Level Flow Control
13102 * (LLFC) messages received
13104 uint64_t rx_llfc_physical_msgs;
13106 * Total number of logical type Link Level Flow Control
13107 * (LLFC) messages received
13109 uint64_t rx_llfc_logical_msgs;
13111 * Total number of logical type Link Level Flow Control
13112 * (LLFC) messages received with CRC error
13114 uint64_t rx_llfc_msgs_with_crc_err;
13115 /* Total number of HCFC messages received */
13116 uint64_t rx_hcfc_msgs;
13117 /* Total number of HCFC messages received with CRC error */
13118 uint64_t rx_hcfc_msgs_with_crc_err;
13119 /* Total number of received bytes */
13121 /* Total number of bytes received in runt frames */
13122 uint64_t rx_runt_bytes;
13123 /* Total number of runt frames received */
13124 uint64_t rx_runt_frames;
13125 /* Total Rx Discards per Port reported by STATS block */
13126 uint64_t rx_stat_discard;
13127 uint64_t rx_stat_err;
13128 } __attribute__((packed));
13130 /********************
13131 * hwrm_port_qstats *
13132 ********************/
13135 /* hwrm_port_qstats_input (size:320b/40B) */
13136 struct hwrm_port_qstats_input {
13137 /* The HWRM command request type. */
13140 * The completion ring to send the completion event on. This should
13141 * be the NQ ID returned from the `nq_alloc` HWRM command.
13143 uint16_t cmpl_ring;
13145 * The sequence ID is used by the driver for tracking multiple
13146 * commands. This ID is treated as opaque data by the firmware and
13147 * the value is returned in the `hwrm_resp_hdr` upon completion.
13151 * The target ID of the command:
13152 * * 0x0-0xFFF8 - The function ID
13153 * * 0xFFF8-0xFFFE - Reserved for internal processors
13156 uint16_t target_id;
13158 * A physical address pointer pointing to a host buffer that the
13159 * command's response data will be written. This can be either a host
13160 * physical address (HPA) or a guest physical address (GPA) and must
13161 * point to a physically contiguous block of memory.
13163 uint64_t resp_addr;
13164 /* Port ID of port that is being queried. */
13166 uint8_t unused_0[6];
13168 * This is the host address where
13169 * Tx port statistics will be stored
13171 uint64_t tx_stat_host_addr;
13173 * This is the host address where
13174 * Rx port statistics will be stored
13176 uint64_t rx_stat_host_addr;
13177 } __attribute__((packed));
13179 /* hwrm_port_qstats_output (size:128b/16B) */
13180 struct hwrm_port_qstats_output {
13181 /* The specific error status for the command. */
13182 uint16_t error_code;
13183 /* The HWRM command request type. */
13185 /* The sequence ID from the original command. */
13187 /* The length of the response data in number of bytes. */
13189 /* The size of TX port statistics block in bytes. */
13190 uint16_t tx_stat_size;
13191 /* The size of RX port statistics block in bytes. */
13192 uint16_t rx_stat_size;
13193 uint8_t unused_0[3];
13195 * This field is used in Output records to indicate that the output
13196 * is completely written to RAM. This field should be read as '1'
13197 * to indicate that the output has been completely written.
13198 * When writing a command completion or response to an internal processor,
13199 * the order of writes has to be such that this field is written last.
13202 } __attribute__((packed));
13204 /* Port Tx Statistics extended Formats */
13205 /* tx_port_stats_ext (size:2048b/256B) */
13206 struct tx_port_stats_ext {
13207 /* Total number of tx bytes count on cos queue 0 */
13208 uint64_t tx_bytes_cos0;
13209 /* Total number of tx bytes count on cos queue 1 */
13210 uint64_t tx_bytes_cos1;
13211 /* Total number of tx bytes count on cos queue 2 */
13212 uint64_t tx_bytes_cos2;
13213 /* Total number of tx bytes count on cos queue 3 */
13214 uint64_t tx_bytes_cos3;
13215 /* Total number of tx bytes count on cos queue 4 */
13216 uint64_t tx_bytes_cos4;
13217 /* Total number of tx bytes count on cos queue 5 */
13218 uint64_t tx_bytes_cos5;
13219 /* Total number of tx bytes count on cos queue 6 */
13220 uint64_t tx_bytes_cos6;
13221 /* Total number of tx bytes count on cos queue 7 */
13222 uint64_t tx_bytes_cos7;
13223 /* Total number of tx packets count on cos queue 0 */
13224 uint64_t tx_packets_cos0;
13225 /* Total number of tx packets count on cos queue 1 */
13226 uint64_t tx_packets_cos1;
13227 /* Total number of tx packets count on cos queue 2 */
13228 uint64_t tx_packets_cos2;
13229 /* Total number of tx packets count on cos queue 3 */
13230 uint64_t tx_packets_cos3;
13231 /* Total number of tx packets count on cos queue 4 */
13232 uint64_t tx_packets_cos4;
13233 /* Total number of tx packets count on cos queue 5 */
13234 uint64_t tx_packets_cos5;
13235 /* Total number of tx packets count on cos queue 6 */
13236 uint64_t tx_packets_cos6;
13237 /* Total number of tx packets count on cos queue 7 */
13238 uint64_t tx_packets_cos7;
13239 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
13240 uint64_t pfc_pri0_tx_duration_us;
13241 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
13242 uint64_t pfc_pri0_tx_transitions;
13243 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
13244 uint64_t pfc_pri1_tx_duration_us;
13245 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
13246 uint64_t pfc_pri1_tx_transitions;
13247 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
13248 uint64_t pfc_pri2_tx_duration_us;
13249 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
13250 uint64_t pfc_pri2_tx_transitions;
13251 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
13252 uint64_t pfc_pri3_tx_duration_us;
13253 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
13254 uint64_t pfc_pri3_tx_transitions;
13255 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
13256 uint64_t pfc_pri4_tx_duration_us;
13257 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
13258 uint64_t pfc_pri4_tx_transitions;
13259 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
13260 uint64_t pfc_pri5_tx_duration_us;
13261 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
13262 uint64_t pfc_pri5_tx_transitions;
13263 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
13264 uint64_t pfc_pri6_tx_duration_us;
13265 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
13266 uint64_t pfc_pri6_tx_transitions;
13267 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
13268 uint64_t pfc_pri7_tx_duration_us;
13269 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
13270 uint64_t pfc_pri7_tx_transitions;
13271 } __attribute__((packed));
13273 /* Port Rx Statistics extended Formats */
13274 /* rx_port_stats_ext (size:2368b/296B) */
13275 struct rx_port_stats_ext {
13276 /* Number of times link state changed to down */
13277 uint64_t link_down_events;
13278 /* Number of times the idle rings with pause bit are found */
13279 uint64_t continuous_pause_events;
13280 /* Number of times the active rings pause bit resumed back */
13281 uint64_t resume_pause_events;
13282 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
13283 uint64_t continuous_roce_pause_events;
13284 /* Number of times, the ROCE cos queue PFC is enabled back */
13285 uint64_t resume_roce_pause_events;
13286 /* Total number of rx bytes count on cos queue 0 */
13287 uint64_t rx_bytes_cos0;
13288 /* Total number of rx bytes count on cos queue 1 */
13289 uint64_t rx_bytes_cos1;
13290 /* Total number of rx bytes count on cos queue 2 */
13291 uint64_t rx_bytes_cos2;
13292 /* Total number of rx bytes count on cos queue 3 */
13293 uint64_t rx_bytes_cos3;
13294 /* Total number of rx bytes count on cos queue 4 */
13295 uint64_t rx_bytes_cos4;
13296 /* Total number of rx bytes count on cos queue 5 */
13297 uint64_t rx_bytes_cos5;
13298 /* Total number of rx bytes count on cos queue 6 */
13299 uint64_t rx_bytes_cos6;
13300 /* Total number of rx bytes count on cos queue 7 */
13301 uint64_t rx_bytes_cos7;
13302 /* Total number of rx packets count on cos queue 0 */
13303 uint64_t rx_packets_cos0;
13304 /* Total number of rx packets count on cos queue 1 */
13305 uint64_t rx_packets_cos1;
13306 /* Total number of rx packets count on cos queue 2 */
13307 uint64_t rx_packets_cos2;
13308 /* Total number of rx packets count on cos queue 3 */
13309 uint64_t rx_packets_cos3;
13310 /* Total number of rx packets count on cos queue 4 */
13311 uint64_t rx_packets_cos4;
13312 /* Total number of rx packets count on cos queue 5 */
13313 uint64_t rx_packets_cos5;
13314 /* Total number of rx packets count on cos queue 6 */
13315 uint64_t rx_packets_cos6;
13316 /* Total number of rx packets count on cos queue 7 */
13317 uint64_t rx_packets_cos7;
13318 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
13319 uint64_t pfc_pri0_rx_duration_us;
13320 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
13321 uint64_t pfc_pri0_rx_transitions;
13322 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
13323 uint64_t pfc_pri1_rx_duration_us;
13324 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
13325 uint64_t pfc_pri1_rx_transitions;
13326 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
13327 uint64_t pfc_pri2_rx_duration_us;
13328 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
13329 uint64_t pfc_pri2_rx_transitions;
13330 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
13331 uint64_t pfc_pri3_rx_duration_us;
13332 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
13333 uint64_t pfc_pri3_rx_transitions;
13334 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
13335 uint64_t pfc_pri4_rx_duration_us;
13336 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
13337 uint64_t pfc_pri4_rx_transitions;
13338 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
13339 uint64_t pfc_pri5_rx_duration_us;
13340 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
13341 uint64_t pfc_pri5_rx_transitions;
13342 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
13343 uint64_t pfc_pri6_rx_duration_us;
13344 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
13345 uint64_t pfc_pri6_rx_transitions;
13346 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
13347 uint64_t pfc_pri7_rx_duration_us;
13348 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
13349 uint64_t pfc_pri7_rx_transitions;
13350 } __attribute__((packed));
13352 /************************
13353 * hwrm_port_qstats_ext *
13354 ************************/
13357 /* hwrm_port_qstats_ext_input (size:320b/40B) */
13358 struct hwrm_port_qstats_ext_input {
13359 /* The HWRM command request type. */
13362 * The completion ring to send the completion event on. This should
13363 * be the NQ ID returned from the `nq_alloc` HWRM command.
13365 uint16_t cmpl_ring;
13367 * The sequence ID is used by the driver for tracking multiple
13368 * commands. This ID is treated as opaque data by the firmware and
13369 * the value is returned in the `hwrm_resp_hdr` upon completion.
13373 * The target ID of the command:
13374 * * 0x0-0xFFF8 - The function ID
13375 * * 0xFFF8-0xFFFE - Reserved for internal processors
13378 uint16_t target_id;
13380 * A physical address pointer pointing to a host buffer that the
13381 * command's response data will be written. This can be either a host
13382 * physical address (HPA) or a guest physical address (GPA) and must
13383 * point to a physically contiguous block of memory.
13385 uint64_t resp_addr;
13386 /* Port ID of port that is being queried. */
13389 * The size of TX port extended
13390 * statistics block in bytes.
13392 uint16_t tx_stat_size;
13394 * The size of RX port extended
13395 * statistics block in bytes
13397 uint16_t rx_stat_size;
13398 uint8_t unused_0[2];
13400 * This is the host address where
13401 * Tx port statistics will be stored
13403 uint64_t tx_stat_host_addr;
13405 * This is the host address where
13406 * Rx port statistics will be stored
13408 uint64_t rx_stat_host_addr;
13409 } __attribute__((packed));
13411 /* hwrm_port_qstats_ext_output (size:128b/16B) */
13412 struct hwrm_port_qstats_ext_output {
13413 /* The specific error status for the command. */
13414 uint16_t error_code;
13415 /* The HWRM command request type. */
13417 /* The sequence ID from the original command. */
13419 /* The length of the response data in number of bytes. */
13421 /* The size of TX port statistics block in bytes. */
13422 uint16_t tx_stat_size;
13423 /* The size of RX port statistics block in bytes. */
13424 uint16_t rx_stat_size;
13425 /* Total number of active cos queues available. */
13426 uint16_t total_active_cos_queues;
13429 * If set to 1, then this field indicates that clear
13430 * roce specific counters is supported.
13432 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
13435 * This field is used in Output records to indicate that the output
13436 * is completely written to RAM. This field should be read as '1'
13437 * to indicate that the output has been completely written.
13438 * When writing a command completion or response to an internal processor,
13439 * the order of writes has to be such that this field is written last.
13442 } __attribute__((packed));
13444 /*************************
13445 * hwrm_port_lpbk_qstats *
13446 *************************/
13449 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
13450 struct hwrm_port_lpbk_qstats_input {
13451 /* The HWRM command request type. */
13454 * The completion ring to send the completion event on. This should
13455 * be the NQ ID returned from the `nq_alloc` HWRM command.
13457 uint16_t cmpl_ring;
13459 * The sequence ID is used by the driver for tracking multiple
13460 * commands. This ID is treated as opaque data by the firmware and
13461 * the value is returned in the `hwrm_resp_hdr` upon completion.
13465 * The target ID of the command:
13466 * * 0x0-0xFFF8 - The function ID
13467 * * 0xFFF8-0xFFFE - Reserved for internal processors
13470 uint16_t target_id;
13472 * A physical address pointer pointing to a host buffer that the
13473 * command's response data will be written. This can be either a host
13474 * physical address (HPA) or a guest physical address (GPA) and must
13475 * point to a physically contiguous block of memory.
13477 uint64_t resp_addr;
13478 } __attribute__((packed));
13480 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
13481 struct hwrm_port_lpbk_qstats_output {
13482 /* The specific error status for the command. */
13483 uint16_t error_code;
13484 /* The HWRM command request type. */
13486 /* The sequence ID from the original command. */
13488 /* The length of the response data in number of bytes. */
13490 /* Number of transmitted unicast frames */
13491 uint64_t lpbk_ucast_frames;
13492 /* Number of transmitted multicast frames */
13493 uint64_t lpbk_mcast_frames;
13494 /* Number of transmitted broadcast frames */
13495 uint64_t lpbk_bcast_frames;
13496 /* Number of transmitted bytes for unicast traffic */
13497 uint64_t lpbk_ucast_bytes;
13498 /* Number of transmitted bytes for multicast traffic */
13499 uint64_t lpbk_mcast_bytes;
13500 /* Number of transmitted bytes for broadcast traffic */
13501 uint64_t lpbk_bcast_bytes;
13502 /* Total Tx Drops for loopback traffic reported by STATS block */
13503 uint64_t tx_stat_discard;
13504 /* Total Tx Error Drops for loopback traffic reported by STATS block */
13505 uint64_t tx_stat_error;
13506 /* Total Rx Drops for loopback traffic reported by STATS block */
13507 uint64_t rx_stat_discard;
13508 /* Total Rx Error Drops for loopback traffic reported by STATS block */
13509 uint64_t rx_stat_error;
13510 uint8_t unused_0[7];
13512 * This field is used in Output records to indicate that the output
13513 * is completely written to RAM. This field should be read as '1'
13514 * to indicate that the output has been completely written.
13515 * When writing a command completion or response to an internal processor,
13516 * the order of writes has to be such that this field is written last.
13519 } __attribute__((packed));
13521 /***********************
13522 * hwrm_port_clr_stats *
13523 ***********************/
13526 /* hwrm_port_clr_stats_input (size:192b/24B) */
13527 struct hwrm_port_clr_stats_input {
13528 /* The HWRM command request type. */
13531 * The completion ring to send the completion event on. This should
13532 * be the NQ ID returned from the `nq_alloc` HWRM command.
13534 uint16_t cmpl_ring;
13536 * The sequence ID is used by the driver for tracking multiple
13537 * commands. This ID is treated as opaque data by the firmware and
13538 * the value is returned in the `hwrm_resp_hdr` upon completion.
13542 * The target ID of the command:
13543 * * 0x0-0xFFF8 - The function ID
13544 * * 0xFFF8-0xFFFE - Reserved for internal processors
13547 uint16_t target_id;
13549 * A physical address pointer pointing to a host buffer that the
13550 * command's response data will be written. This can be either a host
13551 * physical address (HPA) or a guest physical address (GPA) and must
13552 * point to a physically contiguous block of memory.
13554 uint64_t resp_addr;
13555 /* Port ID of port that is being queried. */
13559 * If set to 1, then this field indicates clear the following RoCE
13560 * specific counters.
13561 * RoCE associated TX/RX cos counters
13562 * CNP associated TX/RX cos counters
13563 * RoCE/CNP specific TX/RX flow counters
13564 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
13565 * This flag is honored only when RoCE is enabled on that port.
13567 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
13568 uint8_t unused_0[5];
13569 } __attribute__((packed));
13571 /* hwrm_port_clr_stats_output (size:128b/16B) */
13572 struct hwrm_port_clr_stats_output {
13573 /* The specific error status for the command. */
13574 uint16_t error_code;
13575 /* The HWRM command request type. */
13577 /* The sequence ID from the original command. */
13579 /* The length of the response data in number of bytes. */
13581 uint8_t unused_0[7];
13583 * This field is used in Output records to indicate that the output
13584 * is completely written to RAM. This field should be read as '1'
13585 * to indicate that the output has been completely written.
13586 * When writing a command completion or response to an internal processor,
13587 * the order of writes has to be such that this field is written last.
13590 } __attribute__((packed));
13592 /***********************
13593 * hwrm_port_phy_qcaps *
13594 ***********************/
13597 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
13598 struct hwrm_port_phy_qcaps_input {
13599 /* The HWRM command request type. */
13602 * The completion ring to send the completion event on. This should
13603 * be the NQ ID returned from the `nq_alloc` HWRM command.
13605 uint16_t cmpl_ring;
13607 * The sequence ID is used by the driver for tracking multiple
13608 * commands. This ID is treated as opaque data by the firmware and
13609 * the value is returned in the `hwrm_resp_hdr` upon completion.
13613 * The target ID of the command:
13614 * * 0x0-0xFFF8 - The function ID
13615 * * 0xFFF8-0xFFFE - Reserved for internal processors
13618 uint16_t target_id;
13620 * A physical address pointer pointing to a host buffer that the
13621 * command's response data will be written. This can be either a host
13622 * physical address (HPA) or a guest physical address (GPA) and must
13623 * point to a physically contiguous block of memory.
13625 uint64_t resp_addr;
13626 /* Port ID of port that is being queried. */
13628 uint8_t unused_0[6];
13629 } __attribute__((packed));
13631 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
13632 struct hwrm_port_phy_qcaps_output {
13633 /* The specific error status for the command. */
13634 uint16_t error_code;
13635 /* The HWRM command request type. */
13637 /* The sequence ID from the original command. */
13639 /* The length of the response data in number of bytes. */
13641 /* PHY capability flags */
13644 * If set to 1, then this field indicates that the
13645 * link is capable of supporting EEE.
13647 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
13650 * If set to 1, then this field indicates that the
13651 * PHY is capable of supporting external loopback.
13653 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
13656 * Reserved field. The HWRM shall set this field to 0.
13657 * An HWRM client shall ignore this field.
13659 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
13661 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
13662 /* Number of front panel ports for this device. */
13664 /* Not supported or unknown */
13665 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
13666 /* single port device */
13667 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
13668 /* 2-port device */
13669 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
13670 /* 3-port device */
13671 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
13672 /* 4-port device */
13673 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
13674 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
13675 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
13677 * This is a bit mask to indicate what speeds are supported
13678 * as forced speeds on this link.
13679 * For each speed that can be forced on this link, the
13680 * corresponding mask bit shall be set to '1'.
13682 uint16_t supported_speeds_force_mode;
13683 /* 100Mb link speed (Half-duplex) */
13684 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
13686 /* 100Mb link speed (Full-duplex) */
13687 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
13689 /* 1Gb link speed (Half-duplex) */
13690 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
13692 /* 1Gb link speed (Full-duplex) */
13693 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
13695 /* 2Gb link speed */
13696 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
13698 /* 25Gb link speed */
13699 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
13701 /* 10Gb link speed */
13702 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
13704 /* 20Gb link speed */
13705 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
13707 /* 25Gb link speed */
13708 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
13710 /* 40Gb link speed */
13711 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
13713 /* 50Gb link speed */
13714 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
13716 /* 100Gb link speed */
13717 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
13719 /* 10Mb link speed (Half-duplex) */
13720 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
13722 /* 10Mb link speed (Full-duplex) */
13723 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
13726 * This is a bit mask to indicate what speeds are supported
13727 * for autonegotiation on this link.
13728 * For each speed that can be autonegotiated on this link, the
13729 * corresponding mask bit shall be set to '1'.
13731 uint16_t supported_speeds_auto_mode;
13732 /* 100Mb link speed (Half-duplex) */
13733 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
13735 /* 100Mb link speed (Full-duplex) */
13736 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
13738 /* 1Gb link speed (Half-duplex) */
13739 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
13741 /* 1Gb link speed (Full-duplex) */
13742 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
13744 /* 2Gb link speed */
13745 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
13747 /* 25Gb link speed */
13748 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
13750 /* 10Gb link speed */
13751 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
13753 /* 20Gb link speed */
13754 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
13756 /* 25Gb link speed */
13757 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
13759 /* 40Gb link speed */
13760 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
13762 /* 50Gb link speed */
13763 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
13765 /* 100Gb link speed */
13766 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
13768 /* 10Mb link speed (Half-duplex) */
13769 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
13771 /* 10Mb link speed (Full-duplex) */
13772 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
13775 * This is a bit mask to indicate what speeds are supported
13776 * for EEE on this link.
13777 * For each speed that can be autonegotiated when EEE is enabled
13778 * on this link, the corresponding mask bit shall be set to '1'.
13779 * This field is only valid when the eee_suppotred is set to '1'.
13781 uint16_t supported_speeds_eee_mode;
13783 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
13785 /* 100Mb link speed (Full-duplex) */
13786 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
13789 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
13791 /* 1Gb link speed (Full-duplex) */
13792 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
13795 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
13798 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
13800 /* 10Gb link speed */
13801 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
13803 uint32_t tx_lpi_timer_low;
13805 * The lowest value of TX LPI timer that can be set on this link
13806 * when EEE is enabled. This value is in microseconds.
13807 * This field is valid only when_eee_supported is set to '1'.
13809 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
13811 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
13813 * Reserved field. The HWRM shall set this field to 0.
13814 * An HWRM client shall ignore this field.
13816 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
13817 UINT32_C(0xff000000)
13818 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
13819 uint32_t valid_tx_lpi_timer_high;
13821 * The highest value of TX LPI timer that can be set on this link
13822 * when EEE is enabled. This value is in microseconds.
13823 * This field is valid only when_eee_supported is set to '1'.
13825 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
13827 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
13829 * This field is used in Output records to indicate that the output
13830 * is completely written to RAM. This field should be read as '1'
13831 * to indicate that the output has been completely written.
13832 * When writing a command completion or response to an internal processor,
13833 * the order of writes has to be such that this field is written last.
13835 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
13836 UINT32_C(0xff000000)
13837 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
13838 } __attribute__((packed));
13840 /*********************
13841 * hwrm_port_led_cfg *
13842 *********************/
13845 /* hwrm_port_led_cfg_input (size:512b/64B) */
13846 struct hwrm_port_led_cfg_input {
13847 /* The HWRM command request type. */
13850 * The completion ring to send the completion event on. This should
13851 * be the NQ ID returned from the `nq_alloc` HWRM command.
13853 uint16_t cmpl_ring;
13855 * The sequence ID is used by the driver for tracking multiple
13856 * commands. This ID is treated as opaque data by the firmware and
13857 * the value is returned in the `hwrm_resp_hdr` upon completion.
13861 * The target ID of the command:
13862 * * 0x0-0xFFF8 - The function ID
13863 * * 0xFFF8-0xFFFE - Reserved for internal processors
13866 uint16_t target_id;
13868 * A physical address pointer pointing to a host buffer that the
13869 * command's response data will be written. This can be either a host
13870 * physical address (HPA) or a guest physical address (GPA) and must
13871 * point to a physically contiguous block of memory.
13873 uint64_t resp_addr;
13876 * This bit must be '1' for the led0_id field to be
13879 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
13882 * This bit must be '1' for the led0_state field to be
13885 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
13888 * This bit must be '1' for the led0_color field to be
13891 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
13894 * This bit must be '1' for the led0_blink_on field to be
13897 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
13900 * This bit must be '1' for the led0_blink_off field to be
13903 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
13906 * This bit must be '1' for the led0_group_id field to be
13909 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
13912 * This bit must be '1' for the led1_id field to be
13915 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
13918 * This bit must be '1' for the led1_state field to be
13921 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
13924 * This bit must be '1' for the led1_color field to be
13927 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
13930 * This bit must be '1' for the led1_blink_on field to be
13933 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
13936 * This bit must be '1' for the led1_blink_off field to be
13939 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
13942 * This bit must be '1' for the led1_group_id field to be
13945 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
13948 * This bit must be '1' for the led2_id field to be
13951 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
13954 * This bit must be '1' for the led2_state field to be
13957 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
13960 * This bit must be '1' for the led2_color field to be
13963 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
13966 * This bit must be '1' for the led2_blink_on field to be
13969 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
13972 * This bit must be '1' for the led2_blink_off field to be
13975 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
13978 * This bit must be '1' for the led2_group_id field to be
13981 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
13984 * This bit must be '1' for the led3_id field to be
13987 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
13990 * This bit must be '1' for the led3_state field to be
13993 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
13996 * This bit must be '1' for the led3_color field to be
13999 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
14002 * This bit must be '1' for the led3_blink_on field to be
14005 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
14008 * This bit must be '1' for the led3_blink_off field to be
14011 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
14014 * This bit must be '1' for the led3_group_id field to be
14017 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
14019 /* Port ID of port whose LEDs are configured. */
14022 * The number of LEDs that are being configured.
14023 * Up to 4 LEDs can be configured with this command.
14026 /* Reserved field. */
14028 /* An identifier for the LED #0. */
14030 /* The requested state of the LED #0. */
14031 uint8_t led0_state;
14032 /* Default state of the LED */
14033 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
14035 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
14037 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
14039 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
14040 /* Blink Alternately */
14041 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
14042 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
14043 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
14044 /* The requested color of LED #0. */
14045 uint8_t led0_color;
14047 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
14049 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
14051 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
14052 /* Green or Amber */
14053 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
14054 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
14055 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
14058 * If the LED #0 state is "blink" or "blinkalt", then
14059 * this field represents the requested time in milliseconds
14060 * to keep LED on between cycles.
14062 uint16_t led0_blink_on;
14064 * If the LED #0 state is "blink" or "blinkalt", then
14065 * this field represents the requested time in milliseconds
14066 * to keep LED off between cycles.
14068 uint16_t led0_blink_off;
14070 * An identifier for the group of LEDs that LED #0 belongs
14072 * If set to 0, then the LED #0 shall not be grouped and
14073 * shall be treated as an individual resource.
14074 * For all other non-zero values of this field, LED #0 shall
14075 * be grouped together with the LEDs with the same group ID
14078 uint8_t led0_group_id;
14079 /* Reserved field. */
14081 /* An identifier for the LED #1. */
14083 /* The requested state of the LED #1. */
14084 uint8_t led1_state;
14085 /* Default state of the LED */
14086 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
14088 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
14090 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
14092 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
14093 /* Blink Alternately */
14094 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
14095 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
14096 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
14097 /* The requested color of LED #1. */
14098 uint8_t led1_color;
14100 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
14102 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
14104 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
14105 /* Green or Amber */
14106 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
14107 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
14108 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
14111 * If the LED #1 state is "blink" or "blinkalt", then
14112 * this field represents the requested time in milliseconds
14113 * to keep LED on between cycles.
14115 uint16_t led1_blink_on;
14117 * If the LED #1 state is "blink" or "blinkalt", then
14118 * this field represents the requested time in milliseconds
14119 * to keep LED off between cycles.
14121 uint16_t led1_blink_off;
14123 * An identifier for the group of LEDs that LED #1 belongs
14125 * If set to 0, then the LED #1 shall not be grouped and
14126 * shall be treated as an individual resource.
14127 * For all other non-zero values of this field, LED #1 shall
14128 * be grouped together with the LEDs with the same group ID
14131 uint8_t led1_group_id;
14132 /* Reserved field. */
14134 /* An identifier for the LED #2. */
14136 /* The requested state of the LED #2. */
14137 uint8_t led2_state;
14138 /* Default state of the LED */
14139 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
14141 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
14143 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
14145 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
14146 /* Blink Alternately */
14147 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
14148 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
14149 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
14150 /* The requested color of LED #2. */
14151 uint8_t led2_color;
14153 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
14155 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
14157 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
14158 /* Green or Amber */
14159 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
14160 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
14161 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
14164 * If the LED #2 state is "blink" or "blinkalt", then
14165 * this field represents the requested time in milliseconds
14166 * to keep LED on between cycles.
14168 uint16_t led2_blink_on;
14170 * If the LED #2 state is "blink" or "blinkalt", then
14171 * this field represents the requested time in milliseconds
14172 * to keep LED off between cycles.
14174 uint16_t led2_blink_off;
14176 * An identifier for the group of LEDs that LED #2 belongs
14178 * If set to 0, then the LED #2 shall not be grouped and
14179 * shall be treated as an individual resource.
14180 * For all other non-zero values of this field, LED #2 shall
14181 * be grouped together with the LEDs with the same group ID
14184 uint8_t led2_group_id;
14185 /* Reserved field. */
14187 /* An identifier for the LED #3. */
14189 /* The requested state of the LED #3. */
14190 uint8_t led3_state;
14191 /* Default state of the LED */
14192 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
14194 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
14196 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
14198 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
14199 /* Blink Alternately */
14200 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
14201 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
14202 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
14203 /* The requested color of LED #3. */
14204 uint8_t led3_color;
14206 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
14208 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
14210 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
14211 /* Green or Amber */
14212 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
14213 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
14214 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
14217 * If the LED #3 state is "blink" or "blinkalt", then
14218 * this field represents the requested time in milliseconds
14219 * to keep LED on between cycles.
14221 uint16_t led3_blink_on;
14223 * If the LED #3 state is "blink" or "blinkalt", then
14224 * this field represents the requested time in milliseconds
14225 * to keep LED off between cycles.
14227 uint16_t led3_blink_off;
14229 * An identifier for the group of LEDs that LED #3 belongs
14231 * If set to 0, then the LED #3 shall not be grouped and
14232 * shall be treated as an individual resource.
14233 * For all other non-zero values of this field, LED #3 shall
14234 * be grouped together with the LEDs with the same group ID
14237 uint8_t led3_group_id;
14238 /* Reserved field. */
14240 } __attribute__((packed));
14242 /* hwrm_port_led_cfg_output (size:128b/16B) */
14243 struct hwrm_port_led_cfg_output {
14244 /* The specific error status for the command. */
14245 uint16_t error_code;
14246 /* The HWRM command request type. */
14248 /* The sequence ID from the original command. */
14250 /* The length of the response data in number of bytes. */
14252 uint8_t unused_0[7];
14254 * This field is used in Output records to indicate that the output
14255 * is completely written to RAM. This field should be read as '1'
14256 * to indicate that the output has been completely written.
14257 * When writing a command completion or response to an internal processor,
14258 * the order of writes has to be such that this field is written last.
14261 } __attribute__((packed));
14263 /**********************
14264 * hwrm_port_led_qcfg *
14265 **********************/
14268 /* hwrm_port_led_qcfg_input (size:192b/24B) */
14269 struct hwrm_port_led_qcfg_input {
14270 /* The HWRM command request type. */
14273 * The completion ring to send the completion event on. This should
14274 * be the NQ ID returned from the `nq_alloc` HWRM command.
14276 uint16_t cmpl_ring;
14278 * The sequence ID is used by the driver for tracking multiple
14279 * commands. This ID is treated as opaque data by the firmware and
14280 * the value is returned in the `hwrm_resp_hdr` upon completion.
14284 * The target ID of the command:
14285 * * 0x0-0xFFF8 - The function ID
14286 * * 0xFFF8-0xFFFE - Reserved for internal processors
14289 uint16_t target_id;
14291 * A physical address pointer pointing to a host buffer that the
14292 * command's response data will be written. This can be either a host
14293 * physical address (HPA) or a guest physical address (GPA) and must
14294 * point to a physically contiguous block of memory.
14296 uint64_t resp_addr;
14297 /* Port ID of port whose LED configuration is being queried. */
14299 uint8_t unused_0[6];
14300 } __attribute__((packed));
14302 /* hwrm_port_led_qcfg_output (size:448b/56B) */
14303 struct hwrm_port_led_qcfg_output {
14304 /* The specific error status for the command. */
14305 uint16_t error_code;
14306 /* The HWRM command request type. */
14308 /* The sequence ID from the original command. */
14310 /* The length of the response data in number of bytes. */
14313 * The number of LEDs that are configured on this port.
14314 * Up to 4 LEDs can be returned in the response.
14317 /* An identifier for the LED #0. */
14319 /* The type of LED #0. */
14322 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
14324 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
14326 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
14327 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
14328 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
14329 /* The current state of the LED #0. */
14330 uint8_t led0_state;
14331 /* Default state of the LED */
14332 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
14334 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
14336 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
14338 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
14339 /* Blink Alternately */
14340 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
14341 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
14342 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
14343 /* The color of LED #0. */
14344 uint8_t led0_color;
14346 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
14348 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
14350 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
14351 /* Green or Amber */
14352 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
14353 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
14354 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
14357 * If the LED #0 state is "blink" or "blinkalt", then
14358 * this field represents the requested time in milliseconds
14359 * to keep LED on between cycles.
14361 uint16_t led0_blink_on;
14363 * If the LED #0 state is "blink" or "blinkalt", then
14364 * this field represents the requested time in milliseconds
14365 * to keep LED off between cycles.
14367 uint16_t led0_blink_off;
14369 * An identifier for the group of LEDs that LED #0 belongs
14371 * If set to 0, then the LED #0 is not grouped.
14372 * For all other non-zero values of this field, LED #0 is
14373 * grouped together with the LEDs with the same group ID
14376 uint8_t led0_group_id;
14377 /* An identifier for the LED #1. */
14379 /* The type of LED #1. */
14382 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
14384 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
14386 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
14387 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
14388 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
14389 /* The current state of the LED #1. */
14390 uint8_t led1_state;
14391 /* Default state of the LED */
14392 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
14394 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
14396 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
14398 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
14399 /* Blink Alternately */
14400 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
14401 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
14402 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
14403 /* The color of LED #1. */
14404 uint8_t led1_color;
14406 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
14408 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
14410 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
14411 /* Green or Amber */
14412 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
14413 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
14414 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
14417 * If the LED #1 state is "blink" or "blinkalt", then
14418 * this field represents the requested time in milliseconds
14419 * to keep LED on between cycles.
14421 uint16_t led1_blink_on;
14423 * If the LED #1 state is "blink" or "blinkalt", then
14424 * this field represents the requested time in milliseconds
14425 * to keep LED off between cycles.
14427 uint16_t led1_blink_off;
14429 * An identifier for the group of LEDs that LED #1 belongs
14431 * If set to 0, then the LED #1 is not grouped.
14432 * For all other non-zero values of this field, LED #1 is
14433 * grouped together with the LEDs with the same group ID
14436 uint8_t led1_group_id;
14437 /* An identifier for the LED #2. */
14439 /* The type of LED #2. */
14442 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
14444 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
14446 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
14447 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
14448 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
14449 /* The current state of the LED #2. */
14450 uint8_t led2_state;
14451 /* Default state of the LED */
14452 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
14454 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
14456 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
14458 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
14459 /* Blink Alternately */
14460 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
14461 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
14462 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
14463 /* The color of LED #2. */
14464 uint8_t led2_color;
14466 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
14468 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
14470 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
14471 /* Green or Amber */
14472 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
14473 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
14474 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
14477 * If the LED #2 state is "blink" or "blinkalt", then
14478 * this field represents the requested time in milliseconds
14479 * to keep LED on between cycles.
14481 uint16_t led2_blink_on;
14483 * If the LED #2 state is "blink" or "blinkalt", then
14484 * this field represents the requested time in milliseconds
14485 * to keep LED off between cycles.
14487 uint16_t led2_blink_off;
14489 * An identifier for the group of LEDs that LED #2 belongs
14491 * If set to 0, then the LED #2 is not grouped.
14492 * For all other non-zero values of this field, LED #2 is
14493 * grouped together with the LEDs with the same group ID
14496 uint8_t led2_group_id;
14497 /* An identifier for the LED #3. */
14499 /* The type of LED #3. */
14502 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
14504 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
14506 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
14507 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
14508 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
14509 /* The current state of the LED #3. */
14510 uint8_t led3_state;
14511 /* Default state of the LED */
14512 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
14514 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
14516 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
14518 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
14519 /* Blink Alternately */
14520 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
14521 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
14522 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
14523 /* The color of LED #3. */
14524 uint8_t led3_color;
14526 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
14528 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
14530 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
14531 /* Green or Amber */
14532 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
14533 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
14534 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
14537 * If the LED #3 state is "blink" or "blinkalt", then
14538 * this field represents the requested time in milliseconds
14539 * to keep LED on between cycles.
14541 uint16_t led3_blink_on;
14543 * If the LED #3 state is "blink" or "blinkalt", then
14544 * this field represents the requested time in milliseconds
14545 * to keep LED off between cycles.
14547 uint16_t led3_blink_off;
14549 * An identifier for the group of LEDs that LED #3 belongs
14551 * If set to 0, then the LED #3 is not grouped.
14552 * For all other non-zero values of this field, LED #3 is
14553 * grouped together with the LEDs with the same group ID
14556 uint8_t led3_group_id;
14557 uint8_t unused_4[6];
14559 * This field is used in Output records to indicate that the output
14560 * is completely written to RAM. This field should be read as '1'
14561 * to indicate that the output has been completely written.
14562 * When writing a command completion or response to an internal processor,
14563 * the order of writes has to be such that this field is written last.
14566 } __attribute__((packed));
14568 /***********************
14569 * hwrm_port_led_qcaps *
14570 ***********************/
14573 /* hwrm_port_led_qcaps_input (size:192b/24B) */
14574 struct hwrm_port_led_qcaps_input {
14575 /* The HWRM command request type. */
14578 * The completion ring to send the completion event on. This should
14579 * be the NQ ID returned from the `nq_alloc` HWRM command.
14581 uint16_t cmpl_ring;
14583 * The sequence ID is used by the driver for tracking multiple
14584 * commands. This ID is treated as opaque data by the firmware and
14585 * the value is returned in the `hwrm_resp_hdr` upon completion.
14589 * The target ID of the command:
14590 * * 0x0-0xFFF8 - The function ID
14591 * * 0xFFF8-0xFFFE - Reserved for internal processors
14594 uint16_t target_id;
14596 * A physical address pointer pointing to a host buffer that the
14597 * command's response data will be written. This can be either a host
14598 * physical address (HPA) or a guest physical address (GPA) and must
14599 * point to a physically contiguous block of memory.
14601 uint64_t resp_addr;
14602 /* Port ID of port whose LED configuration is being queried. */
14604 uint8_t unused_0[6];
14605 } __attribute__((packed));
14607 /* hwrm_port_led_qcaps_output (size:384b/48B) */
14608 struct hwrm_port_led_qcaps_output {
14609 /* The specific error status for the command. */
14610 uint16_t error_code;
14611 /* The HWRM command request type. */
14613 /* The sequence ID from the original command. */
14615 /* The length of the response data in number of bytes. */
14618 * The number of LEDs that are configured on this port.
14619 * Up to 4 LEDs can be returned in the response.
14622 /* Reserved for future use. */
14624 /* An identifier for the LED #0. */
14626 /* The type of LED #0. */
14629 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
14631 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
14633 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
14634 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
14635 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
14637 * An identifier for the group of LEDs that LED #0 belongs
14639 * If set to 0, then the LED #0 cannot be grouped.
14640 * For all other non-zero values of this field, LED #0 is
14641 * grouped together with the LEDs with the same group ID
14644 uint8_t led0_group_id;
14646 /* The states supported by LED #0. */
14647 uint16_t led0_state_caps;
14649 * If set to 1, this LED is enabled.
14650 * If set to 0, this LED is disabled.
14652 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
14655 * If set to 1, off state is supported on this LED.
14656 * If set to 0, off state is not supported on this LED.
14658 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
14661 * If set to 1, on state is supported on this LED.
14662 * If set to 0, on state is not supported on this LED.
14664 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
14667 * If set to 1, blink state is supported on this LED.
14668 * If set to 0, blink state is not supported on this LED.
14670 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
14673 * If set to 1, blink_alt state is supported on this LED.
14674 * If set to 0, blink_alt state is not supported on this LED.
14676 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
14678 /* The colors supported by LED #0. */
14679 uint16_t led0_color_caps;
14681 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
14684 * If set to 1, Amber color is supported on this LED.
14685 * If set to 0, Amber color is not supported on this LED.
14687 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
14690 * If set to 1, Green color is supported on this LED.
14691 * If set to 0, Green color is not supported on this LED.
14693 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
14695 /* An identifier for the LED #1. */
14697 /* The type of LED #1. */
14700 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
14702 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
14704 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
14705 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
14706 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
14708 * An identifier for the group of LEDs that LED #1 belongs
14710 * If set to 0, then the LED #0 cannot be grouped.
14711 * For all other non-zero values of this field, LED #0 is
14712 * grouped together with the LEDs with the same group ID
14715 uint8_t led1_group_id;
14717 /* The states supported by LED #1. */
14718 uint16_t led1_state_caps;
14720 * If set to 1, this LED is enabled.
14721 * If set to 0, this LED is disabled.
14723 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
14726 * If set to 1, off state is supported on this LED.
14727 * If set to 0, off state is not supported on this LED.
14729 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
14732 * If set to 1, on state is supported on this LED.
14733 * If set to 0, on state is not supported on this LED.
14735 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
14738 * If set to 1, blink state is supported on this LED.
14739 * If set to 0, blink state is not supported on this LED.
14741 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
14744 * If set to 1, blink_alt state is supported on this LED.
14745 * If set to 0, blink_alt state is not supported on this LED.
14747 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
14749 /* The colors supported by LED #1. */
14750 uint16_t led1_color_caps;
14752 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
14755 * If set to 1, Amber color is supported on this LED.
14756 * If set to 0, Amber color is not supported on this LED.
14758 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
14761 * If set to 1, Green color is supported on this LED.
14762 * If set to 0, Green color is not supported on this LED.
14764 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
14766 /* An identifier for the LED #2. */
14768 /* The type of LED #2. */
14771 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
14773 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
14775 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
14776 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
14777 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
14779 * An identifier for the group of LEDs that LED #0 belongs
14781 * If set to 0, then the LED #0 cannot be grouped.
14782 * For all other non-zero values of this field, LED #0 is
14783 * grouped together with the LEDs with the same group ID
14786 uint8_t led2_group_id;
14788 /* The states supported by LED #2. */
14789 uint16_t led2_state_caps;
14791 * If set to 1, this LED is enabled.
14792 * If set to 0, this LED is disabled.
14794 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
14797 * If set to 1, off state is supported on this LED.
14798 * If set to 0, off state is not supported on this LED.
14800 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
14803 * If set to 1, on state is supported on this LED.
14804 * If set to 0, on state is not supported on this LED.
14806 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
14809 * If set to 1, blink state is supported on this LED.
14810 * If set to 0, blink state is not supported on this LED.
14812 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
14815 * If set to 1, blink_alt state is supported on this LED.
14816 * If set to 0, blink_alt state is not supported on this LED.
14818 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
14820 /* The colors supported by LED #2. */
14821 uint16_t led2_color_caps;
14823 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
14826 * If set to 1, Amber color is supported on this LED.
14827 * If set to 0, Amber color is not supported on this LED.
14829 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
14832 * If set to 1, Green color is supported on this LED.
14833 * If set to 0, Green color is not supported on this LED.
14835 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
14837 /* An identifier for the LED #3. */
14839 /* The type of LED #3. */
14842 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
14844 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
14846 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
14847 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
14848 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
14850 * An identifier for the group of LEDs that LED #3 belongs
14852 * If set to 0, then the LED #0 cannot be grouped.
14853 * For all other non-zero values of this field, LED #0 is
14854 * grouped together with the LEDs with the same group ID
14857 uint8_t led3_group_id;
14859 /* The states supported by LED #3. */
14860 uint16_t led3_state_caps;
14862 * If set to 1, this LED is enabled.
14863 * If set to 0, this LED is disabled.
14865 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
14868 * If set to 1, off state is supported on this LED.
14869 * If set to 0, off state is not supported on this LED.
14871 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
14874 * If set to 1, on state is supported on this LED.
14875 * If set to 0, on state is not supported on this LED.
14877 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
14880 * If set to 1, blink state is supported on this LED.
14881 * If set to 0, blink state is not supported on this LED.
14883 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
14886 * If set to 1, blink_alt state is supported on this LED.
14887 * If set to 0, blink_alt state is not supported on this LED.
14889 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
14891 /* The colors supported by LED #3. */
14892 uint16_t led3_color_caps;
14894 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
14897 * If set to 1, Amber color is supported on this LED.
14898 * If set to 0, Amber color is not supported on this LED.
14900 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
14903 * If set to 1, Green color is supported on this LED.
14904 * If set to 0, Green color is not supported on this LED.
14906 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
14908 uint8_t unused_4[3];
14910 * This field is used in Output records to indicate that the output
14911 * is completely written to RAM. This field should be read as '1'
14912 * to indicate that the output has been completely written.
14913 * When writing a command completion or response to an internal processor,
14914 * the order of writes has to be such that this field is written last.
14917 } __attribute__((packed));
14919 /***********************
14920 * hwrm_queue_qportcfg *
14921 ***********************/
14924 /* hwrm_queue_qportcfg_input (size:192b/24B) */
14925 struct hwrm_queue_qportcfg_input {
14926 /* The HWRM command request type. */
14929 * The completion ring to send the completion event on. This should
14930 * be the NQ ID returned from the `nq_alloc` HWRM command.
14932 uint16_t cmpl_ring;
14934 * The sequence ID is used by the driver for tracking multiple
14935 * commands. This ID is treated as opaque data by the firmware and
14936 * the value is returned in the `hwrm_resp_hdr` upon completion.
14940 * The target ID of the command:
14941 * * 0x0-0xFFF8 - The function ID
14942 * * 0xFFF8-0xFFFE - Reserved for internal processors
14945 uint16_t target_id;
14947 * A physical address pointer pointing to a host buffer that the
14948 * command's response data will be written. This can be either a host
14949 * physical address (HPA) or a guest physical address (GPA) and must
14950 * point to a physically contiguous block of memory.
14952 uint64_t resp_addr;
14955 * Enumeration denoting the RX, TX type of the resource.
14956 * This enumeration is used for resources that are similar for both
14957 * TX and RX paths of the chip.
14959 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
14961 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14963 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14964 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
14965 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
14967 * Port ID of port for which the queue configuration is being
14968 * queried. This field is only required when sent by IPC.
14972 * Drivers will set this capability when it can use
14973 * queue_idx_service_profile to map the queues to application.
14975 uint8_t drv_qmap_cap;
14977 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
14979 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
14980 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
14981 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
14983 } __attribute__((packed));
14985 /* hwrm_queue_qportcfg_output (size:256b/32B) */
14986 struct hwrm_queue_qportcfg_output {
14987 /* The specific error status for the command. */
14988 uint16_t error_code;
14989 /* The HWRM command request type. */
14991 /* The sequence ID from the original command. */
14993 /* The length of the response data in number of bytes. */
14996 * The maximum number of queues that can be configured on this
14998 * Valid values range from 1 through 8.
15000 uint8_t max_configurable_queues;
15002 * The maximum number of lossless queues that can be configured
15004 * Valid values range from 0 through 8.
15006 uint8_t max_configurable_lossless_queues;
15008 * Bitmask indicating which queues can be configured by the
15009 * hwrm_queue_cfg command.
15011 * Each bit represents a specific queue where bit 0 represents
15012 * queue 0 and bit 7 represents queue 7.
15013 * # A value of 0 indicates that the queue is not configurable
15014 * by the hwrm_queue_cfg command.
15015 * # A value of 1 indicates that the queue is configurable.
15016 * # A hwrm_queue_cfg command shall return error when trying to
15017 * configure a queue not configurable.
15019 uint8_t queue_cfg_allowed;
15020 /* Information about queue configuration. */
15021 uint8_t queue_cfg_info;
15023 * If this flag is set to '1', then the queues are
15024 * configured asymmetrically on TX and RX sides.
15025 * If this flag is set to '0', then the queues are
15026 * configured symmetrically on TX and RX sides. For
15027 * symmetric configuration, the queue configuration
15028 * including queue ids and service profiles on the
15029 * TX side is the same as the corresponding queue
15030 * configuration on the RX side.
15032 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
15035 * Bitmask indicating which queues can be configured by the
15036 * hwrm_queue_pfcenable_cfg command.
15038 * Each bit represents a specific priority where bit 0 represents
15039 * priority 0 and bit 7 represents priority 7.
15040 * # A value of 0 indicates that the priority is not configurable by
15041 * the hwrm_queue_pfcenable_cfg command.
15042 * # A value of 1 indicates that the priority is configurable.
15043 * # A hwrm_queue_pfcenable_cfg command shall return error when
15044 * trying to configure a priority that is not configurable.
15046 uint8_t queue_pfcenable_cfg_allowed;
15048 * Bitmask indicating which queues can be configured by the
15049 * hwrm_queue_pri2cos_cfg command.
15051 * Each bit represents a specific queue where bit 0 represents
15052 * queue 0 and bit 7 represents queue 7.
15053 * # A value of 0 indicates that the queue is not configurable
15054 * by the hwrm_queue_pri2cos_cfg command.
15055 * # A value of 1 indicates that the queue is configurable.
15056 * # A hwrm_queue_pri2cos_cfg command shall return error when
15057 * trying to configure a queue that is not configurable.
15059 uint8_t queue_pri2cos_cfg_allowed;
15061 * Bitmask indicating which queues can be configured by the
15062 * hwrm_queue_pri2cos_cfg command.
15064 * Each bit represents a specific queue where bit 0 represents
15065 * queue 0 and bit 7 represents queue 7.
15066 * # A value of 0 indicates that the queue is not configurable
15067 * by the hwrm_queue_pri2cos_cfg command.
15068 * # A value of 1 indicates that the queue is configurable.
15069 * # A hwrm_queue_pri2cos_cfg command shall return error when
15070 * trying to configure a queue not configurable.
15072 uint8_t queue_cos2bw_cfg_allowed;
15074 * ID of CoS Queue 0.
15077 * # This ID can be used on any subsequent call to an hwrm command
15078 * that takes a queue id.
15079 * # IDs must always be queried by this command before any use
15080 * by the driver or software.
15081 * # Any driver or software should not make any assumptions about
15083 * # A value of 0xff indicates that the queue is not available.
15084 * # Available queues may not be in sequential order.
15087 /* This value is applicable to CoS queues only. */
15088 uint8_t queue_id0_service_profile;
15089 /* Lossy (best-effort) */
15090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
15092 /* Lossless (legacy) */
15093 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
15095 /* Lossless RoCE */
15096 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
15098 /* Lossy RoCE CNP */
15099 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15102 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
15104 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15105 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
15107 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
15108 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
15110 * ID of CoS Queue 1.
15113 * # This ID can be used on any subsequent call to an hwrm command
15114 * that takes a queue id.
15115 * # IDs must always be queried by this command before any use
15116 * by the driver or software.
15117 * # Any driver or software should not make any assumptions about
15119 * # A value of 0xff indicates that the queue is not available.
15120 * # Available queues may not be in sequential order.
15123 /* This value is applicable to CoS queues only. */
15124 uint8_t queue_id1_service_profile;
15125 /* Lossy (best-effort) */
15126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
15128 /* Lossless (legacy) */
15129 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
15131 /* Lossless RoCE */
15132 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
15134 /* Lossy RoCE CNP */
15135 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15138 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
15140 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15141 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
15143 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
15144 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
15146 * ID of CoS Queue 2.
15149 * # This ID can be used on any subsequent call to an hwrm command
15150 * that takes a queue id.
15151 * # IDs must always be queried by this command before any use
15152 * by the driver or software.
15153 * # Any driver or software should not make any assumptions about
15155 * # A value of 0xff indicates that the queue is not available.
15156 * # Available queues may not be in sequential order.
15159 /* This value is applicable to CoS queues only. */
15160 uint8_t queue_id2_service_profile;
15161 /* Lossy (best-effort) */
15162 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
15164 /* Lossless (legacy) */
15165 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
15167 /* Lossless RoCE */
15168 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
15170 /* Lossy RoCE CNP */
15171 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15174 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
15176 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15177 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
15179 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
15180 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
15182 * ID of CoS Queue 3.
15185 * # This ID can be used on any subsequent call to an hwrm command
15186 * that takes a queue id.
15187 * # IDs must always be queried by this command before any use
15188 * by the driver or software.
15189 * # Any driver or software should not make any assumptions about
15191 * # A value of 0xff indicates that the queue is not available.
15192 * # Available queues may not be in sequential order.
15195 /* This value is applicable to CoS queues only. */
15196 uint8_t queue_id3_service_profile;
15197 /* Lossy (best-effort) */
15198 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
15200 /* Lossless (legacy) */
15201 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
15203 /* Lossless RoCE */
15204 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
15206 /* Lossy RoCE CNP */
15207 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15210 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
15212 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15213 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
15215 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
15216 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
15218 * ID of CoS Queue 4.
15221 * # This ID can be used on any subsequent call to an hwrm command
15222 * that takes a queue id.
15223 * # IDs must always be queried by this command before any use
15224 * by the driver or software.
15225 * # Any driver or software should not make any assumptions about
15227 * # A value of 0xff indicates that the queue is not available.
15228 * # Available queues may not be in sequential order.
15231 /* This value is applicable to CoS queues only. */
15232 uint8_t queue_id4_service_profile;
15233 /* Lossy (best-effort) */
15234 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
15236 /* Lossless (legacy) */
15237 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
15239 /* Lossless RoCE */
15240 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
15242 /* Lossy RoCE CNP */
15243 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15246 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
15248 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15249 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
15251 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
15252 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
15254 * ID of CoS Queue 5.
15257 * # This ID can be used on any subsequent call to an hwrm command
15258 * that takes a queue id.
15259 * # IDs must always be queried by this command before any use
15260 * by the driver or software.
15261 * # Any driver or software should not make any assumptions about
15263 * # A value of 0xff indicates that the queue is not available.
15264 * # Available queues may not be in sequential order.
15267 /* This value is applicable to CoS queues only. */
15268 uint8_t queue_id5_service_profile;
15269 /* Lossy (best-effort) */
15270 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
15272 /* Lossless (legacy) */
15273 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
15275 /* Lossless RoCE */
15276 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
15278 /* Lossy RoCE CNP */
15279 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15282 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
15284 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15285 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
15287 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
15288 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
15290 * ID of CoS Queue 6.
15293 * # This ID can be used on any subsequent call to an hwrm command
15294 * that takes a queue id.
15295 * # IDs must always be queried by this command before any use
15296 * by the driver or software.
15297 * # Any driver or software should not make any assumptions about
15299 * # A value of 0xff indicates that the queue is not available.
15300 * # Available queues may not be in sequential order.
15303 /* This value is applicable to CoS queues only. */
15304 uint8_t queue_id6_service_profile;
15305 /* Lossy (best-effort) */
15306 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
15308 /* Lossless (legacy) */
15309 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
15311 /* Lossless RoCE */
15312 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
15314 /* Lossy RoCE CNP */
15315 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15318 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
15320 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15321 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
15323 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
15324 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
15326 * ID of CoS Queue 7.
15329 * # This ID can be used on any subsequent call to an hwrm command
15330 * that takes a queue id.
15331 * # IDs must always be queried by this command before any use
15332 * by the driver or software.
15333 * # Any driver or software should not make any assumptions about
15335 * # A value of 0xff indicates that the queue is not available.
15336 * # Available queues may not be in sequential order.
15339 /* This value is applicable to CoS queues only. */
15340 uint8_t queue_id7_service_profile;
15341 /* Lossy (best-effort) */
15342 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
15344 /* Lossless (legacy) */
15345 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
15347 /* Lossless RoCE */
15348 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
15350 /* Lossy RoCE CNP */
15351 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
15354 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
15356 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15357 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
15359 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
15360 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
15362 * This field is used in Output records to indicate that the output
15363 * is completely written to RAM. This field should be read as '1'
15364 * to indicate that the output has been completely written.
15365 * When writing a command completion or response to an internal processor,
15366 * the order of writes has to be such that this field is written last.
15369 } __attribute__((packed));
15371 /*******************
15372 * hwrm_queue_qcfg *
15373 *******************/
15376 /* hwrm_queue_qcfg_input (size:192b/24B) */
15377 struct hwrm_queue_qcfg_input {
15378 /* The HWRM command request type. */
15381 * The completion ring to send the completion event on. This should
15382 * be the NQ ID returned from the `nq_alloc` HWRM command.
15384 uint16_t cmpl_ring;
15386 * The sequence ID is used by the driver for tracking multiple
15387 * commands. This ID is treated as opaque data by the firmware and
15388 * the value is returned in the `hwrm_resp_hdr` upon completion.
15392 * The target ID of the command:
15393 * * 0x0-0xFFF8 - The function ID
15394 * * 0xFFF8-0xFFFE - Reserved for internal processors
15397 uint16_t target_id;
15399 * A physical address pointer pointing to a host buffer that the
15400 * command's response data will be written. This can be either a host
15401 * physical address (HPA) or a guest physical address (GPA) and must
15402 * point to a physically contiguous block of memory.
15404 uint64_t resp_addr;
15407 * Enumeration denoting the RX, TX type of the resource.
15408 * This enumeration is used for resources that are similar for both
15409 * TX and RX paths of the chip.
15411 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
15413 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15415 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15416 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
15417 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
15418 /* Queue ID of the queue. */
15420 } __attribute__((packed));
15422 /* hwrm_queue_qcfg_output (size:128b/16B) */
15423 struct hwrm_queue_qcfg_output {
15424 /* The specific error status for the command. */
15425 uint16_t error_code;
15426 /* The HWRM command request type. */
15428 /* The sequence ID from the original command. */
15430 /* The length of the response data in number of bytes. */
15433 * This value is a the estimate packet length used in the
15436 uint32_t queue_len;
15437 /* This value is applicable to CoS queues only. */
15438 uint8_t service_profile;
15439 /* Lossy (best-effort) */
15440 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
15442 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
15443 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15444 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
15445 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
15446 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
15447 /* Information about queue configuration. */
15448 uint8_t queue_cfg_info;
15450 * If this flag is set to '1', then the queue is
15451 * configured asymmetrically on TX and RX sides.
15452 * If this flag is set to '0', then this queue is
15453 * configured symmetrically on TX and RX sides.
15455 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
15459 * This field is used in Output records to indicate that the output
15460 * is completely written to RAM. This field should be read as '1'
15461 * to indicate that the output has been completely written.
15462 * When writing a command completion or response to an internal processor,
15463 * the order of writes has to be such that this field is written last.
15466 } __attribute__((packed));
15468 /******************
15470 ******************/
15473 /* hwrm_queue_cfg_input (size:320b/40B) */
15474 struct hwrm_queue_cfg_input {
15475 /* The HWRM command request type. */
15478 * The completion ring to send the completion event on. This should
15479 * be the NQ ID returned from the `nq_alloc` HWRM command.
15481 uint16_t cmpl_ring;
15483 * The sequence ID is used by the driver for tracking multiple
15484 * commands. This ID is treated as opaque data by the firmware and
15485 * the value is returned in the `hwrm_resp_hdr` upon completion.
15489 * The target ID of the command:
15490 * * 0x0-0xFFF8 - The function ID
15491 * * 0xFFF8-0xFFFE - Reserved for internal processors
15494 uint16_t target_id;
15496 * A physical address pointer pointing to a host buffer that the
15497 * command's response data will be written. This can be either a host
15498 * physical address (HPA) or a guest physical address (GPA) and must
15499 * point to a physically contiguous block of memory.
15501 uint64_t resp_addr;
15504 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
15505 * This enumeration is used for resources that are similar for both
15506 * TX and RX paths of the chip.
15508 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
15509 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
15511 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15513 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15514 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
15515 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
15516 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
15517 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
15520 * This bit must be '1' for the dflt_len field to be
15523 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
15525 * This bit must be '1' for the service_profile field to be
15528 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
15529 /* Queue ID of queue that is to be configured by this function. */
15532 * This value is a the estimate packet length used in the
15534 * Set to 0xFF... (All Fs) to not adjust this value.
15537 /* This value is applicable to CoS queues only. */
15538 uint8_t service_profile;
15539 /* Lossy (best-effort) */
15540 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
15542 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
15543 /* Set to 0xFF... (All Fs) if there is no service profile specified */
15544 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
15545 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
15546 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
15547 uint8_t unused_0[7];
15548 } __attribute__((packed));
15550 /* hwrm_queue_cfg_output (size:128b/16B) */
15551 struct hwrm_queue_cfg_output {
15552 /* The specific error status for the command. */
15553 uint16_t error_code;
15554 /* The HWRM command request type. */
15556 /* The sequence ID from the original command. */
15558 /* The length of the response data in number of bytes. */
15560 uint8_t unused_0[7];
15562 * This field is used in Output records to indicate that the output
15563 * is completely written to RAM. This field should be read as '1'
15564 * to indicate that the output has been completely written.
15565 * When writing a command completion or response to an internal processor,
15566 * the order of writes has to be such that this field is written last.
15569 } __attribute__((packed));
15571 /*****************************
15572 * hwrm_queue_pfcenable_qcfg *
15573 *****************************/
15576 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
15577 struct hwrm_queue_pfcenable_qcfg_input {
15578 /* The HWRM command request type. */
15581 * The completion ring to send the completion event on. This should
15582 * be the NQ ID returned from the `nq_alloc` HWRM command.
15584 uint16_t cmpl_ring;
15586 * The sequence ID is used by the driver for tracking multiple
15587 * commands. This ID is treated as opaque data by the firmware and
15588 * the value is returned in the `hwrm_resp_hdr` upon completion.
15592 * The target ID of the command:
15593 * * 0x0-0xFFF8 - The function ID
15594 * * 0xFFF8-0xFFFE - Reserved for internal processors
15597 uint16_t target_id;
15599 * A physical address pointer pointing to a host buffer that the
15600 * command's response data will be written. This can be either a host
15601 * physical address (HPA) or a guest physical address (GPA) and must
15602 * point to a physically contiguous block of memory.
15604 uint64_t resp_addr;
15606 * Port ID of port for which the table is being configured.
15607 * The HWRM needs to check whether this function is allowed
15608 * to configure pri2cos mapping on this port.
15611 uint8_t unused_0[6];
15612 } __attribute__((packed));
15614 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
15615 struct hwrm_queue_pfcenable_qcfg_output {
15616 /* The specific error status for the command. */
15617 uint16_t error_code;
15618 /* The HWRM command request type. */
15620 /* The sequence ID from the original command. */
15622 /* The length of the response data in number of bytes. */
15625 /* If set to 1, then PFC is enabled on PRI 0. */
15626 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
15628 /* If set to 1, then PFC is enabled on PRI 1. */
15629 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
15631 /* If set to 1, then PFC is enabled on PRI 2. */
15632 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
15634 /* If set to 1, then PFC is enabled on PRI 3. */
15635 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
15637 /* If set to 1, then PFC is enabled on PRI 4. */
15638 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
15640 /* If set to 1, then PFC is enabled on PRI 5. */
15641 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
15643 /* If set to 1, then PFC is enabled on PRI 6. */
15644 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
15646 /* If set to 1, then PFC is enabled on PRI 7. */
15647 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
15649 uint8_t unused_0[3];
15651 * This field is used in Output records to indicate that the output
15652 * is completely written to RAM. This field should be read as '1'
15653 * to indicate that the output has been completely written.
15654 * When writing a command completion or response to an internal processor,
15655 * the order of writes has to be such that this field is written last.
15658 } __attribute__((packed));
15660 /****************************
15661 * hwrm_queue_pfcenable_cfg *
15662 ****************************/
15665 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
15666 struct hwrm_queue_pfcenable_cfg_input {
15667 /* The HWRM command request type. */
15670 * The completion ring to send the completion event on. This should
15671 * be the NQ ID returned from the `nq_alloc` HWRM command.
15673 uint16_t cmpl_ring;
15675 * The sequence ID is used by the driver for tracking multiple
15676 * commands. This ID is treated as opaque data by the firmware and
15677 * the value is returned in the `hwrm_resp_hdr` upon completion.
15681 * The target ID of the command:
15682 * * 0x0-0xFFF8 - The function ID
15683 * * 0xFFF8-0xFFFE - Reserved for internal processors
15686 uint16_t target_id;
15688 * A physical address pointer pointing to a host buffer that the
15689 * command's response data will be written. This can be either a host
15690 * physical address (HPA) or a guest physical address (GPA) and must
15691 * point to a physically contiguous block of memory.
15693 uint64_t resp_addr;
15695 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
15696 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
15698 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
15699 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
15701 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
15702 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
15704 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
15705 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
15707 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
15708 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
15710 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
15711 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
15713 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
15714 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
15716 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
15717 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
15720 * Port ID of port for which the table is being configured.
15721 * The HWRM needs to check whether this function is allowed
15722 * to configure pri2cos mapping on this port.
15725 uint8_t unused_0[2];
15726 } __attribute__((packed));
15728 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
15729 struct hwrm_queue_pfcenable_cfg_output {
15730 /* The specific error status for the command. */
15731 uint16_t error_code;
15732 /* The HWRM command request type. */
15734 /* The sequence ID from the original command. */
15736 /* The length of the response data in number of bytes. */
15738 uint8_t unused_0[7];
15740 * This field is used in Output records to indicate that the output
15741 * is completely written to RAM. This field should be read as '1'
15742 * to indicate that the output has been completely written.
15743 * When writing a command completion or response to an internal processor,
15744 * the order of writes has to be such that this field is written last.
15747 } __attribute__((packed));
15749 /***************************
15750 * hwrm_queue_pri2cos_qcfg *
15751 ***************************/
15754 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
15755 struct hwrm_queue_pri2cos_qcfg_input {
15756 /* The HWRM command request type. */
15759 * The completion ring to send the completion event on. This should
15760 * be the NQ ID returned from the `nq_alloc` HWRM command.
15762 uint16_t cmpl_ring;
15764 * The sequence ID is used by the driver for tracking multiple
15765 * commands. This ID is treated as opaque data by the firmware and
15766 * the value is returned in the `hwrm_resp_hdr` upon completion.
15770 * The target ID of the command:
15771 * * 0x0-0xFFF8 - The function ID
15772 * * 0xFFF8-0xFFFE - Reserved for internal processors
15775 uint16_t target_id;
15777 * A physical address pointer pointing to a host buffer that the
15778 * command's response data will be written. This can be either a host
15779 * physical address (HPA) or a guest physical address (GPA) and must
15780 * point to a physically contiguous block of memory.
15782 uint64_t resp_addr;
15785 * Enumeration denoting the RX, TX type of the resource.
15786 * This enumeration is used for resources that are similar for both
15787 * TX and RX paths of the chip.
15789 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
15791 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15793 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15794 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
15795 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
15797 * When this bit is set to '0', the query is
15798 * for VLAN PRI field in tunnel headers.
15799 * When this bit is set to '1', the query is
15800 * for VLAN PRI field in inner packet headers.
15802 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
15804 * Port ID of port for which the table is being configured.
15805 * The HWRM needs to check whether this function is allowed
15806 * to configure pri2cos mapping on this port.
15809 uint8_t unused_0[3];
15810 } __attribute__((packed));
15812 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
15813 struct hwrm_queue_pri2cos_qcfg_output {
15814 /* The specific error status for the command. */
15815 uint16_t error_code;
15816 /* The HWRM command request type. */
15818 /* The sequence ID from the original command. */
15820 /* The length of the response data in number of bytes. */
15823 * CoS Queue assigned to priority 0. This value can only
15824 * be changed before traffic has started.
15825 * A value of 0xff indicates that no CoS queue is assigned to the
15826 * specified priority.
15828 uint8_t pri0_cos_queue_id;
15830 * CoS Queue assigned to priority 1. This value can only
15831 * be changed before traffic has started.
15832 * A value of 0xff indicates that no CoS queue is assigned to the
15833 * specified priority.
15835 uint8_t pri1_cos_queue_id;
15837 * CoS Queue assigned to priority 2 This value can only
15838 * be changed before traffic has started.
15839 * A value of 0xff indicates that no CoS queue is assigned to the
15840 * specified priority.
15842 uint8_t pri2_cos_queue_id;
15844 * CoS Queue assigned to priority 3. This value can only
15845 * be changed before traffic has started.
15846 * A value of 0xff indicates that no CoS queue is assigned to the
15847 * specified priority.
15849 uint8_t pri3_cos_queue_id;
15851 * CoS Queue assigned to priority 4. This value can only
15852 * be changed before traffic has started.
15853 * A value of 0xff indicates that no CoS queue is assigned to the
15854 * specified priority.
15856 uint8_t pri4_cos_queue_id;
15858 * CoS Queue assigned to priority 5. This value can only
15859 * be changed before traffic has started.
15860 * A value of 0xff indicates that no CoS queue is assigned to the
15861 * specified priority.
15863 uint8_t pri5_cos_queue_id;
15865 * CoS Queue assigned to priority 6. This value can only
15866 * be changed before traffic has started.
15867 * A value of 0xff indicates that no CoS queue is assigned to the
15868 * specified priority.
15870 uint8_t pri6_cos_queue_id;
15872 * CoS Queue assigned to priority 7. This value can only
15873 * be changed before traffic has started.
15874 * A value of 0xff indicates that no CoS queue is assigned to the
15875 * specified priority.
15877 uint8_t pri7_cos_queue_id;
15878 /* Information about queue configuration. */
15879 uint8_t queue_cfg_info;
15881 * If this flag is set to '1', then the PRI to CoS
15882 * configuration is asymmetric on TX and RX sides.
15883 * If this flag is set to '0', then PRI to CoS configuration
15884 * is symmetric on TX and RX sides.
15886 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
15888 uint8_t unused_0[6];
15890 * This field is used in Output records to indicate that the output
15891 * is completely written to RAM. This field should be read as '1'
15892 * to indicate that the output has been completely written.
15893 * When writing a command completion or response to an internal processor,
15894 * the order of writes has to be such that this field is written last.
15897 } __attribute__((packed));
15899 /**************************
15900 * hwrm_queue_pri2cos_cfg *
15901 **************************/
15904 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
15905 struct hwrm_queue_pri2cos_cfg_input {
15906 /* The HWRM command request type. */
15909 * The completion ring to send the completion event on. This should
15910 * be the NQ ID returned from the `nq_alloc` HWRM command.
15912 uint16_t cmpl_ring;
15914 * The sequence ID is used by the driver for tracking multiple
15915 * commands. This ID is treated as opaque data by the firmware and
15916 * the value is returned in the `hwrm_resp_hdr` upon completion.
15920 * The target ID of the command:
15921 * * 0x0-0xFFF8 - The function ID
15922 * * 0xFFF8-0xFFFE - Reserved for internal processors
15925 uint16_t target_id;
15927 * A physical address pointer pointing to a host buffer that the
15928 * command's response data will be written. This can be either a host
15929 * physical address (HPA) or a guest physical address (GPA) and must
15930 * point to a physically contiguous block of memory.
15932 uint64_t resp_addr;
15935 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
15936 * This enumeration is used for resources that are similar for both
15937 * TX and RX paths of the chip.
15939 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
15940 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
15942 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
15944 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
15945 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
15946 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
15947 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
15948 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
15950 * When this bit is set to '0', the mapping is requested
15951 * for VLAN PRI field in tunnel headers.
15952 * When this bit is set to '1', the mapping is requested
15953 * for VLAN PRI field in inner packet headers.
15955 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
15958 * This bit must be '1' for the pri0_cos_queue_id field to be
15961 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
15964 * This bit must be '1' for the pri1_cos_queue_id field to be
15967 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
15970 * This bit must be '1' for the pri2_cos_queue_id field to be
15973 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
15976 * This bit must be '1' for the pri3_cos_queue_id field to be
15979 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
15982 * This bit must be '1' for the pri4_cos_queue_id field to be
15985 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
15988 * This bit must be '1' for the pri5_cos_queue_id field to be
15991 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
15994 * This bit must be '1' for the pri6_cos_queue_id field to be
15997 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
16000 * This bit must be '1' for the pri7_cos_queue_id field to be
16003 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
16006 * Port ID of port for which the table is being configured.
16007 * The HWRM needs to check whether this function is allowed
16008 * to configure pri2cos mapping on this port.
16012 * CoS Queue assigned to priority 0. This value can only
16013 * be changed before traffic has started.
16015 uint8_t pri0_cos_queue_id;
16017 * CoS Queue assigned to priority 1. This value can only
16018 * be changed before traffic has started.
16020 uint8_t pri1_cos_queue_id;
16022 * CoS Queue assigned to priority 2 This value can only
16023 * be changed before traffic has started.
16025 uint8_t pri2_cos_queue_id;
16027 * CoS Queue assigned to priority 3. This value can only
16028 * be changed before traffic has started.
16030 uint8_t pri3_cos_queue_id;
16032 * CoS Queue assigned to priority 4. This value can only
16033 * be changed before traffic has started.
16035 uint8_t pri4_cos_queue_id;
16037 * CoS Queue assigned to priority 5. This value can only
16038 * be changed before traffic has started.
16040 uint8_t pri5_cos_queue_id;
16042 * CoS Queue assigned to priority 6. This value can only
16043 * be changed before traffic has started.
16045 uint8_t pri6_cos_queue_id;
16047 * CoS Queue assigned to priority 7. This value can only
16048 * be changed before traffic has started.
16050 uint8_t pri7_cos_queue_id;
16051 uint8_t unused_0[7];
16052 } __attribute__((packed));
16054 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
16055 struct hwrm_queue_pri2cos_cfg_output {
16056 /* The specific error status for the command. */
16057 uint16_t error_code;
16058 /* The HWRM command request type. */
16060 /* The sequence ID from the original command. */
16062 /* The length of the response data in number of bytes. */
16064 uint8_t unused_0[7];
16066 * This field is used in Output records to indicate that the output
16067 * is completely written to RAM. This field should be read as '1'
16068 * to indicate that the output has been completely written.
16069 * When writing a command completion or response to an internal processor,
16070 * the order of writes has to be such that this field is written last.
16073 } __attribute__((packed));
16075 /**************************
16076 * hwrm_queue_cos2bw_qcfg *
16077 **************************/
16080 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
16081 struct hwrm_queue_cos2bw_qcfg_input {
16082 /* The HWRM command request type. */
16085 * The completion ring to send the completion event on. This should
16086 * be the NQ ID returned from the `nq_alloc` HWRM command.
16088 uint16_t cmpl_ring;
16090 * The sequence ID is used by the driver for tracking multiple
16091 * commands. This ID is treated as opaque data by the firmware and
16092 * the value is returned in the `hwrm_resp_hdr` upon completion.
16096 * The target ID of the command:
16097 * * 0x0-0xFFF8 - The function ID
16098 * * 0xFFF8-0xFFFE - Reserved for internal processors
16101 uint16_t target_id;
16103 * A physical address pointer pointing to a host buffer that the
16104 * command's response data will be written. This can be either a host
16105 * physical address (HPA) or a guest physical address (GPA) and must
16106 * point to a physically contiguous block of memory.
16108 uint64_t resp_addr;
16110 * Port ID of port for which the table is being configured.
16111 * The HWRM needs to check whether this function is allowed
16112 * to configure TC BW assignment on this port.
16115 uint8_t unused_0[6];
16116 } __attribute__((packed));
16118 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
16119 struct hwrm_queue_cos2bw_qcfg_output {
16120 /* The specific error status for the command. */
16121 uint16_t error_code;
16122 /* The HWRM command request type. */
16124 /* The sequence ID from the original command. */
16126 /* The length of the response data in number of bytes. */
16128 /* ID of CoS Queue 0. */
16133 * Minimum BW allocated to CoS Queue.
16134 * The HWRM will translate this value into byte counter and
16135 * time interval used for this COS inside the device.
16137 uint32_t queue_id0_min_bw;
16138 /* The bandwidth value. */
16139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
16140 UINT32_C(0xfffffff)
16141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
16143 /* The granularity of the value (bits or bytes). */
16144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
16145 UINT32_C(0x10000000)
16146 /* Value is in bits. */
16147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
16148 (UINT32_C(0x0) << 28)
16149 /* Value is in bytes. */
16150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
16151 (UINT32_C(0x1) << 28)
16152 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
16153 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
16154 /* bw_value_unit is 3 b */
16155 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
16156 UINT32_C(0xe0000000)
16157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
16159 /* Value is in Mb or MB (base 10). */
16160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
16161 (UINT32_C(0x0) << 29)
16162 /* Value is in Kb or KB (base 10). */
16163 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
16164 (UINT32_C(0x2) << 29)
16165 /* Value is in bits or bytes. */
16166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
16167 (UINT32_C(0x4) << 29)
16168 /* Value is in Gb or GB (base 10). */
16169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
16170 (UINT32_C(0x6) << 29)
16171 /* Value is in 1/100th of a percentage of total bandwidth. */
16172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16173 (UINT32_C(0x1) << 29)
16175 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
16176 (UINT32_C(0x7) << 29)
16177 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
16178 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
16180 * Maximum BW allocated to CoS Queue.
16181 * The HWRM will translate this value into byte counter and
16182 * time interval used for this COS inside the device.
16184 uint32_t queue_id0_max_bw;
16185 /* The bandwidth value. */
16186 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
16187 UINT32_C(0xfffffff)
16188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
16190 /* The granularity of the value (bits or bytes). */
16191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
16192 UINT32_C(0x10000000)
16193 /* Value is in bits. */
16194 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
16195 (UINT32_C(0x0) << 28)
16196 /* Value is in bytes. */
16197 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
16198 (UINT32_C(0x1) << 28)
16199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
16200 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
16201 /* bw_value_unit is 3 b */
16202 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
16203 UINT32_C(0xe0000000)
16204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
16206 /* Value is in Mb or MB (base 10). */
16207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
16208 (UINT32_C(0x0) << 29)
16209 /* Value is in Kb or KB (base 10). */
16210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
16211 (UINT32_C(0x2) << 29)
16212 /* Value is in bits or bytes. */
16213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
16214 (UINT32_C(0x4) << 29)
16215 /* Value is in Gb or GB (base 10). */
16216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
16217 (UINT32_C(0x6) << 29)
16218 /* Value is in 1/100th of a percentage of total bandwidth. */
16219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16220 (UINT32_C(0x1) << 29)
16222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
16223 (UINT32_C(0x7) << 29)
16224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
16225 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
16226 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16227 uint8_t queue_id0_tsa_assign;
16228 /* Strict Priority */
16229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
16231 /* Enhanced Transmission Selection */
16232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
16235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
16238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
16241 * Priority level for strict priority. Valid only when the
16242 * tsa_assign is 0 - Strict Priority (SP)
16243 * 0..7 - Valid values.
16244 * 8..255 - Reserved.
16246 uint8_t queue_id0_pri_lvl;
16248 * Weight used to allocate remaining BW for this COS after
16249 * servicing guaranteed bandwidths for all COS.
16251 uint8_t queue_id0_bw_weight;
16252 /* ID of CoS Queue 1. */
16255 * Minimum BW allocated to CoS Queue.
16256 * The HWRM will translate this value into byte counter and
16257 * time interval used for this COS inside the device.
16259 uint32_t queue_id1_min_bw;
16260 /* The bandwidth value. */
16261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
16262 UINT32_C(0xfffffff)
16263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
16265 /* The granularity of the value (bits or bytes). */
16266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
16267 UINT32_C(0x10000000)
16268 /* Value is in bits. */
16269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
16270 (UINT32_C(0x0) << 28)
16271 /* Value is in bytes. */
16272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
16273 (UINT32_C(0x1) << 28)
16274 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
16275 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
16276 /* bw_value_unit is 3 b */
16277 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
16278 UINT32_C(0xe0000000)
16279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
16281 /* Value is in Mb or MB (base 10). */
16282 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
16283 (UINT32_C(0x0) << 29)
16284 /* Value is in Kb or KB (base 10). */
16285 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
16286 (UINT32_C(0x2) << 29)
16287 /* Value is in bits or bytes. */
16288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
16289 (UINT32_C(0x4) << 29)
16290 /* Value is in Gb or GB (base 10). */
16291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
16292 (UINT32_C(0x6) << 29)
16293 /* Value is in 1/100th of a percentage of total bandwidth. */
16294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16295 (UINT32_C(0x1) << 29)
16297 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
16298 (UINT32_C(0x7) << 29)
16299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
16300 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
16302 * Maximum BW allocated to CoS queue.
16303 * The HWRM will translate this value into byte counter and
16304 * time interval used for this COS inside the device.
16306 uint32_t queue_id1_max_bw;
16307 /* The bandwidth value. */
16308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
16309 UINT32_C(0xfffffff)
16310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
16312 /* The granularity of the value (bits or bytes). */
16313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
16314 UINT32_C(0x10000000)
16315 /* Value is in bits. */
16316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
16317 (UINT32_C(0x0) << 28)
16318 /* Value is in bytes. */
16319 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
16320 (UINT32_C(0x1) << 28)
16321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
16322 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
16323 /* bw_value_unit is 3 b */
16324 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
16325 UINT32_C(0xe0000000)
16326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
16328 /* Value is in Mb or MB (base 10). */
16329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
16330 (UINT32_C(0x0) << 29)
16331 /* Value is in Kb or KB (base 10). */
16332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
16333 (UINT32_C(0x2) << 29)
16334 /* Value is in bits or bytes. */
16335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
16336 (UINT32_C(0x4) << 29)
16337 /* Value is in Gb or GB (base 10). */
16338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
16339 (UINT32_C(0x6) << 29)
16340 /* Value is in 1/100th of a percentage of total bandwidth. */
16341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16342 (UINT32_C(0x1) << 29)
16344 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
16345 (UINT32_C(0x7) << 29)
16346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
16347 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
16348 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16349 uint8_t queue_id1_tsa_assign;
16350 /* Strict Priority */
16351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
16353 /* Enhanced Transmission Selection */
16354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
16357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
16360 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
16363 * Priority level for strict priority. Valid only when the
16364 * tsa_assign is 0 - Strict Priority (SP)
16365 * 0..7 - Valid values.
16366 * 8..255 - Reserved.
16368 uint8_t queue_id1_pri_lvl;
16370 * Weight used to allocate remaining BW for this COS after
16371 * servicing guaranteed bandwidths for all COS.
16373 uint8_t queue_id1_bw_weight;
16374 /* ID of CoS Queue 2. */
16377 * Minimum BW allocated to CoS Queue.
16378 * The HWRM will translate this value into byte counter and
16379 * time interval used for this COS inside the device.
16381 uint32_t queue_id2_min_bw;
16382 /* The bandwidth value. */
16383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
16384 UINT32_C(0xfffffff)
16385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
16387 /* The granularity of the value (bits or bytes). */
16388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
16389 UINT32_C(0x10000000)
16390 /* Value is in bits. */
16391 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
16392 (UINT32_C(0x0) << 28)
16393 /* Value is in bytes. */
16394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
16395 (UINT32_C(0x1) << 28)
16396 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
16397 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
16398 /* bw_value_unit is 3 b */
16399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
16400 UINT32_C(0xe0000000)
16401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
16403 /* Value is in Mb or MB (base 10). */
16404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
16405 (UINT32_C(0x0) << 29)
16406 /* Value is in Kb or KB (base 10). */
16407 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
16408 (UINT32_C(0x2) << 29)
16409 /* Value is in bits or bytes. */
16410 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
16411 (UINT32_C(0x4) << 29)
16412 /* Value is in Gb or GB (base 10). */
16413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
16414 (UINT32_C(0x6) << 29)
16415 /* Value is in 1/100th of a percentage of total bandwidth. */
16416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16417 (UINT32_C(0x1) << 29)
16419 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
16420 (UINT32_C(0x7) << 29)
16421 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
16422 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
16424 * Maximum BW allocated to CoS queue.
16425 * The HWRM will translate this value into byte counter and
16426 * time interval used for this COS inside the device.
16428 uint32_t queue_id2_max_bw;
16429 /* The bandwidth value. */
16430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
16431 UINT32_C(0xfffffff)
16432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
16434 /* The granularity of the value (bits or bytes). */
16435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
16436 UINT32_C(0x10000000)
16437 /* Value is in bits. */
16438 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
16439 (UINT32_C(0x0) << 28)
16440 /* Value is in bytes. */
16441 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
16442 (UINT32_C(0x1) << 28)
16443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
16444 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
16445 /* bw_value_unit is 3 b */
16446 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
16447 UINT32_C(0xe0000000)
16448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
16450 /* Value is in Mb or MB (base 10). */
16451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
16452 (UINT32_C(0x0) << 29)
16453 /* Value is in Kb or KB (base 10). */
16454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
16455 (UINT32_C(0x2) << 29)
16456 /* Value is in bits or bytes. */
16457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
16458 (UINT32_C(0x4) << 29)
16459 /* Value is in Gb or GB (base 10). */
16460 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
16461 (UINT32_C(0x6) << 29)
16462 /* Value is in 1/100th of a percentage of total bandwidth. */
16463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16464 (UINT32_C(0x1) << 29)
16466 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
16467 (UINT32_C(0x7) << 29)
16468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
16469 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
16470 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16471 uint8_t queue_id2_tsa_assign;
16472 /* Strict Priority */
16473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
16475 /* Enhanced Transmission Selection */
16476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
16479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
16482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
16485 * Priority level for strict priority. Valid only when the
16486 * tsa_assign is 0 - Strict Priority (SP)
16487 * 0..7 - Valid values.
16488 * 8..255 - Reserved.
16490 uint8_t queue_id2_pri_lvl;
16492 * Weight used to allocate remaining BW for this COS after
16493 * servicing guaranteed bandwidths for all COS.
16495 uint8_t queue_id2_bw_weight;
16496 /* ID of CoS Queue 3. */
16499 * Minimum BW allocated to CoS Queue.
16500 * The HWRM will translate this value into byte counter and
16501 * time interval used for this COS inside the device.
16503 uint32_t queue_id3_min_bw;
16504 /* The bandwidth value. */
16505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
16506 UINT32_C(0xfffffff)
16507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
16509 /* The granularity of the value (bits or bytes). */
16510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
16511 UINT32_C(0x10000000)
16512 /* Value is in bits. */
16513 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
16514 (UINT32_C(0x0) << 28)
16515 /* Value is in bytes. */
16516 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
16517 (UINT32_C(0x1) << 28)
16518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
16519 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
16520 /* bw_value_unit is 3 b */
16521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
16522 UINT32_C(0xe0000000)
16523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
16525 /* Value is in Mb or MB (base 10). */
16526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
16527 (UINT32_C(0x0) << 29)
16528 /* Value is in Kb or KB (base 10). */
16529 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
16530 (UINT32_C(0x2) << 29)
16531 /* Value is in bits or bytes. */
16532 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
16533 (UINT32_C(0x4) << 29)
16534 /* Value is in Gb or GB (base 10). */
16535 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
16536 (UINT32_C(0x6) << 29)
16537 /* Value is in 1/100th of a percentage of total bandwidth. */
16538 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16539 (UINT32_C(0x1) << 29)
16541 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
16542 (UINT32_C(0x7) << 29)
16543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
16544 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
16546 * Maximum BW allocated to CoS queue.
16547 * The HWRM will translate this value into byte counter and
16548 * time interval used for this COS inside the device.
16550 uint32_t queue_id3_max_bw;
16551 /* The bandwidth value. */
16552 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
16553 UINT32_C(0xfffffff)
16554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
16556 /* The granularity of the value (bits or bytes). */
16557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
16558 UINT32_C(0x10000000)
16559 /* Value is in bits. */
16560 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
16561 (UINT32_C(0x0) << 28)
16562 /* Value is in bytes. */
16563 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
16564 (UINT32_C(0x1) << 28)
16565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
16566 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
16567 /* bw_value_unit is 3 b */
16568 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
16569 UINT32_C(0xe0000000)
16570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
16572 /* Value is in Mb or MB (base 10). */
16573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
16574 (UINT32_C(0x0) << 29)
16575 /* Value is in Kb or KB (base 10). */
16576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
16577 (UINT32_C(0x2) << 29)
16578 /* Value is in bits or bytes. */
16579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
16580 (UINT32_C(0x4) << 29)
16581 /* Value is in Gb or GB (base 10). */
16582 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
16583 (UINT32_C(0x6) << 29)
16584 /* Value is in 1/100th of a percentage of total bandwidth. */
16585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16586 (UINT32_C(0x1) << 29)
16588 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
16589 (UINT32_C(0x7) << 29)
16590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
16591 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
16592 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16593 uint8_t queue_id3_tsa_assign;
16594 /* Strict Priority */
16595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
16597 /* Enhanced Transmission Selection */
16598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
16601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
16604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
16607 * Priority level for strict priority. Valid only when the
16608 * tsa_assign is 0 - Strict Priority (SP)
16609 * 0..7 - Valid values.
16610 * 8..255 - Reserved.
16612 uint8_t queue_id3_pri_lvl;
16614 * Weight used to allocate remaining BW for this COS after
16615 * servicing guaranteed bandwidths for all COS.
16617 uint8_t queue_id3_bw_weight;
16618 /* ID of CoS Queue 4. */
16621 * Minimum BW allocated to CoS Queue.
16622 * The HWRM will translate this value into byte counter and
16623 * time interval used for this COS inside the device.
16625 uint32_t queue_id4_min_bw;
16626 /* The bandwidth value. */
16627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
16628 UINT32_C(0xfffffff)
16629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
16631 /* The granularity of the value (bits or bytes). */
16632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
16633 UINT32_C(0x10000000)
16634 /* Value is in bits. */
16635 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
16636 (UINT32_C(0x0) << 28)
16637 /* Value is in bytes. */
16638 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
16639 (UINT32_C(0x1) << 28)
16640 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
16641 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
16642 /* bw_value_unit is 3 b */
16643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
16644 UINT32_C(0xe0000000)
16645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
16647 /* Value is in Mb or MB (base 10). */
16648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
16649 (UINT32_C(0x0) << 29)
16650 /* Value is in Kb or KB (base 10). */
16651 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
16652 (UINT32_C(0x2) << 29)
16653 /* Value is in bits or bytes. */
16654 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
16655 (UINT32_C(0x4) << 29)
16656 /* Value is in Gb or GB (base 10). */
16657 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
16658 (UINT32_C(0x6) << 29)
16659 /* Value is in 1/100th of a percentage of total bandwidth. */
16660 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16661 (UINT32_C(0x1) << 29)
16663 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
16664 (UINT32_C(0x7) << 29)
16665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
16666 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
16668 * Maximum BW allocated to CoS queue.
16669 * The HWRM will translate this value into byte counter and
16670 * time interval used for this COS inside the device.
16672 uint32_t queue_id4_max_bw;
16673 /* The bandwidth value. */
16674 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
16675 UINT32_C(0xfffffff)
16676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
16678 /* The granularity of the value (bits or bytes). */
16679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
16680 UINT32_C(0x10000000)
16681 /* Value is in bits. */
16682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
16683 (UINT32_C(0x0) << 28)
16684 /* Value is in bytes. */
16685 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
16686 (UINT32_C(0x1) << 28)
16687 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
16688 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
16689 /* bw_value_unit is 3 b */
16690 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
16691 UINT32_C(0xe0000000)
16692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
16694 /* Value is in Mb or MB (base 10). */
16695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
16696 (UINT32_C(0x0) << 29)
16697 /* Value is in Kb or KB (base 10). */
16698 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
16699 (UINT32_C(0x2) << 29)
16700 /* Value is in bits or bytes. */
16701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
16702 (UINT32_C(0x4) << 29)
16703 /* Value is in Gb or GB (base 10). */
16704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
16705 (UINT32_C(0x6) << 29)
16706 /* Value is in 1/100th of a percentage of total bandwidth. */
16707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16708 (UINT32_C(0x1) << 29)
16710 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
16711 (UINT32_C(0x7) << 29)
16712 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
16713 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
16714 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16715 uint8_t queue_id4_tsa_assign;
16716 /* Strict Priority */
16717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
16719 /* Enhanced Transmission Selection */
16720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
16723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
16726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
16729 * Priority level for strict priority. Valid only when the
16730 * tsa_assign is 0 - Strict Priority (SP)
16731 * 0..7 - Valid values.
16732 * 8..255 - Reserved.
16734 uint8_t queue_id4_pri_lvl;
16736 * Weight used to allocate remaining BW for this COS after
16737 * servicing guaranteed bandwidths for all COS.
16739 uint8_t queue_id4_bw_weight;
16740 /* ID of CoS Queue 5. */
16743 * Minimum BW allocated to CoS Queue.
16744 * The HWRM will translate this value into byte counter and
16745 * time interval used for this COS inside the device.
16747 uint32_t queue_id5_min_bw;
16748 /* The bandwidth value. */
16749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
16750 UINT32_C(0xfffffff)
16751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
16753 /* The granularity of the value (bits or bytes). */
16754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
16755 UINT32_C(0x10000000)
16756 /* Value is in bits. */
16757 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
16758 (UINT32_C(0x0) << 28)
16759 /* Value is in bytes. */
16760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
16761 (UINT32_C(0x1) << 28)
16762 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
16763 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
16764 /* bw_value_unit is 3 b */
16765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
16766 UINT32_C(0xe0000000)
16767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
16769 /* Value is in Mb or MB (base 10). */
16770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
16771 (UINT32_C(0x0) << 29)
16772 /* Value is in Kb or KB (base 10). */
16773 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
16774 (UINT32_C(0x2) << 29)
16775 /* Value is in bits or bytes. */
16776 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
16777 (UINT32_C(0x4) << 29)
16778 /* Value is in Gb or GB (base 10). */
16779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
16780 (UINT32_C(0x6) << 29)
16781 /* Value is in 1/100th of a percentage of total bandwidth. */
16782 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16783 (UINT32_C(0x1) << 29)
16785 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
16786 (UINT32_C(0x7) << 29)
16787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
16788 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
16790 * Maximum BW allocated to CoS queue.
16791 * The HWRM will translate this value into byte counter and
16792 * time interval used for this COS inside the device.
16794 uint32_t queue_id5_max_bw;
16795 /* The bandwidth value. */
16796 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
16797 UINT32_C(0xfffffff)
16798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
16800 /* The granularity of the value (bits or bytes). */
16801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
16802 UINT32_C(0x10000000)
16803 /* Value is in bits. */
16804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
16805 (UINT32_C(0x0) << 28)
16806 /* Value is in bytes. */
16807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
16808 (UINT32_C(0x1) << 28)
16809 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
16810 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
16811 /* bw_value_unit is 3 b */
16812 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
16813 UINT32_C(0xe0000000)
16814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
16816 /* Value is in Mb or MB (base 10). */
16817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
16818 (UINT32_C(0x0) << 29)
16819 /* Value is in Kb or KB (base 10). */
16820 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
16821 (UINT32_C(0x2) << 29)
16822 /* Value is in bits or bytes. */
16823 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
16824 (UINT32_C(0x4) << 29)
16825 /* Value is in Gb or GB (base 10). */
16826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
16827 (UINT32_C(0x6) << 29)
16828 /* Value is in 1/100th of a percentage of total bandwidth. */
16829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16830 (UINT32_C(0x1) << 29)
16832 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
16833 (UINT32_C(0x7) << 29)
16834 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
16835 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
16836 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16837 uint8_t queue_id5_tsa_assign;
16838 /* Strict Priority */
16839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
16841 /* Enhanced Transmission Selection */
16842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
16845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
16848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
16851 * Priority level for strict priority. Valid only when the
16852 * tsa_assign is 0 - Strict Priority (SP)
16853 * 0..7 - Valid values.
16854 * 8..255 - Reserved.
16856 uint8_t queue_id5_pri_lvl;
16858 * Weight used to allocate remaining BW for this COS after
16859 * servicing guaranteed bandwidths for all COS.
16861 uint8_t queue_id5_bw_weight;
16862 /* ID of CoS Queue 6. */
16865 * Minimum BW allocated to CoS Queue.
16866 * The HWRM will translate this value into byte counter and
16867 * time interval used for this COS inside the device.
16869 uint32_t queue_id6_min_bw;
16870 /* The bandwidth value. */
16871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
16872 UINT32_C(0xfffffff)
16873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
16875 /* The granularity of the value (bits or bytes). */
16876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
16877 UINT32_C(0x10000000)
16878 /* Value is in bits. */
16879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
16880 (UINT32_C(0x0) << 28)
16881 /* Value is in bytes. */
16882 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
16883 (UINT32_C(0x1) << 28)
16884 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
16885 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
16886 /* bw_value_unit is 3 b */
16887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
16888 UINT32_C(0xe0000000)
16889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
16891 /* Value is in Mb or MB (base 10). */
16892 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
16893 (UINT32_C(0x0) << 29)
16894 /* Value is in Kb or KB (base 10). */
16895 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
16896 (UINT32_C(0x2) << 29)
16897 /* Value is in bits or bytes. */
16898 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
16899 (UINT32_C(0x4) << 29)
16900 /* Value is in Gb or GB (base 10). */
16901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
16902 (UINT32_C(0x6) << 29)
16903 /* Value is in 1/100th of a percentage of total bandwidth. */
16904 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16905 (UINT32_C(0x1) << 29)
16907 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
16908 (UINT32_C(0x7) << 29)
16909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
16910 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
16912 * Maximum BW allocated to CoS queue.
16913 * The HWRM will translate this value into byte counter and
16914 * time interval used for this COS inside the device.
16916 uint32_t queue_id6_max_bw;
16917 /* The bandwidth value. */
16918 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
16919 UINT32_C(0xfffffff)
16920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
16922 /* The granularity of the value (bits or bytes). */
16923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
16924 UINT32_C(0x10000000)
16925 /* Value is in bits. */
16926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
16927 (UINT32_C(0x0) << 28)
16928 /* Value is in bytes. */
16929 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
16930 (UINT32_C(0x1) << 28)
16931 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
16932 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
16933 /* bw_value_unit is 3 b */
16934 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
16935 UINT32_C(0xe0000000)
16936 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
16938 /* Value is in Mb or MB (base 10). */
16939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
16940 (UINT32_C(0x0) << 29)
16941 /* Value is in Kb or KB (base 10). */
16942 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
16943 (UINT32_C(0x2) << 29)
16944 /* Value is in bits or bytes. */
16945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
16946 (UINT32_C(0x4) << 29)
16947 /* Value is in Gb or GB (base 10). */
16948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
16949 (UINT32_C(0x6) << 29)
16950 /* Value is in 1/100th of a percentage of total bandwidth. */
16951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16952 (UINT32_C(0x1) << 29)
16954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
16955 (UINT32_C(0x7) << 29)
16956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
16957 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
16958 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16959 uint8_t queue_id6_tsa_assign;
16960 /* Strict Priority */
16961 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
16963 /* Enhanced Transmission Selection */
16964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
16967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
16970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
16973 * Priority level for strict priority. Valid only when the
16974 * tsa_assign is 0 - Strict Priority (SP)
16975 * 0..7 - Valid values.
16976 * 8..255 - Reserved.
16978 uint8_t queue_id6_pri_lvl;
16980 * Weight used to allocate remaining BW for this COS after
16981 * servicing guaranteed bandwidths for all COS.
16983 uint8_t queue_id6_bw_weight;
16984 /* ID of CoS Queue 7. */
16987 * Minimum BW allocated to CoS Queue.
16988 * The HWRM will translate this value into byte counter and
16989 * time interval used for this COS inside the device.
16991 uint32_t queue_id7_min_bw;
16992 /* The bandwidth value. */
16993 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
16994 UINT32_C(0xfffffff)
16995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
16997 /* The granularity of the value (bits or bytes). */
16998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
16999 UINT32_C(0x10000000)
17000 /* Value is in bits. */
17001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
17002 (UINT32_C(0x0) << 28)
17003 /* Value is in bytes. */
17004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
17005 (UINT32_C(0x1) << 28)
17006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
17007 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
17008 /* bw_value_unit is 3 b */
17009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
17010 UINT32_C(0xe0000000)
17011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
17013 /* Value is in Mb or MB (base 10). */
17014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
17015 (UINT32_C(0x0) << 29)
17016 /* Value is in Kb or KB (base 10). */
17017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
17018 (UINT32_C(0x2) << 29)
17019 /* Value is in bits or bytes. */
17020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
17021 (UINT32_C(0x4) << 29)
17022 /* Value is in Gb or GB (base 10). */
17023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
17024 (UINT32_C(0x6) << 29)
17025 /* Value is in 1/100th of a percentage of total bandwidth. */
17026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17027 (UINT32_C(0x1) << 29)
17029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
17030 (UINT32_C(0x7) << 29)
17031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
17032 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
17034 * Maximum BW allocated to CoS queue.
17035 * The HWRM will translate this value into byte counter and
17036 * time interval used for this COS inside the device.
17038 uint32_t queue_id7_max_bw;
17039 /* The bandwidth value. */
17040 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
17041 UINT32_C(0xfffffff)
17042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
17044 /* The granularity of the value (bits or bytes). */
17045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
17046 UINT32_C(0x10000000)
17047 /* Value is in bits. */
17048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
17049 (UINT32_C(0x0) << 28)
17050 /* Value is in bytes. */
17051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
17052 (UINT32_C(0x1) << 28)
17053 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
17054 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
17055 /* bw_value_unit is 3 b */
17056 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
17057 UINT32_C(0xe0000000)
17058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
17060 /* Value is in Mb or MB (base 10). */
17061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
17062 (UINT32_C(0x0) << 29)
17063 /* Value is in Kb or KB (base 10). */
17064 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
17065 (UINT32_C(0x2) << 29)
17066 /* Value is in bits or bytes. */
17067 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
17068 (UINT32_C(0x4) << 29)
17069 /* Value is in Gb or GB (base 10). */
17070 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
17071 (UINT32_C(0x6) << 29)
17072 /* Value is in 1/100th of a percentage of total bandwidth. */
17073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17074 (UINT32_C(0x1) << 29)
17076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
17077 (UINT32_C(0x7) << 29)
17078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
17079 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
17080 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17081 uint8_t queue_id7_tsa_assign;
17082 /* Strict Priority */
17083 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
17085 /* Enhanced Transmission Selection */
17086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
17089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
17092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
17095 * Priority level for strict priority. Valid only when the
17096 * tsa_assign is 0 - Strict Priority (SP)
17097 * 0..7 - Valid values.
17098 * 8..255 - Reserved.
17100 uint8_t queue_id7_pri_lvl;
17102 * Weight used to allocate remaining BW for this COS after
17103 * servicing guaranteed bandwidths for all COS.
17105 uint8_t queue_id7_bw_weight;
17106 uint8_t unused_2[4];
17108 * This field is used in Output records to indicate that the output
17109 * is completely written to RAM. This field should be read as '1'
17110 * to indicate that the output has been completely written.
17111 * When writing a command completion or response to an internal processor,
17112 * the order of writes has to be such that this field is written last.
17115 } __attribute__((packed));
17117 /*************************
17118 * hwrm_queue_cos2bw_cfg *
17119 *************************/
17122 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
17123 struct hwrm_queue_cos2bw_cfg_input {
17124 /* The HWRM command request type. */
17127 * The completion ring to send the completion event on. This should
17128 * be the NQ ID returned from the `nq_alloc` HWRM command.
17130 uint16_t cmpl_ring;
17132 * The sequence ID is used by the driver for tracking multiple
17133 * commands. This ID is treated as opaque data by the firmware and
17134 * the value is returned in the `hwrm_resp_hdr` upon completion.
17138 * The target ID of the command:
17139 * * 0x0-0xFFF8 - The function ID
17140 * * 0xFFF8-0xFFFE - Reserved for internal processors
17143 uint16_t target_id;
17145 * A physical address pointer pointing to a host buffer that the
17146 * command's response data will be written. This can be either a host
17147 * physical address (HPA) or a guest physical address (GPA) and must
17148 * point to a physically contiguous block of memory.
17150 uint64_t resp_addr;
17154 * If this bit is set to 1, then all queue_id0 related
17155 * parameters in this command are valid.
17157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
17160 * If this bit is set to 1, then all queue_id1 related
17161 * parameters in this command are valid.
17163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
17166 * If this bit is set to 1, then all queue_id2 related
17167 * parameters in this command are valid.
17169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
17172 * If this bit is set to 1, then all queue_id3 related
17173 * parameters in this command are valid.
17175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
17178 * If this bit is set to 1, then all queue_id4 related
17179 * parameters in this command are valid.
17181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
17184 * If this bit is set to 1, then all queue_id5 related
17185 * parameters in this command are valid.
17187 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
17190 * If this bit is set to 1, then all queue_id6 related
17191 * parameters in this command are valid.
17193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
17196 * If this bit is set to 1, then all queue_id7 related
17197 * parameters in this command are valid.
17199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
17202 * Port ID of port for which the table is being configured.
17203 * The HWRM needs to check whether this function is allowed
17204 * to configure TC BW assignment on this port.
17207 /* ID of CoS Queue 0. */
17211 * Minimum BW allocated to CoS Queue.
17212 * The HWRM will translate this value into byte counter and
17213 * time interval used for this COS inside the device.
17215 uint32_t queue_id0_min_bw;
17216 /* The bandwidth value. */
17217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
17218 UINT32_C(0xfffffff)
17219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
17221 /* The granularity of the value (bits or bytes). */
17222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
17223 UINT32_C(0x10000000)
17224 /* Value is in bits. */
17225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
17226 (UINT32_C(0x0) << 28)
17227 /* Value is in bytes. */
17228 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
17229 (UINT32_C(0x1) << 28)
17230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
17231 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
17232 /* bw_value_unit is 3 b */
17233 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
17234 UINT32_C(0xe0000000)
17235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
17237 /* Value is in Mb or MB (base 10). */
17238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
17239 (UINT32_C(0x0) << 29)
17240 /* Value is in Kb or KB (base 10). */
17241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
17242 (UINT32_C(0x2) << 29)
17243 /* Value is in bits or bytes. */
17244 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
17245 (UINT32_C(0x4) << 29)
17246 /* Value is in Gb or GB (base 10). */
17247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
17248 (UINT32_C(0x6) << 29)
17249 /* Value is in 1/100th of a percentage of total bandwidth. */
17250 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17251 (UINT32_C(0x1) << 29)
17253 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
17254 (UINT32_C(0x7) << 29)
17255 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
17256 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
17258 * Maximum BW allocated to CoS Queue.
17259 * The HWRM will translate this value into byte counter and
17260 * time interval used for this COS inside the device.
17262 uint32_t queue_id0_max_bw;
17263 /* The bandwidth value. */
17264 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
17265 UINT32_C(0xfffffff)
17266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
17268 /* The granularity of the value (bits or bytes). */
17269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
17270 UINT32_C(0x10000000)
17271 /* Value is in bits. */
17272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
17273 (UINT32_C(0x0) << 28)
17274 /* Value is in bytes. */
17275 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
17276 (UINT32_C(0x1) << 28)
17277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
17278 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
17279 /* bw_value_unit is 3 b */
17280 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
17281 UINT32_C(0xe0000000)
17282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
17284 /* Value is in Mb or MB (base 10). */
17285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
17286 (UINT32_C(0x0) << 29)
17287 /* Value is in Kb or KB (base 10). */
17288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
17289 (UINT32_C(0x2) << 29)
17290 /* Value is in bits or bytes. */
17291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
17292 (UINT32_C(0x4) << 29)
17293 /* Value is in Gb or GB (base 10). */
17294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
17295 (UINT32_C(0x6) << 29)
17296 /* Value is in 1/100th of a percentage of total bandwidth. */
17297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17298 (UINT32_C(0x1) << 29)
17300 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
17301 (UINT32_C(0x7) << 29)
17302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
17303 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
17304 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17305 uint8_t queue_id0_tsa_assign;
17306 /* Strict Priority */
17307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
17309 /* Enhanced Transmission Selection */
17310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
17313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
17316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
17319 * Priority level for strict priority. Valid only when the
17320 * tsa_assign is 0 - Strict Priority (SP)
17321 * 0..7 - Valid values.
17322 * 8..255 - Reserved.
17324 uint8_t queue_id0_pri_lvl;
17326 * Weight used to allocate remaining BW for this COS after
17327 * servicing guaranteed bandwidths for all COS.
17329 uint8_t queue_id0_bw_weight;
17330 /* ID of CoS Queue 1. */
17333 * Minimum BW allocated to CoS Queue.
17334 * The HWRM will translate this value into byte counter and
17335 * time interval used for this COS inside the device.
17337 uint32_t queue_id1_min_bw;
17338 /* The bandwidth value. */
17339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
17340 UINT32_C(0xfffffff)
17341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
17343 /* The granularity of the value (bits or bytes). */
17344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
17345 UINT32_C(0x10000000)
17346 /* Value is in bits. */
17347 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
17348 (UINT32_C(0x0) << 28)
17349 /* Value is in bytes. */
17350 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
17351 (UINT32_C(0x1) << 28)
17352 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
17353 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
17354 /* bw_value_unit is 3 b */
17355 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
17356 UINT32_C(0xe0000000)
17357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
17359 /* Value is in Mb or MB (base 10). */
17360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
17361 (UINT32_C(0x0) << 29)
17362 /* Value is in Kb or KB (base 10). */
17363 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
17364 (UINT32_C(0x2) << 29)
17365 /* Value is in bits or bytes. */
17366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
17367 (UINT32_C(0x4) << 29)
17368 /* Value is in Gb or GB (base 10). */
17369 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
17370 (UINT32_C(0x6) << 29)
17371 /* Value is in 1/100th of a percentage of total bandwidth. */
17372 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17373 (UINT32_C(0x1) << 29)
17375 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
17376 (UINT32_C(0x7) << 29)
17377 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
17378 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
17380 * Maximum BW allocated to CoS queue.
17381 * The HWRM will translate this value into byte counter and
17382 * time interval used for this COS inside the device.
17384 uint32_t queue_id1_max_bw;
17385 /* The bandwidth value. */
17386 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
17387 UINT32_C(0xfffffff)
17388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
17390 /* The granularity of the value (bits or bytes). */
17391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
17392 UINT32_C(0x10000000)
17393 /* Value is in bits. */
17394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
17395 (UINT32_C(0x0) << 28)
17396 /* Value is in bytes. */
17397 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
17398 (UINT32_C(0x1) << 28)
17399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
17400 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
17401 /* bw_value_unit is 3 b */
17402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
17403 UINT32_C(0xe0000000)
17404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
17406 /* Value is in Mb or MB (base 10). */
17407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
17408 (UINT32_C(0x0) << 29)
17409 /* Value is in Kb or KB (base 10). */
17410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
17411 (UINT32_C(0x2) << 29)
17412 /* Value is in bits or bytes. */
17413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
17414 (UINT32_C(0x4) << 29)
17415 /* Value is in Gb or GB (base 10). */
17416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
17417 (UINT32_C(0x6) << 29)
17418 /* Value is in 1/100th of a percentage of total bandwidth. */
17419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17420 (UINT32_C(0x1) << 29)
17422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
17423 (UINT32_C(0x7) << 29)
17424 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
17425 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
17426 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17427 uint8_t queue_id1_tsa_assign;
17428 /* Strict Priority */
17429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
17431 /* Enhanced Transmission Selection */
17432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
17435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
17438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
17441 * Priority level for strict priority. Valid only when the
17442 * tsa_assign is 0 - Strict Priority (SP)
17443 * 0..7 - Valid values.
17444 * 8..255 - Reserved.
17446 uint8_t queue_id1_pri_lvl;
17448 * Weight used to allocate remaining BW for this COS after
17449 * servicing guaranteed bandwidths for all COS.
17451 uint8_t queue_id1_bw_weight;
17452 /* ID of CoS Queue 2. */
17455 * Minimum BW allocated to CoS Queue.
17456 * The HWRM will translate this value into byte counter and
17457 * time interval used for this COS inside the device.
17459 uint32_t queue_id2_min_bw;
17460 /* The bandwidth value. */
17461 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
17462 UINT32_C(0xfffffff)
17463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
17465 /* The granularity of the value (bits or bytes). */
17466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
17467 UINT32_C(0x10000000)
17468 /* Value is in bits. */
17469 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
17470 (UINT32_C(0x0) << 28)
17471 /* Value is in bytes. */
17472 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
17473 (UINT32_C(0x1) << 28)
17474 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
17475 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
17476 /* bw_value_unit is 3 b */
17477 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
17478 UINT32_C(0xe0000000)
17479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
17481 /* Value is in Mb or MB (base 10). */
17482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
17483 (UINT32_C(0x0) << 29)
17484 /* Value is in Kb or KB (base 10). */
17485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
17486 (UINT32_C(0x2) << 29)
17487 /* Value is in bits or bytes. */
17488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
17489 (UINT32_C(0x4) << 29)
17490 /* Value is in Gb or GB (base 10). */
17491 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
17492 (UINT32_C(0x6) << 29)
17493 /* Value is in 1/100th of a percentage of total bandwidth. */
17494 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17495 (UINT32_C(0x1) << 29)
17497 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
17498 (UINT32_C(0x7) << 29)
17499 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
17500 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
17502 * Maximum BW allocated to CoS queue.
17503 * The HWRM will translate this value into byte counter and
17504 * time interval used for this COS inside the device.
17506 uint32_t queue_id2_max_bw;
17507 /* The bandwidth value. */
17508 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
17509 UINT32_C(0xfffffff)
17510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
17512 /* The granularity of the value (bits or bytes). */
17513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
17514 UINT32_C(0x10000000)
17515 /* Value is in bits. */
17516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
17517 (UINT32_C(0x0) << 28)
17518 /* Value is in bytes. */
17519 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
17520 (UINT32_C(0x1) << 28)
17521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
17522 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
17523 /* bw_value_unit is 3 b */
17524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
17525 UINT32_C(0xe0000000)
17526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
17528 /* Value is in Mb or MB (base 10). */
17529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
17530 (UINT32_C(0x0) << 29)
17531 /* Value is in Kb or KB (base 10). */
17532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
17533 (UINT32_C(0x2) << 29)
17534 /* Value is in bits or bytes. */
17535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
17536 (UINT32_C(0x4) << 29)
17537 /* Value is in Gb or GB (base 10). */
17538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
17539 (UINT32_C(0x6) << 29)
17540 /* Value is in 1/100th of a percentage of total bandwidth. */
17541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17542 (UINT32_C(0x1) << 29)
17544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
17545 (UINT32_C(0x7) << 29)
17546 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
17547 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
17548 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17549 uint8_t queue_id2_tsa_assign;
17550 /* Strict Priority */
17551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
17553 /* Enhanced Transmission Selection */
17554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
17557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
17560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
17563 * Priority level for strict priority. Valid only when the
17564 * tsa_assign is 0 - Strict Priority (SP)
17565 * 0..7 - Valid values.
17566 * 8..255 - Reserved.
17568 uint8_t queue_id2_pri_lvl;
17570 * Weight used to allocate remaining BW for this COS after
17571 * servicing guaranteed bandwidths for all COS.
17573 uint8_t queue_id2_bw_weight;
17574 /* ID of CoS Queue 3. */
17577 * Minimum BW allocated to CoS Queue.
17578 * The HWRM will translate this value into byte counter and
17579 * time interval used for this COS inside the device.
17581 uint32_t queue_id3_min_bw;
17582 /* The bandwidth value. */
17583 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
17584 UINT32_C(0xfffffff)
17585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
17587 /* The granularity of the value (bits or bytes). */
17588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
17589 UINT32_C(0x10000000)
17590 /* Value is in bits. */
17591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
17592 (UINT32_C(0x0) << 28)
17593 /* Value is in bytes. */
17594 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
17595 (UINT32_C(0x1) << 28)
17596 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
17597 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
17598 /* bw_value_unit is 3 b */
17599 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
17600 UINT32_C(0xe0000000)
17601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
17603 /* Value is in Mb or MB (base 10). */
17604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
17605 (UINT32_C(0x0) << 29)
17606 /* Value is in Kb or KB (base 10). */
17607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
17608 (UINT32_C(0x2) << 29)
17609 /* Value is in bits or bytes. */
17610 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
17611 (UINT32_C(0x4) << 29)
17612 /* Value is in Gb or GB (base 10). */
17613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
17614 (UINT32_C(0x6) << 29)
17615 /* Value is in 1/100th of a percentage of total bandwidth. */
17616 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17617 (UINT32_C(0x1) << 29)
17619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
17620 (UINT32_C(0x7) << 29)
17621 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
17622 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
17624 * Maximum BW allocated to CoS queue.
17625 * The HWRM will translate this value into byte counter and
17626 * time interval used for this COS inside the device.
17628 uint32_t queue_id3_max_bw;
17629 /* The bandwidth value. */
17630 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
17631 UINT32_C(0xfffffff)
17632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
17634 /* The granularity of the value (bits or bytes). */
17635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
17636 UINT32_C(0x10000000)
17637 /* Value is in bits. */
17638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
17639 (UINT32_C(0x0) << 28)
17640 /* Value is in bytes. */
17641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
17642 (UINT32_C(0x1) << 28)
17643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
17644 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
17645 /* bw_value_unit is 3 b */
17646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
17647 UINT32_C(0xe0000000)
17648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
17650 /* Value is in Mb or MB (base 10). */
17651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
17652 (UINT32_C(0x0) << 29)
17653 /* Value is in Kb or KB (base 10). */
17654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
17655 (UINT32_C(0x2) << 29)
17656 /* Value is in bits or bytes. */
17657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
17658 (UINT32_C(0x4) << 29)
17659 /* Value is in Gb or GB (base 10). */
17660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
17661 (UINT32_C(0x6) << 29)
17662 /* Value is in 1/100th of a percentage of total bandwidth. */
17663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17664 (UINT32_C(0x1) << 29)
17666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
17667 (UINT32_C(0x7) << 29)
17668 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
17669 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
17670 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17671 uint8_t queue_id3_tsa_assign;
17672 /* Strict Priority */
17673 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
17675 /* Enhanced Transmission Selection */
17676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
17679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
17682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
17685 * Priority level for strict priority. Valid only when the
17686 * tsa_assign is 0 - Strict Priority (SP)
17687 * 0..7 - Valid values.
17688 * 8..255 - Reserved.
17690 uint8_t queue_id3_pri_lvl;
17692 * Weight used to allocate remaining BW for this COS after
17693 * servicing guaranteed bandwidths for all COS.
17695 uint8_t queue_id3_bw_weight;
17696 /* ID of CoS Queue 4. */
17699 * Minimum BW allocated to CoS Queue.
17700 * The HWRM will translate this value into byte counter and
17701 * time interval used for this COS inside the device.
17703 uint32_t queue_id4_min_bw;
17704 /* The bandwidth value. */
17705 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
17706 UINT32_C(0xfffffff)
17707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
17709 /* The granularity of the value (bits or bytes). */
17710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
17711 UINT32_C(0x10000000)
17712 /* Value is in bits. */
17713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
17714 (UINT32_C(0x0) << 28)
17715 /* Value is in bytes. */
17716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
17717 (UINT32_C(0x1) << 28)
17718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
17719 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
17720 /* bw_value_unit is 3 b */
17721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
17722 UINT32_C(0xe0000000)
17723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
17725 /* Value is in Mb or MB (base 10). */
17726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
17727 (UINT32_C(0x0) << 29)
17728 /* Value is in Kb or KB (base 10). */
17729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
17730 (UINT32_C(0x2) << 29)
17731 /* Value is in bits or bytes. */
17732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
17733 (UINT32_C(0x4) << 29)
17734 /* Value is in Gb or GB (base 10). */
17735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
17736 (UINT32_C(0x6) << 29)
17737 /* Value is in 1/100th of a percentage of total bandwidth. */
17738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17739 (UINT32_C(0x1) << 29)
17741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
17742 (UINT32_C(0x7) << 29)
17743 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
17744 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
17746 * Maximum BW allocated to CoS queue.
17747 * The HWRM will translate this value into byte counter and
17748 * time interval used for this COS inside the device.
17750 uint32_t queue_id4_max_bw;
17751 /* The bandwidth value. */
17752 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
17753 UINT32_C(0xfffffff)
17754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
17756 /* The granularity of the value (bits or bytes). */
17757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
17758 UINT32_C(0x10000000)
17759 /* Value is in bits. */
17760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
17761 (UINT32_C(0x0) << 28)
17762 /* Value is in bytes. */
17763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
17764 (UINT32_C(0x1) << 28)
17765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
17766 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
17767 /* bw_value_unit is 3 b */
17768 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
17769 UINT32_C(0xe0000000)
17770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
17772 /* Value is in Mb or MB (base 10). */
17773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
17774 (UINT32_C(0x0) << 29)
17775 /* Value is in Kb or KB (base 10). */
17776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
17777 (UINT32_C(0x2) << 29)
17778 /* Value is in bits or bytes. */
17779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
17780 (UINT32_C(0x4) << 29)
17781 /* Value is in Gb or GB (base 10). */
17782 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
17783 (UINT32_C(0x6) << 29)
17784 /* Value is in 1/100th of a percentage of total bandwidth. */
17785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17786 (UINT32_C(0x1) << 29)
17788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
17789 (UINT32_C(0x7) << 29)
17790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
17791 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
17792 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17793 uint8_t queue_id4_tsa_assign;
17794 /* Strict Priority */
17795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
17797 /* Enhanced Transmission Selection */
17798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
17801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
17804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
17807 * Priority level for strict priority. Valid only when the
17808 * tsa_assign is 0 - Strict Priority (SP)
17809 * 0..7 - Valid values.
17810 * 8..255 - Reserved.
17812 uint8_t queue_id4_pri_lvl;
17814 * Weight used to allocate remaining BW for this COS after
17815 * servicing guaranteed bandwidths for all COS.
17817 uint8_t queue_id4_bw_weight;
17818 /* ID of CoS Queue 5. */
17821 * Minimum BW allocated to CoS Queue.
17822 * The HWRM will translate this value into byte counter and
17823 * time interval used for this COS inside the device.
17825 uint32_t queue_id5_min_bw;
17826 /* The bandwidth value. */
17827 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
17828 UINT32_C(0xfffffff)
17829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
17831 /* The granularity of the value (bits or bytes). */
17832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
17833 UINT32_C(0x10000000)
17834 /* Value is in bits. */
17835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
17836 (UINT32_C(0x0) << 28)
17837 /* Value is in bytes. */
17838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
17839 (UINT32_C(0x1) << 28)
17840 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
17841 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
17842 /* bw_value_unit is 3 b */
17843 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
17844 UINT32_C(0xe0000000)
17845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
17847 /* Value is in Mb or MB (base 10). */
17848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
17849 (UINT32_C(0x0) << 29)
17850 /* Value is in Kb or KB (base 10). */
17851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
17852 (UINT32_C(0x2) << 29)
17853 /* Value is in bits or bytes. */
17854 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
17855 (UINT32_C(0x4) << 29)
17856 /* Value is in Gb or GB (base 10). */
17857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
17858 (UINT32_C(0x6) << 29)
17859 /* Value is in 1/100th of a percentage of total bandwidth. */
17860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17861 (UINT32_C(0x1) << 29)
17863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
17864 (UINT32_C(0x7) << 29)
17865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
17866 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
17868 * Maximum BW allocated to CoS queue.
17869 * The HWRM will translate this value into byte counter and
17870 * time interval used for this COS inside the device.
17872 uint32_t queue_id5_max_bw;
17873 /* The bandwidth value. */
17874 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
17875 UINT32_C(0xfffffff)
17876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
17878 /* The granularity of the value (bits or bytes). */
17879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
17880 UINT32_C(0x10000000)
17881 /* Value is in bits. */
17882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
17883 (UINT32_C(0x0) << 28)
17884 /* Value is in bytes. */
17885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
17886 (UINT32_C(0x1) << 28)
17887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
17888 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
17889 /* bw_value_unit is 3 b */
17890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
17891 UINT32_C(0xe0000000)
17892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
17894 /* Value is in Mb or MB (base 10). */
17895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
17896 (UINT32_C(0x0) << 29)
17897 /* Value is in Kb or KB (base 10). */
17898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
17899 (UINT32_C(0x2) << 29)
17900 /* Value is in bits or bytes. */
17901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
17902 (UINT32_C(0x4) << 29)
17903 /* Value is in Gb or GB (base 10). */
17904 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
17905 (UINT32_C(0x6) << 29)
17906 /* Value is in 1/100th of a percentage of total bandwidth. */
17907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17908 (UINT32_C(0x1) << 29)
17910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
17911 (UINT32_C(0x7) << 29)
17912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
17913 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
17914 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17915 uint8_t queue_id5_tsa_assign;
17916 /* Strict Priority */
17917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
17919 /* Enhanced Transmission Selection */
17920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
17923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
17926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
17929 * Priority level for strict priority. Valid only when the
17930 * tsa_assign is 0 - Strict Priority (SP)
17931 * 0..7 - Valid values.
17932 * 8..255 - Reserved.
17934 uint8_t queue_id5_pri_lvl;
17936 * Weight used to allocate remaining BW for this COS after
17937 * servicing guaranteed bandwidths for all COS.
17939 uint8_t queue_id5_bw_weight;
17940 /* ID of CoS Queue 6. */
17943 * Minimum BW allocated to CoS Queue.
17944 * The HWRM will translate this value into byte counter and
17945 * time interval used for this COS inside the device.
17947 uint32_t queue_id6_min_bw;
17948 /* The bandwidth value. */
17949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
17950 UINT32_C(0xfffffff)
17951 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
17953 /* The granularity of the value (bits or bytes). */
17954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
17955 UINT32_C(0x10000000)
17956 /* Value is in bits. */
17957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
17958 (UINT32_C(0x0) << 28)
17959 /* Value is in bytes. */
17960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
17961 (UINT32_C(0x1) << 28)
17962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
17963 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
17964 /* bw_value_unit is 3 b */
17965 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
17966 UINT32_C(0xe0000000)
17967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
17969 /* Value is in Mb or MB (base 10). */
17970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
17971 (UINT32_C(0x0) << 29)
17972 /* Value is in Kb or KB (base 10). */
17973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
17974 (UINT32_C(0x2) << 29)
17975 /* Value is in bits or bytes. */
17976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
17977 (UINT32_C(0x4) << 29)
17978 /* Value is in Gb or GB (base 10). */
17979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
17980 (UINT32_C(0x6) << 29)
17981 /* Value is in 1/100th of a percentage of total bandwidth. */
17982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17983 (UINT32_C(0x1) << 29)
17985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
17986 (UINT32_C(0x7) << 29)
17987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
17988 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
17990 * Maximum BW allocated to CoS queue.
17991 * The HWRM will translate this value into byte counter and
17992 * time interval used for this COS inside the device.
17994 uint32_t queue_id6_max_bw;
17995 /* The bandwidth value. */
17996 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
17997 UINT32_C(0xfffffff)
17998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
18000 /* The granularity of the value (bits or bytes). */
18001 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
18002 UINT32_C(0x10000000)
18003 /* Value is in bits. */
18004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
18005 (UINT32_C(0x0) << 28)
18006 /* Value is in bytes. */
18007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
18008 (UINT32_C(0x1) << 28)
18009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
18010 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
18011 /* bw_value_unit is 3 b */
18012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
18013 UINT32_C(0xe0000000)
18014 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
18016 /* Value is in Mb or MB (base 10). */
18017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
18018 (UINT32_C(0x0) << 29)
18019 /* Value is in Kb or KB (base 10). */
18020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
18021 (UINT32_C(0x2) << 29)
18022 /* Value is in bits or bytes. */
18023 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
18024 (UINT32_C(0x4) << 29)
18025 /* Value is in Gb or GB (base 10). */
18026 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
18027 (UINT32_C(0x6) << 29)
18028 /* Value is in 1/100th of a percentage of total bandwidth. */
18029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18030 (UINT32_C(0x1) << 29)
18032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
18033 (UINT32_C(0x7) << 29)
18034 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
18035 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
18036 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18037 uint8_t queue_id6_tsa_assign;
18038 /* Strict Priority */
18039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
18041 /* Enhanced Transmission Selection */
18042 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
18045 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
18048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
18051 * Priority level for strict priority. Valid only when the
18052 * tsa_assign is 0 - Strict Priority (SP)
18053 * 0..7 - Valid values.
18054 * 8..255 - Reserved.
18056 uint8_t queue_id6_pri_lvl;
18058 * Weight used to allocate remaining BW for this COS after
18059 * servicing guaranteed bandwidths for all COS.
18061 uint8_t queue_id6_bw_weight;
18062 /* ID of CoS Queue 7. */
18065 * Minimum BW allocated to CoS Queue.
18066 * The HWRM will translate this value into byte counter and
18067 * time interval used for this COS inside the device.
18069 uint32_t queue_id7_min_bw;
18070 /* The bandwidth value. */
18071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
18072 UINT32_C(0xfffffff)
18073 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
18075 /* The granularity of the value (bits or bytes). */
18076 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
18077 UINT32_C(0x10000000)
18078 /* Value is in bits. */
18079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
18080 (UINT32_C(0x0) << 28)
18081 /* Value is in bytes. */
18082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
18083 (UINT32_C(0x1) << 28)
18084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
18085 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
18086 /* bw_value_unit is 3 b */
18087 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
18088 UINT32_C(0xe0000000)
18089 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
18091 /* Value is in Mb or MB (base 10). */
18092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
18093 (UINT32_C(0x0) << 29)
18094 /* Value is in Kb or KB (base 10). */
18095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
18096 (UINT32_C(0x2) << 29)
18097 /* Value is in bits or bytes. */
18098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
18099 (UINT32_C(0x4) << 29)
18100 /* Value is in Gb or GB (base 10). */
18101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
18102 (UINT32_C(0x6) << 29)
18103 /* Value is in 1/100th of a percentage of total bandwidth. */
18104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
18105 (UINT32_C(0x1) << 29)
18107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
18108 (UINT32_C(0x7) << 29)
18109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
18110 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
18112 * Maximum BW allocated to CoS queue.
18113 * The HWRM will translate this value into byte counter and
18114 * time interval used for this COS inside the device.
18116 uint32_t queue_id7_max_bw;
18117 /* The bandwidth value. */
18118 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
18119 UINT32_C(0xfffffff)
18120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
18122 /* The granularity of the value (bits or bytes). */
18123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
18124 UINT32_C(0x10000000)
18125 /* Value is in bits. */
18126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
18127 (UINT32_C(0x0) << 28)
18128 /* Value is in bytes. */
18129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
18130 (UINT32_C(0x1) << 28)
18131 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
18132 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
18133 /* bw_value_unit is 3 b */
18134 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
18135 UINT32_C(0xe0000000)
18136 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
18138 /* Value is in Mb or MB (base 10). */
18139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
18140 (UINT32_C(0x0) << 29)
18141 /* Value is in Kb or KB (base 10). */
18142 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
18143 (UINT32_C(0x2) << 29)
18144 /* Value is in bits or bytes. */
18145 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
18146 (UINT32_C(0x4) << 29)
18147 /* Value is in Gb or GB (base 10). */
18148 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
18149 (UINT32_C(0x6) << 29)
18150 /* Value is in 1/100th of a percentage of total bandwidth. */
18151 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
18152 (UINT32_C(0x1) << 29)
18154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
18155 (UINT32_C(0x7) << 29)
18156 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
18157 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
18158 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
18159 uint8_t queue_id7_tsa_assign;
18160 /* Strict Priority */
18161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
18163 /* Enhanced Transmission Selection */
18164 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
18167 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
18170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
18173 * Priority level for strict priority. Valid only when the
18174 * tsa_assign is 0 - Strict Priority (SP)
18175 * 0..7 - Valid values.
18176 * 8..255 - Reserved.
18178 uint8_t queue_id7_pri_lvl;
18180 * Weight used to allocate remaining BW for this COS after
18181 * servicing guaranteed bandwidths for all COS.
18183 uint8_t queue_id7_bw_weight;
18184 uint8_t unused_1[5];
18185 } __attribute__((packed));
18187 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
18188 struct hwrm_queue_cos2bw_cfg_output {
18189 /* The specific error status for the command. */
18190 uint16_t error_code;
18191 /* The HWRM command request type. */
18193 /* The sequence ID from the original command. */
18195 /* The length of the response data in number of bytes. */
18197 uint8_t unused_0[7];
18199 * This field is used in Output records to indicate that the output
18200 * is completely written to RAM. This field should be read as '1'
18201 * to indicate that the output has been completely written.
18202 * When writing a command completion or response to an internal processor,
18203 * the order of writes has to be such that this field is written last.
18206 } __attribute__((packed));
18208 /*******************
18209 * hwrm_vnic_alloc *
18210 *******************/
18213 /* hwrm_vnic_alloc_input (size:192b/24B) */
18214 struct hwrm_vnic_alloc_input {
18215 /* The HWRM command request type. */
18218 * The completion ring to send the completion event on. This should
18219 * be the NQ ID returned from the `nq_alloc` HWRM command.
18221 uint16_t cmpl_ring;
18223 * The sequence ID is used by the driver for tracking multiple
18224 * commands. This ID is treated as opaque data by the firmware and
18225 * the value is returned in the `hwrm_resp_hdr` upon completion.
18229 * The target ID of the command:
18230 * * 0x0-0xFFF8 - The function ID
18231 * * 0xFFF8-0xFFFE - Reserved for internal processors
18234 uint16_t target_id;
18236 * A physical address pointer pointing to a host buffer that the
18237 * command's response data will be written. This can be either a host
18238 * physical address (HPA) or a guest physical address (GPA) and must
18239 * point to a physically contiguous block of memory.
18241 uint64_t resp_addr;
18244 * When this bit is '1', this VNIC is requested to
18245 * be the default VNIC for this function.
18247 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
18248 uint8_t unused_0[4];
18249 } __attribute__((packed));
18251 /* hwrm_vnic_alloc_output (size:128b/16B) */
18252 struct hwrm_vnic_alloc_output {
18253 /* The specific error status for the command. */
18254 uint16_t error_code;
18255 /* The HWRM command request type. */
18257 /* The sequence ID from the original command. */
18259 /* The length of the response data in number of bytes. */
18261 /* Logical vnic ID */
18263 uint8_t unused_0[3];
18265 * This field is used in Output records to indicate that the output
18266 * is completely written to RAM. This field should be read as '1'
18267 * to indicate that the output has been completely written.
18268 * When writing a command completion or response to an internal processor,
18269 * the order of writes has to be such that this field is written last.
18272 } __attribute__((packed));
18274 /******************
18276 ******************/
18279 /* hwrm_vnic_free_input (size:192b/24B) */
18280 struct hwrm_vnic_free_input {
18281 /* The HWRM command request type. */
18284 * The completion ring to send the completion event on. This should
18285 * be the NQ ID returned from the `nq_alloc` HWRM command.
18287 uint16_t cmpl_ring;
18289 * The sequence ID is used by the driver for tracking multiple
18290 * commands. This ID is treated as opaque data by the firmware and
18291 * the value is returned in the `hwrm_resp_hdr` upon completion.
18295 * The target ID of the command:
18296 * * 0x0-0xFFF8 - The function ID
18297 * * 0xFFF8-0xFFFE - Reserved for internal processors
18300 uint16_t target_id;
18302 * A physical address pointer pointing to a host buffer that the
18303 * command's response data will be written. This can be either a host
18304 * physical address (HPA) or a guest physical address (GPA) and must
18305 * point to a physically contiguous block of memory.
18307 uint64_t resp_addr;
18308 /* Logical vnic ID */
18310 uint8_t unused_0[4];
18311 } __attribute__((packed));
18313 /* hwrm_vnic_free_output (size:128b/16B) */
18314 struct hwrm_vnic_free_output {
18315 /* The specific error status for the command. */
18316 uint16_t error_code;
18317 /* The HWRM command request type. */
18319 /* The sequence ID from the original command. */
18321 /* The length of the response data in number of bytes. */
18323 uint8_t unused_0[7];
18325 * This field is used in Output records to indicate that the output
18326 * is completely written to RAM. This field should be read as '1'
18327 * to indicate that the output has been completely written.
18328 * When writing a command completion or response to an internal processor,
18329 * the order of writes has to be such that this field is written last.
18332 } __attribute__((packed));
18339 /* hwrm_vnic_cfg_input (size:320b/40B) */
18340 struct hwrm_vnic_cfg_input {
18341 /* The HWRM command request type. */
18344 * The completion ring to send the completion event on. This should
18345 * be the NQ ID returned from the `nq_alloc` HWRM command.
18347 uint16_t cmpl_ring;
18349 * The sequence ID is used by the driver for tracking multiple
18350 * commands. This ID is treated as opaque data by the firmware and
18351 * the value is returned in the `hwrm_resp_hdr` upon completion.
18355 * The target ID of the command:
18356 * * 0x0-0xFFF8 - The function ID
18357 * * 0xFFF8-0xFFFE - Reserved for internal processors
18360 uint16_t target_id;
18362 * A physical address pointer pointing to a host buffer that the
18363 * command's response data will be written. This can be either a host
18364 * physical address (HPA) or a guest physical address (GPA) and must
18365 * point to a physically contiguous block of memory.
18367 uint64_t resp_addr;
18370 * When this bit is '1', the VNIC is requested to
18371 * be the default VNIC for the function.
18373 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
18376 * When this bit is '1', the VNIC is being configured to
18377 * strip VLAN in the RX path.
18378 * If set to '0', then VLAN stripping is disabled on
18381 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
18384 * When this bit is '1', the VNIC is being configured to
18385 * buffer receive packets in the hardware until the host
18386 * posts new receive buffers.
18387 * If set to '0', then bd_stall is being configured to be
18388 * disabled on this VNIC.
18390 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
18393 * When this bit is '1', the VNIC is being configured to
18394 * receive both RoCE and non-RoCE traffic.
18395 * If set to '0', then this VNIC is not configured to be
18396 * operating in dual VNIC mode.
18398 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
18401 * When this flag is set to '1', the VNIC is requested to
18402 * be configured to receive only RoCE traffic.
18403 * If this flag is set to '0', then this flag shall be
18404 * ignored by the HWRM.
18405 * If roce_dual_vnic_mode flag is set to '1'
18406 * or roce_mirroring_capable_vnic_mode flag to 1,
18407 * then the HWRM client shall not set this flag to '1'.
18409 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
18412 * When a VNIC uses one destination ring group for certain
18413 * application (e.g. Receive Flow Steering) where
18414 * exact match is used to direct packets to a VNIC with one
18415 * destination ring group only, there is no need to configure
18416 * RSS indirection table for that VNIC as only one destination
18417 * ring group is used.
18419 * This flag is used to enable a mode where
18420 * RSS is enabled in the VNIC using a RSS context
18421 * for computing RSS hash but the RSS indirection table is
18422 * not configured using hwrm_vnic_rss_cfg.
18424 * If this mode is enabled, then the driver should not program
18425 * RSS indirection table for the RSS context that is used for
18426 * computing RSS hash only.
18428 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
18431 * When this bit is '1', the VNIC is being configured to
18432 * receive both RoCE and non-RoCE traffic, but forward only the
18433 * RoCE traffic further. Also, RoCE traffic can be mirrored to
18436 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
18440 * This bit must be '1' for the dflt_ring_grp field to be
18443 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
18446 * This bit must be '1' for the rss_rule field to be
18449 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
18452 * This bit must be '1' for the cos_rule field to be
18455 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
18458 * This bit must be '1' for the lb_rule field to be
18461 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
18464 * This bit must be '1' for the mru field to be
18467 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
18470 * This bit must be '1' for the default_rx_ring_id field to be
18473 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
18476 * This bit must be '1' for the default_cmpl_ring_id field to be
18479 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
18481 /* Logical vnic ID */
18484 * Default Completion ring for the VNIC. This ring will
18485 * be chosen if packet does not match any RSS rules and if
18486 * there is no COS rule.
18488 uint16_t dflt_ring_grp;
18490 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
18491 * there is no RSS rule.
18495 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
18496 * there is no COS rule.
18500 * RSS ID for load balancing rule/table structure.
18501 * 0xFF... (All Fs) if there is no LB rule.
18505 * The maximum receive unit of the vnic.
18506 * Each vnic is associated with a function.
18507 * The vnic mru value overwrites the mru setting of the
18508 * associated function.
18509 * The HWRM shall make sure that vnic mru does not exceed
18510 * the mru of the port the function is associated with.
18514 * Default Rx ring for the VNIC. This ring will
18515 * be chosen if packet does not match any RSS rules.
18516 * The aggregation ring associated with the Rx ring is
18517 * implied based on the Rx ring specified when the
18518 * aggregation ring was allocated.
18520 uint16_t default_rx_ring_id;
18522 * Default completion ring for the VNIC. This ring will
18523 * be chosen if packet does not match any RSS rules.
18525 uint16_t default_cmpl_ring_id;
18526 } __attribute__((packed));
18528 /* hwrm_vnic_cfg_output (size:128b/16B) */
18529 struct hwrm_vnic_cfg_output {
18530 /* The specific error status for the command. */
18531 uint16_t error_code;
18532 /* The HWRM command request type. */
18534 /* The sequence ID from the original command. */
18536 /* The length of the response data in number of bytes. */
18538 uint8_t unused_0[7];
18540 * This field is used in Output records to indicate that the output
18541 * is completely written to RAM. This field should be read as '1'
18542 * to indicate that the output has been completely written.
18543 * When writing a command completion or response to an internal processor,
18544 * the order of writes has to be such that this field is written last.
18547 } __attribute__((packed));
18549 /******************
18551 ******************/
18554 /* hwrm_vnic_qcfg_input (size:256b/32B) */
18555 struct hwrm_vnic_qcfg_input {
18556 /* The HWRM command request type. */
18559 * The completion ring to send the completion event on. This should
18560 * be the NQ ID returned from the `nq_alloc` HWRM command.
18562 uint16_t cmpl_ring;
18564 * The sequence ID is used by the driver for tracking multiple
18565 * commands. This ID is treated as opaque data by the firmware and
18566 * the value is returned in the `hwrm_resp_hdr` upon completion.
18570 * The target ID of the command:
18571 * * 0x0-0xFFF8 - The function ID
18572 * * 0xFFF8-0xFFFE - Reserved for internal processors
18575 uint16_t target_id;
18577 * A physical address pointer pointing to a host buffer that the
18578 * command's response data will be written. This can be either a host
18579 * physical address (HPA) or a guest physical address (GPA) and must
18580 * point to a physically contiguous block of memory.
18582 uint64_t resp_addr;
18585 * This bit must be '1' for the vf_id_valid field to be
18588 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
18589 /* Logical vnic ID */
18591 /* ID of Virtual Function whose VNIC resource is being queried. */
18593 uint8_t unused_0[6];
18594 } __attribute__((packed));
18596 /* hwrm_vnic_qcfg_output (size:256b/32B) */
18597 struct hwrm_vnic_qcfg_output {
18598 /* The specific error status for the command. */
18599 uint16_t error_code;
18600 /* The HWRM command request type. */
18602 /* The sequence ID from the original command. */
18604 /* The length of the response data in number of bytes. */
18606 /* Default Completion ring for the VNIC. */
18607 uint16_t dflt_ring_grp;
18609 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
18610 * there is no RSS rule.
18614 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
18615 * there is no COS rule.
18619 * RSS ID for load balancing rule/table structure.
18620 * 0xFF... (All Fs) if there is no LB rule.
18623 /* The maximum receive unit of the vnic. */
18625 uint8_t unused_0[2];
18628 * When this bit is '1', the VNIC is the default VNIC for
18631 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
18634 * When this bit is '1', the VNIC is configured to
18635 * strip VLAN in the RX path.
18636 * If set to '0', then VLAN stripping is disabled on
18639 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
18642 * When this bit is '1', the VNIC is configured to
18643 * buffer receive packets in the hardware until the host
18644 * posts new receive buffers.
18645 * If set to '0', then bd_stall is disabled on
18648 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
18651 * When this bit is '1', the VNIC is configured to
18652 * receive both RoCE and non-RoCE traffic.
18653 * If set to '0', then this VNIC is not configured to
18654 * operate in dual VNIC mode.
18656 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
18659 * When this flag is set to '1', the VNIC is configured to
18660 * receive only RoCE traffic.
18661 * When this flag is set to '0', the VNIC is not configured
18662 * to receive only RoCE traffic.
18663 * If roce_dual_vnic_mode flag and this flag both are set
18664 * to '1', then it is an invalid configuration of the
18665 * VNIC. The HWRM should not allow that type of
18666 * mis-configuration by HWRM clients.
18668 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
18671 * When a VNIC uses one destination ring group for certain
18672 * application (e.g. Receive Flow Steering) where
18673 * exact match is used to direct packets to a VNIC with one
18674 * destination ring group only, there is no need to configure
18675 * RSS indirection table for that VNIC as only one destination
18676 * ring group is used.
18678 * When this bit is set to '1', then the VNIC is enabled in a
18679 * mode where RSS is enabled in the VNIC using a RSS context
18680 * for computing RSS hash but the RSS indirection table is
18683 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
18686 * When this bit is '1', the VNIC is configured to
18687 * receive both RoCE and non-RoCE traffic, but forward only
18688 * RoCE traffic further. Also RoCE traffic can be mirrored to
18691 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
18693 uint8_t unused_1[7];
18695 * This field is used in Output records to indicate that the output
18696 * is completely written to RAM. This field should be read as '1'
18697 * to indicate that the output has been completely written.
18698 * When writing a command completion or response to an internal processor,
18699 * the order of writes has to be such that this field is written last.
18702 } __attribute__((packed));
18704 /*******************
18705 * hwrm_vnic_qcaps *
18706 *******************/
18709 /* hwrm_vnic_qcaps_input (size:192b/24B) */
18710 struct hwrm_vnic_qcaps_input {
18711 /* The HWRM command request type. */
18714 * The completion ring to send the completion event on. This should
18715 * be the NQ ID returned from the `nq_alloc` HWRM command.
18717 uint16_t cmpl_ring;
18719 * The sequence ID is used by the driver for tracking multiple
18720 * commands. This ID is treated as opaque data by the firmware and
18721 * the value is returned in the `hwrm_resp_hdr` upon completion.
18725 * The target ID of the command:
18726 * * 0x0-0xFFF8 - The function ID
18727 * * 0xFFF8-0xFFFE - Reserved for internal processors
18730 uint16_t target_id;
18732 * A physical address pointer pointing to a host buffer that the
18733 * command's response data will be written. This can be either a host
18734 * physical address (HPA) or a guest physical address (GPA) and must
18735 * point to a physically contiguous block of memory.
18737 uint64_t resp_addr;
18739 uint8_t unused_0[4];
18740 } __attribute__((packed));
18742 /* hwrm_vnic_qcaps_output (size:192b/24B) */
18743 struct hwrm_vnic_qcaps_output {
18744 /* The specific error status for the command. */
18745 uint16_t error_code;
18746 /* The HWRM command request type. */
18748 /* The sequence ID from the original command. */
18750 /* The length of the response data in number of bytes. */
18752 /* The maximum receive unit that is settable on a vnic. */
18754 uint8_t unused_0[2];
18757 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
18760 * When this bit is '1', the capability of stripping VLAN in
18761 * the RX path is supported on VNIC(s).
18762 * If set to '0', then VLAN stripping capability is
18763 * not supported on VNIC(s).
18765 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
18768 * When this bit is '1', the capability to buffer receive
18769 * packets in the hardware until the host posts new receive buffers
18770 * is supported on VNIC(s).
18771 * If set to '0', then bd_stall capability is not supported
18774 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
18777 * When this bit is '1', the capability to
18778 * receive both RoCE and non-RoCE traffic on VNIC(s) is
18780 * If set to '0', then the capability to receive
18781 * both RoCE and non-RoCE traffic on VNIC(s) is
18784 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
18787 * When this bit is set to '1', the capability to configure
18788 * a VNIC to receive only RoCE traffic is supported.
18789 * When this flag is set to '0', the VNIC capability to
18790 * configure to receive only RoCE traffic is not supported.
18792 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
18795 * When this bit is set to '1', then the capability to enable
18796 * a VNIC in a mode where RSS context without configuring
18797 * RSS indirection table is supported (for RSS hash computation).
18798 * When this bit is set to '0', then a VNIC can not be configured
18799 * with a mode to enable RSS context without configuring RSS
18800 * indirection table.
18802 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
18805 * When this bit is '1', the capability to
18806 * mirror the the RoCE traffic is supported.
18807 * If set to '0', then the capability to mirror the
18808 * RoCE traffic is not supported.
18810 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
18813 * When this bit is '1', the outermost RSS hashing capability
18814 * is supported. If set to '0', then the outermost RSS hashing
18815 * capability is not supported.
18817 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
18819 uint8_t unused_1[7];
18821 * This field is used in Output records to indicate that the output
18822 * is completely written to RAM. This field should be read as '1'
18823 * to indicate that the output has been completely written.
18824 * When writing a command completion or response to an internal processor,
18825 * the order of writes has to be such that this field is written last.
18828 } __attribute__((packed));
18830 /*********************
18831 * hwrm_vnic_tpa_cfg *
18832 *********************/
18835 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
18836 struct hwrm_vnic_tpa_cfg_input {
18837 /* The HWRM command request type. */
18840 * The completion ring to send the completion event on. This should
18841 * be the NQ ID returned from the `nq_alloc` HWRM command.
18843 uint16_t cmpl_ring;
18845 * The sequence ID is used by the driver for tracking multiple
18846 * commands. This ID is treated as opaque data by the firmware and
18847 * the value is returned in the `hwrm_resp_hdr` upon completion.
18851 * The target ID of the command:
18852 * * 0x0-0xFFF8 - The function ID
18853 * * 0xFFF8-0xFFFE - Reserved for internal processors
18856 uint16_t target_id;
18858 * A physical address pointer pointing to a host buffer that the
18859 * command's response data will be written. This can be either a host
18860 * physical address (HPA) or a guest physical address (GPA) and must
18861 * point to a physically contiguous block of memory.
18863 uint64_t resp_addr;
18866 * When this bit is '1', the VNIC shall be configured to
18867 * perform transparent packet aggregation (TPA) of
18868 * non-tunneled TCP packets.
18870 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
18873 * When this bit is '1', the VNIC shall be configured to
18874 * perform transparent packet aggregation (TPA) of
18875 * tunneled TCP packets.
18877 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
18880 * When this bit is '1', the VNIC shall be configured to
18881 * perform transparent packet aggregation (TPA) according
18882 * to Windows Receive Segment Coalescing (RSC) rules.
18884 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
18887 * When this bit is '1', the VNIC shall be configured to
18888 * perform transparent packet aggregation (TPA) according
18889 * to Linux Generic Receive Offload (GRO) rules.
18891 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
18894 * When this bit is '1', the VNIC shall be configured to
18895 * perform transparent packet aggregation (TPA) for TCP
18896 * packets with IP ECN set to non-zero.
18898 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
18901 * When this bit is '1', the VNIC shall be configured to
18902 * perform transparent packet aggregation (TPA) for
18903 * GRE tunneled TCP packets only if all packets have the
18904 * same GRE sequence.
18906 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
18909 * When this bit is '1' and the GRO mode is enabled,
18910 * the VNIC shall be configured to
18911 * perform transparent packet aggregation (TPA) for
18912 * TCP/IPv4 packets with consecutively increasing IPIDs.
18913 * In other words, the last packet that is being
18914 * aggregated to an already existing aggregation context
18915 * shall have IPID 1 more than the IPID of the last packet
18916 * that was aggregated in that aggregation context.
18918 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
18921 * When this bit is '1' and the GRO mode is enabled,
18922 * the VNIC shall be configured to
18923 * perform transparent packet aggregation (TPA) for
18924 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
18927 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
18931 * This bit must be '1' for the max_agg_segs field to be
18934 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
18936 * This bit must be '1' for the max_aggs field to be
18939 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
18941 * This bit must be '1' for the max_agg_timer field to be
18944 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
18946 * This bit must be '1' for the min_agg_len field to be
18949 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
18950 /* Logical vnic ID */
18953 * This is the maximum number of TCP segments that can
18954 * be aggregated (unit is Log2). Max value is 31.
18956 uint16_t max_agg_segs;
18958 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
18960 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
18962 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
18964 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
18965 /* Any segment size larger than this is not valid */
18966 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
18967 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
18968 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
18970 * This is the maximum number of aggregations this VNIC is
18971 * allowed (unit is Log2). Max value is 7
18974 /* 1 aggregation */
18975 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
18976 /* 2 aggregations */
18977 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
18978 /* 4 aggregations */
18979 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
18980 /* 8 aggregations */
18981 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
18982 /* 16 aggregations */
18983 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
18984 /* Any aggregation size larger than this is not valid */
18985 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
18986 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
18987 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
18988 uint8_t unused_0[2];
18990 * This is the maximum amount of time allowed for
18991 * an aggregation context to complete after it was initiated.
18993 uint32_t max_agg_timer;
18995 * This is the minimum amount of payload length required to
18996 * start an aggregation context.
18998 uint32_t min_agg_len;
18999 } __attribute__((packed));
19001 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
19002 struct hwrm_vnic_tpa_cfg_output {
19003 /* The specific error status for the command. */
19004 uint16_t error_code;
19005 /* The HWRM command request type. */
19007 /* The sequence ID from the original command. */
19009 /* The length of the response data in number of bytes. */
19011 uint8_t unused_0[7];
19013 * This field is used in Output records to indicate that the output
19014 * is completely written to RAM. This field should be read as '1'
19015 * to indicate that the output has been completely written.
19016 * When writing a command completion or response to an internal processor,
19017 * the order of writes has to be such that this field is written last.
19020 } __attribute__((packed));
19022 /*********************
19023 * hwrm_vnic_rss_cfg *
19024 *********************/
19027 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
19028 struct hwrm_vnic_rss_cfg_input {
19029 /* The HWRM command request type. */
19032 * The completion ring to send the completion event on. This should
19033 * be the NQ ID returned from the `nq_alloc` HWRM command.
19035 uint16_t cmpl_ring;
19037 * The sequence ID is used by the driver for tracking multiple
19038 * commands. This ID is treated as opaque data by the firmware and
19039 * the value is returned in the `hwrm_resp_hdr` upon completion.
19043 * The target ID of the command:
19044 * * 0x0-0xFFF8 - The function ID
19045 * * 0xFFF8-0xFFFE - Reserved for internal processors
19048 uint16_t target_id;
19050 * A physical address pointer pointing to a host buffer that the
19051 * command's response data will be written. This can be either a host
19052 * physical address (HPA) or a guest physical address (GPA) and must
19053 * point to a physically contiguous block of memory.
19055 uint64_t resp_addr;
19056 uint32_t hash_type;
19058 * When this bit is '1', the RSS hash shall be computed
19059 * over source and destination IPv4 addresses of IPv4
19062 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19064 * When this bit is '1', the RSS hash shall be computed
19065 * over source/destination IPv4 addresses and
19066 * source/destination ports of TCP/IPv4 packets.
19068 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19070 * When this bit is '1', the RSS hash shall be computed
19071 * over source/destination IPv4 addresses and
19072 * source/destination ports of UDP/IPv4 packets.
19074 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19076 * When this bit is '1', the RSS hash shall be computed
19077 * over source and destination IPv4 addresses of IPv6
19080 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19082 * When this bit is '1', the RSS hash shall be computed
19083 * over source/destination IPv6 addresses and
19084 * source/destination ports of TCP/IPv6 packets.
19086 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19088 * When this bit is '1', the RSS hash shall be computed
19089 * over source/destination IPv6 addresses and
19090 * source/destination ports of UDP/IPv6 packets.
19092 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19093 /* VNIC ID of VNIC associated with RSS table being configured. */
19096 * Specifies which VNIC ring table pair to configure.
19097 * Valid values range from 0 to 7.
19099 uint8_t ring_table_pair_index;
19100 /* Flags to specify different RSS hash modes. */
19101 uint8_t hash_mode_flags;
19103 * When this bit is '1', it indicates using current RSS
19104 * hash mode setting configured in the device.
19106 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
19109 * When this bit is '1', it indicates requesting support of
19110 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19111 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19112 * packets, the RSS hash is computed over the normal
19113 * src/dest l3 and src/dest l4 headers.
19115 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19118 * When this bit is '1', it indicates requesting support of
19119 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19120 * tunnel packets. For none-tunnel packets, the RSS hash is
19121 * computed over the normal src/dest l3 headers.
19123 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19126 * When this bit is '1', it indicates requesting support of
19127 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19128 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19129 * packets, the RSS hash is computed over the normal
19130 * src/dest l3 and src/dest l4 headers.
19132 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19135 * When this bit is '1', it indicates requesting support of
19136 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19137 * tunnel packets. For none-tunnel packets, the RSS hash is
19138 * computed over the normal src/dest l3 headers.
19140 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19142 /* This is the address for rss ring group table */
19143 uint64_t ring_grp_tbl_addr;
19144 /* This is the address for rss hash key table */
19145 uint64_t hash_key_tbl_addr;
19146 /* Index to the rss indirection table. */
19147 uint16_t rss_ctx_idx;
19148 uint8_t unused_1[6];
19149 } __attribute__((packed));
19151 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
19152 struct hwrm_vnic_rss_cfg_output {
19153 /* The specific error status for the command. */
19154 uint16_t error_code;
19155 /* The HWRM command request type. */
19157 /* The sequence ID from the original command. */
19159 /* The length of the response data in number of bytes. */
19161 uint8_t unused_0[7];
19163 * This field is used in Output records to indicate that the output
19164 * is completely written to RAM. This field should be read as '1'
19165 * to indicate that the output has been completely written.
19166 * When writing a command completion or response to an internal processor,
19167 * the order of writes has to be such that this field is written last.
19170 } __attribute__((packed));
19172 /**********************
19173 * hwrm_vnic_rss_qcfg *
19174 **********************/
19177 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
19178 struct hwrm_vnic_rss_qcfg_input {
19179 /* The HWRM command request type. */
19182 * The completion ring to send the completion event on. This should
19183 * be the NQ ID returned from the `nq_alloc` HWRM command.
19185 uint16_t cmpl_ring;
19187 * The sequence ID is used by the driver for tracking multiple
19188 * commands. This ID is treated as opaque data by the firmware and
19189 * the value is returned in the `hwrm_resp_hdr` upon completion.
19193 * The target ID of the command:
19194 * * 0x0-0xFFF8 - The function ID
19195 * * 0xFFF8-0xFFFE - Reserved for internal processors
19198 uint16_t target_id;
19200 * A physical address pointer pointing to a host buffer that the
19201 * command's response data will be written. This can be either a host
19202 * physical address (HPA) or a guest physical address (GPA) and must
19203 * point to a physically contiguous block of memory.
19205 uint64_t resp_addr;
19206 /* Index to the rss indirection table. */
19207 uint16_t rss_ctx_idx;
19208 uint8_t unused_0[6];
19209 } __attribute__((packed));
19211 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
19212 struct hwrm_vnic_rss_qcfg_output {
19213 /* The specific error status for the command. */
19214 uint16_t error_code;
19215 /* The HWRM command request type. */
19217 /* The sequence ID from the original command. */
19219 /* The length of the response data in number of bytes. */
19221 uint32_t hash_type;
19223 * When this bit is '1', the RSS hash shall be computed
19224 * over source and destination IPv4 addresses of IPv4
19227 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
19229 * When this bit is '1', the RSS hash shall be computed
19230 * over source/destination IPv4 addresses and
19231 * source/destination ports of TCP/IPv4 packets.
19233 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
19235 * When this bit is '1', the RSS hash shall be computed
19236 * over source/destination IPv4 addresses and
19237 * source/destination ports of UDP/IPv4 packets.
19239 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
19241 * When this bit is '1', the RSS hash shall be computed
19242 * over source and destination IPv4 addresses of IPv6
19245 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
19247 * When this bit is '1', the RSS hash shall be computed
19248 * over source/destination IPv6 addresses and
19249 * source/destination ports of TCP/IPv6 packets.
19251 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
19253 * When this bit is '1', the RSS hash shall be computed
19254 * over source/destination IPv6 addresses and
19255 * source/destination ports of UDP/IPv6 packets.
19257 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
19258 uint8_t unused_0[4];
19259 /* This is the value of rss hash key */
19260 uint32_t hash_key[10];
19261 /* Flags to specify different RSS hash modes. */
19262 uint8_t hash_mode_flags;
19264 * When this bit is '1', it indicates using current RSS
19265 * hash mode setting configured in the device.
19267 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
19270 * When this bit is '1', it indicates requesting support of
19271 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
19272 * l4.src, l4.dest} for tunnel packets. For none-tunnel
19273 * packets, the RSS hash is computed over the normal
19274 * src/dest l3 and src/dest l4 headers.
19276 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
19279 * When this bit is '1', it indicates requesting support of
19280 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
19281 * tunnel packets. For none-tunnel packets, the RSS hash is
19282 * computed over the normal src/dest l3 headers.
19284 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
19287 * When this bit is '1', it indicates requesting support of
19288 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
19289 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
19290 * packets, the RSS hash is computed over the normal
19291 * src/dest l3 and src/dest l4 headers.
19293 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
19296 * When this bit is '1', it indicates requesting support of
19297 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
19298 * tunnel packets. For none-tunnel packets, the RSS hash is
19299 * computed over the normal src/dest l3 headers.
19301 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
19303 uint8_t unused_1[6];
19305 * This field is used in Output records to indicate that the output
19306 * is completely written to RAM. This field should be read as '1'
19307 * to indicate that the output has been completely written.
19308 * When writing a command completion or response to an internal processor,
19309 * the order of writes has to be such that this field is written last.
19312 } __attribute__((packed));
19314 /**************************
19315 * hwrm_vnic_plcmodes_cfg *
19316 **************************/
19319 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
19320 struct hwrm_vnic_plcmodes_cfg_input {
19321 /* The HWRM command request type. */
19324 * The completion ring to send the completion event on. This should
19325 * be the NQ ID returned from the `nq_alloc` HWRM command.
19327 uint16_t cmpl_ring;
19329 * The sequence ID is used by the driver for tracking multiple
19330 * commands. This ID is treated as opaque data by the firmware and
19331 * the value is returned in the `hwrm_resp_hdr` upon completion.
19335 * The target ID of the command:
19336 * * 0x0-0xFFF8 - The function ID
19337 * * 0xFFF8-0xFFFE - Reserved for internal processors
19340 uint16_t target_id;
19342 * A physical address pointer pointing to a host buffer that the
19343 * command's response data will be written. This can be either a host
19344 * physical address (HPA) or a guest physical address (GPA) and must
19345 * point to a physically contiguous block of memory.
19347 uint64_t resp_addr;
19350 * When this bit is '1', the VNIC shall be configured to
19351 * use regular placement algorithm.
19352 * By default, the regular placement algorithm shall be
19353 * enabled on the VNIC.
19355 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
19358 * When this bit is '1', the VNIC shall be configured
19359 * use the jumbo placement algorithm.
19361 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
19364 * When this bit is '1', the VNIC shall be configured
19365 * to enable Header-Data split for IPv4 packets according
19366 * to the following rules:
19367 * # If the packet is identified as TCP/IPv4, then the
19368 * packet is split at the beginning of the TCP payload.
19369 * # If the packet is identified as UDP/IPv4, then the
19370 * packet is split at the beginning of UDP payload.
19371 * # If the packet is identified as non-TCP and non-UDP
19372 * IPv4 packet, then the packet is split at the beginning
19373 * of the upper layer protocol header carried in the IPv4
19376 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
19379 * When this bit is '1', the VNIC shall be configured
19380 * to enable Header-Data split for IPv6 packets according
19381 * to the following rules:
19382 * # If the packet is identified as TCP/IPv6, then the
19383 * packet is split at the beginning of the TCP payload.
19384 * # If the packet is identified as UDP/IPv6, then the
19385 * packet is split at the beginning of UDP payload.
19386 * # If the packet is identified as non-TCP and non-UDP
19387 * IPv6 packet, then the packet is split at the beginning
19388 * of the upper layer protocol header carried in the IPv6
19391 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
19394 * When this bit is '1', the VNIC shall be configured
19395 * to enable Header-Data split for FCoE packets at the
19396 * beginning of FC payload.
19398 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
19401 * When this bit is '1', the VNIC shall be configured
19402 * to enable Header-Data split for RoCE packets at the
19403 * beginning of RoCE payload (after BTH/GRH headers).
19405 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
19409 * This bit must be '1' for the jumbo_thresh_valid field to be
19412 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
19415 * This bit must be '1' for the hds_offset_valid field to be
19418 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
19421 * This bit must be '1' for the hds_threshold_valid field to be
19424 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
19426 /* Logical vnic ID */
19429 * When jumbo placement algorithm is enabled, this value
19430 * is used to determine the threshold for jumbo placement.
19431 * Packets with length larger than this value will be
19432 * placed according to the jumbo placement algorithm.
19434 uint16_t jumbo_thresh;
19436 * This value is used to determine the offset into
19437 * packet buffer where the split data (payload) will be
19438 * placed according to one of of HDS placement algorithm.
19440 * The lengths of packet buffers provided for split data
19441 * shall be larger than this value.
19443 uint16_t hds_offset;
19445 * When one of the HDS placement algorithm is enabled, this
19446 * value is used to determine the threshold for HDS
19448 * Packets with length larger than this value will be
19449 * placed according to the HDS placement algorithm.
19450 * This value shall be in multiple of 4 bytes.
19452 uint16_t hds_threshold;
19453 uint8_t unused_0[6];
19454 } __attribute__((packed));
19456 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
19457 struct hwrm_vnic_plcmodes_cfg_output {
19458 /* The specific error status for the command. */
19459 uint16_t error_code;
19460 /* The HWRM command request type. */
19462 /* The sequence ID from the original command. */
19464 /* The length of the response data in number of bytes. */
19466 uint8_t unused_0[7];
19468 * This field is used in Output records to indicate that the output
19469 * is completely written to RAM. This field should be read as '1'
19470 * to indicate that the output has been completely written.
19471 * When writing a command completion or response to an internal processor,
19472 * the order of writes has to be such that this field is written last.
19475 } __attribute__((packed));
19477 /***************************
19478 * hwrm_vnic_plcmodes_qcfg *
19479 ***************************/
19482 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
19483 struct hwrm_vnic_plcmodes_qcfg_input {
19484 /* The HWRM command request type. */
19487 * The completion ring to send the completion event on. This should
19488 * be the NQ ID returned from the `nq_alloc` HWRM command.
19490 uint16_t cmpl_ring;
19492 * The sequence ID is used by the driver for tracking multiple
19493 * commands. This ID is treated as opaque data by the firmware and
19494 * the value is returned in the `hwrm_resp_hdr` upon completion.
19498 * The target ID of the command:
19499 * * 0x0-0xFFF8 - The function ID
19500 * * 0xFFF8-0xFFFE - Reserved for internal processors
19503 uint16_t target_id;
19505 * A physical address pointer pointing to a host buffer that the
19506 * command's response data will be written. This can be either a host
19507 * physical address (HPA) or a guest physical address (GPA) and must
19508 * point to a physically contiguous block of memory.
19510 uint64_t resp_addr;
19511 /* Logical vnic ID */
19513 uint8_t unused_0[4];
19514 } __attribute__((packed));
19516 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
19517 struct hwrm_vnic_plcmodes_qcfg_output {
19518 /* The specific error status for the command. */
19519 uint16_t error_code;
19520 /* The HWRM command request type. */
19522 /* The sequence ID from the original command. */
19524 /* The length of the response data in number of bytes. */
19528 * When this bit is '1', the VNIC is configured to
19529 * use regular placement algorithm.
19531 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
19534 * When this bit is '1', the VNIC is configured to
19535 * use the jumbo placement algorithm.
19537 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
19540 * When this bit is '1', the VNIC is configured
19541 * to enable Header-Data split for IPv4 packets.
19543 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
19546 * When this bit is '1', the VNIC is configured
19547 * to enable Header-Data split for IPv6 packets.
19549 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
19552 * When this bit is '1', the VNIC is configured
19553 * to enable Header-Data split for FCoE packets.
19555 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
19558 * When this bit is '1', the VNIC is configured
19559 * to enable Header-Data split for RoCE packets.
19561 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
19564 * When this bit is '1', the VNIC is configured
19565 * to be the default VNIC of the requesting function.
19567 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
19570 * When jumbo placement algorithm is enabled, this value
19571 * is used to determine the threshold for jumbo placement.
19572 * Packets with length larger than this value will be
19573 * placed according to the jumbo placement algorithm.
19575 uint16_t jumbo_thresh;
19577 * This value is used to determine the offset into
19578 * packet buffer where the split data (payload) will be
19579 * placed according to one of of HDS placement algorithm.
19581 * The lengths of packet buffers provided for split data
19582 * shall be larger than this value.
19584 uint16_t hds_offset;
19586 * When one of the HDS placement algorithm is enabled, this
19587 * value is used to determine the threshold for HDS
19589 * Packets with length larger than this value will be
19590 * placed according to the HDS placement algorithm.
19591 * This value shall be in multiple of 4 bytes.
19593 uint16_t hds_threshold;
19594 uint8_t unused_0[5];
19596 * This field is used in Output records to indicate that the output
19597 * is completely written to RAM. This field should be read as '1'
19598 * to indicate that the output has been completely written.
19599 * When writing a command completion or response to an internal processor,
19600 * the order of writes has to be such that this field is written last.
19603 } __attribute__((packed));
19605 /**********************************
19606 * hwrm_vnic_rss_cos_lb_ctx_alloc *
19607 **********************************/
19610 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
19611 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
19612 /* The HWRM command request type. */
19615 * The completion ring to send the completion event on. This should
19616 * be the NQ ID returned from the `nq_alloc` HWRM command.
19618 uint16_t cmpl_ring;
19620 * The sequence ID is used by the driver for tracking multiple
19621 * commands. This ID is treated as opaque data by the firmware and
19622 * the value is returned in the `hwrm_resp_hdr` upon completion.
19626 * The target ID of the command:
19627 * * 0x0-0xFFF8 - The function ID
19628 * * 0xFFF8-0xFFFE - Reserved for internal processors
19631 uint16_t target_id;
19633 * A physical address pointer pointing to a host buffer that the
19634 * command's response data will be written. This can be either a host
19635 * physical address (HPA) or a guest physical address (GPA) and must
19636 * point to a physically contiguous block of memory.
19638 uint64_t resp_addr;
19639 } __attribute__((packed));
19641 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
19642 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
19643 /* The specific error status for the command. */
19644 uint16_t error_code;
19645 /* The HWRM command request type. */
19647 /* The sequence ID from the original command. */
19649 /* The length of the response data in number of bytes. */
19651 /* rss_cos_lb_ctx_id is 16 b */
19652 uint16_t rss_cos_lb_ctx_id;
19653 uint8_t unused_0[5];
19655 * This field is used in Output records to indicate that the output
19656 * is completely written to RAM. This field should be read as '1'
19657 * to indicate that the output has been completely written.
19658 * When writing a command completion or response to an internal processor,
19659 * the order of writes has to be such that this field is written last.
19662 } __attribute__((packed));
19664 /*********************************
19665 * hwrm_vnic_rss_cos_lb_ctx_free *
19666 *********************************/
19669 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
19670 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
19671 /* The HWRM command request type. */
19674 * The completion ring to send the completion event on. This should
19675 * be the NQ ID returned from the `nq_alloc` HWRM command.
19677 uint16_t cmpl_ring;
19679 * The sequence ID is used by the driver for tracking multiple
19680 * commands. This ID is treated as opaque data by the firmware and
19681 * the value is returned in the `hwrm_resp_hdr` upon completion.
19685 * The target ID of the command:
19686 * * 0x0-0xFFF8 - The function ID
19687 * * 0xFFF8-0xFFFE - Reserved for internal processors
19690 uint16_t target_id;
19692 * A physical address pointer pointing to a host buffer that the
19693 * command's response data will be written. This can be either a host
19694 * physical address (HPA) or a guest physical address (GPA) and must
19695 * point to a physically contiguous block of memory.
19697 uint64_t resp_addr;
19698 /* rss_cos_lb_ctx_id is 16 b */
19699 uint16_t rss_cos_lb_ctx_id;
19700 uint8_t unused_0[6];
19701 } __attribute__((packed));
19703 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
19704 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
19705 /* The specific error status for the command. */
19706 uint16_t error_code;
19707 /* The HWRM command request type. */
19709 /* The sequence ID from the original command. */
19711 /* The length of the response data in number of bytes. */
19713 uint8_t unused_0[7];
19715 * This field is used in Output records to indicate that the output
19716 * is completely written to RAM. This field should be read as '1'
19717 * to indicate that the output has been completely written.
19718 * When writing a command completion or response to an internal processor,
19719 * the order of writes has to be such that this field is written last.
19722 } __attribute__((packed));
19724 /*******************
19725 * hwrm_ring_alloc *
19726 *******************/
19729 /* hwrm_ring_alloc_input (size:704b/88B) */
19730 struct hwrm_ring_alloc_input {
19731 /* The HWRM command request type. */
19734 * The completion ring to send the completion event on. This should
19735 * be the NQ ID returned from the `nq_alloc` HWRM command.
19737 uint16_t cmpl_ring;
19739 * The sequence ID is used by the driver for tracking multiple
19740 * commands. This ID is treated as opaque data by the firmware and
19741 * the value is returned in the `hwrm_resp_hdr` upon completion.
19745 * The target ID of the command:
19746 * * 0x0-0xFFF8 - The function ID
19747 * * 0xFFF8-0xFFFE - Reserved for internal processors
19750 uint16_t target_id;
19752 * A physical address pointer pointing to a host buffer that the
19753 * command's response data will be written. This can be either a host
19754 * physical address (HPA) or a guest physical address (GPA) and must
19755 * point to a physically contiguous block of memory.
19757 uint64_t resp_addr;
19760 * This bit must be '1' for the ring_arb_cfg field to be
19763 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
19766 * This bit must be '1' for the stat_ctx_id_valid field to be
19769 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
19772 * This bit must be '1' for the max_bw_valid field to be
19775 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
19778 * This bit must be '1' for the rx_ring_id field to be
19781 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
19784 * This bit must be '1' for the nq_ring_id field to be
19787 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
19790 * This bit must be '1' for the rx_buf_size field to be
19793 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
19797 /* L2 Completion Ring (CR) */
19798 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19800 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
19802 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
19803 /* RoCE Notification Completion Ring (ROCE_CR) */
19804 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19805 /* RX Aggregation Ring */
19806 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
19807 /* Notification Queue */
19808 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
19809 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
19810 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
19812 /* Ring allocation flags. */
19815 * For Rx rings, the incoming packet data can be placed at either
19816 * a 0B or 2B offset from the start of the Rx packet buffer. When
19817 * '1', the received packet will be padded with 2B of zeros at the
19818 * front of the packet. Note that this flag is only used for
19819 * Rx rings and is ignored for all other rings included Rx
19820 * Aggregation rings.
19822 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
19824 * This value is a pointer to the page table for the
19827 uint64_t page_tbl_addr;
19828 /* First Byte Offset of the first entry in the first page. */
19831 * Actual page size in 2^page_size. The supported range is increments
19832 * in powers of 2 from 16 bytes to 1GB.
19834 * Page size is 16 B.
19836 * Page size is 4 KB.
19838 * Page size is 8 KB.
19840 * Page size is 64 KB.
19842 * Page size is 2 MB.
19844 * Page size is 4 MB.
19846 * Page size is 1 GB.
19850 * This value indicates the depth of page table.
19851 * For this version of the specification, value other than 0 or
19852 * 1 shall be considered as an invalid value.
19853 * When the page_tbl_depth = 0, then it is treated as a
19854 * special case with the following.
19855 * 1. FBO and page size fields are not valid.
19856 * 2. page_tbl_addr is the physical address of the first
19857 * element of the ring.
19859 uint8_t page_tbl_depth;
19860 uint8_t unused_1[2];
19862 * Number of 16B units in the ring. Minimum size for
19863 * a ring is 16 16B entries.
19867 * Logical ring number for the ring to be allocated.
19868 * This value determines the position in the doorbell
19869 * area where the update to the ring will be made.
19871 * For completion rings, this value is also the MSI-X
19872 * vector number for the function the completion ring is
19875 uint16_t logical_id;
19877 * This field is used only when ring_type is a TX ring.
19878 * This value indicates what completion ring the TX ring
19879 * is associated with.
19881 uint16_t cmpl_ring_id;
19883 * This field is used only when ring_type is a TX ring.
19884 * This value indicates what CoS queue the TX ring
19885 * is associated with.
19889 * When allocating a Rx ring or Rx aggregation ring, this field
19890 * specifies the size of the buffer descriptors posted to the ring.
19892 uint16_t rx_buf_size;
19894 * When allocating an Rx aggregation ring, this field
19895 * specifies the associated Rx ring ID.
19897 uint16_t rx_ring_id;
19899 * When allocating a completion ring, this field
19900 * specifies the associated NQ ring ID.
19902 uint16_t nq_ring_id;
19904 * This field is used only when ring_type is a TX ring.
19905 * This field is used to configure arbitration related
19906 * parameters for a TX ring.
19908 uint16_t ring_arb_cfg;
19909 /* Arbitration policy used for the ring. */
19910 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
19912 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
19914 * Use strict priority for the TX ring.
19915 * Priority value is specified in arb_policy_param
19917 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
19920 * Use weighted fair queue arbitration for the TX ring.
19921 * Weight is specified in arb_policy_param
19923 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
19925 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
19926 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
19927 /* Reserved field. */
19928 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
19930 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
19932 * Arbitration policy specific parameter.
19933 * # For strict priority arbitration policy, this field
19934 * represents a priority value. If set to 0, then the priority
19935 * is not specified and the HWRM is allowed to select
19936 * any priority for this TX ring.
19937 * # For weighted fair queue arbitration policy, this field
19938 * represents a weight value. If set to 0, then the weight
19939 * is not specified and the HWRM is allowed to select
19940 * any weight for this TX ring.
19942 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
19944 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
19947 * This field is reserved for the future use.
19948 * It shall be set to 0.
19950 uint32_t reserved3;
19952 * This field is used only when ring_type is a TX ring.
19953 * This input indicates what statistics context this ring
19954 * should be associated with.
19956 uint32_t stat_ctx_id;
19958 * This field is reserved for the future use.
19959 * It shall be set to 0.
19961 uint32_t reserved4;
19963 * This field is used only when ring_type is a TX ring
19964 * to specify maximum BW allocated to the TX ring.
19965 * The HWRM will translate this value into byte counter and
19966 * time interval used for this ring inside the device.
19969 /* The bandwidth value. */
19970 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
19971 UINT32_C(0xfffffff)
19972 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
19973 /* The granularity of the value (bits or bytes). */
19974 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
19975 UINT32_C(0x10000000)
19976 /* Value is in bits. */
19977 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
19978 (UINT32_C(0x0) << 28)
19979 /* Value is in bytes. */
19980 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
19981 (UINT32_C(0x1) << 28)
19982 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
19983 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
19984 /* bw_value_unit is 3 b */
19985 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
19986 UINT32_C(0xe0000000)
19987 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
19988 /* Value is in Mb or MB (base 10). */
19989 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
19990 (UINT32_C(0x0) << 29)
19991 /* Value is in Kb or KB (base 10). */
19992 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
19993 (UINT32_C(0x2) << 29)
19994 /* Value is in bits or bytes. */
19995 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
19996 (UINT32_C(0x4) << 29)
19997 /* Value is in Gb or GB (base 10). */
19998 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
19999 (UINT32_C(0x6) << 29)
20000 /* Value is in 1/100th of a percentage of total bandwidth. */
20001 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
20002 (UINT32_C(0x1) << 29)
20004 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
20005 (UINT32_C(0x7) << 29)
20006 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
20007 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
20009 * This field is used only when ring_type is a Completion ring.
20010 * This value indicates what interrupt mode should be used
20011 * on this completion ring.
20012 * Note: In the legacy interrupt mode, no more than 16
20013 * completion rings are allowed.
20017 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
20019 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
20021 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
20022 /* No Interrupt - Polled mode */
20023 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
20024 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
20025 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
20026 uint8_t unused_4[3];
20028 * The cq_handle is specified when allocating a completion ring. For
20029 * devices that support NQs, this cq_handle will be included in the
20030 * NQE to specify which CQ should be read to retrieve the completion
20033 uint64_t cq_handle;
20034 } __attribute__((packed));
20036 /* hwrm_ring_alloc_output (size:128b/16B) */
20037 struct hwrm_ring_alloc_output {
20038 /* The specific error status for the command. */
20039 uint16_t error_code;
20040 /* The HWRM command request type. */
20042 /* The sequence ID from the original command. */
20044 /* The length of the response data in number of bytes. */
20047 * Physical number of ring allocated.
20048 * This value shall be unique for a ring type.
20051 /* Logical number of ring allocated. */
20052 uint16_t logical_ring_id;
20053 uint8_t unused_0[3];
20055 * This field is used in Output records to indicate that the output
20056 * is completely written to RAM. This field should be read as '1'
20057 * to indicate that the output has been completely written.
20058 * When writing a command completion or response to an internal processor,
20059 * the order of writes has to be such that this field is written last.
20062 } __attribute__((packed));
20064 /******************
20066 ******************/
20069 /* hwrm_ring_free_input (size:192b/24B) */
20070 struct hwrm_ring_free_input {
20071 /* The HWRM command request type. */
20074 * The completion ring to send the completion event on. This should
20075 * be the NQ ID returned from the `nq_alloc` HWRM command.
20077 uint16_t cmpl_ring;
20079 * The sequence ID is used by the driver for tracking multiple
20080 * commands. This ID is treated as opaque data by the firmware and
20081 * the value is returned in the `hwrm_resp_hdr` upon completion.
20085 * The target ID of the command:
20086 * * 0x0-0xFFF8 - The function ID
20087 * * 0xFFF8-0xFFFE - Reserved for internal processors
20090 uint16_t target_id;
20092 * A physical address pointer pointing to a host buffer that the
20093 * command's response data will be written. This can be either a host
20094 * physical address (HPA) or a guest physical address (GPA) and must
20095 * point to a physically contiguous block of memory.
20097 uint64_t resp_addr;
20100 /* L2 Completion Ring (CR) */
20101 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
20103 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
20105 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
20106 /* RoCE Notification Completion Ring (ROCE_CR) */
20107 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
20108 /* RX Aggregation Ring */
20109 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
20110 /* Notification Queue */
20111 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
20112 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
20113 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
20115 /* Physical number of ring allocated. */
20117 uint8_t unused_1[4];
20118 } __attribute__((packed));
20120 /* hwrm_ring_free_output (size:128b/16B) */
20121 struct hwrm_ring_free_output {
20122 /* The specific error status for the command. */
20123 uint16_t error_code;
20124 /* The HWRM command request type. */
20126 /* The sequence ID from the original command. */
20128 /* The length of the response data in number of bytes. */
20130 uint8_t unused_0[7];
20132 * This field is used in Output records to indicate that the output
20133 * is completely written to RAM. This field should be read as '1'
20134 * to indicate that the output has been completely written.
20135 * When writing a command completion or response to an internal processor,
20136 * the order of writes has to be such that this field is written last.
20139 } __attribute__((packed));
20141 /*******************
20142 * hwrm_ring_reset *
20143 *******************/
20146 /* hwrm_ring_reset_input (size:192b/24B) */
20147 struct hwrm_ring_reset_input {
20148 /* The HWRM command request type. */
20151 * The completion ring to send the completion event on. This should
20152 * be the NQ ID returned from the `nq_alloc` HWRM command.
20154 uint16_t cmpl_ring;
20156 * The sequence ID is used by the driver for tracking multiple
20157 * commands. This ID is treated as opaque data by the firmware and
20158 * the value is returned in the `hwrm_resp_hdr` upon completion.
20162 * The target ID of the command:
20163 * * 0x0-0xFFF8 - The function ID
20164 * * 0xFFF8-0xFFFE - Reserved for internal processors
20167 uint16_t target_id;
20169 * A physical address pointer pointing to a host buffer that the
20170 * command's response data will be written. This can be either a host
20171 * physical address (HPA) or a guest physical address (GPA) and must
20172 * point to a physically contiguous block of memory.
20174 uint64_t resp_addr;
20177 /* L2 Completion Ring (CR) */
20178 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
20180 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
20182 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
20183 /* RoCE Notification Completion Ring (ROCE_CR) */
20184 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
20185 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
20186 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
20188 /* Physical number of the ring. */
20190 uint8_t unused_1[4];
20191 } __attribute__((packed));
20193 /* hwrm_ring_reset_output (size:128b/16B) */
20194 struct hwrm_ring_reset_output {
20195 /* The specific error status for the command. */
20196 uint16_t error_code;
20197 /* The HWRM command request type. */
20199 /* The sequence ID from the original command. */
20201 /* The length of the response data in number of bytes. */
20203 uint8_t unused_0[7];
20205 * This field is used in Output records to indicate that the output
20206 * is completely written to RAM. This field should be read as '1'
20207 * to indicate that the output has been completely written.
20208 * When writing a command completion or response to an internal processor,
20209 * the order of writes has to be such that this field is written last.
20212 } __attribute__((packed));
20214 /**************************
20215 * hwrm_ring_aggint_qcaps *
20216 **************************/
20219 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
20220 struct hwrm_ring_aggint_qcaps_input {
20221 /* The HWRM command request type. */
20224 * The completion ring to send the completion event on. This should
20225 * be the NQ ID returned from the `nq_alloc` HWRM command.
20227 uint16_t cmpl_ring;
20229 * The sequence ID is used by the driver for tracking multiple
20230 * commands. This ID is treated as opaque data by the firmware and
20231 * the value is returned in the `hwrm_resp_hdr` upon completion.
20235 * The target ID of the command:
20236 * * 0x0-0xFFF8 - The function ID
20237 * * 0xFFF8-0xFFFE - Reserved for internal processors
20240 uint16_t target_id;
20242 * A physical address pointer pointing to a host buffer that the
20243 * command's response data will be written. This can be either a host
20244 * physical address (HPA) or a guest physical address (GPA) and must
20245 * point to a physically contiguous block of memory.
20247 uint64_t resp_addr;
20248 } __attribute__((packed));
20250 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
20251 struct hwrm_ring_aggint_qcaps_output {
20252 /* The specific error status for the command. */
20253 uint16_t error_code;
20254 /* The HWRM command request type. */
20256 /* The sequence ID from the original command. */
20258 /* The length of the response data in number of bytes. */
20260 uint32_t cmpl_params;
20262 * When this bit is set to '1', int_lat_tmr_min can be configured
20263 * on completion rings.
20265 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
20268 * When this bit is set to '1', int_lat_tmr_max can be configured
20269 * on completion rings.
20271 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
20274 * When this bit is set to '1', timer_reset can be enabled
20275 * on completion rings.
20277 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
20280 * When this bit is set to '1', ring_idle can be enabled
20281 * on completion rings.
20283 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
20286 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
20287 * on completion rings.
20289 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
20292 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
20293 * on completion rings.
20295 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
20298 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
20299 * on completion rings.
20301 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
20304 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
20305 * on completion rings.
20307 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
20310 * When this bit is set to '1', num_cmpl_aggr_int can be configured
20311 * on completion rings.
20313 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
20315 uint32_t nq_params;
20317 * When this bit is set to '1', int_lat_tmr_min can be configured
20318 * on notification queues.
20320 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
20322 /* Minimum value for num_cmpl_dma_aggr */
20323 uint16_t num_cmpl_dma_aggr_min;
20324 /* Maximum value for num_cmpl_dma_aggr */
20325 uint16_t num_cmpl_dma_aggr_max;
20326 /* Minimum value for num_cmpl_dma_aggr_during_int */
20327 uint16_t num_cmpl_dma_aggr_during_int_min;
20328 /* Maximum value for num_cmpl_dma_aggr_during_int */
20329 uint16_t num_cmpl_dma_aggr_during_int_max;
20330 /* Minimum value for cmpl_aggr_dma_tmr */
20331 uint16_t cmpl_aggr_dma_tmr_min;
20332 /* Maximum value for cmpl_aggr_dma_tmr */
20333 uint16_t cmpl_aggr_dma_tmr_max;
20334 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
20335 uint16_t cmpl_aggr_dma_tmr_during_int_min;
20336 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
20337 uint16_t cmpl_aggr_dma_tmr_during_int_max;
20338 /* Minimum value for int_lat_tmr_min */
20339 uint16_t int_lat_tmr_min_min;
20340 /* Maximum value for int_lat_tmr_min */
20341 uint16_t int_lat_tmr_min_max;
20342 /* Minimum value for int_lat_tmr_max */
20343 uint16_t int_lat_tmr_max_min;
20344 /* Maximum value for int_lat_tmr_max */
20345 uint16_t int_lat_tmr_max_max;
20346 /* Minimum value for num_cmpl_aggr_int */
20347 uint16_t num_cmpl_aggr_int_min;
20348 /* Maximum value for num_cmpl_aggr_int */
20349 uint16_t num_cmpl_aggr_int_max;
20350 /* The units for timer parameters, in nanoseconds. */
20351 uint16_t timer_units;
20352 uint8_t unused_0[1];
20354 * This field is used in Output records to indicate that the output
20355 * is completely written to RAM. This field should be read as '1'
20356 * to indicate that the output has been completely written.
20357 * When writing a command completion or response to an internal processor,
20358 * the order of writes has to be such that this field is written last.
20361 } __attribute__((packed));
20363 /**************************************
20364 * hwrm_ring_cmpl_ring_qaggint_params *
20365 **************************************/
20368 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
20369 struct hwrm_ring_cmpl_ring_qaggint_params_input {
20370 /* The HWRM command request type. */
20373 * The completion ring to send the completion event on. This should
20374 * be the NQ ID returned from the `nq_alloc` HWRM command.
20376 uint16_t cmpl_ring;
20378 * The sequence ID is used by the driver for tracking multiple
20379 * commands. This ID is treated as opaque data by the firmware and
20380 * the value is returned in the `hwrm_resp_hdr` upon completion.
20384 * The target ID of the command:
20385 * * 0x0-0xFFF8 - The function ID
20386 * * 0xFFF8-0xFFFE - Reserved for internal processors
20389 uint16_t target_id;
20391 * A physical address pointer pointing to a host buffer that the
20392 * command's response data will be written. This can be either a host
20393 * physical address (HPA) or a guest physical address (GPA) and must
20394 * point to a physically contiguous block of memory.
20396 uint64_t resp_addr;
20397 /* Physical number of completion ring. */
20399 uint8_t unused_0[6];
20400 } __attribute__((packed));
20402 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
20403 struct hwrm_ring_cmpl_ring_qaggint_params_output {
20404 /* The specific error status for the command. */
20405 uint16_t error_code;
20406 /* The HWRM command request type. */
20408 /* The sequence ID from the original command. */
20410 /* The length of the response data in number of bytes. */
20414 * When this bit is set to '1', interrupt max
20415 * timer is reset whenever a completion is received.
20417 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
20420 * When this bit is set to '1', ring idle mode
20421 * aggregation will be enabled.
20423 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
20426 * Number of completions to aggregate before DMA
20427 * during the normal mode.
20429 uint16_t num_cmpl_dma_aggr;
20431 * Number of completions to aggregate before DMA
20432 * during the interrupt mode.
20434 uint16_t num_cmpl_dma_aggr_during_int;
20436 * Timer in unit of 80-nsec used to aggregate completions before
20437 * DMA during the normal mode (not in interrupt mode).
20439 uint16_t cmpl_aggr_dma_tmr;
20441 * Timer in unit of 80-nsec used to aggregate completions before
20442 * DMA during the interrupt mode.
20444 uint16_t cmpl_aggr_dma_tmr_during_int;
20445 /* Minimum time (in unit of 80-nsec) between two interrupts. */
20446 uint16_t int_lat_tmr_min;
20448 * Maximum wait time (in unit of 80-nsec) spent aggregating
20449 * completions before signaling the interrupt after the
20450 * interrupt is enabled.
20452 uint16_t int_lat_tmr_max;
20454 * Minimum number of completions aggregated before signaling
20457 uint16_t num_cmpl_aggr_int;
20458 uint8_t unused_0[7];
20460 * This field is used in Output records to indicate that the output
20461 * is completely written to RAM. This field should be read as '1'
20462 * to indicate that the output has been completely written.
20463 * When writing a command completion or response to an internal processor,
20464 * the order of writes has to be such that this field is written last.
20467 } __attribute__((packed));
20469 /*****************************************
20470 * hwrm_ring_cmpl_ring_cfg_aggint_params *
20471 *****************************************/
20474 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
20475 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
20476 /* The HWRM command request type. */
20479 * The completion ring to send the completion event on. This should
20480 * be the NQ ID returned from the `nq_alloc` HWRM command.
20482 uint16_t cmpl_ring;
20484 * The sequence ID is used by the driver for tracking multiple
20485 * commands. This ID is treated as opaque data by the firmware and
20486 * the value is returned in the `hwrm_resp_hdr` upon completion.
20490 * The target ID of the command:
20491 * * 0x0-0xFFF8 - The function ID
20492 * * 0xFFF8-0xFFFE - Reserved for internal processors
20495 uint16_t target_id;
20497 * A physical address pointer pointing to a host buffer that the
20498 * command's response data will be written. This can be either a host
20499 * physical address (HPA) or a guest physical address (GPA) and must
20500 * point to a physically contiguous block of memory.
20502 uint64_t resp_addr;
20503 /* Physical number of completion ring. */
20507 * When this bit is set to '1', interrupt latency max
20508 * timer is reset whenever a completion is received.
20510 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
20513 * When this bit is set to '1', ring idle mode
20514 * aggregation will be enabled.
20516 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
20519 * Set this flag to 1 when configuring parameters on a
20520 * notification queue. Set this flag to 0 when configuring
20521 * parameters on a completion queue.
20523 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
20526 * Number of completions to aggregate before DMA
20527 * during the normal mode.
20529 uint16_t num_cmpl_dma_aggr;
20531 * Number of completions to aggregate before DMA
20532 * during the interrupt mode.
20534 uint16_t num_cmpl_dma_aggr_during_int;
20536 * Timer in unit of 80-nsec used to aggregate completions before
20537 * DMA during the normal mode (not in interrupt mode).
20539 uint16_t cmpl_aggr_dma_tmr;
20541 * Timer in unit of 80-nsec used to aggregate completions before
20542 * DMA during the interrupt mode.
20544 uint16_t cmpl_aggr_dma_tmr_during_int;
20545 /* Minimum time (in unit of 80-nsec) between two interrupts. */
20546 uint16_t int_lat_tmr_min;
20548 * Maximum wait time (in unit of 80-nsec) spent aggregating
20549 * cmpls before signaling the interrupt after the
20550 * interrupt is enabled.
20552 uint16_t int_lat_tmr_max;
20554 * Minimum number of completions aggregated before signaling
20557 uint16_t num_cmpl_aggr_int;
20559 * Bitfield that indicates which parameters are to be applied. Only
20560 * required when configuring devices with notification queues, and
20561 * used in that case to set certain parameters on completion queues
20562 * and others on notification queues.
20566 * This bit must be '1' for the num_cmpl_dma_aggr field to be
20569 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
20572 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
20575 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
20578 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
20581 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
20584 * This bit must be '1' for the int_lat_tmr_min field to be
20587 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
20590 * This bit must be '1' for the int_lat_tmr_max field to be
20593 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
20596 * This bit must be '1' for the num_cmpl_aggr_int field to be
20599 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
20601 uint8_t unused_0[4];
20602 } __attribute__((packed));
20604 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
20605 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
20606 /* The specific error status for the command. */
20607 uint16_t error_code;
20608 /* The HWRM command request type. */
20610 /* The sequence ID from the original command. */
20612 /* The length of the response data in number of bytes. */
20614 uint8_t unused_0[7];
20616 * This field is used in Output records to indicate that the output
20617 * is completely written to RAM. This field should be read as '1'
20618 * to indicate that the output has been completely written.
20619 * When writing a command completion or response to an internal processor,
20620 * the order of writes has to be such that this field is written last.
20623 } __attribute__((packed));
20625 /***********************
20626 * hwrm_ring_grp_alloc *
20627 ***********************/
20630 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
20631 struct hwrm_ring_grp_alloc_input {
20632 /* The HWRM command request type. */
20635 * The completion ring to send the completion event on. This should
20636 * be the NQ ID returned from the `nq_alloc` HWRM command.
20638 uint16_t cmpl_ring;
20640 * The sequence ID is used by the driver for tracking multiple
20641 * commands. This ID is treated as opaque data by the firmware and
20642 * the value is returned in the `hwrm_resp_hdr` upon completion.
20646 * The target ID of the command:
20647 * * 0x0-0xFFF8 - The function ID
20648 * * 0xFFF8-0xFFFE - Reserved for internal processors
20651 uint16_t target_id;
20653 * A physical address pointer pointing to a host buffer that the
20654 * command's response data will be written. This can be either a host
20655 * physical address (HPA) or a guest physical address (GPA) and must
20656 * point to a physically contiguous block of memory.
20658 uint64_t resp_addr;
20660 * This value identifies the CR associated with the ring
20665 * This value identifies the main RR associated with the ring
20670 * This value identifies the aggregation RR associated with
20671 * the ring group. If this value is 0xFF... (All Fs), then no
20672 * Aggregation ring will be set.
20676 * This value identifies the statistics context associated
20677 * with the ring group.
20680 } __attribute__((packed));
20682 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
20683 struct hwrm_ring_grp_alloc_output {
20684 /* The specific error status for the command. */
20685 uint16_t error_code;
20686 /* The HWRM command request type. */
20688 /* The sequence ID from the original command. */
20690 /* The length of the response data in number of bytes. */
20693 * This is the ring group ID value. Use this value to program
20694 * the default ring group for the VNIC or as table entries
20695 * in an RSS/COS context.
20697 uint32_t ring_group_id;
20698 uint8_t unused_0[3];
20700 * This field is used in Output records to indicate that the output
20701 * is completely written to RAM. This field should be read as '1'
20702 * to indicate that the output has been completely written.
20703 * When writing a command completion or response to an internal processor,
20704 * the order of writes has to be such that this field is written last.
20707 } __attribute__((packed));
20709 /**********************
20710 * hwrm_ring_grp_free *
20711 **********************/
20714 /* hwrm_ring_grp_free_input (size:192b/24B) */
20715 struct hwrm_ring_grp_free_input {
20716 /* The HWRM command request type. */
20719 * The completion ring to send the completion event on. This should
20720 * be the NQ ID returned from the `nq_alloc` HWRM command.
20722 uint16_t cmpl_ring;
20724 * The sequence ID is used by the driver for tracking multiple
20725 * commands. This ID is treated as opaque data by the firmware and
20726 * the value is returned in the `hwrm_resp_hdr` upon completion.
20730 * The target ID of the command:
20731 * * 0x0-0xFFF8 - The function ID
20732 * * 0xFFF8-0xFFFE - Reserved for internal processors
20735 uint16_t target_id;
20737 * A physical address pointer pointing to a host buffer that the
20738 * command's response data will be written. This can be either a host
20739 * physical address (HPA) or a guest physical address (GPA) and must
20740 * point to a physically contiguous block of memory.
20742 uint64_t resp_addr;
20743 /* This is the ring group ID value. */
20744 uint32_t ring_group_id;
20745 uint8_t unused_0[4];
20746 } __attribute__((packed));
20748 /* hwrm_ring_grp_free_output (size:128b/16B) */
20749 struct hwrm_ring_grp_free_output {
20750 /* The specific error status for the command. */
20751 uint16_t error_code;
20752 /* The HWRM command request type. */
20754 /* The sequence ID from the original command. */
20756 /* The length of the response data in number of bytes. */
20758 uint8_t unused_0[7];
20760 * This field is used in Output records to indicate that the output
20761 * is completely written to RAM. This field should be read as '1'
20762 * to indicate that the output has been completely written.
20763 * When writing a command completion or response to an internal processor,
20764 * the order of writes has to be such that this field is written last.
20767 } __attribute__((packed));
20769 /****************************
20770 * hwrm_cfa_l2_filter_alloc *
20771 ****************************/
20774 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
20775 struct hwrm_cfa_l2_filter_alloc_input {
20776 /* The HWRM command request type. */
20779 * The completion ring to send the completion event on. This should
20780 * be the NQ ID returned from the `nq_alloc` HWRM command.
20782 uint16_t cmpl_ring;
20784 * The sequence ID is used by the driver for tracking multiple
20785 * commands. This ID is treated as opaque data by the firmware and
20786 * the value is returned in the `hwrm_resp_hdr` upon completion.
20790 * The target ID of the command:
20791 * * 0x0-0xFFF8 - The function ID
20792 * * 0xFFF8-0xFFFE - Reserved for internal processors
20795 uint16_t target_id;
20797 * A physical address pointer pointing to a host buffer that the
20798 * command's response data will be written. This can be either a host
20799 * physical address (HPA) or a guest physical address (GPA) and must
20800 * point to a physically contiguous block of memory.
20802 uint64_t resp_addr;
20805 * Enumeration denoting the RX, TX type of the resource.
20806 * This enumeration is used for resources that are similar for both
20807 * TX and RX paths of the chip.
20809 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
20812 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
20815 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
20817 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
20818 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
20819 /* Setting of this flag indicates the applicability to the loopback path. */
20820 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
20823 * Setting of this flag indicates drop action. If this flag is not set,
20824 * then it should be considered accept action.
20826 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
20829 * If this flag is set, all t_l2_* fields are invalid
20830 * and they should not be specified.
20831 * If this flag is set, then l2_* fields refer to
20832 * fields of outermost L2 header.
20834 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
20837 * Enumeration denoting NO_ROCE_L2 to support old drivers.
20838 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
20840 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
20842 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
20843 /* To support old drivers */
20844 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
20845 (UINT32_C(0x0) << 4)
20846 /* Only L2 traffic */
20847 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
20848 (UINT32_C(0x1) << 4)
20849 /* Roce & L2 traffic */
20850 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
20851 (UINT32_C(0x2) << 4)
20852 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
20853 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
20856 * This bit must be '1' for the l2_addr field to be
20859 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
20862 * This bit must be '1' for the l2_addr_mask field to be
20865 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
20868 * This bit must be '1' for the l2_ovlan field to be
20871 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
20874 * This bit must be '1' for the l2_ovlan_mask field to be
20877 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
20880 * This bit must be '1' for the l2_ivlan field to be
20883 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
20886 * This bit must be '1' for the l2_ivlan_mask field to be
20889 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
20892 * This bit must be '1' for the t_l2_addr field to be
20895 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
20898 * This bit must be '1' for the t_l2_addr_mask field to be
20901 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
20904 * This bit must be '1' for the t_l2_ovlan field to be
20907 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
20910 * This bit must be '1' for the t_l2_ovlan_mask field to be
20913 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
20916 * This bit must be '1' for the t_l2_ivlan field to be
20919 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
20922 * This bit must be '1' for the t_l2_ivlan_mask field to be
20925 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
20928 * This bit must be '1' for the src_type field to be
20931 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
20934 * This bit must be '1' for the src_id field to be
20937 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
20940 * This bit must be '1' for the tunnel_type field to be
20943 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
20946 * This bit must be '1' for the dst_id field to be
20949 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
20952 * This bit must be '1' for the mirror_vnic_id field to be
20955 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
20958 * This value sets the match value for the L2 MAC address.
20959 * Destination MAC address for RX path.
20960 * Source MAC address for TX path.
20962 uint8_t l2_addr[6];
20963 uint8_t unused_0[2];
20965 * This value sets the mask value for the L2 address.
20966 * A value of 0 will mask the corresponding bit from
20969 uint8_t l2_addr_mask[6];
20970 /* This value sets VLAN ID value for outer VLAN. */
20973 * This value sets the mask value for the ovlan id.
20974 * A value of 0 will mask the corresponding bit from
20977 uint16_t l2_ovlan_mask;
20978 /* This value sets VLAN ID value for inner VLAN. */
20981 * This value sets the mask value for the ivlan id.
20982 * A value of 0 will mask the corresponding bit from
20985 uint16_t l2_ivlan_mask;
20986 uint8_t unused_1[2];
20988 * This value sets the match value for the tunnel
20990 * Destination MAC address for RX path.
20991 * Source MAC address for TX path.
20993 uint8_t t_l2_addr[6];
20994 uint8_t unused_2[2];
20996 * This value sets the mask value for the tunnel L2
20998 * A value of 0 will mask the corresponding bit from
21001 uint8_t t_l2_addr_mask[6];
21002 /* This value sets VLAN ID value for tunnel outer VLAN. */
21003 uint16_t t_l2_ovlan;
21005 * This value sets the mask value for the tunnel ovlan id.
21006 * A value of 0 will mask the corresponding bit from
21009 uint16_t t_l2_ovlan_mask;
21010 /* This value sets VLAN ID value for tunnel inner VLAN. */
21011 uint16_t t_l2_ivlan;
21013 * This value sets the mask value for the tunnel ivlan id.
21014 * A value of 0 will mask the corresponding bit from
21017 uint16_t t_l2_ivlan_mask;
21018 /* This value identifies the type of source of the packet. */
21021 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
21022 /* Physical function */
21023 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
21024 /* Virtual function */
21025 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
21026 /* Virtual NIC of a function */
21027 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
21028 /* Embedded processor for CFA management */
21029 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
21030 /* Embedded processor for OOB management */
21031 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
21032 /* Embedded processor for RoCE */
21033 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
21034 /* Embedded processor for network proxy functions */
21035 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
21036 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
21037 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
21040 * This value is the id of the source.
21041 * For a network port, it represents port_id.
21042 * For a physical function, it represents fid.
21043 * For a virtual function, it represents vf_id.
21044 * For a vnic, it represents vnic_id.
21045 * For embedded processors, this id is not valid.
21048 * 1. The function ID is implied if it src_id is
21049 * not provided for a src_type that is either
21053 uint8_t tunnel_type;
21055 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21057 /* Virtual eXtensible Local Area Network (VXLAN) */
21058 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21060 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21061 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21063 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21064 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21067 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21069 /* Generic Network Virtualization Encapsulation (Geneve) */
21070 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21072 /* Multi-Protocol Lable Switching (MPLS) */
21073 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21075 /* Stateless Transport Tunnel (STT) */
21076 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21078 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21079 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21081 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21082 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21084 /* Any tunneled traffic */
21085 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21087 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21088 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21091 * If set, this value shall represent the
21092 * Logical VNIC ID of the destination VNIC for the RX
21093 * path and network port id of the destination port for
21098 * Logical VNIC ID of the VNIC where traffic is
21101 uint16_t mirror_vnic_id;
21103 * This hint is provided to help in placing
21104 * the filter in the filter table.
21107 /* No preference */
21108 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
21110 /* Above the given filter */
21111 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
21113 /* Below the given filter */
21114 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
21116 /* As high as possible */
21117 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
21119 /* As low as possible */
21120 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
21122 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
21123 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
21127 * This is the ID of the filter that goes along with
21130 * This field is valid only for the following values.
21131 * 1 - Above the given filter
21132 * 2 - Below the given filter
21134 uint64_t l2_filter_id_hint;
21135 } __attribute__((packed));
21137 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
21138 struct hwrm_cfa_l2_filter_alloc_output {
21139 /* The specific error status for the command. */
21140 uint16_t error_code;
21141 /* The HWRM command request type. */
21143 /* The sequence ID from the original command. */
21145 /* The length of the response data in number of bytes. */
21148 * This value identifies a set of CFA data structures used for an L2
21151 uint64_t l2_filter_id;
21153 * This is the ID of the flow associated with this
21155 * This value shall be used to match and associate the
21156 * flow identifier returned in completion records.
21157 * A value of 0xFFFFFFFF shall indicate no flow id.
21160 uint8_t unused_0[3];
21162 * This field is used in Output records to indicate that the output
21163 * is completely written to RAM. This field should be read as '1'
21164 * to indicate that the output has been completely written.
21165 * When writing a command completion or response to an internal processor,
21166 * the order of writes has to be such that this field is written last.
21169 } __attribute__((packed));
21171 /***************************
21172 * hwrm_cfa_l2_filter_free *
21173 ***************************/
21176 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
21177 struct hwrm_cfa_l2_filter_free_input {
21178 /* The HWRM command request type. */
21181 * The completion ring to send the completion event on. This should
21182 * be the NQ ID returned from the `nq_alloc` HWRM command.
21184 uint16_t cmpl_ring;
21186 * The sequence ID is used by the driver for tracking multiple
21187 * commands. This ID is treated as opaque data by the firmware and
21188 * the value is returned in the `hwrm_resp_hdr` upon completion.
21192 * The target ID of the command:
21193 * * 0x0-0xFFF8 - The function ID
21194 * * 0xFFF8-0xFFFE - Reserved for internal processors
21197 uint16_t target_id;
21199 * A physical address pointer pointing to a host buffer that the
21200 * command's response data will be written. This can be either a host
21201 * physical address (HPA) or a guest physical address (GPA) and must
21202 * point to a physically contiguous block of memory.
21204 uint64_t resp_addr;
21206 * This value identifies a set of CFA data structures used for an L2
21209 uint64_t l2_filter_id;
21210 } __attribute__((packed));
21212 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
21213 struct hwrm_cfa_l2_filter_free_output {
21214 /* The specific error status for the command. */
21215 uint16_t error_code;
21216 /* The HWRM command request type. */
21218 /* The sequence ID from the original command. */
21220 /* The length of the response data in number of bytes. */
21222 uint8_t unused_0[7];
21224 * This field is used in Output records to indicate that the output
21225 * is completely written to RAM. This field should be read as '1'
21226 * to indicate that the output has been completely written.
21227 * When writing a command completion or response to an internal processor,
21228 * the order of writes has to be such that this field is written last.
21231 } __attribute__((packed));
21233 /**************************
21234 * hwrm_cfa_l2_filter_cfg *
21235 **************************/
21238 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
21239 struct hwrm_cfa_l2_filter_cfg_input {
21240 /* The HWRM command request type. */
21243 * The completion ring to send the completion event on. This should
21244 * be the NQ ID returned from the `nq_alloc` HWRM command.
21246 uint16_t cmpl_ring;
21248 * The sequence ID is used by the driver for tracking multiple
21249 * commands. This ID is treated as opaque data by the firmware and
21250 * the value is returned in the `hwrm_resp_hdr` upon completion.
21254 * The target ID of the command:
21255 * * 0x0-0xFFF8 - The function ID
21256 * * 0xFFF8-0xFFFE - Reserved for internal processors
21259 uint16_t target_id;
21261 * A physical address pointer pointing to a host buffer that the
21262 * command's response data will be written. This can be either a host
21263 * physical address (HPA) or a guest physical address (GPA) and must
21264 * point to a physically contiguous block of memory.
21266 uint64_t resp_addr;
21269 * Enumeration denoting the RX, TX type of the resource.
21270 * This enumeration is used for resources that are similar for both
21271 * TX and RX paths of the chip.
21273 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
21276 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
21279 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
21281 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
21282 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
21284 * Setting of this flag indicates drop action. If this flag is not set,
21285 * then it should be considered accept action.
21287 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
21290 * Enumeration denoting NO_ROCE_L2 to support old drivers.
21291 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
21293 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
21295 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
21296 /* To support old drivers */
21297 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
21298 (UINT32_C(0x0) << 2)
21299 /* Only L2 traffic */
21300 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
21301 (UINT32_C(0x1) << 2)
21302 /* Roce & L2 traffic */
21303 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
21304 (UINT32_C(0x2) << 2)
21305 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
21306 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
21309 * This bit must be '1' for the dst_id field to be
21312 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
21315 * This bit must be '1' for the new_mirror_vnic_id field to be
21318 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
21321 * This value identifies a set of CFA data structures used for an L2
21324 uint64_t l2_filter_id;
21326 * If set, this value shall represent the
21327 * Logical VNIC ID of the destination VNIC for the RX
21328 * path and network port id of the destination port for
21333 * New Logical VNIC ID of the VNIC where traffic is
21336 uint32_t new_mirror_vnic_id;
21337 } __attribute__((packed));
21339 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
21340 struct hwrm_cfa_l2_filter_cfg_output {
21341 /* The specific error status for the command. */
21342 uint16_t error_code;
21343 /* The HWRM command request type. */
21345 /* The sequence ID from the original command. */
21347 /* The length of the response data in number of bytes. */
21349 uint8_t unused_0[7];
21351 * This field is used in Output records to indicate that the output
21352 * is completely written to RAM. This field should be read as '1'
21353 * to indicate that the output has been completely written.
21354 * When writing a command completion or response to an internal processor,
21355 * the order of writes has to be such that this field is written last.
21358 } __attribute__((packed));
21360 /***************************
21361 * hwrm_cfa_l2_set_rx_mask *
21362 ***************************/
21365 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
21366 struct hwrm_cfa_l2_set_rx_mask_input {
21367 /* The HWRM command request type. */
21370 * The completion ring to send the completion event on. This should
21371 * be the NQ ID returned from the `nq_alloc` HWRM command.
21373 uint16_t cmpl_ring;
21375 * The sequence ID is used by the driver for tracking multiple
21376 * commands. This ID is treated as opaque data by the firmware and
21377 * the value is returned in the `hwrm_resp_hdr` upon completion.
21381 * The target ID of the command:
21382 * * 0x0-0xFFF8 - The function ID
21383 * * 0xFFF8-0xFFFE - Reserved for internal processors
21386 uint16_t target_id;
21388 * A physical address pointer pointing to a host buffer that the
21389 * command's response data will be written. This can be either a host
21390 * physical address (HPA) or a guest physical address (GPA) and must
21391 * point to a physically contiguous block of memory.
21393 uint64_t resp_addr;
21398 * When this bit is '1', the function is requested to accept
21399 * multi-cast packets specified by the multicast addr table.
21401 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
21404 * When this bit is '1', the function is requested to accept
21405 * all multi-cast packets.
21407 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
21410 * When this bit is '1', the function is requested to accept
21411 * broadcast packets.
21413 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
21416 * When this bit is '1', the function is requested to be
21417 * put in the promiscuous mode.
21419 * The HWRM should accept any function to set up
21420 * promiscuous mode.
21422 * The HWRM shall follow the semantics below for the
21423 * promiscuous mode support.
21424 * # When partitioning is not enabled on a port
21425 * (i.e. single PF on the port), then the PF shall
21426 * be allowed to be in the promiscuous mode. When the
21427 * PF is in the promiscuous mode, then it shall
21428 * receive all host bound traffic on that port.
21429 * # When partitioning is enabled on a port
21430 * (i.e. multiple PFs per port) and a PF on that
21431 * port is in the promiscuous mode, then the PF
21432 * receives all traffic within that partition as
21433 * identified by a unique identifier for the
21434 * PF (e.g. S-Tag). If a unique outer VLAN
21435 * for the PF is specified, then the setting of
21436 * promiscuous mode on that PF shall result in the
21437 * PF receiving all host bound traffic with matching
21439 * # A VF shall can be set in the promiscuous mode.
21440 * In the promiscuous mode, the VF does not receive any
21441 * traffic unless a unique outer VLAN for the
21442 * VF is specified. If a unique outer VLAN
21443 * for the VF is specified, then the setting of
21444 * promiscuous mode on that VF shall result in the
21445 * VF receiving all host bound traffic with the
21446 * matching outer VLAN.
21447 * # The HWRM shall allow the setting of promiscuous
21448 * mode on a function independently from the
21449 * promiscuous mode settings on other functions.
21451 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
21454 * If this flag is set, the corresponding RX
21455 * filters shall be set up to cover multicast/broadcast
21456 * filters for the outermost Layer 2 destination MAC
21459 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
21462 * If this flag is set, the corresponding RX
21463 * filters shall be set up to cover multicast/broadcast
21464 * filters for the VLAN-tagged packets that match the
21465 * TPID and VID fields of VLAN tags in the VLAN tag
21466 * table specified in this command.
21468 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
21471 * If this flag is set, the corresponding RX
21472 * filters shall be set up to cover multicast/broadcast
21473 * filters for non-VLAN tagged packets and VLAN-tagged
21474 * packets that match the TPID and VID fields of VLAN
21475 * tags in the VLAN tag table specified in this command.
21477 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
21480 * If this flag is set, the corresponding RX
21481 * filters shall be set up to cover multicast/broadcast
21482 * filters for non-VLAN tagged packets and VLAN-tagged
21483 * packets matching any VLAN tag.
21485 * If this flag is set, then the HWRM shall ignore
21486 * VLAN tags specified in vlan_tag_tbl.
21488 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
21489 * flags is set, then the HWRM shall ignore
21490 * VLAN tags specified in vlan_tag_tbl.
21492 * The HWRM client shall set at most one flag out of
21493 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
21495 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
21497 /* This is the address for mcast address tbl. */
21498 uint64_t mc_tbl_addr;
21500 * This value indicates how many entries in mc_tbl are valid.
21501 * Each entry is 6 bytes.
21503 uint32_t num_mc_entries;
21504 uint8_t unused_0[4];
21506 * This is the address for VLAN tag table.
21507 * Each VLAN entry in the table is 4 bytes of a VLAN tag
21508 * including TPID, PCP, DEI, and VID fields in network byte
21511 uint64_t vlan_tag_tbl_addr;
21513 * This value indicates how many entries in vlan_tag_tbl are
21514 * valid. Each entry is 4 bytes.
21516 uint32_t num_vlan_tags;
21517 uint8_t unused_1[4];
21518 } __attribute__((packed));
21520 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
21521 struct hwrm_cfa_l2_set_rx_mask_output {
21522 /* The specific error status for the command. */
21523 uint16_t error_code;
21524 /* The HWRM command request type. */
21526 /* The sequence ID from the original command. */
21528 /* The length of the response data in number of bytes. */
21530 uint8_t unused_0[7];
21532 * This field is used in Output records to indicate that the output
21533 * is completely written to RAM. This field should be read as '1'
21534 * to indicate that the output has been completely written.
21535 * When writing a command completion or response to an internal processor,
21536 * the order of writes has to be such that this field is written last.
21539 } __attribute__((packed));
21541 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
21542 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
21544 * command specific error codes that goes to
21545 * the cmd_err field in Common HWRM Error Response.
21548 /* Unknown error */
21549 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
21551 /* Unable to complete operation due to conflict with Ntuple Filter */
21552 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
21554 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
21555 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
21556 uint8_t unused_0[7];
21557 } __attribute__((packed));
21559 /*******************************
21560 * hwrm_cfa_vlan_antispoof_cfg *
21561 *******************************/
21564 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
21565 struct hwrm_cfa_vlan_antispoof_cfg_input {
21566 /* The HWRM command request type. */
21569 * The completion ring to send the completion event on. This should
21570 * be the NQ ID returned from the `nq_alloc` HWRM command.
21572 uint16_t cmpl_ring;
21574 * The sequence ID is used by the driver for tracking multiple
21575 * commands. This ID is treated as opaque data by the firmware and
21576 * the value is returned in the `hwrm_resp_hdr` upon completion.
21580 * The target ID of the command:
21581 * * 0x0-0xFFF8 - The function ID
21582 * * 0xFFF8-0xFFFE - Reserved for internal processors
21585 uint16_t target_id;
21587 * A physical address pointer pointing to a host buffer that the
21588 * command's response data will be written. This can be either a host
21589 * physical address (HPA) or a guest physical address (GPA) and must
21590 * point to a physically contiguous block of memory.
21592 uint64_t resp_addr;
21594 * Function ID of the function that is being configured.
21595 * Only valid for a VF FID configured by the PF.
21598 uint8_t unused_0[2];
21599 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
21600 uint32_t num_vlan_entries;
21602 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
21603 * antispoof table. Each table entry contains the 16-bit TPID
21604 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
21605 * all in network order to match hwrm_cfa_l2_set_rx_mask.
21606 * For an individual VLAN entry, the mask value should be 0xfff
21607 * for the 12-bit VLAN ID.
21609 uint64_t vlan_tag_mask_tbl_addr;
21610 } __attribute__((packed));
21612 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
21613 struct hwrm_cfa_vlan_antispoof_cfg_output {
21614 /* The specific error status for the command. */
21615 uint16_t error_code;
21616 /* The HWRM command request type. */
21618 /* The sequence ID from the original command. */
21620 /* The length of the response data in number of bytes. */
21622 uint8_t unused_0[7];
21624 * This field is used in Output records to indicate that the output
21625 * is completely written to RAM. This field should be read as '1'
21626 * to indicate that the output has been completely written.
21627 * When writing a command completion or response to an internal processor,
21628 * the order of writes has to be such that this field is written last.
21631 } __attribute__((packed));
21633 /********************************
21634 * hwrm_cfa_vlan_antispoof_qcfg *
21635 ********************************/
21638 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
21639 struct hwrm_cfa_vlan_antispoof_qcfg_input {
21640 /* The HWRM command request type. */
21643 * The completion ring to send the completion event on. This should
21644 * be the NQ ID returned from the `nq_alloc` HWRM command.
21646 uint16_t cmpl_ring;
21648 * The sequence ID is used by the driver for tracking multiple
21649 * commands. This ID is treated as opaque data by the firmware and
21650 * the value is returned in the `hwrm_resp_hdr` upon completion.
21654 * The target ID of the command:
21655 * * 0x0-0xFFF8 - The function ID
21656 * * 0xFFF8-0xFFFE - Reserved for internal processors
21659 uint16_t target_id;
21661 * A physical address pointer pointing to a host buffer that the
21662 * command's response data will be written. This can be either a host
21663 * physical address (HPA) or a guest physical address (GPA) and must
21664 * point to a physically contiguous block of memory.
21666 uint64_t resp_addr;
21668 * Function ID of the function that is being queried.
21669 * Only valid for a VF FID queried by the PF.
21672 uint8_t unused_0[2];
21674 * Maximum number of VLAN entries the firmware is allowed to DMA
21675 * to vlan_tag_mask_tbl.
21677 uint32_t max_vlan_entries;
21679 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
21680 * antispoof table to which firmware will DMA to. Each table
21681 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
21682 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
21683 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
21684 * the mask value should be 0xfff for the 12-bit VLAN ID.
21686 uint64_t vlan_tag_mask_tbl_addr;
21687 } __attribute__((packed));
21689 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
21690 struct hwrm_cfa_vlan_antispoof_qcfg_output {
21691 /* The specific error status for the command. */
21692 uint16_t error_code;
21693 /* The HWRM command request type. */
21695 /* The sequence ID from the original command. */
21697 /* The length of the response data in number of bytes. */
21699 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
21700 uint32_t num_vlan_entries;
21701 uint8_t unused_0[3];
21703 * This field is used in Output records to indicate that the output
21704 * is completely written to RAM. This field should be read as '1'
21705 * to indicate that the output has been completely written.
21706 * When writing a command completion or response to an internal processor,
21707 * the order of writes has to be such that this field is written last.
21710 } __attribute__((packed));
21712 /********************************
21713 * hwrm_cfa_tunnel_filter_alloc *
21714 ********************************/
21717 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
21718 struct hwrm_cfa_tunnel_filter_alloc_input {
21719 /* The HWRM command request type. */
21722 * The completion ring to send the completion event on. This should
21723 * be the NQ ID returned from the `nq_alloc` HWRM command.
21725 uint16_t cmpl_ring;
21727 * The sequence ID is used by the driver for tracking multiple
21728 * commands. This ID is treated as opaque data by the firmware and
21729 * the value is returned in the `hwrm_resp_hdr` upon completion.
21733 * The target ID of the command:
21734 * * 0x0-0xFFF8 - The function ID
21735 * * 0xFFF8-0xFFFE - Reserved for internal processors
21738 uint16_t target_id;
21740 * A physical address pointer pointing to a host buffer that the
21741 * command's response data will be written. This can be either a host
21742 * physical address (HPA) or a guest physical address (GPA) and must
21743 * point to a physically contiguous block of memory.
21745 uint64_t resp_addr;
21747 /* Setting of this flag indicates the applicability to the loopback path. */
21748 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
21752 * This bit must be '1' for the l2_filter_id field to be
21755 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
21758 * This bit must be '1' for the l2_addr field to be
21761 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
21764 * This bit must be '1' for the l2_ivlan field to be
21767 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
21770 * This bit must be '1' for the l3_addr field to be
21773 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
21776 * This bit must be '1' for the l3_addr_type field to be
21779 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
21782 * This bit must be '1' for the t_l3_addr_type field to be
21785 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
21788 * This bit must be '1' for the t_l3_addr field to be
21791 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
21794 * This bit must be '1' for the tunnel_type field to be
21797 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
21800 * This bit must be '1' for the vni field to be
21803 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
21806 * This bit must be '1' for the dst_vnic_id field to be
21809 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
21812 * This bit must be '1' for the mirror_vnic_id field to be
21815 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
21818 * This value identifies a set of CFA data structures used for an L2
21821 uint64_t l2_filter_id;
21823 * This value sets the match value for the inner L2
21825 * Destination MAC address for RX path.
21826 * Source MAC address for TX path.
21828 uint8_t l2_addr[6];
21830 * This value sets VLAN ID value for inner VLAN.
21831 * Only 12-bits of VLAN ID are used in setting the filter.
21835 * The value of inner destination IP address to be used in filtering.
21836 * For IPv4, first four bytes represent the IP address.
21838 uint32_t l3_addr[4];
21840 * The value of tunnel destination IP address to be used in filtering.
21841 * For IPv4, first four bytes represent the IP address.
21843 uint32_t t_l3_addr[4];
21845 * This value indicates the type of inner IP address.
21848 * All others are invalid.
21850 uint8_t l3_addr_type;
21852 * This value indicates the type of tunnel IP address.
21855 * All others are invalid.
21857 uint8_t t_l3_addr_type;
21859 uint8_t tunnel_type;
21861 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21863 /* Virtual eXtensible Local Area Network (VXLAN) */
21864 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21866 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21867 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21869 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21870 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21873 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21875 /* Generic Network Virtualization Encapsulation (Geneve) */
21876 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21878 /* Multi-Protocol Lable Switching (MPLS) */
21879 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21881 /* Stateless Transport Tunnel (STT) */
21882 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21884 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21885 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21887 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21888 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21890 /* Any tunneled traffic */
21891 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21893 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21894 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21896 * tunnel_flags allows the user to indicate the tunnel tag detection
21897 * for the tunnel type specified in tunnel_type.
21899 uint8_t tunnel_flags;
21901 * If the tunnel_type is geneve, then this bit indicates if we
21902 * need to match the geneve OAM packet.
21903 * If the tunnel_type is nvgre or gre, then this bit indicates if
21904 * we need to detect checksum present bit in geneve header.
21905 * If the tunnel_type is mpls, then this bit indicates if we need
21906 * to match mpls packet with explicit IPV4/IPV6 null header.
21908 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
21911 * If the tunnel_type is geneve, then this bit indicates if we
21912 * need to detect the critical option bit set in the oam packet.
21913 * If the tunnel_type is nvgre or gre, then this bit indicates
21914 * if we need to match nvgre packets with key present bit set in
21916 * If the tunnel_type is mpls, then this bit indicates if we
21917 * need to match mpls packet with S bit from inner/second label.
21919 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
21922 * If the tunnel_type is geneve, then this bit indicates if we
21923 * need to match geneve packet with extended header bit set in
21925 * If the tunnel_type is nvgre or gre, then this bit indicates
21926 * if we need to match nvgre packets with sequence number
21927 * present bit set in gre header.
21928 * If the tunnel_type is mpls, then this bit indicates if we
21929 * need to match mpls packet with S bit from out/first label.
21931 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
21934 * Virtual Network Identifier (VNI). Only valid with
21935 * tunnel_types VXLAN, NVGRE, and Geneve.
21936 * Only lower 24-bits of VNI field are used
21937 * in setting up the filter.
21940 /* Logical VNIC ID of the destination VNIC. */
21941 uint32_t dst_vnic_id;
21943 * Logical VNIC ID of the VNIC where traffic is
21946 uint32_t mirror_vnic_id;
21947 } __attribute__((packed));
21949 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
21950 struct hwrm_cfa_tunnel_filter_alloc_output {
21951 /* The specific error status for the command. */
21952 uint16_t error_code;
21953 /* The HWRM command request type. */
21955 /* The sequence ID from the original command. */
21957 /* The length of the response data in number of bytes. */
21959 /* This value is an opaque id into CFA data structures. */
21960 uint64_t tunnel_filter_id;
21962 * This is the ID of the flow associated with this
21964 * This value shall be used to match and associate the
21965 * flow identifier returned in completion records.
21966 * A value of 0xFFFFFFFF shall indicate no flow id.
21969 uint8_t unused_0[3];
21971 * This field is used in Output records to indicate that the output
21972 * is completely written to RAM. This field should be read as '1'
21973 * to indicate that the output has been completely written.
21974 * When writing a command completion or response to an internal processor,
21975 * the order of writes has to be such that this field is written last.
21978 } __attribute__((packed));
21980 /*******************************
21981 * hwrm_cfa_tunnel_filter_free *
21982 *******************************/
21985 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
21986 struct hwrm_cfa_tunnel_filter_free_input {
21987 /* The HWRM command request type. */
21990 * The completion ring to send the completion event on. This should
21991 * be the NQ ID returned from the `nq_alloc` HWRM command.
21993 uint16_t cmpl_ring;
21995 * The sequence ID is used by the driver for tracking multiple
21996 * commands. This ID is treated as opaque data by the firmware and
21997 * the value is returned in the `hwrm_resp_hdr` upon completion.
22001 * The target ID of the command:
22002 * * 0x0-0xFFF8 - The function ID
22003 * * 0xFFF8-0xFFFE - Reserved for internal processors
22006 uint16_t target_id;
22008 * A physical address pointer pointing to a host buffer that the
22009 * command's response data will be written. This can be either a host
22010 * physical address (HPA) or a guest physical address (GPA) and must
22011 * point to a physically contiguous block of memory.
22013 uint64_t resp_addr;
22014 /* This value is an opaque id into CFA data structures. */
22015 uint64_t tunnel_filter_id;
22016 } __attribute__((packed));
22018 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
22019 struct hwrm_cfa_tunnel_filter_free_output {
22020 /* The specific error status for the command. */
22021 uint16_t error_code;
22022 /* The HWRM command request type. */
22024 /* The sequence ID from the original command. */
22026 /* The length of the response data in number of bytes. */
22028 uint8_t unused_0[7];
22030 * This field is used in Output records to indicate that the output
22031 * is completely written to RAM. This field should be read as '1'
22032 * to indicate that the output has been completely written.
22033 * When writing a command completion or response to an internal processor,
22034 * the order of writes has to be such that this field is written last.
22037 } __attribute__((packed));
22039 /***************************************
22040 * hwrm_cfa_redirect_tunnel_type_alloc *
22041 ***************************************/
22044 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
22045 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
22046 /* The HWRM command request type. */
22049 * The completion ring to send the completion event on. This should
22050 * be the NQ ID returned from the `nq_alloc` HWRM command.
22052 uint16_t cmpl_ring;
22054 * The sequence ID is used by the driver for tracking multiple
22055 * commands. This ID is treated as opaque data by the firmware and
22056 * the value is returned in the `hwrm_resp_hdr` upon completion.
22060 * The target ID of the command:
22061 * * 0x0-0xFFF8 - The function ID
22062 * * 0xFFF8-0xFFFE - Reserved for internal processors
22065 uint16_t target_id;
22067 * A physical address pointer pointing to a host buffer that the
22068 * command's response data will be written. This can be either a host
22069 * physical address (HPA) or a guest physical address (GPA) and must
22070 * point to a physically contiguous block of memory.
22072 uint64_t resp_addr;
22073 /* The destination function id, to whom the traffic is redirected. */
22076 uint8_t tunnel_type;
22078 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22080 /* Virtual eXtensible Local Area Network (VXLAN) */
22081 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22083 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22084 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22086 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22087 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22090 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22092 /* Generic Network Virtualization Encapsulation (Geneve) */
22093 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22095 /* Multi-Protocol Lable Switching (MPLS) */
22096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22098 /* Stateless Transport Tunnel (STT) */
22099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
22101 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22102 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22104 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22107 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22110 /* Any tunneled traffic */
22111 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22113 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22114 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22115 /* Tunnel alloc flags. */
22117 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
22118 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
22120 uint8_t unused_0[4];
22121 } __attribute__((packed));
22123 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
22124 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
22125 /* The specific error status for the command. */
22126 uint16_t error_code;
22127 /* The HWRM command request type. */
22129 /* The sequence ID from the original command. */
22131 /* The length of the response data in number of bytes. */
22133 uint8_t unused_0[7];
22135 * This field is used in Output records to indicate that the output
22136 * is completely written to RAM. This field should be read as '1'
22137 * to indicate that the output has been completely written.
22138 * When writing a command completion or response to an internal processor,
22139 * the order of writes has to be such that this field is written last.
22142 } __attribute__((packed));
22144 /**************************************
22145 * hwrm_cfa_redirect_tunnel_type_free *
22146 **************************************/
22149 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
22150 struct hwrm_cfa_redirect_tunnel_type_free_input {
22151 /* The HWRM command request type. */
22154 * The completion ring to send the completion event on. This should
22155 * be the NQ ID returned from the `nq_alloc` HWRM command.
22157 uint16_t cmpl_ring;
22159 * The sequence ID is used by the driver for tracking multiple
22160 * commands. This ID is treated as opaque data by the firmware and
22161 * the value is returned in the `hwrm_resp_hdr` upon completion.
22165 * The target ID of the command:
22166 * * 0x0-0xFFF8 - The function ID
22167 * * 0xFFF8-0xFFFE - Reserved for internal processors
22170 uint16_t target_id;
22172 * A physical address pointer pointing to a host buffer that the
22173 * command's response data will be written. This can be either a host
22174 * physical address (HPA) or a guest physical address (GPA) and must
22175 * point to a physically contiguous block of memory.
22177 uint64_t resp_addr;
22178 /* The destination function id, to whom the traffic is redirected. */
22181 uint8_t tunnel_type;
22183 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
22185 /* Virtual eXtensible Local Area Network (VXLAN) */
22186 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
22188 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22189 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
22191 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22192 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
22195 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
22197 /* Generic Network Virtualization Encapsulation (Geneve) */
22198 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
22200 /* Multi-Protocol Lable Switching (MPLS) */
22201 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
22203 /* Stateless Transport Tunnel (STT) */
22204 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
22206 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22207 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
22209 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22210 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22212 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22213 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22215 /* Any tunneled traffic */
22216 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22218 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
22219 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
22220 uint8_t unused_0[5];
22221 } __attribute__((packed));
22223 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
22224 struct hwrm_cfa_redirect_tunnel_type_free_output {
22225 /* The specific error status for the command. */
22226 uint16_t error_code;
22227 /* The HWRM command request type. */
22229 /* The sequence ID from the original command. */
22231 /* The length of the response data in number of bytes. */
22233 uint8_t unused_0[7];
22235 * This field is used in Output records to indicate that the output
22236 * is completely written to RAM. This field should be read as '1'
22237 * to indicate that the output has been completely written.
22238 * When writing a command completion or response to an internal processor,
22239 * the order of writes has to be such that this field is written last.
22242 } __attribute__((packed));
22244 /**************************************
22245 * hwrm_cfa_redirect_tunnel_type_info *
22246 **************************************/
22249 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
22250 struct hwrm_cfa_redirect_tunnel_type_info_input {
22251 /* The HWRM command request type. */
22254 * The completion ring to send the completion event on. This should
22255 * be the NQ ID returned from the `nq_alloc` HWRM command.
22257 uint16_t cmpl_ring;
22259 * The sequence ID is used by the driver for tracking multiple
22260 * commands. This ID is treated as opaque data by the firmware and
22261 * the value is returned in the `hwrm_resp_hdr` upon completion.
22265 * The target ID of the command:
22266 * * 0x0-0xFFF8 - The function ID
22267 * * 0xFFF8-0xFFFE - Reserved for internal processors
22270 uint16_t target_id;
22272 * A physical address pointer pointing to a host buffer that the
22273 * command's response data will be written. This can be either a host
22274 * physical address (HPA) or a guest physical address (GPA) and must
22275 * point to a physically contiguous block of memory.
22277 uint64_t resp_addr;
22278 /* The source function id. */
22281 uint8_t tunnel_type;
22283 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
22285 /* Virtual eXtensible Local Area Network (VXLAN) */
22286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
22288 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22289 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
22291 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22292 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
22295 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
22297 /* Generic Network Virtualization Encapsulation (Geneve) */
22298 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
22300 /* Multi-Protocol Lable Switching (MPLS) */
22301 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
22303 /* Stateless Transport Tunnel (STT) */
22304 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
22306 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22307 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
22309 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22310 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22312 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
22313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
22315 /* Any tunneled traffic */
22316 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22318 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
22319 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
22320 uint8_t unused_0[5];
22321 } __attribute__((packed));
22323 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
22324 struct hwrm_cfa_redirect_tunnel_type_info_output {
22325 /* The specific error status for the command. */
22326 uint16_t error_code;
22327 /* The HWRM command request type. */
22329 /* The sequence ID from the original command. */
22331 /* The length of the response data in number of bytes. */
22333 /* The destination function id, to whom the traffic is redirected. */
22335 uint8_t unused_0[5];
22337 * This field is used in Output records to indicate that the output
22338 * is completely written to RAM. This field should be read as '1'
22339 * to indicate that the output has been completely written.
22340 * When writing a command completion or response to an internal processor,
22341 * the order of writes has to be such that this field is written last.
22344 } __attribute__((packed));
22346 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
22347 struct hwrm_vxlan_ipv4_hdr {
22348 /* IPv4 version and header length. */
22350 /* IPv4 header length */
22351 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
22352 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
22354 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
22355 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
22356 /* IPv4 type of service. */
22358 /* IPv4 identification. */
22360 /* IPv4 flags and offset. */
22361 uint16_t flags_frag_offset;
22364 /* IPv4 protocol. */
22366 /* IPv4 source address. */
22367 uint32_t src_ip_addr;
22368 /* IPv4 destination address. */
22369 uint32_t dest_ip_addr;
22370 } __attribute__((packed));
22372 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
22373 struct hwrm_vxlan_ipv6_hdr {
22374 /* IPv6 version, traffic class and flow label. */
22375 uint32_t ver_tc_flow_label;
22376 /* IPv6 version shift */
22377 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
22379 /* IPv6 version mask */
22380 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
22381 UINT32_C(0xf0000000)
22382 /* IPv6 TC shift */
22383 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
22386 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
22387 UINT32_C(0xff00000)
22388 /* IPv6 flow label shift */
22389 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
22391 /* IPv6 flow label mask */
22392 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
22394 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
22395 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
22396 /* IPv6 payload length. */
22397 uint16_t payload_len;
22398 /* IPv6 next header. */
22402 /* IPv6 source address. */
22403 uint32_t src_ip_addr[4];
22404 /* IPv6 destination address. */
22405 uint32_t dest_ip_addr[4];
22406 } __attribute__((packed));
22408 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
22409 struct hwrm_cfa_encap_data_vxlan {
22410 /* Source MAC address. */
22411 uint8_t src_mac_addr[6];
22414 /* Destination MAC address. */
22415 uint8_t dst_mac_addr[6];
22416 /* Number of VLAN tags. */
22417 uint8_t num_vlan_tags;
22420 /* Outer VLAN TPID. */
22421 uint16_t ovlan_tpid;
22422 /* Outer VLAN TCI. */
22423 uint16_t ovlan_tci;
22424 /* Inner VLAN TPID. */
22425 uint16_t ivlan_tpid;
22426 /* Inner VLAN TCI. */
22427 uint16_t ivlan_tci;
22428 /* L3 header fields. */
22430 /* IP version mask. */
22431 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
22432 /* IP version 4. */
22433 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
22434 /* IP version 6. */
22435 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
22436 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
22437 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
22438 /* UDP source port. */
22440 /* UDP destination port. */
22442 /* VXLAN Network Identifier. */
22444 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
22445 uint8_t hdr_rsvd0[3];
22446 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
22448 /* VXLAN header flags field. */
22451 } __attribute__((packed));
22453 /*******************************
22454 * hwrm_cfa_encap_record_alloc *
22455 *******************************/
22458 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
22459 struct hwrm_cfa_encap_record_alloc_input {
22460 /* The HWRM command request type. */
22463 * The completion ring to send the completion event on. This should
22464 * be the NQ ID returned from the `nq_alloc` HWRM command.
22466 uint16_t cmpl_ring;
22468 * The sequence ID is used by the driver for tracking multiple
22469 * commands. This ID is treated as opaque data by the firmware and
22470 * the value is returned in the `hwrm_resp_hdr` upon completion.
22474 * The target ID of the command:
22475 * * 0x0-0xFFF8 - The function ID
22476 * * 0xFFF8-0xFFFE - Reserved for internal processors
22479 uint16_t target_id;
22481 * A physical address pointer pointing to a host buffer that the
22482 * command's response data will be written. This can be either a host
22483 * physical address (HPA) or a guest physical address (GPA) and must
22484 * point to a physically contiguous block of memory.
22486 uint64_t resp_addr;
22488 /* Setting of this flag indicates the applicability to the loopback path. */
22489 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
22491 /* Encapsulation Type. */
22492 uint8_t encap_type;
22493 /* Virtual eXtensible Local Area Network (VXLAN) */
22494 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
22496 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22497 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
22499 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
22500 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
22503 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
22505 /* Generic Network Virtualization Encapsulation (Geneve) */
22506 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
22508 /* Multi-Protocol Lable Switching (MPLS) */
22509 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
22512 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
22514 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22515 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
22517 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22518 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
22520 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
22521 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
22522 uint8_t unused_0[3];
22523 /* This value is encap data used for the given encap type. */
22524 uint32_t encap_data[20];
22525 } __attribute__((packed));
22527 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
22528 struct hwrm_cfa_encap_record_alloc_output {
22529 /* The specific error status for the command. */
22530 uint16_t error_code;
22531 /* The HWRM command request type. */
22533 /* The sequence ID from the original command. */
22535 /* The length of the response data in number of bytes. */
22537 /* This value is an opaque id into CFA data structures. */
22538 uint32_t encap_record_id;
22539 uint8_t unused_0[3];
22541 * This field is used in Output records to indicate that the output
22542 * is completely written to RAM. This field should be read as '1'
22543 * to indicate that the output has been completely written.
22544 * When writing a command completion or response to an internal processor,
22545 * the order of writes has to be such that this field is written last.
22548 } __attribute__((packed));
22550 /******************************
22551 * hwrm_cfa_encap_record_free *
22552 ******************************/
22555 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
22556 struct hwrm_cfa_encap_record_free_input {
22557 /* The HWRM command request type. */
22560 * The completion ring to send the completion event on. This should
22561 * be the NQ ID returned from the `nq_alloc` HWRM command.
22563 uint16_t cmpl_ring;
22565 * The sequence ID is used by the driver for tracking multiple
22566 * commands. This ID is treated as opaque data by the firmware and
22567 * the value is returned in the `hwrm_resp_hdr` upon completion.
22571 * The target ID of the command:
22572 * * 0x0-0xFFF8 - The function ID
22573 * * 0xFFF8-0xFFFE - Reserved for internal processors
22576 uint16_t target_id;
22578 * A physical address pointer pointing to a host buffer that the
22579 * command's response data will be written. This can be either a host
22580 * physical address (HPA) or a guest physical address (GPA) and must
22581 * point to a physically contiguous block of memory.
22583 uint64_t resp_addr;
22584 /* This value is an opaque id into CFA data structures. */
22585 uint32_t encap_record_id;
22586 uint8_t unused_0[4];
22587 } __attribute__((packed));
22589 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
22590 struct hwrm_cfa_encap_record_free_output {
22591 /* The specific error status for the command. */
22592 uint16_t error_code;
22593 /* The HWRM command request type. */
22595 /* The sequence ID from the original command. */
22597 /* The length of the response data in number of bytes. */
22599 uint8_t unused_0[7];
22601 * This field is used in Output records to indicate that the output
22602 * is completely written to RAM. This field should be read as '1'
22603 * to indicate that the output has been completely written.
22604 * When writing a command completion or response to an internal processor,
22605 * the order of writes has to be such that this field is written last.
22608 } __attribute__((packed));
22610 /********************************
22611 * hwrm_cfa_ntuple_filter_alloc *
22612 ********************************/
22615 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
22616 struct hwrm_cfa_ntuple_filter_alloc_input {
22617 /* The HWRM command request type. */
22620 * The completion ring to send the completion event on. This should
22621 * be the NQ ID returned from the `nq_alloc` HWRM command.
22623 uint16_t cmpl_ring;
22625 * The sequence ID is used by the driver for tracking multiple
22626 * commands. This ID is treated as opaque data by the firmware and
22627 * the value is returned in the `hwrm_resp_hdr` upon completion.
22631 * The target ID of the command:
22632 * * 0x0-0xFFF8 - The function ID
22633 * * 0xFFF8-0xFFFE - Reserved for internal processors
22636 uint16_t target_id;
22638 * A physical address pointer pointing to a host buffer that the
22639 * command's response data will be written. This can be either a host
22640 * physical address (HPA) or a guest physical address (GPA) and must
22641 * point to a physically contiguous block of memory.
22643 uint64_t resp_addr;
22645 /* Setting of this flag indicates the applicability to the loopback path. */
22646 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
22649 * Setting of this flag indicates drop action. If this flag is not set,
22650 * then it should be considered accept action.
22652 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
22655 * Setting of this flag indicates that a meter is expected to be attached
22656 * to this flow. This hint can be used when choosing the action record
22657 * format required for the flow.
22659 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
22663 * This bit must be '1' for the l2_filter_id field to be
22666 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
22669 * This bit must be '1' for the ethertype field to be
22672 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
22675 * This bit must be '1' for the tunnel_type field to be
22678 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
22681 * This bit must be '1' for the src_macaddr field to be
22684 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
22687 * This bit must be '1' for the ipaddr_type field to be
22690 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
22693 * This bit must be '1' for the src_ipaddr field to be
22696 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
22699 * This bit must be '1' for the src_ipaddr_mask field to be
22702 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
22705 * This bit must be '1' for the dst_ipaddr field to be
22708 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
22711 * This bit must be '1' for the dst_ipaddr_mask field to be
22714 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
22717 * This bit must be '1' for the ip_protocol field to be
22720 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
22723 * This bit must be '1' for the src_port field to be
22726 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
22729 * This bit must be '1' for the src_port_mask field to be
22732 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
22735 * This bit must be '1' for the dst_port field to be
22738 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
22741 * This bit must be '1' for the dst_port_mask field to be
22744 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
22747 * This bit must be '1' for the pri_hint field to be
22750 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
22753 * This bit must be '1' for the ntuple_filter_id field to be
22756 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
22759 * This bit must be '1' for the dst_id field to be
22762 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
22765 * This bit must be '1' for the mirror_vnic_id field to be
22768 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
22771 * This bit must be '1' for the dst_macaddr field to be
22774 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
22777 * This value identifies a set of CFA data structures used for an L2
22780 uint64_t l2_filter_id;
22782 * This value indicates the source MAC address in
22783 * the Ethernet header.
22785 uint8_t src_macaddr[6];
22786 /* This value indicates the ethertype in the Ethernet header. */
22787 uint16_t ethertype;
22789 * This value indicates the type of IP address.
22792 * All others are invalid.
22794 uint8_t ip_addr_type;
22796 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
22799 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
22802 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
22804 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
22805 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
22807 * The value of protocol filed in IP header.
22808 * Applies to UDP and TCP traffic.
22812 uint8_t ip_protocol;
22814 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
22817 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
22820 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
22822 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
22823 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
22825 * If set, this value shall represent the
22826 * Logical VNIC ID of the destination VNIC for the RX
22827 * path and network port id of the destination port for
22832 * Logical VNIC ID of the VNIC where traffic is
22835 uint16_t mirror_vnic_id;
22837 * This value indicates the tunnel type for this filter.
22838 * If this field is not specified, then the filter shall
22839 * apply to both non-tunneled and tunneled packets.
22840 * If this field conflicts with the tunnel_type specified
22841 * in the l2_filter_id, then the HWRM shall return an
22842 * error for this command.
22844 uint8_t tunnel_type;
22846 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22848 /* Virtual eXtensible Local Area Network (VXLAN) */
22849 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22851 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22852 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22854 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22858 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22860 /* Generic Network Virtualization Encapsulation (Geneve) */
22861 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22863 /* Multi-Protocol Lable Switching (MPLS) */
22864 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22866 /* Stateless Transport Tunnel (STT) */
22867 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
22869 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22870 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22872 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22875 /* Any tunneled traffic */
22876 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22878 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22879 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22881 * This hint is provided to help in placing
22882 * the filter in the filter table.
22885 /* No preference */
22886 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
22888 /* Above the given filter */
22889 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
22891 /* Below the given filter */
22892 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
22894 /* As high as possible */
22895 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
22897 /* As low as possible */
22898 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
22900 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
22901 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
22903 * The value of source IP address to be used in filtering.
22904 * For IPv4, first four bytes represent the IP address.
22906 uint32_t src_ipaddr[4];
22908 * The value of source IP address mask to be used in
22910 * For IPv4, first four bytes represent the IP address mask.
22912 uint32_t src_ipaddr_mask[4];
22914 * The value of destination IP address to be used in filtering.
22915 * For IPv4, first four bytes represent the IP address.
22917 uint32_t dst_ipaddr[4];
22919 * The value of destination IP address mask to be used in
22921 * For IPv4, first four bytes represent the IP address mask.
22923 uint32_t dst_ipaddr_mask[4];
22925 * The value of source port to be used in filtering.
22926 * Applies to UDP and TCP traffic.
22930 * The value of source port mask to be used in filtering.
22931 * Applies to UDP and TCP traffic.
22933 uint16_t src_port_mask;
22935 * The value of destination port to be used in filtering.
22936 * Applies to UDP and TCP traffic.
22940 * The value of destination port mask to be used in
22942 * Applies to UDP and TCP traffic.
22944 uint16_t dst_port_mask;
22946 * This is the ID of the filter that goes along with
22949 uint64_t ntuple_filter_id_hint;
22950 } __attribute__((packed));
22952 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
22953 struct hwrm_cfa_ntuple_filter_alloc_output {
22954 /* The specific error status for the command. */
22955 uint16_t error_code;
22956 /* The HWRM command request type. */
22958 /* The sequence ID from the original command. */
22960 /* The length of the response data in number of bytes. */
22962 /* This value is an opaque id into CFA data structures. */
22963 uint64_t ntuple_filter_id;
22965 * This is the ID of the flow associated with this
22967 * This value shall be used to match and associate the
22968 * flow identifier returned in completion records.
22969 * A value of 0xFFFFFFFF shall indicate no flow id.
22972 uint8_t unused_0[3];
22974 * This field is used in Output records to indicate that the output
22975 * is completely written to RAM. This field should be read as '1'
22976 * to indicate that the output has been completely written.
22977 * When writing a command completion or response to an internal processor,
22978 * the order of writes has to be such that this field is written last.
22981 } __attribute__((packed));
22983 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
22984 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
22986 * command specific error codes that goes to
22987 * the cmd_err field in Common HWRM Error Response.
22990 /* Unknown error */
22991 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
22993 /* Unable to complete operation due to conflict with Rx Mask VLAN */
22994 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
22996 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
22997 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
22998 uint8_t unused_0[7];
22999 } __attribute__((packed));
23001 /*******************************
23002 * hwrm_cfa_ntuple_filter_free *
23003 *******************************/
23006 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
23007 struct hwrm_cfa_ntuple_filter_free_input {
23008 /* The HWRM command request type. */
23011 * The completion ring to send the completion event on. This should
23012 * be the NQ ID returned from the `nq_alloc` HWRM command.
23014 uint16_t cmpl_ring;
23016 * The sequence ID is used by the driver for tracking multiple
23017 * commands. This ID is treated as opaque data by the firmware and
23018 * the value is returned in the `hwrm_resp_hdr` upon completion.
23022 * The target ID of the command:
23023 * * 0x0-0xFFF8 - The function ID
23024 * * 0xFFF8-0xFFFE - Reserved for internal processors
23027 uint16_t target_id;
23029 * A physical address pointer pointing to a host buffer that the
23030 * command's response data will be written. This can be either a host
23031 * physical address (HPA) or a guest physical address (GPA) and must
23032 * point to a physically contiguous block of memory.
23034 uint64_t resp_addr;
23035 /* This value is an opaque id into CFA data structures. */
23036 uint64_t ntuple_filter_id;
23037 } __attribute__((packed));
23039 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
23040 struct hwrm_cfa_ntuple_filter_free_output {
23041 /* The specific error status for the command. */
23042 uint16_t error_code;
23043 /* The HWRM command request type. */
23045 /* The sequence ID from the original command. */
23047 /* The length of the response data in number of bytes. */
23049 uint8_t unused_0[7];
23051 * This field is used in Output records to indicate that the output
23052 * is completely written to RAM. This field should be read as '1'
23053 * to indicate that the output has been completely written.
23054 * When writing a command completion or response to an internal processor,
23055 * the order of writes has to be such that this field is written last.
23058 } __attribute__((packed));
23060 /******************************
23061 * hwrm_cfa_ntuple_filter_cfg *
23062 ******************************/
23065 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
23066 struct hwrm_cfa_ntuple_filter_cfg_input {
23067 /* The HWRM command request type. */
23070 * The completion ring to send the completion event on. This should
23071 * be the NQ ID returned from the `nq_alloc` HWRM command.
23073 uint16_t cmpl_ring;
23075 * The sequence ID is used by the driver for tracking multiple
23076 * commands. This ID is treated as opaque data by the firmware and
23077 * the value is returned in the `hwrm_resp_hdr` upon completion.
23081 * The target ID of the command:
23082 * * 0x0-0xFFF8 - The function ID
23083 * * 0xFFF8-0xFFFE - Reserved for internal processors
23086 uint16_t target_id;
23088 * A physical address pointer pointing to a host buffer that the
23089 * command's response data will be written. This can be either a host
23090 * physical address (HPA) or a guest physical address (GPA) and must
23091 * point to a physically contiguous block of memory.
23093 uint64_t resp_addr;
23096 * This bit must be '1' for the new_dst_id field to be
23099 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
23102 * This bit must be '1' for the new_mirror_vnic_id field to be
23105 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
23108 * This bit must be '1' for the new_meter_instance_id field to be
23111 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
23113 uint8_t unused_0[4];
23114 /* This value is an opaque id into CFA data structures. */
23115 uint64_t ntuple_filter_id;
23117 * If set, this value shall represent the new
23118 * Logical VNIC ID of the destination VNIC for the RX
23119 * path and new network port id of the destination port for
23122 uint32_t new_dst_id;
23124 * New Logical VNIC ID of the VNIC where traffic is
23127 uint32_t new_mirror_vnic_id;
23129 * New meter to attach to the flow. Specifying the
23130 * invalid instance ID is used to remove any existing
23131 * meter from the flow.
23133 uint16_t new_meter_instance_id;
23135 * A value of 0xfff is considered invalid and implies the
23136 * instance is not configured.
23138 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
23140 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
23141 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
23142 uint8_t unused_1[6];
23143 } __attribute__((packed));
23145 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
23146 struct hwrm_cfa_ntuple_filter_cfg_output {
23147 /* The specific error status for the command. */
23148 uint16_t error_code;
23149 /* The HWRM command request type. */
23151 /* The sequence ID from the original command. */
23153 /* The length of the response data in number of bytes. */
23155 uint8_t unused_0[7];
23157 * This field is used in Output records to indicate that the output
23158 * is completely written to RAM. This field should be read as '1'
23159 * to indicate that the output has been completely written.
23160 * When writing a command completion or response to an internal processor,
23161 * the order of writes has to be such that this field is written last.
23164 } __attribute__((packed));
23166 /**************************
23167 * hwrm_cfa_em_flow_alloc *
23168 **************************/
23171 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
23172 struct hwrm_cfa_em_flow_alloc_input {
23173 /* The HWRM command request type. */
23176 * The completion ring to send the completion event on. This should
23177 * be the NQ ID returned from the `nq_alloc` HWRM command.
23179 uint16_t cmpl_ring;
23181 * The sequence ID is used by the driver for tracking multiple
23182 * commands. This ID is treated as opaque data by the firmware and
23183 * the value is returned in the `hwrm_resp_hdr` upon completion.
23187 * The target ID of the command:
23188 * * 0x0-0xFFF8 - The function ID
23189 * * 0xFFF8-0xFFFE - Reserved for internal processors
23192 uint16_t target_id;
23194 * A physical address pointer pointing to a host buffer that the
23195 * command's response data will be written. This can be either a host
23196 * physical address (HPA) or a guest physical address (GPA) and must
23197 * point to a physically contiguous block of memory.
23199 uint64_t resp_addr;
23202 * Enumeration denoting the RX, TX type of the resource.
23203 * This enumeration is used for resources that are similar for both
23204 * TX and RX paths of the chip.
23206 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
23208 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
23210 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
23211 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
23212 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
23214 * Setting of this flag indicates enabling of a byte counter for a given
23217 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
23219 * Setting of this flag indicates enabling of a packet counter for a given
23222 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
23223 /* Setting of this flag indicates de-capsulation action for the given flow. */
23224 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
23225 /* Setting of this flag indicates encapsulation action for the given flow. */
23226 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
23228 * Setting of this flag indicates drop action. If this flag is not set,
23229 * then it should be considered accept action.
23231 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
23233 * Setting of this flag indicates that a meter is expected to be attached
23234 * to this flow. This hint can be used when choosing the action record
23235 * format required for the flow.
23237 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
23240 * This bit must be '1' for the l2_filter_id field to be
23243 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
23246 * This bit must be '1' for the tunnel_type field to be
23249 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23252 * This bit must be '1' for the tunnel_id field to be
23255 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
23258 * This bit must be '1' for the src_macaddr field to be
23261 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23264 * This bit must be '1' for the dst_macaddr field to be
23267 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
23270 * This bit must be '1' for the ovlan_vid field to be
23273 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
23276 * This bit must be '1' for the ivlan_vid field to be
23279 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
23282 * This bit must be '1' for the ethertype field to be
23285 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
23288 * This bit must be '1' for the src_ipaddr field to be
23291 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23294 * This bit must be '1' for the dst_ipaddr field to be
23297 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
23300 * This bit must be '1' for the ipaddr_type field to be
23303 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23306 * This bit must be '1' for the ip_protocol field to be
23309 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23312 * This bit must be '1' for the src_port field to be
23315 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
23318 * This bit must be '1' for the dst_port field to be
23321 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
23324 * This bit must be '1' for the dst_id field to be
23327 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
23330 * This bit must be '1' for the mirror_vnic_id field to be
23333 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23336 * This bit must be '1' for the encap_record_id field to be
23339 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
23342 * This bit must be '1' for the meter_instance_id field to be
23345 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
23348 * This value identifies a set of CFA data structures used for an L2
23351 uint64_t l2_filter_id;
23353 uint8_t tunnel_type;
23355 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23357 /* Virtual eXtensible Local Area Network (VXLAN) */
23358 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23360 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23361 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23363 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23364 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23367 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23369 /* Generic Network Virtualization Encapsulation (Geneve) */
23370 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23372 /* Multi-Protocol Lable Switching (MPLS) */
23373 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23375 /* Stateless Transport Tunnel (STT) */
23376 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
23378 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23379 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23381 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23382 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23384 /* Any tunneled traffic */
23385 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23387 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23388 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23389 uint8_t unused_0[3];
23391 * Tunnel identifier.
23392 * Virtual Network Identifier (VNI). Only valid with
23393 * tunnel_types VXLAN, NVGRE, and Geneve.
23394 * Only lower 24-bits of VNI field are used
23395 * in setting up the filter.
23397 uint32_t tunnel_id;
23399 * This value indicates the source MAC address in
23400 * the Ethernet header.
23402 uint8_t src_macaddr[6];
23403 /* The meter instance to attach to the flow. */
23404 uint16_t meter_instance_id;
23406 * A value of 0xfff is considered invalid and implies the
23407 * instance is not configured.
23409 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
23411 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
23412 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
23414 * This value indicates the destination MAC address in
23415 * the Ethernet header.
23417 uint8_t dst_macaddr[6];
23419 * This value indicates the VLAN ID of the outer VLAN tag
23420 * in the Ethernet header.
23422 uint16_t ovlan_vid;
23424 * This value indicates the VLAN ID of the inner VLAN tag
23425 * in the Ethernet header.
23427 uint16_t ivlan_vid;
23428 /* This value indicates the ethertype in the Ethernet header. */
23429 uint16_t ethertype;
23431 * This value indicates the type of IP address.
23434 * All others are invalid.
23436 uint8_t ip_addr_type;
23438 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
23440 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
23442 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
23443 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23444 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23446 * The value of protocol filed in IP header.
23447 * Applies to UDP and TCP traffic.
23451 uint8_t ip_protocol;
23453 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
23455 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
23457 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
23458 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
23459 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
23460 uint8_t unused_1[2];
23462 * The value of source IP address to be used in filtering.
23463 * For IPv4, first four bytes represent the IP address.
23465 uint32_t src_ipaddr[4];
23467 * big_endian = True
23468 * The value of destination IP address to be used in filtering.
23469 * For IPv4, first four bytes represent the IP address.
23471 uint32_t dst_ipaddr[4];
23473 * The value of source port to be used in filtering.
23474 * Applies to UDP and TCP traffic.
23478 * The value of destination port to be used in filtering.
23479 * Applies to UDP and TCP traffic.
23483 * If set, this value shall represent the
23484 * Logical VNIC ID of the destination VNIC for the RX
23485 * path and network port id of the destination port for
23490 * Logical VNIC ID of the VNIC where traffic is
23493 uint16_t mirror_vnic_id;
23494 /* Logical ID of the encapsulation record. */
23495 uint32_t encap_record_id;
23496 uint8_t unused_2[4];
23497 } __attribute__((packed));
23499 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
23500 struct hwrm_cfa_em_flow_alloc_output {
23501 /* The specific error status for the command. */
23502 uint16_t error_code;
23503 /* The HWRM command request type. */
23505 /* The sequence ID from the original command. */
23507 /* The length of the response data in number of bytes. */
23509 /* This value is an opaque id into CFA data structures. */
23510 uint64_t em_filter_id;
23512 * This is the ID of the flow associated with this
23514 * This value shall be used to match and associate the
23515 * flow identifier returned in completion records.
23516 * A value of 0xFFFFFFFF shall indicate no flow id.
23519 uint8_t unused_0[3];
23521 * This field is used in Output records to indicate that the output
23522 * is completely written to RAM. This field should be read as '1'
23523 * to indicate that the output has been completely written.
23524 * When writing a command completion or response to an internal processor,
23525 * the order of writes has to be such that this field is written last.
23528 } __attribute__((packed));
23530 /*************************
23531 * hwrm_cfa_em_flow_free *
23532 *************************/
23535 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
23536 struct hwrm_cfa_em_flow_free_input {
23537 /* The HWRM command request type. */
23540 * The completion ring to send the completion event on. This should
23541 * be the NQ ID returned from the `nq_alloc` HWRM command.
23543 uint16_t cmpl_ring;
23545 * The sequence ID is used by the driver for tracking multiple
23546 * commands. This ID is treated as opaque data by the firmware and
23547 * the value is returned in the `hwrm_resp_hdr` upon completion.
23551 * The target ID of the command:
23552 * * 0x0-0xFFF8 - The function ID
23553 * * 0xFFF8-0xFFFE - Reserved for internal processors
23556 uint16_t target_id;
23558 * A physical address pointer pointing to a host buffer that the
23559 * command's response data will be written. This can be either a host
23560 * physical address (HPA) or a guest physical address (GPA) and must
23561 * point to a physically contiguous block of memory.
23563 uint64_t resp_addr;
23564 /* This value is an opaque id into CFA data structures. */
23565 uint64_t em_filter_id;
23566 } __attribute__((packed));
23568 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
23569 struct hwrm_cfa_em_flow_free_output {
23570 /* The specific error status for the command. */
23571 uint16_t error_code;
23572 /* The HWRM command request type. */
23574 /* The sequence ID from the original command. */
23576 /* The length of the response data in number of bytes. */
23578 uint8_t unused_0[7];
23580 * This field is used in Output records to indicate that the output
23581 * is completely written to RAM. This field should be read as '1'
23582 * to indicate that the output has been completely written.
23583 * When writing a command completion or response to an internal processor,
23584 * the order of writes has to be such that this field is written last.
23587 } __attribute__((packed));
23589 /*******************************
23590 * hwrm_cfa_decap_filter_alloc *
23591 *******************************/
23594 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
23595 struct hwrm_cfa_decap_filter_alloc_input {
23596 /* The HWRM command request type. */
23599 * The completion ring to send the completion event on. This should
23600 * be the NQ ID returned from the `nq_alloc` HWRM command.
23602 uint16_t cmpl_ring;
23604 * The sequence ID is used by the driver for tracking multiple
23605 * commands. This ID is treated as opaque data by the firmware and
23606 * the value is returned in the `hwrm_resp_hdr` upon completion.
23610 * The target ID of the command:
23611 * * 0x0-0xFFF8 - The function ID
23612 * * 0xFFF8-0xFFFE - Reserved for internal processors
23615 uint16_t target_id;
23617 * A physical address pointer pointing to a host buffer that the
23618 * command's response data will be written. This can be either a host
23619 * physical address (HPA) or a guest physical address (GPA) and must
23620 * point to a physically contiguous block of memory.
23622 uint64_t resp_addr;
23624 /* ovs_tunnel is 1 b */
23625 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
23629 * This bit must be '1' for the tunnel_type field to be
23632 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23635 * This bit must be '1' for the tunnel_id field to be
23638 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
23641 * This bit must be '1' for the src_macaddr field to be
23644 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23647 * This bit must be '1' for the dst_macaddr field to be
23650 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
23653 * This bit must be '1' for the ovlan_vid field to be
23656 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
23659 * This bit must be '1' for the ivlan_vid field to be
23662 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
23665 * This bit must be '1' for the t_ovlan_vid field to be
23668 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
23671 * This bit must be '1' for the t_ivlan_vid field to be
23674 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
23677 * This bit must be '1' for the ethertype field to be
23680 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
23683 * This bit must be '1' for the src_ipaddr field to be
23686 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23689 * This bit must be '1' for the dst_ipaddr field to be
23692 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
23695 * This bit must be '1' for the ipaddr_type field to be
23698 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23701 * This bit must be '1' for the ip_protocol field to be
23704 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23707 * This bit must be '1' for the src_port field to be
23710 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
23713 * This bit must be '1' for the dst_port field to be
23716 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
23719 * This bit must be '1' for the dst_id field to be
23722 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23725 * This bit must be '1' for the mirror_vnic_id field to be
23728 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23731 * Tunnel identifier.
23732 * Virtual Network Identifier (VNI). Only valid with
23733 * tunnel_types VXLAN, NVGRE, and Geneve.
23734 * Only lower 24-bits of VNI field are used
23735 * in setting up the filter.
23737 uint32_t tunnel_id;
23739 uint8_t tunnel_type;
23741 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23743 /* Virtual eXtensible Local Area Network (VXLAN) */
23744 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23746 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23747 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23749 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23750 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23753 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23755 /* Generic Network Virtualization Encapsulation (Geneve) */
23756 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23758 /* Multi-Protocol Lable Switching (MPLS) */
23759 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23761 /* Stateless Transport Tunnel (STT) */
23762 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23764 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23765 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23767 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23768 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23770 /* Any tunneled traffic */
23771 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23773 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23774 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23778 * This value indicates the source MAC address in
23779 * the Ethernet header.
23781 uint8_t src_macaddr[6];
23782 uint8_t unused_2[2];
23784 * This value indicates the destination MAC address in
23785 * the Ethernet header.
23787 uint8_t dst_macaddr[6];
23789 * This value indicates the VLAN ID of the outer VLAN tag
23790 * in the Ethernet header.
23792 uint16_t ovlan_vid;
23794 * This value indicates the VLAN ID of the inner VLAN tag
23795 * in the Ethernet header.
23797 uint16_t ivlan_vid;
23799 * This value indicates the VLAN ID of the outer VLAN tag
23800 * in the tunnel Ethernet header.
23802 uint16_t t_ovlan_vid;
23804 * This value indicates the VLAN ID of the inner VLAN tag
23805 * in the tunnel Ethernet header.
23807 uint16_t t_ivlan_vid;
23808 /* This value indicates the ethertype in the Ethernet header. */
23809 uint16_t ethertype;
23811 * This value indicates the type of IP address.
23814 * All others are invalid.
23816 uint8_t ip_addr_type;
23818 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
23821 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
23824 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
23826 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23827 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23829 * The value of protocol filed in IP header.
23830 * Applies to UDP and TCP traffic.
23834 uint8_t ip_protocol;
23836 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
23839 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
23842 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
23844 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
23845 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
23849 * The value of source IP address to be used in filtering.
23850 * For IPv4, first four bytes represent the IP address.
23852 uint32_t src_ipaddr[4];
23854 * The value of destination IP address to be used in filtering.
23855 * For IPv4, first four bytes represent the IP address.
23857 uint32_t dst_ipaddr[4];
23859 * The value of source port to be used in filtering.
23860 * Applies to UDP and TCP traffic.
23864 * The value of destination port to be used in filtering.
23865 * Applies to UDP and TCP traffic.
23869 * If set, this value shall represent the
23870 * Logical VNIC ID of the destination VNIC for the RX
23875 * If set, this value shall represent the L2 context that matches the L2
23876 * information of the decap filter.
23878 uint16_t l2_ctxt_ref_id;
23879 } __attribute__((packed));
23881 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
23882 struct hwrm_cfa_decap_filter_alloc_output {
23883 /* The specific error status for the command. */
23884 uint16_t error_code;
23885 /* The HWRM command request type. */
23887 /* The sequence ID from the original command. */
23889 /* The length of the response data in number of bytes. */
23891 /* This value is an opaque id into CFA data structures. */
23892 uint32_t decap_filter_id;
23893 uint8_t unused_0[3];
23895 * This field is used in Output records to indicate that the output
23896 * is completely written to RAM. This field should be read as '1'
23897 * to indicate that the output has been completely written.
23898 * When writing a command completion or response to an internal processor,
23899 * the order of writes has to be such that this field is written last.
23902 } __attribute__((packed));
23904 /******************************
23905 * hwrm_cfa_decap_filter_free *
23906 ******************************/
23909 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
23910 struct hwrm_cfa_decap_filter_free_input {
23911 /* The HWRM command request type. */
23914 * The completion ring to send the completion event on. This should
23915 * be the NQ ID returned from the `nq_alloc` HWRM command.
23917 uint16_t cmpl_ring;
23919 * The sequence ID is used by the driver for tracking multiple
23920 * commands. This ID is treated as opaque data by the firmware and
23921 * the value is returned in the `hwrm_resp_hdr` upon completion.
23925 * The target ID of the command:
23926 * * 0x0-0xFFF8 - The function ID
23927 * * 0xFFF8-0xFFFE - Reserved for internal processors
23930 uint16_t target_id;
23932 * A physical address pointer pointing to a host buffer that the
23933 * command's response data will be written. This can be either a host
23934 * physical address (HPA) or a guest physical address (GPA) and must
23935 * point to a physically contiguous block of memory.
23937 uint64_t resp_addr;
23938 /* This value is an opaque id into CFA data structures. */
23939 uint32_t decap_filter_id;
23940 uint8_t unused_0[4];
23941 } __attribute__((packed));
23943 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
23944 struct hwrm_cfa_decap_filter_free_output {
23945 /* The specific error status for the command. */
23946 uint16_t error_code;
23947 /* The HWRM command request type. */
23949 /* The sequence ID from the original command. */
23951 /* The length of the response data in number of bytes. */
23953 uint8_t unused_0[7];
23955 * This field is used in Output records to indicate that the output
23956 * is completely written to RAM. This field should be read as '1'
23957 * to indicate that the output has been completely written.
23958 * When writing a command completion or response to an internal processor,
23959 * the order of writes has to be such that this field is written last.
23962 } __attribute__((packed));
23964 /***********************
23965 * hwrm_cfa_flow_alloc *
23966 ***********************/
23969 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
23970 struct hwrm_cfa_flow_alloc_input {
23971 /* The HWRM command request type. */
23974 * The completion ring to send the completion event on. This should
23975 * be the NQ ID returned from the `nq_alloc` HWRM command.
23977 uint16_t cmpl_ring;
23979 * The sequence ID is used by the driver for tracking multiple
23980 * commands. This ID is treated as opaque data by the firmware and
23981 * the value is returned in the `hwrm_resp_hdr` upon completion.
23985 * The target ID of the command:
23986 * * 0x0-0xFFF8 - The function ID
23987 * * 0xFFF8-0xFFFE - Reserved for internal processors
23990 uint16_t target_id;
23992 * A physical address pointer pointing to a host buffer that the
23993 * command's response data will be written. This can be either a host
23994 * physical address (HPA) or a guest physical address (GPA) and must
23995 * point to a physically contiguous block of memory.
23997 uint64_t resp_addr;
23999 /* tunnel is 1 b */
24000 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
24002 /* num_vlan is 2 b */
24003 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
24005 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
24007 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
24008 (UINT32_C(0x0) << 1)
24010 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
24011 (UINT32_C(0x1) << 1)
24013 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
24014 (UINT32_C(0x2) << 1)
24015 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
24016 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
24017 /* Enumeration denoting the Flow Type. */
24018 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
24020 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
24022 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
24023 (UINT32_C(0x0) << 3)
24025 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
24026 (UINT32_C(0x1) << 3)
24028 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
24029 (UINT32_C(0x2) << 3)
24030 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
24031 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
24033 * when set to 1, indicates TX flow offload for function specified in src_fid and
24034 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
24035 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
24036 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
24037 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
24038 * belong to the children VFs of the same PF to indicate VM to VM flow.
24040 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
24043 * when set to 1, indicates RX flow offload for function specified in dst_fid and
24044 * the src_fid should be set to invalid value.
24046 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
24049 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
24050 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
24051 * This flag is only valid when the flow direction is RX.
24053 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
24060 /* Tunnel handle valid when tunnel flag is set. */
24061 uint32_t tunnel_handle;
24062 uint16_t action_flags;
24064 * Setting of this flag indicates drop action. If this flag is not set,
24065 * then it should be considered accept action.
24067 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
24069 /* recycle is 1 b */
24070 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
24073 * Setting of this flag indicates drop action. If this flag is not set,
24074 * then it should be considered accept action.
24076 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
24079 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
24081 /* tunnel is 1 b */
24082 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
24084 /* nat_src is 1 b */
24085 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
24087 /* nat_dest is 1 b */
24088 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
24090 /* nat_ipv4_address is 1 b */
24091 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
24093 /* l2_header_rewrite is 1 b */
24094 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
24096 /* ttl_decrement is 1 b */
24097 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
24100 * If set to 1 and flow direction is TX, it indicates decap of L2 header
24101 * and encap of tunnel header. If set to 1 and flow direction is RX, it
24102 * indicates decap of tunnel header and encap L2 header. The type of tunnel
24103 * is specified in the tunnel_type field.
24105 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
24108 * Tx Flow: pf or vf fid.
24112 /* VLAN tpid, valid when push_vlan flag is set. */
24113 uint16_t l2_rewrite_vlan_tpid;
24114 /* VLAN tci, valid when push_vlan flag is set. */
24115 uint16_t l2_rewrite_vlan_tci;
24116 /* Meter id, valid when meter flag is set. */
24117 uint16_t act_meter_id;
24118 /* Flow with the same l2 context tcam key. */
24119 uint16_t ref_flow_handle;
24120 /* This value sets the match value for the ethertype. */
24121 uint16_t ethertype;
24122 /* valid when num tags is 1 or 2. */
24123 uint16_t outer_vlan_tci;
24124 /* This value sets the match value for the Destination MAC address. */
24126 /* valid when num tags is 2. */
24127 uint16_t inner_vlan_tci;
24128 /* This value sets the match value for the Source MAC address. */
24130 /* The bit length of destination IP address mask. */
24131 uint8_t ip_dst_mask_len;
24132 /* The bit length of source IP address mask. */
24133 uint8_t ip_src_mask_len;
24134 /* The value of destination IPv4/IPv6 address. */
24135 uint32_t ip_dst[4];
24136 /* The source IPv4/IPv6 address. */
24137 uint32_t ip_src[4];
24139 * The value of source port.
24140 * Applies to UDP and TCP traffic.
24142 uint16_t l4_src_port;
24144 * The value of source port mask.
24145 * Applies to UDP and TCP traffic.
24147 uint16_t l4_src_port_mask;
24149 * The value of destination port.
24150 * Applies to UDP and TCP traffic.
24152 uint16_t l4_dst_port;
24154 * The value of destination port mask.
24155 * Applies to UDP and TCP traffic.
24157 uint16_t l4_dst_port_mask;
24159 * NAT IPv4/6 address based on address type flag.
24160 * 0 values are ignored.
24162 uint32_t nat_ip_address[4];
24163 /* L2 header re-write Destination MAC address. */
24164 uint16_t l2_rewrite_dmac[3];
24166 * The NAT source/destination port based on direction flag.
24167 * Applies to UDP and TCP traffic.
24168 * 0 values are ignored.
24171 /* L2 header re-write Source MAC address. */
24172 uint16_t l2_rewrite_smac[3];
24173 /* The value of ip protocol. */
24176 uint8_t tunnel_type;
24178 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
24179 /* Virtual eXtensible Local Area Network (VXLAN) */
24180 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
24181 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24182 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
24183 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24184 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
24186 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
24187 /* Generic Network Virtualization Encapsulation (Geneve) */
24188 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
24189 /* Multi-Protocol Lable Switching (MPLS) */
24190 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
24191 /* Stateless Transport Tunnel (STT) */
24192 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
24193 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24194 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
24195 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24196 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
24197 /* Any tunneled traffic */
24198 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
24199 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24200 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
24201 } __attribute__((packed));
24203 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
24204 struct hwrm_cfa_flow_alloc_output {
24205 /* The specific error status for the command. */
24206 uint16_t error_code;
24207 /* The HWRM command request type. */
24209 /* The sequence ID from the original command. */
24211 /* The length of the response data in number of bytes. */
24213 /* Flow record index. */
24214 uint16_t flow_handle;
24215 uint8_t unused_0[2];
24217 * This is the ID of the flow associated with this
24219 * This value shall be used to match and associate the
24220 * flow identifier returned in completion records.
24221 * A value of 0xFFFFFFFF shall indicate no flow id.
24224 /* This value identifies a set of CFA data structures used for a flow. */
24225 uint64_t ext_flow_handle;
24226 uint8_t unused_1[7];
24228 * This field is used in Output records to indicate that the output
24229 * is completely written to RAM. This field should be read as '1'
24230 * to indicate that the output has been completely written.
24231 * When writing a command completion or response to an internal processor,
24232 * the order of writes has to be such that this field is written last.
24235 } __attribute__((packed));
24237 /**********************
24238 * hwrm_cfa_flow_free *
24239 **********************/
24242 /* hwrm_cfa_flow_free_input (size:256b/32B) */
24243 struct hwrm_cfa_flow_free_input {
24244 /* The HWRM command request type. */
24247 * The completion ring to send the completion event on. This should
24248 * be the NQ ID returned from the `nq_alloc` HWRM command.
24250 uint16_t cmpl_ring;
24252 * The sequence ID is used by the driver for tracking multiple
24253 * commands. This ID is treated as opaque data by the firmware and
24254 * the value is returned in the `hwrm_resp_hdr` upon completion.
24258 * The target ID of the command:
24259 * * 0x0-0xFFF8 - The function ID
24260 * * 0xFFF8-0xFFFE - Reserved for internal processors
24263 uint16_t target_id;
24265 * A physical address pointer pointing to a host buffer that the
24266 * command's response data will be written. This can be either a host
24267 * physical address (HPA) or a guest physical address (GPA) and must
24268 * point to a physically contiguous block of memory.
24270 uint64_t resp_addr;
24271 /* Flow record index. */
24272 uint16_t flow_handle;
24273 uint8_t unused_0[6];
24274 /* This value identifies a set of CFA data structures used for a flow. */
24275 uint64_t ext_flow_handle;
24276 } __attribute__((packed));
24278 /* hwrm_cfa_flow_free_output (size:256b/32B) */
24279 struct hwrm_cfa_flow_free_output {
24280 /* The specific error status for the command. */
24281 uint16_t error_code;
24282 /* The HWRM command request type. */
24284 /* The sequence ID from the original command. */
24286 /* The length of the response data in number of bytes. */
24288 /* packet is 64 b */
24292 uint8_t unused_0[7];
24294 * This field is used in Output records to indicate that the output
24295 * is completely written to RAM. This field should be read as '1'
24296 * to indicate that the output has been completely written.
24297 * When writing a command completion or response to an internal processor,
24298 * the order of writes has to be such that this field is written last.
24301 } __attribute__((packed));
24303 /***********************
24304 * hwrm_cfa_flow_flush *
24305 ***********************/
24308 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
24309 struct hwrm_cfa_flow_flush_input {
24310 /* The HWRM command request type. */
24313 * The completion ring to send the completion event on. This should
24314 * be the NQ ID returned from the `nq_alloc` HWRM command.
24316 uint16_t cmpl_ring;
24318 * The sequence ID is used by the driver for tracking multiple
24319 * commands. This ID is treated as opaque data by the firmware and
24320 * the value is returned in the `hwrm_resp_hdr` upon completion.
24324 * The target ID of the command:
24325 * * 0x0-0xFFF8 - The function ID
24326 * * 0xFFF8-0xFFFE - Reserved for internal processors
24329 uint16_t target_id;
24331 * A physical address pointer pointing to a host buffer that the
24332 * command's response data will be written. This can be either a host
24333 * physical address (HPA) or a guest physical address (GPA) and must
24334 * point to a physically contiguous block of memory.
24336 uint64_t resp_addr;
24338 uint8_t unused_0[4];
24339 } __attribute__((packed));
24341 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
24342 struct hwrm_cfa_flow_flush_output {
24343 /* The specific error status for the command. */
24344 uint16_t error_code;
24345 /* The HWRM command request type. */
24347 /* The sequence ID from the original command. */
24349 /* The length of the response data in number of bytes. */
24351 uint8_t unused_0[7];
24353 * This field is used in Output records to indicate that the output
24354 * is completely written to RAM. This field should be read as '1'
24355 * to indicate that the output has been completely written.
24356 * When writing a command completion or response to an internal processor,
24357 * the order of writes has to be such that this field is written last.
24360 } __attribute__((packed));
24362 /***********************
24363 * hwrm_cfa_flow_stats *
24364 ***********************/
24367 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
24368 struct hwrm_cfa_flow_stats_input {
24369 /* The HWRM command request type. */
24372 * The completion ring to send the completion event on. This should
24373 * be the NQ ID returned from the `nq_alloc` HWRM command.
24375 uint16_t cmpl_ring;
24377 * The sequence ID is used by the driver for tracking multiple
24378 * commands. This ID is treated as opaque data by the firmware and
24379 * the value is returned in the `hwrm_resp_hdr` upon completion.
24383 * The target ID of the command:
24384 * * 0x0-0xFFF8 - The function ID
24385 * * 0xFFF8-0xFFFE - Reserved for internal processors
24388 uint16_t target_id;
24390 * A physical address pointer pointing to a host buffer that the
24391 * command's response data will be written. This can be either a host
24392 * physical address (HPA) or a guest physical address (GPA) and must
24393 * point to a physically contiguous block of memory.
24395 uint64_t resp_addr;
24397 uint16_t num_flows;
24399 uint16_t flow_handle_0;
24401 uint16_t flow_handle_1;
24403 uint16_t flow_handle_2;
24405 uint16_t flow_handle_3;
24407 uint16_t flow_handle_4;
24409 uint16_t flow_handle_5;
24411 uint16_t flow_handle_6;
24413 uint16_t flow_handle_7;
24415 uint16_t flow_handle_8;
24417 uint16_t flow_handle_9;
24418 uint8_t unused_0[2];
24419 /* Flow ID of a flow. */
24420 uint32_t flow_id_0;
24421 /* Flow ID of a flow. */
24422 uint32_t flow_id_1;
24423 /* Flow ID of a flow. */
24424 uint32_t flow_id_2;
24425 /* Flow ID of a flow. */
24426 uint32_t flow_id_3;
24427 /* Flow ID of a flow. */
24428 uint32_t flow_id_4;
24429 /* Flow ID of a flow. */
24430 uint32_t flow_id_5;
24431 /* Flow ID of a flow. */
24432 uint32_t flow_id_6;
24433 /* Flow ID of a flow. */
24434 uint32_t flow_id_7;
24435 /* Flow ID of a flow. */
24436 uint32_t flow_id_8;
24437 /* Flow ID of a flow. */
24438 uint32_t flow_id_9;
24439 } __attribute__((packed));
24441 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
24442 struct hwrm_cfa_flow_stats_output {
24443 /* The specific error status for the command. */
24444 uint16_t error_code;
24445 /* The HWRM command request type. */
24447 /* The sequence ID from the original command. */
24449 /* The length of the response data in number of bytes. */
24451 /* packet_0 is 64 b */
24453 /* packet_1 is 64 b */
24455 /* packet_2 is 64 b */
24457 /* packet_3 is 64 b */
24459 /* packet_4 is 64 b */
24461 /* packet_5 is 64 b */
24463 /* packet_6 is 64 b */
24465 /* packet_7 is 64 b */
24467 /* packet_8 is 64 b */
24469 /* packet_9 is 64 b */
24471 /* byte_0 is 64 b */
24473 /* byte_1 is 64 b */
24475 /* byte_2 is 64 b */
24477 /* byte_3 is 64 b */
24479 /* byte_4 is 64 b */
24481 /* byte_5 is 64 b */
24483 /* byte_6 is 64 b */
24485 /* byte_7 is 64 b */
24487 /* byte_8 is 64 b */
24489 /* byte_9 is 64 b */
24491 uint8_t unused_0[7];
24493 * This field is used in Output records to indicate that the output
24494 * is completely written to RAM. This field should be read as '1'
24495 * to indicate that the output has been completely written.
24496 * When writing a command completion or response to an internal processor,
24497 * the order of writes has to be such that this field is written last.
24500 } __attribute__((packed));
24502 /**********************
24503 * hwrm_cfa_pair_info *
24504 **********************/
24507 /* hwrm_cfa_pair_info_input (size:448b/56B) */
24508 struct hwrm_cfa_pair_info_input {
24509 /* The HWRM command request type. */
24512 * The completion ring to send the completion event on. This should
24513 * be the NQ ID returned from the `nq_alloc` HWRM command.
24515 uint16_t cmpl_ring;
24517 * The sequence ID is used by the driver for tracking multiple
24518 * commands. This ID is treated as opaque data by the firmware and
24519 * the value is returned in the `hwrm_resp_hdr` upon completion.
24523 * The target ID of the command:
24524 * * 0x0-0xFFF8 - The function ID
24525 * * 0xFFF8-0xFFFE - Reserved for internal processors
24528 uint16_t target_id;
24530 * A physical address pointer pointing to a host buffer that the
24531 * command's response data will be written. This can be either a host
24532 * physical address (HPA) or a guest physical address (GPA) and must
24533 * point to a physically contiguous block of memory.
24535 uint64_t resp_addr;
24537 /* If this flag is set, lookup by name else lookup by index. */
24538 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
24539 /* If this flag is set, lookup by PF id and VF id. */
24540 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
24541 /* Pair table index. */
24542 uint16_t pair_index;
24543 /* Pair pf index. */
24545 /* Pair vf index. */
24547 /* Pair name (32 byte string). */
24548 char pair_name[32];
24549 } __attribute__((packed));
24551 /* hwrm_cfa_pair_info_output (size:576b/72B) */
24552 struct hwrm_cfa_pair_info_output {
24553 /* The specific error status for the command. */
24554 uint16_t error_code;
24555 /* The HWRM command request type. */
24557 /* The sequence ID from the original command. */
24559 /* The length of the response data in number of bytes. */
24561 /* Pair table index. */
24562 uint16_t next_pair_index;
24563 /* Pair member a's fid. */
24565 /* Logical host number. */
24566 uint8_t host_a_index;
24567 /* Logical PF number. */
24568 uint8_t pf_a_index;
24569 /* Pair member a's Linux logical VF number. */
24570 uint16_t vf_a_index;
24572 uint16_t rx_cfa_code_a;
24573 /* Tx CFA action. */
24574 uint16_t tx_cfa_action_a;
24575 /* Pair member b's fid. */
24577 /* Logical host number. */
24578 uint8_t host_b_index;
24579 /* Logical PF number. */
24580 uint8_t pf_b_index;
24581 /* Pair member a's Linux logical VF number. */
24582 uint16_t vf_b_index;
24584 uint16_t rx_cfa_code_b;
24585 /* Tx CFA action. */
24586 uint16_t tx_cfa_action_b;
24587 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
24589 /* Pair between VF on local host with PF or VF on specified host. */
24590 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
24591 /* Pair between REP on local host with PF or VF on specified host. */
24592 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
24593 /* Pair between REP on local host with REP on specified host. */
24594 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
24595 /* Pair for the proxy interface. */
24596 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
24597 /* Pair for the PF interface. */
24598 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
24599 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
24600 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
24602 uint8_t pair_state;
24603 /* Pair has been allocated */
24604 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
24605 /* Both pair members are active */
24606 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
24607 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
24608 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
24609 /* Pair name (32 byte string). */
24610 char pair_name[32];
24611 uint8_t unused_0[7];
24613 * This field is used in Output records to indicate that the output
24614 * is completely written to RAM. This field should be read as '1'
24615 * to indicate that the output has been completely written.
24616 * When writing a command completion or response to an internal processor,
24617 * the order of writes has to be such that this field is written last.
24620 } __attribute__((packed));
24622 /***************************************
24623 * hwrm_cfa_redirect_query_tunnel_type *
24624 ***************************************/
24627 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
24628 struct hwrm_cfa_redirect_query_tunnel_type_input {
24629 /* The HWRM command request type. */
24632 * The completion ring to send the completion event on. This should
24633 * be the NQ ID returned from the `nq_alloc` HWRM command.
24635 uint16_t cmpl_ring;
24637 * The sequence ID is used by the driver for tracking multiple
24638 * commands. This ID is treated as opaque data by the firmware and
24639 * the value is returned in the `hwrm_resp_hdr` upon completion.
24643 * The target ID of the command:
24644 * * 0x0-0xFFF8 - The function ID
24645 * * 0xFFF8-0xFFFE - Reserved for internal processors
24648 uint16_t target_id;
24650 * A physical address pointer pointing to a host buffer that the
24651 * command's response data will be written. This can be either a host
24652 * physical address (HPA) or a guest physical address (GPA) and must
24653 * point to a physically contiguous block of memory.
24655 uint64_t resp_addr;
24656 /* The source function id. */
24658 uint8_t unused_0[6];
24659 } __attribute__((packed));
24661 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
24662 struct hwrm_cfa_redirect_query_tunnel_type_output {
24663 /* The specific error status for the command. */
24664 uint16_t error_code;
24665 /* The HWRM command request type. */
24667 /* The sequence ID from the original command. */
24669 /* The length of the response data in number of bytes. */
24672 uint32_t tunnel_mask;
24674 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
24676 /* Virtual eXtensible Local Area Network (VXLAN) */
24677 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
24679 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
24680 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
24682 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
24683 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
24686 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
24688 /* Generic Network Virtualization Encapsulation (Geneve) */
24689 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
24691 /* Multi-Protocol Lable Switching (MPLS) */
24692 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
24694 /* Stateless Transport Tunnel (STT) */
24695 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
24697 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
24698 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
24700 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24701 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
24703 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24704 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
24706 /* Any tunneled traffic */
24707 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
24709 uint8_t unused_0[3];
24711 * This field is used in Output records to indicate that the output
24712 * is completely written to RAM. This field should be read as '1'
24713 * to indicate that the output has been completely written.
24714 * When writing a command completion or response to an internal processor,
24715 * the order of writes has to be such that this field is written last.
24718 } __attribute__((packed));
24720 /******************************
24721 * hwrm_tunnel_dst_port_query *
24722 ******************************/
24725 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
24726 struct hwrm_tunnel_dst_port_query_input {
24727 /* The HWRM command request type. */
24730 * The completion ring to send the completion event on. This should
24731 * be the NQ ID returned from the `nq_alloc` HWRM command.
24733 uint16_t cmpl_ring;
24735 * The sequence ID is used by the driver for tracking multiple
24736 * commands. This ID is treated as opaque data by the firmware and
24737 * the value is returned in the `hwrm_resp_hdr` upon completion.
24741 * The target ID of the command:
24742 * * 0x0-0xFFF8 - The function ID
24743 * * 0xFFF8-0xFFFE - Reserved for internal processors
24746 uint16_t target_id;
24748 * A physical address pointer pointing to a host buffer that the
24749 * command's response data will be written. This can be either a host
24750 * physical address (HPA) or a guest physical address (GPA) and must
24751 * point to a physically contiguous block of memory.
24753 uint64_t resp_addr;
24755 uint8_t tunnel_type;
24756 /* Virtual eXtensible Local Area Network (VXLAN) */
24757 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
24759 /* Generic Network Virtualization Encapsulation (Geneve) */
24760 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
24762 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24763 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24765 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24766 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24768 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
24769 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
24770 uint8_t unused_0[7];
24771 } __attribute__((packed));
24773 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
24774 struct hwrm_tunnel_dst_port_query_output {
24775 /* The specific error status for the command. */
24776 uint16_t error_code;
24777 /* The HWRM command request type. */
24779 /* The sequence ID from the original command. */
24781 /* The length of the response data in number of bytes. */
24784 * This field represents the identifier of L4 destination port
24785 * used for the given tunnel type. This field is valid for
24786 * specific tunnel types that use layer 4 (e.g. UDP)
24787 * transports for tunneling.
24789 uint16_t tunnel_dst_port_id;
24791 * This field represents the value of L4 destination port
24792 * identified by tunnel_dst_port_id. This field is valid for
24793 * specific tunnel types that use layer 4 (e.g. UDP)
24794 * transports for tunneling.
24795 * This field is in network byte order.
24797 * A value of 0 means that the destination port is not
24800 uint16_t tunnel_dst_port_val;
24801 uint8_t unused_0[3];
24803 * This field is used in Output records to indicate that the output
24804 * is completely written to RAM. This field should be read as '1'
24805 * to indicate that the output has been completely written.
24806 * When writing a command completion or response to an internal processor,
24807 * the order of writes has to be such that this field is written last.
24810 } __attribute__((packed));
24812 /******************************
24813 * hwrm_tunnel_dst_port_alloc *
24814 ******************************/
24817 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
24818 struct hwrm_tunnel_dst_port_alloc_input {
24819 /* The HWRM command request type. */
24822 * The completion ring to send the completion event on. This should
24823 * be the NQ ID returned from the `nq_alloc` HWRM command.
24825 uint16_t cmpl_ring;
24827 * The sequence ID is used by the driver for tracking multiple
24828 * commands. This ID is treated as opaque data by the firmware and
24829 * the value is returned in the `hwrm_resp_hdr` upon completion.
24833 * The target ID of the command:
24834 * * 0x0-0xFFF8 - The function ID
24835 * * 0xFFF8-0xFFFE - Reserved for internal processors
24838 uint16_t target_id;
24840 * A physical address pointer pointing to a host buffer that the
24841 * command's response data will be written. This can be either a host
24842 * physical address (HPA) or a guest physical address (GPA) and must
24843 * point to a physically contiguous block of memory.
24845 uint64_t resp_addr;
24847 uint8_t tunnel_type;
24848 /* Virtual eXtensible Local Area Network (VXLAN) */
24849 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
24851 /* Generic Network Virtualization Encapsulation (Geneve) */
24852 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
24854 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24855 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24857 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24858 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24860 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
24861 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
24864 * This field represents the value of L4 destination port used
24865 * for the given tunnel type. This field is valid for
24866 * specific tunnel types that use layer 4 (e.g. UDP)
24867 * transports for tunneling.
24869 * This field is in network byte order.
24871 * A value of 0 shall fail the command.
24873 uint16_t tunnel_dst_port_val;
24874 uint8_t unused_1[4];
24875 } __attribute__((packed));
24877 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
24878 struct hwrm_tunnel_dst_port_alloc_output {
24879 /* The specific error status for the command. */
24880 uint16_t error_code;
24881 /* The HWRM command request type. */
24883 /* The sequence ID from the original command. */
24885 /* The length of the response data in number of bytes. */
24888 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
24889 * types that has l4 destination port parameters.
24891 uint16_t tunnel_dst_port_id;
24892 uint8_t unused_0[5];
24894 * This field is used in Output records to indicate that the output
24895 * is completely written to RAM. This field should be read as '1'
24896 * to indicate that the output has been completely written.
24897 * When writing a command completion or response to an internal processor,
24898 * the order of writes has to be such that this field is written last.
24901 } __attribute__((packed));
24903 /*****************************
24904 * hwrm_tunnel_dst_port_free *
24905 *****************************/
24908 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
24909 struct hwrm_tunnel_dst_port_free_input {
24910 /* The HWRM command request type. */
24913 * The completion ring to send the completion event on. This should
24914 * be the NQ ID returned from the `nq_alloc` HWRM command.
24916 uint16_t cmpl_ring;
24918 * The sequence ID is used by the driver for tracking multiple
24919 * commands. This ID is treated as opaque data by the firmware and
24920 * the value is returned in the `hwrm_resp_hdr` upon completion.
24924 * The target ID of the command:
24925 * * 0x0-0xFFF8 - The function ID
24926 * * 0xFFF8-0xFFFE - Reserved for internal processors
24929 uint16_t target_id;
24931 * A physical address pointer pointing to a host buffer that the
24932 * command's response data will be written. This can be either a host
24933 * physical address (HPA) or a guest physical address (GPA) and must
24934 * point to a physically contiguous block of memory.
24936 uint64_t resp_addr;
24938 uint8_t tunnel_type;
24939 /* Virtual eXtensible Local Area Network (VXLAN) */
24940 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
24942 /* Generic Network Virtualization Encapsulation (Geneve) */
24943 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
24945 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
24946 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
24948 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
24949 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
24951 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
24952 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
24955 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
24956 * types that has l4 destination port parameters.
24958 uint16_t tunnel_dst_port_id;
24959 uint8_t unused_1[4];
24960 } __attribute__((packed));
24962 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
24963 struct hwrm_tunnel_dst_port_free_output {
24964 /* The specific error status for the command. */
24965 uint16_t error_code;
24966 /* The HWRM command request type. */
24968 /* The sequence ID from the original command. */
24970 /* The length of the response data in number of bytes. */
24972 uint8_t unused_1[7];
24974 * This field is used in Output records to indicate that the output
24975 * is completely written to RAM. This field should be read as '1'
24976 * to indicate that the output has been completely written.
24977 * When writing a command completion or response to an internal processor,
24978 * the order of writes has to be such that this field is written last.
24981 } __attribute__((packed));
24983 /* Periodic statistics context DMA to host. */
24984 /* ctx_hw_stats (size:1280b/160B) */
24985 struct ctx_hw_stats {
24986 /* Number of received unicast packets */
24987 uint64_t rx_ucast_pkts;
24988 /* Number of received multicast packets */
24989 uint64_t rx_mcast_pkts;
24990 /* Number of received broadcast packets */
24991 uint64_t rx_bcast_pkts;
24992 /* Number of discarded packets on received path */
24993 uint64_t rx_discard_pkts;
24994 /* Number of dropped packets on received path */
24995 uint64_t rx_drop_pkts;
24996 /* Number of received bytes for unicast traffic */
24997 uint64_t rx_ucast_bytes;
24998 /* Number of received bytes for multicast traffic */
24999 uint64_t rx_mcast_bytes;
25000 /* Number of received bytes for broadcast traffic */
25001 uint64_t rx_bcast_bytes;
25002 /* Number of transmitted unicast packets */
25003 uint64_t tx_ucast_pkts;
25004 /* Number of transmitted multicast packets */
25005 uint64_t tx_mcast_pkts;
25006 /* Number of transmitted broadcast packets */
25007 uint64_t tx_bcast_pkts;
25008 /* Number of discarded packets on transmit path */
25009 uint64_t tx_discard_pkts;
25010 /* Number of dropped packets on transmit path */
25011 uint64_t tx_drop_pkts;
25012 /* Number of transmitted bytes for unicast traffic */
25013 uint64_t tx_ucast_bytes;
25014 /* Number of transmitted bytes for multicast traffic */
25015 uint64_t tx_mcast_bytes;
25016 /* Number of transmitted bytes for broadcast traffic */
25017 uint64_t tx_bcast_bytes;
25018 /* Number of TPA packets */
25020 /* Number of TPA bytes */
25021 uint64_t tpa_bytes;
25022 /* Number of TPA events */
25023 uint64_t tpa_events;
25024 /* Number of TPA aborts */
25025 uint64_t tpa_aborts;
25026 } __attribute__((packed));
25028 /***********************
25029 * hwrm_stat_ctx_alloc *
25030 ***********************/
25033 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
25034 struct hwrm_stat_ctx_alloc_input {
25035 /* The HWRM command request type. */
25038 * The completion ring to send the completion event on. This should
25039 * be the NQ ID returned from the `nq_alloc` HWRM command.
25041 uint16_t cmpl_ring;
25043 * The sequence ID is used by the driver for tracking multiple
25044 * commands. This ID is treated as opaque data by the firmware and
25045 * the value is returned in the `hwrm_resp_hdr` upon completion.
25049 * The target ID of the command:
25050 * * 0x0-0xFFF8 - The function ID
25051 * * 0xFFF8-0xFFFE - Reserved for internal processors
25054 uint16_t target_id;
25056 * A physical address pointer pointing to a host buffer that the
25057 * command's response data will be written. This can be either a host
25058 * physical address (HPA) or a guest physical address (GPA) and must
25059 * point to a physically contiguous block of memory.
25061 uint64_t resp_addr;
25062 /* This is the address for statistic block. */
25063 uint64_t stats_dma_addr;
25065 * The statistic block update period in ms.
25066 * e.g. 250ms, 500ms, 750ms, 1000ms.
25067 * If update_period_ms is 0, then the stats update
25068 * shall be never done and the DMA address shall not be used.
25069 * In this case, the stat block can only be read by
25070 * hwrm_stat_ctx_query command.
25072 uint32_t update_period_ms;
25074 * This field is used to specify statistics context specific
25075 * configuration flags.
25077 uint8_t stat_ctx_flags;
25079 * When this bit is set to '1', the statistics context shall be
25080 * allocated for RoCE traffic only. In this case, traffic other
25081 * than offloaded RoCE traffic shall not be included in this
25082 * statistic context.
25083 * When this bit is set to '0', the statistics context shall be
25084 * used for the network traffic other than offloaded RoCE traffic.
25086 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
25087 uint8_t unused_0[3];
25088 } __attribute__((packed));
25090 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
25091 struct hwrm_stat_ctx_alloc_output {
25092 /* The specific error status for the command. */
25093 uint16_t error_code;
25094 /* The HWRM command request type. */
25096 /* The sequence ID from the original command. */
25098 /* The length of the response data in number of bytes. */
25100 /* This is the statistics context ID value. */
25101 uint32_t stat_ctx_id;
25102 uint8_t unused_0[3];
25104 * This field is used in Output records to indicate that the output
25105 * is completely written to RAM. This field should be read as '1'
25106 * to indicate that the output has been completely written.
25107 * When writing a command completion or response to an internal processor,
25108 * the order of writes has to be such that this field is written last.
25111 } __attribute__((packed));
25113 /**********************
25114 * hwrm_stat_ctx_free *
25115 **********************/
25118 /* hwrm_stat_ctx_free_input (size:192b/24B) */
25119 struct hwrm_stat_ctx_free_input {
25120 /* The HWRM command request type. */
25123 * The completion ring to send the completion event on. This should
25124 * be the NQ ID returned from the `nq_alloc` HWRM command.
25126 uint16_t cmpl_ring;
25128 * The sequence ID is used by the driver for tracking multiple
25129 * commands. This ID is treated as opaque data by the firmware and
25130 * the value is returned in the `hwrm_resp_hdr` upon completion.
25134 * The target ID of the command:
25135 * * 0x0-0xFFF8 - The function ID
25136 * * 0xFFF8-0xFFFE - Reserved for internal processors
25139 uint16_t target_id;
25141 * A physical address pointer pointing to a host buffer that the
25142 * command's response data will be written. This can be either a host
25143 * physical address (HPA) or a guest physical address (GPA) and must
25144 * point to a physically contiguous block of memory.
25146 uint64_t resp_addr;
25147 /* ID of the statistics context that is being queried. */
25148 uint32_t stat_ctx_id;
25149 uint8_t unused_0[4];
25150 } __attribute__((packed));
25152 /* hwrm_stat_ctx_free_output (size:128b/16B) */
25153 struct hwrm_stat_ctx_free_output {
25154 /* The specific error status for the command. */
25155 uint16_t error_code;
25156 /* The HWRM command request type. */
25158 /* The sequence ID from the original command. */
25160 /* The length of the response data in number of bytes. */
25162 /* This is the statistics context ID value. */
25163 uint32_t stat_ctx_id;
25164 uint8_t unused_0[3];
25166 * This field is used in Output records to indicate that the output
25167 * is completely written to RAM. This field should be read as '1'
25168 * to indicate that the output has been completely written.
25169 * When writing a command completion or response to an internal processor,
25170 * the order of writes has to be such that this field is written last.
25173 } __attribute__((packed));
25175 /***********************
25176 * hwrm_stat_ctx_query *
25177 ***********************/
25180 /* hwrm_stat_ctx_query_input (size:192b/24B) */
25181 struct hwrm_stat_ctx_query_input {
25182 /* The HWRM command request type. */
25185 * The completion ring to send the completion event on. This should
25186 * be the NQ ID returned from the `nq_alloc` HWRM command.
25188 uint16_t cmpl_ring;
25190 * The sequence ID is used by the driver for tracking multiple
25191 * commands. This ID is treated as opaque data by the firmware and
25192 * the value is returned in the `hwrm_resp_hdr` upon completion.
25196 * The target ID of the command:
25197 * * 0x0-0xFFF8 - The function ID
25198 * * 0xFFF8-0xFFFE - Reserved for internal processors
25201 uint16_t target_id;
25203 * A physical address pointer pointing to a host buffer that the
25204 * command's response data will be written. This can be either a host
25205 * physical address (HPA) or a guest physical address (GPA) and must
25206 * point to a physically contiguous block of memory.
25208 uint64_t resp_addr;
25209 /* ID of the statistics context that is being queried. */
25210 uint32_t stat_ctx_id;
25211 uint8_t unused_0[4];
25212 } __attribute__((packed));
25214 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
25215 struct hwrm_stat_ctx_query_output {
25216 /* The specific error status for the command. */
25217 uint16_t error_code;
25218 /* The HWRM command request type. */
25220 /* The sequence ID from the original command. */
25222 /* The length of the response data in number of bytes. */
25224 /* Number of transmitted unicast packets */
25225 uint64_t tx_ucast_pkts;
25226 /* Number of transmitted multicast packets */
25227 uint64_t tx_mcast_pkts;
25228 /* Number of transmitted broadcast packets */
25229 uint64_t tx_bcast_pkts;
25230 /* Number of transmitted packets with error */
25231 uint64_t tx_err_pkts;
25232 /* Number of dropped packets on transmit path */
25233 uint64_t tx_drop_pkts;
25234 /* Number of transmitted bytes for unicast traffic */
25235 uint64_t tx_ucast_bytes;
25236 /* Number of transmitted bytes for multicast traffic */
25237 uint64_t tx_mcast_bytes;
25238 /* Number of transmitted bytes for broadcast traffic */
25239 uint64_t tx_bcast_bytes;
25240 /* Number of received unicast packets */
25241 uint64_t rx_ucast_pkts;
25242 /* Number of received multicast packets */
25243 uint64_t rx_mcast_pkts;
25244 /* Number of received broadcast packets */
25245 uint64_t rx_bcast_pkts;
25246 /* Number of received packets with error */
25247 uint64_t rx_err_pkts;
25248 /* Number of dropped packets on received path */
25249 uint64_t rx_drop_pkts;
25250 /* Number of received bytes for unicast traffic */
25251 uint64_t rx_ucast_bytes;
25252 /* Number of received bytes for multicast traffic */
25253 uint64_t rx_mcast_bytes;
25254 /* Number of received bytes for broadcast traffic */
25255 uint64_t rx_bcast_bytes;
25256 /* Number of aggregated unicast packets */
25257 uint64_t rx_agg_pkts;
25258 /* Number of aggregated unicast bytes */
25259 uint64_t rx_agg_bytes;
25260 /* Number of aggregation events */
25261 uint64_t rx_agg_events;
25262 /* Number of aborted aggregations */
25263 uint64_t rx_agg_aborts;
25264 uint8_t unused_0[7];
25266 * This field is used in Output records to indicate that the output
25267 * is completely written to RAM. This field should be read as '1'
25268 * to indicate that the output has been completely written.
25269 * When writing a command completion or response to an internal processor,
25270 * the order of writes has to be such that this field is written last.
25273 } __attribute__((packed));
25275 /***************************
25276 * hwrm_stat_ctx_clr_stats *
25277 ***************************/
25280 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
25281 struct hwrm_stat_ctx_clr_stats_input {
25282 /* The HWRM command request type. */
25285 * The completion ring to send the completion event on. This should
25286 * be the NQ ID returned from the `nq_alloc` HWRM command.
25288 uint16_t cmpl_ring;
25290 * The sequence ID is used by the driver for tracking multiple
25291 * commands. This ID is treated as opaque data by the firmware and
25292 * the value is returned in the `hwrm_resp_hdr` upon completion.
25296 * The target ID of the command:
25297 * * 0x0-0xFFF8 - The function ID
25298 * * 0xFFF8-0xFFFE - Reserved for internal processors
25301 uint16_t target_id;
25303 * A physical address pointer pointing to a host buffer that the
25304 * command's response data will be written. This can be either a host
25305 * physical address (HPA) or a guest physical address (GPA) and must
25306 * point to a physically contiguous block of memory.
25308 uint64_t resp_addr;
25309 /* ID of the statistics context that is being queried. */
25310 uint32_t stat_ctx_id;
25311 uint8_t unused_0[4];
25312 } __attribute__((packed));
25314 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
25315 struct hwrm_stat_ctx_clr_stats_output {
25316 /* The specific error status for the command. */
25317 uint16_t error_code;
25318 /* The HWRM command request type. */
25320 /* The sequence ID from the original command. */
25322 /* The length of the response data in number of bytes. */
25324 uint8_t unused_0[7];
25326 * This field is used in Output records to indicate that the output
25327 * is completely written to RAM. This field should be read as '1'
25328 * to indicate that the output has been completely written.
25329 * When writing a command completion or response to an internal processor,
25330 * the order of writes has to be such that this field is written last.
25333 } __attribute__((packed));
25335 /********************
25336 * hwrm_pcie_qstats *
25337 ********************/
25340 /* hwrm_pcie_qstats_input (size:256b/32B) */
25341 struct hwrm_pcie_qstats_input {
25342 /* The HWRM command request type. */
25345 * The completion ring to send the completion event on. This should
25346 * be the NQ ID returned from the `nq_alloc` HWRM command.
25348 uint16_t cmpl_ring;
25350 * The sequence ID is used by the driver for tracking multiple
25351 * commands. This ID is treated as opaque data by the firmware and
25352 * the value is returned in the `hwrm_resp_hdr` upon completion.
25356 * The target ID of the command:
25357 * * 0x0-0xFFF8 - The function ID
25358 * * 0xFFF8-0xFFFE - Reserved for internal processors
25361 uint16_t target_id;
25363 * A physical address pointer pointing to a host buffer that the
25364 * command's response data will be written. This can be either a host
25365 * physical address (HPA) or a guest physical address (GPA) and must
25366 * point to a physically contiguous block of memory.
25368 uint64_t resp_addr;
25370 * The size of PCIe statistics block in bytes.
25371 * Firmware will DMA the PCIe statistics to
25372 * the host with this field size in the response.
25374 uint16_t pcie_stat_size;
25375 uint8_t unused_0[6];
25377 * This is the host address where
25378 * PCIe statistics will be stored
25380 uint64_t pcie_stat_host_addr;
25381 } __attribute__((packed));
25383 /* hwrm_pcie_qstats_output (size:128b/16B) */
25384 struct hwrm_pcie_qstats_output {
25385 /* The specific error status for the command. */
25386 uint16_t error_code;
25387 /* The HWRM command request type. */
25389 /* The sequence ID from the original command. */
25391 /* The length of the response data in number of bytes. */
25393 /* The size of PCIe statistics block in bytes. */
25394 uint16_t pcie_stat_size;
25395 uint8_t unused_0[5];
25397 * This field is used in Output records to indicate that the output
25398 * is completely written to RAM. This field should be read as '1'
25399 * to indicate that the output has been completely written.
25400 * When writing a command completion or response to an internal processor,
25401 * the order of writes has to be such that this field is written last.
25404 } __attribute__((packed));
25406 /* PCIe Statistics Formats */
25407 /* pcie_ctx_hw_stats (size:768b/96B) */
25408 struct pcie_ctx_hw_stats {
25409 /* Number of physical layer receiver errors */
25410 uint64_t pcie_pl_signal_integrity;
25411 /* Number of DLLP CRC errors detected by Data Link Layer */
25412 uint64_t pcie_dl_signal_integrity;
25414 * Number of TLP LCRC and sequence number errors detected
25415 * by Data Link Layer
25417 uint64_t pcie_tl_signal_integrity;
25418 /* Number of times LTSSM entered Recovery state */
25419 uint64_t pcie_link_integrity;
25420 /* Number of TLP bytes that have been trasmitted */
25421 uint64_t pcie_tx_traffic_rate;
25422 /* Number of TLP bytes that have been received */
25423 uint64_t pcie_rx_traffic_rate;
25424 /* Number of DLLP bytes that have been trasmitted */
25425 uint64_t pcie_tx_dllp_statistics;
25426 /* Number of DLLP bytes that have been received */
25427 uint64_t pcie_rx_dllp_statistics;
25429 * Number of times spent in each phase of gen3
25432 uint64_t pcie_equalization_time;
25433 /* Records the last 16 transitions of the LTSSM */
25434 uint32_t pcie_ltssm_histogram[4];
25436 * Record the last 8 reasons on why LTSSM transitioned
25439 uint64_t pcie_recovery_histogram;
25440 } __attribute__((packed));
25442 /**********************
25443 * hwrm_exec_fwd_resp *
25444 **********************/
25447 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
25448 struct hwrm_exec_fwd_resp_input {
25449 /* The HWRM command request type. */
25452 * The completion ring to send the completion event on. This should
25453 * be the NQ ID returned from the `nq_alloc` HWRM command.
25455 uint16_t cmpl_ring;
25457 * The sequence ID is used by the driver for tracking multiple
25458 * commands. This ID is treated as opaque data by the firmware and
25459 * the value is returned in the `hwrm_resp_hdr` upon completion.
25463 * The target ID of the command:
25464 * * 0x0-0xFFF8 - The function ID
25465 * * 0xFFF8-0xFFFE - Reserved for internal processors
25468 uint16_t target_id;
25470 * A physical address pointer pointing to a host buffer that the
25471 * command's response data will be written. This can be either a host
25472 * physical address (HPA) or a guest physical address (GPA) and must
25473 * point to a physically contiguous block of memory.
25475 uint64_t resp_addr;
25477 * This is an encapsulated request. This request should
25478 * be executed by the HWRM and the response should be
25479 * provided in the response buffer inside the encapsulated
25482 uint32_t encap_request[26];
25484 * This value indicates the target id of the response to
25485 * the encapsulated request.
25486 * 0x0 - 0xFFF8 - Used for function ids
25487 * 0xFFF8 - 0xFFFE - Reserved for internal processors
25490 uint16_t encap_resp_target_id;
25491 uint8_t unused_0[6];
25492 } __attribute__((packed));
25494 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
25495 struct hwrm_exec_fwd_resp_output {
25496 /* The specific error status for the command. */
25497 uint16_t error_code;
25498 /* The HWRM command request type. */
25500 /* The sequence ID from the original command. */
25502 /* The length of the response data in number of bytes. */
25504 uint8_t unused_0[7];
25506 * This field is used in Output records to indicate that the output
25507 * is completely written to RAM. This field should be read as '1'
25508 * to indicate that the output has been completely written.
25509 * When writing a command completion or response to an internal processor,
25510 * the order of writes has to be such that this field is written last.
25513 } __attribute__((packed));
25515 /************************
25516 * hwrm_reject_fwd_resp *
25517 ************************/
25520 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
25521 struct hwrm_reject_fwd_resp_input {
25522 /* The HWRM command request type. */
25525 * The completion ring to send the completion event on. This should
25526 * be the NQ ID returned from the `nq_alloc` HWRM command.
25528 uint16_t cmpl_ring;
25530 * The sequence ID is used by the driver for tracking multiple
25531 * commands. This ID is treated as opaque data by the firmware and
25532 * the value is returned in the `hwrm_resp_hdr` upon completion.
25536 * The target ID of the command:
25537 * * 0x0-0xFFF8 - The function ID
25538 * * 0xFFF8-0xFFFE - Reserved for internal processors
25541 uint16_t target_id;
25543 * A physical address pointer pointing to a host buffer that the
25544 * command's response data will be written. This can be either a host
25545 * physical address (HPA) or a guest physical address (GPA) and must
25546 * point to a physically contiguous block of memory.
25548 uint64_t resp_addr;
25550 * This is an encapsulated request. This request should
25551 * be rejected by the HWRM and the error response should be
25552 * provided in the response buffer inside the encapsulated
25555 uint32_t encap_request[26];
25557 * This value indicates the target id of the response to
25558 * the encapsulated request.
25559 * 0x0 - 0xFFF8 - Used for function ids
25560 * 0xFFF8 - 0xFFFE - Reserved for internal processors
25563 uint16_t encap_resp_target_id;
25564 uint8_t unused_0[6];
25565 } __attribute__((packed));
25567 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
25568 struct hwrm_reject_fwd_resp_output {
25569 /* The specific error status for the command. */
25570 uint16_t error_code;
25571 /* The HWRM command request type. */
25573 /* The sequence ID from the original command. */
25575 /* The length of the response data in number of bytes. */
25577 uint8_t unused_0[7];
25579 * This field is used in Output records to indicate that the output
25580 * is completely written to RAM. This field should be read as '1'
25581 * to indicate that the output has been completely written.
25582 * When writing a command completion or response to an internal processor,
25583 * the order of writes has to be such that this field is written last.
25586 } __attribute__((packed));
25593 /* hwrm_fwd_resp_input (size:1024b/128B) */
25594 struct hwrm_fwd_resp_input {
25595 /* The HWRM command request type. */
25598 * The completion ring to send the completion event on. This should
25599 * be the NQ ID returned from the `nq_alloc` HWRM command.
25601 uint16_t cmpl_ring;
25603 * The sequence ID is used by the driver for tracking multiple
25604 * commands. This ID is treated as opaque data by the firmware and
25605 * the value is returned in the `hwrm_resp_hdr` upon completion.
25609 * The target ID of the command:
25610 * * 0x0-0xFFF8 - The function ID
25611 * * 0xFFF8-0xFFFE - Reserved for internal processors
25614 uint16_t target_id;
25616 * A physical address pointer pointing to a host buffer that the
25617 * command's response data will be written. This can be either a host
25618 * physical address (HPA) or a guest physical address (GPA) and must
25619 * point to a physically contiguous block of memory.
25621 uint64_t resp_addr;
25623 * This value indicates the target id of the encapsulated
25625 * 0x0 - 0xFFF8 - Used for function ids
25626 * 0xFFF8 - 0xFFFE - Reserved for internal processors
25629 uint16_t encap_resp_target_id;
25631 * This value indicates the completion ring the encapsulated
25632 * response will be optionally completed on. If the value is
25633 * -1, then no CR completion shall be generated for the
25634 * encapsulated response. Any other value must be a
25635 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
25636 * is provided, then a CR completion shall be generated for
25637 * the encapsulated response.
25639 uint16_t encap_resp_cmpl_ring;
25640 /* This field indicates the length of encapsulated response. */
25641 uint16_t encap_resp_len;
25645 * This is the host address where the encapsulated response
25647 * This area must be 16B aligned and must be cleared to zero
25648 * before the original request is made.
25650 uint64_t encap_resp_addr;
25651 /* This is an encapsulated response. */
25652 uint32_t encap_resp[24];
25653 } __attribute__((packed));
25655 /* hwrm_fwd_resp_output (size:128b/16B) */
25656 struct hwrm_fwd_resp_output {
25657 /* The specific error status for the command. */
25658 uint16_t error_code;
25659 /* The HWRM command request type. */
25661 /* The sequence ID from the original command. */
25663 /* The length of the response data in number of bytes. */
25665 uint8_t unused_0[7];
25667 * This field is used in Output records to indicate that the output
25668 * is completely written to RAM. This field should be read as '1'
25669 * to indicate that the output has been completely written.
25670 * When writing a command completion or response to an internal processor,
25671 * the order of writes has to be such that this field is written last.
25674 } __attribute__((packed));
25676 /*****************************
25677 * hwrm_fwd_async_event_cmpl *
25678 *****************************/
25681 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
25682 struct hwrm_fwd_async_event_cmpl_input {
25683 /* The HWRM command request type. */
25686 * The completion ring to send the completion event on. This should
25687 * be the NQ ID returned from the `nq_alloc` HWRM command.
25689 uint16_t cmpl_ring;
25691 * The sequence ID is used by the driver for tracking multiple
25692 * commands. This ID is treated as opaque data by the firmware and
25693 * the value is returned in the `hwrm_resp_hdr` upon completion.
25697 * The target ID of the command:
25698 * * 0x0-0xFFF8 - The function ID
25699 * * 0xFFF8-0xFFFE - Reserved for internal processors
25702 uint16_t target_id;
25704 * A physical address pointer pointing to a host buffer that the
25705 * command's response data will be written. This can be either a host
25706 * physical address (HPA) or a guest physical address (GPA) and must
25707 * point to a physically contiguous block of memory.
25709 uint64_t resp_addr;
25711 * This value indicates the target id of the encapsulated
25712 * asynchronous event.
25713 * 0x0 - 0xFFF8 - Used for function ids
25714 * 0xFFF8 - 0xFFFE - Reserved for internal processors
25715 * 0xFFFF - Broadcast to all children VFs (only applicable when
25716 * a PF is the requester)
25718 uint16_t encap_async_event_target_id;
25719 uint8_t unused_0[6];
25720 /* This is an encapsulated asynchronous event completion. */
25721 uint32_t encap_async_event_cmpl[4];
25722 } __attribute__((packed));
25724 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
25725 struct hwrm_fwd_async_event_cmpl_output {
25726 /* The specific error status for the command. */
25727 uint16_t error_code;
25728 /* The HWRM command request type. */
25730 /* The sequence ID from the original command. */
25732 /* The length of the response data in number of bytes. */
25734 uint8_t unused_0[7];
25736 * This field is used in Output records to indicate that the output
25737 * is completely written to RAM. This field should be read as '1'
25738 * to indicate that the output has been completely written.
25739 * When writing a command completion or response to an internal processor,
25740 * the order of writes has to be such that this field is written last.
25743 } __attribute__((packed));
25745 /**************************
25746 * hwrm_nvm_raw_write_blk *
25747 **************************/
25750 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
25751 struct hwrm_nvm_raw_write_blk_input {
25752 /* The HWRM command request type. */
25755 * The completion ring to send the completion event on. This should
25756 * be the NQ ID returned from the `nq_alloc` HWRM command.
25758 uint16_t cmpl_ring;
25760 * The sequence ID is used by the driver for tracking multiple
25761 * commands. This ID is treated as opaque data by the firmware and
25762 * the value is returned in the `hwrm_resp_hdr` upon completion.
25766 * The target ID of the command:
25767 * * 0x0-0xFFF8 - The function ID
25768 * * 0xFFF8-0xFFFE - Reserved for internal processors
25771 uint16_t target_id;
25773 * A physical address pointer pointing to a host buffer that the
25774 * command's response data will be written. This can be either a host
25775 * physical address (HPA) or a guest physical address (GPA) and must
25776 * point to a physically contiguous block of memory.
25778 uint64_t resp_addr;
25780 * 64-bit Host Source Address.
25781 * This is the loation of the source data to be written.
25783 uint64_t host_src_addr;
25785 * 32-bit Destination Address.
25786 * This is the NVRAM byte-offset where the source data will be written to.
25788 uint32_t dest_addr;
25789 /* Length of data to be written, in bytes. */
25791 } __attribute__((packed));
25793 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
25794 struct hwrm_nvm_raw_write_blk_output {
25795 /* The specific error status for the command. */
25796 uint16_t error_code;
25797 /* The HWRM command request type. */
25799 /* The sequence ID from the original command. */
25801 /* The length of the response data in number of bytes. */
25803 uint8_t unused_0[7];
25805 * This field is used in Output records to indicate that the output
25806 * is completely written to RAM. This field should be read as '1'
25807 * to indicate that the output has been completely written.
25808 * When writing a command completion or response to an internal processor,
25809 * the order of writes has to be such that this field is written last.
25812 } __attribute__((packed));
25819 /* hwrm_nvm_read_input (size:320b/40B) */
25820 struct hwrm_nvm_read_input {
25821 /* The HWRM command request type. */
25824 * The completion ring to send the completion event on. This should
25825 * be the NQ ID returned from the `nq_alloc` HWRM command.
25827 uint16_t cmpl_ring;
25829 * The sequence ID is used by the driver for tracking multiple
25830 * commands. This ID is treated as opaque data by the firmware and
25831 * the value is returned in the `hwrm_resp_hdr` upon completion.
25835 * The target ID of the command:
25836 * * 0x0-0xFFF8 - The function ID
25837 * * 0xFFF8-0xFFFE - Reserved for internal processors
25840 uint16_t target_id;
25842 * A physical address pointer pointing to a host buffer that the
25843 * command's response data will be written. This can be either a host
25844 * physical address (HPA) or a guest physical address (GPA) and must
25845 * point to a physically contiguous block of memory.
25847 uint64_t resp_addr;
25849 * 64-bit Host Destination Address.
25850 * This is the host address where the data will be written to.
25852 uint64_t host_dest_addr;
25853 /* The 0-based index of the directory entry. */
25855 uint8_t unused_0[2];
25856 /* The NVRAM byte-offset to read from. */
25858 /* The length of the data to be read, in bytes. */
25860 uint8_t unused_1[4];
25861 } __attribute__((packed));
25863 /* hwrm_nvm_read_output (size:128b/16B) */
25864 struct hwrm_nvm_read_output {
25865 /* The specific error status for the command. */
25866 uint16_t error_code;
25867 /* The HWRM command request type. */
25869 /* The sequence ID from the original command. */
25871 /* The length of the response data in number of bytes. */
25873 uint8_t unused_0[7];
25875 * This field is used in Output records to indicate that the output
25876 * is completely written to RAM. This field should be read as '1'
25877 * to indicate that the output has been completely written.
25878 * When writing a command completion or response to an internal processor,
25879 * the order of writes has to be such that this field is written last.
25882 } __attribute__((packed));
25884 /*********************
25885 * hwrm_nvm_raw_dump *
25886 *********************/
25889 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
25890 struct hwrm_nvm_raw_dump_input {
25891 /* The HWRM command request type. */
25894 * The completion ring to send the completion event on. This should
25895 * be the NQ ID returned from the `nq_alloc` HWRM command.
25897 uint16_t cmpl_ring;
25899 * The sequence ID is used by the driver for tracking multiple
25900 * commands. This ID is treated as opaque data by the firmware and
25901 * the value is returned in the `hwrm_resp_hdr` upon completion.
25905 * The target ID of the command:
25906 * * 0x0-0xFFF8 - The function ID
25907 * * 0xFFF8-0xFFFE - Reserved for internal processors
25910 uint16_t target_id;
25912 * A physical address pointer pointing to a host buffer that the
25913 * command's response data will be written. This can be either a host
25914 * physical address (HPA) or a guest physical address (GPA) and must
25915 * point to a physically contiguous block of memory.
25917 uint64_t resp_addr;
25919 * 64-bit Host Destination Address.
25920 * This is the host address where the data will be written to.
25922 uint64_t host_dest_addr;
25923 /* 32-bit NVRAM byte-offset to read from. */
25925 /* Total length of NVRAM contents to be read, in bytes. */
25927 } __attribute__((packed));
25929 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
25930 struct hwrm_nvm_raw_dump_output {
25931 /* The specific error status for the command. */
25932 uint16_t error_code;
25933 /* The HWRM command request type. */
25935 /* The sequence ID from the original command. */
25937 /* The length of the response data in number of bytes. */
25939 uint8_t unused_0[7];
25941 * This field is used in Output records to indicate that the output
25942 * is completely written to RAM. This field should be read as '1'
25943 * to indicate that the output has been completely written.
25944 * When writing a command completion or response to an internal processor,
25945 * the order of writes has to be such that this field is written last.
25948 } __attribute__((packed));
25950 /****************************
25951 * hwrm_nvm_get_dir_entries *
25952 ****************************/
25955 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
25956 struct hwrm_nvm_get_dir_entries_input {
25957 /* The HWRM command request type. */
25960 * The completion ring to send the completion event on. This should
25961 * be the NQ ID returned from the `nq_alloc` HWRM command.
25963 uint16_t cmpl_ring;
25965 * The sequence ID is used by the driver for tracking multiple
25966 * commands. This ID is treated as opaque data by the firmware and
25967 * the value is returned in the `hwrm_resp_hdr` upon completion.
25971 * The target ID of the command:
25972 * * 0x0-0xFFF8 - The function ID
25973 * * 0xFFF8-0xFFFE - Reserved for internal processors
25976 uint16_t target_id;
25978 * A physical address pointer pointing to a host buffer that the
25979 * command's response data will be written. This can be either a host
25980 * physical address (HPA) or a guest physical address (GPA) and must
25981 * point to a physically contiguous block of memory.
25983 uint64_t resp_addr;
25985 * 64-bit Host Destination Address.
25986 * This is the host address where the directory will be written.
25988 uint64_t host_dest_addr;
25989 } __attribute__((packed));
25991 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
25992 struct hwrm_nvm_get_dir_entries_output {
25993 /* The specific error status for the command. */
25994 uint16_t error_code;
25995 /* The HWRM command request type. */
25997 /* The sequence ID from the original command. */
25999 /* The length of the response data in number of bytes. */
26001 uint8_t unused_0[7];
26003 * This field is used in Output records to indicate that the output
26004 * is completely written to RAM. This field should be read as '1'
26005 * to indicate that the output has been completely written.
26006 * When writing a command completion or response to an internal processor,
26007 * the order of writes has to be such that this field is written last.
26010 } __attribute__((packed));
26012 /*************************
26013 * hwrm_nvm_get_dir_info *
26014 *************************/
26017 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
26018 struct hwrm_nvm_get_dir_info_input {
26019 /* The HWRM command request type. */
26022 * The completion ring to send the completion event on. This should
26023 * be the NQ ID returned from the `nq_alloc` HWRM command.
26025 uint16_t cmpl_ring;
26027 * The sequence ID is used by the driver for tracking multiple
26028 * commands. This ID is treated as opaque data by the firmware and
26029 * the value is returned in the `hwrm_resp_hdr` upon completion.
26033 * The target ID of the command:
26034 * * 0x0-0xFFF8 - The function ID
26035 * * 0xFFF8-0xFFFE - Reserved for internal processors
26038 uint16_t target_id;
26040 * A physical address pointer pointing to a host buffer that the
26041 * command's response data will be written. This can be either a host
26042 * physical address (HPA) or a guest physical address (GPA) and must
26043 * point to a physically contiguous block of memory.
26045 uint64_t resp_addr;
26046 } __attribute__((packed));
26048 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
26049 struct hwrm_nvm_get_dir_info_output {
26050 /* The specific error status for the command. */
26051 uint16_t error_code;
26052 /* The HWRM command request type. */
26054 /* The sequence ID from the original command. */
26056 /* The length of the response data in number of bytes. */
26058 /* Number of directory entries in the directory. */
26060 /* Size of each directory entry, in bytes. */
26061 uint32_t entry_length;
26062 uint8_t unused_0[7];
26064 * This field is used in Output records to indicate that the output
26065 * is completely written to RAM. This field should be read as '1'
26066 * to indicate that the output has been completely written.
26067 * When writing a command completion or response to an internal processor,
26068 * the order of writes has to be such that this field is written last.
26071 } __attribute__((packed));
26073 /******************
26075 ******************/
26078 /* hwrm_nvm_write_input (size:384b/48B) */
26079 struct hwrm_nvm_write_input {
26080 /* The HWRM command request type. */
26083 * The completion ring to send the completion event on. This should
26084 * be the NQ ID returned from the `nq_alloc` HWRM command.
26086 uint16_t cmpl_ring;
26088 * The sequence ID is used by the driver for tracking multiple
26089 * commands. This ID is treated as opaque data by the firmware and
26090 * the value is returned in the `hwrm_resp_hdr` upon completion.
26094 * The target ID of the command:
26095 * * 0x0-0xFFF8 - The function ID
26096 * * 0xFFF8-0xFFFE - Reserved for internal processors
26099 uint16_t target_id;
26101 * A physical address pointer pointing to a host buffer that the
26102 * command's response data will be written. This can be either a host
26103 * physical address (HPA) or a guest physical address (GPA) and must
26104 * point to a physically contiguous block of memory.
26106 uint64_t resp_addr;
26108 * 64-bit Host Source Address.
26109 * This is where the source data is.
26111 uint64_t host_src_addr;
26112 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
26115 * Directory ordinal.
26116 * The 0-based instance of the combined Directory Entry Type and Extension.
26118 uint16_t dir_ordinal;
26119 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
26121 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
26124 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
26125 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
26127 uint32_t dir_data_length;
26132 * When this bit is '1', the original active image
26133 * will not be removed. TBD: what purpose is this?
26135 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
26138 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
26139 * If this value is less than the specified data length, it will be ignored.
26140 * The response will contain the actual allocated item length, which may be greater than the requested item length.
26141 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
26142 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
26144 uint32_t dir_item_length;
26146 } __attribute__((packed));
26148 /* hwrm_nvm_write_output (size:128b/16B) */
26149 struct hwrm_nvm_write_output {
26150 /* The specific error status for the command. */
26151 uint16_t error_code;
26152 /* The HWRM command request type. */
26154 /* The sequence ID from the original command. */
26156 /* The length of the response data in number of bytes. */
26159 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
26160 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
26162 uint32_t dir_item_length;
26163 /* The directory index of the created or modified item. */
26167 * This field is used in Output records to indicate that the output
26168 * is completely written to RAM. This field should be read as '1'
26169 * to indicate that the output has been completely written.
26170 * When writing a command completion or response to an internal processor,
26171 * the order of writes has to be such that this field is written last.
26174 } __attribute__((packed));
26176 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
26177 struct hwrm_nvm_write_cmd_err {
26179 * command specific error codes that goes to
26180 * the cmd_err field in Common HWRM Error Response.
26183 /* Unknown error */
26184 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
26185 /* Unable to complete operation due to fragmentation */
26186 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
26187 /* nvm is completely full. */
26188 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
26189 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
26190 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
26191 uint8_t unused_0[7];
26192 } __attribute__((packed));
26194 /*******************
26195 * hwrm_nvm_modify *
26196 *******************/
26199 /* hwrm_nvm_modify_input (size:320b/40B) */
26200 struct hwrm_nvm_modify_input {
26201 /* The HWRM command request type. */
26204 * The completion ring to send the completion event on. This should
26205 * be the NQ ID returned from the `nq_alloc` HWRM command.
26207 uint16_t cmpl_ring;
26209 * The sequence ID is used by the driver for tracking multiple
26210 * commands. This ID is treated as opaque data by the firmware and
26211 * the value is returned in the `hwrm_resp_hdr` upon completion.
26215 * The target ID of the command:
26216 * * 0x0-0xFFF8 - The function ID
26217 * * 0xFFF8-0xFFFE - Reserved for internal processors
26220 uint16_t target_id;
26222 * A physical address pointer pointing to a host buffer that the
26223 * command's response data will be written. This can be either a host
26224 * physical address (HPA) or a guest physical address (GPA) and must
26225 * point to a physically contiguous block of memory.
26227 uint64_t resp_addr;
26229 * 64-bit Host Source Address.
26230 * This is where the modified data is.
26232 uint64_t host_src_addr;
26233 /* 16-bit directory entry index. */
26235 uint8_t unused_0[2];
26236 /* 32-bit NVRAM byte-offset to modify content from. */
26239 * Length of data to be modified, in bytes. The length shall
26243 uint8_t unused_1[4];
26244 } __attribute__((packed));
26246 /* hwrm_nvm_modify_output (size:128b/16B) */
26247 struct hwrm_nvm_modify_output {
26248 /* The specific error status for the command. */
26249 uint16_t error_code;
26250 /* The HWRM command request type. */
26252 /* The sequence ID from the original command. */
26254 /* The length of the response data in number of bytes. */
26256 uint8_t unused_0[7];
26258 * This field is used in Output records to indicate that the output
26259 * is completely written to RAM. This field should be read as '1'
26260 * to indicate that the output has been completely written.
26261 * When writing a command completion or response to an internal processor,
26262 * the order of writes has to be such that this field is written last.
26265 } __attribute__((packed));
26267 /***************************
26268 * hwrm_nvm_find_dir_entry *
26269 ***************************/
26272 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
26273 struct hwrm_nvm_find_dir_entry_input {
26274 /* The HWRM command request type. */
26277 * The completion ring to send the completion event on. This should
26278 * be the NQ ID returned from the `nq_alloc` HWRM command.
26280 uint16_t cmpl_ring;
26282 * The sequence ID is used by the driver for tracking multiple
26283 * commands. This ID is treated as opaque data by the firmware and
26284 * the value is returned in the `hwrm_resp_hdr` upon completion.
26288 * The target ID of the command:
26289 * * 0x0-0xFFF8 - The function ID
26290 * * 0xFFF8-0xFFFE - Reserved for internal processors
26293 uint16_t target_id;
26295 * A physical address pointer pointing to a host buffer that the
26296 * command's response data will be written. This can be either a host
26297 * physical address (HPA) or a guest physical address (GPA) and must
26298 * point to a physically contiguous block of memory.
26300 uint64_t resp_addr;
26303 * This bit must be '1' for the dir_idx_valid field to be
26306 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
26308 /* Directory Entry Index */
26310 /* Directory Entry (Image) Type */
26313 * Directory ordinal.
26314 * The instance of this Directory Type
26316 uint16_t dir_ordinal;
26317 /* The Directory Entry Extension flags. */
26319 /* This value indicates the search option using dir_ordinal. */
26320 uint8_t opt_ordinal;
26321 /* This value indicates the search option using dir_ordinal. */
26322 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
26323 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
26324 /* Equal to specified ordinal value. */
26325 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
26326 /* Greater than or equal to specified ordinal value */
26327 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
26328 /* Greater than specified ordinal value */
26329 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
26330 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
26331 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
26332 uint8_t unused_0[3];
26333 } __attribute__((packed));
26335 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
26336 struct hwrm_nvm_find_dir_entry_output {
26337 /* The specific error status for the command. */
26338 uint16_t error_code;
26339 /* The HWRM command request type. */
26341 /* The sequence ID from the original command. */
26343 /* The length of the response data in number of bytes. */
26345 /* Allocated NVRAM for this directory entry, in bytes. */
26346 uint32_t dir_item_length;
26347 /* Size of the stored data for this directory entry, in bytes. */
26348 uint32_t dir_data_length;
26350 * Firmware version.
26351 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
26354 /* Directory ordinal. */
26355 uint16_t dir_ordinal;
26356 /* Directory Entry Index */
26358 uint8_t unused_0[7];
26360 * This field is used in Output records to indicate that the output
26361 * is completely written to RAM. This field should be read as '1'
26362 * to indicate that the output has been completely written.
26363 * When writing a command completion or response to an internal processor,
26364 * the order of writes has to be such that this field is written last.
26367 } __attribute__((packed));
26369 /****************************
26370 * hwrm_nvm_erase_dir_entry *
26371 ****************************/
26374 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
26375 struct hwrm_nvm_erase_dir_entry_input {
26376 /* The HWRM command request type. */
26379 * The completion ring to send the completion event on. This should
26380 * be the NQ ID returned from the `nq_alloc` HWRM command.
26382 uint16_t cmpl_ring;
26384 * The sequence ID is used by the driver for tracking multiple
26385 * commands. This ID is treated as opaque data by the firmware and
26386 * the value is returned in the `hwrm_resp_hdr` upon completion.
26390 * The target ID of the command:
26391 * * 0x0-0xFFF8 - The function ID
26392 * * 0xFFF8-0xFFFE - Reserved for internal processors
26395 uint16_t target_id;
26397 * A physical address pointer pointing to a host buffer that the
26398 * command's response data will be written. This can be either a host
26399 * physical address (HPA) or a guest physical address (GPA) and must
26400 * point to a physically contiguous block of memory.
26402 uint64_t resp_addr;
26403 /* Directory Entry Index */
26405 uint8_t unused_0[6];
26406 } __attribute__((packed));
26408 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
26409 struct hwrm_nvm_erase_dir_entry_output {
26410 /* The specific error status for the command. */
26411 uint16_t error_code;
26412 /* The HWRM command request type. */
26414 /* The sequence ID from the original command. */
26416 /* The length of the response data in number of bytes. */
26418 uint8_t unused_0[7];
26420 * This field is used in Output records to indicate that the output
26421 * is completely written to RAM. This field should be read as '1'
26422 * to indicate that the output has been completely written.
26423 * When writing a command completion or response to an internal processor,
26424 * the order of writes has to be such that this field is written last.
26427 } __attribute__((packed));
26429 /*************************
26430 * hwrm_nvm_get_dev_info *
26431 *************************/
26434 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
26435 struct hwrm_nvm_get_dev_info_input {
26436 /* The HWRM command request type. */
26439 * The completion ring to send the completion event on. This should
26440 * be the NQ ID returned from the `nq_alloc` HWRM command.
26442 uint16_t cmpl_ring;
26444 * The sequence ID is used by the driver for tracking multiple
26445 * commands. This ID is treated as opaque data by the firmware and
26446 * the value is returned in the `hwrm_resp_hdr` upon completion.
26450 * The target ID of the command:
26451 * * 0x0-0xFFF8 - The function ID
26452 * * 0xFFF8-0xFFFE - Reserved for internal processors
26455 uint16_t target_id;
26457 * A physical address pointer pointing to a host buffer that the
26458 * command's response data will be written. This can be either a host
26459 * physical address (HPA) or a guest physical address (GPA) and must
26460 * point to a physically contiguous block of memory.
26462 uint64_t resp_addr;
26463 } __attribute__((packed));
26465 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
26466 struct hwrm_nvm_get_dev_info_output {
26467 /* The specific error status for the command. */
26468 uint16_t error_code;
26469 /* The HWRM command request type. */
26471 /* The sequence ID from the original command. */
26473 /* The length of the response data in number of bytes. */
26475 /* Manufacturer ID. */
26476 uint16_t manufacturer_id;
26478 uint16_t device_id;
26479 /* Sector size of the NVRAM device. */
26480 uint32_t sector_size;
26481 /* Total size, in bytes of the NVRAM device. */
26482 uint32_t nvram_size;
26483 uint32_t reserved_size;
26484 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
26485 uint32_t available_size;
26486 uint8_t unused_0[3];
26488 * This field is used in Output records to indicate that the output
26489 * is completely written to RAM. This field should be read as '1'
26490 * to indicate that the output has been completely written.
26491 * When writing a command completion or response to an internal processor,
26492 * the order of writes has to be such that this field is written last.
26495 } __attribute__((packed));
26497 /**************************
26498 * hwrm_nvm_mod_dir_entry *
26499 **************************/
26502 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
26503 struct hwrm_nvm_mod_dir_entry_input {
26504 /* The HWRM command request type. */
26507 * The completion ring to send the completion event on. This should
26508 * be the NQ ID returned from the `nq_alloc` HWRM command.
26510 uint16_t cmpl_ring;
26512 * The sequence ID is used by the driver for tracking multiple
26513 * commands. This ID is treated as opaque data by the firmware and
26514 * the value is returned in the `hwrm_resp_hdr` upon completion.
26518 * The target ID of the command:
26519 * * 0x0-0xFFF8 - The function ID
26520 * * 0xFFF8-0xFFFE - Reserved for internal processors
26523 uint16_t target_id;
26525 * A physical address pointer pointing to a host buffer that the
26526 * command's response data will be written. This can be either a host
26527 * physical address (HPA) or a guest physical address (GPA) and must
26528 * point to a physically contiguous block of memory.
26530 uint64_t resp_addr;
26533 * This bit must be '1' for the checksum field to be
26536 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
26537 /* Directory Entry Index */
26540 * Directory ordinal.
26541 * The (0-based) instance of this Directory Type.
26543 uint16_t dir_ordinal;
26544 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
26546 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
26549 * If valid, then this field updates the checksum
26550 * value of the content in the directory entry.
26553 } __attribute__((packed));
26555 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
26556 struct hwrm_nvm_mod_dir_entry_output {
26557 /* The specific error status for the command. */
26558 uint16_t error_code;
26559 /* The HWRM command request type. */
26561 /* The sequence ID from the original command. */
26563 /* The length of the response data in number of bytes. */
26565 uint8_t unused_0[7];
26567 * This field is used in Output records to indicate that the output
26568 * is completely written to RAM. This field should be read as '1'
26569 * to indicate that the output has been completely written.
26570 * When writing a command completion or response to an internal processor,
26571 * the order of writes has to be such that this field is written last.
26574 } __attribute__((packed));
26576 /**************************
26577 * hwrm_nvm_verify_update *
26578 **************************/
26581 /* hwrm_nvm_verify_update_input (size:192b/24B) */
26582 struct hwrm_nvm_verify_update_input {
26583 /* The HWRM command request type. */
26586 * The completion ring to send the completion event on. This should
26587 * be the NQ ID returned from the `nq_alloc` HWRM command.
26589 uint16_t cmpl_ring;
26591 * The sequence ID is used by the driver for tracking multiple
26592 * commands. This ID is treated as opaque data by the firmware and
26593 * the value is returned in the `hwrm_resp_hdr` upon completion.
26597 * The target ID of the command:
26598 * * 0x0-0xFFF8 - The function ID
26599 * * 0xFFF8-0xFFFE - Reserved for internal processors
26602 uint16_t target_id;
26604 * A physical address pointer pointing to a host buffer that the
26605 * command's response data will be written. This can be either a host
26606 * physical address (HPA) or a guest physical address (GPA) and must
26607 * point to a physically contiguous block of memory.
26609 uint64_t resp_addr;
26610 /* Directory Entry Type, to be verified. */
26613 * Directory ordinal.
26614 * The instance of the Directory Type to be verified.
26616 uint16_t dir_ordinal;
26618 * The Directory Entry Extension flags.
26619 * The "UPDATE" extension flag must be set in this value.
26620 * A corresponding directory entry with the same type and ordinal values but *without*
26621 * the "UPDATE" extension flag must also exist. The other flags of the extension must
26622 * be identical between the active and update entries.
26625 uint8_t unused_0[2];
26626 } __attribute__((packed));
26628 /* hwrm_nvm_verify_update_output (size:128b/16B) */
26629 struct hwrm_nvm_verify_update_output {
26630 /* The specific error status for the command. */
26631 uint16_t error_code;
26632 /* The HWRM command request type. */
26634 /* The sequence ID from the original command. */
26636 /* The length of the response data in number of bytes. */
26638 uint8_t unused_0[7];
26640 * This field is used in Output records to indicate that the output
26641 * is completely written to RAM. This field should be read as '1'
26642 * to indicate that the output has been completely written.
26643 * When writing a command completion or response to an internal processor,
26644 * the order of writes has to be such that this field is written last.
26647 } __attribute__((packed));
26649 /***************************
26650 * hwrm_nvm_install_update *
26651 ***************************/
26654 /* hwrm_nvm_install_update_input (size:192b/24B) */
26655 struct hwrm_nvm_install_update_input {
26656 /* The HWRM command request type. */
26659 * The completion ring to send the completion event on. This should
26660 * be the NQ ID returned from the `nq_alloc` HWRM command.
26662 uint16_t cmpl_ring;
26664 * The sequence ID is used by the driver for tracking multiple
26665 * commands. This ID is treated as opaque data by the firmware and
26666 * the value is returned in the `hwrm_resp_hdr` upon completion.
26670 * The target ID of the command:
26671 * * 0x0-0xFFF8 - The function ID
26672 * * 0xFFF8-0xFFFE - Reserved for internal processors
26675 uint16_t target_id;
26677 * A physical address pointer pointing to a host buffer that the
26678 * command's response data will be written. This can be either a host
26679 * physical address (HPA) or a guest physical address (GPA) and must
26680 * point to a physically contiguous block of memory.
26682 uint64_t resp_addr;
26684 * Installation type. If the value 3 through 0xffff is used,
26685 * only packaged items with that type value will be installed and
26686 * conditional installation directives for those packaged items
26687 * will be over-ridden (i.e. 'create' or 'replace' will be treated
26690 uint32_t install_type;
26692 * Perform a normal package installation. Conditional installation
26693 * directives (e.g. 'create' and 'replace') of packaged items
26694 * will be followed.
26696 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
26698 * Install all packaged items regardless of installation directive
26699 * (i.e. treat all packaged items as though they have an installation
26700 * directive of 'install').
26702 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
26703 UINT32_C(0xffffffff)
26704 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
26705 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
26707 /* If set to 1, then securely erase all unused locations in persistent storage. */
26708 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
26711 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
26712 * When combined with erase_unused_space then unspecified images will be securely erased.
26714 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
26717 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
26718 * Allow additional time for this command to complete if this bit is set to 1.
26720 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
26722 uint8_t unused_0[2];
26723 } __attribute__((packed));
26725 /* hwrm_nvm_install_update_output (size:192b/24B) */
26726 struct hwrm_nvm_install_update_output {
26727 /* The specific error status for the command. */
26728 uint16_t error_code;
26729 /* The HWRM command request type. */
26731 /* The sequence ID from the original command. */
26733 /* The length of the response data in number of bytes. */
26736 * Bit-mask of successfully installed items.
26737 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
26738 * A value of 0 indicates that no items were successfully installed.
26740 uint64_t installed_items;
26741 /* result is 8 b */
26743 /* There was no problem with the package installation. */
26744 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
26745 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
26746 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
26747 /* problem_item is 8 b */
26748 uint8_t problem_item;
26749 /* There was no problem with any packaged items. */
26750 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
26752 /* There was a problem with the NVM package itself. */
26753 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
26755 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
26756 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
26757 /* reset_required is 8 b */
26758 uint8_t reset_required;
26760 * No reset is required for installed/updated firmware or
26761 * microcode to take effect.
26763 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
26766 * A PCIe reset (e.g. system reboot) is
26767 * required for newly installed/updated firmware or
26768 * microcode to take effect.
26770 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
26773 * A controller power reset (e.g. system power-cycle) is
26774 * required for newly installed/updated firmware or
26775 * microcode to take effect. Some newly installed/updated
26776 * firmware or microcode may still take effect upon the
26779 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
26781 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
26782 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
26783 uint8_t unused_0[4];
26785 * This field is used in Output records to indicate that the output
26786 * is completely written to RAM. This field should be read as '1'
26787 * to indicate that the output has been completely written.
26788 * When writing a command completion or response to an internal processor,
26789 * the order of writes has to be such that this field is written last.
26792 } __attribute__((packed));
26794 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
26795 struct hwrm_nvm_install_update_cmd_err {
26797 * command specific error codes that goes to
26798 * the cmd_err field in Common HWRM Error Response.
26801 /* Unknown error */
26802 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
26803 /* Unable to complete operation due to fragmentation */
26804 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
26805 /* nvm is completely full. */
26806 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
26807 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
26808 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
26809 uint8_t unused_0[7];
26810 } __attribute__((packed));
26812 /******************
26814 ******************/
26817 /* hwrm_nvm_flush_input (size:128b/16B) */
26818 struct hwrm_nvm_flush_input {
26819 /* The HWRM command request type. */
26822 * The completion ring to send the completion event on. This should
26823 * be the NQ ID returned from the `nq_alloc` HWRM command.
26825 uint16_t cmpl_ring;
26827 * The sequence ID is used by the driver for tracking multiple
26828 * commands. This ID is treated as opaque data by the firmware and
26829 * the value is returned in the `hwrm_resp_hdr` upon completion.
26833 * The target ID of the command:
26834 * * 0x0-0xFFF8 - The function ID
26835 * * 0xFFF8-0xFFFE - Reserved for internal processors
26838 uint16_t target_id;
26840 * A physical address pointer pointing to a host buffer that the
26841 * command's response data will be written. This can be either a host
26842 * physical address (HPA) or a guest physical address (GPA) and must
26843 * point to a physically contiguous block of memory.
26845 uint64_t resp_addr;
26846 } __attribute__((packed));
26848 /* hwrm_nvm_flush_output (size:128b/16B) */
26849 struct hwrm_nvm_flush_output {
26850 /* The specific error status for the command. */
26851 uint16_t error_code;
26852 /* The HWRM command request type. */
26854 /* The sequence ID from the original command. */
26856 /* The length of the response data in number of bytes. */
26858 uint8_t unused_0[7];
26860 * This field is used in Output records to indicate that the output
26861 * is completely written to RAM. This field should be read as '1'
26862 * to indicate that the output has been completely written.
26863 * When writing a command completion or response to an internal processor,
26864 * the order of writes has to be such that this field is written last.
26867 } __attribute__((packed));
26869 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
26870 struct hwrm_nvm_flush_cmd_err {
26872 * command specific error codes that goes to
26873 * the cmd_err field in Common HWRM Error Response.
26876 /* Unknown error */
26877 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
26878 /* flush could not be performed */
26879 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
26880 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
26881 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
26882 uint8_t unused_0[7];
26883 } __attribute__((packed));
26885 /*************************
26886 * hwrm_nvm_get_variable *
26887 *************************/
26890 /* hwrm_nvm_get_variable_input (size:320b/40B) */
26891 struct hwrm_nvm_get_variable_input {
26892 /* The HWRM command request type. */
26895 * The completion ring to send the completion event on. This should
26896 * be the NQ ID returned from the `nq_alloc` HWRM command.
26898 uint16_t cmpl_ring;
26900 * The sequence ID is used by the driver for tracking multiple
26901 * commands. This ID is treated as opaque data by the firmware and
26902 * the value is returned in the `hwrm_resp_hdr` upon completion.
26906 * The target ID of the command:
26907 * * 0x0-0xFFF8 - The function ID
26908 * * 0xFFF8-0xFFFE - Reserved for internal processors
26911 uint16_t target_id;
26913 * A physical address pointer pointing to a host buffer that the
26914 * command's response data will be written. This can be either a host
26915 * physical address (HPA) or a guest physical address (GPA) and must
26916 * point to a physically contiguous block of memory.
26918 uint64_t resp_addr;
26920 * This is the host address where
26921 * nvm variable will be stored
26923 uint64_t dest_data_addr;
26924 /* size of data in bits */
26926 /* nvm cfg option number */
26927 uint16_t option_num;
26929 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
26931 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
26933 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
26934 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
26936 * Number of dimensions for this nvm configuration variable.
26937 * This value indicates how many of the indexN values to use.
26938 * A value of 0 means that none of the indexN values are valid.
26939 * A value of 1 requires at index0 is valued, a value of 2
26940 * requires that index0 and index1 are valid, and so forth
26942 uint16_t dimensions;
26943 /* index for the 1st dimensions */
26945 /* index for the 2nd dimensions */
26947 /* index for the 3rd dimensions */
26949 /* index for the 4th dimensions */
26953 * When this bit is set to 1, the factory default value will be returned,
26954 * 0 returns the operational value.
26956 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
26959 } __attribute__((packed));
26961 /* hwrm_nvm_get_variable_output (size:128b/16B) */
26962 struct hwrm_nvm_get_variable_output {
26963 /* The specific error status for the command. */
26964 uint16_t error_code;
26965 /* The HWRM command request type. */
26967 /* The sequence ID from the original command. */
26969 /* The length of the response data in number of bytes. */
26971 /* size of data of the actual variable retrieved in bits */
26974 * option_num is the option number for the data retrieved. It is possible in the
26975 * future that the option number returned would be different than requested. This
26976 * condition could occur if an option is deprecated and a new option id is defined
26977 * with similar characteristics, but has a slightly different definition. This
26978 * also makes it convenient for the caller to identify the variable result with
26979 * the option id from the response.
26981 uint16_t option_num;
26983 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
26985 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
26987 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
26988 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
26989 uint8_t unused_0[3];
26991 * This field is used in Output records to indicate that the output
26992 * is completely written to RAM. This field should be read as '1'
26993 * to indicate that the output has been completely written.
26994 * When writing a command completion or response to an internal processor,
26995 * the order of writes has to be such that this field is written last.
26998 } __attribute__((packed));
27000 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
27001 struct hwrm_nvm_get_variable_cmd_err {
27003 * command specific error codes that goes to
27004 * the cmd_err field in Common HWRM Error Response.
27007 /* Unknown error */
27008 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27009 /* variable does not exist */
27010 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27011 /* configuration is corrupted and the variable cannot be saved */
27012 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27013 /* length specified is too small */
27014 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
27015 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
27016 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
27017 uint8_t unused_0[7];
27018 } __attribute__((packed));
27020 /*************************
27021 * hwrm_nvm_set_variable *
27022 *************************/
27025 /* hwrm_nvm_set_variable_input (size:320b/40B) */
27026 struct hwrm_nvm_set_variable_input {
27027 /* The HWRM command request type. */
27030 * The completion ring to send the completion event on. This should
27031 * be the NQ ID returned from the `nq_alloc` HWRM command.
27033 uint16_t cmpl_ring;
27035 * The sequence ID is used by the driver for tracking multiple
27036 * commands. This ID is treated as opaque data by the firmware and
27037 * the value is returned in the `hwrm_resp_hdr` upon completion.
27041 * The target ID of the command:
27042 * * 0x0-0xFFF8 - The function ID
27043 * * 0xFFF8-0xFFFE - Reserved for internal processors
27046 uint16_t target_id;
27048 * A physical address pointer pointing to a host buffer that the
27049 * command's response data will be written. This can be either a host
27050 * physical address (HPA) or a guest physical address (GPA) and must
27051 * point to a physically contiguous block of memory.
27053 uint64_t resp_addr;
27055 * This is the host address where
27056 * nvm variable will be copied from
27058 uint64_t src_data_addr;
27059 /* size of data in bits */
27061 /* nvm cfg option number */
27062 uint16_t option_num;
27064 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27066 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
27068 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
27069 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
27071 * Number of dimensions for this nvm configuration variable.
27072 * This value indicates how many of the indexN values to use.
27073 * A value of 0 means that none of the indexN values are valid.
27074 * A value of 1 requires at index0 is valued, a value of 2
27075 * requires that index0 and index1 are valid, and so forth
27077 uint16_t dimensions;
27078 /* index for the 1st dimensions */
27080 /* index for the 2nd dimensions */
27082 /* index for the 3rd dimensions */
27084 /* index for the 4th dimensions */
27087 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
27088 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
27090 /* encryption method */
27091 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
27093 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
27094 /* No encryption. */
27095 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
27096 (UINT32_C(0x0) << 1)
27097 /* one-way encryption. */
27098 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
27099 (UINT32_C(0x1) << 1)
27100 /* symmetric AES256 encryption. */
27101 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
27102 (UINT32_C(0x2) << 1)
27103 /* SHA1 digest appended to plaintext contents, for authentication */
27104 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
27105 (UINT32_C(0x3) << 1)
27106 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
27107 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
27109 } __attribute__((packed));
27111 /* hwrm_nvm_set_variable_output (size:128b/16B) */
27112 struct hwrm_nvm_set_variable_output {
27113 /* The specific error status for the command. */
27114 uint16_t error_code;
27115 /* The HWRM command request type. */
27117 /* The sequence ID from the original command. */
27119 /* The length of the response data in number of bytes. */
27121 uint8_t unused_0[7];
27123 * This field is used in Output records to indicate that the output
27124 * is completely written to RAM. This field should be read as '1'
27125 * to indicate that the output has been completely written.
27126 * When writing a command completion or response to an internal processor,
27127 * the order of writes has to be such that this field is written last.
27130 } __attribute__((packed));
27132 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
27133 struct hwrm_nvm_set_variable_cmd_err {
27135 * command specific error codes that goes to
27136 * the cmd_err field in Common HWRM Error Response.
27139 /* Unknown error */
27140 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27141 /* variable does not exist */
27142 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27143 /* configuration is corrupted and the variable cannot be saved */
27144 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27145 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
27146 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
27147 uint8_t unused_0[7];
27148 } __attribute__((packed));
27150 /****************************
27151 * hwrm_nvm_validate_option *
27152 ****************************/
27155 /* hwrm_nvm_validate_option_input (size:320b/40B) */
27156 struct hwrm_nvm_validate_option_input {
27157 /* The HWRM command request type. */
27160 * The completion ring to send the completion event on. This should
27161 * be the NQ ID returned from the `nq_alloc` HWRM command.
27163 uint16_t cmpl_ring;
27165 * The sequence ID is used by the driver for tracking multiple
27166 * commands. This ID is treated as opaque data by the firmware and
27167 * the value is returned in the `hwrm_resp_hdr` upon completion.
27171 * The target ID of the command:
27172 * * 0x0-0xFFF8 - The function ID
27173 * * 0xFFF8-0xFFFE - Reserved for internal processors
27176 uint16_t target_id;
27178 * A physical address pointer pointing to a host buffer that the
27179 * command's response data will be written. This can be either a host
27180 * physical address (HPA) or a guest physical address (GPA) and must
27181 * point to a physically contiguous block of memory.
27183 uint64_t resp_addr;
27185 * This is the host address where
27186 * nvm variable will be copied from
27188 uint64_t src_data_addr;
27189 /* size of data in bits */
27191 /* nvm cfg option number */
27192 uint16_t option_num;
27194 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
27197 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
27199 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
27200 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
27202 * Number of dimensions for this nvm configuration variable.
27203 * This value indicates how many of the indexN values to use.
27204 * A value of 0 means that none of the indexN values are valid.
27205 * A value of 1 requires at index0 is valued, a value of 2
27206 * requires that index0 and index1 are valid, and so forth
27208 uint16_t dimensions;
27209 /* index for the 1st dimensions */
27211 /* index for the 2nd dimensions */
27213 /* index for the 3rd dimensions */
27215 /* index for the 4th dimensions */
27217 uint8_t unused_0[2];
27218 } __attribute__((packed));
27220 /* hwrm_nvm_validate_option_output (size:128b/16B) */
27221 struct hwrm_nvm_validate_option_output {
27222 /* The specific error status for the command. */
27223 uint16_t error_code;
27224 /* The HWRM command request type. */
27226 /* The sequence ID from the original command. */
27228 /* The length of the response data in number of bytes. */
27231 /* indicates that the value provided for the option is not matching with the saved data. */
27232 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
27233 /* indicates that the value provided for the option is matching the saved data. */
27234 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
27235 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
27236 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
27237 uint8_t unused_0[6];
27239 * This field is used in Output records to indicate that the output
27240 * is completely written to RAM. This field should be read as '1'
27241 * to indicate that the output has been completely written.
27242 * When writing a command completion or response to an internal processor,
27243 * the order of writes has to be such that this field is written last.
27246 } __attribute__((packed));
27248 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
27249 struct hwrm_nvm_validate_option_cmd_err {
27251 * command specific error codes that goes to
27252 * the cmd_err field in Common HWRM Error Response.
27255 /* Unknown error */
27256 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27257 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
27258 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
27259 uint8_t unused_0[7];
27260 } __attribute__((packed));
27262 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */