4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
35 #define _HSI_STRUCT_DEF_EXTERNAL_H_
38 * per-context HW statistics -- chip view
41 struct ctx_hw_stats64 {
42 uint64_t rx_ucast_pkts;
43 uint64_t rx_mcast_pkts;
44 uint64_t rx_bcast_pkts;
45 uint64_t rx_drop_pkts;
47 uint64_t rx_ucast_bytes;
48 uint64_t rx_mcast_bytes;
49 uint64_t rx_bcast_bytes;
51 uint64_t tx_ucast_pkts;
52 uint64_t tx_mcast_pkts;
53 uint64_t tx_bcast_pkts;
54 uint64_t tx_drop_pkts;
56 uint64_t tx_ucast_bytes;
57 uint64_t tx_mcast_bytes;
58 uint64_t tx_bcast_bytes;
66 /* HW Resource Manager Specification 1.2.0 */
67 #define HWRM_VERSION_MAJOR 1
68 #define HWRM_VERSION_MINOR 2
69 #define HWRM_VERSION_UPDATE 0
72 * Following is the signature for HWRM message field that indicates not
73 * applicable (All F's). Need to cast it the size of the field if needed.
75 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
76 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
77 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
78 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
79 #define HW_HASH_KEY_SIZE 40
80 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
85 #define HWRM_VER_GET (UINT32_C(0x0))
86 #define HWRM_FUNC_RESET (UINT32_C(0x11))
87 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
88 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
89 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
90 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
91 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
92 #define HWRM_VNIC_ALLOC (UINT32_C(0x40))
93 #define HWRM_VNIC_FREE (UINT32_C(0x41))
94 #define HWRM_VNIC_CFG (UINT32_C(0x42))
95 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
96 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
97 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
98 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
99 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
100 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
103 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
104 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
106 /* Short TX BD (16 bytes) */
109 * All bits in this field must be valid on the first BD of a packet.
110 * Only the packet_end bit must be valid for the remaining BDs of a
113 /* This value identifies the type of buffer descriptor. */
114 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
115 #define TX_BD_SHORT_TYPE_SFT 0
117 * Indicates that this BD is 16B long and is used for normal L2
118 * packet transmission.
120 #define TX_BD_SHORT_TYPE_TX_BD_SHORT (UINT32_C(0x0) << 0)
122 * If set to 1, the packet ends with the data in the buffer pointed to
123 * by this descriptor. This flag must be valid on every BD.
125 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
127 * If set to 1, the device will not generate a completion for this
128 * transmit packet unless there is an error in it's processing. If this
129 * bit is set to 0, then the packet will be completed normally. This bit
130 * must be valid only on the first BD of a packet.
132 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
134 * This value indicates how many 16B BD locations are consumed in the
135 * ring by this packet. A value of 1 indicates that this BD is the only
136 * BD (and that the it is a short BD). A value of 3 indicates either 3
137 * short BDs or 1 long BD and one short BD in the packet. A value of 0
138 * indicates that there are 32 BD locations in the packet (the maximum).
139 * This field is valid only on the first BD of a packet.
141 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
142 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
144 * This value is a hint for the length of the entire packet. It is used
145 * by the chip to optimize internal processing. The packet will be
146 * dropped if the hint is too short. This field is valid only on the
147 * first BD of a packet.
149 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
150 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
151 /* indicates packet length < 512B */
152 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
153 /* indicates 512 <= packet length < 1KB */
154 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
155 /* indicates 1KB <= packet length < 2KB */
156 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
157 /* indicates packet length >= 2KB */
158 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
159 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
161 * If set to 1, the device immediately updates the Send Consumer Index
162 * after the buffer associated with this descriptor has been transferred
163 * via DMA to NIC memory from host memory. An interrupt may or may not
164 * be generated according to the state of the interrupt avoidance
165 * mechanisms. If this bit is set to 0, then the Consumer Index is only
166 * updated as soon as one of the host interrupt coalescing conditions
167 * has been met. This bit must be valid on the first BD of a packet.
169 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
171 * All bits in this field must be valid on the first BD of a packet.
172 * Only the packet_end bit must be valid for the remaining BDs of a
175 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
176 #define TX_BD_SHORT_FLAGS_SFT 6
180 * This is the length of the host physical buffer this BD describes in
181 * bytes. This field must be valid on all BDs of a packet.
185 * The opaque data field is pass through to the completion and can be
186 * used for any data that the driver wants to associate with the
187 * transmit BD. This field must be valid on the first BD of a packet.
192 * This is the host physical address for the portion of the packet
193 * described by this TX BD. This value must be valid on all BDs of a
197 } __attribute__((packed));
199 /* Long TX BD (32 bytes split to 2 16-byte struct) */
202 * All bits in this field must be valid on the first BD of a packet.
203 * Only the packet_end bit must be valid for the remaining BDs of a
206 /* This value identifies the type of buffer descriptor. */
207 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
208 #define TX_BD_LONG_TYPE_SFT 0
210 * Indicates that this BD is 32B long and is used for normal L2
211 * packet transmission.
213 #define TX_BD_LONG_TYPE_TX_BD_LONG (UINT32_C(0x10) << 0)
215 * If set to 1, the packet ends with the data in the buffer pointed to
216 * by this descriptor. This flag must be valid on every BD.
218 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
220 * If set to 1, the device will not generate a completion for this
221 * transmit packet unless there is an error in it's processing. If this
222 * bit is set to 0, then the packet will be completed normally. This bit
223 * must be valid only on the first BD of a packet.
225 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
227 * This value indicates how many 16B BD locations are consumed in the
228 * ring by this packet. A value of 1 indicates that this BD is the only
229 * BD (and that the it is a short BD). A value of 3 indicates either 3
230 * short BDs or 1 long BD and one short BD in the packet. A value of 0
231 * indicates that there are 32 BD locations in the packet (the maximum).
232 * This field is valid only on the first BD of a packet.
234 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
235 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
237 * This value is a hint for the length of the entire packet. It is used
238 * by the chip to optimize internal processing. The packet will be
239 * dropped if the hint is too short. This field is valid only on the
240 * first BD of a packet.
242 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
243 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
244 /* indicates packet length < 512B */
245 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
246 /* indicates 512 <= packet length < 1KB */
247 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
248 /* indicates 1KB <= packet length < 2KB */
249 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
250 /* indicates packet length >= 2KB */
251 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
252 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
254 * If set to 1, the device immediately updates the Send Consumer Index
255 * after the buffer associated with this descriptor has been transferred
256 * via DMA to NIC memory from host memory. An interrupt may or may not
257 * be generated according to the state of the interrupt avoidance
258 * mechanisms. If this bit is set to 0, then the Consumer Index is only
259 * updated as soon as one of the host interrupt coalescing conditions
260 * has been met. This bit must be valid on the first BD of a packet.
262 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
264 * All bits in this field must be valid on the first BD of a packet.
265 * Only the packet_end bit must be valid for the remaining BDs of a
268 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
269 #define TX_BD_LONG_FLAGS_SFT 6
273 * This is the length of the host physical buffer this BD describes in
274 * bytes. This field must be valid on all BDs of a packet.
279 * The opaque data field is pass through to the completion and can be
280 * used for any data that the driver wants to associate with the
281 * transmit BD. This field must be valid on the first BD of a packet.
286 * This is the host physical address for the portion of the packet
287 * described by this TX BD. This value must be valid on all BDs of a
291 } __attribute__((packed));
293 /* last 16 bytes of Long TX BD */
295 struct tx_bd_long_hi {
297 * All bits in this field must be valid on the first BD of a packet.
298 * Their value on other BDs of the packet will be ignored.
301 * If set to 1, the controller replaces the TCP/UPD checksum fields of
302 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
303 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
304 * checksum for the packet associated with this descriptor. This bit
305 * must be valid on the first BD of a packet.
307 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
309 * If set to 1, the controller replaces the IP checksum of the normal
310 * packets, or the inner IP checksum of the encapsulated packets with
311 * the hardware calculated IP checksum for the packet associated with
312 * this descriptor. This bit must be valid on the first BD of a packet.
314 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
316 * If set to 1, the controller will not append an Ethernet CRC to the
317 * end of the frame. This bit must be valid on the first BD of a packet.
318 * Packet must be 64B or longer when this flag is set. It is not useful
319 * to use this bit with any form of TX offload such as CSO or LSO. The
320 * intent is that the packet from the host already has a valid Ethernet
323 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
325 * If set to 1, the device will record the time at which the packet was
326 * actually transmitted at the TX MAC. This bit must be valid on the
327 * first BD of a packet.
329 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
331 * If set to 1, The controller replaces the tunnel IP checksum field
332 * with hardware calculated IP checksum for the IP header of the packet
333 * associated with this descriptor. In case of VXLAN, the controller
334 * also replaces the outer header UDP checksum with hardware calculated
335 * UDP checksum for the packet associated with this descriptor.
337 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
339 * If set to 1, the device will treat this packet with LSO(Large Send
340 * Offload) processing for both normal or encapsulated packets, which is
341 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
342 * fields must be valid. The driver doesn't need to set t_ip_chksum,
343 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
344 * the appropriate checksum fields for segmented packets. When this bit
345 * is 1, the hdr_size and mss fields must be valid.
347 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
349 * If set to zero when LSO is '1', then the IPID will be treated as a
350 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
351 * set to one when LSO is '1', then the IPID will be treated as a 15b
352 * number and will be wrapped if it exceeds a value 0f 0x7fff.
354 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
356 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
357 * will not be modified during LSO operations. If set to one when LSO is
358 * '1', then the IPID of the tunnel IP header will be incremented for
359 * each subsequent segment of an LSO operation.
361 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
363 * If set to '1', then the RoCE ICRC will be appended to the packet.
364 * Packet must be a valid RoCE format packet.
366 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
368 * If set to '1', then the FCoE CRC will be appended to the packet.
369 * Packet must be a valid FCoE format packet.
371 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
375 * When LSO is '1', this field must contain the offset of the TCP
376 * payload from the beginning of the packet in as 16b words. In case of
377 * encapsulated/tunneling packet, this field contains the offset of the
378 * inner TCP payload from beginning of the packet as 16-bit words. This
379 * value must be valid on the first BD of a packet.
381 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
382 #define TX_BD_LONG_HDR_SIZE_SFT 0
386 * This is the MSS value that will be used to do the LSO processing. The
387 * value is the length in bytes of the TCP payload for each segment
388 * generated by the LSO operation. This value must be valid on the first
391 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
392 #define TX_BD_LONG_MSS_SFT 0
398 * This value selects a CFA action to perform on the packet. Set this
399 * value to zero if no CFA action is desired. This value must be valid
400 * on the first BD of a packet.
405 * This value is action meta-data that defines CFA edit operations that
406 * are done in addition to any action editing.
408 /* When key=1, This is the VLAN tag VID value. */
409 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
410 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
411 /* When key=1, This is the VLAN tag DE value. */
412 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
413 /* When key=1, This is the VLAN tag PRI value. */
414 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
415 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
416 /* When key=1, This is the VLAN tag TPID select value. */
417 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
418 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
420 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
422 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
424 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
426 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
428 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
429 /* Value programmed in CFA VLANTPID register. */
430 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
431 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
432 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
433 /* When key=1, This is the VLAN tag TPID select value. */
434 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
435 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
437 * This field identifies the type of edit to be performed on the packet.
438 * This value must be valid on the first BD of a packet.
440 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
441 #define TX_BD_LONG_CFA_META_KEY_SFT 28
443 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
445 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
446 * - PRI/DE value. - meta[11:0] - VID value.
448 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
449 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
451 } __attribute__((packed));
453 /* RX Producer Packet BD (16 bytes) */
454 struct rx_prod_pkt_bd {
455 /* This value identifies the type of buffer descriptor. */
456 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
457 #define RX_PROD_PKT_BD_TYPE_SFT 0
459 * Indicates that this BD is 16B long and is an RX Producer (ie.
460 * empty) buffer descriptor.
462 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT (UINT32_C(0x4) << 0)
464 * If set to 1, the packet will be placed at the address plus 2B. The 2
465 * Bytes of padding will be written as zero.
468 * This is intended to be used when the host buffer is cache-line
469 * aligned to produce packets that are easy to parse in host memory
470 * while still allowing writes to be cache line aligned.
472 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
474 * If set to 1, the packet write will be padded out to the nearest
475 * cache-line with zero value padding.
478 * If receive buffers start/end on cache-line boundaries, this feature
479 * will ensure that all data writes on the PCI bus start/end on cache
482 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
484 * This value is the number of additional buffers in the ring that
485 * describe the buffer space to be consumed for the this packet. If the
486 * value is zero, then the packet must fit within the space described by
487 * this BD. If this value is 1 or more, it indicates how many additional
488 * "buffer" BDs are in the ring immediately following this BD to be used
489 * for the same network packet. Even if the packet to be placed does not
490 * need all the additional buffers, they will be consumed anyway.
492 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
493 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
494 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
495 #define RX_PROD_PKT_BD_FLAGS_SFT 6
499 * This is the length in Bytes of the host physical buffer where data
500 * for the packet may be placed in host memory.
503 * While this is a Byte resolution value, it is often advantageous to
504 * ensure that the buffers provided end on a host cache line.
509 * The opaque data field is pass through to the completion and can be
510 * used for any data that the driver wants to associate with this
511 * receive buffer set.
516 * This is the host physical address where data for the packet may by
517 * placed in host memory.
520 * While this is a Byte resolution value, it is often advantageous to
521 * ensure that the buffers provide start on a host cache line.
524 } __attribute__((packed));
526 /* Completion Ring Structures */
527 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
528 /* Base Completion Record (16 bytes) */
532 * This field indicates the exact type of the completion. By convention,
533 * the LSB identifies the length of the record in 16B units. Even values
534 * indicate 16B records. Odd values indicate 32B records.
536 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
537 #define CMPL_BASE_TYPE_SFT 0
538 /* TX L2 completion: Completion of TX packet. Length = 16B */
539 #define CMPL_BASE_TYPE_TX_L2 (UINT32_C(0x0) << 0)
541 * RX L2 completion: Completion of and L2 RX packet.
544 #define CMPL_BASE_TYPE_RX_L2 (UINT32_C(0x11) << 0)
546 * RX Aggregation Buffer completion : Completion of an L2
547 * aggregation buffer in support of TPA, HDS, or Jumbo packet
548 * completion. Length = 16B
550 #define CMPL_BASE_TYPE_RX_AGG (UINT32_C(0x12) << 0)
552 * RX L2 TPA Start Completion: Completion at the beginning of a
553 * TPA operation. Length = 32B
555 #define CMPL_BASE_TYPE_RX_TPA_START (UINT32_C(0x13) << 0)
557 * RX L2 TPA End Completion: Completion at the end of a TPA
558 * operation. Length = 32B
560 #define CMPL_BASE_TYPE_RX_TPA_END (UINT32_C(0x15) << 0)
562 * Statistics Ejection Completion: Completion of statistics data
563 * ejection buffer. Length = 16B
565 #define CMPL_BASE_TYPE_STAT_EJECT (UINT32_C(0x1a) << 0)
566 /* HWRM Command Completion: Completion of an HWRM command. */
567 #define CMPL_BASE_TYPE_HWRM_DONE (UINT32_C(0x20) << 0)
568 /* Forwarded HWRM Request */
569 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
570 /* Forwarded HWRM Response */
571 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (UINT32_C(0x24) << 0)
572 /* HWRM Asynchronous Event Information */
573 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (UINT32_C(0x2e) << 0)
574 /* CQ Notification */
575 #define CMPL_BASE_TYPE_CQ_NOTIFICATION (UINT32_C(0x30) << 0)
576 /* SRQ Threshold Event */
577 #define CMPL_BASE_TYPE_SRQ_EVENT (UINT32_C(0x32) << 0)
578 /* DBQ Threshold Event */
579 #define CMPL_BASE_TYPE_DBQ_EVENT (UINT32_C(0x34) << 0)
580 /* QP Async Notification */
581 #define CMPL_BASE_TYPE_QP_EVENT (UINT32_C(0x38) << 0)
582 /* Function Async Notification */
583 #define CMPL_BASE_TYPE_FUNC_EVENT (UINT32_C(0x3a) << 0)
590 * This value is written by the NIC such that it will be different for
591 * each pass through the completion queue. The even passes will write 1.
592 * The odd passes will write 0.
594 #define CMPL_BASE_V UINT32_C(0x1)
596 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
597 #define CMPL_BASE_INFO3_SFT 1
601 } __attribute__((packed));
603 /* TX Completion Record (16 bytes) */
606 * This field indicates the exact type of the completion. By convention,
607 * the LSB identifies the length of the record in 16B units. Even values
608 * indicate 16B records. Odd values indicate 32B records.
610 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
611 #define TX_CMPL_TYPE_SFT 0
612 /* TX L2 completion: Completion of TX packet. Length = 16B */
613 #define TX_CMPL_TYPE_TX_L2 (UINT32_C(0x0) << 0)
615 * When this bit is '1', it indicates a packet that has an error of some
616 * type. Type of error is indicated in error_flags.
618 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
620 * When this bit is '1', it indicates that the packet completed was
621 * transmitted using the push acceleration data provided by the driver.
622 * When this bit is '0', it indicates that the packet had not push
623 * acceleration data written or was executed as a normal packet even
624 * though push data was provided.
626 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
627 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
628 #define TX_CMPL_FLAGS_SFT 6
634 * This is a copy of the opaque field from the first TX BD of this
635 * transmitted packet.
640 * This value is written by the NIC such that it will be different for
641 * each pass through the completion queue. The even passes will write 1.
642 * The odd passes will write 0.
644 #define TX_CMPL_V UINT32_C(0x1)
646 * This error indicates that there was some sort of problem with the BDs
649 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
650 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
652 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
653 /* Bad Format: BDs were not formatted correctly. */
654 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
655 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
656 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
658 * When this bit is '1', it indicates that the length of the packet was
659 * zero. No packet was transmitted.
661 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
663 * When this bit is '1', it indicates that the packet was longer than
664 * the programmed limit in TDI. No packet was transmitted.
666 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
668 * When this bit is '1', it indicates that one or more of the BDs
669 * associated with this packet generated a PCI error. This probably
670 * means the address was not valid.
672 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
674 * When this bit is '1', it indicates that the packet was longer than
675 * indicated by the hint. No packet was transmitted.
677 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
679 * When this bit is '1', it indicates that the packet was dropped due to
680 * Poison TLP error on one or more of the TLPs in the PXP completion.
682 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
683 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
684 #define TX_CMPL_ERRORS_SFT 1
689 } __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;
691 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
694 * This field indicates the exact type of the completion. By convention,
695 * the LSB identifies the length of the record in 16B units. Even values
696 * indicate 16B records. Odd values indicate 32B records.
698 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
699 #define RX_PKT_CMPL_TYPE_SFT 0
701 * RX L2 completion: Completion of and L2 RX packet.
704 #define RX_PKT_CMPL_TYPE_RX_L2 (UINT32_C(0x11) << 0)
706 * When this bit is '1', it indicates a packet that has an error of some
707 * type. Type of error is indicated in error_flags.
709 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
710 /* This field indicates how the packet was placed in the buffer. */
711 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
712 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
713 /* Normal: Packet was placed using normal algorithm. */
714 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
715 /* Jumbo: Packet was placed using jumbo algorithm. */
716 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
718 * Header/Data Separation: Packet was placed using Header/Data
719 * separation algorithm. The separation location is indicated by
722 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
723 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
724 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
725 /* This bit is '1' if the RSS field in this completion is valid. */
726 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
728 * This value indicates what the inner packet determined for the packet
731 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
732 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
733 /* Not Known: Indicates that the packet type was not known. */
734 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
736 * IP Packet: Indicates that the packet was an IP packet, but
737 * further classification was not possible.
739 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
741 * TCP Packet: Indicates that the packet was IP and TCP. This
742 * indicates that the payload_offset field is valid.
744 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
746 * UDP Packet: Indicates that the packet was IP and UDP. This
747 * indicates that the payload_offset field is valid.
749 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
751 * FCoE Packet: Indicates that the packet was recognized as a
752 * FCoE. This also indicates that the payload_offset field is
755 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
757 * RoCE Packet: Indicates that the packet was recognized as a
758 * RoCE. This also indicates that the payload_offset field is
761 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
763 * ICMP Packet: Indicates that the packet was recognized as
764 * ICMP. This indicates that the payload_offset field is valid.
766 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
768 * PtP packet wo/timestamp: Indicates that the packet was
769 * recognized as a PtP packet.
771 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
772 (UINT32_C(0x8) << 12)
774 * PtP packet w/timestamp: Indicates that the packet was
775 * recognized as a PtP packet and that a timestamp was taken for
778 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
779 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
780 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
781 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
782 #define RX_PKT_CMPL_FLAGS_SFT 6
786 * This is the length of the data for the packet stored in the buffer(s)
787 * identified by the opaque value. This includes the packet BD and any
788 * associated buffer BDs. This does not include the the length of any
789 * data places in aggregation BDs.
794 * This is a copy of the opaque field from the RX BD this completion
800 * This value is written by the NIC such that it will be different for
801 * each pass through the completion queue. The even passes will write 1.
802 * The odd passes will write 0.
804 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
806 * This value is the number of aggregation buffers that follow this
807 * entry in the completion ring that are a part of this packet. If the
808 * value is zero, then the packet is completely contained in the buffer
809 * space provided for the packet in the RX ring.
811 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
812 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
816 * This is the RSS hash type for the packet. The value is packed
817 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
819 uint8_t rss_hash_type;
822 * This value indicates the offset from the beginning of the packet
823 * where the inner payload starts. This value is valid for TCP, UDP,
824 * FCoE, and RoCE packets.
826 uint8_t payload_offset;
831 * This value is the RSS hash value calculated for the packet based on
832 * the mode bits and key value in the VNIC.
835 } __attribute__((packed));
837 /* last 16 bytes of RX Packet Completion Record */
838 struct rx_pkt_cmpl_hi {
840 * This indicates that the ip checksum was calculated for the inner
841 * packet and that the ip_cs_error field indicates if there was an
844 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
846 * This indicates that the TCP, UDP or ICMP checksum was calculated for
847 * the inner packet and that the l4_cs_error field indicates if there
850 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
852 * This indicates that the ip checksum was calculated for the tunnel
853 * header and that the t_ip_cs_error field indicates if there was an
856 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
858 * This indicates that the UDP checksum was calculated for the tunnel
859 * packet and that the t_l4_cs_error field indicates if there was an
862 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
863 /* This value indicates what format the metadata field is. */
864 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
865 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
866 /* No metadata informtaion. Value is zero. */
867 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
869 * The metadata field contains the VLAN tag and TPID value. -
870 * metadata[11:0] contains the vlan VID value. - metadata[12]
871 * contains the vlan DE value. - metadata[15:13] contains the
872 * vlan PRI value. - metadata[31:16] contains the vlan TPID
875 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
876 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
877 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
879 * This field indicates the IP type for the inner-most IP header. A
880 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
881 * value is only valid if itype indicates a packet with an IP header.
883 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
887 * This is data from the CFA block as indicated by the meta_format
890 /* When meta_format=1, this value is the VLAN VID. */
891 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
892 #define RX_PKT_CMPL_METADATA_VID_SFT 0
893 /* When meta_format=1, this value is the VLAN DE. */
894 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
895 /* When meta_format=1, this value is the VLAN PRI. */
896 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
897 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
898 /* When meta_format=1, this value is the VLAN TPID. */
899 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
900 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
904 * This value is written by the NIC such that it will be different for
905 * each pass through the completion queue. The even passes will write 1.
906 * The odd passes will write 0.
908 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
910 * This error indicates that there was some sort of problem with the BDs
911 * for the packet that was found after part of the packet was already
912 * placed. The packet should be treated as invalid.
914 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
915 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
916 /* No buffer error */
917 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
920 * Did Not Fit: Packet did not fit into packet buffer provided.
921 * For regular placement, this means the packet did not fit in
922 * the buffer provided. For HDS and jumbo placement, this means
923 * that the packet could not be placed into 7 physical buffers
926 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
929 * Not On Chip: All BDs needed for the packet were not on-chip
930 * when the packet arrived.
932 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
934 /* Bad Format: BDs were not formatted correctly. */
935 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
937 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
938 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
939 /* This indicates that there was an error in the IP header checksum. */
940 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
942 * This indicates that there was an error in the TCP, UDP or ICMP
945 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
947 * This indicates that there was an error in the tunnel IP header
950 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
951 /* This indicates that there was an error in the tunnel UDP checksum. */
952 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
954 * This indicates that there was a CRC error on either an FCoE or RoCE
955 * packet. The itype indicates the packet type.
957 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
959 * This indicates that there was an error in the tunnel portion of the
960 * packet when this field is non-zero.
962 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
963 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
965 * No additional error occurred on the tunnel portion of the
966 * packet of the packet does not have a tunnel.
968 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
970 * Indicates that IP header version does not match expectation
971 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
973 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
976 * Indicates that header length is out of range in the tunnel
977 * header. Valid for IPv4.
979 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
982 * Indicates that the physical packet is shorter than that
983 * claimed by the PPPoE header length for a tunnel PPPoE packet.
985 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
988 * Indicates that physical packet is shorter than that claimed
989 * by the tunnel l3 header length. Valid for IPv4, or IPv6
990 * tunnel packet packets.
992 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
995 * Indicates that the physical packet is shorter than that
996 * claimed by the tunnel UDP header length for a tunnel UDP
997 * packet that is not fragmented.
999 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
1000 (UINT32_C(0x5) << 9)
1002 * indicates that the IPv4 TTL or IPv6 hop limit check have
1003 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
1006 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
1007 (UINT32_C(0x6) << 9)
1008 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
1009 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1011 * This indicates that there was an error in the inner portion of the
1012 * packet when this field is non-zero.
1014 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1015 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1017 * No additional error occurred on the tunnel portion of the
1018 * packet of the packet does not have a tunnel.
1020 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1022 * Indicates that IP header version does not match expectation
1023 * from L2 Ethertype for IPv4 and IPv6 or that option other than
1024 * VFT was parsed on FCoE packet.
1026 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
1027 (UINT32_C(0x1) << 12)
1029 * indicates that header length is out of range. Valid for IPv4
1032 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
1033 (UINT32_C(0x2) << 12)
1035 * indicates that the IPv4 TTL or IPv6 hop limit check have
1036 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
1038 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1040 * Indicates that physical packet is shorter than that claimed
1041 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
1044 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
1045 (UINT32_C(0x4) << 12)
1047 * Indicates that the physical packet is shorter than that
1048 * claimed by the UDP header length for a UDP packet that is not
1051 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
1052 (UINT32_C(0x5) << 12)
1054 * Indicates that TCP header length > IP payload. Valid for TCP
1057 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
1058 (UINT32_C(0x6) << 12)
1059 /* Indicates that TCP header length < 5. Valid for TCP. */
1060 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
1061 (UINT32_C(0x7) << 12)
1063 * Indicates that TCP option headers result in a TCP header size
1064 * that does not match data offset in TCP header. Valid for TCP.
1066 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
1067 (UINT32_C(0x8) << 12)
1068 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
1069 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1070 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1071 #define RX_PKT_CMPL_ERRORS_SFT 1
1075 * This field identifies the CFA action rule that was used for this
1081 * This value holds the reordering sequence number for the packet. If
1082 * the reordering sequence is not valid, then this value is zero. The
1083 * reordering domain for the packet is in the bottom 8 to 10b of the
1084 * rss_hash value. The bottom 20b of this value contain the ordering
1085 * domain value for the packet.
1087 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1088 #define RX_PKT_CMPL_REORDER_SFT 0
1090 } __attribute__((packed));
1092 /* HWRM Forwarded Request (16 bytes) */
1093 struct hwrm_fwd_req_cmpl {
1094 /* Length of forwarded request in bytes. */
1096 * This field indicates the exact type of the completion. By convention,
1097 * the LSB identifies the length of the record in 16B units. Even values
1098 * indicate 16B records. Odd values indicate 32B records.
1100 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
1101 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
1102 /* Forwarded HWRM Request */
1103 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
1104 /* Length of forwarded request in bytes. */
1105 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1106 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1107 uint16_t req_len_type;
1110 * Source ID of this request. Typically used in forwarding requests and
1111 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1112 * Reserved for internal processors 0xFFFF - HWRM
1118 /* Address of forwarded request. */
1120 * This value is written by the NIC such that it will be different for
1121 * each pass through the completion queue. The even passes will write 1.
1122 * The odd passes will write 0.
1124 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
1125 /* Address of forwarded request. */
1126 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1127 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1128 uint64_t req_buf_addr_v;
1129 } __attribute__((packed));
1131 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1132 struct hwrm_async_event_cmpl {
1134 * This field indicates the exact type of the completion. By convention,
1135 * the LSB identifies the length of the record in 16B units. Even values
1136 * indicate 16B records. Odd values indicate 32B records.
1138 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1139 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1140 /* HWRM Asynchronous Event Information */
1141 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT \
1142 (UINT32_C(0x2e) << 0)
1145 /* Identifiers of events. */
1146 /* Link status changed */
1147 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
1148 (UINT32_C(0x0) << 0)
1149 /* Link MTU changed */
1150 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
1151 (UINT32_C(0x1) << 0)
1152 /* Link speed changed */
1153 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
1154 (UINT32_C(0x2) << 0)
1155 /* DCB Configuration changed */
1156 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
1157 (UINT32_C(0x3) << 0)
1158 /* Port connection not allowed */
1159 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
1160 (UINT32_C(0x4) << 0)
1161 /* Link speed configuration was not allowed */
1162 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
1163 (UINT32_C(0x5) << 0)
1164 /* Function driver unloaded */
1165 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
1166 (UINT32_C(0x10) << 0)
1167 /* Function driver loaded */
1168 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
1169 (UINT32_C(0x11) << 0)
1170 /* PF driver unloaded */
1171 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
1172 (UINT32_C(0x20) << 0)
1173 /* PF driver loaded */
1174 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
1175 (UINT32_C(0x21) << 0)
1176 /* VF Function Level Reset (FLR) */
1177 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (UINT32_C(0x30) << 0)
1178 /* VF MAC Address Change */
1179 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
1180 (UINT32_C(0x31) << 0)
1181 /* PF-VF communication channel status change. */
1182 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
1183 (UINT32_C(0x32) << 0)
1185 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
1186 (UINT32_C(0xff) << 0)
1189 /* Event specific data */
1190 uint32_t event_data2;
1194 * This value is written by the NIC such that it will be different for
1195 * each pass through the completion queue. The even passes will write 1.
1196 * The odd passes will write 0.
1198 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1200 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1201 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1204 /* 8-lsb timestamp from POR (100-msec resolution) */
1205 uint8_t timestamp_lo;
1207 /* 16-lsb timestamp from POR (100-msec resolution) */
1208 uint16_t timestamp_hi;
1210 /* Event specific data */
1211 uint32_t event_data1;
1212 } __attribute__((packed));
1215 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
1216 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
1217 * processors inside the chip. This firmware is vital part of the chip's
1218 * hardware. The chip can not be used by driver without it.
1221 /* Input (16 bytes) */
1224 * This value indicates what type of request this is. The format for the
1225 * rest of the command is determined by this field.
1230 * This value indicates the what completion ring the request will be
1231 * optionally completed on. If the value is -1, then no CR completion
1232 * will be generated. Any other value must be a valid CR ring_id value
1233 * for this function.
1237 /* This value indicates the command sequence number. */
1241 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1242 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1247 * This is the host address where the response will be written when the
1248 * request is complete. This area must be 16B aligned and must be
1249 * cleared to zero before the request is made.
1252 } __attribute__((packed));
1254 /* Output (8 bytes) */
1257 * Pass/Fail or error type Note: receiver to verify the in parameters,
1258 * and fail the call with an error when appropriate
1260 uint16_t error_code;
1262 /* This field returns the type of original request. */
1265 /* This field provides original sequence number of the command. */
1269 * This field is the length of the response in bytes. The last byte of
1270 * the response is a valid flag that will read as '1' when the command
1271 * has been completely written to memory.
1274 } __attribute__((packed));
1276 /* hwrm_cfa_l2_filter_alloc */
1278 * A filter is used to identify traffic that contains a matching set of
1279 * parameters like unicast or broadcast MAC address or a VLAN tag amongst
1280 * other things which then allows the ASIC to direct the incoming traffic
1281 * to an appropriate VNIC or Rx ring.
1284 /* Input (96 bytes) */
1285 struct hwrm_cfa_l2_filter_alloc_input {
1287 * This value indicates what type of request this is. The format for the
1288 * rest of the command is determined by this field.
1293 * This value indicates the what completion ring the request will be
1294 * optionally completed on. If the value is -1, then no CR completion
1295 * will be generated. Any other value must be a valid CR ring_id value
1296 * for this function.
1300 /* This value indicates the command sequence number. */
1304 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1305 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1310 * This is the host address where the response will be written when the
1311 * request is complete. This area must be 16B aligned and must be
1312 * cleared to zero before the request is made.
1317 * Enumeration denoting the RX, TX type of the resource. This
1318 * enumeration is used for resources that are similar for both TX and RX
1319 * paths of the chip.
1321 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
1324 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
1325 (UINT32_C(0x0) << 0)
1327 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
1328 (UINT32_C(0x1) << 0)
1329 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
1330 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
1332 * Setting of this flag indicates the applicability to the loopback
1335 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
1338 * Setting of this flag indicates drop action. If this flag is not set,
1339 * then it should be considered accept action.
1341 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
1344 * If this flag is set, all t_l2_* fields are invalid and they should
1345 * not be specified. If this flag is set, then l2_* fields refer to
1346 * fields of outermost L2 header.
1348 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
1352 /* This bit must be '1' for the l2_addr field to be configured. */
1353 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
1355 /* This bit must be '1' for the l2_addr_mask field to be configured. */
1356 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
1358 /* This bit must be '1' for the l2_ovlan field to be configured. */
1359 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
1361 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
1362 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
1364 /* This bit must be '1' for the l2_ivlan field to be configured. */
1365 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
1367 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
1368 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
1370 /* This bit must be '1' for the t_l2_addr field to be configured. */
1371 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
1374 * This bit must be '1' for the t_l2_addr_mask field to be configured.
1376 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
1378 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
1379 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
1382 * This bit must be '1' for the t_l2_ovlan_mask field to be configured.
1384 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
1386 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
1387 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
1390 * This bit must be '1' for the t_l2_ivlan_mask field to be configured.
1392 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
1394 /* This bit must be '1' for the src_type field to be configured. */
1395 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
1397 /* This bit must be '1' for the src_id field to be configured. */
1398 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
1400 /* This bit must be '1' for the tunnel_type field to be configured. */
1401 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
1403 /* This bit must be '1' for the dst_id field to be configured. */
1404 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
1407 * This bit must be '1' for the mirror_vnic_id field to be configured.
1409 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
1414 * This value sets the match value for the L2 MAC address. Destination
1415 * MAC address for RX path. Source MAC address for TX path.
1423 * This value sets the mask value for the L2 address. A value of 0 will
1424 * mask the corresponding bit from compare.
1426 uint8_t l2_addr_mask[6];
1428 /* This value sets VLAN ID value for outer VLAN. */
1432 * This value sets the mask value for the ovlan id. A value of 0 will
1433 * mask the corresponding bit from compare.
1435 uint16_t l2_ovlan_mask;
1437 /* This value sets VLAN ID value for inner VLAN. */
1441 * This value sets the mask value for the ivlan id. A value of 0 will
1442 * mask the corresponding bit from compare.
1444 uint16_t l2_ivlan_mask;
1450 * This value sets the match value for the tunnel L2 MAC address.
1451 * Destination MAC address for RX path. Source MAC address for TX path.
1453 uint8_t t_l2_addr[6];
1459 * This value sets the mask value for the tunnel L2 address. A value of
1460 * 0 will mask the corresponding bit from compare.
1462 uint8_t t_l2_addr_mask[6];
1464 /* This value sets VLAN ID value for tunnel outer VLAN. */
1465 uint16_t t_l2_ovlan;
1468 * This value sets the mask value for the tunnel ovlan id. A value of 0
1469 * will mask the corresponding bit from compare.
1471 uint16_t t_l2_ovlan_mask;
1473 /* This value sets VLAN ID value for tunnel inner VLAN. */
1474 uint16_t t_l2_ivlan;
1477 * This value sets the mask value for the tunnel ivlan id. A value of 0
1478 * will mask the corresponding bit from compare.
1480 uint16_t t_l2_ivlan_mask;
1482 /* This value identifies the type of source of the packet. */
1484 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \
1485 (UINT32_C(0x0) << 0)
1486 /* Physical function */
1487 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \
1488 (UINT32_C(0x1) << 0)
1489 /* Virtual function */
1490 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \
1491 (UINT32_C(0x2) << 0)
1492 /* Virtual NIC of a function */
1493 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \
1494 (UINT32_C(0x3) << 0)
1495 /* Embedded processor for CFA management */
1496 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \
1497 (UINT32_C(0x4) << 0)
1498 /* Embedded processor for OOB management */
1499 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \
1500 (UINT32_C(0x5) << 0)
1501 /* Embedded processor for RoCE */
1502 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \
1503 (UINT32_C(0x6) << 0)
1504 /* Embedded processor for network proxy functions */
1505 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \
1506 (UINT32_C(0x7) << 0)
1511 * This value is the id of the source. For a network port, it represents
1512 * port_id. For a physical function, it represents fid. For a virtual
1513 * function, it represents vf_id. For a vnic, it represents vnic_id. For
1514 * embedded processors, this id is not valid. Notes: 1. The function ID
1515 * is implied if it src_id is not provided for a src_type that is either
1521 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
1522 (UINT32_C(0x0) << 0)
1523 /* Virtual eXtensible Local Area Network (VXLAN) */
1524 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
1525 (UINT32_C(0x1) << 0)
1527 * Network Virtualization Generic Routing Encapsulation (NVGRE)
1529 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
1530 (UINT32_C(0x2) << 0)
1532 * Generic Routing Encapsulation (GRE) inside Ethernet payload
1534 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
1535 (UINT32_C(0x3) << 0)
1537 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
1538 (UINT32_C(0x4) << 0)
1539 /* Generic Network Virtualization Encapsulation (Geneve) */
1540 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
1541 (UINT32_C(0x5) << 0)
1542 /* Multi-Protocol Lable Switching (MPLS) */
1543 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
1544 (UINT32_C(0x6) << 0)
1545 /* Stateless Transport Tunnel (STT) */
1546 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
1547 (UINT32_C(0x7) << 0)
1549 * Generic Routing Encapsulation (GRE) inside IP datagram
1552 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
1553 (UINT32_C(0x8) << 0)
1554 /* Any tunneled traffic */
1555 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
1556 (UINT32_C(0xff) << 0)
1557 uint8_t tunnel_type;
1562 * If set, this value shall represent the Logical VNIC ID of the
1563 * destination VNIC for the RX path and network port id of the
1564 * destination port for the TX path.
1568 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
1569 uint16_t mirror_vnic_id;
1572 * This hint is provided to help in placing the filter in the filter
1576 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
1577 (UINT32_C(0x0) << 0)
1578 /* Above the given filter */
1579 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
1580 (UINT32_C(0x1) << 0)
1581 /* Below the given filter */
1582 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
1583 (UINT32_C(0x2) << 0)
1584 /* As high as possible */
1585 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
1586 (UINT32_C(0x3) << 0)
1587 /* As low as possible */
1588 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
1589 (UINT32_C(0x4) << 0)
1596 * This is the ID of the filter that goes along with the pri_hint. This
1597 * field is valid only for the following values. 1 - Above the given
1598 * filter 2 - Below the given filter
1600 uint64_t l2_filter_id_hint;
1601 } __attribute__((packed));
1603 /* Output (24 bytes) */
1604 struct hwrm_cfa_l2_filter_alloc_output {
1606 * Pass/Fail or error type Note: receiver to verify the in parameters,
1607 * and fail the call with an error when appropriate
1609 uint16_t error_code;
1611 /* This field returns the type of original request. */
1614 /* This field provides original sequence number of the command. */
1618 * This field is the length of the response in bytes. The last byte of
1619 * the response is a valid flag that will read as '1' when the command
1620 * has been completely written to memory.
1625 * This value identifies a set of CFA data structures used for an L2
1628 uint64_t l2_filter_id;
1631 * This is the ID of the flow associated with this filter. This value
1632 * shall be used to match and associate the flow identifier returned in
1633 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
1642 * This field is used in Output records to indicate that the output is
1643 * completely written to RAM. This field should be read as '1' to
1644 * indicate that the output has been completely written. When writing a
1645 * command completion or response to an internal processor, the order of
1646 * writes has to be such that this field is written last.
1649 } __attribute__((packed));
1651 /* hwrm_cfa_l2_filter_free */
1653 * Description: Free a L2 filter. The HWRM shall free all associated filter
1654 * resources with the L2 filter.
1657 /* Input (24 bytes) */
1658 struct hwrm_cfa_l2_filter_free_input {
1660 * This value indicates what type of request this is. The format for the
1661 * rest of the command is determined by this field.
1666 * This value indicates the what completion ring the request will be
1667 * optionally completed on. If the value is -1, then no CR completion
1668 * will be generated. Any other value must be a valid CR ring_id value
1669 * for this function.
1673 /* This value indicates the command sequence number. */
1677 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1678 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1683 * This is the host address where the response will be written when the
1684 * request is complete. This area must be 16B aligned and must be
1685 * cleared to zero before the request is made.
1690 * This value identifies a set of CFA data structures used for an L2
1693 uint64_t l2_filter_id;
1694 } __attribute__((packed));
1696 /* Output (16 bytes) */
1697 struct hwrm_cfa_l2_filter_free_output {
1699 * Pass/Fail or error type Note: receiver to verify the in parameters,
1700 * and fail the call with an error when appropriate
1702 uint16_t error_code;
1704 /* This field returns the type of original request. */
1707 /* This field provides original sequence number of the command. */
1711 * This field is the length of the response in bytes. The last byte of
1712 * the response is a valid flag that will read as '1' when the command
1713 * has been completely written to memory.
1723 * This field is used in Output records to indicate that the output is
1724 * completely written to RAM. This field should be read as '1' to
1725 * indicate that the output has been completely written. When writing a
1726 * command completion or response to an internal processor, the order of
1727 * writes has to be such that this field is written last.
1730 } __attribute__((packed));
1732 /* hwrm_exec_fwd_resp */
1734 * Description: This command is used to send an encapsulated request to the
1735 * HWRM. This command instructs the HWRM to execute the request and forward the
1736 * response of the encapsulated request to the location specified in the
1737 * original request that is encapsulated. The target id of this command shall be
1738 * set to 0xFFFF (HWRM). The response location in this command shall be used to
1739 * acknowledge the receipt of the encapsulated request and forwarding of the
1743 /* Input (128 bytes) */
1744 struct hwrm_exec_fwd_resp_input {
1746 * This value indicates what type of request this is. The format for the
1747 * rest of the command is determined by this field.
1752 * This value indicates the what completion ring the request will be
1753 * optionally completed on. If the value is -1, then no CR completion
1754 * will be generated. Any other value must be a valid CR ring_id value
1755 * for this function.
1759 /* This value indicates the command sequence number. */
1763 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1764 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1769 * This is the host address where the response will be written when the
1770 * request is complete. This area must be 16B aligned and must be
1771 * cleared to zero before the request is made.
1776 * This is an encapsulated request. This request should be executed by
1777 * the HWRM and the response should be provided in the response buffer
1778 * inside the encapsulated request.
1780 uint32_t encap_request[26];
1783 * This value indicates the target id of the response to the
1784 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
1785 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1787 uint16_t encap_resp_target_id;
1789 uint16_t unused_0[3];
1790 } __attribute__((packed));
1792 /* Output (16 bytes) */
1793 struct hwrm_exec_fwd_resp_output {
1795 * Pass/Fail or error type Note: receiver to verify the in parameters,
1796 * and fail the call with an error when appropriate
1798 uint16_t error_code;
1800 /* This field returns the type of original request. */
1803 /* This field provides original sequence number of the command. */
1807 * This field is the length of the response in bytes. The last byte of
1808 * the response is a valid flag that will read as '1' when the command
1809 * has been completely written to memory.
1819 * This field is used in Output records to indicate that the output is
1820 * completely written to RAM. This field should be read as '1' to
1821 * indicate that the output has been completely written. When writing a
1822 * command completion or response to an internal processor, the order of
1823 * writes has to be such that this field is written last.
1826 } __attribute__((packed));
1828 /* hwrm_func_qcaps */
1830 * Description: This command returns capabilities of a function. The input FID
1831 * value is used to indicate what function is being queried. This allows a
1832 * physical function driver to query virtual functions that are children of the
1833 * physical function. The output FID value is needed to configure Rings and
1834 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
1837 /* Input (24 bytes) */
1838 struct hwrm_func_qcaps_input {
1840 * This value indicates what type of request this is. The format for the
1841 * rest of the command is determined by this field.
1846 * This value indicates the what completion ring the request will be
1847 * optionally completed on. If the value is -1, then no CR completion
1848 * will be generated. Any other value must be a valid CR ring_id value
1849 * for this function.
1853 /* This value indicates the command sequence number. */
1857 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1858 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1863 * This is the host address where the response will be written when the
1864 * request is complete. This area must be 16B aligned and must be
1865 * cleared to zero before the request is made.
1870 * Function ID of the function that is being queried. 0xFF... (All Fs)
1871 * if the query is for the requesting function.
1875 uint16_t unused_0[3];
1876 } __attribute__((packed));
1878 /* Output (80 bytes) */
1879 struct hwrm_func_qcaps_output {
1881 * Pass/Fail or error type Note: receiver to verify the in parameters,
1882 * and fail the call with an error when appropriate
1884 uint16_t error_code;
1886 /* This field returns the type of original request. */
1889 /* This field provides original sequence number of the command. */
1893 * This field is the length of the response in bytes. The last byte of
1894 * the response is a valid flag that will read as '1' when the command
1895 * has been completely written to memory.
1900 * FID value. This value is used to identify operations on the PCI bus
1901 * as belonging to a particular PCI function.
1906 * Port ID of port that this function is associated with. Valid only for
1907 * the PF. 0xFF... (All Fs) if this function is not associated with any
1908 * port. 0xFF... (All Fs) if this function is called from a VF.
1912 /* If 1, then Push mode is supported on this function. */
1913 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
1915 * If 1, then the global MSI-X auto-masking is enabled for the device.
1917 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
1920 * If 1, then the Precision Time Protocol (PTP) processing is supported
1921 * on this function. The HWRM should enable PTP on only a single
1922 * Physical Function (PF) per port.
1924 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
1928 * This value is current MAC address configured for this function. A
1929 * value of 00-00-00-00-00-00 indicates no MAC address is currently
1932 uint8_t perm_mac_address[6];
1935 * The maximum number of RSS/COS contexts that can be allocated to the
1938 uint16_t max_rsscos_ctx;
1941 * The maximum number of completion rings that can be allocated to the
1944 uint16_t max_cmpl_rings;
1947 * The maximum number of transmit rings that can be allocated to the
1950 uint16_t max_tx_rings;
1953 * The maximum number of receive rings that can be allocated to the
1956 uint16_t max_rx_rings;
1959 * The maximum number of L2 contexts that can be allocated to the
1962 uint16_t max_l2_ctxs;
1964 /* The maximum number of VNICs that can be allocated to the function. */
1968 * The identifier for the first VF enabled on a PF. This is valid only
1969 * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is
1970 * called on a PF with SR-IOV disabled or on a VF.
1972 uint16_t first_vf_id;
1975 * The maximum number of VFs that can be allocated to the function. This
1976 * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this
1977 * command is called on a PF with SR-IOV disabled or on a VF.
1982 * The maximum number of statistic contexts that can be allocated to the
1985 uint16_t max_stat_ctx;
1988 * The maximum number of Encapsulation records that can be offloaded by
1991 uint32_t max_encap_records;
1994 * The maximum number of decapsulation records that can be offloaded by
1997 uint32_t max_decap_records;
2000 * The maximum number of Exact Match (EM) flows that can be offloaded by
2001 * this function on the TX side.
2003 uint32_t max_tx_em_flows;
2006 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2007 * by this function on the TX side.
2009 uint32_t max_tx_wm_flows;
2012 * The maximum number of Exact Match (EM) flows that can be offloaded by
2013 * this function on the RX side.
2015 uint32_t max_rx_em_flows;
2018 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2019 * by this function on the RX side.
2021 uint32_t max_rx_wm_flows;
2024 * The maximum number of multicast filters that can be supported by this
2025 * function on the RX side.
2027 uint32_t max_mcast_filters;
2030 * The maximum value of flow_id that can be supported in completion
2033 uint32_t max_flow_id;
2036 * The maximum number of HW ring groups that can be supported on this
2039 uint32_t max_hw_ring_grps;
2046 * This field is used in Output records to indicate that the output is
2047 * completely written to RAM. This field should be read as '1' to
2048 * indicate that the output has been completely written. When writing a
2049 * command completion or response to an internal processor, the order of
2050 * writes has to be such that this field is written last.
2053 } __attribute__((packed));
2055 /* hwrm_func_reset */
2057 * Description: This command resets a hardware function (PCIe function) and
2058 * frees any resources used by the function. This command shall be initiated by
2059 * the driver after an FLR has occurred to prepare the function for re-use. This
2060 * command may also be initiated by a driver prior to doing it's own
2061 * configuration. This command puts the function into the reset state. In the
2062 * reset state, global and port related features of the chip are not available.
2065 * Note: This command will reset a function that has already been disabled or
2066 * idled. The command returns all the resources owned by the function so a new
2067 * driver may allocate and configure resources normally.
2070 /* Input (24 bytes) */
2071 struct hwrm_func_reset_input {
2073 * This value indicates what type of request this is. The format for the
2074 * rest of the command is determined by this field.
2079 * This value indicates the what completion ring the request will be
2080 * optionally completed on. If the value is -1, then no CR completion
2081 * will be generated. Any other value must be a valid CR ring_id value
2082 * for this function.
2086 /* This value indicates the command sequence number. */
2090 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2091 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2096 * This is the host address where the response will be written when the
2097 * request is complete. This area must be 16B aligned and must be
2098 * cleared to zero before the request is made.
2102 /* This bit must be '1' for the vf_id_valid field to be configured. */
2103 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID \
2108 * The ID of the VF that this PF is trying to reset. Only the parent PF
2109 * shall be allowed to reset a child VF. A parent PF driver shall use
2110 * this field only when a specific child VF is requested to be reset.
2114 /* This value indicates the level of a function reset. */
2116 * Reset the caller function and its children VFs (if any). If
2117 * no children functions exist, then reset the caller function
2120 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
2121 (UINT32_C(0x0) << 0)
2122 /* Reset the caller function only */
2123 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
2124 (UINT32_C(0x1) << 0)
2126 * Reset all children VFs of the caller function driver if the
2127 * caller is a PF driver. It is an error to specify this level
2128 * by a VF driver. It is an error to specify this level by a PF
2129 * driver with no children VFs.
2131 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
2132 (UINT32_C(0x2) << 0)
2134 * Reset a specific VF of the caller function driver if the
2135 * caller is the parent PF driver. It is an error to specify
2136 * this level by a VF driver. It is an error to specify this
2137 * level by a PF driver that is not the parent of the VF that is
2138 * being requested to reset.
2140 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
2141 (UINT32_C(0x3) << 0)
2142 uint8_t func_reset_level;
2145 } __attribute__((packed));
2147 /* Output (16 bytes) */
2148 struct hwrm_func_reset_output {
2150 * Pass/Fail or error type Note: receiver to verify the in parameters,
2151 * and fail the call with an error when appropriate
2153 uint16_t error_code;
2155 /* This field returns the type of original request. */
2158 /* This field provides original sequence number of the command. */
2162 * This field is the length of the response in bytes. The last byte of
2163 * the response is a valid flag that will read as '1' when the command
2164 * has been completely written to memory.
2174 * This field is used in Output records to indicate that the output is
2175 * completely written to RAM. This field should be read as '1' to
2176 * indicate that the output has been completely written. When writing a
2177 * command completion or response to an internal processor, the order of
2178 * writes has to be such that this field is written last.
2181 } __attribute__((packed));
2183 /* hwrm_port_phy_cfg */
2185 * Description: This command configures the PHY device for the port. It allows
2186 * setting of the most generic settings for the PHY. The HWRM shall complete
2187 * this command as soon as PHY settings are configured. They may not be applied
2188 * when the command response is provided. A VF driver shall not be allowed to
2189 * configure PHY using this command. In a network partition mode, a PF driver
2190 * shall not be allowed to configure PHY using this command.
2193 /* Input (56 bytes) */
2194 struct hwrm_port_phy_cfg_input {
2196 * This value indicates what type of request this is. The format for the
2197 * rest of the command is determined by this field.
2202 * This value indicates the what completion ring the request will be
2203 * optionally completed on. If the value is -1, then no CR completion
2204 * will be generated. Any other value must be a valid CR ring_id value
2205 * for this function.
2209 /* This value indicates the command sequence number. */
2213 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2214 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2219 * This is the host address where the response will be written when the
2220 * request is complete. This area must be 16B aligned and must be
2221 * cleared to zero before the request is made.
2226 * When this bit is set to '1', the PHY for the port shall be reset. #
2227 * If this bit is set to 1, then the HWRM shall reset the PHY after
2228 * applying PHY configuration changes specified in this command. # In
2229 * order to guarantee that PHY configuration changes specified in this
2230 * command take effect, the HWRM client should set this flag to 1. # If
2231 * this bit is not set to 1, then the HWRM may reset the PHY depending
2232 * on the current PHY configuration and settings specified in this
2235 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
2237 * When this bit is set to '1', the link shall be forced to be taken
2238 * down. # When this bit is set to '1", all other command input settings
2239 * related to the link speed shall be ignored. Once the link state is
2240 * forced down, it can be explicitly cleared from that state by setting
2241 * this flag to '0'. # If this flag is set to '0', then the link shall
2242 * be cleared from forced down state if the link is in forced down
2243 * state. There may be conditions (e.g. out-of-band or sideband
2244 * configuration changes for the link) outside the scope of the HWRM
2245 * implementation that may clear forced down link state.
2247 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
2249 * When this bit is set to '1', the link shall be forced to the
2250 * force_link_speed value. When this bit is set to '1', the HWRM client
2251 * should not enable any of the auto negotiation related fields
2252 * represented by auto_XXX fields in this command. When this bit is set
2253 * to '1' and the HWRM client has enabled a auto_XXX field in this
2254 * command, then the HWRM shall ignore the enabled auto_XXX field. When
2255 * this bit is set to zero, the link shall be allowed to autoneg.
2257 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
2259 * When this bit is set to '1', the auto-negotiation process shall be
2260 * restarted on the link.
2262 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
2264 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2265 * requested to be enabled on this link. If EEE is not supported on this
2266 * port, then this flag shall be ignored by the HWRM.
2268 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
2270 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2271 * requested to be disabled on this link. If EEE is not supported on
2272 * this port, then this flag shall be ignored by the HWRM.
2274 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
2276 * When this bit is set to '1' and EEE is enabled on this link, then TX
2277 * LPI is requested to be enabled on the link. If EEE is not supported
2278 * on this port, then this flag shall be ignored by the HWRM. If EEE is
2279 * disabled on this port, then this flag shall be ignored by the HWRM.
2281 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
2284 /* This bit must be '1' for the auto_mode field to be configured. */
2285 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
2286 /* This bit must be '1' for the auto_duplex field to be configured. */
2287 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
2288 /* This bit must be '1' for the auto_pause field to be configured. */
2289 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
2291 * This bit must be '1' for the auto_link_speed field to be configured.
2293 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
2295 * This bit must be '1' for the auto_link_speed_mask field to be
2298 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
2300 /* This bit must be '1' for the wirespeed field to be configured. */
2301 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
2302 /* This bit must be '1' for the lpbk field to be configured. */
2303 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
2304 /* This bit must be '1' for the preemphasis field to be configured. */
2305 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
2306 /* This bit must be '1' for the force_pause field to be configured. */
2307 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
2309 * This bit must be '1' for the eee_link_speed_mask field to be
2312 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
2314 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
2315 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
2318 /* Port ID of port that is to be configured. */
2322 * This is the speed that will be used if the force bit is '1'. If
2323 * unsupported speed is selected, an error will be generated.
2325 /* 100Mb link speed */
2326 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
2327 (UINT32_C(0x1) << 0)
2328 /* 1Gb link speed */
2329 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
2330 (UINT32_C(0xa) << 0)
2331 /* 2Gb link speed */
2332 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
2333 (UINT32_C(0x14) << 0)
2334 /* 2.5Gb link speed */
2335 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
2336 (UINT32_C(0x19) << 0)
2337 /* 10Gb link speed */
2338 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
2339 (UINT32_C(0x64) << 0)
2340 /* 20Mb link speed */
2341 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
2342 (UINT32_C(0xc8) << 0)
2343 /* 25Gb link speed */
2344 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
2345 (UINT32_C(0xfa) << 0)
2346 /* 40Gb link speed */
2347 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
2348 (UINT32_C(0x190) << 0)
2349 /* 50Gb link speed */
2350 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
2351 (UINT32_C(0x1f4) << 0)
2352 /* 100Gb link speed */
2353 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
2354 (UINT32_C(0x3e8) << 0)
2355 /* 10Mb link speed */
2356 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
2357 (UINT32_C(0xffff) << 0)
2358 uint16_t force_link_speed;
2361 * This value is used to identify what autoneg mode is used when the
2362 * link speed is not being forced.
2365 * Disable autoneg or autoneg disabled. No speeds are selected.
2367 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
2368 /* Select all possible speeds for autoneg mode. */
2369 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
2370 (UINT32_C(0x1) << 0)
2372 * Select only the auto_link_speed speed for autoneg mode. This
2373 * mode has been DEPRECATED. An HWRM client should not use this
2376 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
2377 (UINT32_C(0x2) << 0)
2379 * Select the auto_link_speed or any speed below that speed for
2380 * autoneg. This mode has been DEPRECATED. An HWRM client should
2381 * not use this mode.
2383 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
2384 (UINT32_C(0x3) << 0)
2386 * Select the speeds based on the corresponding link speed mask
2387 * value that is provided.
2389 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
2390 (UINT32_C(0x4) << 0)
2394 * This is the duplex setting that will be used if the autoneg_mode is
2395 * "one_speed" or "one_or_below".
2397 /* Half Duplex will be requested. */
2398 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
2399 (UINT32_C(0x0) << 0)
2400 /* Full duplex will be requested. */
2401 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
2402 (UINT32_C(0x1) << 0)
2403 /* Both Half and Full dupex will be requested. */
2404 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
2405 (UINT32_C(0x2) << 0)
2406 uint8_t auto_duplex;
2409 * This value is used to configure the pause that will be used for
2410 * autonegotiation. Add text on the usage of auto_pause and force_pause.
2413 * When this bit is '1', Generation of tx pause messages has been
2414 * requested. Disabled otherwise.
2416 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
2418 * When this bit is '1', Reception of rx pause messages has been
2419 * requested. Disabled otherwise.
2421 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
2423 * When set to 1, the advertisement of pause is enabled. # When the
2424 * auto_mode is not set to none and this flag is set to 1, then the
2425 * auto_pause bits on this port are being advertised and autoneg pause
2426 * results are being interpreted. # When the auto_mode is not set to
2427 * none and this flag is set to 0, the pause is forced as indicated in
2428 * force_pause, and also advertised as auto_pause bits, but the autoneg
2429 * results are not interpreted since the pause configuration is being
2430 * forced. # When the auto_mode is set to none and this flag is set to
2431 * 1, auto_pause bits should be ignored and should be set to 0.
2433 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
2439 * This is the speed that will be used if the autoneg_mode is
2440 * "one_speed" or "one_or_below". If an unsupported speed is selected,
2441 * an error will be generated.
2443 /* 100Mb link speed */
2444 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
2445 (UINT32_C(0x1) << 0)
2446 /* 1Gb link speed */
2447 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
2448 (UINT32_C(0xa) << 0)
2449 /* 2Gb link speed */
2450 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
2451 (UINT32_C(0x14) << 0)
2452 /* 2.5Gb link speed */
2453 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
2454 (UINT32_C(0x19) << 0)
2455 /* 10Gb link speed */
2456 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
2457 (UINT32_C(0x64) << 0)
2458 /* 20Mb link speed */
2459 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
2460 (UINT32_C(0xc8) << 0)
2461 /* 25Gb link speed */
2462 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
2463 (UINT32_C(0xfa) << 0)
2464 /* 40Gb link speed */
2465 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
2466 (UINT32_C(0x190) << 0)
2467 /* 50Gb link speed */
2468 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
2469 (UINT32_C(0x1f4) << 0)
2470 /* 100Gb link speed */
2471 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
2472 (UINT32_C(0x3e8) << 0)
2473 /* 10Mb link speed */
2474 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
2475 (UINT32_C(0xffff) << 0)
2476 uint16_t auto_link_speed;
2479 * This is a mask of link speeds that will be used if autoneg_mode is
2480 * "mask". If unsupported speed is enabled an error will be generated.
2482 /* 100Mb link speed (Half-duplex) */
2483 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
2485 /* 100Mb link speed (Full-duplex) */
2486 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
2488 /* 1Gb link speed (Half-duplex) */
2489 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
2491 /* 1Gb link speed (Full-duplex) */
2492 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
2494 /* 2Gb link speed */
2495 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
2497 /* 2.5Gb link speed */
2498 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
2500 /* 10Gb link speed */
2501 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
2503 /* 20Gb link speed */
2504 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
2506 /* 25Gb link speed */
2507 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
2509 /* 40Gb link speed */
2510 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
2512 /* 50Gb link speed */
2513 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
2515 /* 100Gb link speed */
2516 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
2518 /* 10Mb link speed (Half-duplex) */
2519 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
2521 /* 10Mb link speed (Full-duplex) */
2522 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
2524 uint16_t auto_link_speed_mask;
2526 /* This value controls the wirespeed feature. */
2527 /* Wirespeed feature is disabled. */
2528 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
2529 /* Wirespeed feature is enabled. */
2530 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
2533 /* This value controls the loopback setting for the PHY. */
2534 /* No loopback is selected. Normal operation. */
2535 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
2537 * The HW will be configured with local loopback such that host
2538 * data is sent back to the host without modification.
2540 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
2542 * The HW will be configured with remote loopback such that port
2543 * logic will send packets back out the transmitter that are
2546 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
2550 * This value is used to configure the pause that will be used for force
2554 * When this bit is '1', Generation of tx pause messages is supported.
2555 * Disabled otherwise.
2557 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
2559 * When this bit is '1', Reception of rx pause messages is supported.
2560 * Disabled otherwise.
2562 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
2563 uint8_t force_pause;
2568 * This value controls the pre-emphasis to be used for the link. Driver
2569 * should not set this value (use enable.preemphasis = 0) unless driver
2570 * is sure of setting. Normally HWRM FW will determine proper pre-
2573 uint32_t preemphasis;
2576 * Setting for link speed mask that is used to advertise speeds during
2577 * autonegotiation when EEE is enabled. This field is valid only when
2578 * EEE is enabled. The speeds specified in this field shall be a subset
2579 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
2580 * at least one speed shall be provided in this mask.
2583 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
2584 /* 100Mb link speed (Full-duplex) */
2585 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
2587 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
2588 /* 1Gb link speed (Full-duplex) */
2589 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
2591 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
2594 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
2596 /* 10Gb link speed */
2597 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
2599 uint16_t eee_link_speed_mask;
2605 * Reuested setting of TX LPI timer in microseconds. This field is valid
2606 * only when EEE is enabled and TX LPI is enabled.
2608 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
2610 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
2611 uint32_t tx_lpi_timer;
2614 } __attribute__((packed));
2616 /* Output (16 bytes) */
2617 struct hwrm_port_phy_cfg_output {
2619 * Pass/Fail or error type Note: receiver to verify the in parameters,
2620 * and fail the call with an error when appropriate
2622 uint16_t error_code;
2624 /* This field returns the type of original request. */
2627 /* This field provides original sequence number of the command. */
2631 * This field is the length of the response in bytes. The last byte of
2632 * the response is a valid flag that will read as '1' when the command
2633 * has been completely written to memory.
2643 * This field is used in Output records to indicate that the output is
2644 * completely written to RAM. This field should be read as '1' to
2645 * indicate that the output has been completely written. When writing a
2646 * command completion or response to an internal processor, the order of
2647 * writes has to be such that this field is written last.
2650 } __attribute__((packed));
2654 * Description: This function is called by a driver to determine the HWRM
2655 * interface version supported by the HWRM firmware, the version of HWRM
2656 * firmware implementation, the name of HWRM firmware, the versions of other
2657 * embedded firmwares, and the names of other embedded firmwares, etc. Any
2658 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
2659 * be considered an invalid version.
2662 /* Input (24 bytes) */
2663 struct hwrm_ver_get_input {
2665 * This value indicates what type of request this is. The format for the
2666 * rest of the command is determined by this field.
2671 * This value indicates the what completion ring the request will be
2672 * optionally completed on. If the value is -1, then no CR completion
2673 * will be generated. Any other value must be a valid CR ring_id value
2674 * for this function.
2678 /* This value indicates the command sequence number. */
2682 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2683 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2688 * This is the host address where the response will be written when the
2689 * request is complete. This area must be 16B aligned and must be
2690 * cleared to zero before the request is made.
2695 * This field represents the major version of HWRM interface
2696 * specification supported by the driver HWRM implementation. The
2697 * interface major version is intended to change only when non backward
2698 * compatible changes are made to the HWRM interface specification.
2700 uint8_t hwrm_intf_maj;
2703 * This field represents the minor version of HWRM interface
2704 * specification supported by the driver HWRM implementation. A change
2705 * in interface minor version is used to reflect significant backward
2706 * compatible modification to HWRM interface specification. This can be
2707 * due to addition or removal of functionality. HWRM interface
2708 * specifications with the same major version but different minor
2709 * versions are compatible.
2711 uint8_t hwrm_intf_min;
2714 * This field represents the update version of HWRM interface
2715 * specification supported by the driver HWRM implementation. The
2716 * interface update version is used to reflect minor changes or bug
2717 * fixes to a released HWRM interface specification.
2719 uint8_t hwrm_intf_upd;
2721 uint8_t unused_0[5];
2722 } __attribute__((packed));
2724 /* Output (128 bytes) */
2725 struct hwrm_ver_get_output {
2727 * Pass/Fail or error type Note: receiver to verify the in parameters,
2728 * and fail the call with an error when appropriate
2730 uint16_t error_code;
2732 /* This field returns the type of original request. */
2735 /* This field provides original sequence number of the command. */
2739 * This field is the length of the response in bytes. The last byte of
2740 * the response is a valid flag that will read as '1' when the command
2741 * has been completely written to memory.
2746 * This field represents the major version of HWRM interface
2747 * specification supported by the HWRM implementation. The interface
2748 * major version is intended to change only when non backward compatible
2749 * changes are made to the HWRM interface specification. A HWRM
2750 * implementation that is compliant with this specification shall
2751 * provide value of 1 in this field.
2753 uint8_t hwrm_intf_maj;
2756 * This field represents the minor version of HWRM interface
2757 * specification supported by the HWRM implementation. A change in
2758 * interface minor version is used to reflect significant backward
2759 * compatible modification to HWRM interface specification. This can be
2760 * due to addition or removal of functionality. HWRM interface
2761 * specifications with the same major version but different minor
2762 * versions are compatible. A HWRM implementation that is compliant with
2763 * this specification shall provide value of 0 in this field.
2765 uint8_t hwrm_intf_min;
2768 * This field represents the update version of HWRM interface
2769 * specification supported by the HWRM implementation. The interface
2770 * update version is used to reflect minor changes or bug fixes to a
2771 * released HWRM interface specification. A HWRM implementation that is
2772 * compliant with this specification shall provide value of 1 in this
2775 uint8_t hwrm_intf_upd;
2777 uint8_t hwrm_intf_rsvd;
2780 * This field represents the major version of HWRM firmware. A change in
2781 * firmware major version represents a major firmware release.
2783 uint8_t hwrm_fw_maj;
2786 * This field represents the minor version of HWRM firmware. A change in
2787 * firmware minor version represents significant firmware functionality
2790 uint8_t hwrm_fw_min;
2793 * This field represents the build version of HWRM firmware. A change in
2794 * firmware build version represents bug fixes to a released firmware.
2796 uint8_t hwrm_fw_bld;
2799 * This field is a reserved field. This field can be used to represent
2800 * firmware branches or customer specific releases tied to a specific
2801 * (major,minor,update) version of the HWRM firmware.
2803 uint8_t hwrm_fw_rsvd;
2806 * This field represents the major version of mgmt firmware. A change in
2807 * major version represents a major release.
2809 uint8_t mgmt_fw_maj;
2812 * This field represents the minor version of mgmt firmware. A change in
2813 * minor version represents significant functionality changes.
2815 uint8_t mgmt_fw_min;
2818 * This field represents the build version of mgmt firmware. A change in
2819 * update version represents bug fixes.
2821 uint8_t mgmt_fw_bld;
2824 * This field is a reserved field. This field can be used to represent
2825 * firmware branches or customer specific releases tied to a specific
2826 * (major,minor,update) version
2828 uint8_t mgmt_fw_rsvd;
2831 * This field represents the major version of network control firmware.
2832 * A change in major version represents a major release.
2834 uint8_t netctrl_fw_maj;
2837 * This field represents the minor version of network control firmware.
2838 * A change in minor version represents significant functionality
2841 uint8_t netctrl_fw_min;
2844 * This field represents the build version of network control firmware.
2845 * A change in update version represents bug fixes.
2847 uint8_t netctrl_fw_bld;
2850 * This field is a reserved field. This field can be used to represent
2851 * firmware branches or customer specific releases tied to a specific
2852 * (major,minor,update) version
2854 uint8_t netctrl_fw_rsvd;
2857 * This field is reserved for future use. The responder should set it to
2858 * 0. The requester should ignore this field.
2863 * This field represents the major version of RoCE firmware. A change in
2864 * major version represents a major release.
2866 uint8_t roce_fw_maj;
2869 * This field represents the minor version of RoCE firmware. A change in
2870 * minor version represents significant functionality changes.
2872 uint8_t roce_fw_min;
2875 * This field represents the build version of RoCE firmware. A change in
2876 * update version represents bug fixes.
2878 uint8_t roce_fw_bld;
2881 * This field is a reserved field. This field can be used to represent
2882 * firmware branches or customer specific releases tied to a specific
2883 * (major,minor,update) version
2885 uint8_t roce_fw_rsvd;
2888 * This field represents the name of HWRM FW (ASCII chars without NULL
2891 char hwrm_fw_name[16];
2894 * This field represents the name of mgmt FW (ASCII chars without NULL
2897 char mgmt_fw_name[16];
2900 * This field represents the name of network control firmware (ASCII
2901 * chars without NULL at the end).
2903 char netctrl_fw_name[16];
2906 * This field is reserved for future use. The responder should set it to
2907 * 0. The requester should ignore this field.
2909 uint32_t reserved2[4];
2912 * This field represents the name of RoCE FW (ASCII chars without NULL
2915 char roce_fw_name[16];
2917 /* This field returns the chip number. */
2920 /* This field returns the revision of chip. */
2923 /* This field returns the chip metal number. */
2926 /* This field returns the bond id of the chip. */
2927 uint8_t chip_bond_id;
2930 * This value indicates the type of platform used for chip
2934 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
2935 (UINT32_C(0x0) << 0)
2936 /* FPGA platform of the chip. */
2937 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
2938 (UINT32_C(0x1) << 0)
2939 /* Palladium platform of the chip. */
2940 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
2941 (UINT32_C(0x2) << 0)
2942 uint8_t chip_platform_type;
2945 * This field returns the maximum value of request window that is
2946 * supported by the HWRM. The request window is mapped into device
2947 * address space using MMIO.
2949 uint16_t max_req_win_len;
2952 * This field returns the maximum value of response buffer in bytes. If
2953 * a request specifies the response buffer length that is greater than
2954 * this value, then the HWRM should fail it. The value of this field
2955 * shall be 4KB or more.
2957 uint16_t max_resp_len;
2960 * This field returns the default request timeout value in milliseconds.
2962 uint16_t def_req_timeout;
2969 * This field is used in Output records to indicate that the output is
2970 * completely written to RAM. This field should be read as '1' to
2971 * indicate that the output has been completely written. When writing a
2972 * command completion or response to an internal processor, the order of
2973 * writes has to be such that this field is written last.
2976 } __attribute__((packed));
2978 /* hwrm_queue_qportcfg */
2980 * Description: This function is called by a driver to query queue configuration
2981 * of a port. # The HWRM shall at least advertise one queue with lossy service
2982 * profile. # The driver shall use this command to query queue ids before
2983 * configuring or using any queues. # If a service profile is not set for a
2984 * queue, then the driver shall not use that queue without configuring a service
2985 * profile for it. # If the driver is not allowed to configure service profiles,
2986 * then the driver shall only use queues for which service profiles are pre-
2990 /* Input (24 bytes) */
2991 struct hwrm_queue_qportcfg_input {
2993 * This value indicates what type of request this is. The format for the
2994 * rest of the command is determined by this field.
2999 * This value indicates the what completion ring the request will be
3000 * optionally completed on. If the value is -1, then no CR completion
3001 * will be generated. Any other value must be a valid CR ring_id value
3002 * for this function.
3006 /* This value indicates the command sequence number. */
3010 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3011 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3016 * This is the host address where the response will be written when the
3017 * request is complete. This area must be 16B aligned and must be
3018 * cleared to zero before the request is made.
3023 * Enumeration denoting the RX, TX type of the resource. This
3024 * enumeration is used for resources that are similar for both TX and RX
3025 * paths of the chip.
3027 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
3030 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
3031 (UINT32_C(0x0) << 0)
3033 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
3034 (UINT32_C(0x1) << 0)
3035 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
3036 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
3040 * Port ID of port for which the queue configuration is being queried.
3041 * This field is only required when sent by IPC.
3046 } __attribute__((packed));
3048 /* hwrm_stat_ctx_clr_stats */
3049 /* Description: This command clears statistics of a context. */
3051 /* Input (24 bytes) */
3052 struct hwrm_stat_ctx_clr_stats_input {
3054 * This value indicates what type of request this is. The format for the
3055 * rest of the command is determined by this field.
3060 * This value indicates the what completion ring the request will be
3061 * optionally completed on. If the value is -1, then no CR completion
3062 * will be generated. Any other value must be a valid CR ring_id value
3063 * for this function.
3067 /* This value indicates the command sequence number. */
3071 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3072 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3077 * This is the host address where the response will be written when the
3078 * request is complete. This area must be 16B aligned and must be
3079 * cleared to zero before the request is made.
3083 /* ID of the statistics context that is being queried. */
3084 uint32_t stat_ctx_id;
3087 } __attribute__((packed));
3089 /* Output (16 bytes) */
3090 struct hwrm_stat_ctx_clr_stats_output {
3092 * Pass/Fail or error type Note: receiver to verify the in parameters,
3093 * and fail the call with an error when appropriate
3095 uint16_t error_code;
3097 /* This field returns the type of original request. */
3100 /* This field provides original sequence number of the command. */
3104 * This field is the length of the response in bytes. The last byte of
3105 * the response is a valid flag that will read as '1' when the command
3106 * has been completely written to memory.
3116 * This field is used in Output records to indicate that the output is
3117 * completely written to RAM. This field should be read as '1' to
3118 * indicate that the output has been completely written. When writing a
3119 * command completion or response to an internal processor, the order of
3120 * writes has to be such that this field is written last.
3123 } __attribute__((packed));
3125 /* hwrm_vnic_alloc */
3127 * Description: This VNIC is a resource in the RX side of the chip that is used
3128 * to represent a virtual host "interface". # At the time of VNIC allocation or
3129 * configuration, the function can specify whether it wants the requested VNIC
3130 * to be the default VNIC for the function or not. # If a function requests
3131 * allocation of a VNIC for the first time and a VNIC is successfully allocated
3132 * by the HWRM, then the HWRM shall make the allocated VNIC as the default VNIC
3133 * for that function. # The default VNIC shall be used for the default action
3134 * for a partition or function. # For each VNIC allocated on a function, a
3135 * mapping on the RX side to map the allocated VNIC to source virtual interface
3136 * shall be performed by the HWRM. This should be hidden to the function driver
3137 * requesting the VNIC allocation. This enables broadcast/multicast replication
3138 * with source knockout. # If multicast replication with source knockout is
3139 * enabled, then the internal VNIC to SVIF mapping data structures shall be
3140 * programmed at the time of VNIC allocation.
3143 /* Input (24 bytes) */
3144 struct hwrm_vnic_alloc_input {
3146 * This value indicates what type of request this is. The format for the
3147 * rest of the command is determined by this field.
3152 * This value indicates the what completion ring the request will be
3153 * optionally completed on. If the value is -1, then no CR completion
3154 * will be generated. Any other value must be a valid CR ring_id value
3155 * for this function.
3159 /* This value indicates the command sequence number. */
3163 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3164 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3169 * This is the host address where the response will be written when the
3170 * request is complete. This area must be 16B aligned and must be
3171 * cleared to zero before the request is made.
3176 * When this bit is '1', this VNIC is requested to be the default VNIC
3177 * for this function.
3179 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
3183 } __attribute__((packed));
3185 /* Output (16 bytes) */
3186 struct hwrm_vnic_alloc_output {
3188 * Pass/Fail or error type Note: receiver to verify the in parameters,
3189 * and fail the call with an error when appropriate
3191 uint16_t error_code;
3193 /* This field returns the type of original request. */
3196 /* This field provides original sequence number of the command. */
3200 * This field is the length of the response in bytes. The last byte of
3201 * the response is a valid flag that will read as '1' when the command
3202 * has been completely written to memory.
3206 /* Logical vnic ID */
3214 * This field is used in Output records to indicate that the output is
3215 * completely written to RAM. This field should be read as '1' to
3216 * indicate that the output has been completely written. When writing a
3217 * command completion or response to an internal processor, the order of
3218 * writes has to be such that this field is written last.
3221 } __attribute__((packed));
3224 /* Description: Configure the RX VNIC structure. */
3226 /* Input (40 bytes) */
3227 struct hwrm_vnic_cfg_input {
3229 * This value indicates what type of request this is. The format for the
3230 * rest of the command is determined by this field.
3235 * This value indicates the what completion ring the request will be
3236 * optionally completed on. If the value is -1, then no CR completion
3237 * will be generated. Any other value must be a valid CR ring_id value
3238 * for this function.
3242 /* This value indicates the command sequence number. */
3246 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3247 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3252 * This is the host address where the response will be written when the
3253 * request is complete. This area must be 16B aligned and must be
3254 * cleared to zero before the request is made.
3259 * When this bit is '1', the VNIC is requested to be the default VNIC
3262 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
3264 * When this bit is '1', the VNIC is being configured to strip VLAN in
3265 * the RX path. If set to '0', then VLAN stripping is disabled on this
3268 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
3270 * When this bit is '1', the VNIC is being configured to buffer receive
3271 * packets in the hardware until the host posts new receive buffers. If
3272 * set to '0', then bd_stall is being configured to be disabled on this
3275 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
3277 * When this bit is '1', the VNIC is being configured to receive both
3278 * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not
3279 * configured to be operating in dual VNIC mode.
3281 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
3283 * When this flag is set to '1', the VNIC is requested to be configured
3284 * to receive only RoCE traffic. If this flag is set to '0', then this
3285 * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set
3286 * to '1', then the HWRM client shall not set this flag to '1'.
3288 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
3291 /* This bit must be '1' for the dflt_ring_grp field to be configured. */
3292 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
3293 /* This bit must be '1' for the rss_rule field to be configured. */
3294 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
3295 /* This bit must be '1' for the cos_rule field to be configured. */
3296 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
3297 /* This bit must be '1' for the lb_rule field to be configured. */
3298 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
3299 /* This bit must be '1' for the mru field to be configured. */
3300 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
3303 /* Logical vnic ID */
3307 * Default Completion ring for the VNIC. This ring will be chosen if
3308 * packet does not match any RSS rules and if there is no COS rule.
3310 uint16_t dflt_ring_grp;
3313 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
3319 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
3325 * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
3326 * there is no LB rule.
3331 * The maximum receive unit of the vnic. Each vnic is associated with a
3332 * function. The vnic mru value overwrites the mru setting of the
3333 * associated function. The HWRM shall make sure that vnic mru does not
3334 * exceed the mru of the port the function is associated with.
3339 } __attribute__((packed));
3341 /* Output (16 bytes) */
3342 struct hwrm_vnic_cfg_output {
3344 * Pass/Fail or error type Note: receiver to verify the in parameters,
3345 * and fail the call with an error when appropriate
3347 uint16_t error_code;
3349 /* This field returns the type of original request. */
3352 /* This field provides original sequence number of the command. */
3356 * This field is the length of the response in bytes. The last byte of
3357 * the response is a valid flag that will read as '1' when the command
3358 * has been completely written to memory.
3368 * This field is used in Output records to indicate that the output is
3369 * completely written to RAM. This field should be read as '1' to
3370 * indicate that the output has been completely written. When writing a
3371 * command completion or response to an internal processor, the order of
3372 * writes has to be such that this field is written last.
3375 } __attribute__((packed));
3377 /* hwrm_vnic_free */
3379 * Description: Free a VNIC resource. Idle any resources associated with the
3380 * VNIC as well as the VNIC. Reset and release all resources associated with the
3384 /* Input (24 bytes) */
3385 struct hwrm_vnic_free_input {
3387 * This value indicates what type of request this is. The format for the
3388 * rest of the command is determined by this field.
3393 * This value indicates the what completion ring the request will be
3394 * optionally completed on. If the value is -1, then no CR completion
3395 * will be generated. Any other value must be a valid CR ring_id value
3396 * for this function.
3400 /* This value indicates the command sequence number. */
3404 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3405 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3410 * This is the host address where the response will be written when the
3411 * request is complete. This area must be 16B aligned and must be
3412 * cleared to zero before the request is made.
3416 /* Logical vnic ID */
3420 } __attribute__((packed));
3422 /* Output (16 bytes) */
3423 struct hwrm_vnic_free_output {
3425 * Pass/Fail or error type Note: receiver to verify the in parameters,
3426 * and fail the call with an error when appropriate
3428 uint16_t error_code;
3430 /* This field returns the type of original request. */
3433 /* This field provides original sequence number of the command. */
3437 * This field is the length of the response in bytes. The last byte of
3438 * the response is a valid flag that will read as '1' when the command
3439 * has been completely written to memory.
3449 * This field is used in Output records to indicate that the output is
3450 * completely written to RAM. This field should be read as '1' to
3451 * indicate that the output has been completely written. When writing a
3452 * command completion or response to an internal processor, the order of
3453 * writes has to be such that this field is written last.
3456 } __attribute__((packed));
3458 /* hwrm_vnic_rss_cfg */
3459 /* Description: This function is used to enable RSS configuration. */
3461 /* Input (48 bytes) */
3462 struct hwrm_vnic_rss_cfg_input {
3464 * This value indicates what type of request this is. The format for the
3465 * rest of the command is determined by this field.
3470 * This value indicates the what completion ring the request will be
3471 * optionally completed on. If the value is -1, then no CR completion
3472 * will be generated. Any other value must be a valid CR ring_id value
3473 * for this function.
3477 /* This value indicates the command sequence number. */
3481 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3482 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3487 * This is the host address where the response will be written when the
3488 * request is complete. This area must be 16B aligned and must be
3489 * cleared to zero before the request is made.
3494 * When this bit is '1', the RSS hash shall be computed over source and
3495 * destination IPv4 addresses of IPv4 packets.
3497 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
3499 * When this bit is '1', the RSS hash shall be computed over
3500 * source/destination IPv4 addresses and source/destination ports of
3503 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
3505 * When this bit is '1', the RSS hash shall be computed over
3506 * source/destination IPv4 addresses and source/destination ports of
3509 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
3511 * When this bit is '1', the RSS hash shall be computed over source and
3512 * destination IPv4 addresses of IPv6 packets.
3514 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
3516 * When this bit is '1', the RSS hash shall be computed over
3517 * source/destination IPv6 addresses and source/destination ports of
3520 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
3522 * When this bit is '1', the RSS hash shall be computed over
3523 * source/destination IPv6 addresses and source/destination ports of
3526 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
3531 /* This is the address for rss ring group table */
3532 uint64_t ring_grp_tbl_addr;
3534 /* This is the address for rss hash key table */
3535 uint64_t hash_key_tbl_addr;
3537 /* Index to the rss indirection table. */
3538 uint16_t rss_ctx_idx;
3540 uint16_t unused_1[3];
3541 } __attribute__((packed));
3543 /* Output (16 bytes) */
3544 struct hwrm_vnic_rss_cfg_output {
3546 * Pass/Fail or error type Note: receiver to verify the in parameters,
3547 * and fail the call with an error when appropriate
3549 uint16_t error_code;
3551 /* This field returns the type of original request. */
3554 /* This field provides original sequence number of the command. */
3558 * This field is the length of the response in bytes. The last byte of
3559 * the response is a valid flag that will read as '1' when the command
3560 * has been completely written to memory.
3570 * This field is used in Output records to indicate that the output is
3571 * completely written to RAM. This field should be read as '1' to
3572 * indicate that the output has been completely written. When writing a
3573 * command completion or response to an internal processor, the order of
3574 * writes has to be such that this field is written last.
3577 } __attribute__((packed));
3579 /* Output (32 bytes) */
3580 struct hwrm_queue_qportcfg_output {
3582 * Pass/Fail or error type Note: receiver to verify the in parameters,
3583 * and fail the call with an error when appropriate
3585 uint16_t error_code;
3587 /* This field returns the type of original request. */
3590 /* This field provides original sequence number of the command. */
3594 * This field is the length of the response in bytes. The last byte of
3595 * the response is a valid flag that will read as '1' when the command
3596 * has been completely written to memory.
3600 /* The maximum number of queues that can be configured. */
3601 uint8_t max_configurable_queues;
3603 /* The maximum number of lossless queues that can be configured. */
3604 uint8_t max_configurable_lossless_queues;
3607 * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then
3608 * the HWRM shall allow the host SW driver to configure queues using
3611 uint8_t queue_cfg_allowed;
3614 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3615 * the HWRM shall allow the host SW driver to configure queue buffers
3616 * using hwrm_queue_buffers_cfg.
3618 uint8_t queue_buffers_cfg_allowed;
3621 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3622 * the HWRM shall allow the host SW driver to configure PFC using
3623 * hwrm_queue_pfcenable_cfg.
3625 uint8_t queue_pfcenable_cfg_allowed;
3628 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3629 * the HWRM shall allow the host SW driver to configure Priority to CoS
3630 * mapping using hwrm_queue_pri2cos_cfg.
3632 uint8_t queue_pri2cos_cfg_allowed;
3635 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
3636 * the HWRM shall allow the host SW driver to configure CoS Bandwidth
3637 * configuration using hwrm_queue_cos2bw_cfg.
3639 uint8_t queue_cos2bw_cfg_allowed;
3641 /* ID of CoS Queue 0. FF - Invalid id */
3644 /* This value is applicable to CoS queues only. */
3645 /* Lossy (best-effort) */
3646 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
3647 (UINT32_C(0x0) << 0)
3649 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
3650 (UINT32_C(0x1) << 0)
3652 * Set to 0xFF... (All Fs) if there is no service profile
3655 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
3656 (UINT32_C(0xff) << 0)
3657 uint8_t queue_id0_service_profile;
3659 /* ID of CoS Queue 1. FF - Invalid id */
3661 /* This value is applicable to CoS queues only. */
3662 /* Lossy (best-effort) */
3663 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
3664 (UINT32_C(0x0) << 0)
3666 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
3667 (UINT32_C(0x1) << 0)
3669 * Set to 0xFF... (All Fs) if there is no service profile
3672 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
3673 (UINT32_C(0xff) << 0)
3674 uint8_t queue_id1_service_profile;
3676 /* ID of CoS Queue 2. FF - Invalid id */
3678 /* This value is applicable to CoS queues only. */
3679 /* Lossy (best-effort) */
3680 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
3681 (UINT32_C(0x0) << 0)
3683 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
3684 (UINT32_C(0x1) << 0)
3686 * Set to 0xFF... (All Fs) if there is no service profile
3689 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
3690 (UINT32_C(0xff) << 0)
3691 uint8_t queue_id2_service_profile;
3693 /* ID of CoS Queue 3. FF - Invalid id */
3696 /* This value is applicable to CoS queues only. */
3697 /* Lossy (best-effort) */
3698 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
3699 (UINT32_C(0x0) << 0)
3701 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
3702 (UINT32_C(0x1) << 0)
3704 * Set to 0xFF... (All Fs) if there is no service profile
3707 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
3708 (UINT32_C(0xff) << 0)
3709 uint8_t queue_id3_service_profile;
3711 /* ID of CoS Queue 4. FF - Invalid id */
3713 /* This value is applicable to CoS queues only. */
3714 /* Lossy (best-effort) */
3715 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
3716 (UINT32_C(0x0) << 0)
3718 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
3719 (UINT32_C(0x1) << 0)
3721 * Set to 0xFF... (All Fs) if there is no service profile
3724 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
3725 (UINT32_C(0xff) << 0)
3726 uint8_t queue_id4_service_profile;
3728 /* ID of CoS Queue 5. FF - Invalid id */
3731 /* This value is applicable to CoS queues only. */
3732 /* Lossy (best-effort) */
3733 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
3734 (UINT32_C(0x0) << 0)
3736 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
3737 (UINT32_C(0x1) << 0)
3739 * Set to 0xFF... (All Fs) if there is no service profile
3742 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
3743 (UINT32_C(0xff) << 0)
3744 uint8_t queue_id5_service_profile;
3746 /* ID of CoS Queue 6. FF - Invalid id */
3747 uint8_t queue_id6_service_profile;
3748 /* This value is applicable to CoS queues only. */
3749 /* Lossy (best-effort) */
3750 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
3751 (UINT32_C(0x0) << 0)
3753 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
3754 (UINT32_C(0x1) << 0)
3756 * Set to 0xFF... (All Fs) if there is no service profile
3759 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
3760 (UINT32_C(0xff) << 0)
3763 /* ID of CoS Queue 7. FF - Invalid id */
3766 /* This value is applicable to CoS queues only. */
3767 /* Lossy (best-effort) */
3768 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
3769 (UINT32_C(0x0) << 0)
3771 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
3772 (UINT32_C(0x1) << 0)
3774 * Set to 0xFF... (All Fs) if there is no service profile
3777 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
3778 (UINT32_C(0xff) << 0)
3779 uint8_t queue_id7_service_profile;
3782 * This field is used in Output records to indicate that the output is
3783 * completely written to RAM. This field should be read as '1' to
3784 * indicate that the output has been completely written. When writing a
3785 * command completion or response to an internal processor, the order of
3786 * writes has to be such that this field is written last.
3789 } __attribute__((packed));
3791 /* hwrm_func_drv_rgtr */
3793 * Description: This command is used by the function driver to register its
3794 * information with the HWRM. A function driver shall implement this command. A
3795 * function driver shall use this command during the driver initialization right
3796 * after the HWRM version discovery and default ring resources allocation.
3799 /* Input (80 bytes) */
3800 struct hwrm_func_drv_rgtr_input {
3802 * This value indicates what type of request this is. The format for the
3803 * rest of the command is determined by this field.
3808 * This value indicates the what completion ring the request will be
3809 * optionally completed on. If the value is -1, then no CR completion
3810 * will be generated. Any other value must be a valid CR ring_id value
3811 * for this function.
3815 /* This value indicates the command sequence number. */
3819 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3820 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3825 * This is the host address where the response will be written when the
3826 * request is complete. This area must be 16B aligned and must be
3827 * cleared to zero before the request is made.
3832 * When this bit is '1', the function driver is requesting all requests
3833 * from its children VF drivers to be forwarded to itself. This flag can
3834 * only be set by the PF driver. If a VF driver sets this flag, it
3835 * should be ignored by the HWRM.
3837 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
3839 * When this bit is '1', the function is requesting none of the requests
3840 * from its children VF drivers to be forwarded to itself. This flag can
3841 * only be set by the PF driver. If a VF driver sets this flag, it
3842 * should be ignored by the HWRM.
3844 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
3847 /* This bit must be '1' for the os_type field to be configured. */
3848 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
3849 /* This bit must be '1' for the ver field to be configured. */
3850 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
3851 /* This bit must be '1' for the timestamp field to be configured. */
3852 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
3853 /* This bit must be '1' for the vf_req_fwd field to be configured. */
3854 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
3856 * This bit must be '1' for the async_event_fwd field to be configured.
3858 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
3862 /* This value indicates the type of OS. */
3864 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN \
3865 (UINT32_C(0x0) << 0)
3866 /* Other OS not listed below. */
3867 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER \
3868 (UINT32_C(0x1) << 0)
3870 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS \
3871 (UINT32_C(0xe) << 0)
3873 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS \
3874 (UINT32_C(0x12) << 0)
3876 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS \
3877 (UINT32_C(0x1d) << 0)
3879 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX \
3880 (UINT32_C(0x24) << 0)
3882 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD \
3883 (UINT32_C(0x2a) << 0)
3884 /* VMware ESXi OS. */
3885 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI \
3886 (UINT32_C(0x68) << 0)
3887 /* Microsoft Windows 8 64-bit OS. */
3888 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 \
3889 (UINT32_C(0x73) << 0)
3890 /* Microsoft Windows Server 2012 R2 OS. */
3891 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 \
3892 (UINT32_C(0x74) << 0)
3895 /* This is the major version of the driver. */
3898 /* This is the minor version of the driver. */
3901 /* This is the update version of the driver. */
3908 * This is a 32-bit timestamp provided by the driver for keep alive. The
3909 * timestamp is in multiples of 1ms.
3916 * This is a 256-bit bit mask provided by the PF driver for letting the
3917 * HWRM know what commands issued by the VF driver to the HWRM should be
3918 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
3919 * Setting Nth bit to 1 indicates that requests from the VF driver with
3920 * req_type equal to N shall be forwarded to the parent PF driver. This
3921 * field is not valid for the VF driver.
3923 uint32_t vf_req_fwd[8];
3926 * This is a 256-bit bit mask provided by the function driver (PF or VF
3927 * driver) to indicate the list of asynchronous event completions to be
3928 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
3929 * by the function driver shall result in the HWRM forwarding
3930 * asynchronous event completion with event_id equal to N. If all bits
3931 * are set to 0 (value of 0), then the HWRM shall not forward any
3932 * asynchronous event completion to this function driver.
3934 uint32_t async_event_fwd[8];
3935 } __attribute__((packed));
3937 /* Output (16 bytes) */
3939 struct hwrm_func_drv_rgtr_output {
3941 * Pass/Fail or error type Note: receiver to verify the in parameters,
3942 * and fail the call with an error when appropriate
3944 uint16_t error_code;
3946 /* This field returns the type of original request. */
3949 /* This field provides original sequence number of the command. */
3953 * This field is the length of the response in bytes. The last byte of
3954 * the response is a valid flag that will read as '1' when the command
3955 * has been completely written to memory.
3965 * This field is used in Output records to indicate that the output is
3966 * completely written to RAM. This field should be read as '1' to
3967 * indicate that the output has been completely written. When writing a
3968 * command completion or response to an internal processor, the order of
3969 * writes has to be such that this field is written last.
3972 } __attribute__((packed));
3974 /* hwrm_func_drv_unrgtr */
3976 * Description: This command is used by the function driver to un register with
3977 * the HWRM. A function driver shall implement this command. A function driver
3978 * shall use this command during the driver unloading.
3980 /* Input (24 bytes) */
3982 struct hwrm_func_drv_unrgtr_input {
3984 * This value indicates what type of request this is. The format for the
3985 * rest of the command is determined by this field.
3990 * This value indicates the what completion ring the request will be
3991 * optionally completed on. If the value is -1, then no CR completion
3992 * will be generated. Any other value must be a valid CR ring_id value
3993 * for this function.
3997 /* This value indicates the command sequence number. */
4001 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4002 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4007 * This is the host address where the response will be written when the
4008 * request is complete. This area must be 16B aligned and must be
4009 * cleared to zero before the request is made.
4014 * When this bit is '1', the function driver is notifying the HWRM to
4015 * prepare for the shutdown.
4017 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
4022 } __attribute__((packed));
4024 /* Output (16 bytes) */
4025 struct hwrm_func_drv_unrgtr_output {
4027 * Pass/Fail or error type Note: receiver to verify the in parameters,
4028 * and fail the call with an error when appropriate
4030 uint16_t error_code;
4032 /* This field returns the type of original request. */
4035 /* This field provides original sequence number of the command. */
4039 * This field is the length of the response in bytes. The last byte of
4040 * the response is a valid flag that will read as '1' when the command
4041 * has been completely written to memory.
4051 * This field is used in Output records to indicate that the output is
4052 * completely written to RAM. This field should be read as '1' to
4053 * indicate that the output has been completely written. When writing a
4054 * command completion or response to an internal processor, the order of
4055 * writes has to be such that this field is written last.
4058 } __attribute__((packed));