4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
35 #define _HSI_STRUCT_DEF_EXTERNAL_H_
38 * per-context HW statistics -- chip view
41 struct ctx_hw_stats64 {
42 uint64_t rx_ucast_pkts;
43 uint64_t rx_mcast_pkts;
44 uint64_t rx_bcast_pkts;
45 uint64_t rx_drop_pkts;
47 uint64_t rx_ucast_bytes;
48 uint64_t rx_mcast_bytes;
49 uint64_t rx_bcast_bytes;
51 uint64_t tx_ucast_pkts;
52 uint64_t tx_mcast_pkts;
53 uint64_t tx_bcast_pkts;
54 uint64_t tx_drop_pkts;
56 uint64_t tx_ucast_bytes;
57 uint64_t tx_mcast_bytes;
58 uint64_t tx_bcast_bytes;
66 /* HW Resource Manager Specification 1.2.0 */
67 #define HWRM_VERSION_MAJOR 1
68 #define HWRM_VERSION_MINOR 2
69 #define HWRM_VERSION_UPDATE 0
72 * Following is the signature for HWRM message field that indicates not
73 * applicable (All F's). Need to cast it the size of the field if needed.
75 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
76 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
77 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
78 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
79 #define HW_HASH_KEY_SIZE 40
80 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
85 #define HWRM_VER_GET (UINT32_C(0x0))
86 #define HWRM_FUNC_RESET (UINT32_C(0x11))
87 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
88 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
89 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
90 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
91 #define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
92 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
93 #define HWRM_VNIC_ALLOC (UINT32_C(0x40))
94 #define HWRM_VNIC_FREE (UINT32_C(0x41))
95 #define HWRM_VNIC_CFG (UINT32_C(0x42))
96 #define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
97 #define HWRM_RING_ALLOC (UINT32_C(0x50))
98 #define HWRM_RING_FREE (UINT32_C(0x51))
99 #define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
100 #define HWRM_RING_GRP_FREE (UINT32_C(0x61))
101 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
102 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
103 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
104 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
105 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
106 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
107 #define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
108 #define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
109 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
110 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
113 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
114 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
116 /* Short TX BD (16 bytes) */
119 * All bits in this field must be valid on the first BD of a packet.
120 * Only the packet_end bit must be valid for the remaining BDs of a
123 /* This value identifies the type of buffer descriptor. */
124 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
125 #define TX_BD_SHORT_TYPE_SFT 0
127 * Indicates that this BD is 16B long and is used for normal L2
128 * packet transmission.
130 #define TX_BD_SHORT_TYPE_TX_BD_SHORT (UINT32_C(0x0) << 0)
132 * If set to 1, the packet ends with the data in the buffer pointed to
133 * by this descriptor. This flag must be valid on every BD.
135 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
137 * If set to 1, the device will not generate a completion for this
138 * transmit packet unless there is an error in it's processing. If this
139 * bit is set to 0, then the packet will be completed normally. This bit
140 * must be valid only on the first BD of a packet.
142 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
144 * This value indicates how many 16B BD locations are consumed in the
145 * ring by this packet. A value of 1 indicates that this BD is the only
146 * BD (and that the it is a short BD). A value of 3 indicates either 3
147 * short BDs or 1 long BD and one short BD in the packet. A value of 0
148 * indicates that there are 32 BD locations in the packet (the maximum).
149 * This field is valid only on the first BD of a packet.
151 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
152 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
154 * This value is a hint for the length of the entire packet. It is used
155 * by the chip to optimize internal processing. The packet will be
156 * dropped if the hint is too short. This field is valid only on the
157 * first BD of a packet.
159 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
160 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
161 /* indicates packet length < 512B */
162 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
163 /* indicates 512 <= packet length < 1KB */
164 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
165 /* indicates 1KB <= packet length < 2KB */
166 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
167 /* indicates packet length >= 2KB */
168 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
169 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
171 * If set to 1, the device immediately updates the Send Consumer Index
172 * after the buffer associated with this descriptor has been transferred
173 * via DMA to NIC memory from host memory. An interrupt may or may not
174 * be generated according to the state of the interrupt avoidance
175 * mechanisms. If this bit is set to 0, then the Consumer Index is only
176 * updated as soon as one of the host interrupt coalescing conditions
177 * has been met. This bit must be valid on the first BD of a packet.
179 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
181 * All bits in this field must be valid on the first BD of a packet.
182 * Only the packet_end bit must be valid for the remaining BDs of a
185 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
186 #define TX_BD_SHORT_FLAGS_SFT 6
190 * This is the length of the host physical buffer this BD describes in
191 * bytes. This field must be valid on all BDs of a packet.
195 * The opaque data field is pass through to the completion and can be
196 * used for any data that the driver wants to associate with the
197 * transmit BD. This field must be valid on the first BD of a packet.
202 * This is the host physical address for the portion of the packet
203 * described by this TX BD. This value must be valid on all BDs of a
207 } __attribute__((packed));
209 /* Long TX BD (32 bytes split to 2 16-byte struct) */
212 * All bits in this field must be valid on the first BD of a packet.
213 * Only the packet_end bit must be valid for the remaining BDs of a
216 /* This value identifies the type of buffer descriptor. */
217 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
218 #define TX_BD_LONG_TYPE_SFT 0
220 * Indicates that this BD is 32B long and is used for normal L2
221 * packet transmission.
223 #define TX_BD_LONG_TYPE_TX_BD_LONG (UINT32_C(0x10) << 0)
225 * If set to 1, the packet ends with the data in the buffer pointed to
226 * by this descriptor. This flag must be valid on every BD.
228 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
230 * If set to 1, the device will not generate a completion for this
231 * transmit packet unless there is an error in it's processing. If this
232 * bit is set to 0, then the packet will be completed normally. This bit
233 * must be valid only on the first BD of a packet.
235 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
237 * This value indicates how many 16B BD locations are consumed in the
238 * ring by this packet. A value of 1 indicates that this BD is the only
239 * BD (and that the it is a short BD). A value of 3 indicates either 3
240 * short BDs or 1 long BD and one short BD in the packet. A value of 0
241 * indicates that there are 32 BD locations in the packet (the maximum).
242 * This field is valid only on the first BD of a packet.
244 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
245 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
247 * This value is a hint for the length of the entire packet. It is used
248 * by the chip to optimize internal processing. The packet will be
249 * dropped if the hint is too short. This field is valid only on the
250 * first BD of a packet.
252 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
253 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
254 /* indicates packet length < 512B */
255 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
256 /* indicates 512 <= packet length < 1KB */
257 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
258 /* indicates 1KB <= packet length < 2KB */
259 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
260 /* indicates packet length >= 2KB */
261 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
262 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
264 * If set to 1, the device immediately updates the Send Consumer Index
265 * after the buffer associated with this descriptor has been transferred
266 * via DMA to NIC memory from host memory. An interrupt may or may not
267 * be generated according to the state of the interrupt avoidance
268 * mechanisms. If this bit is set to 0, then the Consumer Index is only
269 * updated as soon as one of the host interrupt coalescing conditions
270 * has been met. This bit must be valid on the first BD of a packet.
272 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
274 * All bits in this field must be valid on the first BD of a packet.
275 * Only the packet_end bit must be valid for the remaining BDs of a
278 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
279 #define TX_BD_LONG_FLAGS_SFT 6
283 * This is the length of the host physical buffer this BD describes in
284 * bytes. This field must be valid on all BDs of a packet.
289 * The opaque data field is pass through to the completion and can be
290 * used for any data that the driver wants to associate with the
291 * transmit BD. This field must be valid on the first BD of a packet.
296 * This is the host physical address for the portion of the packet
297 * described by this TX BD. This value must be valid on all BDs of a
301 } __attribute__((packed));
303 /* last 16 bytes of Long TX BD */
305 struct tx_bd_long_hi {
307 * All bits in this field must be valid on the first BD of a packet.
308 * Their value on other BDs of the packet will be ignored.
311 * If set to 1, the controller replaces the TCP/UPD checksum fields of
312 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
313 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
314 * checksum for the packet associated with this descriptor. This bit
315 * must be valid on the first BD of a packet.
317 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
319 * If set to 1, the controller replaces the IP checksum of the normal
320 * packets, or the inner IP checksum of the encapsulated packets with
321 * the hardware calculated IP checksum for the packet associated with
322 * this descriptor. This bit must be valid on the first BD of a packet.
324 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
326 * If set to 1, the controller will not append an Ethernet CRC to the
327 * end of the frame. This bit must be valid on the first BD of a packet.
328 * Packet must be 64B or longer when this flag is set. It is not useful
329 * to use this bit with any form of TX offload such as CSO or LSO. The
330 * intent is that the packet from the host already has a valid Ethernet
333 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
335 * If set to 1, the device will record the time at which the packet was
336 * actually transmitted at the TX MAC. This bit must be valid on the
337 * first BD of a packet.
339 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
341 * If set to 1, The controller replaces the tunnel IP checksum field
342 * with hardware calculated IP checksum for the IP header of the packet
343 * associated with this descriptor. In case of VXLAN, the controller
344 * also replaces the outer header UDP checksum with hardware calculated
345 * UDP checksum for the packet associated with this descriptor.
347 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
349 * If set to 1, the device will treat this packet with LSO(Large Send
350 * Offload) processing for both normal or encapsulated packets, which is
351 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
352 * fields must be valid. The driver doesn't need to set t_ip_chksum,
353 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
354 * the appropriate checksum fields for segmented packets. When this bit
355 * is 1, the hdr_size and mss fields must be valid.
357 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
359 * If set to zero when LSO is '1', then the IPID will be treated as a
360 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
361 * set to one when LSO is '1', then the IPID will be treated as a 15b
362 * number and will be wrapped if it exceeds a value 0f 0x7fff.
364 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
366 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
367 * will not be modified during LSO operations. If set to one when LSO is
368 * '1', then the IPID of the tunnel IP header will be incremented for
369 * each subsequent segment of an LSO operation.
371 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
373 * If set to '1', then the RoCE ICRC will be appended to the packet.
374 * Packet must be a valid RoCE format packet.
376 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
378 * If set to '1', then the FCoE CRC will be appended to the packet.
379 * Packet must be a valid FCoE format packet.
381 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
385 * When LSO is '1', this field must contain the offset of the TCP
386 * payload from the beginning of the packet in as 16b words. In case of
387 * encapsulated/tunneling packet, this field contains the offset of the
388 * inner TCP payload from beginning of the packet as 16-bit words. This
389 * value must be valid on the first BD of a packet.
391 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
392 #define TX_BD_LONG_HDR_SIZE_SFT 0
396 * This is the MSS value that will be used to do the LSO processing. The
397 * value is the length in bytes of the TCP payload for each segment
398 * generated by the LSO operation. This value must be valid on the first
401 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
402 #define TX_BD_LONG_MSS_SFT 0
408 * This value selects a CFA action to perform on the packet. Set this
409 * value to zero if no CFA action is desired. This value must be valid
410 * on the first BD of a packet.
415 * This value is action meta-data that defines CFA edit operations that
416 * are done in addition to any action editing.
418 /* When key=1, This is the VLAN tag VID value. */
419 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
420 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
421 /* When key=1, This is the VLAN tag DE value. */
422 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
423 /* When key=1, This is the VLAN tag PRI value. */
424 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
425 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
426 /* When key=1, This is the VLAN tag TPID select value. */
427 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
428 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
430 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
432 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
434 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
436 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
438 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
439 /* Value programmed in CFA VLANTPID register. */
440 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
441 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
442 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
443 /* When key=1, This is the VLAN tag TPID select value. */
444 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
445 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
447 * This field identifies the type of edit to be performed on the packet.
448 * This value must be valid on the first BD of a packet.
450 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
451 #define TX_BD_LONG_CFA_META_KEY_SFT 28
453 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
455 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
456 * - PRI/DE value. - meta[11:0] - VID value.
458 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
459 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
461 } __attribute__((packed));
463 /* RX Producer Packet BD (16 bytes) */
464 struct rx_prod_pkt_bd {
465 /* This value identifies the type of buffer descriptor. */
466 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
467 #define RX_PROD_PKT_BD_TYPE_SFT 0
469 * Indicates that this BD is 16B long and is an RX Producer (ie.
470 * empty) buffer descriptor.
472 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT (UINT32_C(0x4) << 0)
474 * If set to 1, the packet will be placed at the address plus 2B. The 2
475 * Bytes of padding will be written as zero.
478 * This is intended to be used when the host buffer is cache-line
479 * aligned to produce packets that are easy to parse in host memory
480 * while still allowing writes to be cache line aligned.
482 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
484 * If set to 1, the packet write will be padded out to the nearest
485 * cache-line with zero value padding.
488 * If receive buffers start/end on cache-line boundaries, this feature
489 * will ensure that all data writes on the PCI bus start/end on cache
492 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
494 * This value is the number of additional buffers in the ring that
495 * describe the buffer space to be consumed for the this packet. If the
496 * value is zero, then the packet must fit within the space described by
497 * this BD. If this value is 1 or more, it indicates how many additional
498 * "buffer" BDs are in the ring immediately following this BD to be used
499 * for the same network packet. Even if the packet to be placed does not
500 * need all the additional buffers, they will be consumed anyway.
502 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
503 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
504 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
505 #define RX_PROD_PKT_BD_FLAGS_SFT 6
509 * This is the length in Bytes of the host physical buffer where data
510 * for the packet may be placed in host memory.
513 * While this is a Byte resolution value, it is often advantageous to
514 * ensure that the buffers provided end on a host cache line.
519 * The opaque data field is pass through to the completion and can be
520 * used for any data that the driver wants to associate with this
521 * receive buffer set.
526 * This is the host physical address where data for the packet may by
527 * placed in host memory.
530 * While this is a Byte resolution value, it is often advantageous to
531 * ensure that the buffers provide start on a host cache line.
534 } __attribute__((packed));
536 /* Completion Ring Structures */
537 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
538 /* Base Completion Record (16 bytes) */
542 * This field indicates the exact type of the completion. By convention,
543 * the LSB identifies the length of the record in 16B units. Even values
544 * indicate 16B records. Odd values indicate 32B records.
546 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
547 #define CMPL_BASE_TYPE_SFT 0
548 /* TX L2 completion: Completion of TX packet. Length = 16B */
549 #define CMPL_BASE_TYPE_TX_L2 (UINT32_C(0x0) << 0)
551 * RX L2 completion: Completion of and L2 RX packet.
554 #define CMPL_BASE_TYPE_RX_L2 (UINT32_C(0x11) << 0)
556 * RX Aggregation Buffer completion : Completion of an L2
557 * aggregation buffer in support of TPA, HDS, or Jumbo packet
558 * completion. Length = 16B
560 #define CMPL_BASE_TYPE_RX_AGG (UINT32_C(0x12) << 0)
562 * RX L2 TPA Start Completion: Completion at the beginning of a
563 * TPA operation. Length = 32B
565 #define CMPL_BASE_TYPE_RX_TPA_START (UINT32_C(0x13) << 0)
567 * RX L2 TPA End Completion: Completion at the end of a TPA
568 * operation. Length = 32B
570 #define CMPL_BASE_TYPE_RX_TPA_END (UINT32_C(0x15) << 0)
572 * Statistics Ejection Completion: Completion of statistics data
573 * ejection buffer. Length = 16B
575 #define CMPL_BASE_TYPE_STAT_EJECT (UINT32_C(0x1a) << 0)
576 /* HWRM Command Completion: Completion of an HWRM command. */
577 #define CMPL_BASE_TYPE_HWRM_DONE (UINT32_C(0x20) << 0)
578 /* Forwarded HWRM Request */
579 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
580 /* Forwarded HWRM Response */
581 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (UINT32_C(0x24) << 0)
582 /* HWRM Asynchronous Event Information */
583 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (UINT32_C(0x2e) << 0)
584 /* CQ Notification */
585 #define CMPL_BASE_TYPE_CQ_NOTIFICATION (UINT32_C(0x30) << 0)
586 /* SRQ Threshold Event */
587 #define CMPL_BASE_TYPE_SRQ_EVENT (UINT32_C(0x32) << 0)
588 /* DBQ Threshold Event */
589 #define CMPL_BASE_TYPE_DBQ_EVENT (UINT32_C(0x34) << 0)
590 /* QP Async Notification */
591 #define CMPL_BASE_TYPE_QP_EVENT (UINT32_C(0x38) << 0)
592 /* Function Async Notification */
593 #define CMPL_BASE_TYPE_FUNC_EVENT (UINT32_C(0x3a) << 0)
600 * This value is written by the NIC such that it will be different for
601 * each pass through the completion queue. The even passes will write 1.
602 * The odd passes will write 0.
604 #define CMPL_BASE_V UINT32_C(0x1)
606 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
607 #define CMPL_BASE_INFO3_SFT 1
611 } __attribute__((packed));
613 /* TX Completion Record (16 bytes) */
616 * This field indicates the exact type of the completion. By convention,
617 * the LSB identifies the length of the record in 16B units. Even values
618 * indicate 16B records. Odd values indicate 32B records.
620 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
621 #define TX_CMPL_TYPE_SFT 0
622 /* TX L2 completion: Completion of TX packet. Length = 16B */
623 #define TX_CMPL_TYPE_TX_L2 (UINT32_C(0x0) << 0)
625 * When this bit is '1', it indicates a packet that has an error of some
626 * type. Type of error is indicated in error_flags.
628 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
630 * When this bit is '1', it indicates that the packet completed was
631 * transmitted using the push acceleration data provided by the driver.
632 * When this bit is '0', it indicates that the packet had not push
633 * acceleration data written or was executed as a normal packet even
634 * though push data was provided.
636 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
637 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
638 #define TX_CMPL_FLAGS_SFT 6
644 * This is a copy of the opaque field from the first TX BD of this
645 * transmitted packet.
650 * This value is written by the NIC such that it will be different for
651 * each pass through the completion queue. The even passes will write 1.
652 * The odd passes will write 0.
654 #define TX_CMPL_V UINT32_C(0x1)
656 * This error indicates that there was some sort of problem with the BDs
659 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
660 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
662 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
663 /* Bad Format: BDs were not formatted correctly. */
664 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
665 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
666 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
668 * When this bit is '1', it indicates that the length of the packet was
669 * zero. No packet was transmitted.
671 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
673 * When this bit is '1', it indicates that the packet was longer than
674 * the programmed limit in TDI. No packet was transmitted.
676 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
678 * When this bit is '1', it indicates that one or more of the BDs
679 * associated with this packet generated a PCI error. This probably
680 * means the address was not valid.
682 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
684 * When this bit is '1', it indicates that the packet was longer than
685 * indicated by the hint. No packet was transmitted.
687 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
689 * When this bit is '1', it indicates that the packet was dropped due to
690 * Poison TLP error on one or more of the TLPs in the PXP completion.
692 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
693 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
694 #define TX_CMPL_ERRORS_SFT 1
699 } __attribute__((packed)) tx_cmpl_t, *ptx_cmpl_t;
701 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
704 * This field indicates the exact type of the completion. By convention,
705 * the LSB identifies the length of the record in 16B units. Even values
706 * indicate 16B records. Odd values indicate 32B records.
708 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
709 #define RX_PKT_CMPL_TYPE_SFT 0
711 * RX L2 completion: Completion of and L2 RX packet.
714 #define RX_PKT_CMPL_TYPE_RX_L2 (UINT32_C(0x11) << 0)
716 * When this bit is '1', it indicates a packet that has an error of some
717 * type. Type of error is indicated in error_flags.
719 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
720 /* This field indicates how the packet was placed in the buffer. */
721 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
722 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
723 /* Normal: Packet was placed using normal algorithm. */
724 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
725 /* Jumbo: Packet was placed using jumbo algorithm. */
726 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
728 * Header/Data Separation: Packet was placed using Header/Data
729 * separation algorithm. The separation location is indicated by
732 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
733 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
734 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
735 /* This bit is '1' if the RSS field in this completion is valid. */
736 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
738 * This value indicates what the inner packet determined for the packet
741 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
742 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
743 /* Not Known: Indicates that the packet type was not known. */
744 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
746 * IP Packet: Indicates that the packet was an IP packet, but
747 * further classification was not possible.
749 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
751 * TCP Packet: Indicates that the packet was IP and TCP. This
752 * indicates that the payload_offset field is valid.
754 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
756 * UDP Packet: Indicates that the packet was IP and UDP. This
757 * indicates that the payload_offset field is valid.
759 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
761 * FCoE Packet: Indicates that the packet was recognized as a
762 * FCoE. This also indicates that the payload_offset field is
765 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
767 * RoCE Packet: Indicates that the packet was recognized as a
768 * RoCE. This also indicates that the payload_offset field is
771 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
773 * ICMP Packet: Indicates that the packet was recognized as
774 * ICMP. This indicates that the payload_offset field is valid.
776 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
778 * PtP packet wo/timestamp: Indicates that the packet was
779 * recognized as a PtP packet.
781 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
782 (UINT32_C(0x8) << 12)
784 * PtP packet w/timestamp: Indicates that the packet was
785 * recognized as a PtP packet and that a timestamp was taken for
788 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
789 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
790 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
791 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
792 #define RX_PKT_CMPL_FLAGS_SFT 6
796 * This is the length of the data for the packet stored in the buffer(s)
797 * identified by the opaque value. This includes the packet BD and any
798 * associated buffer BDs. This does not include the the length of any
799 * data places in aggregation BDs.
804 * This is a copy of the opaque field from the RX BD this completion
810 * This value is written by the NIC such that it will be different for
811 * each pass through the completion queue. The even passes will write 1.
812 * The odd passes will write 0.
814 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
816 * This value is the number of aggregation buffers that follow this
817 * entry in the completion ring that are a part of this packet. If the
818 * value is zero, then the packet is completely contained in the buffer
819 * space provided for the packet in the RX ring.
821 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
822 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
826 * This is the RSS hash type for the packet. The value is packed
827 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
829 uint8_t rss_hash_type;
832 * This value indicates the offset from the beginning of the packet
833 * where the inner payload starts. This value is valid for TCP, UDP,
834 * FCoE, and RoCE packets.
836 uint8_t payload_offset;
841 * This value is the RSS hash value calculated for the packet based on
842 * the mode bits and key value in the VNIC.
845 } __attribute__((packed));
847 /* last 16 bytes of RX Packet Completion Record */
848 struct rx_pkt_cmpl_hi {
850 * This indicates that the ip checksum was calculated for the inner
851 * packet and that the ip_cs_error field indicates if there was an
854 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
856 * This indicates that the TCP, UDP or ICMP checksum was calculated for
857 * the inner packet and that the l4_cs_error field indicates if there
860 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
862 * This indicates that the ip checksum was calculated for the tunnel
863 * header and that the t_ip_cs_error field indicates if there was an
866 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
868 * This indicates that the UDP checksum was calculated for the tunnel
869 * packet and that the t_l4_cs_error field indicates if there was an
872 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
873 /* This value indicates what format the metadata field is. */
874 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
875 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
876 /* No metadata informtaion. Value is zero. */
877 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
879 * The metadata field contains the VLAN tag and TPID value. -
880 * metadata[11:0] contains the vlan VID value. - metadata[12]
881 * contains the vlan DE value. - metadata[15:13] contains the
882 * vlan PRI value. - metadata[31:16] contains the vlan TPID
885 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
886 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
887 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
889 * This field indicates the IP type for the inner-most IP header. A
890 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
891 * value is only valid if itype indicates a packet with an IP header.
893 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
897 * This is data from the CFA block as indicated by the meta_format
900 /* When meta_format=1, this value is the VLAN VID. */
901 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
902 #define RX_PKT_CMPL_METADATA_VID_SFT 0
903 /* When meta_format=1, this value is the VLAN DE. */
904 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
905 /* When meta_format=1, this value is the VLAN PRI. */
906 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
907 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
908 /* When meta_format=1, this value is the VLAN TPID. */
909 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
910 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
914 * This value is written by the NIC such that it will be different for
915 * each pass through the completion queue. The even passes will write 1.
916 * The odd passes will write 0.
918 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
920 * This error indicates that there was some sort of problem with the BDs
921 * for the packet that was found after part of the packet was already
922 * placed. The packet should be treated as invalid.
924 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
925 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
926 /* No buffer error */
927 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
930 * Did Not Fit: Packet did not fit into packet buffer provided.
931 * For regular placement, this means the packet did not fit in
932 * the buffer provided. For HDS and jumbo placement, this means
933 * that the packet could not be placed into 7 physical buffers
936 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
939 * Not On Chip: All BDs needed for the packet were not on-chip
940 * when the packet arrived.
942 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
944 /* Bad Format: BDs were not formatted correctly. */
945 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
947 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
948 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
949 /* This indicates that there was an error in the IP header checksum. */
950 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
952 * This indicates that there was an error in the TCP, UDP or ICMP
955 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
957 * This indicates that there was an error in the tunnel IP header
960 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
961 /* This indicates that there was an error in the tunnel UDP checksum. */
962 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
964 * This indicates that there was a CRC error on either an FCoE or RoCE
965 * packet. The itype indicates the packet type.
967 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
969 * This indicates that there was an error in the tunnel portion of the
970 * packet when this field is non-zero.
972 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
973 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
975 * No additional error occurred on the tunnel portion of the
976 * packet of the packet does not have a tunnel.
978 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
980 * Indicates that IP header version does not match expectation
981 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
983 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
986 * Indicates that header length is out of range in the tunnel
987 * header. Valid for IPv4.
989 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
992 * Indicates that the physical packet is shorter than that
993 * claimed by the PPPoE header length for a tunnel PPPoE packet.
995 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
998 * Indicates that physical packet is shorter than that claimed
999 * by the tunnel l3 header length. Valid for IPv4, or IPv6
1000 * tunnel packet packets.
1002 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
1003 (UINT32_C(0x4) << 9)
1005 * Indicates that the physical packet is shorter than that
1006 * claimed by the tunnel UDP header length for a tunnel UDP
1007 * packet that is not fragmented.
1009 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
1010 (UINT32_C(0x5) << 9)
1012 * indicates that the IPv4 TTL or IPv6 hop limit check have
1013 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
1016 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
1017 (UINT32_C(0x6) << 9)
1018 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
1019 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1021 * This indicates that there was an error in the inner portion of the
1022 * packet when this field is non-zero.
1024 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1025 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1027 * No additional error occurred on the tunnel portion of the
1028 * packet of the packet does not have a tunnel.
1030 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1032 * Indicates that IP header version does not match expectation
1033 * from L2 Ethertype for IPv4 and IPv6 or that option other than
1034 * VFT was parsed on FCoE packet.
1036 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
1037 (UINT32_C(0x1) << 12)
1039 * indicates that header length is out of range. Valid for IPv4
1042 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
1043 (UINT32_C(0x2) << 12)
1045 * indicates that the IPv4 TTL or IPv6 hop limit check have
1046 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
1048 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1050 * Indicates that physical packet is shorter than that claimed
1051 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
1054 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
1055 (UINT32_C(0x4) << 12)
1057 * Indicates that the physical packet is shorter than that
1058 * claimed by the UDP header length for a UDP packet that is not
1061 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
1062 (UINT32_C(0x5) << 12)
1064 * Indicates that TCP header length > IP payload. Valid for TCP
1067 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
1068 (UINT32_C(0x6) << 12)
1069 /* Indicates that TCP header length < 5. Valid for TCP. */
1070 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
1071 (UINT32_C(0x7) << 12)
1073 * Indicates that TCP option headers result in a TCP header size
1074 * that does not match data offset in TCP header. Valid for TCP.
1076 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
1077 (UINT32_C(0x8) << 12)
1078 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
1079 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1080 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1081 #define RX_PKT_CMPL_ERRORS_SFT 1
1085 * This field identifies the CFA action rule that was used for this
1091 * This value holds the reordering sequence number for the packet. If
1092 * the reordering sequence is not valid, then this value is zero. The
1093 * reordering domain for the packet is in the bottom 8 to 10b of the
1094 * rss_hash value. The bottom 20b of this value contain the ordering
1095 * domain value for the packet.
1097 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1098 #define RX_PKT_CMPL_REORDER_SFT 0
1100 } __attribute__((packed));
1102 /* HWRM Forwarded Request (16 bytes) */
1103 struct hwrm_fwd_req_cmpl {
1104 /* Length of forwarded request in bytes. */
1106 * This field indicates the exact type of the completion. By convention,
1107 * the LSB identifies the length of the record in 16B units. Even values
1108 * indicate 16B records. Odd values indicate 32B records.
1110 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
1111 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
1112 /* Forwarded HWRM Request */
1113 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (UINT32_C(0x22) << 0)
1114 /* Length of forwarded request in bytes. */
1115 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1116 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1117 uint16_t req_len_type;
1120 * Source ID of this request. Typically used in forwarding requests and
1121 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1122 * Reserved for internal processors 0xFFFF - HWRM
1128 /* Address of forwarded request. */
1130 * This value is written by the NIC such that it will be different for
1131 * each pass through the completion queue. The even passes will write 1.
1132 * The odd passes will write 0.
1134 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
1135 /* Address of forwarded request. */
1136 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1137 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1138 uint64_t req_buf_addr_v;
1139 } __attribute__((packed));
1141 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1142 struct hwrm_async_event_cmpl {
1144 * This field indicates the exact type of the completion. By convention,
1145 * the LSB identifies the length of the record in 16B units. Even values
1146 * indicate 16B records. Odd values indicate 32B records.
1148 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1149 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1150 /* HWRM Asynchronous Event Information */
1151 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT \
1152 (UINT32_C(0x2e) << 0)
1155 /* Identifiers of events. */
1156 /* Link status changed */
1157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
1158 (UINT32_C(0x0) << 0)
1159 /* Link MTU changed */
1160 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
1161 (UINT32_C(0x1) << 0)
1162 /* Link speed changed */
1163 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
1164 (UINT32_C(0x2) << 0)
1165 /* DCB Configuration changed */
1166 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
1167 (UINT32_C(0x3) << 0)
1168 /* Port connection not allowed */
1169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
1170 (UINT32_C(0x4) << 0)
1171 /* Link speed configuration was not allowed */
1172 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
1173 (UINT32_C(0x5) << 0)
1174 /* Function driver unloaded */
1175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
1176 (UINT32_C(0x10) << 0)
1177 /* Function driver loaded */
1178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
1179 (UINT32_C(0x11) << 0)
1180 /* PF driver unloaded */
1181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
1182 (UINT32_C(0x20) << 0)
1183 /* PF driver loaded */
1184 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
1185 (UINT32_C(0x21) << 0)
1186 /* VF Function Level Reset (FLR) */
1187 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (UINT32_C(0x30) << 0)
1188 /* VF MAC Address Change */
1189 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
1190 (UINT32_C(0x31) << 0)
1191 /* PF-VF communication channel status change. */
1192 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
1193 (UINT32_C(0x32) << 0)
1195 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
1196 (UINT32_C(0xff) << 0)
1199 /* Event specific data */
1200 uint32_t event_data2;
1204 * This value is written by the NIC such that it will be different for
1205 * each pass through the completion queue. The even passes will write 1.
1206 * The odd passes will write 0.
1208 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1210 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1211 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1214 /* 8-lsb timestamp from POR (100-msec resolution) */
1215 uint8_t timestamp_lo;
1217 /* 16-lsb timestamp from POR (100-msec resolution) */
1218 uint16_t timestamp_hi;
1220 /* Event specific data */
1221 uint32_t event_data1;
1222 } __attribute__((packed));
1225 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
1226 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
1227 * processors inside the chip. This firmware is vital part of the chip's
1228 * hardware. The chip can not be used by driver without it.
1231 /* Input (16 bytes) */
1234 * This value indicates what type of request this is. The format for the
1235 * rest of the command is determined by this field.
1240 * This value indicates the what completion ring the request will be
1241 * optionally completed on. If the value is -1, then no CR completion
1242 * will be generated. Any other value must be a valid CR ring_id value
1243 * for this function.
1247 /* This value indicates the command sequence number. */
1251 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1252 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1257 * This is the host address where the response will be written when the
1258 * request is complete. This area must be 16B aligned and must be
1259 * cleared to zero before the request is made.
1262 } __attribute__((packed));
1264 /* Output (8 bytes) */
1267 * Pass/Fail or error type Note: receiver to verify the in parameters,
1268 * and fail the call with an error when appropriate
1270 uint16_t error_code;
1272 /* This field returns the type of original request. */
1275 /* This field provides original sequence number of the command. */
1279 * This field is the length of the response in bytes. The last byte of
1280 * the response is a valid flag that will read as '1' when the command
1281 * has been completely written to memory.
1284 } __attribute__((packed));
1286 /* hwrm_cfa_l2_filter_alloc */
1288 * A filter is used to identify traffic that contains a matching set of
1289 * parameters like unicast or broadcast MAC address or a VLAN tag amongst
1290 * other things which then allows the ASIC to direct the incoming traffic
1291 * to an appropriate VNIC or Rx ring.
1294 /* Input (96 bytes) */
1295 struct hwrm_cfa_l2_filter_alloc_input {
1297 * This value indicates what type of request this is. The format for the
1298 * rest of the command is determined by this field.
1303 * This value indicates the what completion ring the request will be
1304 * optionally completed on. If the value is -1, then no CR completion
1305 * will be generated. Any other value must be a valid CR ring_id value
1306 * for this function.
1310 /* This value indicates the command sequence number. */
1314 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1315 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1320 * This is the host address where the response will be written when the
1321 * request is complete. This area must be 16B aligned and must be
1322 * cleared to zero before the request is made.
1327 * Enumeration denoting the RX, TX type of the resource. This
1328 * enumeration is used for resources that are similar for both TX and RX
1329 * paths of the chip.
1331 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
1334 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
1335 (UINT32_C(0x0) << 0)
1337 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
1338 (UINT32_C(0x1) << 0)
1339 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
1340 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
1342 * Setting of this flag indicates the applicability to the loopback
1345 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
1348 * Setting of this flag indicates drop action. If this flag is not set,
1349 * then it should be considered accept action.
1351 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
1354 * If this flag is set, all t_l2_* fields are invalid and they should
1355 * not be specified. If this flag is set, then l2_* fields refer to
1356 * fields of outermost L2 header.
1358 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
1362 /* This bit must be '1' for the l2_addr field to be configured. */
1363 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
1365 /* This bit must be '1' for the l2_addr_mask field to be configured. */
1366 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
1368 /* This bit must be '1' for the l2_ovlan field to be configured. */
1369 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
1371 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
1372 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
1374 /* This bit must be '1' for the l2_ivlan field to be configured. */
1375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
1377 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
1378 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
1380 /* This bit must be '1' for the t_l2_addr field to be configured. */
1381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
1384 * This bit must be '1' for the t_l2_addr_mask field to be configured.
1386 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
1388 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
1389 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
1392 * This bit must be '1' for the t_l2_ovlan_mask field to be configured.
1394 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
1396 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
1397 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
1400 * This bit must be '1' for the t_l2_ivlan_mask field to be configured.
1402 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
1404 /* This bit must be '1' for the src_type field to be configured. */
1405 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
1407 /* This bit must be '1' for the src_id field to be configured. */
1408 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
1410 /* This bit must be '1' for the tunnel_type field to be configured. */
1411 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
1413 /* This bit must be '1' for the dst_id field to be configured. */
1414 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
1417 * This bit must be '1' for the mirror_vnic_id field to be configured.
1419 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
1424 * This value sets the match value for the L2 MAC address. Destination
1425 * MAC address for RX path. Source MAC address for TX path.
1433 * This value sets the mask value for the L2 address. A value of 0 will
1434 * mask the corresponding bit from compare.
1436 uint8_t l2_addr_mask[6];
1438 /* This value sets VLAN ID value for outer VLAN. */
1442 * This value sets the mask value for the ovlan id. A value of 0 will
1443 * mask the corresponding bit from compare.
1445 uint16_t l2_ovlan_mask;
1447 /* This value sets VLAN ID value for inner VLAN. */
1451 * This value sets the mask value for the ivlan id. A value of 0 will
1452 * mask the corresponding bit from compare.
1454 uint16_t l2_ivlan_mask;
1460 * This value sets the match value for the tunnel L2 MAC address.
1461 * Destination MAC address for RX path. Source MAC address for TX path.
1463 uint8_t t_l2_addr[6];
1469 * This value sets the mask value for the tunnel L2 address. A value of
1470 * 0 will mask the corresponding bit from compare.
1472 uint8_t t_l2_addr_mask[6];
1474 /* This value sets VLAN ID value for tunnel outer VLAN. */
1475 uint16_t t_l2_ovlan;
1478 * This value sets the mask value for the tunnel ovlan id. A value of 0
1479 * will mask the corresponding bit from compare.
1481 uint16_t t_l2_ovlan_mask;
1483 /* This value sets VLAN ID value for tunnel inner VLAN. */
1484 uint16_t t_l2_ivlan;
1487 * This value sets the mask value for the tunnel ivlan id. A value of 0
1488 * will mask the corresponding bit from compare.
1490 uint16_t t_l2_ivlan_mask;
1492 /* This value identifies the type of source of the packet. */
1494 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT \
1495 (UINT32_C(0x0) << 0)
1496 /* Physical function */
1497 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF \
1498 (UINT32_C(0x1) << 0)
1499 /* Virtual function */
1500 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF \
1501 (UINT32_C(0x2) << 0)
1502 /* Virtual NIC of a function */
1503 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC \
1504 (UINT32_C(0x3) << 0)
1505 /* Embedded processor for CFA management */
1506 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG \
1507 (UINT32_C(0x4) << 0)
1508 /* Embedded processor for OOB management */
1509 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE \
1510 (UINT32_C(0x5) << 0)
1511 /* Embedded processor for RoCE */
1512 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO \
1513 (UINT32_C(0x6) << 0)
1514 /* Embedded processor for network proxy functions */
1515 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG \
1516 (UINT32_C(0x7) << 0)
1521 * This value is the id of the source. For a network port, it represents
1522 * port_id. For a physical function, it represents fid. For a virtual
1523 * function, it represents vf_id. For a vnic, it represents vnic_id. For
1524 * embedded processors, this id is not valid. Notes: 1. The function ID
1525 * is implied if it src_id is not provided for a src_type that is either
1531 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
1532 (UINT32_C(0x0) << 0)
1533 /* Virtual eXtensible Local Area Network (VXLAN) */
1534 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
1535 (UINT32_C(0x1) << 0)
1537 * Network Virtualization Generic Routing Encapsulation (NVGRE)
1539 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
1540 (UINT32_C(0x2) << 0)
1542 * Generic Routing Encapsulation (GRE) inside Ethernet payload
1544 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
1545 (UINT32_C(0x3) << 0)
1547 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
1548 (UINT32_C(0x4) << 0)
1549 /* Generic Network Virtualization Encapsulation (Geneve) */
1550 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
1551 (UINT32_C(0x5) << 0)
1552 /* Multi-Protocol Lable Switching (MPLS) */
1553 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
1554 (UINT32_C(0x6) << 0)
1555 /* Stateless Transport Tunnel (STT) */
1556 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
1557 (UINT32_C(0x7) << 0)
1559 * Generic Routing Encapsulation (GRE) inside IP datagram
1562 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
1563 (UINT32_C(0x8) << 0)
1564 /* Any tunneled traffic */
1565 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
1566 (UINT32_C(0xff) << 0)
1567 uint8_t tunnel_type;
1572 * If set, this value shall represent the Logical VNIC ID of the
1573 * destination VNIC for the RX path and network port id of the
1574 * destination port for the TX path.
1578 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
1579 uint16_t mirror_vnic_id;
1582 * This hint is provided to help in placing the filter in the filter
1586 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
1587 (UINT32_C(0x0) << 0)
1588 /* Above the given filter */
1589 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
1590 (UINT32_C(0x1) << 0)
1591 /* Below the given filter */
1592 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
1593 (UINT32_C(0x2) << 0)
1594 /* As high as possible */
1595 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
1596 (UINT32_C(0x3) << 0)
1597 /* As low as possible */
1598 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
1599 (UINT32_C(0x4) << 0)
1606 * This is the ID of the filter that goes along with the pri_hint. This
1607 * field is valid only for the following values. 1 - Above the given
1608 * filter 2 - Below the given filter
1610 uint64_t l2_filter_id_hint;
1611 } __attribute__((packed));
1613 /* Output (24 bytes) */
1614 struct hwrm_cfa_l2_filter_alloc_output {
1616 * Pass/Fail or error type Note: receiver to verify the in parameters,
1617 * and fail the call with an error when appropriate
1619 uint16_t error_code;
1621 /* This field returns the type of original request. */
1624 /* This field provides original sequence number of the command. */
1628 * This field is the length of the response in bytes. The last byte of
1629 * the response is a valid flag that will read as '1' when the command
1630 * has been completely written to memory.
1635 * This value identifies a set of CFA data structures used for an L2
1638 uint64_t l2_filter_id;
1641 * This is the ID of the flow associated with this filter. This value
1642 * shall be used to match and associate the flow identifier returned in
1643 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
1652 * This field is used in Output records to indicate that the output is
1653 * completely written to RAM. This field should be read as '1' to
1654 * indicate that the output has been completely written. When writing a
1655 * command completion or response to an internal processor, the order of
1656 * writes has to be such that this field is written last.
1659 } __attribute__((packed));
1661 /* hwrm_cfa_l2_filter_free */
1663 * Description: Free a L2 filter. The HWRM shall free all associated filter
1664 * resources with the L2 filter.
1667 /* Input (24 bytes) */
1668 struct hwrm_cfa_l2_filter_free_input {
1670 * This value indicates what type of request this is. The format for the
1671 * rest of the command is determined by this field.
1676 * This value indicates the what completion ring the request will be
1677 * optionally completed on. If the value is -1, then no CR completion
1678 * will be generated. Any other value must be a valid CR ring_id value
1679 * for this function.
1683 /* This value indicates the command sequence number. */
1687 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1688 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1693 * This is the host address where the response will be written when the
1694 * request is complete. This area must be 16B aligned and must be
1695 * cleared to zero before the request is made.
1700 * This value identifies a set of CFA data structures used for an L2
1703 uint64_t l2_filter_id;
1704 } __attribute__((packed));
1706 /* Output (16 bytes) */
1707 struct hwrm_cfa_l2_filter_free_output {
1709 * Pass/Fail or error type Note: receiver to verify the in parameters,
1710 * and fail the call with an error when appropriate
1712 uint16_t error_code;
1714 /* This field returns the type of original request. */
1717 /* This field provides original sequence number of the command. */
1721 * This field is the length of the response in bytes. The last byte of
1722 * the response is a valid flag that will read as '1' when the command
1723 * has been completely written to memory.
1733 * This field is used in Output records to indicate that the output is
1734 * completely written to RAM. This field should be read as '1' to
1735 * indicate that the output has been completely written. When writing a
1736 * command completion or response to an internal processor, the order of
1737 * writes has to be such that this field is written last.
1740 } __attribute__((packed));
1742 /* hwrm_cfa_l2_set_rx_mask */
1743 /* Description: This command will set rx mask of the function. */
1745 /* Input (40 bytes) */
1746 struct hwrm_cfa_l2_set_rx_mask_input {
1748 * This value indicates what type of request this is. The format for the
1749 * rest of the command is determined by this field.
1754 * This value indicates the what completion ring the request will be
1755 * optionally completed on. If the value is -1, then no CR completion
1756 * will be generated. Any other value must be a valid CR ring_id value
1757 * for this function.
1761 /* This value indicates the command sequence number. */
1765 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1766 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1771 * This is the host address where the response will be written when the
1772 * request is complete. This area must be 16B aligned and must be
1773 * cleared to zero before the request is made.
1780 /* Reserved for future use. */
1781 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_RESERVED UINT32_C(0x1)
1783 * When this bit is '1', the function is requested to accept multi-cast
1784 * packets specified by the multicast addr table.
1786 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
1788 * When this bit is '1', the function is requested to accept all multi-
1791 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
1793 * When this bit is '1', the function is requested to accept broadcast
1796 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
1798 * When this bit is '1', the function is requested to be put in the
1799 * promiscuous mode. The HWRM should accept any function to set up
1800 * promiscuous mode. The HWRM shall follow the semantics below for the
1801 * promiscuous mode support. # When partitioning is not enabled on a
1802 * port (i.e. single PF on the port), then the PF shall be allowed to be
1803 * in the promiscuous mode. When the PF is in the promiscuous mode, then
1804 * it shall receive all host bound traffic on that port. # When
1805 * partitioning is enabled on a port (i.e. multiple PFs per port) and a
1806 * PF on that port is in the promiscuous mode, then the PF receives all
1807 * traffic within that partition as identified by a unique identifier
1808 * for the PF (e.g. S-Tag). If a unique outer VLAN for the PF is
1809 * specified, then the setting of promiscuous mode on that PF shall
1810 * result in the PF receiving all host bound traffic with matching outer
1811 * VLAN. # A VF shall can be set in the promiscuous mode. In the
1812 * promiscuous mode, the VF does not receive any traffic unless a unique
1813 * outer VLAN for the VF is specified. If a unique outer VLAN for the VF
1814 * is specified, then the setting of promiscuous mode on that VF shall
1815 * result in the VF receiving all host bound traffic with the matching
1816 * outer VLAN. # The HWRM shall allow the setting of promiscuous mode on
1817 * a function independently from the promiscuous mode settings on other
1820 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
1822 * If this flag is set, the corresponding RX filters shall be set up to
1823 * cover multicast/broadcast filters for the outermost Layer 2
1824 * destination MAC address field.
1826 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
1829 /* This is the address for mcast address tbl. */
1830 uint64_t mc_tbl_addr;
1833 * This value indicates how many entries in mc_tbl are valid. Each entry
1836 uint32_t num_mc_entries;
1839 } __attribute__((packed));
1841 /* Output (16 bytes) */
1842 struct hwrm_cfa_l2_set_rx_mask_output {
1844 * Pass/Fail or error type Note: receiver to verify the in parameters,
1845 * and fail the call with an error when appropriate
1847 uint16_t error_code;
1849 /* This field returns the type of original request. */
1852 /* This field provides original sequence number of the command. */
1856 * This field is the length of the response in bytes. The last byte of
1857 * the response is a valid flag that will read as '1' when the command
1858 * has been completely written to memory.
1868 * This field is used in Output records to indicate that the output is
1869 * completely written to RAM. This field should be read as '1' to
1870 * indicate that the output has been completely written. When writing a
1871 * command completion or response to an internal processor, the order of
1872 * writes has to be such that this field is written last.
1875 } __attribute__((packed));
1877 /* hwrm_exec_fwd_resp */
1879 * Description: This command is used to send an encapsulated request to the
1880 * HWRM. This command instructs the HWRM to execute the request and forward the
1881 * response of the encapsulated request to the location specified in the
1882 * original request that is encapsulated. The target id of this command shall be
1883 * set to 0xFFFF (HWRM). The response location in this command shall be used to
1884 * acknowledge the receipt of the encapsulated request and forwarding of the
1888 /* Input (128 bytes) */
1889 struct hwrm_exec_fwd_resp_input {
1891 * This value indicates what type of request this is. The format for the
1892 * rest of the command is determined by this field.
1897 * This value indicates the what completion ring the request will be
1898 * optionally completed on. If the value is -1, then no CR completion
1899 * will be generated. Any other value must be a valid CR ring_id value
1900 * for this function.
1904 /* This value indicates the command sequence number. */
1908 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
1909 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1914 * This is the host address where the response will be written when the
1915 * request is complete. This area must be 16B aligned and must be
1916 * cleared to zero before the request is made.
1921 * This is an encapsulated request. This request should be executed by
1922 * the HWRM and the response should be provided in the response buffer
1923 * inside the encapsulated request.
1925 uint32_t encap_request[26];
1928 * This value indicates the target id of the response to the
1929 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
1930 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
1932 uint16_t encap_resp_target_id;
1934 uint16_t unused_0[3];
1935 } __attribute__((packed));
1937 /* Output (16 bytes) */
1938 struct hwrm_exec_fwd_resp_output {
1940 * Pass/Fail or error type Note: receiver to verify the in parameters,
1941 * and fail the call with an error when appropriate
1943 uint16_t error_code;
1945 /* This field returns the type of original request. */
1948 /* This field provides original sequence number of the command. */
1952 * This field is the length of the response in bytes. The last byte of
1953 * the response is a valid flag that will read as '1' when the command
1954 * has been completely written to memory.
1964 * This field is used in Output records to indicate that the output is
1965 * completely written to RAM. This field should be read as '1' to
1966 * indicate that the output has been completely written. When writing a
1967 * command completion or response to an internal processor, the order of
1968 * writes has to be such that this field is written last.
1971 } __attribute__((packed));
1973 /* hwrm_func_qcaps */
1975 * Description: This command returns capabilities of a function. The input FID
1976 * value is used to indicate what function is being queried. This allows a
1977 * physical function driver to query virtual functions that are children of the
1978 * physical function. The output FID value is needed to configure Rings and
1979 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
1982 /* Input (24 bytes) */
1983 struct hwrm_func_qcaps_input {
1985 * This value indicates what type of request this is. The format for the
1986 * rest of the command is determined by this field.
1991 * This value indicates the what completion ring the request will be
1992 * optionally completed on. If the value is -1, then no CR completion
1993 * will be generated. Any other value must be a valid CR ring_id value
1994 * for this function.
1998 /* This value indicates the command sequence number. */
2002 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2003 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2008 * This is the host address where the response will be written when the
2009 * request is complete. This area must be 16B aligned and must be
2010 * cleared to zero before the request is made.
2015 * Function ID of the function that is being queried. 0xFF... (All Fs)
2016 * if the query is for the requesting function.
2020 uint16_t unused_0[3];
2021 } __attribute__((packed));
2023 /* Output (80 bytes) */
2024 struct hwrm_func_qcaps_output {
2026 * Pass/Fail or error type Note: receiver to verify the in parameters,
2027 * and fail the call with an error when appropriate
2029 uint16_t error_code;
2031 /* This field returns the type of original request. */
2034 /* This field provides original sequence number of the command. */
2038 * This field is the length of the response in bytes. The last byte of
2039 * the response is a valid flag that will read as '1' when the command
2040 * has been completely written to memory.
2045 * FID value. This value is used to identify operations on the PCI bus
2046 * as belonging to a particular PCI function.
2051 * Port ID of port that this function is associated with. Valid only for
2052 * the PF. 0xFF... (All Fs) if this function is not associated with any
2053 * port. 0xFF... (All Fs) if this function is called from a VF.
2057 /* If 1, then Push mode is supported on this function. */
2058 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
2060 * If 1, then the global MSI-X auto-masking is enabled for the device.
2062 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
2065 * If 1, then the Precision Time Protocol (PTP) processing is supported
2066 * on this function. The HWRM should enable PTP on only a single
2067 * Physical Function (PF) per port.
2069 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
2073 * This value is current MAC address configured for this function. A
2074 * value of 00-00-00-00-00-00 indicates no MAC address is currently
2077 uint8_t perm_mac_address[6];
2080 * The maximum number of RSS/COS contexts that can be allocated to the
2083 uint16_t max_rsscos_ctx;
2086 * The maximum number of completion rings that can be allocated to the
2089 uint16_t max_cmpl_rings;
2092 * The maximum number of transmit rings that can be allocated to the
2095 uint16_t max_tx_rings;
2098 * The maximum number of receive rings that can be allocated to the
2101 uint16_t max_rx_rings;
2104 * The maximum number of L2 contexts that can be allocated to the
2107 uint16_t max_l2_ctxs;
2109 /* The maximum number of VNICs that can be allocated to the function. */
2113 * The identifier for the first VF enabled on a PF. This is valid only
2114 * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is
2115 * called on a PF with SR-IOV disabled or on a VF.
2117 uint16_t first_vf_id;
2120 * The maximum number of VFs that can be allocated to the function. This
2121 * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this
2122 * command is called on a PF with SR-IOV disabled or on a VF.
2127 * The maximum number of statistic contexts that can be allocated to the
2130 uint16_t max_stat_ctx;
2133 * The maximum number of Encapsulation records that can be offloaded by
2136 uint32_t max_encap_records;
2139 * The maximum number of decapsulation records that can be offloaded by
2142 uint32_t max_decap_records;
2145 * The maximum number of Exact Match (EM) flows that can be offloaded by
2146 * this function on the TX side.
2148 uint32_t max_tx_em_flows;
2151 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2152 * by this function on the TX side.
2154 uint32_t max_tx_wm_flows;
2157 * The maximum number of Exact Match (EM) flows that can be offloaded by
2158 * this function on the RX side.
2160 uint32_t max_rx_em_flows;
2163 * The maximum number of Wildcard Match (WM) flows that can be offloaded
2164 * by this function on the RX side.
2166 uint32_t max_rx_wm_flows;
2169 * The maximum number of multicast filters that can be supported by this
2170 * function on the RX side.
2172 uint32_t max_mcast_filters;
2175 * The maximum value of flow_id that can be supported in completion
2178 uint32_t max_flow_id;
2181 * The maximum number of HW ring groups that can be supported on this
2184 uint32_t max_hw_ring_grps;
2191 * This field is used in Output records to indicate that the output is
2192 * completely written to RAM. This field should be read as '1' to
2193 * indicate that the output has been completely written. When writing a
2194 * command completion or response to an internal processor, the order of
2195 * writes has to be such that this field is written last.
2198 } __attribute__((packed));
2200 /* hwrm_func_reset */
2202 * Description: This command resets a hardware function (PCIe function) and
2203 * frees any resources used by the function. This command shall be initiated by
2204 * the driver after an FLR has occurred to prepare the function for re-use. This
2205 * command may also be initiated by a driver prior to doing it's own
2206 * configuration. This command puts the function into the reset state. In the
2207 * reset state, global and port related features of the chip are not available.
2210 * Note: This command will reset a function that has already been disabled or
2211 * idled. The command returns all the resources owned by the function so a new
2212 * driver may allocate and configure resources normally.
2215 /* Input (24 bytes) */
2216 struct hwrm_func_reset_input {
2218 * This value indicates what type of request this is. The format for the
2219 * rest of the command is determined by this field.
2224 * This value indicates the what completion ring the request will be
2225 * optionally completed on. If the value is -1, then no CR completion
2226 * will be generated. Any other value must be a valid CR ring_id value
2227 * for this function.
2231 /* This value indicates the command sequence number. */
2235 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2236 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2241 * This is the host address where the response will be written when the
2242 * request is complete. This area must be 16B aligned and must be
2243 * cleared to zero before the request is made.
2247 /* This bit must be '1' for the vf_id_valid field to be configured. */
2248 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID \
2253 * The ID of the VF that this PF is trying to reset. Only the parent PF
2254 * shall be allowed to reset a child VF. A parent PF driver shall use
2255 * this field only when a specific child VF is requested to be reset.
2259 /* This value indicates the level of a function reset. */
2261 * Reset the caller function and its children VFs (if any). If
2262 * no children functions exist, then reset the caller function
2265 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
2266 (UINT32_C(0x0) << 0)
2267 /* Reset the caller function only */
2268 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
2269 (UINT32_C(0x1) << 0)
2271 * Reset all children VFs of the caller function driver if the
2272 * caller is a PF driver. It is an error to specify this level
2273 * by a VF driver. It is an error to specify this level by a PF
2274 * driver with no children VFs.
2276 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
2277 (UINT32_C(0x2) << 0)
2279 * Reset a specific VF of the caller function driver if the
2280 * caller is the parent PF driver. It is an error to specify
2281 * this level by a VF driver. It is an error to specify this
2282 * level by a PF driver that is not the parent of the VF that is
2283 * being requested to reset.
2285 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
2286 (UINT32_C(0x3) << 0)
2287 uint8_t func_reset_level;
2290 } __attribute__((packed));
2292 /* Output (16 bytes) */
2293 struct hwrm_func_reset_output {
2295 * Pass/Fail or error type Note: receiver to verify the in parameters,
2296 * and fail the call with an error when appropriate
2298 uint16_t error_code;
2300 /* This field returns the type of original request. */
2303 /* This field provides original sequence number of the command. */
2307 * This field is the length of the response in bytes. The last byte of
2308 * the response is a valid flag that will read as '1' when the command
2309 * has been completely written to memory.
2319 * This field is used in Output records to indicate that the output is
2320 * completely written to RAM. This field should be read as '1' to
2321 * indicate that the output has been completely written. When writing a
2322 * command completion or response to an internal processor, the order of
2323 * writes has to be such that this field is written last.
2326 } __attribute__((packed));
2328 /* hwrm_port_phy_cfg */
2330 * Description: This command configures the PHY device for the port. It allows
2331 * setting of the most generic settings for the PHY. The HWRM shall complete
2332 * this command as soon as PHY settings are configured. They may not be applied
2333 * when the command response is provided. A VF driver shall not be allowed to
2334 * configure PHY using this command. In a network partition mode, a PF driver
2335 * shall not be allowed to configure PHY using this command.
2338 /* Input (56 bytes) */
2339 struct hwrm_port_phy_cfg_input {
2341 * This value indicates what type of request this is. The format for the
2342 * rest of the command is determined by this field.
2347 * This value indicates the what completion ring the request will be
2348 * optionally completed on. If the value is -1, then no CR completion
2349 * will be generated. Any other value must be a valid CR ring_id value
2350 * for this function.
2354 /* This value indicates the command sequence number. */
2358 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2359 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2364 * This is the host address where the response will be written when the
2365 * request is complete. This area must be 16B aligned and must be
2366 * cleared to zero before the request is made.
2371 * When this bit is set to '1', the PHY for the port shall be reset. #
2372 * If this bit is set to 1, then the HWRM shall reset the PHY after
2373 * applying PHY configuration changes specified in this command. # In
2374 * order to guarantee that PHY configuration changes specified in this
2375 * command take effect, the HWRM client should set this flag to 1. # If
2376 * this bit is not set to 1, then the HWRM may reset the PHY depending
2377 * on the current PHY configuration and settings specified in this
2380 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
2382 * When this bit is set to '1', the link shall be forced to be taken
2383 * down. # When this bit is set to '1", all other command input settings
2384 * related to the link speed shall be ignored. Once the link state is
2385 * forced down, it can be explicitly cleared from that state by setting
2386 * this flag to '0'. # If this flag is set to '0', then the link shall
2387 * be cleared from forced down state if the link is in forced down
2388 * state. There may be conditions (e.g. out-of-band or sideband
2389 * configuration changes for the link) outside the scope of the HWRM
2390 * implementation that may clear forced down link state.
2392 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
2394 * When this bit is set to '1', the link shall be forced to the
2395 * force_link_speed value. When this bit is set to '1', the HWRM client
2396 * should not enable any of the auto negotiation related fields
2397 * represented by auto_XXX fields in this command. When this bit is set
2398 * to '1' and the HWRM client has enabled a auto_XXX field in this
2399 * command, then the HWRM shall ignore the enabled auto_XXX field. When
2400 * this bit is set to zero, the link shall be allowed to autoneg.
2402 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
2404 * When this bit is set to '1', the auto-negotiation process shall be
2405 * restarted on the link.
2407 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
2409 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2410 * requested to be enabled on this link. If EEE is not supported on this
2411 * port, then this flag shall be ignored by the HWRM.
2413 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
2415 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
2416 * requested to be disabled on this link. If EEE is not supported on
2417 * this port, then this flag shall be ignored by the HWRM.
2419 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
2421 * When this bit is set to '1' and EEE is enabled on this link, then TX
2422 * LPI is requested to be enabled on the link. If EEE is not supported
2423 * on this port, then this flag shall be ignored by the HWRM. If EEE is
2424 * disabled on this port, then this flag shall be ignored by the HWRM.
2426 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
2429 /* This bit must be '1' for the auto_mode field to be configured. */
2430 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
2431 /* This bit must be '1' for the auto_duplex field to be configured. */
2432 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
2433 /* This bit must be '1' for the auto_pause field to be configured. */
2434 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
2436 * This bit must be '1' for the auto_link_speed field to be configured.
2438 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
2440 * This bit must be '1' for the auto_link_speed_mask field to be
2443 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
2445 /* This bit must be '1' for the wirespeed field to be configured. */
2446 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
2447 /* This bit must be '1' for the lpbk field to be configured. */
2448 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
2449 /* This bit must be '1' for the preemphasis field to be configured. */
2450 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
2451 /* This bit must be '1' for the force_pause field to be configured. */
2452 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
2454 * This bit must be '1' for the eee_link_speed_mask field to be
2457 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
2459 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
2460 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
2463 /* Port ID of port that is to be configured. */
2467 * This is the speed that will be used if the force bit is '1'. If
2468 * unsupported speed is selected, an error will be generated.
2470 /* 100Mb link speed */
2471 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
2472 (UINT32_C(0x1) << 0)
2473 /* 1Gb link speed */
2474 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
2475 (UINT32_C(0xa) << 0)
2476 /* 2Gb link speed */
2477 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
2478 (UINT32_C(0x14) << 0)
2479 /* 2.5Gb link speed */
2480 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
2481 (UINT32_C(0x19) << 0)
2482 /* 10Gb link speed */
2483 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
2484 (UINT32_C(0x64) << 0)
2485 /* 20Mb link speed */
2486 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
2487 (UINT32_C(0xc8) << 0)
2488 /* 25Gb link speed */
2489 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
2490 (UINT32_C(0xfa) << 0)
2491 /* 40Gb link speed */
2492 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
2493 (UINT32_C(0x190) << 0)
2494 /* 50Gb link speed */
2495 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
2496 (UINT32_C(0x1f4) << 0)
2497 /* 100Gb link speed */
2498 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
2499 (UINT32_C(0x3e8) << 0)
2500 /* 10Mb link speed */
2501 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
2502 (UINT32_C(0xffff) << 0)
2503 uint16_t force_link_speed;
2506 * This value is used to identify what autoneg mode is used when the
2507 * link speed is not being forced.
2510 * Disable autoneg or autoneg disabled. No speeds are selected.
2512 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
2513 /* Select all possible speeds for autoneg mode. */
2514 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
2515 (UINT32_C(0x1) << 0)
2517 * Select only the auto_link_speed speed for autoneg mode. This
2518 * mode has been DEPRECATED. An HWRM client should not use this
2521 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
2522 (UINT32_C(0x2) << 0)
2524 * Select the auto_link_speed or any speed below that speed for
2525 * autoneg. This mode has been DEPRECATED. An HWRM client should
2526 * not use this mode.
2528 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
2529 (UINT32_C(0x3) << 0)
2531 * Select the speeds based on the corresponding link speed mask
2532 * value that is provided.
2534 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
2535 (UINT32_C(0x4) << 0)
2539 * This is the duplex setting that will be used if the autoneg_mode is
2540 * "one_speed" or "one_or_below".
2542 /* Half Duplex will be requested. */
2543 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
2544 (UINT32_C(0x0) << 0)
2545 /* Full duplex will be requested. */
2546 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
2547 (UINT32_C(0x1) << 0)
2548 /* Both Half and Full dupex will be requested. */
2549 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
2550 (UINT32_C(0x2) << 0)
2551 uint8_t auto_duplex;
2554 * This value is used to configure the pause that will be used for
2555 * autonegotiation. Add text on the usage of auto_pause and force_pause.
2558 * When this bit is '1', Generation of tx pause messages has been
2559 * requested. Disabled otherwise.
2561 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
2563 * When this bit is '1', Reception of rx pause messages has been
2564 * requested. Disabled otherwise.
2566 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
2568 * When set to 1, the advertisement of pause is enabled. # When the
2569 * auto_mode is not set to none and this flag is set to 1, then the
2570 * auto_pause bits on this port are being advertised and autoneg pause
2571 * results are being interpreted. # When the auto_mode is not set to
2572 * none and this flag is set to 0, the pause is forced as indicated in
2573 * force_pause, and also advertised as auto_pause bits, but the autoneg
2574 * results are not interpreted since the pause configuration is being
2575 * forced. # When the auto_mode is set to none and this flag is set to
2576 * 1, auto_pause bits should be ignored and should be set to 0.
2578 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
2584 * This is the speed that will be used if the autoneg_mode is
2585 * "one_speed" or "one_or_below". If an unsupported speed is selected,
2586 * an error will be generated.
2588 /* 100Mb link speed */
2589 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
2590 (UINT32_C(0x1) << 0)
2591 /* 1Gb link speed */
2592 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
2593 (UINT32_C(0xa) << 0)
2594 /* 2Gb link speed */
2595 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
2596 (UINT32_C(0x14) << 0)
2597 /* 2.5Gb link speed */
2598 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
2599 (UINT32_C(0x19) << 0)
2600 /* 10Gb link speed */
2601 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
2602 (UINT32_C(0x64) << 0)
2603 /* 20Mb link speed */
2604 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
2605 (UINT32_C(0xc8) << 0)
2606 /* 25Gb link speed */
2607 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
2608 (UINT32_C(0xfa) << 0)
2609 /* 40Gb link speed */
2610 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
2611 (UINT32_C(0x190) << 0)
2612 /* 50Gb link speed */
2613 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
2614 (UINT32_C(0x1f4) << 0)
2615 /* 100Gb link speed */
2616 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
2617 (UINT32_C(0x3e8) << 0)
2618 /* 10Mb link speed */
2619 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
2620 (UINT32_C(0xffff) << 0)
2621 uint16_t auto_link_speed;
2624 * This is a mask of link speeds that will be used if autoneg_mode is
2625 * "mask". If unsupported speed is enabled an error will be generated.
2627 /* 100Mb link speed (Half-duplex) */
2628 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
2630 /* 100Mb link speed (Full-duplex) */
2631 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
2633 /* 1Gb link speed (Half-duplex) */
2634 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
2636 /* 1Gb link speed (Full-duplex) */
2637 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
2639 /* 2Gb link speed */
2640 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
2642 /* 2.5Gb link speed */
2643 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
2645 /* 10Gb link speed */
2646 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
2648 /* 20Gb link speed */
2649 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
2651 /* 25Gb link speed */
2652 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
2654 /* 40Gb link speed */
2655 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
2657 /* 50Gb link speed */
2658 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
2660 /* 100Gb link speed */
2661 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
2663 /* 10Mb link speed (Half-duplex) */
2664 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
2666 /* 10Mb link speed (Full-duplex) */
2667 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
2669 uint16_t auto_link_speed_mask;
2671 /* This value controls the wirespeed feature. */
2672 /* Wirespeed feature is disabled. */
2673 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
2674 /* Wirespeed feature is enabled. */
2675 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
2678 /* This value controls the loopback setting for the PHY. */
2679 /* No loopback is selected. Normal operation. */
2680 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
2682 * The HW will be configured with local loopback such that host
2683 * data is sent back to the host without modification.
2685 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
2687 * The HW will be configured with remote loopback such that port
2688 * logic will send packets back out the transmitter that are
2691 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
2695 * This value is used to configure the pause that will be used for force
2699 * When this bit is '1', Generation of tx pause messages is supported.
2700 * Disabled otherwise.
2702 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
2704 * When this bit is '1', Reception of rx pause messages is supported.
2705 * Disabled otherwise.
2707 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
2708 uint8_t force_pause;
2713 * This value controls the pre-emphasis to be used for the link. Driver
2714 * should not set this value (use enable.preemphasis = 0) unless driver
2715 * is sure of setting. Normally HWRM FW will determine proper pre-
2718 uint32_t preemphasis;
2721 * Setting for link speed mask that is used to advertise speeds during
2722 * autonegotiation when EEE is enabled. This field is valid only when
2723 * EEE is enabled. The speeds specified in this field shall be a subset
2724 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
2725 * at least one speed shall be provided in this mask.
2728 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
2729 /* 100Mb link speed (Full-duplex) */
2730 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
2732 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
2733 /* 1Gb link speed (Full-duplex) */
2734 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
2736 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
2739 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
2741 /* 10Gb link speed */
2742 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
2744 uint16_t eee_link_speed_mask;
2750 * Reuested setting of TX LPI timer in microseconds. This field is valid
2751 * only when EEE is enabled and TX LPI is enabled.
2753 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
2755 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
2756 uint32_t tx_lpi_timer;
2759 } __attribute__((packed));
2761 /* Output (16 bytes) */
2762 struct hwrm_port_phy_cfg_output {
2764 * Pass/Fail or error type Note: receiver to verify the in parameters,
2765 * and fail the call with an error when appropriate
2767 uint16_t error_code;
2769 /* This field returns the type of original request. */
2772 /* This field provides original sequence number of the command. */
2776 * This field is the length of the response in bytes. The last byte of
2777 * the response is a valid flag that will read as '1' when the command
2778 * has been completely written to memory.
2788 * This field is used in Output records to indicate that the output is
2789 * completely written to RAM. This field should be read as '1' to
2790 * indicate that the output has been completely written. When writing a
2791 * command completion or response to an internal processor, the order of
2792 * writes has to be such that this field is written last.
2795 } __attribute__((packed));
2797 /* hwrm_port_phy_qcfg */
2798 /* Description: This command queries the PHY configuration for the port. */
2799 /* Input (24 bytes) */
2801 struct hwrm_port_phy_qcfg_input {
2803 * This value indicates what type of request this is. The format for the
2804 * rest of the command is determined by this field.
2809 * This value indicates the what completion ring the request will be
2810 * optionally completed on. If the value is -1, then no CR completion
2811 * will be generated. Any other value must be a valid CR ring_id value
2812 * for this function.
2816 /* This value indicates the command sequence number. */
2820 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
2821 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
2826 * This is the host address where the response will be written when the
2827 * request is complete. This area must be 16B aligned and must be
2828 * cleared to zero before the request is made.
2832 /* Port ID of port that is to be queried. */
2835 uint16_t unused_0[3];
2836 } __attribute__((packed));
2838 /* Output (96 bytes) */
2839 struct hwrm_port_phy_qcfg_output {
2841 * Pass/Fail or error type Note: receiver to verify the in parameters,
2842 * and fail the call with an error when appropriate
2844 uint16_t error_code;
2846 /* This field returns the type of original request. */
2849 /* This field provides original sequence number of the command. */
2853 * This field is the length of the response in bytes. The last byte of
2854 * the response is a valid flag that will read as '1' when the command
2855 * has been completely written to memory.
2859 /* This value indicates the current link status. */
2860 /* There is no link or cable detected. */
2861 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK (UINT32_C(0x0) << 0)
2862 /* There is no link, but a cable has been detected. */
2863 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL (UINT32_C(0x1) << 0)
2864 /* There is a link. */
2865 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK (UINT32_C(0x2) << 0)
2870 /* This value indicates the current link speed of the connection. */
2871 /* 100Mb link speed */
2872 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB \
2873 (UINT32_C(0x1) << 0)
2874 /* 1Gb link speed */
2875 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB \
2876 (UINT32_C(0xa) << 0)
2877 /* 2Gb link speed */
2878 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB \
2879 (UINT32_C(0x14) << 0)
2880 /* 2.5Gb link speed */
2881 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB \
2882 (UINT32_C(0x19) << 0)
2883 /* 10Gb link speed */
2884 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB \
2885 (UINT32_C(0x64) << 0)
2886 /* 20Mb link speed */
2887 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB \
2888 (UINT32_C(0xc8) << 0)
2889 /* 25Gb link speed */
2890 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB \
2891 (UINT32_C(0xfa) << 0)
2892 /* 40Gb link speed */
2893 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB \
2894 (UINT32_C(0x190) << 0)
2895 /* 50Gb link speed */
2896 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB \
2897 (UINT32_C(0x1f4) << 0)
2898 /* 100Gb link speed */
2899 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB \
2900 (UINT32_C(0x3e8) << 0)
2901 /* 10Mb link speed */
2902 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB \
2903 (UINT32_C(0xffff) << 0)
2904 uint16_t link_speed;
2906 /* This value is indicates the duplex of the current connection. */
2907 /* Half Duplex connection. */
2908 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_HALF (UINT32_C(0x0) << 0)
2909 /* Full duplex connection. */
2910 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL (UINT32_C(0x1) << 0)
2914 * This value is used to indicate the current pause configuration. When
2915 * autoneg is enabled, this value represents the autoneg results of
2916 * pause configuration.
2919 * When this bit is '1', Generation of tx pause messages is supported.
2920 * Disabled otherwise.
2922 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
2924 * When this bit is '1', Reception of rx pause messages is supported.
2925 * Disabled otherwise.
2927 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
2931 * The supported speeds for the port. This is a bit mask. For each speed
2932 * that is supported, the corrresponding bit will be set to '1'.
2934 /* 100Mb link speed (Half-duplex) */
2935 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
2937 /* 100Mb link speed (Full-duplex) */
2938 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
2940 /* 1Gb link speed (Half-duplex) */
2941 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
2943 /* 1Gb link speed (Full-duplex) */
2944 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
2946 /* 2Gb link speed */
2947 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
2949 /* 2.5Gb link speed */
2950 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
2952 /* 10Gb link speed */
2953 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
2955 /* 20Gb link speed */
2956 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
2958 /* 25Gb link speed */
2959 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
2961 /* 40Gb link speed */
2962 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
2964 /* 50Gb link speed */
2965 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
2967 /* 100Gb link speed */
2968 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
2970 /* 10Mb link speed (Half-duplex) */
2971 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
2973 /* 10Mb link speed (Full-duplex) */
2974 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
2976 uint16_t support_speeds;
2979 * Current setting of forced link speed. When the link speed is not
2980 * being forced, this value shall be set to 0.
2982 /* 100Mb link speed */
2983 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB \
2984 (UINT32_C(0x1) << 0)
2985 /* 1Gb link speed */
2986 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB \
2987 (UINT32_C(0xa) << 0)
2988 /* 2Gb link speed */
2989 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB \
2990 (UINT32_C(0x14) << 0)
2991 /* 2.5Gb link speed */
2992 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB \
2993 (UINT32_C(0x19) << 0)
2994 /* 10Gb link speed */
2995 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB \
2996 (UINT32_C(0x64) << 0)
2997 /* 20Mb link speed */
2998 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB \
2999 (UINT32_C(0xc8) << 0)
3000 /* 25Gb link speed */
3001 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB \
3002 (UINT32_C(0xfa) << 0)
3003 /* 40Gb link speed */
3004 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
3005 (UINT32_C(0x190) << 0)
3006 /* 50Gb link speed */
3007 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
3008 (UINT32_C(0x1f4) << 0)
3009 /* 100Gb link speed */
3010 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
3011 (UINT32_C(0x3e8) << 0)
3012 /* 10Mb link speed */
3013 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
3014 (UINT32_C(0xffff) << 0)
3015 uint16_t force_link_speed;
3017 /* Current setting of auto negotiation mode. */
3019 * Disable autoneg or autoneg disabled. No speeds are selected.
3021 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE \
3022 (UINT32_C(0x0) << 0)
3023 /* Select all possible speeds for autoneg mode. */
3024 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS \
3025 (UINT32_C(0x1) << 0)
3027 * Select only the auto_link_speed speed for autoneg mode. This
3028 * mode has been DEPRECATED. An HWRM client should not use this
3031 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED \
3032 (UINT32_C(0x2) << 0)
3034 * Select the auto_link_speed or any speed below that speed for
3035 * autoneg. This mode has been DEPRECATED. An HWRM client should
3036 * not use this mode.
3038 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW \
3039 (UINT32_C(0x3) << 0)
3041 * Select the speeds based on the corresponding link speed mask
3042 * value that is provided.
3044 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK \
3045 (UINT32_C(0x4) << 0)
3049 * Current setting of pause autonegotiation. Move autoneg_pause flag
3053 * When this bit is '1', Generation of tx pause messages has been
3054 * requested. Disabled otherwise.
3056 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
3058 * When this bit is '1', Reception of rx pause messages has been
3059 * requested. Disabled otherwise.
3061 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
3063 * When set to 1, the advertisement of pause is enabled. # When the
3064 * auto_mode is not set to none and this flag is set to 1, then the
3065 * auto_pause bits on this port are being advertised and autoneg pause
3066 * results are being interpreted. # When the auto_mode is not set to
3067 * none and this flag is set to 0, the pause is forced as indicated in
3068 * force_pause, and also advertised as auto_pause bits, but the autoneg
3069 * results are not interpreted since the pause configuration is being
3070 * forced. # When the auto_mode is set to none and this flag is set to
3071 * 1, auto_pause bits should be ignored and should be set to 0.
3073 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
3078 * Current setting for auto_link_speed. This field is only valid when
3079 * auto_mode is set to "one_speed" or "one_or_below".
3081 /* 100Mb link speed */
3082 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB \
3083 (UINT32_C(0x1) << 0)
3084 /* 1Gb link speed */
3085 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB \
3086 (UINT32_C(0xa) << 0)
3087 /* 2Gb link speed */
3088 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB \
3089 (UINT32_C(0x14) << 0)
3090 /* 2.5Gb link speed */
3091 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB \
3092 (UINT32_C(0x19) << 0)
3093 /* 10Gb link speed */
3094 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB \
3095 (UINT32_C(0x64) << 0)
3096 /* 20Mb link speed */
3097 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB \
3098 (UINT32_C(0xc8) << 0)
3099 /* 25Gb link speed */
3100 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB \
3101 (UINT32_C(0xfa) << 0)
3102 /* 40Gb link speed */
3103 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB \
3104 (UINT32_C(0x190) << 0)
3105 /* 50Gb link speed */
3106 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB \
3107 (UINT32_C(0x1f4) << 0)
3108 /* 100Gb link speed */
3109 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB \
3110 (UINT32_C(0x3e8) << 0)
3111 /* 10Mb link speed */
3112 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
3113 (UINT32_C(0xffff) << 0)
3114 uint16_t auto_link_speed;
3117 * Current setting for auto_link_speed_mask that is used to advertise
3118 * speeds during autonegotiation. This field is only valid when
3119 * auto_mode is set to "mask". The speeds specified in this field shall
3120 * be a subset of supported speeds on this port.
3122 /* 100Mb link speed (Half-duplex) */
3123 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
3125 /* 100Mb link speed (Full-duplex) */
3126 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
3128 /* 1Gb link speed (Half-duplex) */
3129 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
3131 /* 1Gb link speed (Full-duplex) */
3132 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
3134 /* 2Gb link speed */
3135 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
3137 /* 2.5Gb link speed */
3138 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
3140 /* 10Gb link speed */
3141 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
3143 /* 20Gb link speed */
3144 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
3146 /* 25Gb link speed */
3147 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
3149 /* 40Gb link speed */
3150 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
3152 /* 50Gb link speed */
3153 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
3155 /* 100Gb link speed */
3156 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
3158 /* 10Mb link speed (Half-duplex) */
3159 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
3161 /* 10Mb link speed (Full-duplex) */
3162 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
3164 uint16_t auto_link_speed_mask;
3166 /* Current setting for wirespeed. */
3167 /* Wirespeed feature is disabled. */
3168 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
3169 /* Wirespeed feature is enabled. */
3170 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
3173 /* Current setting for loopback. */
3174 /* No loopback is selected. Normal operation. */
3175 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE (UINT32_C(0x0) << 0)
3177 * The HW will be configured with local loopback such that host
3178 * data is sent back to the host without modification.
3180 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
3182 * The HW will be configured with remote loopback such that port
3183 * logic will send packets back out the transmitter that are
3186 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
3190 * Current setting of forced pause. When the pause configuration is not
3191 * being forced, then this value shall be set to 0.
3194 * When this bit is '1', Generation of tx pause messages is supported.
3195 * Disabled otherwise.
3197 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX \
3200 * When this bit is '1', Reception of rx pause messages is supported.
3201 * Disabled otherwise.
3203 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX \
3205 uint8_t force_pause;
3208 * This value indicates the current status of the optics module on this
3211 /* Module is inserted and accepted */
3212 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
3213 (UINT32_C(0x0) << 0)
3214 /* Module is rejected and transmit side Laser is disabled. */
3215 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
3216 (UINT32_C(0x1) << 0)
3217 /* Module mismatch warning. */
3218 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
3219 (UINT32_C(0x2) << 0)
3220 /* Module is rejected and powered down. */
3221 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
3222 (UINT32_C(0x3) << 0)
3223 /* Module is not inserted. */
3224 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
3225 (UINT32_C(0x4) << 0)
3226 /* Module status is not applicable. */
3227 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
3228 (UINT32_C(0xff) << 0)
3229 uint8_t module_status;
3231 /* Current setting for preemphasis. */
3232 uint32_t preemphasis;
3234 /* This field represents the major version of the PHY. */
3237 /* This field represents the minor version of the PHY. */
3240 /* This field represents the build version of the PHY. */
3243 /* This value represents a PHY type. */
3245 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
3246 (UINT32_C(0x0) << 0)
3248 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
3249 (UINT32_C(0x1) << 0)
3250 /* BASE-KR4 (Deprecated) */
3251 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
3252 (UINT32_C(0x2) << 0)
3254 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
3255 (UINT32_C(0x3) << 0)
3257 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
3258 (UINT32_C(0x4) << 0)
3259 /* BASE-KR2 (Deprecated) */
3260 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
3261 (UINT32_C(0x5) << 0)
3263 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
3264 (UINT32_C(0x6) << 0)
3266 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
3267 (UINT32_C(0x7) << 0)
3269 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
3270 (UINT32_C(0x8) << 0)
3271 /* EEE capable BASE-T */
3272 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
3273 (UINT32_C(0x9) << 0)
3274 /* SGMII connected external PHY */
3275 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
3276 (UINT32_C(0xa) << 0)
3279 /* This value represents a media type. */
3281 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN \
3282 (UINT32_C(0x0) << 0)
3284 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP (UINT32_C(0x1) << 0)
3285 /* Direct Attached Copper */
3286 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC \
3287 (UINT32_C(0x2) << 0)
3289 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE \
3290 (UINT32_C(0x3) << 0)
3293 /* This value represents a transceiver type. */
3294 /* PHY and MAC are in the same package */
3295 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
3296 (UINT32_C(0x1) << 0)
3297 /* PHY and MAC are in different packages */
3298 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
3299 (UINT32_C(0x2) << 0)
3300 uint8_t xcvr_pkg_type;
3303 * This field represents flags related to EEE configuration. These EEE
3304 * configuration flags are valid only when the auto_mode is not set to
3305 * none (in other words autonegotiation is enabled).
3307 /* This field represents PHY address. */
3308 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
3309 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
3311 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
3312 * Speeds for autoneg with EEE mode enabled are based on
3313 * eee_link_speed_mask.
3315 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
3318 * This flag is valid only when eee_enabled is set to 1. # If
3319 * eee_enabled is set to 0, then EEE mode is disabled and this flag
3320 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
3321 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and in
3322 * use. # If eee_enabled is set to 1 and this flag is set to 0, then
3323 * Energy Efficient Ethernet (EEE) mode is enabled but is currently not
3326 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
3329 * This flag is valid only when eee_enabled is set to 1. # If
3330 * eee_enabled is set to 0, then EEE mode is disabled and this flag
3331 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
3332 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and TX LPI
3333 * is enabled. # If eee_enabled is set to 1 and this flag is set to 0,
3334 * then Energy Efficient Ethernet (EEE) mode is enabled but TX LPI is
3337 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
3340 * This field represents flags related to EEE configuration. These EEE
3341 * configuration flags are valid only when the auto_mode is not set to
3342 * none (in other words autonegotiation is enabled).
3344 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
3346 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
3347 uint8_t eee_config_phy_addr;
3349 /* Reserved field, set to 0 */
3351 * When set to 1, the parallel detection is used to determine the speed
3352 * of the link partner. Parallel detection is used when a
3353 * autonegotiation capable device is connected to a link parter that is
3354 * not capable of autonegotiation.
3356 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT \
3358 /* Reserved field, set to 0 */
3359 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_MASK UINT32_C(0xfe)
3360 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_SFT 1
3361 uint8_t parallel_detect;
3364 * The advertised speeds for the port by the link partner. Each
3365 * advertised speed will be set to '1'.
3367 /* 100Mb link speed (Half-duplex) */
3368 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
3370 /* 100Mb link speed (Full-duplex) */
3371 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
3373 /* 1Gb link speed (Half-duplex) */
3374 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
3376 /* 1Gb link speed (Full-duplex) */
3377 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
3379 /* 2Gb link speed */
3380 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
3382 /* 2.5Gb link speed */
3383 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
3385 /* 10Gb link speed */
3386 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
3388 /* 20Gb link speed */
3389 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
3391 /* 25Gb link speed */
3392 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
3394 /* 40Gb link speed */
3395 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
3397 /* 50Gb link speed */
3398 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
3400 /* 100Gb link speed */
3401 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
3403 /* 10Mb link speed (Half-duplex) */
3404 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
3406 /* 10Mb link speed (Full-duplex) */
3407 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
3409 uint16_t link_partner_adv_speeds;
3412 * The advertised autoneg for the port by the link partner. This field
3413 * is deprecated and should be set to 0.
3416 * Disable autoneg or autoneg disabled. No speeds are selected.
3418 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
3419 (UINT32_C(0x0) << 0)
3420 /* Select all possible speeds for autoneg mode. */
3421 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS\
3422 (UINT32_C(0x1) << 0)
3424 * Select only the auto_link_speed speed for autoneg mode. This
3425 * mode has been DEPRECATED. An HWRM client should not use this
3428 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
3429 (UINT32_C(0x2) << 0)
3431 * Select the auto_link_speed or any speed below that speed for
3432 * autoneg. This mode has been DEPRECATED. An HWRM client should
3433 * not use this mode.
3436 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
3437 (UINT32_C(0x3) << 0)
3439 * Select the speeds based on the corresponding link speed mask
3440 * value that is provided.
3442 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK\
3443 (UINT32_C(0x4) << 0)
3444 uint8_t link_partner_adv_auto_mode;
3446 /* The advertised pause settings on the port by the link partner. */
3448 * When this bit is '1', Generation of tx pause messages is supported.
3449 * Disabled otherwise.
3451 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
3454 * When this bit is '1', Reception of rx pause messages is supported.
3455 * Disabled otherwise.
3457 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
3459 uint8_t link_partner_adv_pause;
3462 * Current setting for link speed mask that is used to advertise speeds
3463 * during autonegotiation when EEE is enabled. This field is valid only
3464 * when eee_enabled flags is set to 1. The speeds specified in this
3465 * field shall be a subset of speeds specified in auto_link_speed_mask.
3468 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
3470 /* 100Mb link speed (Full-duplex) */
3471 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
3474 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
3476 /* 1Gb link speed (Full-duplex) */
3477 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
3480 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
3483 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
3485 /* 10Gb link speed */
3486 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
3488 uint16_t adv_eee_link_speed_mask;
3491 * Current setting for link speed mask that is advertised by the link
3492 * partner when EEE is enabled. This field is valid only when
3493 * eee_enabled flags is set to 1.
3497 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
3499 /* 100Mb link speed (Full-duplex) */
3501 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
3505 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
3507 /* 1Gb link speed (Full-duplex) */
3509 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
3513 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
3517 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
3519 /* 10Gb link speed */
3521 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
3523 uint16_t link_partner_adv_eee_link_speed_mask;
3525 /* This value represents transceiver identifier type. */
3527 * Current setting of TX LPI timer in microseconds. This field is valid
3528 * only when_eee_enabled flag is set to 1 and tx_lpi_enabled is set to
3531 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
3533 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
3534 /* This value represents transceiver identifier type. */
3535 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
3536 UINT32_C(0xff000000)
3537 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT \
3540 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
3541 (UINT32_C(0x0) << 24)
3542 /* SFP/SFP+/SFP28 */
3543 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
3544 (UINT32_C(0x3) << 24)
3546 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
3547 (UINT32_C(0xc) << 24)
3549 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
3550 (UINT32_C(0xd) << 24)
3552 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
3553 (UINT32_C(0x11) << 24)
3554 uint32_t xcvr_identifier_type_tx_lpi_timer;
3559 * Up to 16 bytes of null padded ASCII string representing PHY vendor.
3560 * If the string is set to null, then the vendor name is not available.
3562 char phy_vendor_name[16];
3565 * Up to 16 bytes of null padded ASCII string that identifies vendor
3566 * specific part number of the PHY. If the string is set to null, then
3567 * the vendor specific part number is not available.
3569 char phy_vendor_partnumber[16];
3577 * This field is used in Output records to indicate that the output is
3578 * completely written to RAM. This field should be read as '1' to
3579 * indicate that the output has been completely written. When writing a
3580 * command completion or response to an internal processor, the order of
3581 * writes has to be such that this field is written last.
3584 } __attribute__((packed));
3588 * Description: This function is called by a driver to determine the HWRM
3589 * interface version supported by the HWRM firmware, the version of HWRM
3590 * firmware implementation, the name of HWRM firmware, the versions of other
3591 * embedded firmwares, and the names of other embedded firmwares, etc. Any
3592 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
3593 * be considered an invalid version.
3596 /* Input (24 bytes) */
3597 struct hwrm_ver_get_input {
3599 * This value indicates what type of request this is. The format for the
3600 * rest of the command is determined by this field.
3605 * This value indicates the what completion ring the request will be
3606 * optionally completed on. If the value is -1, then no CR completion
3607 * will be generated. Any other value must be a valid CR ring_id value
3608 * for this function.
3612 /* This value indicates the command sequence number. */
3616 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3617 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3622 * This is the host address where the response will be written when the
3623 * request is complete. This area must be 16B aligned and must be
3624 * cleared to zero before the request is made.
3629 * This field represents the major version of HWRM interface
3630 * specification supported by the driver HWRM implementation. The
3631 * interface major version is intended to change only when non backward
3632 * compatible changes are made to the HWRM interface specification.
3634 uint8_t hwrm_intf_maj;
3637 * This field represents the minor version of HWRM interface
3638 * specification supported by the driver HWRM implementation. A change
3639 * in interface minor version is used to reflect significant backward
3640 * compatible modification to HWRM interface specification. This can be
3641 * due to addition or removal of functionality. HWRM interface
3642 * specifications with the same major version but different minor
3643 * versions are compatible.
3645 uint8_t hwrm_intf_min;
3648 * This field represents the update version of HWRM interface
3649 * specification supported by the driver HWRM implementation. The
3650 * interface update version is used to reflect minor changes or bug
3651 * fixes to a released HWRM interface specification.
3653 uint8_t hwrm_intf_upd;
3655 uint8_t unused_0[5];
3656 } __attribute__((packed));
3658 /* Output (128 bytes) */
3659 struct hwrm_ver_get_output {
3661 * Pass/Fail or error type Note: receiver to verify the in parameters,
3662 * and fail the call with an error when appropriate
3664 uint16_t error_code;
3666 /* This field returns the type of original request. */
3669 /* This field provides original sequence number of the command. */
3673 * This field is the length of the response in bytes. The last byte of
3674 * the response is a valid flag that will read as '1' when the command
3675 * has been completely written to memory.
3680 * This field represents the major version of HWRM interface
3681 * specification supported by the HWRM implementation. The interface
3682 * major version is intended to change only when non backward compatible
3683 * changes are made to the HWRM interface specification. A HWRM
3684 * implementation that is compliant with this specification shall
3685 * provide value of 1 in this field.
3687 uint8_t hwrm_intf_maj;
3690 * This field represents the minor version of HWRM interface
3691 * specification supported by the HWRM implementation. A change in
3692 * interface minor version is used to reflect significant backward
3693 * compatible modification to HWRM interface specification. This can be
3694 * due to addition or removal of functionality. HWRM interface
3695 * specifications with the same major version but different minor
3696 * versions are compatible. A HWRM implementation that is compliant with
3697 * this specification shall provide value of 0 in this field.
3699 uint8_t hwrm_intf_min;
3702 * This field represents the update version of HWRM interface
3703 * specification supported by the HWRM implementation. The interface
3704 * update version is used to reflect minor changes or bug fixes to a
3705 * released HWRM interface specification. A HWRM implementation that is
3706 * compliant with this specification shall provide value of 1 in this
3709 uint8_t hwrm_intf_upd;
3711 uint8_t hwrm_intf_rsvd;
3714 * This field represents the major version of HWRM firmware. A change in
3715 * firmware major version represents a major firmware release.
3717 uint8_t hwrm_fw_maj;
3720 * This field represents the minor version of HWRM firmware. A change in
3721 * firmware minor version represents significant firmware functionality
3724 uint8_t hwrm_fw_min;
3727 * This field represents the build version of HWRM firmware. A change in
3728 * firmware build version represents bug fixes to a released firmware.
3730 uint8_t hwrm_fw_bld;
3733 * This field is a reserved field. This field can be used to represent
3734 * firmware branches or customer specific releases tied to a specific
3735 * (major,minor,update) version of the HWRM firmware.
3737 uint8_t hwrm_fw_rsvd;
3740 * This field represents the major version of mgmt firmware. A change in
3741 * major version represents a major release.
3743 uint8_t mgmt_fw_maj;
3746 * This field represents the minor version of mgmt firmware. A change in
3747 * minor version represents significant functionality changes.
3749 uint8_t mgmt_fw_min;
3752 * This field represents the build version of mgmt firmware. A change in
3753 * update version represents bug fixes.
3755 uint8_t mgmt_fw_bld;
3758 * This field is a reserved field. This field can be used to represent
3759 * firmware branches or customer specific releases tied to a specific
3760 * (major,minor,update) version
3762 uint8_t mgmt_fw_rsvd;
3765 * This field represents the major version of network control firmware.
3766 * A change in major version represents a major release.
3768 uint8_t netctrl_fw_maj;
3771 * This field represents the minor version of network control firmware.
3772 * A change in minor version represents significant functionality
3775 uint8_t netctrl_fw_min;
3778 * This field represents the build version of network control firmware.
3779 * A change in update version represents bug fixes.
3781 uint8_t netctrl_fw_bld;
3784 * This field is a reserved field. This field can be used to represent
3785 * firmware branches or customer specific releases tied to a specific
3786 * (major,minor,update) version
3788 uint8_t netctrl_fw_rsvd;
3791 * This field is reserved for future use. The responder should set it to
3792 * 0. The requester should ignore this field.
3797 * This field represents the major version of RoCE firmware. A change in
3798 * major version represents a major release.
3800 uint8_t roce_fw_maj;
3803 * This field represents the minor version of RoCE firmware. A change in
3804 * minor version represents significant functionality changes.
3806 uint8_t roce_fw_min;
3809 * This field represents the build version of RoCE firmware. A change in
3810 * update version represents bug fixes.
3812 uint8_t roce_fw_bld;
3815 * This field is a reserved field. This field can be used to represent
3816 * firmware branches or customer specific releases tied to a specific
3817 * (major,minor,update) version
3819 uint8_t roce_fw_rsvd;
3822 * This field represents the name of HWRM FW (ASCII chars without NULL
3825 char hwrm_fw_name[16];
3828 * This field represents the name of mgmt FW (ASCII chars without NULL
3831 char mgmt_fw_name[16];
3834 * This field represents the name of network control firmware (ASCII
3835 * chars without NULL at the end).
3837 char netctrl_fw_name[16];
3840 * This field is reserved for future use. The responder should set it to
3841 * 0. The requester should ignore this field.
3843 uint32_t reserved2[4];
3846 * This field represents the name of RoCE FW (ASCII chars without NULL
3849 char roce_fw_name[16];
3851 /* This field returns the chip number. */
3854 /* This field returns the revision of chip. */
3857 /* This field returns the chip metal number. */
3860 /* This field returns the bond id of the chip. */
3861 uint8_t chip_bond_id;
3864 * This value indicates the type of platform used for chip
3868 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC \
3869 (UINT32_C(0x0) << 0)
3870 /* FPGA platform of the chip. */
3871 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA \
3872 (UINT32_C(0x1) << 0)
3873 /* Palladium platform of the chip. */
3874 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM \
3875 (UINT32_C(0x2) << 0)
3876 uint8_t chip_platform_type;
3879 * This field returns the maximum value of request window that is
3880 * supported by the HWRM. The request window is mapped into device
3881 * address space using MMIO.
3883 uint16_t max_req_win_len;
3886 * This field returns the maximum value of response buffer in bytes. If
3887 * a request specifies the response buffer length that is greater than
3888 * this value, then the HWRM should fail it. The value of this field
3889 * shall be 4KB or more.
3891 uint16_t max_resp_len;
3894 * This field returns the default request timeout value in milliseconds.
3896 uint16_t def_req_timeout;
3903 * This field is used in Output records to indicate that the output is
3904 * completely written to RAM. This field should be read as '1' to
3905 * indicate that the output has been completely written. When writing a
3906 * command completion or response to an internal processor, the order of
3907 * writes has to be such that this field is written last.
3910 } __attribute__((packed));
3912 /* hwrm_queue_qportcfg */
3914 * Description: This function is called by a driver to query queue configuration
3915 * of a port. # The HWRM shall at least advertise one queue with lossy service
3916 * profile. # The driver shall use this command to query queue ids before
3917 * configuring or using any queues. # If a service profile is not set for a
3918 * queue, then the driver shall not use that queue without configuring a service
3919 * profile for it. # If the driver is not allowed to configure service profiles,
3920 * then the driver shall only use queues for which service profiles are pre-
3924 /* Input (24 bytes) */
3925 struct hwrm_queue_qportcfg_input {
3927 * This value indicates what type of request this is. The format for the
3928 * rest of the command is determined by this field.
3933 * This value indicates the what completion ring the request will be
3934 * optionally completed on. If the value is -1, then no CR completion
3935 * will be generated. Any other value must be a valid CR ring_id value
3936 * for this function.
3940 /* This value indicates the command sequence number. */
3944 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
3945 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
3950 * This is the host address where the response will be written when the
3951 * request is complete. This area must be 16B aligned and must be
3952 * cleared to zero before the request is made.
3957 * Enumeration denoting the RX, TX type of the resource. This
3958 * enumeration is used for resources that are similar for both TX and RX
3959 * paths of the chip.
3961 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH \
3964 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX \
3965 (UINT32_C(0x0) << 0)
3967 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX \
3968 (UINT32_C(0x1) << 0)
3969 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
3970 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
3974 * Port ID of port for which the queue configuration is being queried.
3975 * This field is only required when sent by IPC.
3980 } __attribute__((packed));
3982 /* hwrm_ring_alloc */
3984 * Description: This command allocates and does basic preparation for a ring.
3987 /* Input (80 bytes) */
3988 struct hwrm_ring_alloc_input {
3990 * This value indicates what type of request this is. The format for the
3991 * rest of the command is determined by this field.
3996 * This value indicates the what completion ring the request will be
3997 * optionally completed on. If the value is -1, then no CR completion
3998 * will be generated. Any other value must be a valid CR ring_id value
3999 * for this function.
4003 /* This value indicates the command sequence number. */
4007 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4008 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4013 * This is the host address where the response will be written when the
4014 * request is complete. This area must be 16B aligned and must be
4015 * cleared to zero before the request is made.
4019 /* This bit must be '1' for the Reserved1 field to be configured. */
4020 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)
4021 /* This bit must be '1' for the Reserved2 field to be configured. */
4022 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2 UINT32_C(0x2)
4023 /* This bit must be '1' for the Reserved3 field to be configured. */
4024 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)
4026 * This bit must be '1' for the stat_ctx_id_valid field to be
4029 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
4030 /* This bit must be '1' for the Reserved4 field to be configured. */
4031 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4 UINT32_C(0x10)
4032 /* This bit must be '1' for the max_bw_valid field to be configured. */
4033 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
4037 /* Completion Ring (CR) */
4038 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
4040 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
4042 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
4048 /* This value is a pointer to the page table for the Ring. */
4049 uint64_t page_tbl_addr;
4051 /* First Byte Offset of the first entry in the first page. */
4055 * Actual page size in 2^page_size. The supported range is increments in
4056 * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12
4057 * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB
4058 * Page size is 64 KB. - 22 = 2 MB Page size is 2 MB. - 23 = 4 MB Page
4059 * size is 4 MB. - 31 = 1 GB Page size is 1 GB.
4064 * This value indicates the depth of page table. For this version of the
4065 * specification, value other than 0 or 1 shall be considered as an
4066 * invalid value. When the page_tbl_depth = 0, then it is treated as a
4067 * special case with the following. 1. FBO and page size fields are not
4068 * valid. 2. page_tbl_addr is the physical address of the first element
4071 uint8_t page_tbl_depth;
4077 * Number of 16B units in the ring. Minimum size for a ring is 16 16B
4083 * Logical ring number for the ring to be allocated. This value
4084 * determines the position in the doorbell area where the update to the
4085 * ring will be made. For completion rings, this value is also the MSI-X
4086 * vector number for the function the completion ring is associated
4089 uint16_t logical_id;
4092 * This field is used only when ring_type is a TX ring. This value
4093 * indicates what completion ring the TX ring is associated with.
4095 uint16_t cmpl_ring_id;
4098 * This field is used only when ring_type is a TX ring. This value
4099 * indicates what CoS queue the TX ring is associated with.
4106 /* This field is reserved for the future use. It shall be set to 0. */
4108 /* This field is reserved for the future use. It shall be set to 0. */
4113 /* This field is reserved for the future use. It shall be set to 0. */
4117 * This field is used only when ring_type is a TX ring. This input
4118 * indicates what statistics context this ring should be associated
4121 uint32_t stat_ctx_id;
4123 /* This field is reserved for the future use. It shall be set to 0. */
4127 * This field is used only when ring_type is a TX ring. Maximum BW
4128 * allocated to this TX ring in Mbps. The HWRM will translate this value
4129 * into byte counter and time interval used for this ring inside the
4135 * This field is used only when ring_type is a Completion ring. This
4136 * value indicates what interrupt mode should be used on this completion
4137 * ring. Note: In the legacy interrupt mode, no more than 16 completion
4138 * rings are allowed.
4141 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY (UINT32_C(0x0) << 0)
4143 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD (UINT32_C(0x1) << 0)
4145 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX (UINT32_C(0x2) << 0)
4146 /* No Interrupt - Polled mode */
4147 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL (UINT32_C(0x3) << 0)
4150 uint8_t unused_8[3];
4151 } __attribute__((packed));
4153 /* Output (16 bytes) */
4155 struct hwrm_ring_alloc_output {
4157 * Pass/Fail or error type Note: receiver to verify the in parameters,
4158 * and fail the call with an error when appropriate
4160 uint16_t error_code;
4162 /* This field returns the type of original request. */
4165 /* This field provides original sequence number of the command. */
4169 * This field is the length of the response in bytes. The last byte of
4170 * the response is a valid flag that will read as '1' when the command
4171 * has been completely written to memory.
4175 /* Physical number of ring allocated. */
4178 /* Logical number of ring allocated. */
4179 uint16_t logical_ring_id;
4186 * This field is used in Output records to indicate that the output is
4187 * completely written to RAM. This field should be read as '1' to
4188 * indicate that the output has been completely written. When writing a
4189 * command completion or response to an internal processor, the order of
4190 * writes has to be such that this field is written last.
4193 } __attribute__((packed));
4195 /* hwrm_ring_free */
4197 * Description: This command is used to free a ring and associated resources.
4199 /* Input (24 bytes) */
4201 struct hwrm_ring_free_input {
4203 * This value indicates what type of request this is. The format for the
4204 * rest of the command is determined by this field.
4209 * This value indicates the what completion ring the request will be
4210 * optionally completed on. If the value is -1, then no CR completion
4211 * will be generated. Any other value must be a valid CR ring_id value
4212 * for this function.
4216 /* This value indicates the command sequence number. */
4220 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4221 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4226 * This is the host address where the response will be written when the
4227 * request is complete. This area must be 16B aligned and must be
4228 * cleared to zero before the request is made.
4233 /* Completion Ring (CR) */
4234 #define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL (UINT32_C(0x0) << 0)
4236 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX (UINT32_C(0x1) << 0)
4238 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX (UINT32_C(0x2) << 0)
4243 /* Physical number of ring allocated. */
4247 } __attribute__((packed));
4249 /* Output (16 bytes) */
4250 struct hwrm_ring_free_output {
4252 * Pass/Fail or error type Note: receiver to verify the in parameters,
4253 * and fail the call with an error when appropriate
4255 uint16_t error_code;
4257 /* This field returns the type of original request. */
4260 /* This field provides original sequence number of the command. */
4264 * This field is the length of the response in bytes. The last byte of
4265 * the response is a valid flag that will read as '1' when the command
4266 * has been completely written to memory.
4276 * This field is used in Output records to indicate that the output is
4277 * completely written to RAM. This field should be read as '1' to
4278 * indicate that the output has been completely written. When writing a
4279 * command completion or response to an internal processor, the order of
4280 * writes has to be such that this field is written last.
4283 } __attribute__((packed));
4285 /* hwrm_ring_grp_alloc */
4287 * Description: This API allocates and does basic preparation for a ring group.
4290 /* Input (24 bytes) */
4291 struct hwrm_ring_grp_alloc_input {
4293 * This value indicates what type of request this is. The format for the
4294 * rest of the command is determined by this field.
4299 * This value indicates the what completion ring the request will be
4300 * optionally completed on. If the value is -1, then no CR completion
4301 * will be generated. Any other value must be a valid CR ring_id value
4302 * for this function.
4306 /* This value indicates the command sequence number. */
4310 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4311 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4316 * This is the host address where the response will be written when the
4317 * request is complete. This area must be 16B aligned and must be
4318 * cleared to zero before the request is made.
4322 /* This value identifies the CR associated with the ring group. */
4325 /* This value identifies the main RR associated with the ring group. */
4329 * This value identifies the aggregation RR associated with the ring
4330 * group. If this value is 0xFF... (All Fs), then no Aggregation ring
4336 * This value identifies the statistics context associated with the ring
4340 } __attribute__((packed));
4342 /* Output (16 bytes) */
4343 struct hwrm_ring_grp_alloc_output {
4345 * Pass/Fail or error type Note: receiver to verify the in parameters,
4346 * and fail the call with an error when appropriate
4348 uint16_t error_code;
4350 /* This field returns the type of original request. */
4353 /* This field provides original sequence number of the command. */
4357 * This field is the length of the response in bytes. The last byte of
4358 * the response is a valid flag that will read as '1' when the command
4359 * has been completely written to memory.
4364 * This is the ring group ID value. Use this value to program the
4365 * default ring group for the VNIC or as table entries in an RSS/COS
4368 uint32_t ring_group_id;
4375 * This field is used in Output records to indicate that the output is
4376 * completely written to RAM. This field should be read as '1' to
4377 * indicate that the output has been completely written. When writing a
4378 * command completion or response to an internal processor, the order of
4379 * writes has to be such that this field is written last.
4382 } __attribute__((packed));
4384 /* hwrm_ring_grp_free */
4386 * Description: This API frees a ring group and associated resources. # If a
4387 * ring in the ring group is reset or free, then the associated rings in the
4388 * ring group shall also be reset/free using hwrm_ring_free. # A function driver
4389 * shall always use hwrm_ring_grp_free after freeing all rings in a group. # As
4390 * a part of executing this command, the HWRM shall reset all associated ring
4394 /* Input (24 bytes) */
4395 struct hwrm_ring_grp_free_input {
4397 * This value indicates what type of request this is. The format for the
4398 * rest of the command is determined by this field.
4403 * This value indicates the what completion ring the request will be
4404 * optionally completed on. If the value is -1, then no CR completion
4405 * will be generated. Any other value must be a valid CR ring_id value
4406 * for this function.
4410 /* This value indicates the command sequence number. */
4414 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4415 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4420 * This is the host address where the response will be written when the
4421 * request is complete. This area must be 16B aligned and must be
4422 * cleared to zero before the request is made.
4426 /* This is the ring group ID value. */
4427 uint32_t ring_group_id;
4430 } __attribute__((packed));
4432 /* Output (16 bytes) */
4433 struct hwrm_ring_grp_free_output {
4435 * Pass/Fail or error type Note: receiver to verify the in parameters,
4436 * and fail the call with an error when appropriate
4438 uint16_t error_code;
4440 /* This field returns the type of original request. */
4443 /* This field provides original sequence number of the command. */
4447 * This field is the length of the response in bytes. The last byte of
4448 * the response is a valid flag that will read as '1' when the command
4449 * has been completely written to memory.
4459 * This field is used in Output records to indicate that the output is
4460 * completely written to RAM. This field should be read as '1' to
4461 * indicate that the output has been completely written. When writing a
4462 * command completion or response to an internal processor, the order of
4463 * writes has to be such that this field is written last.
4466 } __attribute__((packed));
4468 /* hwrm_stat_ctx_alloc */
4470 * Description: This command allocates and does basic preparation for a stat
4474 /* Input (32 bytes) */
4475 struct hwrm_stat_ctx_alloc_input {
4477 * This value indicates what type of request this is. The format for the
4478 * rest of the command is determined by this field.
4483 * This value indicates the what completion ring the request will be
4484 * optionally completed on. If the value is -1, then no CR completion
4485 * will be generated. Any other value must be a valid CR ring_id value
4486 * for this function.
4490 /* This value indicates the command sequence number. */
4494 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4495 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4500 * This is the host address where the response will be written when the
4501 * request is complete. This area must be 16B aligned and must be
4502 * cleared to zero before the request is made.
4506 /* This is the address for statistic block. */
4507 uint64_t stats_dma_addr;
4510 * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,
4513 uint32_t update_period_ms;
4516 } __attribute__((packed));
4518 /* Output (16 bytes) */
4519 struct hwrm_stat_ctx_alloc_output {
4521 * Pass/Fail or error type Note: receiver to verify the in parameters,
4522 * and fail the call with an error when appropriate
4524 uint16_t error_code;
4526 /* This field returns the type of original request. */
4529 /* This field provides original sequence number of the command. */
4533 * This field is the length of the response in bytes. The last byte of
4534 * the response is a valid flag that will read as '1' when the command
4535 * has been completely written to memory.
4539 /* This is the statistics context ID value. */
4540 uint32_t stat_ctx_id;
4547 * This field is used in Output records to indicate that the output is
4548 * completely written to RAM. This field should be read as '1' to
4549 * indicate that the output has been completely written. When writing a
4550 * command completion or response to an internal processor, the order of
4551 * writes has to be such that this field is written last.
4554 } __attribute__((packed));
4556 /* hwrm_stat_ctx_clr_stats */
4557 /* Description: This command clears statistics of a context. */
4559 /* Input (24 bytes) */
4560 struct hwrm_stat_ctx_clr_stats_input {
4562 * This value indicates what type of request this is. The format for the
4563 * rest of the command is determined by this field.
4568 * This value indicates the what completion ring the request will be
4569 * optionally completed on. If the value is -1, then no CR completion
4570 * will be generated. Any other value must be a valid CR ring_id value
4571 * for this function.
4575 /* This value indicates the command sequence number. */
4579 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4580 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4585 * This is the host address where the response will be written when the
4586 * request is complete. This area must be 16B aligned and must be
4587 * cleared to zero before the request is made.
4591 /* ID of the statistics context that is being queried. */
4592 uint32_t stat_ctx_id;
4595 } __attribute__((packed));
4597 /* Output (16 bytes) */
4598 struct hwrm_stat_ctx_clr_stats_output {
4600 * Pass/Fail or error type Note: receiver to verify the in parameters,
4601 * and fail the call with an error when appropriate
4603 uint16_t error_code;
4605 /* This field returns the type of original request. */
4608 /* This field provides original sequence number of the command. */
4612 * This field is the length of the response in bytes. The last byte of
4613 * the response is a valid flag that will read as '1' when the command
4614 * has been completely written to memory.
4624 * This field is used in Output records to indicate that the output is
4625 * completely written to RAM. This field should be read as '1' to
4626 * indicate that the output has been completely written. When writing a
4627 * command completion or response to an internal processor, the order of
4628 * writes has to be such that this field is written last.
4631 } __attribute__((packed));
4633 /* hwrm_stat_ctx_free */
4634 /* Description: This command is used to free a stat context. */
4635 /* Input (24 bytes) */
4637 struct hwrm_stat_ctx_free_input {
4639 * This value indicates what type of request this is. The format for the
4640 * rest of the command is determined by this field.
4645 * This value indicates the what completion ring the request will be
4646 * optionally completed on. If the value is -1, then no CR completion
4647 * will be generated. Any other value must be a valid CR ring_id value
4648 * for this function.
4652 /* This value indicates the command sequence number. */
4656 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4657 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4662 * This is the host address where the response will be written when the
4663 * request is complete. This area must be 16B aligned and must be
4664 * cleared to zero before the request is made.
4668 /* ID of the statistics context that is being queried. */
4669 uint32_t stat_ctx_id;
4672 } __attribute__((packed));
4674 /* Output (16 bytes) */
4676 struct hwrm_stat_ctx_free_output {
4678 * Pass/Fail or error type Note: receiver to verify the in parameters,
4679 * and fail the call with an error when appropriate
4681 uint16_t error_code;
4683 /* This field returns the type of original request. */
4686 /* This field provides original sequence number of the command. */
4690 * This field is the length of the response in bytes. The last byte of
4691 * the response is a valid flag that will read as '1' when the command
4692 * has been completely written to memory.
4696 /* This is the statistics context ID value. */
4697 uint32_t stat_ctx_id;
4704 * This field is used in Output records to indicate that the output is
4705 * completely written to RAM. This field should be read as '1' to
4706 * indicate that the output has been completely written. When writing a
4707 * command completion or response to an internal processor, the order of
4708 * writes has to be such that this field is written last.
4711 } __attribute__((packed));
4713 /* hwrm_vnic_alloc */
4715 * Description: This VNIC is a resource in the RX side of the chip that is used
4716 * to represent a virtual host "interface". # At the time of VNIC allocation or
4717 * configuration, the function can specify whether it wants the requested VNIC
4718 * to be the default VNIC for the function or not. # If a function requests
4719 * allocation of a VNIC for the first time and a VNIC is successfully allocated
4720 * by the HWRM, then the HWRM shall make the allocated VNIC as the default VNIC
4721 * for that function. # The default VNIC shall be used for the default action
4722 * for a partition or function. # For each VNIC allocated on a function, a
4723 * mapping on the RX side to map the allocated VNIC to source virtual interface
4724 * shall be performed by the HWRM. This should be hidden to the function driver
4725 * requesting the VNIC allocation. This enables broadcast/multicast replication
4726 * with source knockout. # If multicast replication with source knockout is
4727 * enabled, then the internal VNIC to SVIF mapping data structures shall be
4728 * programmed at the time of VNIC allocation.
4731 /* Input (24 bytes) */
4732 struct hwrm_vnic_alloc_input {
4734 * This value indicates what type of request this is. The format for the
4735 * rest of the command is determined by this field.
4740 * This value indicates the what completion ring the request will be
4741 * optionally completed on. If the value is -1, then no CR completion
4742 * will be generated. Any other value must be a valid CR ring_id value
4743 * for this function.
4747 /* This value indicates the command sequence number. */
4751 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4752 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4757 * This is the host address where the response will be written when the
4758 * request is complete. This area must be 16B aligned and must be
4759 * cleared to zero before the request is made.
4764 * When this bit is '1', this VNIC is requested to be the default VNIC
4765 * for this function.
4767 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
4771 } __attribute__((packed));
4773 /* Output (16 bytes) */
4774 struct hwrm_vnic_alloc_output {
4776 * Pass/Fail or error type Note: receiver to verify the in parameters,
4777 * and fail the call with an error when appropriate
4779 uint16_t error_code;
4781 /* This field returns the type of original request. */
4784 /* This field provides original sequence number of the command. */
4788 * This field is the length of the response in bytes. The last byte of
4789 * the response is a valid flag that will read as '1' when the command
4790 * has been completely written to memory.
4794 /* Logical vnic ID */
4802 * This field is used in Output records to indicate that the output is
4803 * completely written to RAM. This field should be read as '1' to
4804 * indicate that the output has been completely written. When writing a
4805 * command completion or response to an internal processor, the order of
4806 * writes has to be such that this field is written last.
4809 } __attribute__((packed));
4812 /* Description: Configure the RX VNIC structure. */
4814 /* Input (40 bytes) */
4815 struct hwrm_vnic_cfg_input {
4817 * This value indicates what type of request this is. The format for the
4818 * rest of the command is determined by this field.
4823 * This value indicates the what completion ring the request will be
4824 * optionally completed on. If the value is -1, then no CR completion
4825 * will be generated. Any other value must be a valid CR ring_id value
4826 * for this function.
4830 /* This value indicates the command sequence number. */
4834 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4835 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4840 * This is the host address where the response will be written when the
4841 * request is complete. This area must be 16B aligned and must be
4842 * cleared to zero before the request is made.
4847 * When this bit is '1', the VNIC is requested to be the default VNIC
4850 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
4852 * When this bit is '1', the VNIC is being configured to strip VLAN in
4853 * the RX path. If set to '0', then VLAN stripping is disabled on this
4856 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
4858 * When this bit is '1', the VNIC is being configured to buffer receive
4859 * packets in the hardware until the host posts new receive buffers. If
4860 * set to '0', then bd_stall is being configured to be disabled on this
4863 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
4865 * When this bit is '1', the VNIC is being configured to receive both
4866 * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not
4867 * configured to be operating in dual VNIC mode.
4869 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
4871 * When this flag is set to '1', the VNIC is requested to be configured
4872 * to receive only RoCE traffic. If this flag is set to '0', then this
4873 * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set
4874 * to '1', then the HWRM client shall not set this flag to '1'.
4876 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
4879 /* This bit must be '1' for the dflt_ring_grp field to be configured. */
4880 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
4881 /* This bit must be '1' for the rss_rule field to be configured. */
4882 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
4883 /* This bit must be '1' for the cos_rule field to be configured. */
4884 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
4885 /* This bit must be '1' for the lb_rule field to be configured. */
4886 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
4887 /* This bit must be '1' for the mru field to be configured. */
4888 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
4891 /* Logical vnic ID */
4895 * Default Completion ring for the VNIC. This ring will be chosen if
4896 * packet does not match any RSS rules and if there is no COS rule.
4898 uint16_t dflt_ring_grp;
4901 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
4907 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
4913 * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
4914 * there is no LB rule.
4919 * The maximum receive unit of the vnic. Each vnic is associated with a
4920 * function. The vnic mru value overwrites the mru setting of the
4921 * associated function. The HWRM shall make sure that vnic mru does not
4922 * exceed the mru of the port the function is associated with.
4927 } __attribute__((packed));
4929 /* Output (16 bytes) */
4930 struct hwrm_vnic_cfg_output {
4932 * Pass/Fail or error type Note: receiver to verify the in parameters,
4933 * and fail the call with an error when appropriate
4935 uint16_t error_code;
4937 /* This field returns the type of original request. */
4940 /* This field provides original sequence number of the command. */
4944 * This field is the length of the response in bytes. The last byte of
4945 * the response is a valid flag that will read as '1' when the command
4946 * has been completely written to memory.
4956 * This field is used in Output records to indicate that the output is
4957 * completely written to RAM. This field should be read as '1' to
4958 * indicate that the output has been completely written. When writing a
4959 * command completion or response to an internal processor, the order of
4960 * writes has to be such that this field is written last.
4963 } __attribute__((packed));
4965 /* hwrm_vnic_free */
4967 * Description: Free a VNIC resource. Idle any resources associated with the
4968 * VNIC as well as the VNIC. Reset and release all resources associated with the
4972 /* Input (24 bytes) */
4973 struct hwrm_vnic_free_input {
4975 * This value indicates what type of request this is. The format for the
4976 * rest of the command is determined by this field.
4981 * This value indicates the what completion ring the request will be
4982 * optionally completed on. If the value is -1, then no CR completion
4983 * will be generated. Any other value must be a valid CR ring_id value
4984 * for this function.
4988 /* This value indicates the command sequence number. */
4992 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
4993 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
4998 * This is the host address where the response will be written when the
4999 * request is complete. This area must be 16B aligned and must be
5000 * cleared to zero before the request is made.
5004 /* Logical vnic ID */
5008 } __attribute__((packed));
5010 /* Output (16 bytes) */
5011 struct hwrm_vnic_free_output {
5013 * Pass/Fail or error type Note: receiver to verify the in parameters,
5014 * and fail the call with an error when appropriate
5016 uint16_t error_code;
5018 /* This field returns the type of original request. */
5021 /* This field provides original sequence number of the command. */
5025 * This field is the length of the response in bytes. The last byte of
5026 * the response is a valid flag that will read as '1' when the command
5027 * has been completely written to memory.
5037 * This field is used in Output records to indicate that the output is
5038 * completely written to RAM. This field should be read as '1' to
5039 * indicate that the output has been completely written. When writing a
5040 * command completion or response to an internal processor, the order of
5041 * writes has to be such that this field is written last.
5044 } __attribute__((packed));
5046 /* hwrm_vnic_rss_cfg */
5047 /* Description: This function is used to enable RSS configuration. */
5049 /* Input (48 bytes) */
5050 struct hwrm_vnic_rss_cfg_input {
5052 * This value indicates what type of request this is. The format for the
5053 * rest of the command is determined by this field.
5058 * This value indicates the what completion ring the request will be
5059 * optionally completed on. If the value is -1, then no CR completion
5060 * will be generated. Any other value must be a valid CR ring_id value
5061 * for this function.
5065 /* This value indicates the command sequence number. */
5069 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5070 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5075 * This is the host address where the response will be written when the
5076 * request is complete. This area must be 16B aligned and must be
5077 * cleared to zero before the request is made.
5082 * When this bit is '1', the RSS hash shall be computed over source and
5083 * destination IPv4 addresses of IPv4 packets.
5085 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
5087 * When this bit is '1', the RSS hash shall be computed over
5088 * source/destination IPv4 addresses and source/destination ports of
5091 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
5093 * When this bit is '1', the RSS hash shall be computed over
5094 * source/destination IPv4 addresses and source/destination ports of
5097 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
5099 * When this bit is '1', the RSS hash shall be computed over source and
5100 * destination IPv4 addresses of IPv6 packets.
5102 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
5104 * When this bit is '1', the RSS hash shall be computed over
5105 * source/destination IPv6 addresses and source/destination ports of
5108 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
5110 * When this bit is '1', the RSS hash shall be computed over
5111 * source/destination IPv6 addresses and source/destination ports of
5114 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
5119 /* This is the address for rss ring group table */
5120 uint64_t ring_grp_tbl_addr;
5122 /* This is the address for rss hash key table */
5123 uint64_t hash_key_tbl_addr;
5125 /* Index to the rss indirection table. */
5126 uint16_t rss_ctx_idx;
5128 uint16_t unused_1[3];
5129 } __attribute__((packed));
5131 /* Output (16 bytes) */
5132 struct hwrm_vnic_rss_cfg_output {
5134 * Pass/Fail or error type Note: receiver to verify the in parameters,
5135 * and fail the call with an error when appropriate
5137 uint16_t error_code;
5139 /* This field returns the type of original request. */
5142 /* This field provides original sequence number of the command. */
5146 * This field is the length of the response in bytes. The last byte of
5147 * the response is a valid flag that will read as '1' when the command
5148 * has been completely written to memory.
5158 * This field is used in Output records to indicate that the output is
5159 * completely written to RAM. This field should be read as '1' to
5160 * indicate that the output has been completely written. When writing a
5161 * command completion or response to an internal processor, the order of
5162 * writes has to be such that this field is written last.
5165 } __attribute__((packed));
5167 /* Input (16 bytes) */
5168 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
5170 * This value indicates what type of request this is. The format for the
5171 * rest of the command is determined by this field.
5176 * This value indicates the what completion ring the request will be
5177 * optionally completed on. If the value is -1, then no CR completion
5178 * will be generated. Any other value must be a valid CR ring_id value
5179 * for this function.
5183 /* This value indicates the command sequence number. */
5187 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5188 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5193 * This is the host address where the response will be written when the
5194 * request is complete. This area must be 16B aligned and must be
5195 * cleared to zero before the request is made.
5198 } __attribute__((packed));
5200 /* Output (16 bytes) */
5202 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
5204 * Pass/Fail or error type Note: receiver to verify the in parameters,
5205 * and fail the call with an error when appropriate
5207 uint16_t error_code;
5209 /* This field returns the type of original request. */
5212 /* This field provides original sequence number of the command. */
5216 * This field is the length of the response in bytes. The last byte of
5217 * the response is a valid flag that will read as '1' when the command
5218 * has been completely written to memory.
5222 /* rss_cos_lb_ctx_id is 16 b */
5223 uint16_t rss_cos_lb_ctx_id;
5232 * This field is used in Output records to indicate that the output is
5233 * completely written to RAM. This field should be read as '1' to
5234 * indicate that the output has been completely written. When writing a
5235 * command completion or response to an internal processor, the order of
5236 * writes has to be such that this field is written last.
5239 } __attribute__((packed));
5241 /* hwrm_vnic_rss_cos_lb_ctx_free */
5242 /* Description: This function can be used to free COS/Load Balance context. */
5243 /* Input (24 bytes) */
5245 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
5247 * This value indicates what type of request this is. The format for the
5248 * rest of the command is determined by this field.
5253 * This value indicates the what completion ring the request will be
5254 * optionally completed on. If the value is -1, then no CR completion
5255 * will be generated. Any other value must be a valid CR ring_id value
5256 * for this function.
5260 /* This value indicates the command sequence number. */
5264 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5265 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5270 * This is the host address where the response will be written when the
5271 * request is complete. This area must be 16B aligned and must be
5272 * cleared to zero before the request is made.
5276 /* rss_cos_lb_ctx_id is 16 b */
5277 uint16_t rss_cos_lb_ctx_id;
5279 uint16_t unused_0[3];
5280 } __attribute__((packed));
5282 /* Output (16 bytes) */
5283 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
5285 * Pass/Fail or error type Note: receiver to verify the in parameters,
5286 * and fail the call with an error when appropriate
5288 uint16_t error_code;
5290 /* This field returns the type of original request. */
5293 /* This field provides original sequence number of the command. */
5297 * This field is the length of the response in bytes. The last byte of
5298 * the response is a valid flag that will read as '1' when the command
5299 * has been completely written to memory.
5309 * This field is used in Output records to indicate that the output is
5310 * completely written to RAM. This field should be read as '1' to
5311 * indicate that the output has been completely written. When writing a
5312 * command completion or response to an internal processor, the order of
5313 * writes has to be such that this field is written last.
5316 } __attribute__((packed));
5318 /* Output (32 bytes) */
5319 struct hwrm_queue_qportcfg_output {
5321 * Pass/Fail or error type Note: receiver to verify the in parameters,
5322 * and fail the call with an error when appropriate
5324 uint16_t error_code;
5326 /* This field returns the type of original request. */
5329 /* This field provides original sequence number of the command. */
5333 * This field is the length of the response in bytes. The last byte of
5334 * the response is a valid flag that will read as '1' when the command
5335 * has been completely written to memory.
5339 /* The maximum number of queues that can be configured. */
5340 uint8_t max_configurable_queues;
5342 /* The maximum number of lossless queues that can be configured. */
5343 uint8_t max_configurable_lossless_queues;
5346 * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then
5347 * the HWRM shall allow the host SW driver to configure queues using
5350 uint8_t queue_cfg_allowed;
5353 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5354 * the HWRM shall allow the host SW driver to configure queue buffers
5355 * using hwrm_queue_buffers_cfg.
5357 uint8_t queue_buffers_cfg_allowed;
5360 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5361 * the HWRM shall allow the host SW driver to configure PFC using
5362 * hwrm_queue_pfcenable_cfg.
5364 uint8_t queue_pfcenable_cfg_allowed;
5367 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5368 * the HWRM shall allow the host SW driver to configure Priority to CoS
5369 * mapping using hwrm_queue_pri2cos_cfg.
5371 uint8_t queue_pri2cos_cfg_allowed;
5374 * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then
5375 * the HWRM shall allow the host SW driver to configure CoS Bandwidth
5376 * configuration using hwrm_queue_cos2bw_cfg.
5378 uint8_t queue_cos2bw_cfg_allowed;
5380 /* ID of CoS Queue 0. FF - Invalid id */
5383 /* This value is applicable to CoS queues only. */
5384 /* Lossy (best-effort) */
5385 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
5386 (UINT32_C(0x0) << 0)
5388 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
5389 (UINT32_C(0x1) << 0)
5391 * Set to 0xFF... (All Fs) if there is no service profile
5394 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
5395 (UINT32_C(0xff) << 0)
5396 uint8_t queue_id0_service_profile;
5398 /* ID of CoS Queue 1. FF - Invalid id */
5400 /* This value is applicable to CoS queues only. */
5401 /* Lossy (best-effort) */
5402 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
5403 (UINT32_C(0x0) << 0)
5405 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
5406 (UINT32_C(0x1) << 0)
5408 * Set to 0xFF... (All Fs) if there is no service profile
5411 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
5412 (UINT32_C(0xff) << 0)
5413 uint8_t queue_id1_service_profile;
5415 /* ID of CoS Queue 2. FF - Invalid id */
5417 /* This value is applicable to CoS queues only. */
5418 /* Lossy (best-effort) */
5419 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
5420 (UINT32_C(0x0) << 0)
5422 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
5423 (UINT32_C(0x1) << 0)
5425 * Set to 0xFF... (All Fs) if there is no service profile
5428 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
5429 (UINT32_C(0xff) << 0)
5430 uint8_t queue_id2_service_profile;
5432 /* ID of CoS Queue 3. FF - Invalid id */
5435 /* This value is applicable to CoS queues only. */
5436 /* Lossy (best-effort) */
5437 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
5438 (UINT32_C(0x0) << 0)
5440 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
5441 (UINT32_C(0x1) << 0)
5443 * Set to 0xFF... (All Fs) if there is no service profile
5446 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
5447 (UINT32_C(0xff) << 0)
5448 uint8_t queue_id3_service_profile;
5450 /* ID of CoS Queue 4. FF - Invalid id */
5452 /* This value is applicable to CoS queues only. */
5453 /* Lossy (best-effort) */
5454 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
5455 (UINT32_C(0x0) << 0)
5457 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
5458 (UINT32_C(0x1) << 0)
5460 * Set to 0xFF... (All Fs) if there is no service profile
5463 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
5464 (UINT32_C(0xff) << 0)
5465 uint8_t queue_id4_service_profile;
5467 /* ID of CoS Queue 5. FF - Invalid id */
5470 /* This value is applicable to CoS queues only. */
5471 /* Lossy (best-effort) */
5472 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
5473 (UINT32_C(0x0) << 0)
5475 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
5476 (UINT32_C(0x1) << 0)
5478 * Set to 0xFF... (All Fs) if there is no service profile
5481 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
5482 (UINT32_C(0xff) << 0)
5483 uint8_t queue_id5_service_profile;
5485 /* ID of CoS Queue 6. FF - Invalid id */
5486 uint8_t queue_id6_service_profile;
5487 /* This value is applicable to CoS queues only. */
5488 /* Lossy (best-effort) */
5489 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
5490 (UINT32_C(0x0) << 0)
5492 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
5493 (UINT32_C(0x1) << 0)
5495 * Set to 0xFF... (All Fs) if there is no service profile
5498 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
5499 (UINT32_C(0xff) << 0)
5502 /* ID of CoS Queue 7. FF - Invalid id */
5505 /* This value is applicable to CoS queues only. */
5506 /* Lossy (best-effort) */
5507 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
5508 (UINT32_C(0x0) << 0)
5510 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
5511 (UINT32_C(0x1) << 0)
5513 * Set to 0xFF... (All Fs) if there is no service profile
5516 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
5517 (UINT32_C(0xff) << 0)
5518 uint8_t queue_id7_service_profile;
5521 * This field is used in Output records to indicate that the output is
5522 * completely written to RAM. This field should be read as '1' to
5523 * indicate that the output has been completely written. When writing a
5524 * command completion or response to an internal processor, the order of
5525 * writes has to be such that this field is written last.
5528 } __attribute__((packed));
5530 /* hwrm_func_drv_rgtr */
5532 * Description: This command is used by the function driver to register its
5533 * information with the HWRM. A function driver shall implement this command. A
5534 * function driver shall use this command during the driver initialization right
5535 * after the HWRM version discovery and default ring resources allocation.
5538 /* Input (80 bytes) */
5539 struct hwrm_func_drv_rgtr_input {
5541 * This value indicates what type of request this is. The format for the
5542 * rest of the command is determined by this field.
5547 * This value indicates the what completion ring the request will be
5548 * optionally completed on. If the value is -1, then no CR completion
5549 * will be generated. Any other value must be a valid CR ring_id value
5550 * for this function.
5554 /* This value indicates the command sequence number. */
5558 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5559 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5564 * This is the host address where the response will be written when the
5565 * request is complete. This area must be 16B aligned and must be
5566 * cleared to zero before the request is made.
5571 * When this bit is '1', the function driver is requesting all requests
5572 * from its children VF drivers to be forwarded to itself. This flag can
5573 * only be set by the PF driver. If a VF driver sets this flag, it
5574 * should be ignored by the HWRM.
5576 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
5578 * When this bit is '1', the function is requesting none of the requests
5579 * from its children VF drivers to be forwarded to itself. This flag can
5580 * only be set by the PF driver. If a VF driver sets this flag, it
5581 * should be ignored by the HWRM.
5583 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
5586 /* This bit must be '1' for the os_type field to be configured. */
5587 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
5588 /* This bit must be '1' for the ver field to be configured. */
5589 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
5590 /* This bit must be '1' for the timestamp field to be configured. */
5591 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
5592 /* This bit must be '1' for the vf_req_fwd field to be configured. */
5593 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
5595 * This bit must be '1' for the async_event_fwd field to be configured.
5597 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
5601 /* This value indicates the type of OS. */
5603 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN \
5604 (UINT32_C(0x0) << 0)
5605 /* Other OS not listed below. */
5606 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER \
5607 (UINT32_C(0x1) << 0)
5609 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS \
5610 (UINT32_C(0xe) << 0)
5612 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS \
5613 (UINT32_C(0x12) << 0)
5615 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS \
5616 (UINT32_C(0x1d) << 0)
5618 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX \
5619 (UINT32_C(0x24) << 0)
5621 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD \
5622 (UINT32_C(0x2a) << 0)
5623 /* VMware ESXi OS. */
5624 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI \
5625 (UINT32_C(0x68) << 0)
5626 /* Microsoft Windows 8 64-bit OS. */
5627 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 \
5628 (UINT32_C(0x73) << 0)
5629 /* Microsoft Windows Server 2012 R2 OS. */
5630 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 \
5631 (UINT32_C(0x74) << 0)
5634 /* This is the major version of the driver. */
5637 /* This is the minor version of the driver. */
5640 /* This is the update version of the driver. */
5647 * This is a 32-bit timestamp provided by the driver for keep alive. The
5648 * timestamp is in multiples of 1ms.
5655 * This is a 256-bit bit mask provided by the PF driver for letting the
5656 * HWRM know what commands issued by the VF driver to the HWRM should be
5657 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
5658 * Setting Nth bit to 1 indicates that requests from the VF driver with
5659 * req_type equal to N shall be forwarded to the parent PF driver. This
5660 * field is not valid for the VF driver.
5662 uint32_t vf_req_fwd[8];
5665 * This is a 256-bit bit mask provided by the function driver (PF or VF
5666 * driver) to indicate the list of asynchronous event completions to be
5667 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
5668 * by the function driver shall result in the HWRM forwarding
5669 * asynchronous event completion with event_id equal to N. If all bits
5670 * are set to 0 (value of 0), then the HWRM shall not forward any
5671 * asynchronous event completion to this function driver.
5673 uint32_t async_event_fwd[8];
5674 } __attribute__((packed));
5676 /* Output (16 bytes) */
5678 struct hwrm_func_drv_rgtr_output {
5680 * Pass/Fail or error type Note: receiver to verify the in parameters,
5681 * and fail the call with an error when appropriate
5683 uint16_t error_code;
5685 /* This field returns the type of original request. */
5688 /* This field provides original sequence number of the command. */
5692 * This field is the length of the response in bytes. The last byte of
5693 * the response is a valid flag that will read as '1' when the command
5694 * has been completely written to memory.
5704 * This field is used in Output records to indicate that the output is
5705 * completely written to RAM. This field should be read as '1' to
5706 * indicate that the output has been completely written. When writing a
5707 * command completion or response to an internal processor, the order of
5708 * writes has to be such that this field is written last.
5711 } __attribute__((packed));
5713 /* hwrm_func_drv_unrgtr */
5715 * Description: This command is used by the function driver to un register with
5716 * the HWRM. A function driver shall implement this command. A function driver
5717 * shall use this command during the driver unloading.
5719 /* Input (24 bytes) */
5721 struct hwrm_func_drv_unrgtr_input {
5723 * This value indicates what type of request this is. The format for the
5724 * rest of the command is determined by this field.
5729 * This value indicates the what completion ring the request will be
5730 * optionally completed on. If the value is -1, then no CR completion
5731 * will be generated. Any other value must be a valid CR ring_id value
5732 * for this function.
5736 /* This value indicates the command sequence number. */
5740 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5741 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5746 * This is the host address where the response will be written when the
5747 * request is complete. This area must be 16B aligned and must be
5748 * cleared to zero before the request is made.
5753 * When this bit is '1', the function driver is notifying the HWRM to
5754 * prepare for the shutdown.
5756 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
5761 } __attribute__((packed));
5763 /* Output (16 bytes) */
5764 struct hwrm_func_drv_unrgtr_output {
5766 * Pass/Fail or error type Note: receiver to verify the in parameters,
5767 * and fail the call with an error when appropriate
5769 uint16_t error_code;
5771 /* This field returns the type of original request. */
5774 /* This field provides original sequence number of the command. */
5778 * This field is the length of the response in bytes. The last byte of
5779 * the response is a valid flag that will read as '1' when the command
5780 * has been completely written to memory.
5790 * This field is used in Output records to indicate that the output is
5791 * completely written to RAM. This field should be read as '1' to
5792 * indicate that the output has been completely written. When writing a
5793 * command completion or response to an internal processor, the order of
5794 * writes has to be such that this field is written last.
5797 } __attribute__((packed));