1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* Engine CKV - The device's serial number. */
71 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
72 /* Engine CKV - Per-function random nonce data. */
73 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
74 /* Engine CKV - Initialization vector. */
75 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
76 /* Engine CKV - Authentication tag. */
77 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
78 /* Engine CKV - The encrypted data. */
79 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
80 /* Engine CKV - Supported algorithms. */
81 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
82 /* Engine CKV - The EC curve name and ECC public key information. */
83 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
84 /* Engine CKV - The ECDSA signature. */
85 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
86 #define TLV_TYPE_LAST \
87 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
90 /* tlv (size:64b/8B) */
93 * The command discriminator is used to differentiate between various
94 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
95 * command messages as well as newer TLV encapsulated HWRM commands.
97 * For TLV encapsulated messages this field must be 0x8000.
103 * Indicates the presence of additional TLV encapsulated data
106 #define TLV_FLAGS_MORE UINT32_C(0x1)
107 /* Last TLV in a sequence of TLVs. */
108 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
109 /* More TLVs follow this TLV. */
110 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
112 * When an HWRM receiver detects a TLV type that it does not
113 * support with the TLV required flag set, the receiver must
114 * reject the HWRM message with an error code indicating an
115 * unsupported TLV type.
117 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
119 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
121 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
122 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
124 * This field defines the TLV type value which is divided into
125 * two ranges to differentiate between global and local TLV types.
126 * Global TLV types must be unique across all defined TLV types.
127 * Local TLV types are valid only for extensions to a given
128 * HWRM message and may be repeated across different HWRM message
129 * types. There is a direct correlation of each HWRM message type
130 * to a single global TLV type value.
132 * Global TLV range: `0 - (63k-1)`
134 * Local TLV range: `63k - (64k-1)`
138 * Length of the message data encapsulated by this TLV in bytes.
139 * This length does not include the size of the TLV header itself
140 * and it must be an integer multiple of 8B.
143 } __attribute__((packed));
146 /* input (size:128b/16B) */
149 * This value indicates what type of request this is. The format
150 * for the rest of the command is determined by this field.
154 * This value indicates the what completion ring the request will
155 * be optionally completed on. If the value is -1, then no
156 * CR completion will be generated. Any other value must be a
157 * valid CR ring_id value for this function.
160 /* This value indicates the command sequence number. */
163 * Target ID of this command.
165 * 0x0 - 0xFFF8 - Used for function ids
166 * 0xFFF8 - 0xFFFE - Reserved for internal processors
171 * This is the host address where the response will be written
172 * when the request is complete. This area must be 16B aligned
173 * and must be cleared to zero before the request is made.
176 } __attribute__((packed));
179 /* output (size:64b/8B) */
182 * Pass/Fail or error type
184 * Note: receiver to verify the in parameters, and fail the call
185 * with an error when appropriate
188 /* This field returns the type of original request. */
190 /* This field provides original sequence number of the command. */
193 * This field is the length of the response in bytes. The
194 * last byte of the response is a valid flag that will read
195 * as '1' when the command has been completely written to
199 } __attribute__((packed));
201 /* Short Command Structure */
202 /* hwrm_short_input (size:128b/16B) */
203 struct hwrm_short_input {
205 * This field indicates the type of request in the request buffer.
206 * The format for the rest of the command (request) is determined
211 * This field indicates a signature that is used to identify short
212 * form of the command listed here. This field shall be set to
216 /* Signature indicating this is a short form of HWRM command */
217 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
218 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
219 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
220 /* Reserved for future use. */
222 /* This value indicates the length of the request. */
225 * This is the host address where the request was written.
226 * This area must be 16B aligned.
229 } __attribute__((packed));
233 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
234 * # So only structure definition is provided here.
236 /* cmd_nums (size:64b/8B) */
239 * This version of the specification defines the commands listed in
240 * the table below. The following are general implementation
241 * requirements for these commands:
243 * # All commands listed below that are marked neither
244 * reserved nor experimental shall be implemented by the HWRM.
245 * # A HWRM client compliant to this specification should not use
246 * commands outside of the list below.
247 * # A HWRM client compliant to this specification should not use
248 * command numbers marked reserved below.
249 * # A command marked experimental below may not be implemented
251 * # A command marked experimental may change in the
252 * future version of the HWRM specification.
253 * # A command not listed below may be implemented by the HWRM.
254 * The behavior of commands that are not listed below is outside
255 * the scope of this specification.
258 #define HWRM_VER_GET UINT32_C(0x0)
259 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
260 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
261 /* Reserved for future use. */
262 #define HWRM_RESERVED1 UINT32_C(0x10)
263 #define HWRM_FUNC_RESET UINT32_C(0x11)
264 #define HWRM_FUNC_GETFID UINT32_C(0x12)
265 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
266 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
267 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
268 #define HWRM_FUNC_QCFG UINT32_C(0x16)
269 #define HWRM_FUNC_CFG UINT32_C(0x17)
270 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
271 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
272 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
273 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
274 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
275 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
276 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
277 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
278 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
279 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
281 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
282 #define HWRM_PORT_QSTATS UINT32_C(0x23)
283 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
285 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
287 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
288 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
289 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
291 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
292 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
293 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
294 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
295 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
296 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
297 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
298 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
299 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
300 #define HWRM_QUEUE_CFG UINT32_C(0x32)
301 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
302 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
303 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
304 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
305 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
306 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
307 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
308 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
310 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
312 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
314 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
315 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
316 #define HWRM_VNIC_FREE UINT32_C(0x41)
317 #define HWRM_VNIC_CFG UINT32_C(0x42)
318 #define HWRM_VNIC_QCFG UINT32_C(0x43)
319 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
321 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
322 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
323 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
324 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
325 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
326 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
327 #define HWRM_RING_ALLOC UINT32_C(0x50)
328 #define HWRM_RING_FREE UINT32_C(0x51)
329 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
330 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
331 #define HWRM_RING_RESET UINT32_C(0x5e)
332 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
333 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
334 /* Reserved for future use. */
335 #define HWRM_RESERVED5 UINT32_C(0x64)
336 /* Reserved for future use. */
337 #define HWRM_RESERVED6 UINT32_C(0x65)
338 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
339 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
340 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
341 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
342 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
343 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
344 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
345 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
346 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
348 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
350 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
351 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
352 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
353 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
355 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
357 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
359 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
360 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
361 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
362 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
363 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
364 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
365 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
366 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
367 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
368 #define HWRM_FW_RESET UINT32_C(0xc0)
369 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
371 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
373 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
375 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
377 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
379 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
380 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
381 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
382 #define HWRM_FWD_RESP UINT32_C(0xd2)
383 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
384 #define HWRM_OEM_CMD UINT32_C(0xd4)
385 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
386 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
387 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
388 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
389 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
391 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
393 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
395 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
397 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
399 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
401 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
403 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
405 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
407 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
409 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
411 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
413 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
415 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
417 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
419 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
421 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
423 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
424 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
425 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
426 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
428 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
430 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
432 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
434 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
435 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
436 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
437 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
438 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
439 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
440 /* Engine CKV - Add a new CKEK used to encrypt keys. */
441 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
442 /* Engine CKV - Delete a previously added CKEK. */
443 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
444 /* Engine CKV - Add a new key to the key vault. */
445 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
446 /* Engine CKV - Delete a key from the key vault. */
447 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
448 /* Engine CKV - Delete all keys from the key vault. */
449 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
450 /* Engine CKV - Get random data. */
451 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
452 /* Engine CKV - Generate and encrypt a new AES key. */
453 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
454 /* Engine - Query the available queue groups configuration. */
455 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
456 /* Engine - Query the queue groups assigned to a function. */
457 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
458 /* Engine - Query the available queue group meter profile configuration. */
459 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
460 /* Engine - Query the configuration of a queue group meter profile. */
461 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
462 /* Engine - Allocate a queue group meter profile. */
463 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
464 /* Engine - Free a queue group meter profile. */
465 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
466 /* Engine - Query the meters assigned to a queue group. */
467 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
468 /* Engine - Bind a queue group meter profile to a queue group. */
469 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
470 /* Engine - Unbind a queue group meter profile from a queue group. */
471 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
472 /* Engine - Bind a queue group to a function. */
473 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
474 /* Engine - Query the scheduling group configuration. */
475 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
476 /* Engine - Query the queue groups assigned to a scheduling group. */
477 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
478 /* Engine - Query the configuration of a scheduling group's meter profiles. */
479 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
480 /* Engine - Configure a scheduling group's meter profiles. */
481 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
482 /* Engine - Bind a queue group to a scheduling group. */
483 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
484 /* Engine - Unbind a queue group from its scheduling group. */
485 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
486 /* Engine - Query the Engine configuration. */
487 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
488 /* Engine - Configure the statistics accumulator for an Engine. */
489 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
490 /* Engine - Clear the statistics accumulator for an Engine. */
491 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
492 /* Engine - Query the statistics accumulator for an Engine. */
493 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
494 /* Engine - Allocate an Engine RQ. */
495 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
496 /* Engine - Free an Engine RQ. */
497 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
498 /* Engine - Allocate an Engine CQ. */
499 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
500 /* Engine - Free an Engine CQ. */
501 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
502 /* Engine - Allocate an NQ. */
503 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
504 /* Engine - Free an NQ. */
505 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
506 /* Engine - Set the on-die RQE credit update location. */
507 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
509 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
511 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
513 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
515 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
517 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
519 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
521 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
523 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
525 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
527 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
529 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
531 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
533 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
535 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
536 #define HWRM_DBG_DUMP UINT32_C(0xff14)
538 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
540 #define HWRM_DBG_CFG UINT32_C(0xff16)
542 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
544 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
546 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
548 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
550 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
551 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
552 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
553 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
554 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
555 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
556 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
557 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
558 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
559 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
560 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
561 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
562 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
563 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
564 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
565 #define HWRM_NVM_READ UINT32_C(0xfffd)
566 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
567 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
568 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
569 uint16_t unused_0[3];
570 } __attribute__((packed));
573 /* ret_codes (size:64b/8B) */
576 /* Request was successfully executed by the HWRM. */
577 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
578 /* The HWRM failed to execute the request. */
579 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
581 * The request contains invalid argument(s) or input
584 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
586 * The requester is not allowed to access the requested
587 * resource. This error code shall be provided in a
588 * response to a request to query or modify an existing
589 * resource that is not accessible by the requester.
591 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
593 * The HWRM is unable to allocate the requested resource.
594 * This code only applies to requests for HWRM resource
597 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
599 * Invalid combination of flags is specified in the
602 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
604 * Invalid combination of enables fields is specified in
607 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
609 * Request contains a required TLV that is not supported by
610 * the installed version of firmware.
612 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
614 * No firmware buffer available to accept the request. Driver
615 * should retry the request.
617 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
619 * Generic HWRM execution error that represents an
622 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
624 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
625 /* Unsupported or invalid command */
626 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
627 #define HWRM_ERR_CODE_LAST \
628 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
629 uint16_t unused_0[3];
630 } __attribute__((packed));
633 /* hwrm_err_output (size:128b/16B) */
634 struct hwrm_err_output {
636 * Pass/Fail or error type
638 * Note: receiver to verify the in parameters, and fail the call
639 * with an error when appropriate
642 /* This field returns the type of original request. */
644 /* This field provides original sequence number of the command. */
647 * This field is the length of the response in bytes. The
648 * last byte of the response is a valid flag that will read
649 * as '1' when the command has been completely written to
653 /* debug info for this error response. */
655 /* debug info for this error response. */
658 * In the case of an error response, command specific error
659 * code is returned in this field.
663 * This field is used in Output records to indicate that the output
664 * is completely written to RAM. This field should be read as '1'
665 * to indicate that the output has been completely written.
666 * When writing a command completion or response to an internal processor,
667 * the order of writes has to be such that this field is written last.
670 } __attribute__((packed));
672 * Following is the signature for HWRM message field that indicates not
673 * applicable (All F's). Need to cast it the size of the field if needed.
675 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
676 /* hwrm_func_buf_rgtr */
677 #define HWRM_MAX_REQ_LEN 128
678 /* hwrm_selftest_qlist */
679 #define HWRM_MAX_RESP_LEN 280
680 /* 7 bit indirection table index. */
681 #define HW_HASH_INDEX_SIZE 0x80
682 #define HW_HASH_KEY_SIZE 40
683 /* valid key for HWRM response */
684 #define HWRM_RESP_VALID_KEY 1
685 #define HWRM_VERSION_MAJOR 1
686 #define HWRM_VERSION_MINOR 9
687 #define HWRM_VERSION_UPDATE 2
688 /* non-zero means beta version */
689 #define HWRM_VERSION_RSVD 9
690 #define HWRM_VERSION_STR "1.9.2.9"
697 /* hwrm_ver_get_input (size:192b/24B) */
698 struct hwrm_ver_get_input {
699 /* The HWRM command request type. */
702 * The completion ring to send the completion event on. This should
703 * be the NQ ID returned from the `nq_alloc` HWRM command.
707 * The sequence ID is used by the driver for tracking multiple
708 * commands. This ID is treated as opaque data by the firmware and
709 * the value is returned in the `hwrm_resp_hdr` upon completion.
713 * The target ID of the command:
714 * * 0x0-0xFFF8 - The function ID
715 * * 0xFFF8-0xFFFE - Reserved for internal processors
720 * A physical address pointer pointing to a host buffer that the
721 * command's response data will be written. This can be either a host
722 * physical address (HPA) or a guest physical address (GPA) and must
723 * point to a physically contiguous block of memory.
727 * This field represents the major version of HWRM interface
728 * specification supported by the driver HWRM implementation.
729 * The interface major version is intended to change only when
730 * non backward compatible changes are made to the HWRM
731 * interface specification.
733 uint8_t hwrm_intf_maj;
735 * This field represents the minor version of HWRM interface
736 * specification supported by the driver HWRM implementation.
737 * A change in interface minor version is used to reflect
738 * significant backward compatible modification to HWRM
739 * interface specification.
740 * This can be due to addition or removal of functionality.
741 * HWRM interface specifications with the same major version
742 * but different minor versions are compatible.
744 uint8_t hwrm_intf_min;
746 * This field represents the update version of HWRM interface
747 * specification supported by the driver HWRM implementation.
748 * The interface update version is used to reflect minor
749 * changes or bug fixes to a released HWRM interface
752 uint8_t hwrm_intf_upd;
754 } __attribute__((packed));
756 /* hwrm_ver_get_output (size:1408b/176B) */
757 struct hwrm_ver_get_output {
758 /* The specific error status for the command. */
760 /* The HWRM command request type. */
762 /* The sequence ID from the original command. */
764 /* The length of the response data in number of bytes. */
767 * This field represents the major version of HWRM interface
768 * specification supported by the HWRM implementation.
769 * The interface major version is intended to change only when
770 * non backward compatible changes are made to the HWRM
771 * interface specification.
772 * A HWRM implementation that is compliant with this
773 * specification shall provide value of 1 in this field.
775 uint8_t hwrm_intf_maj_8b;
777 * This field represents the minor version of HWRM interface
778 * specification supported by the HWRM implementation.
779 * A change in interface minor version is used to reflect
780 * significant backward compatible modification to HWRM
781 * interface specification.
782 * This can be due to addition or removal of functionality.
783 * HWRM interface specifications with the same major version
784 * but different minor versions are compatible.
785 * A HWRM implementation that is compliant with this
786 * specification shall provide value of 2 in this field.
788 uint8_t hwrm_intf_min_8b;
790 * This field represents the update version of HWRM interface
791 * specification supported by the HWRM implementation.
792 * The interface update version is used to reflect minor
793 * changes or bug fixes to a released HWRM interface
795 * A HWRM implementation that is compliant with this
796 * specification shall provide value of 2 in this field.
798 uint8_t hwrm_intf_upd_8b;
799 uint8_t hwrm_intf_rsvd_8b;
801 * This field represents the major version of HWRM firmware.
802 * A change in firmware major version represents a major
805 uint8_t hwrm_fw_maj_8b;
807 * This field represents the minor version of HWRM firmware.
808 * A change in firmware minor version represents significant
809 * firmware functionality changes.
811 uint8_t hwrm_fw_min_8b;
813 * This field represents the build version of HWRM firmware.
814 * A change in firmware build version represents bug fixes
815 * to a released firmware.
817 uint8_t hwrm_fw_bld_8b;
819 * This field is a reserved field. This field can be used to
820 * represent firmware branches or customer specific releases
821 * tied to a specific (major,minor,update) version of the
824 uint8_t hwrm_fw_rsvd_8b;
826 * This field represents the major version of mgmt firmware.
827 * A change in major version represents a major release.
829 uint8_t mgmt_fw_maj_8b;
831 * This field represents the minor version of mgmt firmware.
832 * A change in minor version represents significant
833 * functionality changes.
835 uint8_t mgmt_fw_min_8b;
837 * This field represents the build version of mgmt firmware.
838 * A change in update version represents bug fixes.
840 uint8_t mgmt_fw_bld_8b;
842 * This field is a reserved field. This field can be used to
843 * represent firmware branches or customer specific releases
844 * tied to a specific (major,minor,update) version
846 uint8_t mgmt_fw_rsvd_8b;
848 * This field represents the major version of network
850 * A change in major version represents a major release.
852 uint8_t netctrl_fw_maj_8b;
854 * This field represents the minor version of network
856 * A change in minor version represents significant
857 * functionality changes.
859 uint8_t netctrl_fw_min_8b;
861 * This field represents the build version of network
863 * A change in update version represents bug fixes.
865 uint8_t netctrl_fw_bld_8b;
867 * This field is a reserved field. This field can be used to
868 * represent firmware branches or customer specific releases
869 * tied to a specific (major,minor,update) version
871 uint8_t netctrl_fw_rsvd_8b;
873 * This field is used to indicate device's capabilities and
876 uint32_t dev_caps_cfg;
878 * If set to 1, then secure firmware update behavior
880 * If set to 0, then secure firmware update behavior is
883 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
886 * If set to 1, then firmware based DCBX agent is supported.
887 * If set to 0, then firmware based DCBX agent capability
888 * is not supported on this device.
890 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
893 * If set to 1, then HWRM short command format is supported.
894 * If set to 0, then HWRM short command format is not supported.
896 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
899 * If set to 1, then HWRM short command format is required.
900 * If set to 0, then HWRM short command format is not required.
902 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
905 * This field represents the major version of RoCE firmware.
906 * A change in major version represents a major release.
908 uint8_t roce_fw_maj_8b;
910 * This field represents the minor version of RoCE firmware.
911 * A change in minor version represents significant
912 * functionality changes.
914 uint8_t roce_fw_min_8b;
916 * This field represents the build version of RoCE firmware.
917 * A change in update version represents bug fixes.
919 uint8_t roce_fw_bld_8b;
921 * This field is a reserved field. This field can be used to
922 * represent firmware branches or customer specific releases
923 * tied to a specific (major,minor,update) version
925 uint8_t roce_fw_rsvd_8b;
927 * This field represents the name of HWRM FW (ASCII chars
928 * with NULL at the end).
930 char hwrm_fw_name[16];
932 * This field represents the name of mgmt FW (ASCII chars
933 * with NULL at the end).
935 char mgmt_fw_name[16];
937 * This field represents the name of network control
938 * firmware (ASCII chars with NULL at the end).
940 char netctrl_fw_name[16];
942 * This field is reserved for future use.
943 * The responder should set it to 0.
944 * The requester should ignore this field.
946 uint8_t reserved2[16];
948 * This field represents the name of RoCE FW (ASCII chars
949 * with NULL at the end).
951 char roce_fw_name[16];
952 /* This field returns the chip number. */
954 /* This field returns the revision of chip. */
956 /* This field returns the chip metal number. */
958 /* This field returns the bond id of the chip. */
959 uint8_t chip_bond_id;
960 /* This value indicates the type of platform used for chip implementation. */
961 uint8_t chip_platform_type;
963 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
964 /* FPGA platform of the chip. */
965 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
966 /* Palladium platform of the chip. */
967 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
968 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
969 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
971 * This field returns the maximum value of request window that
972 * is supported by the HWRM. The request window is mapped
973 * into device address space using MMIO.
975 uint16_t max_req_win_len;
977 * This field returns the maximum value of response buffer in
980 uint16_t max_resp_len;
982 * This field returns the default request timeout value in
985 uint16_t def_req_timeout;
987 * This field will indicate if any subsystems is not fully
992 * If set to 1, device is not ready.
993 * If set to 0, device is ready to accept all HWRM commands.
995 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
997 * If set to 1, external version present.
998 * If set to 0, external version not present.
1000 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1001 uint8_t unused_0[2];
1003 * For backward compatibility this field must be set to 1.
1004 * Older drivers might look for this field to be 1 before
1005 * processing the message.
1009 * This field represents the major version of HWRM interface
1010 * specification supported by the HWRM implementation.
1011 * The interface major version is intended to change only when
1012 * non backward compatible changes are made to the HWRM
1013 * interface specification. A HWRM implementation that is
1014 * compliant with this specification shall provide value of 1
1017 uint16_t hwrm_intf_major;
1019 * This field represents the minor version of HWRM interface
1020 * specification supported by the HWRM implementation.
1021 * A change in interface minor version is used to reflect
1022 * significant backward compatible modification to HWRM
1023 * interface specification. This can be due to addition or
1024 * removal of functionality. HWRM interface specifications
1025 * with the same major version but different minor versions are
1026 * compatible. A HWRM implementation that is compliant with
1027 * this specification shall provide value of 2 in this field.
1029 uint16_t hwrm_intf_minor;
1031 * This field represents the update version of HWRM interface
1032 * specification supported by the HWRM implementation. The
1033 * interface update version is used to reflect minor changes or
1034 * bug fixes to a released HWRM interface specification.
1035 * A HWRM implementation that is compliant with this
1036 * specification shall provide value of 2 in this field.
1038 uint16_t hwrm_intf_build;
1040 * This field represents the patch version of HWRM interface
1041 * specification supported by the HWRM implementation.
1043 uint16_t hwrm_intf_patch;
1045 * This field represents the major version of HWRM firmware.
1046 * A change in firmware major version represents a major
1049 uint16_t hwrm_fw_major;
1051 * This field represents the minor version of HWRM firmware.
1052 * A change in firmware minor version represents significant
1053 * firmware functionality changes.
1055 uint16_t hwrm_fw_minor;
1057 * This field represents the build version of HWRM firmware.
1058 * A change in firmware build version represents bug fixes to
1059 * a released firmware.
1061 uint16_t hwrm_fw_build;
1063 * This field is a reserved field.
1064 * This field can be used to represent firmware branches or customer
1065 * specific releases tied to a specific (major,minor,update) version
1066 * of the HWRM firmware.
1068 uint16_t hwrm_fw_patch;
1070 * This field represents the major version of mgmt firmware.
1071 * A change in major version represents a major release.
1073 uint16_t mgmt_fw_major;
1075 * This field represents the minor version of HWRM firmware.
1076 * A change in firmware minor version represents significant
1077 * firmware functionality changes.
1079 uint16_t mgmt_fw_minor;
1081 * This field represents the build version of mgmt firmware.
1082 * A change in update version represents bug fixes.
1084 uint16_t mgmt_fw_build;
1086 * This field is a reserved field. This field can be used to
1087 * represent firmware branches or customer specific releases
1088 * tied to a specific (major,minor,update) version.
1090 uint16_t mgmt_fw_patch;
1092 * This field represents the major version of network control
1093 * firmware. A change in major version represents
1096 uint16_t netctrl_fw_major;
1098 * This field represents the minor version of network control
1099 * firmware. A change in minor version represents significant
1100 * functionality changes.
1102 uint16_t netctrl_fw_minor;
1104 * This field represents the build version of network control
1105 * firmware. A change in update version represents bug fixes.
1107 uint16_t netctrl_fw_build;
1109 * This field is a reserved field. This field can be used to
1110 * represent firmware branches or customer specific releases
1111 * tied to a specific (major,minor,update) version
1113 uint16_t netctrl_fw_patch;
1115 * This field represents the major version of RoCE firmware.
1116 * A change in major version represents a major release.
1118 uint16_t roce_fw_major;
1120 * This field represents the minor version of RoCE firmware.
1121 * A change in minor version represents significant
1122 * functionality changes.
1124 uint16_t roce_fw_minor;
1126 * This field represents the build version of RoCE firmware.
1127 * A change in update version represents bug fixes.
1129 uint16_t roce_fw_build;
1131 * This field is a reserved field. This field can be used to
1132 * represent firmware branches or customer specific releases
1133 * tied to a specific (major,minor,update) version
1135 uint16_t roce_fw_patch;
1137 * This field returns the maximum extended request length acceptable
1138 * by the device which allows requests greater than mailbox size when
1139 * used with the short cmd request format.
1141 uint16_t max_ext_req_len;
1142 uint8_t unused_1[5];
1144 * This field is used in Output records to indicate that the output
1145 * is completely written to RAM. This field should be read as '1'
1146 * to indicate that the output has been completely written.
1147 * When writing a command completion or response to an internal processor,
1148 * the order of writes has to be such that this field is written last.
1151 } __attribute__((packed));
1153 /* bd_base (size:64b/8B) */
1156 /* This value identifies the type of buffer descriptor. */
1157 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1158 #define BD_BASE_TYPE_SFT 0
1160 * Indicates that this BD is 16B long and is used for
1161 * normal L2 packet transmission.
1163 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1165 * Indicates that this BD is 1BB long and is an empty
1166 * TX BD. Not valid for use by the driver.
1168 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1170 * Indicates that this BD is 16B long and is an RX Producer
1171 * (ie. empty) buffer descriptor.
1173 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1175 * Indicates that this BD is 16B long and is an RX
1176 * Producer Buffer BD.
1178 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1180 * Indicates that this BD is 16B long and is an
1181 * RX Producer Assembly Buffer Descriptor.
1183 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1185 * Indicates that this BD is 32B long and is used for
1186 * normal L2 packet transmission.
1188 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1189 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG
1190 uint8_t unused_1[7];
1191 } __attribute__((packed));
1193 /* tx_bd_short (size:128b/16B) */
1194 struct tx_bd_short {
1196 * All bits in this field must be valid on the first BD of a packet.
1197 * Only the packet_end bit must be valid for the remaining BDs
1200 uint16_t flags_type;
1201 /* This value identifies the type of buffer descriptor. */
1202 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1203 #define TX_BD_SHORT_TYPE_SFT 0
1205 * Indicates that this BD is 16B long and is used for
1206 * normal L2 packet transmission.
1208 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1209 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1211 * All bits in this field must be valid on the first BD of a packet.
1212 * Only the packet_end bit must be valid for the remaining BDs
1215 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1216 #define TX_BD_SHORT_FLAGS_SFT 6
1218 * If set to 1, the packet ends with the data in the buffer
1219 * pointed to by this descriptor. This flag must be
1220 * valid on every BD.
1222 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1224 * If set to 1, the device will not generate a completion for
1225 * this transmit packet unless there is an error in it's
1228 * is set to 0, then the packet will be completed normally.
1230 * This bit must be valid only on the first BD of a packet.
1232 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1234 * This value indicates how many 16B BD locations are consumed
1235 * in the ring by this packet.
1236 * A value of 1 indicates that this BD is the only BD (and that
1237 * the it is a short BD). A value
1238 * of 3 indicates either 3 short BDs or 1 long BD and one short
1239 * BD in the packet. A value of 0 indicates
1240 * that there are 32 BD locations in the packet (the maximum).
1242 * This field is valid only on the first BD of a packet.
1244 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1245 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1247 * This value is a hint for the length of the entire packet.
1248 * It is used by the chip to optimize internal processing.
1250 * The packet will be dropped if the hint is too short.
1252 * This field is valid only on the first BD of a packet.
1254 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1255 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1256 /* indicates packet length < 512B */
1257 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1258 /* indicates 512 <= packet length < 1KB */
1259 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1260 /* indicates 1KB <= packet length < 2KB */
1261 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1262 /* indicates packet length >= 2KB */
1263 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1264 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1265 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1267 * If set to 1, the device immediately updates the Send Consumer
1268 * Index after the buffer associated with this descriptor has
1269 * been transferred via DMA to NIC memory from host memory. An
1270 * interrupt may or may not be generated according to the state
1271 * of the interrupt avoidance mechanisms. If this bit
1272 * is set to 0, then the Consumer Index is only updated as soon
1273 * as one of the host interrupt coalescing conditions has been met.
1275 * This bit must be valid on the first BD of a packet.
1277 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1279 * This is the length of the host physical buffer this BD describes
1282 * This field must be valid on all BDs of a packet.
1286 * The opaque data field is pass through to the completion and can be
1287 * used for any data that the driver wants to associate with the
1290 * This field must be valid on the first BD of a packet.
1294 * This is the host physical address for the portion of the packet
1295 * described by this TX BD.
1297 * This value must be valid on all BDs of a packet.
1300 } __attribute__((packed));
1302 /* tx_bd_long (size:128b/16B) */
1304 /* This value identifies the type of buffer descriptor. */
1305 uint16_t flags_type;
1307 * This value indicates the type of buffer descriptor.
1310 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1311 #define TX_BD_LONG_TYPE_SFT 0
1313 * Indicates that this BD is 32B long and is used for
1314 * normal L2 packet transmission.
1316 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1317 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1319 * All bits in this field must be valid on the first BD of a packet.
1320 * Only the packet_end bit must be valid for the remaining BDs
1323 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1324 #define TX_BD_LONG_FLAGS_SFT 6
1326 * If set to 1, the packet ends with the data in the buffer
1327 * pointed to by this descriptor. This flag must be
1328 * valid on every BD.
1330 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1332 * If set to 1, the device will not generate a completion for
1333 * this transmit packet unless there is an error in it's
1336 * is set to 0, then the packet will be completed normally.
1338 * This bit must be valid only on the first BD of a packet.
1340 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1342 * This value indicates how many 16B BD locations are consumed
1343 * in the ring by this packet.
1344 * A value of 1 indicates that this BD is the only BD (and that
1345 * the it is a short BD). A value
1346 * of 3 indicates either 3 short BDs or 1 long BD and one short
1347 * BD in the packet. A value of 0 indicates
1348 * that there are 32 BD locations in the packet (the maximum).
1350 * This field is valid only on the first BD of a packet.
1352 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1353 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1355 * This value is a hint for the length of the entire packet.
1356 * It is used by the chip to optimize internal processing.
1358 * The packet will be dropped if the hint is too short.
1360 * This field is valid only on the first BD of a packet.
1362 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1363 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1364 /* indicates packet length < 512B */
1365 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1366 /* indicates 512 <= packet length < 1KB */
1367 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1368 /* indicates 1KB <= packet length < 2KB */
1369 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1370 /* indicates packet length >= 2KB */
1371 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1372 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1374 * If set to 1, the device immediately updates the Send Consumer
1375 * Index after the buffer associated with this descriptor has
1376 * been transferred via DMA to NIC memory from host memory. An
1377 * interrupt may or may not be generated according to the state
1378 * of the interrupt avoidance mechanisms. If this bit
1379 * is set to 0, then the Consumer Index is only updated as soon
1380 * as one of the host interrupt coalescing conditions has been met.
1382 * This bit must be valid on the first BD of a packet.
1384 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1386 * This is the length of the host physical buffer this BD describes
1389 * This field must be valid on all BDs of a packet.
1393 * The opaque data field is pass through to the completion and can be
1394 * used for any data that the driver wants to associate with the
1397 * This field must be valid on the first BD of a packet.
1401 * This is the host physical address for the portion of the packet
1402 * described by this TX BD.
1404 * This value must be valid on all BDs of a packet.
1407 } __attribute__((packed));
1409 /* tx_bd_long_hi (size:128b/16B) */
1410 struct tx_bd_long_hi {
1412 * All bits in this field must be valid on the first BD of a packet.
1413 * Their value on other BDs of the packet will be ignored.
1417 * If set to 1, the controller replaces the TCP/UPD checksum
1418 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1419 * checksum field of the encapsulated TCP/UDP packets with the
1420 * hardware calculated TCP/UDP checksum for the packet associated
1421 * with this descriptor. The flag is ignored if the LSO flag is set.
1423 * This bit must be valid on the first BD of a packet.
1425 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1427 * If set to 1, the controller replaces the IP checksum of the
1428 * normal packets, or the inner IP checksum of the encapsulated
1429 * packets with the hardware calculated IP checksum for the
1430 * packet associated with this descriptor.
1432 * This bit must be valid on the first BD of a packet.
1434 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1436 * If set to 1, the controller will not append an Ethernet CRC
1437 * to the end of the frame.
1439 * This bit must be valid on the first BD of a packet.
1441 * Packet must be 64B or longer when this flag is set. It is not
1442 * useful to use this bit with any form of TX offload such as
1443 * CSO or LSO. The intent is that the packet from the host already
1444 * has a valid Ethernet CRC on the packet.
1446 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1448 * If set to 1, the device will record the time at which the packet
1449 * was actually transmitted at the TX MAC.
1451 * This bit must be valid on the first BD of a packet.
1453 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1455 * If set to 1, The controller replaces the tunnel IP checksum
1456 * field with hardware calculated IP checksum for the IP header
1457 * of the packet associated with this descriptor.
1459 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1460 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1461 * bit is set, outer UDP checksum will be calculated for the following
1463 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1464 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1465 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1466 * checksum will not be calculated.
1467 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1468 * as part of LSO operation.
1470 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1472 * If set to 1, the device will treat this packet with LSO(Large
1473 * Send Offload) processing for both normal or encapsulated
1474 * packets, which is a form of TCP segmentation. When this bit
1475 * is 1, the hdr_size and mss fields must be valid. The driver
1476 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1477 * flags since the controller will replace the appropriate
1478 * checksum fields for segmented packets.
1480 * When this bit is 1, the hdr_size and mss fields must be valid.
1482 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1484 * If set to zero when LSO is '1', then the IPID will be treated
1485 * as a 16b number and will be wrapped if it exceeds a value of
1488 * If set to one when LSO is '1', then the IPID will be treated
1489 * as a 15b number and will be wrapped if it exceeds a value 0f
1492 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1494 * If set to zero when LSO is '1', then the IPID of the tunnel
1495 * IP header will not be modified during LSO operations.
1497 * If set to one when LSO is '1', then the IPID of the tunnel
1498 * IP header will be incremented for each subsequent segment of an
1501 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1504 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1506 * If set to '1', then the RoCE ICRC will be appended to the
1507 * packet. Packet must be a valid RoCE format packet.
1509 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1511 * If set to '1', then the FCoE CRC will be appended to the
1512 * packet. Packet must be a valid FCoE format packet.
1514 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1517 * When LSO is '1', this field must contain the offset of the
1518 * TCP payload from the beginning of the packet in as
1519 * 16b words. In case of encapsulated/tunneling packet, this field
1520 * contains the offset of the inner TCP payload from beginning of the
1521 * packet as 16-bit words.
1523 * This value must be valid on the first BD of a packet.
1525 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1526 #define TX_BD_LONG_HDR_SIZE_SFT 0
1529 * This is the MSS value that will be used to do the LSO processing.
1530 * The value is the length in bytes of the TCP payload for each
1531 * segment generated by the LSO operation.
1533 * This value must be valid on the first BD of a packet.
1535 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1536 #define TX_BD_LONG_MSS_SFT 0
1539 * This value selects a CFA action to perform on the packet.
1540 * Set this value to zero if no CFA action is desired.
1542 * This value must be valid on the first BD of a packet.
1544 uint16_t cfa_action;
1546 * This value is action meta-data that defines CFA edit operations
1547 * that are done in addition to any action editing.
1550 /* When key=1, This is the VLAN tag VID value. */
1551 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1552 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1553 /* When key=1, This is the VLAN tag DE value. */
1554 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1555 /* When key=1, This is the VLAN tag PRI value. */
1556 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1557 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1558 /* When key=1, This is the VLAN tag TPID select value. */
1559 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1560 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1562 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1564 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1566 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1568 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1570 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1571 /* Value programmed in CFA VLANTPID register. */
1572 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1573 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1574 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1575 /* When key=1, This is the VLAN tag TPID select value. */
1576 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1577 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1579 * This field identifies the type of edit to be performed
1582 * This value must be valid on the first BD of a packet.
1584 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1585 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1587 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1589 * - meta[17:16] - TPID select value (0 = 0x8100).
1590 * - meta[15:12] - PRI/DE value.
1591 * - meta[11:0] - VID value.
1593 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1594 #define TX_BD_LONG_CFA_META_KEY_LAST \
1595 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1596 } __attribute__((packed));
1598 /* tx_bd_empty (size:128b/16B) */
1599 struct tx_bd_empty {
1600 /* This value identifies the type of buffer descriptor. */
1602 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1603 #define TX_BD_EMPTY_TYPE_SFT 0
1605 * Indicates that this BD is 1BB long and is an empty
1606 * TX BD. Not valid for use by the driver.
1608 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1609 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1610 uint8_t unused_1[3];
1612 uint8_t unused_3[3];
1613 uint8_t unused_4[8];
1614 } __attribute__((packed));
1616 /* rx_prod_pkt_bd (size:128b/16B) */
1617 struct rx_prod_pkt_bd {
1618 /* This value identifies the type of buffer descriptor. */
1619 uint16_t flags_type;
1620 /* This value identifies the type of buffer descriptor. */
1621 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
1622 #define RX_PROD_PKT_BD_TYPE_SFT 0
1624 * Indicates that this BD is 16B long and is an RX Producer
1625 * (ie. empty) buffer descriptor.
1627 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
1628 #define RX_PROD_PKT_BD_TYPE_LAST \
1629 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
1630 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
1631 #define RX_PROD_PKT_BD_FLAGS_SFT 6
1633 * If set to 1, the packet will be placed at the address plus
1634 * 2B. The 2 Bytes of padding will be written as zero.
1636 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
1638 * If set to 1, the packet write will be padded out to the
1639 * nearest cache-line with zero value padding.
1641 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
1643 * This value is the number of additional buffers in the ring that
1644 * describe the buffer space to be consumed for the this packet.
1645 * If the value is zero, then the packet must fit within the
1646 * space described by this BD. If this value is 1 or more, it
1647 * indicates how many additional "buffer" BDs are in the ring
1648 * immediately following this BD to be used for the same
1651 * Even if the packet to be placed does not need all the
1652 * additional buffers, they will be consumed anyway.
1654 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
1655 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
1657 * This is the length in Bytes of the host physical buffer where
1658 * data for the packet may be placed in host memory.
1662 * The opaque data field is pass through to the completion and can be
1663 * used for any data that the driver wants to associate with this
1664 * receive buffer set.
1668 * This is the host physical address where data for the packet may
1669 * by placed in host memory.
1672 } __attribute__((packed));
1674 /* rx_prod_bfr_bd (size:128b/16B) */
1675 struct rx_prod_bfr_bd {
1676 /* This value identifies the type of buffer descriptor. */
1677 uint16_t flags_type;
1678 /* This value identifies the type of buffer descriptor. */
1679 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
1680 #define RX_PROD_BFR_BD_TYPE_SFT 0
1682 * Indicates that this BD is 16B long and is an RX
1683 * Producer Buffer BD.
1685 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
1686 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
1687 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
1688 #define RX_PROD_BFR_BD_FLAGS_SFT 6
1690 * This is the length in Bytes of the host physical buffer where
1691 * data for the packet may be placed in host memory.
1694 /* This field is not used. */
1697 * This is the host physical address where data for the packet may
1698 * by placed in host memory.
1701 } __attribute__((packed));
1703 /* rx_prod_agg_bd (size:128b/16B) */
1704 struct rx_prod_agg_bd {
1705 /* This value identifies the type of buffer descriptor. */
1706 uint16_t flags_type;
1707 /* This value identifies the type of buffer descriptor. */
1708 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
1709 #define RX_PROD_AGG_BD_TYPE_SFT 0
1711 * Indicates that this BD is 16B long and is an
1712 * RX Producer Assembly Buffer Descriptor.
1714 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
1715 #define RX_PROD_AGG_BD_TYPE_LAST \
1716 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
1717 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
1718 #define RX_PROD_AGG_BD_FLAGS_SFT 6
1720 * If set to 1, the packet write will be padded out to the
1721 * nearest cache-line with zero value padding.
1723 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
1725 * This is the length in Bytes of the host physical buffer where
1726 * data for the packet may be placed in host memory.
1730 * The opaque data field is pass through to the completion and can be
1731 * used for any data that the driver wants to associate with this
1732 * receive assembly buffer.
1736 * This is the host physical address where data for the packet may
1737 * by placed in host memory.
1740 } __attribute__((packed));
1742 /* cmpl_base (size:128b/16B) */
1746 * This field indicates the exact type of the completion.
1747 * By convention, the LSB identifies the length of the
1748 * record in 16B units. Even values indicate 16B
1749 * records. Odd values indicate 32B
1752 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
1753 #define CMPL_BASE_TYPE_SFT 0
1756 * Completion of TX packet. Length = 16B
1758 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
1761 * Completion of and L2 RX packet. Length = 32B
1763 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
1765 * RX Aggregation Buffer completion :
1766 * Completion of an L2 aggregation buffer in support of
1767 * TPA, HDS, or Jumbo packet completion. Length = 16B
1769 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
1771 * RX L2 TPA Start Completion:
1772 * Completion at the beginning of a TPA operation.
1775 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
1777 * RX L2 TPA End Completion:
1778 * Completion at the end of a TPA operation.
1781 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
1783 * Statistics Ejection Completion:
1784 * Completion of statistics data ejection buffer.
1787 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
1789 * HWRM Command Completion:
1790 * Completion of an HWRM command.
1792 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
1793 /* Forwarded HWRM Request */
1794 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
1795 /* Forwarded HWRM Response */
1796 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
1797 /* HWRM Asynchronous Event Information */
1798 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1799 /* CQ Notification */
1800 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
1801 /* SRQ Threshold Event */
1802 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
1803 /* DBQ Threshold Event */
1804 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
1805 /* QP Async Notification */
1806 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
1807 /* Function Async Notification */
1808 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
1809 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
1815 * This value is written by the NIC such that it will be different
1816 * for each pass through the completion queue. The even passes
1817 * will write 1. The odd passes will write 0.
1820 #define CMPL_BASE_V UINT32_C(0x1)
1821 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
1822 #define CMPL_BASE_INFO3_SFT 1
1825 } __attribute__((packed));
1827 /* tx_cmpl (size:128b/16B) */
1829 uint16_t flags_type;
1831 * This field indicates the exact type of the completion.
1832 * By convention, the LSB identifies the length of the
1833 * record in 16B units. Even values indicate 16B
1834 * records. Odd values indicate 32B
1837 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
1838 #define TX_CMPL_TYPE_SFT 0
1841 * Completion of TX packet. Length = 16B
1843 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
1844 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
1845 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1846 #define TX_CMPL_FLAGS_SFT 6
1848 * When this bit is '1', it indicates a packet that has an
1849 * error of some type. Type of error is indicated in
1852 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
1854 * When this bit is '1', it indicates that the packet completed
1855 * was transmitted using the push acceleration data provided
1856 * by the driver. When this bit is '0', it indicates that the
1857 * packet had not push acceleration data written or was executed
1858 * as a normal packet even though push data was provided.
1860 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
1861 /* unused1 is 16 b */
1864 * This is a copy of the opaque field from the first TX BD of this
1865 * transmitted packet.
1870 * This value is written by the NIC such that it will be different
1871 * for each pass through the completion queue. The even passes
1872 * will write 1. The odd passes will write 0.
1874 #define TX_CMPL_V UINT32_C(0x1)
1875 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1876 #define TX_CMPL_ERRORS_SFT 1
1878 * This error indicates that there was some sort of problem
1879 * with the BDs for the packet.
1881 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
1882 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
1884 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
1887 * BDs were not formatted correctly.
1889 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
1890 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
1891 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
1893 * When this bit is '1', it indicates that the length of
1894 * the packet was zero. No packet was transmitted.
1896 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
1898 * When this bit is '1', it indicates that the packet
1899 * was longer than the programmed limit in TDI. No
1900 * packet was transmitted.
1902 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
1904 * When this bit is '1', it indicates that one or more of the
1905 * BDs associated with this packet generated a PCI error.
1906 * This probably means the address was not valid.
1908 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
1910 * When this bit is '1', it indicates that the packet was longer
1911 * than indicated by the hint. No packet was transmitted.
1913 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
1915 * When this bit is '1', it indicates that the packet was
1916 * dropped due to Poison TLP error on one or more of the
1917 * TLPs in the PXP completion.
1919 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
1920 /* unused2 is 16 b */
1922 /* unused3 is 32 b */
1924 } __attribute__((packed));
1926 /* rx_pkt_cmpl (size:128b/16B) */
1927 struct rx_pkt_cmpl {
1928 uint16_t flags_type;
1930 * This field indicates the exact type of the completion.
1931 * By convention, the LSB identifies the length of the
1932 * record in 16B units. Even values indicate 16B
1933 * records. Odd values indicate 32B
1936 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
1937 #define RX_PKT_CMPL_TYPE_SFT 0
1940 * Completion of and L2 RX packet. Length = 32B
1942 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
1943 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
1944 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1945 #define RX_PKT_CMPL_FLAGS_SFT 6
1947 * When this bit is '1', it indicates a packet that has an
1948 * error of some type. Type of error is indicated in
1951 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
1952 /* This field indicates how the packet was placed in the buffer. */
1953 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
1954 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
1957 * Packet was placed using normal algorithm.
1959 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
1962 * Packet was placed using jumbo algorithm.
1964 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
1966 * Header/Data Separation:
1967 * Packet was placed using Header/Data separation algorithm.
1968 * The separation location is indicated by the itype field.
1970 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
1971 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
1972 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
1973 /* This bit is '1' if the RSS field in this completion is valid. */
1974 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
1976 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
1978 * This value indicates what the inner packet determined for the
1981 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
1982 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
1985 * Indicates that the packet type was not known.
1987 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
1988 (UINT32_C(0x0) << 12)
1991 * Indicates that the packet was an IP packet, but further
1992 * classification was not possible.
1994 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
1995 (UINT32_C(0x1) << 12)
1998 * Indicates that the packet was IP and TCP.
1999 * This indicates that the payload_offset field is valid.
2001 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2002 (UINT32_C(0x2) << 12)
2005 * Indicates that the packet was IP and UDP.
2006 * This indicates that the payload_offset field is valid.
2008 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2009 (UINT32_C(0x3) << 12)
2012 * Indicates that the packet was recognized as a FCoE.
2013 * This also indicates that the payload_offset field is valid.
2015 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2016 (UINT32_C(0x4) << 12)
2019 * Indicates that the packet was recognized as a RoCE.
2020 * This also indicates that the payload_offset field is valid.
2022 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2023 (UINT32_C(0x5) << 12)
2026 * Indicates that the packet was recognized as ICMP.
2027 * This indicates that the payload_offset field is valid.
2029 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2030 (UINT32_C(0x7) << 12)
2032 * PtP packet wo/timestamp:
2033 * Indicates that the packet was recognized as a PtP
2036 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2037 (UINT32_C(0x8) << 12)
2039 * PtP packet w/timestamp:
2040 * Indicates that the packet was recognized as a PtP
2041 * packet and that a timestamp was taken for the packet.
2043 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2044 (UINT32_C(0x9) << 12)
2045 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2046 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2048 * This is the length of the data for the packet stored in the
2049 * buffer(s) identified by the opaque value. This includes
2050 * the packet BD and any associated buffer BDs. This does not include
2051 * the the length of any data places in aggregation BDs.
2055 * This is a copy of the opaque field from the RX BD this completion
2059 uint8_t agg_bufs_v1;
2061 * This value is written by the NIC such that it will be different
2062 * for each pass through the completion queue. The even passes
2063 * will write 1. The odd passes will write 0.
2065 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2067 * This value is the number of aggregation buffers that follow this
2068 * entry in the completion ring that are a part of this packet.
2069 * If the value is zero, then the packet is completely contained
2070 * in the buffer space provided for the packet in the RX ring.
2072 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2073 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2074 /* unused1 is 2 b */
2075 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2076 #define RX_PKT_CMPL_UNUSED1_SFT 6
2078 * This is the RSS hash type for the packet. The value is packed
2079 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2081 * The value of tuple_extrac_op provides the information about
2082 * what fields the hash was computed on.
2083 * * 0: The RSS hash was computed over source IP address,
2084 * destination IP address, source port, and destination port of inner
2085 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2086 * the packet headers are considered inner packet headers for the RSS
2087 * hash computation purpose.
2088 * * 1: The RSS hash was computed over source IP address and destination
2089 * IP address of inner IP header. Note: For non-tunneled packets,
2090 * the packet headers are considered inner packet headers for the RSS
2091 * hash computation purpose.
2092 * * 2: The RSS hash was computed over source IP address,
2093 * destination IP address, source port, and destination port of
2094 * IP and TCP or UDP headers of outer tunnel headers.
2095 * Note: For non-tunneled packets, this value is not applicable.
2096 * * 3: The RSS hash was computed over source IP address and
2097 * destination IP address of IP header of outer tunnel headers.
2098 * Note: For non-tunneled packets, this value is not applicable.
2100 * Note that 4-tuples values listed above are applicable
2101 * for layer 4 protocols supported and enabled for RSS in the hardware,
2102 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2103 * enabled for TCP traffic only, then the values of tuple_extract_op
2104 * corresponding to 4-tuples are only valid for TCP traffic.
2106 uint8_t rss_hash_type;
2108 * This value indicates the offset in bytes from the beginning of the packet
2109 * where the inner payload starts. This value is valid for TCP, UDP,
2110 * FCoE, and RoCE packets.
2112 * A value of zero indicates that header is 256B into the packet.
2114 uint8_t payload_offset;
2115 /* unused2 is 8 b */
2118 * This value is the RSS hash value calculated for the packet
2119 * based on the mode bits and key value in the VNIC.
2122 } __attribute__((packed));
2124 /* rx_pkt_cmpl_hi (size:128b/16B) */
2125 struct rx_pkt_cmpl_hi {
2128 * This indicates that the ip checksum was calculated for the
2129 * inner packet and that the ip_cs_error field indicates if there
2132 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2134 * This indicates that the TCP, UDP or ICMP checksum was
2135 * calculated for the inner packet and that the l4_cs_error field
2136 * indicates if there was an error.
2138 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2140 * This indicates that the ip checksum was calculated for the
2141 * tunnel header and that the t_ip_cs_error field indicates if there
2144 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2146 * This indicates that the UDP checksum was
2147 * calculated for the tunnel packet and that the t_l4_cs_error field
2148 * indicates if there was an error.
2150 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2151 /* This value indicates what format the metadata field is. */
2152 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2153 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2154 /* No metadata informtaion. Value is zero. */
2155 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
2157 * The metadata field contains the VLAN tag and TPID value.
2158 * - metadata[11:0] contains the vlan VID value.
2159 * - metadata[12] contains the vlan DE value.
2160 * - metadata[15:13] contains the vlan PRI value.
2161 * - metadata[31:16] contains the vlan TPID value.
2163 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
2164 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2165 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
2167 * This field indicates the IP type for the inner-most IP header.
2168 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2169 * This value is only valid if itype indicates a packet
2170 * with an IP header.
2172 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2174 * This is data from the CFA block as indicated by the meta_format
2178 /* When meta_format=1, this value is the VLAN VID. */
2179 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2180 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2181 /* When meta_format=1, this value is the VLAN DE. */
2182 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2183 /* When meta_format=1, this value is the VLAN PRI. */
2184 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2185 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2186 /* When meta_format=1, this value is the VLAN TPID. */
2187 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2188 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2191 * This value is written by the NIC such that it will be different
2192 * for each pass through the completion queue. The even passes
2193 * will write 1. The odd passes will write 0.
2195 #define RX_PKT_CMPL_V2 \
2197 #define RX_PKT_CMPL_ERRORS_MASK \
2199 #define RX_PKT_CMPL_ERRORS_SFT 1
2201 * This error indicates that there was some sort of problem with
2202 * the BDs for the packet that was found after part of the
2203 * packet was already placed. The packet should be treated as
2206 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2208 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2209 /* No buffer error */
2210 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2211 (UINT32_C(0x0) << 1)
2214 * Packet did not fit into packet buffer provided.
2215 * For regular placement, this means the packet did not fit
2216 * in the buffer provided. For HDS and jumbo placement, this
2217 * means that the packet could not be placed into 7 physical
2220 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2221 (UINT32_C(0x1) << 1)
2224 * All BDs needed for the packet were not on-chip when
2225 * the packet arrived.
2227 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2228 (UINT32_C(0x2) << 1)
2231 * BDs were not formatted correctly.
2233 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2234 (UINT32_C(0x3) << 1)
2235 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2236 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
2238 * This indicates that there was an error in the IP header
2241 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2244 * This indicates that there was an error in the TCP, UDP
2247 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2250 * This indicates that there was an error in the tunnel
2251 * IP header checksum.
2253 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2256 * This indicates that there was an error in the tunnel
2259 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2262 * This indicates that there was a CRC error on either an FCoE
2263 * or RoCE packet. The itype indicates the packet type.
2265 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2268 * This indicates that there was an error in the tunnel
2269 * portion of the packet when this
2270 * field is non-zero.
2272 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2274 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2276 * No additional error occurred on the tunnel portion
2277 * of the packet of the packet does not have a tunnel.
2279 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2280 (UINT32_C(0x0) << 9)
2282 * Indicates that IP header version does not match
2283 * expectation from L2 Ethertype for IPv4 and IPv6
2284 * in the tunnel header.
2286 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2287 (UINT32_C(0x1) << 9)
2289 * Indicates that header length is out of range in the
2290 * tunnel header. Valid for
2293 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2294 (UINT32_C(0x2) << 9)
2296 * Indicates that the physical packet is shorter than that
2297 * claimed by the PPPoE header length for a tunnel PPPoE
2300 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2301 (UINT32_C(0x3) << 9)
2303 * Indicates that physical packet is shorter than that claimed
2304 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2305 * tunnel packet packets.
2307 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2308 (UINT32_C(0x4) << 9)
2310 * Indicates that the physical packet is shorter than that
2311 * claimed by the tunnel UDP header length for a tunnel
2312 * UDP packet that is not fragmented.
2314 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2315 (UINT32_C(0x5) << 9)
2317 * indicates that the IPv4 TTL or IPv6 hop limit check
2318 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2319 * for IPv4, and IPv6.
2321 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2322 (UINT32_C(0x6) << 9)
2323 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2324 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2326 * This indicates that there was an error in the inner
2327 * portion of the packet when this
2328 * field is non-zero.
2330 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2332 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2334 * No additional error occurred on the tunnel portion
2335 * of the packet of the packet does not have a tunnel.
2337 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2338 (UINT32_C(0x0) << 12)
2340 * Indicates that IP header version does not match
2341 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2342 * option other than VFT was parsed on
2345 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2346 (UINT32_C(0x1) << 12)
2348 * indicates that header length is out of range. Valid for
2351 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2352 (UINT32_C(0x2) << 12)
2354 * indicates that the IPv4 TTL or IPv6 hop limit check
2355 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2357 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2358 (UINT32_C(0x3) << 12)
2360 * Indicates that physical packet is shorter than that
2361 * claimed by the l3 header length. Valid for IPv4,
2362 * IPv6 packet or RoCE packets.
2364 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2365 (UINT32_C(0x4) << 12)
2367 * Indicates that the physical packet is shorter than that
2368 * claimed by the UDP header length for a UDP packet that is
2371 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2372 (UINT32_C(0x5) << 12)
2374 * Indicates that TCP header length > IP payload. Valid for
2377 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2378 (UINT32_C(0x6) << 12)
2379 /* Indicates that TCP header length < 5. Valid for TCP. */
2380 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2381 (UINT32_C(0x7) << 12)
2383 * Indicates that TCP option headers result in a TCP header
2384 * size that does not match data offset in TCP header. Valid
2387 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2388 (UINT32_C(0x8) << 12)
2389 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2390 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2392 * This field identifies the CFA action rule that was used for this
2398 * This value holds the reordering sequence number for the packet.
2399 * If the reordering sequence is not valid, then this value is zero.
2400 * The reordering domain for the packet is in the bottom 8 to 10b of
2401 * the rss_hash value. The bottom 20b of this value contain the
2402 * ordering domain value for the packet.
2404 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2405 #define RX_PKT_CMPL_REORDER_SFT 0
2406 } __attribute__((packed));
2408 /* rx_tpa_start_cmpl (size:128b/16B) */
2409 struct rx_tpa_start_cmpl {
2410 uint16_t flags_type;
2412 * This field indicates the exact type of the completion.
2413 * By convention, the LSB identifies the length of the
2414 * record in 16B units. Even values indicate 16B
2415 * records. Odd values indicate 32B
2418 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2419 #define RX_TPA_START_CMPL_TYPE_SFT 0
2421 * RX L2 TPA Start Completion:
2422 * Completion at the beginning of a TPA operation.
2425 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2426 #define RX_TPA_START_CMPL_TYPE_LAST \
2427 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2428 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2429 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2430 /* This bit will always be '0' for TPA start completions. */
2431 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2432 /* This field indicates how the packet was placed in the buffer. */
2433 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2434 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2437 * TPA Packet was placed using jumbo algorithm. This means
2438 * that the first buffer will be filled with data before
2439 * moving to aggregation buffers. Each aggregation buffer
2440 * will be filled before moving to the next aggregation
2443 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2444 (UINT32_C(0x1) << 7)
2446 * Header/Data Separation:
2447 * Packet was placed using Header/Data separation algorithm.
2448 * The separation location is indicated by the itype field.
2450 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2451 (UINT32_C(0x2) << 7)
2454 * Packet will be placed using GRO/Jumbo where the first
2455 * packet is filled with data. Subsequent packets will be
2456 * placed such that any one packet does not span two
2457 * aggregation buffers unless it starts at the beginning of
2458 * an aggregation buffer.
2460 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2461 (UINT32_C(0x5) << 7)
2463 * GRO/Header-Data Separation:
2464 * Packet will be placed using GRO/HDS where the header
2465 * is in the first packet.
2466 * Payload of each packet will be
2467 * placed such that any one packet does not span two
2468 * aggregation buffers unless it starts at the beginning of
2469 * an aggregation buffer.
2471 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2472 (UINT32_C(0x6) << 7)
2473 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2474 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2475 /* This bit is '1' if the RSS field in this completion is valid. */
2476 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2478 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2480 * This value indicates what the inner packet determined for the
2483 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2484 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2487 * Indicates that the packet was IP and TCP.
2489 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2490 (UINT32_C(0x2) << 12)
2491 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2492 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2494 * This value indicates the amount of packet data written to the
2495 * buffer the opaque field in this completion corresponds to.
2499 * This is a copy of the opaque field from the RX BD this completion
2504 * This value is written by the NIC such that it will be different
2505 * for each pass through the completion queue. The even passes
2506 * will write 1. The odd passes will write 0.
2510 * This value is written by the NIC such that it will be different
2511 * for each pass through the completion queue. The even passes
2512 * will write 1. The odd passes will write 0.
2514 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2515 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2517 * This is the RSS hash type for the packet. The value is packed
2518 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2520 * The value of tuple_extrac_op provides the information about
2521 * what fields the hash was computed on.
2522 * * 0: The RSS hash was computed over source IP address,
2523 * destination IP address, source port, and destination port of inner
2524 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2525 * the packet headers are considered inner packet headers for the RSS
2526 * hash computation purpose.
2527 * * 1: The RSS hash was computed over source IP address and destination
2528 * IP address of inner IP header. Note: For non-tunneled packets,
2529 * the packet headers are considered inner packet headers for the RSS
2530 * hash computation purpose.
2531 * * 2: The RSS hash was computed over source IP address,
2532 * destination IP address, source port, and destination port of
2533 * IP and TCP or UDP headers of outer tunnel headers.
2534 * Note: For non-tunneled packets, this value is not applicable.
2535 * * 3: The RSS hash was computed over source IP address and
2536 * destination IP address of IP header of outer tunnel headers.
2537 * Note: For non-tunneled packets, this value is not applicable.
2539 * Note that 4-tuples values listed above are applicable
2540 * for layer 4 protocols supported and enabled for RSS in the hardware,
2541 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2542 * enabled for TCP traffic only, then the values of tuple_extract_op
2543 * corresponding to 4-tuples are only valid for TCP traffic.
2545 uint8_t rss_hash_type;
2547 * This is the aggregation ID that the completion is associated
2548 * with. Use this number to correlate the TPA start completion
2549 * with the TPA end completion.
2552 /* unused2 is 9 b */
2553 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2554 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2556 * This is the aggregation ID that the completion is associated
2557 * with. Use this number to correlate the TPA start completion
2558 * with the TPA end completion.
2560 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
2561 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
2563 * This value is the RSS hash value calculated for the packet
2564 * based on the mode bits and key value in the VNIC.
2567 } __attribute__((packed));
2569 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
2570 struct rx_tpa_start_cmpl_hi {
2573 * This indicates that the ip checksum was calculated for the
2574 * inner packet and that the sum passed for all segments
2575 * included in the aggregation.
2577 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2579 * This indicates that the TCP, UDP or ICMP checksum was
2580 * calculated for the inner packet and that the sum passed
2581 * for all segments included in the aggregation.
2583 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2585 * This indicates that the ip checksum was calculated for the
2586 * tunnel header and that the sum passed for all segments
2587 * included in the aggregation.
2589 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2591 * This indicates that the UDP checksum was
2592 * calculated for the tunnel packet and that the sum passed for
2593 * all segments included in the aggregation.
2595 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2596 /* This value indicates what format the metadata field is. */
2597 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2598 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
2599 /* No metadata informtaion. Value is zero. */
2600 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
2601 (UINT32_C(0x0) << 4)
2603 * The metadata field contains the VLAN tag and TPID value.
2604 * - metadata[11:0] contains the vlan VID value.
2605 * - metadata[12] contains the vlan DE value.
2606 * - metadata[15:13] contains the vlan PRI value.
2607 * - metadata[31:16] contains the vlan TPID value.
2609 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
2610 (UINT32_C(0x1) << 4)
2611 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
2612 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
2614 * This field indicates the IP type for the inner-most IP header.
2615 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2617 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2619 * This is data from the CFA block as indicated by the meta_format
2623 /* When meta_format=1, this value is the VLAN VID. */
2624 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2625 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
2626 /* When meta_format=1, this value is the VLAN DE. */
2627 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
2628 /* When meta_format=1, this value is the VLAN PRI. */
2629 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2630 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
2631 /* When meta_format=1, this value is the VLAN TPID. */
2632 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2633 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
2636 * This value is written by the NIC such that it will be different
2637 * for each pass through the completion queue. The even passes
2638 * will write 1. The odd passes will write 0.
2640 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
2642 * This field identifies the CFA action rule that was used for this
2647 * This is the size in bytes of the inner most L4 header.
2648 * This can be subtracted from the payload_offset to determine
2649 * the start of the inner most L4 header.
2651 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
2653 * This is the offset from the beginning of the packet in bytes for
2654 * the outer L3 header. If there is no outer L3 header, then this
2657 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
2658 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
2660 * This is the offset from the beginning of the packet in bytes for
2661 * the inner most L2 header.
2663 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
2664 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
2666 * This is the offset from the beginning of the packet in bytes for
2667 * the inner most L3 header.
2669 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
2670 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
2672 * This is the size in bytes of the inner most L4 header.
2673 * This can be subtracted from the payload_offset to determine
2674 * the start of the inner most L4 header.
2676 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
2677 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
2678 } __attribute__((packed));
2680 /* rx_tpa_end_cmpl (size:128b/16B) */
2681 struct rx_tpa_end_cmpl {
2682 uint16_t flags_type;
2684 * This field indicates the exact type of the completion.
2685 * By convention, the LSB identifies the length of the
2686 * record in 16B units. Even values indicate 16B
2687 * records. Odd values indicate 32B
2690 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
2691 #define RX_TPA_END_CMPL_TYPE_SFT 0
2693 * RX L2 TPA End Completion:
2694 * Completion at the end of a TPA operation.
2697 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
2698 #define RX_TPA_END_CMPL_TYPE_LAST \
2699 RX_TPA_END_CMPL_TYPE_RX_TPA_END
2700 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2701 #define RX_TPA_END_CMPL_FLAGS_SFT 6
2703 * When this bit is '1', it indicates a packet that has an
2704 * error of some type. Type of error is indicated in
2707 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
2708 /* This field indicates how the packet was placed in the buffer. */
2709 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2710 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
2713 * TPA Packet was placed using jumbo algorithm. This means
2714 * that the first buffer will be filled with data before
2715 * moving to aggregation buffers. Each aggregation buffer
2716 * will be filled before moving to the next aggregation
2719 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
2720 (UINT32_C(0x1) << 7)
2722 * Header/Data Separation:
2723 * Packet was placed using Header/Data separation algorithm.
2724 * The separation location is indicated by the itype field.
2726 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
2727 (UINT32_C(0x2) << 7)
2730 * Packet will be placed using GRO/Jumbo where the first
2731 * packet is filled with data. Subsequent packets will be
2732 * placed such that any one packet does not span two
2733 * aggregation buffers unless it starts at the beginning of
2734 * an aggregation buffer.
2736 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2737 (UINT32_C(0x5) << 7)
2739 * GRO/Header-Data Separation:
2740 * Packet will be placed using GRO/HDS where the header
2741 * is in the first packet.
2742 * Payload of each packet will be
2743 * placed such that any one packet does not span two
2744 * aggregation buffers unless it starts at the beginning of
2745 * an aggregation buffer.
2747 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2748 (UINT32_C(0x6) << 7)
2749 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
2750 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
2752 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
2753 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
2755 * This value indicates what the inner packet determined for the
2758 * Indicates that the packet was IP and TCP. This indicates
2759 * that the ip_cs field is valid and that the tcp_udp_cs
2760 * field is valid and contains the TCP checksum.
2761 * This also indicates that the payload_offset field is valid.
2763 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2764 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
2766 * This value is zero for TPA End completions.
2767 * There is no data in the buffer that corresponds to the opaque
2768 * value in this completion.
2772 * This is a copy of the opaque field from the RX BD this completion
2777 * This value is written by the NIC such that it will be different
2778 * for each pass through the completion queue. The even passes
2779 * will write 1. The odd passes will write 0.
2781 uint8_t agg_bufs_v1;
2783 * This value is written by the NIC such that it will be different
2784 * for each pass through the completion queue. The even passes
2785 * will write 1. The odd passes will write 0.
2787 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
2789 * This value is the number of aggregation buffers that follow this
2790 * entry in the completion ring that are a part of this aggregation
2792 * If the value is zero, then the packet is completely contained
2793 * in the buffer space provided in the aggregation start completion.
2795 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
2796 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
2797 /* This value is the number of segments in the TPA operation. */
2800 * This value indicates the offset in bytes from the beginning of the packet
2801 * where the inner payload starts. This value is valid for TCP, UDP,
2802 * FCoE, and RoCE packets.
2804 * A value of zero indicates an offset of 256 bytes.
2806 uint8_t payload_offset;
2808 /* unused2 is 1 b */
2809 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
2811 * This is the aggregation ID that the completion is associated
2812 * with. Use this number to correlate the TPA start completion
2813 * with the TPA end completion.
2815 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
2816 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
2818 * For non-GRO packets, this value is the
2819 * timestamp delta between earliest and latest timestamp values for
2820 * TPA packet. If packets were not time stamped, then delta will be
2823 * For GRO packets, this field is zero except for the following
2826 * Timestamp present indication. When '0', no Timestamp
2827 * option is in the packet. When '1', then a Timestamp
2828 * option is present in the packet.
2831 } __attribute__((packed));
2833 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
2834 struct rx_tpa_end_cmpl_hi {
2836 * This value is the number of duplicate ACKs that have been
2837 * received as part of the TPA operation.
2839 uint32_t tpa_dup_acks;
2841 * This value is the number of duplicate ACKs that have been
2842 * received as part of the TPA operation.
2844 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
2845 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
2847 * This value is the valid when TPA completion is active. It
2848 * indicates the length of the longest segment of the TPA operation
2849 * for LRO mode and the length of the first segment in GRO mode.
2851 * This value may be used by GRO software to re-construct the original
2852 * packet stream from the TPA packet. This is the length of all
2853 * but the last segment for GRO. In LRO mode this value may be used
2854 * to indicate MSS size to the stack.
2856 uint16_t tpa_seg_len;
2857 /* unused4 is 16 b */
2861 * This value is written by the NIC such that it will be different
2862 * for each pass through the completion queue. The even passes
2863 * will write 1. The odd passes will write 0.
2865 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
2866 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2867 #define RX_TPA_END_CMPL_ERRORS_SFT 1
2869 * This error indicates that there was some sort of problem with
2870 * the BDs for the packet that was found after part of the
2871 * packet was already placed. The packet should be treated as
2874 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2875 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2877 * This error occurs when there is a fatal HW problem in
2878 * the chip only. It indicates that there were not
2879 * BDs on chip but that there was adequate reservation.
2880 * provided by the TPA block.
2882 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2883 (UINT32_C(0x2) << 1)
2885 * This error occurs when TPA block was not configured to
2886 * reserve adequate BDs for TPA operations on this RX
2887 * ring. All data for the TPA operation was not placed.
2889 * This error can also be generated when the number of
2890 * segments is not programmed correctly in TPA and the
2891 * 33 total aggregation buffers allowed for the TPA
2892 * operation has been exceeded.
2894 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
2895 (UINT32_C(0x4) << 1)
2896 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
2897 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
2898 /* unused5 is 16 b */
2901 * This is the opaque value that was completed for the TPA start
2902 * completion that corresponds to this TPA end completion.
2904 uint32_t start_opaque;
2905 } __attribute__((packed));
2907 /* rx_abuf_cmpl (size:128b/16B) */
2908 struct rx_abuf_cmpl {
2911 * This field indicates the exact type of the completion.
2912 * By convention, the LSB identifies the length of the
2913 * record in 16B units. Even values indicate 16B
2914 * records. Odd values indicate 32B
2917 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
2918 #define RX_ABUF_CMPL_TYPE_SFT 0
2920 * RX Aggregation Buffer completion :
2921 * Completion of an L2 aggregation buffer in support of
2922 * TPA, HDS, or Jumbo packet completion. Length = 16B
2924 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
2925 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
2927 * This is the length of the data for the packet stored in this
2928 * aggregation buffer identified by the opaque value. This does not
2929 * include the length of any
2930 * data placed in other aggregation BDs or in the packet or buffer
2931 * BDs. This length does not include any space added due to
2932 * hdr_offset register during HDS placement mode.
2936 * This is a copy of the opaque field from the RX BD this aggregation
2937 * buffer corresponds to.
2942 * This value is written by the NIC such that it will be different
2943 * for each pass through the completion queue. The even passes
2944 * will write 1. The odd passes will write 0.
2946 #define RX_ABUF_CMPL_V UINT32_C(0x1)
2947 /* unused3 is 32 b */
2949 } __attribute__((packed));
2951 /* eject_cmpl (size:128b/16B) */
2955 * This field indicates the exact type of the completion.
2956 * By convention, the LSB identifies the length of the
2957 * record in 16B units. Even values indicate 16B
2958 * records. Odd values indicate 32B
2961 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
2962 #define EJECT_CMPL_TYPE_SFT 0
2964 * Statistics Ejection Completion:
2965 * Completion of statistics data ejection buffer.
2968 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
2969 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
2971 * This is the length of the statistics data stored in this
2976 * This is a copy of the opaque field from the RX BD this ejection
2977 * buffer corresponds to.
2982 * This value is written by the NIC such that it will be different
2983 * for each pass through the completion queue. The even passes
2984 * will write 1. The odd passes will write 0.
2986 #define EJECT_CMPL_V UINT32_C(0x1)
2987 /* unused3 is 32 b */
2989 } __attribute__((packed));
2991 /* hwrm_cmpl (size:128b/16B) */
2995 * This field indicates the exact type of the completion.
2996 * By convention, the LSB identifies the length of the
2997 * record in 16B units. Even values indicate 16B
2998 * records. Odd values indicate 32B
3001 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3002 #define HWRM_CMPL_TYPE_SFT 0
3004 * HWRM Command Completion:
3005 * Completion of an HWRM command.
3007 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3008 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3009 /* This is the sequence_id of the HWRM command that has completed. */
3010 uint16_t sequence_id;
3011 /* unused2 is 32 b */
3015 * This value is written by the NIC such that it will be different
3016 * for each pass through the completion queue. The even passes
3017 * will write 1. The odd passes will write 0.
3019 #define HWRM_CMPL_V UINT32_C(0x1)
3020 /* unused4 is 32 b */
3022 } __attribute__((packed));
3024 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3025 struct hwrm_fwd_req_cmpl {
3027 * This field indicates the exact type of the completion.
3028 * By convention, the LSB identifies the length of the
3029 * record in 16B units. Even values indicate 16B
3030 * records. Odd values indicate 32B
3033 uint16_t req_len_type;
3035 * This field indicates the exact type of the completion.
3036 * By convention, the LSB identifies the length of the
3037 * record in 16B units. Even values indicate 16B
3038 * records. Odd values indicate 32B
3041 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3042 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3043 /* Forwarded HWRM Request */
3044 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3045 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3046 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3047 /* Length of forwarded request in bytes. */
3048 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3049 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3051 * Source ID of this request.
3052 * Typically used in forwarding requests and responses.
3053 * 0x0 - 0xFFF8 - Used for function ids
3054 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3058 /* unused1 is 32 b */
3060 /* Address of forwarded request. */
3061 uint32_t req_buf_addr_v[2];
3063 * This value is written by the NIC such that it will be different
3064 * for each pass through the completion queue. The even passes
3065 * will write 1. The odd passes will write 0.
3067 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3068 /* Address of forwarded request. */
3069 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3070 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3071 } __attribute__((packed));
3073 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3074 struct hwrm_fwd_resp_cmpl {
3077 * This field indicates the exact type of the completion.
3078 * By convention, the LSB identifies the length of the
3079 * record in 16B units. Even values indicate 16B
3080 * records. Odd values indicate 32B
3083 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3084 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3085 /* Forwarded HWRM Response */
3086 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3087 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3088 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3090 * Source ID of this response.
3091 * Typically used in forwarding requests and responses.
3092 * 0x0 - 0xFFF8 - Used for function ids
3093 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3097 /* Length of forwarded response in bytes. */
3099 /* unused2 is 16 b */
3101 /* Address of forwarded request. */
3102 uint32_t resp_buf_addr_v[2];
3104 * This value is written by the NIC such that it will be different
3105 * for each pass through the completion queue. The even passes
3106 * will write 1. The odd passes will write 0.
3108 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3109 /* Address of forwarded request. */
3110 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3111 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3112 } __attribute__((packed));
3114 /* hwrm_async_event_cmpl (size:128b/16B) */
3115 struct hwrm_async_event_cmpl {
3118 * This field indicates the exact type of the completion.
3119 * By convention, the LSB identifies the length of the
3120 * record in 16B units. Even values indicate 16B
3121 * records. Odd values indicate 32B
3124 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3125 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3126 /* HWRM Asynchronous Event Information */
3127 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3128 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3129 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3130 /* Identifiers of events. */
3132 /* Link status changed */
3133 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3135 /* Link MTU changed */
3136 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3138 /* Link speed changed */
3139 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3141 /* DCB Configuration changed */
3142 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3144 /* Port connection not allowed */
3145 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3147 /* Link speed configuration was not allowed */
3148 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3150 /* Link speed configuration change */
3151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3153 /* Port PHY configuration change */
3154 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3156 /* Function driver unloaded */
3157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3159 /* Function driver loaded */
3160 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3162 /* Function FLR related processing has completed */
3163 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3165 /* PF driver unloaded */
3166 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3168 /* PF driver loaded */
3169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3171 /* VF Function Level Reset (FLR) */
3172 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3174 /* VF MAC Address Change */
3175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3177 /* PF-VF communication channel status change. */
3178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3180 /* VF Configuration Change */
3181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3183 /* LLFC/PFC Configuration Change */
3184 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3186 /* Default VNIC Configuration Change */
3187 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
3190 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3192 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3193 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3194 /* Event specific data */
3195 uint32_t event_data2;
3198 * This value is written by the NIC such that it will be different
3199 * for each pass through the completion queue. The even passes
3200 * will write 1. The odd passes will write 0.
3202 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3204 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3205 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3206 /* 8-lsb timestamp from POR (100-msec resolution) */
3207 uint8_t timestamp_lo;
3208 /* 16-lsb timestamp from POR (100-msec resolution) */
3209 uint16_t timestamp_hi;
3210 /* Event specific data */
3211 uint32_t event_data1;
3212 } __attribute__((packed));
3214 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3215 struct hwrm_async_event_cmpl_link_status_change {
3218 * This field indicates the exact type of the completion.
3219 * By convention, the LSB identifies the length of the
3220 * record in 16B units. Even values indicate 16B
3221 * records. Odd values indicate 32B
3224 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3226 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3227 /* HWRM Asynchronous Event Information */
3228 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3230 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3231 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3232 /* Identifiers of events. */
3234 /* Link status changed */
3235 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3237 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3238 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3239 /* Event specific data */
3240 uint32_t event_data2;
3243 * This value is written by the NIC such that it will be different
3244 * for each pass through the completion queue. The even passes
3245 * will write 1. The odd passes will write 0.
3247 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3250 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3252 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3253 /* 8-lsb timestamp from POR (100-msec resolution) */
3254 uint8_t timestamp_lo;
3255 /* 16-lsb timestamp from POR (100-msec resolution) */
3256 uint16_t timestamp_hi;
3257 /* Event specific data */
3258 uint32_t event_data1;
3259 /* Indicates link status change */
3260 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3263 * If this bit set to 0, then it indicates that the link
3264 * was up and it went down.
3266 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3269 * If this bit is set to 1, then it indicates that the link
3270 * was down and it went up.
3272 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3274 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3275 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3276 /* Indicates the physical port this link status change occur */
3277 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3279 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3282 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3284 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3286 /* Indicates the physical function this event occured on. */
3287 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
3289 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
3291 } __attribute__((packed));
3293 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
3294 struct hwrm_async_event_cmpl_link_mtu_change {
3297 * This field indicates the exact type of the completion.
3298 * By convention, the LSB identifies the length of the
3299 * record in 16B units. Even values indicate 16B
3300 * records. Odd values indicate 32B
3303 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
3305 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
3306 /* HWRM Asynchronous Event Information */
3307 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3309 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
3310 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
3311 /* Identifiers of events. */
3313 /* Link MTU changed */
3314 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
3316 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
3317 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
3318 /* Event specific data */
3319 uint32_t event_data2;
3322 * This value is written by the NIC such that it will be different
3323 * for each pass through the completion queue. The even passes
3324 * will write 1. The odd passes will write 0.
3326 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
3328 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
3330 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
3331 /* 8-lsb timestamp from POR (100-msec resolution) */
3332 uint8_t timestamp_lo;
3333 /* 16-lsb timestamp from POR (100-msec resolution) */
3334 uint16_t timestamp_hi;
3335 /* Event specific data */
3336 uint32_t event_data1;
3337 /* The new MTU of the link in bytes. */
3338 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
3340 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
3341 } __attribute__((packed));
3343 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
3344 struct hwrm_async_event_cmpl_link_speed_change {
3347 * This field indicates the exact type of the completion.
3348 * By convention, the LSB identifies the length of the
3349 * record in 16B units. Even values indicate 16B
3350 * records. Odd values indicate 32B
3353 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
3355 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
3356 /* HWRM Asynchronous Event Information */
3357 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3359 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
3360 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
3361 /* Identifiers of events. */
3363 /* Link speed changed */
3364 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
3366 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
3367 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
3368 /* Event specific data */
3369 uint32_t event_data2;
3372 * This value is written by the NIC such that it will be different
3373 * for each pass through the completion queue. The even passes
3374 * will write 1. The odd passes will write 0.
3376 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
3379 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
3381 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
3382 /* 8-lsb timestamp from POR (100-msec resolution) */
3383 uint8_t timestamp_lo;
3384 /* 16-lsb timestamp from POR (100-msec resolution) */
3385 uint16_t timestamp_hi;
3386 /* Event specific data */
3387 uint32_t event_data1;
3389 * When this bit is '1', the link was forced to the
3390 * force_link_speed value.
3392 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
3394 /* The new link speed in 100 Mbps units. */
3395 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
3397 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
3399 /* 100Mb link speed */
3400 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
3401 (UINT32_C(0x1) << 1)
3402 /* 1Gb link speed */
3403 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
3404 (UINT32_C(0xa) << 1)
3405 /* 2Gb link speed */
3406 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
3407 (UINT32_C(0x14) << 1)
3408 /* 25Gb link speed */
3409 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
3410 (UINT32_C(0x19) << 1)
3411 /* 10Gb link speed */
3412 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
3413 (UINT32_C(0x64) << 1)
3414 /* 20Mb link speed */
3415 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
3416 (UINT32_C(0xc8) << 1)
3417 /* 25Gb link speed */
3418 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
3419 (UINT32_C(0xfa) << 1)
3420 /* 40Gb link speed */
3421 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
3422 (UINT32_C(0x190) << 1)
3423 /* 50Gb link speed */
3424 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
3425 (UINT32_C(0x1f4) << 1)
3426 /* 100Gb link speed */
3427 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
3428 (UINT32_C(0x3e8) << 1)
3429 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
3430 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
3432 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3433 UINT32_C(0xffff0000)
3434 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3436 } __attribute__((packed));
3438 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
3439 struct hwrm_async_event_cmpl_dcb_config_change {
3442 * This field indicates the exact type of the completion.
3443 * By convention, the LSB identifies the length of the
3444 * record in 16B units. Even values indicate 16B
3445 * records. Odd values indicate 32B
3448 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
3450 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
3451 /* HWRM Asynchronous Event Information */
3452 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3454 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
3455 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3456 /* Identifiers of events. */
3458 /* DCB Configuration changed */
3459 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
3461 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
3462 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
3463 /* Event specific data */
3464 uint32_t event_data2;
3465 /* ETS configuration change */
3466 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
3468 /* PFC configuration change */
3469 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
3471 /* APP configuration change */
3472 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
3476 * This value is written by the NIC such that it will be different
3477 * for each pass through the completion queue. The even passes
3478 * will write 1. The odd passes will write 0.
3480 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
3483 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
3485 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
3486 /* 8-lsb timestamp from POR (100-msec resolution) */
3487 uint8_t timestamp_lo;
3488 /* 16-lsb timestamp from POR (100-msec resolution) */
3489 uint16_t timestamp_hi;
3490 /* Event specific data */
3491 uint32_t event_data1;
3493 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3495 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3497 /* Priority recommended for RoCE traffic */
3498 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
3500 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
3503 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
3504 (UINT32_C(0xff) << 16)
3505 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
3506 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
3507 /* Priority recommended for L2 traffic */
3508 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
3509 UINT32_C(0xff000000)
3510 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
3513 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
3514 (UINT32_C(0xff) << 24)
3515 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
3516 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
3517 } __attribute__((packed));
3519 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
3520 struct hwrm_async_event_cmpl_port_conn_not_allowed {
3523 * This field indicates the exact type of the completion.
3524 * By convention, the LSB identifies the length of the
3525 * record in 16B units. Even values indicate 16B
3526 * records. Odd values indicate 32B
3529 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
3531 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
3533 /* HWRM Asynchronous Event Information */
3534 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3536 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
3537 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3538 /* Identifiers of events. */
3540 /* Port connection not allowed */
3541 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3543 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
3544 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
3545 /* Event specific data */
3546 uint32_t event_data2;
3549 * This value is written by the NIC such that it will be different
3550 * for each pass through the completion queue. The even passes
3551 * will write 1. The odd passes will write 0.
3553 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
3556 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
3558 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
3559 /* 8-lsb timestamp from POR (100-msec resolution) */
3560 uint8_t timestamp_lo;
3561 /* 16-lsb timestamp from POR (100-msec resolution) */
3562 uint16_t timestamp_hi;
3563 /* Event specific data */
3564 uint32_t event_data1;
3566 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3568 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3571 * This value indicates the current port level enforcement policy
3572 * for the optics module when there is an optical module mismatch
3573 * and port is not connected.
3575 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
3577 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
3579 /* No enforcement */
3580 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
3581 (UINT32_C(0x0) << 16)
3582 /* Disable Transmit side Laser. */
3583 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
3584 (UINT32_C(0x1) << 16)
3585 /* Raise a warning message. */
3586 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
3587 (UINT32_C(0x2) << 16)
3588 /* Power down the module. */
3589 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
3590 (UINT32_C(0x3) << 16)
3591 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
3592 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
3593 } __attribute__((packed));
3595 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
3596 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
3599 * This field indicates the exact type of the completion.
3600 * By convention, the LSB identifies the length of the
3601 * record in 16B units. Even values indicate 16B
3602 * records. Odd values indicate 32B
3605 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
3607 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
3609 /* HWRM Asynchronous Event Information */
3610 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3612 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
3613 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3614 /* Identifiers of events. */
3616 /* Link speed configuration was not allowed */
3617 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3619 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
3620 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
3621 /* Event specific data */
3622 uint32_t event_data2;
3625 * This value is written by the NIC such that it will be different
3626 * for each pass through the completion queue. The even passes
3627 * will write 1. The odd passes will write 0.
3629 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
3632 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
3634 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
3635 /* 8-lsb timestamp from POR (100-msec resolution) */
3636 uint8_t timestamp_lo;
3637 /* 16-lsb timestamp from POR (100-msec resolution) */
3638 uint16_t timestamp_hi;
3639 /* Event specific data */
3640 uint32_t event_data1;
3642 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3644 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3646 } __attribute__((packed));
3648 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
3649 struct hwrm_async_event_cmpl_link_speed_cfg_change {
3652 * This field indicates the exact type of the completion.
3653 * By convention, the LSB identifies the length of the
3654 * record in 16B units. Even values indicate 16B
3655 * records. Odd values indicate 32B
3658 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
3660 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
3662 /* HWRM Asynchronous Event Information */
3663 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3665 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
3666 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3667 /* Identifiers of events. */
3669 /* Link speed configuration change */
3670 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3672 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
3673 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
3674 /* Event specific data */
3675 uint32_t event_data2;
3678 * This value is written by the NIC such that it will be different
3679 * for each pass through the completion queue. The even passes
3680 * will write 1. The odd passes will write 0.
3682 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
3685 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
3687 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
3688 /* 8-lsb timestamp from POR (100-msec resolution) */
3689 uint8_t timestamp_lo;
3690 /* 16-lsb timestamp from POR (100-msec resolution) */
3691 uint16_t timestamp_hi;
3692 /* Event specific data */
3693 uint32_t event_data1;
3695 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3697 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3700 * If set to 1, it indicates that the supported link speeds
3701 * configuration on the port has changed.
3702 * If set to 0, then there is no change in supported link speeds
3705 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
3708 * If set to 1, it indicates that the link speed configuration
3709 * on the port has become illegal or invalid.
3710 * If set to 0, then the link speed configuration on the port is
3713 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
3715 } __attribute__((packed));
3717 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
3718 struct hwrm_async_event_cmpl_port_phy_cfg_change {
3721 * This field indicates the exact type of the completion.
3722 * By convention, the LSB identifies the length of the
3723 * record in 16B units. Even values indicate 16B
3724 * records. Odd values indicate 32B
3727 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
3729 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
3731 /* HWRM Asynchronous Event Information */
3732 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3734 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
3735 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3736 /* Identifiers of events. */
3738 /* Port PHY configuration change */
3739 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
3741 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
3742 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
3743 /* Event specific data */
3744 uint32_t event_data2;
3747 * This value is written by the NIC such that it will be different
3748 * for each pass through the completion queue. The even passes
3749 * will write 1. The odd passes will write 0.
3751 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
3754 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
3756 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
3757 /* 8-lsb timestamp from POR (100-msec resolution) */
3758 uint8_t timestamp_lo;
3759 /* 16-lsb timestamp from POR (100-msec resolution) */
3760 uint16_t timestamp_hi;
3761 /* Event specific data */
3762 uint32_t event_data1;
3764 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3766 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3769 * If set to 1, it indicates that the FEC
3770 * configuration on the port has changed.
3771 * If set to 0, then there is no change in FEC configuration.
3773 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
3776 * If set to 1, it indicates that the EEE configuration
3777 * on the port has changed.
3778 * If set to 0, then there is no change in EEE configuration
3781 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
3784 * If set to 1, it indicates that the pause configuration
3785 * on the PHY has changed.
3786 * If set to 0, then there is no change in the pause
3787 * configuration on the PHY.
3789 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
3791 } __attribute__((packed));
3793 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
3794 struct hwrm_async_event_cmpl_func_drvr_unload {
3797 * This field indicates the exact type of the completion.
3798 * By convention, the LSB identifies the length of the
3799 * record in 16B units. Even values indicate 16B
3800 * records. Odd values indicate 32B
3803 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
3805 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
3806 /* HWRM Asynchronous Event Information */
3807 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
3809 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
3810 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
3811 /* Identifiers of events. */
3813 /* Function driver unloaded */
3814 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
3816 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
3817 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
3818 /* Event specific data */
3819 uint32_t event_data2;
3822 * This value is written by the NIC such that it will be different
3823 * for each pass through the completion queue. The even passes
3824 * will write 1. The odd passes will write 0.
3826 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
3828 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
3830 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
3831 /* 8-lsb timestamp from POR (100-msec resolution) */
3832 uint8_t timestamp_lo;
3833 /* 16-lsb timestamp from POR (100-msec resolution) */
3834 uint16_t timestamp_hi;
3835 /* Event specific data */
3836 uint32_t event_data1;
3838 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
3840 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
3842 } __attribute__((packed));
3844 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
3845 struct hwrm_async_event_cmpl_func_drvr_load {
3848 * This field indicates the exact type of the completion.
3849 * By convention, the LSB identifies the length of the
3850 * record in 16B units. Even values indicate 16B
3851 * records. Odd values indicate 32B
3854 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
3856 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
3857 /* HWRM Asynchronous Event Information */
3858 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
3860 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
3861 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
3862 /* Identifiers of events. */
3864 /* Function driver loaded */
3865 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
3867 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
3868 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
3869 /* Event specific data */
3870 uint32_t event_data2;
3873 * This value is written by the NIC such that it will be different
3874 * for each pass through the completion queue. The even passes
3875 * will write 1. The odd passes will write 0.
3877 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
3879 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
3880 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
3881 /* 8-lsb timestamp from POR (100-msec resolution) */
3882 uint8_t timestamp_lo;
3883 /* 16-lsb timestamp from POR (100-msec resolution) */
3884 uint16_t timestamp_hi;
3885 /* Event specific data */
3886 uint32_t event_data1;
3888 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
3890 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
3891 } __attribute__((packed));
3893 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
3894 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
3897 * This field indicates the exact type of the completion.
3898 * By convention, the LSB identifies the length of the
3899 * record in 16B units. Even values indicate 16B
3900 * records. Odd values indicate 32B
3903 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
3905 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
3907 /* HWRM Asynchronous Event Information */
3908 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
3910 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
3911 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
3912 /* Identifiers of events. */
3914 /* Function FLR related processing has completed */
3915 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3917 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
3918 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
3919 /* Event specific data */
3920 uint32_t event_data2;
3923 * This value is written by the NIC such that it will be different
3924 * for each pass through the completion queue. The even passes
3925 * will write 1. The odd passes will write 0.
3927 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
3930 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
3932 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
3933 /* 8-lsb timestamp from POR (100-msec resolution) */
3934 uint8_t timestamp_lo;
3935 /* 16-lsb timestamp from POR (100-msec resolution) */
3936 uint16_t timestamp_hi;
3937 /* Event specific data */
3938 uint32_t event_data1;
3940 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
3942 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
3944 } __attribute__((packed));
3946 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
3947 struct hwrm_async_event_cmpl_pf_drvr_unload {
3950 * This field indicates the exact type of the completion.
3951 * By convention, the LSB identifies the length of the
3952 * record in 16B units. Even values indicate 16B
3953 * records. Odd values indicate 32B
3956 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
3958 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
3959 /* HWRM Asynchronous Event Information */
3960 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
3962 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
3963 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
3964 /* Identifiers of events. */
3966 /* PF driver unloaded */
3967 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
3969 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
3970 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
3971 /* Event specific data */
3972 uint32_t event_data2;
3975 * This value is written by the NIC such that it will be different
3976 * for each pass through the completion queue. The even passes
3977 * will write 1. The odd passes will write 0.
3979 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
3981 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
3982 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
3983 /* 8-lsb timestamp from POR (100-msec resolution) */
3984 uint8_t timestamp_lo;
3985 /* 16-lsb timestamp from POR (100-msec resolution) */
3986 uint16_t timestamp_hi;
3987 /* Event specific data */
3988 uint32_t event_data1;
3990 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
3992 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
3993 /* Indicates the physical port this pf belongs to */
3994 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
3996 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
3997 } __attribute__((packed));
3999 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
4000 struct hwrm_async_event_cmpl_pf_drvr_load {
4003 * This field indicates the exact type of the completion.
4004 * By convention, the LSB identifies the length of the
4005 * record in 16B units. Even values indicate 16B
4006 * records. Odd values indicate 32B
4009 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4011 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4012 /* HWRM Asynchronous Event Information */
4013 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4015 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4016 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4017 /* Identifiers of events. */
4019 /* PF driver loaded */
4020 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4022 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4023 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4024 /* Event specific data */
4025 uint32_t event_data2;
4028 * This value is written by the NIC such that it will be different
4029 * for each pass through the completion queue. The even passes
4030 * will write 1. The odd passes will write 0.
4032 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4034 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4035 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4036 /* 8-lsb timestamp from POR (100-msec resolution) */
4037 uint8_t timestamp_lo;
4038 /* 16-lsb timestamp from POR (100-msec resolution) */
4039 uint16_t timestamp_hi;
4040 /* Event specific data */
4041 uint32_t event_data1;
4043 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4045 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4046 /* Indicates the physical port this pf belongs to */
4047 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4049 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4050 } __attribute__((packed));
4052 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4053 struct hwrm_async_event_cmpl_vf_flr {
4056 * This field indicates the exact type of the completion.
4057 * By convention, the LSB identifies the length of the
4058 * record in 16B units. Even values indicate 16B
4059 * records. Odd values indicate 32B
4062 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4064 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4065 /* HWRM Asynchronous Event Information */
4066 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4068 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4069 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4070 /* Identifiers of events. */
4072 /* VF Function Level Reset (FLR) */
4073 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4074 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4075 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4076 /* Event specific data */
4077 uint32_t event_data2;
4080 * This value is written by the NIC such that it will be different
4081 * for each pass through the completion queue. The even passes
4082 * will write 1. The odd passes will write 0.
4084 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4086 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4087 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4088 /* 8-lsb timestamp from POR (100-msec resolution) */
4089 uint8_t timestamp_lo;
4090 /* 16-lsb timestamp from POR (100-msec resolution) */
4091 uint16_t timestamp_hi;
4092 /* Event specific data */
4093 uint32_t event_data1;
4095 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4097 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
4098 /* Indicates the physical function this event occured on. */
4099 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
4101 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
4102 } __attribute__((packed));
4104 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
4105 struct hwrm_async_event_cmpl_vf_mac_addr_change {
4108 * This field indicates the exact type of the completion.
4109 * By convention, the LSB identifies the length of the
4110 * record in 16B units. Even values indicate 16B
4111 * records. Odd values indicate 32B
4114 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
4116 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
4117 /* HWRM Asynchronous Event Information */
4118 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4120 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
4121 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
4122 /* Identifiers of events. */
4124 /* VF MAC Address Change */
4125 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
4127 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
4128 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
4129 /* Event specific data */
4130 uint32_t event_data2;
4133 * This value is written by the NIC such that it will be different
4134 * for each pass through the completion queue. The even passes
4135 * will write 1. The odd passes will write 0.
4137 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
4140 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
4142 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
4143 /* 8-lsb timestamp from POR (100-msec resolution) */
4144 uint8_t timestamp_lo;
4145 /* 16-lsb timestamp from POR (100-msec resolution) */
4146 uint16_t timestamp_hi;
4147 /* Event specific data */
4148 uint32_t event_data1;
4150 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
4152 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
4154 } __attribute__((packed));
4156 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
4157 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
4160 * This field indicates the exact type of the completion.
4161 * By convention, the LSB identifies the length of the
4162 * record in 16B units. Even values indicate 16B
4163 * records. Odd values indicate 32B
4166 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
4168 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
4170 /* HWRM Asynchronous Event Information */
4171 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4173 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
4174 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4175 /* Identifiers of events. */
4177 /* PF-VF communication channel status change. */
4178 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4180 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
4181 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
4182 /* Event specific data */
4183 uint32_t event_data2;
4186 * This value is written by the NIC such that it will be different
4187 * for each pass through the completion queue. The even passes
4188 * will write 1. The odd passes will write 0.
4190 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
4193 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
4195 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
4196 /* 8-lsb timestamp from POR (100-msec resolution) */
4197 uint8_t timestamp_lo;
4198 /* 16-lsb timestamp from POR (100-msec resolution) */
4199 uint16_t timestamp_hi;
4200 /* Event specific data */
4201 uint32_t event_data1;
4203 * If this bit is set to 1, then it indicates that the PF-VF
4204 * communication was lost and it is established.
4205 * If this bit set to 0, then it indicates that the PF-VF
4206 * communication was established and it is lost.
4208 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
4210 } __attribute__((packed));
4212 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
4213 struct hwrm_async_event_cmpl_vf_cfg_change {
4216 * This field indicates the exact type of the completion.
4217 * By convention, the LSB identifies the length of the
4218 * record in 16B units. Even values indicate 16B
4219 * records. Odd values indicate 32B
4222 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
4224 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
4225 /* HWRM Asynchronous Event Information */
4226 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4228 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
4229 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4230 /* Identifiers of events. */
4232 /* VF Configuration Change */
4233 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
4235 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
4236 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
4237 /* Event specific data */
4238 uint32_t event_data2;
4241 * This value is written by the NIC such that it will be different
4242 * for each pass through the completion queue. The even passes
4243 * will write 1. The odd passes will write 0.
4245 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
4247 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
4248 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
4249 /* 8-lsb timestamp from POR (100-msec resolution) */
4250 uint8_t timestamp_lo;
4251 /* 16-lsb timestamp from POR (100-msec resolution) */
4252 uint16_t timestamp_hi;
4254 * Each flag provided in this field indicates a specific VF
4255 * configuration change. At least one of these flags shall be set to 1
4256 * when an asynchronous event completion of this type is provided
4259 uint32_t event_data1;
4261 * If this bit is set to 1, then the value of MTU
4262 * was changed on this VF.
4263 * If set to 0, then this bit should be ignored.
4265 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
4268 * If this bit is set to 1, then the value of MRU
4269 * was changed on this VF.
4270 * If set to 0, then this bit should be ignored.
4272 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
4275 * If this bit is set to 1, then the value of default MAC
4276 * address was changed on this VF.
4277 * If set to 0, then this bit should be ignored.
4279 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
4282 * If this bit is set to 1, then the value of default VLAN
4283 * was changed on this VF.
4284 * If set to 0, then this bit should be ignored.
4286 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
4288 } __attribute__((packed));
4290 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
4291 struct hwrm_async_event_cmpl_llfc_pfc_change {
4294 * This field indicates the exact type of the completion.
4295 * By convention, the LSB identifies the length of the
4296 * record in 16B units. Even values indicate 16B
4297 * records. Odd values indicate 32B
4300 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
4302 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
4303 /* HWRM Asynchronous Event Information */
4304 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4306 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
4307 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4308 /* unused1 is 10 b */
4309 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
4311 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
4312 /* Identifiers of events. */
4314 /* LLFC/PFC Configuration Change */
4315 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
4317 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
4318 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
4319 /* Event specific data */
4320 uint32_t event_data2;
4323 * This value is written by the NIC such that it will be different
4324 * for each pass through the completion queue. The even passes
4325 * will write 1. The odd passes will write 0.
4327 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
4329 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
4331 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
4332 /* 8-lsb timestamp from POR (100-msec resolution) */
4333 uint8_t timestamp_lo;
4334 /* 16-lsb timestamp from POR (100-msec resolution) */
4335 uint16_t timestamp_hi;
4336 /* Event specific data */
4337 uint32_t event_data1;
4338 /* Indicates llfc pfc status change */
4339 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
4341 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
4344 * If this field set to 1, then it indicates that llfc is
4347 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
4350 * If this field is set to 2, then it indicates that pfc
4353 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
4355 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
4356 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
4357 /* Indicates the physical port this llfc pfc change occur */
4358 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
4360 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
4363 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4365 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4367 } __attribute__((packed));
4369 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
4370 struct hwrm_async_event_cmpl_default_vnic_change {
4373 * This field indicates the exact type of the completion.
4374 * By convention, the LSB identifies the length of the
4375 * record in 16B units. Even values indicate 16B
4376 * records. Odd values indicate 32B
4379 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
4381 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
4383 /* HWRM Asynchronous Event Information */
4384 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4386 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
4387 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4388 /* unused1 is 10 b */
4389 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
4391 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
4393 /* Identifiers of events. */
4395 /* Notification of a default vnic allocaiton or free */
4396 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
4398 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
4399 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
4400 /* Event specific data */
4401 uint32_t event_data2;
4404 * This value is written by the NIC such that it will be different
4405 * for each pass through the completion queue. The even passes
4406 * will write 1. The odd passes will write 0.
4408 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
4411 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
4413 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
4414 /* 8-lsb timestamp from POR (100-msec resolution) */
4415 uint8_t timestamp_lo;
4416 /* 16-lsb timestamp from POR (100-msec resolution) */
4417 uint16_t timestamp_hi;
4418 /* Event specific data */
4419 uint32_t event_data1;
4420 /* Indicates default vnic configuration change */
4421 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
4423 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
4426 * If this field is set to 1, then it indicates that
4427 * a default VNIC has been allocate.
4429 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
4432 * If this field is set to 2, then it indicates that
4433 * a default VNIC has been freed.
4435 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
4437 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
4438 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
4439 /* Indicates the physical function this event occured on. */
4440 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
4442 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
4444 /* Indicates the virtual function this event occured on */
4445 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
4447 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
4449 } __attribute__((packed));
4451 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
4452 struct hwrm_async_event_cmpl_hwrm_error {
4455 * This field indicates the exact type of the completion.
4456 * By convention, the LSB identifies the length of the
4457 * record in 16B units. Even values indicate 16B
4458 * records. Odd values indicate 32B
4461 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
4463 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
4464 /* HWRM Asynchronous Event Information */
4465 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
4467 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
4468 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
4469 /* Identifiers of events. */
4472 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
4474 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
4475 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
4476 /* Event specific data */
4477 uint32_t event_data2;
4478 /* Severity of HWRM Error */
4479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
4481 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
4483 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
4485 /* Non-fatal Error */
4486 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
4489 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
4491 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
4492 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
4495 * This value is written by the NIC such that it will be different
4496 * for each pass through the completion queue. The even passes
4497 * will write 1. The odd passes will write 0.
4499 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
4501 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
4502 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
4503 /* 8-lsb timestamp from POR (100-msec resolution) */
4504 uint8_t timestamp_lo;
4505 /* 16-lsb timestamp from POR (100-msec resolution) */
4506 uint16_t timestamp_hi;
4507 /* Event specific data */
4508 uint32_t event_data1;
4509 /* Time stamp for error event */
4510 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
4512 } __attribute__((packed));
4514 /*******************
4516 *******************/
4519 /* hwrm_func_reset_input (size:192b/24B) */
4520 struct hwrm_func_reset_input {
4521 /* The HWRM command request type. */
4524 * The completion ring to send the completion event on. This should
4525 * be the NQ ID returned from the `nq_alloc` HWRM command.
4529 * The sequence ID is used by the driver for tracking multiple
4530 * commands. This ID is treated as opaque data by the firmware and
4531 * the value is returned in the `hwrm_resp_hdr` upon completion.
4535 * The target ID of the command:
4536 * * 0x0-0xFFF8 - The function ID
4537 * * 0xFFF8-0xFFFE - Reserved for internal processors
4542 * A physical address pointer pointing to a host buffer that the
4543 * command's response data will be written. This can be either a host
4544 * physical address (HPA) or a guest physical address (GPA) and must
4545 * point to a physically contiguous block of memory.
4550 * This bit must be '1' for the vf_id_valid field to be
4553 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
4555 * The ID of the VF that this PF is trying to reset.
4556 * Only the parent PF shall be allowed to reset a child VF.
4558 * A parent PF driver shall use this field only when a specific child VF
4559 * is requested to be reset.
4562 /* This value indicates the level of a function reset. */
4563 uint8_t func_reset_level;
4565 * Reset the caller function and its children VFs (if any). If no
4566 * children functions exist, then reset the caller function only.
4568 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
4570 /* Reset the caller function only */
4571 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
4574 * Reset all children VFs of the caller function driver if the
4575 * caller is a PF driver.
4576 * It is an error to specify this level by a VF driver.
4577 * It is an error to specify this level by a PF driver with
4580 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
4583 * Reset a specific VF of the caller function driver if the caller
4584 * is the parent PF driver.
4585 * It is an error to specify this level by a VF driver.
4586 * It is an error to specify this level by a PF driver that is not
4587 * the parent of the VF that is being requested to reset.
4589 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
4591 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
4592 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
4594 } __attribute__((packed));
4596 /* hwrm_func_reset_output (size:128b/16B) */
4597 struct hwrm_func_reset_output {
4598 /* The specific error status for the command. */
4599 uint16_t error_code;
4600 /* The HWRM command request type. */
4602 /* The sequence ID from the original command. */
4604 /* The length of the response data in number of bytes. */
4606 uint8_t unused_0[7];
4608 * This field is used in Output records to indicate that the output
4609 * is completely written to RAM. This field should be read as '1'
4610 * to indicate that the output has been completely written.
4611 * When writing a command completion or response to an internal processor,
4612 * the order of writes has to be such that this field is written last.
4615 } __attribute__((packed));
4617 /********************
4618 * hwrm_func_getfid *
4619 ********************/
4622 /* hwrm_func_getfid_input (size:192b/24B) */
4623 struct hwrm_func_getfid_input {
4624 /* The HWRM command request type. */
4627 * The completion ring to send the completion event on. This should
4628 * be the NQ ID returned from the `nq_alloc` HWRM command.
4632 * The sequence ID is used by the driver for tracking multiple
4633 * commands. This ID is treated as opaque data by the firmware and
4634 * the value is returned in the `hwrm_resp_hdr` upon completion.
4638 * The target ID of the command:
4639 * * 0x0-0xFFF8 - The function ID
4640 * * 0xFFF8-0xFFFE - Reserved for internal processors
4645 * A physical address pointer pointing to a host buffer that the
4646 * command's response data will be written. This can be either a host
4647 * physical address (HPA) or a guest physical address (GPA) and must
4648 * point to a physically contiguous block of memory.
4653 * This bit must be '1' for the pci_id field to be
4656 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
4658 * This value is the PCI ID of the queried function.
4659 * If ARI is enabled, then it is
4660 * Bus Number (8b):Function Number(8b). Otherwise, it is
4661 * Bus Number (8b):Device Number (5b):Function Number(3b).
4664 uint8_t unused_0[2];
4665 } __attribute__((packed));
4667 /* hwrm_func_getfid_output (size:128b/16B) */
4668 struct hwrm_func_getfid_output {
4669 /* The specific error status for the command. */
4670 uint16_t error_code;
4671 /* The HWRM command request type. */
4673 /* The sequence ID from the original command. */
4675 /* The length of the response data in number of bytes. */
4678 * FID value. This value is used to identify operations on the PCI
4679 * bus as belonging to a particular PCI function.
4682 uint8_t unused_0[5];
4684 * This field is used in Output records to indicate that the output
4685 * is completely written to RAM. This field should be read as '1'
4686 * to indicate that the output has been completely written.
4687 * When writing a command completion or response to an internal processor,
4688 * the order of writes has to be such that this field is written last.
4691 } __attribute__((packed));
4693 /**********************
4694 * hwrm_func_vf_alloc *
4695 **********************/
4698 /* hwrm_func_vf_alloc_input (size:192b/24B) */
4699 struct hwrm_func_vf_alloc_input {
4700 /* The HWRM command request type. */
4703 * The completion ring to send the completion event on. This should
4704 * be the NQ ID returned from the `nq_alloc` HWRM command.
4708 * The sequence ID is used by the driver for tracking multiple
4709 * commands. This ID is treated as opaque data by the firmware and
4710 * the value is returned in the `hwrm_resp_hdr` upon completion.
4714 * The target ID of the command:
4715 * * 0x0-0xFFF8 - The function ID
4716 * * 0xFFF8-0xFFFE - Reserved for internal processors
4721 * A physical address pointer pointing to a host buffer that the
4722 * command's response data will be written. This can be either a host
4723 * physical address (HPA) or a guest physical address (GPA) and must
4724 * point to a physically contiguous block of memory.
4729 * This bit must be '1' for the first_vf_id field to be
4732 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
4734 * This value is used to identify a Virtual Function (VF).
4735 * The scope of VF ID is local within a PF.
4737 uint16_t first_vf_id;
4738 /* The number of virtual functions requested. */
4740 } __attribute__((packed));
4742 /* hwrm_func_vf_alloc_output (size:128b/16B) */
4743 struct hwrm_func_vf_alloc_output {
4744 /* The specific error status for the command. */
4745 uint16_t error_code;
4746 /* The HWRM command request type. */
4748 /* The sequence ID from the original command. */
4750 /* The length of the response data in number of bytes. */
4752 /* The ID of the first VF allocated. */
4753 uint16_t first_vf_id;
4754 uint8_t unused_0[5];
4756 * This field is used in Output records to indicate that the output
4757 * is completely written to RAM. This field should be read as '1'
4758 * to indicate that the output has been completely written.
4759 * When writing a command completion or response to an internal processor,
4760 * the order of writes has to be such that this field is written last.
4763 } __attribute__((packed));
4765 /*********************
4766 * hwrm_func_vf_free *
4767 *********************/
4770 /* hwrm_func_vf_free_input (size:192b/24B) */
4771 struct hwrm_func_vf_free_input {
4772 /* The HWRM command request type. */
4775 * The completion ring to send the completion event on. This should
4776 * be the NQ ID returned from the `nq_alloc` HWRM command.
4780 * The sequence ID is used by the driver for tracking multiple
4781 * commands. This ID is treated as opaque data by the firmware and
4782 * the value is returned in the `hwrm_resp_hdr` upon completion.
4786 * The target ID of the command:
4787 * * 0x0-0xFFF8 - The function ID
4788 * * 0xFFF8-0xFFFE - Reserved for internal processors
4793 * A physical address pointer pointing to a host buffer that the
4794 * command's response data will be written. This can be either a host
4795 * physical address (HPA) or a guest physical address (GPA) and must
4796 * point to a physically contiguous block of memory.
4801 * This bit must be '1' for the first_vf_id field to be
4804 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
4806 * This value is used to identify a Virtual Function (VF).
4807 * The scope of VF ID is local within a PF.
4809 uint16_t first_vf_id;
4811 * The number of virtual functions requested.
4812 * 0xFFFF - Cleanup all children of this PF.
4815 } __attribute__((packed));
4817 /* hwrm_func_vf_free_output (size:128b/16B) */
4818 struct hwrm_func_vf_free_output {
4819 /* The specific error status for the command. */
4820 uint16_t error_code;
4821 /* The HWRM command request type. */
4823 /* The sequence ID from the original command. */
4825 /* The length of the response data in number of bytes. */
4827 uint8_t unused_0[7];
4829 * This field is used in Output records to indicate that the output
4830 * is completely written to RAM. This field should be read as '1'
4831 * to indicate that the output has been completely written.
4832 * When writing a command completion or response to an internal processor,
4833 * the order of writes has to be such that this field is written last.
4836 } __attribute__((packed));
4838 /********************
4839 * hwrm_func_vf_cfg *
4840 ********************/
4843 /* hwrm_func_vf_cfg_input (size:448b/56B) */
4844 struct hwrm_func_vf_cfg_input {
4845 /* The HWRM command request type. */
4848 * The completion ring to send the completion event on. This should
4849 * be the NQ ID returned from the `nq_alloc` HWRM command.
4853 * The sequence ID is used by the driver for tracking multiple
4854 * commands. This ID is treated as opaque data by the firmware and
4855 * the value is returned in the `hwrm_resp_hdr` upon completion.
4859 * The target ID of the command:
4860 * * 0x0-0xFFF8 - The function ID
4861 * * 0xFFF8-0xFFFE - Reserved for internal processors
4866 * A physical address pointer pointing to a host buffer that the
4867 * command's response data will be written. This can be either a host
4868 * physical address (HPA) or a guest physical address (GPA) and must
4869 * point to a physically contiguous block of memory.
4874 * This bit must be '1' for the mtu field to be
4877 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
4880 * This bit must be '1' for the guest_vlan field to be
4883 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
4886 * This bit must be '1' for the async_event_cr field to be
4889 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
4892 * This bit must be '1' for the dflt_mac_addr field to be
4895 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
4898 * This bit must be '1' for the num_rsscos_ctxs field to be
4901 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
4904 * This bit must be '1' for the num_cmpl_rings field to be
4907 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
4910 * This bit must be '1' for the num_tx_rings field to be
4913 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
4916 * This bit must be '1' for the num_rx_rings field to be
4919 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
4922 * This bit must be '1' for the num_l2_ctxs field to be
4925 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
4928 * This bit must be '1' for the num_vnics field to be
4931 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
4934 * This bit must be '1' for the num_stat_ctxs field to be
4937 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
4940 * This bit must be '1' for the num_hw_ring_grps field to be
4943 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
4946 * The maximum transmission unit requested on the function.
4947 * The HWRM should make sure that the mtu of
4948 * the function does not exceed the mtu of the physical
4949 * port that this function is associated with.
4951 * In addition to requesting mtu per function, it is
4952 * possible to configure mtu per transmit ring.
4953 * By default, the mtu of each transmit ring associated
4954 * with a function is equal to the mtu of the function.
4955 * The HWRM should make sure that the mtu of each transmit
4956 * ring that is assigned to a function has a valid mtu.
4960 * The guest VLAN for the function being configured.
4961 * This field's format is same as 802.1Q Tag's
4962 * Tag Control Information (TCI) format that includes both
4963 * Priority Code Point (PCP) and VLAN Identifier (VID).
4965 uint16_t guest_vlan;
4967 * ID of the target completion ring for receiving asynchronous
4968 * event completions. If this field is not valid, then the
4969 * HWRM shall use the default completion ring of the function
4970 * that is being configured as the target completion ring for
4971 * providing any asynchronous event completions for that
4973 * If this field is valid, then the HWRM shall use the
4974 * completion ring identified by this ID as the target
4975 * completion ring for providing any asynchronous event
4976 * completions for the function that is being configured.
4978 uint16_t async_event_cr;
4980 * This value is the current MAC address requested by the VF
4981 * driver to be configured on this VF. A value of
4982 * 00-00-00-00-00-00 indicates no MAC address configuration
4983 * is requested by the VF driver.
4984 * The parent PF driver may reject or overwrite this
4987 uint8_t dflt_mac_addr[6];
4990 * This bit requests that the firmware test to see if all the assets
4991 * requested in this command (i.e. number of TX rings) are available.
4992 * The firmware will return an error if the requested assets are
4993 * not available. The firwmare will NOT reserve the assets if they
4996 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
4999 * This bit requests that the firmware test to see if all the assets
5000 * requested in this command (i.e. number of RX rings) are available.
5001 * The firmware will return an error if the requested assets are
5002 * not available. The firwmare will NOT reserve the assets if they
5005 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
5008 * This bit requests that the firmware test to see if all the assets
5009 * requested in this command (i.e. number of CMPL rings) are available.
5010 * The firmware will return an error if the requested assets are
5011 * not available. The firwmare will NOT reserve the assets if they
5014 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
5017 * This bit requests that the firmware test to see if all the assets
5018 * requested in this command (i.e. number of RSS ctx) are available.
5019 * The firmware will return an error if the requested assets are
5020 * not available. The firwmare will NOT reserve the assets if they
5023 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
5026 * This bit requests that the firmware test to see if all the assets
5027 * requested in this command (i.e. number of ring groups) are available.
5028 * The firmware will return an error if the requested assets are
5029 * not available. The firwmare will NOT reserve the assets if they
5032 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
5035 * This bit requests that the firmware test to see if all the assets
5036 * requested in this command (i.e. number of stat ctx) are available.
5037 * The firmware will return an error if the requested assets are
5038 * not available. The firwmare will NOT reserve the assets if they
5041 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
5044 * This bit requests that the firmware test to see if all the assets
5045 * requested in this command (i.e. number of VNICs) are available.
5046 * The firmware will return an error if the requested assets are
5047 * not available. The firwmare will NOT reserve the assets if they
5050 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
5053 * This bit requests that the firmware test to see if all the assets
5054 * requested in this command (i.e. number of L2 ctx) are available.
5055 * The firmware will return an error if the requested assets are
5056 * not available. The firwmare will NOT reserve the assets if they
5059 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
5061 /* The number of RSS/COS contexts requested for the VF. */
5062 uint16_t num_rsscos_ctxs;
5063 /* The number of completion rings requested for the VF. */
5064 uint16_t num_cmpl_rings;
5065 /* The number of transmit rings requested for the VF. */
5066 uint16_t num_tx_rings;
5067 /* The number of receive rings requested for the VF. */
5068 uint16_t num_rx_rings;
5069 /* The number of L2 contexts requested for the VF. */
5070 uint16_t num_l2_ctxs;
5071 /* The number of vnics requested for the VF. */
5073 /* The number of statistic contexts requested for the VF. */
5074 uint16_t num_stat_ctxs;
5075 /* The number of HW ring groups requested for the VF. */
5076 uint16_t num_hw_ring_grps;
5077 uint8_t unused_0[4];
5078 } __attribute__((packed));
5080 /* hwrm_func_vf_cfg_output (size:128b/16B) */
5081 struct hwrm_func_vf_cfg_output {
5082 /* The specific error status for the command. */
5083 uint16_t error_code;
5084 /* The HWRM command request type. */
5086 /* The sequence ID from the original command. */
5088 /* The length of the response data in number of bytes. */
5090 uint8_t unused_0[7];
5092 * This field is used in Output records to indicate that the output
5093 * is completely written to RAM. This field should be read as '1'
5094 * to indicate that the output has been completely written.
5095 * When writing a command completion or response to an internal processor,
5096 * the order of writes has to be such that this field is written last.
5099 } __attribute__((packed));
5101 /*******************
5103 *******************/
5106 /* hwrm_func_qcaps_input (size:192b/24B) */
5107 struct hwrm_func_qcaps_input {
5108 /* The HWRM command request type. */
5111 * The completion ring to send the completion event on. This should
5112 * be the NQ ID returned from the `nq_alloc` HWRM command.
5116 * The sequence ID is used by the driver for tracking multiple
5117 * commands. This ID is treated as opaque data by the firmware and
5118 * the value is returned in the `hwrm_resp_hdr` upon completion.
5122 * The target ID of the command:
5123 * * 0x0-0xFFF8 - The function ID
5124 * * 0xFFF8-0xFFFE - Reserved for internal processors
5129 * A physical address pointer pointing to a host buffer that the
5130 * command's response data will be written. This can be either a host
5131 * physical address (HPA) or a guest physical address (GPA) and must
5132 * point to a physically contiguous block of memory.
5136 * Function ID of the function that is being queried.
5137 * 0xFF... (All Fs) if the query is for the requesting
5141 uint8_t unused_0[6];
5142 } __attribute__((packed));
5144 /* hwrm_func_qcaps_output (size:640b/80B) */
5145 struct hwrm_func_qcaps_output {
5146 /* The specific error status for the command. */
5147 uint16_t error_code;
5148 /* The HWRM command request type. */
5150 /* The sequence ID from the original command. */
5152 /* The length of the response data in number of bytes. */
5155 * FID value. This value is used to identify operations on the PCI
5156 * bus as belonging to a particular PCI function.
5160 * Port ID of port that this function is associated with.
5161 * Valid only for the PF.
5162 * 0xFF... (All Fs) if this function is not associated with
5164 * 0xFF... (All Fs) if this function is called from a VF.
5168 /* If 1, then Push mode is supported on this function. */
5169 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
5172 * If 1, then the global MSI-X auto-masking is enabled for the
5175 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
5178 * If 1, then the Precision Time Protocol (PTP) processing
5179 * is supported on this function.
5180 * The HWRM should enable PTP on only a single Physical
5181 * Function (PF) per port.
5183 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
5186 * If 1, then RDMA over Converged Ethernet (RoCE) v1
5187 * is supported on this function.
5189 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
5192 * If 1, then RDMA over Converged Ethernet (RoCE) v2
5193 * is supported on this function.
5195 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
5198 * If 1, then control and configuration of WoL magic packet
5199 * are supported on this function.
5201 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
5204 * If 1, then control and configuration of bitmap pattern
5205 * packet are supported on this function.
5207 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
5210 * If set to 1, then the control and configuration of rate limit
5211 * of an allocated TX ring on the queried function is supported.
5213 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
5216 * If 1, then control and configuration of minimum and
5217 * maximum bandwidths are supported on the queried function.
5219 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
5222 * If the query is for a VF, then this flag shall be ignored.
5223 * If this query is for a PF and this flag is set to 1,
5224 * then the PF has the capability to set the rate limits
5225 * on the TX rings of its children VFs.
5226 * If this query is for a PF and this flag is set to 0, then
5227 * the PF does not have the capability to set the rate limits
5228 * on the TX rings of its children VFs.
5230 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
5233 * If the query is for a VF, then this flag shall be ignored.
5234 * If this query is for a PF and this flag is set to 1,
5235 * then the PF has the capability to set the minimum and/or
5236 * maximum bandwidths for its children VFs.
5237 * If this query is for a PF and this flag is set to 0, then
5238 * the PF does not have the capability to set the minimum or
5239 * maximum bandwidths for its children VFs.
5241 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
5244 * Standard TX Ring mode is used for the allocation of TX ring
5245 * and underlying scheduling resources that allow bandwidth
5246 * reservation and limit settings on the queried function.
5247 * If set to 1, then standard TX ring mode is supported
5248 * on the queried function.
5249 * If set to 0, then standard TX ring mode is not available
5250 * on the queried function.
5252 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
5255 * If the query is for a VF, then this flag shall be ignored,
5256 * If this query is for a PF and this flag is set to 1,
5257 * then the PF has the capability to detect GENEVE tunnel
5260 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
5263 * If the query is for a VF, then this flag shall be ignored,
5264 * If this query is for a PF and this flag is set to 1,
5265 * then the PF has the capability to detect NVGRE tunnel
5268 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
5271 * If the query is for a VF, then this flag shall be ignored,
5272 * If this query is for a PF and this flag is set to 1,
5273 * then the PF has the capability to detect GRE tunnel
5276 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
5279 * If the query is for a VF, then this flag shall be ignored,
5280 * If this query is for a PF and this flag is set to 1,
5281 * then the PF has the capability to detect MPLS tunnel
5284 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
5287 * If the query is for a VF, then this flag shall be ignored,
5288 * If this query is for a PF and this flag is set to 1,
5289 * then the PF has the capability to support pcie stats.
5291 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
5294 * If the query is for a VF, then this flag shall be ignored,
5295 * If this query is for a PF and this flag is set to 1,
5296 * then the PF has the capability to adopt the VF's belonging
5299 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
5302 * If the query is for a VF, then this flag shall be ignored,
5303 * If this query is for a PF and this flag is set to 1,
5304 * then the PF has the capability to administer another PF.
5306 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
5309 * This value is current MAC address configured for this
5310 * function. A value of 00-00-00-00-00-00 indicates no
5311 * MAC address is currently configured.
5313 uint8_t mac_address[6];
5315 * The maximum number of RSS/COS contexts that can be
5316 * allocated to the function.
5318 uint16_t max_rsscos_ctx;
5320 * The maximum number of completion rings that can be
5321 * allocated to the function.
5323 uint16_t max_cmpl_rings;
5325 * The maximum number of transmit rings that can be
5326 * allocated to the function.
5328 uint16_t max_tx_rings;
5330 * The maximum number of receive rings that can be
5331 * allocated to the function.
5333 uint16_t max_rx_rings;
5335 * The maximum number of L2 contexts that can be
5336 * allocated to the function.
5338 uint16_t max_l2_ctxs;
5340 * The maximum number of VNICs that can be
5341 * allocated to the function.
5345 * The identifier for the first VF enabled on a PF. This
5346 * is valid only on the PF with SR-IOV enabled.
5347 * 0xFF... (All Fs) if this command is called on a PF with
5348 * SR-IOV disabled or on a VF.
5350 uint16_t first_vf_id;
5352 * The maximum number of VFs that can be
5353 * allocated to the function. This is valid only on the
5354 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
5355 * command is called on a PF with SR-IOV disabled or
5360 * The maximum number of statistic contexts that can be
5361 * allocated to the function.
5363 uint16_t max_stat_ctx;
5365 * The maximum number of Encapsulation records that can be
5366 * offloaded by this function.
5368 uint32_t max_encap_records;
5370 * The maximum number of decapsulation records that can
5371 * be offloaded by this function.
5373 uint32_t max_decap_records;
5375 * The maximum number of Exact Match (EM) flows that can be
5376 * offloaded by this function on the TX side.
5378 uint32_t max_tx_em_flows;
5380 * The maximum number of Wildcard Match (WM) flows that can
5381 * be offloaded by this function on the TX side.
5383 uint32_t max_tx_wm_flows;
5385 * The maximum number of Exact Match (EM) flows that can be
5386 * offloaded by this function on the RX side.
5388 uint32_t max_rx_em_flows;
5390 * The maximum number of Wildcard Match (WM) flows that can
5391 * be offloaded by this function on the RX side.
5393 uint32_t max_rx_wm_flows;
5395 * The maximum number of multicast filters that can
5396 * be supported by this function on the RX side.
5398 uint32_t max_mcast_filters;
5400 * The maximum value of flow_id that can be supported
5401 * in completion records.
5403 uint32_t max_flow_id;
5405 * The maximum number of HW ring groups that can be
5406 * supported on this function.
5408 uint32_t max_hw_ring_grps;
5410 * The maximum number of strict priority transmit rings
5411 * that can be allocated to the function.
5412 * This number indicates the maximum number of TX rings
5413 * that can be assigned strict priorities out of the
5414 * maximum number of TX rings that can be allocated
5415 * (max_tx_rings) to the function.
5417 uint16_t max_sp_tx_rings;
5420 * This field is used in Output records to indicate that the output
5421 * is completely written to RAM. This field should be read as '1'
5422 * to indicate that the output has been completely written.
5423 * When writing a command completion or response to an internal processor,
5424 * the order of writes has to be such that this field is written last.
5427 } __attribute__((packed));
5434 /* hwrm_func_qcfg_input (size:192b/24B) */
5435 struct hwrm_func_qcfg_input {
5436 /* The HWRM command request type. */
5439 * The completion ring to send the completion event on. This should
5440 * be the NQ ID returned from the `nq_alloc` HWRM command.
5444 * The sequence ID is used by the driver for tracking multiple
5445 * commands. This ID is treated as opaque data by the firmware and
5446 * the value is returned in the `hwrm_resp_hdr` upon completion.
5450 * The target ID of the command:
5451 * * 0x0-0xFFF8 - The function ID
5452 * * 0xFFF8-0xFFFE - Reserved for internal processors
5457 * A physical address pointer pointing to a host buffer that the
5458 * command's response data will be written. This can be either a host
5459 * physical address (HPA) or a guest physical address (GPA) and must
5460 * point to a physically contiguous block of memory.
5464 * Function ID of the function that is being queried.
5465 * 0xFF... (All Fs) if the query is for the requesting
5469 uint8_t unused_0[6];
5470 } __attribute__((packed));
5472 /* hwrm_func_qcfg_output (size:640b/80B) */
5473 struct hwrm_func_qcfg_output {
5474 /* The specific error status for the command. */
5475 uint16_t error_code;
5476 /* The HWRM command request type. */
5478 /* The sequence ID from the original command. */
5480 /* The length of the response data in number of bytes. */
5483 * FID value. This value is used to identify operations on the PCI
5484 * bus as belonging to a particular PCI function.
5488 * Port ID of port that this function is associated with.
5489 * 0xFF... (All Fs) if this function is not associated with
5494 * This value is the current VLAN setting for this
5495 * function. The value of 0 for this field indicates
5496 * no priority tagging or VLAN is used.
5497 * This field's format is same as 802.1Q Tag's
5498 * Tag Control Information (TCI) format that includes both
5499 * Priority Code Point (PCP) and VLAN Identifier (VID).
5504 * If 1, then magic packet based Out-Of-Box WoL is enabled on
5505 * the port associated with this function.
5507 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
5510 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
5511 * on the port associated with this function.
5513 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
5516 * If set to 1, then FW based DCBX agent is enabled and running on
5517 * the port associated with this function.
5518 * If set to 0, then DCBX agent is not running in the firmware.
5520 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
5523 * Standard TX Ring mode is used for the allocation of TX ring
5524 * and underlying scheduling resources that allow bandwidth
5525 * reservation and limit settings on the queried function.
5526 * If set to 1, then standard TX ring mode is enabled
5527 * on the queried function.
5528 * If set to 0, then the standard TX ring mode is disabled
5529 * on the queried function. In this extended TX ring resource
5530 * mode, the minimum and maximum bandwidth settings are not
5531 * supported to allow the allocation of TX rings to span multiple
5534 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
5537 * If set to 1 then FW based LLDP agent is enabled and running on
5538 * the port associated with this function.
5539 * If set to 0 then the LLDP agent is not running in the firmware.
5541 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
5544 * If set to 1, then multi-host mode is active for this function.
5545 * If set to 0, then multi-host mode is inactive for this function
5546 * or not applicable for this device.
5548 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
5551 * This value is current MAC address configured for this
5552 * function. A value of 00-00-00-00-00-00 indicates no
5553 * MAC address is currently configured.
5555 uint8_t mac_address[6];
5557 * This value is current PCI ID of this
5558 * function. If ARI is enabled, then it is
5559 * Bus Number (8b):Function Number(8b). Otherwise, it is
5560 * Bus Number (8b):Device Number (4b):Function Number(4b).
5561 * If multi-host mode is active, the 4 lsb will indicate
5562 * the PF index for this function.
5566 * The number of RSS/COS contexts currently
5567 * allocated to the function.
5569 uint16_t alloc_rsscos_ctx;
5571 * The number of completion rings currently allocated to
5572 * the function. This does not include the rings allocated
5573 * to any children functions if any.
5575 uint16_t alloc_cmpl_rings;
5577 * The number of transmit rings currently allocated to
5578 * the function. This does not include the rings allocated
5579 * to any children functions if any.
5581 uint16_t alloc_tx_rings;
5583 * The number of receive rings currently allocated to
5584 * the function. This does not include the rings allocated
5585 * to any children functions if any.
5587 uint16_t alloc_rx_rings;
5588 /* The allocated number of L2 contexts to the function. */
5589 uint16_t alloc_l2_ctx;
5590 /* The allocated number of vnics to the function. */
5591 uint16_t alloc_vnics;
5593 * The maximum transmission unit of the function.
5594 * For rings allocated on this function, this default
5595 * value is used if ring MTU is not specified.
5599 * The maximum receive unit of the function.
5600 * For vnics allocated on this function, this default
5601 * value is used if vnic MRU is not specified.
5604 /* The statistics context assigned to a function. */
5605 uint16_t stat_ctx_id;
5607 * The HWRM shall return Unknown value for this field
5608 * when this command is used to query VF's configuration.
5610 uint8_t port_partition_type;
5611 /* Single physical function */
5612 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
5613 /* Multiple physical functions */
5614 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
5615 /* Network Partitioning 1.0 */
5616 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
5617 /* Network Partitioning 1.5 */
5618 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
5619 /* Network Partitioning 2.0 */
5620 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
5622 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
5624 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
5625 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
5627 * This field will indicate number of physical functions on this port_partition.
5628 * HWRM shall return unavail (i.e. value of 0) for this field
5629 * when this command is used to query VF's configuration or
5630 * from older firmware that doesn't support this field.
5632 uint8_t port_pf_cnt;
5633 /* number of PFs is not available */
5634 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
5635 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
5636 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
5638 * The default VNIC ID assigned to a function that is
5641 uint16_t dflt_vnic_id;
5642 uint16_t max_mtu_configured;
5644 * Minimum BW allocated for this function.
5645 * The HWRM will translate this value into byte counter and
5646 * time interval used for the scheduler inside the device.
5647 * A value of 0 indicates the minimum bandwidth is not
5651 /* The bandwidth value. */
5652 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
5654 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
5655 /* The granularity of the value (bits or bytes). */
5656 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
5657 UINT32_C(0x10000000)
5658 /* Value is in bits. */
5659 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
5660 (UINT32_C(0x0) << 28)
5661 /* Value is in bytes. */
5662 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
5663 (UINT32_C(0x1) << 28)
5664 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
5665 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
5666 /* bw_value_unit is 3 b */
5667 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
5668 UINT32_C(0xe0000000)
5669 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
5670 /* Value is in Mb or MB (base 10). */
5671 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
5672 (UINT32_C(0x0) << 29)
5673 /* Value is in Kb or KB (base 10). */
5674 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
5675 (UINT32_C(0x2) << 29)
5676 /* Value is in bits or bytes. */
5677 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
5678 (UINT32_C(0x4) << 29)
5679 /* Value is in Gb or GB (base 10). */
5680 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
5681 (UINT32_C(0x6) << 29)
5682 /* Value is in 1/100th of a percentage of total bandwidth. */
5683 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
5684 (UINT32_C(0x1) << 29)
5686 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
5687 (UINT32_C(0x7) << 29)
5688 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
5689 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
5691 * Maximum BW allocated for this function.
5692 * The HWRM will translate this value into byte counter and
5693 * time interval used for the scheduler inside the device.
5694 * A value of 0 indicates that the maximum bandwidth is not
5698 /* The bandwidth value. */
5699 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
5701 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
5702 /* The granularity of the value (bits or bytes). */
5703 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
5704 UINT32_C(0x10000000)
5705 /* Value is in bits. */
5706 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
5707 (UINT32_C(0x0) << 28)
5708 /* Value is in bytes. */
5709 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
5710 (UINT32_C(0x1) << 28)
5711 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
5712 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
5713 /* bw_value_unit is 3 b */
5714 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
5715 UINT32_C(0xe0000000)
5716 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
5717 /* Value is in Mb or MB (base 10). */
5718 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
5719 (UINT32_C(0x0) << 29)
5720 /* Value is in Kb or KB (base 10). */
5721 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
5722 (UINT32_C(0x2) << 29)
5723 /* Value is in bits or bytes. */
5724 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
5725 (UINT32_C(0x4) << 29)
5726 /* Value is in Gb or GB (base 10). */
5727 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
5728 (UINT32_C(0x6) << 29)
5729 /* Value is in 1/100th of a percentage of total bandwidth. */
5730 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
5731 (UINT32_C(0x1) << 29)
5733 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
5734 (UINT32_C(0x7) << 29)
5735 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
5736 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
5738 * This value indicates the Edge virtual bridge mode for the
5739 * domain that this function belongs to.
5742 /* No Edge Virtual Bridging (EVB) */
5743 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
5744 /* Virtual Ethernet Bridge (VEB) */
5745 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
5746 /* Virtual Ethernet Port Aggregator (VEPA) */
5747 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
5748 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
5749 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
5752 * This value indicates the PCIE device cache line size.
5753 * The cache line size allows the DMA writes to terminate and
5754 * start at the cache boundary.
5756 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
5758 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
5759 /* Cache Line Size 64 bytes */
5760 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
5762 /* Cache Line Size 128 bytes */
5763 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
5765 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
5766 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
5767 /* Reserved for future. */
5768 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
5770 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2
5772 * The number of VFs that are allocated to the function.
5773 * This is valid only on the PF with SR-IOV enabled.
5774 * 0xFF... (All Fs) if this command is called on a PF with
5775 * SR-IOV disabled or on a VF.
5779 * The number of allocated multicast filters for this
5780 * function on the RX side.
5782 uint32_t alloc_mcast_filters;
5784 * The number of allocated HW ring groups for this
5787 uint32_t alloc_hw_ring_grps;
5789 * The number of strict priority transmit rings out of
5790 * currently allocated TX rings to the function
5793 uint16_t alloc_sp_tx_rings;
5795 * The number of statistics contexts
5796 * currently reserved for the function.
5798 uint16_t alloc_stat_ctx;
5800 * This field specifies how many NQs are reserved for the PF.
5801 * Remaining NQs that belong to the PF are available for VFs.
5802 * Once a PF has created VFs, it cannot change how many NQs are
5803 * reserved for itself (since the NQs must be contiguous in HW).
5805 uint16_t alloc_msix;
5806 uint8_t unused_2[5];
5808 * This field is used in Output records to indicate that the output
5809 * is completely written to RAM. This field should be read as '1'
5810 * to indicate that the output has been completely written.
5811 * When writing a command completion or response to an internal processor,
5812 * the order of writes has to be such that this field is written last.
5815 } __attribute__((packed));
5817 /***********************
5818 * hwrm_func_vlan_qcfg *
5819 ***********************/
5822 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
5823 struct hwrm_func_vlan_qcfg_input {
5824 /* The HWRM command request type. */
5827 * The completion ring to send the completion event on. This should
5828 * be the NQ ID returned from the `nq_alloc` HWRM command.
5832 * The sequence ID is used by the driver for tracking multiple
5833 * commands. This ID is treated as opaque data by the firmware and
5834 * the value is returned in the `hwrm_resp_hdr` upon completion.
5838 * The target ID of the command:
5839 * * 0x0-0xFFF8 - The function ID
5840 * * 0xFFF8-0xFFFE - Reserved for internal processors
5845 * A physical address pointer pointing to a host buffer that the
5846 * command's response data will be written. This can be either a host
5847 * physical address (HPA) or a guest physical address (GPA) and must
5848 * point to a physically contiguous block of memory.
5852 * Function ID of the function that is being
5854 * If set to 0xFF... (All Fs), then the configuration is
5855 * for the requesting function.
5858 uint8_t unused_0[6];
5859 } __attribute__((packed));
5861 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
5862 struct hwrm_func_vlan_qcfg_output {
5863 /* The specific error status for the command. */
5864 uint16_t error_code;
5865 /* The HWRM command request type. */
5867 /* The sequence ID from the original command. */
5869 /* The length of the response data in number of bytes. */
5871 uint8_t unused_0[7];
5873 * This field is used in Output records to indicate that the output
5874 * is completely written to RAM. This field should be read as '1'
5875 * to indicate that the output has been completely written.
5876 * When writing a command completion or response to an internal processor,
5877 * the order of writes has to be such that this field is written last.
5880 /* S-TAG VLAN identifier configured for the function. */
5882 /* S-TAG PCP value configured for the function. */
5886 * S-TAG TPID value configured for the function. This field is specified in
5887 * network byte order.
5890 /* C-TAG VLAN identifier configured for the function. */
5892 /* C-TAG PCP value configured for the function. */
5896 * C-TAG TPID value configured for the function. This field is specified in
5897 * network byte order.
5905 } __attribute__((packed));
5907 /**********************
5908 * hwrm_func_vlan_cfg *
5909 **********************/
5912 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
5913 struct hwrm_func_vlan_cfg_input {
5914 /* The HWRM command request type. */
5917 * The completion ring to send the completion event on. This should
5918 * be the NQ ID returned from the `nq_alloc` HWRM command.
5922 * The sequence ID is used by the driver for tracking multiple
5923 * commands. This ID is treated as opaque data by the firmware and
5924 * the value is returned in the `hwrm_resp_hdr` upon completion.
5928 * The target ID of the command:
5929 * * 0x0-0xFFF8 - The function ID
5930 * * 0xFFF8-0xFFFE - Reserved for internal processors
5935 * A physical address pointer pointing to a host buffer that the
5936 * command's response data will be written. This can be either a host
5937 * physical address (HPA) or a guest physical address (GPA) and must
5938 * point to a physically contiguous block of memory.
5942 * Function ID of the function that is being
5944 * If set to 0xFF... (All Fs), then the configuration is
5945 * for the requesting function.
5948 uint8_t unused_0[2];
5951 * This bit must be '1' for the stag_vid field to be
5954 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
5956 * This bit must be '1' for the ctag_vid field to be
5959 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
5961 * This bit must be '1' for the stag_pcp field to be
5964 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
5966 * This bit must be '1' for the ctag_pcp field to be
5969 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
5971 * This bit must be '1' for the stag_tpid field to be
5974 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
5976 * This bit must be '1' for the ctag_tpid field to be
5979 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
5980 /* S-TAG VLAN identifier configured for the function. */
5982 /* S-TAG PCP value configured for the function. */
5986 * S-TAG TPID value configured for the function. This field is specified in
5987 * network byte order.
5990 /* C-TAG VLAN identifier configured for the function. */
5992 /* C-TAG PCP value configured for the function. */
5996 * C-TAG TPID value configured for the function. This field is specified in
5997 * network byte order.
6004 uint8_t unused_3[4];
6005 } __attribute__((packed));
6007 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
6008 struct hwrm_func_vlan_cfg_output {
6009 /* The specific error status for the command. */
6010 uint16_t error_code;
6011 /* The HWRM command request type. */
6013 /* The sequence ID from the original command. */
6015 /* The length of the response data in number of bytes. */
6017 uint8_t unused_0[7];
6019 * This field is used in Output records to indicate that the output
6020 * is completely written to RAM. This field should be read as '1'
6021 * to indicate that the output has been completely written.
6022 * When writing a command completion or response to an internal processor,
6023 * the order of writes has to be such that this field is written last.
6026 } __attribute__((packed));
6033 /* hwrm_func_cfg_input (size:704b/88B) */
6034 struct hwrm_func_cfg_input {
6035 /* The HWRM command request type. */
6038 * The completion ring to send the completion event on. This should
6039 * be the NQ ID returned from the `nq_alloc` HWRM command.
6043 * The sequence ID is used by the driver for tracking multiple
6044 * commands. This ID is treated as opaque data by the firmware and
6045 * the value is returned in the `hwrm_resp_hdr` upon completion.
6049 * The target ID of the command:
6050 * * 0x0-0xFFF8 - The function ID
6051 * * 0xFFF8-0xFFFE - Reserved for internal processors
6056 * A physical address pointer pointing to a host buffer that the
6057 * command's response data will be written. This can be either a host
6058 * physical address (HPA) or a guest physical address (GPA) and must
6059 * point to a physically contiguous block of memory.
6063 * Function ID of the function that is being
6065 * If set to 0xFF... (All Fs), then the the configuration is
6066 * for the requesting function.
6070 * This field specifies how many NQs will be reserved for the PF.
6071 * Remaining NQs that belong to the PF become available for VFs.
6072 * Once a PF has created VFs, it cannot change how many NQs are
6073 * reserved for itself (since the NQs must be contiguous in HW).
6078 * When this bit is '1', the function is disabled with
6079 * source MAC address check.
6080 * This is an anti-spoofing check. If this flag is set,
6081 * then the function shall be configured to disallow
6082 * transmission of frames with the source MAC address that
6083 * is configured for this function.
6085 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
6088 * When this bit is '1', the function is enabled with
6089 * source MAC address check.
6090 * This is an anti-spoofing check. If this flag is set,
6091 * then the function shall be configured to allow
6092 * transmission of frames with the source MAC address that
6093 * is configured for this function.
6095 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
6098 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
6100 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
6102 * Standard TX Ring mode is used for the allocation of TX ring
6103 * and underlying scheduling resources that allow bandwidth
6104 * reservation and limit settings on the queried function.
6105 * If set to 1, then standard TX ring mode is requested to be
6106 * enabled on the function being configured.
6108 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
6111 * Standard TX Ring mode is used for the allocation of TX ring
6112 * and underlying scheduling resources that allow bandwidth
6113 * reservation and limit settings on the queried function.
6114 * If set to 1, then the standard TX ring mode is requested to
6115 * be disabled on the function being configured. In this extended
6116 * TX ring resource mode, the minimum and maximum bandwidth settings
6117 * are not supported to allow the allocation of TX rings to
6118 * span multiple scheduler nodes.
6120 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
6123 * If this bit is set, virtual mac address configured
6124 * in this command will be persistent over warm boot.
6126 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
6129 * This bit only applies to the VF. If this bit is set, the statistic
6130 * context counters will not be cleared when the statistic context is freed
6131 * or a function reset is called on VF. This bit will be cleared when the PF
6132 * is unloaded or a function reset is called on the PF.
6134 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
6137 * This bit requests that the firmware test to see if all the assets
6138 * requested in this command (i.e. number of TX rings) are available.
6139 * The firmware will return an error if the requested assets are
6140 * not available. The firwmare will NOT reserve the assets if they
6143 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6146 * This bit requests that the firmware test to see if all the assets
6147 * requested in this command (i.e. number of RX rings) are available.
6148 * The firmware will return an error if the requested assets are
6149 * not available. The firwmare will NOT reserve the assets if they
6152 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6155 * This bit requests that the firmware test to see if all the assets
6156 * requested in this command (i.e. number of CMPL rings) are available.
6157 * The firmware will return an error if the requested assets are
6158 * not available. The firwmare will NOT reserve the assets if they
6161 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6164 * This bit requests that the firmware test to see if all the assets
6165 * requested in this command (i.e. number of RSS ctx) are available.
6166 * The firmware will return an error if the requested assets are
6167 * not available. The firwmare will NOT reserve the assets if they
6170 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6173 * This bit requests that the firmware test to see if all the assets
6174 * requested in this command (i.e. number of ring groups) are available.
6175 * The firmware will return an error if the requested assets are
6176 * not available. The firwmare will NOT reserve the assets if they
6179 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6182 * This bit requests that the firmware test to see if all the assets
6183 * requested in this command (i.e. number of stat ctx) are available.
6184 * The firmware will return an error if the requested assets are
6185 * not available. The firwmare will NOT reserve the assets if they
6188 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6191 * This bit requests that the firmware test to see if all the assets
6192 * requested in this command (i.e. number of VNICs) are available.
6193 * The firmware will return an error if the requested assets are
6194 * not available. The firwmare will NOT reserve the assets if they
6197 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6200 * This bit requests that the firmware test to see if all the assets
6201 * requested in this command (i.e. number of L2 ctx) are available.
6202 * The firmware will return an error if the requested assets are
6203 * not available. The firwmare will NOT reserve the assets if they
6206 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6210 * This bit must be '1' for the mtu field to be
6213 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
6216 * This bit must be '1' for the mru field to be
6219 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
6222 * This bit must be '1' for the num_rsscos_ctxs field to be
6225 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6228 * This bit must be '1' for the num_cmpl_rings field to be
6231 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6234 * This bit must be '1' for the num_tx_rings field to be
6237 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6240 * This bit must be '1' for the num_rx_rings field to be
6243 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6246 * This bit must be '1' for the num_l2_ctxs field to be
6249 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6252 * This bit must be '1' for the num_vnics field to be
6255 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
6258 * This bit must be '1' for the num_stat_ctxs field to be
6261 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6264 * This bit must be '1' for the dflt_mac_addr field to be
6267 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6270 * This bit must be '1' for the dflt_vlan field to be
6273 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
6276 * This bit must be '1' for the dflt_ip_addr field to be
6279 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
6282 * This bit must be '1' for the min_bw field to be
6285 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
6288 * This bit must be '1' for the max_bw field to be
6291 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
6294 * This bit must be '1' for the async_event_cr field to be
6297 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6300 * This bit must be '1' for the vlan_antispoof_mode field to be
6303 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
6306 * This bit must be '1' for the allowed_vlan_pris field to be
6309 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
6312 * This bit must be '1' for the evb_mode field to be
6315 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
6318 * This bit must be '1' for the num_mcast_filters field to be
6321 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
6324 * This bit must be '1' for the num_hw_ring_grps field to be
6327 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6330 * This bit must be '1' for the cache_linesize field to be
6333 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
6336 * This bit must be '1' for the num_msix field to be
6339 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
6342 * The maximum transmission unit of the function.
6343 * The HWRM should make sure that the mtu of
6344 * the function does not exceed the mtu of the physical
6345 * port that this function is associated with.
6347 * In addition to configuring mtu per function, it is
6348 * possible to configure mtu per transmit ring.
6349 * By default, the mtu of each transmit ring associated
6350 * with a function is equal to the mtu of the function.
6351 * The HWRM should make sure that the mtu of each transmit
6352 * ring that is assigned to a function has a valid mtu.
6356 * The maximum receive unit of the function.
6357 * The HWRM should make sure that the mru of
6358 * the function does not exceed the mru of the physical
6359 * port that this function is associated with.
6361 * In addition to configuring mru per function, it is
6362 * possible to configure mru per vnic.
6363 * By default, the mru of each vnic associated
6364 * with a function is equal to the mru of the function.
6365 * The HWRM should make sure that the mru of each vnic
6366 * that is assigned to a function has a valid mru.
6370 * The number of RSS/COS contexts requested for the
6373 uint16_t num_rsscos_ctxs;
6375 * The number of completion rings requested for the
6376 * function. This does not include the rings allocated
6377 * to any children functions if any.
6379 uint16_t num_cmpl_rings;
6381 * The number of transmit rings requested for the function.
6382 * This does not include the rings allocated to any
6383 * children functions if any.
6385 uint16_t num_tx_rings;
6387 * The number of receive rings requested for the function.
6388 * This does not include the rings allocated
6389 * to any children functions if any.
6391 uint16_t num_rx_rings;
6392 /* The requested number of L2 contexts for the function. */
6393 uint16_t num_l2_ctxs;
6394 /* The requested number of vnics for the function. */
6396 /* The requested number of statistic contexts for the function. */
6397 uint16_t num_stat_ctxs;
6399 * The number of HW ring groups that should
6400 * be reserved for this function.
6402 uint16_t num_hw_ring_grps;
6403 /* The default MAC address for the function being configured. */
6404 uint8_t dflt_mac_addr[6];
6406 * The default VLAN for the function being configured.
6407 * This field's format is same as 802.1Q Tag's
6408 * Tag Control Information (TCI) format that includes both
6409 * Priority Code Point (PCP) and VLAN Identifier (VID).
6413 * The default IP address for the function being configured.
6414 * This address is only used in enabling source property check.
6416 uint32_t dflt_ip_addr[4];
6418 * Minimum BW allocated for this function.
6419 * The HWRM will translate this value into byte counter and
6420 * time interval used for the scheduler inside the device.
6423 /* The bandwidth value. */
6424 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
6426 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
6427 /* The granularity of the value (bits or bytes). */
6428 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
6429 UINT32_C(0x10000000)
6430 /* Value is in bits. */
6431 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
6432 (UINT32_C(0x0) << 28)
6433 /* Value is in bytes. */
6434 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
6435 (UINT32_C(0x1) << 28)
6436 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
6437 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
6438 /* bw_value_unit is 3 b */
6439 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
6440 UINT32_C(0xe0000000)
6441 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6442 /* Value is in Mb or MB (base 10). */
6443 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
6444 (UINT32_C(0x0) << 29)
6445 /* Value is in Kb or KB (base 10). */
6446 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
6447 (UINT32_C(0x2) << 29)
6448 /* Value is in bits or bytes. */
6449 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
6450 (UINT32_C(0x4) << 29)
6451 /* Value is in Gb or GB (base 10). */
6452 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
6453 (UINT32_C(0x6) << 29)
6454 /* Value is in 1/100th of a percentage of total bandwidth. */
6455 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
6456 (UINT32_C(0x1) << 29)
6458 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
6459 (UINT32_C(0x7) << 29)
6460 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
6461 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6463 * Maximum BW allocated for this function.
6464 * The HWRM will translate this value into byte counter and
6465 * time interval used for the scheduler inside the device.
6468 /* The bandwidth value. */
6469 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
6471 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
6472 /* The granularity of the value (bits or bytes). */
6473 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
6474 UINT32_C(0x10000000)
6475 /* Value is in bits. */
6476 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
6477 (UINT32_C(0x0) << 28)
6478 /* Value is in bytes. */
6479 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
6480 (UINT32_C(0x1) << 28)
6481 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
6482 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
6483 /* bw_value_unit is 3 b */
6484 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
6485 UINT32_C(0xe0000000)
6486 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6487 /* Value is in Mb or MB (base 10). */
6488 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
6489 (UINT32_C(0x0) << 29)
6490 /* Value is in Kb or KB (base 10). */
6491 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
6492 (UINT32_C(0x2) << 29)
6493 /* Value is in bits or bytes. */
6494 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
6495 (UINT32_C(0x4) << 29)
6496 /* Value is in Gb or GB (base 10). */
6497 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
6498 (UINT32_C(0x6) << 29)
6499 /* Value is in 1/100th of a percentage of total bandwidth. */
6500 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
6501 (UINT32_C(0x1) << 29)
6503 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
6504 (UINT32_C(0x7) << 29)
6505 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
6506 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6508 * ID of the target completion ring for receiving asynchronous
6509 * event completions. If this field is not valid, then the
6510 * HWRM shall use the default completion ring of the function
6511 * that is being configured as the target completion ring for
6512 * providing any asynchronous event completions for that
6514 * If this field is valid, then the HWRM shall use the
6515 * completion ring identified by this ID as the target
6516 * completion ring for providing any asynchronous event
6517 * completions for the function that is being configured.
6519 uint16_t async_event_cr;
6520 /* VLAN Anti-spoofing mode. */
6521 uint8_t vlan_antispoof_mode;
6522 /* No VLAN anti-spoofing checks are enabled */
6523 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
6525 /* Validate VLAN against the configured VLAN(s) */
6526 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
6528 /* Insert VLAN if it does not exist, otherwise discard */
6529 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
6531 /* Insert VLAN if it does not exist, override VLAN if it exists */
6532 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
6534 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
6535 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
6537 * This bit field defines VLAN PRIs that are allowed on
6539 * If nth bit is set, then VLAN PRI n is allowed on this
6542 uint8_t allowed_vlan_pris;
6544 * The HWRM shall allow a PF driver to change EVB mode for the
6545 * partition it belongs to.
6546 * The HWRM shall not allow a VF driver to change the EVB mode.
6547 * The HWRM shall take into account the switching of EVB mode
6548 * from one to another and reconfigure hardware resources as
6550 * The switching from VEB to VEPA mode requires
6551 * the disabling of the loopback traffic. Additionally,
6552 * source knock outs are handled differently in VEB and VEPA
6556 /* No Edge Virtual Bridging (EVB) */
6557 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6558 /* Virtual Ethernet Bridge (VEB) */
6559 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
6560 /* Virtual Ethernet Port Aggregator (VEPA) */
6561 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
6562 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
6563 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
6566 * This value indicates the PCIE device cache line size.
6567 * The cache line size allows the DMA writes to terminate and
6568 * start at the cache boundary.
6570 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
6572 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
6573 /* Cache Line Size 64 bytes */
6574 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
6576 /* Cache Line Size 128 bytes */
6577 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
6579 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
6580 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
6581 /* Reserved for future. */
6582 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
6584 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2
6586 * The number of multicast filters that should
6587 * be reserved for this function on the RX side.
6589 uint16_t num_mcast_filters;
6590 } __attribute__((packed));
6592 /* hwrm_func_cfg_output (size:128b/16B) */
6593 struct hwrm_func_cfg_output {
6594 /* The specific error status for the command. */
6595 uint16_t error_code;
6596 /* The HWRM command request type. */
6598 /* The sequence ID from the original command. */
6600 /* The length of the response data in number of bytes. */
6602 uint8_t unused_0[7];
6604 * This field is used in Output records to indicate that the output
6605 * is completely written to RAM. This field should be read as '1'
6606 * to indicate that the output has been completely written.
6607 * When writing a command completion or response to an internal processor,
6608 * the order of writes has to be such that this field is written last.
6611 } __attribute__((packed));
6613 /********************
6614 * hwrm_func_qstats *
6615 ********************/
6618 /* hwrm_func_qstats_input (size:192b/24B) */
6619 struct hwrm_func_qstats_input {
6620 /* The HWRM command request type. */
6623 * The completion ring to send the completion event on. This should
6624 * be the NQ ID returned from the `nq_alloc` HWRM command.
6628 * The sequence ID is used by the driver for tracking multiple
6629 * commands. This ID is treated as opaque data by the firmware and
6630 * the value is returned in the `hwrm_resp_hdr` upon completion.
6634 * The target ID of the command:
6635 * * 0x0-0xFFF8 - The function ID
6636 * * 0xFFF8-0xFFFE - Reserved for internal processors
6641 * A physical address pointer pointing to a host buffer that the
6642 * command's response data will be written. This can be either a host
6643 * physical address (HPA) or a guest physical address (GPA) and must
6644 * point to a physically contiguous block of memory.
6648 * Function ID of the function that is being queried.
6649 * 0xFF... (All Fs) if the query is for the requesting
6653 uint8_t unused_0[6];
6654 } __attribute__((packed));
6656 /* hwrm_func_qstats_output (size:1408b/176B) */
6657 struct hwrm_func_qstats_output {
6658 /* The specific error status for the command. */
6659 uint16_t error_code;
6660 /* The HWRM command request type. */
6662 /* The sequence ID from the original command. */
6664 /* The length of the response data in number of bytes. */
6666 /* Number of transmitted unicast packets on the function. */
6667 uint64_t tx_ucast_pkts;
6668 /* Number of transmitted multicast packets on the function. */
6669 uint64_t tx_mcast_pkts;
6670 /* Number of transmitted broadcast packets on the function. */
6671 uint64_t tx_bcast_pkts;
6673 * Number of transmitted packets that were discarded due to
6674 * internal NIC resource problems. For transmit, this
6675 * can only happen if TMP is configured to allow dropping
6676 * in HOL blocking conditions, which is not a normal
6679 uint64_t tx_discard_pkts;
6681 * Number of dropped packets on transmit path on the function.
6682 * These are packets that have been marked for drop by
6683 * the TE CFA block or are packets that exceeded the
6684 * transmit MTU limit for the function.
6686 uint64_t tx_drop_pkts;
6687 /* Number of transmitted bytes for unicast traffic on the function. */
6688 uint64_t tx_ucast_bytes;
6689 /* Number of transmitted bytes for multicast traffic on the function. */
6690 uint64_t tx_mcast_bytes;
6691 /* Number of transmitted bytes for broadcast traffic on the function. */
6692 uint64_t tx_bcast_bytes;
6693 /* Number of received unicast packets on the function. */
6694 uint64_t rx_ucast_pkts;
6695 /* Number of received multicast packets on the function. */
6696 uint64_t rx_mcast_pkts;
6697 /* Number of received broadcast packets on the function. */
6698 uint64_t rx_bcast_pkts;
6700 * Number of received packets that were discarded on the function
6701 * due to resource limitations. This can happen for 3 reasons.
6702 * # The BD used for the packet has a bad format.
6703 * # There were no BDs available in the ring for the packet.
6704 * # There were no BDs available on-chip for the packet.
6706 uint64_t rx_discard_pkts;
6708 * Number of dropped packets on received path on the function.
6709 * These are packets that have been marked for drop by the
6712 uint64_t rx_drop_pkts;
6713 /* Number of received bytes for unicast traffic on the function. */
6714 uint64_t rx_ucast_bytes;
6715 /* Number of received bytes for multicast traffic on the function. */
6716 uint64_t rx_mcast_bytes;
6717 /* Number of received bytes for broadcast traffic on the function. */
6718 uint64_t rx_bcast_bytes;
6719 /* Number of aggregated unicast packets on the function. */
6720 uint64_t rx_agg_pkts;
6721 /* Number of aggregated unicast bytes on the function. */
6722 uint64_t rx_agg_bytes;
6723 /* Number of aggregation events on the function. */
6724 uint64_t rx_agg_events;
6725 /* Number of aborted aggregations on the function. */
6726 uint64_t rx_agg_aborts;
6727 uint8_t unused_0[7];
6729 * This field is used in Output records to indicate that the output
6730 * is completely written to RAM. This field should be read as '1'
6731 * to indicate that the output has been completely written.
6732 * When writing a command completion or response to an internal processor,
6733 * the order of writes has to be such that this field is written last.
6736 } __attribute__((packed));
6738 /***********************
6739 * hwrm_func_clr_stats *
6740 ***********************/
6743 /* hwrm_func_clr_stats_input (size:192b/24B) */
6744 struct hwrm_func_clr_stats_input {
6745 /* The HWRM command request type. */
6748 * The completion ring to send the completion event on. This should
6749 * be the NQ ID returned from the `nq_alloc` HWRM command.
6753 * The sequence ID is used by the driver for tracking multiple
6754 * commands. This ID is treated as opaque data by the firmware and
6755 * the value is returned in the `hwrm_resp_hdr` upon completion.
6759 * The target ID of the command:
6760 * * 0x0-0xFFF8 - The function ID
6761 * * 0xFFF8-0xFFFE - Reserved for internal processors
6766 * A physical address pointer pointing to a host buffer that the
6767 * command's response data will be written. This can be either a host
6768 * physical address (HPA) or a guest physical address (GPA) and must
6769 * point to a physically contiguous block of memory.
6773 * Function ID of the function.
6774 * 0xFF... (All Fs) if the query is for the requesting
6778 uint8_t unused_0[6];
6779 } __attribute__((packed));
6781 /* hwrm_func_clr_stats_output (size:128b/16B) */
6782 struct hwrm_func_clr_stats_output {
6783 /* The specific error status for the command. */
6784 uint16_t error_code;
6785 /* The HWRM command request type. */
6787 /* The sequence ID from the original command. */
6789 /* The length of the response data in number of bytes. */
6791 uint8_t unused_0[7];
6793 * This field is used in Output records to indicate that the output
6794 * is completely written to RAM. This field should be read as '1'
6795 * to indicate that the output has been completely written.
6796 * When writing a command completion or response to an internal processor,
6797 * the order of writes has to be such that this field is written last.
6800 } __attribute__((packed));
6802 /**************************
6803 * hwrm_func_vf_resc_free *
6804 **************************/
6807 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
6808 struct hwrm_func_vf_resc_free_input {
6809 /* The HWRM command request type. */
6812 * The completion ring to send the completion event on. This should
6813 * be the NQ ID returned from the `nq_alloc` HWRM command.
6817 * The sequence ID is used by the driver for tracking multiple
6818 * commands. This ID is treated as opaque data by the firmware and
6819 * the value is returned in the `hwrm_resp_hdr` upon completion.
6823 * The target ID of the command:
6824 * * 0x0-0xFFF8 - The function ID
6825 * * 0xFFF8-0xFFFE - Reserved for internal processors
6830 * A physical address pointer pointing to a host buffer that the
6831 * command's response data will be written. This can be either a host
6832 * physical address (HPA) or a guest physical address (GPA) and must
6833 * point to a physically contiguous block of memory.
6837 * This value is used to identify a Virtual Function (VF).
6838 * The scope of VF ID is local within a PF.
6841 uint8_t unused_0[6];
6842 } __attribute__((packed));
6844 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
6845 struct hwrm_func_vf_resc_free_output {
6846 /* The specific error status for the command. */
6847 uint16_t error_code;
6848 /* The HWRM command request type. */
6850 /* The sequence ID from the original command. */
6852 /* The length of the response data in number of bytes. */
6854 uint8_t unused_0[7];
6856 * This field is used in Output records to indicate that the output
6857 * is completely written to RAM. This field should be read as '1'
6858 * to indicate that the output has been completely written.
6859 * When writing a command completion or response to an internal processor,
6860 * the order of writes has to be such that this field is written last.
6863 } __attribute__((packed));
6865 /*******************************
6866 * hwrm_func_vf_vnic_ids_query *
6867 *******************************/
6870 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
6871 struct hwrm_func_vf_vnic_ids_query_input {
6872 /* The HWRM command request type. */
6875 * The completion ring to send the completion event on. This should
6876 * be the NQ ID returned from the `nq_alloc` HWRM command.
6880 * The sequence ID is used by the driver for tracking multiple
6881 * commands. This ID is treated as opaque data by the firmware and
6882 * the value is returned in the `hwrm_resp_hdr` upon completion.
6886 * The target ID of the command:
6887 * * 0x0-0xFFF8 - The function ID
6888 * * 0xFFF8-0xFFFE - Reserved for internal processors
6893 * A physical address pointer pointing to a host buffer that the
6894 * command's response data will be written. This can be either a host
6895 * physical address (HPA) or a guest physical address (GPA) and must
6896 * point to a physically contiguous block of memory.
6900 * This value is used to identify a Virtual Function (VF).
6901 * The scope of VF ID is local within a PF.
6904 uint8_t unused_0[2];
6905 /* Max number of vnic ids in vnic id table */
6906 uint32_t max_vnic_id_cnt;
6907 /* This is the address for VF VNIC ID table */
6908 uint64_t vnic_id_tbl_addr;
6909 } __attribute__((packed));
6911 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
6912 struct hwrm_func_vf_vnic_ids_query_output {
6913 /* The specific error status for the command. */
6914 uint16_t error_code;
6915 /* The HWRM command request type. */
6917 /* The sequence ID from the original command. */
6919 /* The length of the response data in number of bytes. */
6922 * Actual number of vnic ids
6924 * Each VNIC ID is written as a 32-bit number.
6926 uint32_t vnic_id_cnt;
6927 uint8_t unused_0[3];
6929 * This field is used in Output records to indicate that the output
6930 * is completely written to RAM. This field should be read as '1'
6931 * to indicate that the output has been completely written.
6932 * When writing a command completion or response to an internal processor,
6933 * the order of writes has to be such that this field is written last.
6936 } __attribute__((packed));
6938 /**********************
6939 * hwrm_func_drv_rgtr *
6940 **********************/
6943 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
6944 struct hwrm_func_drv_rgtr_input {
6945 /* The HWRM command request type. */
6948 * The completion ring to send the completion event on. This should
6949 * be the NQ ID returned from the `nq_alloc` HWRM command.
6953 * The sequence ID is used by the driver for tracking multiple
6954 * commands. This ID is treated as opaque data by the firmware and
6955 * the value is returned in the `hwrm_resp_hdr` upon completion.
6959 * The target ID of the command:
6960 * * 0x0-0xFFF8 - The function ID
6961 * * 0xFFF8-0xFFFE - Reserved for internal processors
6966 * A physical address pointer pointing to a host buffer that the
6967 * command's response data will be written. This can be either a host
6968 * physical address (HPA) or a guest physical address (GPA) and must
6969 * point to a physically contiguous block of memory.
6974 * When this bit is '1', the function driver is requesting
6975 * all requests from its children VF drivers to be
6976 * forwarded to itself.
6977 * This flag can only be set by the PF driver.
6978 * If a VF driver sets this flag, it should be ignored
6981 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
6983 * When this bit is '1', the function is requesting none of
6984 * the requests from its children VF drivers to be
6985 * forwarded to itself.
6986 * This flag can only be set by the PF driver.
6987 * If a VF driver sets this flag, it should be ignored
6990 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
6992 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
6993 * fields shall be ignored and ver_maj, ver_min, ver_upd
6994 * and ver_patch shall be used for the driver version information.
6995 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
6996 * fields shall be used for the driver version information and
6997 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
6999 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
7002 * This bit must be '1' for the os_type field to be
7005 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
7008 * This bit must be '1' for the ver field to be
7011 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
7014 * This bit must be '1' for the timestamp field to be
7017 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
7020 * This bit must be '1' for the vf_req_fwd field to be
7023 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
7026 * This bit must be '1' for the async_event_fwd field to be
7029 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
7031 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7034 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7035 /* Other OS not listed below. */
7036 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
7038 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7040 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7042 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7044 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
7046 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7047 /* VMware ESXi OS. */
7048 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
7049 /* Microsoft Windows 8 64-bit OS. */
7050 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7051 /* Microsoft Windows Server 2012 R2 OS. */
7052 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7054 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7055 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
7056 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
7057 /* This is the 8bit major version of the driver. */
7059 /* This is the 8bit minor version of the driver. */
7061 /* This is the 8bit update version of the driver. */
7063 uint8_t unused_0[3];
7065 * This is a 32-bit timestamp provided by the driver for
7067 * The timestamp is in multiples of 1ms.
7070 uint8_t unused_1[4];
7072 * This is a 256-bit bit mask provided by the PF driver for
7073 * letting the HWRM know what commands issued by the VF driver
7074 * to the HWRM should be forwarded to the PF driver.
7075 * Nth bit refers to the Nth req_type.
7077 * Setting Nth bit to 1 indicates that requests from the
7078 * VF driver with req_type equal to N shall be forwarded to
7079 * the parent PF driver.
7081 * This field is not valid for the VF driver.
7083 uint32_t vf_req_fwd[8];
7085 * This is a 256-bit bit mask provided by the function driver
7086 * (PF or VF driver) to indicate the list of asynchronous event
7087 * completions to be forwarded.
7089 * Nth bit refers to the Nth event_id.
7091 * Setting Nth bit to 1 by the function driver shall result in
7092 * the HWRM forwarding asynchronous event completion with
7093 * event_id equal to N.
7095 * If all bits are set to 0 (value of 0), then the HWRM shall
7096 * not forward any asynchronous event completion to this
7099 uint32_t async_event_fwd[8];
7100 /* This is the 16bit major version of the driver. */
7102 /* This is the 16bit minor version of the driver. */
7104 /* This is the 16bit update version of the driver. */
7106 /* This is the 16bit patch version of the driver. */
7108 } __attribute__((packed));
7110 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
7111 struct hwrm_func_drv_rgtr_output {
7112 /* The specific error status for the command. */
7113 uint16_t error_code;
7114 /* The HWRM command request type. */
7116 /* The sequence ID from the original command. */
7118 /* The length of the response data in number of bytes. */
7120 uint8_t unused_0[7];
7122 * This field is used in Output records to indicate that the output
7123 * is completely written to RAM. This field should be read as '1'
7124 * to indicate that the output has been completely written.
7125 * When writing a command completion or response to an internal processor,
7126 * the order of writes has to be such that this field is written last.
7129 } __attribute__((packed));
7131 /************************
7132 * hwrm_func_drv_unrgtr *
7133 ************************/
7136 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
7137 struct hwrm_func_drv_unrgtr_input {
7138 /* The HWRM command request type. */
7141 * The completion ring to send the completion event on. This should
7142 * be the NQ ID returned from the `nq_alloc` HWRM command.
7146 * The sequence ID is used by the driver for tracking multiple
7147 * commands. This ID is treated as opaque data by the firmware and
7148 * the value is returned in the `hwrm_resp_hdr` upon completion.
7152 * The target ID of the command:
7153 * * 0x0-0xFFF8 - The function ID
7154 * * 0xFFF8-0xFFFE - Reserved for internal processors
7159 * A physical address pointer pointing to a host buffer that the
7160 * command's response data will be written. This can be either a host
7161 * physical address (HPA) or a guest physical address (GPA) and must
7162 * point to a physically contiguous block of memory.
7167 * When this bit is '1', the function driver is notifying
7168 * the HWRM to prepare for the shutdown.
7170 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
7172 uint8_t unused_0[4];
7173 } __attribute__((packed));
7175 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
7176 struct hwrm_func_drv_unrgtr_output {
7177 /* The specific error status for the command. */
7178 uint16_t error_code;
7179 /* The HWRM command request type. */
7181 /* The sequence ID from the original command. */
7183 /* The length of the response data in number of bytes. */
7185 uint8_t unused_0[7];
7187 * This field is used in Output records to indicate that the output
7188 * is completely written to RAM. This field should be read as '1'
7189 * to indicate that the output has been completely written.
7190 * When writing a command completion or response to an internal processor,
7191 * the order of writes has to be such that this field is written last.
7194 } __attribute__((packed));
7196 /**********************
7197 * hwrm_func_buf_rgtr *
7198 **********************/
7201 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
7202 struct hwrm_func_buf_rgtr_input {
7203 /* The HWRM command request type. */
7206 * The completion ring to send the completion event on. This should
7207 * be the NQ ID returned from the `nq_alloc` HWRM command.
7211 * The sequence ID is used by the driver for tracking multiple
7212 * commands. This ID is treated as opaque data by the firmware and
7213 * the value is returned in the `hwrm_resp_hdr` upon completion.
7217 * The target ID of the command:
7218 * * 0x0-0xFFF8 - The function ID
7219 * * 0xFFF8-0xFFFE - Reserved for internal processors
7224 * A physical address pointer pointing to a host buffer that the
7225 * command's response data will be written. This can be either a host
7226 * physical address (HPA) or a guest physical address (GPA) and must
7227 * point to a physically contiguous block of memory.
7232 * This bit must be '1' for the vf_id field to be
7235 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7237 * This bit must be '1' for the err_buf_addr field to be
7240 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
7242 * This value is used to identify a Virtual Function (VF).
7243 * The scope of VF ID is local within a PF.
7247 * This field represents the number of pages used for request
7250 uint16_t req_buf_num_pages;
7252 * This field represents the page size used for request
7255 uint16_t req_buf_page_size;
7257 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
7259 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
7261 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
7263 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
7265 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
7267 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
7269 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
7270 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
7271 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
7272 /* The length of the request buffer per VF in bytes. */
7273 uint16_t req_buf_len;
7274 /* The length of the response buffer in bytes. */
7275 uint16_t resp_buf_len;
7276 uint8_t unused_0[2];
7277 /* This field represents the page address of page #0. */
7278 uint64_t req_buf_page_addr0;
7279 /* This field represents the page address of page #1. */
7280 uint64_t req_buf_page_addr1;
7281 /* This field represents the page address of page #2. */
7282 uint64_t req_buf_page_addr2;
7283 /* This field represents the page address of page #3. */
7284 uint64_t req_buf_page_addr3;
7285 /* This field represents the page address of page #4. */
7286 uint64_t req_buf_page_addr4;
7287 /* This field represents the page address of page #5. */
7288 uint64_t req_buf_page_addr5;
7289 /* This field represents the page address of page #6. */
7290 uint64_t req_buf_page_addr6;
7291 /* This field represents the page address of page #7. */
7292 uint64_t req_buf_page_addr7;
7293 /* This field represents the page address of page #8. */
7294 uint64_t req_buf_page_addr8;
7295 /* This field represents the page address of page #9. */
7296 uint64_t req_buf_page_addr9;
7298 * This field is used to receive the error reporting from
7299 * the chipset. Only applicable for PFs.
7301 uint64_t error_buf_addr;
7303 * This field is used to receive the response forwarded by the
7306 uint64_t resp_buf_addr;
7307 } __attribute__((packed));
7309 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
7310 struct hwrm_func_buf_rgtr_output {
7311 /* The specific error status for the command. */
7312 uint16_t error_code;
7313 /* The HWRM command request type. */
7315 /* The sequence ID from the original command. */
7317 /* The length of the response data in number of bytes. */
7319 uint8_t unused_0[7];
7321 * This field is used in Output records to indicate that the output
7322 * is completely written to RAM. This field should be read as '1'
7323 * to indicate that the output has been completely written.
7324 * When writing a command completion or response to an internal processor,
7325 * the order of writes has to be such that this field is written last.
7328 } __attribute__((packed));
7330 /************************
7331 * hwrm_func_buf_unrgtr *
7332 ************************/
7335 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
7336 struct hwrm_func_buf_unrgtr_input {
7337 /* The HWRM command request type. */
7340 * The completion ring to send the completion event on. This should
7341 * be the NQ ID returned from the `nq_alloc` HWRM command.
7345 * The sequence ID is used by the driver for tracking multiple
7346 * commands. This ID is treated as opaque data by the firmware and
7347 * the value is returned in the `hwrm_resp_hdr` upon completion.
7351 * The target ID of the command:
7352 * * 0x0-0xFFF8 - The function ID
7353 * * 0xFFF8-0xFFFE - Reserved for internal processors
7358 * A physical address pointer pointing to a host buffer that the
7359 * command's response data will be written. This can be either a host
7360 * physical address (HPA) or a guest physical address (GPA) and must
7361 * point to a physically contiguous block of memory.
7366 * This bit must be '1' for the vf_id field to be
7369 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7371 * This value is used to identify a Virtual Function (VF).
7372 * The scope of VF ID is local within a PF.
7375 uint8_t unused_0[2];
7376 } __attribute__((packed));
7378 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
7379 struct hwrm_func_buf_unrgtr_output {
7380 /* The specific error status for the command. */
7381 uint16_t error_code;
7382 /* The HWRM command request type. */
7384 /* The sequence ID from the original command. */
7386 /* The length of the response data in number of bytes. */
7388 uint8_t unused_0[7];
7390 * This field is used in Output records to indicate that the output
7391 * is completely written to RAM. This field should be read as '1'
7392 * to indicate that the output has been completely written.
7393 * When writing a command completion or response to an internal processor,
7394 * the order of writes has to be such that this field is written last.
7397 } __attribute__((packed));
7399 /**********************
7400 * hwrm_func_drv_qver *
7401 **********************/
7404 /* hwrm_func_drv_qver_input (size:192b/24B) */
7405 struct hwrm_func_drv_qver_input {
7406 /* The HWRM command request type. */
7409 * The completion ring to send the completion event on. This should
7410 * be the NQ ID returned from the `nq_alloc` HWRM command.
7414 * The sequence ID is used by the driver for tracking multiple
7415 * commands. This ID is treated as opaque data by the firmware and
7416 * the value is returned in the `hwrm_resp_hdr` upon completion.
7420 * The target ID of the command:
7421 * * 0x0-0xFFF8 - The function ID
7422 * * 0xFFF8-0xFFFE - Reserved for internal processors
7427 * A physical address pointer pointing to a host buffer that the
7428 * command's response data will be written. This can be either a host
7429 * physical address (HPA) or a guest physical address (GPA) and must
7430 * point to a physically contiguous block of memory.
7433 /* Reserved for future use. */
7436 * Function ID of the function that is being queried.
7437 * 0xFF... (All Fs) if the query is for the requesting
7441 uint8_t unused_0[2];
7442 } __attribute__((packed));
7444 /* hwrm_func_drv_qver_output (size:192b/24B) */
7445 struct hwrm_func_drv_qver_output {
7446 /* The specific error status for the command. */
7447 uint16_t error_code;
7448 /* The HWRM command request type. */
7450 /* The sequence ID from the original command. */
7452 /* The length of the response data in number of bytes. */
7454 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7457 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7458 /* Other OS not listed below. */
7459 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
7461 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7463 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7465 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7467 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
7469 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7470 /* VMware ESXi OS. */
7471 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
7472 /* Microsoft Windows 8 64-bit OS. */
7473 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7474 /* Microsoft Windows Server 2012 R2 OS. */
7475 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7477 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7478 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
7479 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
7480 /* This is the 8bit major version of the driver. */
7482 /* This is the 8bit minor version of the driver. */
7484 /* This is the 8bit update version of the driver. */
7486 uint8_t unused_0[2];
7488 * This field is used in Output records to indicate that the output
7489 * is completely written to RAM. This field should be read as '1'
7490 * to indicate that the output has been completely written.
7491 * When writing a command completion or response to an internal processor,
7492 * the order of writes has to be such that this field is written last.
7495 /* This is the 16bit major version of the driver. */
7497 /* This is the 16bit minor version of the driver. */
7499 /* This is the 16bit update version of the driver. */
7501 /* This is the 16bit patch version of the driver. */
7503 } __attribute__((packed));
7505 /****************************
7506 * hwrm_func_resource_qcaps *
7507 ****************************/
7510 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
7511 struct hwrm_func_resource_qcaps_input {
7512 /* The HWRM command request type. */
7515 * The completion ring to send the completion event on. This should
7516 * be the NQ ID returned from the `nq_alloc` HWRM command.
7520 * The sequence ID is used by the driver for tracking multiple
7521 * commands. This ID is treated as opaque data by the firmware and
7522 * the value is returned in the `hwrm_resp_hdr` upon completion.
7526 * The target ID of the command:
7527 * * 0x0-0xFFF8 - The function ID
7528 * * 0xFFF8-0xFFFE - Reserved for internal processors
7533 * A physical address pointer pointing to a host buffer that the
7534 * command's response data will be written. This can be either a host
7535 * physical address (HPA) or a guest physical address (GPA) and must
7536 * point to a physically contiguous block of memory.
7540 * Function ID of the function that is being queried.
7541 * 0xFF... (All Fs) if the query is for the requesting
7545 uint8_t unused_0[6];
7546 } __attribute__((packed));
7548 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
7549 struct hwrm_func_resource_qcaps_output {
7550 /* The specific error status for the command. */
7551 uint16_t error_code;
7552 /* The HWRM command request type. */
7554 /* The sequence ID from the original command. */
7556 /* The length of the response data in number of bytes. */
7558 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
7560 /* Maximum guaranteed number of MSI-X vectors supported by function */
7562 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
7563 uint16_t vf_reservation_strategy;
7564 /* The PF driver should evenly divide its remaining resources among all VFs. */
7565 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
7567 /* The PF driver should only reserve minimal resources for each VF. */
7568 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
7571 * The PF driver should not reserve any resources for each VF until the
7572 * the VF interface is brought up.
7574 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
7576 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
7577 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
7578 /* Minimum guaranteed number of RSS/COS contexts */
7579 uint16_t min_rsscos_ctx;
7580 /* Maximum non-guaranteed number of RSS/COS contexts */
7581 uint16_t max_rsscos_ctx;
7582 /* Minimum guaranteed number of completion rings */
7583 uint16_t min_cmpl_rings;
7584 /* Maximum non-guaranteed number of completion rings */
7585 uint16_t max_cmpl_rings;
7586 /* Minimum guaranteed number of transmit rings */
7587 uint16_t min_tx_rings;
7588 /* Maximum non-guaranteed number of transmit rings */
7589 uint16_t max_tx_rings;
7590 /* Minimum guaranteed number of receive rings */
7591 uint16_t min_rx_rings;
7592 /* Maximum non-guaranteed number of receive rings */
7593 uint16_t max_rx_rings;
7594 /* Minimum guaranteed number of L2 contexts */
7595 uint16_t min_l2_ctxs;
7596 /* Maximum non-guaranteed number of L2 contexts */
7597 uint16_t max_l2_ctxs;
7598 /* Minimum guaranteed number of VNICs */
7600 /* Maximum non-guaranteed number of VNICs */
7602 /* Minimum guaranteed number of statistic contexts */
7603 uint16_t min_stat_ctx;
7604 /* Maximum non-guaranteed number of statistic contexts */
7605 uint16_t max_stat_ctx;
7606 /* Minimum guaranteed number of ring groups */
7607 uint16_t min_hw_ring_grps;
7608 /* Maximum non-guaranteed number of ring groups */
7609 uint16_t max_hw_ring_grps;
7611 * Maximum number of inputs into the transmit scheduler for this function.
7612 * The number of TX rings assigned to the function cannot exceed this value.
7614 uint16_t max_tx_scheduler_inputs;
7615 uint8_t unused_0[7];
7617 * This field is used in Output records to indicate that the output
7618 * is completely written to RAM. This field should be read as '1'
7619 * to indicate that the output has been completely written.
7620 * When writing a command completion or response to an internal processor,
7621 * the order of writes has to be such that this field is written last.
7624 } __attribute__((packed));
7626 /*****************************
7627 * hwrm_func_vf_resource_cfg *
7628 *****************************/
7631 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
7632 struct hwrm_func_vf_resource_cfg_input {
7633 /* The HWRM command request type. */
7636 * The completion ring to send the completion event on. This should
7637 * be the NQ ID returned from the `nq_alloc` HWRM command.
7641 * The sequence ID is used by the driver for tracking multiple
7642 * commands. This ID is treated as opaque data by the firmware and
7643 * the value is returned in the `hwrm_resp_hdr` upon completion.
7647 * The target ID of the command:
7648 * * 0x0-0xFFF8 - The function ID
7649 * * 0xFFF8-0xFFFE - Reserved for internal processors
7654 * A physical address pointer pointing to a host buffer that the
7655 * command's response data will be written. This can be either a host
7656 * physical address (HPA) or a guest physical address (GPA) and must
7657 * point to a physically contiguous block of memory.
7660 /* VF ID that is being configured by PF */
7662 /* Maximum guaranteed number of MSI-X vectors for the function */
7664 /* Minimum guaranteed number of RSS/COS contexts */
7665 uint16_t min_rsscos_ctx;
7666 /* Maximum non-guaranteed number of RSS/COS contexts */
7667 uint16_t max_rsscos_ctx;
7668 /* Minimum guaranteed number of completion rings */
7669 uint16_t min_cmpl_rings;
7670 /* Maximum non-guaranteed number of completion rings */
7671 uint16_t max_cmpl_rings;
7672 /* Minimum guaranteed number of transmit rings */
7673 uint16_t min_tx_rings;
7674 /* Maximum non-guaranteed number of transmit rings */
7675 uint16_t max_tx_rings;
7676 /* Minimum guaranteed number of receive rings */
7677 uint16_t min_rx_rings;
7678 /* Maximum non-guaranteed number of receive rings */
7679 uint16_t max_rx_rings;
7680 /* Minimum guaranteed number of L2 contexts */
7681 uint16_t min_l2_ctxs;
7682 /* Maximum non-guaranteed number of L2 contexts */
7683 uint16_t max_l2_ctxs;
7684 /* Minimum guaranteed number of VNICs */
7686 /* Maximum non-guaranteed number of VNICs */
7688 /* Minimum guaranteed number of statistic contexts */
7689 uint16_t min_stat_ctx;
7690 /* Maximum non-guaranteed number of statistic contexts */
7691 uint16_t max_stat_ctx;
7692 /* Minimum guaranteed number of ring groups */
7693 uint16_t min_hw_ring_grps;
7694 /* Maximum non-guaranteed number of ring groups */
7695 uint16_t max_hw_ring_grps;
7696 uint8_t unused_0[4];
7697 } __attribute__((packed));
7699 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
7700 struct hwrm_func_vf_resource_cfg_output {
7701 /* The specific error status for the command. */
7702 uint16_t error_code;
7703 /* The HWRM command request type. */
7705 /* The sequence ID from the original command. */
7707 /* The length of the response data in number of bytes. */
7709 /* Reserved number of RSS/COS contexts */
7710 uint16_t reserved_rsscos_ctx;
7711 /* Reserved number of completion rings */
7712 uint16_t reserved_cmpl_rings;
7713 /* Reserved number of transmit rings */
7714 uint16_t reserved_tx_rings;
7715 /* Reserved number of receive rings */
7716 uint16_t reserved_rx_rings;
7717 /* Reserved number of L2 contexts */
7718 uint16_t reserved_l2_ctxs;
7719 /* Reserved number of VNICs */
7720 uint16_t reserved_vnics;
7721 /* Reserved number of statistic contexts */
7722 uint16_t reserved_stat_ctx;
7723 /* Reserved number of ring groups */
7724 uint16_t reserved_hw_ring_grps;
7725 uint8_t unused_0[7];
7727 * This field is used in Output records to indicate that the output
7728 * is completely written to RAM. This field should be read as '1'
7729 * to indicate that the output has been completely written.
7730 * When writing a command completion or response to an internal processor,
7731 * the order of writes has to be such that this field is written last.
7734 } __attribute__((packed));
7736 /*********************************
7737 * hwrm_func_backing_store_qcaps *
7738 *********************************/
7741 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
7742 struct hwrm_func_backing_store_qcaps_input {
7743 /* The HWRM command request type. */
7746 * The completion ring to send the completion event on. This should
7747 * be the NQ ID returned from the `nq_alloc` HWRM command.
7751 * The sequence ID is used by the driver for tracking multiple
7752 * commands. This ID is treated as opaque data by the firmware and
7753 * the value is returned in the `hwrm_resp_hdr` upon completion.
7757 * The target ID of the command:
7758 * * 0x0-0xFFF8 - The function ID
7759 * * 0xFFF8-0xFFFE - Reserved for internal processors
7764 * A physical address pointer pointing to a host buffer that the
7765 * command's response data will be written. This can be either a host
7766 * physical address (HPA) or a guest physical address (GPA) and must
7767 * point to a physically contiguous block of memory.
7770 } __attribute__((packed));
7772 /* hwrm_func_backing_store_qcaps_output (size:512b/64B) */
7773 struct hwrm_func_backing_store_qcaps_output {
7774 /* The specific error status for the command. */
7775 uint16_t error_code;
7776 /* The HWRM command request type. */
7778 /* The sequence ID from the original command. */
7780 /* The length of the response data in number of bytes. */
7782 /* Maximum number of QP context entries supported for this function. */
7783 uint32_t qp_max_entries;
7785 * Minimum number of QP context entries that are needed to be reserved
7786 * for QP1 for the PF and its VFs. PF drivers must allocate at least
7787 * this many QP context entries, even if RoCE will not be used.
7789 uint16_t qp_min_qp1_entries;
7790 /* Maximum number of QP context entries that can be used for L2. */
7791 uint16_t qp_max_l2_entries;
7792 /* Number of bytes that must be allocated for each context entry. */
7793 uint16_t qp_entry_size;
7794 /* Maximum number of SRQ context entries that can be used for L2. */
7795 uint16_t srq_max_l2_entries;
7796 /* Maximum number of SRQ context entries supported for this function. */
7797 uint32_t srq_max_entries;
7798 /* Number of bytes that must be allocated for each context entry. */
7799 uint16_t srq_entry_size;
7800 /* Maximum number of CQ context entries that can be used for L2. */
7801 uint16_t cq_max_l2_entries;
7802 /* Maximum number of CQ context entries supported for this function. */
7803 uint32_t cq_max_entries;
7804 /* Number of bytes that must be allocated for each context entry. */
7805 uint16_t cq_entry_size;
7806 /* Maximum number of VNIC context entries supported for this function. */
7807 uint16_t vnic_max_vnic_entries;
7808 /* Maximum number of Ring table context entries supported for this function. */
7809 uint16_t vnic_max_ring_table_entries;
7810 /* Number of bytes that must be allocated for each context entry. */
7811 uint16_t vnic_entry_size;
7812 /* Maximum number of statistic context entries supported for this function. */
7813 uint32_t stat_max_entries;
7814 /* Number of bytes that must be allocated for each context entry. */
7815 uint16_t stat_entry_size;
7816 /* Maximum number of TQM context entries supported per ring. */
7817 uint16_t tqm_max_entries_per_ring;
7818 /* Number of bytes that must be allocated for each context entry. */
7819 uint16_t tqm_entry_size;
7820 /* Number of bytes that must be allocated for each context entry. */
7821 uint16_t mrav_entry_size;
7822 /* Maximum number of MR/AV context entries supported for this function. */
7823 uint32_t mrav_max_entries;
7824 /* Maximum number of Timer context entries supported for this function. */
7825 uint32_t tim_max_entries;
7826 /* Number of bytes that must be allocated for each context entry. */
7827 uint16_t tim_entry_size;
7830 * This field is used in Output records to indicate that the output
7831 * is completely written to RAM. This field should be read as '1'
7832 * to indicate that the output has been completely written.
7833 * When writing a command completion or response to an internal processor,
7834 * the order of writes has to be such that this field is written last.
7837 } __attribute__((packed));
7839 /*******************************
7840 * hwrm_func_backing_store_cfg *
7841 *******************************/
7844 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
7845 struct hwrm_func_backing_store_cfg_input {
7846 /* The HWRM command request type. */
7849 * The completion ring to send the completion event on. This should
7850 * be the NQ ID returned from the `nq_alloc` HWRM command.
7854 * The sequence ID is used by the driver for tracking multiple
7855 * commands. This ID is treated as opaque data by the firmware and
7856 * the value is returned in the `hwrm_resp_hdr` upon completion.
7860 * The target ID of the command:
7861 * * 0x0-0xFFF8 - The function ID
7862 * * 0xFFF8-0xFFFE - Reserved for internal processors
7867 * A physical address pointer pointing to a host buffer that the
7868 * command's response data will be written. This can be either a host
7869 * physical address (HPA) or a guest physical address (GPA) and must
7870 * point to a physically contiguous block of memory.
7875 * When set, the firmware only uses on-chip resources and does not
7876 * expect any backing store to be provided by the host driver. This
7877 * mode provides minimal L2 functionality (e.g. limited L2 resources,
7880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
7884 * This bit must be '1' for the qp fields to be
7887 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
7890 * This bit must be '1' for the srq fields to be
7893 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
7896 * This bit must be '1' for the cq fields to be
7899 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
7902 * This bit must be '1' for the vnic fields to be
7905 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
7908 * This bit must be '1' for the stat fields to be
7911 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
7914 * This bit must be '1' for the tqm_sp fields to be
7917 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
7920 * This bit must be '1' for the tqm_ring0 fields to be
7923 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
7926 * This bit must be '1' for the tqm_ring1 fields to be
7929 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
7932 * This bit must be '1' for the tqm_ring2 fields to be
7935 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
7938 * This bit must be '1' for the tqm_ring3 fields to be
7941 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
7944 * This bit must be '1' for the tqm_ring4 fields to be
7947 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
7950 * This bit must be '1' for the tqm_ring5 fields to be
7953 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
7956 * This bit must be '1' for the tqm_ring6 fields to be
7959 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
7962 * This bit must be '1' for the tqm_ring7 fields to be
7965 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
7968 * This bit must be '1' for the mrav fields to be
7971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
7974 * This bit must be '1' for the tim fields to be
7977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
7979 /* QPC page size and level. */
7980 uint8_t qpc_pg_size_qpc_lvl;
7981 /* QPC PBL indirect levels. */
7982 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
7984 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
7985 /* PBL pointer is physical start address. */
7986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
7988 /* PBL pointer points to PTE table. */
7989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
7991 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
7994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
7995 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
7996 /* QPC page size. */
7997 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
7999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
8001 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
8002 (UINT32_C(0x0) << 4)
8004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
8005 (UINT32_C(0x1) << 4)
8007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
8008 (UINT32_C(0x2) << 4)
8010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
8011 (UINT32_C(0x3) << 4)
8013 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
8014 (UINT32_C(0x4) << 4)
8016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
8017 (UINT32_C(0x5) << 4)
8018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
8019 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
8020 /* SRQ page size and level. */
8021 uint8_t srq_pg_size_srq_lvl;
8022 /* SRQ PBL indirect levels. */
8023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
8025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
8026 /* PBL pointer is physical start address. */
8027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
8029 /* PBL pointer points to PTE table. */
8030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
8032 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
8035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
8036 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
8037 /* SRQ page size. */
8038 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
8040 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
8042 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
8043 (UINT32_C(0x0) << 4)
8045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
8046 (UINT32_C(0x1) << 4)
8048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
8049 (UINT32_C(0x2) << 4)
8051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
8052 (UINT32_C(0x3) << 4)
8054 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
8055 (UINT32_C(0x4) << 4)
8057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
8058 (UINT32_C(0x5) << 4)
8059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
8060 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
8061 /* CQ page size and level. */
8062 uint8_t cq_pg_size_cq_lvl;
8063 /* CQ PBL indirect levels. */
8064 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
8066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
8067 /* PBL pointer is physical start address. */
8068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
8070 /* PBL pointer points to PTE table. */
8071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
8073 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
8076 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
8077 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
8079 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
8081 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
8083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
8084 (UINT32_C(0x0) << 4)
8086 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
8087 (UINT32_C(0x1) << 4)
8089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
8090 (UINT32_C(0x2) << 4)
8092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
8093 (UINT32_C(0x3) << 4)
8095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
8096 (UINT32_C(0x4) << 4)
8098 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
8099 (UINT32_C(0x5) << 4)
8100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
8101 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
8102 /* VNIC page size and level. */
8103 uint8_t vnic_pg_size_vnic_lvl;
8104 /* VNIC PBL indirect levels. */
8105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
8107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
8108 /* PBL pointer is physical start address. */
8109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
8111 /* PBL pointer points to PTE table. */
8112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
8114 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
8117 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
8118 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
8119 /* VNIC page size. */
8120 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
8122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
8124 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
8125 (UINT32_C(0x0) << 4)
8127 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
8128 (UINT32_C(0x1) << 4)
8130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
8131 (UINT32_C(0x2) << 4)
8133 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
8134 (UINT32_C(0x3) << 4)
8136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
8137 (UINT32_C(0x4) << 4)
8139 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
8140 (UINT32_C(0x5) << 4)
8141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
8142 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
8143 /* Stat page size and level. */
8144 uint8_t stat_pg_size_stat_lvl;
8145 /* Stat PBL indirect levels. */
8146 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
8148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
8149 /* PBL pointer is physical start address. */
8150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
8152 /* PBL pointer points to PTE table. */
8153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
8155 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
8158 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
8159 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
8160 /* Stat page size. */
8161 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
8163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
8165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
8166 (UINT32_C(0x0) << 4)
8168 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
8169 (UINT32_C(0x1) << 4)
8171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
8172 (UINT32_C(0x2) << 4)
8174 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
8175 (UINT32_C(0x3) << 4)
8177 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
8178 (UINT32_C(0x4) << 4)
8180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
8181 (UINT32_C(0x5) << 4)
8182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
8183 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
8184 /* TQM slow path page size and level. */
8185 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
8186 /* TQM slow path PBL indirect levels. */
8187 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
8189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
8190 /* PBL pointer is physical start address. */
8191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
8193 /* PBL pointer points to PTE table. */
8194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
8196 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
8199 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
8200 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
8201 /* TQM slow path page size. */
8202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
8204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
8206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
8207 (UINT32_C(0x0) << 4)
8209 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
8210 (UINT32_C(0x1) << 4)
8212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
8213 (UINT32_C(0x2) << 4)
8215 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
8216 (UINT32_C(0x3) << 4)
8218 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
8219 (UINT32_C(0x4) << 4)
8221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
8222 (UINT32_C(0x5) << 4)
8223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
8224 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
8225 /* TQM ring 0 page size and level. */
8226 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
8227 /* TQM ring 0 PBL indirect levels. */
8228 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
8230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
8231 /* PBL pointer is physical start address. */
8232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
8234 /* PBL pointer points to PTE table. */
8235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
8237 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
8240 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
8241 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
8242 /* TQM ring 0 page size. */
8243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
8245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
8247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
8248 (UINT32_C(0x0) << 4)
8250 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
8251 (UINT32_C(0x1) << 4)
8253 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
8254 (UINT32_C(0x2) << 4)
8256 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
8257 (UINT32_C(0x3) << 4)
8259 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
8260 (UINT32_C(0x4) << 4)
8262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
8263 (UINT32_C(0x5) << 4)
8264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
8265 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
8266 /* TQM ring 1 page size and level. */
8267 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
8268 /* TQM ring 1 PBL indirect levels. */
8269 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
8271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
8272 /* PBL pointer is physical start address. */
8273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
8275 /* PBL pointer points to PTE table. */
8276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
8278 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
8281 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
8282 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
8283 /* TQM ring 1 page size. */
8284 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
8286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
8288 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
8289 (UINT32_C(0x0) << 4)
8291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
8292 (UINT32_C(0x1) << 4)
8294 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
8295 (UINT32_C(0x2) << 4)
8297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
8298 (UINT32_C(0x3) << 4)
8300 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
8301 (UINT32_C(0x4) << 4)
8303 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
8304 (UINT32_C(0x5) << 4)
8305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
8306 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
8307 /* TQM ring 2 page size and level. */
8308 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
8309 /* TQM ring 2 PBL indirect levels. */
8310 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
8312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
8313 /* PBL pointer is physical start address. */
8314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
8316 /* PBL pointer points to PTE table. */
8317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
8319 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
8322 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
8323 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
8324 /* TQM ring 2 page size. */
8325 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
8327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
8329 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
8330 (UINT32_C(0x0) << 4)
8332 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
8333 (UINT32_C(0x1) << 4)
8335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
8336 (UINT32_C(0x2) << 4)
8338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
8339 (UINT32_C(0x3) << 4)
8341 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
8342 (UINT32_C(0x4) << 4)
8344 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
8345 (UINT32_C(0x5) << 4)
8346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
8347 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
8348 /* TQM ring 3 page size and level. */
8349 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
8350 /* TQM ring 3 PBL indirect levels. */
8351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
8353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
8354 /* PBL pointer is physical start address. */
8355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
8357 /* PBL pointer points to PTE table. */
8358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
8360 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
8363 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
8364 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
8365 /* TQM ring 3 page size. */
8366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
8368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
8370 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
8371 (UINT32_C(0x0) << 4)
8373 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
8374 (UINT32_C(0x1) << 4)
8376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
8377 (UINT32_C(0x2) << 4)
8379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
8380 (UINT32_C(0x3) << 4)
8382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
8383 (UINT32_C(0x4) << 4)
8385 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
8386 (UINT32_C(0x5) << 4)
8387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
8388 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
8389 /* TQM ring 4 page size and level. */
8390 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
8391 /* TQM ring 4 PBL indirect levels. */
8392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
8394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
8395 /* PBL pointer is physical start address. */
8396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
8398 /* PBL pointer points to PTE table. */
8399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
8401 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
8404 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
8405 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
8406 /* TQM ring 4 page size. */
8407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
8409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
8411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
8412 (UINT32_C(0x0) << 4)
8414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
8415 (UINT32_C(0x1) << 4)
8417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
8418 (UINT32_C(0x2) << 4)
8420 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
8421 (UINT32_C(0x3) << 4)
8423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
8424 (UINT32_C(0x4) << 4)
8426 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
8427 (UINT32_C(0x5) << 4)
8428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
8429 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
8430 /* TQM ring 5 page size and level. */
8431 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
8432 /* TQM ring 5 PBL indirect levels. */
8433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
8435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
8436 /* PBL pointer is physical start address. */
8437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
8439 /* PBL pointer points to PTE table. */
8440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
8442 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
8445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
8446 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
8447 /* TQM ring 5 page size. */
8448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
8450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
8452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
8453 (UINT32_C(0x0) << 4)
8455 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
8456 (UINT32_C(0x1) << 4)
8458 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
8459 (UINT32_C(0x2) << 4)
8461 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
8462 (UINT32_C(0x3) << 4)
8464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
8465 (UINT32_C(0x4) << 4)
8467 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
8468 (UINT32_C(0x5) << 4)
8469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
8470 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
8471 /* TQM ring 6 page size and level. */
8472 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
8473 /* TQM ring 6 PBL indirect levels. */
8474 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
8476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
8477 /* PBL pointer is physical start address. */
8478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
8480 /* PBL pointer points to PTE table. */
8481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
8483 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
8486 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
8487 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
8488 /* TQM ring 6 page size. */
8489 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
8491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
8493 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
8494 (UINT32_C(0x0) << 4)
8496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
8497 (UINT32_C(0x1) << 4)
8499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
8500 (UINT32_C(0x2) << 4)
8502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
8503 (UINT32_C(0x3) << 4)
8505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
8506 (UINT32_C(0x4) << 4)
8508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
8509 (UINT32_C(0x5) << 4)
8510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
8511 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
8512 /* TQM ring 7 page size and level. */
8513 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
8514 /* TQM ring 7 PBL indirect levels. */
8515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
8517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
8518 /* PBL pointer is physical start address. */
8519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
8521 /* PBL pointer points to PTE table. */
8522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
8524 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
8527 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
8528 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
8529 /* TQM ring 7 page size. */
8530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
8532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
8534 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
8535 (UINT32_C(0x0) << 4)
8537 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
8538 (UINT32_C(0x1) << 4)
8540 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
8541 (UINT32_C(0x2) << 4)
8543 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
8544 (UINT32_C(0x3) << 4)
8546 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
8547 (UINT32_C(0x4) << 4)
8549 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
8550 (UINT32_C(0x5) << 4)
8551 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
8552 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
8553 /* MR/AV page size and level. */
8554 uint8_t mrav_pg_size_mrav_lvl;
8555 /* MR/AV PBL indirect levels. */
8556 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
8558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
8559 /* PBL pointer is physical start address. */
8560 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
8562 /* PBL pointer points to PTE table. */
8563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
8565 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
8568 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
8569 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
8570 /* MR/AV page size. */
8571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
8573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
8575 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
8576 (UINT32_C(0x0) << 4)
8578 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
8579 (UINT32_C(0x1) << 4)
8581 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
8582 (UINT32_C(0x2) << 4)
8584 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
8585 (UINT32_C(0x3) << 4)
8587 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
8588 (UINT32_C(0x4) << 4)
8590 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
8591 (UINT32_C(0x5) << 4)
8592 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
8593 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
8594 /* Timer page size and level. */
8595 uint8_t tim_pg_size_tim_lvl;
8596 /* Timer PBL indirect levels. */
8597 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
8599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
8600 /* PBL pointer is physical start address. */
8601 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
8603 /* PBL pointer points to PTE table. */
8604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
8606 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
8609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
8610 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
8611 /* Timer page size. */
8612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
8614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
8616 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
8617 (UINT32_C(0x0) << 4)
8619 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
8620 (UINT32_C(0x1) << 4)
8622 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
8623 (UINT32_C(0x2) << 4)
8625 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
8626 (UINT32_C(0x3) << 4)
8628 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
8629 (UINT32_C(0x4) << 4)
8631 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
8632 (UINT32_C(0x5) << 4)
8633 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
8634 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
8635 /* QP page directory. */
8636 uint64_t qpc_page_dir;
8637 /* SRQ page directory. */
8638 uint64_t srq_page_dir;
8639 /* CQ page directory. */
8640 uint64_t cq_page_dir;
8641 /* VNIC page directory. */
8642 uint64_t vnic_page_dir;
8643 /* Stat page directory. */
8644 uint64_t stat_page_dir;
8645 /* TQM slowpath page directory. */
8646 uint64_t tqm_sp_page_dir;
8647 /* TQM ring 0 page directory. */
8648 uint64_t tqm_ring0_page_dir;
8649 /* TQM ring 1 page directory. */
8650 uint64_t tqm_ring1_page_dir;
8651 /* TQM ring 2 page directory. */
8652 uint64_t tqm_ring2_page_dir;
8653 /* TQM ring 3 page directory. */
8654 uint64_t tqm_ring3_page_dir;
8655 /* TQM ring 4 page directory. */
8656 uint64_t tqm_ring4_page_dir;
8657 /* TQM ring 5 page directory. */
8658 uint64_t tqm_ring5_page_dir;
8659 /* TQM ring 6 page directory. */
8660 uint64_t tqm_ring6_page_dir;
8661 /* TQM ring 7 page directory. */
8662 uint64_t tqm_ring7_page_dir;
8663 /* MR/AV page directory. */
8664 uint64_t mrav_page_dir;
8665 /* Timer page directory. */
8666 uint64_t tim_page_dir;
8667 /* Number of QPs. */
8668 uint32_t qp_num_entries;
8669 /* Number of SRQs. */
8670 uint32_t srq_num_entries;
8671 /* Number of CQs. */
8672 uint32_t cq_num_entries;
8673 /* Number of Stats. */
8674 uint32_t stat_num_entries;
8675 /* Number of TQM slowpath entries. */
8676 uint32_t tqm_sp_num_entries;
8677 /* Number of TQM ring 0 entries. */
8678 uint32_t tqm_ring0_num_entries;
8679 /* Number of TQM ring 1 entries. */
8680 uint32_t tqm_ring1_num_entries;
8681 /* Number of TQM ring 2 entries. */
8682 uint32_t tqm_ring2_num_entries;
8683 /* Number of TQM ring 3 entries. */
8684 uint32_t tqm_ring3_num_entries;
8685 /* Number of TQM ring 4 entries. */
8686 uint32_t tqm_ring4_num_entries;
8687 /* Number of TQM ring 5 entries. */
8688 uint32_t tqm_ring5_num_entries;
8689 /* Number of TQM ring 6 entries. */
8690 uint32_t tqm_ring6_num_entries;
8691 /* Number of TQM ring 7 entries. */
8692 uint32_t tqm_ring7_num_entries;
8693 /* Number of MR/AV entries. */
8694 uint32_t mrav_num_entries;
8695 /* Number of Timer entries. */
8696 uint32_t tim_num_entries;
8697 /* Number of entries to reserve for QP1 */
8698 uint16_t qp_num_qp1_entries;
8699 /* Number of entries to reserve for L2 */
8700 uint16_t qp_num_l2_entries;
8701 /* Number of bytes that have been allocated for each context entry. */
8702 uint16_t qp_entry_size;
8703 /* Number of entries to reserve for L2 */
8704 uint16_t srq_num_l2_entries;
8705 /* Number of bytes that have been allocated for each context entry. */
8706 uint16_t srq_entry_size;
8707 /* Number of entries to reserve for L2 */
8708 uint16_t cq_num_l2_entries;
8709 /* Number of bytes that have been allocated for each context entry. */
8710 uint16_t cq_entry_size;
8711 /* Number of entries to reserve for VNIC entries */
8712 uint16_t vnic_num_vnic_entries;
8713 /* Number of entries to reserve for Ring table entries */
8714 uint16_t vnic_num_ring_table_entries;
8715 /* Number of bytes that have been allocated for each context entry. */
8716 uint16_t vnic_entry_size;
8717 /* Number of bytes that have been allocated for each context entry. */
8718 uint16_t stat_entry_size;
8719 /* Number of bytes that have been allocated for each context entry. */
8720 uint16_t tqm_entry_size;
8721 /* Number of bytes that have been allocated for each context entry. */
8722 uint16_t mrav_entry_size;
8723 /* Number of bytes that have been allocated for each context entry. */
8724 uint16_t tim_entry_size;
8725 } __attribute__((packed));
8727 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
8728 struct hwrm_func_backing_store_cfg_output {
8729 /* The specific error status for the command. */
8730 uint16_t error_code;
8731 /* The HWRM command request type. */
8733 /* The sequence ID from the original command. */
8735 /* The length of the response data in number of bytes. */
8737 uint8_t unused_0[7];
8739 * This field is used in Output records to indicate that the output
8740 * is completely written to RAM. This field should be read as '1'
8741 * to indicate that the output has been completely written.
8742 * When writing a command completion or response to an internal processor,
8743 * the order of writes has to be such that this field is written last.
8746 } __attribute__((packed));
8748 /********************************
8749 * hwrm_func_backing_store_qcfg *
8750 ********************************/
8753 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
8754 struct hwrm_func_backing_store_qcfg_input {
8755 /* The HWRM command request type. */
8758 * The completion ring to send the completion event on. This should
8759 * be the NQ ID returned from the `nq_alloc` HWRM command.
8763 * The sequence ID is used by the driver for tracking multiple
8764 * commands. This ID is treated as opaque data by the firmware and
8765 * the value is returned in the `hwrm_resp_hdr` upon completion.
8769 * The target ID of the command:
8770 * * 0x0-0xFFF8 - The function ID
8771 * * 0xFFF8-0xFFFE - Reserved for internal processors
8776 * A physical address pointer pointing to a host buffer that the
8777 * command's response data will be written. This can be either a host
8778 * physical address (HPA) or a guest physical address (GPA) and must
8779 * point to a physically contiguous block of memory.
8782 } __attribute__((packed));
8784 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
8785 struct hwrm_func_backing_store_qcfg_output {
8786 /* The specific error status for the command. */
8787 uint16_t error_code;
8788 /* The HWRM command request type. */
8790 /* The sequence ID from the original command. */
8792 /* The length of the response data in number of bytes. */
8796 * When set, the firmware only uses on-chip resources and does not
8797 * expect any backing store to be provided by the host driver. This
8798 * mode provides minimal L2 functionality (e.g. limited L2 resources,
8801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
8803 uint8_t unused_0[4];
8805 * This bit must be '1' for the qp fields to be
8808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
8811 * This bit must be '1' for the srq fields to be
8814 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
8817 * This bit must be '1' for the cq fields to be
8820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
8823 * This bit must be '1' for the vnic fields to be
8826 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
8829 * This bit must be '1' for the stat fields to be
8832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
8835 * This bit must be '1' for the tqm_sp fields to be
8838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
8841 * This bit must be '1' for the tqm_ring0 fields to be
8844 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
8847 * This bit must be '1' for the tqm_ring1 fields to be
8850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
8853 * This bit must be '1' for the tqm_ring2 fields to be
8856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
8859 * This bit must be '1' for the tqm_ring3 fields to be
8862 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
8865 * This bit must be '1' for the tqm_ring4 fields to be
8868 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
8871 * This bit must be '1' for the tqm_ring5 fields to be
8874 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
8877 * This bit must be '1' for the tqm_ring6 fields to be
8880 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
8883 * This bit must be '1' for the tqm_ring7 fields to be
8886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
8889 * This bit must be '1' for the mrav fields to be
8892 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
8895 * This bit must be '1' for the tim fields to be
8898 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
8900 /* QPC page size and level. */
8901 uint8_t qpc_pg_size_qpc_lvl;
8902 /* QPC PBL indirect levels. */
8903 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
8905 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
8906 /* PBL pointer is physical start address. */
8907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
8909 /* PBL pointer points to PTE table. */
8910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
8912 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8913 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
8915 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
8916 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
8917 /* QPC page size. */
8918 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
8920 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
8922 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
8923 (UINT32_C(0x0) << 4)
8925 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
8926 (UINT32_C(0x1) << 4)
8928 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
8929 (UINT32_C(0x2) << 4)
8931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
8932 (UINT32_C(0x3) << 4)
8934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
8935 (UINT32_C(0x4) << 4)
8937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
8938 (UINT32_C(0x5) << 4)
8939 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
8940 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
8941 /* SRQ page size and level. */
8942 uint8_t srq_pg_size_srq_lvl;
8943 /* SRQ PBL indirect levels. */
8944 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
8946 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
8947 /* PBL pointer is physical start address. */
8948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
8950 /* PBL pointer points to PTE table. */
8951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
8953 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8954 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
8956 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
8957 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
8958 /* SRQ page size. */
8959 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
8961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
8963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
8964 (UINT32_C(0x0) << 4)
8966 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
8967 (UINT32_C(0x1) << 4)
8969 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
8970 (UINT32_C(0x2) << 4)
8972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
8973 (UINT32_C(0x3) << 4)
8975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
8976 (UINT32_C(0x4) << 4)
8978 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
8979 (UINT32_C(0x5) << 4)
8980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
8981 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
8982 /* CQ page size and level. */
8983 uint8_t cq_pg_size_cq_lvl;
8984 /* CQ PBL indirect levels. */
8985 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
8987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
8988 /* PBL pointer is physical start address. */
8989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
8991 /* PBL pointer points to PTE table. */
8992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
8994 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8995 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
8997 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
8998 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
9000 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
9002 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
9004 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
9005 (UINT32_C(0x0) << 4)
9007 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
9008 (UINT32_C(0x1) << 4)
9010 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
9011 (UINT32_C(0x2) << 4)
9013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
9014 (UINT32_C(0x3) << 4)
9016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
9017 (UINT32_C(0x4) << 4)
9019 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
9020 (UINT32_C(0x5) << 4)
9021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
9022 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
9023 /* VNIC page size and level. */
9024 uint8_t vnic_pg_size_vnic_lvl;
9025 /* VNIC PBL indirect levels. */
9026 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
9028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
9029 /* PBL pointer is physical start address. */
9030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
9032 /* PBL pointer points to PTE table. */
9033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
9035 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9036 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
9038 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
9039 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
9040 /* VNIC page size. */
9041 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
9043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
9045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
9046 (UINT32_C(0x0) << 4)
9048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
9049 (UINT32_C(0x1) << 4)
9051 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
9052 (UINT32_C(0x2) << 4)
9054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
9055 (UINT32_C(0x3) << 4)
9057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
9058 (UINT32_C(0x4) << 4)
9060 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
9061 (UINT32_C(0x5) << 4)
9062 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
9063 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
9064 /* Stat page size and level. */
9065 uint8_t stat_pg_size_stat_lvl;
9066 /* Stat PBL indirect levels. */
9067 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
9069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
9070 /* PBL pointer is physical start address. */
9071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
9073 /* PBL pointer points to PTE table. */
9074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
9076 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9077 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
9079 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
9080 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
9081 /* Stat page size. */
9082 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
9084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
9086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
9087 (UINT32_C(0x0) << 4)
9089 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
9090 (UINT32_C(0x1) << 4)
9092 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
9093 (UINT32_C(0x2) << 4)
9095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
9096 (UINT32_C(0x3) << 4)
9098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
9099 (UINT32_C(0x4) << 4)
9101 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
9102 (UINT32_C(0x5) << 4)
9103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
9104 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
9105 /* TQM slow path page size and level. */
9106 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
9107 /* TQM slow path PBL indirect levels. */
9108 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
9110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
9111 /* PBL pointer is physical start address. */
9112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
9114 /* PBL pointer points to PTE table. */
9115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
9117 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
9120 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
9121 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
9122 /* TQM slow path page size. */
9123 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
9125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
9127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
9128 (UINT32_C(0x0) << 4)
9130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
9131 (UINT32_C(0x1) << 4)
9133 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
9134 (UINT32_C(0x2) << 4)
9136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
9137 (UINT32_C(0x3) << 4)
9139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
9140 (UINT32_C(0x4) << 4)
9142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
9143 (UINT32_C(0x5) << 4)
9144 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
9145 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
9146 /* TQM ring 0 page size and level. */
9147 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9148 /* TQM ring 0 PBL indirect levels. */
9149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
9151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
9152 /* PBL pointer is physical start address. */
9153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
9155 /* PBL pointer points to PTE table. */
9156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
9158 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
9161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
9162 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
9163 /* TQM ring 0 page size. */
9164 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
9166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
9168 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
9169 (UINT32_C(0x0) << 4)
9171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
9172 (UINT32_C(0x1) << 4)
9174 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
9175 (UINT32_C(0x2) << 4)
9177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
9178 (UINT32_C(0x3) << 4)
9180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
9181 (UINT32_C(0x4) << 4)
9183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
9184 (UINT32_C(0x5) << 4)
9185 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
9186 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
9187 /* TQM ring 1 page size and level. */
9188 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9189 /* TQM ring 1 PBL indirect levels. */
9190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
9192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
9193 /* PBL pointer is physical start address. */
9194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
9196 /* PBL pointer points to PTE table. */
9197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
9199 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
9202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
9203 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
9204 /* TQM ring 1 page size. */
9205 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
9207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
9209 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
9210 (UINT32_C(0x0) << 4)
9212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
9213 (UINT32_C(0x1) << 4)
9215 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
9216 (UINT32_C(0x2) << 4)
9218 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
9219 (UINT32_C(0x3) << 4)
9221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
9222 (UINT32_C(0x4) << 4)
9224 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
9225 (UINT32_C(0x5) << 4)
9226 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
9227 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
9228 /* TQM ring 2 page size and level. */
9229 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9230 /* TQM ring 2 PBL indirect levels. */
9231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
9233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
9234 /* PBL pointer is physical start address. */
9235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
9237 /* PBL pointer points to PTE table. */
9238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
9240 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
9243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
9244 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
9245 /* TQM ring 2 page size. */
9246 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
9248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
9250 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
9251 (UINT32_C(0x0) << 4)
9253 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
9254 (UINT32_C(0x1) << 4)
9256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
9257 (UINT32_C(0x2) << 4)
9259 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
9260 (UINT32_C(0x3) << 4)
9262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
9263 (UINT32_C(0x4) << 4)
9265 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
9266 (UINT32_C(0x5) << 4)
9267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
9268 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
9269 /* TQM ring 3 page size and level. */
9270 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9271 /* TQM ring 3 PBL indirect levels. */
9272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
9274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
9275 /* PBL pointer is physical start address. */
9276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
9278 /* PBL pointer points to PTE table. */
9279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
9281 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
9284 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
9285 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
9286 /* TQM ring 3 page size. */
9287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
9289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
9291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
9292 (UINT32_C(0x0) << 4)
9294 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
9295 (UINT32_C(0x1) << 4)
9297 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
9298 (UINT32_C(0x2) << 4)
9300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
9301 (UINT32_C(0x3) << 4)
9303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
9304 (UINT32_C(0x4) << 4)
9306 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
9307 (UINT32_C(0x5) << 4)
9308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
9309 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
9310 /* TQM ring 4 page size and level. */
9311 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9312 /* TQM ring 4 PBL indirect levels. */
9313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
9315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
9316 /* PBL pointer is physical start address. */
9317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
9319 /* PBL pointer points to PTE table. */
9320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
9322 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
9325 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
9326 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
9327 /* TQM ring 4 page size. */
9328 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
9330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
9332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
9333 (UINT32_C(0x0) << 4)
9335 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
9336 (UINT32_C(0x1) << 4)
9338 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
9339 (UINT32_C(0x2) << 4)
9341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
9342 (UINT32_C(0x3) << 4)
9344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
9345 (UINT32_C(0x4) << 4)
9347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
9348 (UINT32_C(0x5) << 4)
9349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
9350 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
9351 /* TQM ring 5 page size and level. */
9352 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9353 /* TQM ring 5 PBL indirect levels. */
9354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
9356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
9357 /* PBL pointer is physical start address. */
9358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
9360 /* PBL pointer points to PTE table. */
9361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
9363 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
9366 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
9367 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
9368 /* TQM ring 5 page size. */
9369 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
9371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
9373 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
9374 (UINT32_C(0x0) << 4)
9376 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
9377 (UINT32_C(0x1) << 4)
9379 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
9380 (UINT32_C(0x2) << 4)
9382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
9383 (UINT32_C(0x3) << 4)
9385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
9386 (UINT32_C(0x4) << 4)
9388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
9389 (UINT32_C(0x5) << 4)
9390 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
9391 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
9392 /* TQM ring 6 page size and level. */
9393 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9394 /* TQM ring 6 PBL indirect levels. */
9395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
9397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
9398 /* PBL pointer is physical start address. */
9399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
9401 /* PBL pointer points to PTE table. */
9402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
9404 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
9407 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
9408 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
9409 /* TQM ring 6 page size. */
9410 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
9412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
9414 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
9415 (UINT32_C(0x0) << 4)
9417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
9418 (UINT32_C(0x1) << 4)
9420 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
9421 (UINT32_C(0x2) << 4)
9423 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
9424 (UINT32_C(0x3) << 4)
9426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
9427 (UINT32_C(0x4) << 4)
9429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
9430 (UINT32_C(0x5) << 4)
9431 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
9432 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
9433 /* TQM ring 7 page size and level. */
9434 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9435 /* TQM ring 7 PBL indirect levels. */
9436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
9438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
9439 /* PBL pointer is physical start address. */
9440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
9442 /* PBL pointer points to PTE table. */
9443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
9445 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
9448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
9449 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
9450 /* TQM ring 7 page size. */
9451 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
9453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
9455 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
9456 (UINT32_C(0x0) << 4)
9458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
9459 (UINT32_C(0x1) << 4)
9461 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
9462 (UINT32_C(0x2) << 4)
9464 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
9465 (UINT32_C(0x3) << 4)
9467 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
9468 (UINT32_C(0x4) << 4)
9470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
9471 (UINT32_C(0x5) << 4)
9472 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
9473 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
9474 /* MR/AV page size and level. */
9475 uint8_t mrav_pg_size_mrav_lvl;
9476 /* MR/AV PBL indirect levels. */
9477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
9479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
9480 /* PBL pointer is physical start address. */
9481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
9483 /* PBL pointer points to PTE table. */
9484 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
9486 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
9489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
9490 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
9491 /* MR/AV page size. */
9492 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
9494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
9496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
9497 (UINT32_C(0x0) << 4)
9499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
9500 (UINT32_C(0x1) << 4)
9502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
9503 (UINT32_C(0x2) << 4)
9505 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
9506 (UINT32_C(0x3) << 4)
9508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
9509 (UINT32_C(0x4) << 4)
9511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
9512 (UINT32_C(0x5) << 4)
9513 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
9514 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
9515 /* Timer page size and level. */
9516 uint8_t tim_pg_size_tim_lvl;
9517 /* Timer PBL indirect levels. */
9518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
9520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
9521 /* PBL pointer is physical start address. */
9522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
9524 /* PBL pointer points to PTE table. */
9525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
9527 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
9530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
9531 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
9532 /* Timer page size. */
9533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
9535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
9537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
9538 (UINT32_C(0x0) << 4)
9540 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
9541 (UINT32_C(0x1) << 4)
9543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
9544 (UINT32_C(0x2) << 4)
9546 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
9547 (UINT32_C(0x3) << 4)
9549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
9550 (UINT32_C(0x4) << 4)
9552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
9553 (UINT32_C(0x5) << 4)
9554 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
9555 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
9556 /* QP page directory. */
9557 uint64_t qpc_page_dir;
9558 /* SRQ page directory. */
9559 uint64_t srq_page_dir;
9560 /* CQ page directory. */
9561 uint64_t cq_page_dir;
9562 /* VNIC page directory. */
9563 uint64_t vnic_page_dir;
9564 /* Stat page directory. */
9565 uint64_t stat_page_dir;
9566 /* TQM slowpath page directory. */
9567 uint64_t tqm_sp_page_dir;
9568 /* TQM ring 0 page directory. */
9569 uint64_t tqm_ring0_page_dir;
9570 /* TQM ring 1 page directory. */
9571 uint64_t tqm_ring1_page_dir;
9572 /* TQM ring 2 page directory. */
9573 uint64_t tqm_ring2_page_dir;
9574 /* TQM ring 3 page directory. */
9575 uint64_t tqm_ring3_page_dir;
9576 /* TQM ring 4 page directory. */
9577 uint64_t tqm_ring4_page_dir;
9578 /* TQM ring 5 page directory. */
9579 uint64_t tqm_ring5_page_dir;
9580 /* TQM ring 6 page directory. */
9581 uint64_t tqm_ring6_page_dir;
9582 /* TQM ring 7 page directory. */
9583 uint64_t tqm_ring7_page_dir;
9584 /* MR/AV page directory. */
9585 uint64_t mrav_page_dir;
9586 /* Timer page directory. */
9587 uint64_t tim_page_dir;
9588 /* Number of entries to reserve for QP1 */
9589 uint16_t qp_num_qp1_entries;
9590 /* Number of entries to reserve for L2 */
9591 uint16_t qp_num_l2_entries;
9592 /* Number of QPs. */
9593 uint32_t qp_num_entries;
9594 /* Number of SRQs. */
9595 uint32_t srq_num_entries;
9596 /* Number of entries to reserve for L2 */
9597 uint16_t srq_num_l2_entries;
9598 /* Number of entries to reserve for L2 */
9599 uint16_t cq_num_l2_entries;
9600 /* Number of CQs. */
9601 uint32_t cq_num_entries;
9602 /* Number of entries to reserve for VNIC entries */
9603 uint16_t vnic_num_vnic_entries;
9604 /* Number of entries to reserve for Ring table entries */
9605 uint16_t vnic_num_ring_table_entries;
9606 /* Number of Stats. */
9607 uint32_t stat_num_entries;
9608 /* Number of TQM slowpath entries. */
9609 uint32_t tqm_sp_num_entries;
9610 /* Number of TQM ring 0 entries. */
9611 uint32_t tqm_ring0_num_entries;
9612 /* Number of TQM ring 1 entries. */
9613 uint32_t tqm_ring1_num_entries;
9614 /* Number of TQM ring 2 entries. */
9615 uint32_t tqm_ring2_num_entries;
9616 /* Number of TQM ring 3 entries. */
9617 uint32_t tqm_ring3_num_entries;
9618 /* Number of TQM ring 4 entries. */
9619 uint32_t tqm_ring4_num_entries;
9620 /* Number of TQM ring 5 entries. */
9621 uint32_t tqm_ring5_num_entries;
9622 /* Number of TQM ring 6 entries. */
9623 uint32_t tqm_ring6_num_entries;
9624 /* Number of TQM ring 7 entries. */
9625 uint32_t tqm_ring7_num_entries;
9626 /* Number of MR/AV entries. */
9627 uint32_t mrav_num_entries;
9628 /* Number of Timer entries. */
9629 uint32_t tim_num_entries;
9630 uint8_t unused_1[7];
9632 * This field is used in Output records to indicate that the output
9633 * is completely written to RAM. This field should be read as '1'
9634 * to indicate that the output has been completely written.
9635 * When writing a command completion or response to an internal processor,
9636 * the order of writes has to be such that this field is written last.
9639 } __attribute__((packed));
9641 /*********************
9642 * hwrm_port_phy_cfg *
9643 *********************/
9646 /* hwrm_port_phy_cfg_input (size:448b/56B) */
9647 struct hwrm_port_phy_cfg_input {
9648 /* The HWRM command request type. */
9651 * The completion ring to send the completion event on. This should
9652 * be the NQ ID returned from the `nq_alloc` HWRM command.
9656 * The sequence ID is used by the driver for tracking multiple
9657 * commands. This ID is treated as opaque data by the firmware and
9658 * the value is returned in the `hwrm_resp_hdr` upon completion.
9662 * The target ID of the command:
9663 * * 0x0-0xFFF8 - The function ID
9664 * * 0xFFF8-0xFFFE - Reserved for internal processors
9669 * A physical address pointer pointing to a host buffer that the
9670 * command's response data will be written. This can be either a host
9671 * physical address (HPA) or a guest physical address (GPA) and must
9672 * point to a physically contiguous block of memory.
9677 * When this bit is set to '1', the PHY for the port shall
9680 * # If this bit is set to 1, then the HWRM shall reset the
9681 * PHY after applying PHY configuration changes specified
9683 * # In order to guarantee that PHY configuration changes
9684 * specified in this command take effect, the HWRM
9685 * client should set this flag to 1.
9686 * # If this bit is not set to 1, then the HWRM may reset
9687 * the PHY depending on the current PHY configuration and
9688 * settings specified in this command.
9690 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
9692 /* deprecated bit. Do not use!!! */
9693 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
9696 * When this bit is set to '1', the link shall be forced to
9697 * the force_link_speed value.
9699 * When this bit is set to '1', the HWRM client should
9700 * not enable any of the auto negotiation related
9701 * fields represented by auto_XXX fields in this command.
9702 * When this bit is set to '1' and the HWRM client has
9703 * enabled a auto_XXX field in this command, then the
9704 * HWRM shall ignore the enabled auto_XXX field.
9706 * When this bit is set to zero, the link
9707 * shall be allowed to autoneg.
9709 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
9712 * When this bit is set to '1', the auto-negotiation process
9713 * shall be restarted on the link.
9715 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
9718 * When this bit is set to '1', Energy Efficient Ethernet
9719 * (EEE) is requested to be enabled on this link.
9720 * If EEE is not supported on this port, then this flag
9721 * shall be ignored by the HWRM.
9723 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
9726 * When this bit is set to '1', Energy Efficient Ethernet
9727 * (EEE) is requested to be disabled on this link.
9728 * If EEE is not supported on this port, then this flag
9729 * shall be ignored by the HWRM.
9731 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
9734 * When this bit is set to '1' and EEE is enabled on this
9735 * link, then TX LPI is requested to be enabled on the link.
9736 * If EEE is not supported on this port, then this flag
9737 * shall be ignored by the HWRM.
9738 * If EEE is disabled on this port, then this flag shall be
9739 * ignored by the HWRM.
9741 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
9744 * When this bit is set to '1' and EEE is enabled on this
9745 * link, then TX LPI is requested to be disabled on the link.
9746 * If EEE is not supported on this port, then this flag
9747 * shall be ignored by the HWRM.
9748 * If EEE is disabled on this port, then this flag shall be
9749 * ignored by the HWRM.
9751 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
9754 * When set to 1, then the HWRM shall enable FEC autonegotitation
9755 * on this port if supported.
9756 * When set to 0, then this flag shall be ignored.
9757 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
9760 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
9763 * When set to 1, then the HWRM shall disable FEC autonegotiation
9764 * on this port if supported.
9765 * When set to 0, then this flag shall be ignored.
9766 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
9769 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
9772 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
9773 * on this port if supported.
9774 * When set to 0, then this flag shall be ignored.
9775 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
9778 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
9781 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
9782 * on this port if supported.
9783 * When set to 0, then this flag shall be ignored.
9784 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
9787 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
9790 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
9791 * on this port if supported.
9792 * When set to 0, then this flag shall be ignored.
9793 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
9796 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
9799 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
9800 * on this port if supported.
9801 * When set to 0, then this flag shall be ignored.
9802 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
9805 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
9808 * When this bit is set to '1', the link shall be forced to
9811 * # When this bit is set to '1", all other
9812 * command input settings related to the link speed shall
9814 * Once the link state is forced down, it can be
9815 * explicitly cleared from that state by setting this flag
9817 * # If this flag is set to '0', then the link shall be
9818 * cleared from forced down state if the link is in forced
9820 * There may be conditions (e.g. out-of-band or sideband
9821 * configuration changes for the link) outside the scope
9822 * of the HWRM implementation that may clear forced down
9825 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
9829 * This bit must be '1' for the auto_mode field to be
9832 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
9835 * This bit must be '1' for the auto_duplex field to be
9838 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
9841 * This bit must be '1' for the auto_pause field to be
9844 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
9847 * This bit must be '1' for the auto_link_speed field to be
9850 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
9853 * This bit must be '1' for the auto_link_speed_mask field to be
9856 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
9859 * This bit must be '1' for the wirespeed field to be
9862 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
9865 * This bit must be '1' for the lpbk field to be
9868 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
9871 * This bit must be '1' for the preemphasis field to be
9874 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
9877 * This bit must be '1' for the force_pause field to be
9880 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
9883 * This bit must be '1' for the eee_link_speed_mask field to be
9886 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
9889 * This bit must be '1' for the tx_lpi_timer field to be
9892 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
9894 /* Port ID of port that is to be configured. */
9897 * This is the speed that will be used if the force
9898 * bit is '1'. If unsupported speed is selected, an error
9899 * will be generated.
9901 uint16_t force_link_speed;
9902 /* 100Mb link speed */
9903 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
9904 /* 1Gb link speed */
9905 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
9906 /* 2Gb link speed */
9907 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
9908 /* 25Gb link speed */
9909 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
9910 /* 10Gb link speed */
9911 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
9912 /* 20Mb link speed */
9913 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
9914 /* 25Gb link speed */
9915 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
9916 /* 40Gb link speed */
9917 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
9918 /* 50Gb link speed */
9919 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
9920 /* 100Gb link speed */
9921 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
9922 /* 10Mb link speed */
9923 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
9924 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
9925 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
9927 * This value is used to identify what autoneg mode is
9928 * used when the link speed is not being forced.
9931 /* Disable autoneg or autoneg disabled. No speeds are selected. */
9932 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
9933 /* Select all possible speeds for autoneg mode. */
9934 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
9936 * Select only the auto_link_speed speed for autoneg mode. This mode has
9937 * been DEPRECATED. An HWRM client should not use this mode.
9939 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
9941 * Select the auto_link_speed or any speed below that speed for autoneg.
9942 * This mode has been DEPRECATED. An HWRM client should not use this mode.
9944 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
9946 * Select the speeds based on the corresponding link speed mask value
9949 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
9950 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
9951 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
9953 * This is the duplex setting that will be used if the autoneg_mode
9954 * is "one_speed" or "one_or_below".
9956 uint8_t auto_duplex;
9957 /* Half Duplex will be requested. */
9958 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
9959 /* Full duplex will be requested. */
9960 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
9961 /* Both Half and Full dupex will be requested. */
9962 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
9963 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
9964 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
9966 * This value is used to configure the pause that will be
9967 * used for autonegotiation.
9968 * Add text on the usage of auto_pause and force_pause.
9972 * When this bit is '1', Generation of tx pause messages
9973 * has been requested. Disabled otherwise.
9975 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
9978 * When this bit is '1', Reception of rx pause messages
9979 * has been requested. Disabled otherwise.
9981 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
9984 * When set to 1, the advertisement of pause is enabled.
9986 * # When the auto_mode is not set to none and this flag is
9987 * set to 1, then the auto_pause bits on this port are being
9988 * advertised and autoneg pause results are being interpreted.
9989 * # When the auto_mode is not set to none and this
9990 * flag is set to 0, the pause is forced as indicated in
9991 * force_pause, and also advertised as auto_pause bits, but
9992 * the autoneg results are not interpreted since the pause
9993 * configuration is being forced.
9994 * # When the auto_mode is set to none and this flag is set to
9995 * 1, auto_pause bits should be ignored and should be set to 0.
9997 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
10001 * This is the speed that will be used if the autoneg_mode
10002 * is "one_speed" or "one_or_below". If an unsupported speed
10003 * is selected, an error will be generated.
10005 uint16_t auto_link_speed;
10006 /* 100Mb link speed */
10007 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
10008 /* 1Gb link speed */
10009 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
10010 /* 2Gb link speed */
10011 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
10012 /* 25Gb link speed */
10013 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
10014 /* 10Gb link speed */
10015 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
10016 /* 20Mb link speed */
10017 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
10018 /* 25Gb link speed */
10019 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
10020 /* 40Gb link speed */
10021 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
10022 /* 50Gb link speed */
10023 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
10024 /* 100Gb link speed */
10025 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
10026 /* 10Mb link speed */
10027 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
10028 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
10029 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
10031 * This is a mask of link speeds that will be used if
10032 * autoneg_mode is "mask". If unsupported speed is enabled
10033 * an error will be generated.
10035 uint16_t auto_link_speed_mask;
10036 /* 100Mb link speed (Half-duplex) */
10037 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
10039 /* 100Mb link speed (Full-duplex) */
10040 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
10042 /* 1Gb link speed (Half-duplex) */
10043 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
10045 /* 1Gb link speed (Full-duplex) */
10046 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
10048 /* 2Gb link speed */
10049 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
10051 /* 25Gb link speed */
10052 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
10054 /* 10Gb link speed */
10055 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
10057 /* 20Gb link speed */
10058 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
10060 /* 25Gb link speed */
10061 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
10063 /* 40Gb link speed */
10064 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
10066 /* 50Gb link speed */
10067 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
10069 /* 100Gb link speed */
10070 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
10072 /* 10Mb link speed (Half-duplex) */
10073 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
10075 /* 10Mb link speed (Full-duplex) */
10076 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
10078 /* This value controls the wirespeed feature. */
10080 /* Wirespeed feature is disabled. */
10081 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
10082 /* Wirespeed feature is enabled. */
10083 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
10084 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
10085 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
10086 /* This value controls the loopback setting for the PHY. */
10088 /* No loopback is selected. Normal operation. */
10089 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
10091 * The HW will be configured with local loopback such that
10092 * host data is sent back to the host without modification.
10094 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
10096 * The HW will be configured with remote loopback such that
10097 * port logic will send packets back out the transmitter that
10100 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
10102 * The HW will be configured with external loopback such that
10103 * host data is sent on the trasmitter and based on the external
10104 * loopback connection the data will be received without modification.
10106 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
10107 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
10108 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
10110 * This value is used to configure the pause that will be
10111 * used for force mode.
10113 uint8_t force_pause;
10115 * When this bit is '1', Generation of tx pause messages
10116 * is supported. Disabled otherwise.
10118 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
10120 * When this bit is '1', Reception of rx pause messages
10121 * is supported. Disabled otherwise.
10123 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
10126 * This value controls the pre-emphasis to be used for the
10127 * link. Driver should not set this value (use
10128 * enable.preemphasis = 0) unless driver is sure of setting.
10129 * Normally HWRM FW will determine proper pre-emphasis.
10131 uint32_t preemphasis;
10133 * Setting for link speed mask that is used to
10134 * advertise speeds during autonegotiation when EEE is enabled.
10135 * This field is valid only when EEE is enabled.
10136 * The speeds specified in this field shall be a subset of
10137 * speeds specified in auto_link_speed_mask.
10138 * If EEE is enabled,then at least one speed shall be provided
10141 uint16_t eee_link_speed_mask;
10143 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
10145 /* 100Mb link speed (Full-duplex) */
10146 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
10149 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
10151 /* 1Gb link speed (Full-duplex) */
10152 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
10155 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
10158 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
10160 /* 10Gb link speed */
10161 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
10163 uint8_t unused_2[2];
10165 * Reuested setting of TX LPI timer in microseconds.
10166 * This field is valid only when EEE is enabled and TX LPI is
10169 uint32_t tx_lpi_timer;
10170 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
10171 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
10173 } __attribute__((packed));
10175 /* hwrm_port_phy_cfg_output (size:128b/16B) */
10176 struct hwrm_port_phy_cfg_output {
10177 /* The specific error status for the command. */
10178 uint16_t error_code;
10179 /* The HWRM command request type. */
10181 /* The sequence ID from the original command. */
10183 /* The length of the response data in number of bytes. */
10185 uint8_t unused_0[7];
10187 * This field is used in Output records to indicate that the output
10188 * is completely written to RAM. This field should be read as '1'
10189 * to indicate that the output has been completely written.
10190 * When writing a command completion or response to an internal processor,
10191 * the order of writes has to be such that this field is written last.
10194 } __attribute__((packed));
10196 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
10197 struct hwrm_port_phy_cfg_cmd_err {
10199 * command specific error codes that goes to
10200 * the cmd_err field in Common HWRM Error Response.
10203 /* Unknown error */
10204 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
10205 /* Unable to complete operation due to invalid speed */
10206 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
10208 * retry the command since the phy is not ready.
10209 * retry count is returned in opaque_0.
10210 * This is only valid for the first command and
10211 * this value will not change for successive calls.
10212 * but if a 0 is returned at any time then this should
10213 * be treated as an un recoverable failure,
10215 * retry interval in milli seconds is returned in opaque_1.
10216 * This specifies the time that user should wait before
10217 * issuing the next port_phy_cfg command.
10219 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
10220 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
10221 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
10222 uint8_t unused_0[7];
10223 } __attribute__((packed));
10225 /**********************
10226 * hwrm_port_phy_qcfg *
10227 **********************/
10230 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
10231 struct hwrm_port_phy_qcfg_input {
10232 /* The HWRM command request type. */
10235 * The completion ring to send the completion event on. This should
10236 * be the NQ ID returned from the `nq_alloc` HWRM command.
10238 uint16_t cmpl_ring;
10240 * The sequence ID is used by the driver for tracking multiple
10241 * commands. This ID is treated as opaque data by the firmware and
10242 * the value is returned in the `hwrm_resp_hdr` upon completion.
10246 * The target ID of the command:
10247 * * 0x0-0xFFF8 - The function ID
10248 * * 0xFFF8-0xFFFE - Reserved for internal processors
10251 uint16_t target_id;
10253 * A physical address pointer pointing to a host buffer that the
10254 * command's response data will be written. This can be either a host
10255 * physical address (HPA) or a guest physical address (GPA) and must
10256 * point to a physically contiguous block of memory.
10258 uint64_t resp_addr;
10259 /* Port ID of port that is to be queried. */
10261 uint8_t unused_0[6];
10262 } __attribute__((packed));
10264 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
10265 struct hwrm_port_phy_qcfg_output {
10266 /* The specific error status for the command. */
10267 uint16_t error_code;
10268 /* The HWRM command request type. */
10270 /* The sequence ID from the original command. */
10272 /* The length of the response data in number of bytes. */
10274 /* This value indicates the current link status. */
10276 /* There is no link or cable detected. */
10277 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
10278 /* There is no link, but a cable has been detected. */
10279 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
10280 /* There is a link. */
10281 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
10282 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
10283 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
10285 /* This value indicates the current link speed of the connection. */
10286 uint16_t link_speed;
10287 /* 100Mb link speed */
10288 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
10289 /* 1Gb link speed */
10290 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
10291 /* 2Gb link speed */
10292 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
10293 /* 25Gb link speed */
10294 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
10295 /* 10Gb link speed */
10296 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
10297 /* 20Mb link speed */
10298 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
10299 /* 25Gb link speed */
10300 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
10301 /* 40Gb link speed */
10302 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
10303 /* 50Gb link speed */
10304 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
10305 /* 100Gb link speed */
10306 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
10307 /* 10Mb link speed */
10308 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
10309 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
10310 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
10312 * This value is indicates the duplex of the current
10315 uint8_t duplex_cfg;
10316 /* Half Duplex connection. */
10317 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
10318 /* Full duplex connection. */
10319 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
10320 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
10321 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
10323 * This value is used to indicate the current
10324 * pause configuration. When autoneg is enabled, this value
10325 * represents the autoneg results of pause configuration.
10329 * When this bit is '1', Generation of tx pause messages
10330 * is supported. Disabled otherwise.
10332 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
10334 * When this bit is '1', Reception of rx pause messages
10335 * is supported. Disabled otherwise.
10337 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
10339 * The supported speeds for the port. This is a bit mask.
10340 * For each speed that is supported, the corrresponding
10341 * bit will be set to '1'.
10343 uint16_t support_speeds;
10344 /* 100Mb link speed (Half-duplex) */
10345 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
10347 /* 100Mb link speed (Full-duplex) */
10348 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
10350 /* 1Gb link speed (Half-duplex) */
10351 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
10353 /* 1Gb link speed (Full-duplex) */
10354 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
10356 /* 2Gb link speed */
10357 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
10359 /* 25Gb link speed */
10360 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
10362 /* 10Gb link speed */
10363 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
10365 /* 20Gb link speed */
10366 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
10368 /* 25Gb link speed */
10369 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
10371 /* 40Gb link speed */
10372 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
10374 /* 50Gb link speed */
10375 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
10377 /* 100Gb link speed */
10378 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
10380 /* 10Mb link speed (Half-duplex) */
10381 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
10383 /* 10Mb link speed (Full-duplex) */
10384 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
10387 * Current setting of forced link speed.
10388 * When the link speed is not being forced, this
10389 * value shall be set to 0.
10391 uint16_t force_link_speed;
10392 /* 100Mb link speed */
10393 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
10394 /* 1Gb link speed */
10395 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
10396 /* 2Gb link speed */
10397 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
10398 /* 25Gb link speed */
10399 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
10400 /* 10Gb link speed */
10401 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
10402 /* 20Mb link speed */
10403 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
10404 /* 25Gb link speed */
10405 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
10406 /* 40Gb link speed */
10407 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
10409 /* 50Gb link speed */
10410 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
10412 /* 100Gb link speed */
10413 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
10415 /* 10Mb link speed */
10416 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
10418 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
10419 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
10420 /* Current setting of auto negotiation mode. */
10422 /* Disable autoneg or autoneg disabled. No speeds are selected. */
10423 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
10424 /* Select all possible speeds for autoneg mode. */
10425 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
10427 * Select only the auto_link_speed speed for autoneg mode. This mode has
10428 * been DEPRECATED. An HWRM client should not use this mode.
10430 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
10432 * Select the auto_link_speed or any speed below that speed for autoneg.
10433 * This mode has been DEPRECATED. An HWRM client should not use this mode.
10435 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
10437 * Select the speeds based on the corresponding link speed mask value
10438 * that is provided.
10440 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
10441 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
10442 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
10444 * Current setting of pause autonegotiation.
10445 * Move autoneg_pause flag here.
10447 uint8_t auto_pause;
10449 * When this bit is '1', Generation of tx pause messages
10450 * has been requested. Disabled otherwise.
10452 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
10455 * When this bit is '1', Reception of rx pause messages
10456 * has been requested. Disabled otherwise.
10458 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
10461 * When set to 1, the advertisement of pause is enabled.
10463 * # When the auto_mode is not set to none and this flag is
10464 * set to 1, then the auto_pause bits on this port are being
10465 * advertised and autoneg pause results are being interpreted.
10466 * # When the auto_mode is not set to none and this
10467 * flag is set to 0, the pause is forced as indicated in
10468 * force_pause, and also advertised as auto_pause bits, but
10469 * the autoneg results are not interpreted since the pause
10470 * configuration is being forced.
10471 * # When the auto_mode is set to none and this flag is set to
10472 * 1, auto_pause bits should be ignored and should be set to 0.
10474 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
10477 * Current setting for auto_link_speed. This field is only
10478 * valid when auto_mode is set to "one_speed" or "one_or_below".
10480 uint16_t auto_link_speed;
10481 /* 100Mb link speed */
10482 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
10483 /* 1Gb link speed */
10484 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
10485 /* 2Gb link speed */
10486 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
10487 /* 25Gb link speed */
10488 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
10489 /* 10Gb link speed */
10490 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
10491 /* 20Mb link speed */
10492 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
10493 /* 25Gb link speed */
10494 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
10495 /* 40Gb link speed */
10496 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
10497 /* 50Gb link speed */
10498 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
10499 /* 100Gb link speed */
10500 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
10501 /* 10Mb link speed */
10502 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
10504 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
10505 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
10507 * Current setting for auto_link_speed_mask that is used to
10508 * advertise speeds during autonegotiation.
10509 * This field is only valid when auto_mode is set to "mask".
10510 * The speeds specified in this field shall be a subset of
10511 * supported speeds on this port.
10513 uint16_t auto_link_speed_mask;
10514 /* 100Mb link speed (Half-duplex) */
10515 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
10517 /* 100Mb link speed (Full-duplex) */
10518 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
10520 /* 1Gb link speed (Half-duplex) */
10521 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
10523 /* 1Gb link speed (Full-duplex) */
10524 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
10526 /* 2Gb link speed */
10527 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
10529 /* 25Gb link speed */
10530 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
10532 /* 10Gb link speed */
10533 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
10535 /* 20Gb link speed */
10536 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
10538 /* 25Gb link speed */
10539 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
10541 /* 40Gb link speed */
10542 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
10544 /* 50Gb link speed */
10545 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
10547 /* 100Gb link speed */
10548 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
10550 /* 10Mb link speed (Half-duplex) */
10551 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
10553 /* 10Mb link speed (Full-duplex) */
10554 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
10556 /* Current setting for wirespeed. */
10558 /* Wirespeed feature is disabled. */
10559 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
10560 /* Wirespeed feature is enabled. */
10561 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
10562 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
10563 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
10564 /* Current setting for loopback. */
10566 /* No loopback is selected. Normal operation. */
10567 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
10569 * The HW will be configured with local loopback such that
10570 * host data is sent back to the host without modification.
10572 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
10574 * The HW will be configured with remote loopback such that
10575 * port logic will send packets back out the transmitter that
10578 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
10580 * The HW will be configured with external loopback such that
10581 * host data is sent on the trasmitter and based on the external
10582 * loopback connection the data will be received without modification.
10584 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
10585 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
10586 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
10588 * Current setting of forced pause.
10589 * When the pause configuration is not being forced, then
10590 * this value shall be set to 0.
10592 uint8_t force_pause;
10594 * When this bit is '1', Generation of tx pause messages
10595 * is supported. Disabled otherwise.
10597 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
10599 * When this bit is '1', Reception of rx pause messages
10600 * is supported. Disabled otherwise.
10602 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
10604 * This value indicates the current status of the optics module on
10607 uint8_t module_status;
10608 /* Module is inserted and accepted */
10609 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
10611 /* Module is rejected and transmit side Laser is disabled. */
10612 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
10614 /* Module mismatch warning. */
10615 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
10617 /* Module is rejected and powered down. */
10618 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
10620 /* Module is not inserted. */
10621 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
10623 /* Module status is not applicable. */
10624 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
10626 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
10627 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
10628 /* Current setting for preemphasis. */
10629 uint32_t preemphasis;
10630 /* This field represents the major version of the PHY. */
10632 /* This field represents the minor version of the PHY. */
10634 /* This field represents the build version of the PHY. */
10636 /* This value represents a PHY type. */
10639 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
10642 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
10644 /* BASE-KR4 (Deprecated) */
10645 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
10648 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
10651 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
10653 /* BASE-KR2 (Deprecated) */
10654 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
10657 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
10660 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
10663 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
10665 /* EEE capable BASE-T */
10666 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
10668 /* SGMII connected external PHY */
10669 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
10671 /* 25G_BASECR_CA_L */
10672 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
10674 /* 25G_BASECR_CA_S */
10675 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
10677 /* 25G_BASECR_CA_N */
10678 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
10681 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
10684 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
10687 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
10690 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
10693 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
10695 /* 100G_BASESR10 */
10696 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
10699 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
10702 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
10705 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
10708 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
10710 /* 40G_ACTIVE_CABLE */
10711 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
10714 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
10717 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
10720 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
10722 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
10723 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
10724 /* This value represents a media type. */
10725 uint8_t media_type;
10727 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
10729 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
10730 /* Direct Attached Copper */
10731 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
10733 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
10734 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
10735 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
10736 /* This value represents a transceiver type. */
10737 uint8_t xcvr_pkg_type;
10738 /* PHY and MAC are in the same package */
10739 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
10741 /* PHY and MAC are in different packages */
10742 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
10744 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
10745 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
10746 uint8_t eee_config_phy_addr;
10747 /* This field represents PHY address. */
10748 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
10750 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
10752 * This field represents flags related to EEE configuration.
10753 * These EEE configuration flags are valid only when the
10754 * auto_mode is not set to none (in other words autonegotiation
10757 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
10759 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
10761 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
10762 * Speeds for autoneg with EEE mode enabled
10763 * are based on eee_link_speed_mask.
10765 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
10768 * This flag is valid only when eee_enabled is set to 1.
10770 * # If eee_enabled is set to 0, then EEE mode is disabled
10771 * and this flag shall be ignored.
10772 * # If eee_enabled is set to 1 and this flag is set to 1,
10773 * then Energy Efficient Ethernet (EEE) mode is enabled
10775 * # If eee_enabled is set to 1 and this flag is set to 0,
10776 * then Energy Efficient Ethernet (EEE) mode is enabled
10777 * but is currently not in use.
10779 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
10782 * This flag is valid only when eee_enabled is set to 1.
10784 * # If eee_enabled is set to 0, then EEE mode is disabled
10785 * and this flag shall be ignored.
10786 * # If eee_enabled is set to 1 and this flag is set to 1,
10787 * then Energy Efficient Ethernet (EEE) mode is enabled
10788 * and TX LPI is enabled.
10789 * # If eee_enabled is set to 1 and this flag is set to 0,
10790 * then Energy Efficient Ethernet (EEE) mode is enabled
10791 * but TX LPI is disabled.
10793 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
10796 * When set to 1, the parallel detection is used to determine
10797 * the speed of the link partner.
10799 * Parallel detection is used when a autonegotiation capable
10800 * device is connected to a link parter that is not capable
10801 * of autonegotiation.
10803 uint8_t parallel_detect;
10805 * When set to 1, the parallel detection is used to determine
10806 * the speed of the link partner.
10808 * Parallel detection is used when a autonegotiation capable
10809 * device is connected to a link parter that is not capable
10810 * of autonegotiation.
10812 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
10814 * The advertised speeds for the port by the link partner.
10815 * Each advertised speed will be set to '1'.
10817 uint16_t link_partner_adv_speeds;
10818 /* 100Mb link speed (Half-duplex) */
10819 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
10821 /* 100Mb link speed (Full-duplex) */
10822 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
10824 /* 1Gb link speed (Half-duplex) */
10825 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
10827 /* 1Gb link speed (Full-duplex) */
10828 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
10830 /* 2Gb link speed */
10831 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
10833 /* 25Gb link speed */
10834 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
10836 /* 10Gb link speed */
10837 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
10839 /* 20Gb link speed */
10840 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
10842 /* 25Gb link speed */
10843 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
10845 /* 40Gb link speed */
10846 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
10848 /* 50Gb link speed */
10849 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
10851 /* 100Gb link speed */
10852 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
10854 /* 10Mb link speed (Half-duplex) */
10855 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
10857 /* 10Mb link speed (Full-duplex) */
10858 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
10861 * The advertised autoneg for the port by the link partner.
10862 * This field is deprecated and should be set to 0.
10864 uint8_t link_partner_adv_auto_mode;
10865 /* Disable autoneg or autoneg disabled. No speeds are selected. */
10866 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
10868 /* Select all possible speeds for autoneg mode. */
10869 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
10872 * Select only the auto_link_speed speed for autoneg mode. This mode has
10873 * been DEPRECATED. An HWRM client should not use this mode.
10875 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
10878 * Select the auto_link_speed or any speed below that speed for autoneg.
10879 * This mode has been DEPRECATED. An HWRM client should not use this mode.
10881 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
10884 * Select the speeds based on the corresponding link speed mask value
10885 * that is provided.
10887 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
10889 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
10890 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
10891 /* The advertised pause settings on the port by the link partner. */
10892 uint8_t link_partner_adv_pause;
10894 * When this bit is '1', Generation of tx pause messages
10895 * is supported. Disabled otherwise.
10897 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
10900 * When this bit is '1', Reception of rx pause messages
10901 * is supported. Disabled otherwise.
10903 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
10906 * Current setting for link speed mask that is used to
10907 * advertise speeds during autonegotiation when EEE is enabled.
10908 * This field is valid only when eee_enabled flags is set to 1.
10909 * The speeds specified in this field shall be a subset of
10910 * speeds specified in auto_link_speed_mask.
10912 uint16_t adv_eee_link_speed_mask;
10914 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
10916 /* 100Mb link speed (Full-duplex) */
10917 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
10920 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
10922 /* 1Gb link speed (Full-duplex) */
10923 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
10926 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
10929 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
10931 /* 10Gb link speed */
10932 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
10935 * Current setting for link speed mask that is advertised by
10936 * the link partner when EEE is enabled.
10937 * This field is valid only when eee_enabled flags is set to 1.
10939 uint16_t link_partner_adv_eee_link_speed_mask;
10941 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
10943 /* 100Mb link speed (Full-duplex) */
10944 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
10947 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
10949 /* 1Gb link speed (Full-duplex) */
10950 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
10953 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
10956 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
10958 /* 10Gb link speed */
10959 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
10961 uint32_t xcvr_identifier_type_tx_lpi_timer;
10963 * Current setting of TX LPI timer in microseconds.
10964 * This field is valid only when_eee_enabled flag is set to 1
10965 * and tx_lpi_enabled is set to 1.
10967 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
10969 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
10970 /* This value represents transceiver identifier type. */
10971 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
10972 UINT32_C(0xff000000)
10973 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
10975 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
10976 (UINT32_C(0x0) << 24)
10977 /* SFP/SFP+/SFP28 */
10978 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
10979 (UINT32_C(0x3) << 24)
10981 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
10982 (UINT32_C(0xc) << 24)
10984 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
10985 (UINT32_C(0xd) << 24)
10987 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
10988 (UINT32_C(0x11) << 24)
10989 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
10990 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
10992 * This value represents the current configuration of
10993 * Forward Error Correction (FEC) on the port.
10997 * When set to 1, then FEC is not supported on this port. If this flag
10998 * is set to 1, then all other FEC configuration flags shall be ignored.
10999 * When set to 0, then FEC is supported as indicated by other
11000 * configuration flags.
11001 * If no cable is attached and the HWRM does not yet know the FEC
11002 * capability, then the HWRM shall set this flag to 1 when reporting
11005 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
11008 * When set to 1, then FEC autonegotiation is supported on this port.
11009 * When set to 0, then FEC autonegotiation is not supported on this port.
11011 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
11014 * When set to 1, then FEC autonegotiation is enabled on this port.
11015 * When set to 0, then FEC autonegotiation is disabled if supported.
11016 * This flag should be ignored if FEC autonegotiation is not supported on this port.
11018 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
11021 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
11022 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
11024 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
11027 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
11028 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
11029 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
11031 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
11034 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
11035 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
11037 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
11040 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
11041 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
11042 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
11044 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
11047 * This value is indicates the duplex of the current
11048 * connection state.
11050 uint8_t duplex_state;
11051 /* Half Duplex connection. */
11052 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
11053 /* Full duplex connection. */
11054 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
11055 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
11056 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
11057 /* Option flags fields. */
11058 uint8_t option_flags;
11059 /* When this bit is '1', Media auto detect is enabled. */
11060 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
11063 * Up to 16 bytes of null padded ASCII string representing
11065 * If the string is set to null, then the vendor name is not
11068 char phy_vendor_name[16];
11070 * Up to 16 bytes of null padded ASCII string that
11071 * identifies vendor specific part number of the PHY.
11072 * If the string is set to null, then the vendor specific
11073 * part number is not available.
11075 char phy_vendor_partnumber[16];
11076 uint8_t unused_2[7];
11078 * This field is used in Output records to indicate that the output
11079 * is completely written to RAM. This field should be read as '1'
11080 * to indicate that the output has been completely written.
11081 * When writing a command completion or response to an internal processor,
11082 * the order of writes has to be such that this field is written last.
11085 } __attribute__((packed));
11087 /*********************
11088 * hwrm_port_mac_cfg *
11089 *********************/
11092 /* hwrm_port_mac_cfg_input (size:320b/40B) */
11093 struct hwrm_port_mac_cfg_input {
11094 /* The HWRM command request type. */
11097 * The completion ring to send the completion event on. This should
11098 * be the NQ ID returned from the `nq_alloc` HWRM command.
11100 uint16_t cmpl_ring;
11102 * The sequence ID is used by the driver for tracking multiple
11103 * commands. This ID is treated as opaque data by the firmware and
11104 * the value is returned in the `hwrm_resp_hdr` upon completion.
11108 * The target ID of the command:
11109 * * 0x0-0xFFF8 - The function ID
11110 * * 0xFFF8-0xFFFE - Reserved for internal processors
11113 uint16_t target_id;
11115 * A physical address pointer pointing to a host buffer that the
11116 * command's response data will be written. This can be either a host
11117 * physical address (HPA) or a guest physical address (GPA) and must
11118 * point to a physically contiguous block of memory.
11120 uint64_t resp_addr;
11122 * In this field, there are a number of CoS mappings related flags
11123 * that are used to configure CoS mappings and their corresponding
11124 * priorities in the hardware.
11125 * For the priorities of CoS mappings, the HWRM uses the following
11126 * priority order (high to low) by default:
11129 * # tunnel_vlan_pri
11132 * A subset of CoS mappings can be enabled.
11133 * If a priority is not specified for an enabled CoS mapping, the
11134 * priority will be assigned in the above order for the enabled CoS
11135 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
11136 * enabled and their priorities are not specified, the following
11137 * priority order (high to low) will be used by the HWRM:
11142 * vlan_pri CoS mapping together with default CoS with lower priority
11143 * are enabled by default by the HWRM.
11147 * When this bit is '1', this command will configure
11148 * the MAC to match the current link state of the PHY.
11149 * If the link is not established on the PHY, then this
11150 * bit has no effect.
11152 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
11155 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11156 * is requested to be enabled.
11158 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
11161 * When this bit is set to '1', tunnel VLAN PRI field to
11162 * CoS mapping is requested to be enabled.
11164 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
11167 * When this bit is set to '1', the IP DSCP to CoS mapping is
11168 * requested to be enabled.
11170 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
11173 * When this bit is '1', the HWRM is requested to
11174 * enable timestamp capture capability on the receive side
11177 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
11180 * When this bit is '1', the HWRM is requested to
11181 * disable timestamp capture capability on the receive side
11184 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
11187 * When this bit is '1', the HWRM is requested to
11188 * enable timestamp capture capability on the transmit side
11191 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
11194 * When this bit is '1', the HWRM is requested to
11195 * disable timestamp capture capability on the transmit side
11198 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
11201 * When this bit is '1', the Out-Of-Box WoL is requested to
11202 * be enabled on this port.
11204 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
11207 * When this bit is '1', the the Out-Of-Box WoL is requested to
11208 * be disabled on this port.
11210 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
11213 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11214 * is requested to be disabled.
11216 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
11219 * When this bit is set to '1', tunnel VLAN PRI field to
11220 * CoS mapping is requested to be disabled.
11222 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
11225 * When this bit is set to '1', the IP DSCP to CoS mapping is
11226 * requested to be disabled.
11228 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
11232 * This bit must be '1' for the ipg field to be
11235 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
11238 * This bit must be '1' for the lpbk field to be
11241 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
11244 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
11247 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
11250 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
11253 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
11256 * This bit must be '1' for the dscp2cos_map_pri field to be
11259 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
11262 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
11265 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
11268 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
11271 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
11274 * This bit must be '1' for the cos_field_cfg field to be
11277 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
11279 /* Port ID of port that is to be configured. */
11282 * This value is used to configure the minimum IPG that will
11283 * be sent between packets by this port.
11286 /* This value controls the loopback setting for the MAC. */
11288 /* No loopback is selected. Normal operation. */
11289 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
11291 * The HW will be configured with local loopback such that
11292 * host data is sent back to the host without modification.
11294 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
11296 * The HW will be configured with remote loopback such that
11297 * port logic will send packets back out the transmitter that
11300 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
11301 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
11302 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
11304 * This value controls the priority setting of VLAN PRI to CoS
11305 * mapping based on VLAN Tags of inner packet headers of
11306 * tunneled packets or packet headers of non-tunneled packets.
11308 * # Each XXX_pri variable shall have a unique priority value
11309 * when it is being specified.
11310 * # When comparing priorities of mappings, higher value
11311 * indicates higher priority.
11312 * For example, a value of 0-3 is returned where 0 is being
11313 * the lowest priority and 3 is being the highest priority.
11315 uint8_t vlan_pri2cos_map_pri;
11316 /* Reserved field. */
11319 * This value controls the priority setting of VLAN PRI to CoS
11320 * mapping based on VLAN Tags of tunneled header.
11321 * This mapping only applies when tunneled headers
11324 * # Each XXX_pri variable shall have a unique priority value
11325 * when it is being specified.
11326 * # When comparing priorities of mappings, higher value
11327 * indicates higher priority.
11328 * For example, a value of 0-3 is returned where 0 is being
11329 * the lowest priority and 3 is being the highest priority.
11331 uint8_t tunnel_pri2cos_map_pri;
11333 * This value controls the priority setting of IP DSCP to CoS
11334 * mapping based on inner IP header of tunneled packets or
11335 * IP header of non-tunneled packets.
11337 * # Each XXX_pri variable shall have a unique priority value
11338 * when it is being specified.
11339 * # When comparing priorities of mappings, higher value
11340 * indicates higher priority.
11341 * For example, a value of 0-3 is returned where 0 is being
11342 * the lowest priority and 3 is being the highest priority.
11344 uint8_t dscp2pri_map_pri;
11346 * This is a 16-bit bit mask that is used to request a
11347 * specific configuration of time stamp capture of PTP messages
11348 * on the receive side of this port.
11349 * This field shall be ignored if the ptp_rx_ts_capture_enable
11350 * flag is not set in this command.
11351 * Otherwise, if bit 'i' is set, then the HWRM is being
11352 * requested to configure the receive side of the port to
11353 * capture the time stamp of every received PTP message
11354 * with messageType field value set to i.
11356 uint16_t rx_ts_capture_ptp_msg_type;
11358 * This is a 16-bit bit mask that is used to request a
11359 * specific configuration of time stamp capture of PTP messages
11360 * on the transmit side of this port.
11361 * This field shall be ignored if the ptp_tx_ts_capture_enable
11362 * flag is not set in this command.
11363 * Otherwise, if bit 'i' is set, then the HWRM is being
11364 * requested to configure the transmit sied of the port to
11365 * capture the time stamp of every transmitted PTP message
11366 * with messageType field value set to i.
11368 uint16_t tx_ts_capture_ptp_msg_type;
11369 /* Configuration of CoS fields. */
11370 uint8_t cos_field_cfg;
11372 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
11375 * This field is used to specify selection of VLAN PRI value
11376 * based on whether one or two VLAN Tags are present in
11377 * the inner packet headers of tunneled packets or
11378 * non-tunneled packets.
11379 * This field is valid only if inner VLAN PRI to CoS mapping
11381 * If VLAN PRI to CoS mapping is not enabled, then this
11382 * field shall be ignored.
11384 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
11386 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
11389 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11390 * present in the inner packet headers
11392 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
11393 (UINT32_C(0x0) << 1)
11395 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11396 * present in the inner packet headers.
11397 * No VLAN PRI shall be selected for this configuration
11398 * if only one VLAN Tag is present in the inner
11401 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
11402 (UINT32_C(0x1) << 1)
11404 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11405 * are present in the inner packet headers
11407 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
11408 (UINT32_C(0x2) << 1)
11410 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
11411 (UINT32_C(0x3) << 1)
11412 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
11413 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
11415 * This field is used to specify selection of tunnel VLAN
11416 * PRI value based on whether one or two VLAN Tags are
11417 * present in tunnel headers.
11418 * This field is valid only if tunnel VLAN PRI to CoS mapping
11420 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
11421 * field shall be ignored.
11423 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
11425 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
11428 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11429 * present in the tunnel packet headers
11431 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
11432 (UINT32_C(0x0) << 3)
11434 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11435 * present in the tunnel packet headers.
11436 * No tunnel VLAN PRI shall be selected for this
11437 * configuration if only one VLAN Tag is present in
11438 * the tunnel packet headers.
11440 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
11441 (UINT32_C(0x1) << 3)
11443 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11444 * are present in the tunnel packet headers
11446 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
11447 (UINT32_C(0x2) << 3)
11449 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
11450 (UINT32_C(0x3) << 3)
11451 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
11452 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
11454 * This field shall be used to provide default CoS value
11455 * that has been configured on this port.
11456 * This field is valid only if default CoS mapping
11458 * If default CoS mapping is not enabled, then this
11459 * field shall be ignored.
11461 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
11463 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
11465 uint8_t unused_0[3];
11466 } __attribute__((packed));
11468 /* hwrm_port_mac_cfg_output (size:128b/16B) */
11469 struct hwrm_port_mac_cfg_output {
11470 /* The specific error status for the command. */
11471 uint16_t error_code;
11472 /* The HWRM command request type. */
11474 /* The sequence ID from the original command. */
11476 /* The length of the response data in number of bytes. */
11479 * This is the configured maximum length of Ethernet packet
11480 * payload that is allowed to be received on the port.
11481 * This value does not include the number of bytes used by
11482 * Ethernet header and trailer (CRC).
11486 * This is the configured maximum length of Ethernet packet
11487 * payload that is allowed to be transmitted on the port.
11488 * This value does not include the number of bytes used by
11489 * Ethernet header and trailer (CRC).
11492 /* Current configuration of the IPG value. */
11494 /* Current value of the loopback value. */
11496 /* No loopback is selected. Normal operation. */
11497 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11499 * The HW will be configured with local loopback such that
11500 * host data is sent back to the host without modification.
11502 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11504 * The HW will be configured with remote loopback such that
11505 * port logic will send packets back out the transmitter that
11508 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11509 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
11510 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
11513 * This field is used in Output records to indicate that the output
11514 * is completely written to RAM. This field should be read as '1'
11515 * to indicate that the output has been completely written.
11516 * When writing a command completion or response to an internal processor,
11517 * the order of writes has to be such that this field is written last.
11520 } __attribute__((packed));
11522 /**********************
11523 * hwrm_port_mac_qcfg *
11524 **********************/
11527 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
11528 struct hwrm_port_mac_qcfg_input {
11529 /* The HWRM command request type. */
11532 * The completion ring to send the completion event on. This should
11533 * be the NQ ID returned from the `nq_alloc` HWRM command.
11535 uint16_t cmpl_ring;
11537 * The sequence ID is used by the driver for tracking multiple
11538 * commands. This ID is treated as opaque data by the firmware and
11539 * the value is returned in the `hwrm_resp_hdr` upon completion.
11543 * The target ID of the command:
11544 * * 0x0-0xFFF8 - The function ID
11545 * * 0xFFF8-0xFFFE - Reserved for internal processors
11548 uint16_t target_id;
11550 * A physical address pointer pointing to a host buffer that the
11551 * command's response data will be written. This can be either a host
11552 * physical address (HPA) or a guest physical address (GPA) and must
11553 * point to a physically contiguous block of memory.
11555 uint64_t resp_addr;
11556 /* Port ID of port that is to be configured. */
11558 uint8_t unused_0[6];
11559 } __attribute__((packed));
11561 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
11562 struct hwrm_port_mac_qcfg_output {
11563 /* The specific error status for the command. */
11564 uint16_t error_code;
11565 /* The HWRM command request type. */
11567 /* The sequence ID from the original command. */
11569 /* The length of the response data in number of bytes. */
11572 * This is the configured maximum length of Ethernet packet
11573 * payload that is allowed to be received on the port.
11574 * This value does not include the number of bytes used by the
11575 * Ethernet header and trailer (CRC).
11579 * This is the configured maximum length of Ethernet packet
11580 * payload that is allowed to be transmitted on the port.
11581 * This value does not include the number of bytes used by the
11582 * Ethernet header and trailer (CRC).
11586 * The minimum IPG that will
11587 * be sent between packets by this port.
11590 /* The loopback setting for the MAC. */
11592 /* No loopback is selected. Normal operation. */
11593 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11595 * The HW will be configured with local loopback such that
11596 * host data is sent back to the host without modification.
11598 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11600 * The HW will be configured with remote loopback such that
11601 * port logic will send packets back out the transmitter that
11604 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11605 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
11606 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
11608 * Priority setting for VLAN PRI to CoS mapping.
11609 * # Each XXX_pri variable shall have a unique priority value
11610 * when it is being used.
11611 * # When comparing priorities of mappings, higher value
11612 * indicates higher priority.
11613 * For example, a value of 0-3 is returned where 0 is being
11614 * the lowest priority and 3 is being the highest priority.
11615 * # If the correspoding CoS mapping is not enabled, then this
11616 * field should be ignored.
11617 * # This value indicates the normalized priority value retained
11620 uint8_t vlan_pri2cos_map_pri;
11622 * In this field, a number of CoS mappings related flags
11623 * are used to indicate configured CoS mappings.
11627 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11630 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
11633 * When this bit is set to '1', tunnel VLAN PRI field to
11634 * CoS mapping is enabled.
11636 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
11639 * When this bit is set to '1', the IP DSCP to CoS mapping is
11642 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
11645 * When this bit is '1', the Out-Of-Box WoL is enabled on this
11648 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
11650 /* When this bit is '1', PTP is enabled for RX on this port. */
11651 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
11653 /* When this bit is '1', PTP is enabled for TX on this port. */
11654 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
11657 * Priority setting for tunnel VLAN PRI to CoS mapping.
11658 * # Each XXX_pri variable shall have a unique priority value
11659 * when it is being used.
11660 * # When comparing priorities of mappings, higher value
11661 * indicates higher priority.
11662 * For example, a value of 0-3 is returned where 0 is being
11663 * the lowest priority and 3 is being the highest priority.
11664 * # If the correspoding CoS mapping is not enabled, then this
11665 * field should be ignored.
11666 * # This value indicates the normalized priority value retained
11669 uint8_t tunnel_pri2cos_map_pri;
11671 * Priority setting for DSCP to PRI mapping.
11672 * # Each XXX_pri variable shall have a unique priority value
11673 * when it is being used.
11674 * # When comparing priorities of mappings, higher value
11675 * indicates higher priority.
11676 * For example, a value of 0-3 is returned where 0 is being
11677 * the lowest priority and 3 is being the highest priority.
11678 * # If the correspoding CoS mapping is not enabled, then this
11679 * field should be ignored.
11680 * # This value indicates the normalized priority value retained
11683 uint8_t dscp2pri_map_pri;
11685 * This is a 16-bit bit mask that represents the
11686 * current configuration of time stamp capture of PTP messages
11687 * on the receive side of this port.
11688 * If bit 'i' is set, then the receive side of the port
11689 * is configured to capture the time stamp of every
11690 * received PTP message with messageType field value set
11692 * If all bits are set to 0 (i.e. field value set 0),
11693 * then the receive side of the port is not configured
11694 * to capture timestamp for PTP messages.
11695 * If all bits are set to 1, then the receive side of the
11696 * port is configured to capture timestamp for all PTP
11699 uint16_t rx_ts_capture_ptp_msg_type;
11701 * This is a 16-bit bit mask that represents the
11702 * current configuration of time stamp capture of PTP messages
11703 * on the transmit side of this port.
11704 * If bit 'i' is set, then the transmit side of the port
11705 * is configured to capture the time stamp of every
11706 * received PTP message with messageType field value set
11708 * If all bits are set to 0 (i.e. field value set 0),
11709 * then the transmit side of the port is not configured
11710 * to capture timestamp for PTP messages.
11711 * If all bits are set to 1, then the transmit side of the
11712 * port is configured to capture timestamp for all PTP
11715 uint16_t tx_ts_capture_ptp_msg_type;
11716 /* Configuration of CoS fields. */
11717 uint8_t cos_field_cfg;
11719 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
11722 * This field is used for selecting VLAN PRI value
11723 * based on whether one or two VLAN Tags are present in
11724 * the inner packet headers of tunneled packets or
11725 * non-tunneled packets.
11727 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
11729 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
11732 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11733 * present in the inner packet headers
11735 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
11736 (UINT32_C(0x0) << 1)
11738 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11739 * present in the inner packet headers.
11740 * No VLAN PRI is selected for this configuration
11741 * if only one VLAN Tag is present in the inner
11744 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
11745 (UINT32_C(0x1) << 1)
11747 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11748 * are present in the inner packet headers
11750 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
11751 (UINT32_C(0x2) << 1)
11753 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
11754 (UINT32_C(0x3) << 1)
11755 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
11756 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
11758 * This field is used for selecting tunnel VLAN PRI value
11759 * based on whether one or two VLAN Tags are present in
11760 * the tunnel headers of tunneled packets. This selection
11761 * does not apply to non-tunneled packets.
11763 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
11765 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
11768 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11769 * present in the tunnel packet headers
11771 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
11772 (UINT32_C(0x0) << 3)
11774 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11775 * present in the tunnel packet headers.
11776 * No VLAN PRI is selected for this configuration
11777 * if only one VLAN Tag is present in the tunnel
11780 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
11781 (UINT32_C(0x1) << 3)
11783 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11784 * are present in the tunnel packet headers
11786 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
11787 (UINT32_C(0x2) << 3)
11789 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
11790 (UINT32_C(0x3) << 3)
11791 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
11792 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
11794 * This field is used to provide default CoS value that
11795 * has been configured on this port.
11797 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
11799 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
11802 * This field is used in Output records to indicate that the output
11803 * is completely written to RAM. This field should be read as '1'
11804 * to indicate that the output has been completely written.
11805 * When writing a command completion or response to an internal processor,
11806 * the order of writes has to be such that this field is written last.
11809 } __attribute__((packed));
11811 /**************************
11812 * hwrm_port_mac_ptp_qcfg *
11813 **************************/
11816 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
11817 struct hwrm_port_mac_ptp_qcfg_input {
11818 /* The HWRM command request type. */
11821 * The completion ring to send the completion event on. This should
11822 * be the NQ ID returned from the `nq_alloc` HWRM command.
11824 uint16_t cmpl_ring;
11826 * The sequence ID is used by the driver for tracking multiple
11827 * commands. This ID is treated as opaque data by the firmware and
11828 * the value is returned in the `hwrm_resp_hdr` upon completion.
11832 * The target ID of the command:
11833 * * 0x0-0xFFF8 - The function ID
11834 * * 0xFFF8-0xFFFE - Reserved for internal processors
11837 uint16_t target_id;
11839 * A physical address pointer pointing to a host buffer that the
11840 * command's response data will be written. This can be either a host
11841 * physical address (HPA) or a guest physical address (GPA) and must
11842 * point to a physically contiguous block of memory.
11844 uint64_t resp_addr;
11845 /* Port ID of port that is being queried. */
11847 uint8_t unused_0[6];
11848 } __attribute__((packed));
11850 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
11851 struct hwrm_port_mac_ptp_qcfg_output {
11852 /* The specific error status for the command. */
11853 uint16_t error_code;
11854 /* The HWRM command request type. */
11856 /* The sequence ID from the original command. */
11858 /* The length of the response data in number of bytes. */
11861 * In this field, a number of PTP related flags
11862 * are used to indicate configured PTP capabilities.
11866 * When this bit is set to '1', the PTP related registers are
11867 * directly accessible by the host.
11869 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
11872 * When this bit is set to '1', the PTP information is accessible
11873 * via HWRM commands.
11875 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
11877 uint8_t unused_0[3];
11878 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
11879 uint32_t rx_ts_reg_off_lower;
11880 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
11881 uint32_t rx_ts_reg_off_upper;
11882 /* Offset of the PTP register for the sequence ID for RX. */
11883 uint32_t rx_ts_reg_off_seq_id;
11884 /* Offset of the first PTP source ID for RX. */
11885 uint32_t rx_ts_reg_off_src_id_0;
11886 /* Offset of the second PTP source ID for RX. */
11887 uint32_t rx_ts_reg_off_src_id_1;
11888 /* Offset of the third PTP source ID for RX. */
11889 uint32_t rx_ts_reg_off_src_id_2;
11890 /* Offset of the domain ID for RX. */
11891 uint32_t rx_ts_reg_off_domain_id;
11892 /* Offset of the PTP FIFO register for RX. */
11893 uint32_t rx_ts_reg_off_fifo;
11894 /* Offset of the PTP advance FIFO register for RX. */
11895 uint32_t rx_ts_reg_off_fifo_adv;
11896 /* PTP timestamp granularity for RX. */
11897 uint32_t rx_ts_reg_off_granularity;
11898 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
11899 uint32_t tx_ts_reg_off_lower;
11900 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
11901 uint32_t tx_ts_reg_off_upper;
11902 /* Offset of the PTP register for the sequence ID for TX. */
11903 uint32_t tx_ts_reg_off_seq_id;
11904 /* Offset of the PTP FIFO register for TX. */
11905 uint32_t tx_ts_reg_off_fifo;
11906 /* PTP timestamp granularity for TX. */
11907 uint32_t tx_ts_reg_off_granularity;
11908 uint8_t unused_1[7];
11910 * This field is used in Output records to indicate that the output
11911 * is completely written to RAM. This field should be read as '1'
11912 * to indicate that the output has been completely written.
11913 * When writing a command completion or response to an internal processor,
11914 * the order of writes has to be such that this field is written last.
11917 } __attribute__((packed));
11919 /********************
11920 * hwrm_port_qstats *
11921 ********************/
11924 /* hwrm_port_qstats_input (size:320b/40B) */
11925 struct hwrm_port_qstats_input {
11926 /* The HWRM command request type. */
11929 * The completion ring to send the completion event on. This should
11930 * be the NQ ID returned from the `nq_alloc` HWRM command.
11932 uint16_t cmpl_ring;
11934 * The sequence ID is used by the driver for tracking multiple
11935 * commands. This ID is treated as opaque data by the firmware and
11936 * the value is returned in the `hwrm_resp_hdr` upon completion.
11940 * The target ID of the command:
11941 * * 0x0-0xFFF8 - The function ID
11942 * * 0xFFF8-0xFFFE - Reserved for internal processors
11945 uint16_t target_id;
11947 * A physical address pointer pointing to a host buffer that the
11948 * command's response data will be written. This can be either a host
11949 * physical address (HPA) or a guest physical address (GPA) and must
11950 * point to a physically contiguous block of memory.
11952 uint64_t resp_addr;
11953 /* Port ID of port that is being queried. */
11955 uint8_t unused_0[6];
11957 * This is the host address where
11958 * Tx port statistics will be stored
11960 uint64_t tx_stat_host_addr;
11962 * This is the host address where
11963 * Rx port statistics will be stored
11965 uint64_t rx_stat_host_addr;
11966 } __attribute__((packed));
11968 /* hwrm_port_qstats_output (size:128b/16B) */
11969 struct hwrm_port_qstats_output {
11970 /* The specific error status for the command. */
11971 uint16_t error_code;
11972 /* The HWRM command request type. */
11974 /* The sequence ID from the original command. */
11976 /* The length of the response data in number of bytes. */
11978 /* The size of TX port statistics block in bytes. */
11979 uint16_t tx_stat_size;
11980 /* The size of RX port statistics block in bytes. */
11981 uint16_t rx_stat_size;
11982 uint8_t unused_0[3];
11984 * This field is used in Output records to indicate that the output
11985 * is completely written to RAM. This field should be read as '1'
11986 * to indicate that the output has been completely written.
11987 * When writing a command completion or response to an internal processor,
11988 * the order of writes has to be such that this field is written last.
11991 } __attribute__((packed));
11993 /************************
11994 * hwrm_port_qstats_ext *
11995 ************************/
11998 /* hwrm_port_qstats_ext_input (size:320b/40B) */
11999 struct hwrm_port_qstats_ext_input {
12000 /* The HWRM command request type. */
12003 * The completion ring to send the completion event on. This should
12004 * be the NQ ID returned from the `nq_alloc` HWRM command.
12006 uint16_t cmpl_ring;
12008 * The sequence ID is used by the driver for tracking multiple
12009 * commands. This ID is treated as opaque data by the firmware and
12010 * the value is returned in the `hwrm_resp_hdr` upon completion.
12014 * The target ID of the command:
12015 * * 0x0-0xFFF8 - The function ID
12016 * * 0xFFF8-0xFFFE - Reserved for internal processors
12019 uint16_t target_id;
12021 * A physical address pointer pointing to a host buffer that the
12022 * command's response data will be written. This can be either a host
12023 * physical address (HPA) or a guest physical address (GPA) and must
12024 * point to a physically contiguous block of memory.
12026 uint64_t resp_addr;
12027 /* Port ID of port that is being queried. */
12030 * The size of TX port extended
12031 * statistics block in bytes.
12033 uint16_t tx_stat_size;
12035 * The size of RX port extended
12036 * statistics block in bytes
12038 uint16_t rx_stat_size;
12039 uint8_t unused_0[2];
12041 * This is the host address where
12042 * Tx port statistics will be stored
12044 uint64_t tx_stat_host_addr;
12046 * This is the host address where
12047 * Rx port statistics will be stored
12049 uint64_t rx_stat_host_addr;
12050 } __attribute__((packed));
12052 /* hwrm_port_qstats_ext_output (size:128b/16B) */
12053 struct hwrm_port_qstats_ext_output {
12054 /* The specific error status for the command. */
12055 uint16_t error_code;
12056 /* The HWRM command request type. */
12058 /* The sequence ID from the original command. */
12060 /* The length of the response data in number of bytes. */
12062 /* The size of TX port statistics block in bytes. */
12063 uint16_t tx_stat_size;
12064 /* The size of RX port statistics block in bytes. */
12065 uint16_t rx_stat_size;
12066 uint8_t unused_0[3];
12068 * This field is used in Output records to indicate that the output
12069 * is completely written to RAM. This field should be read as '1'
12070 * to indicate that the output has been completely written.
12071 * When writing a command completion or response to an internal processor,
12072 * the order of writes has to be such that this field is written last.
12075 } __attribute__((packed));
12077 /*************************
12078 * hwrm_port_lpbk_qstats *
12079 *************************/
12082 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
12083 struct hwrm_port_lpbk_qstats_input {
12084 /* The HWRM command request type. */
12087 * The completion ring to send the completion event on. This should
12088 * be the NQ ID returned from the `nq_alloc` HWRM command.
12090 uint16_t cmpl_ring;
12092 * The sequence ID is used by the driver for tracking multiple
12093 * commands. This ID is treated as opaque data by the firmware and
12094 * the value is returned in the `hwrm_resp_hdr` upon completion.
12098 * The target ID of the command:
12099 * * 0x0-0xFFF8 - The function ID
12100 * * 0xFFF8-0xFFFE - Reserved for internal processors
12103 uint16_t target_id;
12105 * A physical address pointer pointing to a host buffer that the
12106 * command's response data will be written. This can be either a host
12107 * physical address (HPA) or a guest physical address (GPA) and must
12108 * point to a physically contiguous block of memory.
12110 uint64_t resp_addr;
12111 } __attribute__((packed));
12113 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
12114 struct hwrm_port_lpbk_qstats_output {
12115 /* The specific error status for the command. */
12116 uint16_t error_code;
12117 /* The HWRM command request type. */
12119 /* The sequence ID from the original command. */
12121 /* The length of the response data in number of bytes. */
12123 /* Number of transmitted unicast frames */
12124 uint64_t lpbk_ucast_frames;
12125 /* Number of transmitted multicast frames */
12126 uint64_t lpbk_mcast_frames;
12127 /* Number of transmitted broadcast frames */
12128 uint64_t lpbk_bcast_frames;
12129 /* Number of transmitted bytes for unicast traffic */
12130 uint64_t lpbk_ucast_bytes;
12131 /* Number of transmitted bytes for multicast traffic */
12132 uint64_t lpbk_mcast_bytes;
12133 /* Number of transmitted bytes for broadcast traffic */
12134 uint64_t lpbk_bcast_bytes;
12135 /* Total Tx Drops for loopback traffic reported by STATS block */
12136 uint64_t tx_stat_discard;
12137 /* Total Tx Error Drops for loopback traffic reported by STATS block */
12138 uint64_t tx_stat_error;
12139 /* Total Rx Drops for loopback traffic reported by STATS block */
12140 uint64_t rx_stat_discard;
12141 /* Total Rx Error Drops for loopback traffic reported by STATS block */
12142 uint64_t rx_stat_error;
12143 uint8_t unused_0[7];
12145 * This field is used in Output records to indicate that the output
12146 * is completely written to RAM. This field should be read as '1'
12147 * to indicate that the output has been completely written.
12148 * When writing a command completion or response to an internal processor,
12149 * the order of writes has to be such that this field is written last.
12152 } __attribute__((packed));
12154 /***********************
12155 * hwrm_port_clr_stats *
12156 ***********************/
12159 /* hwrm_port_clr_stats_input (size:192b/24B) */
12160 struct hwrm_port_clr_stats_input {
12161 /* The HWRM command request type. */
12164 * The completion ring to send the completion event on. This should
12165 * be the NQ ID returned from the `nq_alloc` HWRM command.
12167 uint16_t cmpl_ring;
12169 * The sequence ID is used by the driver for tracking multiple
12170 * commands. This ID is treated as opaque data by the firmware and
12171 * the value is returned in the `hwrm_resp_hdr` upon completion.
12175 * The target ID of the command:
12176 * * 0x0-0xFFF8 - The function ID
12177 * * 0xFFF8-0xFFFE - Reserved for internal processors
12180 uint16_t target_id;
12182 * A physical address pointer pointing to a host buffer that the
12183 * command's response data will be written. This can be either a host
12184 * physical address (HPA) or a guest physical address (GPA) and must
12185 * point to a physically contiguous block of memory.
12187 uint64_t resp_addr;
12188 /* Port ID of port that is being queried. */
12190 uint8_t unused_0[6];
12191 } __attribute__((packed));
12193 /* hwrm_port_clr_stats_output (size:128b/16B) */
12194 struct hwrm_port_clr_stats_output {
12195 /* The specific error status for the command. */
12196 uint16_t error_code;
12197 /* The HWRM command request type. */
12199 /* The sequence ID from the original command. */
12201 /* The length of the response data in number of bytes. */
12203 uint8_t unused_0[7];
12205 * This field is used in Output records to indicate that the output
12206 * is completely written to RAM. This field should be read as '1'
12207 * to indicate that the output has been completely written.
12208 * When writing a command completion or response to an internal processor,
12209 * the order of writes has to be such that this field is written last.
12212 } __attribute__((packed));
12214 /****************************
12215 * hwrm_port_lpbk_clr_stats *
12216 ****************************/
12219 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
12220 struct hwrm_port_lpbk_clr_stats_input {
12221 /* The HWRM command request type. */
12224 * The completion ring to send the completion event on. This should
12225 * be the NQ ID returned from the `nq_alloc` HWRM command.
12227 uint16_t cmpl_ring;
12229 * The sequence ID is used by the driver for tracking multiple
12230 * commands. This ID is treated as opaque data by the firmware and
12231 * the value is returned in the `hwrm_resp_hdr` upon completion.
12235 * The target ID of the command:
12236 * * 0x0-0xFFF8 - The function ID
12237 * * 0xFFF8-0xFFFE - Reserved for internal processors
12240 uint16_t target_id;
12242 * A physical address pointer pointing to a host buffer that the
12243 * command's response data will be written. This can be either a host
12244 * physical address (HPA) or a guest physical address (GPA) and must
12245 * point to a physically contiguous block of memory.
12247 uint64_t resp_addr;
12248 } __attribute__((packed));
12250 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
12251 struct hwrm_port_lpbk_clr_stats_output {
12252 /* The specific error status for the command. */
12253 uint16_t error_code;
12254 /* The HWRM command request type. */
12256 /* The sequence ID from the original command. */
12258 /* The length of the response data in number of bytes. */
12260 uint8_t unused_0[7];
12262 * This field is used in Output records to indicate that the output
12263 * is completely written to RAM. This field should be read as '1'
12264 * to indicate that the output has been completely written.
12265 * When writing a command completion or response to an internal processor,
12266 * the order of writes has to be such that this field is written last.
12269 } __attribute__((packed));
12271 /**********************
12272 * hwrm_port_ts_query *
12273 **********************/
12276 /* hwrm_port_ts_query_input (size:192b/24B) */
12277 struct hwrm_port_ts_query_input {
12278 /* The HWRM command request type. */
12281 * The completion ring to send the completion event on. This should
12282 * be the NQ ID returned from the `nq_alloc` HWRM command.
12284 uint16_t cmpl_ring;
12286 * The sequence ID is used by the driver for tracking multiple
12287 * commands. This ID is treated as opaque data by the firmware and
12288 * the value is returned in the `hwrm_resp_hdr` upon completion.
12292 * The target ID of the command:
12293 * * 0x0-0xFFF8 - The function ID
12294 * * 0xFFF8-0xFFFE - Reserved for internal processors
12297 uint16_t target_id;
12299 * A physical address pointer pointing to a host buffer that the
12300 * command's response data will be written. This can be either a host
12301 * physical address (HPA) or a guest physical address (GPA) and must
12302 * point to a physically contiguous block of memory.
12304 uint64_t resp_addr;
12307 * Enumeration denoting the RX, TX type of the resource.
12308 * This enumeration is used for resources that are similar for both
12309 * TX and RX paths of the chip.
12311 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
12313 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
12315 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
12316 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
12317 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
12318 /* Port ID of port that is being queried. */
12320 uint8_t unused_0[2];
12321 } __attribute__((packed));
12323 /* hwrm_port_ts_query_output (size:192b/24B) */
12324 struct hwrm_port_ts_query_output {
12325 /* The specific error status for the command. */
12326 uint16_t error_code;
12327 /* The HWRM command request type. */
12329 /* The sequence ID from the original command. */
12331 /* The length of the response data in number of bytes. */
12333 /* Timestamp value of PTP message captured. */
12334 uint64_t ptp_msg_ts;
12335 /* Sequence ID of the PTP message captured. */
12336 uint16_t ptp_msg_seqid;
12337 uint8_t unused_0[5];
12339 * This field is used in Output records to indicate that the output
12340 * is completely written to RAM. This field should be read as '1'
12341 * to indicate that the output has been completely written.
12342 * When writing a command completion or response to an internal processor,
12343 * the order of writes has to be such that this field is written last.
12346 } __attribute__((packed));
12348 /***********************
12349 * hwrm_port_phy_qcaps *
12350 ***********************/
12353 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
12354 struct hwrm_port_phy_qcaps_input {
12355 /* The HWRM command request type. */
12358 * The completion ring to send the completion event on. This should
12359 * be the NQ ID returned from the `nq_alloc` HWRM command.
12361 uint16_t cmpl_ring;
12363 * The sequence ID is used by the driver for tracking multiple
12364 * commands. This ID is treated as opaque data by the firmware and
12365 * the value is returned in the `hwrm_resp_hdr` upon completion.
12369 * The target ID of the command:
12370 * * 0x0-0xFFF8 - The function ID
12371 * * 0xFFF8-0xFFFE - Reserved for internal processors
12374 uint16_t target_id;
12376 * A physical address pointer pointing to a host buffer that the
12377 * command's response data will be written. This can be either a host
12378 * physical address (HPA) or a guest physical address (GPA) and must
12379 * point to a physically contiguous block of memory.
12381 uint64_t resp_addr;
12382 /* Port ID of port that is being queried. */
12384 uint8_t unused_0[6];
12385 } __attribute__((packed));
12387 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
12388 struct hwrm_port_phy_qcaps_output {
12389 /* The specific error status for the command. */
12390 uint16_t error_code;
12391 /* The HWRM command request type. */
12393 /* The sequence ID from the original command. */
12395 /* The length of the response data in number of bytes. */
12397 /* PHY capability flags */
12400 * If set to 1, then this field indicates that the
12401 * link is capable of supporting EEE.
12403 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
12406 * If set to 1, then this field indicates that the
12407 * PHY is capable of supporting external loopback.
12409 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
12412 * Reserved field. The HWRM shall set this field to 0.
12413 * An HWRM client shall ignore this field.
12415 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
12417 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
12418 /* Number of front panel ports for this device. */
12420 /* Not supported or unknown */
12421 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
12422 /* single port device */
12423 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
12424 /* 2-port device */
12425 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
12426 /* 3-port device */
12427 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
12428 /* 4-port device */
12429 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
12430 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
12431 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
12433 * This is a bit mask to indicate what speeds are supported
12434 * as forced speeds on this link.
12435 * For each speed that can be forced on this link, the
12436 * corresponding mask bit shall be set to '1'.
12438 uint16_t supported_speeds_force_mode;
12439 /* 100Mb link speed (Half-duplex) */
12440 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
12442 /* 100Mb link speed (Full-duplex) */
12443 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
12445 /* 1Gb link speed (Half-duplex) */
12446 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
12448 /* 1Gb link speed (Full-duplex) */
12449 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
12451 /* 2Gb link speed */
12452 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
12454 /* 25Gb link speed */
12455 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
12457 /* 10Gb link speed */
12458 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
12460 /* 20Gb link speed */
12461 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
12463 /* 25Gb link speed */
12464 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
12466 /* 40Gb link speed */
12467 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
12469 /* 50Gb link speed */
12470 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
12472 /* 100Gb link speed */
12473 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
12475 /* 10Mb link speed (Half-duplex) */
12476 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
12478 /* 10Mb link speed (Full-duplex) */
12479 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
12482 * This is a bit mask to indicate what speeds are supported
12483 * for autonegotiation on this link.
12484 * For each speed that can be autonegotiated on this link, the
12485 * corresponding mask bit shall be set to '1'.
12487 uint16_t supported_speeds_auto_mode;
12488 /* 100Mb link speed (Half-duplex) */
12489 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
12491 /* 100Mb link speed (Full-duplex) */
12492 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
12494 /* 1Gb link speed (Half-duplex) */
12495 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
12497 /* 1Gb link speed (Full-duplex) */
12498 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
12500 /* 2Gb link speed */
12501 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
12503 /* 25Gb link speed */
12504 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
12506 /* 10Gb link speed */
12507 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
12509 /* 20Gb link speed */
12510 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
12512 /* 25Gb link speed */
12513 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
12515 /* 40Gb link speed */
12516 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
12518 /* 50Gb link speed */
12519 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
12521 /* 100Gb link speed */
12522 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
12524 /* 10Mb link speed (Half-duplex) */
12525 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
12527 /* 10Mb link speed (Full-duplex) */
12528 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
12531 * This is a bit mask to indicate what speeds are supported
12532 * for EEE on this link.
12533 * For each speed that can be autonegotiated when EEE is enabled
12534 * on this link, the corresponding mask bit shall be set to '1'.
12535 * This field is only valid when the eee_suppotred is set to '1'.
12537 uint16_t supported_speeds_eee_mode;
12539 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
12541 /* 100Mb link speed (Full-duplex) */
12542 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
12545 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
12547 /* 1Gb link speed (Full-duplex) */
12548 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
12551 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
12554 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
12556 /* 10Gb link speed */
12557 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
12559 uint32_t tx_lpi_timer_low;
12561 * The lowest value of TX LPI timer that can be set on this link
12562 * when EEE is enabled. This value is in microseconds.
12563 * This field is valid only when_eee_supported is set to '1'.
12565 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
12567 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
12569 * Reserved field. The HWRM shall set this field to 0.
12570 * An HWRM client shall ignore this field.
12572 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
12573 UINT32_C(0xff000000)
12574 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
12575 uint32_t valid_tx_lpi_timer_high;
12577 * The highest value of TX LPI timer that can be set on this link
12578 * when EEE is enabled. This value is in microseconds.
12579 * This field is valid only when_eee_supported is set to '1'.
12581 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
12583 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
12585 * This field is used in Output records to indicate that the output
12586 * is completely written to RAM. This field should be read as '1'
12587 * to indicate that the output has been completely written.
12588 * When writing a command completion or response to an internal processor,
12589 * the order of writes has to be such that this field is written last.
12591 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
12592 UINT32_C(0xff000000)
12593 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
12594 } __attribute__((packed));
12596 /***************************
12597 * hwrm_port_phy_i2c_write *
12598 ***************************/
12601 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */
12602 struct hwrm_port_phy_i2c_write_input {
12603 /* The HWRM command request type. */
12606 * The completion ring to send the completion event on. This should
12607 * be the NQ ID returned from the `nq_alloc` HWRM command.
12609 uint16_t cmpl_ring;
12611 * The sequence ID is used by the driver for tracking multiple
12612 * commands. This ID is treated as opaque data by the firmware and
12613 * the value is returned in the `hwrm_resp_hdr` upon completion.
12617 * The target ID of the command:
12618 * * 0x0-0xFFF8 - The function ID
12619 * * 0xFFF8-0xFFFE - Reserved for internal processors
12622 uint16_t target_id;
12624 * A physical address pointer pointing to a host buffer that the
12625 * command's response data will be written. This can be either a host
12626 * physical address (HPA) or a guest physical address (GPA) and must
12627 * point to a physically contiguous block of memory.
12629 uint64_t resp_addr;
12633 * This bit must be '1' for the page_offset field to be
12636 #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \
12638 /* Port ID of port. */
12640 /* 8-bit I2C slave address. */
12641 uint8_t i2c_slave_addr;
12643 /* The page number that is being accessed over I2C. */
12644 uint16_t page_number;
12645 /* Offset within the page that is being accessed over I2C. */
12646 uint16_t page_offset;
12648 * Length of data to write, in bytes starting at the offset
12649 * specified above. If the offset is not specified, then
12650 * the data shall be written from the beginning of the page.
12652 uint8_t data_length;
12653 uint8_t unused_1[7];
12654 /* Up to 64B of data. */
12656 } __attribute__((packed));
12658 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */
12659 struct hwrm_port_phy_i2c_write_output {
12660 /* The specific error status for the command. */
12661 uint16_t error_code;
12662 /* The HWRM command request type. */
12664 /* The sequence ID from the original command. */
12666 /* The length of the response data in number of bytes. */
12668 uint8_t unused_0[7];
12670 * This field is used in Output records to indicate that the output
12671 * is completely written to RAM. This field should be read as '1'
12672 * to indicate that the output has been completely written.
12673 * When writing a command completion or response to an internal processor,
12674 * the order of writes has to be such that this field is written last.
12677 } __attribute__((packed));
12679 /**************************
12680 * hwrm_port_phy_i2c_read *
12681 **************************/
12684 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
12685 struct hwrm_port_phy_i2c_read_input {
12686 /* The HWRM command request type. */
12689 * The completion ring to send the completion event on. This should
12690 * be the NQ ID returned from the `nq_alloc` HWRM command.
12692 uint16_t cmpl_ring;
12694 * The sequence ID is used by the driver for tracking multiple
12695 * commands. This ID is treated as opaque data by the firmware and
12696 * the value is returned in the `hwrm_resp_hdr` upon completion.
12700 * The target ID of the command:
12701 * * 0x0-0xFFF8 - The function ID
12702 * * 0xFFF8-0xFFFE - Reserved for internal processors
12705 uint16_t target_id;
12707 * A physical address pointer pointing to a host buffer that the
12708 * command's response data will be written. This can be either a host
12709 * physical address (HPA) or a guest physical address (GPA) and must
12710 * point to a physically contiguous block of memory.
12712 uint64_t resp_addr;
12716 * This bit must be '1' for the page_offset field to be
12719 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \
12721 /* Port ID of port. */
12723 /* 8-bit I2C slave address. */
12724 uint8_t i2c_slave_addr;
12726 /* The page number that is being accessed over I2C. */
12727 uint16_t page_number;
12728 /* Offset within the page that is being accessed over I2C. */
12729 uint16_t page_offset;
12731 * Length of data to read, in bytes starting at the offset
12732 * specified above. If the offset is not specified, then
12733 * the data shall be read from the beginning of the page.
12735 uint8_t data_length;
12736 uint8_t unused_1[7];
12737 } __attribute__((packed));
12739 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
12740 struct hwrm_port_phy_i2c_read_output {
12741 /* The specific error status for the command. */
12742 uint16_t error_code;
12743 /* The HWRM command request type. */
12745 /* The sequence ID from the original command. */
12747 /* The length of the response data in number of bytes. */
12749 /* Up to 64B of data. */
12751 uint8_t unused_0[7];
12753 * This field is used in Output records to indicate that the output
12754 * is completely written to RAM. This field should be read as '1'
12755 * to indicate that the output has been completely written.
12756 * When writing a command completion or response to an internal processor,
12757 * the order of writes has to be such that this field is written last.
12760 } __attribute__((packed));
12762 /*********************
12763 * hwrm_port_led_cfg *
12764 *********************/
12767 /* hwrm_port_led_cfg_input (size:512b/64B) */
12768 struct hwrm_port_led_cfg_input {
12769 /* The HWRM command request type. */
12772 * The completion ring to send the completion event on. This should
12773 * be the NQ ID returned from the `nq_alloc` HWRM command.
12775 uint16_t cmpl_ring;
12777 * The sequence ID is used by the driver for tracking multiple
12778 * commands. This ID is treated as opaque data by the firmware and
12779 * the value is returned in the `hwrm_resp_hdr` upon completion.
12783 * The target ID of the command:
12784 * * 0x0-0xFFF8 - The function ID
12785 * * 0xFFF8-0xFFFE - Reserved for internal processors
12788 uint16_t target_id;
12790 * A physical address pointer pointing to a host buffer that the
12791 * command's response data will be written. This can be either a host
12792 * physical address (HPA) or a guest physical address (GPA) and must
12793 * point to a physically contiguous block of memory.
12795 uint64_t resp_addr;
12798 * This bit must be '1' for the led0_id field to be
12801 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
12804 * This bit must be '1' for the led0_state field to be
12807 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
12810 * This bit must be '1' for the led0_color field to be
12813 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
12816 * This bit must be '1' for the led0_blink_on field to be
12819 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
12822 * This bit must be '1' for the led0_blink_off field to be
12825 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
12828 * This bit must be '1' for the led0_group_id field to be
12831 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
12834 * This bit must be '1' for the led1_id field to be
12837 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
12840 * This bit must be '1' for the led1_state field to be
12843 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
12846 * This bit must be '1' for the led1_color field to be
12849 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
12852 * This bit must be '1' for the led1_blink_on field to be
12855 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
12858 * This bit must be '1' for the led1_blink_off field to be
12861 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
12864 * This bit must be '1' for the led1_group_id field to be
12867 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
12870 * This bit must be '1' for the led2_id field to be
12873 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
12876 * This bit must be '1' for the led2_state field to be
12879 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
12882 * This bit must be '1' for the led2_color field to be
12885 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
12888 * This bit must be '1' for the led2_blink_on field to be
12891 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
12894 * This bit must be '1' for the led2_blink_off field to be
12897 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
12900 * This bit must be '1' for the led2_group_id field to be
12903 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
12906 * This bit must be '1' for the led3_id field to be
12909 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
12912 * This bit must be '1' for the led3_state field to be
12915 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
12918 * This bit must be '1' for the led3_color field to be
12921 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
12924 * This bit must be '1' for the led3_blink_on field to be
12927 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
12930 * This bit must be '1' for the led3_blink_off field to be
12933 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
12936 * This bit must be '1' for the led3_group_id field to be
12939 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
12941 /* Port ID of port whose LEDs are configured. */
12944 * The number of LEDs that are being configured.
12945 * Up to 4 LEDs can be configured with this command.
12948 /* Reserved field. */
12950 /* An identifier for the LED #0. */
12952 /* The requested state of the LED #0. */
12953 uint8_t led0_state;
12954 /* Default state of the LED */
12955 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
12957 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
12959 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
12961 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
12962 /* Blink Alternately */
12963 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
12964 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
12965 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
12966 /* The requested color of LED #0. */
12967 uint8_t led0_color;
12969 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
12971 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
12973 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
12974 /* Green or Amber */
12975 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
12976 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
12977 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
12980 * If the LED #0 state is "blink" or "blinkalt", then
12981 * this field represents the requested time in milliseconds
12982 * to keep LED on between cycles.
12984 uint16_t led0_blink_on;
12986 * If the LED #0 state is "blink" or "blinkalt", then
12987 * this field represents the requested time in milliseconds
12988 * to keep LED off between cycles.
12990 uint16_t led0_blink_off;
12992 * An identifier for the group of LEDs that LED #0 belongs
12994 * If set to 0, then the LED #0 shall not be grouped and
12995 * shall be treated as an individual resource.
12996 * For all other non-zero values of this field, LED #0 shall
12997 * be grouped together with the LEDs with the same group ID
13000 uint8_t led0_group_id;
13001 /* Reserved field. */
13003 /* An identifier for the LED #1. */
13005 /* The requested state of the LED #1. */
13006 uint8_t led1_state;
13007 /* Default state of the LED */
13008 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
13010 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
13012 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
13014 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
13015 /* Blink Alternately */
13016 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
13017 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
13018 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
13019 /* The requested color of LED #1. */
13020 uint8_t led1_color;
13022 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
13024 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
13026 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
13027 /* Green or Amber */
13028 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
13029 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
13030 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
13033 * If the LED #1 state is "blink" or "blinkalt", then
13034 * this field represents the requested time in milliseconds
13035 * to keep LED on between cycles.
13037 uint16_t led1_blink_on;
13039 * If the LED #1 state is "blink" or "blinkalt", then
13040 * this field represents the requested time in milliseconds
13041 * to keep LED off between cycles.
13043 uint16_t led1_blink_off;
13045 * An identifier for the group of LEDs that LED #1 belongs
13047 * If set to 0, then the LED #1 shall not be grouped and
13048 * shall be treated as an individual resource.
13049 * For all other non-zero values of this field, LED #1 shall
13050 * be grouped together with the LEDs with the same group ID
13053 uint8_t led1_group_id;
13054 /* Reserved field. */
13056 /* An identifier for the LED #2. */
13058 /* The requested state of the LED #2. */
13059 uint8_t led2_state;
13060 /* Default state of the LED */
13061 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
13063 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
13065 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
13067 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
13068 /* Blink Alternately */
13069 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
13070 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
13071 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
13072 /* The requested color of LED #2. */
13073 uint8_t led2_color;
13075 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
13077 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
13079 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
13080 /* Green or Amber */
13081 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
13082 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
13083 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
13086 * If the LED #2 state is "blink" or "blinkalt", then
13087 * this field represents the requested time in milliseconds
13088 * to keep LED on between cycles.
13090 uint16_t led2_blink_on;
13092 * If the LED #2 state is "blink" or "blinkalt", then
13093 * this field represents the requested time in milliseconds
13094 * to keep LED off between cycles.
13096 uint16_t led2_blink_off;
13098 * An identifier for the group of LEDs that LED #2 belongs
13100 * If set to 0, then the LED #2 shall not be grouped and
13101 * shall be treated as an individual resource.
13102 * For all other non-zero values of this field, LED #2 shall
13103 * be grouped together with the LEDs with the same group ID
13106 uint8_t led2_group_id;
13107 /* Reserved field. */
13109 /* An identifier for the LED #3. */
13111 /* The requested state of the LED #3. */
13112 uint8_t led3_state;
13113 /* Default state of the LED */
13114 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
13116 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
13118 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
13120 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
13121 /* Blink Alternately */
13122 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
13123 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
13124 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
13125 /* The requested color of LED #3. */
13126 uint8_t led3_color;
13128 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
13130 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
13132 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
13133 /* Green or Amber */
13134 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
13135 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
13136 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
13139 * If the LED #3 state is "blink" or "blinkalt", then
13140 * this field represents the requested time in milliseconds
13141 * to keep LED on between cycles.
13143 uint16_t led3_blink_on;
13145 * If the LED #3 state is "blink" or "blinkalt", then
13146 * this field represents the requested time in milliseconds
13147 * to keep LED off between cycles.
13149 uint16_t led3_blink_off;
13151 * An identifier for the group of LEDs that LED #3 belongs
13153 * If set to 0, then the LED #3 shall not be grouped and
13154 * shall be treated as an individual resource.
13155 * For all other non-zero values of this field, LED #3 shall
13156 * be grouped together with the LEDs with the same group ID
13159 uint8_t led3_group_id;
13160 /* Reserved field. */
13162 } __attribute__((packed));
13164 /* hwrm_port_led_cfg_output (size:128b/16B) */
13165 struct hwrm_port_led_cfg_output {
13166 /* The specific error status for the command. */
13167 uint16_t error_code;
13168 /* The HWRM command request type. */
13170 /* The sequence ID from the original command. */
13172 /* The length of the response data in number of bytes. */
13174 uint8_t unused_0[7];
13176 * This field is used in Output records to indicate that the output
13177 * is completely written to RAM. This field should be read as '1'
13178 * to indicate that the output has been completely written.
13179 * When writing a command completion or response to an internal processor,
13180 * the order of writes has to be such that this field is written last.
13183 } __attribute__((packed));
13185 /**********************
13186 * hwrm_port_led_qcfg *
13187 **********************/
13190 /* hwrm_port_led_qcfg_input (size:192b/24B) */
13191 struct hwrm_port_led_qcfg_input {
13192 /* The HWRM command request type. */
13195 * The completion ring to send the completion event on. This should
13196 * be the NQ ID returned from the `nq_alloc` HWRM command.
13198 uint16_t cmpl_ring;
13200 * The sequence ID is used by the driver for tracking multiple
13201 * commands. This ID is treated as opaque data by the firmware and
13202 * the value is returned in the `hwrm_resp_hdr` upon completion.
13206 * The target ID of the command:
13207 * * 0x0-0xFFF8 - The function ID
13208 * * 0xFFF8-0xFFFE - Reserved for internal processors
13211 uint16_t target_id;
13213 * A physical address pointer pointing to a host buffer that the
13214 * command's response data will be written. This can be either a host
13215 * physical address (HPA) or a guest physical address (GPA) and must
13216 * point to a physically contiguous block of memory.
13218 uint64_t resp_addr;
13219 /* Port ID of port whose LED configuration is being queried. */
13221 uint8_t unused_0[6];
13222 } __attribute__((packed));
13224 /* hwrm_port_led_qcfg_output (size:448b/56B) */
13225 struct hwrm_port_led_qcfg_output {
13226 /* The specific error status for the command. */
13227 uint16_t error_code;
13228 /* The HWRM command request type. */
13230 /* The sequence ID from the original command. */
13232 /* The length of the response data in number of bytes. */
13235 * The number of LEDs that are configured on this port.
13236 * Up to 4 LEDs can be returned in the response.
13239 /* An identifier for the LED #0. */
13241 /* The type of LED #0. */
13244 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
13246 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
13248 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
13249 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
13250 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
13251 /* The current state of the LED #0. */
13252 uint8_t led0_state;
13253 /* Default state of the LED */
13254 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
13256 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
13258 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
13260 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
13261 /* Blink Alternately */
13262 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
13263 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
13264 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
13265 /* The color of LED #0. */
13266 uint8_t led0_color;
13268 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
13270 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
13272 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
13273 /* Green or Amber */
13274 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
13275 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
13276 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
13279 * If the LED #0 state is "blink" or "blinkalt", then
13280 * this field represents the requested time in milliseconds
13281 * to keep LED on between cycles.
13283 uint16_t led0_blink_on;
13285 * If the LED #0 state is "blink" or "blinkalt", then
13286 * this field represents the requested time in milliseconds
13287 * to keep LED off between cycles.
13289 uint16_t led0_blink_off;
13291 * An identifier for the group of LEDs that LED #0 belongs
13293 * If set to 0, then the LED #0 is not grouped.
13294 * For all other non-zero values of this field, LED #0 is
13295 * grouped together with the LEDs with the same group ID
13298 uint8_t led0_group_id;
13299 /* An identifier for the LED #1. */
13301 /* The type of LED #1. */
13304 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
13306 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
13308 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
13309 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
13310 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
13311 /* The current state of the LED #1. */
13312 uint8_t led1_state;
13313 /* Default state of the LED */
13314 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
13316 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
13318 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
13320 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
13321 /* Blink Alternately */
13322 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
13323 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
13324 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
13325 /* The color of LED #1. */
13326 uint8_t led1_color;
13328 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
13330 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
13332 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
13333 /* Green or Amber */
13334 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
13335 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
13336 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
13339 * If the LED #1 state is "blink" or "blinkalt", then
13340 * this field represents the requested time in milliseconds
13341 * to keep LED on between cycles.
13343 uint16_t led1_blink_on;
13345 * If the LED #1 state is "blink" or "blinkalt", then
13346 * this field represents the requested time in milliseconds
13347 * to keep LED off between cycles.
13349 uint16_t led1_blink_off;
13351 * An identifier for the group of LEDs that LED #1 belongs
13353 * If set to 0, then the LED #1 is not grouped.
13354 * For all other non-zero values of this field, LED #1 is
13355 * grouped together with the LEDs with the same group ID
13358 uint8_t led1_group_id;
13359 /* An identifier for the LED #2. */
13361 /* The type of LED #2. */
13364 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
13366 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
13368 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
13369 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
13370 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
13371 /* The current state of the LED #2. */
13372 uint8_t led2_state;
13373 /* Default state of the LED */
13374 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
13376 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
13378 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
13380 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
13381 /* Blink Alternately */
13382 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
13383 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
13384 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
13385 /* The color of LED #2. */
13386 uint8_t led2_color;
13388 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
13390 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
13392 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
13393 /* Green or Amber */
13394 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
13395 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
13396 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
13399 * If the LED #2 state is "blink" or "blinkalt", then
13400 * this field represents the requested time in milliseconds
13401 * to keep LED on between cycles.
13403 uint16_t led2_blink_on;
13405 * If the LED #2 state is "blink" or "blinkalt", then
13406 * this field represents the requested time in milliseconds
13407 * to keep LED off between cycles.
13409 uint16_t led2_blink_off;
13411 * An identifier for the group of LEDs that LED #2 belongs
13413 * If set to 0, then the LED #2 is not grouped.
13414 * For all other non-zero values of this field, LED #2 is
13415 * grouped together with the LEDs with the same group ID
13418 uint8_t led2_group_id;
13419 /* An identifier for the LED #3. */
13421 /* The type of LED #3. */
13424 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
13426 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
13428 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
13429 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
13430 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
13431 /* The current state of the LED #3. */
13432 uint8_t led3_state;
13433 /* Default state of the LED */
13434 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
13436 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
13438 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
13440 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
13441 /* Blink Alternately */
13442 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
13443 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
13444 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
13445 /* The color of LED #3. */
13446 uint8_t led3_color;
13448 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
13450 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
13452 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
13453 /* Green or Amber */
13454 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
13455 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
13456 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
13459 * If the LED #3 state is "blink" or "blinkalt", then
13460 * this field represents the requested time in milliseconds
13461 * to keep LED on between cycles.
13463 uint16_t led3_blink_on;
13465 * If the LED #3 state is "blink" or "blinkalt", then
13466 * this field represents the requested time in milliseconds
13467 * to keep LED off between cycles.
13469 uint16_t led3_blink_off;
13471 * An identifier for the group of LEDs that LED #3 belongs
13473 * If set to 0, then the LED #3 is not grouped.
13474 * For all other non-zero values of this field, LED #3 is
13475 * grouped together with the LEDs with the same group ID
13478 uint8_t led3_group_id;
13479 uint8_t unused_4[6];
13481 * This field is used in Output records to indicate that the output
13482 * is completely written to RAM. This field should be read as '1'
13483 * to indicate that the output has been completely written.
13484 * When writing a command completion or response to an internal processor,
13485 * the order of writes has to be such that this field is written last.
13488 } __attribute__((packed));
13490 /***********************
13491 * hwrm_port_led_qcaps *
13492 ***********************/
13495 /* hwrm_port_led_qcaps_input (size:192b/24B) */
13496 struct hwrm_port_led_qcaps_input {
13497 /* The HWRM command request type. */
13500 * The completion ring to send the completion event on. This should
13501 * be the NQ ID returned from the `nq_alloc` HWRM command.
13503 uint16_t cmpl_ring;
13505 * The sequence ID is used by the driver for tracking multiple
13506 * commands. This ID is treated as opaque data by the firmware and
13507 * the value is returned in the `hwrm_resp_hdr` upon completion.
13511 * The target ID of the command:
13512 * * 0x0-0xFFF8 - The function ID
13513 * * 0xFFF8-0xFFFE - Reserved for internal processors
13516 uint16_t target_id;
13518 * A physical address pointer pointing to a host buffer that the
13519 * command's response data will be written. This can be either a host
13520 * physical address (HPA) or a guest physical address (GPA) and must
13521 * point to a physically contiguous block of memory.
13523 uint64_t resp_addr;
13524 /* Port ID of port whose LED configuration is being queried. */
13526 uint8_t unused_0[6];
13527 } __attribute__((packed));
13529 /* hwrm_port_led_qcaps_output (size:384b/48B) */
13530 struct hwrm_port_led_qcaps_output {
13531 /* The specific error status for the command. */
13532 uint16_t error_code;
13533 /* The HWRM command request type. */
13535 /* The sequence ID from the original command. */
13537 /* The length of the response data in number of bytes. */
13540 * The number of LEDs that are configured on this port.
13541 * Up to 4 LEDs can be returned in the response.
13544 /* Reserved for future use. */
13546 /* An identifier for the LED #0. */
13548 /* The type of LED #0. */
13551 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
13553 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
13555 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
13556 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
13557 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
13559 * An identifier for the group of LEDs that LED #0 belongs
13561 * If set to 0, then the LED #0 cannot be grouped.
13562 * For all other non-zero values of this field, LED #0 is
13563 * grouped together with the LEDs with the same group ID
13566 uint8_t led0_group_id;
13568 /* The states supported by LED #0. */
13569 uint16_t led0_state_caps;
13571 * If set to 1, this LED is enabled.
13572 * If set to 0, this LED is disabled.
13574 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
13577 * If set to 1, off state is supported on this LED.
13578 * If set to 0, off state is not supported on this LED.
13580 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
13583 * If set to 1, on state is supported on this LED.
13584 * If set to 0, on state is not supported on this LED.
13586 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
13589 * If set to 1, blink state is supported on this LED.
13590 * If set to 0, blink state is not supported on this LED.
13592 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
13595 * If set to 1, blink_alt state is supported on this LED.
13596 * If set to 0, blink_alt state is not supported on this LED.
13598 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
13600 /* The colors supported by LED #0. */
13601 uint16_t led0_color_caps;
13603 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
13606 * If set to 1, Amber color is supported on this LED.
13607 * If set to 0, Amber color is not supported on this LED.
13609 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
13612 * If set to 1, Green color is supported on this LED.
13613 * If set to 0, Green color is not supported on this LED.
13615 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
13617 /* An identifier for the LED #1. */
13619 /* The type of LED #1. */
13622 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
13624 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
13626 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
13627 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
13628 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
13630 * An identifier for the group of LEDs that LED #1 belongs
13632 * If set to 0, then the LED #0 cannot be grouped.
13633 * For all other non-zero values of this field, LED #0 is
13634 * grouped together with the LEDs with the same group ID
13637 uint8_t led1_group_id;
13639 /* The states supported by LED #1. */
13640 uint16_t led1_state_caps;
13642 * If set to 1, this LED is enabled.
13643 * If set to 0, this LED is disabled.
13645 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
13648 * If set to 1, off state is supported on this LED.
13649 * If set to 0, off state is not supported on this LED.
13651 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
13654 * If set to 1, on state is supported on this LED.
13655 * If set to 0, on state is not supported on this LED.
13657 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
13660 * If set to 1, blink state is supported on this LED.
13661 * If set to 0, blink state is not supported on this LED.
13663 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
13666 * If set to 1, blink_alt state is supported on this LED.
13667 * If set to 0, blink_alt state is not supported on this LED.
13669 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
13671 /* The colors supported by LED #1. */
13672 uint16_t led1_color_caps;
13674 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
13677 * If set to 1, Amber color is supported on this LED.
13678 * If set to 0, Amber color is not supported on this LED.
13680 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
13683 * If set to 1, Green color is supported on this LED.
13684 * If set to 0, Green color is not supported on this LED.
13686 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
13688 /* An identifier for the LED #2. */
13690 /* The type of LED #2. */
13693 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
13695 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
13697 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
13698 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
13699 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
13701 * An identifier for the group of LEDs that LED #0 belongs
13703 * If set to 0, then the LED #0 cannot be grouped.
13704 * For all other non-zero values of this field, LED #0 is
13705 * grouped together with the LEDs with the same group ID
13708 uint8_t led2_group_id;
13710 /* The states supported by LED #2. */
13711 uint16_t led2_state_caps;
13713 * If set to 1, this LED is enabled.
13714 * If set to 0, this LED is disabled.
13716 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
13719 * If set to 1, off state is supported on this LED.
13720 * If set to 0, off state is not supported on this LED.
13722 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
13725 * If set to 1, on state is supported on this LED.
13726 * If set to 0, on state is not supported on this LED.
13728 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
13731 * If set to 1, blink state is supported on this LED.
13732 * If set to 0, blink state is not supported on this LED.
13734 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
13737 * If set to 1, blink_alt state is supported on this LED.
13738 * If set to 0, blink_alt state is not supported on this LED.
13740 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
13742 /* The colors supported by LED #2. */
13743 uint16_t led2_color_caps;
13745 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
13748 * If set to 1, Amber color is supported on this LED.
13749 * If set to 0, Amber color is not supported on this LED.
13751 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
13754 * If set to 1, Green color is supported on this LED.
13755 * If set to 0, Green color is not supported on this LED.
13757 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
13759 /* An identifier for the LED #3. */
13761 /* The type of LED #3. */
13764 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
13766 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
13768 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
13769 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
13770 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
13772 * An identifier for the group of LEDs that LED #3 belongs
13774 * If set to 0, then the LED #0 cannot be grouped.
13775 * For all other non-zero values of this field, LED #0 is
13776 * grouped together with the LEDs with the same group ID
13779 uint8_t led3_group_id;
13781 /* The states supported by LED #3. */
13782 uint16_t led3_state_caps;
13784 * If set to 1, this LED is enabled.
13785 * If set to 0, this LED is disabled.
13787 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
13790 * If set to 1, off state is supported on this LED.
13791 * If set to 0, off state is not supported on this LED.
13793 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
13796 * If set to 1, on state is supported on this LED.
13797 * If set to 0, on state is not supported on this LED.
13799 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
13802 * If set to 1, blink state is supported on this LED.
13803 * If set to 0, blink state is not supported on this LED.
13805 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
13808 * If set to 1, blink_alt state is supported on this LED.
13809 * If set to 0, blink_alt state is not supported on this LED.
13811 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
13813 /* The colors supported by LED #3. */
13814 uint16_t led3_color_caps;
13816 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
13819 * If set to 1, Amber color is supported on this LED.
13820 * If set to 0, Amber color is not supported on this LED.
13822 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
13825 * If set to 1, Green color is supported on this LED.
13826 * If set to 0, Green color is not supported on this LED.
13828 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
13830 uint8_t unused_4[3];
13832 * This field is used in Output records to indicate that the output
13833 * is completely written to RAM. This field should be read as '1'
13834 * to indicate that the output has been completely written.
13835 * When writing a command completion or response to an internal processor,
13836 * the order of writes has to be such that this field is written last.
13839 } __attribute__((packed));
13841 /***********************
13842 * hwrm_queue_qportcfg *
13843 ***********************/
13846 /* hwrm_queue_qportcfg_input (size:192b/24B) */
13847 struct hwrm_queue_qportcfg_input {
13848 /* The HWRM command request type. */
13851 * The completion ring to send the completion event on. This should
13852 * be the NQ ID returned from the `nq_alloc` HWRM command.
13854 uint16_t cmpl_ring;
13856 * The sequence ID is used by the driver for tracking multiple
13857 * commands. This ID is treated as opaque data by the firmware and
13858 * the value is returned in the `hwrm_resp_hdr` upon completion.
13862 * The target ID of the command:
13863 * * 0x0-0xFFF8 - The function ID
13864 * * 0xFFF8-0xFFFE - Reserved for internal processors
13867 uint16_t target_id;
13869 * A physical address pointer pointing to a host buffer that the
13870 * command's response data will be written. This can be either a host
13871 * physical address (HPA) or a guest physical address (GPA) and must
13872 * point to a physically contiguous block of memory.
13874 uint64_t resp_addr;
13877 * Enumeration denoting the RX, TX type of the resource.
13878 * This enumeration is used for resources that are similar for both
13879 * TX and RX paths of the chip.
13881 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
13883 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13885 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13886 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
13887 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
13889 * Port ID of port for which the queue configuration is being
13890 * queried. This field is only required when sent by IPC.
13894 * Drivers will set this capability when it can use
13895 * queue_idx_service_profile to map the queues to application.
13897 uint8_t drv_qmap_cap;
13899 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
13901 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
13902 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
13903 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
13905 } __attribute__((packed));
13907 /* hwrm_queue_qportcfg_output (size:256b/32B) */
13908 struct hwrm_queue_qportcfg_output {
13909 /* The specific error status for the command. */
13910 uint16_t error_code;
13911 /* The HWRM command request type. */
13913 /* The sequence ID from the original command. */
13915 /* The length of the response data in number of bytes. */
13918 * The maximum number of queues that can be configured on this
13920 * Valid values range from 1 through 8.
13922 uint8_t max_configurable_queues;
13924 * The maximum number of lossless queues that can be configured
13926 * Valid values range from 0 through 8.
13928 uint8_t max_configurable_lossless_queues;
13930 * Bitmask indicating which queues can be configured by the
13931 * hwrm_queue_cfg command.
13933 * Each bit represents a specific queue where bit 0 represents
13934 * queue 0 and bit 7 represents queue 7.
13935 * # A value of 0 indicates that the queue is not configurable
13936 * by the hwrm_queue_cfg command.
13937 * # A value of 1 indicates that the queue is configurable.
13938 * # A hwrm_queue_cfg command shall return error when trying to
13939 * configure a queue not configurable.
13941 uint8_t queue_cfg_allowed;
13942 /* Information about queue configuration. */
13943 uint8_t queue_cfg_info;
13945 * If this flag is set to '1', then the queues are
13946 * configured asymmetrically on TX and RX sides.
13947 * If this flag is set to '0', then the queues are
13948 * configured symmetrically on TX and RX sides. For
13949 * symmetric configuration, the queue configuration
13950 * including queue ids and service profiles on the
13951 * TX side is the same as the corresponding queue
13952 * configuration on the RX side.
13954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
13957 * Bitmask indicating which queues can be configured by the
13958 * hwrm_queue_pfcenable_cfg command.
13960 * Each bit represents a specific priority where bit 0 represents
13961 * priority 0 and bit 7 represents priority 7.
13962 * # A value of 0 indicates that the priority is not configurable by
13963 * the hwrm_queue_pfcenable_cfg command.
13964 * # A value of 1 indicates that the priority is configurable.
13965 * # A hwrm_queue_pfcenable_cfg command shall return error when
13966 * trying to configure a priority that is not configurable.
13968 uint8_t queue_pfcenable_cfg_allowed;
13970 * Bitmask indicating which queues can be configured by the
13971 * hwrm_queue_pri2cos_cfg command.
13973 * Each bit represents a specific queue where bit 0 represents
13974 * queue 0 and bit 7 represents queue 7.
13975 * # A value of 0 indicates that the queue is not configurable
13976 * by the hwrm_queue_pri2cos_cfg command.
13977 * # A value of 1 indicates that the queue is configurable.
13978 * # A hwrm_queue_pri2cos_cfg command shall return error when
13979 * trying to configure a queue that is not configurable.
13981 uint8_t queue_pri2cos_cfg_allowed;
13983 * Bitmask indicating which queues can be configured by the
13984 * hwrm_queue_pri2cos_cfg command.
13986 * Each bit represents a specific queue where bit 0 represents
13987 * queue 0 and bit 7 represents queue 7.
13988 * # A value of 0 indicates that the queue is not configurable
13989 * by the hwrm_queue_pri2cos_cfg command.
13990 * # A value of 1 indicates that the queue is configurable.
13991 * # A hwrm_queue_pri2cos_cfg command shall return error when
13992 * trying to configure a queue not configurable.
13994 uint8_t queue_cos2bw_cfg_allowed;
13996 * ID of CoS Queue 0.
13999 * # This ID can be used on any subsequent call to an hwrm command
14000 * that takes a queue id.
14001 * # IDs must always be queried by this command before any use
14002 * by the driver or software.
14003 * # Any driver or software should not make any assumptions about
14005 * # A value of 0xff indicates that the queue is not available.
14006 * # Available queues may not be in sequential order.
14009 /* This value is applicable to CoS queues only. */
14010 uint8_t queue_id0_service_profile;
14011 /* Lossy (best-effort) */
14012 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
14014 /* Lossless (legacy) */
14015 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
14017 /* Lossless RoCE */
14018 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
14020 /* Lossy RoCE CNP */
14021 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14024 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
14026 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14027 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
14029 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
14030 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
14032 * ID of CoS Queue 1.
14035 * # This ID can be used on any subsequent call to an hwrm command
14036 * that takes a queue id.
14037 * # IDs must always be queried by this command before any use
14038 * by the driver or software.
14039 * # Any driver or software should not make any assumptions about
14041 * # A value of 0xff indicates that the queue is not available.
14042 * # Available queues may not be in sequential order.
14045 /* This value is applicable to CoS queues only. */
14046 uint8_t queue_id1_service_profile;
14047 /* Lossy (best-effort) */
14048 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
14050 /* Lossless (legacy) */
14051 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
14053 /* Lossless RoCE */
14054 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
14056 /* Lossy RoCE CNP */
14057 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14060 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
14062 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14063 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
14065 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
14066 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
14068 * ID of CoS Queue 2.
14071 * # This ID can be used on any subsequent call to an hwrm command
14072 * that takes a queue id.
14073 * # IDs must always be queried by this command before any use
14074 * by the driver or software.
14075 * # Any driver or software should not make any assumptions about
14077 * # A value of 0xff indicates that the queue is not available.
14078 * # Available queues may not be in sequential order.
14081 /* This value is applicable to CoS queues only. */
14082 uint8_t queue_id2_service_profile;
14083 /* Lossy (best-effort) */
14084 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
14086 /* Lossless (legacy) */
14087 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
14089 /* Lossless RoCE */
14090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
14092 /* Lossy RoCE CNP */
14093 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14096 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
14098 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14099 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
14101 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
14102 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
14104 * ID of CoS Queue 3.
14107 * # This ID can be used on any subsequent call to an hwrm command
14108 * that takes a queue id.
14109 * # IDs must always be queried by this command before any use
14110 * by the driver or software.
14111 * # Any driver or software should not make any assumptions about
14113 * # A value of 0xff indicates that the queue is not available.
14114 * # Available queues may not be in sequential order.
14117 /* This value is applicable to CoS queues only. */
14118 uint8_t queue_id3_service_profile;
14119 /* Lossy (best-effort) */
14120 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
14122 /* Lossless (legacy) */
14123 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
14125 /* Lossless RoCE */
14126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
14128 /* Lossy RoCE CNP */
14129 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14132 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
14134 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14135 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
14137 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
14138 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
14140 * ID of CoS Queue 4.
14143 * # This ID can be used on any subsequent call to an hwrm command
14144 * that takes a queue id.
14145 * # IDs must always be queried by this command before any use
14146 * by the driver or software.
14147 * # Any driver or software should not make any assumptions about
14149 * # A value of 0xff indicates that the queue is not available.
14150 * # Available queues may not be in sequential order.
14153 /* This value is applicable to CoS queues only. */
14154 uint8_t queue_id4_service_profile;
14155 /* Lossy (best-effort) */
14156 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
14158 /* Lossless (legacy) */
14159 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
14161 /* Lossless RoCE */
14162 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
14164 /* Lossy RoCE CNP */
14165 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14168 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
14170 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14171 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
14173 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
14174 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
14176 * ID of CoS Queue 5.
14179 * # This ID can be used on any subsequent call to an hwrm command
14180 * that takes a queue id.
14181 * # IDs must always be queried by this command before any use
14182 * by the driver or software.
14183 * # Any driver or software should not make any assumptions about
14185 * # A value of 0xff indicates that the queue is not available.
14186 * # Available queues may not be in sequential order.
14189 /* This value is applicable to CoS queues only. */
14190 uint8_t queue_id5_service_profile;
14191 /* Lossy (best-effort) */
14192 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
14194 /* Lossless (legacy) */
14195 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
14197 /* Lossless RoCE */
14198 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
14200 /* Lossy RoCE CNP */
14201 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14204 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
14206 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14207 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
14209 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
14210 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
14212 * ID of CoS Queue 6.
14215 * # This ID can be used on any subsequent call to an hwrm command
14216 * that takes a queue id.
14217 * # IDs must always be queried by this command before any use
14218 * by the driver or software.
14219 * # Any driver or software should not make any assumptions about
14221 * # A value of 0xff indicates that the queue is not available.
14222 * # Available queues may not be in sequential order.
14225 /* This value is applicable to CoS queues only. */
14226 uint8_t queue_id6_service_profile;
14227 /* Lossy (best-effort) */
14228 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
14230 /* Lossless (legacy) */
14231 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
14233 /* Lossless RoCE */
14234 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
14236 /* Lossy RoCE CNP */
14237 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14240 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
14242 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14243 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
14245 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
14246 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
14248 * ID of CoS Queue 7.
14251 * # This ID can be used on any subsequent call to an hwrm command
14252 * that takes a queue id.
14253 * # IDs must always be queried by this command before any use
14254 * by the driver or software.
14255 * # Any driver or software should not make any assumptions about
14257 * # A value of 0xff indicates that the queue is not available.
14258 * # Available queues may not be in sequential order.
14261 /* This value is applicable to CoS queues only. */
14262 uint8_t queue_id7_service_profile;
14263 /* Lossy (best-effort) */
14264 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
14266 /* Lossless (legacy) */
14267 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
14269 /* Lossless RoCE */
14270 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
14272 /* Lossy RoCE CNP */
14273 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14276 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
14278 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14279 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
14281 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
14282 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
14284 * This field is used in Output records to indicate that the output
14285 * is completely written to RAM. This field should be read as '1'
14286 * to indicate that the output has been completely written.
14287 * When writing a command completion or response to an internal processor,
14288 * the order of writes has to be such that this field is written last.
14291 } __attribute__((packed));
14293 /*******************
14294 * hwrm_queue_qcfg *
14295 *******************/
14298 /* hwrm_queue_qcfg_input (size:192b/24B) */
14299 struct hwrm_queue_qcfg_input {
14300 /* The HWRM command request type. */
14303 * The completion ring to send the completion event on. This should
14304 * be the NQ ID returned from the `nq_alloc` HWRM command.
14306 uint16_t cmpl_ring;
14308 * The sequence ID is used by the driver for tracking multiple
14309 * commands. This ID is treated as opaque data by the firmware and
14310 * the value is returned in the `hwrm_resp_hdr` upon completion.
14314 * The target ID of the command:
14315 * * 0x0-0xFFF8 - The function ID
14316 * * 0xFFF8-0xFFFE - Reserved for internal processors
14319 uint16_t target_id;
14321 * A physical address pointer pointing to a host buffer that the
14322 * command's response data will be written. This can be either a host
14323 * physical address (HPA) or a guest physical address (GPA) and must
14324 * point to a physically contiguous block of memory.
14326 uint64_t resp_addr;
14329 * Enumeration denoting the RX, TX type of the resource.
14330 * This enumeration is used for resources that are similar for both
14331 * TX and RX paths of the chip.
14333 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
14335 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14337 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14338 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
14339 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
14340 /* Queue ID of the queue. */
14342 } __attribute__((packed));
14344 /* hwrm_queue_qcfg_output (size:128b/16B) */
14345 struct hwrm_queue_qcfg_output {
14346 /* The specific error status for the command. */
14347 uint16_t error_code;
14348 /* The HWRM command request type. */
14350 /* The sequence ID from the original command. */
14352 /* The length of the response data in number of bytes. */
14355 * This value is a the estimate packet length used in the
14358 uint32_t queue_len;
14359 /* This value is applicable to CoS queues only. */
14360 uint8_t service_profile;
14361 /* Lossy (best-effort) */
14362 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
14364 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
14365 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14366 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
14367 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
14368 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
14369 /* Information about queue configuration. */
14370 uint8_t queue_cfg_info;
14372 * If this flag is set to '1', then the queue is
14373 * configured asymmetrically on TX and RX sides.
14374 * If this flag is set to '0', then this queue is
14375 * configured symmetrically on TX and RX sides.
14377 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
14381 * This field is used in Output records to indicate that the output
14382 * is completely written to RAM. This field should be read as '1'
14383 * to indicate that the output has been completely written.
14384 * When writing a command completion or response to an internal processor,
14385 * the order of writes has to be such that this field is written last.
14388 } __attribute__((packed));
14390 /******************
14392 ******************/
14395 /* hwrm_queue_cfg_input (size:320b/40B) */
14396 struct hwrm_queue_cfg_input {
14397 /* The HWRM command request type. */
14400 * The completion ring to send the completion event on. This should
14401 * be the NQ ID returned from the `nq_alloc` HWRM command.
14403 uint16_t cmpl_ring;
14405 * The sequence ID is used by the driver for tracking multiple
14406 * commands. This ID is treated as opaque data by the firmware and
14407 * the value is returned in the `hwrm_resp_hdr` upon completion.
14411 * The target ID of the command:
14412 * * 0x0-0xFFF8 - The function ID
14413 * * 0xFFF8-0xFFFE - Reserved for internal processors
14416 uint16_t target_id;
14418 * A physical address pointer pointing to a host buffer that the
14419 * command's response data will be written. This can be either a host
14420 * physical address (HPA) or a guest physical address (GPA) and must
14421 * point to a physically contiguous block of memory.
14423 uint64_t resp_addr;
14426 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
14427 * This enumeration is used for resources that are similar for both
14428 * TX and RX paths of the chip.
14430 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
14431 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
14433 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14435 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14436 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
14437 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
14438 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
14439 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
14442 * This bit must be '1' for the dflt_len field to be
14445 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
14447 * This bit must be '1' for the service_profile field to be
14450 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
14451 /* Queue ID of queue that is to be configured by this function. */
14454 * This value is a the estimate packet length used in the
14456 * Set to 0xFF... (All Fs) to not adjust this value.
14459 /* This value is applicable to CoS queues only. */
14460 uint8_t service_profile;
14461 /* Lossy (best-effort) */
14462 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
14464 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
14465 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14466 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
14467 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
14468 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
14469 uint8_t unused_0[7];
14470 } __attribute__((packed));
14472 /* hwrm_queue_cfg_output (size:128b/16B) */
14473 struct hwrm_queue_cfg_output {
14474 /* The specific error status for the command. */
14475 uint16_t error_code;
14476 /* The HWRM command request type. */
14478 /* The sequence ID from the original command. */
14480 /* The length of the response data in number of bytes. */
14482 uint8_t unused_0[7];
14484 * This field is used in Output records to indicate that the output
14485 * is completely written to RAM. This field should be read as '1'
14486 * to indicate that the output has been completely written.
14487 * When writing a command completion or response to an internal processor,
14488 * the order of writes has to be such that this field is written last.
14491 } __attribute__((packed));
14493 /*****************************
14494 * hwrm_queue_pfcenable_qcfg *
14495 *****************************/
14498 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
14499 struct hwrm_queue_pfcenable_qcfg_input {
14500 /* The HWRM command request type. */
14503 * The completion ring to send the completion event on. This should
14504 * be the NQ ID returned from the `nq_alloc` HWRM command.
14506 uint16_t cmpl_ring;
14508 * The sequence ID is used by the driver for tracking multiple
14509 * commands. This ID is treated as opaque data by the firmware and
14510 * the value is returned in the `hwrm_resp_hdr` upon completion.
14514 * The target ID of the command:
14515 * * 0x0-0xFFF8 - The function ID
14516 * * 0xFFF8-0xFFFE - Reserved for internal processors
14519 uint16_t target_id;
14521 * A physical address pointer pointing to a host buffer that the
14522 * command's response data will be written. This can be either a host
14523 * physical address (HPA) or a guest physical address (GPA) and must
14524 * point to a physically contiguous block of memory.
14526 uint64_t resp_addr;
14528 * Port ID of port for which the table is being configured.
14529 * The HWRM needs to check whether this function is allowed
14530 * to configure pri2cos mapping on this port.
14533 uint8_t unused_0[6];
14534 } __attribute__((packed));
14536 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
14537 struct hwrm_queue_pfcenable_qcfg_output {
14538 /* The specific error status for the command. */
14539 uint16_t error_code;
14540 /* The HWRM command request type. */
14542 /* The sequence ID from the original command. */
14544 /* The length of the response data in number of bytes. */
14547 /* If set to 1, then PFC is enabled on PRI 0. */
14548 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
14550 /* If set to 1, then PFC is enabled on PRI 1. */
14551 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
14553 /* If set to 1, then PFC is enabled on PRI 2. */
14554 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
14556 /* If set to 1, then PFC is enabled on PRI 3. */
14557 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
14559 /* If set to 1, then PFC is enabled on PRI 4. */
14560 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
14562 /* If set to 1, then PFC is enabled on PRI 5. */
14563 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
14565 /* If set to 1, then PFC is enabled on PRI 6. */
14566 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
14568 /* If set to 1, then PFC is enabled on PRI 7. */
14569 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
14571 uint8_t unused_0[3];
14573 * This field is used in Output records to indicate that the output
14574 * is completely written to RAM. This field should be read as '1'
14575 * to indicate that the output has been completely written.
14576 * When writing a command completion or response to an internal processor,
14577 * the order of writes has to be such that this field is written last.
14580 } __attribute__((packed));
14582 /****************************
14583 * hwrm_queue_pfcenable_cfg *
14584 ****************************/
14587 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
14588 struct hwrm_queue_pfcenable_cfg_input {
14589 /* The HWRM command request type. */
14592 * The completion ring to send the completion event on. This should
14593 * be the NQ ID returned from the `nq_alloc` HWRM command.
14595 uint16_t cmpl_ring;
14597 * The sequence ID is used by the driver for tracking multiple
14598 * commands. This ID is treated as opaque data by the firmware and
14599 * the value is returned in the `hwrm_resp_hdr` upon completion.
14603 * The target ID of the command:
14604 * * 0x0-0xFFF8 - The function ID
14605 * * 0xFFF8-0xFFFE - Reserved for internal processors
14608 uint16_t target_id;
14610 * A physical address pointer pointing to a host buffer that the
14611 * command's response data will be written. This can be either a host
14612 * physical address (HPA) or a guest physical address (GPA) and must
14613 * point to a physically contiguous block of memory.
14615 uint64_t resp_addr;
14617 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
14618 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
14620 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
14621 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
14623 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
14624 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
14626 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
14627 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
14629 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
14630 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
14632 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
14633 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
14635 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
14636 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
14638 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
14639 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
14642 * Port ID of port for which the table is being configured.
14643 * The HWRM needs to check whether this function is allowed
14644 * to configure pri2cos mapping on this port.
14647 uint8_t unused_0[2];
14648 } __attribute__((packed));
14650 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
14651 struct hwrm_queue_pfcenable_cfg_output {
14652 /* The specific error status for the command. */
14653 uint16_t error_code;
14654 /* The HWRM command request type. */
14656 /* The sequence ID from the original command. */
14658 /* The length of the response data in number of bytes. */
14660 uint8_t unused_0[7];
14662 * This field is used in Output records to indicate that the output
14663 * is completely written to RAM. This field should be read as '1'
14664 * to indicate that the output has been completely written.
14665 * When writing a command completion or response to an internal processor,
14666 * the order of writes has to be such that this field is written last.
14669 } __attribute__((packed));
14671 /***************************
14672 * hwrm_queue_pri2cos_qcfg *
14673 ***************************/
14676 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
14677 struct hwrm_queue_pri2cos_qcfg_input {
14678 /* The HWRM command request type. */
14681 * The completion ring to send the completion event on. This should
14682 * be the NQ ID returned from the `nq_alloc` HWRM command.
14684 uint16_t cmpl_ring;
14686 * The sequence ID is used by the driver for tracking multiple
14687 * commands. This ID is treated as opaque data by the firmware and
14688 * the value is returned in the `hwrm_resp_hdr` upon completion.
14692 * The target ID of the command:
14693 * * 0x0-0xFFF8 - The function ID
14694 * * 0xFFF8-0xFFFE - Reserved for internal processors
14697 uint16_t target_id;
14699 * A physical address pointer pointing to a host buffer that the
14700 * command's response data will be written. This can be either a host
14701 * physical address (HPA) or a guest physical address (GPA) and must
14702 * point to a physically contiguous block of memory.
14704 uint64_t resp_addr;
14707 * Enumeration denoting the RX, TX type of the resource.
14708 * This enumeration is used for resources that are similar for both
14709 * TX and RX paths of the chip.
14711 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
14713 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14715 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14716 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
14717 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
14719 * When this bit is set to '0', the query is
14720 * for VLAN PRI field in tunnel headers.
14721 * When this bit is set to '1', the query is
14722 * for VLAN PRI field in inner packet headers.
14724 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
14726 * Port ID of port for which the table is being configured.
14727 * The HWRM needs to check whether this function is allowed
14728 * to configure pri2cos mapping on this port.
14731 uint8_t unused_0[3];
14732 } __attribute__((packed));
14734 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
14735 struct hwrm_queue_pri2cos_qcfg_output {
14736 /* The specific error status for the command. */
14737 uint16_t error_code;
14738 /* The HWRM command request type. */
14740 /* The sequence ID from the original command. */
14742 /* The length of the response data in number of bytes. */
14745 * CoS Queue assigned to priority 0. This value can only
14746 * be changed before traffic has started.
14747 * A value of 0xff indicates that no CoS queue is assigned to the
14748 * specified priority.
14750 uint8_t pri0_cos_queue_id;
14752 * CoS Queue assigned to priority 1. This value can only
14753 * be changed before traffic has started.
14754 * A value of 0xff indicates that no CoS queue is assigned to the
14755 * specified priority.
14757 uint8_t pri1_cos_queue_id;
14759 * CoS Queue assigned to priority 2 This value can only
14760 * be changed before traffic has started.
14761 * A value of 0xff indicates that no CoS queue is assigned to the
14762 * specified priority.
14764 uint8_t pri2_cos_queue_id;
14766 * CoS Queue assigned to priority 3. This value can only
14767 * be changed before traffic has started.
14768 * A value of 0xff indicates that no CoS queue is assigned to the
14769 * specified priority.
14771 uint8_t pri3_cos_queue_id;
14773 * CoS Queue assigned to priority 4. This value can only
14774 * be changed before traffic has started.
14775 * A value of 0xff indicates that no CoS queue is assigned to the
14776 * specified priority.
14778 uint8_t pri4_cos_queue_id;
14780 * CoS Queue assigned to priority 5. This value can only
14781 * be changed before traffic has started.
14782 * A value of 0xff indicates that no CoS queue is assigned to the
14783 * specified priority.
14785 uint8_t pri5_cos_queue_id;
14787 * CoS Queue assigned to priority 6. This value can only
14788 * be changed before traffic has started.
14789 * A value of 0xff indicates that no CoS queue is assigned to the
14790 * specified priority.
14792 uint8_t pri6_cos_queue_id;
14794 * CoS Queue assigned to priority 7. This value can only
14795 * be changed before traffic has started.
14796 * A value of 0xff indicates that no CoS queue is assigned to the
14797 * specified priority.
14799 uint8_t pri7_cos_queue_id;
14800 /* Information about queue configuration. */
14801 uint8_t queue_cfg_info;
14803 * If this flag is set to '1', then the PRI to CoS
14804 * configuration is asymmetric on TX and RX sides.
14805 * If this flag is set to '0', then PRI to CoS configuration
14806 * is symmetric on TX and RX sides.
14808 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
14810 uint8_t unused_0[6];
14812 * This field is used in Output records to indicate that the output
14813 * is completely written to RAM. This field should be read as '1'
14814 * to indicate that the output has been completely written.
14815 * When writing a command completion or response to an internal processor,
14816 * the order of writes has to be such that this field is written last.
14819 } __attribute__((packed));
14821 /**************************
14822 * hwrm_queue_pri2cos_cfg *
14823 **************************/
14826 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
14827 struct hwrm_queue_pri2cos_cfg_input {
14828 /* The HWRM command request type. */
14831 * The completion ring to send the completion event on. This should
14832 * be the NQ ID returned from the `nq_alloc` HWRM command.
14834 uint16_t cmpl_ring;
14836 * The sequence ID is used by the driver for tracking multiple
14837 * commands. This ID is treated as opaque data by the firmware and
14838 * the value is returned in the `hwrm_resp_hdr` upon completion.
14842 * The target ID of the command:
14843 * * 0x0-0xFFF8 - The function ID
14844 * * 0xFFF8-0xFFFE - Reserved for internal processors
14847 uint16_t target_id;
14849 * A physical address pointer pointing to a host buffer that the
14850 * command's response data will be written. This can be either a host
14851 * physical address (HPA) or a guest physical address (GPA) and must
14852 * point to a physically contiguous block of memory.
14854 uint64_t resp_addr;
14857 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
14858 * This enumeration is used for resources that are similar for both
14859 * TX and RX paths of the chip.
14861 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
14862 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
14864 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14866 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14867 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
14868 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
14869 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
14870 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
14872 * When this bit is set to '0', the mapping is requested
14873 * for VLAN PRI field in tunnel headers.
14874 * When this bit is set to '1', the mapping is requested
14875 * for VLAN PRI field in inner packet headers.
14877 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
14880 * This bit must be '1' for the pri0_cos_queue_id field to be
14883 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
14886 * This bit must be '1' for the pri1_cos_queue_id field to be
14889 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
14892 * This bit must be '1' for the pri2_cos_queue_id field to be
14895 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
14898 * This bit must be '1' for the pri3_cos_queue_id field to be
14901 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
14904 * This bit must be '1' for the pri4_cos_queue_id field to be
14907 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
14910 * This bit must be '1' for the pri5_cos_queue_id field to be
14913 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
14916 * This bit must be '1' for the pri6_cos_queue_id field to be
14919 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
14922 * This bit must be '1' for the pri7_cos_queue_id field to be
14925 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
14928 * Port ID of port for which the table is being configured.
14929 * The HWRM needs to check whether this function is allowed
14930 * to configure pri2cos mapping on this port.
14934 * CoS Queue assigned to priority 0. This value can only
14935 * be changed before traffic has started.
14937 uint8_t pri0_cos_queue_id;
14939 * CoS Queue assigned to priority 1. This value can only
14940 * be changed before traffic has started.
14942 uint8_t pri1_cos_queue_id;
14944 * CoS Queue assigned to priority 2 This value can only
14945 * be changed before traffic has started.
14947 uint8_t pri2_cos_queue_id;
14949 * CoS Queue assigned to priority 3. This value can only
14950 * be changed before traffic has started.
14952 uint8_t pri3_cos_queue_id;
14954 * CoS Queue assigned to priority 4. This value can only
14955 * be changed before traffic has started.
14957 uint8_t pri4_cos_queue_id;
14959 * CoS Queue assigned to priority 5. This value can only
14960 * be changed before traffic has started.
14962 uint8_t pri5_cos_queue_id;
14964 * CoS Queue assigned to priority 6. This value can only
14965 * be changed before traffic has started.
14967 uint8_t pri6_cos_queue_id;
14969 * CoS Queue assigned to priority 7. This value can only
14970 * be changed before traffic has started.
14972 uint8_t pri7_cos_queue_id;
14973 uint8_t unused_0[7];
14974 } __attribute__((packed));
14976 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
14977 struct hwrm_queue_pri2cos_cfg_output {
14978 /* The specific error status for the command. */
14979 uint16_t error_code;
14980 /* The HWRM command request type. */
14982 /* The sequence ID from the original command. */
14984 /* The length of the response data in number of bytes. */
14986 uint8_t unused_0[7];
14988 * This field is used in Output records to indicate that the output
14989 * is completely written to RAM. This field should be read as '1'
14990 * to indicate that the output has been completely written.
14991 * When writing a command completion or response to an internal processor,
14992 * the order of writes has to be such that this field is written last.
14995 } __attribute__((packed));
14997 /**************************
14998 * hwrm_queue_cos2bw_qcfg *
14999 **************************/
15002 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
15003 struct hwrm_queue_cos2bw_qcfg_input {
15004 /* The HWRM command request type. */
15007 * The completion ring to send the completion event on. This should
15008 * be the NQ ID returned from the `nq_alloc` HWRM command.
15010 uint16_t cmpl_ring;
15012 * The sequence ID is used by the driver for tracking multiple
15013 * commands. This ID is treated as opaque data by the firmware and
15014 * the value is returned in the `hwrm_resp_hdr` upon completion.
15018 * The target ID of the command:
15019 * * 0x0-0xFFF8 - The function ID
15020 * * 0xFFF8-0xFFFE - Reserved for internal processors
15023 uint16_t target_id;
15025 * A physical address pointer pointing to a host buffer that the
15026 * command's response data will be written. This can be either a host
15027 * physical address (HPA) or a guest physical address (GPA) and must
15028 * point to a physically contiguous block of memory.
15030 uint64_t resp_addr;
15032 * Port ID of port for which the table is being configured.
15033 * The HWRM needs to check whether this function is allowed
15034 * to configure TC BW assignment on this port.
15037 uint8_t unused_0[6];
15038 } __attribute__((packed));
15040 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
15041 struct hwrm_queue_cos2bw_qcfg_output {
15042 /* The specific error status for the command. */
15043 uint16_t error_code;
15044 /* The HWRM command request type. */
15046 /* The sequence ID from the original command. */
15048 /* The length of the response data in number of bytes. */
15050 /* ID of CoS Queue 0. */
15055 * Minimum BW allocated to CoS Queue.
15056 * The HWRM will translate this value into byte counter and
15057 * time interval used for this COS inside the device.
15059 uint32_t queue_id0_min_bw;
15060 /* The bandwidth value. */
15061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
15062 UINT32_C(0xfffffff)
15063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
15065 /* The granularity of the value (bits or bytes). */
15066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
15067 UINT32_C(0x10000000)
15068 /* Value is in bits. */
15069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
15070 (UINT32_C(0x0) << 28)
15071 /* Value is in bytes. */
15072 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
15073 (UINT32_C(0x1) << 28)
15074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
15075 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
15076 /* bw_value_unit is 3 b */
15077 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
15078 UINT32_C(0xe0000000)
15079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
15081 /* Value is in Mb or MB (base 10). */
15082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
15083 (UINT32_C(0x0) << 29)
15084 /* Value is in Kb or KB (base 10). */
15085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
15086 (UINT32_C(0x2) << 29)
15087 /* Value is in bits or bytes. */
15088 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
15089 (UINT32_C(0x4) << 29)
15090 /* Value is in Gb or GB (base 10). */
15091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
15092 (UINT32_C(0x6) << 29)
15093 /* Value is in 1/100th of a percentage of total bandwidth. */
15094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15095 (UINT32_C(0x1) << 29)
15097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
15098 (UINT32_C(0x7) << 29)
15099 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
15100 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
15102 * Maximum BW allocated to CoS Queue.
15103 * The HWRM will translate this value into byte counter and
15104 * time interval used for this COS inside the device.
15106 uint32_t queue_id0_max_bw;
15107 /* The bandwidth value. */
15108 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
15109 UINT32_C(0xfffffff)
15110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
15112 /* The granularity of the value (bits or bytes). */
15113 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
15114 UINT32_C(0x10000000)
15115 /* Value is in bits. */
15116 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
15117 (UINT32_C(0x0) << 28)
15118 /* Value is in bytes. */
15119 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
15120 (UINT32_C(0x1) << 28)
15121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
15122 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
15123 /* bw_value_unit is 3 b */
15124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
15125 UINT32_C(0xe0000000)
15126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
15128 /* Value is in Mb or MB (base 10). */
15129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
15130 (UINT32_C(0x0) << 29)
15131 /* Value is in Kb or KB (base 10). */
15132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
15133 (UINT32_C(0x2) << 29)
15134 /* Value is in bits or bytes. */
15135 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
15136 (UINT32_C(0x4) << 29)
15137 /* Value is in Gb or GB (base 10). */
15138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
15139 (UINT32_C(0x6) << 29)
15140 /* Value is in 1/100th of a percentage of total bandwidth. */
15141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15142 (UINT32_C(0x1) << 29)
15144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
15145 (UINT32_C(0x7) << 29)
15146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
15147 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
15148 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15149 uint8_t queue_id0_tsa_assign;
15150 /* Strict Priority */
15151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
15153 /* Enhanced Transmission Selection */
15154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
15157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
15160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
15163 * Priority level for strict priority. Valid only when the
15164 * tsa_assign is 0 - Strict Priority (SP)
15165 * 0..7 - Valid values.
15166 * 8..255 - Reserved.
15168 uint8_t queue_id0_pri_lvl;
15170 * Weight used to allocate remaining BW for this COS after
15171 * servicing guaranteed bandwidths for all COS.
15173 uint8_t queue_id0_bw_weight;
15174 /* ID of CoS Queue 1. */
15177 * Minimum BW allocated to CoS Queue.
15178 * The HWRM will translate this value into byte counter and
15179 * time interval used for this COS inside the device.
15181 uint32_t queue_id1_min_bw;
15182 /* The bandwidth value. */
15183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
15184 UINT32_C(0xfffffff)
15185 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
15187 /* The granularity of the value (bits or bytes). */
15188 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
15189 UINT32_C(0x10000000)
15190 /* Value is in bits. */
15191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
15192 (UINT32_C(0x0) << 28)
15193 /* Value is in bytes. */
15194 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
15195 (UINT32_C(0x1) << 28)
15196 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
15197 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
15198 /* bw_value_unit is 3 b */
15199 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
15200 UINT32_C(0xe0000000)
15201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
15203 /* Value is in Mb or MB (base 10). */
15204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
15205 (UINT32_C(0x0) << 29)
15206 /* Value is in Kb or KB (base 10). */
15207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
15208 (UINT32_C(0x2) << 29)
15209 /* Value is in bits or bytes. */
15210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
15211 (UINT32_C(0x4) << 29)
15212 /* Value is in Gb or GB (base 10). */
15213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
15214 (UINT32_C(0x6) << 29)
15215 /* Value is in 1/100th of a percentage of total bandwidth. */
15216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15217 (UINT32_C(0x1) << 29)
15219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
15220 (UINT32_C(0x7) << 29)
15221 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
15222 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
15224 * Maximum BW allocated to CoS queue.
15225 * The HWRM will translate this value into byte counter and
15226 * time interval used for this COS inside the device.
15228 uint32_t queue_id1_max_bw;
15229 /* The bandwidth value. */
15230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
15231 UINT32_C(0xfffffff)
15232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
15234 /* The granularity of the value (bits or bytes). */
15235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
15236 UINT32_C(0x10000000)
15237 /* Value is in bits. */
15238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
15239 (UINT32_C(0x0) << 28)
15240 /* Value is in bytes. */
15241 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
15242 (UINT32_C(0x1) << 28)
15243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
15244 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
15245 /* bw_value_unit is 3 b */
15246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
15247 UINT32_C(0xe0000000)
15248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
15250 /* Value is in Mb or MB (base 10). */
15251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
15252 (UINT32_C(0x0) << 29)
15253 /* Value is in Kb or KB (base 10). */
15254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
15255 (UINT32_C(0x2) << 29)
15256 /* Value is in bits or bytes. */
15257 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
15258 (UINT32_C(0x4) << 29)
15259 /* Value is in Gb or GB (base 10). */
15260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
15261 (UINT32_C(0x6) << 29)
15262 /* Value is in 1/100th of a percentage of total bandwidth. */
15263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15264 (UINT32_C(0x1) << 29)
15266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
15267 (UINT32_C(0x7) << 29)
15268 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
15269 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
15270 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15271 uint8_t queue_id1_tsa_assign;
15272 /* Strict Priority */
15273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
15275 /* Enhanced Transmission Selection */
15276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
15279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
15282 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
15285 * Priority level for strict priority. Valid only when the
15286 * tsa_assign is 0 - Strict Priority (SP)
15287 * 0..7 - Valid values.
15288 * 8..255 - Reserved.
15290 uint8_t queue_id1_pri_lvl;
15292 * Weight used to allocate remaining BW for this COS after
15293 * servicing guaranteed bandwidths for all COS.
15295 uint8_t queue_id1_bw_weight;
15296 /* ID of CoS Queue 2. */
15299 * Minimum BW allocated to CoS Queue.
15300 * The HWRM will translate this value into byte counter and
15301 * time interval used for this COS inside the device.
15303 uint32_t queue_id2_min_bw;
15304 /* The bandwidth value. */
15305 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
15306 UINT32_C(0xfffffff)
15307 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
15309 /* The granularity of the value (bits or bytes). */
15310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
15311 UINT32_C(0x10000000)
15312 /* Value is in bits. */
15313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
15314 (UINT32_C(0x0) << 28)
15315 /* Value is in bytes. */
15316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
15317 (UINT32_C(0x1) << 28)
15318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
15319 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
15320 /* bw_value_unit is 3 b */
15321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
15322 UINT32_C(0xe0000000)
15323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
15325 /* Value is in Mb or MB (base 10). */
15326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
15327 (UINT32_C(0x0) << 29)
15328 /* Value is in Kb or KB (base 10). */
15329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
15330 (UINT32_C(0x2) << 29)
15331 /* Value is in bits or bytes. */
15332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
15333 (UINT32_C(0x4) << 29)
15334 /* Value is in Gb or GB (base 10). */
15335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
15336 (UINT32_C(0x6) << 29)
15337 /* Value is in 1/100th of a percentage of total bandwidth. */
15338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15339 (UINT32_C(0x1) << 29)
15341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
15342 (UINT32_C(0x7) << 29)
15343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
15344 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
15346 * Maximum BW allocated to CoS queue.
15347 * The HWRM will translate this value into byte counter and
15348 * time interval used for this COS inside the device.
15350 uint32_t queue_id2_max_bw;
15351 /* The bandwidth value. */
15352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
15353 UINT32_C(0xfffffff)
15354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
15356 /* The granularity of the value (bits or bytes). */
15357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
15358 UINT32_C(0x10000000)
15359 /* Value is in bits. */
15360 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
15361 (UINT32_C(0x0) << 28)
15362 /* Value is in bytes. */
15363 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
15364 (UINT32_C(0x1) << 28)
15365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
15366 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
15367 /* bw_value_unit is 3 b */
15368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
15369 UINT32_C(0xe0000000)
15370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
15372 /* Value is in Mb or MB (base 10). */
15373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
15374 (UINT32_C(0x0) << 29)
15375 /* Value is in Kb or KB (base 10). */
15376 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
15377 (UINT32_C(0x2) << 29)
15378 /* Value is in bits or bytes. */
15379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
15380 (UINT32_C(0x4) << 29)
15381 /* Value is in Gb or GB (base 10). */
15382 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
15383 (UINT32_C(0x6) << 29)
15384 /* Value is in 1/100th of a percentage of total bandwidth. */
15385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15386 (UINT32_C(0x1) << 29)
15388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
15389 (UINT32_C(0x7) << 29)
15390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
15391 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
15392 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15393 uint8_t queue_id2_tsa_assign;
15394 /* Strict Priority */
15395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
15397 /* Enhanced Transmission Selection */
15398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
15401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
15404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
15407 * Priority level for strict priority. Valid only when the
15408 * tsa_assign is 0 - Strict Priority (SP)
15409 * 0..7 - Valid values.
15410 * 8..255 - Reserved.
15412 uint8_t queue_id2_pri_lvl;
15414 * Weight used to allocate remaining BW for this COS after
15415 * servicing guaranteed bandwidths for all COS.
15417 uint8_t queue_id2_bw_weight;
15418 /* ID of CoS Queue 3. */
15421 * Minimum BW allocated to CoS Queue.
15422 * The HWRM will translate this value into byte counter and
15423 * time interval used for this COS inside the device.
15425 uint32_t queue_id3_min_bw;
15426 /* The bandwidth value. */
15427 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
15428 UINT32_C(0xfffffff)
15429 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
15431 /* The granularity of the value (bits or bytes). */
15432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
15433 UINT32_C(0x10000000)
15434 /* Value is in bits. */
15435 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
15436 (UINT32_C(0x0) << 28)
15437 /* Value is in bytes. */
15438 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
15439 (UINT32_C(0x1) << 28)
15440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
15441 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
15442 /* bw_value_unit is 3 b */
15443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
15444 UINT32_C(0xe0000000)
15445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
15447 /* Value is in Mb or MB (base 10). */
15448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
15449 (UINT32_C(0x0) << 29)
15450 /* Value is in Kb or KB (base 10). */
15451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
15452 (UINT32_C(0x2) << 29)
15453 /* Value is in bits or bytes. */
15454 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
15455 (UINT32_C(0x4) << 29)
15456 /* Value is in Gb or GB (base 10). */
15457 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
15458 (UINT32_C(0x6) << 29)
15459 /* Value is in 1/100th of a percentage of total bandwidth. */
15460 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15461 (UINT32_C(0x1) << 29)
15463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
15464 (UINT32_C(0x7) << 29)
15465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
15466 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
15468 * Maximum BW allocated to CoS queue.
15469 * The HWRM will translate this value into byte counter and
15470 * time interval used for this COS inside the device.
15472 uint32_t queue_id3_max_bw;
15473 /* The bandwidth value. */
15474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
15475 UINT32_C(0xfffffff)
15476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
15478 /* The granularity of the value (bits or bytes). */
15479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
15480 UINT32_C(0x10000000)
15481 /* Value is in bits. */
15482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
15483 (UINT32_C(0x0) << 28)
15484 /* Value is in bytes. */
15485 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
15486 (UINT32_C(0x1) << 28)
15487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
15488 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
15489 /* bw_value_unit is 3 b */
15490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
15491 UINT32_C(0xe0000000)
15492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
15494 /* Value is in Mb or MB (base 10). */
15495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
15496 (UINT32_C(0x0) << 29)
15497 /* Value is in Kb or KB (base 10). */
15498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
15499 (UINT32_C(0x2) << 29)
15500 /* Value is in bits or bytes. */
15501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
15502 (UINT32_C(0x4) << 29)
15503 /* Value is in Gb or GB (base 10). */
15504 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
15505 (UINT32_C(0x6) << 29)
15506 /* Value is in 1/100th of a percentage of total bandwidth. */
15507 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15508 (UINT32_C(0x1) << 29)
15510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
15511 (UINT32_C(0x7) << 29)
15512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
15513 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
15514 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15515 uint8_t queue_id3_tsa_assign;
15516 /* Strict Priority */
15517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
15519 /* Enhanced Transmission Selection */
15520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
15523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
15526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
15529 * Priority level for strict priority. Valid only when the
15530 * tsa_assign is 0 - Strict Priority (SP)
15531 * 0..7 - Valid values.
15532 * 8..255 - Reserved.
15534 uint8_t queue_id3_pri_lvl;
15536 * Weight used to allocate remaining BW for this COS after
15537 * servicing guaranteed bandwidths for all COS.
15539 uint8_t queue_id3_bw_weight;
15540 /* ID of CoS Queue 4. */
15543 * Minimum BW allocated to CoS Queue.
15544 * The HWRM will translate this value into byte counter and
15545 * time interval used for this COS inside the device.
15547 uint32_t queue_id4_min_bw;
15548 /* The bandwidth value. */
15549 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
15550 UINT32_C(0xfffffff)
15551 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
15553 /* The granularity of the value (bits or bytes). */
15554 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
15555 UINT32_C(0x10000000)
15556 /* Value is in bits. */
15557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
15558 (UINT32_C(0x0) << 28)
15559 /* Value is in bytes. */
15560 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
15561 (UINT32_C(0x1) << 28)
15562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
15563 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
15564 /* bw_value_unit is 3 b */
15565 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
15566 UINT32_C(0xe0000000)
15567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
15569 /* Value is in Mb or MB (base 10). */
15570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
15571 (UINT32_C(0x0) << 29)
15572 /* Value is in Kb or KB (base 10). */
15573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
15574 (UINT32_C(0x2) << 29)
15575 /* Value is in bits or bytes. */
15576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
15577 (UINT32_C(0x4) << 29)
15578 /* Value is in Gb or GB (base 10). */
15579 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
15580 (UINT32_C(0x6) << 29)
15581 /* Value is in 1/100th of a percentage of total bandwidth. */
15582 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15583 (UINT32_C(0x1) << 29)
15585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
15586 (UINT32_C(0x7) << 29)
15587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
15588 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
15590 * Maximum BW allocated to CoS queue.
15591 * The HWRM will translate this value into byte counter and
15592 * time interval used for this COS inside the device.
15594 uint32_t queue_id4_max_bw;
15595 /* The bandwidth value. */
15596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
15597 UINT32_C(0xfffffff)
15598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
15600 /* The granularity of the value (bits or bytes). */
15601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
15602 UINT32_C(0x10000000)
15603 /* Value is in bits. */
15604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
15605 (UINT32_C(0x0) << 28)
15606 /* Value is in bytes. */
15607 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
15608 (UINT32_C(0x1) << 28)
15609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
15610 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
15611 /* bw_value_unit is 3 b */
15612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
15613 UINT32_C(0xe0000000)
15614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
15616 /* Value is in Mb or MB (base 10). */
15617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
15618 (UINT32_C(0x0) << 29)
15619 /* Value is in Kb or KB (base 10). */
15620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
15621 (UINT32_C(0x2) << 29)
15622 /* Value is in bits or bytes. */
15623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
15624 (UINT32_C(0x4) << 29)
15625 /* Value is in Gb or GB (base 10). */
15626 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
15627 (UINT32_C(0x6) << 29)
15628 /* Value is in 1/100th of a percentage of total bandwidth. */
15629 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15630 (UINT32_C(0x1) << 29)
15632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
15633 (UINT32_C(0x7) << 29)
15634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
15635 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
15636 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15637 uint8_t queue_id4_tsa_assign;
15638 /* Strict Priority */
15639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
15641 /* Enhanced Transmission Selection */
15642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
15645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
15648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
15651 * Priority level for strict priority. Valid only when the
15652 * tsa_assign is 0 - Strict Priority (SP)
15653 * 0..7 - Valid values.
15654 * 8..255 - Reserved.
15656 uint8_t queue_id4_pri_lvl;
15658 * Weight used to allocate remaining BW for this COS after
15659 * servicing guaranteed bandwidths for all COS.
15661 uint8_t queue_id4_bw_weight;
15662 /* ID of CoS Queue 5. */
15665 * Minimum BW allocated to CoS Queue.
15666 * The HWRM will translate this value into byte counter and
15667 * time interval used for this COS inside the device.
15669 uint32_t queue_id5_min_bw;
15670 /* The bandwidth value. */
15671 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
15672 UINT32_C(0xfffffff)
15673 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
15675 /* The granularity of the value (bits or bytes). */
15676 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
15677 UINT32_C(0x10000000)
15678 /* Value is in bits. */
15679 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
15680 (UINT32_C(0x0) << 28)
15681 /* Value is in bytes. */
15682 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
15683 (UINT32_C(0x1) << 28)
15684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
15685 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
15686 /* bw_value_unit is 3 b */
15687 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
15688 UINT32_C(0xe0000000)
15689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
15691 /* Value is in Mb or MB (base 10). */
15692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
15693 (UINT32_C(0x0) << 29)
15694 /* Value is in Kb or KB (base 10). */
15695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
15696 (UINT32_C(0x2) << 29)
15697 /* Value is in bits or bytes. */
15698 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
15699 (UINT32_C(0x4) << 29)
15700 /* Value is in Gb or GB (base 10). */
15701 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
15702 (UINT32_C(0x6) << 29)
15703 /* Value is in 1/100th of a percentage of total bandwidth. */
15704 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15705 (UINT32_C(0x1) << 29)
15707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
15708 (UINT32_C(0x7) << 29)
15709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
15710 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
15712 * Maximum BW allocated to CoS queue.
15713 * The HWRM will translate this value into byte counter and
15714 * time interval used for this COS inside the device.
15716 uint32_t queue_id5_max_bw;
15717 /* The bandwidth value. */
15718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
15719 UINT32_C(0xfffffff)
15720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
15722 /* The granularity of the value (bits or bytes). */
15723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
15724 UINT32_C(0x10000000)
15725 /* Value is in bits. */
15726 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
15727 (UINT32_C(0x0) << 28)
15728 /* Value is in bytes. */
15729 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
15730 (UINT32_C(0x1) << 28)
15731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
15732 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
15733 /* bw_value_unit is 3 b */
15734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
15735 UINT32_C(0xe0000000)
15736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
15738 /* Value is in Mb or MB (base 10). */
15739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
15740 (UINT32_C(0x0) << 29)
15741 /* Value is in Kb or KB (base 10). */
15742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
15743 (UINT32_C(0x2) << 29)
15744 /* Value is in bits or bytes. */
15745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
15746 (UINT32_C(0x4) << 29)
15747 /* Value is in Gb or GB (base 10). */
15748 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
15749 (UINT32_C(0x6) << 29)
15750 /* Value is in 1/100th of a percentage of total bandwidth. */
15751 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15752 (UINT32_C(0x1) << 29)
15754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
15755 (UINT32_C(0x7) << 29)
15756 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
15757 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
15758 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15759 uint8_t queue_id5_tsa_assign;
15760 /* Strict Priority */
15761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
15763 /* Enhanced Transmission Selection */
15764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
15767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
15770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
15773 * Priority level for strict priority. Valid only when the
15774 * tsa_assign is 0 - Strict Priority (SP)
15775 * 0..7 - Valid values.
15776 * 8..255 - Reserved.
15778 uint8_t queue_id5_pri_lvl;
15780 * Weight used to allocate remaining BW for this COS after
15781 * servicing guaranteed bandwidths for all COS.
15783 uint8_t queue_id5_bw_weight;
15784 /* ID of CoS Queue 6. */
15787 * Minimum BW allocated to CoS Queue.
15788 * The HWRM will translate this value into byte counter and
15789 * time interval used for this COS inside the device.
15791 uint32_t queue_id6_min_bw;
15792 /* The bandwidth value. */
15793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
15794 UINT32_C(0xfffffff)
15795 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
15797 /* The granularity of the value (bits or bytes). */
15798 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
15799 UINT32_C(0x10000000)
15800 /* Value is in bits. */
15801 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
15802 (UINT32_C(0x0) << 28)
15803 /* Value is in bytes. */
15804 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
15805 (UINT32_C(0x1) << 28)
15806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
15807 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
15808 /* bw_value_unit is 3 b */
15809 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
15810 UINT32_C(0xe0000000)
15811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
15813 /* Value is in Mb or MB (base 10). */
15814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
15815 (UINT32_C(0x0) << 29)
15816 /* Value is in Kb or KB (base 10). */
15817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
15818 (UINT32_C(0x2) << 29)
15819 /* Value is in bits or bytes. */
15820 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
15821 (UINT32_C(0x4) << 29)
15822 /* Value is in Gb or GB (base 10). */
15823 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
15824 (UINT32_C(0x6) << 29)
15825 /* Value is in 1/100th of a percentage of total bandwidth. */
15826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15827 (UINT32_C(0x1) << 29)
15829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
15830 (UINT32_C(0x7) << 29)
15831 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
15832 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
15834 * Maximum BW allocated to CoS queue.
15835 * The HWRM will translate this value into byte counter and
15836 * time interval used for this COS inside the device.
15838 uint32_t queue_id6_max_bw;
15839 /* The bandwidth value. */
15840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
15841 UINT32_C(0xfffffff)
15842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
15844 /* The granularity of the value (bits or bytes). */
15845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
15846 UINT32_C(0x10000000)
15847 /* Value is in bits. */
15848 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
15849 (UINT32_C(0x0) << 28)
15850 /* Value is in bytes. */
15851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
15852 (UINT32_C(0x1) << 28)
15853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
15854 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
15855 /* bw_value_unit is 3 b */
15856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
15857 UINT32_C(0xe0000000)
15858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
15860 /* Value is in Mb or MB (base 10). */
15861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
15862 (UINT32_C(0x0) << 29)
15863 /* Value is in Kb or KB (base 10). */
15864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
15865 (UINT32_C(0x2) << 29)
15866 /* Value is in bits or bytes. */
15867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
15868 (UINT32_C(0x4) << 29)
15869 /* Value is in Gb or GB (base 10). */
15870 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
15871 (UINT32_C(0x6) << 29)
15872 /* Value is in 1/100th of a percentage of total bandwidth. */
15873 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15874 (UINT32_C(0x1) << 29)
15876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
15877 (UINT32_C(0x7) << 29)
15878 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
15879 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
15880 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15881 uint8_t queue_id6_tsa_assign;
15882 /* Strict Priority */
15883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
15885 /* Enhanced Transmission Selection */
15886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
15889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
15892 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
15895 * Priority level for strict priority. Valid only when the
15896 * tsa_assign is 0 - Strict Priority (SP)
15897 * 0..7 - Valid values.
15898 * 8..255 - Reserved.
15900 uint8_t queue_id6_pri_lvl;
15902 * Weight used to allocate remaining BW for this COS after
15903 * servicing guaranteed bandwidths for all COS.
15905 uint8_t queue_id6_bw_weight;
15906 /* ID of CoS Queue 7. */
15909 * Minimum BW allocated to CoS Queue.
15910 * The HWRM will translate this value into byte counter and
15911 * time interval used for this COS inside the device.
15913 uint32_t queue_id7_min_bw;
15914 /* The bandwidth value. */
15915 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
15916 UINT32_C(0xfffffff)
15917 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
15919 /* The granularity of the value (bits or bytes). */
15920 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
15921 UINT32_C(0x10000000)
15922 /* Value is in bits. */
15923 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
15924 (UINT32_C(0x0) << 28)
15925 /* Value is in bytes. */
15926 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
15927 (UINT32_C(0x1) << 28)
15928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
15929 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
15930 /* bw_value_unit is 3 b */
15931 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
15932 UINT32_C(0xe0000000)
15933 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
15935 /* Value is in Mb or MB (base 10). */
15936 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
15937 (UINT32_C(0x0) << 29)
15938 /* Value is in Kb or KB (base 10). */
15939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
15940 (UINT32_C(0x2) << 29)
15941 /* Value is in bits or bytes. */
15942 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
15943 (UINT32_C(0x4) << 29)
15944 /* Value is in Gb or GB (base 10). */
15945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
15946 (UINT32_C(0x6) << 29)
15947 /* Value is in 1/100th of a percentage of total bandwidth. */
15948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15949 (UINT32_C(0x1) << 29)
15951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
15952 (UINT32_C(0x7) << 29)
15953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
15954 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
15956 * Maximum BW allocated to CoS queue.
15957 * The HWRM will translate this value into byte counter and
15958 * time interval used for this COS inside the device.
15960 uint32_t queue_id7_max_bw;
15961 /* The bandwidth value. */
15962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
15963 UINT32_C(0xfffffff)
15964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
15966 /* The granularity of the value (bits or bytes). */
15967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
15968 UINT32_C(0x10000000)
15969 /* Value is in bits. */
15970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
15971 (UINT32_C(0x0) << 28)
15972 /* Value is in bytes. */
15973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
15974 (UINT32_C(0x1) << 28)
15975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
15976 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
15977 /* bw_value_unit is 3 b */
15978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
15979 UINT32_C(0xe0000000)
15980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
15982 /* Value is in Mb or MB (base 10). */
15983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
15984 (UINT32_C(0x0) << 29)
15985 /* Value is in Kb or KB (base 10). */
15986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
15987 (UINT32_C(0x2) << 29)
15988 /* Value is in bits or bytes. */
15989 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
15990 (UINT32_C(0x4) << 29)
15991 /* Value is in Gb or GB (base 10). */
15992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
15993 (UINT32_C(0x6) << 29)
15994 /* Value is in 1/100th of a percentage of total bandwidth. */
15995 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15996 (UINT32_C(0x1) << 29)
15998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
15999 (UINT32_C(0x7) << 29)
16000 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
16001 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
16002 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16003 uint8_t queue_id7_tsa_assign;
16004 /* Strict Priority */
16005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
16007 /* Enhanced Transmission Selection */
16008 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
16011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
16014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
16017 * Priority level for strict priority. Valid only when the
16018 * tsa_assign is 0 - Strict Priority (SP)
16019 * 0..7 - Valid values.
16020 * 8..255 - Reserved.
16022 uint8_t queue_id7_pri_lvl;
16024 * Weight used to allocate remaining BW for this COS after
16025 * servicing guaranteed bandwidths for all COS.
16027 uint8_t queue_id7_bw_weight;
16028 uint8_t unused_2[4];
16030 * This field is used in Output records to indicate that the output
16031 * is completely written to RAM. This field should be read as '1'
16032 * to indicate that the output has been completely written.
16033 * When writing a command completion or response to an internal processor,
16034 * the order of writes has to be such that this field is written last.
16037 } __attribute__((packed));
16039 /*************************
16040 * hwrm_queue_cos2bw_cfg *
16041 *************************/
16044 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
16045 struct hwrm_queue_cos2bw_cfg_input {
16046 /* The HWRM command request type. */
16049 * The completion ring to send the completion event on. This should
16050 * be the NQ ID returned from the `nq_alloc` HWRM command.
16052 uint16_t cmpl_ring;
16054 * The sequence ID is used by the driver for tracking multiple
16055 * commands. This ID is treated as opaque data by the firmware and
16056 * the value is returned in the `hwrm_resp_hdr` upon completion.
16060 * The target ID of the command:
16061 * * 0x0-0xFFF8 - The function ID
16062 * * 0xFFF8-0xFFFE - Reserved for internal processors
16065 uint16_t target_id;
16067 * A physical address pointer pointing to a host buffer that the
16068 * command's response data will be written. This can be either a host
16069 * physical address (HPA) or a guest physical address (GPA) and must
16070 * point to a physically contiguous block of memory.
16072 uint64_t resp_addr;
16076 * If this bit is set to 1, then all queue_id0 related
16077 * parameters in this command are valid.
16079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
16082 * If this bit is set to 1, then all queue_id1 related
16083 * parameters in this command are valid.
16085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
16088 * If this bit is set to 1, then all queue_id2 related
16089 * parameters in this command are valid.
16091 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
16094 * If this bit is set to 1, then all queue_id3 related
16095 * parameters in this command are valid.
16097 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
16100 * If this bit is set to 1, then all queue_id4 related
16101 * parameters in this command are valid.
16103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
16106 * If this bit is set to 1, then all queue_id5 related
16107 * parameters in this command are valid.
16109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
16112 * If this bit is set to 1, then all queue_id6 related
16113 * parameters in this command are valid.
16115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
16118 * If this bit is set to 1, then all queue_id7 related
16119 * parameters in this command are valid.
16121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
16124 * Port ID of port for which the table is being configured.
16125 * The HWRM needs to check whether this function is allowed
16126 * to configure TC BW assignment on this port.
16129 /* ID of CoS Queue 0. */
16133 * Minimum BW allocated to CoS Queue.
16134 * The HWRM will translate this value into byte counter and
16135 * time interval used for this COS inside the device.
16137 uint32_t queue_id0_min_bw;
16138 /* The bandwidth value. */
16139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
16140 UINT32_C(0xfffffff)
16141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
16143 /* The granularity of the value (bits or bytes). */
16144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
16145 UINT32_C(0x10000000)
16146 /* Value is in bits. */
16147 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
16148 (UINT32_C(0x0) << 28)
16149 /* Value is in bytes. */
16150 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
16151 (UINT32_C(0x1) << 28)
16152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
16153 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
16154 /* bw_value_unit is 3 b */
16155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
16156 UINT32_C(0xe0000000)
16157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
16159 /* Value is in Mb or MB (base 10). */
16160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
16161 (UINT32_C(0x0) << 29)
16162 /* Value is in Kb or KB (base 10). */
16163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
16164 (UINT32_C(0x2) << 29)
16165 /* Value is in bits or bytes. */
16166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
16167 (UINT32_C(0x4) << 29)
16168 /* Value is in Gb or GB (base 10). */
16169 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
16170 (UINT32_C(0x6) << 29)
16171 /* Value is in 1/100th of a percentage of total bandwidth. */
16172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16173 (UINT32_C(0x1) << 29)
16175 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
16176 (UINT32_C(0x7) << 29)
16177 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
16178 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
16180 * Maximum BW allocated to CoS Queue.
16181 * The HWRM will translate this value into byte counter and
16182 * time interval used for this COS inside the device.
16184 uint32_t queue_id0_max_bw;
16185 /* The bandwidth value. */
16186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
16187 UINT32_C(0xfffffff)
16188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
16190 /* The granularity of the value (bits or bytes). */
16191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
16192 UINT32_C(0x10000000)
16193 /* Value is in bits. */
16194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
16195 (UINT32_C(0x0) << 28)
16196 /* Value is in bytes. */
16197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
16198 (UINT32_C(0x1) << 28)
16199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
16200 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
16201 /* bw_value_unit is 3 b */
16202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
16203 UINT32_C(0xe0000000)
16204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
16206 /* Value is in Mb or MB (base 10). */
16207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
16208 (UINT32_C(0x0) << 29)
16209 /* Value is in Kb or KB (base 10). */
16210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
16211 (UINT32_C(0x2) << 29)
16212 /* Value is in bits or bytes. */
16213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
16214 (UINT32_C(0x4) << 29)
16215 /* Value is in Gb or GB (base 10). */
16216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
16217 (UINT32_C(0x6) << 29)
16218 /* Value is in 1/100th of a percentage of total bandwidth. */
16219 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16220 (UINT32_C(0x1) << 29)
16222 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
16223 (UINT32_C(0x7) << 29)
16224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
16225 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
16226 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16227 uint8_t queue_id0_tsa_assign;
16228 /* Strict Priority */
16229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
16231 /* Enhanced Transmission Selection */
16232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
16235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
16238 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
16241 * Priority level for strict priority. Valid only when the
16242 * tsa_assign is 0 - Strict Priority (SP)
16243 * 0..7 - Valid values.
16244 * 8..255 - Reserved.
16246 uint8_t queue_id0_pri_lvl;
16248 * Weight used to allocate remaining BW for this COS after
16249 * servicing guaranteed bandwidths for all COS.
16251 uint8_t queue_id0_bw_weight;
16252 /* ID of CoS Queue 1. */
16255 * Minimum BW allocated to CoS Queue.
16256 * The HWRM will translate this value into byte counter and
16257 * time interval used for this COS inside the device.
16259 uint32_t queue_id1_min_bw;
16260 /* The bandwidth value. */
16261 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
16262 UINT32_C(0xfffffff)
16263 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
16265 /* The granularity of the value (bits or bytes). */
16266 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
16267 UINT32_C(0x10000000)
16268 /* Value is in bits. */
16269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
16270 (UINT32_C(0x0) << 28)
16271 /* Value is in bytes. */
16272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
16273 (UINT32_C(0x1) << 28)
16274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
16275 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
16276 /* bw_value_unit is 3 b */
16277 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
16278 UINT32_C(0xe0000000)
16279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
16281 /* Value is in Mb or MB (base 10). */
16282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
16283 (UINT32_C(0x0) << 29)
16284 /* Value is in Kb or KB (base 10). */
16285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
16286 (UINT32_C(0x2) << 29)
16287 /* Value is in bits or bytes. */
16288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
16289 (UINT32_C(0x4) << 29)
16290 /* Value is in Gb or GB (base 10). */
16291 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
16292 (UINT32_C(0x6) << 29)
16293 /* Value is in 1/100th of a percentage of total bandwidth. */
16294 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16295 (UINT32_C(0x1) << 29)
16297 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
16298 (UINT32_C(0x7) << 29)
16299 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
16300 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
16302 * Maximum BW allocated to CoS queue.
16303 * The HWRM will translate this value into byte counter and
16304 * time interval used for this COS inside the device.
16306 uint32_t queue_id1_max_bw;
16307 /* The bandwidth value. */
16308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
16309 UINT32_C(0xfffffff)
16310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
16312 /* The granularity of the value (bits or bytes). */
16313 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
16314 UINT32_C(0x10000000)
16315 /* Value is in bits. */
16316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
16317 (UINT32_C(0x0) << 28)
16318 /* Value is in bytes. */
16319 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
16320 (UINT32_C(0x1) << 28)
16321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
16322 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
16323 /* bw_value_unit is 3 b */
16324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
16325 UINT32_C(0xe0000000)
16326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
16328 /* Value is in Mb or MB (base 10). */
16329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
16330 (UINT32_C(0x0) << 29)
16331 /* Value is in Kb or KB (base 10). */
16332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
16333 (UINT32_C(0x2) << 29)
16334 /* Value is in bits or bytes. */
16335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
16336 (UINT32_C(0x4) << 29)
16337 /* Value is in Gb or GB (base 10). */
16338 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
16339 (UINT32_C(0x6) << 29)
16340 /* Value is in 1/100th of a percentage of total bandwidth. */
16341 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16342 (UINT32_C(0x1) << 29)
16344 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
16345 (UINT32_C(0x7) << 29)
16346 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
16347 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
16348 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16349 uint8_t queue_id1_tsa_assign;
16350 /* Strict Priority */
16351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
16353 /* Enhanced Transmission Selection */
16354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
16357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
16360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
16363 * Priority level for strict priority. Valid only when the
16364 * tsa_assign is 0 - Strict Priority (SP)
16365 * 0..7 - Valid values.
16366 * 8..255 - Reserved.
16368 uint8_t queue_id1_pri_lvl;
16370 * Weight used to allocate remaining BW for this COS after
16371 * servicing guaranteed bandwidths for all COS.
16373 uint8_t queue_id1_bw_weight;
16374 /* ID of CoS Queue 2. */
16377 * Minimum BW allocated to CoS Queue.
16378 * The HWRM will translate this value into byte counter and
16379 * time interval used for this COS inside the device.
16381 uint32_t queue_id2_min_bw;
16382 /* The bandwidth value. */
16383 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
16384 UINT32_C(0xfffffff)
16385 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
16387 /* The granularity of the value (bits or bytes). */
16388 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
16389 UINT32_C(0x10000000)
16390 /* Value is in bits. */
16391 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
16392 (UINT32_C(0x0) << 28)
16393 /* Value is in bytes. */
16394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
16395 (UINT32_C(0x1) << 28)
16396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
16397 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
16398 /* bw_value_unit is 3 b */
16399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
16400 UINT32_C(0xe0000000)
16401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
16403 /* Value is in Mb or MB (base 10). */
16404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
16405 (UINT32_C(0x0) << 29)
16406 /* Value is in Kb or KB (base 10). */
16407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
16408 (UINT32_C(0x2) << 29)
16409 /* Value is in bits or bytes. */
16410 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
16411 (UINT32_C(0x4) << 29)
16412 /* Value is in Gb or GB (base 10). */
16413 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
16414 (UINT32_C(0x6) << 29)
16415 /* Value is in 1/100th of a percentage of total bandwidth. */
16416 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16417 (UINT32_C(0x1) << 29)
16419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
16420 (UINT32_C(0x7) << 29)
16421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
16422 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
16424 * Maximum BW allocated to CoS queue.
16425 * The HWRM will translate this value into byte counter and
16426 * time interval used for this COS inside the device.
16428 uint32_t queue_id2_max_bw;
16429 /* The bandwidth value. */
16430 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
16431 UINT32_C(0xfffffff)
16432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
16434 /* The granularity of the value (bits or bytes). */
16435 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
16436 UINT32_C(0x10000000)
16437 /* Value is in bits. */
16438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
16439 (UINT32_C(0x0) << 28)
16440 /* Value is in bytes. */
16441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
16442 (UINT32_C(0x1) << 28)
16443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
16444 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
16445 /* bw_value_unit is 3 b */
16446 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
16447 UINT32_C(0xe0000000)
16448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
16450 /* Value is in Mb or MB (base 10). */
16451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
16452 (UINT32_C(0x0) << 29)
16453 /* Value is in Kb or KB (base 10). */
16454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
16455 (UINT32_C(0x2) << 29)
16456 /* Value is in bits or bytes. */
16457 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
16458 (UINT32_C(0x4) << 29)
16459 /* Value is in Gb or GB (base 10). */
16460 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
16461 (UINT32_C(0x6) << 29)
16462 /* Value is in 1/100th of a percentage of total bandwidth. */
16463 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16464 (UINT32_C(0x1) << 29)
16466 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
16467 (UINT32_C(0x7) << 29)
16468 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
16469 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
16470 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16471 uint8_t queue_id2_tsa_assign;
16472 /* Strict Priority */
16473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
16475 /* Enhanced Transmission Selection */
16476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
16479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
16482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
16485 * Priority level for strict priority. Valid only when the
16486 * tsa_assign is 0 - Strict Priority (SP)
16487 * 0..7 - Valid values.
16488 * 8..255 - Reserved.
16490 uint8_t queue_id2_pri_lvl;
16492 * Weight used to allocate remaining BW for this COS after
16493 * servicing guaranteed bandwidths for all COS.
16495 uint8_t queue_id2_bw_weight;
16496 /* ID of CoS Queue 3. */
16499 * Minimum BW allocated to CoS Queue.
16500 * The HWRM will translate this value into byte counter and
16501 * time interval used for this COS inside the device.
16503 uint32_t queue_id3_min_bw;
16504 /* The bandwidth value. */
16505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
16506 UINT32_C(0xfffffff)
16507 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
16509 /* The granularity of the value (bits or bytes). */
16510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
16511 UINT32_C(0x10000000)
16512 /* Value is in bits. */
16513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
16514 (UINT32_C(0x0) << 28)
16515 /* Value is in bytes. */
16516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
16517 (UINT32_C(0x1) << 28)
16518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
16519 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
16520 /* bw_value_unit is 3 b */
16521 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
16522 UINT32_C(0xe0000000)
16523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
16525 /* Value is in Mb or MB (base 10). */
16526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
16527 (UINT32_C(0x0) << 29)
16528 /* Value is in Kb or KB (base 10). */
16529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
16530 (UINT32_C(0x2) << 29)
16531 /* Value is in bits or bytes. */
16532 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
16533 (UINT32_C(0x4) << 29)
16534 /* Value is in Gb or GB (base 10). */
16535 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
16536 (UINT32_C(0x6) << 29)
16537 /* Value is in 1/100th of a percentage of total bandwidth. */
16538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16539 (UINT32_C(0x1) << 29)
16541 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
16542 (UINT32_C(0x7) << 29)
16543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
16544 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
16546 * Maximum BW allocated to CoS queue.
16547 * The HWRM will translate this value into byte counter and
16548 * time interval used for this COS inside the device.
16550 uint32_t queue_id3_max_bw;
16551 /* The bandwidth value. */
16552 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
16553 UINT32_C(0xfffffff)
16554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
16556 /* The granularity of the value (bits or bytes). */
16557 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
16558 UINT32_C(0x10000000)
16559 /* Value is in bits. */
16560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
16561 (UINT32_C(0x0) << 28)
16562 /* Value is in bytes. */
16563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
16564 (UINT32_C(0x1) << 28)
16565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
16566 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
16567 /* bw_value_unit is 3 b */
16568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
16569 UINT32_C(0xe0000000)
16570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
16572 /* Value is in Mb or MB (base 10). */
16573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
16574 (UINT32_C(0x0) << 29)
16575 /* Value is in Kb or KB (base 10). */
16576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
16577 (UINT32_C(0x2) << 29)
16578 /* Value is in bits or bytes. */
16579 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
16580 (UINT32_C(0x4) << 29)
16581 /* Value is in Gb or GB (base 10). */
16582 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
16583 (UINT32_C(0x6) << 29)
16584 /* Value is in 1/100th of a percentage of total bandwidth. */
16585 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16586 (UINT32_C(0x1) << 29)
16588 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
16589 (UINT32_C(0x7) << 29)
16590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
16591 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
16592 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16593 uint8_t queue_id3_tsa_assign;
16594 /* Strict Priority */
16595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
16597 /* Enhanced Transmission Selection */
16598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
16601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
16604 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
16607 * Priority level for strict priority. Valid only when the
16608 * tsa_assign is 0 - Strict Priority (SP)
16609 * 0..7 - Valid values.
16610 * 8..255 - Reserved.
16612 uint8_t queue_id3_pri_lvl;
16614 * Weight used to allocate remaining BW for this COS after
16615 * servicing guaranteed bandwidths for all COS.
16617 uint8_t queue_id3_bw_weight;
16618 /* ID of CoS Queue 4. */
16621 * Minimum BW allocated to CoS Queue.
16622 * The HWRM will translate this value into byte counter and
16623 * time interval used for this COS inside the device.
16625 uint32_t queue_id4_min_bw;
16626 /* The bandwidth value. */
16627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
16628 UINT32_C(0xfffffff)
16629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
16631 /* The granularity of the value (bits or bytes). */
16632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
16633 UINT32_C(0x10000000)
16634 /* Value is in bits. */
16635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
16636 (UINT32_C(0x0) << 28)
16637 /* Value is in bytes. */
16638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
16639 (UINT32_C(0x1) << 28)
16640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
16641 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
16642 /* bw_value_unit is 3 b */
16643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
16644 UINT32_C(0xe0000000)
16645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
16647 /* Value is in Mb or MB (base 10). */
16648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
16649 (UINT32_C(0x0) << 29)
16650 /* Value is in Kb or KB (base 10). */
16651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
16652 (UINT32_C(0x2) << 29)
16653 /* Value is in bits or bytes. */
16654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
16655 (UINT32_C(0x4) << 29)
16656 /* Value is in Gb or GB (base 10). */
16657 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
16658 (UINT32_C(0x6) << 29)
16659 /* Value is in 1/100th of a percentage of total bandwidth. */
16660 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16661 (UINT32_C(0x1) << 29)
16663 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
16664 (UINT32_C(0x7) << 29)
16665 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
16666 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
16668 * Maximum BW allocated to CoS queue.
16669 * The HWRM will translate this value into byte counter and
16670 * time interval used for this COS inside the device.
16672 uint32_t queue_id4_max_bw;
16673 /* The bandwidth value. */
16674 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
16675 UINT32_C(0xfffffff)
16676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
16678 /* The granularity of the value (bits or bytes). */
16679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
16680 UINT32_C(0x10000000)
16681 /* Value is in bits. */
16682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
16683 (UINT32_C(0x0) << 28)
16684 /* Value is in bytes. */
16685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
16686 (UINT32_C(0x1) << 28)
16687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
16688 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
16689 /* bw_value_unit is 3 b */
16690 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
16691 UINT32_C(0xe0000000)
16692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
16694 /* Value is in Mb or MB (base 10). */
16695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
16696 (UINT32_C(0x0) << 29)
16697 /* Value is in Kb or KB (base 10). */
16698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
16699 (UINT32_C(0x2) << 29)
16700 /* Value is in bits or bytes. */
16701 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
16702 (UINT32_C(0x4) << 29)
16703 /* Value is in Gb or GB (base 10). */
16704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
16705 (UINT32_C(0x6) << 29)
16706 /* Value is in 1/100th of a percentage of total bandwidth. */
16707 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16708 (UINT32_C(0x1) << 29)
16710 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
16711 (UINT32_C(0x7) << 29)
16712 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
16713 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
16714 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16715 uint8_t queue_id4_tsa_assign;
16716 /* Strict Priority */
16717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
16719 /* Enhanced Transmission Selection */
16720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
16723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
16726 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
16729 * Priority level for strict priority. Valid only when the
16730 * tsa_assign is 0 - Strict Priority (SP)
16731 * 0..7 - Valid values.
16732 * 8..255 - Reserved.
16734 uint8_t queue_id4_pri_lvl;
16736 * Weight used to allocate remaining BW for this COS after
16737 * servicing guaranteed bandwidths for all COS.
16739 uint8_t queue_id4_bw_weight;
16740 /* ID of CoS Queue 5. */
16743 * Minimum BW allocated to CoS Queue.
16744 * The HWRM will translate this value into byte counter and
16745 * time interval used for this COS inside the device.
16747 uint32_t queue_id5_min_bw;
16748 /* The bandwidth value. */
16749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
16750 UINT32_C(0xfffffff)
16751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
16753 /* The granularity of the value (bits or bytes). */
16754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
16755 UINT32_C(0x10000000)
16756 /* Value is in bits. */
16757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
16758 (UINT32_C(0x0) << 28)
16759 /* Value is in bytes. */
16760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
16761 (UINT32_C(0x1) << 28)
16762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
16763 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
16764 /* bw_value_unit is 3 b */
16765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
16766 UINT32_C(0xe0000000)
16767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
16769 /* Value is in Mb or MB (base 10). */
16770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
16771 (UINT32_C(0x0) << 29)
16772 /* Value is in Kb or KB (base 10). */
16773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
16774 (UINT32_C(0x2) << 29)
16775 /* Value is in bits or bytes. */
16776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
16777 (UINT32_C(0x4) << 29)
16778 /* Value is in Gb or GB (base 10). */
16779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
16780 (UINT32_C(0x6) << 29)
16781 /* Value is in 1/100th of a percentage of total bandwidth. */
16782 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16783 (UINT32_C(0x1) << 29)
16785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
16786 (UINT32_C(0x7) << 29)
16787 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
16788 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
16790 * Maximum BW allocated to CoS queue.
16791 * The HWRM will translate this value into byte counter and
16792 * time interval used for this COS inside the device.
16794 uint32_t queue_id5_max_bw;
16795 /* The bandwidth value. */
16796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
16797 UINT32_C(0xfffffff)
16798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
16800 /* The granularity of the value (bits or bytes). */
16801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
16802 UINT32_C(0x10000000)
16803 /* Value is in bits. */
16804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
16805 (UINT32_C(0x0) << 28)
16806 /* Value is in bytes. */
16807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
16808 (UINT32_C(0x1) << 28)
16809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
16810 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
16811 /* bw_value_unit is 3 b */
16812 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
16813 UINT32_C(0xe0000000)
16814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
16816 /* Value is in Mb or MB (base 10). */
16817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
16818 (UINT32_C(0x0) << 29)
16819 /* Value is in Kb or KB (base 10). */
16820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
16821 (UINT32_C(0x2) << 29)
16822 /* Value is in bits or bytes. */
16823 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
16824 (UINT32_C(0x4) << 29)
16825 /* Value is in Gb or GB (base 10). */
16826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
16827 (UINT32_C(0x6) << 29)
16828 /* Value is in 1/100th of a percentage of total bandwidth. */
16829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16830 (UINT32_C(0x1) << 29)
16832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
16833 (UINT32_C(0x7) << 29)
16834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
16835 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
16836 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16837 uint8_t queue_id5_tsa_assign;
16838 /* Strict Priority */
16839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
16841 /* Enhanced Transmission Selection */
16842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
16845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
16848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
16851 * Priority level for strict priority. Valid only when the
16852 * tsa_assign is 0 - Strict Priority (SP)
16853 * 0..7 - Valid values.
16854 * 8..255 - Reserved.
16856 uint8_t queue_id5_pri_lvl;
16858 * Weight used to allocate remaining BW for this COS after
16859 * servicing guaranteed bandwidths for all COS.
16861 uint8_t queue_id5_bw_weight;
16862 /* ID of CoS Queue 6. */
16865 * Minimum BW allocated to CoS Queue.
16866 * The HWRM will translate this value into byte counter and
16867 * time interval used for this COS inside the device.
16869 uint32_t queue_id6_min_bw;
16870 /* The bandwidth value. */
16871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
16872 UINT32_C(0xfffffff)
16873 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
16875 /* The granularity of the value (bits or bytes). */
16876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
16877 UINT32_C(0x10000000)
16878 /* Value is in bits. */
16879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
16880 (UINT32_C(0x0) << 28)
16881 /* Value is in bytes. */
16882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
16883 (UINT32_C(0x1) << 28)
16884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
16885 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
16886 /* bw_value_unit is 3 b */
16887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
16888 UINT32_C(0xe0000000)
16889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
16891 /* Value is in Mb or MB (base 10). */
16892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
16893 (UINT32_C(0x0) << 29)
16894 /* Value is in Kb or KB (base 10). */
16895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
16896 (UINT32_C(0x2) << 29)
16897 /* Value is in bits or bytes. */
16898 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
16899 (UINT32_C(0x4) << 29)
16900 /* Value is in Gb or GB (base 10). */
16901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
16902 (UINT32_C(0x6) << 29)
16903 /* Value is in 1/100th of a percentage of total bandwidth. */
16904 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16905 (UINT32_C(0x1) << 29)
16907 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
16908 (UINT32_C(0x7) << 29)
16909 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
16910 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
16912 * Maximum BW allocated to CoS queue.
16913 * The HWRM will translate this value into byte counter and
16914 * time interval used for this COS inside the device.
16916 uint32_t queue_id6_max_bw;
16917 /* The bandwidth value. */
16918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
16919 UINT32_C(0xfffffff)
16920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
16922 /* The granularity of the value (bits or bytes). */
16923 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
16924 UINT32_C(0x10000000)
16925 /* Value is in bits. */
16926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
16927 (UINT32_C(0x0) << 28)
16928 /* Value is in bytes. */
16929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
16930 (UINT32_C(0x1) << 28)
16931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
16932 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
16933 /* bw_value_unit is 3 b */
16934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
16935 UINT32_C(0xe0000000)
16936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
16938 /* Value is in Mb or MB (base 10). */
16939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
16940 (UINT32_C(0x0) << 29)
16941 /* Value is in Kb or KB (base 10). */
16942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
16943 (UINT32_C(0x2) << 29)
16944 /* Value is in bits or bytes. */
16945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
16946 (UINT32_C(0x4) << 29)
16947 /* Value is in Gb or GB (base 10). */
16948 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
16949 (UINT32_C(0x6) << 29)
16950 /* Value is in 1/100th of a percentage of total bandwidth. */
16951 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16952 (UINT32_C(0x1) << 29)
16954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
16955 (UINT32_C(0x7) << 29)
16956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
16957 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
16958 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16959 uint8_t queue_id6_tsa_assign;
16960 /* Strict Priority */
16961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
16963 /* Enhanced Transmission Selection */
16964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
16967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
16970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
16973 * Priority level for strict priority. Valid only when the
16974 * tsa_assign is 0 - Strict Priority (SP)
16975 * 0..7 - Valid values.
16976 * 8..255 - Reserved.
16978 uint8_t queue_id6_pri_lvl;
16980 * Weight used to allocate remaining BW for this COS after
16981 * servicing guaranteed bandwidths for all COS.
16983 uint8_t queue_id6_bw_weight;
16984 /* ID of CoS Queue 7. */
16987 * Minimum BW allocated to CoS Queue.
16988 * The HWRM will translate this value into byte counter and
16989 * time interval used for this COS inside the device.
16991 uint32_t queue_id7_min_bw;
16992 /* The bandwidth value. */
16993 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
16994 UINT32_C(0xfffffff)
16995 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
16997 /* The granularity of the value (bits or bytes). */
16998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
16999 UINT32_C(0x10000000)
17000 /* Value is in bits. */
17001 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
17002 (UINT32_C(0x0) << 28)
17003 /* Value is in bytes. */
17004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
17005 (UINT32_C(0x1) << 28)
17006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
17007 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
17008 /* bw_value_unit is 3 b */
17009 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
17010 UINT32_C(0xe0000000)
17011 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
17013 /* Value is in Mb or MB (base 10). */
17014 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
17015 (UINT32_C(0x0) << 29)
17016 /* Value is in Kb or KB (base 10). */
17017 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
17018 (UINT32_C(0x2) << 29)
17019 /* Value is in bits or bytes. */
17020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
17021 (UINT32_C(0x4) << 29)
17022 /* Value is in Gb or GB (base 10). */
17023 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
17024 (UINT32_C(0x6) << 29)
17025 /* Value is in 1/100th of a percentage of total bandwidth. */
17026 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
17027 (UINT32_C(0x1) << 29)
17029 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
17030 (UINT32_C(0x7) << 29)
17031 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
17032 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
17034 * Maximum BW allocated to CoS queue.
17035 * The HWRM will translate this value into byte counter and
17036 * time interval used for this COS inside the device.
17038 uint32_t queue_id7_max_bw;
17039 /* The bandwidth value. */
17040 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
17041 UINT32_C(0xfffffff)
17042 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
17044 /* The granularity of the value (bits or bytes). */
17045 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
17046 UINT32_C(0x10000000)
17047 /* Value is in bits. */
17048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
17049 (UINT32_C(0x0) << 28)
17050 /* Value is in bytes. */
17051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
17052 (UINT32_C(0x1) << 28)
17053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
17054 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
17055 /* bw_value_unit is 3 b */
17056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
17057 UINT32_C(0xe0000000)
17058 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
17060 /* Value is in Mb or MB (base 10). */
17061 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
17062 (UINT32_C(0x0) << 29)
17063 /* Value is in Kb or KB (base 10). */
17064 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
17065 (UINT32_C(0x2) << 29)
17066 /* Value is in bits or bytes. */
17067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
17068 (UINT32_C(0x4) << 29)
17069 /* Value is in Gb or GB (base 10). */
17070 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
17071 (UINT32_C(0x6) << 29)
17072 /* Value is in 1/100th of a percentage of total bandwidth. */
17073 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
17074 (UINT32_C(0x1) << 29)
17076 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
17077 (UINT32_C(0x7) << 29)
17078 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
17079 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
17080 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
17081 uint8_t queue_id7_tsa_assign;
17082 /* Strict Priority */
17083 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
17085 /* Enhanced Transmission Selection */
17086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
17089 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
17092 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
17095 * Priority level for strict priority. Valid only when the
17096 * tsa_assign is 0 - Strict Priority (SP)
17097 * 0..7 - Valid values.
17098 * 8..255 - Reserved.
17100 uint8_t queue_id7_pri_lvl;
17102 * Weight used to allocate remaining BW for this COS after
17103 * servicing guaranteed bandwidths for all COS.
17105 uint8_t queue_id7_bw_weight;
17106 uint8_t unused_1[5];
17107 } __attribute__((packed));
17109 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
17110 struct hwrm_queue_cos2bw_cfg_output {
17111 /* The specific error status for the command. */
17112 uint16_t error_code;
17113 /* The HWRM command request type. */
17115 /* The sequence ID from the original command. */
17117 /* The length of the response data in number of bytes. */
17119 uint8_t unused_0[7];
17121 * This field is used in Output records to indicate that the output
17122 * is completely written to RAM. This field should be read as '1'
17123 * to indicate that the output has been completely written.
17124 * When writing a command completion or response to an internal processor,
17125 * the order of writes has to be such that this field is written last.
17128 } __attribute__((packed));
17130 /*************************
17131 * hwrm_queue_dscp_qcaps *
17132 *************************/
17135 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
17136 struct hwrm_queue_dscp_qcaps_input {
17137 /* The HWRM command request type. */
17140 * The completion ring to send the completion event on. This should
17141 * be the NQ ID returned from the `nq_alloc` HWRM command.
17143 uint16_t cmpl_ring;
17145 * The sequence ID is used by the driver for tracking multiple
17146 * commands. This ID is treated as opaque data by the firmware and
17147 * the value is returned in the `hwrm_resp_hdr` upon completion.
17151 * The target ID of the command:
17152 * * 0x0-0xFFF8 - The function ID
17153 * * 0xFFF8-0xFFFE - Reserved for internal processors
17156 uint16_t target_id;
17158 * A physical address pointer pointing to a host buffer that the
17159 * command's response data will be written. This can be either a host
17160 * physical address (HPA) or a guest physical address (GPA) and must
17161 * point to a physically contiguous block of memory.
17163 uint64_t resp_addr;
17165 * Port ID of port for which the table is being configured.
17166 * The HWRM needs to check whether this function is allowed
17167 * to configure pri2cos mapping on this port.
17170 uint8_t unused_0[7];
17171 } __attribute__((packed));
17173 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
17174 struct hwrm_queue_dscp_qcaps_output {
17175 /* The specific error status for the command. */
17176 uint16_t error_code;
17177 /* The HWRM command request type. */
17179 /* The sequence ID from the original command. */
17181 /* The length of the response data in number of bytes. */
17183 /* The number of bits provided by the hardware for the DSCP value. */
17184 uint8_t num_dscp_bits;
17186 /* Max number of DSCP-MASK-PRI entries supported. */
17187 uint16_t max_entries;
17188 uint8_t unused_1[3];
17190 * This field is used in Output records to indicate that the output
17191 * is completely written to RAM. This field should be read as '1'
17192 * to indicate that the output has been completely written.
17193 * When writing a command completion or response to an internal processor,
17194 * the order of writes has to be such that this field is written last.
17197 } __attribute__((packed));
17199 /****************************
17200 * hwrm_queue_dscp2pri_qcfg *
17201 ****************************/
17204 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
17205 struct hwrm_queue_dscp2pri_qcfg_input {
17206 /* The HWRM command request type. */
17209 * The completion ring to send the completion event on. This should
17210 * be the NQ ID returned from the `nq_alloc` HWRM command.
17212 uint16_t cmpl_ring;
17214 * The sequence ID is used by the driver for tracking multiple
17215 * commands. This ID is treated as opaque data by the firmware and
17216 * the value is returned in the `hwrm_resp_hdr` upon completion.
17220 * The target ID of the command:
17221 * * 0x0-0xFFF8 - The function ID
17222 * * 0xFFF8-0xFFFE - Reserved for internal processors
17225 uint16_t target_id;
17227 * A physical address pointer pointing to a host buffer that the
17228 * command's response data will be written. This can be either a host
17229 * physical address (HPA) or a guest physical address (GPA) and must
17230 * point to a physically contiguous block of memory.
17232 uint64_t resp_addr;
17234 * This is the host address where the 24-bits DSCP-MASK-PRI
17235 * tuple(s) will be copied to.
17237 uint64_t dest_data_addr;
17239 * Port ID of port for which the table is being configured.
17240 * The HWRM needs to check whether this function is allowed
17241 * to configure pri2cos mapping on this port.
17245 /* Size of the buffer pointed to by dest_data_addr. */
17246 uint16_t dest_data_buffer_size;
17247 uint8_t unused_1[4];
17248 } __attribute__((packed));
17250 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
17251 struct hwrm_queue_dscp2pri_qcfg_output {
17252 /* The specific error status for the command. */
17253 uint16_t error_code;
17254 /* The HWRM command request type. */
17256 /* The sequence ID from the original command. */
17258 /* The length of the response data in number of bytes. */
17261 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
17262 * by the dest_data_addr.
17264 uint16_t entry_cnt;
17266 * This is the default PRI which un-initialized DSCP values are
17269 uint8_t default_pri;
17270 uint8_t unused_0[4];
17272 * This field is used in Output records to indicate that the output
17273 * is completely written to RAM. This field should be read as '1'
17274 * to indicate that the output has been completely written.
17275 * When writing a command completion or response to an internal processor,
17276 * the order of writes has to be such that this field is written last.
17279 } __attribute__((packed));
17281 /***************************
17282 * hwrm_queue_dscp2pri_cfg *
17283 ***************************/
17286 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
17287 struct hwrm_queue_dscp2pri_cfg_input {
17288 /* The HWRM command request type. */
17291 * The completion ring to send the completion event on. This should
17292 * be the NQ ID returned from the `nq_alloc` HWRM command.
17294 uint16_t cmpl_ring;
17296 * The sequence ID is used by the driver for tracking multiple
17297 * commands. This ID is treated as opaque data by the firmware and
17298 * the value is returned in the `hwrm_resp_hdr` upon completion.
17302 * The target ID of the command:
17303 * * 0x0-0xFFF8 - The function ID
17304 * * 0xFFF8-0xFFFE - Reserved for internal processors
17307 uint16_t target_id;
17309 * A physical address pointer pointing to a host buffer that the
17310 * command's response data will be written. This can be either a host
17311 * physical address (HPA) or a guest physical address (GPA) and must
17312 * point to a physically contiguous block of memory.
17314 uint64_t resp_addr;
17316 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
17317 * will be copied from.
17319 uint64_t src_data_addr;
17321 /* use_hw_default_pri is 1 b */
17322 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
17326 * This bit must be '1' for the default_pri field to be
17329 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
17332 * Port ID of port for which the table is being configured.
17333 * The HWRM needs to check whether this function is allowed
17334 * to configure pri2cos mapping on this port.
17338 * This is the default PRI which un-initialized DSCP values will be
17341 uint8_t default_pri;
17343 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
17344 * to by src_data_addr.
17346 uint16_t entry_cnt;
17347 uint8_t unused_0[4];
17348 } __attribute__((packed));
17350 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
17351 struct hwrm_queue_dscp2pri_cfg_output {
17352 /* The specific error status for the command. */
17353 uint16_t error_code;
17354 /* The HWRM command request type. */
17356 /* The sequence ID from the original command. */
17358 /* The length of the response data in number of bytes. */
17360 uint8_t unused_0[7];
17362 * This field is used in Output records to indicate that the output
17363 * is completely written to RAM. This field should be read as '1'
17364 * to indicate that the output has been completely written.
17365 * When writing a command completion or response to an internal processor,
17366 * the order of writes has to be such that this field is written last.
17369 } __attribute__((packed));
17371 /*******************
17372 * hwrm_vnic_alloc *
17373 *******************/
17376 /* hwrm_vnic_alloc_input (size:192b/24B) */
17377 struct hwrm_vnic_alloc_input {
17378 /* The HWRM command request type. */
17381 * The completion ring to send the completion event on. This should
17382 * be the NQ ID returned from the `nq_alloc` HWRM command.
17384 uint16_t cmpl_ring;
17386 * The sequence ID is used by the driver for tracking multiple
17387 * commands. This ID is treated as opaque data by the firmware and
17388 * the value is returned in the `hwrm_resp_hdr` upon completion.
17392 * The target ID of the command:
17393 * * 0x0-0xFFF8 - The function ID
17394 * * 0xFFF8-0xFFFE - Reserved for internal processors
17397 uint16_t target_id;
17399 * A physical address pointer pointing to a host buffer that the
17400 * command's response data will be written. This can be either a host
17401 * physical address (HPA) or a guest physical address (GPA) and must
17402 * point to a physically contiguous block of memory.
17404 uint64_t resp_addr;
17407 * When this bit is '1', this VNIC is requested to
17408 * be the default VNIC for this function.
17410 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
17411 uint8_t unused_0[4];
17412 } __attribute__((packed));
17414 /* hwrm_vnic_alloc_output (size:128b/16B) */
17415 struct hwrm_vnic_alloc_output {
17416 /* The specific error status for the command. */
17417 uint16_t error_code;
17418 /* The HWRM command request type. */
17420 /* The sequence ID from the original command. */
17422 /* The length of the response data in number of bytes. */
17424 /* Logical vnic ID */
17426 uint8_t unused_0[3];
17428 * This field is used in Output records to indicate that the output
17429 * is completely written to RAM. This field should be read as '1'
17430 * to indicate that the output has been completely written.
17431 * When writing a command completion or response to an internal processor,
17432 * the order of writes has to be such that this field is written last.
17435 } __attribute__((packed));
17437 /******************
17439 ******************/
17442 /* hwrm_vnic_free_input (size:192b/24B) */
17443 struct hwrm_vnic_free_input {
17444 /* The HWRM command request type. */
17447 * The completion ring to send the completion event on. This should
17448 * be the NQ ID returned from the `nq_alloc` HWRM command.
17450 uint16_t cmpl_ring;
17452 * The sequence ID is used by the driver for tracking multiple
17453 * commands. This ID is treated as opaque data by the firmware and
17454 * the value is returned in the `hwrm_resp_hdr` upon completion.
17458 * The target ID of the command:
17459 * * 0x0-0xFFF8 - The function ID
17460 * * 0xFFF8-0xFFFE - Reserved for internal processors
17463 uint16_t target_id;
17465 * A physical address pointer pointing to a host buffer that the
17466 * command's response data will be written. This can be either a host
17467 * physical address (HPA) or a guest physical address (GPA) and must
17468 * point to a physically contiguous block of memory.
17470 uint64_t resp_addr;
17471 /* Logical vnic ID */
17473 uint8_t unused_0[4];
17474 } __attribute__((packed));
17476 /* hwrm_vnic_free_output (size:128b/16B) */
17477 struct hwrm_vnic_free_output {
17478 /* The specific error status for the command. */
17479 uint16_t error_code;
17480 /* The HWRM command request type. */
17482 /* The sequence ID from the original command. */
17484 /* The length of the response data in number of bytes. */
17486 uint8_t unused_0[7];
17488 * This field is used in Output records to indicate that the output
17489 * is completely written to RAM. This field should be read as '1'
17490 * to indicate that the output has been completely written.
17491 * When writing a command completion or response to an internal processor,
17492 * the order of writes has to be such that this field is written last.
17495 } __attribute__((packed));
17502 /* hwrm_vnic_cfg_input (size:320b/40B) */
17503 struct hwrm_vnic_cfg_input {
17504 /* The HWRM command request type. */
17507 * The completion ring to send the completion event on. This should
17508 * be the NQ ID returned from the `nq_alloc` HWRM command.
17510 uint16_t cmpl_ring;
17512 * The sequence ID is used by the driver for tracking multiple
17513 * commands. This ID is treated as opaque data by the firmware and
17514 * the value is returned in the `hwrm_resp_hdr` upon completion.
17518 * The target ID of the command:
17519 * * 0x0-0xFFF8 - The function ID
17520 * * 0xFFF8-0xFFFE - Reserved for internal processors
17523 uint16_t target_id;
17525 * A physical address pointer pointing to a host buffer that the
17526 * command's response data will be written. This can be either a host
17527 * physical address (HPA) or a guest physical address (GPA) and must
17528 * point to a physically contiguous block of memory.
17530 uint64_t resp_addr;
17533 * When this bit is '1', the VNIC is requested to
17534 * be the default VNIC for the function.
17536 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
17539 * When this bit is '1', the VNIC is being configured to
17540 * strip VLAN in the RX path.
17541 * If set to '0', then VLAN stripping is disabled on
17544 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
17547 * When this bit is '1', the VNIC is being configured to
17548 * buffer receive packets in the hardware until the host
17549 * posts new receive buffers.
17550 * If set to '0', then bd_stall is being configured to be
17551 * disabled on this VNIC.
17553 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
17556 * When this bit is '1', the VNIC is being configured to
17557 * receive both RoCE and non-RoCE traffic.
17558 * If set to '0', then this VNIC is not configured to be
17559 * operating in dual VNIC mode.
17561 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
17564 * When this flag is set to '1', the VNIC is requested to
17565 * be configured to receive only RoCE traffic.
17566 * If this flag is set to '0', then this flag shall be
17567 * ignored by the HWRM.
17568 * If roce_dual_vnic_mode flag is set to '1'
17569 * or roce_mirroring_capable_vnic_mode flag to 1,
17570 * then the HWRM client shall not set this flag to '1'.
17572 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
17575 * When a VNIC uses one destination ring group for certain
17576 * application (e.g. Receive Flow Steering) where
17577 * exact match is used to direct packets to a VNIC with one
17578 * destination ring group only, there is no need to configure
17579 * RSS indirection table for that VNIC as only one destination
17580 * ring group is used.
17582 * This flag is used to enable a mode where
17583 * RSS is enabled in the VNIC using a RSS context
17584 * for computing RSS hash but the RSS indirection table is
17585 * not configured using hwrm_vnic_rss_cfg.
17587 * If this mode is enabled, then the driver should not program
17588 * RSS indirection table for the RSS context that is used for
17589 * computing RSS hash only.
17591 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
17594 * When this bit is '1', the VNIC is being configured to
17595 * receive both RoCE and non-RoCE traffic, but forward only the
17596 * RoCE traffic further. Also, RoCE traffic can be mirrored to
17599 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
17603 * This bit must be '1' for the dflt_ring_grp field to be
17606 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
17609 * This bit must be '1' for the rss_rule field to be
17612 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
17615 * This bit must be '1' for the cos_rule field to be
17618 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
17621 * This bit must be '1' for the lb_rule field to be
17624 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
17627 * This bit must be '1' for the mru field to be
17630 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
17633 * This bit must be '1' for the default_rx_ring_id field to be
17636 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
17639 * This bit must be '1' for the default_cmpl_ring_id field to be
17642 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
17644 /* Logical vnic ID */
17647 * Default Completion ring for the VNIC. This ring will
17648 * be chosen if packet does not match any RSS rules and if
17649 * there is no COS rule.
17651 uint16_t dflt_ring_grp;
17653 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
17654 * there is no RSS rule.
17658 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
17659 * there is no COS rule.
17663 * RSS ID for load balancing rule/table structure.
17664 * 0xFF... (All Fs) if there is no LB rule.
17668 * The maximum receive unit of the vnic.
17669 * Each vnic is associated with a function.
17670 * The vnic mru value overwrites the mru setting of the
17671 * associated function.
17672 * The HWRM shall make sure that vnic mru does not exceed
17673 * the mru of the port the function is associated with.
17677 * Default Rx ring for the VNIC. This ring will
17678 * be chosen if packet does not match any RSS rules.
17679 * The aggregation ring associated with the Rx ring is
17680 * implied based on the Rx ring specified when the
17681 * aggregation ring was allocated.
17683 uint16_t default_rx_ring_id;
17685 * Default completion ring for the VNIC. This ring will
17686 * be chosen if packet does not match any RSS rules.
17688 uint16_t default_cmpl_ring_id;
17689 } __attribute__((packed));
17691 /* hwrm_vnic_cfg_output (size:128b/16B) */
17692 struct hwrm_vnic_cfg_output {
17693 /* The specific error status for the command. */
17694 uint16_t error_code;
17695 /* The HWRM command request type. */
17697 /* The sequence ID from the original command. */
17699 /* The length of the response data in number of bytes. */
17701 uint8_t unused_0[7];
17703 * This field is used in Output records to indicate that the output
17704 * is completely written to RAM. This field should be read as '1'
17705 * to indicate that the output has been completely written.
17706 * When writing a command completion or response to an internal processor,
17707 * the order of writes has to be such that this field is written last.
17710 } __attribute__((packed));
17712 /******************
17714 ******************/
17717 /* hwrm_vnic_qcfg_input (size:256b/32B) */
17718 struct hwrm_vnic_qcfg_input {
17719 /* The HWRM command request type. */
17722 * The completion ring to send the completion event on. This should
17723 * be the NQ ID returned from the `nq_alloc` HWRM command.
17725 uint16_t cmpl_ring;
17727 * The sequence ID is used by the driver for tracking multiple
17728 * commands. This ID is treated as opaque data by the firmware and
17729 * the value is returned in the `hwrm_resp_hdr` upon completion.
17733 * The target ID of the command:
17734 * * 0x0-0xFFF8 - The function ID
17735 * * 0xFFF8-0xFFFE - Reserved for internal processors
17738 uint16_t target_id;
17740 * A physical address pointer pointing to a host buffer that the
17741 * command's response data will be written. This can be either a host
17742 * physical address (HPA) or a guest physical address (GPA) and must
17743 * point to a physically contiguous block of memory.
17745 uint64_t resp_addr;
17748 * This bit must be '1' for the vf_id_valid field to be
17751 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
17752 /* Logical vnic ID */
17754 /* ID of Virtual Function whose VNIC resource is being queried. */
17756 uint8_t unused_0[6];
17757 } __attribute__((packed));
17759 /* hwrm_vnic_qcfg_output (size:256b/32B) */
17760 struct hwrm_vnic_qcfg_output {
17761 /* The specific error status for the command. */
17762 uint16_t error_code;
17763 /* The HWRM command request type. */
17765 /* The sequence ID from the original command. */
17767 /* The length of the response data in number of bytes. */
17769 /* Default Completion ring for the VNIC. */
17770 uint16_t dflt_ring_grp;
17772 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
17773 * there is no RSS rule.
17777 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
17778 * there is no COS rule.
17782 * RSS ID for load balancing rule/table structure.
17783 * 0xFF... (All Fs) if there is no LB rule.
17786 /* The maximum receive unit of the vnic. */
17788 uint8_t unused_0[2];
17791 * When this bit is '1', the VNIC is the default VNIC for
17794 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
17797 * When this bit is '1', the VNIC is configured to
17798 * strip VLAN in the RX path.
17799 * If set to '0', then VLAN stripping is disabled on
17802 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
17805 * When this bit is '1', the VNIC is configured to
17806 * buffer receive packets in the hardware until the host
17807 * posts new receive buffers.
17808 * If set to '0', then bd_stall is disabled on
17811 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
17814 * When this bit is '1', the VNIC is configured to
17815 * receive both RoCE and non-RoCE traffic.
17816 * If set to '0', then this VNIC is not configured to
17817 * operate in dual VNIC mode.
17819 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
17822 * When this flag is set to '1', the VNIC is configured to
17823 * receive only RoCE traffic.
17824 * When this flag is set to '0', the VNIC is not configured
17825 * to receive only RoCE traffic.
17826 * If roce_dual_vnic_mode flag and this flag both are set
17827 * to '1', then it is an invalid configuration of the
17828 * VNIC. The HWRM should not allow that type of
17829 * mis-configuration by HWRM clients.
17831 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
17834 * When a VNIC uses one destination ring group for certain
17835 * application (e.g. Receive Flow Steering) where
17836 * exact match is used to direct packets to a VNIC with one
17837 * destination ring group only, there is no need to configure
17838 * RSS indirection table for that VNIC as only one destination
17839 * ring group is used.
17841 * When this bit is set to '1', then the VNIC is enabled in a
17842 * mode where RSS is enabled in the VNIC using a RSS context
17843 * for computing RSS hash but the RSS indirection table is
17846 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
17849 * When this bit is '1', the VNIC is configured to
17850 * receive both RoCE and non-RoCE traffic, but forward only
17851 * RoCE traffic further. Also RoCE traffic can be mirrored to
17854 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
17856 uint8_t unused_1[7];
17858 * This field is used in Output records to indicate that the output
17859 * is completely written to RAM. This field should be read as '1'
17860 * to indicate that the output has been completely written.
17861 * When writing a command completion or response to an internal processor,
17862 * the order of writes has to be such that this field is written last.
17865 } __attribute__((packed));
17867 /*******************
17868 * hwrm_vnic_qcaps *
17869 *******************/
17872 /* hwrm_vnic_qcaps_input (size:192b/24B) */
17873 struct hwrm_vnic_qcaps_input {
17874 /* The HWRM command request type. */
17877 * The completion ring to send the completion event on. This should
17878 * be the NQ ID returned from the `nq_alloc` HWRM command.
17880 uint16_t cmpl_ring;
17882 * The sequence ID is used by the driver for tracking multiple
17883 * commands. This ID is treated as opaque data by the firmware and
17884 * the value is returned in the `hwrm_resp_hdr` upon completion.
17888 * The target ID of the command:
17889 * * 0x0-0xFFF8 - The function ID
17890 * * 0xFFF8-0xFFFE - Reserved for internal processors
17893 uint16_t target_id;
17895 * A physical address pointer pointing to a host buffer that the
17896 * command's response data will be written. This can be either a host
17897 * physical address (HPA) or a guest physical address (GPA) and must
17898 * point to a physically contiguous block of memory.
17900 uint64_t resp_addr;
17902 uint8_t unused_0[4];
17903 } __attribute__((packed));
17905 /* hwrm_vnic_qcaps_output (size:192b/24B) */
17906 struct hwrm_vnic_qcaps_output {
17907 /* The specific error status for the command. */
17908 uint16_t error_code;
17909 /* The HWRM command request type. */
17911 /* The sequence ID from the original command. */
17913 /* The length of the response data in number of bytes. */
17915 /* The maximum receive unit that is settable on a vnic. */
17917 uint8_t unused_0[2];
17920 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
17923 * When this bit is '1', the capability of stripping VLAN in
17924 * the RX path is supported on VNIC(s).
17925 * If set to '0', then VLAN stripping capability is
17926 * not supported on VNIC(s).
17928 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
17931 * When this bit is '1', the capability to buffer receive
17932 * packets in the hardware until the host posts new receive buffers
17933 * is supported on VNIC(s).
17934 * If set to '0', then bd_stall capability is not supported
17937 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
17940 * When this bit is '1', the capability to
17941 * receive both RoCE and non-RoCE traffic on VNIC(s) is
17943 * If set to '0', then the capability to receive
17944 * both RoCE and non-RoCE traffic on VNIC(s) is
17947 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
17950 * When this bit is set to '1', the capability to configure
17951 * a VNIC to receive only RoCE traffic is supported.
17952 * When this flag is set to '0', the VNIC capability to
17953 * configure to receive only RoCE traffic is not supported.
17955 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
17958 * When this bit is set to '1', then the capability to enable
17959 * a VNIC in a mode where RSS context without configuring
17960 * RSS indirection table is supported (for RSS hash computation).
17961 * When this bit is set to '0', then a VNIC can not be configured
17962 * with a mode to enable RSS context without configuring RSS
17963 * indirection table.
17965 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
17968 * When this bit is '1', the capability to
17969 * mirror the the RoCE traffic is supported.
17970 * If set to '0', then the capability to mirror the
17971 * RoCE traffic is not supported.
17973 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
17976 * When this bit is '1', the outermost RSS hashing capability
17977 * is supported. If set to '0', then the outermost RSS hashing
17978 * capability is not supported.
17980 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
17982 uint8_t unused_1[7];
17984 * This field is used in Output records to indicate that the output
17985 * is completely written to RAM. This field should be read as '1'
17986 * to indicate that the output has been completely written.
17987 * When writing a command completion or response to an internal processor,
17988 * the order of writes has to be such that this field is written last.
17991 } __attribute__((packed));
17993 /*********************
17994 * hwrm_vnic_tpa_cfg *
17995 *********************/
17998 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
17999 struct hwrm_vnic_tpa_cfg_input {
18000 /* The HWRM command request type. */
18003 * The completion ring to send the completion event on. This should
18004 * be the NQ ID returned from the `nq_alloc` HWRM command.
18006 uint16_t cmpl_ring;
18008 * The sequence ID is used by the driver for tracking multiple
18009 * commands. This ID is treated as opaque data by the firmware and
18010 * the value is returned in the `hwrm_resp_hdr` upon completion.
18014 * The target ID of the command:
18015 * * 0x0-0xFFF8 - The function ID
18016 * * 0xFFF8-0xFFFE - Reserved for internal processors
18019 uint16_t target_id;
18021 * A physical address pointer pointing to a host buffer that the
18022 * command's response data will be written. This can be either a host
18023 * physical address (HPA) or a guest physical address (GPA) and must
18024 * point to a physically contiguous block of memory.
18026 uint64_t resp_addr;
18029 * When this bit is '1', the VNIC shall be configured to
18030 * perform transparent packet aggregation (TPA) of
18031 * non-tunneled TCP packets.
18033 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
18036 * When this bit is '1', the VNIC shall be configured to
18037 * perform transparent packet aggregation (TPA) of
18038 * tunneled TCP packets.
18040 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
18043 * When this bit is '1', the VNIC shall be configured to
18044 * perform transparent packet aggregation (TPA) according
18045 * to Windows Receive Segment Coalescing (RSC) rules.
18047 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
18050 * When this bit is '1', the VNIC shall be configured to
18051 * perform transparent packet aggregation (TPA) according
18052 * to Linux Generic Receive Offload (GRO) rules.
18054 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
18057 * When this bit is '1', the VNIC shall be configured to
18058 * perform transparent packet aggregation (TPA) for TCP
18059 * packets with IP ECN set to non-zero.
18061 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
18064 * When this bit is '1', the VNIC shall be configured to
18065 * perform transparent packet aggregation (TPA) for
18066 * GRE tunneled TCP packets only if all packets have the
18067 * same GRE sequence.
18069 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
18072 * When this bit is '1' and the GRO mode is enabled,
18073 * the VNIC shall be configured to
18074 * perform transparent packet aggregation (TPA) for
18075 * TCP/IPv4 packets with consecutively increasing IPIDs.
18076 * In other words, the last packet that is being
18077 * aggregated to an already existing aggregation context
18078 * shall have IPID 1 more than the IPID of the last packet
18079 * that was aggregated in that aggregation context.
18081 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
18084 * When this bit is '1' and the GRO mode is enabled,
18085 * the VNIC shall be configured to
18086 * perform transparent packet aggregation (TPA) for
18087 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
18090 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
18094 * This bit must be '1' for the max_agg_segs field to be
18097 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
18099 * This bit must be '1' for the max_aggs field to be
18102 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
18104 * This bit must be '1' for the max_agg_timer field to be
18107 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
18109 * This bit must be '1' for the min_agg_len field to be
18112 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
18113 /* Logical vnic ID */
18116 * This is the maximum number of TCP segments that can
18117 * be aggregated (unit is Log2). Max value is 31.
18119 uint16_t max_agg_segs;
18121 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
18123 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
18125 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
18127 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
18128 /* Any segment size larger than this is not valid */
18129 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
18130 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
18131 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
18133 * This is the maximum number of aggregations this VNIC is
18134 * allowed (unit is Log2). Max value is 7
18137 /* 1 aggregation */
18138 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
18139 /* 2 aggregations */
18140 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
18141 /* 4 aggregations */
18142 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
18143 /* 8 aggregations */
18144 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
18145 /* 16 aggregations */
18146 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
18147 /* Any aggregation size larger than this is not valid */
18148 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
18149 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
18150 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
18151 uint8_t unused_0[2];
18153 * This is the maximum amount of time allowed for
18154 * an aggregation context to complete after it was initiated.
18156 uint32_t max_agg_timer;
18158 * This is the minimum amount of payload length required to
18159 * start an aggregation context.
18161 uint32_t min_agg_len;
18162 } __attribute__((packed));
18164 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
18165 struct hwrm_vnic_tpa_cfg_output {
18166 /* The specific error status for the command. */
18167 uint16_t error_code;
18168 /* The HWRM command request type. */
18170 /* The sequence ID from the original command. */
18172 /* The length of the response data in number of bytes. */
18174 uint8_t unused_0[7];
18176 * This field is used in Output records to indicate that the output
18177 * is completely written to RAM. This field should be read as '1'
18178 * to indicate that the output has been completely written.
18179 * When writing a command completion or response to an internal processor,
18180 * the order of writes has to be such that this field is written last.
18183 } __attribute__((packed));
18185 /**********************
18186 * hwrm_vnic_tpa_qcfg *
18187 **********************/
18190 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
18191 struct hwrm_vnic_tpa_qcfg_input {
18192 /* The HWRM command request type. */
18195 * The completion ring to send the completion event on. This should
18196 * be the NQ ID returned from the `nq_alloc` HWRM command.
18198 uint16_t cmpl_ring;
18200 * The sequence ID is used by the driver for tracking multiple
18201 * commands. This ID is treated as opaque data by the firmware and
18202 * the value is returned in the `hwrm_resp_hdr` upon completion.
18206 * The target ID of the command:
18207 * * 0x0-0xFFF8 - The function ID
18208 * * 0xFFF8-0xFFFE - Reserved for internal processors
18211 uint16_t target_id;
18213 * A physical address pointer pointing to a host buffer that the
18214 * command's response data will be written. This can be either a host
18215 * physical address (HPA) or a guest physical address (GPA) and must
18216 * point to a physically contiguous block of memory.
18218 uint64_t resp_addr;
18219 /* Logical vnic ID */
18221 uint8_t unused_0[6];
18222 } __attribute__((packed));
18224 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
18225 struct hwrm_vnic_tpa_qcfg_output {
18226 /* The specific error status for the command. */
18227 uint16_t error_code;
18228 /* The HWRM command request type. */
18230 /* The sequence ID from the original command. */
18232 /* The length of the response data in number of bytes. */
18236 * When this bit is '1', the VNIC is configured to
18237 * perform transparent packet aggregation (TPA) of
18238 * non-tunneled TCP packets.
18240 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \
18243 * When this bit is '1', the VNIC is configured to
18244 * perform transparent packet aggregation (TPA) of
18245 * tunneled TCP packets.
18247 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \
18250 * When this bit is '1', the VNIC is configured to
18251 * perform transparent packet aggregation (TPA) according
18252 * to Windows Receive Segment Coalescing (RSC) rules.
18254 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \
18257 * When this bit is '1', the VNIC is configured to
18258 * perform transparent packet aggregation (TPA) according
18259 * to Linux Generic Receive Offload (GRO) rules.
18261 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \
18264 * When this bit is '1', the VNIC is configured to
18265 * perform transparent packet aggregation (TPA) for TCP
18266 * packets with IP ECN set to non-zero.
18268 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \
18271 * When this bit is '1', the VNIC is configured to
18272 * perform transparent packet aggregation (TPA) for
18273 * GRE tunneled TCP packets only if all packets have the
18274 * same GRE sequence.
18276 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
18279 * When this bit is '1' and the GRO mode is enabled,
18280 * the VNIC is configured to
18281 * perform transparent packet aggregation (TPA) for
18282 * TCP/IPv4 packets with consecutively increasing IPIDs.
18283 * In other words, the last packet that is being
18284 * aggregated to an already existing aggregation context
18285 * shall have IPID 1 more than the IPID of the last packet
18286 * that was aggregated in that aggregation context.
18288 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \
18291 * When this bit is '1' and the GRO mode is enabled,
18292 * the VNIC is configured to
18293 * perform transparent packet aggregation (TPA) for
18294 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
18297 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \
18300 * This is the maximum number of TCP segments that can
18301 * be aggregated (unit is Log2). Max value is 31.
18303 uint16_t max_agg_segs;
18305 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
18307 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
18309 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
18311 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
18312 /* Any segment size larger than this is not valid */
18313 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
18314 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \
18315 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX
18317 * This is the maximum number of aggregations this VNIC is
18318 * allowed (unit is Log2). Max value is 7
18321 /* 1 aggregation */
18322 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
18323 /* 2 aggregations */
18324 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
18325 /* 4 aggregations */
18326 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
18327 /* 8 aggregations */
18328 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
18329 /* 16 aggregations */
18330 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
18331 /* Any aggregation size larger than this is not valid */
18332 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
18333 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \
18334 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX
18336 * This is the maximum amount of time allowed for
18337 * an aggregation context to complete after it was initiated.
18339 uint32_t max_agg_timer;
18341 * This is the minimum amount of payload length required to
18342 * start an aggregation context.
18344 uint32_t min_agg_len;
18345 uint8_t unused_0[7];
18347 * This field is used in Output records to indicate that the output
18348 * is completely written to RAM. This field should be read as '1'
18349 * to indicate that the output has been completely written.
18350 * When writing a command completion or response to an internal processor,
18351 * the order of writes has to be such that this field is written last.
18354 } __attribute__((packed));
18356 /*********************
18357 * hwrm_vnic_rss_cfg *
18358 *********************/
18361 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
18362 struct hwrm_vnic_rss_cfg_input {
18363 /* The HWRM command request type. */
18366 * The completion ring to send the completion event on. This should
18367 * be the NQ ID returned from the `nq_alloc` HWRM command.
18369 uint16_t cmpl_ring;
18371 * The sequence ID is used by the driver for tracking multiple
18372 * commands. This ID is treated as opaque data by the firmware and
18373 * the value is returned in the `hwrm_resp_hdr` upon completion.
18377 * The target ID of the command:
18378 * * 0x0-0xFFF8 - The function ID
18379 * * 0xFFF8-0xFFFE - Reserved for internal processors
18382 uint16_t target_id;
18384 * A physical address pointer pointing to a host buffer that the
18385 * command's response data will be written. This can be either a host
18386 * physical address (HPA) or a guest physical address (GPA) and must
18387 * point to a physically contiguous block of memory.
18389 uint64_t resp_addr;
18390 uint32_t hash_type;
18392 * When this bit is '1', the RSS hash shall be computed
18393 * over source and destination IPv4 addresses of IPv4
18396 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18398 * When this bit is '1', the RSS hash shall be computed
18399 * over source/destination IPv4 addresses and
18400 * source/destination ports of TCP/IPv4 packets.
18402 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18404 * When this bit is '1', the RSS hash shall be computed
18405 * over source/destination IPv4 addresses and
18406 * source/destination ports of UDP/IPv4 packets.
18408 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18410 * When this bit is '1', the RSS hash shall be computed
18411 * over source and destination IPv4 addresses of IPv6
18414 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18416 * When this bit is '1', the RSS hash shall be computed
18417 * over source/destination IPv6 addresses and
18418 * source/destination ports of TCP/IPv6 packets.
18420 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18422 * When this bit is '1', the RSS hash shall be computed
18423 * over source/destination IPv6 addresses and
18424 * source/destination ports of UDP/IPv6 packets.
18426 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18427 /* VNIC ID of VNIC associated with RSS table being configured. */
18430 * Specifies which VNIC ring table pair to configure.
18431 * Valid values range from 0 to 7.
18433 uint8_t ring_table_pair_index;
18434 /* Flags to specify different RSS hash modes. */
18435 uint8_t hash_mode_flags;
18437 * When this bit is '1', it indicates using current RSS
18438 * hash mode setting configured in the device.
18440 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
18443 * When this bit is '1', it indicates requesting support of
18444 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18445 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18446 * packets, the RSS hash is computed over the normal
18447 * src/dest l3 and src/dest l4 headers.
18449 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18452 * When this bit is '1', it indicates requesting support of
18453 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18454 * tunnel packets. For none-tunnel packets, the RSS hash is
18455 * computed over the normal src/dest l3 headers.
18457 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18460 * When this bit is '1', it indicates requesting support of
18461 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18462 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18463 * packets, the RSS hash is computed over the normal
18464 * src/dest l3 and src/dest l4 headers.
18466 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18469 * When this bit is '1', it indicates requesting support of
18470 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18471 * tunnel packets. For none-tunnel packets, the RSS hash is
18472 * computed over the normal src/dest l3 headers.
18474 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18476 /* This is the address for rss ring group table */
18477 uint64_t ring_grp_tbl_addr;
18478 /* This is the address for rss hash key table */
18479 uint64_t hash_key_tbl_addr;
18480 /* Index to the rss indirection table. */
18481 uint16_t rss_ctx_idx;
18482 uint8_t unused_1[6];
18483 } __attribute__((packed));
18485 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
18486 struct hwrm_vnic_rss_cfg_output {
18487 /* The specific error status for the command. */
18488 uint16_t error_code;
18489 /* The HWRM command request type. */
18491 /* The sequence ID from the original command. */
18493 /* The length of the response data in number of bytes. */
18495 uint8_t unused_0[7];
18497 * This field is used in Output records to indicate that the output
18498 * is completely written to RAM. This field should be read as '1'
18499 * to indicate that the output has been completely written.
18500 * When writing a command completion or response to an internal processor,
18501 * the order of writes has to be such that this field is written last.
18504 } __attribute__((packed));
18506 /**********************
18507 * hwrm_vnic_rss_qcfg *
18508 **********************/
18511 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
18512 struct hwrm_vnic_rss_qcfg_input {
18513 /* The HWRM command request type. */
18516 * The completion ring to send the completion event on. This should
18517 * be the NQ ID returned from the `nq_alloc` HWRM command.
18519 uint16_t cmpl_ring;
18521 * The sequence ID is used by the driver for tracking multiple
18522 * commands. This ID is treated as opaque data by the firmware and
18523 * the value is returned in the `hwrm_resp_hdr` upon completion.
18527 * The target ID of the command:
18528 * * 0x0-0xFFF8 - The function ID
18529 * * 0xFFF8-0xFFFE - Reserved for internal processors
18532 uint16_t target_id;
18534 * A physical address pointer pointing to a host buffer that the
18535 * command's response data will be written. This can be either a host
18536 * physical address (HPA) or a guest physical address (GPA) and must
18537 * point to a physically contiguous block of memory.
18539 uint64_t resp_addr;
18540 /* Index to the rss indirection table. */
18541 uint16_t rss_ctx_idx;
18542 uint8_t unused_0[6];
18543 } __attribute__((packed));
18545 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
18546 struct hwrm_vnic_rss_qcfg_output {
18547 /* The specific error status for the command. */
18548 uint16_t error_code;
18549 /* The HWRM command request type. */
18551 /* The sequence ID from the original command. */
18553 /* The length of the response data in number of bytes. */
18555 uint32_t hash_type;
18557 * When this bit is '1', the RSS hash shall be computed
18558 * over source and destination IPv4 addresses of IPv4
18561 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18563 * When this bit is '1', the RSS hash shall be computed
18564 * over source/destination IPv4 addresses and
18565 * source/destination ports of TCP/IPv4 packets.
18567 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18569 * When this bit is '1', the RSS hash shall be computed
18570 * over source/destination IPv4 addresses and
18571 * source/destination ports of UDP/IPv4 packets.
18573 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18575 * When this bit is '1', the RSS hash shall be computed
18576 * over source and destination IPv4 addresses of IPv6
18579 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18581 * When this bit is '1', the RSS hash shall be computed
18582 * over source/destination IPv6 addresses and
18583 * source/destination ports of TCP/IPv6 packets.
18585 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18587 * When this bit is '1', the RSS hash shall be computed
18588 * over source/destination IPv6 addresses and
18589 * source/destination ports of UDP/IPv6 packets.
18591 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18592 uint8_t unused_0[4];
18593 /* This is the value of rss hash key */
18594 uint32_t hash_key[10];
18595 /* Flags to specify different RSS hash modes. */
18596 uint8_t hash_mode_flags;
18598 * When this bit is '1', it indicates using current RSS
18599 * hash mode setting configured in the device.
18601 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
18604 * When this bit is '1', it indicates requesting support of
18605 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18606 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18607 * packets, the RSS hash is computed over the normal
18608 * src/dest l3 and src/dest l4 headers.
18610 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18613 * When this bit is '1', it indicates requesting support of
18614 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18615 * tunnel packets. For none-tunnel packets, the RSS hash is
18616 * computed over the normal src/dest l3 headers.
18618 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18621 * When this bit is '1', it indicates requesting support of
18622 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18623 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18624 * packets, the RSS hash is computed over the normal
18625 * src/dest l3 and src/dest l4 headers.
18627 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18630 * When this bit is '1', it indicates requesting support of
18631 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18632 * tunnel packets. For none-tunnel packets, the RSS hash is
18633 * computed over the normal src/dest l3 headers.
18635 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18637 uint8_t unused_1[6];
18639 * This field is used in Output records to indicate that the output
18640 * is completely written to RAM. This field should be read as '1'
18641 * to indicate that the output has been completely written.
18642 * When writing a command completion or response to an internal processor,
18643 * the order of writes has to be such that this field is written last.
18646 } __attribute__((packed));
18648 /**************************
18649 * hwrm_vnic_plcmodes_cfg *
18650 **************************/
18653 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
18654 struct hwrm_vnic_plcmodes_cfg_input {
18655 /* The HWRM command request type. */
18658 * The completion ring to send the completion event on. This should
18659 * be the NQ ID returned from the `nq_alloc` HWRM command.
18661 uint16_t cmpl_ring;
18663 * The sequence ID is used by the driver for tracking multiple
18664 * commands. This ID is treated as opaque data by the firmware and
18665 * the value is returned in the `hwrm_resp_hdr` upon completion.
18669 * The target ID of the command:
18670 * * 0x0-0xFFF8 - The function ID
18671 * * 0xFFF8-0xFFFE - Reserved for internal processors
18674 uint16_t target_id;
18676 * A physical address pointer pointing to a host buffer that the
18677 * command's response data will be written. This can be either a host
18678 * physical address (HPA) or a guest physical address (GPA) and must
18679 * point to a physically contiguous block of memory.
18681 uint64_t resp_addr;
18684 * When this bit is '1', the VNIC shall be configured to
18685 * use regular placement algorithm.
18686 * By default, the regular placement algorithm shall be
18687 * enabled on the VNIC.
18689 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
18692 * When this bit is '1', the VNIC shall be configured
18693 * use the jumbo placement algorithm.
18695 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
18698 * When this bit is '1', the VNIC shall be configured
18699 * to enable Header-Data split for IPv4 packets according
18700 * to the following rules:
18701 * # If the packet is identified as TCP/IPv4, then the
18702 * packet is split at the beginning of the TCP payload.
18703 * # If the packet is identified as UDP/IPv4, then the
18704 * packet is split at the beginning of UDP payload.
18705 * # If the packet is identified as non-TCP and non-UDP
18706 * IPv4 packet, then the packet is split at the beginning
18707 * of the upper layer protocol header carried in the IPv4
18710 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
18713 * When this bit is '1', the VNIC shall be configured
18714 * to enable Header-Data split for IPv6 packets according
18715 * to the following rules:
18716 * # If the packet is identified as TCP/IPv6, then the
18717 * packet is split at the beginning of the TCP payload.
18718 * # If the packet is identified as UDP/IPv6, then the
18719 * packet is split at the beginning of UDP payload.
18720 * # If the packet is identified as non-TCP and non-UDP
18721 * IPv6 packet, then the packet is split at the beginning
18722 * of the upper layer protocol header carried in the IPv6
18725 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
18728 * When this bit is '1', the VNIC shall be configured
18729 * to enable Header-Data split for FCoE packets at the
18730 * beginning of FC payload.
18732 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
18735 * When this bit is '1', the VNIC shall be configured
18736 * to enable Header-Data split for RoCE packets at the
18737 * beginning of RoCE payload (after BTH/GRH headers).
18739 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
18743 * This bit must be '1' for the jumbo_thresh_valid field to be
18746 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
18749 * This bit must be '1' for the hds_offset_valid field to be
18752 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
18755 * This bit must be '1' for the hds_threshold_valid field to be
18758 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
18760 /* Logical vnic ID */
18763 * When jumbo placement algorithm is enabled, this value
18764 * is used to determine the threshold for jumbo placement.
18765 * Packets with length larger than this value will be
18766 * placed according to the jumbo placement algorithm.
18768 uint16_t jumbo_thresh;
18770 * This value is used to determine the offset into
18771 * packet buffer where the split data (payload) will be
18772 * placed according to one of of HDS placement algorithm.
18774 * The lengths of packet buffers provided for split data
18775 * shall be larger than this value.
18777 uint16_t hds_offset;
18779 * When one of the HDS placement algorithm is enabled, this
18780 * value is used to determine the threshold for HDS
18782 * Packets with length larger than this value will be
18783 * placed according to the HDS placement algorithm.
18784 * This value shall be in multiple of 4 bytes.
18786 uint16_t hds_threshold;
18787 uint8_t unused_0[6];
18788 } __attribute__((packed));
18790 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
18791 struct hwrm_vnic_plcmodes_cfg_output {
18792 /* The specific error status for the command. */
18793 uint16_t error_code;
18794 /* The HWRM command request type. */
18796 /* The sequence ID from the original command. */
18798 /* The length of the response data in number of bytes. */
18800 uint8_t unused_0[7];
18802 * This field is used in Output records to indicate that the output
18803 * is completely written to RAM. This field should be read as '1'
18804 * to indicate that the output has been completely written.
18805 * When writing a command completion or response to an internal processor,
18806 * the order of writes has to be such that this field is written last.
18809 } __attribute__((packed));
18811 /***************************
18812 * hwrm_vnic_plcmodes_qcfg *
18813 ***************************/
18816 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
18817 struct hwrm_vnic_plcmodes_qcfg_input {
18818 /* The HWRM command request type. */
18821 * The completion ring to send the completion event on. This should
18822 * be the NQ ID returned from the `nq_alloc` HWRM command.
18824 uint16_t cmpl_ring;
18826 * The sequence ID is used by the driver for tracking multiple
18827 * commands. This ID is treated as opaque data by the firmware and
18828 * the value is returned in the `hwrm_resp_hdr` upon completion.
18832 * The target ID of the command:
18833 * * 0x0-0xFFF8 - The function ID
18834 * * 0xFFF8-0xFFFE - Reserved for internal processors
18837 uint16_t target_id;
18839 * A physical address pointer pointing to a host buffer that the
18840 * command's response data will be written. This can be either a host
18841 * physical address (HPA) or a guest physical address (GPA) and must
18842 * point to a physically contiguous block of memory.
18844 uint64_t resp_addr;
18845 /* Logical vnic ID */
18847 uint8_t unused_0[4];
18848 } __attribute__((packed));
18850 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
18851 struct hwrm_vnic_plcmodes_qcfg_output {
18852 /* The specific error status for the command. */
18853 uint16_t error_code;
18854 /* The HWRM command request type. */
18856 /* The sequence ID from the original command. */
18858 /* The length of the response data in number of bytes. */
18862 * When this bit is '1', the VNIC is configured to
18863 * use regular placement algorithm.
18865 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
18868 * When this bit is '1', the VNIC is configured to
18869 * use the jumbo placement algorithm.
18871 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
18874 * When this bit is '1', the VNIC is configured
18875 * to enable Header-Data split for IPv4 packets.
18877 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
18880 * When this bit is '1', the VNIC is configured
18881 * to enable Header-Data split for IPv6 packets.
18883 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
18886 * When this bit is '1', the VNIC is configured
18887 * to enable Header-Data split for FCoE packets.
18889 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
18892 * When this bit is '1', the VNIC is configured
18893 * to enable Header-Data split for RoCE packets.
18895 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
18898 * When this bit is '1', the VNIC is configured
18899 * to be the default VNIC of the requesting function.
18901 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
18904 * When jumbo placement algorithm is enabled, this value
18905 * is used to determine the threshold for jumbo placement.
18906 * Packets with length larger than this value will be
18907 * placed according to the jumbo placement algorithm.
18909 uint16_t jumbo_thresh;
18911 * This value is used to determine the offset into
18912 * packet buffer where the split data (payload) will be
18913 * placed according to one of of HDS placement algorithm.
18915 * The lengths of packet buffers provided for split data
18916 * shall be larger than this value.
18918 uint16_t hds_offset;
18920 * When one of the HDS placement algorithm is enabled, this
18921 * value is used to determine the threshold for HDS
18923 * Packets with length larger than this value will be
18924 * placed according to the HDS placement algorithm.
18925 * This value shall be in multiple of 4 bytes.
18927 uint16_t hds_threshold;
18928 uint8_t unused_0[5];
18930 * This field is used in Output records to indicate that the output
18931 * is completely written to RAM. This field should be read as '1'
18932 * to indicate that the output has been completely written.
18933 * When writing a command completion or response to an internal processor,
18934 * the order of writes has to be such that this field is written last.
18937 } __attribute__((packed));
18939 /**********************************
18940 * hwrm_vnic_rss_cos_lb_ctx_alloc *
18941 **********************************/
18944 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
18945 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
18946 /* The HWRM command request type. */
18949 * The completion ring to send the completion event on. This should
18950 * be the NQ ID returned from the `nq_alloc` HWRM command.
18952 uint16_t cmpl_ring;
18954 * The sequence ID is used by the driver for tracking multiple
18955 * commands. This ID is treated as opaque data by the firmware and
18956 * the value is returned in the `hwrm_resp_hdr` upon completion.
18960 * The target ID of the command:
18961 * * 0x0-0xFFF8 - The function ID
18962 * * 0xFFF8-0xFFFE - Reserved for internal processors
18965 uint16_t target_id;
18967 * A physical address pointer pointing to a host buffer that the
18968 * command's response data will be written. This can be either a host
18969 * physical address (HPA) or a guest physical address (GPA) and must
18970 * point to a physically contiguous block of memory.
18972 uint64_t resp_addr;
18973 } __attribute__((packed));
18975 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
18976 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
18977 /* The specific error status for the command. */
18978 uint16_t error_code;
18979 /* The HWRM command request type. */
18981 /* The sequence ID from the original command. */
18983 /* The length of the response data in number of bytes. */
18985 /* rss_cos_lb_ctx_id is 16 b */
18986 uint16_t rss_cos_lb_ctx_id;
18987 uint8_t unused_0[5];
18989 * This field is used in Output records to indicate that the output
18990 * is completely written to RAM. This field should be read as '1'
18991 * to indicate that the output has been completely written.
18992 * When writing a command completion or response to an internal processor,
18993 * the order of writes has to be such that this field is written last.
18996 } __attribute__((packed));
18998 /*********************************
18999 * hwrm_vnic_rss_cos_lb_ctx_free *
19000 *********************************/
19003 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
19004 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
19005 /* The HWRM command request type. */
19008 * The completion ring to send the completion event on. This should
19009 * be the NQ ID returned from the `nq_alloc` HWRM command.
19011 uint16_t cmpl_ring;
19013 * The sequence ID is used by the driver for tracking multiple
19014 * commands. This ID is treated as opaque data by the firmware and
19015 * the value is returned in the `hwrm_resp_hdr` upon completion.
19019 * The target ID of the command:
19020 * * 0x0-0xFFF8 - The function ID
19021 * * 0xFFF8-0xFFFE - Reserved for internal processors
19024 uint16_t target_id;
19026 * A physical address pointer pointing to a host buffer that the
19027 * command's response data will be written. This can be either a host
19028 * physical address (HPA) or a guest physical address (GPA) and must
19029 * point to a physically contiguous block of memory.
19031 uint64_t resp_addr;
19032 /* rss_cos_lb_ctx_id is 16 b */
19033 uint16_t rss_cos_lb_ctx_id;
19034 uint8_t unused_0[6];
19035 } __attribute__((packed));
19037 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
19038 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
19039 /* The specific error status for the command. */
19040 uint16_t error_code;
19041 /* The HWRM command request type. */
19043 /* The sequence ID from the original command. */
19045 /* The length of the response data in number of bytes. */
19047 uint8_t unused_0[7];
19049 * This field is used in Output records to indicate that the output
19050 * is completely written to RAM. This field should be read as '1'
19051 * to indicate that the output has been completely written.
19052 * When writing a command completion or response to an internal processor,
19053 * the order of writes has to be such that this field is written last.
19056 } __attribute__((packed));
19058 /*******************
19059 * hwrm_ring_alloc *
19060 *******************/
19063 /* hwrm_ring_alloc_input (size:640b/80B) */
19064 struct hwrm_ring_alloc_input {
19065 /* The HWRM command request type. */
19068 * The completion ring to send the completion event on. This should
19069 * be the NQ ID returned from the `nq_alloc` HWRM command.
19071 uint16_t cmpl_ring;
19073 * The sequence ID is used by the driver for tracking multiple
19074 * commands. This ID is treated as opaque data by the firmware and
19075 * the value is returned in the `hwrm_resp_hdr` upon completion.
19079 * The target ID of the command:
19080 * * 0x0-0xFFF8 - The function ID
19081 * * 0xFFF8-0xFFFE - Reserved for internal processors
19084 uint16_t target_id;
19086 * A physical address pointer pointing to a host buffer that the
19087 * command's response data will be written. This can be either a host
19088 * physical address (HPA) or a guest physical address (GPA) and must
19089 * point to a physically contiguous block of memory.
19091 uint64_t resp_addr;
19094 * This bit must be '1' for the ring_arb_cfg field to be
19097 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
19100 * This bit must be '1' for the stat_ctx_id_valid field to be
19103 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
19106 * This bit must be '1' for the max_bw_valid field to be
19109 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
19112 * This bit must be '1' for the rx_ring_id field to be
19115 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
19118 * This bit must be '1' for the nq_ring_id field to be
19121 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
19124 * This bit must be '1' for the rx_buf_size field to be
19127 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
19131 /* L2 Completion Ring (CR) */
19132 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19134 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
19136 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
19137 /* RoCE Notification Completion Ring (ROCE_CR) */
19138 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19139 /* RX Aggregation Ring */
19140 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
19141 /* Notification Queue */
19142 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
19143 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
19144 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
19145 uint8_t unused_0[3];
19147 * This value is a pointer to the page table for the
19150 uint64_t page_tbl_addr;
19151 /* First Byte Offset of the first entry in the first page. */
19154 * Actual page size in 2^page_size. The supported range is increments
19155 * in powers of 2 from 16 bytes to 1GB.
19157 * Page size is 16 B.
19159 * Page size is 4 KB.
19161 * Page size is 8 KB.
19163 * Page size is 64 KB.
19165 * Page size is 2 MB.
19167 * Page size is 4 MB.
19169 * Page size is 1 GB.
19173 * This value indicates the depth of page table.
19174 * For this version of the specification, value other than 0 or
19175 * 1 shall be considered as an invalid value.
19176 * When the page_tbl_depth = 0, then it is treated as a
19177 * special case with the following.
19178 * 1. FBO and page size fields are not valid.
19179 * 2. page_tbl_addr is the physical address of the first
19180 * element of the ring.
19182 uint8_t page_tbl_depth;
19183 uint8_t unused_1[2];
19185 * Number of 16B units in the ring. Minimum size for
19186 * a ring is 16 16B entries.
19190 * Logical ring number for the ring to be allocated.
19191 * This value determines the position in the doorbell
19192 * area where the update to the ring will be made.
19194 * For completion rings, this value is also the MSI-X
19195 * vector number for the function the completion ring is
19198 uint16_t logical_id;
19200 * This field is used only when ring_type is a TX ring.
19201 * This value indicates what completion ring the TX ring
19202 * is associated with.
19204 uint16_t cmpl_ring_id;
19206 * This field is used only when ring_type is a TX ring.
19207 * This value indicates what CoS queue the TX ring
19208 * is associated with.
19212 * When allocating a Rx ring or Rx aggregation ring, this field
19213 * specifies the size of the buffer descriptors posted to the ring.
19215 uint16_t rx_buf_size;
19217 * When allocating an Rx aggregation ring, this field
19218 * specifies the associated Rx ring ID.
19220 uint16_t rx_ring_id;
19222 * When allocating a completion ring, this field
19223 * specifies the associated NQ ring ID.
19225 uint16_t nq_ring_id;
19227 * This field is used only when ring_type is a TX ring.
19228 * This field is used to configure arbitration related
19229 * parameters for a TX ring.
19231 uint16_t ring_arb_cfg;
19232 /* Arbitration policy used for the ring. */
19233 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
19235 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
19237 * Use strict priority for the TX ring.
19238 * Priority value is specified in arb_policy_param
19240 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
19243 * Use weighted fair queue arbitration for the TX ring.
19244 * Weight is specified in arb_policy_param
19246 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
19248 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
19249 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
19250 /* Reserved field. */
19251 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
19253 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
19255 * Arbitration policy specific parameter.
19256 * # For strict priority arbitration policy, this field
19257 * represents a priority value. If set to 0, then the priority
19258 * is not specified and the HWRM is allowed to select
19259 * any priority for this TX ring.
19260 * # For weighted fair queue arbitration policy, this field
19261 * represents a weight value. If set to 0, then the weight
19262 * is not specified and the HWRM is allowed to select
19263 * any weight for this TX ring.
19265 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
19267 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
19270 * This field is reserved for the future use.
19271 * It shall be set to 0.
19273 uint32_t reserved3;
19275 * This field is used only when ring_type is a TX ring.
19276 * This input indicates what statistics context this ring
19277 * should be associated with.
19279 uint32_t stat_ctx_id;
19281 * This field is reserved for the future use.
19282 * It shall be set to 0.
19284 uint32_t reserved4;
19286 * This field is used only when ring_type is a TX ring
19287 * to specify maximum BW allocated to the TX ring.
19288 * The HWRM will translate this value into byte counter and
19289 * time interval used for this ring inside the device.
19292 /* The bandwidth value. */
19293 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
19294 UINT32_C(0xfffffff)
19295 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
19296 /* The granularity of the value (bits or bytes). */
19297 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
19298 UINT32_C(0x10000000)
19299 /* Value is in bits. */
19300 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
19301 (UINT32_C(0x0) << 28)
19302 /* Value is in bytes. */
19303 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
19304 (UINT32_C(0x1) << 28)
19305 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
19306 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
19307 /* bw_value_unit is 3 b */
19308 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
19309 UINT32_C(0xe0000000)
19310 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
19311 /* Value is in Mb or MB (base 10). */
19312 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
19313 (UINT32_C(0x0) << 29)
19314 /* Value is in Kb or KB (base 10). */
19315 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
19316 (UINT32_C(0x2) << 29)
19317 /* Value is in bits or bytes. */
19318 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
19319 (UINT32_C(0x4) << 29)
19320 /* Value is in Gb or GB (base 10). */
19321 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
19322 (UINT32_C(0x6) << 29)
19323 /* Value is in 1/100th of a percentage of total bandwidth. */
19324 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19325 (UINT32_C(0x1) << 29)
19327 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
19328 (UINT32_C(0x7) << 29)
19329 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
19330 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
19332 * This field is used only when ring_type is a Completion ring.
19333 * This value indicates what interrupt mode should be used
19334 * on this completion ring.
19335 * Note: In the legacy interrupt mode, no more than 16
19336 * completion rings are allowed.
19340 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
19342 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
19344 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
19345 /* No Interrupt - Polled mode */
19346 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
19347 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
19348 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
19349 uint8_t unused_4[3];
19350 } __attribute__((packed));
19352 /* hwrm_ring_alloc_output (size:128b/16B) */
19353 struct hwrm_ring_alloc_output {
19354 /* The specific error status for the command. */
19355 uint16_t error_code;
19356 /* The HWRM command request type. */
19358 /* The sequence ID from the original command. */
19360 /* The length of the response data in number of bytes. */
19363 * Physical number of ring allocated.
19364 * This value shall be unique for a ring type.
19367 /* Logical number of ring allocated. */
19368 uint16_t logical_ring_id;
19369 uint8_t unused_0[3];
19371 * This field is used in Output records to indicate that the output
19372 * is completely written to RAM. This field should be read as '1'
19373 * to indicate that the output has been completely written.
19374 * When writing a command completion or response to an internal processor,
19375 * the order of writes has to be such that this field is written last.
19378 } __attribute__((packed));
19380 /******************
19382 ******************/
19385 /* hwrm_ring_free_input (size:192b/24B) */
19386 struct hwrm_ring_free_input {
19387 /* The HWRM command request type. */
19390 * The completion ring to send the completion event on. This should
19391 * be the NQ ID returned from the `nq_alloc` HWRM command.
19393 uint16_t cmpl_ring;
19395 * The sequence ID is used by the driver for tracking multiple
19396 * commands. This ID is treated as opaque data by the firmware and
19397 * the value is returned in the `hwrm_resp_hdr` upon completion.
19401 * The target ID of the command:
19402 * * 0x0-0xFFF8 - The function ID
19403 * * 0xFFF8-0xFFFE - Reserved for internal processors
19406 uint16_t target_id;
19408 * A physical address pointer pointing to a host buffer that the
19409 * command's response data will be written. This can be either a host
19410 * physical address (HPA) or a guest physical address (GPA) and must
19411 * point to a physically contiguous block of memory.
19413 uint64_t resp_addr;
19416 /* L2 Completion Ring (CR) */
19417 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19419 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
19421 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
19422 /* RoCE Notification Completion Ring (ROCE_CR) */
19423 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19424 /* RX Aggregation Ring */
19425 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
19426 /* Notification Queue */
19427 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
19428 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
19429 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
19431 /* Physical number of ring allocated. */
19433 uint8_t unused_1[4];
19434 } __attribute__((packed));
19436 /* hwrm_ring_free_output (size:128b/16B) */
19437 struct hwrm_ring_free_output {
19438 /* The specific error status for the command. */
19439 uint16_t error_code;
19440 /* The HWRM command request type. */
19442 /* The sequence ID from the original command. */
19444 /* The length of the response data in number of bytes. */
19446 uint8_t unused_0[7];
19448 * This field is used in Output records to indicate that the output
19449 * is completely written to RAM. This field should be read as '1'
19450 * to indicate that the output has been completely written.
19451 * When writing a command completion or response to an internal processor,
19452 * the order of writes has to be such that this field is written last.
19455 } __attribute__((packed));
19457 /**************************************
19458 * hwrm_ring_cmpl_ring_qaggint_params *
19459 **************************************/
19462 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
19463 struct hwrm_ring_cmpl_ring_qaggint_params_input {
19464 /* The HWRM command request type. */
19467 * The completion ring to send the completion event on. This should
19468 * be the NQ ID returned from the `nq_alloc` HWRM command.
19470 uint16_t cmpl_ring;
19472 * The sequence ID is used by the driver for tracking multiple
19473 * commands. This ID is treated as opaque data by the firmware and
19474 * the value is returned in the `hwrm_resp_hdr` upon completion.
19478 * The target ID of the command:
19479 * * 0x0-0xFFF8 - The function ID
19480 * * 0xFFF8-0xFFFE - Reserved for internal processors
19483 uint16_t target_id;
19485 * A physical address pointer pointing to a host buffer that the
19486 * command's response data will be written. This can be either a host
19487 * physical address (HPA) or a guest physical address (GPA) and must
19488 * point to a physically contiguous block of memory.
19490 uint64_t resp_addr;
19491 /* Physical number of completion ring. */
19493 uint8_t unused_0[6];
19494 } __attribute__((packed));
19496 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
19497 struct hwrm_ring_cmpl_ring_qaggint_params_output {
19498 /* The specific error status for the command. */
19499 uint16_t error_code;
19500 /* The HWRM command request type. */
19502 /* The sequence ID from the original command. */
19504 /* The length of the response data in number of bytes. */
19508 * When this bit is set to '1', interrupt max
19509 * timer is reset whenever a completion is received.
19511 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
19514 * When this bit is set to '1', ring idle mode
19515 * aggregation will be enabled.
19517 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
19520 * Number of completions to aggregate before DMA
19521 * during the normal mode.
19523 uint16_t num_cmpl_dma_aggr;
19525 * Number of completions to aggregate before DMA
19526 * during the interrupt mode.
19528 uint16_t num_cmpl_dma_aggr_during_int;
19530 * Timer in unit of 80-nsec used to aggregate completions before
19531 * DMA during the normal mode (not in interrupt mode).
19533 uint16_t cmpl_aggr_dma_tmr;
19535 * Timer in unit of 80-nsec used to aggregate completions before
19536 * DMA during the interrupt mode.
19538 uint16_t cmpl_aggr_dma_tmr_during_int;
19539 /* Minimum time (in unit of 80-nsec) between two interrupts. */
19540 uint16_t int_lat_tmr_min;
19542 * Maximum wait time (in unit of 80-nsec) spent aggregating
19543 * completions before signaling the interrupt after the
19544 * interrupt is enabled.
19546 uint16_t int_lat_tmr_max;
19548 * Minimum number of completions aggregated before signaling
19551 uint16_t num_cmpl_aggr_int;
19552 uint8_t unused_0[7];
19554 * This field is used in Output records to indicate that the output
19555 * is completely written to RAM. This field should be read as '1'
19556 * to indicate that the output has been completely written.
19557 * When writing a command completion or response to an internal processor,
19558 * the order of writes has to be such that this field is written last.
19561 } __attribute__((packed));
19563 /*****************************************
19564 * hwrm_ring_cmpl_ring_cfg_aggint_params *
19565 *****************************************/
19568 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
19569 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
19570 /* The HWRM command request type. */
19573 * The completion ring to send the completion event on. This should
19574 * be the NQ ID returned from the `nq_alloc` HWRM command.
19576 uint16_t cmpl_ring;
19578 * The sequence ID is used by the driver for tracking multiple
19579 * commands. This ID is treated as opaque data by the firmware and
19580 * the value is returned in the `hwrm_resp_hdr` upon completion.
19584 * The target ID of the command:
19585 * * 0x0-0xFFF8 - The function ID
19586 * * 0xFFF8-0xFFFE - Reserved for internal processors
19589 uint16_t target_id;
19591 * A physical address pointer pointing to a host buffer that the
19592 * command's response data will be written. This can be either a host
19593 * physical address (HPA) or a guest physical address (GPA) and must
19594 * point to a physically contiguous block of memory.
19596 uint64_t resp_addr;
19597 /* Physical number of completion ring. */
19601 * When this bit is set to '1', interrupt latency max
19602 * timer is reset whenever a completion is received.
19604 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
19607 * When this bit is set to '1', ring idle mode
19608 * aggregation will be enabled.
19610 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
19613 * Set this flag to 1 when configuring parameters on a
19614 * notification queue. Set this flag to 0 when configuring
19615 * parameters on a completion queue.
19617 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
19620 * Number of completions to aggregate before DMA
19621 * during the normal mode.
19623 uint16_t num_cmpl_dma_aggr;
19625 * Number of completions to aggregate before DMA
19626 * during the interrupt mode.
19628 uint16_t num_cmpl_dma_aggr_during_int;
19630 * Timer in unit of 80-nsec used to aggregate completions before
19631 * DMA during the normal mode (not in interrupt mode).
19633 uint16_t cmpl_aggr_dma_tmr;
19635 * Timer in unit of 80-nsec used to aggregate completions before
19636 * DMA during the interrupt mode.
19638 uint16_t cmpl_aggr_dma_tmr_during_int;
19639 /* Minimum time (in unit of 80-nsec) between two interrupts. */
19640 uint16_t int_lat_tmr_min;
19642 * Maximum wait time (in unit of 80-nsec) spent aggregating
19643 * cmpls before signaling the interrupt after the
19644 * interrupt is enabled.
19646 uint16_t int_lat_tmr_max;
19648 * Minimum number of completions aggregated before signaling
19651 uint16_t num_cmpl_aggr_int;
19653 * Bitfield that indicates which parameters are to be applied. Only
19654 * required when configuring devices with notification queues, and
19655 * used in that case to set certain parameters on completion queues
19656 * and others on notification queues.
19660 * This bit must be '1' for the num_cmpl_dma_aggr field to be
19663 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
19666 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
19669 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
19672 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
19675 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
19678 * This bit must be '1' for the int_lat_tmr_min field to be
19681 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
19684 * This bit must be '1' for the int_lat_tmr_max field to be
19687 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
19690 * This bit must be '1' for the num_cmpl_aggr_int field to be
19693 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
19695 uint8_t unused_0[4];
19696 } __attribute__((packed));
19698 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
19699 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
19700 /* The specific error status for the command. */
19701 uint16_t error_code;
19702 /* The HWRM command request type. */
19704 /* The sequence ID from the original command. */
19706 /* The length of the response data in number of bytes. */
19708 uint8_t unused_0[7];
19710 * This field is used in Output records to indicate that the output
19711 * is completely written to RAM. This field should be read as '1'
19712 * to indicate that the output has been completely written.
19713 * When writing a command completion or response to an internal processor,
19714 * the order of writes has to be such that this field is written last.
19717 } __attribute__((packed));
19719 /*******************
19720 * hwrm_ring_reset *
19721 *******************/
19724 /* hwrm_ring_reset_input (size:192b/24B) */
19725 struct hwrm_ring_reset_input {
19726 /* The HWRM command request type. */
19729 * The completion ring to send the completion event on. This should
19730 * be the NQ ID returned from the `nq_alloc` HWRM command.
19732 uint16_t cmpl_ring;
19734 * The sequence ID is used by the driver for tracking multiple
19735 * commands. This ID is treated as opaque data by the firmware and
19736 * the value is returned in the `hwrm_resp_hdr` upon completion.
19740 * The target ID of the command:
19741 * * 0x0-0xFFF8 - The function ID
19742 * * 0xFFF8-0xFFFE - Reserved for internal processors
19745 uint16_t target_id;
19747 * A physical address pointer pointing to a host buffer that the
19748 * command's response data will be written. This can be either a host
19749 * physical address (HPA) or a guest physical address (GPA) and must
19750 * point to a physically contiguous block of memory.
19752 uint64_t resp_addr;
19755 /* L2 Completion Ring (CR) */
19756 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19758 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
19760 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
19761 /* RoCE Notification Completion Ring (ROCE_CR) */
19762 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19763 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
19764 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
19766 /* Physical number of the ring. */
19768 uint8_t unused_1[4];
19769 } __attribute__((packed));
19771 /* hwrm_ring_reset_output (size:128b/16B) */
19772 struct hwrm_ring_reset_output {
19773 /* The specific error status for the command. */
19774 uint16_t error_code;
19775 /* The HWRM command request type. */
19777 /* The sequence ID from the original command. */
19779 /* The length of the response data in number of bytes. */
19781 uint8_t unused_0[7];
19783 * This field is used in Output records to indicate that the output
19784 * is completely written to RAM. This field should be read as '1'
19785 * to indicate that the output has been completely written.
19786 * When writing a command completion or response to an internal processor,
19787 * the order of writes has to be such that this field is written last.
19790 } __attribute__((packed));
19792 /***********************
19793 * hwrm_ring_grp_alloc *
19794 ***********************/
19797 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
19798 struct hwrm_ring_grp_alloc_input {
19799 /* The HWRM command request type. */
19802 * The completion ring to send the completion event on. This should
19803 * be the NQ ID returned from the `nq_alloc` HWRM command.
19805 uint16_t cmpl_ring;
19807 * The sequence ID is used by the driver for tracking multiple
19808 * commands. This ID is treated as opaque data by the firmware and
19809 * the value is returned in the `hwrm_resp_hdr` upon completion.
19813 * The target ID of the command:
19814 * * 0x0-0xFFF8 - The function ID
19815 * * 0xFFF8-0xFFFE - Reserved for internal processors
19818 uint16_t target_id;
19820 * A physical address pointer pointing to a host buffer that the
19821 * command's response data will be written. This can be either a host
19822 * physical address (HPA) or a guest physical address (GPA) and must
19823 * point to a physically contiguous block of memory.
19825 uint64_t resp_addr;
19827 * This value identifies the CR associated with the ring
19832 * This value identifies the main RR associated with the ring
19837 * This value identifies the aggregation RR associated with
19838 * the ring group. If this value is 0xFF... (All Fs), then no
19839 * Aggregation ring will be set.
19843 * This value identifies the statistics context associated
19844 * with the ring group.
19847 } __attribute__((packed));
19849 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
19850 struct hwrm_ring_grp_alloc_output {
19851 /* The specific error status for the command. */
19852 uint16_t error_code;
19853 /* The HWRM command request type. */
19855 /* The sequence ID from the original command. */
19857 /* The length of the response data in number of bytes. */
19860 * This is the ring group ID value. Use this value to program
19861 * the default ring group for the VNIC or as table entries
19862 * in an RSS/COS context.
19864 uint32_t ring_group_id;
19865 uint8_t unused_0[3];
19867 * This field is used in Output records to indicate that the output
19868 * is completely written to RAM. This field should be read as '1'
19869 * to indicate that the output has been completely written.
19870 * When writing a command completion or response to an internal processor,
19871 * the order of writes has to be such that this field is written last.
19874 } __attribute__((packed));
19876 /**********************
19877 * hwrm_ring_grp_free *
19878 **********************/
19881 /* hwrm_ring_grp_free_input (size:192b/24B) */
19882 struct hwrm_ring_grp_free_input {
19883 /* The HWRM command request type. */
19886 * The completion ring to send the completion event on. This should
19887 * be the NQ ID returned from the `nq_alloc` HWRM command.
19889 uint16_t cmpl_ring;
19891 * The sequence ID is used by the driver for tracking multiple
19892 * commands. This ID is treated as opaque data by the firmware and
19893 * the value is returned in the `hwrm_resp_hdr` upon completion.
19897 * The target ID of the command:
19898 * * 0x0-0xFFF8 - The function ID
19899 * * 0xFFF8-0xFFFE - Reserved for internal processors
19902 uint16_t target_id;
19904 * A physical address pointer pointing to a host buffer that the
19905 * command's response data will be written. This can be either a host
19906 * physical address (HPA) or a guest physical address (GPA) and must
19907 * point to a physically contiguous block of memory.
19909 uint64_t resp_addr;
19910 /* This is the ring group ID value. */
19911 uint32_t ring_group_id;
19912 uint8_t unused_0[4];
19913 } __attribute__((packed));
19915 /* hwrm_ring_grp_free_output (size:128b/16B) */
19916 struct hwrm_ring_grp_free_output {
19917 /* The specific error status for the command. */
19918 uint16_t error_code;
19919 /* The HWRM command request type. */
19921 /* The sequence ID from the original command. */
19923 /* The length of the response data in number of bytes. */
19925 uint8_t unused_0[7];
19927 * This field is used in Output records to indicate that the output
19928 * is completely written to RAM. This field should be read as '1'
19929 * to indicate that the output has been completely written.
19930 * When writing a command completion or response to an internal processor,
19931 * the order of writes has to be such that this field is written last.
19934 } __attribute__((packed));
19936 /****************************
19937 * hwrm_cfa_l2_filter_alloc *
19938 ****************************/
19941 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
19942 struct hwrm_cfa_l2_filter_alloc_input {
19943 /* The HWRM command request type. */
19946 * The completion ring to send the completion event on. This should
19947 * be the NQ ID returned from the `nq_alloc` HWRM command.
19949 uint16_t cmpl_ring;
19951 * The sequence ID is used by the driver for tracking multiple
19952 * commands. This ID is treated as opaque data by the firmware and
19953 * the value is returned in the `hwrm_resp_hdr` upon completion.
19957 * The target ID of the command:
19958 * * 0x0-0xFFF8 - The function ID
19959 * * 0xFFF8-0xFFFE - Reserved for internal processors
19962 uint16_t target_id;
19964 * A physical address pointer pointing to a host buffer that the
19965 * command's response data will be written. This can be either a host
19966 * physical address (HPA) or a guest physical address (GPA) and must
19967 * point to a physically contiguous block of memory.
19969 uint64_t resp_addr;
19972 * Enumeration denoting the RX, TX type of the resource.
19973 * This enumeration is used for resources that are similar for both
19974 * TX and RX paths of the chip.
19976 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
19979 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
19982 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
19984 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
19985 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
19986 /* Setting of this flag indicates the applicability to the loopback path. */
19987 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
19990 * Setting of this flag indicates drop action. If this flag is not set,
19991 * then it should be considered accept action.
19993 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
19996 * If this flag is set, all t_l2_* fields are invalid
19997 * and they should not be specified.
19998 * If this flag is set, then l2_* fields refer to
19999 * fields of outermost L2 header.
20001 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
20005 * This bit must be '1' for the l2_addr field to be
20008 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
20011 * This bit must be '1' for the l2_addr_mask field to be
20014 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
20017 * This bit must be '1' for the l2_ovlan field to be
20020 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
20023 * This bit must be '1' for the l2_ovlan_mask field to be
20026 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
20029 * This bit must be '1' for the l2_ivlan field to be
20032 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
20035 * This bit must be '1' for the l2_ivlan_mask field to be
20038 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
20041 * This bit must be '1' for the t_l2_addr field to be
20044 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
20047 * This bit must be '1' for the t_l2_addr_mask field to be
20050 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
20053 * This bit must be '1' for the t_l2_ovlan field to be
20056 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
20059 * This bit must be '1' for the t_l2_ovlan_mask field to be
20062 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
20065 * This bit must be '1' for the t_l2_ivlan field to be
20068 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
20071 * This bit must be '1' for the t_l2_ivlan_mask field to be
20074 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
20077 * This bit must be '1' for the src_type field to be
20080 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
20083 * This bit must be '1' for the src_id field to be
20086 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
20089 * This bit must be '1' for the tunnel_type field to be
20092 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
20095 * This bit must be '1' for the dst_id field to be
20098 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
20101 * This bit must be '1' for the mirror_vnic_id field to be
20104 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
20107 * This value sets the match value for the L2 MAC address.
20108 * Destination MAC address for RX path.
20109 * Source MAC address for TX path.
20111 uint8_t l2_addr[6];
20112 uint8_t unused_0[2];
20114 * This value sets the mask value for the L2 address.
20115 * A value of 0 will mask the corresponding bit from
20118 uint8_t l2_addr_mask[6];
20119 /* This value sets VLAN ID value for outer VLAN. */
20122 * This value sets the mask value for the ovlan id.
20123 * A value of 0 will mask the corresponding bit from
20126 uint16_t l2_ovlan_mask;
20127 /* This value sets VLAN ID value for inner VLAN. */
20130 * This value sets the mask value for the ivlan id.
20131 * A value of 0 will mask the corresponding bit from
20134 uint16_t l2_ivlan_mask;
20135 uint8_t unused_1[2];
20137 * This value sets the match value for the tunnel
20139 * Destination MAC address for RX path.
20140 * Source MAC address for TX path.
20142 uint8_t t_l2_addr[6];
20143 uint8_t unused_2[2];
20145 * This value sets the mask value for the tunnel L2
20147 * A value of 0 will mask the corresponding bit from
20150 uint8_t t_l2_addr_mask[6];
20151 /* This value sets VLAN ID value for tunnel outer VLAN. */
20152 uint16_t t_l2_ovlan;
20154 * This value sets the mask value for the tunnel ovlan id.
20155 * A value of 0 will mask the corresponding bit from
20158 uint16_t t_l2_ovlan_mask;
20159 /* This value sets VLAN ID value for tunnel inner VLAN. */
20160 uint16_t t_l2_ivlan;
20162 * This value sets the mask value for the tunnel ivlan id.
20163 * A value of 0 will mask the corresponding bit from
20166 uint16_t t_l2_ivlan_mask;
20167 /* This value identifies the type of source of the packet. */
20170 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
20171 /* Physical function */
20172 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
20173 /* Virtual function */
20174 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
20175 /* Virtual NIC of a function */
20176 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
20177 /* Embedded processor for CFA management */
20178 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
20179 /* Embedded processor for OOB management */
20180 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
20181 /* Embedded processor for RoCE */
20182 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
20183 /* Embedded processor for network proxy functions */
20184 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
20185 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
20186 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
20189 * This value is the id of the source.
20190 * For a network port, it represents port_id.
20191 * For a physical function, it represents fid.
20192 * For a virtual function, it represents vf_id.
20193 * For a vnic, it represents vnic_id.
20194 * For embedded processors, this id is not valid.
20197 * 1. The function ID is implied if it src_id is
20198 * not provided for a src_type that is either
20202 uint8_t tunnel_type;
20204 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
20206 /* Virtual eXtensible Local Area Network (VXLAN) */
20207 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20209 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
20210 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
20212 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
20213 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
20216 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
20218 /* Generic Network Virtualization Encapsulation (Geneve) */
20219 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
20221 /* Multi-Protocol Lable Switching (MPLS) */
20222 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
20224 /* Stateless Transport Tunnel (STT) */
20225 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
20227 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
20228 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
20230 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20231 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20233 /* Any tunneled traffic */
20234 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
20236 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
20237 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
20240 * If set, this value shall represent the
20241 * Logical VNIC ID of the destination VNIC for the RX
20242 * path and network port id of the destination port for
20247 * Logical VNIC ID of the VNIC where traffic is
20250 uint16_t mirror_vnic_id;
20252 * This hint is provided to help in placing
20253 * the filter in the filter table.
20256 /* No preference */
20257 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
20259 /* Above the given filter */
20260 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
20262 /* Below the given filter */
20263 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
20265 /* As high as possible */
20266 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
20268 /* As low as possible */
20269 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
20271 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
20272 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
20276 * This is the ID of the filter that goes along with
20279 * This field is valid only for the following values.
20280 * 1 - Above the given filter
20281 * 2 - Below the given filter
20283 uint64_t l2_filter_id_hint;
20284 } __attribute__((packed));
20286 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
20287 struct hwrm_cfa_l2_filter_alloc_output {
20288 /* The specific error status for the command. */
20289 uint16_t error_code;
20290 /* The HWRM command request type. */
20292 /* The sequence ID from the original command. */
20294 /* The length of the response data in number of bytes. */
20297 * This value identifies a set of CFA data structures used for an L2
20300 uint64_t l2_filter_id;
20302 * This is the ID of the flow associated with this
20304 * This value shall be used to match and associate the
20305 * flow identifier returned in completion records.
20306 * A value of 0xFFFFFFFF shall indicate no flow id.
20309 uint8_t unused_0[3];
20311 * This field is used in Output records to indicate that the output
20312 * is completely written to RAM. This field should be read as '1'
20313 * to indicate that the output has been completely written.
20314 * When writing a command completion or response to an internal processor,
20315 * the order of writes has to be such that this field is written last.
20318 } __attribute__((packed));
20320 /***************************
20321 * hwrm_cfa_l2_filter_free *
20322 ***************************/
20325 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
20326 struct hwrm_cfa_l2_filter_free_input {
20327 /* The HWRM command request type. */
20330 * The completion ring to send the completion event on. This should
20331 * be the NQ ID returned from the `nq_alloc` HWRM command.
20333 uint16_t cmpl_ring;
20335 * The sequence ID is used by the driver for tracking multiple
20336 * commands. This ID is treated as opaque data by the firmware and
20337 * the value is returned in the `hwrm_resp_hdr` upon completion.
20341 * The target ID of the command:
20342 * * 0x0-0xFFF8 - The function ID
20343 * * 0xFFF8-0xFFFE - Reserved for internal processors
20346 uint16_t target_id;
20348 * A physical address pointer pointing to a host buffer that the
20349 * command's response data will be written. This can be either a host
20350 * physical address (HPA) or a guest physical address (GPA) and must
20351 * point to a physically contiguous block of memory.
20353 uint64_t resp_addr;
20355 * This value identifies a set of CFA data structures used for an L2
20358 uint64_t l2_filter_id;
20359 } __attribute__((packed));
20361 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
20362 struct hwrm_cfa_l2_filter_free_output {
20363 /* The specific error status for the command. */
20364 uint16_t error_code;
20365 /* The HWRM command request type. */
20367 /* The sequence ID from the original command. */
20369 /* The length of the response data in number of bytes. */
20371 uint8_t unused_0[7];
20373 * This field is used in Output records to indicate that the output
20374 * is completely written to RAM. This field should be read as '1'
20375 * to indicate that the output has been completely written.
20376 * When writing a command completion or response to an internal processor,
20377 * the order of writes has to be such that this field is written last.
20380 } __attribute__((packed));
20382 /**************************
20383 * hwrm_cfa_l2_filter_cfg *
20384 **************************/
20387 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
20388 struct hwrm_cfa_l2_filter_cfg_input {
20389 /* The HWRM command request type. */
20392 * The completion ring to send the completion event on. This should
20393 * be the NQ ID returned from the `nq_alloc` HWRM command.
20395 uint16_t cmpl_ring;
20397 * The sequence ID is used by the driver for tracking multiple
20398 * commands. This ID is treated as opaque data by the firmware and
20399 * the value is returned in the `hwrm_resp_hdr` upon completion.
20403 * The target ID of the command:
20404 * * 0x0-0xFFF8 - The function ID
20405 * * 0xFFF8-0xFFFE - Reserved for internal processors
20408 uint16_t target_id;
20410 * A physical address pointer pointing to a host buffer that the
20411 * command's response data will be written. This can be either a host
20412 * physical address (HPA) or a guest physical address (GPA) and must
20413 * point to a physically contiguous block of memory.
20415 uint64_t resp_addr;
20418 * Enumeration denoting the RX, TX type of the resource.
20419 * This enumeration is used for resources that are similar for both
20420 * TX and RX paths of the chip.
20422 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
20424 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
20426 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
20427 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
20428 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
20430 * Setting of this flag indicates drop action. If this flag is not set,
20431 * then it should be considered accept action.
20433 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
20436 * This bit must be '1' for the dst_id field to be
20439 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
20442 * This bit must be '1' for the new_mirror_vnic_id field to be
20445 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
20448 * This value identifies a set of CFA data structures used for an L2
20451 uint64_t l2_filter_id;
20453 * If set, this value shall represent the
20454 * Logical VNIC ID of the destination VNIC for the RX
20455 * path and network port id of the destination port for
20460 * New Logical VNIC ID of the VNIC where traffic is
20463 uint32_t new_mirror_vnic_id;
20464 } __attribute__((packed));
20466 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
20467 struct hwrm_cfa_l2_filter_cfg_output {
20468 /* The specific error status for the command. */
20469 uint16_t error_code;
20470 /* The HWRM command request type. */
20472 /* The sequence ID from the original command. */
20474 /* The length of the response data in number of bytes. */
20476 uint8_t unused_0[7];
20478 * This field is used in Output records to indicate that the output
20479 * is completely written to RAM. This field should be read as '1'
20480 * to indicate that the output has been completely written.
20481 * When writing a command completion or response to an internal processor,
20482 * the order of writes has to be such that this field is written last.
20485 } __attribute__((packed));
20487 /***************************
20488 * hwrm_cfa_l2_set_rx_mask *
20489 ***************************/
20492 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
20493 struct hwrm_cfa_l2_set_rx_mask_input {
20494 /* The HWRM command request type. */
20497 * The completion ring to send the completion event on. This should
20498 * be the NQ ID returned from the `nq_alloc` HWRM command.
20500 uint16_t cmpl_ring;
20502 * The sequence ID is used by the driver for tracking multiple
20503 * commands. This ID is treated as opaque data by the firmware and
20504 * the value is returned in the `hwrm_resp_hdr` upon completion.
20508 * The target ID of the command:
20509 * * 0x0-0xFFF8 - The function ID
20510 * * 0xFFF8-0xFFFE - Reserved for internal processors
20513 uint16_t target_id;
20515 * A physical address pointer pointing to a host buffer that the
20516 * command's response data will be written. This can be either a host
20517 * physical address (HPA) or a guest physical address (GPA) and must
20518 * point to a physically contiguous block of memory.
20520 uint64_t resp_addr;
20525 * When this bit is '1', the function is requested to accept
20526 * multi-cast packets specified by the multicast addr table.
20528 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
20531 * When this bit is '1', the function is requested to accept
20532 * all multi-cast packets.
20534 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
20537 * When this bit is '1', the function is requested to accept
20538 * broadcast packets.
20540 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
20543 * When this bit is '1', the function is requested to be
20544 * put in the promiscuous mode.
20546 * The HWRM should accept any function to set up
20547 * promiscuous mode.
20549 * The HWRM shall follow the semantics below for the
20550 * promiscuous mode support.
20551 * # When partitioning is not enabled on a port
20552 * (i.e. single PF on the port), then the PF shall
20553 * be allowed to be in the promiscuous mode. When the
20554 * PF is in the promiscuous mode, then it shall
20555 * receive all host bound traffic on that port.
20556 * # When partitioning is enabled on a port
20557 * (i.e. multiple PFs per port) and a PF on that
20558 * port is in the promiscuous mode, then the PF
20559 * receives all traffic within that partition as
20560 * identified by a unique identifier for the
20561 * PF (e.g. S-Tag). If a unique outer VLAN
20562 * for the PF is specified, then the setting of
20563 * promiscuous mode on that PF shall result in the
20564 * PF receiving all host bound traffic with matching
20566 * # A VF shall can be set in the promiscuous mode.
20567 * In the promiscuous mode, the VF does not receive any
20568 * traffic unless a unique outer VLAN for the
20569 * VF is specified. If a unique outer VLAN
20570 * for the VF is specified, then the setting of
20571 * promiscuous mode on that VF shall result in the
20572 * VF receiving all host bound traffic with the
20573 * matching outer VLAN.
20574 * # The HWRM shall allow the setting of promiscuous
20575 * mode on a function independently from the
20576 * promiscuous mode settings on other functions.
20578 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
20581 * If this flag is set, the corresponding RX
20582 * filters shall be set up to cover multicast/broadcast
20583 * filters for the outermost Layer 2 destination MAC
20586 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
20589 * If this flag is set, the corresponding RX
20590 * filters shall be set up to cover multicast/broadcast
20591 * filters for the VLAN-tagged packets that match the
20592 * TPID and VID fields of VLAN tags in the VLAN tag
20593 * table specified in this command.
20595 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
20598 * If this flag is set, the corresponding RX
20599 * filters shall be set up to cover multicast/broadcast
20600 * filters for non-VLAN tagged packets and VLAN-tagged
20601 * packets that match the TPID and VID fields of VLAN
20602 * tags in the VLAN tag table specified in this command.
20604 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
20607 * If this flag is set, the corresponding RX
20608 * filters shall be set up to cover multicast/broadcast
20609 * filters for non-VLAN tagged packets and VLAN-tagged
20610 * packets matching any VLAN tag.
20612 * If this flag is set, then the HWRM shall ignore
20613 * VLAN tags specified in vlan_tag_tbl.
20615 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
20616 * flags is set, then the HWRM shall ignore
20617 * VLAN tags specified in vlan_tag_tbl.
20619 * The HWRM client shall set at most one flag out of
20620 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
20622 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
20624 /* This is the address for mcast address tbl. */
20625 uint64_t mc_tbl_addr;
20627 * This value indicates how many entries in mc_tbl are valid.
20628 * Each entry is 6 bytes.
20630 uint32_t num_mc_entries;
20631 uint8_t unused_0[4];
20633 * This is the address for VLAN tag table.
20634 * Each VLAN entry in the table is 4 bytes of a VLAN tag
20635 * including TPID, PCP, DEI, and VID fields in network byte
20638 uint64_t vlan_tag_tbl_addr;
20640 * This value indicates how many entries in vlan_tag_tbl are
20641 * valid. Each entry is 4 bytes.
20643 uint32_t num_vlan_tags;
20644 uint8_t unused_1[4];
20645 } __attribute__((packed));
20647 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
20648 struct hwrm_cfa_l2_set_rx_mask_output {
20649 /* The specific error status for the command. */
20650 uint16_t error_code;
20651 /* The HWRM command request type. */
20653 /* The sequence ID from the original command. */
20655 /* The length of the response data in number of bytes. */
20657 uint8_t unused_0[7];
20659 * This field is used in Output records to indicate that the output
20660 * is completely written to RAM. This field should be read as '1'
20661 * to indicate that the output has been completely written.
20662 * When writing a command completion or response to an internal processor,
20663 * the order of writes has to be such that this field is written last.
20666 } __attribute__((packed));
20668 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
20669 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
20671 * command specific error codes that goes to
20672 * the cmd_err field in Common HWRM Error Response.
20675 /* Unknown error */
20676 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
20678 /* Unable to complete operation due to conflict with Ntuple Filter */
20679 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
20681 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
20682 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
20683 uint8_t unused_0[7];
20684 } __attribute__((packed));
20686 /*******************************
20687 * hwrm_cfa_vlan_antispoof_cfg *
20688 *******************************/
20691 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
20692 struct hwrm_cfa_vlan_antispoof_cfg_input {
20693 /* The HWRM command request type. */
20696 * The completion ring to send the completion event on. This should
20697 * be the NQ ID returned from the `nq_alloc` HWRM command.
20699 uint16_t cmpl_ring;
20701 * The sequence ID is used by the driver for tracking multiple
20702 * commands. This ID is treated as opaque data by the firmware and
20703 * the value is returned in the `hwrm_resp_hdr` upon completion.
20707 * The target ID of the command:
20708 * * 0x0-0xFFF8 - The function ID
20709 * * 0xFFF8-0xFFFE - Reserved for internal processors
20712 uint16_t target_id;
20714 * A physical address pointer pointing to a host buffer that the
20715 * command's response data will be written. This can be either a host
20716 * physical address (HPA) or a guest physical address (GPA) and must
20717 * point to a physically contiguous block of memory.
20719 uint64_t resp_addr;
20721 * Function ID of the function that is being configured.
20722 * Only valid for a VF FID configured by the PF.
20725 uint8_t unused_0[2];
20726 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
20727 uint32_t num_vlan_entries;
20729 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
20730 * antispoof table. Each table entry contains the 16-bit TPID
20731 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
20732 * all in network order to match hwrm_cfa_l2_set_rx_mask.
20733 * For an individual VLAN entry, the mask value should be 0xfff
20734 * for the 12-bit VLAN ID.
20736 uint64_t vlan_tag_mask_tbl_addr;
20737 } __attribute__((packed));
20739 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
20740 struct hwrm_cfa_vlan_antispoof_cfg_output {
20741 /* The specific error status for the command. */
20742 uint16_t error_code;
20743 /* The HWRM command request type. */
20745 /* The sequence ID from the original command. */
20747 /* The length of the response data in number of bytes. */
20749 uint8_t unused_0[7];
20751 * This field is used in Output records to indicate that the output
20752 * is completely written to RAM. This field should be read as '1'
20753 * to indicate that the output has been completely written.
20754 * When writing a command completion or response to an internal processor,
20755 * the order of writes has to be such that this field is written last.
20758 } __attribute__((packed));
20760 /********************************
20761 * hwrm_cfa_vlan_antispoof_qcfg *
20762 ********************************/
20765 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
20766 struct hwrm_cfa_vlan_antispoof_qcfg_input {
20767 /* The HWRM command request type. */
20770 * The completion ring to send the completion event on. This should
20771 * be the NQ ID returned from the `nq_alloc` HWRM command.
20773 uint16_t cmpl_ring;
20775 * The sequence ID is used by the driver for tracking multiple
20776 * commands. This ID is treated as opaque data by the firmware and
20777 * the value is returned in the `hwrm_resp_hdr` upon completion.
20781 * The target ID of the command:
20782 * * 0x0-0xFFF8 - The function ID
20783 * * 0xFFF8-0xFFFE - Reserved for internal processors
20786 uint16_t target_id;
20788 * A physical address pointer pointing to a host buffer that the
20789 * command's response data will be written. This can be either a host
20790 * physical address (HPA) or a guest physical address (GPA) and must
20791 * point to a physically contiguous block of memory.
20793 uint64_t resp_addr;
20795 * Function ID of the function that is being queried.
20796 * Only valid for a VF FID queried by the PF.
20799 uint8_t unused_0[2];
20801 * Maximum number of VLAN entries the firmware is allowed to DMA
20802 * to vlan_tag_mask_tbl.
20804 uint32_t max_vlan_entries;
20806 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
20807 * antispoof table to which firmware will DMA to. Each table
20808 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
20809 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
20810 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
20811 * the mask value should be 0xfff for the 12-bit VLAN ID.
20813 uint64_t vlan_tag_mask_tbl_addr;
20814 } __attribute__((packed));
20816 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
20817 struct hwrm_cfa_vlan_antispoof_qcfg_output {
20818 /* The specific error status for the command. */
20819 uint16_t error_code;
20820 /* The HWRM command request type. */
20822 /* The sequence ID from the original command. */
20824 /* The length of the response data in number of bytes. */
20826 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
20827 uint32_t num_vlan_entries;
20828 uint8_t unused_0[3];
20830 * This field is used in Output records to indicate that the output
20831 * is completely written to RAM. This field should be read as '1'
20832 * to indicate that the output has been completely written.
20833 * When writing a command completion or response to an internal processor,
20834 * the order of writes has to be such that this field is written last.
20837 } __attribute__((packed));
20839 /********************************
20840 * hwrm_cfa_tunnel_filter_alloc *
20841 ********************************/
20844 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
20845 struct hwrm_cfa_tunnel_filter_alloc_input {
20846 /* The HWRM command request type. */
20849 * The completion ring to send the completion event on. This should
20850 * be the NQ ID returned from the `nq_alloc` HWRM command.
20852 uint16_t cmpl_ring;
20854 * The sequence ID is used by the driver for tracking multiple
20855 * commands. This ID is treated as opaque data by the firmware and
20856 * the value is returned in the `hwrm_resp_hdr` upon completion.
20860 * The target ID of the command:
20861 * * 0x0-0xFFF8 - The function ID
20862 * * 0xFFF8-0xFFFE - Reserved for internal processors
20865 uint16_t target_id;
20867 * A physical address pointer pointing to a host buffer that the
20868 * command's response data will be written. This can be either a host
20869 * physical address (HPA) or a guest physical address (GPA) and must
20870 * point to a physically contiguous block of memory.
20872 uint64_t resp_addr;
20874 /* Setting of this flag indicates the applicability to the loopback path. */
20875 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
20879 * This bit must be '1' for the l2_filter_id field to be
20882 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
20885 * This bit must be '1' for the l2_addr field to be
20888 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
20891 * This bit must be '1' for the l2_ivlan field to be
20894 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
20897 * This bit must be '1' for the l3_addr field to be
20900 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
20903 * This bit must be '1' for the l3_addr_type field to be
20906 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
20909 * This bit must be '1' for the t_l3_addr_type field to be
20912 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
20915 * This bit must be '1' for the t_l3_addr field to be
20918 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
20921 * This bit must be '1' for the tunnel_type field to be
20924 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
20927 * This bit must be '1' for the vni field to be
20930 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
20933 * This bit must be '1' for the dst_vnic_id field to be
20936 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
20939 * This bit must be '1' for the mirror_vnic_id field to be
20942 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
20945 * This value identifies a set of CFA data structures used for an L2
20948 uint64_t l2_filter_id;
20950 * This value sets the match value for the inner L2
20952 * Destination MAC address for RX path.
20953 * Source MAC address for TX path.
20955 uint8_t l2_addr[6];
20957 * This value sets VLAN ID value for inner VLAN.
20958 * Only 12-bits of VLAN ID are used in setting the filter.
20962 * The value of inner destination IP address to be used in filtering.
20963 * For IPv4, first four bytes represent the IP address.
20965 uint32_t l3_addr[4];
20967 * The value of tunnel destination IP address to be used in filtering.
20968 * For IPv4, first four bytes represent the IP address.
20970 uint32_t t_l3_addr[4];
20972 * This value indicates the type of inner IP address.
20975 * All others are invalid.
20977 uint8_t l3_addr_type;
20979 * This value indicates the type of tunnel IP address.
20982 * All others are invalid.
20984 uint8_t t_l3_addr_type;
20986 uint8_t tunnel_type;
20988 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
20990 /* Virtual eXtensible Local Area Network (VXLAN) */
20991 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20993 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
20994 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
20996 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
20997 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21000 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21002 /* Generic Network Virtualization Encapsulation (Geneve) */
21003 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21005 /* Multi-Protocol Lable Switching (MPLS) */
21006 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21008 /* Stateless Transport Tunnel (STT) */
21009 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21011 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21012 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21014 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21015 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21017 /* Any tunneled traffic */
21018 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21020 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21021 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21023 * tunnel_flags allows the user to indicate the tunnel tag detection
21024 * for the tunnel type specified in tunnel_type.
21026 uint8_t tunnel_flags;
21028 * If the tunnel_type is geneve, then this bit indicates if we
21029 * need to match the geneve OAM packet.
21030 * If the tunnel_type is nvgre or gre, then this bit indicates if
21031 * we need to detect checksum present bit in geneve header.
21032 * If the tunnel_type is mpls, then this bit indicates if we need
21033 * to match mpls packet with explicit IPV4/IPV6 null header.
21035 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
21038 * If the tunnel_type is geneve, then this bit indicates if we
21039 * need to detect the critical option bit set in the oam packet.
21040 * If the tunnel_type is nvgre or gre, then this bit indicates
21041 * if we need to match nvgre packets with key present bit set in
21043 * If the tunnel_type is mpls, then this bit indicates if we
21044 * need to match mpls packet with S bit from inner/second label.
21046 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
21049 * If the tunnel_type is geneve, then this bit indicates if we
21050 * need to match geneve packet with extended header bit set in
21052 * If the tunnel_type is nvgre or gre, then this bit indicates
21053 * if we need to match nvgre packets with sequence number
21054 * present bit set in gre header.
21055 * If the tunnel_type is mpls, then this bit indicates if we
21056 * need to match mpls packet with S bit from out/first label.
21058 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
21061 * Virtual Network Identifier (VNI). Only valid with
21062 * tunnel_types VXLAN, NVGRE, and Geneve.
21063 * Only lower 24-bits of VNI field are used
21064 * in setting up the filter.
21067 /* Logical VNIC ID of the destination VNIC. */
21068 uint32_t dst_vnic_id;
21070 * Logical VNIC ID of the VNIC where traffic is
21073 uint32_t mirror_vnic_id;
21074 } __attribute__((packed));
21076 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
21077 struct hwrm_cfa_tunnel_filter_alloc_output {
21078 /* The specific error status for the command. */
21079 uint16_t error_code;
21080 /* The HWRM command request type. */
21082 /* The sequence ID from the original command. */
21084 /* The length of the response data in number of bytes. */
21086 /* This value is an opaque id into CFA data structures. */
21087 uint64_t tunnel_filter_id;
21089 * This is the ID of the flow associated with this
21091 * This value shall be used to match and associate the
21092 * flow identifier returned in completion records.
21093 * A value of 0xFFFFFFFF shall indicate no flow id.
21096 uint8_t unused_0[3];
21098 * This field is used in Output records to indicate that the output
21099 * is completely written to RAM. This field should be read as '1'
21100 * to indicate that the output has been completely written.
21101 * When writing a command completion or response to an internal processor,
21102 * the order of writes has to be such that this field is written last.
21105 } __attribute__((packed));
21107 /*******************************
21108 * hwrm_cfa_tunnel_filter_free *
21109 *******************************/
21112 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
21113 struct hwrm_cfa_tunnel_filter_free_input {
21114 /* The HWRM command request type. */
21117 * The completion ring to send the completion event on. This should
21118 * be the NQ ID returned from the `nq_alloc` HWRM command.
21120 uint16_t cmpl_ring;
21122 * The sequence ID is used by the driver for tracking multiple
21123 * commands. This ID is treated as opaque data by the firmware and
21124 * the value is returned in the `hwrm_resp_hdr` upon completion.
21128 * The target ID of the command:
21129 * * 0x0-0xFFF8 - The function ID
21130 * * 0xFFF8-0xFFFE - Reserved for internal processors
21133 uint16_t target_id;
21135 * A physical address pointer pointing to a host buffer that the
21136 * command's response data will be written. This can be either a host
21137 * physical address (HPA) or a guest physical address (GPA) and must
21138 * point to a physically contiguous block of memory.
21140 uint64_t resp_addr;
21141 /* This value is an opaque id into CFA data structures. */
21142 uint64_t tunnel_filter_id;
21143 } __attribute__((packed));
21145 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
21146 struct hwrm_cfa_tunnel_filter_free_output {
21147 /* The specific error status for the command. */
21148 uint16_t error_code;
21149 /* The HWRM command request type. */
21151 /* The sequence ID from the original command. */
21153 /* The length of the response data in number of bytes. */
21155 uint8_t unused_0[7];
21157 * This field is used in Output records to indicate that the output
21158 * is completely written to RAM. This field should be read as '1'
21159 * to indicate that the output has been completely written.
21160 * When writing a command completion or response to an internal processor,
21161 * the order of writes has to be such that this field is written last.
21164 } __attribute__((packed));
21166 /***************************************
21167 * hwrm_cfa_redirect_tunnel_type_alloc *
21168 ***************************************/
21171 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
21172 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
21173 /* The HWRM command request type. */
21176 * The completion ring to send the completion event on. This should
21177 * be the NQ ID returned from the `nq_alloc` HWRM command.
21179 uint16_t cmpl_ring;
21181 * The sequence ID is used by the driver for tracking multiple
21182 * commands. This ID is treated as opaque data by the firmware and
21183 * the value is returned in the `hwrm_resp_hdr` upon completion.
21187 * The target ID of the command:
21188 * * 0x0-0xFFF8 - The function ID
21189 * * 0xFFF8-0xFFFE - Reserved for internal processors
21192 uint16_t target_id;
21194 * A physical address pointer pointing to a host buffer that the
21195 * command's response data will be written. This can be either a host
21196 * physical address (HPA) or a guest physical address (GPA) and must
21197 * point to a physically contiguous block of memory.
21199 uint64_t resp_addr;
21200 /* The destination function id, to whom the traffic is redirected. */
21203 uint8_t tunnel_type;
21205 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21207 /* Virtual eXtensible Local Area Network (VXLAN) */
21208 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21210 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21211 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21213 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21214 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21217 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21219 /* Generic Network Virtualization Encapsulation (Geneve) */
21220 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21222 /* Multi-Protocol Lable Switching (MPLS) */
21223 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21225 /* Stateless Transport Tunnel (STT) */
21226 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
21228 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21229 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21231 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21232 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21234 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21235 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21237 /* Any tunneled traffic */
21238 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21240 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21241 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21242 /* Tunnel alloc flags. */
21244 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
21245 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
21247 uint8_t unused_0[4];
21248 } __attribute__((packed));
21250 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
21251 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
21252 /* The specific error status for the command. */
21253 uint16_t error_code;
21254 /* The HWRM command request type. */
21256 /* The sequence ID from the original command. */
21258 /* The length of the response data in number of bytes. */
21260 uint8_t unused_0[7];
21262 * This field is used in Output records to indicate that the output
21263 * is completely written to RAM. This field should be read as '1'
21264 * to indicate that the output has been completely written.
21265 * When writing a command completion or response to an internal processor,
21266 * the order of writes has to be such that this field is written last.
21269 } __attribute__((packed));
21271 /**************************************
21272 * hwrm_cfa_redirect_tunnel_type_free *
21273 **************************************/
21276 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
21277 struct hwrm_cfa_redirect_tunnel_type_free_input {
21278 /* The HWRM command request type. */
21281 * The completion ring to send the completion event on. This should
21282 * be the NQ ID returned from the `nq_alloc` HWRM command.
21284 uint16_t cmpl_ring;
21286 * The sequence ID is used by the driver for tracking multiple
21287 * commands. This ID is treated as opaque data by the firmware and
21288 * the value is returned in the `hwrm_resp_hdr` upon completion.
21292 * The target ID of the command:
21293 * * 0x0-0xFFF8 - The function ID
21294 * * 0xFFF8-0xFFFE - Reserved for internal processors
21297 uint16_t target_id;
21299 * A physical address pointer pointing to a host buffer that the
21300 * command's response data will be written. This can be either a host
21301 * physical address (HPA) or a guest physical address (GPA) and must
21302 * point to a physically contiguous block of memory.
21304 uint64_t resp_addr;
21305 /* The destination function id, to whom the traffic is redirected. */
21308 uint8_t tunnel_type;
21310 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
21312 /* Virtual eXtensible Local Area Network (VXLAN) */
21313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
21315 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21316 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
21318 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21319 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
21322 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
21324 /* Generic Network Virtualization Encapsulation (Geneve) */
21325 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
21327 /* Multi-Protocol Lable Switching (MPLS) */
21328 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
21330 /* Stateless Transport Tunnel (STT) */
21331 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
21333 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21334 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
21336 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21337 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21339 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21340 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21342 /* Any tunneled traffic */
21343 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21345 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
21346 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
21347 uint8_t unused_0[5];
21348 } __attribute__((packed));
21350 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
21351 struct hwrm_cfa_redirect_tunnel_type_free_output {
21352 /* The specific error status for the command. */
21353 uint16_t error_code;
21354 /* The HWRM command request type. */
21356 /* The sequence ID from the original command. */
21358 /* The length of the response data in number of bytes. */
21360 uint8_t unused_0[7];
21362 * This field is used in Output records to indicate that the output
21363 * is completely written to RAM. This field should be read as '1'
21364 * to indicate that the output has been completely written.
21365 * When writing a command completion or response to an internal processor,
21366 * the order of writes has to be such that this field is written last.
21369 } __attribute__((packed));
21371 /**************************************
21372 * hwrm_cfa_redirect_tunnel_type_info *
21373 **************************************/
21376 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
21377 struct hwrm_cfa_redirect_tunnel_type_info_input {
21378 /* The HWRM command request type. */
21381 * The completion ring to send the completion event on. This should
21382 * be the NQ ID returned from the `nq_alloc` HWRM command.
21384 uint16_t cmpl_ring;
21386 * The sequence ID is used by the driver for tracking multiple
21387 * commands. This ID is treated as opaque data by the firmware and
21388 * the value is returned in the `hwrm_resp_hdr` upon completion.
21392 * The target ID of the command:
21393 * * 0x0-0xFFF8 - The function ID
21394 * * 0xFFF8-0xFFFE - Reserved for internal processors
21397 uint16_t target_id;
21399 * A physical address pointer pointing to a host buffer that the
21400 * command's response data will be written. This can be either a host
21401 * physical address (HPA) or a guest physical address (GPA) and must
21402 * point to a physically contiguous block of memory.
21404 uint64_t resp_addr;
21405 /* The source function id. */
21408 uint8_t tunnel_type;
21410 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
21412 /* Virtual eXtensible Local Area Network (VXLAN) */
21413 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
21415 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21416 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
21418 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21419 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
21422 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
21424 /* Generic Network Virtualization Encapsulation (Geneve) */
21425 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
21427 /* Multi-Protocol Lable Switching (MPLS) */
21428 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
21430 /* Stateless Transport Tunnel (STT) */
21431 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
21433 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21434 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
21436 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21437 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21439 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21440 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21442 /* Any tunneled traffic */
21443 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21445 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
21446 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
21447 uint8_t unused_0[5];
21448 } __attribute__((packed));
21450 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
21451 struct hwrm_cfa_redirect_tunnel_type_info_output {
21452 /* The specific error status for the command. */
21453 uint16_t error_code;
21454 /* The HWRM command request type. */
21456 /* The sequence ID from the original command. */
21458 /* The length of the response data in number of bytes. */
21460 /* The destination function id, to whom the traffic is redirected. */
21462 uint8_t unused_0[5];
21464 * This field is used in Output records to indicate that the output
21465 * is completely written to RAM. This field should be read as '1'
21466 * to indicate that the output has been completely written.
21467 * When writing a command completion or response to an internal processor,
21468 * the order of writes has to be such that this field is written last.
21471 } __attribute__((packed));
21473 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
21474 struct hwrm_vxlan_ipv4_hdr {
21475 /* IPv4 version and header length. */
21477 /* IPv4 header length */
21478 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
21479 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
21481 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
21482 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
21483 /* IPv4 type of service. */
21485 /* IPv4 identification. */
21487 /* IPv4 flags and offset. */
21488 uint16_t flags_frag_offset;
21491 /* IPv4 protocol. */
21493 /* IPv4 source address. */
21494 uint32_t src_ip_addr;
21495 /* IPv4 destination address. */
21496 uint32_t dest_ip_addr;
21497 } __attribute__((packed));
21499 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
21500 struct hwrm_vxlan_ipv6_hdr {
21501 /* IPv6 version, traffic class and flow label. */
21502 uint32_t ver_tc_flow_label;
21503 /* IPv6 version shift */
21504 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
21506 /* IPv6 version mask */
21507 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
21508 UINT32_C(0xf0000000)
21509 /* IPv6 TC shift */
21510 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
21513 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
21514 UINT32_C(0xff00000)
21515 /* IPv6 flow label shift */
21516 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
21518 /* IPv6 flow label mask */
21519 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
21521 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
21522 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
21523 /* IPv6 payload length. */
21524 uint16_t payload_len;
21525 /* IPv6 next header. */
21529 /* IPv6 source address. */
21530 uint32_t src_ip_addr[4];
21531 /* IPv6 destination address. */
21532 uint32_t dest_ip_addr[4];
21533 } __attribute__((packed));
21535 /* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
21536 struct hwrm_cfa_encap_data_vxlan {
21537 /* Source MAC address. */
21538 uint8_t src_mac_addr[6];
21541 /* Destination MAC address. */
21542 uint8_t dst_mac_addr[6];
21543 /* Number of VLAN tags. */
21544 uint8_t num_vlan_tags;
21547 /* Outer VLAN TPID. */
21548 uint16_t ovlan_tpid;
21549 /* Outer VLAN TCI. */
21550 uint16_t ovlan_tci;
21551 /* Inner VLAN TPID. */
21552 uint16_t ivlan_tpid;
21553 /* Inner VLAN TCI. */
21554 uint16_t ivlan_tci;
21555 /* L3 header fields. */
21557 /* IP version mask. */
21558 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
21559 /* IP version 4. */
21560 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
21561 /* IP version 6. */
21562 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
21563 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
21564 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
21565 /* UDP source port. */
21567 /* UDP destination port. */
21569 /* VXLAN Network Identifier. */
21571 } __attribute__((packed));
21573 /*******************************
21574 * hwrm_cfa_encap_record_alloc *
21575 *******************************/
21578 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
21579 struct hwrm_cfa_encap_record_alloc_input {
21580 /* The HWRM command request type. */
21583 * The completion ring to send the completion event on. This should
21584 * be the NQ ID returned from the `nq_alloc` HWRM command.
21586 uint16_t cmpl_ring;
21588 * The sequence ID is used by the driver for tracking multiple
21589 * commands. This ID is treated as opaque data by the firmware and
21590 * the value is returned in the `hwrm_resp_hdr` upon completion.
21594 * The target ID of the command:
21595 * * 0x0-0xFFF8 - The function ID
21596 * * 0xFFF8-0xFFFE - Reserved for internal processors
21599 uint16_t target_id;
21601 * A physical address pointer pointing to a host buffer that the
21602 * command's response data will be written. This can be either a host
21603 * physical address (HPA) or a guest physical address (GPA) and must
21604 * point to a physically contiguous block of memory.
21606 uint64_t resp_addr;
21608 /* Setting of this flag indicates the applicability to the loopback path. */
21609 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
21611 /* Encapsulation Type. */
21612 uint8_t encap_type;
21613 /* Virtual eXtensible Local Area Network (VXLAN) */
21614 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
21616 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21617 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
21619 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
21620 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
21623 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
21625 /* Generic Network Virtualization Encapsulation (Geneve) */
21626 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
21628 /* Multi-Protocol Lable Switching (MPLS) */
21629 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
21632 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
21634 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21635 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
21637 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
21638 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE
21639 uint8_t unused_0[3];
21640 /* This value is encap data used for the given encap type. */
21641 uint32_t encap_data[20];
21642 } __attribute__((packed));
21644 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
21645 struct hwrm_cfa_encap_record_alloc_output {
21646 /* The specific error status for the command. */
21647 uint16_t error_code;
21648 /* The HWRM command request type. */
21650 /* The sequence ID from the original command. */
21652 /* The length of the response data in number of bytes. */
21654 /* This value is an opaque id into CFA data structures. */
21655 uint32_t encap_record_id;
21656 uint8_t unused_0[3];
21658 * This field is used in Output records to indicate that the output
21659 * is completely written to RAM. This field should be read as '1'
21660 * to indicate that the output has been completely written.
21661 * When writing a command completion or response to an internal processor,
21662 * the order of writes has to be such that this field is written last.
21665 } __attribute__((packed));
21667 /******************************
21668 * hwrm_cfa_encap_record_free *
21669 ******************************/
21672 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
21673 struct hwrm_cfa_encap_record_free_input {
21674 /* The HWRM command request type. */
21677 * The completion ring to send the completion event on. This should
21678 * be the NQ ID returned from the `nq_alloc` HWRM command.
21680 uint16_t cmpl_ring;
21682 * The sequence ID is used by the driver for tracking multiple
21683 * commands. This ID is treated as opaque data by the firmware and
21684 * the value is returned in the `hwrm_resp_hdr` upon completion.
21688 * The target ID of the command:
21689 * * 0x0-0xFFF8 - The function ID
21690 * * 0xFFF8-0xFFFE - Reserved for internal processors
21693 uint16_t target_id;
21695 * A physical address pointer pointing to a host buffer that the
21696 * command's response data will be written. This can be either a host
21697 * physical address (HPA) or a guest physical address (GPA) and must
21698 * point to a physically contiguous block of memory.
21700 uint64_t resp_addr;
21701 /* This value is an opaque id into CFA data structures. */
21702 uint32_t encap_record_id;
21703 uint8_t unused_0[4];
21704 } __attribute__((packed));
21706 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
21707 struct hwrm_cfa_encap_record_free_output {
21708 /* The specific error status for the command. */
21709 uint16_t error_code;
21710 /* The HWRM command request type. */
21712 /* The sequence ID from the original command. */
21714 /* The length of the response data in number of bytes. */
21716 uint8_t unused_0[7];
21718 * This field is used in Output records to indicate that the output
21719 * is completely written to RAM. This field should be read as '1'
21720 * to indicate that the output has been completely written.
21721 * When writing a command completion or response to an internal processor,
21722 * the order of writes has to be such that this field is written last.
21725 } __attribute__((packed));
21727 /********************************
21728 * hwrm_cfa_ntuple_filter_alloc *
21729 ********************************/
21732 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
21733 struct hwrm_cfa_ntuple_filter_alloc_input {
21734 /* The HWRM command request type. */
21737 * The completion ring to send the completion event on. This should
21738 * be the NQ ID returned from the `nq_alloc` HWRM command.
21740 uint16_t cmpl_ring;
21742 * The sequence ID is used by the driver for tracking multiple
21743 * commands. This ID is treated as opaque data by the firmware and
21744 * the value is returned in the `hwrm_resp_hdr` upon completion.
21748 * The target ID of the command:
21749 * * 0x0-0xFFF8 - The function ID
21750 * * 0xFFF8-0xFFFE - Reserved for internal processors
21753 uint16_t target_id;
21755 * A physical address pointer pointing to a host buffer that the
21756 * command's response data will be written. This can be either a host
21757 * physical address (HPA) or a guest physical address (GPA) and must
21758 * point to a physically contiguous block of memory.
21760 uint64_t resp_addr;
21762 /* Setting of this flag indicates the applicability to the loopback path. */
21763 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
21766 * Setting of this flag indicates drop action. If this flag is not set,
21767 * then it should be considered accept action.
21769 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
21772 * Setting of this flag indicates that a meter is expected to be attached
21773 * to this flow. This hint can be used when choosing the action record
21774 * format required for the flow.
21776 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
21780 * This bit must be '1' for the l2_filter_id field to be
21783 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
21786 * This bit must be '1' for the ethertype field to be
21789 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
21792 * This bit must be '1' for the tunnel_type field to be
21795 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
21798 * This bit must be '1' for the src_macaddr field to be
21801 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
21804 * This bit must be '1' for the ipaddr_type field to be
21807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
21810 * This bit must be '1' for the src_ipaddr field to be
21813 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
21816 * This bit must be '1' for the src_ipaddr_mask field to be
21819 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
21822 * This bit must be '1' for the dst_ipaddr field to be
21825 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
21828 * This bit must be '1' for the dst_ipaddr_mask field to be
21831 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
21834 * This bit must be '1' for the ip_protocol field to be
21837 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
21840 * This bit must be '1' for the src_port field to be
21843 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
21846 * This bit must be '1' for the src_port_mask field to be
21849 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
21852 * This bit must be '1' for the dst_port field to be
21855 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
21858 * This bit must be '1' for the dst_port_mask field to be
21861 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
21864 * This bit must be '1' for the pri_hint field to be
21867 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
21870 * This bit must be '1' for the ntuple_filter_id field to be
21873 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
21876 * This bit must be '1' for the dst_id field to be
21879 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
21882 * This bit must be '1' for the mirror_vnic_id field to be
21885 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
21888 * This bit must be '1' for the dst_macaddr field to be
21891 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
21894 * This value identifies a set of CFA data structures used for an L2
21897 uint64_t l2_filter_id;
21899 * This value indicates the source MAC address in
21900 * the Ethernet header.
21902 uint8_t src_macaddr[6];
21903 /* This value indicates the ethertype in the Ethernet header. */
21904 uint16_t ethertype;
21906 * This value indicates the type of IP address.
21909 * All others are invalid.
21911 uint8_t ip_addr_type;
21913 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
21916 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
21919 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
21921 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
21922 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
21924 * The value of protocol filed in IP header.
21925 * Applies to UDP and TCP traffic.
21929 uint8_t ip_protocol;
21931 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
21934 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
21937 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
21939 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
21940 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
21942 * If set, this value shall represent the
21943 * Logical VNIC ID of the destination VNIC for the RX
21944 * path and network port id of the destination port for
21949 * Logical VNIC ID of the VNIC where traffic is
21952 uint16_t mirror_vnic_id;
21954 * This value indicates the tunnel type for this filter.
21955 * If this field is not specified, then the filter shall
21956 * apply to both non-tunneled and tunneled packets.
21957 * If this field conflicts with the tunnel_type specified
21958 * in the l2_filter_id, then the HWRM shall return an
21959 * error for this command.
21961 uint8_t tunnel_type;
21963 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21965 /* Virtual eXtensible Local Area Network (VXLAN) */
21966 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21968 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21969 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21971 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21972 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21975 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21977 /* Generic Network Virtualization Encapsulation (Geneve) */
21978 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21980 /* Multi-Protocol Lable Switching (MPLS) */
21981 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21983 /* Stateless Transport Tunnel (STT) */
21984 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21986 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21987 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21989 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21990 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21992 /* Any tunneled traffic */
21993 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21995 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21996 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21998 * This hint is provided to help in placing
21999 * the filter in the filter table.
22002 /* No preference */
22003 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
22005 /* Above the given filter */
22006 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
22008 /* Below the given filter */
22009 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
22011 /* As high as possible */
22012 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
22014 /* As low as possible */
22015 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
22017 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
22018 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
22020 * The value of source IP address to be used in filtering.
22021 * For IPv4, first four bytes represent the IP address.
22023 uint32_t src_ipaddr[4];
22025 * The value of source IP address mask to be used in
22027 * For IPv4, first four bytes represent the IP address mask.
22029 uint32_t src_ipaddr_mask[4];
22031 * The value of destination IP address to be used in filtering.
22032 * For IPv4, first four bytes represent the IP address.
22034 uint32_t dst_ipaddr[4];
22036 * The value of destination IP address mask to be used in
22038 * For IPv4, first four bytes represent the IP address mask.
22040 uint32_t dst_ipaddr_mask[4];
22042 * The value of source port to be used in filtering.
22043 * Applies to UDP and TCP traffic.
22047 * The value of source port mask to be used in filtering.
22048 * Applies to UDP and TCP traffic.
22050 uint16_t src_port_mask;
22052 * The value of destination port to be used in filtering.
22053 * Applies to UDP and TCP traffic.
22057 * The value of destination port mask to be used in
22059 * Applies to UDP and TCP traffic.
22061 uint16_t dst_port_mask;
22063 * This is the ID of the filter that goes along with
22066 uint64_t ntuple_filter_id_hint;
22067 } __attribute__((packed));
22069 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
22070 struct hwrm_cfa_ntuple_filter_alloc_output {
22071 /* The specific error status for the command. */
22072 uint16_t error_code;
22073 /* The HWRM command request type. */
22075 /* The sequence ID from the original command. */
22077 /* The length of the response data in number of bytes. */
22079 /* This value is an opaque id into CFA data structures. */
22080 uint64_t ntuple_filter_id;
22082 * This is the ID of the flow associated with this
22084 * This value shall be used to match and associate the
22085 * flow identifier returned in completion records.
22086 * A value of 0xFFFFFFFF shall indicate no flow id.
22089 uint8_t unused_0[3];
22091 * This field is used in Output records to indicate that the output
22092 * is completely written to RAM. This field should be read as '1'
22093 * to indicate that the output has been completely written.
22094 * When writing a command completion or response to an internal processor,
22095 * the order of writes has to be such that this field is written last.
22098 } __attribute__((packed));
22100 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
22101 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
22103 * command specific error codes that goes to
22104 * the cmd_err field in Common HWRM Error Response.
22107 /* Unknown error */
22108 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
22110 /* Unable to complete operation due to conflict with Rx Mask VLAN */
22111 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
22113 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
22114 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
22115 uint8_t unused_0[7];
22116 } __attribute__((packed));
22118 /*******************************
22119 * hwrm_cfa_ntuple_filter_free *
22120 *******************************/
22123 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
22124 struct hwrm_cfa_ntuple_filter_free_input {
22125 /* The HWRM command request type. */
22128 * The completion ring to send the completion event on. This should
22129 * be the NQ ID returned from the `nq_alloc` HWRM command.
22131 uint16_t cmpl_ring;
22133 * The sequence ID is used by the driver for tracking multiple
22134 * commands. This ID is treated as opaque data by the firmware and
22135 * the value is returned in the `hwrm_resp_hdr` upon completion.
22139 * The target ID of the command:
22140 * * 0x0-0xFFF8 - The function ID
22141 * * 0xFFF8-0xFFFE - Reserved for internal processors
22144 uint16_t target_id;
22146 * A physical address pointer pointing to a host buffer that the
22147 * command's response data will be written. This can be either a host
22148 * physical address (HPA) or a guest physical address (GPA) and must
22149 * point to a physically contiguous block of memory.
22151 uint64_t resp_addr;
22152 /* This value is an opaque id into CFA data structures. */
22153 uint64_t ntuple_filter_id;
22154 } __attribute__((packed));
22156 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
22157 struct hwrm_cfa_ntuple_filter_free_output {
22158 /* The specific error status for the command. */
22159 uint16_t error_code;
22160 /* The HWRM command request type. */
22162 /* The sequence ID from the original command. */
22164 /* The length of the response data in number of bytes. */
22166 uint8_t unused_0[7];
22168 * This field is used in Output records to indicate that the output
22169 * is completely written to RAM. This field should be read as '1'
22170 * to indicate that the output has been completely written.
22171 * When writing a command completion or response to an internal processor,
22172 * the order of writes has to be such that this field is written last.
22175 } __attribute__((packed));
22177 /******************************
22178 * hwrm_cfa_ntuple_filter_cfg *
22179 ******************************/
22182 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
22183 struct hwrm_cfa_ntuple_filter_cfg_input {
22184 /* The HWRM command request type. */
22187 * The completion ring to send the completion event on. This should
22188 * be the NQ ID returned from the `nq_alloc` HWRM command.
22190 uint16_t cmpl_ring;
22192 * The sequence ID is used by the driver for tracking multiple
22193 * commands. This ID is treated as opaque data by the firmware and
22194 * the value is returned in the `hwrm_resp_hdr` upon completion.
22198 * The target ID of the command:
22199 * * 0x0-0xFFF8 - The function ID
22200 * * 0xFFF8-0xFFFE - Reserved for internal processors
22203 uint16_t target_id;
22205 * A physical address pointer pointing to a host buffer that the
22206 * command's response data will be written. This can be either a host
22207 * physical address (HPA) or a guest physical address (GPA) and must
22208 * point to a physically contiguous block of memory.
22210 uint64_t resp_addr;
22213 * This bit must be '1' for the new_dst_id field to be
22216 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
22219 * This bit must be '1' for the new_mirror_vnic_id field to be
22222 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
22225 * This bit must be '1' for the new_meter_instance_id field to be
22228 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
22230 uint8_t unused_0[4];
22231 /* This value is an opaque id into CFA data structures. */
22232 uint64_t ntuple_filter_id;
22234 * If set, this value shall represent the new
22235 * Logical VNIC ID of the destination VNIC for the RX
22236 * path and new network port id of the destination port for
22239 uint32_t new_dst_id;
22241 * New Logical VNIC ID of the VNIC where traffic is
22244 uint32_t new_mirror_vnic_id;
22246 * New meter to attach to the flow. Specifying the
22247 * invalid instance ID is used to remove any existing
22248 * meter from the flow.
22250 uint16_t new_meter_instance_id;
22252 * A value of 0xfff is considered invalid and implies the
22253 * instance is not configured.
22255 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
22257 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
22258 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
22259 uint8_t unused_1[6];
22260 } __attribute__((packed));
22262 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
22263 struct hwrm_cfa_ntuple_filter_cfg_output {
22264 /* The specific error status for the command. */
22265 uint16_t error_code;
22266 /* The HWRM command request type. */
22268 /* The sequence ID from the original command. */
22270 /* The length of the response data in number of bytes. */
22272 uint8_t unused_0[7];
22274 * This field is used in Output records to indicate that the output
22275 * is completely written to RAM. This field should be read as '1'
22276 * to indicate that the output has been completely written.
22277 * When writing a command completion or response to an internal processor,
22278 * the order of writes has to be such that this field is written last.
22281 } __attribute__((packed));
22283 /**************************
22284 * hwrm_cfa_em_flow_alloc *
22285 **************************/
22288 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
22289 struct hwrm_cfa_em_flow_alloc_input {
22290 /* The HWRM command request type. */
22293 * The completion ring to send the completion event on. This should
22294 * be the NQ ID returned from the `nq_alloc` HWRM command.
22296 uint16_t cmpl_ring;
22298 * The sequence ID is used by the driver for tracking multiple
22299 * commands. This ID is treated as opaque data by the firmware and
22300 * the value is returned in the `hwrm_resp_hdr` upon completion.
22304 * The target ID of the command:
22305 * * 0x0-0xFFF8 - The function ID
22306 * * 0xFFF8-0xFFFE - Reserved for internal processors
22309 uint16_t target_id;
22311 * A physical address pointer pointing to a host buffer that the
22312 * command's response data will be written. This can be either a host
22313 * physical address (HPA) or a guest physical address (GPA) and must
22314 * point to a physically contiguous block of memory.
22316 uint64_t resp_addr;
22319 * Enumeration denoting the RX, TX type of the resource.
22320 * This enumeration is used for resources that are similar for both
22321 * TX and RX paths of the chip.
22323 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
22325 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22327 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22328 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
22329 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
22331 * Setting of this flag indicates enabling of a byte counter for a given
22334 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
22336 * Setting of this flag indicates enabling of a packet counter for a given
22339 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
22340 /* Setting of this flag indicates de-capsulation action for the given flow. */
22341 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
22342 /* Setting of this flag indicates encapsulation action for the given flow. */
22343 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
22345 * Setting of this flag indicates drop action. If this flag is not set,
22346 * then it should be considered accept action.
22348 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
22350 * Setting of this flag indicates that a meter is expected to be attached
22351 * to this flow. This hint can be used when choosing the action record
22352 * format required for the flow.
22354 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
22357 * This bit must be '1' for the l2_filter_id field to be
22360 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
22363 * This bit must be '1' for the tunnel_type field to be
22366 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
22369 * This bit must be '1' for the tunnel_id field to be
22372 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
22375 * This bit must be '1' for the src_macaddr field to be
22378 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
22381 * This bit must be '1' for the dst_macaddr field to be
22384 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
22387 * This bit must be '1' for the ovlan_vid field to be
22390 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
22393 * This bit must be '1' for the ivlan_vid field to be
22396 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
22399 * This bit must be '1' for the ethertype field to be
22402 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
22405 * This bit must be '1' for the src_ipaddr field to be
22408 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
22411 * This bit must be '1' for the dst_ipaddr field to be
22414 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
22417 * This bit must be '1' for the ipaddr_type field to be
22420 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
22423 * This bit must be '1' for the ip_protocol field to be
22426 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
22429 * This bit must be '1' for the src_port field to be
22432 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
22435 * This bit must be '1' for the dst_port field to be
22438 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
22441 * This bit must be '1' for the dst_id field to be
22444 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
22447 * This bit must be '1' for the mirror_vnic_id field to be
22450 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
22453 * This bit must be '1' for the encap_record_id field to be
22456 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
22459 * This bit must be '1' for the meter_instance_id field to be
22462 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
22465 * This value identifies a set of CFA data structures used for an L2
22468 uint64_t l2_filter_id;
22470 uint8_t tunnel_type;
22472 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22474 /* Virtual eXtensible Local Area Network (VXLAN) */
22475 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22477 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22478 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22480 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22481 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22484 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22486 /* Generic Network Virtualization Encapsulation (Geneve) */
22487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22489 /* Multi-Protocol Lable Switching (MPLS) */
22490 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22492 /* Stateless Transport Tunnel (STT) */
22493 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
22495 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22496 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22498 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22499 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22501 /* Any tunneled traffic */
22502 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22504 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22505 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22506 uint8_t unused_0[3];
22508 * Tunnel identifier.
22509 * Virtual Network Identifier (VNI). Only valid with
22510 * tunnel_types VXLAN, NVGRE, and Geneve.
22511 * Only lower 24-bits of VNI field are used
22512 * in setting up the filter.
22514 uint32_t tunnel_id;
22516 * This value indicates the source MAC address in
22517 * the Ethernet header.
22519 uint8_t src_macaddr[6];
22520 /* The meter instance to attach to the flow. */
22521 uint16_t meter_instance_id;
22523 * A value of 0xfff is considered invalid and implies the
22524 * instance is not configured.
22526 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
22528 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
22529 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
22531 * This value indicates the destination MAC address in
22532 * the Ethernet header.
22534 uint8_t dst_macaddr[6];
22536 * This value indicates the VLAN ID of the outer VLAN tag
22537 * in the Ethernet header.
22539 uint16_t ovlan_vid;
22541 * This value indicates the VLAN ID of the inner VLAN tag
22542 * in the Ethernet header.
22544 uint16_t ivlan_vid;
22545 /* This value indicates the ethertype in the Ethernet header. */
22546 uint16_t ethertype;
22548 * This value indicates the type of IP address.
22551 * All others are invalid.
22553 uint8_t ip_addr_type;
22555 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
22557 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
22559 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
22560 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
22561 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
22563 * The value of protocol filed in IP header.
22564 * Applies to UDP and TCP traffic.
22568 uint8_t ip_protocol;
22570 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
22572 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
22574 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
22575 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
22576 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
22577 uint8_t unused_1[2];
22579 * The value of source IP address to be used in filtering.
22580 * For IPv4, first four bytes represent the IP address.
22582 uint32_t src_ipaddr[4];
22584 * big_endian = True
22585 * The value of destination IP address to be used in filtering.
22586 * For IPv4, first four bytes represent the IP address.
22588 uint32_t dst_ipaddr[4];
22590 * The value of source port to be used in filtering.
22591 * Applies to UDP and TCP traffic.
22595 * The value of destination port to be used in filtering.
22596 * Applies to UDP and TCP traffic.
22600 * If set, this value shall represent the
22601 * Logical VNIC ID of the destination VNIC for the RX
22602 * path and network port id of the destination port for
22607 * Logical VNIC ID of the VNIC where traffic is
22610 uint16_t mirror_vnic_id;
22611 /* Logical ID of the encapsulation record. */
22612 uint32_t encap_record_id;
22613 uint8_t unused_2[4];
22614 } __attribute__((packed));
22616 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
22617 struct hwrm_cfa_em_flow_alloc_output {
22618 /* The specific error status for the command. */
22619 uint16_t error_code;
22620 /* The HWRM command request type. */
22622 /* The sequence ID from the original command. */
22624 /* The length of the response data in number of bytes. */
22626 /* This value is an opaque id into CFA data structures. */
22627 uint64_t em_filter_id;
22629 * This is the ID of the flow associated with this
22631 * This value shall be used to match and associate the
22632 * flow identifier returned in completion records.
22633 * A value of 0xFFFFFFFF shall indicate no flow id.
22636 uint8_t unused_0[3];
22638 * This field is used in Output records to indicate that the output
22639 * is completely written to RAM. This field should be read as '1'
22640 * to indicate that the output has been completely written.
22641 * When writing a command completion or response to an internal processor,
22642 * the order of writes has to be such that this field is written last.
22645 } __attribute__((packed));
22647 /*************************
22648 * hwrm_cfa_em_flow_free *
22649 *************************/
22652 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
22653 struct hwrm_cfa_em_flow_free_input {
22654 /* The HWRM command request type. */
22657 * The completion ring to send the completion event on. This should
22658 * be the NQ ID returned from the `nq_alloc` HWRM command.
22660 uint16_t cmpl_ring;
22662 * The sequence ID is used by the driver for tracking multiple
22663 * commands. This ID is treated as opaque data by the firmware and
22664 * the value is returned in the `hwrm_resp_hdr` upon completion.
22668 * The target ID of the command:
22669 * * 0x0-0xFFF8 - The function ID
22670 * * 0xFFF8-0xFFFE - Reserved for internal processors
22673 uint16_t target_id;
22675 * A physical address pointer pointing to a host buffer that the
22676 * command's response data will be written. This can be either a host
22677 * physical address (HPA) or a guest physical address (GPA) and must
22678 * point to a physically contiguous block of memory.
22680 uint64_t resp_addr;
22681 /* This value is an opaque id into CFA data structures. */
22682 uint64_t em_filter_id;
22683 } __attribute__((packed));
22685 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
22686 struct hwrm_cfa_em_flow_free_output {
22687 /* The specific error status for the command. */
22688 uint16_t error_code;
22689 /* The HWRM command request type. */
22691 /* The sequence ID from the original command. */
22693 /* The length of the response data in number of bytes. */
22695 uint8_t unused_0[7];
22697 * This field is used in Output records to indicate that the output
22698 * is completely written to RAM. This field should be read as '1'
22699 * to indicate that the output has been completely written.
22700 * When writing a command completion or response to an internal processor,
22701 * the order of writes has to be such that this field is written last.
22704 } __attribute__((packed));
22706 /************************
22707 * hwrm_cfa_em_flow_cfg *
22708 ************************/
22711 /* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
22712 struct hwrm_cfa_em_flow_cfg_input {
22713 /* The HWRM command request type. */
22716 * The completion ring to send the completion event on. This should
22717 * be the NQ ID returned from the `nq_alloc` HWRM command.
22719 uint16_t cmpl_ring;
22721 * The sequence ID is used by the driver for tracking multiple
22722 * commands. This ID is treated as opaque data by the firmware and
22723 * the value is returned in the `hwrm_resp_hdr` upon completion.
22727 * The target ID of the command:
22728 * * 0x0-0xFFF8 - The function ID
22729 * * 0xFFF8-0xFFFE - Reserved for internal processors
22732 uint16_t target_id;
22734 * A physical address pointer pointing to a host buffer that the
22735 * command's response data will be written. This can be either a host
22736 * physical address (HPA) or a guest physical address (GPA) and must
22737 * point to a physically contiguous block of memory.
22739 uint64_t resp_addr;
22742 * This bit must be '1' for the new_dst_id field to be
22745 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \
22748 * This bit must be '1' for the new_mirror_vnic_id field to be
22751 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
22754 * This bit must be '1' for the new_meter_instance_id field to be
22757 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
22759 uint8_t unused_0[4];
22760 /* This value is an opaque id into CFA data structures. */
22761 uint64_t em_filter_id;
22763 * If set, this value shall represent the new
22764 * Logical VNIC ID of the destination VNIC for the RX
22765 * path and network port id of the destination port for
22768 uint32_t new_dst_id;
22770 * New Logical VNIC ID of the VNIC where traffic is
22773 uint32_t new_mirror_vnic_id;
22775 * New meter to attach to the flow. Specifying the
22776 * invalid instance ID is used to remove any existing
22777 * meter from the flow.
22779 uint16_t new_meter_instance_id;
22781 * A value of 0xfff is considered invalid and implies the
22782 * instance is not configured.
22784 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
22786 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
22787 HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
22788 uint8_t unused_1[6];
22789 } __attribute__((packed));
22791 /* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
22792 struct hwrm_cfa_em_flow_cfg_output {
22793 /* The specific error status for the command. */
22794 uint16_t error_code;
22795 /* The HWRM command request type. */
22797 /* The sequence ID from the original command. */
22799 /* The length of the response data in number of bytes. */
22801 uint8_t unused_0[7];
22803 * This field is used in Output records to indicate that the output
22804 * is completely written to RAM. This field should be read as '1'
22805 * to indicate that the output has been completely written.
22806 * When writing a command completion or response to an internal processor,
22807 * the order of writes has to be such that this field is written last.
22810 } __attribute__((packed));
22812 /********************************
22813 * hwrm_cfa_meter_profile_alloc *
22814 ********************************/
22817 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
22818 struct hwrm_cfa_meter_profile_alloc_input {
22819 /* The HWRM command request type. */
22822 * The completion ring to send the completion event on. This should
22823 * be the NQ ID returned from the `nq_alloc` HWRM command.
22825 uint16_t cmpl_ring;
22827 * The sequence ID is used by the driver for tracking multiple
22828 * commands. This ID is treated as opaque data by the firmware and
22829 * the value is returned in the `hwrm_resp_hdr` upon completion.
22833 * The target ID of the command:
22834 * * 0x0-0xFFF8 - The function ID
22835 * * 0xFFF8-0xFFFE - Reserved for internal processors
22838 uint16_t target_id;
22840 * A physical address pointer pointing to a host buffer that the
22841 * command's response data will be written. This can be either a host
22842 * physical address (HPA) or a guest physical address (GPA) and must
22843 * point to a physically contiguous block of memory.
22845 uint64_t resp_addr;
22848 * Enumeration denoting the RX, TX type of the resource.
22849 * This enumeration is used for resources that are similar for both
22850 * TX and RX paths of the chip.
22852 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
22854 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
22857 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
22859 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
22860 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
22861 /* The meter algorithm type. */
22862 uint8_t meter_type;
22863 /* RFC 2697 (srTCM) */
22864 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
22866 /* RFC 2698 (trTCM) */
22867 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
22869 /* RFC 4115 (trTCM) */
22870 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
22872 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
22873 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
22875 * This field is reserved for the future use.
22876 * It shall be set to 0.
22878 uint16_t reserved1;
22880 * This field is reserved for the future use.
22881 * It shall be set to 0.
22883 uint32_t reserved2;
22884 /* A meter rate specified in bytes-per-second. */
22885 uint32_t commit_rate;
22886 /* The bandwidth value. */
22887 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
22888 UINT32_C(0xfffffff)
22889 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
22891 /* The granularity of the value (bits or bytes). */
22892 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
22893 UINT32_C(0x10000000)
22894 /* Value is in bits. */
22895 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
22896 (UINT32_C(0x0) << 28)
22897 /* Value is in bytes. */
22898 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
22899 (UINT32_C(0x1) << 28)
22900 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
22901 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
22902 /* bw_value_unit is 3 b */
22903 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
22904 UINT32_C(0xe0000000)
22905 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
22907 /* Value is in Mb or MB (base 10). */
22908 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
22909 (UINT32_C(0x0) << 29)
22910 /* Value is in Kb or KB (base 10). */
22911 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
22912 (UINT32_C(0x2) << 29)
22913 /* Value is in bits or bytes. */
22914 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
22915 (UINT32_C(0x4) << 29)
22916 /* Value is in Gb or GB (base 10). */
22917 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
22918 (UINT32_C(0x6) << 29)
22919 /* Value is in 1/100th of a percentage of total bandwidth. */
22920 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
22921 (UINT32_C(0x1) << 29)
22923 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
22924 (UINT32_C(0x7) << 29)
22925 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
22926 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
22927 /* A meter burst size specified in bytes. */
22928 uint32_t commit_burst;
22929 /* The bandwidth value. */
22930 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
22931 UINT32_C(0xfffffff)
22932 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
22934 /* The granularity of the value (bits or bytes). */
22935 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
22936 UINT32_C(0x10000000)
22937 /* Value is in bits. */
22938 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
22939 (UINT32_C(0x0) << 28)
22940 /* Value is in bytes. */
22941 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
22942 (UINT32_C(0x1) << 28)
22943 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
22944 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
22945 /* bw_value_unit is 3 b */
22946 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
22947 UINT32_C(0xe0000000)
22948 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
22950 /* Value is in Mb or MB (base 10). */
22951 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
22952 (UINT32_C(0x0) << 29)
22953 /* Value is in Kb or KB (base 10). */
22954 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
22955 (UINT32_C(0x2) << 29)
22956 /* Value is in bits or bytes. */
22957 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
22958 (UINT32_C(0x4) << 29)
22959 /* Value is in Gb or GB (base 10). */
22960 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
22961 (UINT32_C(0x6) << 29)
22962 /* Value is in 1/100th of a percentage of total bandwidth. */
22963 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
22964 (UINT32_C(0x1) << 29)
22966 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
22967 (UINT32_C(0x7) << 29)
22968 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
22969 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
22970 /* A meter rate specified in bytes-per-second. */
22971 uint32_t excess_peak_rate;
22972 /* The bandwidth value. */
22973 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
22974 UINT32_C(0xfffffff)
22975 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
22977 /* The granularity of the value (bits or bytes). */
22978 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
22979 UINT32_C(0x10000000)
22980 /* Value is in bits. */
22981 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
22982 (UINT32_C(0x0) << 28)
22983 /* Value is in bytes. */
22984 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
22985 (UINT32_C(0x1) << 28)
22986 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
22987 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
22988 /* bw_value_unit is 3 b */
22989 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
22990 UINT32_C(0xe0000000)
22991 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
22993 /* Value is in Mb or MB (base 10). */
22994 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
22995 (UINT32_C(0x0) << 29)
22996 /* Value is in Kb or KB (base 10). */
22997 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
22998 (UINT32_C(0x2) << 29)
22999 /* Value is in bits or bytes. */
23000 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
23001 (UINT32_C(0x4) << 29)
23002 /* Value is in Gb or GB (base 10). */
23003 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
23004 (UINT32_C(0x6) << 29)
23005 /* Value is in 1/100th of a percentage of total bandwidth. */
23006 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
23007 (UINT32_C(0x1) << 29)
23009 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
23010 (UINT32_C(0x7) << 29)
23011 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
23012 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
23013 /* A meter burst size specified in bytes. */
23014 uint32_t excess_peak_burst;
23015 /* The bandwidth value. */
23016 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
23017 UINT32_C(0xfffffff)
23018 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
23020 /* The granularity of the value (bits or bytes). */
23021 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
23022 UINT32_C(0x10000000)
23023 /* Value is in bits. */
23024 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
23025 (UINT32_C(0x0) << 28)
23026 /* Value is in bytes. */
23027 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
23028 (UINT32_C(0x1) << 28)
23029 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
23030 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
23031 /* bw_value_unit is 3 b */
23032 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
23033 UINT32_C(0xe0000000)
23034 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
23036 /* Value is in Mb or MB (base 10). */
23037 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
23038 (UINT32_C(0x0) << 29)
23039 /* Value is in Kb or KB (base 10). */
23040 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
23041 (UINT32_C(0x2) << 29)
23042 /* Value is in bits or bytes. */
23043 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
23044 (UINT32_C(0x4) << 29)
23045 /* Value is in Gb or GB (base 10). */
23046 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
23047 (UINT32_C(0x6) << 29)
23048 /* Value is in 1/100th of a percentage of total bandwidth. */
23049 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
23050 (UINT32_C(0x1) << 29)
23052 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
23053 (UINT32_C(0x7) << 29)
23054 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
23055 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
23056 } __attribute__((packed));
23058 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
23059 struct hwrm_cfa_meter_profile_alloc_output {
23060 /* The specific error status for the command. */
23061 uint16_t error_code;
23062 /* The HWRM command request type. */
23064 /* The sequence ID from the original command. */
23066 /* The length of the response data in number of bytes. */
23068 /* This value identifies a meter profile in CFA. */
23069 uint16_t meter_profile_id;
23071 * A value of 0xfff is considered invalid and implies the
23072 * profile is not configured.
23074 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
23076 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
23077 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
23078 uint8_t unused_0[5];
23080 * This field is used in Output records to indicate that the output
23081 * is completely written to RAM. This field should be read as '1'
23082 * to indicate that the output has been completely written.
23083 * When writing a command completion or response to an internal processor,
23084 * the order of writes has to be such that this field is written last.
23087 } __attribute__((packed));
23089 /*******************************
23090 * hwrm_cfa_meter_profile_free *
23091 *******************************/
23094 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
23095 struct hwrm_cfa_meter_profile_free_input {
23096 /* The HWRM command request type. */
23099 * The completion ring to send the completion event on. This should
23100 * be the NQ ID returned from the `nq_alloc` HWRM command.
23102 uint16_t cmpl_ring;
23104 * The sequence ID is used by the driver for tracking multiple
23105 * commands. This ID is treated as opaque data by the firmware and
23106 * the value is returned in the `hwrm_resp_hdr` upon completion.
23110 * The target ID of the command:
23111 * * 0x0-0xFFF8 - The function ID
23112 * * 0xFFF8-0xFFFE - Reserved for internal processors
23115 uint16_t target_id;
23117 * A physical address pointer pointing to a host buffer that the
23118 * command's response data will be written. This can be either a host
23119 * physical address (HPA) or a guest physical address (GPA) and must
23120 * point to a physically contiguous block of memory.
23122 uint64_t resp_addr;
23125 * Enumeration denoting the RX, TX type of the resource.
23126 * This enumeration is used for resources that are similar for both
23127 * TX and RX paths of the chip.
23129 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
23131 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
23134 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
23136 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
23137 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
23139 /* This value identifies a meter profile in CFA. */
23140 uint16_t meter_profile_id;
23142 * A value of 0xfff is considered invalid and implies the
23143 * profile is not configured.
23145 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
23147 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
23148 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
23149 uint8_t unused_1[4];
23150 } __attribute__((packed));
23152 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
23153 struct hwrm_cfa_meter_profile_free_output {
23154 /* The specific error status for the command. */
23155 uint16_t error_code;
23156 /* The HWRM command request type. */
23158 /* The sequence ID from the original command. */
23160 /* The length of the response data in number of bytes. */
23162 uint8_t unused_0[7];
23164 * This field is used in Output records to indicate that the output
23165 * is completely written to RAM. This field should be read as '1'
23166 * to indicate that the output has been completely written.
23167 * When writing a command completion or response to an internal processor,
23168 * the order of writes has to be such that this field is written last.
23171 } __attribute__((packed));
23173 /******************************
23174 * hwrm_cfa_meter_profile_cfg *
23175 ******************************/
23178 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
23179 struct hwrm_cfa_meter_profile_cfg_input {
23180 /* The HWRM command request type. */
23183 * The completion ring to send the completion event on. This should
23184 * be the NQ ID returned from the `nq_alloc` HWRM command.
23186 uint16_t cmpl_ring;
23188 * The sequence ID is used by the driver for tracking multiple
23189 * commands. This ID is treated as opaque data by the firmware and
23190 * the value is returned in the `hwrm_resp_hdr` upon completion.
23194 * The target ID of the command:
23195 * * 0x0-0xFFF8 - The function ID
23196 * * 0xFFF8-0xFFFE - Reserved for internal processors
23199 uint16_t target_id;
23201 * A physical address pointer pointing to a host buffer that the
23202 * command's response data will be written. This can be either a host
23203 * physical address (HPA) or a guest physical address (GPA) and must
23204 * point to a physically contiguous block of memory.
23206 uint64_t resp_addr;
23209 * Enumeration denoting the RX, TX type of the resource.
23210 * This enumeration is used for resources that are similar for both
23211 * TX and RX paths of the chip.
23213 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
23215 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
23217 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
23218 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
23219 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
23220 /* The meter algorithm type. */
23221 uint8_t meter_type;
23222 /* RFC 2697 (srTCM) */
23223 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
23225 /* RFC 2698 (trTCM) */
23226 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
23228 /* RFC 4115 (trTCM) */
23229 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
23231 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
23232 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
23233 /* This value identifies a meter profile in CFA. */
23234 uint16_t meter_profile_id;
23236 * A value of 0xfff is considered invalid and implies the
23237 * profile is not configured.
23239 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
23241 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
23242 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
23244 * This field is reserved for the future use.
23245 * It shall be set to 0.
23248 /* A meter rate specified in bytes-per-second. */
23249 uint32_t commit_rate;
23250 /* The bandwidth value. */
23251 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
23252 UINT32_C(0xfffffff)
23253 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
23255 /* The granularity of the value (bits or bytes). */
23256 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
23257 UINT32_C(0x10000000)
23258 /* Value is in bits. */
23259 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
23260 (UINT32_C(0x0) << 28)
23261 /* Value is in bytes. */
23262 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
23263 (UINT32_C(0x1) << 28)
23264 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
23265 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
23266 /* bw_value_unit is 3 b */
23267 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
23268 UINT32_C(0xe0000000)
23269 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
23271 /* Value is in Mb or MB (base 10). */
23272 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
23273 (UINT32_C(0x0) << 29)
23274 /* Value is in Kb or KB (base 10). */
23275 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
23276 (UINT32_C(0x2) << 29)
23277 /* Value is in bits or bytes. */
23278 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
23279 (UINT32_C(0x4) << 29)
23280 /* Value is in Gb or GB (base 10). */
23281 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
23282 (UINT32_C(0x6) << 29)
23283 /* Value is in 1/100th of a percentage of total bandwidth. */
23284 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
23285 (UINT32_C(0x1) << 29)
23287 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
23288 (UINT32_C(0x7) << 29)
23289 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
23290 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
23291 /* A meter burst size specified in bytes. */
23292 uint32_t commit_burst;
23293 /* The bandwidth value. */
23294 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
23295 UINT32_C(0xfffffff)
23296 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
23298 /* The granularity of the value (bits or bytes). */
23299 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
23300 UINT32_C(0x10000000)
23301 /* Value is in bits. */
23302 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
23303 (UINT32_C(0x0) << 28)
23304 /* Value is in bytes. */
23305 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
23306 (UINT32_C(0x1) << 28)
23307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
23308 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
23309 /* bw_value_unit is 3 b */
23310 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
23311 UINT32_C(0xe0000000)
23312 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
23314 /* Value is in Mb or MB (base 10). */
23315 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
23316 (UINT32_C(0x0) << 29)
23317 /* Value is in Kb or KB (base 10). */
23318 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
23319 (UINT32_C(0x2) << 29)
23320 /* Value is in bits or bytes. */
23321 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
23322 (UINT32_C(0x4) << 29)
23323 /* Value is in Gb or GB (base 10). */
23324 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
23325 (UINT32_C(0x6) << 29)
23326 /* Value is in 1/100th of a percentage of total bandwidth. */
23327 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
23328 (UINT32_C(0x1) << 29)
23330 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
23331 (UINT32_C(0x7) << 29)
23332 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
23333 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
23334 /* A meter rate specified in bytes-per-second. */
23335 uint32_t excess_peak_rate;
23336 /* The bandwidth value. */
23337 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
23338 UINT32_C(0xfffffff)
23339 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
23341 /* The granularity of the value (bits or bytes). */
23342 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
23343 UINT32_C(0x10000000)
23344 /* Value is in bits. */
23345 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
23346 (UINT32_C(0x0) << 28)
23347 /* Value is in bytes. */
23348 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
23349 (UINT32_C(0x1) << 28)
23350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
23351 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
23352 /* bw_value_unit is 3 b */
23353 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
23354 UINT32_C(0xe0000000)
23355 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
23357 /* Value is in Mb or MB (base 10). */
23358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
23359 (UINT32_C(0x0) << 29)
23360 /* Value is in Kb or KB (base 10). */
23361 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
23362 (UINT32_C(0x2) << 29)
23363 /* Value is in bits or bytes. */
23364 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
23365 (UINT32_C(0x4) << 29)
23366 /* Value is in Gb or GB (base 10). */
23367 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
23368 (UINT32_C(0x6) << 29)
23369 /* Value is in 1/100th of a percentage of total bandwidth. */
23370 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
23371 (UINT32_C(0x1) << 29)
23373 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
23374 (UINT32_C(0x7) << 29)
23375 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
23376 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
23377 /* A meter burst size specified in bytes. */
23378 uint32_t excess_peak_burst;
23379 /* The bandwidth value. */
23380 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
23381 UINT32_C(0xfffffff)
23382 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
23384 /* The granularity of the value (bits or bytes). */
23385 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
23386 UINT32_C(0x10000000)
23387 /* Value is in bits. */
23388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
23389 (UINT32_C(0x0) << 28)
23390 /* Value is in bytes. */
23391 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
23392 (UINT32_C(0x1) << 28)
23393 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
23394 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
23395 /* bw_value_unit is 3 b */
23396 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
23397 UINT32_C(0xe0000000)
23398 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
23400 /* Value is in Mb or MB (base 10). */
23401 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
23402 (UINT32_C(0x0) << 29)
23403 /* Value is in Kb or KB (base 10). */
23404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
23405 (UINT32_C(0x2) << 29)
23406 /* Value is in bits or bytes. */
23407 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
23408 (UINT32_C(0x4) << 29)
23409 /* Value is in Gb or GB (base 10). */
23410 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
23411 (UINT32_C(0x6) << 29)
23412 /* Value is in 1/100th of a percentage of total bandwidth. */
23413 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
23414 (UINT32_C(0x1) << 29)
23416 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
23417 (UINT32_C(0x7) << 29)
23418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
23419 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
23420 } __attribute__((packed));
23422 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
23423 struct hwrm_cfa_meter_profile_cfg_output {
23424 /* The specific error status for the command. */
23425 uint16_t error_code;
23426 /* The HWRM command request type. */
23428 /* The sequence ID from the original command. */
23430 /* The length of the response data in number of bytes. */
23432 uint8_t unused_0[7];
23434 * This field is used in Output records to indicate that the output
23435 * is completely written to RAM. This field should be read as '1'
23436 * to indicate that the output has been completely written.
23437 * When writing a command completion or response to an internal processor,
23438 * the order of writes has to be such that this field is written last.
23441 } __attribute__((packed));
23443 /*********************************
23444 * hwrm_cfa_meter_instance_alloc *
23445 *********************************/
23448 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
23449 struct hwrm_cfa_meter_instance_alloc_input {
23450 /* The HWRM command request type. */
23453 * The completion ring to send the completion event on. This should
23454 * be the NQ ID returned from the `nq_alloc` HWRM command.
23456 uint16_t cmpl_ring;
23458 * The sequence ID is used by the driver for tracking multiple
23459 * commands. This ID is treated as opaque data by the firmware and
23460 * the value is returned in the `hwrm_resp_hdr` upon completion.
23464 * The target ID of the command:
23465 * * 0x0-0xFFF8 - The function ID
23466 * * 0xFFF8-0xFFFE - Reserved for internal processors
23469 uint16_t target_id;
23471 * A physical address pointer pointing to a host buffer that the
23472 * command's response data will be written. This can be either a host
23473 * physical address (HPA) or a guest physical address (GPA) and must
23474 * point to a physically contiguous block of memory.
23476 uint64_t resp_addr;
23479 * Enumeration denoting the RX, TX type of the resource.
23480 * This enumeration is used for resources that are similar for both
23481 * TX and RX paths of the chip.
23483 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
23486 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
23489 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
23491 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
23492 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
23494 /* This value identifies a meter profile in CFA. */
23495 uint16_t meter_profile_id;
23497 * A value of 0xfff is considered invalid and implies the
23498 * profile is not configured.
23500 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
23502 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
23503 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
23504 uint8_t unused_1[4];
23505 } __attribute__((packed));
23507 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
23508 struct hwrm_cfa_meter_instance_alloc_output {
23509 /* The specific error status for the command. */
23510 uint16_t error_code;
23511 /* The HWRM command request type. */
23513 /* The sequence ID from the original command. */
23515 /* The length of the response data in number of bytes. */
23517 /* This value identifies a meter instance in CFA. */
23518 uint16_t meter_instance_id;
23520 * A value of 0xfff is considered invalid and implies the
23521 * instance is not configured.
23523 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
23525 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
23526 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
23527 uint8_t unused_0[5];
23529 * This field is used in Output records to indicate that the output
23530 * is completely written to RAM. This field should be read as '1'
23531 * to indicate that the output has been completely written.
23532 * When writing a command completion or response to an internal processor,
23533 * the order of writes has to be such that this field is written last.
23536 } __attribute__((packed));
23538 /********************************
23539 * hwrm_cfa_meter_instance_free *
23540 ********************************/
23543 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
23544 struct hwrm_cfa_meter_instance_free_input {
23545 /* The HWRM command request type. */
23548 * The completion ring to send the completion event on. This should
23549 * be the NQ ID returned from the `nq_alloc` HWRM command.
23551 uint16_t cmpl_ring;
23553 * The sequence ID is used by the driver for tracking multiple
23554 * commands. This ID is treated as opaque data by the firmware and
23555 * the value is returned in the `hwrm_resp_hdr` upon completion.
23559 * The target ID of the command:
23560 * * 0x0-0xFFF8 - The function ID
23561 * * 0xFFF8-0xFFFE - Reserved for internal processors
23564 uint16_t target_id;
23566 * A physical address pointer pointing to a host buffer that the
23567 * command's response data will be written. This can be either a host
23568 * physical address (HPA) or a guest physical address (GPA) and must
23569 * point to a physically contiguous block of memory.
23571 uint64_t resp_addr;
23574 * Enumeration denoting the RX, TX type of the resource.
23575 * This enumeration is used for resources that are similar for both
23576 * TX and RX paths of the chip.
23578 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
23580 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
23583 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
23585 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
23586 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
23588 /* This value identifies a meter instance in CFA. */
23589 uint16_t meter_instance_id;
23591 * A value of 0xfff is considered invalid and implies the
23592 * instance is not configured.
23594 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
23596 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
23597 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
23598 uint8_t unused_1[4];
23599 } __attribute__((packed));
23601 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
23602 struct hwrm_cfa_meter_instance_free_output {
23603 /* The specific error status for the command. */
23604 uint16_t error_code;
23605 /* The HWRM command request type. */
23607 /* The sequence ID from the original command. */
23609 /* The length of the response data in number of bytes. */
23611 uint8_t unused_0[7];
23613 * This field is used in Output records to indicate that the output
23614 * is completely written to RAM. This field should be read as '1'
23615 * to indicate that the output has been completely written.
23616 * When writing a command completion or response to an internal processor,
23617 * the order of writes has to be such that this field is written last.
23620 } __attribute__((packed));
23622 /*******************************
23623 * hwrm_cfa_decap_filter_alloc *
23624 *******************************/
23627 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
23628 struct hwrm_cfa_decap_filter_alloc_input {
23629 /* The HWRM command request type. */
23632 * The completion ring to send the completion event on. This should
23633 * be the NQ ID returned from the `nq_alloc` HWRM command.
23635 uint16_t cmpl_ring;
23637 * The sequence ID is used by the driver for tracking multiple
23638 * commands. This ID is treated as opaque data by the firmware and
23639 * the value is returned in the `hwrm_resp_hdr` upon completion.
23643 * The target ID of the command:
23644 * * 0x0-0xFFF8 - The function ID
23645 * * 0xFFF8-0xFFFE - Reserved for internal processors
23648 uint16_t target_id;
23650 * A physical address pointer pointing to a host buffer that the
23651 * command's response data will be written. This can be either a host
23652 * physical address (HPA) or a guest physical address (GPA) and must
23653 * point to a physically contiguous block of memory.
23655 uint64_t resp_addr;
23657 /* ovs_tunnel is 1 b */
23658 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
23662 * This bit must be '1' for the tunnel_type field to be
23665 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23668 * This bit must be '1' for the tunnel_id field to be
23671 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
23674 * This bit must be '1' for the src_macaddr field to be
23677 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23680 * This bit must be '1' for the dst_macaddr field to be
23683 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
23686 * This bit must be '1' for the ovlan_vid field to be
23689 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
23692 * This bit must be '1' for the ivlan_vid field to be
23695 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
23698 * This bit must be '1' for the t_ovlan_vid field to be
23701 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
23704 * This bit must be '1' for the t_ivlan_vid field to be
23707 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
23710 * This bit must be '1' for the ethertype field to be
23713 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
23716 * This bit must be '1' for the src_ipaddr field to be
23719 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23722 * This bit must be '1' for the dst_ipaddr field to be
23725 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
23728 * This bit must be '1' for the ipaddr_type field to be
23731 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23734 * This bit must be '1' for the ip_protocol field to be
23737 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23740 * This bit must be '1' for the src_port field to be
23743 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
23746 * This bit must be '1' for the dst_port field to be
23749 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
23752 * This bit must be '1' for the dst_id field to be
23755 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23758 * This bit must be '1' for the mirror_vnic_id field to be
23761 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23764 * Tunnel identifier.
23765 * Virtual Network Identifier (VNI). Only valid with
23766 * tunnel_types VXLAN, NVGRE, and Geneve.
23767 * Only lower 24-bits of VNI field are used
23768 * in setting up the filter.
23770 uint32_t tunnel_id;
23772 uint8_t tunnel_type;
23774 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23776 /* Virtual eXtensible Local Area Network (VXLAN) */
23777 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23779 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23780 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23782 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23783 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23786 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23788 /* Generic Network Virtualization Encapsulation (Geneve) */
23789 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23791 /* Multi-Protocol Lable Switching (MPLS) */
23792 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23794 /* Stateless Transport Tunnel (STT) */
23795 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23797 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23798 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23800 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23801 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23803 /* Any tunneled traffic */
23804 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23806 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23807 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23811 * This value indicates the source MAC address in
23812 * the Ethernet header.
23814 uint8_t src_macaddr[6];
23815 uint8_t unused_2[2];
23817 * This value indicates the destination MAC address in
23818 * the Ethernet header.
23820 uint8_t dst_macaddr[6];
23822 * This value indicates the VLAN ID of the outer VLAN tag
23823 * in the Ethernet header.
23825 uint16_t ovlan_vid;
23827 * This value indicates the VLAN ID of the inner VLAN tag
23828 * in the Ethernet header.
23830 uint16_t ivlan_vid;
23832 * This value indicates the VLAN ID of the outer VLAN tag
23833 * in the tunnel Ethernet header.
23835 uint16_t t_ovlan_vid;
23837 * This value indicates the VLAN ID of the inner VLAN tag
23838 * in the tunnel Ethernet header.
23840 uint16_t t_ivlan_vid;
23841 /* This value indicates the ethertype in the Ethernet header. */
23842 uint16_t ethertype;
23844 * This value indicates the type of IP address.
23847 * All others are invalid.
23849 uint8_t ip_addr_type;
23851 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
23854 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
23857 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
23859 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23860 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23862 * The value of protocol filed in IP header.
23863 * Applies to UDP and TCP traffic.
23867 uint8_t ip_protocol;
23869 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
23872 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
23875 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
23877 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
23878 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
23882 * The value of source IP address to be used in filtering.
23883 * For IPv4, first four bytes represent the IP address.
23885 uint32_t src_ipaddr[4];
23887 * The value of destination IP address to be used in filtering.
23888 * For IPv4, first four bytes represent the IP address.
23890 uint32_t dst_ipaddr[4];
23892 * The value of source port to be used in filtering.
23893 * Applies to UDP and TCP traffic.
23897 * The value of destination port to be used in filtering.
23898 * Applies to UDP and TCP traffic.
23902 * If set, this value shall represent the
23903 * Logical VNIC ID of the destination VNIC for the RX
23908 * If set, this value shall represent the L2 context that matches the L2
23909 * information of the decap filter.
23911 uint16_t l2_ctxt_ref_id;
23912 } __attribute__((packed));
23914 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
23915 struct hwrm_cfa_decap_filter_alloc_output {
23916 /* The specific error status for the command. */
23917 uint16_t error_code;
23918 /* The HWRM command request type. */
23920 /* The sequence ID from the original command. */
23922 /* The length of the response data in number of bytes. */
23924 /* This value is an opaque id into CFA data structures. */
23925 uint32_t decap_filter_id;
23926 uint8_t unused_0[3];
23928 * This field is used in Output records to indicate that the output
23929 * is completely written to RAM. This field should be read as '1'
23930 * to indicate that the output has been completely written.
23931 * When writing a command completion or response to an internal processor,
23932 * the order of writes has to be such that this field is written last.
23935 } __attribute__((packed));
23937 /******************************
23938 * hwrm_cfa_decap_filter_free *
23939 ******************************/
23942 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
23943 struct hwrm_cfa_decap_filter_free_input {
23944 /* The HWRM command request type. */
23947 * The completion ring to send the completion event on. This should
23948 * be the NQ ID returned from the `nq_alloc` HWRM command.
23950 uint16_t cmpl_ring;
23952 * The sequence ID is used by the driver for tracking multiple
23953 * commands. This ID is treated as opaque data by the firmware and
23954 * the value is returned in the `hwrm_resp_hdr` upon completion.
23958 * The target ID of the command:
23959 * * 0x0-0xFFF8 - The function ID
23960 * * 0xFFF8-0xFFFE - Reserved for internal processors
23963 uint16_t target_id;
23965 * A physical address pointer pointing to a host buffer that the
23966 * command's response data will be written. This can be either a host
23967 * physical address (HPA) or a guest physical address (GPA) and must
23968 * point to a physically contiguous block of memory.
23970 uint64_t resp_addr;
23971 /* This value is an opaque id into CFA data structures. */
23972 uint32_t decap_filter_id;
23973 uint8_t unused_0[4];
23974 } __attribute__((packed));
23976 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
23977 struct hwrm_cfa_decap_filter_free_output {
23978 /* The specific error status for the command. */
23979 uint16_t error_code;
23980 /* The HWRM command request type. */
23982 /* The sequence ID from the original command. */
23984 /* The length of the response data in number of bytes. */
23986 uint8_t unused_0[7];
23988 * This field is used in Output records to indicate that the output
23989 * is completely written to RAM. This field should be read as '1'
23990 * to indicate that the output has been completely written.
23991 * When writing a command completion or response to an internal processor,
23992 * the order of writes has to be such that this field is written last.
23995 } __attribute__((packed));
23997 /***********************
23998 * hwrm_cfa_flow_alloc *
23999 ***********************/
24002 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
24003 struct hwrm_cfa_flow_alloc_input {
24004 /* The HWRM command request type. */
24007 * The completion ring to send the completion event on. This should
24008 * be the NQ ID returned from the `nq_alloc` HWRM command.
24010 uint16_t cmpl_ring;
24012 * The sequence ID is used by the driver for tracking multiple
24013 * commands. This ID is treated as opaque data by the firmware and
24014 * the value is returned in the `hwrm_resp_hdr` upon completion.
24018 * The target ID of the command:
24019 * * 0x0-0xFFF8 - The function ID
24020 * * 0xFFF8-0xFFFE - Reserved for internal processors
24023 uint16_t target_id;
24025 * A physical address pointer pointing to a host buffer that the
24026 * command's response data will be written. This can be either a host
24027 * physical address (HPA) or a guest physical address (GPA) and must
24028 * point to a physically contiguous block of memory.
24030 uint64_t resp_addr;
24032 /* tunnel is 1 b */
24033 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
24034 /* num_vlan is 2 b */
24035 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
24036 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
24038 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
24039 (UINT32_C(0x0) << 1)
24041 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
24042 (UINT32_C(0x1) << 1)
24044 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
24045 (UINT32_C(0x2) << 1)
24046 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
24047 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
24048 /* Enumeration denoting the Flow Type. */
24049 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
24050 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
24052 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
24053 (UINT32_C(0x0) << 3)
24055 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
24056 (UINT32_C(0x1) << 3)
24058 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
24059 (UINT32_C(0x2) << 3)
24060 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
24061 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
24067 /* Tunnel handle valid when tunnel flag is set. */
24068 uint32_t tunnel_handle;
24069 uint16_t action_flags;
24071 * Setting of this flag indicates drop action. If this flag is not set,
24072 * then it should be considered accept action.
24074 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
24076 /* recycle is 1 b */
24077 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
24080 * Setting of this flag indicates drop action. If this flag is not set,
24081 * then it should be considered accept action.
24083 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
24086 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
24088 /* tunnel is 1 b */
24089 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
24091 /* nat_src is 1 b */
24092 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
24094 /* nat_dest is 1 b */
24095 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
24097 /* nat_ipv4_address is 1 b */
24098 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
24100 /* l2_header_rewrite is 1 b */
24101 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
24103 /* ttl_decrement is 1 b */
24104 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
24107 * Tx Flow: pf or vf fid.
24111 /* VLAN tpid, valid when push_vlan flag is set. */
24112 uint16_t l2_rewrite_vlan_tpid;
24113 /* VLAN tci, valid when push_vlan flag is set. */
24114 uint16_t l2_rewrite_vlan_tci;
24115 /* Meter id, valid when meter flag is set. */
24116 uint16_t act_meter_id;
24117 /* Flow with the same l2 context tcam key. */
24118 uint16_t ref_flow_handle;
24119 /* This value sets the match value for the ethertype. */
24120 uint16_t ethertype;
24121 /* valid when num tags is 1 or 2. */
24122 uint16_t outer_vlan_tci;
24123 /* This value sets the match value for the Destination MAC address. */
24125 /* valid when num tags is 2. */
24126 uint16_t inner_vlan_tci;
24127 /* This value sets the match value for the Source MAC address. */
24129 /* The bit length of destination IP address mask. */
24130 uint8_t ip_dst_mask_len;
24131 /* The bit length of source IP address mask. */
24132 uint8_t ip_src_mask_len;
24133 /* The value of destination IPv4/IPv6 address. */
24134 uint32_t ip_dst[4];
24135 /* The source IPv4/IPv6 address. */
24136 uint32_t ip_src[4];
24138 * The value of source port.
24139 * Applies to UDP and TCP traffic.
24141 uint16_t l4_src_port;
24143 * The value of source port mask.
24144 * Applies to UDP and TCP traffic.
24146 uint16_t l4_src_port_mask;
24148 * The value of destination port.
24149 * Applies to UDP and TCP traffic.
24151 uint16_t l4_dst_port;
24153 * The value of destination port mask.
24154 * Applies to UDP and TCP traffic.
24156 uint16_t l4_dst_port_mask;
24158 * NAT IPv4/6 address based on address type flag.
24159 * 0 values are ignored.
24161 uint32_t nat_ip_address[4];
24162 /* L2 header re-write Destination MAC address. */
24163 uint16_t l2_rewrite_dmac[3];
24165 * The NAT source/destination port based on direction flag.
24166 * Applies to UDP and TCP traffic.
24167 * 0 values are ignored.
24170 /* L2 header re-write Source MAC address. */
24171 uint16_t l2_rewrite_smac[3];
24172 /* The value of ip protocol. */
24175 } __attribute__((packed));
24177 /* hwrm_cfa_flow_alloc_output (size:128b/16B) */
24178 struct hwrm_cfa_flow_alloc_output {
24179 /* The specific error status for the command. */
24180 uint16_t error_code;
24181 /* The HWRM command request type. */
24183 /* The sequence ID from the original command. */
24185 /* The length of the response data in number of bytes. */
24187 /* Flow record index. */
24188 uint16_t flow_handle;
24189 uint8_t unused_0[5];
24191 * This field is used in Output records to indicate that the output
24192 * is completely written to RAM. This field should be read as '1'
24193 * to indicate that the output has been completely written.
24194 * When writing a command completion or response to an internal processor,
24195 * the order of writes has to be such that this field is written last.
24198 } __attribute__((packed));
24200 /**********************
24201 * hwrm_cfa_flow_free *
24202 **********************/
24205 /* hwrm_cfa_flow_free_input (size:192b/24B) */
24206 struct hwrm_cfa_flow_free_input {
24207 /* The HWRM command request type. */
24210 * The completion ring to send the completion event on. This should
24211 * be the NQ ID returned from the `nq_alloc` HWRM command.
24213 uint16_t cmpl_ring;
24215 * The sequence ID is used by the driver for tracking multiple
24216 * commands. This ID is treated as opaque data by the firmware and
24217 * the value is returned in the `hwrm_resp_hdr` upon completion.
24221 * The target ID of the command:
24222 * * 0x0-0xFFF8 - The function ID
24223 * * 0xFFF8-0xFFFE - Reserved for internal processors
24226 uint16_t target_id;
24228 * A physical address pointer pointing to a host buffer that the
24229 * command's response data will be written. This can be either a host
24230 * physical address (HPA) or a guest physical address (GPA) and must
24231 * point to a physically contiguous block of memory.
24233 uint64_t resp_addr;
24234 /* Flow record index. */
24235 uint16_t flow_handle;
24236 uint8_t unused_0[6];
24237 } __attribute__((packed));
24239 /* hwrm_cfa_flow_free_output (size:256b/32B) */
24240 struct hwrm_cfa_flow_free_output {
24241 /* The specific error status for the command. */
24242 uint16_t error_code;
24243 /* The HWRM command request type. */
24245 /* The sequence ID from the original command. */
24247 /* The length of the response data in number of bytes. */
24249 /* packet is 64 b */
24253 uint8_t unused_0[7];
24255 * This field is used in Output records to indicate that the output
24256 * is completely written to RAM. This field should be read as '1'
24257 * to indicate that the output has been completely written.
24258 * When writing a command completion or response to an internal processor,
24259 * the order of writes has to be such that this field is written last.
24262 } __attribute__((packed));
24264 /**********************
24265 * hwrm_cfa_flow_info *
24266 **********************/
24269 /* hwrm_cfa_flow_info_input (size:192b/24B) */
24270 struct hwrm_cfa_flow_info_input {
24271 /* The HWRM command request type. */
24274 * The completion ring to send the completion event on. This should
24275 * be the NQ ID returned from the `nq_alloc` HWRM command.
24277 uint16_t cmpl_ring;
24279 * The sequence ID is used by the driver for tracking multiple
24280 * commands. This ID is treated as opaque data by the firmware and
24281 * the value is returned in the `hwrm_resp_hdr` upon completion.
24285 * The target ID of the command:
24286 * * 0x0-0xFFF8 - The function ID
24287 * * 0xFFF8-0xFFFE - Reserved for internal processors
24290 uint16_t target_id;
24292 * A physical address pointer pointing to a host buffer that the
24293 * command's response data will be written. This can be either a host
24294 * physical address (HPA) or a guest physical address (GPA) and must
24295 * point to a physically contiguous block of memory.
24297 uint64_t resp_addr;
24298 /* Flow record index. */
24299 uint16_t flow_handle;
24300 /* Max flow handle */
24301 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
24303 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
24304 /* CNP flow handle */
24305 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
24307 /* Direction rx = 1 */
24308 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
24310 uint8_t unused_0[6];
24311 } __attribute__((packed));
24313 /* hwrm_cfa_flow_info_output (size:448b/56B) */
24314 struct hwrm_cfa_flow_info_output {
24315 /* The specific error status for the command. */
24316 uint16_t error_code;
24317 /* The HWRM command request type. */
24319 /* The sequence ID from the original command. */
24321 /* The length of the response data in number of bytes. */
24325 /* profile is 8 b */
24327 /* src_fid is 16 b */
24329 /* dst_fid is 16 b */
24331 /* l2_ctxt_id is 16 b */
24332 uint16_t l2_ctxt_id;
24333 /* em_info is 64 b */
24335 /* tcam_info is 64 b */
24336 uint64_t tcam_info;
24337 /* vfp_tcam_info is 64 b */
24338 uint64_t vfp_tcam_info;
24339 /* ar_id is 16 b */
24341 /* flow_handle is 16 b */
24342 uint16_t flow_handle;
24343 /* tunnel_handle is 32 b */
24344 uint32_t tunnel_handle;
24345 uint8_t unused_0[7];
24347 * This field is used in Output records to indicate that the output
24348 * is completely written to RAM. This field should be read as '1'
24349 * to indicate that the output has been completely written.
24350 * When writing a command completion or response to an internal processor,
24351 * the order of writes has to be such that this field is written last.
24354 } __attribute__((packed));
24356 /***********************
24357 * hwrm_cfa_flow_flush *
24358 ***********************/
24361 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
24362 struct hwrm_cfa_flow_flush_input {
24363 /* The HWRM command request type. */
24366 * The completion ring to send the completion event on. This should
24367 * be the NQ ID returned from the `nq_alloc` HWRM command.
24369 uint16_t cmpl_ring;
24371 * The sequence ID is used by the driver for tracking multiple
24372 * commands. This ID is treated as opaque data by the firmware and
24373 * the value is returned in the `hwrm_resp_hdr` upon completion.
24377 * The target ID of the command:
24378 * * 0x0-0xFFF8 - The function ID
24379 * * 0xFFF8-0xFFFE - Reserved for internal processors
24382 uint16_t target_id;
24384 * A physical address pointer pointing to a host buffer that the
24385 * command's response data will be written. This can be either a host
24386 * physical address (HPA) or a guest physical address (GPA) and must
24387 * point to a physically contiguous block of memory.
24389 uint64_t resp_addr;
24391 uint8_t unused_0[4];
24392 } __attribute__((packed));
24394 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
24395 struct hwrm_cfa_flow_flush_output {
24396 /* The specific error status for the command. */
24397 uint16_t error_code;
24398 /* The HWRM command request type. */
24400 /* The sequence ID from the original command. */
24402 /* The length of the response data in number of bytes. */
24404 uint8_t unused_0[7];
24406 * This field is used in Output records to indicate that the output
24407 * is completely written to RAM. This field should be read as '1'
24408 * to indicate that the output has been completely written.
24409 * When writing a command completion or response to an internal processor,
24410 * the order of writes has to be such that this field is written last.
24413 } __attribute__((packed));
24415 /***********************
24416 * hwrm_cfa_flow_stats *
24417 ***********************/
24420 /* hwrm_cfa_flow_stats_input (size:320b/40B) */
24421 struct hwrm_cfa_flow_stats_input {
24422 /* The HWRM command request type. */
24425 * The completion ring to send the completion event on. This should
24426 * be the NQ ID returned from the `nq_alloc` HWRM command.
24428 uint16_t cmpl_ring;
24430 * The sequence ID is used by the driver for tracking multiple
24431 * commands. This ID is treated as opaque data by the firmware and
24432 * the value is returned in the `hwrm_resp_hdr` upon completion.
24436 * The target ID of the command:
24437 * * 0x0-0xFFF8 - The function ID
24438 * * 0xFFF8-0xFFFE - Reserved for internal processors
24441 uint16_t target_id;
24443 * A physical address pointer pointing to a host buffer that the
24444 * command's response data will be written. This can be either a host
24445 * physical address (HPA) or a guest physical address (GPA) and must
24446 * point to a physically contiguous block of memory.
24448 uint64_t resp_addr;
24450 uint16_t num_flows;
24452 uint16_t flow_handle_0;
24454 uint16_t flow_handle_1;
24456 uint16_t flow_handle_2;
24458 uint16_t flow_handle_3;
24460 uint16_t flow_handle_4;
24462 uint16_t flow_handle_5;
24464 uint16_t flow_handle_6;
24466 uint16_t flow_handle_7;
24468 uint16_t flow_handle_8;
24470 uint16_t flow_handle_9;
24471 uint8_t unused_0[2];
24472 } __attribute__((packed));
24474 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
24475 struct hwrm_cfa_flow_stats_output {
24476 /* The specific error status for the command. */
24477 uint16_t error_code;
24478 /* The HWRM command request type. */
24480 /* The sequence ID from the original command. */
24482 /* The length of the response data in number of bytes. */
24484 /* packet_0 is 64 b */
24486 /* packet_1 is 64 b */
24488 /* packet_2 is 64 b */
24490 /* packet_3 is 64 b */
24492 /* packet_4 is 64 b */
24494 /* packet_5 is 64 b */
24496 /* packet_6 is 64 b */
24498 /* packet_7 is 64 b */
24500 /* packet_8 is 64 b */
24502 /* packet_9 is 64 b */
24504 /* byte_0 is 64 b */
24506 /* byte_1 is 64 b */
24508 /* byte_2 is 64 b */
24510 /* byte_3 is 64 b */
24512 /* byte_4 is 64 b */
24514 /* byte_5 is 64 b */
24516 /* byte_6 is 64 b */
24518 /* byte_7 is 64 b */
24520 /* byte_8 is 64 b */
24522 /* byte_9 is 64 b */
24524 uint8_t unused_0[7];
24526 * This field is used in Output records to indicate that the output
24527 * is completely written to RAM. This field should be read as '1'
24528 * to indicate that the output has been completely written.
24529 * When writing a command completion or response to an internal processor,
24530 * the order of writes has to be such that this field is written last.
24533 } __attribute__((packed));
24535 /**************************
24536 * hwrm_cfa_vf_pair_alloc *
24537 **************************/
24540 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
24541 struct hwrm_cfa_vf_pair_alloc_input {
24542 /* The HWRM command request type. */
24545 * The completion ring to send the completion event on. This should
24546 * be the NQ ID returned from the `nq_alloc` HWRM command.
24548 uint16_t cmpl_ring;
24550 * The sequence ID is used by the driver for tracking multiple
24551 * commands. This ID is treated as opaque data by the firmware and
24552 * the value is returned in the `hwrm_resp_hdr` upon completion.
24556 * The target ID of the command:
24557 * * 0x0-0xFFF8 - The function ID
24558 * * 0xFFF8-0xFFFE - Reserved for internal processors
24561 uint16_t target_id;
24563 * A physical address pointer pointing to a host buffer that the
24564 * command's response data will be written. This can be either a host
24565 * physical address (HPA) or a guest physical address (GPA) and must
24566 * point to a physically contiguous block of memory.
24568 uint64_t resp_addr;
24569 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24571 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24573 uint8_t unused_0[4];
24574 /* VF Pair name (32 byte string). */
24575 char pair_name[32];
24576 } __attribute__((packed));
24578 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
24579 struct hwrm_cfa_vf_pair_alloc_output {
24580 /* The specific error status for the command. */
24581 uint16_t error_code;
24582 /* The HWRM command request type. */
24584 /* The sequence ID from the original command. */
24586 /* The length of the response data in number of bytes. */
24588 uint8_t unused_0[7];
24590 * This field is used in Output records to indicate that the output
24591 * is completely written to RAM. This field should be read as '1'
24592 * to indicate that the output has been completely written.
24593 * When writing a command completion or response to an internal processor,
24594 * the order of writes has to be such that this field is written last.
24597 } __attribute__((packed));
24599 /*************************
24600 * hwrm_cfa_vf_pair_free *
24601 *************************/
24604 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
24605 struct hwrm_cfa_vf_pair_free_input {
24606 /* The HWRM command request type. */
24609 * The completion ring to send the completion event on. This should
24610 * be the NQ ID returned from the `nq_alloc` HWRM command.
24612 uint16_t cmpl_ring;
24614 * The sequence ID is used by the driver for tracking multiple
24615 * commands. This ID is treated as opaque data by the firmware and
24616 * the value is returned in the `hwrm_resp_hdr` upon completion.
24620 * The target ID of the command:
24621 * * 0x0-0xFFF8 - The function ID
24622 * * 0xFFF8-0xFFFE - Reserved for internal processors
24625 uint16_t target_id;
24627 * A physical address pointer pointing to a host buffer that the
24628 * command's response data will be written. This can be either a host
24629 * physical address (HPA) or a guest physical address (GPA) and must
24630 * point to a physically contiguous block of memory.
24632 uint64_t resp_addr;
24633 /* VF Pair name (32 byte string). */
24634 char pair_name[32];
24635 } __attribute__((packed));
24637 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
24638 struct hwrm_cfa_vf_pair_free_output {
24639 /* The specific error status for the command. */
24640 uint16_t error_code;
24641 /* The HWRM command request type. */
24643 /* The sequence ID from the original command. */
24645 /* The length of the response data in number of bytes. */
24647 uint8_t unused_0[7];
24649 * This field is used in Output records to indicate that the output
24650 * is completely written to RAM. This field should be read as '1'
24651 * to indicate that the output has been completely written.
24652 * When writing a command completion or response to an internal processor,
24653 * the order of writes has to be such that this field is written last.
24656 } __attribute__((packed));
24658 /*************************
24659 * hwrm_cfa_vf_pair_info *
24660 *************************/
24663 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
24664 struct hwrm_cfa_vf_pair_info_input {
24665 /* The HWRM command request type. */
24668 * The completion ring to send the completion event on. This should
24669 * be the NQ ID returned from the `nq_alloc` HWRM command.
24671 uint16_t cmpl_ring;
24673 * The sequence ID is used by the driver for tracking multiple
24674 * commands. This ID is treated as opaque data by the firmware and
24675 * the value is returned in the `hwrm_resp_hdr` upon completion.
24679 * The target ID of the command:
24680 * * 0x0-0xFFF8 - The function ID
24681 * * 0xFFF8-0xFFFE - Reserved for internal processors
24684 uint16_t target_id;
24686 * A physical address pointer pointing to a host buffer that the
24687 * command's response data will be written. This can be either a host
24688 * physical address (HPA) or a guest physical address (GPA) and must
24689 * point to a physically contiguous block of memory.
24691 uint64_t resp_addr;
24693 /* If this flag is set, lookup by name else lookup by index. */
24694 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
24695 /* vf pair table index. */
24696 uint16_t vf_pair_index;
24697 uint8_t unused_0[2];
24698 /* VF Pair name (32 byte string). */
24699 char vf_pair_name[32];
24700 } __attribute__((packed));
24702 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
24703 struct hwrm_cfa_vf_pair_info_output {
24704 /* The specific error status for the command. */
24705 uint16_t error_code;
24706 /* The HWRM command request type. */
24708 /* The sequence ID from the original command. */
24710 /* The length of the response data in number of bytes. */
24712 /* vf pair table index. */
24713 uint16_t next_vf_pair_index;
24714 /* vf pair member a's vf_fid. */
24716 /* vf pair member a's Linux logical VF number. */
24717 uint16_t vf_a_index;
24718 /* vf pair member b's vf_fid. */
24720 /* vf pair member a's Linux logical VF number. */
24721 uint16_t vf_b_index;
24722 /* vf pair state. */
24723 uint8_t pair_state;
24724 /* Pair has been allocated */
24725 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
24726 /* Both pair members are active */
24727 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
24728 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
24729 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
24730 uint8_t unused_0[5];
24731 /* VF Pair name (32 byte string). */
24732 char pair_name[32];
24733 uint8_t unused_1[7];
24735 * This field is used in Output records to indicate that the output
24736 * is completely written to RAM. This field should be read as '1'
24737 * to indicate that the output has been completely written.
24738 * When writing a command completion or response to an internal processor,
24739 * the order of writes has to be such that this field is written last.
24742 } __attribute__((packed));
24744 /***********************
24745 * hwrm_cfa_pair_alloc *
24746 ***********************/
24749 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
24750 struct hwrm_cfa_pair_alloc_input {
24751 /* The HWRM command request type. */
24754 * The completion ring to send the completion event on. This should
24755 * be the NQ ID returned from the `nq_alloc` HWRM command.
24757 uint16_t cmpl_ring;
24759 * The sequence ID is used by the driver for tracking multiple
24760 * commands. This ID is treated as opaque data by the firmware and
24761 * the value is returned in the `hwrm_resp_hdr` upon completion.
24765 * The target ID of the command:
24766 * * 0x0-0xFFF8 - The function ID
24767 * * 0xFFF8-0xFFFE - Reserved for internal processors
24770 uint16_t target_id;
24772 * A physical address pointer pointing to a host buffer that the
24773 * command's response data will be written. This can be either a host
24774 * physical address (HPA) or a guest physical address (GPA) and must
24775 * point to a physically contiguous block of memory.
24777 uint64_t resp_addr;
24778 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */
24780 /* Pair between VF on local host with PF or VF on specified host. */
24781 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
24782 /* Pair between REP on local host with PF or VF on specified host. */
24783 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
24784 /* Pair between REP on local host with REP on specified host. */
24785 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
24786 /* Pair for the proxy interface. */
24787 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
24788 /* Pair for the PF interface. */
24789 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
24790 /* Modify exiting rep2fn pair and move pair to new PF. */
24791 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
24792 /* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */
24793 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
24794 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
24795 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL
24797 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24799 /* Logical Host (0xff-local host). */
24801 /* Logical PF (0xff-PF for command channel). */
24803 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24805 /* Loopback port (0xff-internal loopback), valid for mode-3. */
24807 /* Priority used for encap of loopback packets valid for mode-3. */
24809 /* New PF for rep2fn modify, valid for mode 5. */
24810 uint16_t new_pf_fid;
24813 * This bit must be '1' for the q_ab field to be
24816 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
24818 * This bit must be '1' for the q_ba field to be
24821 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
24823 * This bit must be '1' for the fc_ab field to be
24826 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
24828 * This bit must be '1' for the fc_ba field to be
24831 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
24832 /* VF Pair name (32 byte string). */
24833 char pair_name[32];
24835 * The q_ab value specifies the logical index of the TX/RX CoS
24836 * queue to be assigned for traffic in the A to B direction of
24837 * the interface pair. The default value is 0.
24841 * The q_ba value specifies the logical index of the TX/RX CoS
24842 * queue to be assigned for traffic in the B to A direction of
24843 * the interface pair. The default value is 1.
24847 * Specifies whether RX ring flow control is disabled (0) or enabled
24848 * (1) in the A to B direction. The default value is 0, meaning that
24849 * packets will be dropped when the B-side RX rings are full.
24853 * Specifies whether RX ring flow control is disabled (0) or enabled
24854 * (1) in the B to A direction. The default value is 1, meaning that
24855 * the RX CoS queue will be flow controlled when the A-side RX rings
24859 uint8_t unused_1[4];
24860 } __attribute__((packed));
24862 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
24863 struct hwrm_cfa_pair_alloc_output {
24864 /* The specific error status for the command. */
24865 uint16_t error_code;
24866 /* The HWRM command request type. */
24868 /* The sequence ID from the original command. */
24870 /* The length of the response data in number of bytes. */
24872 /* Only valid for modes 1 and 2. */
24873 uint16_t rx_cfa_code_a;
24874 /* Only valid for modes 1 and 2. */
24875 uint16_t tx_cfa_action_a;
24876 /* Only valid for mode 2. */
24877 uint16_t rx_cfa_code_b;
24878 /* Only valid for mode 2. */
24879 uint16_t tx_cfa_action_b;
24880 uint8_t unused_0[7];
24882 * This field is used in Output records to indicate that the output
24883 * is completely written to RAM. This field should be read as '1'
24884 * to indicate that the output has been completely written.
24885 * When writing a command completion or response to an internal processor,
24886 * the order of writes has to be such that this field is written last.
24889 } __attribute__((packed));
24891 /**********************
24892 * hwrm_cfa_pair_free *
24893 **********************/
24896 /* hwrm_cfa_pair_free_input (size:384b/48B) */
24897 struct hwrm_cfa_pair_free_input {
24898 /* The HWRM command request type. */
24901 * The completion ring to send the completion event on. This should
24902 * be the NQ ID returned from the `nq_alloc` HWRM command.
24904 uint16_t cmpl_ring;
24906 * The sequence ID is used by the driver for tracking multiple
24907 * commands. This ID is treated as opaque data by the firmware and
24908 * the value is returned in the `hwrm_resp_hdr` upon completion.
24912 * The target ID of the command:
24913 * * 0x0-0xFFF8 - The function ID
24914 * * 0xFFF8-0xFFFE - Reserved for internal processors
24917 uint16_t target_id;
24919 * A physical address pointer pointing to a host buffer that the
24920 * command's response data will be written. This can be either a host
24921 * physical address (HPA) or a guest physical address (GPA) and must
24922 * point to a physically contiguous block of memory.
24924 uint64_t resp_addr;
24925 /* VF Pair name (32 byte string). */
24926 char pair_name[32];
24927 } __attribute__((packed));
24929 /* hwrm_cfa_pair_free_output (size:128b/16B) */
24930 struct hwrm_cfa_pair_free_output {
24931 /* The specific error status for the command. */
24932 uint16_t error_code;
24933 /* The HWRM command request type. */
24935 /* The sequence ID from the original command. */
24937 /* The length of the response data in number of bytes. */
24939 uint8_t unused_0[7];
24941 * This field is used in Output records to indicate that the output
24942 * is completely written to RAM. This field should be read as '1'
24943 * to indicate that the output has been completely written.
24944 * When writing a command completion or response to an internal processor,
24945 * the order of writes has to be such that this field is written last.
24948 } __attribute__((packed));
24950 /**********************
24951 * hwrm_cfa_pair_info *
24952 **********************/
24955 /* hwrm_cfa_pair_info_input (size:448b/56B) */
24956 struct hwrm_cfa_pair_info_input {
24957 /* The HWRM command request type. */
24960 * The completion ring to send the completion event on. This should
24961 * be the NQ ID returned from the `nq_alloc` HWRM command.
24963 uint16_t cmpl_ring;
24965 * The sequence ID is used by the driver for tracking multiple
24966 * commands. This ID is treated as opaque data by the firmware and
24967 * the value is returned in the `hwrm_resp_hdr` upon completion.
24971 * The target ID of the command:
24972 * * 0x0-0xFFF8 - The function ID
24973 * * 0xFFF8-0xFFFE - Reserved for internal processors
24976 uint16_t target_id;
24978 * A physical address pointer pointing to a host buffer that the
24979 * command's response data will be written. This can be either a host
24980 * physical address (HPA) or a guest physical address (GPA) and must
24981 * point to a physically contiguous block of memory.
24983 uint64_t resp_addr;
24985 /* If this flag is set, lookup by name else lookup by index. */
24986 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
24987 /* If this flag is set, lookup by PF id and VF id. */
24988 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
24989 /* Pair table index. */
24990 uint16_t pair_index;
24991 /* Pair pf index. */
24993 /* Pair vf index. */
24995 /* Pair name (32 byte string). */
24996 char pair_name[32];
24997 } __attribute__((packed));
24999 /* hwrm_cfa_pair_info_output (size:576b/72B) */
25000 struct hwrm_cfa_pair_info_output {
25001 /* The specific error status for the command. */
25002 uint16_t error_code;
25003 /* The HWRM command request type. */
25005 /* The sequence ID from the original command. */
25007 /* The length of the response data in number of bytes. */
25009 /* Pair table index. */
25010 uint16_t next_pair_index;
25011 /* Pair member a's fid. */
25013 /* Logical host number. */
25014 uint8_t host_a_index;
25015 /* Logical PF number. */
25016 uint8_t pf_a_index;
25017 /* Pair member a's Linux logical VF number. */
25018 uint16_t vf_a_index;
25020 uint16_t rx_cfa_code_a;
25021 /* Tx CFA action. */
25022 uint16_t tx_cfa_action_a;
25023 /* Pair member b's fid. */
25025 /* Logical host number. */
25026 uint8_t host_b_index;
25027 /* Logical PF number. */
25028 uint8_t pf_b_index;
25029 /* Pair member a's Linux logical VF number. */
25030 uint16_t vf_b_index;
25032 uint16_t rx_cfa_code_b;
25033 /* Tx CFA action. */
25034 uint16_t tx_cfa_action_b;
25035 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
25037 /* Pair between VF on local host with PF or VF on specified host. */
25038 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
25039 /* Pair between REP on local host with PF or VF on specified host. */
25040 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
25041 /* Pair between REP on local host with REP on specified host. */
25042 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
25043 /* Pair for the proxy interface. */
25044 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
25045 /* Pair for the PF interface. */
25046 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
25047 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
25048 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
25050 uint8_t pair_state;
25051 /* Pair has been allocated */
25052 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
25053 /* Both pair members are active */
25054 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
25055 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
25056 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
25057 /* Pair name (32 byte string). */
25058 char pair_name[32];
25059 uint8_t unused_0[7];
25061 * This field is used in Output records to indicate that the output
25062 * is completely written to RAM. This field should be read as '1'
25063 * to indicate that the output has been completely written.
25064 * When writing a command completion or response to an internal processor,
25065 * the order of writes has to be such that this field is written last.
25068 } __attribute__((packed));
25070 /**********************
25071 * hwrm_cfa_vfr_alloc *
25072 **********************/
25075 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
25076 struct hwrm_cfa_vfr_alloc_input {
25077 /* The HWRM command request type. */
25080 * The completion ring to send the completion event on. This should
25081 * be the NQ ID returned from the `nq_alloc` HWRM command.
25083 uint16_t cmpl_ring;
25085 * The sequence ID is used by the driver for tracking multiple
25086 * commands. This ID is treated as opaque data by the firmware and
25087 * the value is returned in the `hwrm_resp_hdr` upon completion.
25091 * The target ID of the command:
25092 * * 0x0-0xFFF8 - The function ID
25093 * * 0xFFF8-0xFFFE - Reserved for internal processors
25096 uint16_t target_id;
25098 * A physical address pointer pointing to a host buffer that the
25099 * command's response data will be written. This can be either a host
25100 * physical address (HPA) or a guest physical address (GPA) and must
25101 * point to a physically contiguous block of memory.
25103 uint64_t resp_addr;
25104 /* Logical VF number (range: 0 -> MAX_VFS -1). */
25107 * This field is reserved for the future use.
25108 * It shall be set to 0.
25111 uint8_t unused_0[4];
25112 /* VF Representor name (32 byte string). */
25114 } __attribute__((packed));
25116 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
25117 struct hwrm_cfa_vfr_alloc_output {
25118 /* The specific error status for the command. */
25119 uint16_t error_code;
25120 /* The HWRM command request type. */
25122 /* The sequence ID from the original command. */
25124 /* The length of the response data in number of bytes. */
25127 uint16_t rx_cfa_code;
25128 /* Tx CFA action. */
25129 uint16_t tx_cfa_action;
25130 uint8_t unused_0[3];
25132 * This field is used in Output records to indicate that the output
25133 * is completely written to RAM. This field should be read as '1'
25134 * to indicate that the output has been completely written.
25135 * When writing a command completion or response to an internal processor,
25136 * the order of writes has to be such that this field is written last.
25139 } __attribute__((packed));
25141 /*********************
25142 * hwrm_cfa_vfr_free *
25143 *********************/
25146 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
25147 struct hwrm_cfa_vfr_free_input {
25148 /* The HWRM command request type. */
25151 * The completion ring to send the completion event on. This should
25152 * be the NQ ID returned from the `nq_alloc` HWRM command.
25154 uint16_t cmpl_ring;
25156 * The sequence ID is used by the driver for tracking multiple
25157 * commands. This ID is treated as opaque data by the firmware and
25158 * the value is returned in the `hwrm_resp_hdr` upon completion.
25162 * The target ID of the command:
25163 * * 0x0-0xFFF8 - The function ID
25164 * * 0xFFF8-0xFFFE - Reserved for internal processors
25167 uint16_t target_id;
25169 * A physical address pointer pointing to a host buffer that the
25170 * command's response data will be written. This can be either a host
25171 * physical address (HPA) or a guest physical address (GPA) and must
25172 * point to a physically contiguous block of memory.
25174 uint64_t resp_addr;
25175 /* VF Representor name (32 byte string). */
25177 } __attribute__((packed));
25179 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
25180 struct hwrm_cfa_vfr_free_output {
25181 /* The specific error status for the command. */
25182 uint16_t error_code;
25183 /* The HWRM command request type. */
25185 /* The sequence ID from the original command. */
25187 /* The length of the response data in number of bytes. */
25189 uint8_t unused_0[7];
25191 * This field is used in Output records to indicate that the output
25192 * is completely written to RAM. This field should be read as '1'
25193 * to indicate that the output has been completely written.
25194 * When writing a command completion or response to an internal processor,
25195 * the order of writes has to be such that this field is written last.
25198 } __attribute__((packed));
25200 /******************************
25201 * hwrm_tunnel_dst_port_query *
25202 ******************************/
25205 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
25206 struct hwrm_tunnel_dst_port_query_input {
25207 /* The HWRM command request type. */
25210 * The completion ring to send the completion event on. This should
25211 * be the NQ ID returned from the `nq_alloc` HWRM command.
25213 uint16_t cmpl_ring;
25215 * The sequence ID is used by the driver for tracking multiple
25216 * commands. This ID is treated as opaque data by the firmware and
25217 * the value is returned in the `hwrm_resp_hdr` upon completion.
25221 * The target ID of the command:
25222 * * 0x0-0xFFF8 - The function ID
25223 * * 0xFFF8-0xFFFE - Reserved for internal processors
25226 uint16_t target_id;
25228 * A physical address pointer pointing to a host buffer that the
25229 * command's response data will be written. This can be either a host
25230 * physical address (HPA) or a guest physical address (GPA) and must
25231 * point to a physically contiguous block of memory.
25233 uint64_t resp_addr;
25235 uint8_t tunnel_type;
25236 /* Virtual eXtensible Local Area Network (VXLAN) */
25237 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
25239 /* Generic Network Virtualization Encapsulation (Geneve) */
25240 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
25242 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25243 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25245 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25246 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25248 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
25249 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
25250 uint8_t unused_0[7];
25251 } __attribute__((packed));
25253 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
25254 struct hwrm_tunnel_dst_port_query_output {
25255 /* The specific error status for the command. */
25256 uint16_t error_code;
25257 /* The HWRM command request type. */
25259 /* The sequence ID from the original command. */
25261 /* The length of the response data in number of bytes. */
25264 * This field represents the identifier of L4 destination port
25265 * used for the given tunnel type. This field is valid for
25266 * specific tunnel types that use layer 4 (e.g. UDP)
25267 * transports for tunneling.
25269 uint16_t tunnel_dst_port_id;
25271 * This field represents the value of L4 destination port
25272 * identified by tunnel_dst_port_id. This field is valid for
25273 * specific tunnel types that use layer 4 (e.g. UDP)
25274 * transports for tunneling.
25275 * This field is in network byte order.
25277 * A value of 0 means that the destination port is not
25280 uint16_t tunnel_dst_port_val;
25281 uint8_t unused_0[3];
25283 * This field is used in Output records to indicate that the output
25284 * is completely written to RAM. This field should be read as '1'
25285 * to indicate that the output has been completely written.
25286 * When writing a command completion or response to an internal processor,
25287 * the order of writes has to be such that this field is written last.
25290 } __attribute__((packed));
25292 /******************************
25293 * hwrm_tunnel_dst_port_alloc *
25294 ******************************/
25297 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
25298 struct hwrm_tunnel_dst_port_alloc_input {
25299 /* The HWRM command request type. */
25302 * The completion ring to send the completion event on. This should
25303 * be the NQ ID returned from the `nq_alloc` HWRM command.
25305 uint16_t cmpl_ring;
25307 * The sequence ID is used by the driver for tracking multiple
25308 * commands. This ID is treated as opaque data by the firmware and
25309 * the value is returned in the `hwrm_resp_hdr` upon completion.
25313 * The target ID of the command:
25314 * * 0x0-0xFFF8 - The function ID
25315 * * 0xFFF8-0xFFFE - Reserved for internal processors
25318 uint16_t target_id;
25320 * A physical address pointer pointing to a host buffer that the
25321 * command's response data will be written. This can be either a host
25322 * physical address (HPA) or a guest physical address (GPA) and must
25323 * point to a physically contiguous block of memory.
25325 uint64_t resp_addr;
25327 uint8_t tunnel_type;
25328 /* Virtual eXtensible Local Area Network (VXLAN) */
25329 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25331 /* Generic Network Virtualization Encapsulation (Geneve) */
25332 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25334 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25335 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25337 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25338 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25340 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25341 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
25344 * This field represents the value of L4 destination port used
25345 * for the given tunnel type. This field is valid for
25346 * specific tunnel types that use layer 4 (e.g. UDP)
25347 * transports for tunneling.
25349 * This field is in network byte order.
25351 * A value of 0 shall fail the command.
25353 uint16_t tunnel_dst_port_val;
25354 uint8_t unused_1[4];
25355 } __attribute__((packed));
25357 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
25358 struct hwrm_tunnel_dst_port_alloc_output {
25359 /* The specific error status for the command. */
25360 uint16_t error_code;
25361 /* The HWRM command request type. */
25363 /* The sequence ID from the original command. */
25365 /* The length of the response data in number of bytes. */
25368 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
25369 * types that has l4 destination port parameters.
25371 uint16_t tunnel_dst_port_id;
25372 uint8_t unused_0[5];
25374 * This field is used in Output records to indicate that the output
25375 * is completely written to RAM. This field should be read as '1'
25376 * to indicate that the output has been completely written.
25377 * When writing a command completion or response to an internal processor,
25378 * the order of writes has to be such that this field is written last.
25381 } __attribute__((packed));
25383 /*****************************
25384 * hwrm_tunnel_dst_port_free *
25385 *****************************/
25388 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
25389 struct hwrm_tunnel_dst_port_free_input {
25390 /* The HWRM command request type. */
25393 * The completion ring to send the completion event on. This should
25394 * be the NQ ID returned from the `nq_alloc` HWRM command.
25396 uint16_t cmpl_ring;
25398 * The sequence ID is used by the driver for tracking multiple
25399 * commands. This ID is treated as opaque data by the firmware and
25400 * the value is returned in the `hwrm_resp_hdr` upon completion.
25404 * The target ID of the command:
25405 * * 0x0-0xFFF8 - The function ID
25406 * * 0xFFF8-0xFFFE - Reserved for internal processors
25409 uint16_t target_id;
25411 * A physical address pointer pointing to a host buffer that the
25412 * command's response data will be written. This can be either a host
25413 * physical address (HPA) or a guest physical address (GPA) and must
25414 * point to a physically contiguous block of memory.
25416 uint64_t resp_addr;
25418 uint8_t tunnel_type;
25419 /* Virtual eXtensible Local Area Network (VXLAN) */
25420 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
25422 /* Generic Network Virtualization Encapsulation (Geneve) */
25423 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
25425 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25426 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25428 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25429 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25431 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
25432 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
25435 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
25436 * types that has l4 destination port parameters.
25438 uint16_t tunnel_dst_port_id;
25439 uint8_t unused_1[4];
25440 } __attribute__((packed));
25442 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
25443 struct hwrm_tunnel_dst_port_free_output {
25444 /* The specific error status for the command. */
25445 uint16_t error_code;
25446 /* The HWRM command request type. */
25448 /* The sequence ID from the original command. */
25450 /* The length of the response data in number of bytes. */
25452 uint8_t unused_1[7];
25454 * This field is used in Output records to indicate that the output
25455 * is completely written to RAM. This field should be read as '1'
25456 * to indicate that the output has been completely written.
25457 * When writing a command completion or response to an internal processor,
25458 * the order of writes has to be such that this field is written last.
25461 } __attribute__((packed));
25463 /* ctx_hw_stats (size:1280b/160B) */
25464 struct ctx_hw_stats {
25465 /* Number of received unicast packets */
25466 uint64_t rx_ucast_pkts;
25467 /* Number of received multicast packets */
25468 uint64_t rx_mcast_pkts;
25469 /* Number of received broadcast packets */
25470 uint64_t rx_bcast_pkts;
25471 /* Number of discarded packets on received path */
25472 uint64_t rx_discard_pkts;
25473 /* Number of dropped packets on received path */
25474 uint64_t rx_drop_pkts;
25475 /* Number of received bytes for unicast traffic */
25476 uint64_t rx_ucast_bytes;
25477 /* Number of received bytes for multicast traffic */
25478 uint64_t rx_mcast_bytes;
25479 /* Number of received bytes for broadcast traffic */
25480 uint64_t rx_bcast_bytes;
25481 /* Number of transmitted unicast packets */
25482 uint64_t tx_ucast_pkts;
25483 /* Number of transmitted multicast packets */
25484 uint64_t tx_mcast_pkts;
25485 /* Number of transmitted broadcast packets */
25486 uint64_t tx_bcast_pkts;
25487 /* Number of discarded packets on transmit path */
25488 uint64_t tx_discard_pkts;
25489 /* Number of dropped packets on transmit path */
25490 uint64_t tx_drop_pkts;
25491 /* Number of transmitted bytes for unicast traffic */
25492 uint64_t tx_ucast_bytes;
25493 /* Number of transmitted bytes for multicast traffic */
25494 uint64_t tx_mcast_bytes;
25495 /* Number of transmitted bytes for broadcast traffic */
25496 uint64_t tx_bcast_bytes;
25497 /* Number of TPA packets */
25499 /* Number of TPA bytes */
25500 uint64_t tpa_bytes;
25501 /* Number of TPA events */
25502 uint64_t tpa_events;
25503 /* Number of TPA aborts */
25504 uint64_t tpa_aborts;
25505 } __attribute__((packed));
25507 /***********************
25508 * hwrm_stat_ctx_alloc *
25509 ***********************/
25512 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
25513 struct hwrm_stat_ctx_alloc_input {
25514 /* The HWRM command request type. */
25517 * The completion ring to send the completion event on. This should
25518 * be the NQ ID returned from the `nq_alloc` HWRM command.
25520 uint16_t cmpl_ring;
25522 * The sequence ID is used by the driver for tracking multiple
25523 * commands. This ID is treated as opaque data by the firmware and
25524 * the value is returned in the `hwrm_resp_hdr` upon completion.
25528 * The target ID of the command:
25529 * * 0x0-0xFFF8 - The function ID
25530 * * 0xFFF8-0xFFFE - Reserved for internal processors
25533 uint16_t target_id;
25535 * A physical address pointer pointing to a host buffer that the
25536 * command's response data will be written. This can be either a host
25537 * physical address (HPA) or a guest physical address (GPA) and must
25538 * point to a physically contiguous block of memory.
25540 uint64_t resp_addr;
25541 /* This is the address for statistic block. */
25542 uint64_t stats_dma_addr;
25544 * The statistic block update period in ms.
25545 * e.g. 250ms, 500ms, 750ms, 1000ms.
25546 * If update_period_ms is 0, then the stats update
25547 * shall be never done and the DMA address shall not be used.
25548 * In this case, the stat block can only be read by
25549 * hwrm_stat_ctx_query command.
25551 uint32_t update_period_ms;
25553 * This field is used to specify statistics context specific
25554 * configuration flags.
25556 uint8_t stat_ctx_flags;
25558 * When this bit is set to '1', the statistics context shall be
25559 * allocated for RoCE traffic only. In this case, traffic other
25560 * than offloaded RoCE traffic shall not be included in this
25561 * statistic context.
25562 * When this bit is set to '0', the statistics context shall be
25563 * used for the network traffic other than offloaded RoCE traffic.
25565 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
25566 uint8_t unused_0[3];
25567 } __attribute__((packed));
25569 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
25570 struct hwrm_stat_ctx_alloc_output {
25571 /* The specific error status for the command. */
25572 uint16_t error_code;
25573 /* The HWRM command request type. */
25575 /* The sequence ID from the original command. */
25577 /* The length of the response data in number of bytes. */
25579 /* This is the statistics context ID value. */
25580 uint32_t stat_ctx_id;
25581 uint8_t unused_0[3];
25583 * This field is used in Output records to indicate that the output
25584 * is completely written to RAM. This field should be read as '1'
25585 * to indicate that the output has been completely written.
25586 * When writing a command completion or response to an internal processor,
25587 * the order of writes has to be such that this field is written last.
25590 } __attribute__((packed));
25592 /**********************
25593 * hwrm_stat_ctx_free *
25594 **********************/
25597 /* hwrm_stat_ctx_free_input (size:192b/24B) */
25598 struct hwrm_stat_ctx_free_input {
25599 /* The HWRM command request type. */
25602 * The completion ring to send the completion event on. This should
25603 * be the NQ ID returned from the `nq_alloc` HWRM command.
25605 uint16_t cmpl_ring;
25607 * The sequence ID is used by the driver for tracking multiple
25608 * commands. This ID is treated as opaque data by the firmware and
25609 * the value is returned in the `hwrm_resp_hdr` upon completion.
25613 * The target ID of the command:
25614 * * 0x0-0xFFF8 - The function ID
25615 * * 0xFFF8-0xFFFE - Reserved for internal processors
25618 uint16_t target_id;
25620 * A physical address pointer pointing to a host buffer that the
25621 * command's response data will be written. This can be either a host
25622 * physical address (HPA) or a guest physical address (GPA) and must
25623 * point to a physically contiguous block of memory.
25625 uint64_t resp_addr;
25626 /* ID of the statistics context that is being queried. */
25627 uint32_t stat_ctx_id;
25628 uint8_t unused_0[4];
25629 } __attribute__((packed));
25631 /* hwrm_stat_ctx_free_output (size:128b/16B) */
25632 struct hwrm_stat_ctx_free_output {
25633 /* The specific error status for the command. */
25634 uint16_t error_code;
25635 /* The HWRM command request type. */
25637 /* The sequence ID from the original command. */
25639 /* The length of the response data in number of bytes. */
25641 /* This is the statistics context ID value. */
25642 uint32_t stat_ctx_id;
25643 uint8_t unused_0[3];
25645 * This field is used in Output records to indicate that the output
25646 * is completely written to RAM. This field should be read as '1'
25647 * to indicate that the output has been completely written.
25648 * When writing a command completion or response to an internal processor,
25649 * the order of writes has to be such that this field is written last.
25652 } __attribute__((packed));
25654 /***********************
25655 * hwrm_stat_ctx_query *
25656 ***********************/
25659 /* hwrm_stat_ctx_query_input (size:192b/24B) */
25660 struct hwrm_stat_ctx_query_input {
25661 /* The HWRM command request type. */
25664 * The completion ring to send the completion event on. This should
25665 * be the NQ ID returned from the `nq_alloc` HWRM command.
25667 uint16_t cmpl_ring;
25669 * The sequence ID is used by the driver for tracking multiple
25670 * commands. This ID is treated as opaque data by the firmware and
25671 * the value is returned in the `hwrm_resp_hdr` upon completion.
25675 * The target ID of the command:
25676 * * 0x0-0xFFF8 - The function ID
25677 * * 0xFFF8-0xFFFE - Reserved for internal processors
25680 uint16_t target_id;
25682 * A physical address pointer pointing to a host buffer that the
25683 * command's response data will be written. This can be either a host
25684 * physical address (HPA) or a guest physical address (GPA) and must
25685 * point to a physically contiguous block of memory.
25687 uint64_t resp_addr;
25688 /* ID of the statistics context that is being queried. */
25689 uint32_t stat_ctx_id;
25690 uint8_t unused_0[4];
25691 } __attribute__((packed));
25693 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
25694 struct hwrm_stat_ctx_query_output {
25695 /* The specific error status for the command. */
25696 uint16_t error_code;
25697 /* The HWRM command request type. */
25699 /* The sequence ID from the original command. */
25701 /* The length of the response data in number of bytes. */
25703 /* Number of transmitted unicast packets */
25704 uint64_t tx_ucast_pkts;
25705 /* Number of transmitted multicast packets */
25706 uint64_t tx_mcast_pkts;
25707 /* Number of transmitted broadcast packets */
25708 uint64_t tx_bcast_pkts;
25709 /* Number of transmitted packets with error */
25710 uint64_t tx_err_pkts;
25711 /* Number of dropped packets on transmit path */
25712 uint64_t tx_drop_pkts;
25713 /* Number of transmitted bytes for unicast traffic */
25714 uint64_t tx_ucast_bytes;
25715 /* Number of transmitted bytes for multicast traffic */
25716 uint64_t tx_mcast_bytes;
25717 /* Number of transmitted bytes for broadcast traffic */
25718 uint64_t tx_bcast_bytes;
25719 /* Number of received unicast packets */
25720 uint64_t rx_ucast_pkts;
25721 /* Number of received multicast packets */
25722 uint64_t rx_mcast_pkts;
25723 /* Number of received broadcast packets */
25724 uint64_t rx_bcast_pkts;
25725 /* Number of received packets with error */
25726 uint64_t rx_err_pkts;
25727 /* Number of dropped packets on received path */
25728 uint64_t rx_drop_pkts;
25729 /* Number of received bytes for unicast traffic */
25730 uint64_t rx_ucast_bytes;
25731 /* Number of received bytes for multicast traffic */
25732 uint64_t rx_mcast_bytes;
25733 /* Number of received bytes for broadcast traffic */
25734 uint64_t rx_bcast_bytes;
25735 /* Number of aggregated unicast packets */
25736 uint64_t rx_agg_pkts;
25737 /* Number of aggregated unicast bytes */
25738 uint64_t rx_agg_bytes;
25739 /* Number of aggregation events */
25740 uint64_t rx_agg_events;
25741 /* Number of aborted aggregations */
25742 uint64_t rx_agg_aborts;
25743 uint8_t unused_0[7];
25745 * This field is used in Output records to indicate that the output
25746 * is completely written to RAM. This field should be read as '1'
25747 * to indicate that the output has been completely written.
25748 * When writing a command completion or response to an internal processor,
25749 * the order of writes has to be such that this field is written last.
25752 } __attribute__((packed));
25754 /***************************
25755 * hwrm_stat_ctx_clr_stats *
25756 ***************************/
25759 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
25760 struct hwrm_stat_ctx_clr_stats_input {
25761 /* The HWRM command request type. */
25764 * The completion ring to send the completion event on. This should
25765 * be the NQ ID returned from the `nq_alloc` HWRM command.
25767 uint16_t cmpl_ring;
25769 * The sequence ID is used by the driver for tracking multiple
25770 * commands. This ID is treated as opaque data by the firmware and
25771 * the value is returned in the `hwrm_resp_hdr` upon completion.
25775 * The target ID of the command:
25776 * * 0x0-0xFFF8 - The function ID
25777 * * 0xFFF8-0xFFFE - Reserved for internal processors
25780 uint16_t target_id;
25782 * A physical address pointer pointing to a host buffer that the
25783 * command's response data will be written. This can be either a host
25784 * physical address (HPA) or a guest physical address (GPA) and must
25785 * point to a physically contiguous block of memory.
25787 uint64_t resp_addr;
25788 /* ID of the statistics context that is being queried. */
25789 uint32_t stat_ctx_id;
25790 uint8_t unused_0[4];
25791 } __attribute__((packed));
25793 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
25794 struct hwrm_stat_ctx_clr_stats_output {
25795 /* The specific error status for the command. */
25796 uint16_t error_code;
25797 /* The HWRM command request type. */
25799 /* The sequence ID from the original command. */
25801 /* The length of the response data in number of bytes. */
25803 uint8_t unused_0[7];
25805 * This field is used in Output records to indicate that the output
25806 * is completely written to RAM. This field should be read as '1'
25807 * to indicate that the output has been completely written.
25808 * When writing a command completion or response to an internal processor,
25809 * the order of writes has to be such that this field is written last.
25812 } __attribute__((packed));
25814 /********************
25815 * hwrm_pcie_qstats *
25816 ********************/
25819 /* hwrm_pcie_qstats_input (size:256b/32B) */
25820 struct hwrm_pcie_qstats_input {
25821 /* The HWRM command request type. */
25824 * The completion ring to send the completion event on. This should
25825 * be the NQ ID returned from the `nq_alloc` HWRM command.
25827 uint16_t cmpl_ring;
25829 * The sequence ID is used by the driver for tracking multiple
25830 * commands. This ID is treated as opaque data by the firmware and
25831 * the value is returned in the `hwrm_resp_hdr` upon completion.
25835 * The target ID of the command:
25836 * * 0x0-0xFFF8 - The function ID
25837 * * 0xFFF8-0xFFFE - Reserved for internal processors
25840 uint16_t target_id;
25842 * A physical address pointer pointing to a host buffer that the
25843 * command's response data will be written. This can be either a host
25844 * physical address (HPA) or a guest physical address (GPA) and must
25845 * point to a physically contiguous block of memory.
25847 uint64_t resp_addr;
25849 * The size of PCIe statistics block in bytes.
25850 * Firmware will DMA the PCIe statistics to
25851 * the host with this field size in the response.
25853 uint16_t pcie_stat_size;
25854 uint8_t unused_0[6];
25856 * This is the host address where
25857 * PCIe statistics will be stored
25859 uint64_t pcie_stat_host_addr;
25860 } __attribute__((packed));
25862 /* hwrm_pcie_qstats_output (size:128b/16B) */
25863 struct hwrm_pcie_qstats_output {
25864 /* The specific error status for the command. */
25865 uint16_t error_code;
25866 /* The HWRM command request type. */
25868 /* The sequence ID from the original command. */
25870 /* The length of the response data in number of bytes. */
25872 /* The size of PCIe statistics block in bytes. */
25873 uint16_t pcie_stat_size;
25874 uint8_t unused_0[5];
25876 * This field is used in Output records to indicate that the output
25877 * is completely written to RAM. This field should be read as '1'
25878 * to indicate that the output has been completely written.
25879 * When writing a command completion or response to an internal processor,
25880 * the order of writes has to be such that this field is written last.
25883 } __attribute__((packed));
25885 /* Port Tx Statistics Formats */
25886 /* tx_port_stats (size:3264b/408B) */
25887 struct tx_port_stats {
25888 /* Total Number of 64 Bytes frames transmitted */
25889 uint64_t tx_64b_frames;
25890 /* Total Number of 65-127 Bytes frames transmitted */
25891 uint64_t tx_65b_127b_frames;
25892 /* Total Number of 128-255 Bytes frames transmitted */
25893 uint64_t tx_128b_255b_frames;
25894 /* Total Number of 256-511 Bytes frames transmitted */
25895 uint64_t tx_256b_511b_frames;
25896 /* Total Number of 512-1023 Bytes frames transmitted */
25897 uint64_t tx_512b_1023b_frames;
25898 /* Total Number of 1024-1518 Bytes frames transmitted */
25899 uint64_t tx_1024b_1518_frames;
25901 * Total Number of each good VLAN (exludes FCS errors)
25902 * frame transmitted which is 1519 to 1522 bytes in length
25903 * inclusive (excluding framing bits but including FCS bytes).
25905 uint64_t tx_good_vlan_frames;
25906 /* Total Number of 1519-2047 Bytes frames transmitted */
25907 uint64_t tx_1519b_2047_frames;
25908 /* Total Number of 2048-4095 Bytes frames transmitted */
25909 uint64_t tx_2048b_4095b_frames;
25910 /* Total Number of 4096-9216 Bytes frames transmitted */
25911 uint64_t tx_4096b_9216b_frames;
25912 /* Total Number of 9217-16383 Bytes frames transmitted */
25913 uint64_t tx_9217b_16383b_frames;
25914 /* Total Number of good frames transmitted */
25915 uint64_t tx_good_frames;
25916 /* Total Number of frames transmitted */
25917 uint64_t tx_total_frames;
25918 /* Total number of unicast frames transmitted */
25919 uint64_t tx_ucast_frames;
25920 /* Total number of multicast frames transmitted */
25921 uint64_t tx_mcast_frames;
25922 /* Total number of broadcast frames transmitted */
25923 uint64_t tx_bcast_frames;
25924 /* Total number of PAUSE control frames transmitted */
25925 uint64_t tx_pause_frames;
25927 * Total number of PFC/per-priority PAUSE
25928 * control frames transmitted
25930 uint64_t tx_pfc_frames;
25931 /* Total number of jabber frames transmitted */
25932 uint64_t tx_jabber_frames;
25933 /* Total number of frames transmitted with FCS error */
25934 uint64_t tx_fcs_err_frames;
25935 /* Total number of control frames transmitted */
25936 uint64_t tx_control_frames;
25937 /* Total number of over-sized frames transmitted */
25938 uint64_t tx_oversz_frames;
25939 /* Total number of frames with single deferral */
25940 uint64_t tx_single_dfrl_frames;
25941 /* Total number of frames with multiple deferrals */
25942 uint64_t tx_multi_dfrl_frames;
25943 /* Total number of frames with single collision */
25944 uint64_t tx_single_coll_frames;
25945 /* Total number of frames with multiple collisions */
25946 uint64_t tx_multi_coll_frames;
25947 /* Total number of frames with late collisions */
25948 uint64_t tx_late_coll_frames;
25949 /* Total number of frames with excessive collisions */
25950 uint64_t tx_excessive_coll_frames;
25951 /* Total number of fragmented frames transmitted */
25952 uint64_t tx_frag_frames;
25953 /* Total number of transmit errors */
25955 /* Total number of single VLAN tagged frames transmitted */
25956 uint64_t tx_tagged_frames;
25957 /* Total number of double VLAN tagged frames transmitted */
25958 uint64_t tx_dbl_tagged_frames;
25959 /* Total number of runt frames transmitted */
25960 uint64_t tx_runt_frames;
25961 /* Total number of TX FIFO under runs */
25962 uint64_t tx_fifo_underruns;
25964 * Total number of PFC frames with PFC enabled bit for
25965 * Pri 0 transmitted
25967 uint64_t tx_pfc_ena_frames_pri0;
25969 * Total number of PFC frames with PFC enabled bit for
25970 * Pri 1 transmitted
25972 uint64_t tx_pfc_ena_frames_pri1;
25974 * Total number of PFC frames with PFC enabled bit for
25975 * Pri 2 transmitted
25977 uint64_t tx_pfc_ena_frames_pri2;
25979 * Total number of PFC frames with PFC enabled bit for
25980 * Pri 3 transmitted
25982 uint64_t tx_pfc_ena_frames_pri3;
25984 * Total number of PFC frames with PFC enabled bit for
25985 * Pri 4 transmitted
25987 uint64_t tx_pfc_ena_frames_pri4;
25989 * Total number of PFC frames with PFC enabled bit for
25990 * Pri 5 transmitted
25992 uint64_t tx_pfc_ena_frames_pri5;
25994 * Total number of PFC frames with PFC enabled bit for
25995 * Pri 6 transmitted
25997 uint64_t tx_pfc_ena_frames_pri6;
25999 * Total number of PFC frames with PFC enabled bit for
26000 * Pri 7 transmitted
26002 uint64_t tx_pfc_ena_frames_pri7;
26003 /* Total number of EEE LPI Events on TX */
26004 uint64_t tx_eee_lpi_events;
26005 /* EEE LPI Duration Counter on TX */
26006 uint64_t tx_eee_lpi_duration;
26008 * Total number of Link Level Flow Control (LLFC) messages
26011 uint64_t tx_llfc_logical_msgs;
26012 /* Total number of HCFC messages transmitted */
26013 uint64_t tx_hcfc_msgs;
26014 /* Total number of TX collisions */
26015 uint64_t tx_total_collisions;
26016 /* Total number of transmitted bytes */
26018 /* Total number of end-to-end HOL frames */
26019 uint64_t tx_xthol_frames;
26020 /* Total Tx Drops per Port reported by STATS block */
26021 uint64_t tx_stat_discard;
26022 /* Total Tx Error Drops per Port reported by STATS block */
26023 uint64_t tx_stat_error;
26024 } __attribute__((packed));
26026 /* Port Rx Statistics Formats */
26027 /* rx_port_stats (size:4224b/528B) */
26028 struct rx_port_stats {
26029 /* Total Number of 64 Bytes frames received */
26030 uint64_t rx_64b_frames;
26031 /* Total Number of 65-127 Bytes frames received */
26032 uint64_t rx_65b_127b_frames;
26033 /* Total Number of 128-255 Bytes frames received */
26034 uint64_t rx_128b_255b_frames;
26035 /* Total Number of 256-511 Bytes frames received */
26036 uint64_t rx_256b_511b_frames;
26037 /* Total Number of 512-1023 Bytes frames received */
26038 uint64_t rx_512b_1023b_frames;
26039 /* Total Number of 1024-1518 Bytes frames received */
26040 uint64_t rx_1024b_1518_frames;
26042 * Total Number of each good VLAN (exludes FCS errors)
26043 * frame received which is 1519 to 1522 bytes in length
26044 * inclusive (excluding framing bits but including FCS bytes).
26046 uint64_t rx_good_vlan_frames;
26047 /* Total Number of 1519-2047 Bytes frames received */
26048 uint64_t rx_1519b_2047b_frames;
26049 /* Total Number of 2048-4095 Bytes frames received */
26050 uint64_t rx_2048b_4095b_frames;
26051 /* Total Number of 4096-9216 Bytes frames received */
26052 uint64_t rx_4096b_9216b_frames;
26053 /* Total Number of 9217-16383 Bytes frames received */
26054 uint64_t rx_9217b_16383b_frames;
26055 /* Total number of frames received */
26056 uint64_t rx_total_frames;
26057 /* Total number of unicast frames received */
26058 uint64_t rx_ucast_frames;
26059 /* Total number of multicast frames received */
26060 uint64_t rx_mcast_frames;
26061 /* Total number of broadcast frames received */
26062 uint64_t rx_bcast_frames;
26063 /* Total number of received frames with FCS error */
26064 uint64_t rx_fcs_err_frames;
26065 /* Total number of control frames received */
26066 uint64_t rx_ctrl_frames;
26067 /* Total number of PAUSE frames received */
26068 uint64_t rx_pause_frames;
26069 /* Total number of PFC frames received */
26070 uint64_t rx_pfc_frames;
26072 * Total number of frames received with an unsupported
26075 uint64_t rx_unsupported_opcode_frames;
26077 * Total number of frames received with an unsupported
26078 * DA for pause and PFC
26080 uint64_t rx_unsupported_da_pausepfc_frames;
26081 /* Total number of frames received with an unsupported SA */
26082 uint64_t rx_wrong_sa_frames;
26083 /* Total number of received packets with alignment error */
26084 uint64_t rx_align_err_frames;
26085 /* Total number of received frames with out-of-range length */
26086 uint64_t rx_oor_len_frames;
26087 /* Total number of received frames with error termination */
26088 uint64_t rx_code_err_frames;
26090 * Total number of received frames with a false carrier is
26091 * detected during idle, as defined by RX_ER samples active
26092 * and RXD is 0xE. The event is reported along with the
26093 * statistics generated on the next received frame. Only
26094 * one false carrier condition can be detected and logged
26097 * Carrier event, valid for 10M/100M speed modes only.
26099 uint64_t rx_false_carrier_frames;
26100 /* Total number of over-sized frames received */
26101 uint64_t rx_ovrsz_frames;
26102 /* Total number of jabber packets received */
26103 uint64_t rx_jbr_frames;
26104 /* Total number of received frames with MTU error */
26105 uint64_t rx_mtu_err_frames;
26106 /* Total number of received frames with CRC match */
26107 uint64_t rx_match_crc_frames;
26108 /* Total number of frames received promiscuously */
26109 uint64_t rx_promiscuous_frames;
26111 * Total number of received frames with one or two VLAN
26114 uint64_t rx_tagged_frames;
26115 /* Total number of received frames with two VLAN tags */
26116 uint64_t rx_double_tagged_frames;
26117 /* Total number of truncated frames received */
26118 uint64_t rx_trunc_frames;
26119 /* Total number of good frames (without errors) received */
26120 uint64_t rx_good_frames;
26122 * Total number of received PFC frames with transition from
26123 * XON to XOFF on Pri 0
26125 uint64_t rx_pfc_xon2xoff_frames_pri0;
26127 * Total number of received PFC frames with transition from
26128 * XON to XOFF on Pri 1
26130 uint64_t rx_pfc_xon2xoff_frames_pri1;
26132 * Total number of received PFC frames with transition from
26133 * XON to XOFF on Pri 2
26135 uint64_t rx_pfc_xon2xoff_frames_pri2;
26137 * Total number of received PFC frames with transition from
26138 * XON to XOFF on Pri 3
26140 uint64_t rx_pfc_xon2xoff_frames_pri3;
26142 * Total number of received PFC frames with transition from
26143 * XON to XOFF on Pri 4
26145 uint64_t rx_pfc_xon2xoff_frames_pri4;
26147 * Total number of received PFC frames with transition from
26148 * XON to XOFF on Pri 5
26150 uint64_t rx_pfc_xon2xoff_frames_pri5;
26152 * Total number of received PFC frames with transition from
26153 * XON to XOFF on Pri 6
26155 uint64_t rx_pfc_xon2xoff_frames_pri6;
26157 * Total number of received PFC frames with transition from
26158 * XON to XOFF on Pri 7
26160 uint64_t rx_pfc_xon2xoff_frames_pri7;
26162 * Total number of received PFC frames with PFC enabled
26165 uint64_t rx_pfc_ena_frames_pri0;
26167 * Total number of received PFC frames with PFC enabled
26170 uint64_t rx_pfc_ena_frames_pri1;
26172 * Total number of received PFC frames with PFC enabled
26175 uint64_t rx_pfc_ena_frames_pri2;
26177 * Total number of received PFC frames with PFC enabled
26180 uint64_t rx_pfc_ena_frames_pri3;
26182 * Total number of received PFC frames with PFC enabled
26185 uint64_t rx_pfc_ena_frames_pri4;
26187 * Total number of received PFC frames with PFC enabled
26190 uint64_t rx_pfc_ena_frames_pri5;
26192 * Total number of received PFC frames with PFC enabled
26195 uint64_t rx_pfc_ena_frames_pri6;
26197 * Total number of received PFC frames with PFC enabled
26200 uint64_t rx_pfc_ena_frames_pri7;
26201 /* Total Number of frames received with SCH CRC error */
26202 uint64_t rx_sch_crc_err_frames;
26203 /* Total Number of under-sized frames received */
26204 uint64_t rx_undrsz_frames;
26205 /* Total Number of fragmented frames received */
26206 uint64_t rx_frag_frames;
26207 /* Total number of RX EEE LPI Events */
26208 uint64_t rx_eee_lpi_events;
26209 /* EEE LPI Duration Counter on RX */
26210 uint64_t rx_eee_lpi_duration;
26212 * Total number of physical type Link Level Flow Control
26213 * (LLFC) messages received
26215 uint64_t rx_llfc_physical_msgs;
26217 * Total number of logical type Link Level Flow Control
26218 * (LLFC) messages received
26220 uint64_t rx_llfc_logical_msgs;
26222 * Total number of logical type Link Level Flow Control
26223 * (LLFC) messages received with CRC error
26225 uint64_t rx_llfc_msgs_with_crc_err;
26226 /* Total number of HCFC messages received */
26227 uint64_t rx_hcfc_msgs;
26228 /* Total number of HCFC messages received with CRC error */
26229 uint64_t rx_hcfc_msgs_with_crc_err;
26230 /* Total number of received bytes */
26232 /* Total number of bytes received in runt frames */
26233 uint64_t rx_runt_bytes;
26234 /* Total number of runt frames received */
26235 uint64_t rx_runt_frames;
26236 /* Total Rx Discards per Port reported by STATS block */
26237 uint64_t rx_stat_discard;
26238 uint64_t rx_stat_err;
26239 } __attribute__((packed));
26241 /* Port Rx Statistics extended Formats */
26242 /* rx_port_stats_ext (size:320b/40B) */
26243 struct rx_port_stats_ext {
26244 /* Number of times link state changed to down */
26245 uint64_t link_down_events;
26246 /* Number of times the idle rings with pause bit are found */
26247 uint64_t continuous_pause_events;
26248 /* Number of times the active rings pause bit resumed back */
26249 uint64_t resume_pause_events;
26250 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
26251 uint64_t continuous_roce_pause_events;
26252 /* Number of times, the ROCE cos queue PFC is enabled back */
26253 uint64_t resume_roce_pause_events;
26254 } __attribute__((packed));
26256 /* PCIe Statistics Formats */
26257 /* pcie_ctx_hw_stats (size:768b/96B) */
26258 struct pcie_ctx_hw_stats {
26259 /* Number of physical layer receiver errors */
26260 uint64_t pcie_pl_signal_integrity;
26261 /* Number of DLLP CRC errors detected by Data Link Layer */
26262 uint64_t pcie_dl_signal_integrity;
26264 * Number of TLP LCRC and sequence number errors detected
26265 * by Data Link Layer
26267 uint64_t pcie_tl_signal_integrity;
26268 /* Number of times LTSSM entered Recovery state */
26269 uint64_t pcie_link_integrity;
26270 /* Number of TLP bytes that have been trasmitted */
26271 uint64_t pcie_tx_traffic_rate;
26272 /* Number of TLP bytes that have been received */
26273 uint64_t pcie_rx_traffic_rate;
26274 /* Number of DLLP bytes that have been trasmitted */
26275 uint64_t pcie_tx_dllp_statistics;
26276 /* Number of DLLP bytes that have been received */
26277 uint64_t pcie_rx_dllp_statistics;
26279 * Number of times spent in each phase of gen3
26282 uint64_t pcie_equalization_time;
26283 /* Records the last 16 transitions of the LTSSM */
26284 uint32_t pcie_ltssm_histogram[4];
26286 * Record the last 8 reasons on why LTSSM transitioned
26289 uint64_t pcie_recovery_histogram;
26290 } __attribute__((packed));
26292 /**********************
26293 * hwrm_exec_fwd_resp *
26294 **********************/
26297 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
26298 struct hwrm_exec_fwd_resp_input {
26299 /* The HWRM command request type. */
26302 * The completion ring to send the completion event on. This should
26303 * be the NQ ID returned from the `nq_alloc` HWRM command.
26305 uint16_t cmpl_ring;
26307 * The sequence ID is used by the driver for tracking multiple
26308 * commands. This ID is treated as opaque data by the firmware and
26309 * the value is returned in the `hwrm_resp_hdr` upon completion.
26313 * The target ID of the command:
26314 * * 0x0-0xFFF8 - The function ID
26315 * * 0xFFF8-0xFFFE - Reserved for internal processors
26318 uint16_t target_id;
26320 * A physical address pointer pointing to a host buffer that the
26321 * command's response data will be written. This can be either a host
26322 * physical address (HPA) or a guest physical address (GPA) and must
26323 * point to a physically contiguous block of memory.
26325 uint64_t resp_addr;
26327 * This is an encapsulated request. This request should
26328 * be executed by the HWRM and the response should be
26329 * provided in the response buffer inside the encapsulated
26332 uint32_t encap_request[26];
26334 * This value indicates the target id of the response to
26335 * the encapsulated request.
26336 * 0x0 - 0xFFF8 - Used for function ids
26337 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26340 uint16_t encap_resp_target_id;
26341 uint8_t unused_0[6];
26342 } __attribute__((packed));
26344 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
26345 struct hwrm_exec_fwd_resp_output {
26346 /* The specific error status for the command. */
26347 uint16_t error_code;
26348 /* The HWRM command request type. */
26350 /* The sequence ID from the original command. */
26352 /* The length of the response data in number of bytes. */
26354 uint8_t unused_0[7];
26356 * This field is used in Output records to indicate that the output
26357 * is completely written to RAM. This field should be read as '1'
26358 * to indicate that the output has been completely written.
26359 * When writing a command completion or response to an internal processor,
26360 * the order of writes has to be such that this field is written last.
26363 } __attribute__((packed));
26365 /************************
26366 * hwrm_reject_fwd_resp *
26367 ************************/
26370 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
26371 struct hwrm_reject_fwd_resp_input {
26372 /* The HWRM command request type. */
26375 * The completion ring to send the completion event on. This should
26376 * be the NQ ID returned from the `nq_alloc` HWRM command.
26378 uint16_t cmpl_ring;
26380 * The sequence ID is used by the driver for tracking multiple
26381 * commands. This ID is treated as opaque data by the firmware and
26382 * the value is returned in the `hwrm_resp_hdr` upon completion.
26386 * The target ID of the command:
26387 * * 0x0-0xFFF8 - The function ID
26388 * * 0xFFF8-0xFFFE - Reserved for internal processors
26391 uint16_t target_id;
26393 * A physical address pointer pointing to a host buffer that the
26394 * command's response data will be written. This can be either a host
26395 * physical address (HPA) or a guest physical address (GPA) and must
26396 * point to a physically contiguous block of memory.
26398 uint64_t resp_addr;
26400 * This is an encapsulated request. This request should
26401 * be rejected by the HWRM and the error response should be
26402 * provided in the response buffer inside the encapsulated
26405 uint32_t encap_request[26];
26407 * This value indicates the target id of the response to
26408 * the encapsulated request.
26409 * 0x0 - 0xFFF8 - Used for function ids
26410 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26413 uint16_t encap_resp_target_id;
26414 uint8_t unused_0[6];
26415 } __attribute__((packed));
26417 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
26418 struct hwrm_reject_fwd_resp_output {
26419 /* The specific error status for the command. */
26420 uint16_t error_code;
26421 /* The HWRM command request type. */
26423 /* The sequence ID from the original command. */
26425 /* The length of the response data in number of bytes. */
26427 uint8_t unused_0[7];
26429 * This field is used in Output records to indicate that the output
26430 * is completely written to RAM. This field should be read as '1'
26431 * to indicate that the output has been completely written.
26432 * When writing a command completion or response to an internal processor,
26433 * the order of writes has to be such that this field is written last.
26436 } __attribute__((packed));
26443 /* hwrm_fwd_resp_input (size:1024b/128B) */
26444 struct hwrm_fwd_resp_input {
26445 /* The HWRM command request type. */
26448 * The completion ring to send the completion event on. This should
26449 * be the NQ ID returned from the `nq_alloc` HWRM command.
26451 uint16_t cmpl_ring;
26453 * The sequence ID is used by the driver for tracking multiple
26454 * commands. This ID is treated as opaque data by the firmware and
26455 * the value is returned in the `hwrm_resp_hdr` upon completion.
26459 * The target ID of the command:
26460 * * 0x0-0xFFF8 - The function ID
26461 * * 0xFFF8-0xFFFE - Reserved for internal processors
26464 uint16_t target_id;
26466 * A physical address pointer pointing to a host buffer that the
26467 * command's response data will be written. This can be either a host
26468 * physical address (HPA) or a guest physical address (GPA) and must
26469 * point to a physically contiguous block of memory.
26471 uint64_t resp_addr;
26473 * This value indicates the target id of the encapsulated
26475 * 0x0 - 0xFFF8 - Used for function ids
26476 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26479 uint16_t encap_resp_target_id;
26481 * This value indicates the completion ring the encapsulated
26482 * response will be optionally completed on. If the value is
26483 * -1, then no CR completion shall be generated for the
26484 * encapsulated response. Any other value must be a
26485 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
26486 * is provided, then a CR completion shall be generated for
26487 * the encapsulated response.
26489 uint16_t encap_resp_cmpl_ring;
26490 /* This field indicates the length of encapsulated response. */
26491 uint16_t encap_resp_len;
26495 * This is the host address where the encapsulated response
26497 * This area must be 16B aligned and must be cleared to zero
26498 * before the original request is made.
26500 uint64_t encap_resp_addr;
26501 /* This is an encapsulated response. */
26502 uint32_t encap_resp[24];
26503 } __attribute__((packed));
26505 /* hwrm_fwd_resp_output (size:128b/16B) */
26506 struct hwrm_fwd_resp_output {
26507 /* The specific error status for the command. */
26508 uint16_t error_code;
26509 /* The HWRM command request type. */
26511 /* The sequence ID from the original command. */
26513 /* The length of the response data in number of bytes. */
26515 uint8_t unused_0[7];
26517 * This field is used in Output records to indicate that the output
26518 * is completely written to RAM. This field should be read as '1'
26519 * to indicate that the output has been completely written.
26520 * When writing a command completion or response to an internal processor,
26521 * the order of writes has to be such that this field is written last.
26524 } __attribute__((packed));
26526 /*****************************
26527 * hwrm_fwd_async_event_cmpl *
26528 *****************************/
26531 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
26532 struct hwrm_fwd_async_event_cmpl_input {
26533 /* The HWRM command request type. */
26536 * The completion ring to send the completion event on. This should
26537 * be the NQ ID returned from the `nq_alloc` HWRM command.
26539 uint16_t cmpl_ring;
26541 * The sequence ID is used by the driver for tracking multiple
26542 * commands. This ID is treated as opaque data by the firmware and
26543 * the value is returned in the `hwrm_resp_hdr` upon completion.
26547 * The target ID of the command:
26548 * * 0x0-0xFFF8 - The function ID
26549 * * 0xFFF8-0xFFFE - Reserved for internal processors
26552 uint16_t target_id;
26554 * A physical address pointer pointing to a host buffer that the
26555 * command's response data will be written. This can be either a host
26556 * physical address (HPA) or a guest physical address (GPA) and must
26557 * point to a physically contiguous block of memory.
26559 uint64_t resp_addr;
26561 * This value indicates the target id of the encapsulated
26562 * asynchronous event.
26563 * 0x0 - 0xFFF8 - Used for function ids
26564 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26565 * 0xFFFF - Broadcast to all children VFs (only applicable when
26566 * a PF is the requester)
26568 uint16_t encap_async_event_target_id;
26569 uint8_t unused_0[6];
26570 /* This is an encapsulated asynchronous event completion. */
26571 uint32_t encap_async_event_cmpl[4];
26572 } __attribute__((packed));
26574 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
26575 struct hwrm_fwd_async_event_cmpl_output {
26576 /* The specific error status for the command. */
26577 uint16_t error_code;
26578 /* The HWRM command request type. */
26580 /* The sequence ID from the original command. */
26582 /* The length of the response data in number of bytes. */
26584 uint8_t unused_0[7];
26586 * This field is used in Output records to indicate that the output
26587 * is completely written to RAM. This field should be read as '1'
26588 * to indicate that the output has been completely written.
26589 * When writing a command completion or response to an internal processor,
26590 * the order of writes has to be such that this field is written last.
26593 } __attribute__((packed));
26595 /**************************
26596 * hwrm_nvm_raw_write_blk *
26597 **************************/
26600 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
26601 struct hwrm_nvm_raw_write_blk_input {
26602 /* The HWRM command request type. */
26605 * The completion ring to send the completion event on. This should
26606 * be the NQ ID returned from the `nq_alloc` HWRM command.
26608 uint16_t cmpl_ring;
26610 * The sequence ID is used by the driver for tracking multiple
26611 * commands. This ID is treated as opaque data by the firmware and
26612 * the value is returned in the `hwrm_resp_hdr` upon completion.
26616 * The target ID of the command:
26617 * * 0x0-0xFFF8 - The function ID
26618 * * 0xFFF8-0xFFFE - Reserved for internal processors
26621 uint16_t target_id;
26623 * A physical address pointer pointing to a host buffer that the
26624 * command's response data will be written. This can be either a host
26625 * physical address (HPA) or a guest physical address (GPA) and must
26626 * point to a physically contiguous block of memory.
26628 uint64_t resp_addr;
26630 * 64-bit Host Source Address.
26631 * This is the loation of the source data to be written.
26633 uint64_t host_src_addr;
26635 * 32-bit Destination Address.
26636 * This is the NVRAM byte-offset where the source data will be written to.
26638 uint32_t dest_addr;
26639 /* Length of data to be written, in bytes. */
26641 } __attribute__((packed));
26643 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
26644 struct hwrm_nvm_raw_write_blk_output {
26645 /* The specific error status for the command. */
26646 uint16_t error_code;
26647 /* The HWRM command request type. */
26649 /* The sequence ID from the original command. */
26651 /* The length of the response data in number of bytes. */
26653 uint8_t unused_0[7];
26655 * This field is used in Output records to indicate that the output
26656 * is completely written to RAM. This field should be read as '1'
26657 * to indicate that the output has been completely written.
26658 * When writing a command completion or response to an internal processor,
26659 * the order of writes has to be such that this field is written last.
26662 } __attribute__((packed));
26669 /* hwrm_nvm_read_input (size:320b/40B) */
26670 struct hwrm_nvm_read_input {
26671 /* The HWRM command request type. */
26674 * The completion ring to send the completion event on. This should
26675 * be the NQ ID returned from the `nq_alloc` HWRM command.
26677 uint16_t cmpl_ring;
26679 * The sequence ID is used by the driver for tracking multiple
26680 * commands. This ID is treated as opaque data by the firmware and
26681 * the value is returned in the `hwrm_resp_hdr` upon completion.
26685 * The target ID of the command:
26686 * * 0x0-0xFFF8 - The function ID
26687 * * 0xFFF8-0xFFFE - Reserved for internal processors
26690 uint16_t target_id;
26692 * A physical address pointer pointing to a host buffer that the
26693 * command's response data will be written. This can be either a host
26694 * physical address (HPA) or a guest physical address (GPA) and must
26695 * point to a physically contiguous block of memory.
26697 uint64_t resp_addr;
26699 * 64-bit Host Destination Address.
26700 * This is the host address where the data will be written to.
26702 uint64_t host_dest_addr;
26703 /* The 0-based index of the directory entry. */
26705 uint8_t unused_0[2];
26706 /* The NVRAM byte-offset to read from. */
26708 /* The length of the data to be read, in bytes. */
26710 uint8_t unused_1[4];
26711 } __attribute__((packed));
26713 /* hwrm_nvm_read_output (size:128b/16B) */
26714 struct hwrm_nvm_read_output {
26715 /* The specific error status for the command. */
26716 uint16_t error_code;
26717 /* The HWRM command request type. */
26719 /* The sequence ID from the original command. */
26721 /* The length of the response data in number of bytes. */
26723 uint8_t unused_0[7];
26725 * This field is used in Output records to indicate that the output
26726 * is completely written to RAM. This field should be read as '1'
26727 * to indicate that the output has been completely written.
26728 * When writing a command completion or response to an internal processor,
26729 * the order of writes has to be such that this field is written last.
26732 } __attribute__((packed));
26734 /*********************
26735 * hwrm_nvm_raw_dump *
26736 *********************/
26739 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
26740 struct hwrm_nvm_raw_dump_input {
26741 /* The HWRM command request type. */
26744 * The completion ring to send the completion event on. This should
26745 * be the NQ ID returned from the `nq_alloc` HWRM command.
26747 uint16_t cmpl_ring;
26749 * The sequence ID is used by the driver for tracking multiple
26750 * commands. This ID is treated as opaque data by the firmware and
26751 * the value is returned in the `hwrm_resp_hdr` upon completion.
26755 * The target ID of the command:
26756 * * 0x0-0xFFF8 - The function ID
26757 * * 0xFFF8-0xFFFE - Reserved for internal processors
26760 uint16_t target_id;
26762 * A physical address pointer pointing to a host buffer that the
26763 * command's response data will be written. This can be either a host
26764 * physical address (HPA) or a guest physical address (GPA) and must
26765 * point to a physically contiguous block of memory.
26767 uint64_t resp_addr;
26769 * 64-bit Host Destination Address.
26770 * This is the host address where the data will be written to.
26772 uint64_t host_dest_addr;
26773 /* 32-bit NVRAM byte-offset to read from. */
26775 /* Total length of NVRAM contents to be read, in bytes. */
26777 } __attribute__((packed));
26779 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
26780 struct hwrm_nvm_raw_dump_output {
26781 /* The specific error status for the command. */
26782 uint16_t error_code;
26783 /* The HWRM command request type. */
26785 /* The sequence ID from the original command. */
26787 /* The length of the response data in number of bytes. */
26789 uint8_t unused_0[7];
26791 * This field is used in Output records to indicate that the output
26792 * is completely written to RAM. This field should be read as '1'
26793 * to indicate that the output has been completely written.
26794 * When writing a command completion or response to an internal processor,
26795 * the order of writes has to be such that this field is written last.
26798 } __attribute__((packed));
26800 /****************************
26801 * hwrm_nvm_get_dir_entries *
26802 ****************************/
26805 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
26806 struct hwrm_nvm_get_dir_entries_input {
26807 /* The HWRM command request type. */
26810 * The completion ring to send the completion event on. This should
26811 * be the NQ ID returned from the `nq_alloc` HWRM command.
26813 uint16_t cmpl_ring;
26815 * The sequence ID is used by the driver for tracking multiple
26816 * commands. This ID is treated as opaque data by the firmware and
26817 * the value is returned in the `hwrm_resp_hdr` upon completion.
26821 * The target ID of the command:
26822 * * 0x0-0xFFF8 - The function ID
26823 * * 0xFFF8-0xFFFE - Reserved for internal processors
26826 uint16_t target_id;
26828 * A physical address pointer pointing to a host buffer that the
26829 * command's response data will be written. This can be either a host
26830 * physical address (HPA) or a guest physical address (GPA) and must
26831 * point to a physically contiguous block of memory.
26833 uint64_t resp_addr;
26835 * 64-bit Host Destination Address.
26836 * This is the host address where the directory will be written.
26838 uint64_t host_dest_addr;
26839 } __attribute__((packed));
26841 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
26842 struct hwrm_nvm_get_dir_entries_output {
26843 /* The specific error status for the command. */
26844 uint16_t error_code;
26845 /* The HWRM command request type. */
26847 /* The sequence ID from the original command. */
26849 /* The length of the response data in number of bytes. */
26851 uint8_t unused_0[7];
26853 * This field is used in Output records to indicate that the output
26854 * is completely written to RAM. This field should be read as '1'
26855 * to indicate that the output has been completely written.
26856 * When writing a command completion or response to an internal processor,
26857 * the order of writes has to be such that this field is written last.
26860 } __attribute__((packed));
26862 /*************************
26863 * hwrm_nvm_get_dir_info *
26864 *************************/
26867 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
26868 struct hwrm_nvm_get_dir_info_input {
26869 /* The HWRM command request type. */
26872 * The completion ring to send the completion event on. This should
26873 * be the NQ ID returned from the `nq_alloc` HWRM command.
26875 uint16_t cmpl_ring;
26877 * The sequence ID is used by the driver for tracking multiple
26878 * commands. This ID is treated as opaque data by the firmware and
26879 * the value is returned in the `hwrm_resp_hdr` upon completion.
26883 * The target ID of the command:
26884 * * 0x0-0xFFF8 - The function ID
26885 * * 0xFFF8-0xFFFE - Reserved for internal processors
26888 uint16_t target_id;
26890 * A physical address pointer pointing to a host buffer that the
26891 * command's response data will be written. This can be either a host
26892 * physical address (HPA) or a guest physical address (GPA) and must
26893 * point to a physically contiguous block of memory.
26895 uint64_t resp_addr;
26896 } __attribute__((packed));
26898 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
26899 struct hwrm_nvm_get_dir_info_output {
26900 /* The specific error status for the command. */
26901 uint16_t error_code;
26902 /* The HWRM command request type. */
26904 /* The sequence ID from the original command. */
26906 /* The length of the response data in number of bytes. */
26908 /* Number of directory entries in the directory. */
26910 /* Size of each directory entry, in bytes. */
26911 uint32_t entry_length;
26912 uint8_t unused_0[7];
26914 * This field is used in Output records to indicate that the output
26915 * is completely written to RAM. This field should be read as '1'
26916 * to indicate that the output has been completely written.
26917 * When writing a command completion or response to an internal processor,
26918 * the order of writes has to be such that this field is written last.
26921 } __attribute__((packed));
26923 /******************
26925 ******************/
26928 /* hwrm_nvm_write_input (size:384b/48B) */
26929 struct hwrm_nvm_write_input {
26930 /* The HWRM command request type. */
26933 * The completion ring to send the completion event on. This should
26934 * be the NQ ID returned from the `nq_alloc` HWRM command.
26936 uint16_t cmpl_ring;
26938 * The sequence ID is used by the driver for tracking multiple
26939 * commands. This ID is treated as opaque data by the firmware and
26940 * the value is returned in the `hwrm_resp_hdr` upon completion.
26944 * The target ID of the command:
26945 * * 0x0-0xFFF8 - The function ID
26946 * * 0xFFF8-0xFFFE - Reserved for internal processors
26949 uint16_t target_id;
26951 * A physical address pointer pointing to a host buffer that the
26952 * command's response data will be written. This can be either a host
26953 * physical address (HPA) or a guest physical address (GPA) and must
26954 * point to a physically contiguous block of memory.
26956 uint64_t resp_addr;
26958 * 64-bit Host Source Address.
26959 * This is where the source data is.
26961 uint64_t host_src_addr;
26962 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
26965 * Directory ordinal.
26966 * The 0-based instance of the combined Directory Entry Type and Extension.
26968 uint16_t dir_ordinal;
26969 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
26971 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
26974 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
26975 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
26977 uint32_t dir_data_length;
26982 * When this bit is '1', the original active image
26983 * will not be removed. TBD: what purpose is this?
26985 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
26988 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
26989 * If this value is less than the specified data length, it will be ignored.
26990 * The response will contain the actual allocated item length, which may be greater than the requested item length.
26991 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
26992 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
26994 uint32_t dir_item_length;
26996 } __attribute__((packed));
26998 /* hwrm_nvm_write_output (size:128b/16B) */
26999 struct hwrm_nvm_write_output {
27000 /* The specific error status for the command. */
27001 uint16_t error_code;
27002 /* The HWRM command request type. */
27004 /* The sequence ID from the original command. */
27006 /* The length of the response data in number of bytes. */
27009 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
27010 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
27012 uint32_t dir_item_length;
27013 /* The directory index of the created or modified item. */
27017 * This field is used in Output records to indicate that the output
27018 * is completely written to RAM. This field should be read as '1'
27019 * to indicate that the output has been completely written.
27020 * When writing a command completion or response to an internal processor,
27021 * the order of writes has to be such that this field is written last.
27024 } __attribute__((packed));
27026 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
27027 struct hwrm_nvm_write_cmd_err {
27029 * command specific error codes that goes to
27030 * the cmd_err field in Common HWRM Error Response.
27033 /* Unknown error */
27034 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27035 /* Unable to complete operation due to fragmentation */
27036 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
27037 /* nvm is completely full. */
27038 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
27039 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
27040 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
27041 uint8_t unused_0[7];
27042 } __attribute__((packed));
27044 /*******************
27045 * hwrm_nvm_modify *
27046 *******************/
27049 /* hwrm_nvm_modify_input (size:320b/40B) */
27050 struct hwrm_nvm_modify_input {
27051 /* The HWRM command request type. */
27054 * The completion ring to send the completion event on. This should
27055 * be the NQ ID returned from the `nq_alloc` HWRM command.
27057 uint16_t cmpl_ring;
27059 * The sequence ID is used by the driver for tracking multiple
27060 * commands. This ID is treated as opaque data by the firmware and
27061 * the value is returned in the `hwrm_resp_hdr` upon completion.
27065 * The target ID of the command:
27066 * * 0x0-0xFFF8 - The function ID
27067 * * 0xFFF8-0xFFFE - Reserved for internal processors
27070 uint16_t target_id;
27072 * A physical address pointer pointing to a host buffer that the
27073 * command's response data will be written. This can be either a host
27074 * physical address (HPA) or a guest physical address (GPA) and must
27075 * point to a physically contiguous block of memory.
27077 uint64_t resp_addr;
27079 * 64-bit Host Source Address.
27080 * This is where the modified data is.
27082 uint64_t host_src_addr;
27083 /* 16-bit directory entry index. */
27085 uint8_t unused_0[2];
27086 /* 32-bit NVRAM byte-offset to modify content from. */
27089 * Length of data to be modified, in bytes. The length shall
27093 uint8_t unused_1[4];
27094 } __attribute__((packed));
27096 /* hwrm_nvm_modify_output (size:128b/16B) */
27097 struct hwrm_nvm_modify_output {
27098 /* The specific error status for the command. */
27099 uint16_t error_code;
27100 /* The HWRM command request type. */
27102 /* The sequence ID from the original command. */
27104 /* The length of the response data in number of bytes. */
27106 uint8_t unused_0[7];
27108 * This field is used in Output records to indicate that the output
27109 * is completely written to RAM. This field should be read as '1'
27110 * to indicate that the output has been completely written.
27111 * When writing a command completion or response to an internal processor,
27112 * the order of writes has to be such that this field is written last.
27115 } __attribute__((packed));
27117 /***************************
27118 * hwrm_nvm_find_dir_entry *
27119 ***************************/
27122 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
27123 struct hwrm_nvm_find_dir_entry_input {
27124 /* The HWRM command request type. */
27127 * The completion ring to send the completion event on. This should
27128 * be the NQ ID returned from the `nq_alloc` HWRM command.
27130 uint16_t cmpl_ring;
27132 * The sequence ID is used by the driver for tracking multiple
27133 * commands. This ID is treated as opaque data by the firmware and
27134 * the value is returned in the `hwrm_resp_hdr` upon completion.
27138 * The target ID of the command:
27139 * * 0x0-0xFFF8 - The function ID
27140 * * 0xFFF8-0xFFFE - Reserved for internal processors
27143 uint16_t target_id;
27145 * A physical address pointer pointing to a host buffer that the
27146 * command's response data will be written. This can be either a host
27147 * physical address (HPA) or a guest physical address (GPA) and must
27148 * point to a physically contiguous block of memory.
27150 uint64_t resp_addr;
27153 * This bit must be '1' for the dir_idx_valid field to be
27156 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
27158 /* Directory Entry Index */
27160 /* Directory Entry (Image) Type */
27163 * Directory ordinal.
27164 * The instance of this Directory Type
27166 uint16_t dir_ordinal;
27167 /* The Directory Entry Extension flags. */
27169 /* This value indicates the search option using dir_ordinal. */
27170 uint8_t opt_ordinal;
27171 /* This value indicates the search option using dir_ordinal. */
27172 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
27173 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
27174 /* Equal to specified ordinal value. */
27175 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
27176 /* Greater than or equal to specified ordinal value */
27177 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
27178 /* Greater than specified ordinal value */
27179 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
27180 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
27181 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
27182 uint8_t unused_0[3];
27183 } __attribute__((packed));
27185 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
27186 struct hwrm_nvm_find_dir_entry_output {
27187 /* The specific error status for the command. */
27188 uint16_t error_code;
27189 /* The HWRM command request type. */
27191 /* The sequence ID from the original command. */
27193 /* The length of the response data in number of bytes. */
27195 /* Allocated NVRAM for this directory entry, in bytes. */
27196 uint32_t dir_item_length;
27197 /* Size of the stored data for this directory entry, in bytes. */
27198 uint32_t dir_data_length;
27200 * Firmware version.
27201 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
27204 /* Directory ordinal. */
27205 uint16_t dir_ordinal;
27206 /* Directory Entry Index */
27208 uint8_t unused_0[7];
27210 * This field is used in Output records to indicate that the output
27211 * is completely written to RAM. This field should be read as '1'
27212 * to indicate that the output has been completely written.
27213 * When writing a command completion or response to an internal processor,
27214 * the order of writes has to be such that this field is written last.
27217 } __attribute__((packed));
27219 /****************************
27220 * hwrm_nvm_erase_dir_entry *
27221 ****************************/
27224 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
27225 struct hwrm_nvm_erase_dir_entry_input {
27226 /* The HWRM command request type. */
27229 * The completion ring to send the completion event on. This should
27230 * be the NQ ID returned from the `nq_alloc` HWRM command.
27232 uint16_t cmpl_ring;
27234 * The sequence ID is used by the driver for tracking multiple
27235 * commands. This ID is treated as opaque data by the firmware and
27236 * the value is returned in the `hwrm_resp_hdr` upon completion.
27240 * The target ID of the command:
27241 * * 0x0-0xFFF8 - The function ID
27242 * * 0xFFF8-0xFFFE - Reserved for internal processors
27245 uint16_t target_id;
27247 * A physical address pointer pointing to a host buffer that the
27248 * command's response data will be written. This can be either a host
27249 * physical address (HPA) or a guest physical address (GPA) and must
27250 * point to a physically contiguous block of memory.
27252 uint64_t resp_addr;
27253 /* Directory Entry Index */
27255 uint8_t unused_0[6];
27256 } __attribute__((packed));
27258 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
27259 struct hwrm_nvm_erase_dir_entry_output {
27260 /* The specific error status for the command. */
27261 uint16_t error_code;
27262 /* The HWRM command request type. */
27264 /* The sequence ID from the original command. */
27266 /* The length of the response data in number of bytes. */
27268 uint8_t unused_0[7];
27270 * This field is used in Output records to indicate that the output
27271 * is completely written to RAM. This field should be read as '1'
27272 * to indicate that the output has been completely written.
27273 * When writing a command completion or response to an internal processor,
27274 * the order of writes has to be such that this field is written last.
27277 } __attribute__((packed));
27279 /*************************
27280 * hwrm_nvm_get_dev_info *
27281 *************************/
27284 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
27285 struct hwrm_nvm_get_dev_info_input {
27286 /* The HWRM command request type. */
27289 * The completion ring to send the completion event on. This should
27290 * be the NQ ID returned from the `nq_alloc` HWRM command.
27292 uint16_t cmpl_ring;
27294 * The sequence ID is used by the driver for tracking multiple
27295 * commands. This ID is treated as opaque data by the firmware and
27296 * the value is returned in the `hwrm_resp_hdr` upon completion.
27300 * The target ID of the command:
27301 * * 0x0-0xFFF8 - The function ID
27302 * * 0xFFF8-0xFFFE - Reserved for internal processors
27305 uint16_t target_id;
27307 * A physical address pointer pointing to a host buffer that the
27308 * command's response data will be written. This can be either a host
27309 * physical address (HPA) or a guest physical address (GPA) and must
27310 * point to a physically contiguous block of memory.
27312 uint64_t resp_addr;
27313 } __attribute__((packed));
27315 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
27316 struct hwrm_nvm_get_dev_info_output {
27317 /* The specific error status for the command. */
27318 uint16_t error_code;
27319 /* The HWRM command request type. */
27321 /* The sequence ID from the original command. */
27323 /* The length of the response data in number of bytes. */
27325 /* Manufacturer ID. */
27326 uint16_t manufacturer_id;
27328 uint16_t device_id;
27329 /* Sector size of the NVRAM device. */
27330 uint32_t sector_size;
27331 /* Total size, in bytes of the NVRAM device. */
27332 uint32_t nvram_size;
27333 uint32_t reserved_size;
27334 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
27335 uint32_t available_size;
27336 uint8_t unused_0[3];
27338 * This field is used in Output records to indicate that the output
27339 * is completely written to RAM. This field should be read as '1'
27340 * to indicate that the output has been completely written.
27341 * When writing a command completion or response to an internal processor,
27342 * the order of writes has to be such that this field is written last.
27345 } __attribute__((packed));
27347 /**************************
27348 * hwrm_nvm_mod_dir_entry *
27349 **************************/
27352 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
27353 struct hwrm_nvm_mod_dir_entry_input {
27354 /* The HWRM command request type. */
27357 * The completion ring to send the completion event on. This should
27358 * be the NQ ID returned from the `nq_alloc` HWRM command.
27360 uint16_t cmpl_ring;
27362 * The sequence ID is used by the driver for tracking multiple
27363 * commands. This ID is treated as opaque data by the firmware and
27364 * the value is returned in the `hwrm_resp_hdr` upon completion.
27368 * The target ID of the command:
27369 * * 0x0-0xFFF8 - The function ID
27370 * * 0xFFF8-0xFFFE - Reserved for internal processors
27373 uint16_t target_id;
27375 * A physical address pointer pointing to a host buffer that the
27376 * command's response data will be written. This can be either a host
27377 * physical address (HPA) or a guest physical address (GPA) and must
27378 * point to a physically contiguous block of memory.
27380 uint64_t resp_addr;
27383 * This bit must be '1' for the checksum field to be
27386 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
27387 /* Directory Entry Index */
27390 * Directory ordinal.
27391 * The (0-based) instance of this Directory Type.
27393 uint16_t dir_ordinal;
27394 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
27396 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
27399 * If valid, then this field updates the checksum
27400 * value of the content in the directory entry.
27403 } __attribute__((packed));
27405 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
27406 struct hwrm_nvm_mod_dir_entry_output {
27407 /* The specific error status for the command. */
27408 uint16_t error_code;
27409 /* The HWRM command request type. */
27411 /* The sequence ID from the original command. */
27413 /* The length of the response data in number of bytes. */
27415 uint8_t unused_0[7];
27417 * This field is used in Output records to indicate that the output
27418 * is completely written to RAM. This field should be read as '1'
27419 * to indicate that the output has been completely written.
27420 * When writing a command completion or response to an internal processor,
27421 * the order of writes has to be such that this field is written last.
27424 } __attribute__((packed));
27426 /**************************
27427 * hwrm_nvm_verify_update *
27428 **************************/
27431 /* hwrm_nvm_verify_update_input (size:192b/24B) */
27432 struct hwrm_nvm_verify_update_input {
27433 /* The HWRM command request type. */
27436 * The completion ring to send the completion event on. This should
27437 * be the NQ ID returned from the `nq_alloc` HWRM command.
27439 uint16_t cmpl_ring;
27441 * The sequence ID is used by the driver for tracking multiple
27442 * commands. This ID is treated as opaque data by the firmware and
27443 * the value is returned in the `hwrm_resp_hdr` upon completion.
27447 * The target ID of the command:
27448 * * 0x0-0xFFF8 - The function ID
27449 * * 0xFFF8-0xFFFE - Reserved for internal processors
27452 uint16_t target_id;
27454 * A physical address pointer pointing to a host buffer that the
27455 * command's response data will be written. This can be either a host
27456 * physical address (HPA) or a guest physical address (GPA) and must
27457 * point to a physically contiguous block of memory.
27459 uint64_t resp_addr;
27460 /* Directory Entry Type, to be verified. */
27463 * Directory ordinal.
27464 * The instance of the Directory Type to be verified.
27466 uint16_t dir_ordinal;
27468 * The Directory Entry Extension flags.
27469 * The "UPDATE" extension flag must be set in this value.
27470 * A corresponding directory entry with the same type and ordinal values but *without*
27471 * the "UPDATE" extension flag must also exist. The other flags of the extension must
27472 * be identical between the active and update entries.
27475 uint8_t unused_0[2];
27476 } __attribute__((packed));
27478 /* hwrm_nvm_verify_update_output (size:128b/16B) */
27479 struct hwrm_nvm_verify_update_output {
27480 /* The specific error status for the command. */
27481 uint16_t error_code;
27482 /* The HWRM command request type. */
27484 /* The sequence ID from the original command. */
27486 /* The length of the response data in number of bytes. */
27488 uint8_t unused_0[7];
27490 * This field is used in Output records to indicate that the output
27491 * is completely written to RAM. This field should be read as '1'
27492 * to indicate that the output has been completely written.
27493 * When writing a command completion or response to an internal processor,
27494 * the order of writes has to be such that this field is written last.
27497 } __attribute__((packed));
27499 /***************************
27500 * hwrm_nvm_install_update *
27501 ***************************/
27504 /* hwrm_nvm_install_update_input (size:192b/24B) */
27505 struct hwrm_nvm_install_update_input {
27506 /* The HWRM command request type. */
27509 * The completion ring to send the completion event on. This should
27510 * be the NQ ID returned from the `nq_alloc` HWRM command.
27512 uint16_t cmpl_ring;
27514 * The sequence ID is used by the driver for tracking multiple
27515 * commands. This ID is treated as opaque data by the firmware and
27516 * the value is returned in the `hwrm_resp_hdr` upon completion.
27520 * The target ID of the command:
27521 * * 0x0-0xFFF8 - The function ID
27522 * * 0xFFF8-0xFFFE - Reserved for internal processors
27525 uint16_t target_id;
27527 * A physical address pointer pointing to a host buffer that the
27528 * command's response data will be written. This can be either a host
27529 * physical address (HPA) or a guest physical address (GPA) and must
27530 * point to a physically contiguous block of memory.
27532 uint64_t resp_addr;
27534 * Installation type. If the value 3 through 0xffff is used,
27535 * only packaged items with that type value will be installed and
27536 * conditional installation directives for those packaged items
27537 * will be over-ridden (i.e. 'create' or 'replace' will be treated
27540 uint32_t install_type;
27542 * Perform a normal package installation. Conditional installation
27543 * directives (e.g. 'create' and 'replace') of packaged items
27544 * will be followed.
27546 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
27548 * Install all packaged items regardless of installation directive
27549 * (i.e. treat all packaged items as though they have an installation
27550 * directive of 'install').
27552 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
27553 UINT32_C(0xffffffff)
27554 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
27555 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
27557 /* If set to 1, then securely erase all unused locations in persistent storage. */
27558 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
27561 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
27562 * When combined with erase_unused_space then unspecified images will be securely erased.
27564 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
27567 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
27568 * Allow additional time for this command to complete if this bit is set to 1.
27570 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
27572 uint8_t unused_0[2];
27573 } __attribute__((packed));
27575 /* hwrm_nvm_install_update_output (size:192b/24B) */
27576 struct hwrm_nvm_install_update_output {
27577 /* The specific error status for the command. */
27578 uint16_t error_code;
27579 /* The HWRM command request type. */
27581 /* The sequence ID from the original command. */
27583 /* The length of the response data in number of bytes. */
27586 * Bit-mask of successfully installed items.
27587 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
27588 * A value of 0 indicates that no items were successfully installed.
27590 uint64_t installed_items;
27591 /* result is 8 b */
27593 /* There was no problem with the package installation. */
27594 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
27595 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
27596 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
27597 /* problem_item is 8 b */
27598 uint8_t problem_item;
27599 /* There was no problem with any packaged items. */
27600 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
27602 /* There was a problem with the NVM package itself. */
27603 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
27605 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
27606 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
27607 /* reset_required is 8 b */
27608 uint8_t reset_required;
27610 * No reset is required for installed/updated firmware or
27611 * microcode to take effect.
27613 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
27616 * A PCIe reset (e.g. system reboot) is
27617 * required for newly installed/updated firmware or
27618 * microcode to take effect.
27620 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
27623 * A controller power reset (e.g. system power-cycle) is
27624 * required for newly installed/updated firmware or
27625 * microcode to take effect. Some newly installed/updated
27626 * firmware or microcode may still take effect upon the
27629 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
27631 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
27632 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
27633 uint8_t unused_0[4];
27635 * This field is used in Output records to indicate that the output
27636 * is completely written to RAM. This field should be read as '1'
27637 * to indicate that the output has been completely written.
27638 * When writing a command completion or response to an internal processor,
27639 * the order of writes has to be such that this field is written last.
27642 } __attribute__((packed));
27644 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
27645 struct hwrm_nvm_install_update_cmd_err {
27647 * command specific error codes that goes to
27648 * the cmd_err field in Common HWRM Error Response.
27651 /* Unknown error */
27652 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27653 /* Unable to complete operation due to fragmentation */
27654 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
27655 /* nvm is completely full. */
27656 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
27657 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
27658 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
27659 uint8_t unused_0[7];
27660 } __attribute__((packed));
27662 /******************
27664 ******************/
27667 /* hwrm_nvm_flush_input (size:128b/16B) */
27668 struct hwrm_nvm_flush_input {
27669 /* The HWRM command request type. */
27672 * The completion ring to send the completion event on. This should
27673 * be the NQ ID returned from the `nq_alloc` HWRM command.
27675 uint16_t cmpl_ring;
27677 * The sequence ID is used by the driver for tracking multiple
27678 * commands. This ID is treated as opaque data by the firmware and
27679 * the value is returned in the `hwrm_resp_hdr` upon completion.
27683 * The target ID of the command:
27684 * * 0x0-0xFFF8 - The function ID
27685 * * 0xFFF8-0xFFFE - Reserved for internal processors
27688 uint16_t target_id;
27690 * A physical address pointer pointing to a host buffer that the
27691 * command's response data will be written. This can be either a host
27692 * physical address (HPA) or a guest physical address (GPA) and must
27693 * point to a physically contiguous block of memory.
27695 uint64_t resp_addr;
27696 } __attribute__((packed));
27698 /* hwrm_nvm_flush_output (size:128b/16B) */
27699 struct hwrm_nvm_flush_output {
27700 /* The specific error status for the command. */
27701 uint16_t error_code;
27702 /* The HWRM command request type. */
27704 /* The sequence ID from the original command. */
27706 /* The length of the response data in number of bytes. */
27708 uint8_t unused_0[7];
27710 * This field is used in Output records to indicate that the output
27711 * is completely written to RAM. This field should be read as '1'
27712 * to indicate that the output has been completely written.
27713 * When writing a command completion or response to an internal processor,
27714 * the order of writes has to be such that this field is written last.
27717 } __attribute__((packed));
27719 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
27720 struct hwrm_nvm_flush_cmd_err {
27722 * command specific error codes that goes to
27723 * the cmd_err field in Common HWRM Error Response.
27726 /* Unknown error */
27727 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27728 /* flush could not be performed */
27729 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
27730 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
27731 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
27732 uint8_t unused_0[7];
27733 } __attribute__((packed));
27735 /*************************
27736 * hwrm_nvm_get_variable *
27737 *************************/
27740 /* hwrm_nvm_get_variable_input (size:320b/40B) */
27741 struct hwrm_nvm_get_variable_input {
27742 /* The HWRM command request type. */
27745 * The completion ring to send the completion event on. This should
27746 * be the NQ ID returned from the `nq_alloc` HWRM command.
27748 uint16_t cmpl_ring;
27750 * The sequence ID is used by the driver for tracking multiple
27751 * commands. This ID is treated as opaque data by the firmware and
27752 * the value is returned in the `hwrm_resp_hdr` upon completion.
27756 * The target ID of the command:
27757 * * 0x0-0xFFF8 - The function ID
27758 * * 0xFFF8-0xFFFE - Reserved for internal processors
27761 uint16_t target_id;
27763 * A physical address pointer pointing to a host buffer that the
27764 * command's response data will be written. This can be either a host
27765 * physical address (HPA) or a guest physical address (GPA) and must
27766 * point to a physically contiguous block of memory.
27768 uint64_t resp_addr;
27770 * This is the host address where
27771 * nvm variable will be stored
27773 uint64_t dest_data_addr;
27774 /* size of data in bits */
27776 /* nvm cfg option number */
27777 uint16_t option_num;
27779 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27781 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
27783 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
27784 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
27786 * Number of dimensions for this nvm configuration variable.
27787 * This value indicates how many of the indexN values to use.
27788 * A value of 0 means that none of the indexN values are valid.
27789 * A value of 1 requires at index0 is valued, a value of 2
27790 * requires that index0 and index1 are valid, and so forth
27792 uint16_t dimensions;
27793 /* index for the 1st dimensions */
27795 /* index for the 2nd dimensions */
27797 /* index for the 3rd dimensions */
27799 /* index for the 4th dimensions */
27803 * When this bit is set to 1, the factory default value will be returned,
27804 * 0 returns the operational value.
27806 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
27809 } __attribute__((packed));
27811 /* hwrm_nvm_get_variable_output (size:128b/16B) */
27812 struct hwrm_nvm_get_variable_output {
27813 /* The specific error status for the command. */
27814 uint16_t error_code;
27815 /* The HWRM command request type. */
27817 /* The sequence ID from the original command. */
27819 /* The length of the response data in number of bytes. */
27821 /* size of data of the actual variable retrieved in bits */
27824 * option_num is the option number for the data retrieved. It is possible in the
27825 * future that the option number returned would be different than requested. This
27826 * condition could occur if an option is deprecated and a new option id is defined
27827 * with similar characteristics, but has a slightly different definition. This
27828 * also makes it convenient for the caller to identify the variable result with
27829 * the option id from the response.
27831 uint16_t option_num;
27833 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27835 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
27837 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
27838 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
27839 uint8_t unused_0[3];
27841 * This field is used in Output records to indicate that the output
27842 * is completely written to RAM. This field should be read as '1'
27843 * to indicate that the output has been completely written.
27844 * When writing a command completion or response to an internal processor,
27845 * the order of writes has to be such that this field is written last.
27848 } __attribute__((packed));
27850 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
27851 struct hwrm_nvm_get_variable_cmd_err {
27853 * command specific error codes that goes to
27854 * the cmd_err field in Common HWRM Error Response.
27857 /* Unknown error */
27858 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27859 /* variable does not exist */
27860 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27861 /* configuration is corrupted and the variable cannot be saved */
27862 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27863 /* length specified is too small */
27864 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
27865 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
27866 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
27867 uint8_t unused_0[7];
27868 } __attribute__((packed));
27870 /*************************
27871 * hwrm_nvm_set_variable *
27872 *************************/
27875 /* hwrm_nvm_set_variable_input (size:320b/40B) */
27876 struct hwrm_nvm_set_variable_input {
27877 /* The HWRM command request type. */
27880 * The completion ring to send the completion event on. This should
27881 * be the NQ ID returned from the `nq_alloc` HWRM command.
27883 uint16_t cmpl_ring;
27885 * The sequence ID is used by the driver for tracking multiple
27886 * commands. This ID is treated as opaque data by the firmware and
27887 * the value is returned in the `hwrm_resp_hdr` upon completion.
27891 * The target ID of the command:
27892 * * 0x0-0xFFF8 - The function ID
27893 * * 0xFFF8-0xFFFE - Reserved for internal processors
27896 uint16_t target_id;
27898 * A physical address pointer pointing to a host buffer that the
27899 * command's response data will be written. This can be either a host
27900 * physical address (HPA) or a guest physical address (GPA) and must
27901 * point to a physically contiguous block of memory.
27903 uint64_t resp_addr;
27905 * This is the host address where
27906 * nvm variable will be copied from
27908 uint64_t src_data_addr;
27909 /* size of data in bits */
27911 /* nvm cfg option number */
27912 uint16_t option_num;
27914 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27916 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
27918 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
27919 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
27921 * Number of dimensions for this nvm configuration variable.
27922 * This value indicates how many of the indexN values to use.
27923 * A value of 0 means that none of the indexN values are valid.
27924 * A value of 1 requires at index0 is valued, a value of 2
27925 * requires that index0 and index1 are valid, and so forth
27927 uint16_t dimensions;
27928 /* index for the 1st dimensions */
27930 /* index for the 2nd dimensions */
27932 /* index for the 3rd dimensions */
27934 /* index for the 4th dimensions */
27937 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
27938 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
27940 /* encryption method */
27941 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
27943 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
27944 /* No encryption. */
27945 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
27946 (UINT32_C(0x0) << 1)
27947 /* one-way encryption. */
27948 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
27949 (UINT32_C(0x1) << 1)
27950 /* symmetric AES256 encryption. */
27951 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
27952 (UINT32_C(0x2) << 1)
27953 /* SHA1 digest appended to plaintext contents, for authentication */
27954 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
27955 (UINT32_C(0x3) << 1)
27956 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
27957 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
27959 } __attribute__((packed));
27961 /* hwrm_nvm_set_variable_output (size:128b/16B) */
27962 struct hwrm_nvm_set_variable_output {
27963 /* The specific error status for the command. */
27964 uint16_t error_code;
27965 /* The HWRM command request type. */
27967 /* The sequence ID from the original command. */
27969 /* The length of the response data in number of bytes. */
27971 uint8_t unused_0[7];
27973 * This field is used in Output records to indicate that the output
27974 * is completely written to RAM. This field should be read as '1'
27975 * to indicate that the output has been completely written.
27976 * When writing a command completion or response to an internal processor,
27977 * the order of writes has to be such that this field is written last.
27980 } __attribute__((packed));
27982 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
27983 struct hwrm_nvm_set_variable_cmd_err {
27985 * command specific error codes that goes to
27986 * the cmd_err field in Common HWRM Error Response.
27989 /* Unknown error */
27990 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27991 /* variable does not exist */
27992 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27993 /* configuration is corrupted and the variable cannot be saved */
27994 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27995 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
27996 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
27997 uint8_t unused_0[7];
27998 } __attribute__((packed));
28000 /****************************
28001 * hwrm_nvm_validate_option *
28002 ****************************/
28005 /* hwrm_nvm_validate_option_input (size:320b/40B) */
28006 struct hwrm_nvm_validate_option_input {
28007 /* The HWRM command request type. */
28010 * The completion ring to send the completion event on. This should
28011 * be the NQ ID returned from the `nq_alloc` HWRM command.
28013 uint16_t cmpl_ring;
28015 * The sequence ID is used by the driver for tracking multiple
28016 * commands. This ID is treated as opaque data by the firmware and
28017 * the value is returned in the `hwrm_resp_hdr` upon completion.
28021 * The target ID of the command:
28022 * * 0x0-0xFFF8 - The function ID
28023 * * 0xFFF8-0xFFFE - Reserved for internal processors
28026 uint16_t target_id;
28028 * A physical address pointer pointing to a host buffer that the
28029 * command's response data will be written. This can be either a host
28030 * physical address (HPA) or a guest physical address (GPA) and must
28031 * point to a physically contiguous block of memory.
28033 uint64_t resp_addr;
28035 * This is the host address where
28036 * nvm variable will be copied from
28038 uint64_t src_data_addr;
28039 /* size of data in bits */
28041 /* nvm cfg option number */
28042 uint16_t option_num;
28044 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
28047 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
28049 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
28050 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
28052 * Number of dimensions for this nvm configuration variable.
28053 * This value indicates how many of the indexN values to use.
28054 * A value of 0 means that none of the indexN values are valid.
28055 * A value of 1 requires at index0 is valued, a value of 2
28056 * requires that index0 and index1 are valid, and so forth
28058 uint16_t dimensions;
28059 /* index for the 1st dimensions */
28061 /* index for the 2nd dimensions */
28063 /* index for the 3rd dimensions */
28065 /* index for the 4th dimensions */
28067 uint8_t unused_0[2];
28068 } __attribute__((packed));
28070 /* hwrm_nvm_validate_option_output (size:128b/16B) */
28071 struct hwrm_nvm_validate_option_output {
28072 /* The specific error status for the command. */
28073 uint16_t error_code;
28074 /* The HWRM command request type. */
28076 /* The sequence ID from the original command. */
28078 /* The length of the response data in number of bytes. */
28081 /* indicates that the value provided for the option is not matching with the saved data. */
28082 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
28083 /* indicates that the value provided for the option is matching the saved data. */
28084 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
28085 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
28086 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
28087 uint8_t unused_0[6];
28089 * This field is used in Output records to indicate that the output
28090 * is completely written to RAM. This field should be read as '1'
28091 * to indicate that the output has been completely written.
28092 * When writing a command completion or response to an internal processor,
28093 * the order of writes has to be such that this field is written last.
28096 } __attribute__((packed));
28098 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
28099 struct hwrm_nvm_validate_option_cmd_err {
28101 * command specific error codes that goes to
28102 * the cmd_err field in Common HWRM Error Response.
28105 /* Unknown error */
28106 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
28107 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
28108 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
28109 uint8_t unused_0[7];
28110 } __attribute__((packed));
28112 /*****************************
28113 * hwrm_nvm_factory_defaults *
28114 *****************************/
28117 /* hwrm_nvm_factory_defaults_input (size:192b/24B) */
28118 struct hwrm_nvm_factory_defaults_input {
28119 /* The HWRM command request type. */
28122 * The completion ring to send the completion event on. This should
28123 * be the NQ ID returned from the `nq_alloc` HWRM command.
28125 uint16_t cmpl_ring;
28127 * The sequence ID is used by the driver for tracking multiple
28128 * commands. This ID is treated as opaque data by the firmware and
28129 * the value is returned in the `hwrm_resp_hdr` upon completion.
28133 * The target ID of the command:
28134 * * 0x0-0xFFF8 - The function ID
28135 * * 0xFFF8-0xFFFE - Reserved for internal processors
28138 uint16_t target_id;
28140 * A physical address pointer pointing to a host buffer that the
28141 * command's response data will be written. This can be either a host
28142 * physical address (HPA) or a guest physical address (GPA) and must
28143 * point to a physically contiguous block of memory.
28145 uint64_t resp_addr;
28148 /* If set to 1, it will trigger restoration of factory default settings */
28149 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
28150 /* If set to 1, it will trigger creation of factory default settings */
28151 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
28152 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \
28153 HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE
28154 uint8_t unused_0[7];
28155 } __attribute__((packed));
28157 /* hwrm_nvm_factory_defaults_output (size:128b/16B) */
28158 struct hwrm_nvm_factory_defaults_output {
28159 /* The specific error status for the command. */
28160 uint16_t error_code;
28161 /* The HWRM command request type. */
28163 /* The sequence ID from the original command. */
28165 /* The length of the response data in number of bytes. */
28168 /* factory defaults created successfully. */
28169 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \
28171 /* factory defaults restored successfully. */
28172 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \
28174 /* factory defaults already created. */
28175 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \
28177 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \
28178 HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY
28179 uint8_t unused_0[6];
28181 * This field is used in Output records to indicate that the output
28182 * is completely written to RAM. This field should be read as '1'
28183 * to indicate that the output has been completely written.
28184 * When writing a command completion or response to an internal processor,
28185 * the order of writes has to be such that this field is written last.
28188 } __attribute__((packed));
28190 /* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */
28191 struct hwrm_nvm_factory_defaults_cmd_err {
28193 * command specific error codes that goes to
28194 * the cmd_err field in Common HWRM Error Response.
28197 /* Unknown error */
28198 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \
28200 /* valid configuration not present to create defaults */
28201 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \
28203 /* No saved configuration present to restore, restore failed */
28204 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \
28206 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \
28207 HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG
28208 uint8_t unused_0[7];
28209 } __attribute__((packed));
28211 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */