1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2021 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
273 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
274 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
275 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
276 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
277 /* Reserved for future use. */
278 #define HWRM_RESERVED1 UINT32_C(0x10)
279 #define HWRM_FUNC_RESET UINT32_C(0x11)
280 #define HWRM_FUNC_GETFID UINT32_C(0x12)
281 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
282 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
283 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
284 #define HWRM_FUNC_QCFG UINT32_C(0x16)
285 #define HWRM_FUNC_CFG UINT32_C(0x17)
286 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
287 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
288 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
289 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
290 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
291 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
292 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
293 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
294 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
295 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
297 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
298 #define HWRM_PORT_QSTATS UINT32_C(0x23)
299 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
301 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
303 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
304 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
305 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
307 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
308 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
309 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
310 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
311 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
312 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
313 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
314 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
315 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
316 #define HWRM_QUEUE_CFG UINT32_C(0x32)
317 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
318 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
319 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
320 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
321 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
322 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
323 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
324 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
325 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
326 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
327 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
328 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
329 #define HWRM_VNIC_FREE UINT32_C(0x41)
330 #define HWRM_VNIC_CFG UINT32_C(0x42)
331 #define HWRM_VNIC_QCFG UINT32_C(0x43)
332 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
334 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
335 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
336 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
337 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
338 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
339 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
340 /* Updates specific fields in RX VNIC structure */
341 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
342 #define HWRM_RING_ALLOC UINT32_C(0x50)
343 #define HWRM_RING_FREE UINT32_C(0x51)
344 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
345 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
346 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
347 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
348 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
349 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
350 #define HWRM_RING_RESET UINT32_C(0x5e)
351 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
352 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
353 #define HWRM_RING_CFG UINT32_C(0x62)
354 #define HWRM_RING_QCFG UINT32_C(0x63)
355 /* Reserved for future use. */
356 #define HWRM_RESERVED5 UINT32_C(0x64)
357 /* Reserved for future use. */
358 #define HWRM_RESERVED6 UINT32_C(0x65)
359 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
360 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
361 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
362 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
363 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
364 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
365 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
366 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
367 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
368 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
369 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
370 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
371 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
372 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
373 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
375 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
377 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
378 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
379 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
380 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
382 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
384 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
386 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
387 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
388 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
389 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
390 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
391 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
392 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
393 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
394 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
395 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
396 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
397 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
398 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
399 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
400 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
402 #define HWRM_RESERVED7 UINT32_C(0xba)
403 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
404 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
405 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
406 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
407 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
408 #define HWRM_FW_RESET UINT32_C(0xc0)
409 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
410 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
411 #define HWRM_FW_SYNC UINT32_C(0xc3)
412 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
413 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
414 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
415 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
417 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
419 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
421 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
423 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
425 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
426 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
427 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
428 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
429 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
430 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
431 #define HWRM_FWD_RESP UINT32_C(0xd2)
432 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
433 #define HWRM_OEM_CMD UINT32_C(0xd4)
434 /* Tells the fw to run PRBS test on a given port and lane. */
435 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
436 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
437 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
438 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
439 /* Tells the fw to collect dsc dump on a given port and lane. */
440 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
441 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
442 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
443 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
444 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
445 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
446 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
447 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
448 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
450 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
452 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
454 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
456 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
458 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
460 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
462 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
464 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
466 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
468 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
470 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
472 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
474 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
476 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
478 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
480 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
482 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
484 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
486 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
487 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
488 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
489 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
491 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
493 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
495 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
497 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
498 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
499 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
501 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
503 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
505 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
507 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
509 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
511 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
513 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
515 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
517 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
519 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
521 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
523 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
525 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
527 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
529 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
531 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
533 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
535 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
536 /* Experimental - DEPRECATED */
537 #define HWRM_CFA_TFLIB UINT32_C(0x125)
538 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
539 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
540 /* Engine CKV - Add a new CKEK used to encrypt keys. */
541 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
542 /* Engine CKV - Delete a previously added CKEK. */
543 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
544 /* Engine CKV - Add a new key to the key vault. */
545 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
546 /* Engine CKV - Delete a key from the key vault. */
547 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
548 /* Engine CKV - Delete all keys from the key vault. */
549 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
550 /* Engine CKV - Get random data. */
551 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
552 /* Engine CKV - Generate and encrypt a new AES key. */
553 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
554 /* Engine CKV - Configure a label index with a label value. */
555 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
556 /* Engine CKV - Query a label */
557 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
558 /* Engine - Query the available queue groups configuration. */
559 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
560 /* Engine - Query the queue groups assigned to a function. */
561 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
562 /* Engine - Query the available queue group meter profile configuration. */
563 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
564 /* Engine - Query the configuration of a queue group meter profile. */
565 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
566 /* Engine - Allocate a queue group meter profile. */
567 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
568 /* Engine - Free a queue group meter profile. */
569 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
570 /* Engine - Query the meters assigned to a queue group. */
571 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
572 /* Engine - Bind a queue group meter profile to a queue group. */
573 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
574 /* Engine - Unbind a queue group meter profile from a queue group. */
575 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
576 /* Engine - Bind a queue group to a function. */
577 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
578 /* Engine - Query the scheduling group configuration. */
579 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
580 /* Engine - Query the queue groups assigned to a scheduling group. */
581 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
582 /* Engine - Query the configuration of a scheduling group's meter profiles. */
583 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
584 /* Engine - Configure a scheduling group's meter profiles. */
585 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
586 /* Engine - Bind a queue group to a scheduling group. */
587 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
588 /* Engine - Unbind a queue group from its scheduling group. */
589 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
590 /* Engine - Query the Engine configuration. */
591 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
592 /* Engine - Configure the statistics accumulator for an Engine. */
593 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
594 /* Engine - Clear the statistics accumulator for an Engine. */
595 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
596 /* Engine - Query the statistics accumulator for an Engine. */
597 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
598 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
599 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
600 /* Engine - Allocate an Engine RQ. */
601 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
602 /* Engine - Free an Engine RQ. */
603 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
604 /* Engine - Allocate an Engine CQ. */
605 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
606 /* Engine - Free an Engine CQ. */
607 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
608 /* Engine - Allocate an NQ. */
609 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
610 /* Engine - Free an NQ. */
611 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
612 /* Engine - Set the on-die RQE credit update location. */
613 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
614 /* Engine - Query the engine function configuration. */
615 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
617 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
619 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
621 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
623 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
625 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
626 /* Configures the BW of any VF */
627 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
628 /* Queries the BW of any VF */
629 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
630 /* Queries pf ids belong to specified host(s) */
631 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
632 /* Queries extended stats per function */
633 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
634 /* Queries extended statistics context */
635 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
636 /* Configure SoC packet DMA settings */
637 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
638 /* Query SoC packet DMA settings */
639 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
641 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
643 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
645 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
647 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
649 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
651 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
652 /* Returns the current value of a free running counter from the device. */
653 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
655 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
657 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
659 * Tells the fw to run the DMA read from the host and DMA write
662 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
663 /* Tells the fw to program the fru memory */
664 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
665 /* Tells the fw to read the fru memory */
666 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
667 /* Used to provision SoC software images */
668 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
669 /* Retrieves the SoC status and image provisioning information */
670 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
671 /* Tells the fw to program the seeprom memory */
672 #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
673 /* Tells the fw to read the seeprom memory */
674 #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
675 /* Tells the fw to get the health of seeprom data */
676 #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
678 #define HWRM_TF UINT32_C(0x2bc)
680 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
682 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
684 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
686 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
688 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
690 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
692 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
694 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
696 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
698 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
700 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
702 #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
704 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
706 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
708 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
710 #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
712 #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
714 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
716 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
718 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
720 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
722 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
724 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
726 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
728 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
730 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
732 #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
734 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
736 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
738 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
740 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
742 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
744 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
746 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
748 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
750 #define HWRM_SV UINT32_C(0x400)
752 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
754 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
756 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
758 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
759 #define HWRM_DBG_DUMP UINT32_C(0xff14)
761 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
763 #define HWRM_DBG_CFG UINT32_C(0xff16)
765 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
767 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
769 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
771 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
773 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
775 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
777 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
779 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
780 /* Send driver debug information to firmware */
781 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
782 /* Query debug capabilities of firmware */
783 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
784 /* Retrieve debug settings of firmware */
785 #define HWRM_DBG_QCFG UINT32_C(0xff21)
786 /* Set destination parameters for crashdump medium */
787 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
788 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
790 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
791 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
792 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
793 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
794 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
795 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
796 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
797 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
798 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
799 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
800 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
801 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
802 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
803 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
804 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
805 #define HWRM_NVM_READ UINT32_C(0xfffd)
806 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
807 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
808 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
809 uint16_t unused_0[3];
813 /* ret_codes (size:64b/8B) */
816 /* Request was successfully executed by the HWRM. */
817 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
818 /* The HWRM failed to execute the request. */
819 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
821 * The request contains invalid argument(s) or input
824 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
826 * The requester is not allowed to access the requested
827 * resource. This error code shall be provided in a
828 * response to a request to query or modify an existing
829 * resource that is not accessible by the requester.
831 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
833 * The HWRM is unable to allocate the requested resource.
834 * This code only applies to requests for HWRM resource
837 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
839 * Invalid combination of flags is specified in the
842 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
844 * Invalid combination of enables fields is specified in
847 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
849 * Request contains a required TLV that is not supported by
850 * the installed version of firmware.
852 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
854 * No firmware buffer available to accept the request. Driver
855 * should retry the request.
857 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
859 * This error code is only reported by firmware when some
860 * sub-option of a supported HWRM command is unsupported.
862 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
864 * This error code is only reported by firmware when the specific
865 * request is not able to process when the HOT reset in progress.
867 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
869 * This error code is only reported by firmware when the registered
870 * driver instances are not capable of hot reset.
872 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
874 * This error code is only reported by the firmware when during
875 * flow allocation when a request for a flow counter fails because
876 * the number of flow counters are exhausted.
878 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
880 * This error code is only reported by firmware when the registered
881 * driver instances requested to offloaded a flow but was unable to because
882 * the requested key's hash collides with the installed keys.
884 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
886 * This error code is only reported by firmware when the registered
887 * driver instances requested to offloaded a flow but was unable to because
888 * the same key has already been installed.
890 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
892 * Generic HWRM execution error that represents an
895 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
897 * Firmware is unable to service the request at the present time. Caller
898 * may try again later.
900 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
902 * This error code is reported by Firmware when an operation requested
903 * by the host is not allowed due to a secure lock violation.
905 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
907 * This value indicates that the HWRM response is in TLV format and
908 * should be interpreted as one or more TLVs starting with the
909 * hwrm_resp_hdr TLV. This value is not an indication of any error
910 * by itself, just an indication that the response should be parsed
911 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
913 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
915 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
916 /* Unsupported or invalid command */
917 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
918 #define HWRM_ERR_CODE_LAST \
919 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
920 uint16_t unused_0[3];
924 /* hwrm_err_output (size:128b/16B) */
925 struct hwrm_err_output {
927 * Pass/Fail or error type
929 * Note: receiver to verify the in parameters, and fail the call
930 * with an error when appropriate
933 /* This field returns the type of original request. */
935 /* This field provides original sequence number of the command. */
938 * This field is the length of the response in bytes. The
939 * last byte of the response is a valid flag that will read
940 * as '1' when the command has been completely written to
944 /* debug info for this error response. */
946 /* debug info for this error response. */
949 * In the case of an error response, command specific error
950 * code is returned in this field.
954 * This field is used in Output records to indicate that the output
955 * is completely written to RAM. This field should be read as '1'
956 * to indicate that the output has been completely written.
957 * When writing a command completion or response to an internal processor,
958 * the order of writes has to be such that this field is written last.
963 * Following is the signature for HWRM message field that indicates not
964 * applicable (All F's). Need to cast it the size of the field if needed.
966 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
967 /* hwrm_func_buf_rgtr */
968 #define HWRM_MAX_REQ_LEN 128
969 /* hwrm_cfa_flow_info */
970 #define HWRM_MAX_RESP_LEN 704
971 /* 7 bit indirection table index. */
972 #define HW_HASH_INDEX_SIZE 0x80
973 #define HW_HASH_KEY_SIZE 40
974 /* valid key for HWRM response */
975 #define HWRM_RESP_VALID_KEY 1
976 /* Reserved for BONO processor */
977 #define HWRM_TARGET_ID_BONO 0xFFF8
978 /* Reserved for KONG processor */
979 #define HWRM_TARGET_ID_KONG 0xFFF9
980 /* Reserved for APE processor */
981 #define HWRM_TARGET_ID_APE 0xFFFA
983 * This value will be used by tools for User-space HWRM Interface.
984 * When tool execute any HWRM command with this target_id, firmware
985 * will copy the response and/or data payload via register space instead
988 #define HWRM_TARGET_ID_TOOLS 0xFFFD
989 #define HWRM_VERSION_MAJOR 1
990 #define HWRM_VERSION_MINOR 10
991 #define HWRM_VERSION_UPDATE 2
992 /* non-zero means beta version */
993 #define HWRM_VERSION_RSVD 22
994 #define HWRM_VERSION_STR "1.10.2.22"
1001 /* hwrm_ver_get_input (size:192b/24B) */
1002 struct hwrm_ver_get_input {
1003 /* The HWRM command request type. */
1006 * The completion ring to send the completion event on. This should
1007 * be the NQ ID returned from the `nq_alloc` HWRM command.
1011 * The sequence ID is used by the driver for tracking multiple
1012 * commands. This ID is treated as opaque data by the firmware and
1013 * the value is returned in the `hwrm_resp_hdr` upon completion.
1017 * The target ID of the command:
1018 * * 0x0-0xFFF8 - The function ID
1019 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1020 * * 0xFFFD - Reserved for user-space HWRM interface
1025 * A physical address pointer pointing to a host buffer that the
1026 * command's response data will be written. This can be either a host
1027 * physical address (HPA) or a guest physical address (GPA) and must
1028 * point to a physically contiguous block of memory.
1032 * This field represents the major version of HWRM interface
1033 * specification supported by the driver HWRM implementation.
1034 * The interface major version is intended to change only when
1035 * non backward compatible changes are made to the HWRM
1036 * interface specification.
1038 uint8_t hwrm_intf_maj;
1040 * This field represents the minor version of HWRM interface
1041 * specification supported by the driver HWRM implementation.
1042 * A change in interface minor version is used to reflect
1043 * significant backward compatible modification to HWRM
1044 * interface specification.
1045 * This can be due to addition or removal of functionality.
1046 * HWRM interface specifications with the same major version
1047 * but different minor versions are compatible.
1049 uint8_t hwrm_intf_min;
1051 * This field represents the update version of HWRM interface
1052 * specification supported by the driver HWRM implementation.
1053 * The interface update version is used to reflect minor
1054 * changes or bug fixes to a released HWRM interface
1057 uint8_t hwrm_intf_upd;
1058 uint8_t unused_0[5];
1061 /* hwrm_ver_get_output (size:1408b/176B) */
1062 struct hwrm_ver_get_output {
1063 /* The specific error status for the command. */
1064 uint16_t error_code;
1065 /* The HWRM command request type. */
1067 /* The sequence ID from the original command. */
1069 /* The length of the response data in number of bytes. */
1072 * This field represents the major version of HWRM interface
1073 * specification supported by the HWRM implementation.
1074 * The interface major version is intended to change only when
1075 * non backward compatible changes are made to the HWRM
1076 * interface specification.
1077 * A HWRM implementation that is compliant with this
1078 * specification shall provide value of 1 in this field.
1080 uint8_t hwrm_intf_maj_8b;
1082 * This field represents the minor version of HWRM interface
1083 * specification supported by the HWRM implementation.
1084 * A change in interface minor version is used to reflect
1085 * significant backward compatible modification to HWRM
1086 * interface specification.
1087 * This can be due to addition or removal of functionality.
1088 * HWRM interface specifications with the same major version
1089 * but different minor versions are compatible.
1090 * A HWRM implementation that is compliant with this
1091 * specification shall provide value of 2 in this field.
1093 uint8_t hwrm_intf_min_8b;
1095 * This field represents the update version of HWRM interface
1096 * specification supported by the HWRM implementation.
1097 * The interface update version is used to reflect minor
1098 * changes or bug fixes to a released HWRM interface
1100 * A HWRM implementation that is compliant with this
1101 * specification shall provide value of 2 in this field.
1103 uint8_t hwrm_intf_upd_8b;
1104 uint8_t hwrm_intf_rsvd_8b;
1106 * This field represents the major version of HWRM firmware.
1107 * A change in firmware major version represents a major
1110 uint8_t hwrm_fw_maj_8b;
1112 * This field represents the minor version of HWRM firmware.
1113 * A change in firmware minor version represents significant
1114 * firmware functionality changes.
1116 uint8_t hwrm_fw_min_8b;
1118 * This field represents the build version of HWRM firmware.
1119 * A change in firmware build version represents bug fixes
1120 * to a released firmware.
1122 uint8_t hwrm_fw_bld_8b;
1124 * This field is a reserved field. This field can be used to
1125 * represent firmware branches or customer specific releases
1126 * tied to a specific (major,minor,update) version of the
1129 uint8_t hwrm_fw_rsvd_8b;
1131 * This field represents the major version of mgmt firmware.
1132 * A change in major version represents a major release.
1134 uint8_t mgmt_fw_maj_8b;
1136 * This field represents the minor version of mgmt firmware.
1137 * A change in minor version represents significant
1138 * functionality changes.
1140 uint8_t mgmt_fw_min_8b;
1142 * This field represents the build version of mgmt firmware.
1143 * A change in update version represents bug fixes.
1145 uint8_t mgmt_fw_bld_8b;
1147 * This field is a reserved field. This field can be used to
1148 * represent firmware branches or customer specific releases
1149 * tied to a specific (major,minor,update) version
1151 uint8_t mgmt_fw_rsvd_8b;
1153 * This field represents the major version of network
1155 * A change in major version represents a major release.
1157 uint8_t netctrl_fw_maj_8b;
1159 * This field represents the minor version of network
1161 * A change in minor version represents significant
1162 * functionality changes.
1164 uint8_t netctrl_fw_min_8b;
1166 * This field represents the build version of network
1168 * A change in update version represents bug fixes.
1170 uint8_t netctrl_fw_bld_8b;
1172 * This field is a reserved field. This field can be used to
1173 * represent firmware branches or customer specific releases
1174 * tied to a specific (major,minor,update) version
1176 uint8_t netctrl_fw_rsvd_8b;
1178 * This field is used to indicate device's capabilities and
1181 uint32_t dev_caps_cfg;
1183 * If set to 1, then secure firmware update behavior
1185 * If set to 0, then secure firmware update behavior is
1188 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1191 * If set to 1, then firmware based DCBX agent is supported.
1192 * If set to 0, then firmware based DCBX agent capability
1193 * is not supported on this device.
1195 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1198 * If set to 1, then HWRM short command format is supported.
1199 * If set to 0, then HWRM short command format is not supported.
1201 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1204 * If set to 1, then HWRM short command format is required.
1205 * If set to 0, then HWRM short command format is not required.
1207 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1210 * If set to 1, then the KONG host mailbox channel is supported.
1211 * If set to 0, then the KONG host mailbox channel is not supported.
1212 * By default, this flag should be 0 for older version of core firmware.
1214 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1217 * If set to 1, then the 64bit flow handle is supported in addition to the
1218 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1219 * supported. By default, this flag should be 0 for older version of core firmware.
1221 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1224 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1225 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1226 * If set to 0, then filter types not supported.
1227 * By default, this flag should be 0 for older version of core firmware.
1229 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1232 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1233 * If set to 0, firmware can't supported virtio vSwitch offload model.
1234 * By default, this flag should be 0 for older version of core firmware.
1236 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1239 * If set to 1, firmware is capable to support trusted VF.
1240 * If set to 0, firmware is not capable to support trusted VF.
1241 * By default, this flag should be 0 for older version of core firmware.
1243 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1246 * If set to 1, firmware is capable to support flow aging.
1247 * If set to 0, firmware is not capable to support flow aging.
1248 * By default, this flag should be 0 for older version of core firmware.
1250 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1253 * If set to 1, firmware is capable to support advanced flow counters like,
1254 * Meter drop counters and EEM counters.
1255 * If set to 0, firmware is not capable to support advanced flow counters.
1256 * By default, this flag should be 0 for older version of core firmware.
1258 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1261 * If set to 1, the firmware is able to support the use of the CFA
1262 * Extended Exact Match(EEM) feature.
1263 * If set to 0, firmware is not capable to support the use of the
1265 * By default, this flag should be 0 for older version of core firmware.
1267 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1270 * If set to 1, the firmware is able to support advance CFA flow management
1271 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1272 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1274 * By default, this flag should be 0 for older version of core firmware.
1276 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1279 * Deprecated and replaced with cfa_truflow_supported.
1280 * If set to 1, the firmware is able to support TFLIB features.
1281 * If set to 0, then the firmware doesn’t support TFLIB features.
1282 * By default, this flag should be 0 for older version of core firmware.
1284 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1287 * If set to 1, the firmware is able to support TruFlow features.
1288 * If set to 0, then the firmware doesn’t support TruFlow features.
1289 * By default, this flag should be 0 for older version of
1292 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1295 * This field represents the major version of RoCE firmware.
1296 * A change in major version represents a major release.
1298 uint8_t roce_fw_maj_8b;
1300 * This field represents the minor version of RoCE firmware.
1301 * A change in minor version represents significant
1302 * functionality changes.
1304 uint8_t roce_fw_min_8b;
1306 * This field represents the build version of RoCE firmware.
1307 * A change in update version represents bug fixes.
1309 uint8_t roce_fw_bld_8b;
1311 * This field is a reserved field. This field can be used to
1312 * represent firmware branches or customer specific releases
1313 * tied to a specific (major,minor,update) version
1315 uint8_t roce_fw_rsvd_8b;
1317 * This field represents the name of HWRM FW (ASCII chars
1318 * with NULL at the end).
1320 char hwrm_fw_name[16];
1322 * This field represents the name of mgmt FW (ASCII chars
1323 * with NULL at the end).
1325 char mgmt_fw_name[16];
1327 * This field represents the name of network control
1328 * firmware (ASCII chars with NULL at the end).
1330 char netctrl_fw_name[16];
1331 /* This field represents the active board package name. */
1332 char active_pkg_name[16];
1334 * This field represents the name of RoCE FW (ASCII chars
1335 * with NULL at the end).
1337 char roce_fw_name[16];
1338 /* This field returns the chip number. */
1340 /* This field returns the revision of chip. */
1342 /* This field returns the chip metal number. */
1344 /* This field returns the bond id of the chip. */
1345 uint8_t chip_bond_id;
1346 /* This value indicates the type of platform used for chip implementation. */
1347 uint8_t chip_platform_type;
1349 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1350 /* FPGA platform of the chip. */
1351 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1352 /* Palladium platform of the chip. */
1353 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1354 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1355 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1357 * This field returns the maximum value of request window that
1358 * is supported by the HWRM. The request window is mapped
1359 * into device address space using MMIO.
1361 uint16_t max_req_win_len;
1363 * This field returns the maximum value of response buffer in
1366 uint16_t max_resp_len;
1368 * This field returns the default request timeout value in
1371 uint16_t def_req_timeout;
1373 * This field will indicate if any subsystems is not fully
1378 * If set to 1, it will indicate to host drivers that firmware is
1379 * not ready to start full blown HWRM commands. Host drivers should
1380 * re-try HWRM_VER_GET with some timeout period. The timeout period
1381 * can be selected up to 5 seconds. Host drivers should also check
1382 * for dev_not_rdy_backing_store to identify if flag is set due to
1383 * backing store not been available.
1384 * For Example, PCIe hot-plug:
1385 * Hot plug timing is system dependent. It generally takes up to
1386 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1387 * If set to 0, device is ready to accept all HWRM commands.
1389 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \
1392 * If set to 1, external version present.
1393 * If set to 0, external version not present.
1395 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \
1398 * Firmware sets this flag along with dev_not_rdy flag to indicate
1399 * host drivers that it has not completed resource initialization
1400 * required for data path operations. Host drivers should not send
1401 * any HWRM command that requires data path resources. Firmware will
1402 * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
1403 * those commands once both the flags are cleared.
1404 * If this flag and dev_not_rdy flag are set to 0, device is ready
1405 * to accept all HWRM commands.
1407 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \
1409 uint8_t unused_0[2];
1411 * For backward compatibility this field must be set to 1.
1412 * Older drivers might look for this field to be 1 before
1413 * processing the message.
1417 * This field represents the major version of HWRM interface
1418 * specification supported by the HWRM implementation.
1419 * The interface major version is intended to change only when
1420 * non backward compatible changes are made to the HWRM
1421 * interface specification. A HWRM implementation that is
1422 * compliant with this specification shall provide value of 1
1425 uint16_t hwrm_intf_major;
1427 * This field represents the minor version of HWRM interface
1428 * specification supported by the HWRM implementation.
1429 * A change in interface minor version is used to reflect
1430 * significant backward compatible modification to HWRM
1431 * interface specification. This can be due to addition or
1432 * removal of functionality. HWRM interface specifications
1433 * with the same major version but different minor versions are
1434 * compatible. A HWRM implementation that is compliant with
1435 * this specification shall provide value of 2 in this field.
1437 uint16_t hwrm_intf_minor;
1439 * This field represents the update version of HWRM interface
1440 * specification supported by the HWRM implementation. The
1441 * interface update version is used to reflect minor changes or
1442 * bug fixes to a released HWRM interface specification.
1443 * A HWRM implementation that is compliant with this
1444 * specification shall provide value of 2 in this field.
1446 uint16_t hwrm_intf_build;
1448 * This field represents the patch version of HWRM interface
1449 * specification supported by the HWRM implementation.
1451 uint16_t hwrm_intf_patch;
1453 * This field represents the major version of HWRM firmware.
1454 * A change in firmware major version represents a major
1457 uint16_t hwrm_fw_major;
1459 * This field represents the minor version of HWRM firmware.
1460 * A change in firmware minor version represents significant
1461 * firmware functionality changes.
1463 uint16_t hwrm_fw_minor;
1465 * This field represents the build version of HWRM firmware.
1466 * A change in firmware build version represents bug fixes to
1467 * a released firmware.
1469 uint16_t hwrm_fw_build;
1471 * This field is a reserved field.
1472 * This field can be used to represent firmware branches or customer
1473 * specific releases tied to a specific (major,minor,update) version
1474 * of the HWRM firmware.
1476 uint16_t hwrm_fw_patch;
1478 * This field represents the major version of mgmt firmware.
1479 * A change in major version represents a major release.
1481 uint16_t mgmt_fw_major;
1483 * This field represents the minor version of HWRM firmware.
1484 * A change in firmware minor version represents significant
1485 * firmware functionality changes.
1487 uint16_t mgmt_fw_minor;
1489 * This field represents the build version of mgmt firmware.
1490 * A change in update version represents bug fixes.
1492 uint16_t mgmt_fw_build;
1494 * This field is a reserved field. This field can be used to
1495 * represent firmware branches or customer specific releases
1496 * tied to a specific (major,minor,update) version.
1498 uint16_t mgmt_fw_patch;
1500 * This field represents the major version of network control
1501 * firmware. A change in major version represents
1504 uint16_t netctrl_fw_major;
1506 * This field represents the minor version of network control
1507 * firmware. A change in minor version represents significant
1508 * functionality changes.
1510 uint16_t netctrl_fw_minor;
1512 * This field represents the build version of network control
1513 * firmware. A change in update version represents bug fixes.
1515 uint16_t netctrl_fw_build;
1517 * This field is a reserved field. This field can be used to
1518 * represent firmware branches or customer specific releases
1519 * tied to a specific (major,minor,update) version
1521 uint16_t netctrl_fw_patch;
1523 * This field represents the major version of RoCE firmware.
1524 * A change in major version represents a major release.
1526 uint16_t roce_fw_major;
1528 * This field represents the minor version of RoCE firmware.
1529 * A change in minor version represents significant
1530 * functionality changes.
1532 uint16_t roce_fw_minor;
1534 * This field represents the build version of RoCE firmware.
1535 * A change in update version represents bug fixes.
1537 uint16_t roce_fw_build;
1539 * This field is a reserved field. This field can be used to
1540 * represent firmware branches or customer specific releases
1541 * tied to a specific (major,minor,update) version
1543 uint16_t roce_fw_patch;
1545 * This field returns the maximum extended request length acceptable
1546 * by the device which allows requests greater than mailbox size when
1547 * used with the short cmd request format.
1549 uint16_t max_ext_req_len;
1550 uint8_t unused_1[5];
1552 * This field is used in Output records to indicate that the output
1553 * is completely written to RAM. This field should be read as '1'
1554 * to indicate that the output has been completely written.
1555 * When writing a command completion or response to an internal processor,
1556 * the order of writes has to be such that this field is written last.
1561 /* cfa_bds_read_cmd_data_msg (size:128b/16B) */
1562 struct cfa_bds_read_cmd_data_msg {
1563 /* This value selects the format for the mid-path command for the CFA. */
1566 * This is read command. From 32 to 128B can be read from a table
1567 * using this command.
1569 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
1570 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST \
1571 CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
1572 /* This value selects the table type to be acted upon. */
1574 /* This value selects the table type to be acted upon. */
1575 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1576 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1577 /* This command acts on the action table of the specified scope. */
1578 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1579 /* This command acts on the exact match table of the specified scope. */
1580 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1581 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST \
1582 CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
1583 /* This value selects which table scope will be accessed. */
1584 uint8_t table_scope;
1585 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1586 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1588 * This value identifies the number of 32B units will be accessed. A
1589 * value of zero is invalid. Maximum value is 4.
1592 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1593 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
1594 /* This is the 32B index into the selected table to access. */
1595 uint32_t table_index;
1596 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1597 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1599 * This is the 64b host address where you want the data returned to. The
1600 * data will be written to the same function as the one that owns the SQ
1601 * this command is read from. The bottom two bits of this value must be
1602 * zero. The size of the write is controlled by the data_size field.
1604 uint64_t host_address;
1607 /* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
1608 struct cfa_bds_write_cmd_data_msg {
1609 /* This value selects the format for the mid-path command for the CFA. */
1612 * This is write command. From 32 to 128B can be written to a table
1613 * using this command.
1615 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
1616 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST \
1617 CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
1618 /* This value selects the table type to be acted upon. */
1619 uint8_t write_thru_table_type;
1620 /* This value selects the table type to be acted upon. */
1621 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1622 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1623 /* This command acts on the action table of the specified scope. */
1624 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1625 /* This command acts on the exact match table of the specified scope. */
1626 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1627 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1628 CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
1630 * Indicates write-through control. Indicates write-through when set,
1631 * or write back when cleared.
1633 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1634 /* This value selects which table scope will be accessed. */
1635 uint8_t table_scope;
1636 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1637 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1639 * This value identifies the number of 32B units will be accessed. A
1640 * value of zero is invalid. Maximum value is 4.
1643 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1644 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1645 /* This is the 32B index into the selected table to access. */
1646 uint32_t table_index;
1647 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
1648 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1652 * This is the data to be written. Data length is determined by the
1653 * data_size field. The bd_cnt in the encapsulating BD must also be set
1654 * correctly to ensure that the BD is processed correctly and the full
1655 * WRITE_CMD message is extracted from the BD.
1660 /* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
1661 struct cfa_bds_read_clr_cmd_data_msg {
1662 /* This value selects the format for the mid-path command for the CFA. */
1665 * This is read-clear command. 32B can be read from a table and
1666 * a 16b mask can be used to clear specific 16b units after the
1667 * read as an atomic operation.
1669 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
1670 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST \
1671 CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
1672 /* This value selects the table type to be acted upon. */
1674 /* This value selects the table type to be acted upon. */
1675 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1676 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1677 /* This command acts on the action table of the specified scope. */
1678 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
1679 /* This command acts on the exact match table of the specified scope. */
1680 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
1681 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST \
1682 CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
1683 /* This value selects which table scope will be accessed. */
1684 uint8_t table_scope;
1685 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1686 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1688 * This value identifies the number of 32B units will be accessed.
1689 * Always set the value to 1.
1692 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1693 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
1694 /* This is the 32B index into the selected table to access. */
1695 uint32_t table_index;
1696 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \
1698 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1700 * This is the 64b host address where you want the data returned to. The
1701 * data will be written to the same function as the one that owns the SQ
1702 * this command is read from. The bottom two bits of this value must be
1703 * zero. The size of the write is controlled by the data_size field.
1705 uint64_t host_address;
1707 * This is active high clear mask for the 32B of data that this command
1708 * can read. Bit 0 of the field will clear bits 15:0 of the first word
1709 * of data read when set to '1'.
1711 uint16_t clear_mask;
1712 uint16_t unused0[3];
1713 uint16_t unused1[4];
1716 /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
1717 struct cfa_bds_em_insert_cmd_data_msg {
1718 /* This value selects the format for the mid-path command for the CFA. */
1721 * An exact match table insert will be attempted into the table.
1722 * If there is a free location in the bucket, the payload will
1723 * be written to the bucket.
1725 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
1726 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST \
1727 CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
1729 * Indicates write-through control. Indicates write-through when set,
1730 * or write back when cleared.
1733 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1734 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
1736 * Indicates write-through control. Indicates write-through when set,
1737 * or write back when cleared.
1739 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1740 /* This value selects which table scope will be accessed. */
1741 uint8_t table_scope;
1742 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1743 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1745 * This value identifies the number of 32B units will be accessed. A
1746 * value of zero is invalid. Maximum value is 4.
1749 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1750 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1751 /* This is the 32B index into the selected table to access. */
1752 uint32_t table_index;
1753 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK \
1755 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1757 * This is the 64b host address where you want the data returned to. The
1758 * data will be written to the same function as the one that owns the SQ
1760 uint64_t host_address;
1762 * This is the Exact Match Lookup Record. Data length is determined by
1763 * the data_size field. The bd_cnt in the encapsulating BD must also be
1768 /* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
1769 struct cfa_bds_em_delete_cmd_data_msg {
1770 /* This value selects the format for the mid-path command for the CFA. */
1772 /* An exact match table delete will be attempted. */
1773 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
1774 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST \
1775 CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
1777 * Indicates write-through control. Indicates write-through when set,
1778 * or write back when cleared.
1781 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
1782 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
1784 * Indicates write-through control. Indicates write-through when set,
1785 * or write back when cleared.
1787 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
1788 /* This value selects which table scope will be accessed. */
1789 uint8_t table_scope;
1790 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1791 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1793 * This value identifies the number of 32B units will be accessed. A
1794 * value of zero is invalid. Maximum value is 4.
1797 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1798 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1801 * This is the 64b host address where you want the data returned to. The
1802 * data will be written to the same function as the one that owns the SQ
1804 uint64_t host_address;
1806 * This is the Exact Match Lookup Record. Data length is determined by
1807 * the data_size field. The bd_cnt in the encapsulating BD must also be
1810 uint32_t unused1[2];
1813 /* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
1814 struct cfa_bds_invalidate_cmd_data_msg {
1815 /* This value selects the format for the mid-path command for the CFA. */
1818 * The specified table area will be invalidated. If it is needed.
1819 * again, it will be read from the backing store.
1821 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
1822 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST \
1823 CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
1824 /* This value selects the table type to be acted upon. */
1826 /* This value selects the table type to be acted upon. */
1827 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
1828 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
1829 /* This command acts on the action table of the specified scope. */
1830 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION \
1832 /* This command acts on the exact match table of the specified scope. */
1833 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM \
1835 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST \
1836 CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
1837 /* This value selects which table scope will be accessed. */
1838 uint8_t table_scope;
1839 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
1840 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1841 /* This value specifies the number of cache lines to invalidate. */
1843 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1844 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
1845 /* This is the 32B index into the selected table to access. */
1846 uint32_t table_index;
1847 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \
1849 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
1853 /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
1854 struct cfa_bds_event_collect_cmd_data_msg {
1855 /* This value selects the format for the mid-path command for the CFA. */
1857 /* Reads notification messages from the Host Notification Queue. */
1858 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT \
1860 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST \
1861 CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
1863 /* This value selects which table scope will be accessed. */
1864 uint8_t table_scope;
1865 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK \
1867 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
1869 * This value identifies the number of 32B units will be accessed. A
1870 * value of zero is invalid. Maximum value is 4.
1873 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
1874 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
1877 * This is the 64b host address where you want the data returned to. The
1878 * data will be written to the same function as the one that owns the SQ
1880 uint64_t host_address;
1883 /* ce_bds_add_data_msg (size:512b/64B) */
1884 struct ce_bds_add_data_msg {
1885 uint32_t version_algorithm_kid_opcode;
1887 * This value selects the operation for the mid-path command for the
1890 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
1891 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
1893 * This is the add command. Using this opcode, Host Driver can add
1894 * information required for kTLS processing. The information is
1895 * updated in the CFCK context.
1897 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
1898 #define CE_BDS_ADD_DATA_MSG_OPCODE_LAST \
1899 CE_BDS_ADD_DATA_MSG_OPCODE_ADD
1901 * This field is the Crypto Context ID. The KID is used to store
1902 * information used by the associated kTLS offloaded connection.
1904 #define CE_BDS_ADD_DATA_MSG_KID_MASK \
1906 #define CE_BDS_ADD_DATA_MSG_KID_SFT 4
1908 * Currently only two algorithms are supported, AES_GCM_128 and
1909 * AES_GCM_256. Additional bits for future growth.
1911 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK \
1913 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
1914 /* AES_GCM_128 Algorithm */
1915 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \
1917 /* AES_GCM_256 Algorithm */
1918 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \
1921 * Version number of TLS connection. HW will provide registers that
1922 * converts the 4b encoded version number to 16b of actual version
1923 * number in the TLS Header. * Initialized --> By mid-path command *
1924 * Updated --> Never though another mid-path command will result in an
1927 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK \
1928 UINT32_C(0xf0000000)
1929 #define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
1930 /* TLS1.2 Version */
1931 #define CE_BDS_ADD_DATA_MSG__TLS1_2 \
1932 (UINT32_C(0x0) << 28)
1933 /* TLS1.3 Version */
1934 #define CE_BDS_ADD_DATA_MSG__TLS1_3 \
1935 (UINT32_C(0x1) << 28)
1936 #define CE_BDS_ADD_DATA_MSG__LAST \
1937 CE_BDS_ADD_DATA_MSG__TLS1_3
1939 * Command Type in the TLS header. HW will provide registers that
1940 * converts the 3b encoded command type to 8b of actual command type in
1941 * the TLS Header. * Initialized --> By mid-path command * Updated -->
1942 * Never though another mid-path command will result in an update
1945 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7)
1946 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0
1948 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0)
1949 #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \
1950 CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP
1953 * Salt is part of the nonce that is used as the Initial Vector (IV) in
1954 * AES-GCM cipher suites. These are exchanged as part of the handshake
1955 * process and is either the client_write_iv (when the client is
1956 * sending) or server_write_iv (when the server is sending). In
1957 * TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
1958 * generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
1959 * is zero padded to 12B and then xor'ed with the 4B of salt to generate
1960 * the 12B of IV. This value is initialized by this mid-path command.
1965 * This field keeps track of the TCP sequence number that is expected as
1966 * the first byte in the next TCP packet. This field is calculated by HW
1967 * using the output of the parser. The field is initialized as part of
1968 * the Mid-path BD download/update of a kTLS connection. For every TCP
1969 * packet processed, TCE HW will update the value to Current packet TCP
1970 * sequence number + Current packet TCP Payload Length.
1972 uint32_t pkt_tcp_seq_num;
1974 * This field maintains the TCP sequence number of the first byte in the
1975 * header of the active TLS record. This field is initialized as part of
1976 * the Mid-path BD download/update of a kTLS connection. For every
1977 * record that is processed, TCE HW copies the value from the
1978 * next_tls_header_tcp_seq_num field.
1980 uint32_t tls_header_tcp_seq_num;
1982 * This is sequence number for the TLS record in a particular session.
1983 * In TLS1.2, record sequence number is part of the Associated Data (AD)
1984 * in the AEAD algorithm. In TLS1.3, record sequence number is part of
1985 * the Initial Vector (IV). The field is initialized as part of the
1986 * mid-path BD download/update of a kTLS connection. TCE HW increments
1987 * the field after that for every record processed as it parses the TCP
1990 uint32_t record_seq_num[2];
1992 * Key used for encrypting or decrypting TLS records. The Key is
1993 * exchanged during the hand-shake protocol by the client-server and
1994 * provided to HW through this mid-path BD.
1996 uint32_t session_key[8];
1999 /* ce_bds_delete_data_msg (size:64b/8B) */
2000 struct ce_bds_delete_data_msg {
2001 uint32_t kid_opcode;
2003 * This value selects the operation for the mid-path command for the
2006 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2007 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2009 * This is the delete command. Using this opcode, the host Driver
2010 * can remove a key context from the CFCK. If context is deleted
2011 * and packets with the same KID come through the pipeline, the
2012 * following actions are taken. For transmit packets, no crypto
2013 * operation will be performed, payload will be zero'ed out. For
2014 * receive packets, no crypto operation will be performed,
2015 * payload will be unmodified.
2017 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2018 #define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST \
2019 CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
2021 * This field is the Crypto Context ID. The KID is used to store
2022 * information used by the associated kTLS offloaded connection.
2024 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2025 #define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
2029 /* ce_bds_resync_resp_ack_msg (size:128b/16B) */
2030 struct ce_bds_resync_resp_ack_msg {
2031 uint32_t resync_status_kid_opcode;
2033 * This value selects the operation for the mid-path command for the
2036 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2037 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2039 * This command is used by the driver as a response to the resync
2040 * request sent by the crypto engine.
2042 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2043 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST \
2044 CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
2046 * This field is the Crypto Context ID. The KID is used to store
2047 * information used by the associated kTLS offloaded connection.
2049 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2050 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
2052 * This field indicates if the resync request resulted in a success or
2055 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS \
2058 * An ACK indicates that the driver was able to find the TLS record
2059 * associated with TCP sequence number provided by the HW
2061 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK \
2062 (UINT32_C(0x0) << 24)
2063 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST \
2064 CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
2066 * This field is the echo of the TCP sequence number provided in the
2067 * resync request by the HW. If HW sent multiple resync requests, it
2068 * only tracks the latest TCP sequence number. When the response from
2069 * the Driver doesn't match the latest request, HW will drop the resync
2072 uint32_t resync_record_tcp_seq_num;
2074 * This field indicates the TLS record sequence number associated with
2075 * the resync request. HW will take this number and add the delta records
2076 * it has found since sending the resync request, update the context and
2077 * resume decrypting records.
2079 uint32_t resync_record_seq_num[2];
2082 /* ce_bds_resync_resp_nack_msg (size:64b/8B) */
2083 struct ce_bds_resync_resp_nack_msg {
2084 uint32_t resync_status_kid_opcode;
2086 * This value selects the operation for the mid-path command for the
2089 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2090 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2092 * This command is used by the driver as a response to the resync
2093 * request sent by the crypto engine.
2095 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2096 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST \
2097 CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
2099 * This field is the Crypto Context ID. The KID is used to store
2100 * information used by the associated kTLS offloaded connection.
2102 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK \
2104 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
2106 * This field indicates if the resync request resulted in a success or
2109 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS \
2112 * An NAK indicates that the driver wasn't able to find the TLS
2113 * record associated with TCP sequence number provided by the HW
2115 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK \
2116 (UINT32_C(0x1) << 24)
2117 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST \
2118 CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
2120 * This field is the echo of the TCP sequence number provided in the
2121 * resync request by the HW. If HW sent multiple resync requests, it
2122 * only tracks the latest TCP sequence number. When the response from
2123 * the Driver doesn't match the latest request, HW will drop the resync
2126 uint32_t resync_record_tcp_seq_num;
2129 /* crypto_presync_bd_cmd (size:256b/32B) */
2130 struct crypto_presync_bd_cmd {
2133 * Typically, presync BDs are used for packet retransmissions. Source
2134 * port sends all the packets in order over the network to destination
2135 * port and packets get dropped in the network. The destination port
2136 * will request retranmission of dropped packets and source port driver
2137 * will send presync BD to setup the transmitter appropriately. It will
2138 * provide the start and end TCP sequence number of the data to be
2139 * transmitted. HW keeps two sets of context variable, one for in order
2140 * traffic and one for retransmission traffic. HW is designed to
2141 * transmit everything posted in the presync BD and return to in order
2142 * mode after that. No inorder context variables are updated in the
2143 * process. There is a special case where packets can be dropped
2144 * between the TCP stack and Device Driver (Berkeley Packet Filter for
2145 * ex) and HW still needs to transmit rest of the traffic. In this
2146 * mode, driver will send a presync BD as if it is a retransmission but
2147 * at the end of the transmission, the in order variables need to be
2148 * updated. This flag is used by driver to indicate that in order
2149 * variables needs to be updated at the end of completing the task
2150 * associated with the presync BD.
2152 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \
2157 * This field maintains the TCP sequence number of the first byte in the
2158 * Header of the active TLS record. This field is set to 0 during
2159 * mid-path BD updates, but is set to correct value when a presync BD is
2160 * detected. For every record that is processed, the value from the
2161 * next_tls_header_tcp_seq_num field is copied.
2163 uint32_t header_tcp_seq_num;
2165 * When a retransmitted packet has a TLS authentication TAG present and
2166 * the data spans multiple TCP Packets, HW is required to read the entire
2167 * record to recalculate the TAG but only transmit what is required. This
2168 * field is the start TCP sequence number of the packet(s) that need to
2169 * be re-transmitted. This field is initialized to 0 during Mid-path BD
2170 * add command and initialized to value provided by the driver when
2171 * Pre-sync BD is detected. This field is never updated unless another
2172 * Pre-sync BD signaling a new retransmission is scheduled.
2174 uint32_t start_tcp_seq_num;
2176 * When a retransmitted packet has a TLS authentication TAG present and
2177 * the data spans multiple TCP Packets, HW is required to read the
2178 * entire record to recalculate the TAG but only transmit what is
2179 * required. This field is the end TCP sequence number of the packet(s)
2180 * that need to be re-transmitted. This field is initialized to 0 during
2181 * Mid-path BD add command and initialized to value provided by the
2182 * driver when Pre-sync BD is detected. This field is never updated
2183 * unless another Pre-sync BD signaling a new retransmission is
2186 uint32_t end_tcp_seq_num;
2188 * For TLS1.2, an explicit nonce is used as part of the IV (concatenated
2189 * with the SALT). For retans packets, this field is extracted from the
2190 * TLS record, field right after the TLS Header and stored in the
2191 * context. This field needs to be stored in context as TCP segmentation
2192 * could have split the field into multiple TCP packets. This value is
2193 * initialized to 0 when presync BD is detected by taking the value from
2194 * the first TLS header. When subsequent TLS Headers are detected, the
2195 * value is extracted from packet.
2197 uint32_t explicit_nonce[2];
2199 * This is sequence number for the TLS record in a particular session. In
2200 * TLS1.2, record sequence number is part of the Associated Data (AD) in
2201 * the AEAD algorithm. In TLS1.3, record sequence number is part of the
2202 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
2203 * download. Is initialized to correct value when a pre-sync BD is
2204 * detected. TCE HW increments the field after that for every record
2205 * processed as it parses the TCP packet. Subsequent pre-sync BDs
2206 * delivering more retransmission instruction will also update this
2209 uint32_t record_seq_num[2];
2212 /* bd_base (size:64b/8B) */
2215 /* This value identifies the type of buffer descriptor. */
2216 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
2217 #define BD_BASE_TYPE_SFT 0
2219 * Indicates that this BD is 16B long and is used for
2220 * normal L2 packet transmission.
2222 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
2224 * Indicates that this BD is 1BB long and is an empty
2225 * TX BD. Not valid for use by the driver.
2227 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2229 * Indicates that this BD is 16B long and is an RX Producer
2230 * (i.e. empty) buffer descriptor.
2232 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
2234 * Indicates that this BD is 16B long and is an RX
2235 * Producer Buffer BD.
2237 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
2239 * Indicates that this BD is 16B long and is an
2240 * RX Producer Assembly Buffer Descriptor.
2242 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
2244 * Indicates that this BD is used to issue a command to one of
2245 * the mid-path destinations.
2247 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
2249 * Indicates that this BD is used to issue a cryptographic pre-
2250 * sync command through the fast path and destined for TCE.
2252 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
2254 * Indicates that this BD is 32B long and is used for
2255 * normal L2 packet transmission.
2257 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
2259 * Indicates that this BD is 32B long and is used for
2260 * L2 packet transmission for small packets that require
2263 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2264 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
2265 uint8_t unused_1[7];
2268 /* tx_bd_short (size:128b/16B) */
2269 struct tx_bd_short {
2271 * All bits in this field must be valid on the first BD of a packet.
2272 * Only the packet_end bit must be valid for the remaining BDs
2275 uint16_t flags_type;
2276 /* This value identifies the type of buffer descriptor. */
2277 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
2278 #define TX_BD_SHORT_TYPE_SFT 0
2280 * Indicates that this BD is 16B long and is used for
2281 * normal L2 packet transmission.
2283 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
2284 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
2286 * All bits in this field must be valid on the first BD of a packet.
2287 * Only the packet_end bit must be valid for the remaining BDs
2290 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
2291 #define TX_BD_SHORT_FLAGS_SFT 6
2293 * If set to 1, the packet ends with the data in the buffer
2294 * pointed to by this descriptor. This flag must be
2295 * valid on every BD.
2297 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
2299 * If set to 1, the device will not generate a completion for
2300 * this transmit packet unless there is an error in it's
2303 * is set to 0, then the packet will be completed normally.
2305 * This bit must be valid only on the first BD of a packet.
2307 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
2309 * This value indicates how many 16B BD locations are consumed
2310 * in the ring by this packet.
2311 * A value of 1 indicates that this BD is the only BD (and that
2312 * it is a short BD). A value
2313 * of 3 indicates either 3 short BDs or 1 long BD and one short
2314 * BD in the packet. A value of 0 indicates
2315 * that there are 32 BD locations in the packet (the maximum).
2317 * This field is valid only on the first BD of a packet.
2319 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2320 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
2322 * This value is a hint for the length of the entire packet.
2323 * It is used by the chip to optimize internal processing.
2325 * The packet will be dropped if the hint is too short.
2327 * This field is valid only on the first BD of a packet.
2329 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
2330 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
2331 /* indicates packet length < 512B */
2332 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2333 /* indicates 512 <= packet length < 1KB */
2334 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2335 /* indicates 1KB <= packet length < 2KB */
2336 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2337 /* indicates packet length >= 2KB */
2338 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2339 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
2340 TX_BD_SHORT_FLAGS_LHINT_GTE2K
2342 * If set to 1, the device immediately updates the Send Consumer
2343 * Index after the buffer associated with this descriptor has
2344 * been transferred via DMA to NIC memory from host memory. An
2345 * interrupt may or may not be generated according to the state
2346 * of the interrupt avoidance mechanisms. If this bit
2347 * is set to 0, then the Consumer Index is only updated as soon
2348 * as one of the host interrupt coalescing conditions has been met.
2350 * This bit must be valid on the first BD of a packet.
2352 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
2354 * This is the length of the host physical buffer this BD describes
2357 * This field must be valid on all BDs of a packet.
2361 * The opaque data field is pass through to the completion and can be
2362 * used for any data that the driver wants to associate with the
2365 * This field must be valid on the first BD of a packet. If completion
2366 * coalescing is enabled on the TX ring, it is suggested that the driver
2367 * populate the opaque field to indicate the specific TX ring with which
2368 * the completion is associated, then utilize the opaque and sq_cons_idx
2369 * fields in the coalesced completion record to determine the specific
2370 * packets that are to be completed on that ring.
2374 * This is the host physical address for the portion of the packet
2375 * described by this TX BD.
2377 * This value must be valid on all BDs of a packet.
2382 /* tx_bd_long (size:128b/16B) */
2384 /* This value identifies the type of buffer descriptor. */
2385 uint16_t flags_type;
2387 * This value indicates the type of buffer descriptor.
2390 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
2391 #define TX_BD_LONG_TYPE_SFT 0
2393 * Indicates that this BD is 32B long and is used for
2394 * normal L2 packet transmission.
2396 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
2397 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
2399 * All bits in this field must be valid on the first BD of a packet.
2400 * Only the packet_end bit must be valid for the remaining BDs
2403 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
2404 #define TX_BD_LONG_FLAGS_SFT 6
2406 * If set to 1, the packet ends with the data in the buffer
2407 * pointed to by this descriptor. This flag must be
2408 * valid on every BD.
2410 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
2412 * If set to 1, the device will not generate a completion for
2413 * this transmit packet unless there is an error in it's
2416 * is set to 0, then the packet will be completed normally.
2418 * This bit must be valid only on the first BD of a packet.
2420 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
2422 * This value indicates how many 16B BD locations are consumed
2423 * in the ring by this packet.
2424 * A value of 1 indicates that this BD is the only BD (and that
2425 * it is a short BD). A value
2426 * of 3 indicates either 3 short BDs or 1 long BD and one short
2427 * BD in the packet. A value of 0 indicates
2428 * that there are 32 BD locations in the packet (the maximum).
2430 * This field is valid only on the first BD of a packet.
2432 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2433 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
2435 * This value is a hint for the length of the entire packet.
2436 * It is used by the chip to optimize internal processing.
2438 * The packet will be dropped if the hint is too short.
2440 * This field is valid only on the first BD of a packet.
2442 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
2443 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
2444 /* indicates packet length < 512B */
2445 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
2446 /* indicates 512 <= packet length < 1KB */
2447 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
2448 /* indicates 1KB <= packet length < 2KB */
2449 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
2450 /* indicates packet length >= 2KB */
2451 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
2452 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
2454 * If set to 1, the device immediately updates the Send Consumer
2455 * Index after the buffer associated with this descriptor has
2456 * been transferred via DMA to NIC memory from host memory. An
2457 * interrupt may or may not be generated according to the state
2458 * of the interrupt avoidance mechanisms. If this bit
2459 * is set to 0, then the Consumer Index is only updated as soon
2460 * as one of the host interrupt coalescing conditions has been met.
2462 * This bit must be valid on the first BD of a packet.
2464 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
2466 * This is the length of the host physical buffer this BD describes
2469 * This field must be valid on all BDs of a packet.
2473 * The opaque data field is passed through to the completion and can be
2474 * used for any data that the driver wants to associate with the
2477 * This field must be valid on the first BD of a packet. If completion
2478 * coalescing is enabled on the TX ring, it is suggested that the driver
2479 * populate the opaque field to indicate the specific TX ring with which
2480 * the completion is associated, then utilize the opaque and sq_cons_idx
2481 * fields in the coalesced completion record to determine the specific
2482 * packets that are to be completed on that ring.
2486 * This is the host physical address for the portion of the packet
2487 * described by this TX BD.
2489 * This value must be valid on all BDs of a packet.
2494 /* Last 16 bytes of tx_bd_long. */
2495 /* tx_bd_long_hi (size:128b/16B) */
2496 struct tx_bd_long_hi {
2498 * All bits in this field must be valid on the first BD of a packet.
2499 * Their value on other BDs of the packet will be ignored.
2503 * If set to 1, the controller replaces the TCP/UPD checksum
2504 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2505 * checksum field of the encapsulated TCP/UDP packets with the
2506 * hardware calculated TCP/UDP checksum for the packet associated
2507 * with this descriptor. The flag is ignored if the LSO flag is set.
2509 * This bit must be valid on the first BD of a packet.
2511 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2513 * If set to 1, the controller replaces the IP checksum of the
2514 * normal packets, or the inner IP checksum of the encapsulated
2515 * packets with the hardware calculated IP checksum for the
2516 * packet associated with this descriptor.
2518 * This bit must be valid on the first BD of a packet.
2520 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2522 * If set to 1, the controller will not append an Ethernet CRC
2523 * to the end of the frame.
2525 * This bit must be valid on the first BD of a packet.
2527 * Packet must be 64B or longer when this flag is set. It is not
2528 * useful to use this bit with any form of TX offload such as
2529 * CSO or LSO. The intent is that the packet from the host already
2530 * has a valid Ethernet CRC on the packet.
2532 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
2534 * If set to 1, the device will record the time at which the packet
2535 * was actually transmitted at the TX MAC for 2-step time sync.
2537 * This bit must be valid on the first BD of a packet.
2539 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
2541 * If set to 1, The controller replaces the tunnel IP checksum
2542 * field with hardware calculated IP checksum for the IP header
2543 * of the packet associated with this descriptor.
2545 * For outer UDP checksum, global outer UDP checksum TE_NIC register
2546 * needs to be enabled. If the global outer UDP checksum TE_NIC register
2547 * bit is set, outer UDP checksum will be calculated for the following
2549 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
2550 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
2551 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
2552 * checksum will not be calculated.
2553 * 2. Packets with lso flag set which implies inner TCP checksum calculation
2554 * as part of LSO operation.
2556 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2558 * If set to 1, the device will treat this packet with LSO(Large
2559 * Send Offload) processing for both normal or encapsulated
2560 * packets, which is a form of TCP segmentation. When this bit
2561 * is 1, the hdr_size and mss fields must be valid. The driver
2562 * doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
2563 * tcp_udp_chksum flags since the controller will replace the
2564 * appropriate checksum fields for segmented packets.
2566 * When this bit is 1, the hdr_size and mss fields must be valid.
2568 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
2570 * If set to zero when LSO is '1', then the IPID will be treated
2571 * as a 16b number and will be wrapped if it exceeds a value of
2574 * If set to one when LSO is '1', then the IPID will be treated
2575 * as a 15b number and will be wrapped if it exceeds a value 0f
2578 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
2580 * If set to zero when LSO is '1', then the IPID of the tunnel
2581 * IP header will not be modified during LSO operations.
2583 * If set to one when LSO is '1', then the IPID of the tunnel
2584 * IP header will be incremented for each subsequent segment of an
2587 * The flag is ignored if the LSO packet is a normal (non-tunneled)
2590 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
2592 * If set to '1', then the RoCE ICRC will be appended to the
2593 * packet. Packet must be a valid RoCE format packet.
2595 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
2597 * If set to '1', then the FCoE CRC will be appended to the
2598 * packet. Packet must be a valid FCoE format packet.
2600 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
2602 * If set to '1', then the timestamp from the BD is used. If cleared
2603 * to 0, then TWE provides the timestamp.
2605 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
2607 * If set to '1', this operation will cause a trace capture in each
2608 * block it passes through.
2610 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2612 * If set to '1', the device will record the time at which the packet
2613 * was actually transmitted at the TX MAC for 1-step time sync. This
2614 * bit must be valid on the first BD of a packet.
2616 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2618 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2619 * field with hardware calculated IP checksum for the IP header of the
2620 * packet associated with this descriptor. For outer UDP checksum, it
2621 * will be the following behavior for all cases independent of settings
2622 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2623 * is 0, then do not update it. If outer UDP checksum is non zero, then
2624 * the hardware should compute and update it.
2626 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2628 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2629 * header will not be modified during LSO operations. If set to one
2630 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2631 * incremented for each subsequent segment of an LSO operation. The
2632 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2635 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
2637 * If set to '1', When set to 1, KTLS encryption will be enabled for
2640 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2641 uint16_t kid_or_ts_low_hdr_size;
2643 * When LSO is '1', this field must contain the offset of the
2644 * TCP payload from the beginning of the packet in as
2645 * 16b words. In case of encapsulated/tunneling packet, this field
2646 * contains the offset of the inner TCP payload from beginning of the
2647 * packet as 16-bit words.
2649 * This value must be valid on the first BD of a packet.
2651 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
2652 #define TX_BD_LONG_HDR_SIZE_SFT 0
2654 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2655 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of the
2658 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
2659 #define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
2660 uint32_t kid_or_ts_high_mss;
2662 * This is the MSS value that will be used to do the LSO processing.
2663 * The value is the length in bytes of the TCP payload for each
2664 * segment generated by the LSO operation.
2666 * This value must be valid on the first BD of a packet.
2668 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
2669 #define TX_BD_LONG_MSS_SFT 0
2671 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2672 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2673 * of this field contain the upper 13 bits of the 20-bit KID.
2675 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2676 #define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
2678 * This value selects bits 25:16 of the CFA action to perform on the
2679 * packet. See the cfa_action field for more information.
2681 uint16_t cfa_action_high;
2682 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2683 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
2685 * This value selects a CFA action to perform on the packet.
2686 * Set this value to zero if no CFA action is desired.
2688 * This value must be valid on the first BD of a packet.
2690 uint16_t cfa_action;
2692 * This value is action meta-data that defines CFA edit operations
2693 * that are done in addition to any action editing.
2696 /* When key=1, This is the VLAN tag VID value. */
2697 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2698 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
2699 /* When key=1, This is the VLAN tag DE value. */
2700 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
2701 /* When key=1, This is the VLAN tag PRI value. */
2702 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2703 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
2704 /* When key=1, This is the VLAN tag TPID select value. */
2705 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2706 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
2708 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \
2709 (UINT32_C(0x0) << 16)
2711 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \
2712 (UINT32_C(0x1) << 16)
2714 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \
2715 (UINT32_C(0x2) << 16)
2717 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \
2718 (UINT32_C(0x3) << 16)
2720 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \
2721 (UINT32_C(0x4) << 16)
2722 /* Value programmed in CFA VLANTPID register. */
2723 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \
2724 (UINT32_C(0x5) << 16)
2725 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
2726 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
2727 /* When key=1, This is the VLAN tag TPID select value. */
2728 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
2729 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
2731 * This field identifies the type of edit to be performed
2734 * This value must be valid on the first BD of a packet.
2736 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
2737 #define TX_BD_LONG_CFA_META_KEY_SFT 28
2739 #define TX_BD_LONG_CFA_META_KEY_NONE \
2740 (UINT32_C(0x0) << 28)
2742 * - meta[17:16] - TPID select value (0 = 0x8100).
2743 * - meta[15:12] - PRI/DE value.
2744 * - meta[11:0] - VID value.
2746 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \
2747 (UINT32_C(0x1) << 28)
2750 * - Wh+/SR - this option is not supported.
2751 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
2752 * is set in the Lookup Table.
2753 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
2754 * en_bd_meta is set in the Lookup Table.
2756 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \
2757 (UINT32_C(0x2) << 28)
2758 #define TX_BD_LONG_CFA_META_KEY_LAST \
2759 TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
2763 * This structure is used to inform the NIC of packet data that needs to be
2764 * transmitted with additional processing that requires extra data such as
2765 * VLAN insertion plus attached inline data. This BD type may be used to
2766 * improve latency for small packets needing the additional extended features
2767 * supported by long BDs.
2769 /* tx_bd_long_inline (size:256b/32B) */
2770 struct tx_bd_long_inline {
2771 uint16_t flags_type;
2772 /* This value identifies the type of buffer descriptor. */
2773 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
2774 #define TX_BD_LONG_INLINE_TYPE_SFT 0
2776 * This type of BD is 32B long and is used for inline L2 packet
2779 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
2780 #define TX_BD_LONG_INLINE_TYPE_LAST \
2781 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
2783 * All bits in this field may be set on the first BD of a packet.
2784 * Only the packet_end bit may be set in non-first BDs.
2786 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
2787 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
2789 * If set to 1, the packet ends with the data in the buffer
2790 * pointed to by this descriptor. This flag must be
2791 * valid on every BD.
2793 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
2795 * If set to 1, the device will not generate a completion for
2796 * this transmit packet unless there is an error in its processing.
2797 * If this bit is set to 0, then the packet will be completed
2800 * This bit may be set only on the first BD of a packet.
2802 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
2804 * This value indicates how many 16B BD locations are consumed
2805 * in the ring by this packet, including the BD and inline
2808 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
2809 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
2810 /* This field is deprecated. */
2811 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
2812 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2814 * If set to 1, the device immediately updates the Send Consumer
2815 * Index after the buffer associated with this descriptor has
2816 * been transferred via DMA to NIC memory from host memory. An
2817 * interrupt may or may not be generated according to the state
2818 * of the interrupt avoidance mechanisms. If this bit
2819 * is set to 0, then the Consumer Index is only updated as soon
2820 * as one of the host interrupt coalescing conditions has been met.
2822 * This bit must be valid on the first BD of a packet.
2824 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2826 * This is the length of the inline data, not including BD length, in
2828 * The maximum value is 480.
2830 * This field must be valid on all BDs of a packet.
2834 * The opaque data field is passed through to the completion and can be
2835 * used for any data that the driver wants to associate with the transmit
2836 * BD. This field must be valid on the first BD of a packet. If
2837 * completion coalescing is enabled on the TX ring, it is suggested that
2838 * the driver populate the opaque field to indicate the specific TX ring
2839 * with which the completion is associated, then utilize the opaque and
2840 * sq_cons_idx fields in the coalesced completion record to determine
2841 * the specific packets that are to be completed on that ring.
2843 * This field must be valid on the first BD of a packet.
2848 * All bits in this field must be valid on the first BD of a packet.
2849 * Their value on other BDs of the packet is ignored.
2853 * If set to 1, the controller replaces the TCP/UPD checksum
2854 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2855 * checksum field of the encapsulated TCP/UDP packets with the
2856 * hardware calculated TCP/UDP checksum for the packet associated
2857 * with this descriptor. The flag is ignored if the LSO flag is set.
2859 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2861 * If set to 1, the controller replaces the IP checksum of the
2862 * normal packets, or the inner IP checksum of the encapsulated
2863 * packets with the hardware calculated IP checksum for the
2864 * packet associated with this descriptor.
2866 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2868 * If set to 1, the controller will not append an Ethernet CRC
2869 * to the end of the frame.
2871 * Packet must be 64B or longer when this flag is set. It is not
2872 * useful to use this bit with any form of TX offload such as
2873 * CSO or LSO. The intent is that the packet from the host already
2874 * has a valid Ethernet CRC on the packet.
2876 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2878 * If set to 1, the device will record the time at which the packet
2879 * was actually transmitted at the TX MAC for 2-step time sync. This
2880 * bit must be valid on the first BD of a packet.
2882 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2884 * If set to 1, the controller replaces the tunnel IP checksum
2885 * field with hardware calculated IP checksum for the IP header
2886 * of the packet associated with this descriptor. The hardware
2887 * updates an outer UDP checksum if it is non-zero.
2889 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2891 * This bit must be 0 for BDs of this type. LSO is not supported with
2894 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2895 /* Since LSO is not supported with inline BDs, this bit is not used. */
2896 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2897 /* Since LSO is not supported with inline BDs, this bit is not used. */
2898 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2900 * If set to '1', then the RoCE ICRC will be appended to the
2901 * packet. Packet must be a valid RoCE format packet.
2903 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2905 * If set to '1', then the FCoE CRC will be appended to the
2906 * packet. Packet must be a valid FCoE format packet.
2908 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2910 * If set to '1', then the timestamp from the BD is used. If cleared
2911 * to 0, then TWE provides the timestamp.
2913 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
2915 * If set to '1', this operation will cause a trace capture in each
2916 * block it passes through.
2918 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
2920 * If set to '1', the device will record the time at which the packet
2921 * was actually transmitted at the TX MAC for 1-step time sync. This
2922 * bit must be valid on the first BD of a packet.
2924 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
2926 * If set to '1', the controller replaces the Outer-tunnel IP checksum
2927 * field with hardware calculated IP checksum for the IP header of the
2928 * packet associated with this descriptor. For outer UDP checksum, it
2929 * will be the following behavior for all cases independent of settings
2930 * of inner LSO and checksum offload BD flags. If outer UDP checksum
2931 * is 0, then do not update it. If outer UDP checksum is non zero, then
2932 * the hardware should compute and update it.
2934 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
2936 * If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
2937 * header will not be modified during LSO operations. If set to one
2938 * when LSO is '1', then the IPID of the Outer-tunnel IP header will be
2939 * incremented for each subsequent segment of an LSO operation. The
2940 * flag is ignored if the LSO packet is a normal (non-tunneled) TCP
2943 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
2945 * If set to '1', When set to 1, KTLS encryption will be enabled for
2948 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
2950 uint8_t kid_or_ts_low;
2951 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
2953 * If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
2954 * timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
2957 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
2958 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
2959 uint32_t kid_or_ts_high;
2960 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
2961 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
2963 * If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
2964 * timestamp. If lflags.crypto_en is 1, the least significant 13 bits
2965 * of this field contain the upper 13 bits of the 20-bit KID.
2967 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
2968 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
2970 * This value selects bits 25:16 of the CFA action to perform on the
2971 * packet. See the cfa_action field for more information.
2973 uint16_t cfa_action_high;
2974 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
2975 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
2977 * This value selects a CFA action to perform on the packet.
2978 * Set this value to zero if no CFA action is desired.
2980 * This value must be valid on the first BD of a packet.
2982 uint16_t cfa_action;
2984 * This value is action meta-data that defines CFA edit operations
2985 * that are done in addition to any action editing.
2988 /* When key = 1, this is the VLAN tag VID value. */
2989 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2990 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2991 /* When key = 1, this is the VLAN tag DE value. */
2992 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \
2994 /* When key = 1, this is the VLAN tag PRI value. */
2995 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \
2997 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2998 /* When key = 1, this is the VLAN tag TPID select value. */
2999 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \
3001 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
3003 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
3004 (UINT32_C(0x0) << 16)
3006 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
3007 (UINT32_C(0x1) << 16)
3009 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
3010 (UINT32_C(0x2) << 16)
3012 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
3013 (UINT32_C(0x3) << 16)
3015 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
3016 (UINT32_C(0x4) << 16)
3017 /* Value programmed in CFA VLANTPID register. */
3018 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
3019 (UINT32_C(0x5) << 16)
3020 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
3021 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
3022 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
3024 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
3026 * This field identifies the type of edit to be performed
3029 * This value must be valid on the first BD of a packet.
3031 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
3032 UINT32_C(0xf0000000)
3033 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
3035 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
3036 (UINT32_C(0x0) << 28)
3038 * - meta[17:16] - TPID select value (0 = 0x8100).
3039 * - meta[15:12] - PRI/DE value.
3040 * - meta[11:0] - VID value.
3042 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
3043 (UINT32_C(0x1) << 28)
3046 * - Wh+/SR - this option is not supported.
3047 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3048 * is set in the Lookup Table.
3049 * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
3050 * en_bd_meta is set in the Lookup Table.
3052 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \
3053 (UINT32_C(0x2) << 28)
3054 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
3055 TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
3058 /* tx_bd_empty (size:128b/16B) */
3059 struct tx_bd_empty {
3060 /* This value identifies the type of buffer descriptor. */
3062 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
3063 #define TX_BD_EMPTY_TYPE_SFT 0
3065 * Indicates that this BD is 1BB long and is an empty
3066 * TX BD. Not valid for use by the driver.
3068 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3069 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
3070 uint8_t unused_1[3];
3072 uint8_t unused_3[3];
3073 uint8_t unused_4[8];
3076 /* tx_bd_mp_cmd (size:128b/16B) */
3077 struct tx_bd_mp_cmd {
3078 /* Unless otherwise stated, sub-fields of this field are always valid. */
3079 uint16_t flags_type;
3080 /* This value identifies the type of buffer descriptor. */
3081 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
3082 #define TX_BD_MP_CMD_TYPE_SFT 0
3084 * Indicates that this BD is used to issue a command to one of
3085 * the mid-path destinations.
3087 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3088 #define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
3089 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
3090 #define TX_BD_MP_CMD_FLAGS_SFT 6
3092 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3093 #define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
3095 * This value indicates the number of 16B BD locations (slots)
3096 * consumed in the ring by this mid-path command BD, including the
3097 * BD header and the command field.
3099 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3100 #define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
3102 * This value defines the length of command field in bytes. The maximum
3103 * value shall be 496.
3107 * The opaque data field is pass through to the completion and can be
3108 * used for any data that the driver wants to associate with this
3109 * Tx mid-path command.
3115 /* tx_bd_presync_cmd (size:128b/16B) */
3116 struct tx_bd_presync_cmd {
3117 /* Unless otherwise stated, sub-fields of this field are always valid. */
3118 uint16_t flags_type;
3119 /* This value identifies the type of buffer descriptor. */
3120 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
3121 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
3123 * Indicates that this BD is used to issue a cryptographic pre-
3124 * sync command through the fast path and destined for TCE.
3126 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3127 #define TX_BD_PRESYNC_CMD_TYPE_LAST \
3128 TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
3129 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
3130 #define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
3132 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
3133 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
3135 * This value indicates the number of 16B BD locations (slots)
3136 * consumed in the ring by this pre-sync command BD, including the
3137 * BD header and the command field.
3139 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3140 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
3142 * This value defines the length of command field in bytes. The maximum
3143 * value shall be 496.
3147 * The opaque data field is pass through to TCE and can be used for
3152 * This field is the Crypto Context ID to which the retransmit packet is
3153 * applied. The KID references the context fields used by the
3154 * associated kTLS offloaded connection.
3158 * The KID value of all-ones is reserved for non-KTLS packets, which
3159 * only implies that this value must not be used when filling this
3160 * field for crypto packets.
3162 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
3163 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
3167 /* rx_prod_pkt_bd (size:128b/16B) */
3168 struct rx_prod_pkt_bd {
3169 /* This value identifies the type of buffer descriptor. */
3170 uint16_t flags_type;
3171 /* This value identifies the type of buffer descriptor. */
3172 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
3173 #define RX_PROD_PKT_BD_TYPE_SFT 0
3175 * Indicates that this BD is 16B long and is an RX Producer
3176 * (i.e. empty) buffer descriptor.
3178 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
3179 #define RX_PROD_PKT_BD_TYPE_LAST \
3180 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
3181 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
3182 #define RX_PROD_PKT_BD_FLAGS_SFT 6
3184 * If set to 1, the packet will be placed at the address plus
3185 * 2B. The 2 Bytes of padding will be written as zero.
3187 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
3189 * If set to 1, the packet write will be padded out to the
3190 * nearest cache-line with zero value padding.
3192 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
3194 * This field has been deprecated. There can be no additional
3195 * BDs for this packet from this ring.
3198 * This value is the number of additional buffers in the ring that
3199 * describe the buffer space to be consumed for this packet.
3200 * If the value is zero, then the packet must fit within the
3201 * space described by this BD. If this value is 1 or more, it
3202 * indicates how many additional "buffer" BDs are in the ring
3203 * immediately following this BD to be used for the same
3204 * network packet. Even if the packet to be placed does not need
3205 * all the additional buffers, they will be consumed anyway.
3207 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
3208 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
3210 * This is the length in Bytes of the host physical buffer where
3211 * data for the packet may be placed in host memory.
3215 * The opaque data field is pass through to the completion and can be
3216 * used for any data that the driver wants to associate with this
3217 * receive buffer set.
3221 * This is the host physical address where data for the packet may
3222 * be placed in host memory.
3227 /* rx_prod_bfr_bd (size:128b/16B) */
3228 struct rx_prod_bfr_bd {
3229 /* This value identifies the type of buffer descriptor. */
3230 uint16_t flags_type;
3231 /* This value identifies the type of buffer descriptor. */
3232 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
3233 #define RX_PROD_BFR_BD_TYPE_SFT 0
3235 * Indicates that this BD is 16B long and is an RX
3236 * Producer Buffer BD.
3238 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
3239 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
3240 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
3241 #define RX_PROD_BFR_BD_FLAGS_SFT 6
3243 * This is the length in Bytes of the host physical buffer where
3244 * data for the packet may be placed in host memory.
3247 /* This field is not used. */
3250 * This is the host physical address where data for the packet may
3251 * be placed in host memory.
3256 /* rx_prod_agg_bd (size:128b/16B) */
3257 struct rx_prod_agg_bd {
3258 /* This value identifies the type of buffer descriptor. */
3259 uint16_t flags_type;
3260 /* This value identifies the type of buffer descriptor. */
3261 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
3262 #define RX_PROD_AGG_BD_TYPE_SFT 0
3264 * Indicates that this BD is 16B long and is an
3265 * RX Producer Assembly Buffer Descriptor.
3267 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
3268 #define RX_PROD_AGG_BD_TYPE_LAST \
3269 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
3270 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
3271 #define RX_PROD_AGG_BD_FLAGS_SFT 6
3273 * If set to 1, the packet write will be padded out to the
3274 * nearest cache-line with zero value padding.
3276 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
3278 * This is the length in Bytes of the host physical buffer where
3279 * data for the packet may be placed in host memory.
3283 * The opaque data field is pass through to the completion and can be
3284 * used for any data that the driver wants to associate with this
3285 * receive assembly buffer.
3289 * This is the host physical address where data for the packet may
3290 * be placed in host memory.
3295 /* cfa_cmpls_cmp_data_msg (size:128b/16B) */
3296 struct cfa_cmpls_cmp_data_msg {
3297 uint32_t mp_client_dma_length_opcode_status_type;
3299 * This field represents the Mid-Path client that generated the
3302 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3303 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3304 /* Mid Path Short Completion with length = 16B. */
3305 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT \
3307 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3308 CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3309 /* This value indicates the status for the command. */
3310 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
3311 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
3312 /* Completed without error. */
3313 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK \
3314 (UINT32_C(0x0) << 6)
3315 /* Indicates an unsupported CFA opcode in the command. */
3316 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR \
3317 (UINT32_C(0x1) << 6)
3319 * Indicates a CFA command formatting error. This error can occur on
3320 * any of the supported CFA commands.
3322 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR \
3323 (UINT32_C(0x2) << 6)
3325 * Indicates an SVIF-Table scope error. This error can occur on any
3326 * of the supported CFA commands.
3328 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR \
3329 (UINT32_C(0x3) << 6)
3331 * Indicates that the table_index is either outside of the
3332 * table_scope range set by its EM_SIZE or, for EM Insert, it is in
3333 * the static bucket range. This error can occur on EM Insert
3334 * commands. It can also occur on Read, Read Clear, Write, and
3335 * Invalidate commands if the table_type is EM.
3337 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR \
3338 (UINT32_C(0x4) << 6)
3340 * Cache operation responded with an error. This error can occur on
3341 * Read, Read Clear, Write, EM Insert, and EM Delete commands.
3343 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR \
3344 (UINT32_C(0x5) << 6)
3346 * Indicates failure on EM Insert or EM Delete Command. Hash index
3347 * and hash msb are returned in table_index and hash_msb fields.
3348 * Dma_length is set to 1 if the bucket is also returned (as dma
3351 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL \
3352 (UINT32_C(0x6) << 6)
3354 * Indicates no notifications were available on an Event Collection
3357 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL \
3358 (UINT32_C(0x7) << 6)
3359 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3360 CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
3361 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
3362 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
3363 /* This is the opcode from the command. */
3364 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK \
3366 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
3368 * This is read command. From 32 to 128B can be read from a table
3369 * using this command.
3371 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ \
3372 (UINT32_C(0x0) << 12)
3374 * This is write command. From 32 to 128B can be written to a table
3375 * using this command.
3377 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE \
3378 (UINT32_C(0x1) << 12)
3380 * This is read-clear command. 32B can be read from a table and a 16b
3381 * mask can be used to clear specific 16b units after the read as an
3384 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR \
3385 (UINT32_C(0x2) << 12)
3387 * An exact match table insert will be attempted into the table. If
3388 * there is a free location in the bucket, the payload will be
3389 * written to the bucket.
3391 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT \
3392 (UINT32_C(0x3) << 12)
3393 /* An exact match table delete will be attempted. */
3394 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE \
3395 (UINT32_C(0x4) << 12)
3397 * The specified table area will be invalidated. If it is needed
3398 * again, it will be read from the backing store.
3400 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE \
3401 (UINT32_C(0x5) << 12)
3402 /* Reads notification messages from the Host Notification Queue. */
3403 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT \
3404 (UINT32_C(0x6) << 12)
3405 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST \
3406 CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
3408 * This field indicates the length of the DMA that accompanies the
3409 * completion. Specified in units of DWords (32b). Valid values are
3410 * between 0 and 128. A value of zero indicates that there is no DMA
3411 * that accompanies the completion.
3413 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK \
3415 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
3417 * This field represents the Mid-Path client that generated the
3420 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK \
3421 UINT32_C(0xf0000000)
3422 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
3423 /* TX configrable flow processing block. */
3424 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA \
3425 (UINT32_C(0x2) << 28)
3426 /* RX configrable flow processing block. */
3427 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA \
3428 (UINT32_C(0x3) << 28)
3429 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \
3430 CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
3432 * This is a copy of the opaque field from the mid path BD of this
3436 uint16_t hash_msb_v;
3438 * This value is written by the NIC such that it will be different for
3439 * each pass through the completion queue. The even passes will
3440 * write 1. The odd passes will write 0.
3442 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3443 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
3444 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
3446 * This is the upper 12b of the hash, returned on Exact Match
3447 * Insertion/Deletion Commands.
3449 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
3450 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
3451 /* This is the table type from the command. */
3453 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
3454 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
3455 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
3456 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
3457 /* This command acts on the action table of the specified scope. */
3458 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
3459 /* This command acts on the exact match table of the specified scope. */
3460 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
3461 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST \
3462 CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
3463 uint8_t table_scope;
3464 /* This is the table scope from the command. */
3465 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
3466 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
3467 uint32_t table_index;
3469 * This is the table index from the command (if it exists). However, if
3470 * an Exact Match Insertion/Deletion command failed, then this is the
3471 * table index of the calculated static hash bucket.
3473 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
3474 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
3477 /* CFA Mid-Path 32B DMA Message */
3478 /* cfa_dma32b_data_msg (size:256b/32B) */
3479 struct cfa_dma32b_data_msg {
3480 /* DMA data value. */
3484 /* CFA Mid-Path 64B DMA Message */
3485 /* cfa_dma64b_data_msg (size:512b/64B) */
3486 struct cfa_dma64b_data_msg {
3487 /* DMA data value. */
3491 /* CFA Mid-Path 96B DMA Message */
3492 /* cfa_dma96b_data_msg (size:768b/96B) */
3493 struct cfa_dma96b_data_msg {
3494 /* DMA data value. */
3498 /* CFA Mid-Path 128B DMA Message */
3499 /* cfa_dma128b_data_msg (size:1024b/128B) */
3500 struct cfa_dma128b_data_msg {
3501 /* DMA data value. */
3505 /* ce_cmpls_cmp_data_msg (size:128b/16B) */
3506 struct ce_cmpls_cmp_data_msg {
3507 uint16_t status_subtype_type;
3509 * This field indicates the exact type of the completion. By
3510 * convention, the LSB identifies the length of the record in 16B
3511 * units. Even values indicate 16B records. Odd values indicate 32B
3514 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
3515 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
3516 /* Completion of a Mid Path Command. Length = 16B */
3517 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3518 #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \
3519 CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
3521 * This value indicates the CE sub-type operation that is being
3524 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0)
3525 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6
3526 /* Completion Response for a Solicited Command. */
3527 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6)
3528 /* Error Completion (Unsolicited). */
3529 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6)
3530 /* Re-Sync Completion (Unsolicited) */
3531 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6)
3532 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \
3533 CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
3534 /* This value indicates the status for the command. */
3535 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00)
3536 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10
3537 /* Completed without error. */
3538 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \
3539 (UINT32_C(0x0) << 10)
3540 /* CFCK load error. */
3541 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \
3542 (UINT32_C(0x1) << 10)
3543 /* FID check error. */
3544 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \
3545 (UINT32_C(0x2) << 10)
3546 #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \
3547 CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR
3550 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf)
3551 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0
3553 * This field represents the Mid-Path client that generated the
3556 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0)
3557 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4
3558 /* TX crypto engine block. */
3559 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4)
3560 /* RX crypto engine block. */
3561 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4)
3562 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \
3563 CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE
3565 * This is a copy of the opaque field from the mid path BD of this
3572 * This value is written by the NIC such that it will be different
3573 * for each pass through the completion queue. The even passes will
3574 * write 1. The odd passes will write 0.
3576 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
3578 * This field is the Crypto Context ID. The KID is used to store
3579 * information used by the associated kTLS offloaded connection.
3581 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe)
3582 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1
3586 /* cmpl_base (size:128b/16B) */
3590 * This field indicates the exact type of the completion.
3591 * By convention, the LSB identifies the length of the
3592 * record in 16B units. Even values indicate 16B
3593 * records. Odd values indicate 32B
3596 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
3597 #define CMPL_BASE_TYPE_SFT 0
3600 * Completion of TX packet. Length = 16B
3602 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
3605 * Completion of NO-OP. Length = 16B
3607 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
3609 * TX L2 coalesced completion:
3610 * Completion of coalesced TX packet. Length = 16B
3612 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
3614 * TX L2 PTP completion:
3615 * Completion of PTP TX packet. Length = 32B
3617 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
3619 * RX L2 TPA Start V2 Completion:
3620 * Completion of and L2 RX packet. Length = 32B
3621 * This is the new version of the RX_TPA_START completion used
3622 * in SR2 and later chips.
3624 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
3626 * RX L2 V2 completion:
3627 * Completion of and L2 RX packet. Length = 32B
3628 * This is the new version of the RX_L2 completion used in SR2
3631 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
3634 * Completion of and L2 RX packet. Length = 32B
3636 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
3638 * RX Aggregation Buffer completion :
3639 * Completion of an L2 aggregation buffer in support of
3640 * TPA, HDS, or Jumbo packet completion. Length = 16B
3642 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
3644 * RX L2 TPA Start Completion:
3645 * Completion at the beginning of a TPA operation.
3648 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
3650 * RX L2 TPA End Completion:
3651 * Completion at the end of a TPA operation.
3654 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
3656 * Statistics Ejection Completion:
3657 * Completion of statistics data ejection buffer.
3660 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
3662 * VEE Flush Completion:
3663 * This completion is inserted manually by
3664 * the Primate and processed by the VEE hardware to ensure that
3665 * all completions on a VEE function have been processed by the
3666 * VEE hardware before FLR process is completed.
3668 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
3670 * Mid Path Short Completion :
3671 * Completion of a Mid Path Command. Length = 16B
3673 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
3675 * Mid Path Long Completion :
3676 * Completion of a Mid Path Command. Length = 32B
3678 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
3680 * HWRM Command Completion:
3681 * Completion of an HWRM command.
3683 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
3684 /* Forwarded HWRM Request */
3685 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3686 /* Forwarded HWRM Response */
3687 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3688 /* HWRM Asynchronous Event Information */
3689 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3690 /* CQ Notification */
3691 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
3692 /* SRQ Threshold Event */
3693 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
3694 /* DBQ Threshold Event */
3695 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
3696 /* QP Async Notification */
3697 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
3698 /* Function Async Notification */
3699 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
3700 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
3706 * This value is written by the NIC such that it will be different
3707 * for each pass through the completion queue. The even passes
3708 * will write 1. The odd passes will write 0.
3711 #define CMPL_BASE_V UINT32_C(0x1)
3712 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
3713 #define CMPL_BASE_INFO3_SFT 1
3718 /* tx_cmpl (size:128b/16B) */
3720 uint16_t flags_type;
3722 * This field indicates the exact type of the completion.
3723 * By convention, the LSB identifies the length of the
3724 * record in 16B units. Even values indicate 16B
3725 * records. Odd values indicate 32B
3728 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
3729 #define TX_CMPL_TYPE_SFT 0
3732 * Completion of TX packet. Length = 16B
3734 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
3735 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
3736 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3737 #define TX_CMPL_FLAGS_SFT 6
3739 * When this bit is '1', it indicates a packet that has an
3740 * error of some type. Type of error is indicated in
3743 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
3745 * When this bit is '1', it indicates that the packet completed
3746 * was transmitted using the push acceleration data provided
3747 * by the driver. When this bit is '0', it indicates that the
3748 * packet had not push acceleration data written or was executed
3749 * as a normal packet even though push data was provided.
3751 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
3752 /* unused1 is 16 b */
3755 * This is a copy of the opaque field from the first TX BD of this
3756 * transmitted packet. Note that, if the packet was described by a short
3757 * CSO or short CSO inline BD, then the 16-bit opaque field from the
3758 * short CSO BD will appear in the bottom 16 bits of this field.
3763 * This value is written by the NIC such that it will be different
3764 * for each pass through the completion queue. The even passes
3765 * will write 1. The odd passes will write 0.
3767 #define TX_CMPL_V UINT32_C(0x1)
3768 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
3769 #define TX_CMPL_ERRORS_SFT 1
3771 * This error indicates that there was some sort of problem
3772 * with the BDs for the packet.
3774 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3775 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3777 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
3778 (UINT32_C(0x0) << 1)
3781 * BDs were not formatted correctly.
3783 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
3784 (UINT32_C(0x2) << 1)
3785 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
3786 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
3788 * When this bit is '1', it indicates that the length of
3789 * the packet was zero. No packet was transmitted.
3791 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3793 * When this bit is '1', it indicates that the packet
3794 * was longer than the programmed limit in TDI. No
3795 * packet was transmitted.
3797 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3799 * When this bit is '1', it indicates that one or more of the
3800 * BDs associated with this packet generated a PCI error.
3801 * This probably means the address was not valid.
3803 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
3805 * When this bit is '1', it indicates that the packet was longer
3806 * than indicated by the hint. No packet was transmitted.
3808 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3810 * When this bit is '1', it indicates that the packet was
3811 * dropped due to Poison TLP error on one or more of the
3812 * TLPs in the PXP completion.
3814 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
3816 * When this bit is '1', it indicates that the packet was dropped
3817 * due to a transient internal error in TDC. The packet or LSO can
3818 * be retried and may transmit successfully on a subsequent attempt.
3820 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
3822 * When this bit is '1', it was not possible to collect a a timestamp
3823 * for a PTP completion, in which case the timestamp_hi and
3824 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3825 * completion, the timestamp_hi and timestamp_lo fields are valid.
3826 * RJRN will copy the value of this bit into the field of the same
3827 * name in all TX completions, regardless of whether such completions
3828 * are PTP completions or other TX completions.
3830 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
3831 /* unused2 is 16 b */
3833 /* unused3 is 32 b */
3837 /* tx_cmpl_coal (size:128b/16B) */
3838 struct tx_cmpl_coal {
3839 uint16_t flags_type;
3841 * This field indicates the exact type of the completion.
3842 * By convention, the LSB identifies the length of the
3843 * record in 16B units. Even values indicate 16B
3844 * records. Odd values indicate 32B
3847 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
3848 #define TX_CMPL_COAL_TYPE_SFT 0
3850 * TX L2 coalesced completion:
3851 * Completion of TX packet. Length = 16B
3853 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
3854 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
3855 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
3856 #define TX_CMPL_COAL_FLAGS_SFT 6
3858 * When this bit is '1', it indicates a packet that has an
3859 * error of some type. Type of error is indicated in
3862 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
3864 * When this bit is '1', it indicates that the packet completed
3865 * was transmitted using the push acceleration data provided
3866 * by the driver. When this bit is '0', it indicates that the
3867 * packet had not push acceleration data written or was executed
3868 * as a normal packet even though push data was provided.
3870 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
3871 /* unused1 is 16 b */
3874 * This is a copy of the opaque field from the first TX BD of the packet
3875 * which corresponds with the reported sq_cons_idx. Note that, with
3876 * coalesced completions, completions are generated for only some of the
3877 * packets. The driver will see the opaque field for only those packets.
3878 * Note that, if the packet was described by a short CSO or short CSO
3879 * inline BD, then the 16-bit opaque field from the short CSO BD will
3880 * appear in the bottom 16 bits of this field. For TX rings with
3881 * completion coalescing enabled (which would use the coalesced
3882 * completion record), it is suggested that the driver populate the
3883 * opaque field to indicate the specific TX ring with which the
3884 * completion is associated, then utilize the opaque and sq_cons_idx
3885 * fields in the coalesced completion record to determine the specific
3886 * packets that are to be completed on that ring.
3891 * This value is written by the NIC such that it will be different
3892 * for each pass through the completion queue. The even passes
3893 * will write 1. The odd passes will write 0.
3895 #define TX_CMPL_COAL_V UINT32_C(0x1)
3896 #define TX_CMPL_COAL_ERRORS_MASK \
3898 #define TX_CMPL_COAL_ERRORS_SFT 1
3900 * This error indicates that there was some sort of problem
3901 * with the BDs for the packet.
3903 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
3904 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
3906 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
3907 (UINT32_C(0x0) << 1)
3910 * BDs were not formatted correctly.
3912 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
3913 (UINT32_C(0x2) << 1)
3914 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
3915 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
3917 * When this bit is '1', it indicates that the length of
3918 * the packet was zero. No packet was transmitted.
3920 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
3922 * When this bit is '1', it indicates that the packet
3923 * was longer than the programmed limit in TDI. No
3924 * packet was transmitted.
3926 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
3928 * When this bit is '1', it indicates that one or more of the
3929 * BDs associated with this packet generated a PCI error.
3930 * This probably means the address was not valid.
3932 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
3934 * When this bit is '1', it indicates that the packet was longer
3935 * than indicated by the hint. No packet was transmitted.
3937 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
3939 * When this bit is '1', it indicates that the packet was
3940 * dropped due to Poison TLP error on one or more of the
3941 * TLPs in the PXP completion.
3943 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
3946 * When this bit is '1', it indicates that the packet was dropped
3947 * due to a transient internal error in TDC. The packet or LSO can
3948 * be retried and may transmit successfully on a subsequent attempt.
3950 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
3953 * When this bit is '1', it was not possible to collect a a timestamp
3954 * for a PTP completion, in which case the timestamp_hi and
3955 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
3956 * completion, the timestamp_hi and timestamp_lo fields are valid.
3957 * RJRN will copy the value of this bit into the field of the same
3958 * name in all TX completions, regardless of whether such
3959 * completions are PTP completions or other TX completions.
3961 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
3963 /* unused2 is 16 b */
3965 uint32_t sq_cons_idx;
3967 * This value is SQ index for the start of the packet following the
3968 * last completed packet.
3970 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
3971 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
3974 /* tx_cmpl_ptp (size:128b/16B) */
3975 struct tx_cmpl_ptp {
3976 uint16_t flags_type;
3978 * This field indicates the exact type of the completion.
3979 * By convention, the LSB identifies the length of the
3980 * record in 16B units. Even values indicate 16B
3981 * records. Odd values indicate 32B
3984 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
3985 #define TX_CMPL_PTP_TYPE_SFT 0
3987 * TX L2 PTP completion:
3988 * Completion of TX packet. Length = 32B
3990 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
3991 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
3992 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
3993 #define TX_CMPL_PTP_FLAGS_SFT 6
3995 * When this bit is '1', it indicates a packet that has an
3996 * error of some type. Type of error is indicated in
3999 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
4001 * When this bit is '1', it indicates that the packet completed
4002 * was transmitted using the push acceleration data provided
4003 * by the driver. When this bit is '0', it indicates that the
4004 * packet had not push acceleration data written or was executed
4005 * as a normal packet even though push data was provided.
4007 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
4008 /* unused1 is 16 b */
4011 * This is a copy of the opaque field from the first TX BD of this
4012 * transmitted packet. Note that, if the packet was described by a short
4013 * CSO or short CSO inline BD, then the 16-bit opaque field from the
4014 * short CSO BD will appear in the bottom 16 bits of this field.
4019 * This value is written by the NIC such that it will be different
4020 * for each pass through the completion queue. The even passes
4021 * will write 1. The odd passes will write 0.
4023 #define TX_CMPL_PTP_V UINT32_C(0x1)
4024 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
4025 #define TX_CMPL_PTP_ERRORS_SFT 1
4027 * This error indicates that there was some sort of problem
4028 * with the BDs for the packet.
4030 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4031 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
4033 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
4034 (UINT32_C(0x0) << 1)
4037 * BDs were not formatted correctly.
4039 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
4040 (UINT32_C(0x2) << 1)
4041 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
4042 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
4044 * When this bit is '1', it indicates that the length of
4045 * the packet was zero. No packet was transmitted.
4047 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4049 * When this bit is '1', it indicates that the packet
4050 * was longer than the programmed limit in TDI. No
4051 * packet was transmitted.
4053 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4055 * When this bit is '1', it indicates that one or more of the
4056 * BDs associated with this packet generated a PCI error.
4057 * This probably means the address was not valid.
4059 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
4061 * When this bit is '1', it indicates that the packet was longer
4062 * than indicated by the hint. No packet was transmitted.
4064 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4066 * When this bit is '1', it indicates that the packet was
4067 * dropped due to Poison TLP error on one or more of the
4068 * TLPs in the PXP completion.
4070 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4072 * When this bit is '1', it indicates that the packet was dropped due
4073 * to a transient internal error in TDC. The packet or LSO can be
4074 * retried and may transmit successfully on a subsequent attempt.
4076 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4078 * When this bit is '1', it was not possible to collect a a timestamp
4079 * for a PTP completion, in which case the timestamp_hi and
4080 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4081 * completion, the timestamp_hi and timestamp_lo fields are valid.
4082 * RJRN will copy the value of this bit into the field of the same
4083 * name in all TX completions, regardless of whether such
4084 * completions are PTP completions or other TX completions.
4086 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4087 /* unused2 is 16 b */
4090 * This is timestamp value (lower 32bits) read from PM for the PTP
4091 * timestamp enabled packet.
4093 uint32_t timestamp_lo;
4096 /* tx_cmpl_ptp_hi (size:128b/16B) */
4097 struct tx_cmpl_ptp_hi {
4099 * This is timestamp value (lower 32bits) read from PM for the PTP
4100 * timestamp enabled packet.
4102 uint16_t timestamp_hi[3];
4103 uint16_t reserved16;
4106 * This value is written by the NIC such that it will be different for
4107 * each pass through the completion queue.The even passes will write 1.
4108 * The odd passes will write 0
4110 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
4113 /* rx_pkt_cmpl (size:128b/16B) */
4114 struct rx_pkt_cmpl {
4115 uint16_t flags_type;
4117 * This field indicates the exact type of the completion.
4118 * By convention, the LSB identifies the length of the
4119 * record in 16B units. Even values indicate 16B
4120 * records. Odd values indicate 32B
4123 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
4124 #define RX_PKT_CMPL_TYPE_SFT 0
4127 * Completion of and L2 RX packet. Length = 32B
4129 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
4130 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
4131 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4132 #define RX_PKT_CMPL_FLAGS_SFT 6
4134 * When this bit is '1', it indicates a packet that has an
4135 * error of some type. Type of error is indicated in
4138 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
4139 /* This field indicates how the packet was placed in the buffer. */
4140 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4141 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
4144 * Packet was placed using normal algorithm.
4146 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
4149 * Packet was placed using jumbo algorithm.
4151 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
4153 * Header/Data Separation:
4154 * Packet was placed using Header/Data separation algorithm.
4155 * The separation location is indicated by the itype field.
4157 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
4158 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
4159 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
4160 /* This bit is '1' if the RSS field in this completion is valid. */
4161 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4163 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4165 * This value indicates what the inner packet determined for the
4168 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4169 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
4172 * Indicates that the packet type was not known.
4174 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4175 (UINT32_C(0x0) << 12)
4178 * Indicates that the packet was an IP packet, but further
4179 * classification was not possible.
4181 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
4182 (UINT32_C(0x1) << 12)
4185 * Indicates that the packet was IP and TCP.
4186 * This indicates that the payload_offset field is valid.
4188 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
4189 (UINT32_C(0x2) << 12)
4192 * Indicates that the packet was IP and UDP.
4193 * This indicates that the payload_offset field is valid.
4195 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
4196 (UINT32_C(0x3) << 12)
4199 * Indicates that the packet was recognized as a FCoE.
4200 * This also indicates that the payload_offset field is valid.
4202 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
4203 (UINT32_C(0x4) << 12)
4206 * Indicates that the packet was recognized as a RoCE.
4207 * This also indicates that the payload_offset field is valid.
4209 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
4210 (UINT32_C(0x5) << 12)
4213 * Indicates that the packet was recognized as ICMP.
4214 * This indicates that the payload_offset field is valid.
4216 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
4217 (UINT32_C(0x7) << 12)
4219 * PtP packet wo/timestamp:
4220 * Indicates that the packet was recognized as a PtP
4223 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4224 (UINT32_C(0x8) << 12)
4226 * PtP packet w/timestamp:
4227 * Indicates that the packet was recognized as a PtP
4228 * packet and that a timestamp was taken for the packet.
4230 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4231 (UINT32_C(0x9) << 12)
4232 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
4233 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4235 * This is the length of the data for the packet stored in the
4236 * buffer(s) identified by the opaque value. This includes
4237 * the packet BD and any associated buffer BDs. This does not include
4238 * the length of any data places in aggregation BDs.
4242 * This is a copy of the opaque field from the RX BD this completion
4246 uint8_t agg_bufs_v1;
4248 * This value is written by the NIC such that it will be different
4249 * for each pass through the completion queue. The even passes
4250 * will write 1. The odd passes will write 0.
4252 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
4254 * This value is the number of aggregation buffers that follow this
4255 * entry in the completion ring that are a part of this packet.
4256 * If the value is zero, then the packet is completely contained
4257 * in the buffer space provided for the packet in the RX ring.
4259 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4260 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
4261 /* unused1 is 2 b */
4262 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4263 #define RX_PKT_CMPL_UNUSED1_SFT 6
4265 * This is the RSS hash type for the packet. The value is packed
4266 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4268 * The value of tuple_extrac_op provides the information about
4269 * what fields the hash was computed on.
4270 * * 0: The RSS hash was computed over source IP address,
4271 * destination IP address, source port, and destination port of inner
4272 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4273 * the packet headers are considered inner packet headers for the RSS
4274 * hash computation purpose.
4275 * * 1: The RSS hash was computed over source IP address and destination
4276 * IP address of inner IP header. Note: For non-tunneled packets,
4277 * the packet headers are considered inner packet headers for the RSS
4278 * hash computation purpose.
4279 * * 2: The RSS hash was computed over source IP address,
4280 * destination IP address, source port, and destination port of
4281 * IP and TCP or UDP headers of outer tunnel headers.
4282 * Note: For non-tunneled packets, this value is not applicable.
4283 * * 3: The RSS hash was computed over source IP address and
4284 * destination IP address of IP header of outer tunnel headers.
4285 * Note: For non-tunneled packets, this value is not applicable.
4287 * Note that 4-tuples values listed above are applicable
4288 * for layer 4 protocols supported and enabled for RSS in the hardware,
4289 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4290 * enabled for TCP traffic only, then the values of tuple_extract_op
4291 * corresponding to 4-tuples are only valid for TCP traffic.
4293 uint8_t rss_hash_type;
4295 * This value indicates the offset in bytes from the beginning of the packet
4296 * where the inner payload starts. This value is valid for TCP, UDP,
4297 * FCoE, and RoCE packets.
4299 * A value of zero indicates that header is 256B into the packet.
4301 uint8_t payload_offset;
4302 /* unused2 is 8 b */
4305 * This value is the RSS hash value calculated for the packet
4306 * based on the mode bits and key value in the VNIC.
4311 /* Last 16 bytes of rx_pkt_cmpl. */
4312 /* rx_pkt_cmpl_hi (size:128b/16B) */
4313 struct rx_pkt_cmpl_hi {
4316 * This indicates that the ip checksum was calculated for the
4317 * inner packet and that the ip_cs_error field indicates if there
4320 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4322 * This indicates that the TCP, UDP or ICMP checksum was
4323 * calculated for the inner packet and that the l4_cs_error field
4324 * indicates if there was an error.
4326 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4328 * This indicates that the ip checksum was calculated for the
4329 * tunnel header and that the t_ip_cs_error field indicates if there
4332 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4334 * This indicates that the UDP checksum was
4335 * calculated for the tunnel packet and that the t_l4_cs_error field
4336 * indicates if there was an error.
4338 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4339 /* This value indicates what format the metadata field is. */
4340 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4341 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
4342 /* No metadata information. Value is zero. */
4343 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
4344 (UINT32_C(0x0) << 4)
4346 * The metadata field contains the VLAN tag and TPID value.
4347 * - metadata[11:0] contains the vlan VID value.
4348 * - metadata[12] contains the vlan DE value.
4349 * - metadata[15:13] contains the vlan PRI value.
4350 * - metadata[31:16] contains the vlan TPID value.
4352 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
4353 (UINT32_C(0x1) << 4)
4355 * If ext_meta_format is equal to 1, the metadata field
4356 * contains the lower 16b of the tunnel ID value, justified
4358 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4359 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
4360 * - NVGRE = TNI[23:0] -> Tenant Network ID
4361 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
4362 * - IPV4 = 0 (not populated)
4363 * - IPV6 = Flow Label[19:0]
4364 * - PPPoE = sessionID[15:0]
4365 * - MPLs = Outer label[19:0]
4366 * - UPAR = Selected[31:0] with bit mask
4368 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4369 (UINT32_C(0x2) << 4)
4371 * if ext_meta_format is equal to 1, metadata field contains
4372 * 16b metadata from the prepended header (chdr_data).
4374 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4375 (UINT32_C(0x3) << 4)
4377 * If ext_meta_format is equal to 1, the metadata field contains
4378 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
4380 * - metadata[8:0] contains the outer_l3_offset.
4381 * - metadata[17:9] contains the inner_l2_offset.
4382 * - metadata[26:18] contains the inner_l3_offset.
4383 * - metadata[31:27] contains the inner_l4_size.
4385 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4386 (UINT32_C(0x4) << 4)
4387 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
4388 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4390 * This field indicates the IP type for the inner-most IP header.
4391 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4392 * This value is only valid if itype indicates a packet
4393 * with an IP header.
4395 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4397 * This indicates that the complete 1's complement checksum was
4398 * calculated for the packet.
4400 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
4402 * The combination of this value and meta_format indicated what
4403 * format the metadata field is.
4405 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
4406 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
4408 * This value is the complete 1's complement checksum calculated from
4409 * the start of the outer L3 header to the end of the packet (not
4410 * including the ethernet crc). It is valid when the
4411 * 'complete_checksum_calc' flag is set.
4413 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4414 UINT32_C(0xffff0000)
4415 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4417 * This is data from the CFA block as indicated by the meta_format
4421 /* When meta_format=1, this value is the VLAN VID. */
4422 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4423 #define RX_PKT_CMPL_METADATA_VID_SFT 0
4424 /* When meta_format=1, this value is the VLAN DE. */
4425 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
4426 /* When meta_format=1, this value is the VLAN PRI. */
4427 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4428 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
4429 /* When meta_format=1, this value is the VLAN TPID. */
4430 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4431 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
4434 * This value is written by the NIC such that it will be different
4435 * for each pass through the completion queue. The even passes
4436 * will write 1. The odd passes will write 0.
4438 #define RX_PKT_CMPL_V2 \
4440 #define RX_PKT_CMPL_ERRORS_MASK \
4442 #define RX_PKT_CMPL_ERRORS_SFT 1
4444 * This error indicates that there was some sort of problem with
4445 * the BDs for the packet that was found after part of the
4446 * packet was already placed. The packet should be treated as
4449 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
4451 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4452 /* No buffer error */
4453 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4454 (UINT32_C(0x0) << 1)
4457 * Packet did not fit into packet buffer provided.
4458 * For regular placement, this means the packet did not fit
4459 * in the buffer provided. For HDS and jumbo placement, this
4460 * means that the packet could not be placed into 7 physical
4463 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4464 (UINT32_C(0x1) << 1)
4467 * All BDs needed for the packet were not on-chip when
4468 * the packet arrived.
4470 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4471 (UINT32_C(0x2) << 1)
4474 * BDs were not formatted correctly.
4476 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4477 (UINT32_C(0x3) << 1)
4480 * There was a bad_format error on the previous operation
4482 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4483 (UINT32_C(0x5) << 1)
4484 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
4485 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4487 * This indicates that there was an error in the IP header
4490 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
4493 * This indicates that there was an error in the TCP, UDP
4496 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
4499 * This indicates that there was an error in the tunnel
4500 * IP header checksum.
4502 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
4505 * This indicates that there was an error in the tunnel
4508 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
4511 * This indicates that there was a CRC error on either an FCoE
4512 * or RoCE packet. The itype indicates the packet type.
4514 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
4517 * This indicates that there was an error in the tunnel
4518 * portion of the packet when this
4519 * field is non-zero.
4521 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
4523 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
4525 * No additional error occurred on the tunnel portion
4526 * or the packet of the packet does not have a tunnel.
4528 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
4529 (UINT32_C(0x0) << 9)
4531 * Indicates that IP header version does not match
4532 * expectation from L2 Ethertype for IPv4 and IPv6
4533 * in the tunnel header.
4535 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
4536 (UINT32_C(0x1) << 9)
4538 * Indicates that header length is out of range in the
4539 * tunnel header. Valid for
4542 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
4543 (UINT32_C(0x2) << 9)
4545 * Indicates that the physical packet is shorter than that
4546 * claimed by the PPPoE header length for a tunnel PPPoE
4549 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
4550 (UINT32_C(0x3) << 9)
4552 * Indicates that physical packet is shorter than that claimed
4553 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4554 * tunnel packet packets.
4556 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
4557 (UINT32_C(0x4) << 9)
4559 * Indicates that the physical packet is shorter than that
4560 * claimed by the tunnel UDP header length for a tunnel
4561 * UDP packet that is not fragmented.
4563 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
4564 (UINT32_C(0x5) << 9)
4566 * indicates that the IPv4 TTL or IPv6 hop limit check
4567 * have failed (e.g. TTL = 0) in the tunnel header. Valid
4568 * for IPv4, and IPv6.
4570 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
4571 (UINT32_C(0x6) << 9)
4572 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
4573 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4575 * This indicates that there was an error in the inner
4576 * portion of the packet when this
4577 * field is non-zero.
4579 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
4581 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
4583 * No additional error occurred on the tunnel portion
4584 * or the packet of the packet does not have a tunnel.
4586 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
4587 (UINT32_C(0x0) << 12)
4589 * Indicates that IP header version does not match
4590 * expectation from L2 Ethertype for IPv4 and IPv6 or that
4591 * option other than VFT was parsed on
4594 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
4595 (UINT32_C(0x1) << 12)
4597 * indicates that header length is out of range. Valid for
4600 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
4601 (UINT32_C(0x2) << 12)
4603 * indicates that the IPv4 TTL or IPv6 hop limit check
4604 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4606 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
4607 (UINT32_C(0x3) << 12)
4609 * Indicates that physical packet is shorter than that
4610 * claimed by the l3 header length. Valid for IPv4,
4611 * IPv6 packet or RoCE packets.
4613 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
4614 (UINT32_C(0x4) << 12)
4616 * Indicates that the physical packet is shorter than that
4617 * claimed by the UDP header length for a UDP packet that is
4620 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
4621 (UINT32_C(0x5) << 12)
4623 * Indicates that TCP header length > IP payload. Valid for
4626 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
4627 (UINT32_C(0x6) << 12)
4628 /* Indicates that TCP header length < 5. Valid for TCP. */
4629 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4630 (UINT32_C(0x7) << 12)
4632 * Indicates that TCP option headers result in a TCP header
4633 * size that does not match data offset in TCP header. Valid
4636 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4637 (UINT32_C(0x8) << 12)
4638 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
4639 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4641 * This field identifies the CFA action rule that was used for this
4647 * This value holds the reordering sequence number for the packet.
4648 * If the reordering sequence is not valid, then this value is zero.
4649 * The reordering domain for the packet is in the bottom 8 to 10b of
4650 * the rss_hash value. The bottom 20b of this value contain the
4651 * ordering domain value for the packet.
4653 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
4654 #define RX_PKT_CMPL_REORDER_SFT 0
4657 /* rx_pkt_v2_cmpl (size:128b/16B) */
4658 struct rx_pkt_v2_cmpl {
4659 uint16_t flags_type;
4661 * This field indicates the exact type of the completion.
4662 * By convention, the LSB identifies the length of the
4663 * record in 16B units. Even values indicate 16B
4664 * records. Odd values indicate 32B
4667 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
4668 #define RX_PKT_V2_CMPL_TYPE_SFT 0
4670 * RX L2 V2 completion:
4671 * Completion of and L2 RX packet. Length = 32B
4672 * This is the new version of the RX_L2 completion used in SR2
4675 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
4676 #define RX_PKT_V2_CMPL_TYPE_LAST \
4677 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
4678 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4679 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
4681 * When this bit is '1', it indicates a packet that has an
4682 * error of some type. Type of error is indicated in
4685 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
4686 /* This field indicates how the packet was placed in the buffer. */
4687 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4688 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4691 * Packet was placed using normal algorithm.
4693 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
4694 (UINT32_C(0x0) << 7)
4697 * Packet was placed using jumbo algorithm.
4699 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4700 (UINT32_C(0x1) << 7)
4702 * Header/Data Separation:
4703 * Packet was placed using Header/Data separation algorithm.
4704 * The separation location is indicated by the itype field.
4706 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
4707 (UINT32_C(0x2) << 7)
4710 * Packet was placed using truncation algorithm. The
4711 * placed (truncated) length is indicated in the payload_offset
4712 * field. The original length is indicated in the len field.
4714 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
4715 (UINT32_C(0x3) << 7)
4716 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
4717 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
4718 /* This bit is '1' if the RSS field in this completion is valid. */
4719 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4721 * This bit is '1' if metadata has been added to the end of the
4722 * packet in host memory. Metadata starts at the first 32B boundary
4723 * after the end of the packet for regular and jumbo placement.
4724 * It starts at the first 32B boundary after the end of the header
4725 * for HDS placement. The length of the metadata is indicated in the
4728 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4730 * This value indicates what the inner packet determined for the
4733 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4734 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
4737 * Indicates that the packet type was not known.
4739 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
4740 (UINT32_C(0x0) << 12)
4743 * Indicates that the packet was an IP packet, but further
4744 * classification was not possible.
4746 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
4747 (UINT32_C(0x1) << 12)
4750 * Indicates that the packet was IP and TCP.
4751 * This indicates that the payload_offset field is valid.
4753 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
4754 (UINT32_C(0x2) << 12)
4757 * Indicates that the packet was IP and UDP.
4758 * This indicates that the payload_offset field is valid.
4760 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
4761 (UINT32_C(0x3) << 12)
4764 * Indicates that the packet was recognized as a FCoE.
4765 * This also indicates that the payload_offset field is valid.
4767 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
4768 (UINT32_C(0x4) << 12)
4771 * Indicates that the packet was recognized as a RoCE.
4772 * This also indicates that the payload_offset field is valid.
4774 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
4775 (UINT32_C(0x5) << 12)
4778 * Indicates that the packet was recognized as ICMP.
4779 * This indicates that the payload_offset field is valid.
4781 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
4782 (UINT32_C(0x7) << 12)
4784 * PtP packet wo/timestamp:
4785 * Indicates that the packet was recognized as a PtP
4788 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
4789 (UINT32_C(0x8) << 12)
4791 * PtP packet w/timestamp:
4792 * Indicates that the packet was recognized as a PtP
4793 * packet and that a timestamp was taken for the packet.
4795 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
4796 (UINT32_C(0x9) << 12)
4797 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
4798 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
4800 * This is the length of the data for the packet stored in the
4801 * buffer(s) identified by the opaque value. This includes
4802 * the packet BD and any associated buffer BDs. This does not include
4803 * the length of any data places in aggregation BDs.
4807 * This is a copy of the opaque field from the RX BD this completion
4811 uint8_t agg_bufs_v1;
4813 * This value is written by the NIC such that it will be different
4814 * for each pass through the completion queue. The even passes
4815 * will write 1. The odd passes will write 0.
4817 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
4819 * This value is the number of aggregation buffers that follow this
4820 * entry in the completion ring that are a part of this packet.
4821 * If the value is zero, then the packet is completely contained
4822 * in the buffer space provided for the packet in the RX ring.
4824 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
4825 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
4826 /* unused1 is 2 b */
4827 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
4828 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
4830 * This is the RSS hash type for the packet. The value is packed
4831 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4833 * The value of tuple_extrac_op provides the information about
4834 * what fields the hash was computed on.
4835 * * 0: The RSS hash was computed over source IP address,
4836 * destination IP address, source port, and destination port of inner
4837 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4838 * the packet headers are considered inner packet headers for the RSS
4839 * hash computation purpose.
4840 * * 1: The RSS hash was computed over source IP address and destination
4841 * IP address of inner IP header. Note: For non-tunneled packets,
4842 * the packet headers are considered inner packet headers for the RSS
4843 * hash computation purpose.
4844 * * 2: The RSS hash was computed over source IP address,
4845 * destination IP address, source port, and destination port of
4846 * IP and TCP or UDP headers of outer tunnel headers.
4847 * Note: For non-tunneled packets, this value is not applicable.
4848 * * 3: The RSS hash was computed over source IP address and
4849 * destination IP address of IP header of outer tunnel headers.
4850 * Note: For non-tunneled packets, this value is not applicable.
4852 * Note that 4-tuples values listed above are applicable
4853 * for layer 4 protocols supported and enabled for RSS in the hardware,
4854 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4855 * enabled for TCP traffic only, then the values of tuple_extract_op
4856 * corresponding to 4-tuples are only valid for TCP traffic.
4858 uint8_t rss_hash_type;
4859 uint16_t metadata1_payload_offset;
4861 * This is data from the CFA as indicated by the meta_format field.
4862 * If truncation placement is not used, this value indicates the offset
4863 * in bytes from the beginning of the packet where the inner payload
4864 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
4865 * truncation placement is used, this value represents the placed
4866 * (truncated) length of the packet.
4868 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
4869 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
4870 /* This is data from the CFA as indicated by the meta_format field. */
4871 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4872 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
4873 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4874 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4875 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4877 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
4878 (UINT32_C(0x0) << 12)
4880 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
4881 (UINT32_C(0x1) << 12)
4883 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
4884 (UINT32_C(0x2) << 12)
4886 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
4887 (UINT32_C(0x3) << 12)
4889 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
4890 (UINT32_C(0x4) << 12)
4891 /* Value programmed in CFA VLANTPID register. */
4892 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
4893 (UINT32_C(0x5) << 12)
4894 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_LAST \
4895 RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
4896 /* When meta_format != 0, this value is the VLAN valid. */
4897 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4899 * This value is the RSS hash value calculated for the packet
4900 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
4901 * is set in VNIC context, this is the lower 32b of the host address
4902 * from the first BD used to place the packet.
4907 /* Last 16 bytes of RX Packet V2 Completion Record */
4908 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
4909 struct rx_pkt_v2_cmpl_hi {
4912 * When this bit is '0', the cs_ok field has the following definition:-
4913 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4914 * in the delivered packet, counted from the outer-most header group to
4915 * the inner-most header group, stopping at the first error. -
4916 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4917 * in the delivered packet, counted from the outer-most header group to
4918 * the inner-most header group, stopping at the first error. When this
4919 * bit is '1', the cs_ok field has the following definition: -
4920 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4921 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4922 * will be '1' if all the parsed header groups with an IP checksum are
4923 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4924 * header groups with an L4 checksum are valid.
4926 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
4928 /* This value indicates what format the metadata field is. */
4929 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
4931 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
4932 /* There is no metadata information. Values are zero. */
4933 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
4934 (UINT32_C(0x0) << 4)
4936 * The {metadata1, metadata0} fields contain the vtag
4937 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4938 * de, vid[11:0]} The metadata2 field contains the table scope
4939 * and action record pointer. - metadata2[25:0] contains the
4940 * action record pointer. - metadata2[31:26] contains the table
4943 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
4944 (UINT32_C(0x1) << 4)
4946 * The {metadata1, metadata0} fields contain the vtag
4948 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4949 * The metadata2 field contains the Tunnel ID
4950 * value, justified to LSB. i
4951 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4952 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4953 * - NVGRE = TNI[23:0] -> Tenant Network ID
4954 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4955 * - IPv4 = 0 (not populated)
4956 * - IPv6 = Flow Label[19:0]
4957 * - PPPoE = sessionID[15:0]
4958 * - MPLs = Outer label[19:0]
4959 * - UPAR = Selected[31:0] with bit mask
4961 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
4962 (UINT32_C(0x2) << 4)
4964 * The {metadata1, metadata0} fields contain the vtag
4966 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4967 * The metadata2 field contains the 32b metadata from the prepended
4968 * header (chdr_data).
4970 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
4971 (UINT32_C(0x3) << 4)
4973 * The {metadata1, metadata0} fields contain the vtag
4975 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4976 * The metadata2 field contains the outer_l3_offset,
4977 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4978 * - metadata2[8:0] contains the outer_l3_offset.
4979 * - metadata2[17:9] contains the inner_l2_offset.
4980 * - metadata2[26:18] contains the inner_l3_offset.
4981 * - metadata2[31:27] contains the inner_l4_size.
4983 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
4984 (UINT32_C(0x4) << 4)
4985 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
4986 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
4988 * This field indicates the IP type for the inner-most IP header.
4989 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4990 * This value is only valid if itype indicates a packet
4991 * with an IP header.
4993 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
4996 * This indicates that the complete 1's complement checksum was
4997 * calculated for the packet.
4999 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
5002 * This field indicates the status of IP and L4 CS calculations done
5003 * by the chip. The format of this field is indicated by the
5004 * cs_all_ok_mode bit.
5006 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
5008 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
5010 * This value is the complete 1's complement checksum calculated from
5011 * the start of the outer L3 header to the end of the packet (not
5012 * including the ethernet crc). It is valid when the
5013 * 'complete_checksum_calc' flag is set.
5015 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
5016 UINT32_C(0xffff0000)
5017 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5019 * This is data from the CFA block as indicated by the meta_format
5021 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5022 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5023 * act_rec_ptr[25:0]}
5024 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5025 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5026 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5027 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5028 * of the host address from the first BD used to place the packet.
5033 * This value is written by the NIC such that it will be different
5034 * for each pass through the completion queue. The even passes
5035 * will write 1. The odd passes will write 0.
5037 #define RX_PKT_V2_CMPL_HI_V2 \
5039 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
5041 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
5043 * This error indicates that there was some sort of problem with
5044 * the BDs for the packet that was found after part of the
5045 * packet was already placed. The packet should be treated as
5048 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
5050 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
5051 /* No buffer error */
5052 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
5053 (UINT32_C(0x0) << 1)
5055 * Did Not Fit: Packet did not fit into packet buffer provided.
5056 * For regular placement, this means the packet did not fit in
5057 * the buffer provided. For HDS and jumbo placement, this means
5058 * that the packet could not be placed into 8 physical buffers
5059 * (if fixed-size buffers are used), or that the packet could
5060 * not be placed in the number of physical buffers configured
5061 * for the VNIC (if variable-size buffers are used)
5063 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5064 (UINT32_C(0x1) << 1)
5066 * Not On Chip: All BDs needed for the packet were not on-chip
5067 * when the packet arrived. For regular placement, this error is
5068 * not valid. For HDS and jumbo placement, this means that not
5069 * enough agg BDs were posted to place the packet.
5071 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5072 (UINT32_C(0x2) << 1)
5075 * BDs were not formatted correctly.
5077 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5078 (UINT32_C(0x3) << 1)
5081 * There was a bad_format error on the previous operation
5083 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
5084 (UINT32_C(0x5) << 1)
5085 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
5086 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
5088 * This indicates that there was an error in the outer tunnel
5089 * portion of the packet when this field is non-zero.
5091 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
5093 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
5095 * No additional error occurred on the outer tunnel portion
5096 * of the packet or the packet does not have a outer tunnel.
5098 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
5099 (UINT32_C(0x0) << 4)
5101 * Indicates that IP header version does not match expectation
5102 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
5104 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
5105 (UINT32_C(0x1) << 4)
5107 * Indicates that header length is out of range in the outer
5108 * tunnel header. Valid for IPv4.
5110 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
5111 (UINT32_C(0x2) << 4)
5113 * Indicates that physical packet is shorter than that claimed
5114 * by the outer tunnel l3 header length. Valid for IPv4, or
5115 * IPv6 outer tunnel packets.
5117 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
5118 (UINT32_C(0x3) << 4)
5120 * Indicates that the physical packet is shorter than that
5121 * claimed by the outer tunnel UDP header length for a outer
5122 * tunnel UDP packet that is not fragmented.
5124 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
5125 (UINT32_C(0x4) << 4)
5127 * Indicates that the IPv4 TTL or IPv6 hop limit check have
5128 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
5131 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
5132 (UINT32_C(0x5) << 4)
5134 * Indicates that the IP checksum failed its check in the outer
5137 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
5138 (UINT32_C(0x6) << 4)
5140 * Indicates that the L4 checksum failed its check in the outer
5143 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
5144 (UINT32_C(0x7) << 4)
5145 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
5146 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
5148 * This indicates that there was a CRC error on either an FCoE
5149 * or RoCE packet. The itype indicates the packet type.
5151 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
5154 * This indicates that there was an error in the tunnel portion
5155 * of the packet when this field is non-zero.
5157 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
5159 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
5161 * No additional error occurred on the tunnel portion
5162 * of the packet or the packet does not have a tunnel.
5164 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
5165 (UINT32_C(0x0) << 9)
5167 * Indicates that IP header version does not match expectation
5168 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
5170 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
5171 (UINT32_C(0x1) << 9)
5173 * Indicates that header length is out of range in the tunnel
5174 * header. Valid for IPv4.
5176 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
5177 (UINT32_C(0x2) << 9)
5179 * Indicates that physical packet is shorter than that claimed
5180 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
5183 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
5184 (UINT32_C(0x3) << 9)
5186 * Indicates that the physical packet is shorter than that claimed
5187 * by the tunnel UDP header length for a tunnel UDP packet that is
5190 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
5191 (UINT32_C(0x4) << 9)
5193 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
5194 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
5196 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
5197 (UINT32_C(0x5) << 9)
5199 * Indicates that the IP checksum failed its check in the tunnel
5202 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
5203 (UINT32_C(0x6) << 9)
5205 * Indicates that the L4 checksum failed its check in the tunnel
5208 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
5209 (UINT32_C(0x7) << 9)
5210 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
5211 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
5213 * This indicates that there was an error in the inner
5214 * portion of the packet when this
5215 * field is non-zero.
5217 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
5219 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
5221 * No additional error occurred on the tunnel portion
5222 * or the packet of the packet does not have a tunnel.
5224 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
5225 (UINT32_C(0x0) << 12)
5227 * Indicates that IP header version does not match
5228 * expectation from L2 Ethertype for IPv4 and IPv6 or that
5229 * option other than VFT was parsed on
5232 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
5233 (UINT32_C(0x1) << 12)
5235 * indicates that header length is out of range. Valid for
5238 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
5239 (UINT32_C(0x2) << 12)
5241 * indicates that the IPv4 TTL or IPv6 hop limit check
5242 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5244 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
5245 (UINT32_C(0x3) << 12)
5247 * Indicates that physical packet is shorter than that
5248 * claimed by the l3 header length. Valid for IPv4,
5249 * IPv6 packet or RoCE packets.
5251 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
5252 (UINT32_C(0x4) << 12)
5254 * Indicates that the physical packet is shorter than that
5255 * claimed by the UDP header length for a UDP packet that is
5258 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
5259 (UINT32_C(0x5) << 12)
5261 * Indicates that TCP header length > IP payload. Valid for
5264 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
5265 (UINT32_C(0x6) << 12)
5266 /* Indicates that TCP header length < 5. Valid for TCP. */
5267 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
5268 (UINT32_C(0x7) << 12)
5270 * Indicates that TCP option headers result in a TCP header
5271 * size that does not match data offset in TCP header. Valid
5274 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
5275 (UINT32_C(0x8) << 12)
5277 * Indicates that the IP checksum failed its check in the
5280 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
5281 (UINT32_C(0x9) << 12)
5283 * Indicates that the L4 checksum failed its check in the
5286 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
5287 (UINT32_C(0xa) << 12)
5288 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
5289 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
5291 * This is data from the CFA block as indicated by the meta_format
5295 /* When meta_format=1, this value is the VLAN VID. */
5296 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
5297 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
5298 /* When meta_format=1, this value is the VLAN DE. */
5299 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
5300 /* When meta_format=1, this value is the VLAN PRI. */
5301 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
5302 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
5304 * The timestamp field contains the 32b timestamp for the packet from
5311 * This TPA completion structure is used on devices where the
5312 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5314 /* rx_tpa_start_cmpl (size:128b/16B) */
5315 struct rx_tpa_start_cmpl {
5316 uint16_t flags_type;
5318 * This field indicates the exact type of the completion.
5319 * By convention, the LSB identifies the length of the
5320 * record in 16B units. Even values indicate 16B
5321 * records. Odd values indicate 32B
5324 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
5325 #define RX_TPA_START_CMPL_TYPE_SFT 0
5327 * RX L2 TPA Start Completion:
5328 * Completion at the beginning of a TPA operation.
5331 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
5332 #define RX_TPA_START_CMPL_TYPE_LAST \
5333 RX_TPA_START_CMPL_TYPE_RX_TPA_START
5334 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5335 #define RX_TPA_START_CMPL_FLAGS_SFT 6
5336 /* This bit will always be '0' for TPA start completions. */
5337 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
5338 /* This field indicates how the packet was placed in the buffer. */
5339 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5340 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
5343 * TPA Packet was placed using jumbo algorithm. This means
5344 * that the first buffer will be filled with data before
5345 * moving to aggregation buffers. Each aggregation buffer
5346 * will be filled before moving to the next aggregation
5349 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5350 (UINT32_C(0x1) << 7)
5352 * Header/Data Separation:
5353 * Packet was placed using Header/Data separation algorithm.
5354 * The separation location is indicated by the itype field.
5356 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
5357 (UINT32_C(0x2) << 7)
5360 * Packet will be placed using GRO/Jumbo where the first
5361 * packet is filled with data. Subsequent packets will be
5362 * placed such that any one packet does not span two
5363 * aggregation buffers unless it starts at the beginning of
5364 * an aggregation buffer.
5366 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5367 (UINT32_C(0x5) << 7)
5369 * GRO/Header-Data Separation:
5370 * Packet will be placed using GRO/HDS where the header
5371 * is in the first packet.
5372 * Payload of each packet will be
5373 * placed such that any one packet does not span two
5374 * aggregation buffers unless it starts at the beginning of
5375 * an aggregation buffer.
5377 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5378 (UINT32_C(0x6) << 7)
5379 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
5380 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5381 /* This bit is '1' if the RSS field in this completion is valid. */
5382 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5384 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
5386 * This value indicates what the inner packet determined for the
5389 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5390 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
5393 * Indicates that the packet was IP and TCP.
5395 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
5396 (UINT32_C(0x2) << 12)
5397 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
5398 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
5400 * This value indicates the amount of packet data written to the
5401 * buffer the opaque field in this completion corresponds to.
5405 * This is a copy of the opaque field from the RX BD this completion
5410 * This value is written by the NIC such that it will be different
5411 * for each pass through the completion queue. The even passes
5412 * will write 1. The odd passes will write 0.
5416 * This value is written by the NIC such that it will be different
5417 * for each pass through the completion queue. The even passes
5418 * will write 1. The odd passes will write 0.
5420 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
5421 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
5423 * This is the RSS hash type for the packet. The value is packed
5424 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5426 * The value of tuple_extrac_op provides the information about
5427 * what fields the hash was computed on.
5428 * * 0: The RSS hash was computed over source IP address,
5429 * destination IP address, source port, and destination port of inner
5430 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5431 * the packet headers are considered inner packet headers for the RSS
5432 * hash computation purpose.
5433 * * 1: The RSS hash was computed over source IP address and destination
5434 * IP address of inner IP header. Note: For non-tunneled packets,
5435 * the packet headers are considered inner packet headers for the RSS
5436 * hash computation purpose.
5437 * * 2: The RSS hash was computed over source IP address,
5438 * destination IP address, source port, and destination port of
5439 * IP and TCP or UDP headers of outer tunnel headers.
5440 * Note: For non-tunneled packets, this value is not applicable.
5441 * * 3: The RSS hash was computed over source IP address and
5442 * destination IP address of IP header of outer tunnel headers.
5443 * Note: For non-tunneled packets, this value is not applicable.
5445 * Note that 4-tuples values listed above are applicable
5446 * for layer 4 protocols supported and enabled for RSS in the hardware,
5447 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5448 * enabled for TCP traffic only, then the values of tuple_extract_op
5449 * corresponding to 4-tuples are only valid for TCP traffic.
5451 uint8_t rss_hash_type;
5453 * This is the aggregation ID that the completion is associated
5454 * with. Use this number to correlate the TPA start completion
5455 * with the TPA end completion.
5458 /* unused2 is 9 b */
5459 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
5460 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
5462 * This is the aggregation ID that the completion is associated
5463 * with. Use this number to correlate the TPA start completion
5464 * with the TPA end completion.
5466 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
5467 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
5469 * This value is the RSS hash value calculated for the packet
5470 * based on the mode bits and key value in the VNIC.
5476 * Last 16 bytes of rx_tpa_start_cmpl.
5478 * This TPA completion structure is used on devices where the
5479 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5481 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
5482 struct rx_tpa_start_cmpl_hi {
5485 * This indicates that the ip checksum was calculated for the
5486 * inner packet and that the sum passed for all segments
5487 * included in the aggregation.
5489 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5491 * This indicates that the TCP, UDP or ICMP checksum was
5492 * calculated for the inner packet and that the sum passed
5493 * for all segments included in the aggregation.
5495 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5497 * This indicates that the ip checksum was calculated for the
5498 * tunnel header and that the sum passed for all segments
5499 * included in the aggregation.
5501 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5503 * This indicates that the UDP checksum was
5504 * calculated for the tunnel packet and that the sum passed for
5505 * all segments included in the aggregation.
5507 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5508 /* This value indicates what format the metadata field is. */
5509 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5510 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5511 /* No metadata information. Value is zero. */
5512 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
5513 (UINT32_C(0x0) << 4)
5515 * The metadata field contains the VLAN tag and TPID value.
5516 * - metadata[11:0] contains the vlan VID value.
5517 * - metadata[12] contains the vlan DE value.
5518 * - metadata[15:13] contains the vlan PRI value.
5519 * - metadata[31:16] contains the vlan TPID value.
5521 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5522 (UINT32_C(0x1) << 4)
5523 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
5524 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
5526 * This field indicates the IP type for the inner-most IP header.
5527 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5529 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5531 * This is data from the CFA block as indicated by the meta_format
5535 /* When meta_format=1, this value is the VLAN VID. */
5536 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5537 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
5538 /* When meta_format=1, this value is the VLAN DE. */
5539 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
5540 /* When meta_format=1, this value is the VLAN PRI. */
5541 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5542 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
5543 /* When meta_format=1, this value is the VLAN TPID. */
5544 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5545 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
5548 * This value is written by the NIC such that it will be different
5549 * for each pass through the completion queue. The even passes
5550 * will write 1. The odd passes will write 0.
5552 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
5554 * This field identifies the CFA action rule that was used for this
5559 * This is the size in bytes of the inner most L4 header.
5560 * This can be subtracted from the payload_offset to determine
5561 * the start of the inner most L4 header.
5563 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5565 * This is the offset from the beginning of the packet in bytes for
5566 * the outer L3 header. If there is no outer L3 header, then this
5569 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5570 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
5572 * This is the offset from the beginning of the packet in bytes for
5573 * the inner most L2 header.
5575 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5576 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
5578 * This is the offset from the beginning of the packet in bytes for
5579 * the inner most L3 header.
5581 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5582 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
5584 * This is the size in bytes of the inner most L4 header.
5585 * This can be subtracted from the payload_offset to determine
5586 * the start of the inner most L4 header.
5588 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5589 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
5593 * This TPA completion structure is used on devices where the
5594 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5595 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
5598 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
5599 struct rx_tpa_start_v2_cmpl {
5600 uint16_t flags_type;
5602 * This field indicates the exact type of the completion.
5603 * By convention, the LSB identifies the length of the
5604 * record in 16B units. Even values indicate 16B
5605 * records. Odd values indicate 32B
5608 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
5610 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
5612 * RX L2 TPA Start V2 Completion:
5613 * Completion at the beginning of a TPA operation.
5615 * This is the new version of the RX_TPA_START completion used
5616 * in SR2 and later chips.
5618 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
5620 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
5621 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
5622 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
5624 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
5626 * When this bit is '1', it indicates a packet that has an error
5627 * of some type. Type of error is indicated in error_flags.
5629 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
5631 /* This field indicates how the packet was placed in the buffer. */
5632 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
5634 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
5637 * TPA Packet was placed using jumbo algorithm. This means
5638 * that the first buffer will be filled with data before
5639 * moving to aggregation buffers. Each aggregation buffer
5640 * will be filled before moving to the next aggregation
5643 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
5644 (UINT32_C(0x1) << 7)
5646 * Header/Data Separation:
5647 * Packet was placed using Header/Data separation algorithm.
5648 * The separation location is indicated by the itype field.
5650 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
5651 (UINT32_C(0x2) << 7)
5654 * Packet will be placed using In-Order Completion/Jumbo where
5655 * the first packet of the aggregation is placed using Jumbo
5656 * Placement. Subsequent packets will be placed such that each
5657 * packet starts at the beginning of an aggregation buffer.
5659 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
5660 (UINT32_C(0x4) << 7)
5663 * Packet will be placed using GRO/Jumbo where the first
5664 * packet is filled with data. Subsequent packets will be
5665 * placed such that any one packet does not span two
5666 * aggregation buffers unless it starts at the beginning of
5667 * an aggregation buffer.
5669 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5670 (UINT32_C(0x5) << 7)
5672 * GRO/Header-Data Separation:
5673 * Packet will be placed using GRO/HDS where the header
5674 * is in the first packet.
5675 * Payload of each packet will be
5676 * placed such that any one packet does not span two
5677 * aggregation buffers unless it starts at the beginning of
5678 * an aggregation buffer.
5680 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5681 (UINT32_C(0x6) << 7)
5683 * IOC/Header-Data Separation:
5684 * Packet will be placed using In-Order Completion/HDS where
5685 * the header is in the first packet buffer. Payload of each
5686 * packet will be placed such that each packet starts at the
5687 * beginning of an aggregation buffer.
5689 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
5690 (UINT32_C(0x7) << 7)
5691 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
5692 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
5693 /* This bit is '1' if the RSS field in this completion is valid. */
5694 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
5697 * This bit is '1' if metadata has been added to the end of the
5698 * packet in host memory. Metadata starts at the first 32B boundary
5699 * after the end of the packet for regular and jumbo placement. It
5700 * starts at the first 32B boundary after the end of the header for
5701 * HDS placement. The length of the metadata is indicated in the
5704 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
5707 * This value indicates what the inner packet determined for the
5710 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
5712 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
5715 * Indicates that the packet was IP and TCP.
5717 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
5718 (UINT32_C(0x2) << 12)
5719 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
5720 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
5722 * This value indicates the amount of packet data written to the
5723 * buffer the opaque field in this completion corresponds to.
5727 * This is a copy of the opaque field from the RX BD this completion
5728 * corresponds to. If the VNIC is configured to not use an Rx BD for
5729 * the TPA Start completion, then this is a copy of the opaque field
5730 * from the first BD used to place the TPA Start packet.
5734 * This value is written by the NIC such that it will be different
5735 * for each pass through the completion queue. The even passes
5736 * will write 1. The odd passes will write 0.
5740 * This value is written by the NIC such that it will be different
5741 * for each pass through the completion queue. The even passes
5742 * will write 1. The odd passes will write 0.
5744 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
5745 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
5747 * This is the RSS hash type for the packet. The value is packed
5748 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5750 * The value of tuple_extrac_op provides the information about
5751 * what fields the hash was computed on.
5752 * * 0: The RSS hash was computed over source IP address,
5753 * destination IP address, source port, and destination port of inner
5754 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5755 * the packet headers are considered inner packet headers for the RSS
5756 * hash computation purpose.
5757 * * 1: The RSS hash was computed over source IP address and destination
5758 * IP address of inner IP header. Note: For non-tunneled packets,
5759 * the packet headers are considered inner packet headers for the RSS
5760 * hash computation purpose.
5761 * * 2: The RSS hash was computed over source IP address,
5762 * destination IP address, source port, and destination port of
5763 * IP and TCP or UDP headers of outer tunnel headers.
5764 * Note: For non-tunneled packets, this value is not applicable.
5765 * * 3: The RSS hash was computed over source IP address and
5766 * destination IP address of IP header of outer tunnel headers.
5767 * Note: For non-tunneled packets, this value is not applicable.
5769 * Note that 4-tuples values listed above are applicable
5770 * for layer 4 protocols supported and enabled for RSS in the hardware,
5771 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5772 * enabled for TCP traffic only, then the values of tuple_extract_op
5773 * corresponding to 4-tuples are only valid for TCP traffic.
5775 uint8_t rss_hash_type;
5777 * This is the aggregation ID that the completion is associated
5778 * with. Use this number to correlate the TPA start completion
5779 * with the TPA end completion.
5783 * This is the aggregation ID that the completion is associated
5784 * with. Use this number to correlate the TPA start completion
5785 * with the TPA end completion.
5787 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
5788 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
5789 #define RX_TPA_START_V2_CMPL_METADATA1_MASK \
5791 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
5792 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5793 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK \
5795 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
5797 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 \
5798 (UINT32_C(0x0) << 12)
5800 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 \
5801 (UINT32_C(0x1) << 12)
5803 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 \
5804 (UINT32_C(0x2) << 12)
5806 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 \
5807 (UINT32_C(0x3) << 12)
5809 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 \
5810 (UINT32_C(0x4) << 12)
5811 /* Value programmed in CFA VLANTPID register. */
5812 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG \
5813 (UINT32_C(0x5) << 12)
5814 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_LAST \
5815 RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG
5816 /* When meta_format != 0, this value is the VLAN valid. */
5817 #define RX_TPA_START_V2_CMPL_METADATA1_VALID \
5820 * This value is the RSS hash value calculated for the packet
5821 * based on the mode bits and key value in the VNIC.
5822 * When vee_cmpl_mode is set in VNIC context, this is the lower
5823 * 32b of the host address from the first BD used to place the packet.
5829 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
5831 * This TPA completion structure is used on devices where the
5832 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
5834 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
5835 struct rx_tpa_start_v2_cmpl_hi {
5837 /* This indicates that the aggregation was done using GRO rules. */
5838 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
5841 * When this bit is '0', the cs_ok field has the following definition:-
5842 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
5843 * in the delivered packet, counted from the outer-most header group to
5844 * the inner-most header group, stopping at the first error. -
5845 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
5846 * in the delivered packet, counted from the outer-most header group to
5847 * the inner-most header group, stopping at the first error. When this
5848 * bit is '1', the cs_ok field has the following definition: -
5849 * hdr_cnt[2:0] = The number of header groups that were parsed by the
5850 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
5851 * will be '1' if all the parsed header groups with an IP checksum are
5852 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
5853 * header groups with an L4 checksum are valid.
5855 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
5857 /* This value indicates what format the metadata field is. */
5858 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
5860 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
5861 /* There is no metadata information. Values are zero. */
5862 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
5863 (UINT32_C(0x0) << 4)
5865 * The {metadata1, metadata0} fields contain the vtag
5866 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
5867 * de, vid[11:0]} The metadata2 field contains the table scope
5868 * and action record pointer. - metadata2[25:0] contains the
5869 * action record pointer. - metadata2[31:26] contains the table
5872 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
5873 (UINT32_C(0x1) << 4)
5875 * The {metadata1, metadata0} fields contain the vtag
5877 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5878 * The metadata2 field contains the Tunnel ID
5879 * value, justified to LSB. i
5880 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5881 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
5882 * - NVGRE = TNI[23:0] -> Tenant Network ID
5883 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
5884 * - IPv4 = 0 (not populated)
5885 * - IPv6 = Flow Label[19:0]
5886 * - PPPoE = sessionID[15:0]
5887 * - MPLs = Outer label[19:0]
5888 * - UPAR = Selected[31:0] with bit mask
5890 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5891 (UINT32_C(0x2) << 4)
5893 * The {metadata1, metadata0} fields contain the vtag
5895 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
5896 * The metadata2 field contains the 32b metadata from the prepended
5897 * header (chdr_data).
5899 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5900 (UINT32_C(0x3) << 4)
5902 * The {metadata1, metadata0} fields contain the vtag
5904 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
5905 * The metadata2 field contains the outer_l3_offset,
5906 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
5907 * - metadata2[8:0] contains the outer_l3_offset.
5908 * - metadata2[17:9] contains the inner_l2_offset.
5909 * - metadata2[26:18] contains the inner_l3_offset.
5910 * - metadata2[31:27] contains the inner_l4_size.
5912 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5913 (UINT32_C(0x4) << 4)
5914 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
5915 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5917 * This field indicates the IP type for the inner-most IP header.
5918 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5919 * This value is only valid if itype indicates a packet
5920 * with an IP header.
5922 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
5925 * This indicates that the complete 1's complement checksum was
5926 * calculated for the packet in the affregation.
5928 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5931 * This field indicates the status of IP and L4 CS calculations done
5932 * by the chip. The format of this field is indicated by the
5933 * cs_all_ok_mode bit.
5934 * CS status for TPA packets is always valid. This means that "all_ok"
5935 * status will always be set. The ok count status will be set
5936 * appropriately for the packet header, such that all existing CS
5939 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
5941 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
5943 * This value is the complete 1's complement checksum calculated from
5944 * the start of the outer L3 header to the end of the packet (not
5945 * including the ethernet crc). It is valid when the
5946 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5947 * the complete checksum is calculated for the first packet in the
5950 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5951 UINT32_C(0xffff0000)
5952 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5954 * This is data from the CFA block as indicated by the meta_format
5956 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
5957 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
5958 * act_rec_ptr[25:0]}
5959 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
5960 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
5961 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
5962 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
5963 * of the host address from the first BD used to place the packet.
5968 * This value is written by the NIC such that it will be different
5969 * for each pass through the completion queue. The even passes
5970 * will write 1. The odd passes will write 0.
5972 #define RX_TPA_START_V2_CMPL_V2 \
5974 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
5976 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
5978 * This error indicates that there was some sort of problem with
5979 * the BDs for the packetThe packet should be treated as
5982 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
5984 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5985 /* No buffer error */
5986 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5987 (UINT32_C(0x0) << 1)
5990 * Packet did not fit into packet buffer provided. This means
5991 * that the TPA Start packet was too big to be placed into the
5992 * per-packet maximum number of physical buffers configured for
5993 * the VNIC, or that it was too big to be placed into the
5994 * per-aggregation maximum number of physical buffers configured
5995 * for the VNIC. This error only occurs when the VNIC is
5996 * configured for variable size receive buffers.
5998 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5999 (UINT32_C(0x1) << 1)
6002 * BDs were not formatted correctly.
6004 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6005 (UINT32_C(0x3) << 1)
6008 * There was a bad_format error on the previous operation
6010 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6011 (UINT32_C(0x5) << 1)
6012 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
6013 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6015 * This is data from the CFA block as indicated by the meta_format
6019 /* When meta_format != 0, this value is the VLAN VID. */
6020 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
6021 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
6022 /* When meta_format != 0, this value is the VLAN DE. */
6023 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
6024 /* When meta_format != 0, this value is the VLAN PRI. */
6025 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
6026 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
6028 * This field contains the outer_l3_offset, inner_l2_offset,
6029 * inner_l3_offset, and inner_l4_size.
6031 * hdr_offsets[8:0] contains the outer_l3_offset.
6032 * hdr_offsets[17:9] contains the inner_l2_offset.
6033 * hdr_offsets[26:18] contains the inner_l3_offset.
6034 * hdr_offsets[31:27] contains the inner_l4_size.
6036 uint32_t hdr_offsets;
6040 * This TPA completion structure is used on devices where the
6041 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6043 /* rx_tpa_end_cmpl (size:128b/16B) */
6044 struct rx_tpa_end_cmpl {
6045 uint16_t flags_type;
6047 * This field indicates the exact type of the completion.
6048 * By convention, the LSB identifies the length of the
6049 * record in 16B units. Even values indicate 16B
6050 * records. Odd values indicate 32B
6053 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
6054 #define RX_TPA_END_CMPL_TYPE_SFT 0
6056 * RX L2 TPA End Completion:
6057 * Completion at the end of a TPA operation.
6060 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
6061 #define RX_TPA_END_CMPL_TYPE_LAST \
6062 RX_TPA_END_CMPL_TYPE_RX_TPA_END
6063 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6064 #define RX_TPA_END_CMPL_FLAGS_SFT 6
6066 * When this bit is '1', it indicates a packet that has an
6067 * error of some type. Type of error is indicated in
6070 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
6071 /* This field indicates how the packet was placed in the buffer. */
6072 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6073 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
6076 * TPA Packet was placed using jumbo algorithm. This means
6077 * that the first buffer will be filled with data before
6078 * moving to aggregation buffers. Each aggregation buffer
6079 * will be filled before moving to the next aggregation
6082 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6083 (UINT32_C(0x1) << 7)
6085 * Header/Data Separation:
6086 * Packet was placed using Header/Data separation algorithm.
6087 * The separation location is indicated by the itype field.
6089 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
6090 (UINT32_C(0x2) << 7)
6093 * Packet will be placed using In-Order Completion/Jumbo where
6094 * the first packet of the aggregation is placed using Jumbo
6095 * Placement. Subsequent packets will be placed such that each
6096 * packet starts at the beginning of an aggregation buffer.
6098 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
6099 (UINT32_C(0x4) << 7)
6102 * Packet will be placed using GRO/Jumbo where the first
6103 * packet is filled with data. Subsequent packets will be
6104 * placed such that any one packet does not span two
6105 * aggregation buffers unless it starts at the beginning of
6106 * an aggregation buffer.
6108 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6109 (UINT32_C(0x5) << 7)
6111 * GRO/Header-Data Separation:
6112 * Packet will be placed using GRO/HDS where the header
6113 * is in the first packet.
6114 * Payload of each packet will be
6115 * placed such that any one packet does not span two
6116 * aggregation buffers unless it starts at the beginning of
6117 * an aggregation buffer.
6119 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6120 (UINT32_C(0x6) << 7)
6122 * IOC/Header-Data Separation:
6123 * Packet will be placed using In-Order Completion/HDS where
6124 * the header is in the first packet buffer. Payload of each
6125 * packet will be placed such that each packet starts at the
6126 * beginning of an aggregation buffer.
6128 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6129 (UINT32_C(0x7) << 7)
6130 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
6131 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6133 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
6135 * This bit is '1' if metadata has been added to the end of the
6136 * packet in host memory. Metadata starts at the first 32B boundary
6137 * after the end of the packet for regular and jumbo placement.
6138 * It starts at the first 32B boundary after the end of the header
6139 * for HDS placement. The length of the metadata is indicated in the
6142 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6144 * This value indicates what the inner packet determined for the
6147 * Indicates that the packet was IP and TCP. This indicates
6148 * that the ip_cs field is valid and that the tcp_udp_cs
6149 * field is valid and contains the TCP checksum.
6150 * This also indicates that the payload_offset field is valid.
6152 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
6154 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
6156 * This value is zero for TPA End completions.
6157 * There is no data in the buffer that corresponds to the opaque
6158 * value in this completion.
6162 * This is a copy of the opaque field from the RX BD this completion
6167 * This value is written by the NIC such that it will be different
6168 * for each pass through the completion queue. The even passes
6169 * will write 1. The odd passes will write 0.
6171 uint8_t agg_bufs_v1;
6173 * This value is written by the NIC such that it will be different
6174 * for each pass through the completion queue. The even passes
6175 * will write 1. The odd passes will write 0.
6177 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
6179 * This value is the number of aggregation buffers that follow this
6180 * entry in the completion ring that are a part of this aggregation
6182 * If the value is zero, then the packet is completely contained
6183 * in the buffer space provided in the aggregation start completion.
6185 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
6186 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
6187 /* This value is the number of segments in the TPA operation. */
6190 * This value indicates the offset in bytes from the beginning of the packet
6191 * where the inner payload starts. This value is valid for TCP, UDP,
6192 * FCoE, and RoCE packets.
6194 * A value of zero indicates an offset of 256 bytes.
6196 uint8_t payload_offset;
6198 /* unused2 is 1 b */
6199 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
6201 * This is the aggregation ID that the completion is associated
6202 * with. Use this number to correlate the TPA start completion
6203 * with the TPA end completion.
6205 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
6206 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
6208 * For non-GRO packets, this value is the
6209 * timestamp delta between earliest and latest timestamp values for
6210 * TPA packet. If packets were not time stamped, then delta will be
6213 * For GRO packets, this field is zero except for the following
6216 * Timestamp present indication. When '0', no Timestamp
6217 * option is in the packet. When '1', then a Timestamp
6218 * option is present in the packet.
6224 * Last 16 bytes of rx_tpa_end_cmpl.
6226 * This TPA completion structure is used on devices where the
6227 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
6229 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
6230 struct rx_tpa_end_cmpl_hi {
6231 uint32_t tpa_dup_acks;
6233 * This value is the number of duplicate ACKs that have been
6234 * received as part of the TPA operation.
6236 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6237 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
6239 * This value is the valid when TPA completion is active. It
6240 * indicates the length of the longest segment of the TPA operation
6241 * for LRO mode and the length of the first segment in GRO mode.
6243 * This value may be used by GRO software to re-construct the original
6244 * packet stream from the TPA packet. This is the length of all
6245 * but the last segment for GRO. In LRO mode this value may be used
6246 * to indicate MSS size to the stack.
6248 uint16_t tpa_seg_len;
6249 /* unused4 is 16 b */
6253 * This value is written by the NIC such that it will be different
6254 * for each pass through the completion queue. The even passes
6255 * will write 1. The odd passes will write 0.
6257 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
6258 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
6259 #define RX_TPA_END_CMPL_ERRORS_SFT 1
6261 * This error indicates that there was some sort of problem with
6262 * the BDs for the packet that was found after part of the
6263 * packet was already placed. The packet should be treated as
6266 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6267 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6269 * This error occurs when there is a fatal HW problem in
6270 * the chip only. It indicates that there were not
6271 * BDs on chip but that there was adequate reservation.
6272 * provided by the TPA block.
6274 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6275 (UINT32_C(0x2) << 1)
6277 * This error occurs when TPA block was not configured to
6278 * reserve adequate BDs for TPA operations on this RX
6279 * ring. All data for the TPA operation was not placed.
6281 * This error can also be generated when the number of
6282 * segments is not programmed correctly in TPA and the
6283 * 33 total aggregation buffers allowed for the TPA
6284 * operation has been exceeded.
6286 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6287 (UINT32_C(0x4) << 1)
6288 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6289 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
6290 /* unused5 is 16 b */
6293 * This is the opaque value that was completed for the TPA start
6294 * completion that corresponds to this TPA end completion.
6296 uint32_t start_opaque;
6300 * This TPA completion structure is used on devices where the
6301 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6303 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
6304 struct rx_tpa_v2_start_cmpl {
6305 uint16_t flags_type;
6307 * This field indicates the exact type of the completion.
6308 * By convention, the LSB identifies the length of the
6309 * record in 16B units. Even values indicate 16B
6310 * records. Odd values indicate 32B
6313 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
6315 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
6317 * RX L2 TPA Start Completion:
6318 * Completion at the beginning of a TPA operation.
6321 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
6323 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
6324 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
6325 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
6327 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
6328 /* This bit will always be '0' for TPA start completions. */
6329 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
6331 /* This field indicates how the packet was placed in the buffer. */
6332 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
6334 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
6337 * TPA Packet was placed using jumbo algorithm. This means
6338 * that the first buffer will be filled with data before
6339 * moving to aggregation buffers. Each aggregation buffer
6340 * will be filled before moving to the next aggregation
6343 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
6344 (UINT32_C(0x1) << 7)
6346 * Header/Data Separation:
6347 * Packet was placed using Header/Data separation algorithm.
6348 * The separation location is indicated by the itype field.
6350 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
6351 (UINT32_C(0x2) << 7)
6354 * Packet will be placed using GRO/Jumbo where the first
6355 * packet is filled with data. Subsequent packets will be
6356 * placed such that any one packet does not span two
6357 * aggregation buffers unless it starts at the beginning of
6358 * an aggregation buffer.
6360 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6361 (UINT32_C(0x5) << 7)
6363 * GRO/Header-Data Separation:
6364 * Packet will be placed using GRO/HDS where the header
6365 * is in the first packet.
6366 * Payload of each packet will be
6367 * placed such that any one packet does not span two
6368 * aggregation buffers unless it starts at the beginning of
6369 * an aggregation buffer.
6371 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6372 (UINT32_C(0x6) << 7)
6373 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
6374 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
6375 /* This bit is '1' if the RSS field in this completion is valid. */
6376 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
6379 * For devices that support timestamps, when this bit is cleared the
6380 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6381 * field contains the 32b timestamp for
6382 * the packet from the MAC. When this bit is set, the
6383 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
6384 * field contains the outer_l3_offset, inner_l2_offset,
6385 * inner_l3_offset, and inner_l4_size.
6387 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
6390 * This value indicates what the inner packet determined for the
6393 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
6395 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
6398 * Indicates that the packet was IP and TCP.
6400 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
6401 (UINT32_C(0x2) << 12)
6402 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
6403 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
6405 * This value indicates the amount of packet data written to the
6406 * buffer the opaque field in this completion corresponds to.
6410 * This is a copy of the opaque field from the RX BD this completion
6415 * This value is written by the NIC such that it will be different
6416 * for each pass through the completion queue. The even passes
6417 * will write 1. The odd passes will write 0.
6421 * This value is written by the NIC such that it will be different
6422 * for each pass through the completion queue. The even passes
6423 * will write 1. The odd passes will write 0.
6425 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
6426 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
6428 * This is the RSS hash type for the packet. The value is packed
6429 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6431 * The value of tuple_extrac_op provides the information about
6432 * what fields the hash was computed on.
6433 * * 0: The RSS hash was computed over source IP address,
6434 * destination IP address, source port, and destination port of inner
6435 * IP and TCP or UDP headers. Note: For non-tunneled packets,
6436 * the packet headers are considered inner packet headers for the RSS
6437 * hash computation purpose.
6438 * * 1: The RSS hash was computed over source IP address and destination
6439 * IP address of inner IP header. Note: For non-tunneled packets,
6440 * the packet headers are considered inner packet headers for the RSS
6441 * hash computation purpose.
6442 * * 2: The RSS hash was computed over source IP address,
6443 * destination IP address, source port, and destination port of
6444 * IP and TCP or UDP headers of outer tunnel headers.
6445 * Note: For non-tunneled packets, this value is not applicable.
6446 * * 3: The RSS hash was computed over source IP address and
6447 * destination IP address of IP header of outer tunnel headers.
6448 * Note: For non-tunneled packets, this value is not applicable.
6450 * Note that 4-tuples values listed above are applicable
6451 * for layer 4 protocols supported and enabled for RSS in the hardware,
6452 * HWRM firmware, and drivers. For example, if RSS hash is supported and
6453 * enabled for TCP traffic only, then the values of tuple_extract_op
6454 * corresponding to 4-tuples are only valid for TCP traffic.
6456 uint8_t rss_hash_type;
6458 * This is the aggregation ID that the completion is associated
6459 * with. Use this number to correlate the TPA start completion
6460 * with the TPA end completion.
6464 * This value is the RSS hash value calculated for the packet
6465 * based on the mode bits and key value in the VNIC.
6471 * Last 16 bytes of rx_tpa_v2_start_cmpl.
6473 * This TPA completion structure is used on devices where the
6474 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6476 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
6477 struct rx_tpa_v2_start_cmpl_hi {
6480 * This indicates that the ip checksum was calculated for the
6481 * inner packet and that the sum passed for all segments
6482 * included in the aggregation.
6484 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
6487 * This indicates that the TCP, UDP or ICMP checksum was
6488 * calculated for the inner packet and that the sum passed
6489 * for all segments included in the aggregation.
6491 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
6494 * This indicates that the ip checksum was calculated for the
6495 * tunnel header and that the sum passed for all segments
6496 * included in the aggregation.
6498 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
6501 * This indicates that the UDP checksum was
6502 * calculated for the tunnel packet and that the sum passed for
6503 * all segments included in the aggregation.
6505 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
6507 /* This value indicates what format the metadata field is. */
6508 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
6510 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
6511 /* No metadata informtaion. Value is zero. */
6512 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
6513 (UINT32_C(0x0) << 4)
6515 * The metadata field contains the VLAN tag and TPID value.
6516 * - metadata[11:0] contains the vlan VID value.
6517 * - metadata[12] contains the vlan DE value.
6518 * - metadata[15:13] contains the vlan PRI value.
6519 * - metadata[31:16] contains the vlan TPID value.
6521 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
6522 (UINT32_C(0x1) << 4)
6524 * If ext_meta_format is equal to 1, the metadata field
6525 * contains the lower 16b of the tunnel ID value, justified
6527 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6528 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
6529 * - NVGRE = TNI[23:0] -> Tenant Network ID
6530 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
6531 * - IPV4 = 0 (not populated)
6532 * - IPV6 = Flow Label[19:0]
6533 * - PPPoE = sessionID[15:0]
6534 * - MPLs = Outer label[19:0]
6535 * - UPAR = Selected[31:0] with bit mask
6537 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
6538 (UINT32_C(0x2) << 4)
6540 * if ext_meta_format is equal to 1, metadata field contains
6541 * 16b metadata from the prepended header (chdr_data).
6543 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
6544 (UINT32_C(0x3) << 4)
6546 * If ext_meta_format is equal to 1, the metadata field contains
6547 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
6549 * - metadata[8:0] contains the outer_l3_offset.
6550 * - metadata[17:9] contains the inner_l2_offset.
6551 * - metadata[26:18] contains the inner_l3_offset.
6552 * - metadata[31:27] contains the inner_l4_size.
6554 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
6555 (UINT32_C(0x4) << 4)
6556 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
6557 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
6559 * This field indicates the IP type for the inner-most IP header.
6560 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6562 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
6565 * This indicates that the complete 1's complement checksum was
6566 * calculated for the packet.
6568 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
6571 * The combination of this value and meta_format indicated what
6572 * format the metadata field is.
6574 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
6576 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
6578 * This value is the complete 1's complement checksum calculated from
6579 * the start of the outer L3 header to the end of the packet (not
6580 * including the ethernet crc). It is valid when the
6581 * 'complete_checksum_calc' flag is set. For TPA Start completions,
6582 * the complete checksum is calculated for the first packet in the
6585 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
6586 UINT32_C(0xffff0000)
6587 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
6589 * This is data from the CFA block as indicated by the meta_format
6593 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
6594 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
6595 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
6596 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
6597 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
6598 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
6599 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
6600 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
6601 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
6602 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
6603 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
6606 * This value is written by the NIC such that it will be different
6607 * for each pass through the completion queue. The even passes
6608 * will write 1. The odd passes will write 0.
6610 #define RX_TPA_V2_START_CMPL_V2 \
6612 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
6614 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
6616 * This error indicates that there was some sort of problem with
6617 * the BDs for the packet that was found after part of the
6618 * packet was already placed. The packet should be treated as
6621 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
6623 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6624 /* No buffer error */
6625 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6626 (UINT32_C(0x0) << 1)
6629 * BDs were not formatted correctly.
6631 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6632 (UINT32_C(0x3) << 1)
6635 * There was a bad_format error on the previous operation
6637 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6638 (UINT32_C(0x5) << 1)
6639 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
6640 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6642 * This field identifies the CFA action rule that was used for this
6647 * For devices that support timestamps this field is overridden
6648 * with the timestamp value. When `flags.timestamp_fld_format` is
6649 * cleared, this field contains the 32b timestamp for the packet from the
6652 * When `flags.timestamp_fld_format` is set, this field contains the
6653 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
6656 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
6658 * This is the offset from the beginning of the packet in bytes for
6659 * the outer L3 header. If there is no outer L3 header, then this
6662 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
6663 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
6665 * This is the offset from the beginning of the packet in bytes for
6666 * the inner most L2 header.
6668 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
6669 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
6671 * This is the offset from the beginning of the packet in bytes for
6672 * the inner most L3 header.
6674 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
6675 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
6677 * This is the size in bytes of the inner most L4 header.
6678 * This can be subtracted from the payload_offset to determine
6679 * the start of the inner most L4 header.
6681 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
6682 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
6686 * This TPA completion structure is used on devices where the
6687 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6689 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
6690 struct rx_tpa_v2_end_cmpl {
6691 uint16_t flags_type;
6693 * This field indicates the exact type of the completion.
6694 * By convention, the LSB identifies the length of the
6695 * record in 16B units. Even values indicate 16B
6696 * records. Odd values indicate 32B
6699 #define RX_TPA_V2_END_CMPL_TYPE_MASK \
6701 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
6703 * RX L2 TPA End Completion:
6704 * Completion at the end of a TPA operation.
6707 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END \
6709 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
6710 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
6711 #define RX_TPA_V2_END_CMPL_FLAGS_MASK \
6713 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
6715 * When this bit is '1', it indicates a packet that has an
6716 * error of some type. Type of error is indicated in
6719 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR \
6721 /* This field indicates how the packet was placed in the buffer. */
6722 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK \
6724 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
6727 * TPA Packet was placed using jumbo algorithm. This means
6728 * that the first buffer will be filled with data before
6729 * moving to aggregation buffers. Each aggregation buffer
6730 * will be filled before moving to the next aggregation
6733 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
6734 (UINT32_C(0x1) << 7)
6736 * Header/Data Separation:
6737 * Packet was placed using Header/Data separation algorithm.
6738 * The separation location is indicated by the itype field.
6740 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
6741 (UINT32_C(0x2) << 7)
6744 * Packet will be placed using GRO/Jumbo where the first
6745 * packet is filled with data. Subsequent packets will be
6746 * placed such that any one packet does not span two
6747 * aggregation buffers unless it starts at the beginning of
6748 * an aggregation buffer.
6750 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
6751 (UINT32_C(0x5) << 7)
6753 * GRO/Header-Data Separation:
6754 * Packet will be placed using GRO/HDS where the header
6755 * is in the first packet.
6756 * Payload of each packet will be
6757 * placed such that any one packet does not span two
6758 * aggregation buffers unless it starts at the beginning of
6759 * an aggregation buffer.
6761 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
6762 (UINT32_C(0x6) << 7)
6764 * IOC/Header-Data Separation:
6765 * Packet will be placed using In-Order Completion/HDS where
6766 * the header is in the first packet buffer. Payload of each
6767 * packet will be placed such that each packet starts at the
6768 * beginning of an aggregation buffer.
6770 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
6771 (UINT32_C(0x7) << 7)
6772 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
6773 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
6775 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED \
6778 * This bit is '1' if metadata has been added to the end of the
6779 * packet in host memory. Metadata starts at the first 32B boundary
6780 * after the end of the packet for regular and jumbo placement.
6781 * It starts at the first 32B boundary after the end of the header
6782 * for HDS placement. The length of the metadata is indicated in the
6785 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT \
6788 * This value indicates what the inner packet determined for the
6791 * Indicates that the packet was IP and TCP. This indicates
6792 * that the ip_cs field is valid and that the tcp_udp_cs
6793 * field is valid and contains the TCP checksum.
6794 * This also indicates that the payload_offset field is valid.
6796 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK \
6798 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
6800 * This value is zero for TPA End completions.
6801 * There is no data in the buffer that corresponds to the opaque
6802 * value in this completion.
6806 * This is a copy of the opaque field from the RX BD this completion
6812 * This value is written by the NIC such that it will be different
6813 * for each pass through the completion queue. The even passes
6814 * will write 1. The odd passes will write 0.
6816 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
6817 /* This value is the number of segments in the TPA operation. */
6820 * This is the aggregation ID that the completion is associated
6821 * with. Use this number to correlate the TPA start completion
6822 * with the TPA end completion.
6826 * For non-GRO packets, this value is the
6827 * timestamp delta between earliest and latest timestamp values for
6828 * TPA packet. If packets were not time stamped, then delta will be
6831 * For GRO packets, this field is zero except for the following
6834 * Timestamp present indication. When '0', no Timestamp
6835 * option is in the packet. When '1', then a Timestamp
6836 * option is present in the packet.
6842 * Last 16 bytes of rx_tpa_v2_end_cmpl.
6844 * This TPA completion structure is used on devices where the
6845 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6847 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
6848 struct rx_tpa_v2_end_cmpl_hi {
6850 * This value is the number of duplicate ACKs that have been
6851 * received as part of the TPA operation.
6853 uint16_t tpa_dup_acks;
6855 * This value is the number of duplicate ACKs that have been
6856 * received as part of the TPA operation.
6858 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
6859 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
6861 * This value indicated the offset in bytes from the beginning of
6862 * the packet where the inner payload starts. This value is valid
6863 * for TCP, UDP, FCoE and RoCE packets
6865 uint8_t payload_offset;
6867 * The value is the total number of aggregation buffers that were
6868 * used in the TPA operation. All TPA aggregation buffer completions
6869 * precede the TPA End completion. If the value is zero, then the
6870 * aggregation is completely contained in the buffer space provided
6871 * in the aggregation start completion.
6872 * Note that the field is simply provided as a cross check.
6874 uint8_t tpa_agg_bufs;
6876 * This value is the valid when TPA completion is active. It
6877 * indicates the length of the longest segment of the TPA operation
6878 * for LRO mode and the length of the first segment in GRO mode.
6880 * This value may be used by GRO software to re-construct the original
6881 * packet stream from the TPA packet. This is the length of all
6882 * but the last segment for GRO. In LRO mode this value may be used
6883 * to indicate MSS size to the stack.
6885 uint16_t tpa_seg_len;
6889 * This value is written by the NIC such that it will be different
6890 * for each pass through the completion queue. The even passes
6891 * will write 1. The odd passes will write 0.
6893 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
6894 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
6896 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
6898 * This error indicates that there was some sort of problem with
6899 * the BDs for the packet that was found after part of the
6900 * packet was already placed. The packet should be treated as
6903 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
6905 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
6906 /* No buffer error */
6907 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
6908 (UINT32_C(0x0) << 1)
6910 * This error occurs when there is a fatal HW problem in
6911 * the chip only. It indicates that there were not
6912 * BDs on chip but that there was adequate reservation.
6913 * provided by the TPA block.
6915 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
6916 (UINT32_C(0x2) << 1)
6919 * BDs were not formatted correctly.
6921 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
6922 (UINT32_C(0x3) << 1)
6924 * This error occurs when TPA block was not configured to
6925 * reserve adequate BDs for TPA operations on this RX
6926 * ring. All data for the TPA operation was not placed.
6928 * This error can also be generated when the number of
6929 * segments is not programmed correctly in TPA and the
6930 * 33 total aggregation buffers allowed for the TPA
6931 * operation has been exceeded.
6933 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
6934 (UINT32_C(0x4) << 1)
6937 * There was a bad_format error on the previous operation
6939 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
6940 (UINT32_C(0x5) << 1)
6941 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
6942 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
6945 * This is the opaque value that was completed for the TPA start
6946 * completion that corresponds to this TPA end completion.
6948 uint32_t start_opaque;
6952 * This TPA completion structure is used on devices where the
6953 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
6955 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
6956 struct rx_tpa_v2_abuf_cmpl {
6959 * This field indicates the exact type of the completion.
6960 * By convention, the LSB identifies the length of the
6961 * record in 16B units. Even values indicate 16B
6962 * records. Odd values indicate 32B
6965 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
6966 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
6968 * RX TPA Aggregation Buffer completion :
6969 * Completion of an L2 aggregation buffer in support of
6970 * TPA packet completion. Length = 16B
6972 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
6973 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
6974 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
6976 * This is the length of the data for the packet stored in this
6977 * aggregation buffer identified by the opaque value. This does not
6978 * include the length of any
6979 * data placed in other aggregation BDs or in the packet or buffer
6980 * BDs. This length does not include any space added due to
6981 * hdr_offset register during HDS placement mode.
6985 * This is a copy of the opaque field from the RX BD this aggregation
6986 * buffer corresponds to.
6991 * This value is written by the NIC such that it will be different
6992 * for each pass through the completion queue. The even passes
6993 * will write 1. The odd passes will write 0.
6995 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
6997 * This is the aggregation ID that the completion is associated with. Use
6998 * this number to correlate the TPA agg completion with the TPA start
6999 * completion and the TPA end completion.
7005 /* rx_abuf_cmpl (size:128b/16B) */
7006 struct rx_abuf_cmpl {
7009 * This field indicates the exact type of the completion.
7010 * By convention, the LSB identifies the length of the
7011 * record in 16B units. Even values indicate 16B
7012 * records. Odd values indicate 32B
7015 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
7016 #define RX_ABUF_CMPL_TYPE_SFT 0
7018 * RX Aggregation Buffer completion :
7019 * Completion of an L2 aggregation buffer in support of
7020 * TPA, HDS, or Jumbo packet completion. Length = 16B
7022 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
7023 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
7025 * This is the length of the data for the packet stored in this
7026 * aggregation buffer identified by the opaque value. This does not
7027 * include the length of any
7028 * data placed in other aggregation BDs or in the packet or buffer
7029 * BDs. This length does not include any space added due to
7030 * hdr_offset register during HDS placement mode.
7034 * This is a copy of the opaque field from the RX BD this aggregation
7035 * buffer corresponds to.
7040 * This value is written by the NIC such that it will be different
7041 * for each pass through the completion queue. The even passes
7042 * will write 1. The odd passes will write 0.
7044 #define RX_ABUF_CMPL_V UINT32_C(0x1)
7045 /* unused3 is 32 b */
7049 /* VEE FLUSH Completion Record (16 bytes) */
7050 /* vee_flush (size:128b/16B) */
7052 uint32_t downstream_path_type;
7054 * This field indicates the exact type of the completion.
7055 * By convention, the LSB identifies the length of the
7056 * record in 16B units. Even values indicate 16B
7057 * records. Odd values indicate 32B
7060 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
7061 #define VEE_FLUSH_TYPE_SFT 0
7063 * VEE Flush Completion:
7064 * This completion is inserted manually by the Primate and processed
7065 * by the VEE hardware to ensure that all completions on a VEE
7066 * function have been processed by the VEE hardware before FLR
7067 * process is completed.
7069 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
7070 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
7071 /* downstream_path is 1 b */
7072 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
7073 /* This completion is associated with VEE Transmit */
7074 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
7075 /* This completion is associated with VEE Receive */
7076 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
7077 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
7079 * This is an opaque value that is passed through the completion
7080 * to the VEE handler SW and is used to indicate what VEE VQ or
7081 * function has completed FLR processing.
7086 * This value is written by the NIC such that it will be different
7087 * for each pass through the completion queue. The even passes will
7088 * write 1. The odd passes will write 0.
7090 #define VEE_FLUSH_V UINT32_C(0x1)
7091 /* unused3 is 32 b */
7095 /* eject_cmpl (size:128b/16B) */
7099 * This field indicates the exact type of the completion.
7100 * By convention, the LSB identifies the length of the
7101 * record in 16B units. Even values indicate 16B
7102 * records. Odd values indicate 32B
7105 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
7106 #define EJECT_CMPL_TYPE_SFT 0
7108 * Statistics Ejection Completion:
7109 * Completion of statistics data ejection buffer.
7112 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
7113 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
7114 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7115 #define EJECT_CMPL_FLAGS_SFT 6
7117 * When this bit is '1', it indicates a packet that has an
7118 * error of some type. Type of error is indicated in
7121 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
7123 * This is the length of the statistics data stored in this
7128 * This is a copy of the opaque field from the RX BD this ejection
7129 * buffer corresponds to.
7134 * This value is written by the NIC such that it will be different
7135 * for each pass through the completion queue. The even passes
7136 * will write 1. The odd passes will write 0.
7138 #define EJECT_CMPL_V UINT32_C(0x1)
7139 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7140 #define EJECT_CMPL_ERRORS_SFT 1
7142 * This error indicates that there was some sort of problem with
7143 * the BDs for statistics ejection. The statistics ejection should
7144 * be treated as invalid
7146 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7147 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
7148 /* No buffer error */
7149 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
7150 (UINT32_C(0x0) << 1)
7153 * Statistics did not fit into aggregation buffer provided.
7155 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
7156 (UINT32_C(0x1) << 1)
7159 * BDs were not formatted correctly.
7161 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
7162 (UINT32_C(0x3) << 1)
7165 * There was a bad_format error on the previous operation
7167 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
7168 (UINT32_C(0x5) << 1)
7169 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
7170 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
7171 /* reserved16 is 16 b */
7172 uint16_t reserved16;
7173 /* unused3 is 32 b */
7177 /* hwrm_cmpl (size:128b/16B) */
7181 * This field indicates the exact type of the completion.
7182 * By convention, the LSB identifies the length of the
7183 * record in 16B units. Even values indicate 16B
7184 * records. Odd values indicate 32B
7187 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
7188 #define HWRM_CMPL_TYPE_SFT 0
7190 * HWRM Command Completion:
7191 * Completion of an HWRM command.
7193 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
7194 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
7195 /* This is the sequence_id of the HWRM command that has completed. */
7196 uint16_t sequence_id;
7197 /* unused2 is 32 b */
7201 * This value is written by the NIC such that it will be different
7202 * for each pass through the completion queue. The even passes
7203 * will write 1. The odd passes will write 0.
7205 #define HWRM_CMPL_V UINT32_C(0x1)
7206 /* unused4 is 32 b */
7210 /* hwrm_fwd_req_cmpl (size:128b/16B) */
7211 struct hwrm_fwd_req_cmpl {
7213 * This field indicates the exact type of the completion.
7214 * By convention, the LSB identifies the length of the
7215 * record in 16B units. Even values indicate 16B
7216 * records. Odd values indicate 32B
7219 uint16_t req_len_type;
7221 * This field indicates the exact type of the completion.
7222 * By convention, the LSB identifies the length of the
7223 * record in 16B units. Even values indicate 16B
7224 * records. Odd values indicate 32B
7227 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
7228 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
7229 /* Forwarded HWRM Request */
7230 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
7231 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
7232 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
7233 /* Length of forwarded request in bytes. */
7234 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
7235 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
7237 * Source ID of this request.
7238 * Typically used in forwarding requests and responses.
7239 * 0x0 - 0xFFF8 - Used for function ids
7240 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7244 /* unused1 is 32 b */
7246 /* Address of forwarded request. */
7247 uint32_t req_buf_addr_v[2];
7249 * This value is written by the NIC such that it will be different
7250 * for each pass through the completion queue. The even passes
7251 * will write 1. The odd passes will write 0.
7253 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
7254 /* Address of forwarded request. */
7255 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7256 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
7259 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
7260 struct hwrm_fwd_resp_cmpl {
7263 * This field indicates the exact type of the completion.
7264 * By convention, the LSB identifies the length of the
7265 * record in 16B units. Even values indicate 16B
7266 * records. Odd values indicate 32B
7269 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
7270 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
7271 /* Forwarded HWRM Response */
7272 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
7273 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
7274 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
7276 * Source ID of this response.
7277 * Typically used in forwarding requests and responses.
7278 * 0x0 - 0xFFF8 - Used for function ids
7279 * 0xFFF8 - 0xFFFE - Reserved for internal processors
7283 /* Length of forwarded response in bytes. */
7285 /* unused2 is 16 b */
7287 /* Address of forwarded request. */
7288 uint32_t resp_buf_addr_v[2];
7290 * This value is written by the NIC such that it will be different
7291 * for each pass through the completion queue. The even passes
7292 * will write 1. The odd passes will write 0.
7294 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
7295 /* Address of forwarded request. */
7296 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
7297 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
7300 /* hwrm_async_event_cmpl (size:128b/16B) */
7301 struct hwrm_async_event_cmpl {
7304 * This field indicates the exact type of the completion.
7305 * By convention, the LSB identifies the length of the
7306 * record in 16B units. Even values indicate 16B
7307 * records. Odd values indicate 32B
7310 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
7311 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
7312 /* HWRM Asynchronous Event Information */
7313 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
7314 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
7315 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
7316 /* Identifiers of events. */
7318 /* Link status changed */
7319 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
7321 /* Link MTU changed */
7322 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
7324 /* Link speed changed */
7325 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
7327 /* DCB Configuration changed */
7328 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
7330 /* Port connection not allowed */
7331 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7333 /* Link speed configuration was not allowed */
7334 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7336 /* Link speed configuration change */
7337 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7339 /* Port PHY configuration change */
7340 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
7342 /* Reset notification to clients */
7343 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
7345 /* Master function selection event */
7346 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
7349 * An event signifying that a ring has been disabled by
7352 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG \
7354 /* Function driver unloaded */
7355 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
7357 /* Function driver loaded */
7358 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
7360 /* Function FLR related processing has completed */
7361 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7363 /* PF driver unloaded */
7364 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
7366 /* PF driver loaded */
7367 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
7369 /* VF Function Level Reset (FLR) */
7370 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
7372 /* VF MAC Address Change */
7373 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
7375 /* PF-VF communication channel status change. */
7376 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7378 /* VF Configuration Change */
7379 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
7381 /* LLFC/PFC Configuration Change */
7382 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
7384 /* Default VNIC Configuration Change */
7385 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
7388 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
7391 * A debug notification being posted to the driver. These
7392 * notifications are purely for diagnostic purpose and should not be
7393 * used for functional purpose. The driver is not supposed to act
7394 * on these messages except to log/record it.
7396 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
7399 * An EEM flow cached memory flush for all flows request event being
7400 * posted to the PF driver.
7402 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7405 * An EEM flow cache memory flush completion event being posted to the
7406 * firmware by the PF driver. This is indication that host EEM flush
7407 * has completed by the PF.
7409 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7412 * A tcp flag action change event being posted to the PF or trusted VF
7413 * driver by the firmware. The PF or trusted VF driver should query
7414 * the firmware for the new TCP flag action update after receiving
7417 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7420 * An EEM flow active event being posted to the PF or trusted VF driver
7421 * by the firmware. The PF or trusted VF driver should update the
7422 * flow's aging timer after receiving this async event.
7424 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
7427 * A eem cfg change event being posted to the trusted VF driver by the
7428 * firmware if the parent PF EEM configuration changed.
7430 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
7434 * TFLIB unique default VNIC Configuration Change
7436 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
7440 * TFLIB unique link status changed
7442 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
7445 * An event signifying completion for HWRM_FW_STATE_QUIESCE
7446 * (completion, timeout, or error)
7448 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
7451 * An event signifying a HWRM command is in progress and its
7452 * response will be deferred. This event is used on crypto controllers
7455 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
7458 * An event signifying that a PFC WatchDog configuration
7459 * has changed on any port / cos.
7461 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
7464 * An echo request from the firmware. An echo response is expected by
7467 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \
7469 /* Maximum Registrable event id. */
7470 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \
7473 * A trace log message. This contains firmware trace logs string
7474 * embedded in the asynchronous message. This is an experimental
7475 * event, not meant for production use at this time.
7477 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
7480 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
7482 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
7483 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
7484 /* Event specific data */
7485 uint32_t event_data2;
7488 * This value is written by the NIC such that it will be different
7489 * for each pass through the completion queue. The even passes
7490 * will write 1. The odd passes will write 0.
7492 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
7494 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
7495 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
7496 /* 8-lsb timestamp from POR (100-msec resolution) */
7497 uint8_t timestamp_lo;
7498 /* 16-lsb timestamp from POR (100-msec resolution) */
7499 uint16_t timestamp_hi;
7500 /* Event specific data */
7501 uint32_t event_data1;
7504 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
7505 struct hwrm_async_event_cmpl_link_status_change {
7508 * This field indicates the exact type of the completion.
7509 * By convention, the LSB identifies the length of the
7510 * record in 16B units. Even values indicate 16B
7511 * records. Odd values indicate 32B
7514 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
7516 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
7517 /* HWRM Asynchronous Event Information */
7518 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7520 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
7521 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7522 /* Identifiers of events. */
7524 /* Link status changed */
7525 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
7527 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
7528 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
7529 /* Event specific data */
7530 uint32_t event_data2;
7533 * This value is written by the NIC such that it will be different
7534 * for each pass through the completion queue. The even passes
7535 * will write 1. The odd passes will write 0.
7537 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
7540 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
7542 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
7543 /* 8-lsb timestamp from POR (100-msec resolution) */
7544 uint8_t timestamp_lo;
7545 /* 16-lsb timestamp from POR (100-msec resolution) */
7546 uint16_t timestamp_hi;
7547 /* Event specific data */
7548 uint32_t event_data1;
7549 /* Indicates link status change */
7550 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
7553 * If this bit set to 0, then it indicates that the link
7554 * was up and it went down.
7556 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
7559 * If this bit is set to 1, then it indicates that the link
7560 * was down and it went up.
7562 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
7564 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
7565 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
7566 /* Indicates the physical port this link status change occur */
7567 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
7569 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
7572 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7574 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7576 /* Indicates the physical function this event occurred on. */
7577 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
7579 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
7583 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
7584 struct hwrm_async_event_cmpl_link_mtu_change {
7587 * This field indicates the exact type of the completion.
7588 * By convention, the LSB identifies the length of the
7589 * record in 16B units. Even values indicate 16B
7590 * records. Odd values indicate 32B
7593 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
7595 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
7596 /* HWRM Asynchronous Event Information */
7597 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7599 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
7600 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
7601 /* Identifiers of events. */
7603 /* Link MTU changed */
7604 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
7606 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
7607 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
7608 /* Event specific data */
7609 uint32_t event_data2;
7612 * This value is written by the NIC such that it will be different
7613 * for each pass through the completion queue. The even passes
7614 * will write 1. The odd passes will write 0.
7616 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
7618 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
7620 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
7621 /* 8-lsb timestamp from POR (100-msec resolution) */
7622 uint8_t timestamp_lo;
7623 /* 16-lsb timestamp from POR (100-msec resolution) */
7624 uint16_t timestamp_hi;
7625 /* Event specific data */
7626 uint32_t event_data1;
7627 /* The new MTU of the link in bytes. */
7628 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
7630 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
7633 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
7634 struct hwrm_async_event_cmpl_link_speed_change {
7637 * This field indicates the exact type of the completion.
7638 * By convention, the LSB identifies the length of the
7639 * record in 16B units. Even values indicate 16B
7640 * records. Odd values indicate 32B
7643 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
7645 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
7646 /* HWRM Asynchronous Event Information */
7647 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7649 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
7650 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
7651 /* Identifiers of events. */
7653 /* Link speed changed */
7654 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
7656 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
7657 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
7658 /* Event specific data */
7659 uint32_t event_data2;
7662 * This value is written by the NIC such that it will be different
7663 * for each pass through the completion queue. The even passes
7664 * will write 1. The odd passes will write 0.
7666 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
7669 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
7671 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
7672 /* 8-lsb timestamp from POR (100-msec resolution) */
7673 uint8_t timestamp_lo;
7674 /* 16-lsb timestamp from POR (100-msec resolution) */
7675 uint16_t timestamp_hi;
7676 /* Event specific data */
7677 uint32_t event_data1;
7679 * When this bit is '1', the link was forced to the
7680 * force_link_speed value.
7682 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
7684 /* The new link speed in 100 Mbps units. */
7685 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
7687 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
7689 /* 100Mb link speed */
7690 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
7691 (UINT32_C(0x1) << 1)
7692 /* 1Gb link speed */
7693 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
7694 (UINT32_C(0xa) << 1)
7695 /* 2Gb link speed */
7696 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
7697 (UINT32_C(0x14) << 1)
7698 /* 25Gb link speed */
7699 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
7700 (UINT32_C(0x19) << 1)
7701 /* 10Gb link speed */
7702 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
7703 (UINT32_C(0x64) << 1)
7704 /* 20Mb link speed */
7705 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
7706 (UINT32_C(0xc8) << 1)
7707 /* 25Gb link speed */
7708 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
7709 (UINT32_C(0xfa) << 1)
7710 /* 40Gb link speed */
7711 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
7712 (UINT32_C(0x190) << 1)
7713 /* 50Gb link speed */
7714 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
7715 (UINT32_C(0x1f4) << 1)
7716 /* 100Gb link speed */
7717 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
7718 (UINT32_C(0x3e8) << 1)
7719 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
7720 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
7722 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7723 UINT32_C(0xffff0000)
7724 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7728 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
7729 struct hwrm_async_event_cmpl_dcb_config_change {
7732 * This field indicates the exact type of the completion.
7733 * By convention, the LSB identifies the length of the
7734 * record in 16B units. Even values indicate 16B
7735 * records. Odd values indicate 32B
7738 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
7740 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
7741 /* HWRM Asynchronous Event Information */
7742 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7744 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
7745 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7746 /* Identifiers of events. */
7748 /* DCB Configuration changed */
7749 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
7751 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
7752 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
7753 /* Event specific data */
7754 uint32_t event_data2;
7755 /* ETS configuration change */
7756 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
7758 /* PFC configuration change */
7759 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
7761 /* APP configuration change */
7762 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
7766 * This value is written by the NIC such that it will be different
7767 * for each pass through the completion queue. The even passes
7768 * will write 1. The odd passes will write 0.
7770 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
7773 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
7775 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
7776 /* 8-lsb timestamp from POR (100-msec resolution) */
7777 uint8_t timestamp_lo;
7778 /* 16-lsb timestamp from POR (100-msec resolution) */
7779 uint16_t timestamp_hi;
7780 /* Event specific data */
7781 uint32_t event_data1;
7783 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7785 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7787 /* Priority recommended for RoCE traffic */
7788 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
7790 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
7793 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
7794 (UINT32_C(0xff) << 16)
7795 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
7796 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
7797 /* Priority recommended for L2 traffic */
7798 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
7799 UINT32_C(0xff000000)
7800 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
7803 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
7804 (UINT32_C(0xff) << 24)
7805 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
7806 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
7809 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
7810 struct hwrm_async_event_cmpl_port_conn_not_allowed {
7813 * This field indicates the exact type of the completion.
7814 * By convention, the LSB identifies the length of the
7815 * record in 16B units. Even values indicate 16B
7816 * records. Odd values indicate 32B
7819 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
7821 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
7823 /* HWRM Asynchronous Event Information */
7824 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7826 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
7827 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7828 /* Identifiers of events. */
7830 /* Port connection not allowed */
7831 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
7833 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
7834 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
7835 /* Event specific data */
7836 uint32_t event_data2;
7839 * This value is written by the NIC such that it will be different
7840 * for each pass through the completion queue. The even passes
7841 * will write 1. The odd passes will write 0.
7843 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
7846 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
7848 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
7849 /* 8-lsb timestamp from POR (100-msec resolution) */
7850 uint8_t timestamp_lo;
7851 /* 16-lsb timestamp from POR (100-msec resolution) */
7852 uint16_t timestamp_hi;
7853 /* Event specific data */
7854 uint32_t event_data1;
7856 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7858 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7861 * This value indicates the current port level enforcement policy
7862 * for the optics module when there is an optical module mismatch
7863 * and port is not connected.
7865 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
7867 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
7869 /* No enforcement */
7870 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
7871 (UINT32_C(0x0) << 16)
7872 /* Disable Transmit side Laser. */
7873 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
7874 (UINT32_C(0x1) << 16)
7875 /* Raise a warning message. */
7876 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
7877 (UINT32_C(0x2) << 16)
7878 /* Power down the module. */
7879 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
7880 (UINT32_C(0x3) << 16)
7881 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
7882 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
7885 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
7886 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
7889 * This field indicates the exact type of the completion.
7890 * By convention, the LSB identifies the length of the
7891 * record in 16B units. Even values indicate 16B
7892 * records. Odd values indicate 32B
7895 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
7897 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
7899 /* HWRM Asynchronous Event Information */
7900 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
7902 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
7903 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
7904 /* Identifiers of events. */
7906 /* Link speed configuration was not allowed */
7907 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
7909 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
7910 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
7911 /* Event specific data */
7912 uint32_t event_data2;
7915 * This value is written by the NIC such that it will be different
7916 * for each pass through the completion queue. The even passes
7917 * will write 1. The odd passes will write 0.
7919 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
7922 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
7924 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
7925 /* 8-lsb timestamp from POR (100-msec resolution) */
7926 uint8_t timestamp_lo;
7927 /* 16-lsb timestamp from POR (100-msec resolution) */
7928 uint16_t timestamp_hi;
7929 /* Event specific data */
7930 uint32_t event_data1;
7932 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
7934 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
7938 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
7939 struct hwrm_async_event_cmpl_link_speed_cfg_change {
7942 * This field indicates the exact type of the completion.
7943 * By convention, the LSB identifies the length of the
7944 * record in 16B units. Even values indicate 16B
7945 * records. Odd values indicate 32B
7948 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
7950 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
7952 /* HWRM Asynchronous Event Information */
7953 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7955 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
7956 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7957 /* Identifiers of events. */
7959 /* Link speed configuration change */
7960 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
7962 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
7963 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
7964 /* Event specific data */
7965 uint32_t event_data2;
7968 * This value is written by the NIC such that it will be different
7969 * for each pass through the completion queue. The even passes
7970 * will write 1. The odd passes will write 0.
7972 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
7975 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
7977 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
7978 /* 8-lsb timestamp from POR (100-msec resolution) */
7979 uint8_t timestamp_lo;
7980 /* 16-lsb timestamp from POR (100-msec resolution) */
7981 uint16_t timestamp_hi;
7982 /* Event specific data */
7983 uint32_t event_data1;
7985 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7987 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7990 * If set to 1, it indicates that the supported link speeds
7991 * configuration on the port has changed.
7992 * If set to 0, then there is no change in supported link speeds
7995 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
7998 * If set to 1, it indicates that the link speed configuration
7999 * on the port has become illegal or invalid.
8000 * If set to 0, then the link speed configuration on the port is
8003 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
8007 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
8008 struct hwrm_async_event_cmpl_port_phy_cfg_change {
8011 * This field indicates the exact type of the completion.
8012 * By convention, the LSB identifies the length of the
8013 * record in 16B units. Even values indicate 16B
8014 * records. Odd values indicate 32B
8017 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
8019 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
8021 /* HWRM Asynchronous Event Information */
8022 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8024 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
8025 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8026 /* Identifiers of events. */
8028 /* Port PHY configuration change */
8029 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
8031 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
8032 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
8033 /* Event specific data */
8034 uint32_t event_data2;
8037 * This value is written by the NIC such that it will be different
8038 * for each pass through the completion queue. The even passes
8039 * will write 1. The odd passes will write 0.
8041 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
8044 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
8046 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
8047 /* 8-lsb timestamp from POR (100-msec resolution) */
8048 uint8_t timestamp_lo;
8049 /* 16-lsb timestamp from POR (100-msec resolution) */
8050 uint16_t timestamp_hi;
8051 /* Event specific data */
8052 uint32_t event_data1;
8054 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8056 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8059 * If set to 1, it indicates that the FEC
8060 * configuration on the port has changed.
8061 * If set to 0, then there is no change in FEC configuration.
8063 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
8066 * If set to 1, it indicates that the EEE configuration
8067 * on the port has changed.
8068 * If set to 0, then there is no change in EEE configuration
8071 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
8074 * If set to 1, it indicates that the pause configuration
8075 * on the PHY has changed.
8076 * If set to 0, then there is no change in the pause
8077 * configuration on the PHY.
8079 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
8083 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
8084 struct hwrm_async_event_cmpl_reset_notify {
8087 * This field indicates the exact type of the completion.
8088 * By convention, the LSB identifies the length of the
8089 * record in 16B units. Even values indicate 16B
8090 * records. Odd values indicate 32B
8093 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
8095 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
8096 /* HWRM Asynchronous Event Information */
8097 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
8099 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
8100 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
8101 /* Identifiers of events. */
8103 /* Notify clients of imminent reset. */
8104 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
8106 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
8107 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
8108 /* Event specific data. The data is for internal debug use only. */
8109 uint32_t event_data2;
8111 * These bits indicate the status as being reported by the firmware.
8112 * This value is exactly the same as status code in fw_status register.
8113 * If the status code is equal to 0x8000, then the reset is initiated
8114 * by the Host using the FW_RESET command when the FW is in a healthy
8115 * state. If the status code is not equal to 0x8000, then the reset is
8116 * initiated by the FW to recover from the error or FATAL state.
8118 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \
8120 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \
8124 * This value is written by the NIC such that it will be different
8125 * for each pass through the completion queue. The even passes
8126 * will write 1. The odd passes will write 0.
8128 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
8130 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
8131 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
8133 * 8-lsb timestamp (100-msec resolution)
8134 * The Minimum time required for the Firmware readiness after sending this
8135 * notification to the driver instances.
8137 uint8_t timestamp_lo;
8139 * 16-lsb timestamp (100-msec resolution)
8140 * The Maximum Firmware Reset bail out value in the order of 100
8141 * milli seconds. The driver instances will use this value to re-initiate the
8142 * registration process again if the core firmware didn’t set the ready
8145 uint16_t timestamp_hi;
8146 /* Event specific data */
8147 uint32_t event_data1;
8148 /* Indicates driver action requested */
8149 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
8151 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
8154 * If set to 1, it indicates that the l2 client should
8155 * stop sending in band traffic to Nitro.
8156 * if set to 0, there is no change in L2 client behavior.
8158 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
8161 * If set to 1, it indicates that the L2 client should
8162 * bring down the interface.
8163 * If set to 0, then there is no change in L2 client behavior.
8165 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
8167 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
8168 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
8169 /* Indicates reason for reset. */
8170 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
8172 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
8174 /* A management client has requested reset. */
8175 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
8176 (UINT32_C(0x1) << 8)
8177 /* A fatal firmware exception has occurred. */
8178 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
8179 (UINT32_C(0x2) << 8)
8180 /* A non-fatal firmware exception has occurred. */
8181 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
8182 (UINT32_C(0x3) << 8)
8184 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \
8185 (UINT32_C(0x4) << 8)
8186 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
8187 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET
8189 * Minimum time before driver should attempt access - units 100ms ticks.
8192 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
8193 UINT32_C(0xffff0000)
8194 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
8198 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
8199 struct hwrm_async_event_cmpl_error_recovery {
8202 * This field indicates the exact type of the completion.
8203 * By convention, the LSB identifies the length of the
8204 * record in 16B units. Even values indicate 16B
8205 * records. Odd values indicate 32B
8208 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
8210 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
8211 /* HWRM Asynchronous Event Information */
8212 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
8214 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
8215 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
8216 /* Identifiers of events. */
8219 * This async notification message can be used for selecting or
8220 * deselecting master function for error recovery,
8221 * and to communicate to all the functions whether error recovery
8222 * was enabled/disabled.
8224 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
8226 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
8227 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
8228 /* Event specific data */
8229 uint32_t event_data2;
8232 * This value is written by the NIC such that it will be different
8233 * for each pass through the completion queue. The even passes
8234 * will write 1. The odd passes will write 0.
8236 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
8238 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
8239 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
8240 /* 8-lsb timestamp (100-msec resolution) */
8241 uint8_t timestamp_lo;
8242 /* 16-lsb timestamp (100-msec resolution) */
8243 uint16_t timestamp_hi;
8244 /* Event specific data */
8245 uint32_t event_data1;
8246 /* Indicates driver action requested */
8247 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
8249 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
8252 * If set to 1, this function is selected as Master function.
8253 * This function has responsibility to do 'chip reset' when it
8254 * detects a fatal error. If set to 0, master function functionality
8255 * is disabled on this function.
8257 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
8260 * If set to 1, error recovery is enabled.
8261 * If set to 0, error recovery is disabled.
8263 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
8267 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
8268 struct hwrm_async_event_cmpl_ring_monitor_msg {
8271 * This field indicates the exact type of the completion.
8272 * By convention, the LSB identifies the length of the
8273 * record in 16B units. Even values indicate 16B
8274 * records. Odd values indicate 32B
8277 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK \
8279 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
8280 /* HWRM Asynchronous Event Information */
8281 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT \
8283 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST \
8284 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
8285 /* Identifiers of events. */
8287 /* Ring Monitor Message. */
8288 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG \
8290 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST \
8291 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
8292 /* Event specific data */
8293 uint32_t event_data2;
8294 /* Type of Ring disabled. */
8295 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK \
8297 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT \
8299 /* tx ring disabled. */
8300 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX \
8302 /* rx ring disabled. */
8303 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX \
8305 /* cmpl ring disabled. */
8306 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL \
8308 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST \
8309 HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
8312 * This value is written by the NIC such that it will be different
8313 * for each pass through the completion queue. The even passes
8314 * will write 1. The odd passes will write 0.
8316 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
8318 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK \
8320 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
8321 /* 8-lsb timestamp from POR (100-msec resolution) */
8322 uint8_t timestamp_lo;
8323 /* 16-lsb timestamp from POR (100-msec resolution) */
8324 uint16_t timestamp_hi;
8326 * Event specific data. If ring_type_disabled indicates a tx,rx or cmpl
8327 * then this field will indicate the ring id.
8329 uint32_t event_data1;
8332 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
8333 struct hwrm_async_event_cmpl_func_drvr_unload {
8336 * This field indicates the exact type of the completion.
8337 * By convention, the LSB identifies the length of the
8338 * record in 16B units. Even values indicate 16B
8339 * records. Odd values indicate 32B
8342 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
8344 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
8345 /* HWRM Asynchronous Event Information */
8346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8348 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
8349 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8350 /* Identifiers of events. */
8352 /* Function driver unloaded */
8353 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
8355 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
8356 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
8357 /* Event specific data */
8358 uint32_t event_data2;
8361 * This value is written by the NIC such that it will be different
8362 * for each pass through the completion queue. The even passes
8363 * will write 1. The odd passes will write 0.
8365 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
8367 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
8369 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
8370 /* 8-lsb timestamp from POR (100-msec resolution) */
8371 uint8_t timestamp_lo;
8372 /* 16-lsb timestamp from POR (100-msec resolution) */
8373 uint16_t timestamp_hi;
8374 /* Event specific data */
8375 uint32_t event_data1;
8377 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8379 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
8383 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
8384 struct hwrm_async_event_cmpl_func_drvr_load {
8387 * This field indicates the exact type of the completion.
8388 * By convention, the LSB identifies the length of the
8389 * record in 16B units. Even values indicate 16B
8390 * records. Odd values indicate 32B
8393 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
8395 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
8396 /* HWRM Asynchronous Event Information */
8397 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8399 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
8400 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8401 /* Identifiers of events. */
8403 /* Function driver loaded */
8404 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
8406 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
8407 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
8408 /* Event specific data */
8409 uint32_t event_data2;
8412 * This value is written by the NIC such that it will be different
8413 * for each pass through the completion queue. The even passes
8414 * will write 1. The odd passes will write 0.
8416 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
8418 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8419 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
8420 /* 8-lsb timestamp from POR (100-msec resolution) */
8421 uint8_t timestamp_lo;
8422 /* 16-lsb timestamp from POR (100-msec resolution) */
8423 uint16_t timestamp_hi;
8424 /* Event specific data */
8425 uint32_t event_data1;
8427 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8429 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8432 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
8433 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
8436 * This field indicates the exact type of the completion.
8437 * By convention, the LSB identifies the length of the
8438 * record in 16B units. Even values indicate 16B
8439 * records. Odd values indicate 32B
8442 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
8444 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
8446 /* HWRM Asynchronous Event Information */
8447 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
8449 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
8450 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
8451 /* Identifiers of events. */
8453 /* Function FLR related processing has completed */
8454 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
8456 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
8457 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
8458 /* Event specific data */
8459 uint32_t event_data2;
8462 * This value is written by the NIC such that it will be different
8463 * for each pass through the completion queue. The even passes
8464 * will write 1. The odd passes will write 0.
8466 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
8469 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
8471 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
8472 /* 8-lsb timestamp from POR (100-msec resolution) */
8473 uint8_t timestamp_lo;
8474 /* 16-lsb timestamp from POR (100-msec resolution) */
8475 uint16_t timestamp_hi;
8476 /* Event specific data */
8477 uint32_t event_data1;
8479 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
8481 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
8485 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
8486 struct hwrm_async_event_cmpl_pf_drvr_unload {
8489 * This field indicates the exact type of the completion.
8490 * By convention, the LSB identifies the length of the
8491 * record in 16B units. Even values indicate 16B
8492 * records. Odd values indicate 32B
8495 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
8497 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
8498 /* HWRM Asynchronous Event Information */
8499 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
8501 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
8502 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
8503 /* Identifiers of events. */
8505 /* PF driver unloaded */
8506 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
8508 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
8509 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
8510 /* Event specific data */
8511 uint32_t event_data2;
8514 * This value is written by the NIC such that it will be different
8515 * for each pass through the completion queue. The even passes
8516 * will write 1. The odd passes will write 0.
8518 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
8520 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
8521 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
8522 /* 8-lsb timestamp from POR (100-msec resolution) */
8523 uint8_t timestamp_lo;
8524 /* 16-lsb timestamp from POR (100-msec resolution) */
8525 uint16_t timestamp_hi;
8526 /* Event specific data */
8527 uint32_t event_data1;
8529 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
8531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
8532 /* Indicates the physical port this pf belongs to */
8533 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
8535 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
8538 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
8539 struct hwrm_async_event_cmpl_pf_drvr_load {
8542 * This field indicates the exact type of the completion.
8543 * By convention, the LSB identifies the length of the
8544 * record in 16B units. Even values indicate 16B
8545 * records. Odd values indicate 32B
8548 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
8550 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
8551 /* HWRM Asynchronous Event Information */
8552 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
8554 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
8555 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
8556 /* Identifiers of events. */
8558 /* PF driver loaded */
8559 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
8561 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
8562 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
8563 /* Event specific data */
8564 uint32_t event_data2;
8567 * This value is written by the NIC such that it will be different
8568 * for each pass through the completion queue. The even passes
8569 * will write 1. The odd passes will write 0.
8571 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
8573 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
8574 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
8575 /* 8-lsb timestamp from POR (100-msec resolution) */
8576 uint8_t timestamp_lo;
8577 /* 16-lsb timestamp from POR (100-msec resolution) */
8578 uint16_t timestamp_hi;
8579 /* Event specific data */
8580 uint32_t event_data1;
8582 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
8584 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
8585 /* Indicates the physical port this pf belongs to */
8586 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
8588 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
8591 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
8592 struct hwrm_async_event_cmpl_vf_flr {
8595 * This field indicates the exact type of the completion.
8596 * By convention, the LSB identifies the length of the
8597 * record in 16B units. Even values indicate 16B
8598 * records. Odd values indicate 32B
8601 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
8603 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
8604 /* HWRM Asynchronous Event Information */
8605 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
8607 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
8608 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
8609 /* Identifiers of events. */
8611 /* VF Function Level Reset (FLR) */
8612 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
8613 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
8614 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
8615 /* Event specific data */
8616 uint32_t event_data2;
8619 * This value is written by the NIC such that it will be different
8620 * for each pass through the completion queue. The even passes
8621 * will write 1. The odd passes will write 0.
8623 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
8625 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
8626 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
8627 /* 8-lsb timestamp from POR (100-msec resolution) */
8628 uint8_t timestamp_lo;
8629 /* 16-lsb timestamp from POR (100-msec resolution) */
8630 uint16_t timestamp_hi;
8631 /* Event specific data */
8632 uint32_t event_data1;
8634 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
8636 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
8637 /* Indicates the physical function this event occurred on. */
8638 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
8640 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
8643 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
8644 struct hwrm_async_event_cmpl_vf_mac_addr_change {
8647 * This field indicates the exact type of the completion.
8648 * By convention, the LSB identifies the length of the
8649 * record in 16B units. Even values indicate 16B
8650 * records. Odd values indicate 32B
8653 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
8655 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
8656 /* HWRM Asynchronous Event Information */
8657 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8659 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
8660 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
8661 /* Identifiers of events. */
8663 /* VF MAC Address Change */
8664 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
8666 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
8667 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
8668 /* Event specific data */
8669 uint32_t event_data2;
8672 * This value is written by the NIC such that it will be different
8673 * for each pass through the completion queue. The even passes
8674 * will write 1. The odd passes will write 0.
8676 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
8679 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
8681 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
8682 /* 8-lsb timestamp from POR (100-msec resolution) */
8683 uint8_t timestamp_lo;
8684 /* 16-lsb timestamp from POR (100-msec resolution) */
8685 uint16_t timestamp_hi;
8686 /* Event specific data */
8687 uint32_t event_data1;
8689 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
8691 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
8695 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
8696 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
8699 * This field indicates the exact type of the completion.
8700 * By convention, the LSB identifies the length of the
8701 * record in 16B units. Even values indicate 16B
8702 * records. Odd values indicate 32B
8705 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
8707 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
8709 /* HWRM Asynchronous Event Information */
8710 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8712 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
8713 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
8714 /* Identifiers of events. */
8716 /* PF-VF communication channel status change. */
8717 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
8719 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
8720 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
8721 /* Event specific data */
8722 uint32_t event_data2;
8725 * This value is written by the NIC such that it will be different
8726 * for each pass through the completion queue. The even passes
8727 * will write 1. The odd passes will write 0.
8729 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
8732 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
8734 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
8735 /* 8-lsb timestamp from POR (100-msec resolution) */
8736 uint8_t timestamp_lo;
8737 /* 16-lsb timestamp from POR (100-msec resolution) */
8738 uint16_t timestamp_hi;
8739 /* Event specific data */
8740 uint32_t event_data1;
8742 * If this bit is set to 1, then it indicates that the PF-VF
8743 * communication was lost and it is established.
8744 * If this bit set to 0, then it indicates that the PF-VF
8745 * communication was established and it is lost.
8747 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
8751 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
8752 struct hwrm_async_event_cmpl_vf_cfg_change {
8755 * This field indicates the exact type of the completion.
8756 * By convention, the LSB identifies the length of the
8757 * record in 16B units. Even values indicate 16B
8758 * records. Odd values indicate 32B
8761 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
8763 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
8764 /* HWRM Asynchronous Event Information */
8765 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8767 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
8768 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8769 /* Identifiers of events. */
8771 /* VF Configuration Change */
8772 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
8774 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
8775 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
8776 /* Event specific data */
8777 uint32_t event_data2;
8780 * This value is written by the NIC such that it will be different
8781 * for each pass through the completion queue. The even passes
8782 * will write 1. The odd passes will write 0.
8784 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
8786 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
8787 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
8788 /* 8-lsb timestamp from POR (100-msec resolution) */
8789 uint8_t timestamp_lo;
8790 /* 16-lsb timestamp from POR (100-msec resolution) */
8791 uint16_t timestamp_hi;
8793 * Each flag provided in this field indicates a specific VF
8794 * configuration change. At least one of these flags shall be set to 1
8795 * when an asynchronous event completion of this type is provided
8798 uint32_t event_data1;
8800 * If this bit is set to 1, then the value of MTU
8801 * was changed on this VF.
8802 * If set to 0, then this bit should be ignored.
8804 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
8807 * If this bit is set to 1, then the value of MRU
8808 * was changed on this VF.
8809 * If set to 0, then this bit should be ignored.
8811 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
8814 * If this bit is set to 1, then the value of default MAC
8815 * address was changed on this VF.
8816 * If set to 0, then this bit should be ignored.
8818 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
8821 * If this bit is set to 1, then the value of default VLAN
8822 * was changed on this VF.
8823 * If set to 0, then this bit should be ignored.
8825 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
8828 * If this bit is set to 1, then the value of trusted VF enable
8829 * was changed on this VF.
8830 * If set to 0, then this bit should be ignored.
8832 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
8836 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
8837 struct hwrm_async_event_cmpl_llfc_pfc_change {
8840 * This field indicates the exact type of the completion.
8841 * By convention, the LSB identifies the length of the
8842 * record in 16B units. Even values indicate 16B
8843 * records. Odd values indicate 32B
8846 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
8848 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
8849 /* HWRM Asynchronous Event Information */
8850 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8852 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
8853 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8854 /* unused1 is 10 b */
8855 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
8857 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
8858 /* Identifiers of events. */
8860 /* LLFC/PFC Configuration Change */
8861 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
8863 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
8864 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
8865 /* Event specific data */
8866 uint32_t event_data2;
8869 * This value is written by the NIC such that it will be different
8870 * for each pass through the completion queue. The even passes
8871 * will write 1. The odd passes will write 0.
8873 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
8875 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
8877 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
8878 /* 8-lsb timestamp from POR (100-msec resolution) */
8879 uint8_t timestamp_lo;
8880 /* 16-lsb timestamp from POR (100-msec resolution) */
8881 uint16_t timestamp_hi;
8882 /* Event specific data */
8883 uint32_t event_data1;
8884 /* Indicates llfc pfc status change */
8885 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
8887 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
8890 * If this field set to 1, then it indicates that llfc is
8893 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
8896 * If this field is set to 2, then it indicates that pfc
8899 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
8901 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
8902 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
8903 /* Indicates the physical port this llfc pfc change occur */
8904 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
8906 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
8909 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8911 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8915 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
8916 struct hwrm_async_event_cmpl_default_vnic_change {
8919 * This field indicates the exact type of the completion.
8920 * By convention, the LSB identifies the length of the
8921 * record in 16B units. Even values indicate 16B
8922 * records. Odd values indicate 32B
8925 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
8927 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
8929 /* HWRM Asynchronous Event Information */
8930 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8932 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
8933 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
8934 /* unused1 is 10 b */
8935 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
8937 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
8939 /* Identifiers of events. */
8941 /* Notification of a default vnic allocation or free */
8942 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
8944 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
8945 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
8946 /* Event specific data */
8947 uint32_t event_data2;
8950 * This value is written by the NIC such that it will be different
8951 * for each pass through the completion queue. The even passes
8952 * will write 1. The odd passes will write 0.
8954 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
8957 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
8959 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
8960 /* 8-lsb timestamp from POR (100-msec resolution) */
8961 uint8_t timestamp_lo;
8962 /* 16-lsb timestamp from POR (100-msec resolution) */
8963 uint16_t timestamp_hi;
8964 /* Event specific data */
8965 uint32_t event_data1;
8966 /* Indicates default vnic configuration change */
8967 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
8969 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
8972 * If this field is set to 1, then it indicates that
8973 * a default VNIC has been allocate.
8975 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
8978 * If this field is set to 2, then it indicates that
8979 * a default VNIC has been freed.
8981 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
8983 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
8984 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
8985 /* Indicates the physical function this event occurred on. */
8986 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
8988 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
8990 /* Indicates the virtual function this event occurred on */
8991 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
8993 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
8997 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
8998 struct hwrm_async_event_cmpl_hw_flow_aged {
9001 * This field indicates the exact type of the completion.
9002 * By convention, the LSB identifies the length of the
9003 * record in 16B units. Even values indicate 16B
9004 * records. Odd values indicate 32B
9007 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
9009 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
9010 /* HWRM Asynchronous Event Information */
9011 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
9013 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
9014 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
9015 /* Identifiers of events. */
9017 /* Notification of a hw flow aged */
9018 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
9020 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
9021 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
9022 /* Event specific data */
9023 uint32_t event_data2;
9026 * This value is written by the NIC such that it will be different
9027 * for each pass through the completion queue. The even passes
9028 * will write 1. The odd passes will write 0.
9030 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
9032 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
9033 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
9034 /* 8-lsb timestamp from POR (100-msec resolution) */
9035 uint8_t timestamp_lo;
9036 /* 16-lsb timestamp from POR (100-msec resolution) */
9037 uint16_t timestamp_hi;
9038 /* Event specific data */
9039 uint32_t event_data1;
9040 /* Indicates flow ID this event occurred on. */
9041 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
9042 UINT32_C(0x7fffffff)
9043 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
9045 /* Indicates flow direction this event occurred on. */
9046 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
9047 UINT32_C(0x80000000)
9049 * If this bit set to 0, then it indicates that the aged
9050 * event was rx flow.
9052 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
9053 (UINT32_C(0x0) << 31)
9055 * If this bit is set to 1, then it indicates that the aged
9056 * event was tx flow.
9058 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
9059 (UINT32_C(0x1) << 31)
9060 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
9061 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
9064 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
9065 struct hwrm_async_event_cmpl_eem_cache_flush_req {
9068 * This field indicates the exact type of the completion.
9069 * By convention, the LSB identifies the length of the
9070 * record in 16B units. Even values indicate 16B
9071 * records. Odd values indicate 32B
9074 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
9076 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
9078 /* HWRM Asynchronous Event Information */
9079 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
9081 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
9082 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
9083 /* Identifiers of events. */
9085 /* Notification of a eem_cache_flush request */
9086 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
9088 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
9089 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
9090 /* Event specific data */
9091 uint32_t event_data2;
9094 * This value is written by the NIC such that it will be different
9095 * for each pass through the completion queue. The even passes
9096 * will write 1. The odd passes will write 0.
9098 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
9101 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
9103 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
9104 /* 8-lsb timestamp from POR (100-msec resolution) */
9105 uint8_t timestamp_lo;
9106 /* 16-lsb timestamp from POR (100-msec resolution) */
9107 uint16_t timestamp_hi;
9108 /* Event specific data */
9109 uint32_t event_data1;
9112 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
9113 struct hwrm_async_event_cmpl_eem_cache_flush_done {
9116 * This field indicates the exact type of the completion.
9117 * By convention, the LSB identifies the length of the
9118 * record in 16B units. Even values indicate 16B
9119 * records. Odd values indicate 32B
9122 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
9124 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
9126 /* HWRM Asynchronous Event Information */
9127 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
9129 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
9130 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
9131 /* Identifiers of events. */
9134 * Notification of a host eem_cache_flush has completed. This event
9135 * is generated by the host driver.
9137 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
9139 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
9140 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
9141 /* Event specific data */
9142 uint32_t event_data2;
9145 * This value is written by the NIC such that it will be different
9146 * for each pass through the completion queue. The even passes
9147 * will write 1. The odd passes will write 0.
9149 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
9152 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
9154 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
9155 /* 8-lsb timestamp from POR (100-msec resolution) */
9156 uint8_t timestamp_lo;
9157 /* 16-lsb timestamp from POR (100-msec resolution) */
9158 uint16_t timestamp_hi;
9159 /* Event specific data */
9160 uint32_t event_data1;
9161 /* Indicates function ID that this event occurred on. */
9162 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
9164 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
9168 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
9169 struct hwrm_async_event_cmpl_tcp_flag_action_change {
9172 * This field indicates the exact type of the completion.
9173 * By convention, the LSB identifies the length of the
9174 * record in 16B units. Even values indicate 16B
9175 * records. Odd values indicate 32B
9178 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
9180 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
9182 /* HWRM Asynchronous Event Information */
9183 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9185 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
9186 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
9187 /* Identifiers of events. */
9189 /* Notification of tcp flag action change */
9190 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
9192 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
9193 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
9194 /* Event specific data */
9195 uint32_t event_data2;
9198 * This value is written by the NIC such that it will be different
9199 * for each pass through the completion queue. The even passes
9200 * will write 1. The odd passes will write 0.
9202 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
9205 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
9207 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
9208 /* 8-lsb timestamp from POR (100-msec resolution) */
9209 uint8_t timestamp_lo;
9210 /* 16-lsb timestamp from POR (100-msec resolution) */
9211 uint16_t timestamp_hi;
9212 /* Event specific data */
9213 uint32_t event_data1;
9216 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
9217 struct hwrm_async_event_cmpl_eem_flow_active {
9220 * This field indicates the exact type of the completion.
9221 * By convention, the LSB identifies the length of the
9222 * record in 16B units. Even values indicate 16B
9223 * records. Odd values indicate 32B
9226 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
9228 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
9229 /* HWRM Asynchronous Event Information */
9230 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
9232 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
9233 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
9234 /* Identifiers of events. */
9236 /* Notification of an active eem flow */
9237 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
9239 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
9240 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
9241 /* Event specific data */
9242 uint32_t event_data2;
9243 /* Indicates the 2nd global id this event occurred on. */
9244 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
9245 UINT32_C(0x3fffffff)
9246 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
9249 * Indicates flow direction of the flow identified by
9252 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
9253 UINT32_C(0x40000000)
9254 /* If this bit is set to 0, then it indicates that this rx flow. */
9255 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
9256 (UINT32_C(0x0) << 30)
9257 /* If this bit is set to 1, then it indicates that this tx flow. */
9258 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
9259 (UINT32_C(0x1) << 30)
9260 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
9261 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
9264 * This value is written by the NIC such that it will be different
9265 * for each pass through the completion queue. The even passes
9266 * will write 1. The odd passes will write 0.
9268 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
9270 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
9272 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
9273 /* 8-lsb timestamp from POR (100-msec resolution) */
9274 uint8_t timestamp_lo;
9275 /* 16-lsb timestamp from POR (100-msec resolution) */
9276 uint16_t timestamp_hi;
9277 /* Event specific data */
9278 uint32_t event_data1;
9279 /* Indicates the 1st global id this event occurred on. */
9280 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
9281 UINT32_C(0x3fffffff)
9282 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
9285 * Indicates flow direction of the flow identified by the
9288 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
9289 UINT32_C(0x40000000)
9290 /* If this bit is set to 0, then it indicates that this is rx flow. */
9291 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
9292 (UINT32_C(0x0) << 30)
9293 /* If this bit is set to 1, then it indicates that this is tx flow. */
9294 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
9295 (UINT32_C(0x1) << 30)
9296 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
9297 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
9299 * Indicates EEM flow aging mode this event occurred on. If
9300 * this bit is set to 0, the event_data1 is the EEM global
9301 * ID. If this bit is set to 1, the event_data1 is the number
9302 * of global ID in the context memory.
9304 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
9305 UINT32_C(0x80000000)
9306 /* EEM flow aging mode 0. */
9307 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
9308 (UINT32_C(0x0) << 31)
9309 /* EEM flow aging mode 1. */
9310 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
9311 (UINT32_C(0x1) << 31)
9312 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
9313 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
9316 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
9317 struct hwrm_async_event_cmpl_eem_cfg_change {
9320 * This field indicates the exact type of the completion.
9321 * By convention, the LSB identifies the length of the
9322 * record in 16B units. Even values indicate 16B
9323 * records. Odd values indicate 32B
9326 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
9328 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
9329 /* HWRM Asynchronous Event Information */
9330 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9332 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
9333 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9334 /* Identifiers of events. */
9336 /* Notification of EEM configuration change */
9337 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
9339 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
9340 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
9341 /* Event specific data */
9342 uint32_t event_data2;
9345 * This value is written by the NIC such that it will be different
9346 * for each pass through the completion queue. The even passes
9347 * will write 1. The odd passes will write 0.
9349 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
9351 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9352 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
9353 /* 8-lsb timestamp from POR (100-msec resolution) */
9354 uint8_t timestamp_lo;
9355 /* 16-lsb timestamp from POR (100-msec resolution) */
9356 uint16_t timestamp_hi;
9357 /* Event specific data */
9358 uint32_t event_data1;
9360 * Value of 1 to indicate EEM TX configuration is enabled. Value of
9361 * 0 to indicate the EEM TX configuration is disabled.
9363 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
9366 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
9367 * to indicate the EEM RX configuration is disabled.
9369 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
9373 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
9374 struct hwrm_async_event_cmpl_quiesce_done {
9377 * This field indicates the exact type of the completion.
9378 * By convention, the LSB identifies the length of the
9379 * record in 16B units. Even values indicate 16B
9380 * records. Odd values indicate 32B
9383 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
9385 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
9386 /* HWRM Asynchronous Event Information */
9387 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
9389 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
9390 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
9391 /* Identifiers of events. */
9393 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
9394 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
9396 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
9397 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
9398 /* Event specific data */
9399 uint32_t event_data2;
9400 /* Status of HWRM_FW_STATE_QUIESCE completion */
9401 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
9403 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
9406 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9407 * completed successfully.
9409 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
9412 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
9415 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
9418 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
9419 * encountered an error.
9421 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
9423 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
9424 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
9426 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
9428 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
9431 * Additional information about internal hardware state related to
9432 * idle/quiesce state. QUIESCE may succeed per quiesce_status
9433 * regardless of idle_state_flags. If QUIESCE fails, the host may
9434 * inspect idle_state_flags to determine whether a retry is warranted.
9436 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
9438 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
9441 * Failure to quiesce is caused by host not updating the NQ consumer
9444 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
9446 /* Flag 1 indicating partial non-idle state. */
9447 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
9449 /* Flag 2 indicating partial non-idle state. */
9450 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
9452 /* Flag 3 indicating partial non-idle state. */
9453 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
9457 * This value is written by the NIC such that it will be different
9458 * for each pass through the completion queue. The even passes
9459 * will write 1. The odd passes will write 0.
9461 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
9463 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
9464 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
9465 /* 8-lsb timestamp from POR (100-msec resolution) */
9466 uint8_t timestamp_lo;
9467 /* 16-lsb timestamp from POR (100-msec resolution) */
9468 uint16_t timestamp_hi;
9469 /* Event specific data */
9470 uint32_t event_data1;
9471 /* Time stamp for error event */
9472 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
9476 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
9477 struct hwrm_async_event_cmpl_deferred_response {
9480 * This field indicates the exact type of the completion.
9481 * By convention, the LSB identifies the length of the
9482 * record in 16B units. Even values indicate 16B
9483 * records. Odd values indicate 32B
9486 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
9488 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
9489 /* HWRM Asynchronous Event Information */
9490 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
9492 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
9493 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
9494 /* Identifiers of events. */
9497 * An event signifying a HWRM command is in progress and its
9498 * response will be deferred
9500 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
9502 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
9503 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
9504 /* Event specific data */
9505 uint32_t event_data2;
9507 * The PF's mailbox is clear to issue another command.
9508 * A command with this seq_id is still in progress
9509 * and will return a regular HWRM completion when done.
9510 * 'event_data1' field, if non-zero, contains the estimated
9511 * execution time for the command.
9513 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
9515 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
9519 * This value is written by the NIC such that it will be different
9520 * for each pass through the completion queue. The even passes
9521 * will write 1. The odd passes will write 0.
9523 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
9526 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
9528 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
9529 /* 8-lsb timestamp from POR (100-msec resolution) */
9530 uint8_t timestamp_lo;
9531 /* 16-lsb timestamp from POR (100-msec resolution) */
9532 uint16_t timestamp_hi;
9533 /* Estimated remaining time of command execution in ms (if not zero) */
9534 uint32_t event_data1;
9537 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
9538 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
9541 * This field indicates the exact type of the completion.
9542 * By convention, the LSB identifies the length of the
9543 * record in 16B units. Even values indicate 16B
9544 * records. Odd values indicate 32B
9547 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
9549 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
9551 /* HWRM Asynchronous Event Information */
9552 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
9554 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
9555 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
9556 /* Identifiers of events. */
9558 /* PFC watchdog configuration change for given port/cos */
9559 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
9561 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
9562 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
9563 /* Event specific data */
9564 uint32_t event_data2;
9567 * This value is written by the NIC such that it will be different
9568 * for each pass through the completion queue. The even passes
9569 * will write 1. The odd passes will write 0.
9571 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
9574 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
9576 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
9577 /* 8-lsb timestamp from POR (100-msec resolution) */
9578 uint8_t timestamp_lo;
9579 /* 16-lsb timestamp from POR (100-msec resolution) */
9580 uint16_t timestamp_hi;
9581 /* Event specific data */
9582 uint32_t event_data1;
9584 * 1 in bit position X indicates PFC watchdog should
9587 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
9589 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
9591 /* 1 means PFC WD for COS0 is on, 0 - off. */
9592 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
9594 /* 1 means PFC WD for COS1 is on, 0 - off. */
9595 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
9597 /* 1 means PFC WD for COS2 is on, 0 - off. */
9598 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
9600 /* 1 means PFC WD for COS3 is on, 0 - off. */
9601 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
9603 /* 1 means PFC WD for COS4 is on, 0 - off. */
9604 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
9606 /* 1 means PFC WD for COS5 is on, 0 - off. */
9607 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
9609 /* 1 means PFC WD for COS6 is on, 0 - off. */
9610 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
9612 /* 1 means PFC WD for COS7 is on, 0 - off. */
9613 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
9616 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
9618 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
9622 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
9623 struct hwrm_async_event_cmpl_echo_request {
9626 * This field indicates the exact type of the completion.
9627 * By convention, the LSB identifies the length of the
9628 * record in 16B units. Even values indicate 16B
9629 * records. Odd values indicate 32B
9632 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \
9634 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
9635 /* HWRM Asynchronous Event Information */
9636 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \
9638 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \
9639 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
9640 /* Identifiers of events. */
9643 * An echo request from the firmware. An echo response is expected by
9646 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \
9648 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \
9649 HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
9650 /* Event specific data that should be provided in the echo response */
9651 uint32_t event_data2;
9654 * This value is written by the NIC such that it will be different
9655 * for each pass through the completion queue. The even passes
9656 * will write 1. The odd passes will write 0.
9658 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
9660 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
9661 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
9662 /* 8-lsb timestamp from POR (100-msec resolution) */
9663 uint8_t timestamp_lo;
9664 /* 16-lsb timestamp from POR (100-msec resolution) */
9665 uint16_t timestamp_hi;
9666 /* Event specific data that should be provided in the echo response */
9667 uint32_t event_data1;
9670 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
9671 struct hwrm_async_event_cmpl_fw_trace_msg {
9674 * This field indicates the exact type of the completion.
9675 * By convention, the LSB identifies the length of the
9676 * record in 16B units. Even values indicate 16B
9677 * records. Odd values indicate 32B
9680 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
9682 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
9683 /* HWRM Asynchronous Event Information */
9684 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
9686 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
9687 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
9688 /* Identifiers of events. */
9690 /* Firmware trace log message */
9691 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
9693 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
9694 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
9695 /* Trace byte 0 to 3 */
9696 uint32_t event_data2;
9698 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
9700 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
9702 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
9704 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
9706 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
9708 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
9710 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
9711 UINT32_C(0xff000000)
9712 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
9715 * This value is written by the NIC such that it will be different
9716 * for each pass through the completion queue. The even passes
9717 * will write 1. The odd passes will write 0.
9719 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
9721 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
9722 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
9724 uint8_t timestamp_lo;
9725 /* Indicates if the string is partial or complete. */
9726 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
9728 /* Complete string */
9729 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
9731 /* Partial string */
9732 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
9734 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
9735 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
9736 /* Indicates the firmware that sent the trace message. */
9737 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
9739 /* Primary firmware */
9740 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
9741 (UINT32_C(0x0) << 1)
9742 /* Secondary firmware */
9743 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
9744 (UINT32_C(0x1) << 1)
9745 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
9746 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
9747 /* Trace byte 4 to 5 */
9748 uint16_t timestamp_hi;
9750 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
9752 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
9754 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
9756 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
9757 /* Trace byte 6 to 9 */
9758 uint32_t event_data1;
9760 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
9762 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
9764 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
9766 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
9768 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
9770 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
9772 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
9773 UINT32_C(0xff000000)
9774 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
9777 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
9778 struct hwrm_async_event_cmpl_hwrm_error {
9781 * This field indicates the exact type of the completion.
9782 * By convention, the LSB identifies the length of the
9783 * record in 16B units. Even values indicate 16B
9784 * records. Odd values indicate 32B
9787 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
9789 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
9790 /* HWRM Asynchronous Event Information */
9791 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
9793 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
9794 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
9795 /* Identifiers of events. */
9798 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
9800 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
9801 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
9802 /* Event specific data */
9803 uint32_t event_data2;
9804 /* Severity of HWRM Error */
9805 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
9807 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
9809 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
9811 /* Non-fatal Error */
9812 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
9815 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
9817 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
9818 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
9821 * This value is written by the NIC such that it will be different
9822 * for each pass through the completion queue. The even passes
9823 * will write 1. The odd passes will write 0.
9825 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
9827 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
9828 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
9829 /* 8-lsb timestamp from POR (100-msec resolution) */
9830 uint8_t timestamp_lo;
9831 /* 16-lsb timestamp from POR (100-msec resolution) */
9832 uint16_t timestamp_hi;
9833 /* Event specific data */
9834 uint32_t event_data1;
9835 /* Time stamp for error event */
9836 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
9840 /* metadata_base_msg (size:64b/8B) */
9841 struct metadata_base_msg {
9842 uint16_t md_type_link;
9843 /* This field classifies the data present in the meta-data. */
9844 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
9845 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
9846 /* Meta data fields are not valid */
9847 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
9849 * This setting is used when packets are coming in-order. Depending on
9850 * the state of the receive context, the meta-data will carry different
9853 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
9855 * With this setting HW passes the TCP sequence number of the TLS
9856 * record that it is requesting a resync on in the meta data.
9858 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
9859 #define METADATA_BASE_MSG_MD_TYPE_LAST \
9860 METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9862 * This field indicates where the next metadata block starts. It is
9863 * counted in 16B units. A value of zero indicates that there is no
9866 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
9867 #define METADATA_BASE_MSG_LINK_SFT 5
9872 /* tls_metadata_base_msg (size:64b/8B) */
9873 struct tls_metadata_base_msg {
9874 uint32_t md_type_link_flags_kid_lo;
9875 /* This field classifies the data present in the meta-data. */
9876 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \
9878 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
9880 * This setting is used when packets are coming in-order. Depending on
9881 * the state of the receive context, the meta-data will carry different
9884 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \
9887 * With this setting HW passes the TCP sequence number of the TLS
9888 * record that it is requesting a resync on in the meta data.
9890 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC \
9892 #define TLS_METADATA_BASE_MSG_MD_TYPE_LAST \
9893 TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC
9895 * This field indicates where the next metadata block starts. It is
9896 * counted in 16B units. A value of zero indicates that there is no
9899 #define TLS_METADATA_BASE_MSG_LINK_MASK \
9901 #define TLS_METADATA_BASE_MSG_LINK_SFT 5
9902 /* These are flags present in the metadata. */
9903 #define TLS_METADATA_BASE_MSG_FLAGS_MASK \
9905 #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9
9907 * A value of 1 implies that the packet was decrypted by HW. Otherwise
9908 * the packet is passed on as it came in on the wire.
9910 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED \
9913 * This field indicates the state of the ghash field passed in the
9916 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \
9918 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10
9920 * This enumeration states that the ghash is not valid in the
9923 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID \
9924 (UINT32_C(0x0) << 10)
9926 * This enumeration indicates that this pkt contains the record's
9927 * tag and this pkt was received ooo, the partial_ghash field
9928 * contains the ghash.
9930 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC \
9931 (UINT32_C(0x1) << 10)
9933 * This enumeration indicates that the current record's tag wasn't
9934 * seen and the chip is moving on to the next record, the
9935 * partial_ghash field contains the ghash.
9937 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC \
9938 (UINT32_C(0x2) << 10)
9939 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_LAST \
9940 TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC
9941 /* This field indicates the status of tag authentication. */
9942 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
9944 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
9946 * This enumeration is set when there is no tags present in the
9949 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
9950 (UINT32_C(0x0) << 12)
9952 * This enumeration states that there is at least one tag in the
9953 * packet and every tag is valid.
9955 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
9956 (UINT32_C(0x1) << 12)
9958 * This enumeration states that there is at least one tag in the
9959 * packet and at least one of the tag is invalid. The entire packet
9960 * is sent decrypted to the host.
9962 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
9963 (UINT32_C(0x2) << 12)
9964 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
9965 TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
9967 * A value of 1 indicates that this packet contains a record that
9968 * starts in the packet and extends beyond the packet.
9970 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \
9973 * This value indicates the lower 7-bit of the Crypto Key ID
9974 * associated with this operation.
9976 #define TLS_METADATA_BASE_MSG_KID_LO_MASK \
9977 UINT32_C(0xfe000000)
9978 #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25
9981 * This value indicates the upper 13-bit of the Crypto Key ID
9982 * associated with this operation.
9984 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
9985 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
9989 /* tls_metadata_insync_msg (size:192b/24B) */
9990 struct tls_metadata_insync_msg {
9991 uint32_t md_type_link_flags_kid_lo;
9992 /* This field classifies the data present in the meta-data. */
9993 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \
9995 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
9997 * This setting is used when packets are coming in-order. Depending on
9998 * the state of the receive context, the meta-data will carry different
10001 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \
10003 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_LAST \
10004 TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC
10006 * This field indicates where the next metadata block starts. It is
10007 * counted in 16B units. A value of zero indicates that there is no
10010 #define TLS_METADATA_INSYNC_MSG_LINK_MASK \
10012 #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5
10013 /* These are flags present in the metadata. */
10014 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \
10015 UINT32_C(0x1fffe00)
10016 #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9
10018 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10019 * the packet is passed on as it came in on the wire.
10021 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED \
10024 * This field indicates the state of the ghash field passed in the
10027 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \
10029 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10
10031 * This enumeration states that the ghash is not valid in the
10034 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID \
10035 (UINT32_C(0x0) << 10)
10037 * This enumeration indicates that this pkt contains the record's
10038 * tag and this pkt was received ooo, the partial_ghash field
10039 * contains the ghash.
10041 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC \
10042 (UINT32_C(0x1) << 10)
10044 * This enumeration indicates that the current record's tag wasn't
10045 * seen and the chip is moving on to the next record, the
10046 * partial_ghash field contains the ghash.
10048 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC \
10049 (UINT32_C(0x2) << 10)
10050 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_LAST \
10051 TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC
10052 /* This field indicates the status of tag authentication. */
10053 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10055 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10057 * This enumeration is set when there is no tags present in the
10060 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10061 (UINT32_C(0x0) << 12)
10063 * This enumeration states that there is at least one tag in the
10064 * packet and every tag is valid.
10066 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS \
10067 (UINT32_C(0x1) << 12)
10069 * This enumeration states that there is at least one tag in the
10070 * packet and at least one of the tag is invalid. The entire packet
10071 * is sent decrypted to the host.
10073 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE \
10074 (UINT32_C(0x2) << 12)
10075 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10076 TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE
10078 * A value of 1 indicates that this packet contains a record that
10079 * starts in the packet and extends beyond the packet.
10081 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10084 * This value indicates the lower 7-bit of the Crypto Key ID
10085 * associated with this operation.
10087 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \
10088 UINT32_C(0xfe000000)
10089 #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25
10092 * This value indicates the upper 13-bit of the Crypto Key ID
10093 * associated with this operation.
10095 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10096 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
10098 * This field is only valid when md_type is set to tls_insync. This field
10099 * indicates the offset within the current TCP packet where the TLS header
10100 * starts. If there are multiple TLS headers in the packet, this provides
10101 * the offset of the last TLS header.
10103 * The field is calculated by subtracting TCP sequence number of the first
10104 * byte of the TCP payload of the packet from the TCP sequence number of
10105 * the last TLS header in the packet.
10107 uint16_t tls_header_offset;
10109 * This is the sequence Number of the record that was processed by the HW.
10110 * If there are multiple records in a packet, this would be the sequence
10111 * number of the last record.
10113 uint64_t record_seq_num;
10115 * This field contains cumulative partial GHASH value of all the packets
10116 * decrypted by the HW associated with a TLS record. This field is valid
10117 * on when packets belonging to have arrived out-of-order and HW could
10118 * not decrypt every packet and authenticate the record. Partial GHASH is
10119 * only sent out with packet having the TAG field.
10121 uint64_t partial_ghash;
10124 /* tls_metadata_resync_msg (size:256b/32B) */
10125 struct tls_metadata_resync_msg {
10126 uint32_t md_type_link_flags_kid_lo;
10127 /* This field classifies the data present in the meta-data. */
10128 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \
10130 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
10132 * With this setting HW passes the TCP sequence number of the TLS
10133 * record that it is requesting a resync on in the meta data.
10135 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC \
10137 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_LAST \
10138 TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC
10140 * This field indicates where the next metadata block starts. It is
10141 * counted in 16B units. A value of zero indicates that there is no
10144 #define TLS_METADATA_RESYNC_MSG_LINK_MASK \
10146 #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5
10147 /* These are flags present in the metadata. */
10148 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \
10149 UINT32_C(0x1fffe00)
10150 #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9
10152 * A value of 1 implies that the packet was decrypted by HW. Otherwise
10153 * the packet is passed on as it came in on the wire.
10155 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED \
10158 * This field indicates the state of the ghash field passed in the
10161 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \
10163 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10
10165 * This enumeration states that the ghash is not valid in the
10168 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID \
10169 (UINT32_C(0x0) << 10)
10170 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_LAST \
10171 TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID
10172 /* This field indicates the status of tag authentication. */
10173 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \
10175 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12
10177 * This enumeration is set when there is no tags present in the
10180 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \
10181 (UINT32_C(0x0) << 12)
10182 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \
10183 TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE
10185 * A value of 1 indicates that this packet contains a record that
10186 * starts in the packet and extends beyond the packet.
10188 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \
10191 * This value indicates the lower 7-bit of the Crypto Key ID
10192 * associated with this operation.
10194 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \
10195 UINT32_C(0xfe000000)
10196 #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25
10199 * This value indicates the upper 13-bit of the Crypto Key ID
10200 * associated with this operation.
10202 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
10203 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
10204 /* This field is unused in this context. */
10205 uint16_t metadata_0;
10207 * This field indicates the TCP sequence number of the TLS record that HW
10208 * is requesting a resync on from the Driver. HW will keep a count of the
10209 * TLS records it found after this record (delta_records). Driver will
10210 * provide the TLS Record Sequence Number associated with the record. HW
10211 * will add the delta_records to the Record Sequence Number provided by
10212 * the driver and get back on sync.
10214 uint32_t resync_record_tcp_seq_num;
10216 /* This field is unused in this context. */
10217 uint64_t metadata_2;
10218 /* This field is unused in this context. */
10219 uint64_t metadata_3;
10222 /*******************
10223 * hwrm_func_reset *
10224 *******************/
10227 /* hwrm_func_reset_input (size:192b/24B) */
10228 struct hwrm_func_reset_input {
10229 /* The HWRM command request type. */
10232 * The completion ring to send the completion event on. This should
10233 * be the NQ ID returned from the `nq_alloc` HWRM command.
10235 uint16_t cmpl_ring;
10237 * The sequence ID is used by the driver for tracking multiple
10238 * commands. This ID is treated as opaque data by the firmware and
10239 * the value is returned in the `hwrm_resp_hdr` upon completion.
10243 * The target ID of the command:
10244 * * 0x0-0xFFF8 - The function ID
10245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10246 * * 0xFFFD - Reserved for user-space HWRM interface
10249 uint16_t target_id;
10251 * A physical address pointer pointing to a host buffer that the
10252 * command's response data will be written. This can be either a host
10253 * physical address (HPA) or a guest physical address (GPA) and must
10254 * point to a physically contiguous block of memory.
10256 uint64_t resp_addr;
10259 * This bit must be '1' for the vf_id_valid field to be
10262 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
10264 * The ID of the VF that this PF is trying to reset.
10265 * Only the parent PF shall be allowed to reset a child VF.
10267 * A parent PF driver shall use this field only when a specific child VF
10268 * is requested to be reset.
10271 /* This value indicates the level of a function reset. */
10272 uint8_t func_reset_level;
10274 * Reset the caller function and its children VFs (if any). If no
10275 * children functions exist, then reset the caller function only.
10277 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
10279 /* Reset the caller function only */
10280 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
10283 * Reset all children VFs of the caller function driver if the
10284 * caller is a PF driver.
10285 * It is an error to specify this level by a VF driver.
10286 * It is an error to specify this level by a PF driver with
10289 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
10292 * Reset a specific VF of the caller function driver if the caller
10293 * is the parent PF driver.
10294 * It is an error to specify this level by a VF driver.
10295 * It is an error to specify this level by a PF driver that is not
10296 * the parent of the VF that is being requested to reset.
10298 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
10300 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
10301 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
10305 /* hwrm_func_reset_output (size:128b/16B) */
10306 struct hwrm_func_reset_output {
10307 /* The specific error status for the command. */
10308 uint16_t error_code;
10309 /* The HWRM command request type. */
10311 /* The sequence ID from the original command. */
10313 /* The length of the response data in number of bytes. */
10315 uint8_t unused_0[7];
10317 * This field is used in Output records to indicate that the output
10318 * is completely written to RAM. This field should be read as '1'
10319 * to indicate that the output has been completely written.
10320 * When writing a command completion or response to an internal processor,
10321 * the order of writes has to be such that this field is written last.
10326 /********************
10327 * hwrm_func_getfid *
10328 ********************/
10331 /* hwrm_func_getfid_input (size:192b/24B) */
10332 struct hwrm_func_getfid_input {
10333 /* The HWRM command request type. */
10336 * The completion ring to send the completion event on. This should
10337 * be the NQ ID returned from the `nq_alloc` HWRM command.
10339 uint16_t cmpl_ring;
10341 * The sequence ID is used by the driver for tracking multiple
10342 * commands. This ID is treated as opaque data by the firmware and
10343 * the value is returned in the `hwrm_resp_hdr` upon completion.
10347 * The target ID of the command:
10348 * * 0x0-0xFFF8 - The function ID
10349 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10350 * * 0xFFFD - Reserved for user-space HWRM interface
10353 uint16_t target_id;
10355 * A physical address pointer pointing to a host buffer that the
10356 * command's response data will be written. This can be either a host
10357 * physical address (HPA) or a guest physical address (GPA) and must
10358 * point to a physically contiguous block of memory.
10360 uint64_t resp_addr;
10363 * This bit must be '1' for the pci_id field to be
10366 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
10368 * This value is the PCI ID of the queried function.
10369 * If ARI is enabled, then it is
10370 * Bus Number (8b):Function Number(8b). Otherwise, it is
10371 * Bus Number (8b):Device Number (5b):Function Number(3b).
10374 uint8_t unused_0[2];
10377 /* hwrm_func_getfid_output (size:128b/16B) */
10378 struct hwrm_func_getfid_output {
10379 /* The specific error status for the command. */
10380 uint16_t error_code;
10381 /* The HWRM command request type. */
10383 /* The sequence ID from the original command. */
10385 /* The length of the response data in number of bytes. */
10388 * FID value. This value is used to identify operations on the PCI
10389 * bus as belonging to a particular PCI function.
10392 uint8_t unused_0[5];
10394 * This field is used in Output records to indicate that the output
10395 * is completely written to RAM. This field should be read as '1'
10396 * to indicate that the output has been completely written.
10397 * When writing a command completion or response to an internal processor,
10398 * the order of writes has to be such that this field is written last.
10403 /**********************
10404 * hwrm_func_vf_alloc *
10405 **********************/
10408 /* hwrm_func_vf_alloc_input (size:192b/24B) */
10409 struct hwrm_func_vf_alloc_input {
10410 /* The HWRM command request type. */
10413 * The completion ring to send the completion event on. This should
10414 * be the NQ ID returned from the `nq_alloc` HWRM command.
10416 uint16_t cmpl_ring;
10418 * The sequence ID is used by the driver for tracking multiple
10419 * commands. This ID is treated as opaque data by the firmware and
10420 * the value is returned in the `hwrm_resp_hdr` upon completion.
10424 * The target ID of the command:
10425 * * 0x0-0xFFF8 - The function ID
10426 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10427 * * 0xFFFD - Reserved for user-space HWRM interface
10430 uint16_t target_id;
10432 * A physical address pointer pointing to a host buffer that the
10433 * command's response data will be written. This can be either a host
10434 * physical address (HPA) or a guest physical address (GPA) and must
10435 * point to a physically contiguous block of memory.
10437 uint64_t resp_addr;
10440 * This bit must be '1' for the first_vf_id field to be
10443 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10445 * This value is used to identify a Virtual Function (VF).
10446 * The scope of VF ID is local within a PF.
10448 uint16_t first_vf_id;
10449 /* The number of virtual functions requested. */
10453 /* hwrm_func_vf_alloc_output (size:128b/16B) */
10454 struct hwrm_func_vf_alloc_output {
10455 /* The specific error status for the command. */
10456 uint16_t error_code;
10457 /* The HWRM command request type. */
10459 /* The sequence ID from the original command. */
10461 /* The length of the response data in number of bytes. */
10463 /* The ID of the first VF allocated. */
10464 uint16_t first_vf_id;
10465 uint8_t unused_0[5];
10467 * This field is used in Output records to indicate that the output
10468 * is completely written to RAM. This field should be read as '1'
10469 * to indicate that the output has been completely written.
10470 * When writing a command completion or response to an internal processor,
10471 * the order of writes has to be such that this field is written last.
10476 /*********************
10477 * hwrm_func_vf_free *
10478 *********************/
10481 /* hwrm_func_vf_free_input (size:192b/24B) */
10482 struct hwrm_func_vf_free_input {
10483 /* The HWRM command request type. */
10486 * The completion ring to send the completion event on. This should
10487 * be the NQ ID returned from the `nq_alloc` HWRM command.
10489 uint16_t cmpl_ring;
10491 * The sequence ID is used by the driver for tracking multiple
10492 * commands. This ID is treated as opaque data by the firmware and
10493 * the value is returned in the `hwrm_resp_hdr` upon completion.
10497 * The target ID of the command:
10498 * * 0x0-0xFFF8 - The function ID
10499 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10500 * * 0xFFFD - Reserved for user-space HWRM interface
10503 uint16_t target_id;
10505 * A physical address pointer pointing to a host buffer that the
10506 * command's response data will be written. This can be either a host
10507 * physical address (HPA) or a guest physical address (GPA) and must
10508 * point to a physically contiguous block of memory.
10510 uint64_t resp_addr;
10513 * This bit must be '1' for the first_vf_id field to be
10516 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
10518 * This value is used to identify a Virtual Function (VF).
10519 * The scope of VF ID is local within a PF.
10521 uint16_t first_vf_id;
10523 * The number of virtual functions requested.
10524 * 0xFFFF - Cleanup all children of this PF.
10529 /* hwrm_func_vf_free_output (size:128b/16B) */
10530 struct hwrm_func_vf_free_output {
10531 /* The specific error status for the command. */
10532 uint16_t error_code;
10533 /* The HWRM command request type. */
10535 /* The sequence ID from the original command. */
10537 /* The length of the response data in number of bytes. */
10539 uint8_t unused_0[7];
10541 * This field is used in Output records to indicate that the output
10542 * is completely written to RAM. This field should be read as '1'
10543 * to indicate that the output has been completely written.
10544 * When writing a command completion or response to an internal processor,
10545 * the order of writes has to be such that this field is written last.
10550 /********************
10551 * hwrm_func_vf_cfg *
10552 ********************/
10555 /* hwrm_func_vf_cfg_input (size:448b/56B) */
10556 struct hwrm_func_vf_cfg_input {
10557 /* The HWRM command request type. */
10560 * The completion ring to send the completion event on. This should
10561 * be the NQ ID returned from the `nq_alloc` HWRM command.
10563 uint16_t cmpl_ring;
10565 * The sequence ID is used by the driver for tracking multiple
10566 * commands. This ID is treated as opaque data by the firmware and
10567 * the value is returned in the `hwrm_resp_hdr` upon completion.
10571 * The target ID of the command:
10572 * * 0x0-0xFFF8 - The function ID
10573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10574 * * 0xFFFD - Reserved for user-space HWRM interface
10577 uint16_t target_id;
10579 * A physical address pointer pointing to a host buffer that the
10580 * command's response data will be written. This can be either a host
10581 * physical address (HPA) or a guest physical address (GPA) and must
10582 * point to a physically contiguous block of memory.
10584 uint64_t resp_addr;
10587 * This bit must be '1' for the mtu field to be
10590 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
10593 * This bit must be '1' for the guest_vlan field to be
10596 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
10599 * This bit must be '1' for the async_event_cr field to be
10602 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10605 * This bit must be '1' for the dflt_mac_addr field to be
10608 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10611 * This bit must be '1' for the num_rsscos_ctxs field to be
10614 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10617 * This bit must be '1' for the num_cmpl_rings field to be
10620 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10623 * This bit must be '1' for the num_tx_rings field to be
10626 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10629 * This bit must be '1' for the num_rx_rings field to be
10632 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10635 * This bit must be '1' for the num_l2_ctxs field to be
10638 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10641 * This bit must be '1' for the num_vnics field to be
10644 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
10647 * This bit must be '1' for the num_stat_ctxs field to be
10650 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10653 * This bit must be '1' for the num_hw_ring_grps field to be
10656 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10659 * The maximum transmission unit requested on the function.
10660 * The HWRM should make sure that the mtu of
10661 * the function does not exceed the mtu of the physical
10662 * port that this function is associated with.
10664 * In addition to requesting mtu per function, it is
10665 * possible to configure mtu per transmit ring.
10666 * By default, the mtu of each transmit ring associated
10667 * with a function is equal to the mtu of the function.
10668 * The HWRM should make sure that the mtu of each transmit
10669 * ring that is assigned to a function has a valid mtu.
10673 * The guest VLAN for the function being configured.
10674 * This field's format is same as 802.1Q Tag's
10675 * Tag Control Information (TCI) format that includes both
10676 * Priority Code Point (PCP) and VLAN Identifier (VID).
10678 uint16_t guest_vlan;
10680 * ID of the target completion ring for receiving asynchronous
10681 * event completions. If this field is not valid, then the
10682 * HWRM shall use the default completion ring of the function
10683 * that is being configured as the target completion ring for
10684 * providing any asynchronous event completions for that
10686 * If this field is valid, then the HWRM shall use the
10687 * completion ring identified by this ID as the target
10688 * completion ring for providing any asynchronous event
10689 * completions for the function that is being configured.
10691 uint16_t async_event_cr;
10693 * This value is the current MAC address requested by the VF
10694 * driver to be configured on this VF. A value of
10695 * 00-00-00-00-00-00 indicates no MAC address configuration
10696 * is requested by the VF driver.
10697 * The parent PF driver may reject or overwrite this
10700 uint8_t dflt_mac_addr[6];
10703 * This bit requests that the firmware test to see if all the assets
10704 * requested in this command (i.e. number of TX rings) are available.
10705 * The firmware will return an error if the requested assets are
10706 * not available. The firwmare will NOT reserve the assets if they
10709 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10712 * This bit requests that the firmware test to see if all the assets
10713 * requested in this command (i.e. number of RX rings) are available.
10714 * The firmware will return an error if the requested assets are
10715 * not available. The firwmare will NOT reserve the assets if they
10718 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10721 * This bit requests that the firmware test to see if all the assets
10722 * requested in this command (i.e. number of CMPL rings) are available.
10723 * The firmware will return an error if the requested assets are
10724 * not available. The firwmare will NOT reserve the assets if they
10727 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10730 * This bit requests that the firmware test to see if all the assets
10731 * requested in this command (i.e. number of RSS ctx) are available.
10732 * The firmware will return an error if the requested assets are
10733 * not available. The firwmare will NOT reserve the assets if they
10736 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10739 * This bit requests that the firmware test to see if all the assets
10740 * requested in this command (i.e. number of ring groups) are available.
10741 * The firmware will return an error if the requested assets are
10742 * not available. The firwmare will NOT reserve the assets if they
10745 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10748 * This bit requests that the firmware test to see if all the assets
10749 * requested in this command (i.e. number of stat ctx) are available.
10750 * The firmware will return an error if the requested assets are
10751 * not available. The firwmare will NOT reserve the assets if they
10754 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10757 * This bit requests that the firmware test to see if all the assets
10758 * requested in this command (i.e. number of VNICs) are available.
10759 * The firmware will return an error if the requested assets are
10760 * not available. The firwmare will NOT reserve the assets if they
10763 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10766 * This bit requests that the firmware test to see if all the assets
10767 * requested in this command (i.e. number of L2 ctx) are available.
10768 * The firmware will return an error if the requested assets are
10769 * not available. The firwmare will NOT reserve the assets if they
10772 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10775 * If this bit is set to 1, the VF driver is requesting FW to enable
10776 * PPP TX PUSH feature on all the TX rings specified in the
10777 * num_tx_rings field. By default, the PPP TX push feature is
10778 * disabled for all the TX rings of the VF. This flag is ignored if
10779 * the num_tx_rings field is not specified or the VF doesn't support
10780 * PPP tx push feature.
10782 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10785 * If this bit is set to 1, the VF driver is requesting FW to disable
10786 * PPP TX PUSH feature on all the TX rings of the VF. This flag is
10787 * ignored if the VF doesn't support PPP tx push feature.
10789 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
10791 /* The number of RSS/COS contexts requested for the VF. */
10792 uint16_t num_rsscos_ctxs;
10793 /* The number of completion rings requested for the VF. */
10794 uint16_t num_cmpl_rings;
10795 /* The number of transmit rings requested for the VF. */
10796 uint16_t num_tx_rings;
10797 /* The number of receive rings requested for the VF. */
10798 uint16_t num_rx_rings;
10799 /* The number of L2 contexts requested for the VF. */
10800 uint16_t num_l2_ctxs;
10801 /* The number of vnics requested for the VF. */
10802 uint16_t num_vnics;
10803 /* The number of statistic contexts requested for the VF. */
10804 uint16_t num_stat_ctxs;
10805 /* The number of HW ring groups requested for the VF. */
10806 uint16_t num_hw_ring_grps;
10807 uint8_t unused_0[4];
10810 /* hwrm_func_vf_cfg_output (size:128b/16B) */
10811 struct hwrm_func_vf_cfg_output {
10812 /* The specific error status for the command. */
10813 uint16_t error_code;
10814 /* The HWRM command request type. */
10816 /* The sequence ID from the original command. */
10818 /* The length of the response data in number of bytes. */
10820 uint8_t unused_0[7];
10822 * This field is used in Output records to indicate that the output
10823 * is completely written to RAM. This field should be read as '1'
10824 * to indicate that the output has been completely written.
10825 * When writing a command completion or response to an internal processor,
10826 * the order of writes has to be such that this field is written last.
10831 /*******************
10832 * hwrm_func_qcaps *
10833 *******************/
10836 /* hwrm_func_qcaps_input (size:192b/24B) */
10837 struct hwrm_func_qcaps_input {
10838 /* The HWRM command request type. */
10841 * The completion ring to send the completion event on. This should
10842 * be the NQ ID returned from the `nq_alloc` HWRM command.
10844 uint16_t cmpl_ring;
10846 * The sequence ID is used by the driver for tracking multiple
10847 * commands. This ID is treated as opaque data by the firmware and
10848 * the value is returned in the `hwrm_resp_hdr` upon completion.
10852 * The target ID of the command:
10853 * * 0x0-0xFFF8 - The function ID
10854 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10855 * * 0xFFFD - Reserved for user-space HWRM interface
10858 uint16_t target_id;
10860 * A physical address pointer pointing to a host buffer that the
10861 * command's response data will be written. This can be either a host
10862 * physical address (HPA) or a guest physical address (GPA) and must
10863 * point to a physically contiguous block of memory.
10865 uint64_t resp_addr;
10867 * Function ID of the function that is being queried.
10868 * 0xFF... (All Fs) if the query is for the requesting
10870 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
10871 * to be used by a trusted VF to query its parent PF.
10874 uint8_t unused_0[6];
10877 /* hwrm_func_qcaps_output (size:704b/88B) */
10878 struct hwrm_func_qcaps_output {
10879 /* The specific error status for the command. */
10880 uint16_t error_code;
10881 /* The HWRM command request type. */
10883 /* The sequence ID from the original command. */
10885 /* The length of the response data in number of bytes. */
10888 * FID value. This value is used to identify operations on the PCI
10889 * bus as belonging to a particular PCI function.
10893 * Port ID of port that this function is associated with.
10894 * Valid only for the PF.
10895 * 0xFF... (All Fs) if this function is not associated with
10897 * 0xFF... (All Fs) if this function is called from a VF.
10901 /* If 1, then Push mode is supported on this function. */
10902 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
10905 * If 1, then the global MSI-X auto-masking is enabled for the
10908 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
10911 * If 1, then the Precision Time Protocol (PTP) processing
10912 * is supported on this function.
10913 * The HWRM should enable PTP on only a single Physical
10914 * Function (PF) per port.
10916 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
10919 * If 1, then RDMA over Converged Ethernet (RoCE) v1
10920 * is supported on this function.
10922 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
10925 * If 1, then RDMA over Converged Ethernet (RoCE) v2
10926 * is supported on this function.
10928 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
10931 * If 1, then control and configuration of WoL magic packet
10932 * are supported on this function.
10934 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
10937 * If 1, then control and configuration of bitmap pattern
10938 * packet are supported on this function.
10940 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
10943 * If set to 1, then the control and configuration of rate limit
10944 * of an allocated TX ring on the queried function is supported.
10946 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
10949 * If 1, then control and configuration of minimum and
10950 * maximum bandwidths are supported on the queried function.
10952 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
10955 * If the query is for a VF, then this flag shall be ignored.
10956 * If this query is for a PF and this flag is set to 1,
10957 * then the PF has the capability to set the rate limits
10958 * on the TX rings of its children VFs.
10959 * If this query is for a PF and this flag is set to 0, then
10960 * the PF does not have the capability to set the rate limits
10961 * on the TX rings of its children VFs.
10963 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
10966 * If the query is for a VF, then this flag shall be ignored.
10967 * If this query is for a PF and this flag is set to 1,
10968 * then the PF has the capability to set the minimum and/or
10969 * maximum bandwidths for its children VFs.
10970 * If this query is for a PF and this flag is set to 0, then
10971 * the PF does not have the capability to set the minimum or
10972 * maximum bandwidths for its children VFs.
10974 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
10977 * Standard TX Ring mode is used for the allocation of TX ring
10978 * and underlying scheduling resources that allow bandwidth
10979 * reservation and limit settings on the queried function.
10980 * If set to 1, then standard TX ring mode is supported
10981 * on the queried function.
10982 * If set to 0, then standard TX ring mode is not available
10983 * on the queried function.
10985 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
10988 * If the query is for a VF, then this flag shall be ignored,
10989 * If this query is for a PF and this flag is set to 1,
10990 * then the PF has the capability to detect GENEVE tunnel
10993 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
10996 * If the query is for a VF, then this flag shall be ignored,
10997 * If this query is for a PF and this flag is set to 1,
10998 * then the PF has the capability to detect NVGRE tunnel
11001 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
11004 * If the query is for a VF, then this flag shall be ignored,
11005 * If this query is for a PF and this flag is set to 1,
11006 * then the PF has the capability to detect GRE tunnel
11009 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
11012 * If the query is for a VF, then this flag shall be ignored,
11013 * If this query is for a PF and this flag is set to 1,
11014 * then the PF has the capability to detect MPLS tunnel
11017 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
11020 * If the query is for a VF, then this flag shall be ignored,
11021 * If this query is for a PF and this flag is set to 1,
11022 * then the PF has the capability to support pcie stats.
11024 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
11027 * If the query is for a VF, then this flag shall be ignored,
11028 * If this query is for a PF and this flag is set to 1,
11029 * then the PF has the capability to adopt the VF's belonging
11032 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
11035 * If the query is for a VF, then this flag shall be ignored,
11036 * If this query is for a PF and this flag is set to 1,
11037 * then the PF has the administrative privilege to configure another PF
11039 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
11042 * If the query is for a VF, then this flag shall be ignored.
11043 * If this query is for a PF and this flag is set to 1, then
11044 * the PF will know that the firmware has the capability to track
11045 * the virtual link status.
11047 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
11050 * If 1, then this function supports the push mode that uses
11051 * write combine buffers and the long inline tx buffer descriptor.
11053 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
11056 * If 1, then FW has capability to allocate TX rings dynamically
11057 * in ring alloc even if PF reserved pool is zero.
11058 * This bit will be used only for PFs.
11060 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
11063 * When this bit is '1', it indicates that core firmware is
11064 * capable of Hot Reset.
11066 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
11069 * This flag will be set to 1 by the FW if FW supports adapter error
11072 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
11075 * If the query is for a VF, then this flag shall be ignored.
11076 * If this query is for a PF and this flag is set to 1, then
11077 * the PF has the capability to support extended stats.
11079 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
11080 UINT32_C(0x1000000)
11082 * If the query is for a VF, then this flag shall be ignored.
11083 * If this query is for a PF and this flag is set to 1, then host
11084 * must initiate reset or reload (or fastboot) the firmware image
11085 * upon detection of device shutdown state.
11087 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
11088 UINT32_C(0x2000000)
11090 * If the query is for a VF, then this flag (always set to 0) shall
11091 * be ignored. If this query is for a PF and this flag is set to 1,
11092 * host, when registered for the default vnic change async event,
11093 * receives async notification whenever a default vnic state is
11094 * changed for any of child or adopted VFs.
11096 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
11097 UINT32_C(0x4000000)
11098 /* If set to 1, then the vlan acceleration for TX is disabled. */
11099 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
11100 UINT32_C(0x8000000)
11102 * When this bit is '1', it indicates that core firmware supports
11103 * DBG_COREDUMP_XXX commands.
11105 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
11106 UINT32_C(0x10000000)
11108 * When this bit is '1', it indicates that core firmware supports
11109 * DBG_CRASHDUMP_XXX commands.
11111 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
11112 UINT32_C(0x20000000)
11114 * If the query is for a VF, then this flag should be ignored.
11115 * If the query is for a PF and this flag is set to 1, then
11116 * the PF has the capability to support retrieval of
11117 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
11118 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
11119 * If this flag is set to 1, only that (supported) command should
11120 * be used for retrieval of PFC related statistics (rather than
11121 * hwrm_port_qstats_ext command, which could previously be used).
11123 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
11124 UINT32_C(0x40000000)
11126 * When this bit is '1', it indicates that core firmware supports
11127 * DBG_QCAPS command
11129 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
11130 UINT32_C(0x80000000)
11132 * This value is current MAC address configured for this
11133 * function. A value of 00-00-00-00-00-00 indicates no
11134 * MAC address is currently configured.
11136 uint8_t mac_address[6];
11138 * The maximum number of RSS/COS contexts that can be
11139 * allocated to the function.
11141 uint16_t max_rsscos_ctx;
11143 * The maximum number of completion rings that can be
11144 * allocated to the function.
11146 uint16_t max_cmpl_rings;
11148 * The maximum number of transmit rings that can be
11149 * allocated to the function.
11151 uint16_t max_tx_rings;
11153 * The maximum number of receive rings that can be
11154 * allocated to the function.
11156 uint16_t max_rx_rings;
11158 * The maximum number of L2 contexts that can be
11159 * allocated to the function.
11161 uint16_t max_l2_ctxs;
11163 * The maximum number of VNICs that can be
11164 * allocated to the function.
11166 uint16_t max_vnics;
11168 * The identifier for the first VF enabled on a PF. This
11169 * is valid only on the PF with SR-IOV enabled.
11170 * 0xFF... (All Fs) if this command is called on a PF with
11171 * SR-IOV disabled or on a VF.
11173 uint16_t first_vf_id;
11175 * The maximum number of VFs that can be
11176 * allocated to the function. This is valid only on the
11177 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
11178 * command is called on a PF with SR-IOV disabled or
11183 * The maximum number of statistic contexts that can be
11184 * allocated to the function.
11186 uint16_t max_stat_ctx;
11188 * The maximum number of Encapsulation records that can be
11189 * offloaded by this function.
11191 uint32_t max_encap_records;
11193 * The maximum number of decapsulation records that can
11194 * be offloaded by this function.
11196 uint32_t max_decap_records;
11198 * The maximum number of Exact Match (EM) flows that can be
11199 * offloaded by this function on the TX side.
11201 uint32_t max_tx_em_flows;
11203 * The maximum number of Wildcard Match (WM) flows that can
11204 * be offloaded by this function on the TX side.
11206 uint32_t max_tx_wm_flows;
11208 * The maximum number of Exact Match (EM) flows that can be
11209 * offloaded by this function on the RX side.
11211 uint32_t max_rx_em_flows;
11213 * The maximum number of Wildcard Match (WM) flows that can
11214 * be offloaded by this function on the RX side.
11216 uint32_t max_rx_wm_flows;
11218 * The maximum number of multicast filters that can
11219 * be supported by this function on the RX side.
11221 uint32_t max_mcast_filters;
11223 * The maximum value of flow_id that can be supported
11224 * in completion records.
11226 uint32_t max_flow_id;
11228 * The maximum number of HW ring groups that can be
11229 * supported on this function.
11231 uint32_t max_hw_ring_grps;
11233 * The maximum number of strict priority transmit rings
11234 * that can be allocated to the function.
11235 * This number indicates the maximum number of TX rings
11236 * that can be assigned strict priorities out of the
11237 * maximum number of TX rings that can be allocated
11238 * (max_tx_rings) to the function.
11240 uint16_t max_sp_tx_rings;
11241 uint8_t unused_0[2];
11242 uint32_t flags_ext;
11244 * If 1, the device can be configured to set the ECN bits in the
11245 * IP header of received packets if the receive queue length
11246 * exceeds a given threshold.
11248 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
11251 * If 1, the device can report the number of received packets
11252 * that it marked as having experienced congestion.
11254 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
11257 * If 1, the device can report extended hw statistics (including
11258 * additional tpa statistics).
11260 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
11263 * If set to 1, then the core firmware has support to enable/
11264 * disable hot reset support for interface dynamically through
11267 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
11269 /* If 1, the proxy mode is supported on this function */
11270 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
11273 * If 1, the tx rings source interface override feature is supported
11274 * on this function.
11276 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
11279 * If 1, the device supports scheduler queues. SCHQs can be managed
11280 * using RING_SCHQ_ALLOC/CFG/FREE commands.
11282 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED \
11285 * If set to 1, then this function supports the TX push mode that
11286 * uses ping-pong buffers from the push pages.
11288 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
11291 * If set to 1, then this function doesn't have the privilege to
11292 * configure the EVB mode of the port it uses.
11294 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \
11297 * If set to 1, then the HW and FW support the SoC packet DMA
11298 * datapath between SoC and NIC. This function can act as the
11299 * HWRM communication transport agent on behalf of the SoC SPD
11300 * software module. This capability is only advertised to the
11303 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \
11306 * If set to 1, then this function supports FW_LIVEPATCH for
11307 * firmware livepatch commands.
11309 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \
11312 * When this bit is '1', it indicates that core firmware is
11313 * capable of fast Reset.
11315 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \
11318 * When this bit is '1', it indicates that firmware and hardware
11319 * are capable of updating tx_metadata via hwrm_ring_cfg command.
11321 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \
11324 * If set to 1, then the device can report the action
11325 * needed to activate set nvm options.
11327 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \
11330 * When this bit is '1', it indicates that the BD metadata feature
11331 * is supported for this function.
11333 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \
11336 * When this bit is '1', it indicates that the echo request feature
11337 * is supported for this function. If the driver registers for the
11338 * echo request asynchronous event, then the firmware can send an
11339 * unsolicited echo request to the driver and expect an echo
11342 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \
11344 /* The maximum number of SCHQs supported by this device. */
11346 uint8_t mpc_chnls_cap;
11348 * When this bit is '1', it indicates that HW and firmware
11349 * supports the use of a MPC channel with destination set
11350 * to the TX crypto engine block.
11352 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
11354 * When this bit is '1', it indicates that HW and firmware
11355 * supports the use of a MPC channel with destination set
11356 * to the RX crypto engine block.
11358 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
11360 * When this bit is '1', it indicates that HW and firmware
11361 * supports the use of a MPC channel with destination set
11362 * to the TX configurable flow processing block.
11364 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
11366 * When this bit is '1', it indicates that HW and firmware
11367 * supports the use of a MPC channel with destination set
11368 * to the RX configurable flow processing block.
11370 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
11372 * When this bit is '1', it indicates that HW and firmware
11373 * supports the use of a MPC channel with destination set
11374 * to the primate processor block.
11376 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
11379 * This field is used in Output records to indicate that the output
11380 * is completely written to RAM. This field should be read as '1'
11381 * to indicate that the output has been completely written.
11382 * When writing a command completion or response to an internal processor,
11383 * the order of writes has to be such that this field is written last.
11388 /******************
11390 ******************/
11393 /* hwrm_func_qcfg_input (size:192b/24B) */
11394 struct hwrm_func_qcfg_input {
11395 /* The HWRM command request type. */
11398 * The completion ring to send the completion event on. This should
11399 * be the NQ ID returned from the `nq_alloc` HWRM command.
11401 uint16_t cmpl_ring;
11403 * The sequence ID is used by the driver for tracking multiple
11404 * commands. This ID is treated as opaque data by the firmware and
11405 * the value is returned in the `hwrm_resp_hdr` upon completion.
11409 * The target ID of the command:
11410 * * 0x0-0xFFF8 - The function ID
11411 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11412 * * 0xFFFD - Reserved for user-space HWRM interface
11415 uint16_t target_id;
11417 * A physical address pointer pointing to a host buffer that the
11418 * command's response data will be written. This can be either a host
11419 * physical address (HPA) or a guest physical address (GPA) and must
11420 * point to a physically contiguous block of memory.
11422 uint64_t resp_addr;
11424 * Function ID of the function that is being queried.
11425 * 0xFF... (All Fs) if the query is for the requesting
11427 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
11428 * to be used by a trusted VF to query its parent PF.
11431 uint8_t unused_0[6];
11434 /* hwrm_func_qcfg_output (size:768b/96B) */
11435 struct hwrm_func_qcfg_output {
11436 /* The specific error status for the command. */
11437 uint16_t error_code;
11438 /* The HWRM command request type. */
11440 /* The sequence ID from the original command. */
11442 /* The length of the response data in number of bytes. */
11445 * FID value. This value is used to identify operations on the PCI
11446 * bus as belonging to a particular PCI function.
11450 * Port ID of port that this function is associated with.
11451 * 0xFF... (All Fs) if this function is not associated with
11456 * This value is the current VLAN setting for this
11457 * function. The value of 0 for this field indicates
11458 * no priority tagging or VLAN is used.
11459 * This field's format is same as 802.1Q Tag's
11460 * Tag Control Information (TCI) format that includes both
11461 * Priority Code Point (PCP) and VLAN Identifier (VID).
11466 * If 1, then magic packet based Out-Of-Box WoL is enabled on
11467 * the port associated with this function.
11469 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
11472 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
11473 * on the port associated with this function.
11475 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
11478 * If set to 1, then FW based DCBX agent is enabled and running on
11479 * the port associated with this function.
11480 * If set to 0, then DCBX agent is not running in the firmware.
11482 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
11485 * Standard TX Ring mode is used for the allocation of TX ring
11486 * and underlying scheduling resources that allow bandwidth
11487 * reservation and limit settings on the queried function.
11488 * If set to 1, then standard TX ring mode is enabled
11489 * on the queried function.
11490 * If set to 0, then the standard TX ring mode is disabled
11491 * on the queried function. In this extended TX ring resource
11492 * mode, the minimum and maximum bandwidth settings are not
11493 * supported to allow the allocation of TX rings to span multiple
11496 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
11499 * If set to 1 then FW based LLDP agent is enabled and running on
11500 * the port associated with this function.
11501 * If set to 0 then the LLDP agent is not running in the firmware.
11503 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
11506 * If set to 1, then multi-host mode is active for this function.
11507 * The NIC is attached to two or more independent host systems
11508 * through two or more PCIe endpoints.
11509 * If set to 0, then multi-host mode is inactive for this function
11510 * or not applicable for this device.
11512 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
11515 * If the function that is being queried is a PF, then the HWRM shall
11516 * set this field to 0 and the HWRM client shall ignore this field.
11517 * If the function that is being queried is a VF, then the HWRM shall
11518 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
11519 * shall set this field to 0.
11521 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
11524 * If set to 1, then secure mode is enabled for this function or device.
11525 * If set to 0, then secure mode is disabled (or normal mode) for this
11526 * function or device.
11528 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
11531 * If set to 1, then this PF is enabled with a preboot driver that
11532 * requires access to the legacy L2 ring model and legacy 32b
11533 * doorbells. If set to 0, then this PF is not allowed to use
11534 * the legacy L2 rings. This feature is not allowed on VFs and
11535 * is only relevant for devices that require a context backing
11538 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
11541 * If set to 1, then the firmware and all currently registered driver
11542 * instances support hot reset. The hot reset support will be updated
11543 * dynamically based on the driver interface advertisement.
11544 * If set to 0, then the adapter is not currently able to initiate
11547 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
11550 * If set to 1, then the PPP tx push mode is enabled for all the
11551 * reserved TX rings of this function. If set to 0, then PPP tx push
11552 * mode is disabled for all the reserved TX rings of this function.
11554 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
11557 * If set to 1, then the firmware will notify driver using async
11558 * event when a ring is disabled due to a Hardware error.
11560 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \
11563 * If set to 1, then the firmware and all currently registered driver
11564 * instances support fast reset. The fast reset support will be
11565 * updated dynamically based on the driver interface advertisement.
11566 * If set to 0, then the adapter is not currently able to initiate
11569 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \
11572 * If set to 1, then multi-root mode is active for this function.
11573 * The NIC is attached to a single host with a single operating
11574 * system, but through two or more PCIe endpoints.
11575 * If set to 0, then multi-root mode is inactive for this function
11576 * or not applicable for this device.
11578 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \
11581 * This value is current MAC address configured for this
11582 * function. A value of 00-00-00-00-00-00 indicates no
11583 * MAC address is currently configured.
11585 uint8_t mac_address[6];
11587 * This value is current PCI ID of this
11588 * function. If ARI is enabled, then it is
11589 * Bus Number (8b):Function Number(8b). Otherwise, it is
11590 * Bus Number (8b):Device Number (4b):Function Number(4b).
11591 * If multi-host mode is active, the 4 lsb will indicate
11592 * the PF index for this function.
11596 * The number of RSS/COS contexts currently
11597 * allocated to the function.
11599 uint16_t alloc_rsscos_ctx;
11601 * The number of completion rings currently allocated to
11602 * the function. This does not include the rings allocated
11603 * to any children functions if any.
11605 uint16_t alloc_cmpl_rings;
11607 * The number of transmit rings currently allocated to
11608 * the function. This does not include the rings allocated
11609 * to any children functions if any.
11611 uint16_t alloc_tx_rings;
11613 * The number of receive rings currently allocated to
11614 * the function. This does not include the rings allocated
11615 * to any children functions if any.
11617 uint16_t alloc_rx_rings;
11618 /* The allocated number of L2 contexts to the function. */
11619 uint16_t alloc_l2_ctx;
11620 /* The allocated number of vnics to the function. */
11621 uint16_t alloc_vnics;
11623 * The maximum transmission unit of the function.
11624 * If the reported mtu value is non-zero then it will used for the
11625 * rings allocated on this function. otherwise the default
11626 * value is used if ring MTU is not specified.
11630 * The maximum receive unit of the function.
11631 * For vnics allocated on this function, this default
11632 * value is used if vnic MRU is not specified.
11635 /* The statistics context assigned to a function. */
11636 uint16_t stat_ctx_id;
11638 * The HWRM shall return Unknown value for this field
11639 * when this command is used to query VF's configuration.
11641 uint8_t port_partition_type;
11642 /* Single physical function */
11643 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
11644 /* Multiple physical functions */
11645 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
11646 /* Network Partitioning 1.0 */
11647 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
11648 /* Network Partitioning 1.5 */
11649 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
11650 /* Network Partitioning 2.0 */
11651 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
11653 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
11655 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
11656 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
11658 * This field will indicate number of physical functions on this port_partition.
11659 * HWRM shall return unavail (i.e. value of 0) for this field
11660 * when this command is used to query VF's configuration or
11661 * from older firmware that doesn't support this field.
11663 uint8_t port_pf_cnt;
11664 /* number of PFs is not available */
11665 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
11666 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
11667 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
11669 * The default VNIC ID assigned to a function that is
11672 uint16_t dflt_vnic_id;
11673 uint16_t max_mtu_configured;
11675 * Minimum BW allocated for this function.
11676 * The HWRM will translate this value into byte counter and
11677 * time interval used for the scheduler inside the device.
11678 * A value of 0 indicates the minimum bandwidth is not
11682 /* The bandwidth value. */
11683 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
11684 UINT32_C(0xfffffff)
11685 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
11686 /* The granularity of the value (bits or bytes). */
11687 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
11688 UINT32_C(0x10000000)
11689 /* Value is in bits. */
11690 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
11691 (UINT32_C(0x0) << 28)
11692 /* Value is in bytes. */
11693 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
11694 (UINT32_C(0x1) << 28)
11695 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
11696 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
11697 /* bw_value_unit is 3 b */
11698 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
11699 UINT32_C(0xe0000000)
11700 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
11701 /* Value is in Mb or MB (base 10). */
11702 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
11703 (UINT32_C(0x0) << 29)
11704 /* Value is in Kb or KB (base 10). */
11705 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
11706 (UINT32_C(0x2) << 29)
11707 /* Value is in bits or bytes. */
11708 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
11709 (UINT32_C(0x4) << 29)
11710 /* Value is in Gb or GB (base 10). */
11711 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
11712 (UINT32_C(0x6) << 29)
11713 /* Value is in 1/100th of a percentage of total bandwidth. */
11714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
11715 (UINT32_C(0x1) << 29)
11717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
11718 (UINT32_C(0x7) << 29)
11719 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
11720 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
11722 * Maximum BW allocated for this function.
11723 * The HWRM will translate this value into byte counter and
11724 * time interval used for the scheduler inside the device.
11725 * A value of 0 indicates that the maximum bandwidth is not
11729 /* The bandwidth value. */
11730 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
11731 UINT32_C(0xfffffff)
11732 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
11733 /* The granularity of the value (bits or bytes). */
11734 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
11735 UINT32_C(0x10000000)
11736 /* Value is in bits. */
11737 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
11738 (UINT32_C(0x0) << 28)
11739 /* Value is in bytes. */
11740 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
11741 (UINT32_C(0x1) << 28)
11742 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
11743 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
11744 /* bw_value_unit is 3 b */
11745 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
11746 UINT32_C(0xe0000000)
11747 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
11748 /* Value is in Mb or MB (base 10). */
11749 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
11750 (UINT32_C(0x0) << 29)
11751 /* Value is in Kb or KB (base 10). */
11752 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
11753 (UINT32_C(0x2) << 29)
11754 /* Value is in bits or bytes. */
11755 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
11756 (UINT32_C(0x4) << 29)
11757 /* Value is in Gb or GB (base 10). */
11758 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
11759 (UINT32_C(0x6) << 29)
11760 /* Value is in 1/100th of a percentage of total bandwidth. */
11761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
11762 (UINT32_C(0x1) << 29)
11764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
11765 (UINT32_C(0x7) << 29)
11766 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
11767 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
11769 * This value indicates the Edge virtual bridge mode for the
11770 * domain that this function belongs to.
11773 /* No Edge Virtual Bridging (EVB) */
11774 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
11775 /* Virtual Ethernet Bridge (VEB) */
11776 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
11777 /* Virtual Ethernet Port Aggregator (VEPA) */
11778 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
11779 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
11780 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
11783 * This value indicates the PCIE device cache line size.
11784 * The cache line size allows the DMA writes to terminate and
11785 * start at the cache boundary.
11787 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
11789 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
11790 /* Cache Line Size 64 bytes */
11791 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
11793 /* Cache Line Size 128 bytes */
11794 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
11796 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
11797 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
11798 /* This value is the virtual link admin state setting. */
11799 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
11801 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
11802 /* Admin link state is in forced down mode. */
11803 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
11804 (UINT32_C(0x0) << 2)
11805 /* Admin link state is in forced up mode. */
11806 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
11807 (UINT32_C(0x1) << 2)
11808 /* Admin link state is in auto mode - follows the physical link state. */
11809 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
11810 (UINT32_C(0x2) << 2)
11811 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
11812 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
11813 /* Reserved for future. */
11814 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
11816 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
11818 * The number of VFs that are allocated to the function.
11819 * This is valid only on the PF with SR-IOV enabled.
11820 * 0xFF... (All Fs) if this command is called on a PF with
11821 * SR-IOV disabled or on a VF.
11823 uint16_t alloc_vfs;
11825 * The number of allocated multicast filters for this
11826 * function on the RX side.
11828 uint32_t alloc_mcast_filters;
11830 * The number of allocated HW ring groups for this
11833 uint32_t alloc_hw_ring_grps;
11835 * The number of strict priority transmit rings out of
11836 * currently allocated TX rings to the function
11837 * (alloc_tx_rings).
11839 uint16_t alloc_sp_tx_rings;
11841 * The number of statistics contexts
11842 * currently reserved for the function.
11844 uint16_t alloc_stat_ctx;
11846 * This field specifies how many NQs are reserved for the PF.
11847 * Remaining NQs that belong to the PF are available for VFs.
11848 * Once a PF has created VFs, it cannot change how many NQs are
11849 * reserved for itself (since the NQs must be contiguous in HW).
11851 uint16_t alloc_msix;
11853 * The number of registered VF’s associated with the PF. This field
11854 * should be ignored when the request received on the VF interface.
11855 * This field will be updated on the PF interface to initiate
11856 * the unregister request on PF in the HOT Reset Process.
11858 uint16_t registered_vfs;
11860 * The size of the doorbell BAR in KBytes reserved for L2 including
11861 * any area that is shared between L2 and RoCE. The L2 driver
11862 * should only map the L2 portion of the doorbell BAR. Any rounding
11863 * of the BAR size to the native CPU page size should be performed
11864 * by the driver. If the value is zero, no special partitioning
11865 * of the doorbell BAR between L2 and RoCE is required.
11867 uint16_t l2_doorbell_bar_size_kb;
11870 * For backward compatibility this field must be set to 1.
11871 * Older drivers might look for this field to be 1 before
11872 * processing the message.
11876 * This GRC address location is used by the Host driver interfaces to poll
11877 * the adapter ready state to re-initiate the registration process again
11878 * after receiving the RESET Notify event.
11880 uint32_t reset_addr_poll;
11882 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
11883 * this value to find out the doorbell page offset from the BAR.
11885 uint16_t legacy_l2_db_size_kb;
11886 uint16_t svif_info;
11888 * This field specifies the source virtual interface of the function being
11889 * queried. Drivers can use this to program svif field in the L2 context
11892 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
11893 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
11894 /* This field specifies whether svif is valid or not */
11895 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
11898 * When this bit is '1', it indicates that a MPC channel with
11899 * destination set to the TX crypto engine block is enabled.
11901 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED \
11904 * When this bit is '1', it indicates that a MPC channel with
11905 * destination set to the RX crypto engine block is enabled.
11907 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED \
11910 * When this bit is '1', it indicates that a MPC channel with
11911 * destination set to the TX configurable flow processing block is
11914 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED \
11917 * When this bit is '1', it indicates that a MPC channel with
11918 * destination set to the RX configurable flow processing block is
11921 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED \
11924 * When this bit is '1', it indicates that a MPC channel with
11925 * destination set to the primate processor block is enabled.
11927 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \
11929 uint8_t unused_2[6];
11931 * This field is used in Output records to indicate that the output
11932 * is completely written to RAM. This field should be read as '1'
11933 * to indicate that the output has been completely written.
11934 * When writing a command completion or response to an internal processor,
11935 * the order of writes has to be such that this field is written last.
11945 /* hwrm_func_cfg_input (size:768b/96B) */
11946 struct hwrm_func_cfg_input {
11947 /* The HWRM command request type. */
11950 * The completion ring to send the completion event on. This should
11951 * be the NQ ID returned from the `nq_alloc` HWRM command.
11953 uint16_t cmpl_ring;
11955 * The sequence ID is used by the driver for tracking multiple
11956 * commands. This ID is treated as opaque data by the firmware and
11957 * the value is returned in the `hwrm_resp_hdr` upon completion.
11961 * The target ID of the command:
11962 * * 0x0-0xFFF8 - The function ID
11963 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11964 * * 0xFFFD - Reserved for user-space HWRM interface
11967 uint16_t target_id;
11969 * A physical address pointer pointing to a host buffer that the
11970 * command's response data will be written. This can be either a host
11971 * physical address (HPA) or a guest physical address (GPA) and must
11972 * point to a physically contiguous block of memory.
11974 uint64_t resp_addr;
11976 * Function ID of the function that is being
11978 * If set to 0xFF... (All Fs), then the configuration is
11979 * for the requesting function.
11983 * This field specifies how many NQs will be reserved for the PF.
11984 * Remaining NQs that belong to the PF become available for VFs.
11985 * Once a PF has created VFs, it cannot change how many NQs are
11986 * reserved for itself (since the NQs must be contiguous in HW).
11991 * When this bit is '1', the function is disabled with
11992 * source MAC address check.
11993 * This is an anti-spoofing check. If this flag is set,
11994 * then the function shall be configured to disallow
11995 * transmission of frames with the source MAC address that
11996 * is configured for this function.
11998 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
12001 * When this bit is '1', the function is enabled with
12002 * source MAC address check.
12003 * This is an anti-spoofing check. If this flag is set,
12004 * then the function shall be configured to allow
12005 * transmission of frames with the source MAC address that
12006 * is configured for this function.
12008 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
12011 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
12013 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
12015 * Standard TX Ring mode is used for the allocation of TX ring
12016 * and underlying scheduling resources that allow bandwidth
12017 * reservation and limit settings on the queried function.
12018 * If set to 1, then standard TX ring mode is requested to be
12019 * enabled on the function being configured.
12021 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
12024 * Standard TX Ring mode is used for the allocation of TX ring
12025 * and underlying scheduling resources that allow bandwidth
12026 * reservation and limit settings on the queried function.
12027 * If set to 1, then the standard TX ring mode is requested to
12028 * be disabled on the function being configured. In this extended
12029 * TX ring resource mode, the minimum and maximum bandwidth settings
12030 * are not supported to allow the allocation of TX rings to
12031 * span multiple scheduler nodes.
12033 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
12036 * If this bit is set, virtual mac address configured
12037 * in this command will be persistent over warm boot.
12039 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
12042 * This bit only applies to the VF. If this bit is set, the statistic
12043 * context counters will not be cleared when the statistic context is freed
12044 * or a function reset is called on VF. This bit will be cleared when the PF
12045 * is unloaded or a function reset is called on the PF.
12047 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
12050 * This bit requests that the firmware test to see if all the assets
12051 * requested in this command (i.e. number of TX rings) are available.
12052 * The firmware will return an error if the requested assets are
12053 * not available. The firwmare will NOT reserve the assets if they
12056 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
12059 * This bit requests that the firmware test to see if all the assets
12060 * requested in this command (i.e. number of RX rings) are available.
12061 * The firmware will return an error if the requested assets are
12062 * not available. The firwmare will NOT reserve the assets if they
12065 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
12068 * This bit requests that the firmware test to see if all the assets
12069 * requested in this command (i.e. number of CMPL rings) are available.
12070 * The firmware will return an error if the requested assets are
12071 * not available. The firwmare will NOT reserve the assets if they
12074 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
12077 * This bit requests that the firmware test to see if all the assets
12078 * requested in this command (i.e. number of RSS ctx) are available.
12079 * The firmware will return an error if the requested assets are
12080 * not available. The firwmare will NOT reserve the assets if they
12083 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
12086 * This bit requests that the firmware test to see if all the assets
12087 * requested in this command (i.e. number of ring groups) are available.
12088 * The firmware will return an error if the requested assets are
12089 * not available. The firwmare will NOT reserve the assets if they
12092 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
12095 * This bit requests that the firmware test to see if all the assets
12096 * requested in this command (i.e. number of stat ctx) are available.
12097 * The firmware will return an error if the requested assets are
12098 * not available. The firwmare will NOT reserve the assets if they
12101 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
12104 * This bit requests that the firmware test to see if all the assets
12105 * requested in this command (i.e. number of VNICs) are available.
12106 * The firmware will return an error if the requested assets are
12107 * not available. The firwmare will NOT reserve the assets if they
12110 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
12113 * This bit requests that the firmware test to see if all the assets
12114 * requested in this command (i.e. number of L2 ctx) are available.
12115 * The firmware will return an error if the requested assets are
12116 * not available. The firwmare will NOT reserve the assets if they
12119 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
12122 * This configuration change can be initiated by a PF driver. This
12123 * configuration request shall be targeted to a VF. From local host
12124 * resident HWRM clients, only the parent PF driver shall be allowed
12125 * to initiate this change on one of its children VFs. If this bit is
12126 * set to 1, then the VF that is being configured is requested to be
12129 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
12132 * When this bit it set, even if PF reserved pool size is zero,
12133 * FW will allow driver to create TX rings in ring alloc,
12134 * by reserving TX ring, S3 node dynamically.
12136 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
12139 * This bit requests that the firmware test to see if all the assets
12140 * requested in this command (i.e. number of NQ rings) are available.
12141 * The firmware will return an error if the requested assets are
12142 * not available. The firwmare will NOT reserve the assets if they
12145 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
12148 * This configuration change can be initiated by a PF driver. This
12149 * configuration request shall be targeted to a VF. From local host
12150 * resident HWRM clients, only the parent PF driver shall be allowed
12151 * to initiate this change on one of its children VFs. If this bit is
12152 * set to 1, then the VF that is being configured is requested to be
12155 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
12156 UINT32_C(0x1000000)
12158 * This bit is used by preboot drivers on a PF that require access
12159 * to the legacy L2 ring model and legacy 32b doorbells. This
12160 * feature is not allowed on VFs and is only relevant for devices
12161 * that require a context backing store.
12163 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
12164 UINT32_C(0x2000000)
12166 * If this bit is set to 0, then the interface does not support hot
12167 * reset capability which it advertised with the hot_reset_support
12168 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
12169 * flag to 0, adapter cannot do the hot reset. In this state, if the
12170 * firmware receives a hot reset request, firmware must fail the
12171 * request. If this bit is set to 1, then interface is renabling the
12172 * hot reset capability.
12174 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
12175 UINT32_C(0x4000000)
12177 * If this bit is set to 1, the PF driver is requesting FW
12178 * to enable PPP TX PUSH feature on all the TX rings specified in
12179 * the num_tx_rings field. By default, the PPP TX push feature is
12180 * disabled for all the TX rings of the function. This flag is
12181 * ignored if num_tx_rings field is not specified or the function
12182 * doesn't support PPP tx push feature.
12184 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
12185 UINT32_C(0x8000000)
12187 * If this bit is set to 1, the PF driver is requesting FW
12188 * to disable PPP TX PUSH feature on all the TX rings specified in
12189 * the num_tx_rings field. This flag is ignored if num_tx_rings
12190 * field is not specified or the function doesn't support PPP tx
12193 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \
12194 UINT32_C(0x10000000)
12196 * If this bit is set to 1, the driver is requesting FW to enable
12197 * the BD_METADATA feature for this function. The FW returns error
12198 * on this request if the TX_METADATA is enabled for this function.
12200 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \
12201 UINT32_C(0x20000000)
12203 * If this bit is set to 1, the driver is requesting FW to disable
12204 * the BD_METADATA feature for this function. The FW returns error
12205 * on this request if the TX_METADATA is enabled for this function.
12207 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \
12208 UINT32_C(0x40000000)
12211 * This bit must be '1' for the mtu field to be
12214 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
12217 * This bit must be '1' for the mru field to be
12220 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
12223 * This bit must be '1' for the num_rsscos_ctxs field to be
12226 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
12229 * This bit must be '1' for the num_cmpl_rings field to be
12232 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
12235 * This bit must be '1' for the num_tx_rings field to be
12238 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
12241 * This bit must be '1' for the num_rx_rings field to be
12244 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
12247 * This bit must be '1' for the num_l2_ctxs field to be
12250 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
12253 * This bit must be '1' for the num_vnics field to be
12256 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
12259 * This bit must be '1' for the num_stat_ctxs field to be
12262 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
12265 * This bit must be '1' for the dflt_mac_addr field to be
12268 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
12271 * This bit must be '1' for the dflt_vlan field to be
12274 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
12277 * This bit must be '1' for the dflt_ip_addr field to be
12280 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
12283 * This bit must be '1' for the min_bw field to be
12286 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
12289 * This bit must be '1' for the max_bw field to be
12292 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
12295 * This bit must be '1' for the async_event_cr field to be
12298 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
12301 * This bit must be '1' for the vlan_antispoof_mode field to be
12304 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
12307 * This bit must be '1' for the allowed_vlan_pris field to be
12310 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
12313 * This bit must be '1' for the evb_mode field to be
12316 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
12319 * This bit must be '1' for the num_mcast_filters field to be
12322 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
12325 * This bit must be '1' for the num_hw_ring_grps field to be
12328 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
12331 * This bit must be '1' for the cache_linesize field to be
12334 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
12337 * This bit must be '1' for the num_msix field to be
12340 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
12343 * This bit must be '1' for the link admin state field to be
12346 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
12349 * This bit must be '1' for the hot_reset_if_en_dis field to be
12352 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
12355 * This bit must be '1' for the schq_id field to be
12358 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID \
12359 UINT32_C(0x1000000)
12361 * This bit must be '1' for the mpc_chnls field to be
12364 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS \
12365 UINT32_C(0x2000000)
12367 * The maximum transmission unit of the function.
12368 * The HWRM should make sure that the mtu of
12369 * the function does not exceed the mtu of the physical
12370 * port that this function is associated with.
12372 * In addition to configuring mtu per function, it is
12373 * possible to configure mtu per transmit ring.
12374 * By default, the mtu of each transmit ring associated
12375 * with a function is equal to the mtu of the function.
12376 * The HWRM should make sure that the mtu of each transmit
12377 * ring that is assigned to a function has a valid mtu.
12381 * The maximum receive unit of the function.
12382 * The HWRM should make sure that the mru of
12383 * the function does not exceed the mru of the physical
12384 * port that this function is associated with.
12386 * In addition to configuring mru per function, it is
12387 * possible to configure mru per vnic.
12388 * By default, the mru of each vnic associated
12389 * with a function is equal to the mru of the function.
12390 * The HWRM should make sure that the mru of each vnic
12391 * that is assigned to a function has a valid mru.
12395 * The number of RSS/COS contexts requested for the
12398 uint16_t num_rsscos_ctxs;
12400 * The number of completion rings requested for the
12401 * function. This does not include the rings allocated
12402 * to any children functions if any.
12404 uint16_t num_cmpl_rings;
12406 * The number of transmit rings requested for the function.
12407 * This does not include the rings allocated to any
12408 * children functions if any.
12410 uint16_t num_tx_rings;
12412 * The number of receive rings requested for the function.
12413 * This does not include the rings allocated
12414 * to any children functions if any.
12416 uint16_t num_rx_rings;
12417 /* The requested number of L2 contexts for the function. */
12418 uint16_t num_l2_ctxs;
12419 /* The requested number of vnics for the function. */
12420 uint16_t num_vnics;
12421 /* The requested number of statistic contexts for the function. */
12422 uint16_t num_stat_ctxs;
12424 * The number of HW ring groups that should
12425 * be reserved for this function.
12427 uint16_t num_hw_ring_grps;
12428 /* The default MAC address for the function being configured. */
12429 uint8_t dflt_mac_addr[6];
12431 * The default VLAN for the function being configured.
12432 * This field's format is same as 802.1Q Tag's
12433 * Tag Control Information (TCI) format that includes both
12434 * Priority Code Point (PCP) and VLAN Identifier (VID).
12436 uint16_t dflt_vlan;
12438 * The default IP address for the function being configured.
12439 * This address is only used in enabling source property check.
12441 uint32_t dflt_ip_addr[4];
12443 * Minimum BW allocated for this function.
12444 * The HWRM will translate this value into byte counter and
12445 * time interval used for the scheduler inside the device.
12448 /* The bandwidth value. */
12449 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
12450 UINT32_C(0xfffffff)
12451 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
12452 /* The granularity of the value (bits or bytes). */
12453 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
12454 UINT32_C(0x10000000)
12455 /* Value is in bits. */
12456 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
12457 (UINT32_C(0x0) << 28)
12458 /* Value is in bytes. */
12459 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
12460 (UINT32_C(0x1) << 28)
12461 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
12462 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
12463 /* bw_value_unit is 3 b */
12464 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
12465 UINT32_C(0xe0000000)
12466 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
12467 /* Value is in Mb or MB (base 10). */
12468 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
12469 (UINT32_C(0x0) << 29)
12470 /* Value is in Kb or KB (base 10). */
12471 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
12472 (UINT32_C(0x2) << 29)
12473 /* Value is in bits or bytes. */
12474 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
12475 (UINT32_C(0x4) << 29)
12476 /* Value is in Gb or GB (base 10). */
12477 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
12478 (UINT32_C(0x6) << 29)
12479 /* Value is in 1/100th of a percentage of total bandwidth. */
12480 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
12481 (UINT32_C(0x1) << 29)
12483 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
12484 (UINT32_C(0x7) << 29)
12485 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
12486 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
12488 * Maximum BW allocated for this function.
12489 * The HWRM will translate this value into byte counter and
12490 * time interval used for the scheduler inside the device.
12493 /* The bandwidth value. */
12494 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
12495 UINT32_C(0xfffffff)
12496 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
12497 /* The granularity of the value (bits or bytes). */
12498 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
12499 UINT32_C(0x10000000)
12500 /* Value is in bits. */
12501 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
12502 (UINT32_C(0x0) << 28)
12503 /* Value is in bytes. */
12504 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
12505 (UINT32_C(0x1) << 28)
12506 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
12507 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
12508 /* bw_value_unit is 3 b */
12509 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
12510 UINT32_C(0xe0000000)
12511 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
12512 /* Value is in Mb or MB (base 10). */
12513 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
12514 (UINT32_C(0x0) << 29)
12515 /* Value is in Kb or KB (base 10). */
12516 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
12517 (UINT32_C(0x2) << 29)
12518 /* Value is in bits or bytes. */
12519 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
12520 (UINT32_C(0x4) << 29)
12521 /* Value is in Gb or GB (base 10). */
12522 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
12523 (UINT32_C(0x6) << 29)
12524 /* Value is in 1/100th of a percentage of total bandwidth. */
12525 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
12526 (UINT32_C(0x1) << 29)
12528 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
12529 (UINT32_C(0x7) << 29)
12530 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
12531 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
12533 * ID of the target completion ring for receiving asynchronous
12534 * event completions. If this field is not valid, then the
12535 * HWRM shall use the default completion ring of the function
12536 * that is being configured as the target completion ring for
12537 * providing any asynchronous event completions for that
12539 * If this field is valid, then the HWRM shall use the
12540 * completion ring identified by this ID as the target
12541 * completion ring for providing any asynchronous event
12542 * completions for the function that is being configured.
12544 uint16_t async_event_cr;
12545 /* VLAN Anti-spoofing mode. */
12546 uint8_t vlan_antispoof_mode;
12547 /* No VLAN anti-spoofing checks are enabled */
12548 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
12550 /* Validate VLAN against the configured VLAN(s) */
12551 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
12553 /* Insert VLAN if it does not exist, otherwise discard */
12554 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
12556 /* Insert VLAN if it does not exist, override VLAN if it exists */
12557 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
12559 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
12560 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
12562 * This bit field defines VLAN PRIs that are allowed on
12564 * If nth bit is set, then VLAN PRI n is allowed on this
12567 uint8_t allowed_vlan_pris;
12569 * The evb_mode is configured on a per port basis. The default evb_mode
12570 * is configured based on the NVM EVB mode setting upon firmware
12571 * initialization. The HWRM allows a PF driver to change EVB mode for a
12572 * port used by the PF only when one of the following conditions is
12574 * 1. The current operating mode is single function mode.
12575 * (ie. one PF per port)
12576 * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the
12577 * EVB mode of the port used by the PAXC PF. None of the X86 PFs
12578 * should have privileges.
12579 * The HWRM doesn't permit any PFs to change the underlying EVB mode
12580 * when running as MHB or NPAR mode in performance NIC configuration.
12581 * The HWRM doesn't permit a VF driver to change the EVB mode.
12582 * Once the HWRM determines a function doesn't meet the conditions
12583 * to configure the EVB mode, it sets the evb_mode_cfg_not_supported
12584 * flag in HWRM_FUNC_QCAPS command response for the function.
12585 * The HWRM takes into account the switching of EVB mode from one to
12586 * another and reconfigure hardware resources as reqiured. The
12587 * switching from VEB to VEPA mode requires the disabling of the
12588 * loopback traffic. Additionally, source knockouts are handled
12589 * differently in VEB and VEPA modes.
12592 /* No Edge Virtual Bridging (EVB) */
12593 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
12594 /* Virtual Ethernet Bridge (VEB) */
12595 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
12596 /* Virtual Ethernet Port Aggregator (VEPA) */
12597 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
12598 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
12599 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
12602 * This value indicates the PCIE device cache line size.
12603 * The cache line size allows the DMA writes to terminate and
12604 * start at the cache boundary.
12606 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
12608 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
12609 /* Cache Line Size 64 bytes */
12610 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
12612 /* Cache Line Size 128 bytes */
12613 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
12615 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
12616 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
12617 /* This value is the virtual link admin state setting. */
12618 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
12620 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
12621 /* Admin state is forced down. */
12622 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
12623 (UINT32_C(0x0) << 2)
12624 /* Admin state is forced up. */
12625 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
12626 (UINT32_C(0x1) << 2)
12627 /* Admin state is in auto mode - is to follow the physical link state. */
12628 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
12629 (UINT32_C(0x2) << 2)
12630 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
12631 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
12632 /* Reserved for future. */
12633 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
12635 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
12637 * The number of multicast filters that should
12638 * be reserved for this function on the RX side.
12640 uint16_t num_mcast_filters;
12641 /* Used by a PF driver to associate a SCHQ with a VF. */
12643 uint16_t mpc_chnls;
12645 * When this bit is '1', the caller requests to enable a MPC
12646 * channel with destination to the TX crypto engine block.
12647 * When this bit is ‘0’, this flag has no effect.
12649 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
12651 * When this bit is '1', the caller requests to disable a MPC
12652 * channel with destination to the TX crypto engine block.
12653 * When this bit is ‘0’, this flag has no effect.
12655 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
12657 * When this bit is '1', the caller requests to enable a MPC
12658 * channel with destination to the RX crypto engine block.
12659 * When this bit is ‘0’, this flag has no effect.
12661 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
12663 * When this bit is '1', the caller requests to disable a MPC
12664 * channel with destination to the RX crypto engine block.
12665 * When this bit is ‘0’, this flag has no effect.
12667 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
12669 * When this bit is '1', the caller requests to enable a MPC
12670 * channel with destination to the TX configurable flow processing
12671 * block. When this bit is ‘0’, this flag has no effect.
12673 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE \
12676 * When this bit is '1', the caller requests to disable a MPC
12677 * channel with destination to the TX configurable flow processing
12678 * block. When this bit is ‘0’, this flag has no effect.
12680 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \
12683 * When this bit is '1', the caller requests to enable a MPC
12684 * channel with destination to the RX configurable flow processing
12685 * block. When this bit is ‘0’, this flag has no effect.
12687 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE \
12690 * When this bit is '1', the caller requests to disable a MPC
12691 * channel with destination to the RX configurable flow processing
12692 * block. When this bit is ‘0’, this flag has no effect.
12694 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \
12697 * When this bit is '1', the caller requests to enable a MPC
12698 * channel with destination to the primate processor block.
12699 * When this bit is ‘0’, this flag has no effect.
12701 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE \
12704 * When this bit is '1', the caller requests to disable a MPC
12705 * channel with destination to the primate processor block.
12706 * When this bit is ‘0’, this flag has no effect.
12708 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE \
12710 uint8_t unused_0[4];
12713 /* hwrm_func_cfg_output (size:128b/16B) */
12714 struct hwrm_func_cfg_output {
12715 /* The specific error status for the command. */
12716 uint16_t error_code;
12717 /* The HWRM command request type. */
12719 /* The sequence ID from the original command. */
12721 /* The length of the response data in number of bytes. */
12723 uint8_t unused_0[7];
12725 * This field is used in Output records to indicate that the output
12726 * is completely written to RAM. This field should be read as '1'
12727 * to indicate that the output has been completely written.
12728 * When writing a command completion or response to an internal processor,
12729 * the order of writes has to be such that this field is written last.
12734 /********************
12735 * hwrm_func_qstats *
12736 ********************/
12739 /* hwrm_func_qstats_input (size:192b/24B) */
12740 struct hwrm_func_qstats_input {
12741 /* The HWRM command request type. */
12744 * The completion ring to send the completion event on. This should
12745 * be the NQ ID returned from the `nq_alloc` HWRM command.
12747 uint16_t cmpl_ring;
12749 * The sequence ID is used by the driver for tracking multiple
12750 * commands. This ID is treated as opaque data by the firmware and
12751 * the value is returned in the `hwrm_resp_hdr` upon completion.
12755 * The target ID of the command:
12756 * * 0x0-0xFFF8 - The function ID
12757 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12758 * * 0xFFFD - Reserved for user-space HWRM interface
12761 uint16_t target_id;
12763 * A physical address pointer pointing to a host buffer that the
12764 * command's response data will be written. This can be either a host
12765 * physical address (HPA) or a guest physical address (GPA) and must
12766 * point to a physically contiguous block of memory.
12768 uint64_t resp_addr;
12770 * Function ID of the function that is being queried.
12771 * 0xFF... (All Fs) if the query is for the requesting
12773 * A privileged PF can query for other function's statistics.
12776 /* This flags indicates the type of statistics request. */
12778 /* This value is not used to avoid backward compatibility issues. */
12779 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12781 * flags should be set to 1 when request is for only RoCE statistics.
12782 * This will be honored only if the caller_fid is a privileged PF.
12783 * In all other cases FID and caller_fid should be the same.
12785 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12787 * flags should be set to 2 when request is for the counter mask,
12788 * representing the width of each of the stats counters, rather
12789 * than counters themselves.
12791 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12792 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
12793 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
12794 uint8_t unused_0[5];
12797 /* hwrm_func_qstats_output (size:1408b/176B) */
12798 struct hwrm_func_qstats_output {
12799 /* The specific error status for the command. */
12800 uint16_t error_code;
12801 /* The HWRM command request type. */
12803 /* The sequence ID from the original command. */
12805 /* The length of the response data in number of bytes. */
12807 /* Number of transmitted unicast packets on the function. */
12808 uint64_t tx_ucast_pkts;
12809 /* Number of transmitted multicast packets on the function. */
12810 uint64_t tx_mcast_pkts;
12811 /* Number of transmitted broadcast packets on the function. */
12812 uint64_t tx_bcast_pkts;
12814 * Number of transmitted packets that were discarded due to
12815 * internal NIC resource problems. For transmit, this
12816 * can only happen if TMP is configured to allow dropping
12817 * in HOL blocking conditions, which is not a normal
12820 uint64_t tx_discard_pkts;
12822 * Number of dropped packets on transmit path on the function.
12823 * These are packets that have been marked for drop by
12824 * the TE CFA block or are packets that exceeded the
12825 * transmit MTU limit for the function.
12827 uint64_t tx_drop_pkts;
12828 /* Number of transmitted bytes for unicast traffic on the function. */
12829 uint64_t tx_ucast_bytes;
12830 /* Number of transmitted bytes for multicast traffic on the function. */
12831 uint64_t tx_mcast_bytes;
12832 /* Number of transmitted bytes for broadcast traffic on the function. */
12833 uint64_t tx_bcast_bytes;
12834 /* Number of received unicast packets on the function. */
12835 uint64_t rx_ucast_pkts;
12836 /* Number of received multicast packets on the function. */
12837 uint64_t rx_mcast_pkts;
12838 /* Number of received broadcast packets on the function. */
12839 uint64_t rx_bcast_pkts;
12841 * Number of received packets that were discarded on the function
12842 * due to resource limitations. This can happen for 3 reasons.
12843 * # The BD used for the packet has a bad format.
12844 * # There were no BDs available in the ring for the packet.
12845 * # There were no BDs available on-chip for the packet.
12847 uint64_t rx_discard_pkts;
12849 * Number of dropped packets on received path on the function.
12850 * These are packets that have been marked for drop by the
12853 uint64_t rx_drop_pkts;
12854 /* Number of received bytes for unicast traffic on the function. */
12855 uint64_t rx_ucast_bytes;
12856 /* Number of received bytes for multicast traffic on the function. */
12857 uint64_t rx_mcast_bytes;
12858 /* Number of received bytes for broadcast traffic on the function. */
12859 uint64_t rx_bcast_bytes;
12860 /* Number of aggregated unicast packets on the function. */
12861 uint64_t rx_agg_pkts;
12862 /* Number of aggregated unicast bytes on the function. */
12863 uint64_t rx_agg_bytes;
12864 /* Number of aggregation events on the function. */
12865 uint64_t rx_agg_events;
12866 /* Number of aborted aggregations on the function. */
12867 uint64_t rx_agg_aborts;
12868 uint8_t unused_0[7];
12870 * This field is used in Output records to indicate that the output
12871 * is completely written to RAM. This field should be read as '1'
12872 * to indicate that the output has been completely written.
12873 * When writing a command completion or response to an internal processor,
12874 * the order of writes has to be such that this field is written last.
12879 /************************
12880 * hwrm_func_qstats_ext *
12881 ************************/
12884 /* hwrm_func_qstats_ext_input (size:256b/32B) */
12885 struct hwrm_func_qstats_ext_input {
12886 /* The HWRM command request type. */
12889 * The completion ring to send the completion event on. This should
12890 * be the NQ ID returned from the `nq_alloc` HWRM command.
12892 uint16_t cmpl_ring;
12894 * The sequence ID is used by the driver for tracking multiple
12895 * commands. This ID is treated as opaque data by the firmware and
12896 * the value is returned in the `hwrm_resp_hdr` upon completion.
12900 * The target ID of the command:
12901 * * 0x0-0xFFF8 - The function ID
12902 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
12903 * * 0xFFFD - Reserved for user-space HWRM interface
12906 uint16_t target_id;
12908 * A physical address pointer pointing to a host buffer that the
12909 * command's response data will be written. This can be either a host
12910 * physical address (HPA) or a guest physical address (GPA) and must
12911 * point to a physically contiguous block of memory.
12913 uint64_t resp_addr;
12915 * Function ID of the function that is being queried.
12916 * 0xFF... (All Fs) if the query is for the requesting
12918 * A privileged PF can query for other function's statistics.
12921 /* This flags indicates the type of statistics request. */
12923 /* This value is not used to avoid backward compatibility issues. */
12924 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
12926 * flags should be set to 1 when request is for only RoCE statistics.
12927 * This will be honored only if the caller_fid is a privileged PF.
12928 * In all other cases FID and caller_fid should be the same.
12930 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
12932 * flags should be set to 2 when request is for the counter mask
12933 * representing the width of each of the stats counters, rather
12934 * than counters themselves.
12936 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
12937 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
12938 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
12939 uint8_t unused_0[1];
12942 * This bit must be '1' for the schq_id and traffic_class fields to
12945 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
12946 /* Specifies the SCHQ for which to gather statistics */
12949 * Specifies the traffic class for which to gather statistics. Valid
12950 * values are 0 through (max_configurable_queues - 1), where
12951 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
12953 uint16_t traffic_class;
12954 uint8_t unused_1[4];
12957 /* hwrm_func_qstats_ext_output (size:1536b/192B) */
12958 struct hwrm_func_qstats_ext_output {
12959 /* The specific error status for the command. */
12960 uint16_t error_code;
12961 /* The HWRM command request type. */
12963 /* The sequence ID from the original command. */
12965 /* The length of the response data in number of bytes. */
12967 /* Number of received unicast packets */
12968 uint64_t rx_ucast_pkts;
12969 /* Number of received multicast packets */
12970 uint64_t rx_mcast_pkts;
12971 /* Number of received broadcast packets */
12972 uint64_t rx_bcast_pkts;
12973 /* Number of discarded packets on received path */
12974 uint64_t rx_discard_pkts;
12975 /* Number of packets on receive path with error */
12976 uint64_t rx_error_pkts;
12977 /* Number of received bytes for unicast traffic */
12978 uint64_t rx_ucast_bytes;
12979 /* Number of received bytes for multicast traffic */
12980 uint64_t rx_mcast_bytes;
12981 /* Number of received bytes for broadcast traffic */
12982 uint64_t rx_bcast_bytes;
12983 /* Number of transmitted unicast packets */
12984 uint64_t tx_ucast_pkts;
12985 /* Number of transmitted multicast packets */
12986 uint64_t tx_mcast_pkts;
12987 /* Number of transmitted broadcast packets */
12988 uint64_t tx_bcast_pkts;
12989 /* Number of packets on transmit path with error */
12990 uint64_t tx_error_pkts;
12991 /* Number of discarded packets on transmit path */
12992 uint64_t tx_discard_pkts;
12993 /* Number of transmitted bytes for unicast traffic */
12994 uint64_t tx_ucast_bytes;
12995 /* Number of transmitted bytes for multicast traffic */
12996 uint64_t tx_mcast_bytes;
12997 /* Number of transmitted bytes for broadcast traffic */
12998 uint64_t tx_bcast_bytes;
12999 /* Number of TPA eligible packets */
13000 uint64_t rx_tpa_eligible_pkt;
13001 /* Number of TPA eligible bytes */
13002 uint64_t rx_tpa_eligible_bytes;
13003 /* Number of TPA packets */
13004 uint64_t rx_tpa_pkt;
13005 /* Number of TPA bytes */
13006 uint64_t rx_tpa_bytes;
13007 /* Number of TPA errors */
13008 uint64_t rx_tpa_errors;
13009 /* Number of TPA errors */
13010 uint64_t rx_tpa_events;
13011 uint8_t unused_0[7];
13013 * This field is used in Output records to indicate that the output
13014 * is completely written to RAM. This field should be read as '1'
13015 * to indicate that the output has been completely written.
13016 * When writing a command completion or response to an internal processor,
13017 * the order of writes has to be such that this field is written last.
13022 /***********************
13023 * hwrm_func_clr_stats *
13024 ***********************/
13027 /* hwrm_func_clr_stats_input (size:192b/24B) */
13028 struct hwrm_func_clr_stats_input {
13029 /* The HWRM command request type. */
13032 * The completion ring to send the completion event on. This should
13033 * be the NQ ID returned from the `nq_alloc` HWRM command.
13035 uint16_t cmpl_ring;
13037 * The sequence ID is used by the driver for tracking multiple
13038 * commands. This ID is treated as opaque data by the firmware and
13039 * the value is returned in the `hwrm_resp_hdr` upon completion.
13043 * The target ID of the command:
13044 * * 0x0-0xFFF8 - The function ID
13045 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13046 * * 0xFFFD - Reserved for user-space HWRM interface
13049 uint16_t target_id;
13051 * A physical address pointer pointing to a host buffer that the
13052 * command's response data will be written. This can be either a host
13053 * physical address (HPA) or a guest physical address (GPA) and must
13054 * point to a physically contiguous block of memory.
13056 uint64_t resp_addr;
13058 * Function ID of the function.
13059 * 0xFF... (All Fs) if the query is for the requesting
13063 uint8_t unused_0[6];
13066 /* hwrm_func_clr_stats_output (size:128b/16B) */
13067 struct hwrm_func_clr_stats_output {
13068 /* The specific error status for the command. */
13069 uint16_t error_code;
13070 /* The HWRM command request type. */
13072 /* The sequence ID from the original command. */
13074 /* The length of the response data in number of bytes. */
13076 uint8_t unused_0[7];
13078 * This field is used in Output records to indicate that the output
13079 * is completely written to RAM. This field should be read as '1'
13080 * to indicate that the output has been completely written.
13081 * When writing a command completion or response to an internal processor,
13082 * the order of writes has to be such that this field is written last.
13087 /**************************
13088 * hwrm_func_vf_resc_free *
13089 **************************/
13092 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
13093 struct hwrm_func_vf_resc_free_input {
13094 /* The HWRM command request type. */
13097 * The completion ring to send the completion event on. This should
13098 * be the NQ ID returned from the `nq_alloc` HWRM command.
13100 uint16_t cmpl_ring;
13102 * The sequence ID is used by the driver for tracking multiple
13103 * commands. This ID is treated as opaque data by the firmware and
13104 * the value is returned in the `hwrm_resp_hdr` upon completion.
13108 * The target ID of the command:
13109 * * 0x0-0xFFF8 - The function ID
13110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13111 * * 0xFFFD - Reserved for user-space HWRM interface
13114 uint16_t target_id;
13116 * A physical address pointer pointing to a host buffer that the
13117 * command's response data will be written. This can be either a host
13118 * physical address (HPA) or a guest physical address (GPA) and must
13119 * point to a physically contiguous block of memory.
13121 uint64_t resp_addr;
13123 * This value is used to identify a Virtual Function (VF).
13124 * The scope of VF ID is local within a PF.
13127 uint8_t unused_0[6];
13130 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
13131 struct hwrm_func_vf_resc_free_output {
13132 /* The specific error status for the command. */
13133 uint16_t error_code;
13134 /* The HWRM command request type. */
13136 /* The sequence ID from the original command. */
13138 /* The length of the response data in number of bytes. */
13140 uint8_t unused_0[7];
13142 * This field is used in Output records to indicate that the output
13143 * is completely written to RAM. This field should be read as '1'
13144 * to indicate that the output has been completely written.
13145 * When writing a command completion or response to an internal processor,
13146 * the order of writes has to be such that this field is written last.
13151 /**********************
13152 * hwrm_func_drv_rgtr *
13153 **********************/
13156 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
13157 struct hwrm_func_drv_rgtr_input {
13158 /* The HWRM command request type. */
13161 * The completion ring to send the completion event on. This should
13162 * be the NQ ID returned from the `nq_alloc` HWRM command.
13164 uint16_t cmpl_ring;
13166 * The sequence ID is used by the driver for tracking multiple
13167 * commands. This ID is treated as opaque data by the firmware and
13168 * the value is returned in the `hwrm_resp_hdr` upon completion.
13172 * The target ID of the command:
13173 * * 0x0-0xFFF8 - The function ID
13174 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13175 * * 0xFFFD - Reserved for user-space HWRM interface
13178 uint16_t target_id;
13180 * A physical address pointer pointing to a host buffer that the
13181 * command's response data will be written. This can be either a host
13182 * physical address (HPA) or a guest physical address (GPA) and must
13183 * point to a physically contiguous block of memory.
13185 uint64_t resp_addr;
13188 * When this bit is '1', the function driver is requesting
13189 * all requests from its children VF drivers to be
13190 * forwarded to itself.
13191 * This flag can only be set by the PF driver.
13192 * If a VF driver sets this flag, it should be ignored
13195 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
13198 * When this bit is '1', the function is requesting none of
13199 * the requests from its children VF drivers to be
13200 * forwarded to itself.
13201 * This flag can only be set by the PF driver.
13202 * If a VF driver sets this flag, it should be ignored
13205 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
13208 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
13209 * fields shall be ignored and ver_maj, ver_min, ver_upd
13210 * and ver_patch shall be used for the driver version information.
13211 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
13212 * fields shall be used for the driver version information and
13213 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
13215 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
13218 * When this bit is '1', the function is indicating support of
13219 * 64bit flow handle. The firmware that only supports 64bit flow
13220 * handle should check this bit before allowing processing of
13221 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
13222 * with 64bit flow handle support can only be compatible with drivers
13223 * that support 64bit flow handle. The legacy drivers that don't support
13224 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
13225 * running with new firmware that only supports 64bit flow handle. The new
13226 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
13227 * status to the legacy driver when encounters these commands.
13229 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
13232 * When this bit is '1', the function is indicating support of
13233 * Hot Reset. The driver interface will destroy the resources,
13234 * unregister the function and register again up on receiving
13235 * the RESET_NOTIFY Async notification from the core firmware.
13236 * The core firmware will this use flag and trigger the Hot Reset
13237 * process only if all the registered driver instances are capable
13240 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
13243 * When this bit is 1, the function is indicating the support of the
13244 * error recovery capability. Error recovery support will be used by
13245 * firmware only if all the driver instances support error recovery
13246 * process. By setting this bit, driver is indicating support for
13247 * corresponding async event completion message. These will be
13248 * delivered to the driver even if they did not register for it.
13249 * If supported, after receiving reset notify async event with fatal
13250 * flag set in event data1, then all the drivers have to tear down
13251 * their resources without sending any HWRM commands to FW.
13253 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
13256 * When this bit is 1, the function is indicating the support of the
13257 * Master capability. The Firmware will use this capability to select the
13258 * Master function. The master function will be used to initiate
13259 * designated functionality like error recovery etc… If none of the
13260 * registered PF’s or trusted VF’s indicate this support, then
13261 * firmware will select the 1st registered PF as Master capable instance.
13263 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
13266 * When this bit is 1, the function is indicating the support of the
13267 * fast reset capability. Fast reset support will be used by
13268 * firmware only if all the driver instances support fast reset
13269 * process. By setting this bit, driver is indicating support for
13270 * corresponding async event completion message. These will be
13271 * delivered to the driver even if they did not register for it.
13272 * If supported, after receiving reset notify async event with fast
13273 * reset flag set in event data1, then all the drivers have to tear
13274 * down their resources without sending any HWRM commands to FW.
13276 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \
13280 * This bit must be '1' for the os_type field to be
13283 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
13286 * This bit must be '1' for the ver field to be
13289 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
13292 * This bit must be '1' for the timestamp field to be
13295 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
13298 * This bit must be '1' for the vf_req_fwd field to be
13301 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
13304 * This bit must be '1' for the async_event_fwd field to be
13307 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
13309 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13312 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13313 /* Other OS not listed below. */
13314 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
13316 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13318 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13320 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13322 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
13324 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13325 /* VMware ESXi OS. */
13326 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
13327 /* Microsoft Windows 8 64-bit OS. */
13328 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13329 /* Microsoft Windows Server 2012 R2 OS. */
13330 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13332 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13333 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
13334 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
13335 /* This is the 8bit major version of the driver. */
13336 uint8_t ver_maj_8b;
13337 /* This is the 8bit minor version of the driver. */
13338 uint8_t ver_min_8b;
13339 /* This is the 8bit update version of the driver. */
13340 uint8_t ver_upd_8b;
13341 uint8_t unused_0[3];
13343 * This is a 32-bit timestamp provided by the driver for
13345 * The timestamp is in multiples of 1ms.
13347 uint32_t timestamp;
13348 uint8_t unused_1[4];
13350 * This is a 256-bit bit mask provided by the PF driver for
13351 * letting the HWRM know what commands issued by the VF driver
13352 * to the HWRM should be forwarded to the PF driver.
13353 * Nth bit refers to the Nth req_type.
13355 * Setting Nth bit to 1 indicates that requests from the
13356 * VF driver with req_type equal to N shall be forwarded to
13357 * the parent PF driver.
13359 * This field is not valid for the VF driver.
13361 uint32_t vf_req_fwd[8];
13363 * This is a 256-bit bit mask provided by the function driver
13364 * (PF or VF driver) to indicate the list of asynchronous event
13365 * completions to be forwarded.
13367 * Nth bit refers to the Nth event_id.
13369 * Setting Nth bit to 1 by the function driver shall result in
13370 * the HWRM forwarding asynchronous event completion with
13371 * event_id equal to N.
13373 * If all bits are set to 0 (value of 0), then the HWRM shall
13374 * not forward any asynchronous event completion to this
13377 uint32_t async_event_fwd[8];
13378 /* This is the 16bit major version of the driver. */
13380 /* This is the 16bit minor version of the driver. */
13382 /* This is the 16bit update version of the driver. */
13384 /* This is the 16bit patch version of the driver. */
13385 uint16_t ver_patch;
13388 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
13389 struct hwrm_func_drv_rgtr_output {
13390 /* The specific error status for the command. */
13391 uint16_t error_code;
13392 /* The HWRM command request type. */
13394 /* The sequence ID from the original command. */
13396 /* The length of the response data in number of bytes. */
13400 * When this bit is '1', it indicates that the
13401 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
13403 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
13405 uint8_t unused_0[3];
13407 * This field is used in Output records to indicate that the output
13408 * is completely written to RAM. This field should be read as '1'
13409 * to indicate that the output has been completely written.
13410 * When writing a command completion or response to an internal processor,
13411 * the order of writes has to be such that this field is written last.
13416 /************************
13417 * hwrm_func_drv_unrgtr *
13418 ************************/
13421 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
13422 struct hwrm_func_drv_unrgtr_input {
13423 /* The HWRM command request type. */
13426 * The completion ring to send the completion event on. This should
13427 * be the NQ ID returned from the `nq_alloc` HWRM command.
13429 uint16_t cmpl_ring;
13431 * The sequence ID is used by the driver for tracking multiple
13432 * commands. This ID is treated as opaque data by the firmware and
13433 * the value is returned in the `hwrm_resp_hdr` upon completion.
13437 * The target ID of the command:
13438 * * 0x0-0xFFF8 - The function ID
13439 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13440 * * 0xFFFD - Reserved for user-space HWRM interface
13443 uint16_t target_id;
13445 * A physical address pointer pointing to a host buffer that the
13446 * command's response data will be written. This can be either a host
13447 * physical address (HPA) or a guest physical address (GPA) and must
13448 * point to a physically contiguous block of memory.
13450 uint64_t resp_addr;
13453 * When this bit is '1', the function driver is notifying
13454 * the HWRM to prepare for the shutdown.
13456 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
13458 uint8_t unused_0[4];
13461 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
13462 struct hwrm_func_drv_unrgtr_output {
13463 /* The specific error status for the command. */
13464 uint16_t error_code;
13465 /* The HWRM command request type. */
13467 /* The sequence ID from the original command. */
13469 /* The length of the response data in number of bytes. */
13471 uint8_t unused_0[7];
13473 * This field is used in Output records to indicate that the output
13474 * is completely written to RAM. This field should be read as '1'
13475 * to indicate that the output has been completely written.
13476 * When writing a command completion or response to an internal processor,
13477 * the order of writes has to be such that this field is written last.
13482 /**********************
13483 * hwrm_func_buf_rgtr *
13484 **********************/
13487 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
13488 struct hwrm_func_buf_rgtr_input {
13489 /* The HWRM command request type. */
13492 * The completion ring to send the completion event on. This should
13493 * be the NQ ID returned from the `nq_alloc` HWRM command.
13495 uint16_t cmpl_ring;
13497 * The sequence ID is used by the driver for tracking multiple
13498 * commands. This ID is treated as opaque data by the firmware and
13499 * the value is returned in the `hwrm_resp_hdr` upon completion.
13503 * The target ID of the command:
13504 * * 0x0-0xFFF8 - The function ID
13505 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13506 * * 0xFFFD - Reserved for user-space HWRM interface
13509 uint16_t target_id;
13511 * A physical address pointer pointing to a host buffer that the
13512 * command's response data will be written. This can be either a host
13513 * physical address (HPA) or a guest physical address (GPA) and must
13514 * point to a physically contiguous block of memory.
13516 uint64_t resp_addr;
13519 * This bit must be '1' for the vf_id field to be
13522 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13524 * This bit must be '1' for the err_buf_addr field to be
13527 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
13529 * This value is used to identify a Virtual Function (VF).
13530 * The scope of VF ID is local within a PF.
13534 * This field represents the number of pages used for request
13537 uint16_t req_buf_num_pages;
13539 * This field represents the page size used for request
13542 uint16_t req_buf_page_size;
13544 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
13546 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
13548 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
13550 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
13552 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
13554 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
13556 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
13557 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
13558 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
13559 /* The length of the request buffer per VF in bytes. */
13560 uint16_t req_buf_len;
13561 /* The length of the response buffer in bytes. */
13562 uint16_t resp_buf_len;
13563 uint8_t unused_0[2];
13564 /* This field represents the page address of page #0. */
13565 uint64_t req_buf_page_addr0;
13566 /* This field represents the page address of page #1. */
13567 uint64_t req_buf_page_addr1;
13568 /* This field represents the page address of page #2. */
13569 uint64_t req_buf_page_addr2;
13570 /* This field represents the page address of page #3. */
13571 uint64_t req_buf_page_addr3;
13572 /* This field represents the page address of page #4. */
13573 uint64_t req_buf_page_addr4;
13574 /* This field represents the page address of page #5. */
13575 uint64_t req_buf_page_addr5;
13576 /* This field represents the page address of page #6. */
13577 uint64_t req_buf_page_addr6;
13578 /* This field represents the page address of page #7. */
13579 uint64_t req_buf_page_addr7;
13580 /* This field represents the page address of page #8. */
13581 uint64_t req_buf_page_addr8;
13582 /* This field represents the page address of page #9. */
13583 uint64_t req_buf_page_addr9;
13585 * This field is used to receive the error reporting from
13586 * the chipset. Only applicable for PFs.
13588 uint64_t error_buf_addr;
13590 * This field is used to receive the response forwarded by the
13593 uint64_t resp_buf_addr;
13596 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
13597 struct hwrm_func_buf_rgtr_output {
13598 /* The specific error status for the command. */
13599 uint16_t error_code;
13600 /* The HWRM command request type. */
13602 /* The sequence ID from the original command. */
13604 /* The length of the response data in number of bytes. */
13606 uint8_t unused_0[7];
13608 * This field is used in Output records to indicate that the output
13609 * is completely written to RAM. This field should be read as '1'
13610 * to indicate that the output has been completely written.
13611 * When writing a command completion or response to an internal processor,
13612 * the order of writes has to be such that this field is written last.
13617 /************************
13618 * hwrm_func_buf_unrgtr *
13619 ************************/
13622 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
13623 struct hwrm_func_buf_unrgtr_input {
13624 /* The HWRM command request type. */
13627 * The completion ring to send the completion event on. This should
13628 * be the NQ ID returned from the `nq_alloc` HWRM command.
13630 uint16_t cmpl_ring;
13632 * The sequence ID is used by the driver for tracking multiple
13633 * commands. This ID is treated as opaque data by the firmware and
13634 * the value is returned in the `hwrm_resp_hdr` upon completion.
13638 * The target ID of the command:
13639 * * 0x0-0xFFF8 - The function ID
13640 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13641 * * 0xFFFD - Reserved for user-space HWRM interface
13644 uint16_t target_id;
13646 * A physical address pointer pointing to a host buffer that the
13647 * command's response data will be written. This can be either a host
13648 * physical address (HPA) or a guest physical address (GPA) and must
13649 * point to a physically contiguous block of memory.
13651 uint64_t resp_addr;
13654 * This bit must be '1' for the vf_id field to be
13657 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
13659 * This value is used to identify a Virtual Function (VF).
13660 * The scope of VF ID is local within a PF.
13663 uint8_t unused_0[2];
13666 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
13667 struct hwrm_func_buf_unrgtr_output {
13668 /* The specific error status for the command. */
13669 uint16_t error_code;
13670 /* The HWRM command request type. */
13672 /* The sequence ID from the original command. */
13674 /* The length of the response data in number of bytes. */
13676 uint8_t unused_0[7];
13678 * This field is used in Output records to indicate that the output
13679 * is completely written to RAM. This field should be read as '1'
13680 * to indicate that the output has been completely written.
13681 * When writing a command completion or response to an internal processor,
13682 * the order of writes has to be such that this field is written last.
13687 /**********************
13688 * hwrm_func_drv_qver *
13689 **********************/
13692 /* hwrm_func_drv_qver_input (size:192b/24B) */
13693 struct hwrm_func_drv_qver_input {
13694 /* The HWRM command request type. */
13697 * The completion ring to send the completion event on. This should
13698 * be the NQ ID returned from the `nq_alloc` HWRM command.
13700 uint16_t cmpl_ring;
13702 * The sequence ID is used by the driver for tracking multiple
13703 * commands. This ID is treated as opaque data by the firmware and
13704 * the value is returned in the `hwrm_resp_hdr` upon completion.
13708 * The target ID of the command:
13709 * * 0x0-0xFFF8 - The function ID
13710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13711 * * 0xFFFD - Reserved for user-space HWRM interface
13714 uint16_t target_id;
13716 * A physical address pointer pointing to a host buffer that the
13717 * command's response data will be written. This can be either a host
13718 * physical address (HPA) or a guest physical address (GPA) and must
13719 * point to a physically contiguous block of memory.
13721 uint64_t resp_addr;
13722 /* Reserved for future use. */
13725 * Function ID of the function that is being queried.
13726 * 0xFF... (All Fs) if the query is for the requesting
13730 uint8_t unused_0[2];
13733 /* hwrm_func_drv_qver_output (size:256b/32B) */
13734 struct hwrm_func_drv_qver_output {
13735 /* The specific error status for the command. */
13736 uint16_t error_code;
13737 /* The HWRM command request type. */
13739 /* The sequence ID from the original command. */
13741 /* The length of the response data in number of bytes. */
13743 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
13746 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
13747 /* Other OS not listed below. */
13748 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
13750 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
13752 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
13754 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
13756 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
13758 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
13759 /* VMware ESXi OS. */
13760 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
13761 /* Microsoft Windows 8 64-bit OS. */
13762 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
13763 /* Microsoft Windows Server 2012 R2 OS. */
13764 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
13766 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
13767 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
13768 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
13769 /* This is the 8bit major version of the driver. */
13770 uint8_t ver_maj_8b;
13771 /* This is the 8bit minor version of the driver. */
13772 uint8_t ver_min_8b;
13773 /* This is the 8bit update version of the driver. */
13774 uint8_t ver_upd_8b;
13775 uint8_t unused_0[3];
13776 /* This is the 16bit major version of the driver. */
13778 /* This is the 16bit minor version of the driver. */
13780 /* This is the 16bit update version of the driver. */
13782 /* This is the 16bit patch version of the driver. */
13783 uint16_t ver_patch;
13784 uint8_t unused_1[7];
13786 * This field is used in Output records to indicate that the output
13787 * is completely written to RAM. This field should be read as '1'
13788 * to indicate that the output has been completely written.
13789 * When writing a command completion or response to an internal processor,
13790 * the order of writes has to be such that this field is written last.
13795 /****************************
13796 * hwrm_func_resource_qcaps *
13797 ****************************/
13800 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
13801 struct hwrm_func_resource_qcaps_input {
13802 /* The HWRM command request type. */
13805 * The completion ring to send the completion event on. This should
13806 * be the NQ ID returned from the `nq_alloc` HWRM command.
13808 uint16_t cmpl_ring;
13810 * The sequence ID is used by the driver for tracking multiple
13811 * commands. This ID is treated as opaque data by the firmware and
13812 * the value is returned in the `hwrm_resp_hdr` upon completion.
13816 * The target ID of the command:
13817 * * 0x0-0xFFF8 - The function ID
13818 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13819 * * 0xFFFD - Reserved for user-space HWRM interface
13822 uint16_t target_id;
13824 * A physical address pointer pointing to a host buffer that the
13825 * command's response data will be written. This can be either a host
13826 * physical address (HPA) or a guest physical address (GPA) and must
13827 * point to a physically contiguous block of memory.
13829 uint64_t resp_addr;
13831 * Function ID of the function that is being queried.
13832 * 0xFF... (All Fs) if the query is for the requesting
13836 uint8_t unused_0[6];
13839 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
13840 struct hwrm_func_resource_qcaps_output {
13841 /* The specific error status for the command. */
13842 uint16_t error_code;
13843 /* The HWRM command request type. */
13845 /* The sequence ID from the original command. */
13847 /* The length of the response data in number of bytes. */
13849 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
13851 /* Maximum guaranteed number of MSI-X vectors supported by function */
13853 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
13854 uint16_t vf_reservation_strategy;
13855 /* The PF driver should evenly divide its remaining resources among all VFs. */
13856 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
13858 /* The PF driver should only reserve minimal resources for each VF. */
13859 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
13862 * The PF driver should not reserve any resources for each VF until the
13863 * the VF interface is brought up.
13865 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
13867 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
13868 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
13869 /* Minimum guaranteed number of RSS/COS contexts */
13870 uint16_t min_rsscos_ctx;
13871 /* Maximum non-guaranteed number of RSS/COS contexts */
13872 uint16_t max_rsscos_ctx;
13873 /* Minimum guaranteed number of completion rings */
13874 uint16_t min_cmpl_rings;
13875 /* Maximum non-guaranteed number of completion rings */
13876 uint16_t max_cmpl_rings;
13877 /* Minimum guaranteed number of transmit rings */
13878 uint16_t min_tx_rings;
13879 /* Maximum non-guaranteed number of transmit rings */
13880 uint16_t max_tx_rings;
13881 /* Minimum guaranteed number of receive rings */
13882 uint16_t min_rx_rings;
13883 /* Maximum non-guaranteed number of receive rings */
13884 uint16_t max_rx_rings;
13885 /* Minimum guaranteed number of L2 contexts */
13886 uint16_t min_l2_ctxs;
13887 /* Maximum non-guaranteed number of L2 contexts */
13888 uint16_t max_l2_ctxs;
13889 /* Minimum guaranteed number of VNICs */
13890 uint16_t min_vnics;
13891 /* Maximum non-guaranteed number of VNICs */
13892 uint16_t max_vnics;
13893 /* Minimum guaranteed number of statistic contexts */
13894 uint16_t min_stat_ctx;
13895 /* Maximum non-guaranteed number of statistic contexts */
13896 uint16_t max_stat_ctx;
13897 /* Minimum guaranteed number of ring groups */
13898 uint16_t min_hw_ring_grps;
13899 /* Maximum non-guaranteed number of ring groups */
13900 uint16_t max_hw_ring_grps;
13902 * Maximum number of inputs into the transmit scheduler for this function.
13903 * The number of TX rings assigned to the function cannot exceed this value.
13905 uint16_t max_tx_scheduler_inputs;
13908 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
13909 * feature to reserve all minimum resources when minimum >= 1, otherwise
13910 * returns an error.
13912 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
13914 uint8_t unused_0[5];
13916 * This field is used in Output records to indicate that the output
13917 * is completely written to RAM. This field should be read as '1'
13918 * to indicate that the output has been completely written.
13919 * When writing a command completion or response to an internal processor,
13920 * the order of writes has to be such that this field is written last.
13925 /*****************************
13926 * hwrm_func_vf_resource_cfg *
13927 *****************************/
13930 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
13931 struct hwrm_func_vf_resource_cfg_input {
13932 /* The HWRM command request type. */
13935 * The completion ring to send the completion event on. This should
13936 * be the NQ ID returned from the `nq_alloc` HWRM command.
13938 uint16_t cmpl_ring;
13940 * The sequence ID is used by the driver for tracking multiple
13941 * commands. This ID is treated as opaque data by the firmware and
13942 * the value is returned in the `hwrm_resp_hdr` upon completion.
13946 * The target ID of the command:
13947 * * 0x0-0xFFF8 - The function ID
13948 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13949 * * 0xFFFD - Reserved for user-space HWRM interface
13952 uint16_t target_id;
13954 * A physical address pointer pointing to a host buffer that the
13955 * command's response data will be written. This can be either a host
13956 * physical address (HPA) or a guest physical address (GPA) and must
13957 * point to a physically contiguous block of memory.
13959 uint64_t resp_addr;
13960 /* VF ID that is being configured by PF */
13962 /* Maximum guaranteed number of MSI-X vectors for the function */
13964 /* Minimum guaranteed number of RSS/COS contexts */
13965 uint16_t min_rsscos_ctx;
13966 /* Maximum non-guaranteed number of RSS/COS contexts */
13967 uint16_t max_rsscos_ctx;
13968 /* Minimum guaranteed number of completion rings */
13969 uint16_t min_cmpl_rings;
13970 /* Maximum non-guaranteed number of completion rings */
13971 uint16_t max_cmpl_rings;
13972 /* Minimum guaranteed number of transmit rings */
13973 uint16_t min_tx_rings;
13974 /* Maximum non-guaranteed number of transmit rings */
13975 uint16_t max_tx_rings;
13976 /* Minimum guaranteed number of receive rings */
13977 uint16_t min_rx_rings;
13978 /* Maximum non-guaranteed number of receive rings */
13979 uint16_t max_rx_rings;
13980 /* Minimum guaranteed number of L2 contexts */
13981 uint16_t min_l2_ctxs;
13982 /* Maximum non-guaranteed number of L2 contexts */
13983 uint16_t max_l2_ctxs;
13984 /* Minimum guaranteed number of VNICs */
13985 uint16_t min_vnics;
13986 /* Maximum non-guaranteed number of VNICs */
13987 uint16_t max_vnics;
13988 /* Minimum guaranteed number of statistic contexts */
13989 uint16_t min_stat_ctx;
13990 /* Maximum non-guaranteed number of statistic contexts */
13991 uint16_t max_stat_ctx;
13992 /* Minimum guaranteed number of ring groups */
13993 uint16_t min_hw_ring_grps;
13994 /* Maximum non-guaranteed number of ring groups */
13995 uint16_t max_hw_ring_grps;
13998 * If this bit is set, all minimum resources requested should be
13999 * reserved if minimum >= 1, otherwise return error. In case of
14000 * error, keep all existing reservations before the call.
14002 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \
14004 uint8_t unused_0[2];
14007 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
14008 struct hwrm_func_vf_resource_cfg_output {
14009 /* The specific error status for the command. */
14010 uint16_t error_code;
14011 /* The HWRM command request type. */
14013 /* The sequence ID from the original command. */
14015 /* The length of the response data in number of bytes. */
14017 /* Reserved number of RSS/COS contexts */
14018 uint16_t reserved_rsscos_ctx;
14019 /* Reserved number of completion rings */
14020 uint16_t reserved_cmpl_rings;
14021 /* Reserved number of transmit rings */
14022 uint16_t reserved_tx_rings;
14023 /* Reserved number of receive rings */
14024 uint16_t reserved_rx_rings;
14025 /* Reserved number of L2 contexts */
14026 uint16_t reserved_l2_ctxs;
14027 /* Reserved number of VNICs */
14028 uint16_t reserved_vnics;
14029 /* Reserved number of statistic contexts */
14030 uint16_t reserved_stat_ctx;
14031 /* Reserved number of ring groups */
14032 uint16_t reserved_hw_ring_grps;
14033 uint8_t unused_0[7];
14035 * This field is used in Output records to indicate that the output
14036 * is completely written to RAM. This field should be read as '1'
14037 * to indicate that the output has been completely written.
14038 * When writing a command completion or response to an internal processor,
14039 * the order of writes has to be such that this field is written last.
14044 /*********************************
14045 * hwrm_func_backing_store_qcaps *
14046 *********************************/
14049 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
14050 struct hwrm_func_backing_store_qcaps_input {
14051 /* The HWRM command request type. */
14054 * The completion ring to send the completion event on. This should
14055 * be the NQ ID returned from the `nq_alloc` HWRM command.
14057 uint16_t cmpl_ring;
14059 * The sequence ID is used by the driver for tracking multiple
14060 * commands. This ID is treated as opaque data by the firmware and
14061 * the value is returned in the `hwrm_resp_hdr` upon completion.
14065 * The target ID of the command:
14066 * * 0x0-0xFFF8 - The function ID
14067 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14068 * * 0xFFFD - Reserved for user-space HWRM interface
14071 uint16_t target_id;
14073 * A physical address pointer pointing to a host buffer that the
14074 * command's response data will be written. This can be either a host
14075 * physical address (HPA) or a guest physical address (GPA) and must
14076 * point to a physically contiguous block of memory.
14078 uint64_t resp_addr;
14081 /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */
14082 struct hwrm_func_backing_store_qcaps_output {
14083 /* The specific error status for the command. */
14084 uint16_t error_code;
14085 /* The HWRM command request type. */
14087 /* The sequence ID from the original command. */
14089 /* The length of the response data in number of bytes. */
14091 /* Maximum number of QP context entries supported for this function. */
14092 uint32_t qp_max_entries;
14094 * Minimum number of QP context entries that are needed to be reserved
14095 * for QP1 for the PF and its VFs. PF drivers must allocate at least
14096 * this many QP context entries, even if RoCE will not be used.
14098 uint16_t qp_min_qp1_entries;
14099 /* Maximum number of QP context entries that can be used for L2. */
14100 uint16_t qp_max_l2_entries;
14101 /* Number of bytes that must be allocated for each context entry. */
14102 uint16_t qp_entry_size;
14103 /* Maximum number of SRQ context entries that can be used for L2. */
14104 uint16_t srq_max_l2_entries;
14105 /* Maximum number of SRQ context entries supported for this function. */
14106 uint32_t srq_max_entries;
14107 /* Number of bytes that must be allocated for each context entry. */
14108 uint16_t srq_entry_size;
14109 /* Maximum number of CQ context entries that can be used for L2. */
14110 uint16_t cq_max_l2_entries;
14111 /* Maximum number of CQ context entries supported for this function. */
14112 uint32_t cq_max_entries;
14113 /* Number of bytes that must be allocated for each context entry. */
14114 uint16_t cq_entry_size;
14115 /* Maximum number of VNIC context entries supported for this function. */
14116 uint16_t vnic_max_vnic_entries;
14117 /* Maximum number of Ring table context entries supported for this function. */
14118 uint16_t vnic_max_ring_table_entries;
14119 /* Number of bytes that must be allocated for each context entry. */
14120 uint16_t vnic_entry_size;
14121 /* Maximum number of statistic context entries supported for this function. */
14122 uint32_t stat_max_entries;
14123 /* Number of bytes that must be allocated for each context entry. */
14124 uint16_t stat_entry_size;
14125 /* Number of bytes that must be allocated for each context entry. */
14126 uint16_t tqm_entry_size;
14127 /* Minimum number of TQM context entries required per ring. */
14128 uint32_t tqm_min_entries_per_ring;
14130 * Maximum number of TQM context entries supported per ring. This is
14131 * actually a recommended TQM queue size based on worst case usage of
14134 * TQM fastpath rings should be sized large enough to accommodate the
14135 * maximum number of QPs (either L2 or RoCE, or both if shared)
14136 * that can be enqueued to the TQM ring.
14138 * TQM slowpath rings should be sized as follows:
14140 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
14143 * num_vnics is the number of VNICs allocated in the VNIC backing store
14144 * num_l2_tx_rings is the number of L2 rings in the QP backing store
14145 * num_roce_qps is the number of RoCE QPs in the QP backing store
14146 * tqm_min_size is tqm_min_entries_per_ring reported by
14147 * HWRM_FUNC_BACKING_STORE_QCAPS
14149 * Note that TQM ring sizes cannot be extended while the system is
14150 * operational. If a PF driver needs to extend a TQM ring, it needs
14151 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
14152 * the backing store.
14154 uint32_t tqm_max_entries_per_ring;
14156 * Maximum number of MR plus AV context entries supported for this
14159 uint32_t mrav_max_entries;
14160 /* Number of bytes that must be allocated for each context entry. */
14161 uint16_t mrav_entry_size;
14162 /* Number of bytes that must be allocated for each context entry. */
14163 uint16_t tim_entry_size;
14164 /* Maximum number of Timer context entries supported for this function. */
14165 uint32_t tim_max_entries;
14167 * When this field is zero, the 32b `mrav_num_entries` field in the
14168 * `backing_store_cfg` and `backing_store_qcfg` commands represents
14169 * the total number of MR plus AV entries allowed in the MR/AV backing
14172 * When this field is non-zero, the 32b `mrav_num_entries` field in
14173 * the `backing_store_cfg` and `backing_store_qcfg` commands is
14174 * logically divided into two 16b fields. Bits `[31:16]` represents
14175 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
14176 * Both of these values are represented in a unit granularity
14177 * specified by this field. For example, if this field is 16 and
14178 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
14179 * is 8192 and the number of AV entries is 4096.
14181 uint16_t mrav_num_entries_units;
14183 * The number of entries specified for any TQM ring must be a
14184 * multiple of this value to prevent any resource allocation
14187 uint8_t tqm_entries_multiple;
14189 * Initializer to be used by drivers
14190 * to initialize context memory to ensure
14191 * context subsystem flags an error for an attack
14192 * before the first time context load.
14194 uint8_t ctx_kind_initializer;
14196 * Specifies which context kinds need to be initialized with the
14197 * ctx_kind_initializer.
14199 uint16_t ctx_init_mask;
14201 * If this bit is '1' then this context type should be initialized
14202 * with the ctx_kind_initializer at the specified offset.
14204 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \
14207 * If this bit is '1' then this context type should be initialized
14208 * with the ctx_kind_initializer at the specified offset.
14210 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \
14213 * If this bit is '1' then this context type should be initialized
14214 * with the ctx_kind_initializer at the specified offset.
14216 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \
14219 * If this bit is '1' then this context type should be initialized
14220 * with the ctx_kind_initializer at the specified offset.
14222 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \
14225 * If this bit is '1' then this context type should be initialized
14226 * with the ctx_kind_initializer at the specified offset.
14228 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \
14231 * If this bit is '1' then this context type should be initialized
14232 * with the ctx_kind_initializer at the specified offset.
14234 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \
14237 * Specifies the doubleword offset of ctx_kind_initializer for this
14240 uint8_t qp_init_offset;
14242 * Specifies the doubleword offset of ctx_kind_initializer for this
14245 uint8_t srq_init_offset;
14247 * Specifies the doubleword offset of ctx_kind_initializer for this
14250 uint8_t cq_init_offset;
14252 * Specifies the doubleword offset of ctx_kind_initializer for this
14255 uint8_t vnic_init_offset;
14257 * Count of TQM fastpath rings to be used for allocating backing store.
14258 * Backing store configuration must be specified for each TQM ring from
14259 * this count in `backing_store_cfg`.
14260 * Only first 8 TQM FP rings will be advertised with this field.
14262 uint8_t tqm_fp_rings_count;
14264 * Specifies the doubleword offset of ctx_kind_initializer for this
14267 uint8_t stat_init_offset;
14269 * Specifies the doubleword offset of ctx_kind_initializer for this
14272 uint8_t mrav_init_offset;
14274 * Count of TQM extended fastpath rings to be used for allocating
14275 * backing store beyond 8 rings(rings 9,10,11)
14276 * Backing store configuration must be specified for each TQM ring from
14277 * this count in `backing_store_cfg`.
14279 uint8_t tqm_fp_rings_count_ext;
14280 /* Reserved for future. */
14283 * This field is used in Output records to indicate that the output
14284 * is completely written to RAM. This field should be read as '1'
14285 * to indicate that the output has been completely written.
14286 * When writing a command completion or response to an internal processor,
14287 * the order of writes has to be such that this field is written last.
14292 /* tqm_fp_ring_cfg (size:128b/16B) */
14293 struct tqm_fp_ring_cfg {
14294 /* TQM ring page size and level. */
14295 uint8_t tqm_ring_pg_size_tqm_ring_lvl;
14296 /* TQM ring PBL indirect levels. */
14297 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \
14299 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
14300 /* PBL pointer is physical start address. */
14301 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \
14303 /* PBL pointer points to PTE table. */
14304 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \
14307 * PBL pointer points to PDE table with each entry pointing to
14310 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \
14312 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \
14313 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
14314 /* TQM ring page size. */
14315 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \
14317 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4
14319 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \
14320 (UINT32_C(0x0) << 4)
14322 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \
14323 (UINT32_C(0x1) << 4)
14325 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \
14326 (UINT32_C(0x2) << 4)
14328 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \
14329 (UINT32_C(0x3) << 4)
14331 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \
14332 (UINT32_C(0x4) << 4)
14334 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \
14335 (UINT32_C(0x5) << 4)
14336 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \
14337 TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
14339 /* Number of TQM ring entries. */
14340 uint32_t tqm_ring_num_entries;
14341 /* TQM ring page directory. */
14342 uint64_t tqm_ring_page_dir;
14345 /*******************************
14346 * hwrm_func_backing_store_cfg *
14347 *******************************/
14350 /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */
14351 struct hwrm_func_backing_store_cfg_input {
14352 /* The HWRM command request type. */
14355 * The completion ring to send the completion event on. This should
14356 * be the NQ ID returned from the `nq_alloc` HWRM command.
14358 uint16_t cmpl_ring;
14360 * The sequence ID is used by the driver for tracking multiple
14361 * commands. This ID is treated as opaque data by the firmware and
14362 * the value is returned in the `hwrm_resp_hdr` upon completion.
14366 * The target ID of the command:
14367 * * 0x0-0xFFF8 - The function ID
14368 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14369 * * 0xFFFD - Reserved for user-space HWRM interface
14372 uint16_t target_id;
14374 * A physical address pointer pointing to a host buffer that the
14375 * command's response data will be written. This can be either a host
14376 * physical address (HPA) or a guest physical address (GPA) and must
14377 * point to a physically contiguous block of memory.
14379 uint64_t resp_addr;
14382 * When set, the firmware only uses on-chip resources and does not
14383 * expect any backing store to be provided by the host driver. This
14384 * mode provides minimal L2 functionality (e.g. limited L2 resources,
14387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
14390 * When set, the 32b `mrav_num_entries` field is logically divided
14391 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
14393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
14397 * This bit must be '1' for the qp fields to be
14400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
14403 * This bit must be '1' for the srq fields to be
14406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
14409 * This bit must be '1' for the cq fields to be
14412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
14415 * This bit must be '1' for the vnic fields to be
14418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
14421 * This bit must be '1' for the stat fields to be
14424 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
14427 * This bit must be '1' for the tqm_sp fields to be
14430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
14433 * This bit must be '1' for the tqm_ring0 fields to be
14436 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
14439 * This bit must be '1' for the tqm_ring1 fields to be
14442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
14445 * This bit must be '1' for the tqm_ring2 fields to be
14448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
14451 * This bit must be '1' for the tqm_ring3 fields to be
14454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
14457 * This bit must be '1' for the tqm_ring4 fields to be
14460 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
14463 * This bit must be '1' for the tqm_ring5 fields to be
14466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
14469 * This bit must be '1' for the tqm_ring6 fields to be
14472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
14475 * This bit must be '1' for the tqm_ring7 fields to be
14478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
14481 * This bit must be '1' for the mrav fields to be
14484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
14487 * This bit must be '1' for the tim fields to be
14490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
14493 * This bit must be '1' for the tqm_ring8 fields to be
14496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \
14499 * This bit must be '1' for the tqm_ring9 fields to be
14502 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \
14505 * This bit must be '1' for the tqm_ring10 fields to be
14508 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \
14510 /* QPC page size and level. */
14511 uint8_t qpc_pg_size_qpc_lvl;
14512 /* QPC PBL indirect levels. */
14513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
14515 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
14516 /* PBL pointer is physical start address. */
14517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
14519 /* PBL pointer points to PTE table. */
14520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
14522 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14523 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
14525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
14526 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
14527 /* QPC page size. */
14528 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
14530 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
14532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
14533 (UINT32_C(0x0) << 4)
14535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
14536 (UINT32_C(0x1) << 4)
14538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
14539 (UINT32_C(0x2) << 4)
14541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
14542 (UINT32_C(0x3) << 4)
14544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
14545 (UINT32_C(0x4) << 4)
14547 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
14548 (UINT32_C(0x5) << 4)
14549 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
14550 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
14551 /* SRQ page size and level. */
14552 uint8_t srq_pg_size_srq_lvl;
14553 /* SRQ PBL indirect levels. */
14554 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
14556 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
14557 /* PBL pointer is physical start address. */
14558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
14560 /* PBL pointer points to PTE table. */
14561 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
14563 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14564 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
14566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
14567 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
14568 /* SRQ page size. */
14569 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
14571 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
14573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
14574 (UINT32_C(0x0) << 4)
14576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
14577 (UINT32_C(0x1) << 4)
14579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
14580 (UINT32_C(0x2) << 4)
14582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
14583 (UINT32_C(0x3) << 4)
14585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
14586 (UINT32_C(0x4) << 4)
14588 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
14589 (UINT32_C(0x5) << 4)
14590 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
14591 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
14592 /* CQ page size and level. */
14593 uint8_t cq_pg_size_cq_lvl;
14594 /* CQ PBL indirect levels. */
14595 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
14597 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
14598 /* PBL pointer is physical start address. */
14599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
14601 /* PBL pointer points to PTE table. */
14602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
14604 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14605 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
14607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
14608 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
14609 /* CQ page size. */
14610 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
14612 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
14614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
14615 (UINT32_C(0x0) << 4)
14617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
14618 (UINT32_C(0x1) << 4)
14620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
14621 (UINT32_C(0x2) << 4)
14623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
14624 (UINT32_C(0x3) << 4)
14626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
14627 (UINT32_C(0x4) << 4)
14629 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
14630 (UINT32_C(0x5) << 4)
14631 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
14632 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
14633 /* VNIC page size and level. */
14634 uint8_t vnic_pg_size_vnic_lvl;
14635 /* VNIC PBL indirect levels. */
14636 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
14638 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
14639 /* PBL pointer is physical start address. */
14640 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
14642 /* PBL pointer points to PTE table. */
14643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
14645 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14646 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
14648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
14649 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
14650 /* VNIC page size. */
14651 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
14653 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
14655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
14656 (UINT32_C(0x0) << 4)
14658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
14659 (UINT32_C(0x1) << 4)
14661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
14662 (UINT32_C(0x2) << 4)
14664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
14665 (UINT32_C(0x3) << 4)
14667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
14668 (UINT32_C(0x4) << 4)
14670 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
14671 (UINT32_C(0x5) << 4)
14672 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
14673 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
14674 /* Stat page size and level. */
14675 uint8_t stat_pg_size_stat_lvl;
14676 /* Stat PBL indirect levels. */
14677 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
14679 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
14680 /* PBL pointer is physical start address. */
14681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
14683 /* PBL pointer points to PTE table. */
14684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
14686 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14687 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
14689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
14690 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
14691 /* Stat page size. */
14692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
14694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
14696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
14697 (UINT32_C(0x0) << 4)
14699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
14700 (UINT32_C(0x1) << 4)
14702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
14703 (UINT32_C(0x2) << 4)
14705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
14706 (UINT32_C(0x3) << 4)
14708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
14709 (UINT32_C(0x4) << 4)
14711 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
14712 (UINT32_C(0x5) << 4)
14713 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
14714 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
14715 /* TQM slow path page size and level. */
14716 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
14717 /* TQM slow path PBL indirect levels. */
14718 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
14720 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
14721 /* PBL pointer is physical start address. */
14722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
14724 /* PBL pointer points to PTE table. */
14725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
14727 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
14730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
14731 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
14732 /* TQM slow path page size. */
14733 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
14735 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
14737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
14738 (UINT32_C(0x0) << 4)
14740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
14741 (UINT32_C(0x1) << 4)
14743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
14744 (UINT32_C(0x2) << 4)
14746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
14747 (UINT32_C(0x3) << 4)
14749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
14750 (UINT32_C(0x4) << 4)
14752 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
14753 (UINT32_C(0x5) << 4)
14754 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
14755 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
14756 /* TQM ring 0 page size and level. */
14757 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
14758 /* TQM ring 0 PBL indirect levels. */
14759 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
14761 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
14762 /* PBL pointer is physical start address. */
14763 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
14765 /* PBL pointer points to PTE table. */
14766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
14768 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14769 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
14771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
14772 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
14773 /* TQM ring 0 page size. */
14774 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
14776 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
14778 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
14779 (UINT32_C(0x0) << 4)
14781 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
14782 (UINT32_C(0x1) << 4)
14784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
14785 (UINT32_C(0x2) << 4)
14787 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
14788 (UINT32_C(0x3) << 4)
14790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
14791 (UINT32_C(0x4) << 4)
14793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
14794 (UINT32_C(0x5) << 4)
14795 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
14796 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
14797 /* TQM ring 1 page size and level. */
14798 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
14799 /* TQM ring 1 PBL indirect levels. */
14800 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
14802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
14803 /* PBL pointer is physical start address. */
14804 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
14806 /* PBL pointer points to PTE table. */
14807 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
14809 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
14812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
14813 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
14814 /* TQM ring 1 page size. */
14815 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
14817 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
14819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
14820 (UINT32_C(0x0) << 4)
14822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
14823 (UINT32_C(0x1) << 4)
14825 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
14826 (UINT32_C(0x2) << 4)
14828 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
14829 (UINT32_C(0x3) << 4)
14831 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
14832 (UINT32_C(0x4) << 4)
14834 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
14835 (UINT32_C(0x5) << 4)
14836 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
14837 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
14838 /* TQM ring 2 page size and level. */
14839 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
14840 /* TQM ring 2 PBL indirect levels. */
14841 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
14843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
14844 /* PBL pointer is physical start address. */
14845 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
14847 /* PBL pointer points to PTE table. */
14848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
14850 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14851 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
14853 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
14854 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
14855 /* TQM ring 2 page size. */
14856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
14858 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
14860 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
14861 (UINT32_C(0x0) << 4)
14863 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
14864 (UINT32_C(0x1) << 4)
14866 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
14867 (UINT32_C(0x2) << 4)
14869 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
14870 (UINT32_C(0x3) << 4)
14872 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
14873 (UINT32_C(0x4) << 4)
14875 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
14876 (UINT32_C(0x5) << 4)
14877 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
14878 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
14879 /* TQM ring 3 page size and level. */
14880 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
14881 /* TQM ring 3 PBL indirect levels. */
14882 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
14884 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
14885 /* PBL pointer is physical start address. */
14886 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
14888 /* PBL pointer points to PTE table. */
14889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
14891 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
14894 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
14895 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
14896 /* TQM ring 3 page size. */
14897 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
14899 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
14901 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
14902 (UINT32_C(0x0) << 4)
14904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
14905 (UINT32_C(0x1) << 4)
14907 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
14908 (UINT32_C(0x2) << 4)
14910 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
14911 (UINT32_C(0x3) << 4)
14913 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
14914 (UINT32_C(0x4) << 4)
14916 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
14917 (UINT32_C(0x5) << 4)
14918 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
14919 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
14920 /* TQM ring 4 page size and level. */
14921 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
14922 /* TQM ring 4 PBL indirect levels. */
14923 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
14925 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
14926 /* PBL pointer is physical start address. */
14927 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
14929 /* PBL pointer points to PTE table. */
14930 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
14932 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
14935 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
14936 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
14937 /* TQM ring 4 page size. */
14938 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
14940 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
14942 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
14943 (UINT32_C(0x0) << 4)
14945 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
14946 (UINT32_C(0x1) << 4)
14948 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
14949 (UINT32_C(0x2) << 4)
14951 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
14952 (UINT32_C(0x3) << 4)
14954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
14955 (UINT32_C(0x4) << 4)
14957 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
14958 (UINT32_C(0x5) << 4)
14959 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
14960 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
14961 /* TQM ring 5 page size and level. */
14962 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
14963 /* TQM ring 5 PBL indirect levels. */
14964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
14966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
14967 /* PBL pointer is physical start address. */
14968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
14970 /* PBL pointer points to PTE table. */
14971 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
14973 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
14974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
14976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
14977 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
14978 /* TQM ring 5 page size. */
14979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
14981 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
14983 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
14984 (UINT32_C(0x0) << 4)
14986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
14987 (UINT32_C(0x1) << 4)
14989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
14990 (UINT32_C(0x2) << 4)
14992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
14993 (UINT32_C(0x3) << 4)
14995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
14996 (UINT32_C(0x4) << 4)
14998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
14999 (UINT32_C(0x5) << 4)
15000 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
15001 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
15002 /* TQM ring 6 page size and level. */
15003 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
15004 /* TQM ring 6 PBL indirect levels. */
15005 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
15007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
15008 /* PBL pointer is physical start address. */
15009 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
15011 /* PBL pointer points to PTE table. */
15012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
15014 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
15017 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
15018 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
15019 /* TQM ring 6 page size. */
15020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
15022 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
15024 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
15025 (UINT32_C(0x0) << 4)
15027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
15028 (UINT32_C(0x1) << 4)
15030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
15031 (UINT32_C(0x2) << 4)
15033 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
15034 (UINT32_C(0x3) << 4)
15036 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
15037 (UINT32_C(0x4) << 4)
15039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
15040 (UINT32_C(0x5) << 4)
15041 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
15042 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
15043 /* TQM ring 7 page size and level. */
15044 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
15045 /* TQM ring 7 PBL indirect levels. */
15046 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
15048 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
15049 /* PBL pointer is physical start address. */
15050 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
15052 /* PBL pointer points to PTE table. */
15053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
15055 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
15058 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
15059 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
15060 /* TQM ring 7 page size. */
15061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
15063 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
15065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
15066 (UINT32_C(0x0) << 4)
15068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
15069 (UINT32_C(0x1) << 4)
15071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
15072 (UINT32_C(0x2) << 4)
15074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
15075 (UINT32_C(0x3) << 4)
15077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
15078 (UINT32_C(0x4) << 4)
15080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
15081 (UINT32_C(0x5) << 4)
15082 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
15083 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
15084 /* MR/AV page size and level. */
15085 uint8_t mrav_pg_size_mrav_lvl;
15086 /* MR/AV PBL indirect levels. */
15087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
15089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
15090 /* PBL pointer is physical start address. */
15091 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
15093 /* PBL pointer points to PTE table. */
15094 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
15096 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
15099 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
15100 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
15101 /* MR/AV page size. */
15102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
15104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
15106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
15107 (UINT32_C(0x0) << 4)
15109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
15110 (UINT32_C(0x1) << 4)
15112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
15113 (UINT32_C(0x2) << 4)
15115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
15116 (UINT32_C(0x3) << 4)
15118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
15119 (UINT32_C(0x4) << 4)
15121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
15122 (UINT32_C(0x5) << 4)
15123 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
15124 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
15125 /* Timer page size and level. */
15126 uint8_t tim_pg_size_tim_lvl;
15127 /* Timer PBL indirect levels. */
15128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
15130 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
15131 /* PBL pointer is physical start address. */
15132 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
15134 /* PBL pointer points to PTE table. */
15135 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
15137 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
15140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
15141 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
15142 /* Timer page size. */
15143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
15145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
15147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
15148 (UINT32_C(0x0) << 4)
15150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
15151 (UINT32_C(0x1) << 4)
15153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
15154 (UINT32_C(0x2) << 4)
15156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
15157 (UINT32_C(0x3) << 4)
15159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
15160 (UINT32_C(0x4) << 4)
15162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
15163 (UINT32_C(0x5) << 4)
15164 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
15165 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
15166 /* QP page directory. */
15167 uint64_t qpc_page_dir;
15168 /* SRQ page directory. */
15169 uint64_t srq_page_dir;
15170 /* CQ page directory. */
15171 uint64_t cq_page_dir;
15172 /* VNIC page directory. */
15173 uint64_t vnic_page_dir;
15174 /* Stat page directory. */
15175 uint64_t stat_page_dir;
15176 /* TQM slowpath page directory. */
15177 uint64_t tqm_sp_page_dir;
15178 /* TQM ring 0 page directory. */
15179 uint64_t tqm_ring0_page_dir;
15180 /* TQM ring 1 page directory. */
15181 uint64_t tqm_ring1_page_dir;
15182 /* TQM ring 2 page directory. */
15183 uint64_t tqm_ring2_page_dir;
15184 /* TQM ring 3 page directory. */
15185 uint64_t tqm_ring3_page_dir;
15186 /* TQM ring 4 page directory. */
15187 uint64_t tqm_ring4_page_dir;
15188 /* TQM ring 5 page directory. */
15189 uint64_t tqm_ring5_page_dir;
15190 /* TQM ring 6 page directory. */
15191 uint64_t tqm_ring6_page_dir;
15192 /* TQM ring 7 page directory. */
15193 uint64_t tqm_ring7_page_dir;
15194 /* MR/AV page directory. */
15195 uint64_t mrav_page_dir;
15196 /* Timer page directory. */
15197 uint64_t tim_page_dir;
15198 /* Number of QPs. */
15199 uint32_t qp_num_entries;
15200 /* Number of SRQs. */
15201 uint32_t srq_num_entries;
15202 /* Number of CQs. */
15203 uint32_t cq_num_entries;
15204 /* Number of Stats. */
15205 uint32_t stat_num_entries;
15207 * Number of TQM slowpath entries.
15209 * TQM slowpath rings should be sized as follows:
15211 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
15214 * num_vnics is the number of VNICs allocated in the VNIC backing store
15215 * num_l2_tx_rings is the number of L2 rings in the QP backing store
15216 * num_roce_qps is the number of RoCE QPs in the QP backing store
15217 * tqm_min_size is tqm_min_entries_per_ring reported by
15218 * HWRM_FUNC_BACKING_STORE_QCAPS
15220 * Note that TQM ring sizes cannot be extended while the system is
15221 * operational. If a PF driver needs to extend a TQM ring, it needs
15222 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15223 * the backing store.
15225 uint32_t tqm_sp_num_entries;
15227 * Number of TQM ring 0 entries.
15229 * TQM fastpath rings should be sized large enough to accommodate the
15230 * maximum number of QPs (either L2 or RoCE, or both if shared)
15231 * that can be enqueued to the TQM ring.
15233 * Note that TQM ring sizes cannot be extended while the system is
15234 * operational. If a PF driver needs to extend a TQM ring, it needs
15235 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15236 * the backing store.
15238 uint32_t tqm_ring0_num_entries;
15240 * Number of TQM ring 1 entries.
15242 * TQM fastpath rings should be sized large enough to accommodate the
15243 * maximum number of QPs (either L2 or RoCE, or both if shared)
15244 * that can be enqueued to the TQM ring.
15246 * Note that TQM ring sizes cannot be extended while the system is
15247 * operational. If a PF driver needs to extend a TQM ring, it needs
15248 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15249 * the backing store.
15251 uint32_t tqm_ring1_num_entries;
15253 * Number of TQM ring 2 entries.
15255 * TQM fastpath rings should be sized large enough to accommodate the
15256 * maximum number of QPs (either L2 or RoCE, or both if shared)
15257 * that can be enqueued to the TQM ring.
15259 * Note that TQM ring sizes cannot be extended while the system is
15260 * operational. If a PF driver needs to extend a TQM ring, it needs
15261 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15262 * the backing store.
15264 uint32_t tqm_ring2_num_entries;
15266 * Number of TQM ring 3 entries.
15268 * TQM fastpath rings should be sized large enough to accommodate the
15269 * maximum number of QPs (either L2 or RoCE, or both if shared)
15270 * that can be enqueued to the TQM ring.
15272 * Note that TQM ring sizes cannot be extended while the system is
15273 * operational. If a PF driver needs to extend a TQM ring, it needs
15274 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15275 * the backing store.
15277 uint32_t tqm_ring3_num_entries;
15279 * Number of TQM ring 4 entries.
15281 * TQM fastpath rings should be sized large enough to accommodate the
15282 * maximum number of QPs (either L2 or RoCE, or both if shared)
15283 * that can be enqueued to the TQM ring.
15285 * Note that TQM ring sizes cannot be extended while the system is
15286 * operational. If a PF driver needs to extend a TQM ring, it needs
15287 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15288 * the backing store.
15290 uint32_t tqm_ring4_num_entries;
15292 * Number of TQM ring 5 entries.
15294 * TQM fastpath rings should be sized large enough to accommodate the
15295 * maximum number of QPs (either L2 or RoCE, or both if shared)
15296 * that can be enqueued to the TQM ring.
15298 * Note that TQM ring sizes cannot be extended while the system is
15299 * operational. If a PF driver needs to extend a TQM ring, it needs
15300 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15301 * the backing store.
15303 uint32_t tqm_ring5_num_entries;
15305 * Number of TQM ring 6 entries.
15307 * TQM fastpath rings should be sized large enough to accommodate the
15308 * maximum number of QPs (either L2 or RoCE, or both if shared)
15309 * that can be enqueued to the TQM ring.
15311 * Note that TQM ring sizes cannot be extended while the system is
15312 * operational. If a PF driver needs to extend a TQM ring, it needs
15313 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15314 * the backing store.
15316 uint32_t tqm_ring6_num_entries;
15318 * Number of TQM ring 7 entries.
15320 * TQM fastpath rings should be sized large enough to accommodate the
15321 * maximum number of QPs (either L2 or RoCE, or both if shared)
15322 * that can be enqueued to the TQM ring.
15324 * Note that TQM ring sizes cannot be extended while the system is
15325 * operational. If a PF driver needs to extend a TQM ring, it needs
15326 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
15327 * the backing store.
15329 uint32_t tqm_ring7_num_entries;
15331 * If the MR/AV split reservation flag is not set, then this field
15332 * represents the total number of MR plus AV entries. For versions
15333 * of firmware that support the split reservation, when it is not
15334 * specified half of the entries will be reserved for MRs and the
15335 * other half for AVs.
15337 * If the MR/AV split reservation flag is set, then this
15338 * field is logically divided into two 16b fields. Bits `[31:16]`
15339 * represents the `mr_num_entries` and bits `[15:0]` represents
15340 * `av_num_entries`. The granularity of these values is defined by
15341 * the `mrav_num_entries_unit` field returned by the
15342 * `backing_store_qcaps` command.
15344 uint32_t mrav_num_entries;
15345 /* Number of Timer entries. */
15346 uint32_t tim_num_entries;
15347 /* Number of entries to reserve for QP1 */
15348 uint16_t qp_num_qp1_entries;
15349 /* Number of entries to reserve for L2 */
15350 uint16_t qp_num_l2_entries;
15351 /* Number of bytes that have been allocated for each context entry. */
15352 uint16_t qp_entry_size;
15353 /* Number of entries to reserve for L2 */
15354 uint16_t srq_num_l2_entries;
15355 /* Number of bytes that have been allocated for each context entry. */
15356 uint16_t srq_entry_size;
15357 /* Number of entries to reserve for L2 */
15358 uint16_t cq_num_l2_entries;
15359 /* Number of bytes that have been allocated for each context entry. */
15360 uint16_t cq_entry_size;
15361 /* Number of entries to reserve for VNIC entries */
15362 uint16_t vnic_num_vnic_entries;
15363 /* Number of entries to reserve for Ring table entries */
15364 uint16_t vnic_num_ring_table_entries;
15365 /* Number of bytes that have been allocated for each context entry. */
15366 uint16_t vnic_entry_size;
15367 /* Number of bytes that have been allocated for each context entry. */
15368 uint16_t stat_entry_size;
15369 /* Number of bytes that have been allocated for each context entry. */
15370 uint16_t tqm_entry_size;
15371 /* Number of bytes that have been allocated for each context entry. */
15372 uint16_t mrav_entry_size;
15373 /* Number of bytes that have been allocated for each context entry. */
15374 uint16_t tim_entry_size;
15375 /* TQM ring page size and level. */
15376 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
15377 /* TQM ring PBL indirect levels. */
15378 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \
15380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \
15382 /* PBL pointer is physical start address. */
15383 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \
15385 /* PBL pointer points to PTE table. */
15386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \
15389 * PBL pointer points to PDE table with each entry pointing to
15392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \
15394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \
15395 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2
15396 /* TQM ring page size. */
15397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \
15399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \
15402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
15403 (UINT32_C(0x0) << 4)
15405 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
15406 (UINT32_C(0x1) << 4)
15408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
15409 (UINT32_C(0x2) << 4)
15411 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
15412 (UINT32_C(0x3) << 4)
15414 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
15415 (UINT32_C(0x4) << 4)
15417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
15418 (UINT32_C(0x5) << 4)
15419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \
15420 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G
15421 uint8_t ring8_unused[3];
15422 /* Number of TQM ring entries. */
15423 uint32_t tqm_ring8_num_entries;
15424 /* TQM ring page directory. */
15425 uint64_t tqm_ring8_page_dir;
15426 /* TQM ring page size and level. */
15427 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
15428 /* TQM ring PBL indirect levels. */
15429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \
15431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \
15433 /* PBL pointer is physical start address. */
15434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \
15436 /* PBL pointer points to PTE table. */
15437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \
15440 * PBL pointer points to PDE table with each entry pointing to
15443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \
15445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \
15446 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2
15447 /* TQM ring page size. */
15448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \
15450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \
15453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
15454 (UINT32_C(0x0) << 4)
15456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
15457 (UINT32_C(0x1) << 4)
15459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
15460 (UINT32_C(0x2) << 4)
15462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
15463 (UINT32_C(0x3) << 4)
15465 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
15466 (UINT32_C(0x4) << 4)
15468 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
15469 (UINT32_C(0x5) << 4)
15470 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \
15471 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G
15472 uint8_t ring9_unused[3];
15473 /* Number of TQM ring entries. */
15474 uint32_t tqm_ring9_num_entries;
15475 /* TQM ring page directory. */
15476 uint64_t tqm_ring9_page_dir;
15477 /* TQM ring page size and level. */
15478 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
15479 /* TQM ring PBL indirect levels. */
15480 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \
15482 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \
15484 /* PBL pointer is physical start address. */
15485 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \
15487 /* PBL pointer points to PTE table. */
15488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \
15491 * PBL pointer points to PDE table with each entry pointing to
15494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \
15496 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \
15497 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2
15498 /* TQM ring page size. */
15499 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \
15501 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \
15504 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
15505 (UINT32_C(0x0) << 4)
15507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
15508 (UINT32_C(0x1) << 4)
15510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
15511 (UINT32_C(0x2) << 4)
15513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
15514 (UINT32_C(0x3) << 4)
15516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
15517 (UINT32_C(0x4) << 4)
15519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
15520 (UINT32_C(0x5) << 4)
15521 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \
15522 HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G
15523 uint8_t ring10_unused[3];
15524 /* Number of TQM ring entries. */
15525 uint32_t tqm_ring10_num_entries;
15526 /* TQM ring page directory. */
15527 uint64_t tqm_ring10_page_dir;
15530 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
15531 struct hwrm_func_backing_store_cfg_output {
15532 /* The specific error status for the command. */
15533 uint16_t error_code;
15534 /* The HWRM command request type. */
15536 /* The sequence ID from the original command. */
15538 /* The length of the response data in number of bytes. */
15540 uint8_t unused_0[7];
15542 * This field is used in Output records to indicate that the output
15543 * is completely written to RAM. This field should be read as '1'
15544 * to indicate that the output has been completely written.
15545 * When writing a command completion or response to an internal processor,
15546 * the order of writes has to be such that this field is written last.
15551 /********************************
15552 * hwrm_func_backing_store_qcfg *
15553 ********************************/
15556 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
15557 struct hwrm_func_backing_store_qcfg_input {
15558 /* The HWRM command request type. */
15561 * The completion ring to send the completion event on. This should
15562 * be the NQ ID returned from the `nq_alloc` HWRM command.
15564 uint16_t cmpl_ring;
15566 * The sequence ID is used by the driver for tracking multiple
15567 * commands. This ID is treated as opaque data by the firmware and
15568 * the value is returned in the `hwrm_resp_hdr` upon completion.
15572 * The target ID of the command:
15573 * * 0x0-0xFFF8 - The function ID
15574 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15575 * * 0xFFFD - Reserved for user-space HWRM interface
15578 uint16_t target_id;
15580 * A physical address pointer pointing to a host buffer that the
15581 * command's response data will be written. This can be either a host
15582 * physical address (HPA) or a guest physical address (GPA) and must
15583 * point to a physically contiguous block of memory.
15585 uint64_t resp_addr;
15588 /* hwrm_func_backing_store_qcfg_output (size:2304b/288B) */
15589 struct hwrm_func_backing_store_qcfg_output {
15590 /* The specific error status for the command. */
15591 uint16_t error_code;
15592 /* The HWRM command request type. */
15594 /* The sequence ID from the original command. */
15596 /* The length of the response data in number of bytes. */
15600 * When set, the firmware only uses on-chip resources and does not
15601 * expect any backing store to be provided by the host driver. This
15602 * mode provides minimal L2 functionality (e.g. limited L2 resources,
15605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
15608 * When set, the 32b `mrav_num_entries` field is logically divided
15609 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
15611 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
15615 * This bit must be '1' for the qp fields to be
15618 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \
15621 * This bit must be '1' for the srq fields to be
15624 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \
15627 * This bit must be '1' for the cq fields to be
15630 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \
15633 * This bit must be '1' for the vnic fields to be
15636 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \
15639 * This bit must be '1' for the stat fields to be
15642 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \
15645 * This bit must be '1' for the tqm_sp fields to be
15648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \
15651 * This bit must be '1' for the tqm_ring0 fields to be
15654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \
15657 * This bit must be '1' for the tqm_ring1 fields to be
15660 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \
15663 * This bit must be '1' for the tqm_ring2 fields to be
15666 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \
15669 * This bit must be '1' for the tqm_ring3 fields to be
15672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \
15675 * This bit must be '1' for the tqm_ring4 fields to be
15678 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \
15681 * This bit must be '1' for the tqm_ring5 fields to be
15684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \
15687 * This bit must be '1' for the tqm_ring6 fields to be
15690 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \
15693 * This bit must be '1' for the tqm_ring7 fields to be
15696 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \
15699 * This bit must be '1' for the mrav fields to be
15702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \
15705 * This bit must be '1' for the tim fields to be
15708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \
15711 * This bit must be '1' for the tqm_ring8 fields to be
15714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \
15717 * This bit must be '1' for the tqm_ring9 fields to be
15720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \
15723 * This bit must be '1' for the tqm_ring10 fields to be
15726 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \
15728 /* QPC page size and level. */
15729 uint8_t qpc_pg_size_qpc_lvl;
15730 /* QPC PBL indirect levels. */
15731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
15733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
15734 /* PBL pointer is physical start address. */
15735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
15737 /* PBL pointer points to PTE table. */
15738 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
15740 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
15743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
15744 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
15745 /* QPC page size. */
15746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
15748 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
15750 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
15751 (UINT32_C(0x0) << 4)
15753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
15754 (UINT32_C(0x1) << 4)
15756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
15757 (UINT32_C(0x2) << 4)
15759 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
15760 (UINT32_C(0x3) << 4)
15762 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
15763 (UINT32_C(0x4) << 4)
15765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
15766 (UINT32_C(0x5) << 4)
15767 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
15768 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
15769 /* SRQ page size and level. */
15770 uint8_t srq_pg_size_srq_lvl;
15771 /* SRQ PBL indirect levels. */
15772 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
15774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
15775 /* PBL pointer is physical start address. */
15776 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
15778 /* PBL pointer points to PTE table. */
15779 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
15781 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
15784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
15785 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
15786 /* SRQ page size. */
15787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
15789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
15791 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
15792 (UINT32_C(0x0) << 4)
15794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
15795 (UINT32_C(0x1) << 4)
15797 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
15798 (UINT32_C(0x2) << 4)
15800 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
15801 (UINT32_C(0x3) << 4)
15803 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
15804 (UINT32_C(0x4) << 4)
15806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
15807 (UINT32_C(0x5) << 4)
15808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
15809 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
15810 /* CQ page size and level. */
15811 uint8_t cq_pg_size_cq_lvl;
15812 /* CQ PBL indirect levels. */
15813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
15815 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
15816 /* PBL pointer is physical start address. */
15817 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
15819 /* PBL pointer points to PTE table. */
15820 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
15822 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15823 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
15825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
15826 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
15827 /* CQ page size. */
15828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
15830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
15832 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
15833 (UINT32_C(0x0) << 4)
15835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
15836 (UINT32_C(0x1) << 4)
15838 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
15839 (UINT32_C(0x2) << 4)
15841 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
15842 (UINT32_C(0x3) << 4)
15844 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
15845 (UINT32_C(0x4) << 4)
15847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
15848 (UINT32_C(0x5) << 4)
15849 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
15850 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
15851 /* VNIC page size and level. */
15852 uint8_t vnic_pg_size_vnic_lvl;
15853 /* VNIC PBL indirect levels. */
15854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
15856 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
15857 /* PBL pointer is physical start address. */
15858 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
15860 /* PBL pointer points to PTE table. */
15861 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
15863 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15864 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
15866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
15867 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
15868 /* VNIC page size. */
15869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
15871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
15873 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
15874 (UINT32_C(0x0) << 4)
15876 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
15877 (UINT32_C(0x1) << 4)
15879 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
15880 (UINT32_C(0x2) << 4)
15882 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
15883 (UINT32_C(0x3) << 4)
15885 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
15886 (UINT32_C(0x4) << 4)
15888 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
15889 (UINT32_C(0x5) << 4)
15890 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
15891 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
15892 /* Stat page size and level. */
15893 uint8_t stat_pg_size_stat_lvl;
15894 /* Stat PBL indirect levels. */
15895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
15897 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
15898 /* PBL pointer is physical start address. */
15899 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
15901 /* PBL pointer points to PTE table. */
15902 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
15904 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15905 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
15907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
15908 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
15909 /* Stat page size. */
15910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
15912 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
15914 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
15915 (UINT32_C(0x0) << 4)
15917 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
15918 (UINT32_C(0x1) << 4)
15920 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
15921 (UINT32_C(0x2) << 4)
15923 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
15924 (UINT32_C(0x3) << 4)
15926 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
15927 (UINT32_C(0x4) << 4)
15929 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
15930 (UINT32_C(0x5) << 4)
15931 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
15932 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
15933 /* TQM slow path page size and level. */
15934 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
15935 /* TQM slow path PBL indirect levels. */
15936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
15938 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
15939 /* PBL pointer is physical start address. */
15940 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
15942 /* PBL pointer points to PTE table. */
15943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
15945 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15946 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
15948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
15949 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
15950 /* TQM slow path page size. */
15951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
15953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
15955 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
15956 (UINT32_C(0x0) << 4)
15958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
15959 (UINT32_C(0x1) << 4)
15961 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
15962 (UINT32_C(0x2) << 4)
15964 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
15965 (UINT32_C(0x3) << 4)
15967 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
15968 (UINT32_C(0x4) << 4)
15970 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
15971 (UINT32_C(0x5) << 4)
15972 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
15973 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
15974 /* TQM ring 0 page size and level. */
15975 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
15976 /* TQM ring 0 PBL indirect levels. */
15977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
15979 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
15980 /* PBL pointer is physical start address. */
15981 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
15983 /* PBL pointer points to PTE table. */
15984 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
15986 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
15987 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
15989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
15990 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
15991 /* TQM ring 0 page size. */
15992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
15994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
15996 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
15997 (UINT32_C(0x0) << 4)
15999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
16000 (UINT32_C(0x1) << 4)
16002 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
16003 (UINT32_C(0x2) << 4)
16005 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
16006 (UINT32_C(0x3) << 4)
16008 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
16009 (UINT32_C(0x4) << 4)
16011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
16012 (UINT32_C(0x5) << 4)
16013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
16014 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
16015 /* TQM ring 1 page size and level. */
16016 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
16017 /* TQM ring 1 PBL indirect levels. */
16018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
16020 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
16021 /* PBL pointer is physical start address. */
16022 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
16024 /* PBL pointer points to PTE table. */
16025 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
16027 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
16030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
16031 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
16032 /* TQM ring 1 page size. */
16033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
16035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
16037 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
16038 (UINT32_C(0x0) << 4)
16040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
16041 (UINT32_C(0x1) << 4)
16043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
16044 (UINT32_C(0x2) << 4)
16046 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
16047 (UINT32_C(0x3) << 4)
16049 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
16050 (UINT32_C(0x4) << 4)
16052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
16053 (UINT32_C(0x5) << 4)
16054 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
16055 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
16056 /* TQM ring 2 page size and level. */
16057 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
16058 /* TQM ring 2 PBL indirect levels. */
16059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
16061 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
16062 /* PBL pointer is physical start address. */
16063 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
16065 /* PBL pointer points to PTE table. */
16066 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
16068 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16069 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
16071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
16072 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
16073 /* TQM ring 2 page size. */
16074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
16076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
16078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
16079 (UINT32_C(0x0) << 4)
16081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
16082 (UINT32_C(0x1) << 4)
16084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
16085 (UINT32_C(0x2) << 4)
16087 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
16088 (UINT32_C(0x3) << 4)
16090 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
16091 (UINT32_C(0x4) << 4)
16093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
16094 (UINT32_C(0x5) << 4)
16095 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
16096 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
16097 /* TQM ring 3 page size and level. */
16098 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
16099 /* TQM ring 3 PBL indirect levels. */
16100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
16102 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
16103 /* PBL pointer is physical start address. */
16104 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
16106 /* PBL pointer points to PTE table. */
16107 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
16109 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16110 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
16112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
16113 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
16114 /* TQM ring 3 page size. */
16115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
16117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
16119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
16120 (UINT32_C(0x0) << 4)
16122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
16123 (UINT32_C(0x1) << 4)
16125 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
16126 (UINT32_C(0x2) << 4)
16128 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
16129 (UINT32_C(0x3) << 4)
16131 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
16132 (UINT32_C(0x4) << 4)
16134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
16135 (UINT32_C(0x5) << 4)
16136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
16137 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
16138 /* TQM ring 4 page size and level. */
16139 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
16140 /* TQM ring 4 PBL indirect levels. */
16141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
16143 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
16144 /* PBL pointer is physical start address. */
16145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
16147 /* PBL pointer points to PTE table. */
16148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
16150 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
16153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
16154 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
16155 /* TQM ring 4 page size. */
16156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
16158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
16160 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
16161 (UINT32_C(0x0) << 4)
16163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
16164 (UINT32_C(0x1) << 4)
16166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
16167 (UINT32_C(0x2) << 4)
16169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
16170 (UINT32_C(0x3) << 4)
16172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
16173 (UINT32_C(0x4) << 4)
16175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
16176 (UINT32_C(0x5) << 4)
16177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
16178 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
16179 /* TQM ring 5 page size and level. */
16180 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
16181 /* TQM ring 5 PBL indirect levels. */
16182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
16184 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
16185 /* PBL pointer is physical start address. */
16186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
16188 /* PBL pointer points to PTE table. */
16189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
16191 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
16194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
16195 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
16196 /* TQM ring 5 page size. */
16197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
16199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
16201 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
16202 (UINT32_C(0x0) << 4)
16204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
16205 (UINT32_C(0x1) << 4)
16207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
16208 (UINT32_C(0x2) << 4)
16210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
16211 (UINT32_C(0x3) << 4)
16213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
16214 (UINT32_C(0x4) << 4)
16216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
16217 (UINT32_C(0x5) << 4)
16218 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
16219 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
16220 /* TQM ring 6 page size and level. */
16221 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
16222 /* TQM ring 6 PBL indirect levels. */
16223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
16225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
16226 /* PBL pointer is physical start address. */
16227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
16229 /* PBL pointer points to PTE table. */
16230 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
16232 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
16235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
16236 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
16237 /* TQM ring 6 page size. */
16238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
16240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
16242 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
16243 (UINT32_C(0x0) << 4)
16245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
16246 (UINT32_C(0x1) << 4)
16248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
16249 (UINT32_C(0x2) << 4)
16251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
16252 (UINT32_C(0x3) << 4)
16254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
16255 (UINT32_C(0x4) << 4)
16257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
16258 (UINT32_C(0x5) << 4)
16259 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
16260 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
16261 /* TQM ring 7 page size and level. */
16262 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
16263 /* TQM ring 7 PBL indirect levels. */
16264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
16266 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
16267 /* PBL pointer is physical start address. */
16268 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
16270 /* PBL pointer points to PTE table. */
16271 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
16273 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
16276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
16277 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
16278 /* TQM ring 7 page size. */
16279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
16281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
16283 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
16284 (UINT32_C(0x0) << 4)
16286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
16287 (UINT32_C(0x1) << 4)
16289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
16290 (UINT32_C(0x2) << 4)
16292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
16293 (UINT32_C(0x3) << 4)
16295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
16296 (UINT32_C(0x4) << 4)
16298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
16299 (UINT32_C(0x5) << 4)
16300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
16301 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
16302 /* MR/AV page size and level. */
16303 uint8_t mrav_pg_size_mrav_lvl;
16304 /* MR/AV PBL indirect levels. */
16305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
16307 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
16308 /* PBL pointer is physical start address. */
16309 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
16311 /* PBL pointer points to PTE table. */
16312 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
16314 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
16317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
16318 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
16319 /* MR/AV page size. */
16320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
16322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
16324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
16325 (UINT32_C(0x0) << 4)
16327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
16328 (UINT32_C(0x1) << 4)
16330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
16331 (UINT32_C(0x2) << 4)
16333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
16334 (UINT32_C(0x3) << 4)
16336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
16337 (UINT32_C(0x4) << 4)
16339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
16340 (UINT32_C(0x5) << 4)
16341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
16342 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
16343 /* Timer page size and level. */
16344 uint8_t tim_pg_size_tim_lvl;
16345 /* Timer PBL indirect levels. */
16346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
16348 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
16349 /* PBL pointer is physical start address. */
16350 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
16352 /* PBL pointer points to PTE table. */
16353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
16355 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
16356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
16358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
16359 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
16360 /* Timer page size. */
16361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
16363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
16365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
16366 (UINT32_C(0x0) << 4)
16368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
16369 (UINT32_C(0x1) << 4)
16371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
16372 (UINT32_C(0x2) << 4)
16374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
16375 (UINT32_C(0x3) << 4)
16377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
16378 (UINT32_C(0x4) << 4)
16380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
16381 (UINT32_C(0x5) << 4)
16382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
16383 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
16384 /* QP page directory. */
16385 uint64_t qpc_page_dir;
16386 /* SRQ page directory. */
16387 uint64_t srq_page_dir;
16388 /* CQ page directory. */
16389 uint64_t cq_page_dir;
16390 /* VNIC page directory. */
16391 uint64_t vnic_page_dir;
16392 /* Stat page directory. */
16393 uint64_t stat_page_dir;
16394 /* TQM slowpath page directory. */
16395 uint64_t tqm_sp_page_dir;
16396 /* TQM ring 0 page directory. */
16397 uint64_t tqm_ring0_page_dir;
16398 /* TQM ring 1 page directory. */
16399 uint64_t tqm_ring1_page_dir;
16400 /* TQM ring 2 page directory. */
16401 uint64_t tqm_ring2_page_dir;
16402 /* TQM ring 3 page directory. */
16403 uint64_t tqm_ring3_page_dir;
16404 /* TQM ring 4 page directory. */
16405 uint64_t tqm_ring4_page_dir;
16406 /* TQM ring 5 page directory. */
16407 uint64_t tqm_ring5_page_dir;
16408 /* TQM ring 6 page directory. */
16409 uint64_t tqm_ring6_page_dir;
16410 /* TQM ring 7 page directory. */
16411 uint64_t tqm_ring7_page_dir;
16412 /* MR/AV page directory. */
16413 uint64_t mrav_page_dir;
16414 /* Timer page directory. */
16415 uint64_t tim_page_dir;
16416 /* Number of entries to reserve for QP1 */
16417 uint16_t qp_num_qp1_entries;
16418 /* Number of entries to reserve for L2 */
16419 uint16_t qp_num_l2_entries;
16420 /* Number of QPs. */
16421 uint32_t qp_num_entries;
16422 /* Number of SRQs. */
16423 uint32_t srq_num_entries;
16424 /* Number of entries to reserve for L2 */
16425 uint16_t srq_num_l2_entries;
16426 /* Number of entries to reserve for L2 */
16427 uint16_t cq_num_l2_entries;
16428 /* Number of CQs. */
16429 uint32_t cq_num_entries;
16430 /* Number of entries to reserve for VNIC entries */
16431 uint16_t vnic_num_vnic_entries;
16432 /* Number of entries to reserve for Ring table entries */
16433 uint16_t vnic_num_ring_table_entries;
16434 /* Number of Stats. */
16435 uint32_t stat_num_entries;
16436 /* Number of TQM slowpath entries. */
16437 uint32_t tqm_sp_num_entries;
16438 /* Number of TQM ring 0 entries. */
16439 uint32_t tqm_ring0_num_entries;
16440 /* Number of TQM ring 1 entries. */
16441 uint32_t tqm_ring1_num_entries;
16442 /* Number of TQM ring 2 entries. */
16443 uint32_t tqm_ring2_num_entries;
16444 /* Number of TQM ring 3 entries. */
16445 uint32_t tqm_ring3_num_entries;
16446 /* Number of TQM ring 4 entries. */
16447 uint32_t tqm_ring4_num_entries;
16448 /* Number of TQM ring 5 entries. */
16449 uint32_t tqm_ring5_num_entries;
16450 /* Number of TQM ring 6 entries. */
16451 uint32_t tqm_ring6_num_entries;
16452 /* Number of TQM ring 7 entries. */
16453 uint32_t tqm_ring7_num_entries;
16455 * If the MR/AV split reservation flag is not set, then this field
16456 * represents the total number of MR plus AV entries. For versions
16457 * of firmware that support the split reservation, when it is not
16458 * specified half of the entries will be reserved for MRs and the
16459 * other half for AVs.
16461 * If the MR/AV split reservation flag is set, then this
16462 * field is logically divided into two 16b fields. Bits `[31:16]`
16463 * represents the `mr_num_entries` and bits `[15:0]` represents
16464 * `av_num_entries`. The granularity of these values is defined by
16465 * the `mrav_num_entries_unit` field returned by the
16466 * `backing_store_qcaps` command.
16468 uint32_t mrav_num_entries;
16469 /* Number of Timer entries. */
16470 uint32_t tim_num_entries;
16471 /* TQM ring page size and level. */
16472 uint8_t tqm_ring8_pg_size_tqm_ring_lvl;
16473 /* TQM ring PBL indirect levels. */
16474 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \
16476 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \
16478 /* PBL pointer is physical start address. */
16479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \
16481 /* PBL pointer points to PTE table. */
16482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \
16485 * PBL pointer points to PDE table with each entry pointing to
16488 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \
16490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \
16491 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2
16492 /* TQM ring page size. */
16493 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \
16495 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \
16498 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \
16499 (UINT32_C(0x0) << 4)
16501 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \
16502 (UINT32_C(0x1) << 4)
16504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \
16505 (UINT32_C(0x2) << 4)
16507 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \
16508 (UINT32_C(0x3) << 4)
16510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \
16511 (UINT32_C(0x4) << 4)
16513 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \
16514 (UINT32_C(0x5) << 4)
16515 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \
16516 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G
16517 uint8_t ring8_unused[3];
16518 /* Number of TQM ring entries. */
16519 uint32_t tqm_ring8_num_entries;
16520 /* TQM ring page directory. */
16521 uint64_t tqm_ring8_page_dir;
16522 /* TQM ring page size and level. */
16523 uint8_t tqm_ring9_pg_size_tqm_ring_lvl;
16524 /* TQM ring PBL indirect levels. */
16525 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \
16527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \
16529 /* PBL pointer is physical start address. */
16530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \
16532 /* PBL pointer points to PTE table. */
16533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \
16536 * PBL pointer points to PDE table with each entry pointing to
16539 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \
16541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \
16542 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2
16543 /* TQM ring page size. */
16544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \
16546 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \
16549 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \
16550 (UINT32_C(0x0) << 4)
16552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \
16553 (UINT32_C(0x1) << 4)
16555 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \
16556 (UINT32_C(0x2) << 4)
16558 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \
16559 (UINT32_C(0x3) << 4)
16561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \
16562 (UINT32_C(0x4) << 4)
16564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \
16565 (UINT32_C(0x5) << 4)
16566 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \
16567 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G
16568 uint8_t ring9_unused[3];
16569 /* Number of TQM ring entries. */
16570 uint32_t tqm_ring9_num_entries;
16571 /* TQM ring page directory. */
16572 uint64_t tqm_ring9_page_dir;
16573 /* TQM ring page size and level. */
16574 uint8_t tqm_ring10_pg_size_tqm_ring_lvl;
16575 /* TQM ring PBL indirect levels. */
16576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \
16578 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \
16580 /* PBL pointer is physical start address. */
16581 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \
16583 /* PBL pointer points to PTE table. */
16584 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \
16587 * PBL pointer points to PDE table with each entry pointing to
16590 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \
16592 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \
16593 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2
16594 /* TQM ring page size. */
16595 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \
16597 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \
16600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \
16601 (UINT32_C(0x0) << 4)
16603 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \
16604 (UINT32_C(0x1) << 4)
16606 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \
16607 (UINT32_C(0x2) << 4)
16609 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \
16610 (UINT32_C(0x3) << 4)
16612 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \
16613 (UINT32_C(0x4) << 4)
16615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \
16616 (UINT32_C(0x5) << 4)
16617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \
16618 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G
16619 uint8_t ring10_unused[3];
16620 /* Number of TQM ring entries. */
16621 uint32_t tqm_ring10_num_entries;
16622 /* TQM ring page directory. */
16623 uint64_t tqm_ring10_page_dir;
16624 uint8_t unused_1[7];
16626 * This field is used in Output records to indicate that the output
16627 * is completely written to RAM. This field should be read as 1
16628 * to indicate that the output has been completely written.
16629 * When writing a command completion or response to an internal
16630 * processor, the order of writes has to be such that this field
16636 /****************************
16637 * hwrm_error_recovery_qcfg *
16638 ****************************/
16641 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
16642 struct hwrm_error_recovery_qcfg_input {
16643 /* The HWRM command request type. */
16646 * The completion ring to send the completion event on. This should
16647 * be the NQ ID returned from the `nq_alloc` HWRM command.
16649 uint16_t cmpl_ring;
16651 * The sequence ID is used by the driver for tracking multiple
16652 * commands. This ID is treated as opaque data by the firmware and
16653 * the value is returned in the `hwrm_resp_hdr` upon completion.
16657 * The target ID of the command:
16658 * * 0x0-0xFFF8 - The function ID
16659 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16660 * * 0xFFFD - Reserved for user-space HWRM interface
16663 uint16_t target_id;
16665 * A physical address pointer pointing to a host buffer that the
16666 * command's response data will be written. This can be either a host
16667 * physical address (HPA) or a guest physical address (GPA) and must
16668 * point to a physically contiguous block of memory.
16670 uint64_t resp_addr;
16671 uint8_t unused_0[8];
16674 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
16675 struct hwrm_error_recovery_qcfg_output {
16676 /* The specific error status for the command. */
16677 uint16_t error_code;
16678 /* The HWRM command request type. */
16680 /* The sequence ID from the original command. */
16682 /* The length of the response data in number of bytes. */
16686 * When this flag is set to 1, error recovery will be initiated
16687 * through master function driver.
16689 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
16691 * When this flag is set to 1, error recovery will be performed
16692 * through Co processor.
16694 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
16696 * Driver Polling frequency. This value is in units of 100msec.
16697 * Typical value would be 10 to indicate 1sec.
16698 * Drivers can poll FW health status, Heartbeat, reset_counter with
16701 uint32_t driver_polling_freq;
16703 * This value is in units of 100msec.
16704 * Typical value would be 30 to indicate 3sec.
16705 * Master function wait period from detecting a fatal error to
16706 * initiating reset. In this time period Master PF expects every
16707 * active driver will detect fatal error.
16709 uint32_t master_func_wait_period;
16711 * This value is in units of 100msec.
16712 * Typical value would be 50 to indicate 5sec.
16713 * Normal function wait period from fatal error detection to
16714 * polling FW health status. In this time period, drivers should not
16715 * do any PCIe MMIO transaction and should not send any HWRM commands.
16717 uint32_t normal_func_wait_period;
16719 * This value is in units of 100msec.
16720 * Typical value would be 20 to indicate 2sec.
16721 * This field indicates that, master function wait period after chip
16722 * reset. After this time, master function should reinitialize with
16725 uint32_t master_func_wait_period_after_reset;
16727 * This value is in units of 100msec.
16728 * Typical value would be 60 to indicate 6sec.
16729 * This field is applicable to both master and normal functions.
16730 * Even after chip reset, if FW status not changed to ready,
16731 * then all the functions can poll for this much time and bailout.
16733 uint32_t max_bailout_time_after_reset;
16735 * FW health status register.
16736 * Lower 2 bits indicates address space location and upper 30 bits
16737 * indicates upper 30bits of the register address.
16738 * A value of 0xFFFF-FFFF indicates this register does not exist.
16740 uint32_t fw_health_status_reg;
16741 /* Lower 2 bits indicates address space location. */
16742 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
16744 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
16747 * If value is 0, this register is located in PCIe config space.
16748 * Drivers have to map appropriate window to access this
16751 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
16754 * If value is 1, this register is located in GRC address space.
16755 * Drivers have to map appropriate window to access this
16758 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
16761 * If value is 2, this register is located in first BAR address
16762 * space. Drivers have to map appropriate window to access this
16765 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
16768 * If value is 3, this register is located in second BAR address
16769 * space. Drivers have to map appropriate window to access this
16770 * Drivers have to map appropriate window to access this
16773 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
16775 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
16776 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
16777 /* Upper 30bits of the register address. */
16778 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
16779 UINT32_C(0xfffffffc)
16780 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
16783 * FW HeartBeat register.
16784 * Lower 2 bits indicates address space location and upper 30 bits
16785 * indicates actual address.
16786 * A value of 0xFFFF-FFFF indicates this register does not exist.
16788 uint32_t fw_heartbeat_reg;
16789 /* Lower 2 bits indicates address space location. */
16790 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
16792 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
16795 * If value is 0, this register is located in PCIe config space.
16796 * Drivers have to map appropriate window to access this
16799 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
16802 * If value is 1, this register is located in GRC address space.
16803 * Drivers have to map appropriate window to access this
16806 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
16809 * If value is 2, this register is located in first BAR address
16810 * space. Drivers have to map appropriate window to access this
16813 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
16816 * If value is 3, this register is located in second BAR address
16817 * space. Drivers have to map appropriate window to access this
16820 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
16822 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
16823 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
16824 /* Upper 30bits of the register address. */
16825 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
16826 UINT32_C(0xfffffffc)
16827 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
16830 * FW reset counter.
16831 * Lower 2 bits indicates address space location and upper 30 bits
16832 * indicates actual address.
16833 * A value of 0xFFFF-FFFF indicates this register does not exist.
16835 uint32_t fw_reset_cnt_reg;
16836 /* Lower 2 bits indicates address space location. */
16837 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
16839 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
16842 * If value is 0, this register is located in PCIe config space.
16843 * Drivers have to map appropriate window to access this
16846 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
16849 * If value is 1, this register is located in GRC address space.
16850 * Drivers have to map appropriate window to access this
16853 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
16856 * If value is 2, this register is located in first BAR address
16857 * space. Drivers have to map appropriate window to access this
16860 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
16863 * If value is 3, this register is located in second BAR address
16864 * space. Drivers have to map appropriate window to access this
16867 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
16869 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
16870 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
16871 /* Upper 30bits of the register address. */
16872 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
16873 UINT32_C(0xfffffffc)
16874 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
16877 * Reset Inprogress Register address for PFs.
16878 * Lower 2 bits indicates address space location and upper 30 bits
16879 * indicates actual address.
16880 * A value of 0xFFFF-FFFF indicates this register does not exist.
16882 uint32_t reset_inprogress_reg;
16883 /* Lower 2 bits indicates address space location. */
16884 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
16886 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
16889 * If value is 0, this register is located in PCIe config space.
16890 * Drivers have to map appropriate window to access this
16893 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
16896 * If value is 1, this register is located in GRC address space.
16897 * Drivers have to map appropriate window to access this
16900 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
16903 * If value is 2, this register is located in first BAR address
16904 * space. Drivers have to map appropriate window to access this
16907 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
16910 * If value is 3, this register is located in second BAR address
16911 * space. Drivers have to map appropriate window to access this
16914 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
16916 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
16917 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
16918 /* Upper 30bits of the register address. */
16919 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
16920 UINT32_C(0xfffffffc)
16921 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
16923 /* This field indicates the mask value for reset_inprogress_reg. */
16924 uint32_t reset_inprogress_reg_mask;
16925 uint8_t unused_0[3];
16927 * Array of registers and value count to reset the Chip
16928 * Each array count has reset_reg, reset_reg_val, delay_after_reset
16929 * in TLV format. Depending upon Chip type, number of reset registers
16930 * will vary. Drivers have to write reset_reg_val in the reset_reg
16931 * location in the same sequence in order to recover from a fatal
16934 uint8_t reg_array_cnt;
16937 * Lower 2 bits indicates address space location and upper 30 bits
16938 * indicates actual address.
16939 * A value of 0xFFFF-FFFF indicates this register does not exist.
16941 uint32_t reset_reg[16];
16942 /* Lower 2 bits indicates address space location. */
16943 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
16945 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
16947 * If value is 0, this register is located in PCIe config space.
16948 * Drivers have to map appropriate window to access this
16951 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
16954 * If value is 1, this register is located in GRC address space.
16955 * Drivers have to map appropriate window to access this
16958 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
16961 * If value is 2, this register is located in first BAR address
16962 * space. Drivers have to map appropriate window to access this
16965 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
16968 * If value is 3, this register is located in second BAR address
16969 * space. Drivers have to map appropriate window to access this
16972 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
16974 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
16975 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
16976 /* Upper 30bits of the register address. */
16977 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
16978 UINT32_C(0xfffffffc)
16979 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
16980 /* Value to be written in reset_reg to reset the controller. */
16981 uint32_t reset_reg_val[16];
16983 * This value is in units of 1msec.
16984 * Typical value would be 10 to indicate 10msec.
16985 * Some of the operations like Core reset require delay before
16986 * accessing PCIE MMIO register space.
16987 * If this value is non-zero, drivers have to wait for
16988 * this much time after writing reset_reg_val in reset_reg.
16990 uint8_t delay_after_reset[16];
16992 * Error recovery counter.
16993 * Lower 2 bits indicates address space location and upper 30 bits
16994 * indicates actual address.
16995 * A value of 0xFFFF-FFFF indicates this register does not exist.
16997 uint32_t err_recovery_cnt_reg;
16998 /* Lower 2 bits indicates address space location. */
16999 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
17001 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
17004 * If value is 0, this register is located in PCIe config space.
17005 * Drivers have to map appropriate window to access this
17008 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
17011 * If value is 1, this register is located in GRC address space.
17012 * Drivers have to map appropriate window to access this
17015 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
17018 * If value is 2, this register is located in first BAR address
17019 * space. Drivers have to map appropriate window to access this
17022 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
17025 * If value is 3, this register is located in second BAR address
17026 * space. Drivers have to map appropriate window to access this
17029 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
17031 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
17032 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
17033 /* Upper 30bits of the register address. */
17034 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
17035 UINT32_C(0xfffffffc)
17036 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
17038 uint8_t unused_1[3];
17040 * This field is used in Output records to indicate that the output
17041 * is completely written to RAM. This field should be read as '1'
17042 * to indicate that the output has been completely written.
17043 * When writing a command completion or response to an internal
17044 * processor, the order of writes has to be such that this field
17050 /***************************
17051 * hwrm_func_echo_response *
17052 ****************************/
17055 /* hwrm_func_echo_response_input (size:192b/24B) */
17056 struct hwrm_func_echo_response_input {
17057 /* The HWRM command request type. */
17060 * The completion ring to send the completion event on. This should
17061 * be the NQ ID returned from the `nq_alloc` HWRM command.
17063 uint16_t cmpl_ring;
17065 * The sequence ID is used by the driver for tracking multiple
17066 * commands. This ID is treated as opaque data by the firmware and
17067 * the value is returned in the `hwrm_resp_hdr` upon completion.
17071 * The target ID of the command:
17072 * 0x0-0xFFF8 - The function ID
17073 * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17074 * 0xFFFD - Reserved for user-space HWRM interface
17077 uint16_t target_id;
17079 * A physical address pointer pointing to a host buffer that the
17080 * command's response data will be written. This can be either a host
17081 * physical address (HPA) or a guest physical address (GPA) and must
17082 * point to a physically contiguous block of memory.
17084 uint64_t resp_addr;
17085 uint32_t event_data1;
17086 uint32_t event_data2;
17089 /* hwrm_func_echo_response_output (size:128b/16B) */
17090 struct hwrm_func_echo_response_output {
17091 /* The specific error status for the command. */
17092 uint16_t error_code;
17093 /* The HWRM command request type. */
17095 /* The sequence ID from the original command. */
17097 /* The length of the response data in number of bytes. */
17099 uint8_t unused_0[7];
17101 * This field is used in Output records to indicate that the output
17102 * is completely written to RAM. This field should be read as '1'
17103 * to indicate that the output has been completely written.
17104 * When writing a command completion or response to an internal processor,
17105 * the order of writes has to be such that this field is written last.
17110 /***********************
17111 * hwrm_func_vlan_qcfg *
17112 ***********************/
17115 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
17116 struct hwrm_func_vlan_qcfg_input {
17117 /* The HWRM command request type. */
17120 * The completion ring to send the completion event on. This should
17121 * be the NQ ID returned from the `nq_alloc` HWRM command.
17123 uint16_t cmpl_ring;
17125 * The sequence ID is used by the driver for tracking multiple
17126 * commands. This ID is treated as opaque data by the firmware and
17127 * the value is returned in the `hwrm_resp_hdr` upon completion.
17131 * The target ID of the command:
17132 * * 0x0-0xFFF8 - The function ID
17133 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17134 * * 0xFFFD - Reserved for user-space HWRM interface
17137 uint16_t target_id;
17139 * A physical address pointer pointing to a host buffer that the
17140 * command's response data will be written. This can be either a host
17141 * physical address (HPA) or a guest physical address (GPA) and must
17142 * point to a physically contiguous block of memory.
17144 uint64_t resp_addr;
17146 * Function ID of the function that is being
17148 * If set to 0xFF... (All Fs), then the configuration is
17149 * for the requesting function.
17152 uint8_t unused_0[6];
17155 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
17156 struct hwrm_func_vlan_qcfg_output {
17157 /* The specific error status for the command. */
17158 uint16_t error_code;
17159 /* The HWRM command request type. */
17161 /* The sequence ID from the original command. */
17163 /* The length of the response data in number of bytes. */
17166 /* S-TAG VLAN identifier configured for the function. */
17168 /* S-TAG PCP value configured for the function. */
17172 * S-TAG TPID value configured for the function. This field is specified in
17173 * network byte order.
17175 uint16_t stag_tpid;
17176 /* C-TAG VLAN identifier configured for the function. */
17178 /* C-TAG PCP value configured for the function. */
17182 * C-TAG TPID value configured for the function. This field is specified in
17183 * network byte order.
17185 uint16_t ctag_tpid;
17190 uint8_t unused_3[3];
17192 * This field is used in Output records to indicate that the output
17193 * is completely written to RAM. This field should be read as '1'
17194 * to indicate that the output has been completely written.
17195 * When writing a command completion or response to an internal processor,
17196 * the order of writes has to be such that this field is written last.
17201 /**********************
17202 * hwrm_func_vlan_cfg *
17203 **********************/
17206 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
17207 struct hwrm_func_vlan_cfg_input {
17208 /* The HWRM command request type. */
17211 * The completion ring to send the completion event on. This should
17212 * be the NQ ID returned from the `nq_alloc` HWRM command.
17214 uint16_t cmpl_ring;
17216 * The sequence ID is used by the driver for tracking multiple
17217 * commands. This ID is treated as opaque data by the firmware and
17218 * the value is returned in the `hwrm_resp_hdr` upon completion.
17222 * The target ID of the command:
17223 * * 0x0-0xFFF8 - The function ID
17224 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17225 * * 0xFFFD - Reserved for user-space HWRM interface
17228 uint16_t target_id;
17230 * A physical address pointer pointing to a host buffer that the
17231 * command's response data will be written. This can be either a host
17232 * physical address (HPA) or a guest physical address (GPA) and must
17233 * point to a physically contiguous block of memory.
17235 uint64_t resp_addr;
17237 * Function ID of the function that is being
17239 * If set to 0xFF... (All Fs), then the configuration is
17240 * for the requesting function.
17243 uint8_t unused_0[2];
17246 * This bit must be '1' for the stag_vid field to be
17249 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
17251 * This bit must be '1' for the ctag_vid field to be
17254 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
17256 * This bit must be '1' for the stag_pcp field to be
17259 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
17261 * This bit must be '1' for the ctag_pcp field to be
17264 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
17266 * This bit must be '1' for the stag_tpid field to be
17269 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
17271 * This bit must be '1' for the ctag_tpid field to be
17274 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
17275 /* S-TAG VLAN identifier configured for the function. */
17277 /* S-TAG PCP value configured for the function. */
17281 * S-TAG TPID value configured for the function. This field is specified in
17282 * network byte order.
17284 uint16_t stag_tpid;
17285 /* C-TAG VLAN identifier configured for the function. */
17287 /* C-TAG PCP value configured for the function. */
17291 * C-TAG TPID value configured for the function. This field is specified in
17292 * network byte order.
17294 uint16_t ctag_tpid;
17299 uint8_t unused_3[4];
17302 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
17303 struct hwrm_func_vlan_cfg_output {
17304 /* The specific error status for the command. */
17305 uint16_t error_code;
17306 /* The HWRM command request type. */
17308 /* The sequence ID from the original command. */
17310 /* The length of the response data in number of bytes. */
17312 uint8_t unused_0[7];
17314 * This field is used in Output records to indicate that the output
17315 * is completely written to RAM. This field should be read as '1'
17316 * to indicate that the output has been completely written.
17317 * When writing a command completion or response to an internal processor,
17318 * the order of writes has to be such that this field is written last.
17323 /*******************************
17324 * hwrm_func_vf_vnic_ids_query *
17325 *******************************/
17328 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
17329 struct hwrm_func_vf_vnic_ids_query_input {
17330 /* The HWRM command request type. */
17333 * The completion ring to send the completion event on. This should
17334 * be the NQ ID returned from the `nq_alloc` HWRM command.
17336 uint16_t cmpl_ring;
17338 * The sequence ID is used by the driver for tracking multiple
17339 * commands. This ID is treated as opaque data by the firmware and
17340 * the value is returned in the `hwrm_resp_hdr` upon completion.
17344 * The target ID of the command:
17345 * * 0x0-0xFFF8 - The function ID
17346 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17347 * * 0xFFFD - Reserved for user-space HWRM interface
17350 uint16_t target_id;
17352 * A physical address pointer pointing to a host buffer that the
17353 * command's response data will be written. This can be either a host
17354 * physical address (HPA) or a guest physical address (GPA) and must
17355 * point to a physically contiguous block of memory.
17357 uint64_t resp_addr;
17359 * This value is used to identify a Virtual Function (VF).
17360 * The scope of VF ID is local within a PF.
17363 uint8_t unused_0[2];
17364 /* Max number of vnic ids in vnic id table */
17365 uint32_t max_vnic_id_cnt;
17366 /* This is the address for VF VNIC ID table */
17367 uint64_t vnic_id_tbl_addr;
17370 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
17371 struct hwrm_func_vf_vnic_ids_query_output {
17372 /* The specific error status for the command. */
17373 uint16_t error_code;
17374 /* The HWRM command request type. */
17376 /* The sequence ID from the original command. */
17378 /* The length of the response data in number of bytes. */
17381 * Actual number of vnic ids
17383 * Each VNIC ID is written as a 32-bit number.
17385 uint32_t vnic_id_cnt;
17386 uint8_t unused_0[3];
17388 * This field is used in Output records to indicate that the output
17389 * is completely written to RAM. This field should be read as '1'
17390 * to indicate that the output has been completely written.
17391 * When writing a command completion or response to an internal processor,
17392 * the order of writes has to be such that this field is written last.
17397 /***********************
17398 * hwrm_func_vf_bw_cfg *
17399 ***********************/
17402 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
17403 struct hwrm_func_vf_bw_cfg_input {
17404 /* The HWRM command request type. */
17407 * The completion ring to send the completion event on. This should
17408 * be the NQ ID returned from the `nq_alloc` HWRM command.
17410 uint16_t cmpl_ring;
17412 * The sequence ID is used by the driver for tracking multiple
17413 * commands. This ID is treated as opaque data by the firmware and
17414 * the value is returned in the `hwrm_resp_hdr` upon completion.
17418 * The target ID of the command:
17419 * * 0x0-0xFFF8 - The function ID
17420 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17421 * * 0xFFFD - Reserved for user-space HWRM interface
17424 uint16_t target_id;
17426 * A physical address pointer pointing to a host buffer that the
17427 * command's response data will be written. This can be either a host
17428 * physical address (HPA) or a guest physical address (GPA) and must
17429 * point to a physically contiguous block of memory.
17431 uint64_t resp_addr;
17433 * The number of VF functions that are being configured.
17434 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
17437 uint16_t unused[3];
17438 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
17440 /* The physical VF id the adjustment will be made to. */
17441 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
17442 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
17444 * This field configures the rate scale percentage of the VF as specified
17445 * by the physical VF id.
17447 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
17448 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
17449 /* 0% of the max tx rate */
17450 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
17451 (UINT32_C(0x0) << 12)
17452 /* 6.66% of the max tx rate */
17453 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
17454 (UINT32_C(0x1) << 12)
17455 /* 13.33% of the max tx rate */
17456 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
17457 (UINT32_C(0x2) << 12)
17458 /* 20% of the max tx rate */
17459 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
17460 (UINT32_C(0x3) << 12)
17461 /* 26.66% of the max tx rate */
17462 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
17463 (UINT32_C(0x4) << 12)
17464 /* 33% of the max tx rate */
17465 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
17466 (UINT32_C(0x5) << 12)
17467 /* 40% of the max tx rate */
17468 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
17469 (UINT32_C(0x6) << 12)
17470 /* 46.66% of the max tx rate */
17471 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
17472 (UINT32_C(0x7) << 12)
17473 /* 53.33% of the max tx rate */
17474 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
17475 (UINT32_C(0x8) << 12)
17476 /* 60% of the max tx rate */
17477 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
17478 (UINT32_C(0x9) << 12)
17479 /* 66.66% of the max tx rate */
17480 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
17481 (UINT32_C(0xa) << 12)
17482 /* 53.33% of the max tx rate */
17483 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
17484 (UINT32_C(0xb) << 12)
17485 /* 80% of the max tx rate */
17486 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
17487 (UINT32_C(0xc) << 12)
17488 /* 86.66% of the max tx rate */
17489 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
17490 (UINT32_C(0xd) << 12)
17491 /* 93.33% of the max tx rate */
17492 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
17493 (UINT32_C(0xe) << 12)
17494 /* 100% of the max tx rate */
17495 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
17496 (UINT32_C(0xf) << 12)
17497 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
17498 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
17501 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
17502 struct hwrm_func_vf_bw_cfg_output {
17503 /* The specific error status for the command. */
17504 uint16_t error_code;
17505 /* The HWRM command request type. */
17507 /* The sequence ID from the original command. */
17509 /* The length of the response data in number of bytes. */
17511 uint8_t unused_0[7];
17513 * This field is used in Output records to indicate that the output
17514 * is completely written to RAM. This field should be read as '1'
17515 * to indicate that the output has been completely written.
17516 * When writing a command completion or response to an internal processor,
17517 * the order of writes has to be such that this field is written last.
17522 /************************
17523 * hwrm_func_vf_bw_qcfg *
17524 ************************/
17527 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
17528 struct hwrm_func_vf_bw_qcfg_input {
17529 /* The HWRM command request type. */
17532 * The completion ring to send the completion event on. This should
17533 * be the NQ ID returned from the `nq_alloc` HWRM command.
17535 uint16_t cmpl_ring;
17537 * The sequence ID is used by the driver for tracking multiple
17538 * commands. This ID is treated as opaque data by the firmware and
17539 * the value is returned in the `hwrm_resp_hdr` upon completion.
17543 * The target ID of the command:
17544 * * 0x0-0xFFF8 - The function ID
17545 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17546 * * 0xFFFD - Reserved for user-space HWRM interface
17549 uint16_t target_id;
17551 * A physical address pointer pointing to a host buffer that the
17552 * command's response data will be written. This can be either a host
17553 * physical address (HPA) or a guest physical address (GPA) and must
17554 * point to a physically contiguous block of memory.
17556 uint64_t resp_addr;
17558 * The number of VF functions that are being queried.
17559 * The inline response space allows the host to query up to 50 VFs'
17560 * rate scale percentage
17563 uint16_t unused[3];
17564 /* These 16-bit fields contain the VF fid */
17566 /* The physical VF id of interest */
17567 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
17568 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
17571 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
17572 struct hwrm_func_vf_bw_qcfg_output {
17573 /* The specific error status for the command. */
17574 uint16_t error_code;
17575 /* The HWRM command request type. */
17577 /* The sequence ID from the original command. */
17579 /* The length of the response data in number of bytes. */
17582 * The number of VF functions that are being queried.
17583 * The inline response space allows the host to query up to 50 VFs' rate
17587 uint16_t unused[3];
17588 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
17590 /* The physical VF id the adjustment will be made to. */
17591 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
17592 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
17594 * This field configures the rate scale percentage of the VF as specified
17595 * by the physical VF id.
17597 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
17598 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
17599 /* 0% of the max tx rate */
17600 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
17601 (UINT32_C(0x0) << 12)
17602 /* 6.66% of the max tx rate */
17603 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
17604 (UINT32_C(0x1) << 12)
17605 /* 13.33% of the max tx rate */
17606 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
17607 (UINT32_C(0x2) << 12)
17608 /* 20% of the max tx rate */
17609 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
17610 (UINT32_C(0x3) << 12)
17611 /* 26.66% of the max tx rate */
17612 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
17613 (UINT32_C(0x4) << 12)
17614 /* 33% of the max tx rate */
17615 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
17616 (UINT32_C(0x5) << 12)
17617 /* 40% of the max tx rate */
17618 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
17619 (UINT32_C(0x6) << 12)
17620 /* 46.66% of the max tx rate */
17621 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
17622 (UINT32_C(0x7) << 12)
17623 /* 53.33% of the max tx rate */
17624 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
17625 (UINT32_C(0x8) << 12)
17626 /* 60% of the max tx rate */
17627 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
17628 (UINT32_C(0x9) << 12)
17629 /* 66.66% of the max tx rate */
17630 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
17631 (UINT32_C(0xa) << 12)
17632 /* 53.33% of the max tx rate */
17633 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
17634 (UINT32_C(0xb) << 12)
17635 /* 80% of the max tx rate */
17636 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
17637 (UINT32_C(0xc) << 12)
17638 /* 86.66% of the max tx rate */
17639 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
17640 (UINT32_C(0xd) << 12)
17641 /* 93.33% of the max tx rate */
17642 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
17643 (UINT32_C(0xe) << 12)
17644 /* 100% of the max tx rate */
17645 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
17646 (UINT32_C(0xf) << 12)
17647 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
17648 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
17649 uint8_t unused_0[7];
17651 * This field is used in Output records to indicate that the output
17652 * is completely written to RAM. This field should be read as '1'
17653 * to indicate that the output has been completely written.
17654 * When writing a command completion or response to an internal processor,
17655 * the order of writes has to be such that this field is written last.
17660 /***************************
17661 * hwrm_func_drv_if_change *
17662 ***************************/
17665 /* hwrm_func_drv_if_change_input (size:192b/24B) */
17666 struct hwrm_func_drv_if_change_input {
17667 /* The HWRM command request type. */
17670 * The completion ring to send the completion event on. This should
17671 * be the NQ ID returned from the `nq_alloc` HWRM command.
17673 uint16_t cmpl_ring;
17675 * The sequence ID is used by the driver for tracking multiple
17676 * commands. This ID is treated as opaque data by the firmware and
17677 * the value is returned in the `hwrm_resp_hdr` upon completion.
17681 * The target ID of the command:
17682 * * 0x0-0xFFF8 - The function ID
17683 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17684 * * 0xFFFD - Reserved for user-space HWRM interface
17687 uint16_t target_id;
17689 * A physical address pointer pointing to a host buffer that the
17690 * command's response data will be written. This can be either a host
17691 * physical address (HPA) or a guest physical address (GPA) and must
17692 * point to a physically contiguous block of memory.
17694 uint64_t resp_addr;
17697 * When this bit is '1', the function driver is indicating
17698 * that the IF state is changing to UP state. The call should
17699 * be made at the beginning of the driver's open call before
17700 * resources are allocated. After making the call, the driver
17701 * should check the response to see if any resources may have
17702 * changed (see the response below). If the driver fails
17703 * the open call, the driver should make this call again with
17704 * this bit cleared to indicate that the IF state is not UP.
17705 * During the driver's close call when the IF state is changing
17706 * to DOWN, the driver should make this call with the bit cleared
17707 * after all resources have been freed.
17709 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
17713 /* hwrm_func_drv_if_change_output (size:128b/16B) */
17714 struct hwrm_func_drv_if_change_output {
17715 /* The specific error status for the command. */
17716 uint16_t error_code;
17717 /* The HWRM command request type. */
17719 /* The sequence ID from the original command. */
17721 /* The length of the response data in number of bytes. */
17725 * When this bit is '1', it indicates that the resources reserved
17726 * for this function may have changed. The driver should check
17727 * resource capabilities and reserve resources again before
17728 * allocating resources.
17730 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
17733 * When this bit is '1', it indicates that the firmware got changed / reset.
17734 * The driver should do complete re-initialization when that bit is set.
17736 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
17738 uint8_t unused_0[3];
17740 * This field is used in Output records to indicate that the output
17741 * is completely written to RAM. This field should be read as '1'
17742 * to indicate that the output has been completely written.
17743 * When writing a command completion or response to an internal processor,
17744 * the order of writes has to be such that this field is written last.
17749 /*******************************
17750 * hwrm_func_host_pf_ids_query *
17751 *******************************/
17754 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
17755 struct hwrm_func_host_pf_ids_query_input {
17756 /* The HWRM command request type. */
17759 * The completion ring to send the completion event on. This should
17760 * be the NQ ID returned from the `nq_alloc` HWRM command.
17762 uint16_t cmpl_ring;
17764 * The sequence ID is used by the driver for tracking multiple
17765 * commands. This ID is treated as opaque data by the firmware and
17766 * the value is returned in the `hwrm_resp_hdr` upon completion.
17770 * The target ID of the command:
17771 * * 0x0-0xFFF8 - The function ID
17772 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17773 * * 0xFFFD - Reserved for user-space HWRM interface
17776 uint16_t target_id;
17778 * A physical address pointer pointing to a host buffer that the
17779 * command's response data will be written. This can be either a host
17780 * physical address (HPA) or a guest physical address (GPA) and must
17781 * point to a physically contiguous block of memory.
17783 uint64_t resp_addr;
17786 * # If this bit is set to '1', the query will contain PF(s)
17787 * belongs to SOC host.
17789 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
17791 * # If this bit is set to '1', the query will contain PF(s)
17792 * belongs to EP0 host.
17794 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
17796 * # If this bit is set to '1', the query will contain PF(s)
17797 * belongs to EP1 host.
17799 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
17801 * # If this bit is set to '1', the query will contain PF(s)
17802 * belongs to EP2 host.
17804 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
17806 * # If this bit is set to '1', the query will contain PF(s)
17807 * belongs to EP3 host.
17809 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
17811 * This provides a filter of what PF(s) will be returned in the
17816 * all available PF(s) belong to the host(s) (defined in the
17817 * host field). This includes the hidden PFs.
17819 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
17821 * all available PF(s) belong to the host(s) (defined in the
17822 * host field) that is available for L2 traffic.
17824 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
17826 * all available PF(s) belong to the host(s) (defined in the
17827 * host field) that is available for ROCE traffic.
17829 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
17830 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
17831 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
17832 uint8_t unused_1[6];
17835 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
17836 struct hwrm_func_host_pf_ids_query_output {
17837 /* The specific error status for the command. */
17838 uint16_t error_code;
17839 /* The HWRM command request type. */
17841 /* The sequence ID from the original command. */
17843 /* The length of the response data in number of bytes. */
17845 /* This provides the first PF ID of the device. */
17846 uint16_t first_pf_id;
17847 uint16_t pf_ordinal_mask;
17849 * When this bit is '1', it indicates first PF belongs to one of
17850 * the hosts defined in the input request.
17852 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
17855 * When this bit is '1', it indicates 2nd PF belongs to one of the
17856 * hosts defined in the input request.
17858 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
17861 * When this bit is '1', it indicates 3rd PF belongs to one of the
17862 * hosts defined in the input request.
17864 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
17867 * When this bit is '1', it indicates 4th PF belongs to one of the
17868 * hosts defined in the input request.
17870 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
17873 * When this bit is '1', it indicates 5th PF belongs to one of the
17874 * hosts defined in the input request.
17876 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
17879 * When this bit is '1', it indicates 6th PF belongs to one of the
17880 * hosts defined in the input request.
17882 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
17885 * When this bit is '1', it indicates 7th PF belongs to one of the
17886 * hosts defined in the input request.
17888 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
17891 * When this bit is '1', it indicates 8th PF belongs to one of the
17892 * hosts defined in the input request.
17894 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
17897 * When this bit is '1', it indicates 9th PF belongs to one of the
17898 * hosts defined in the input request.
17900 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
17903 * When this bit is '1', it indicates 10th PF belongs to one of the
17904 * hosts defined in the input request.
17906 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
17909 * When this bit is '1', it indicates 11th PF belongs to one of the
17910 * hosts defined in the input request.
17912 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
17915 * When this bit is '1', it indicates 12th PF belongs to one of the
17916 * hosts defined in the input request.
17918 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
17921 * When this bit is '1', it indicates 13th PF belongs to one of the
17922 * hosts defined in the input request.
17924 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
17927 * When this bit is '1', it indicates 14th PF belongs to one of the
17928 * hosts defined in the input request.
17930 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
17933 * When this bit is '1', it indicates 15th PF belongs to one of the
17934 * hosts defined in the input request.
17936 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
17939 * When this bit is '1', it indicates 16th PF belongs to one of the
17940 * hosts defined in the input request.
17942 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
17944 uint8_t unused_1[3];
17946 * This field is used in Output records to indicate that the output
17947 * is completely written to RAM. This field should be read as '1'
17948 * to indicate that the output has been completely written.
17949 * When writing a command completion or response to an internal processor,
17950 * the order of writes has to be such that this field is written last.
17955 /*********************
17956 * hwrm_func_spd_cfg *
17957 *********************/
17960 /* hwrm_func_spd_cfg_input (size:384b/48B) */
17961 struct hwrm_func_spd_cfg_input {
17962 /* The HWRM command request type. */
17965 * The completion ring to send the completion event on. This should
17966 * be the NQ ID returned from the `nq_alloc` HWRM command.
17968 uint16_t cmpl_ring;
17970 * The sequence ID is used by the driver for tracking multiple
17971 * commands. This ID is treated as opaque data by the firmware and
17972 * the value is returned in the `hwrm_resp_hdr` upon completion.
17976 * The target ID of the command:
17977 * * 0x0-0xFFF8 - The function ID
17978 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17979 * * 0xFFFD - Reserved for user-space HWRM interface
17982 uint16_t target_id;
17984 * A physical address pointer pointing to a host buffer that the
17985 * command's response data will be written. This can be either a host
17986 * physical address (HPA) or a guest physical address (GPA) and must
17987 * point to a physically contiguous block of memory.
17989 uint64_t resp_addr;
17991 /* Set this bit is '1' to enable the SPD datapath forwarding. */
17992 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
17993 /* Set this bit is '1' to disable the SPD datapath forwarding. */
17994 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
17996 * Set this bit is '1' to enable the SPD datapath checksum
17999 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
18001 * Set this bit is '1' to disable the SPD datapath checksum
18004 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
18006 * Set this bit is '1' to enable the SPD datapath debug
18009 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
18011 * Set this bit is '1' to disable the SPD datapath debug
18014 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
18017 * This bit must be '1' for the ethertype field to be
18020 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \
18023 * This bit must be '1' for the hash_mode_flags field to be
18026 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \
18029 * This bit must be '1' for the hash_type field to be
18032 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \
18035 * This bit must be '1' for the ring_tbl_addr field to be
18038 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \
18041 * This bit must be '1' for the hash_key_tbl_addr field to be
18044 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \
18047 * Ethertype value used in the encapsulated SPD packet header.
18048 * The user must choose a value that is not conflicting with
18049 * publicly defined ethertype values. By default, the ethertype
18050 * value of 0xffff is used if there is no user specified value.
18052 uint16_t ethertype;
18053 /* Flags to specify different RSS hash modes. */
18054 uint8_t hash_mode_flags;
18056 * When this bit is '1', it indicates using current RSS
18057 * hash mode setting configured in the device.
18059 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
18062 * When this bit is '1', it indicates requesting support of
18063 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18064 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18065 * packets, the RSS hash is computed over the normal
18066 * src/dest l3 and src/dest l4 headers.
18068 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18071 * When this bit is '1', it indicates requesting support of
18072 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18073 * tunnel packets. For none-tunnel packets, the RSS hash is
18074 * computed over the normal src/dest l3 headers.
18076 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18079 * When this bit is '1', it indicates requesting support of
18080 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18081 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18082 * packets, the RSS hash is computed over the normal
18083 * src/dest l3 and src/dest l4 headers.
18085 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18088 * When this bit is '1', it indicates requesting support of
18089 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18090 * tunnel packets. For none-tunnel packets, the RSS hash is
18091 * computed over the normal src/dest l3 headers.
18093 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18096 uint32_t hash_type;
18098 * When this bit is '1', the RSS hash shall be computed
18099 * over source and destination IPv4 addresses of IPv4
18102 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18104 * When this bit is '1', the RSS hash shall be computed
18105 * over source/destination IPv4 addresses and
18106 * source/destination ports of TCP/IPv4 packets.
18108 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18110 * When this bit is '1', the RSS hash shall be computed
18111 * over source/destination IPv4 addresses and
18112 * source/destination ports of UDP/IPv4 packets.
18114 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18116 * When this bit is '1', the RSS hash shall be computed
18117 * over source and destination IPv4 addresses of IPv6
18120 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18122 * When this bit is '1', the RSS hash shall be computed
18123 * over source/destination IPv6 addresses and
18124 * source/destination ports of TCP/IPv6 packets.
18126 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18128 * When this bit is '1', the RSS hash shall be computed
18129 * over source/destination IPv6 addresses and
18130 * source/destination ports of UDP/IPv6 packets.
18132 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18133 /* This is the address for rss ring group table */
18134 uint64_t ring_grp_tbl_addr;
18135 /* This is the address for rss hash key table */
18136 uint64_t hash_key_tbl_addr;
18139 /* hwrm_func_spd_cfg_output (size:128b/16B) */
18140 struct hwrm_func_spd_cfg_output {
18141 /* The specific error status for the command. */
18142 uint16_t error_code;
18143 /* The HWRM command request type. */
18145 /* The sequence ID from the original command. */
18147 /* The length of the response data in number of bytes. */
18149 uint8_t unused_0[7];
18151 * This field is used in Output records to indicate that the output
18152 * is completely written to RAM. This field should be read as '1'
18153 * to indicate that the output has been completely written.
18154 * When writing a command completion or response to an internal processor,
18155 * the order of writes has to be such that this field is written last.
18160 /**********************
18161 * hwrm_func_spd_qcfg *
18162 **********************/
18165 /* hwrm_func_spd_qcfg_input (size:128b/16B) */
18166 struct hwrm_func_spd_qcfg_input {
18167 /* The HWRM command request type. */
18170 * The completion ring to send the completion event on. This should
18171 * be the NQ ID returned from the `nq_alloc` HWRM command.
18173 uint16_t cmpl_ring;
18175 * The sequence ID is used by the driver for tracking multiple
18176 * commands. This ID is treated as opaque data by the firmware and
18177 * the value is returned in the `hwrm_resp_hdr` upon completion.
18181 * The target ID of the command:
18182 * * 0x0-0xFFF8 - The function ID
18183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18184 * * 0xFFFD - Reserved for user-space HWRM interface
18187 uint16_t target_id;
18189 * A physical address pointer pointing to a host buffer that the
18190 * command's response data will be written. This can be either a host
18191 * physical address (HPA) or a guest physical address (GPA) and must
18192 * point to a physically contiguous block of memory.
18194 uint64_t resp_addr;
18197 /* hwrm_func_spd_qcfg_output (size:512b/64B) */
18198 struct hwrm_func_spd_qcfg_output {
18199 /* The specific error status for the command. */
18200 uint16_t error_code;
18201 /* The HWRM command request type. */
18203 /* The sequence ID from the original command. */
18205 /* The length of the response data in number of bytes. */
18209 * The SPD datapath forwarding is currently enabled when this
18210 * flag is set to '1'.
18212 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
18214 * The SPD datapath checksum feature is currently enabled when
18215 * this flag is set to '1'.
18217 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
18219 * The SPD datapath debug feature is currently enabled when
18220 * this flag is set to '1'.
18222 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
18223 uint32_t hash_type;
18225 * When this bit is '1', the RSS hash shall be computed
18226 * over source and destination IPv4 addresses of IPv4
18229 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18231 * When this bit is '1', the RSS hash shall be computed
18232 * over source/destination IPv4 addresses and
18233 * source/destination ports of TCP/IPv4 packets.
18235 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18237 * When this bit is '1', the RSS hash shall be computed
18238 * over source/destination IPv4 addresses and
18239 * source/destination ports of UDP/IPv4 packets.
18241 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18243 * When this bit is '1', the RSS hash shall be computed
18244 * over source and destination IPv4 addresses of IPv6
18247 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18249 * When this bit is '1', the RSS hash shall be computed
18250 * over source/destination IPv6 addresses and
18251 * source/destination ports of TCP/IPv6 packets.
18253 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18255 * When this bit is '1', the RSS hash shall be computed
18256 * over source/destination IPv6 addresses and
18257 * source/destination ports of UDP/IPv6 packets.
18259 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18260 /* This is the value of rss hash key */
18261 uint32_t hash_key[10];
18262 /* Flags to specify different RSS hash modes. */
18263 uint8_t hash_mode_flags;
18265 * When this bit is '1', it indicates using current RSS
18266 * hash mode setting configured in the device.
18268 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
18271 * When this bit is '1', it indicates requesting support of
18272 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18273 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18274 * packets, the RSS hash is computed over the normal
18275 * src/dest l3 and src/dest l4 headers.
18277 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18280 * When this bit is '1', it indicates requesting support of
18281 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18282 * tunnel packets. For none-tunnel packets, the RSS hash is
18283 * computed over the normal src/dest l3 headers.
18285 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18288 * When this bit is '1', it indicates requesting support of
18289 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18290 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18291 * packets, the RSS hash is computed over the normal
18292 * src/dest l3 and src/dest l4 headers.
18294 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18297 * When this bit is '1', it indicates requesting support of
18298 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18299 * tunnel packets. For none-tunnel packets, the RSS hash is
18300 * computed over the normal src/dest l3 headers.
18302 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18306 * Ethertype value used in the encapsulated SPD packet header.
18307 * The user must choose a value that is not conflicting with
18308 * publicly defined ethertype values. By default, the ethertype
18309 * value of 0xffff is used if there is no user specified value.
18311 uint16_t ethertype;
18312 uint8_t unused_2[3];
18314 * This field is used in Output records to indicate that the output
18315 * is completely written to RAM. This field should be read as '1'
18316 * to indicate that the output has been completely written.
18317 * When writing a command completion or response to an internal processor,
18318 * the order of writes has to be such that this field is written last.
18323 /*********************
18324 * hwrm_port_phy_cfg *
18325 *********************/
18328 /* hwrm_port_phy_cfg_input (size:448b/56B) */
18329 struct hwrm_port_phy_cfg_input {
18330 /* The HWRM command request type. */
18333 * The completion ring to send the completion event on. This should
18334 * be the NQ ID returned from the `nq_alloc` HWRM command.
18336 uint16_t cmpl_ring;
18338 * The sequence ID is used by the driver for tracking multiple
18339 * commands. This ID is treated as opaque data by the firmware and
18340 * the value is returned in the `hwrm_resp_hdr` upon completion.
18344 * The target ID of the command:
18345 * * 0x0-0xFFF8 - The function ID
18346 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18347 * * 0xFFFD - Reserved for user-space HWRM interface
18350 uint16_t target_id;
18352 * A physical address pointer pointing to a host buffer that the
18353 * command's response data will be written. This can be either a host
18354 * physical address (HPA) or a guest physical address (GPA) and must
18355 * point to a physically contiguous block of memory.
18357 uint64_t resp_addr;
18360 * When this bit is set to '1', the PHY for the port shall
18363 * # If this bit is set to 1, then the HWRM shall reset the
18364 * PHY after applying PHY configuration changes specified
18366 * # In order to guarantee that PHY configuration changes
18367 * specified in this command take effect, the HWRM
18368 * client should set this flag to 1.
18369 * # If this bit is not set to 1, then the HWRM may reset
18370 * the PHY depending on the current PHY configuration and
18371 * settings specified in this command.
18373 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
18375 /* deprecated bit. Do not use!!! */
18376 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
18379 * When this bit is set to '1', and the force_pam4_link_speed
18380 * bit in the 'enables' field is '0', the link shall be forced
18381 * to the force_link_speed value.
18383 * When this bit is set to '1', and the force_pam4_link_speed
18384 * bit in the 'enables' field is '1', the link shall be forced
18385 * to the force_pam4_link_speed value.
18387 * When this bit is set to '1', the HWRM client should
18388 * not enable any of the auto negotiation related
18389 * fields represented by auto_XXX fields in this command.
18390 * When this bit is set to '1' and the HWRM client has
18391 * enabled a auto_XXX field in this command, then the
18392 * HWRM shall ignore the enabled auto_XXX field.
18394 * When this bit is set to zero, the link
18395 * shall be allowed to autoneg.
18397 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
18400 * When this bit is set to '1', the auto-negotiation process
18401 * shall be restarted on the link.
18403 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
18406 * When this bit is set to '1', Energy Efficient Ethernet
18407 * (EEE) is requested to be enabled on this link.
18408 * If EEE is not supported on this port, then this flag
18409 * shall be ignored by the HWRM.
18411 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
18414 * When this bit is set to '1', Energy Efficient Ethernet
18415 * (EEE) is requested to be disabled on this link.
18416 * If EEE is not supported on this port, then this flag
18417 * shall be ignored by the HWRM.
18419 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
18422 * When this bit is set to '1' and EEE is enabled on this
18423 * link, then TX LPI is requested to be enabled on the link.
18424 * If EEE is not supported on this port, then this flag
18425 * shall be ignored by the HWRM.
18426 * If EEE is disabled on this port, then this flag shall be
18427 * ignored by the HWRM.
18429 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
18432 * When this bit is set to '1' and EEE is enabled on this
18433 * link, then TX LPI is requested to be disabled on the link.
18434 * If EEE is not supported on this port, then this flag
18435 * shall be ignored by the HWRM.
18436 * If EEE is disabled on this port, then this flag shall be
18437 * ignored by the HWRM.
18439 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
18442 * When set to 1, then the HWRM shall enable FEC autonegotitation
18443 * on this port if supported. When enabled, at least one of the
18444 * FEC modes must be advertised by enabling the fec_clause_74_enable,
18445 * fec_clause_91_enable, fec_rs544_1xn_enable, fec_rs544_ieee_enable,
18446 * fec_rs272_1xn_enable, or fec_rs272_ieee_enable flag. If none
18447 * of the FEC mode is currently enabled, the HWRM shall choose
18448 * a default advertisement setting.
18449 * The default advertisement setting can be queried by calling
18450 * hwrm_port_phy_qcfg. Note that the link speed must be
18451 * in autonegotiation mode for FEC autonegotiation to take effect.
18452 * When set to 0, then this flag shall be ignored.
18453 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
18456 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
18459 * When set to 1, then the HWRM shall disable FEC autonegotiation
18460 * on this port and use forced FEC mode. In forced FEC mode, one
18461 * or more FEC forced settings under the same clause can be set.
18462 * When set to 0, then this flag shall be ignored.
18463 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
18466 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
18469 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
18470 * on this port if supported, by advertising FEC CLAUSE 74 if
18471 * FEC autonegotiation is enabled or force enabled otherwise.
18472 * When set to 0, then this flag shall be ignored.
18473 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
18476 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
18479 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
18480 * on this port if supported, by not advertising FEC CLAUSE 74 if
18481 * FEC autonegotiation is enabled or force disabled otherwise.
18482 * When set to 0, then this flag shall be ignored.
18483 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
18486 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
18489 * When set to 1, then the HWRM shall enable FEC CLAUSE 91
18490 * (Reed Solomon RS(528,514) for NRZ) on this port if supported,
18491 * by advertising FEC RS(528,514) if FEC autonegotiation is enabled
18492 * or force enabled otherwise. In forced FEC mode, this flag
18493 * will only take effect if the speed is NRZ. Additional
18494 * RS544 or RS272 flags (also under clause 91) may be set for PAM4
18495 * in forced FEC mode.
18496 * When set to 0, then this flag shall be ignored.
18497 * If FEC RS(528,514) is not supported, then the HWRM shall ignore
18500 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
18503 * When set to 1, then the HWRM shall disable FEC CLAUSE 91
18504 * (Reed Solomon RS(528,514) for NRZ) on this port if supported, by
18505 * not advertising RS(528,514) if FEC autonegotiation is enabled or
18506 * force disabled otherwise. When set to 0, then this flag shall be
18507 * ignored. If FEC RS(528,514) is not supported, then the HWRM
18508 * shall ignore this flag.
18510 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
18513 * When this bit is set to '1', the link shall be forced to
18516 * # When this bit is set to '1", all other
18517 * command input settings related to the link speed shall
18519 * Once the link state is forced down, it can be
18520 * explicitly cleared from that state by setting this flag
18522 * # If this flag is set to '0', then the link shall be
18523 * cleared from forced down state if the link is in forced
18525 * There may be conditions (e.g. out-of-band or sideband
18526 * configuration changes for the link) outside the scope
18527 * of the HWRM implementation that may clear forced down
18530 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
18533 * When set to 1, then the HWRM shall enable FEC RS544_1XN
18534 * on this port if supported, by advertising FEC RS544_1XN if
18535 * FEC autonegotiation is enabled or force enabled otherwise.
18536 * In forced mode, this flag will only take effect if the speed is
18537 * PAM4. If this flag and fec_rs544_ieee_enable are set, the
18538 * HWRM shall choose one of the RS544 modes.
18539 * When set to 0, then this flag shall be ignored.
18540 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
18543 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE \
18546 * When set to 1, then the HWRM shall disable FEC RS544_1XN
18547 * on this port if supported, by not advertising FEC RS544_1XN if
18548 * FEC autonegotiation is enabled or force disabled otherwise.
18549 * When set to 0, then this flag shall be ignored.
18550 * If FEC RS544_1XN is not supported, then the HWRM shall ignore this
18553 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE \
18556 * When set to 1, then the HWRM shall enable FEC RS(544,514)
18557 * on this port if supported, by advertising FEC RS(544,514) if
18558 * FEC autonegotiation is enabled or force enabled otherwise.
18559 * In forced mode, this flag will only take effect if the speed is
18560 * PAM4. If this flag and fec_rs544_1xn_enable are set, the
18561 * HWRM shall choose one of the RS544 modes.
18562 * When set to 0, then this flag shall be ignored.
18563 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
18566 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE \
18569 * When set to 1, then the HWRM shall disable FEC RS(544,514)
18570 * on this port if supported, by not advertising FEC RS(544,514) if
18571 * FEC autonegotiation is enabled or force disabled otherwise.
18572 * When set to 0, then this flag shall be ignored.
18573 * If FEC RS(544,514) is not supported, then the HWRM shall ignore
18576 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE \
18579 * When set to 1, then the HWRM shall enable FEC RS272_1XN
18580 * on this port if supported, by advertising FEC RS272_1XN if
18581 * FEC autonegotiation is enabled or force enabled otherwise.
18582 * In forced mode, this flag will only take effect if the speed is
18583 * PAM4. If this flag and fec_rs272_ieee_enable are set, the
18584 * HWRM shall choose one of the RS272 modes. Note that RS272
18585 * and RS544 modes cannot be set at the same time in forced FEC mode.
18586 * When set to 0, then this flag shall be ignored.
18587 * If FEC RS272_1XN is not supported, then the HWRM shall ignore this
18590 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE \
18593 * When set to 1, then the HWRM shall disable FEC RS272_1XN
18594 * on this port if supported, by not advertising FEC RS272_1XN if
18595 * FEC autonegotiation is enabled or force disabled otherwise.
18596 * When set to 0, then this flag shall be ignored.
18597 * If FEC RS272_1XN is not supported, then the HWRM shall ignore
18600 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE \
18603 * When set to 1, then the HWRM shall enable FEC RS(272,257)
18604 * on this port if supported, by advertising FEC RS(272,257) if
18605 * FEC autonegotiation is enabled or force enabled otherwise.
18606 * In forced mode, this flag will only take effect if the speed is
18607 * PAM4. If this flag and fec_rs272_1xn_enable are set, the
18608 * HWRM shall choose one of the RS272 modes. Note that RS272
18609 * and RS544 modes cannot be set at the same time in forced FEC mode.
18610 * When set to 0, then this flag shall be ignored.
18611 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
18614 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE \
18617 * When set to 1, then the HWRM shall disable FEC RS(272,257)
18618 * on this port if supported, by not advertising FEC RS(272,257) if
18619 * FEC autonegotiation is enabled or force disabled otherwise.
18620 * When set to 0, then this flag shall be ignored.
18621 * If FEC RS(272,257) is not supported, then the HWRM shall ignore
18624 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE \
18628 * This bit must be '1' for the auto_mode field to be
18631 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
18634 * This bit must be '1' for the auto_duplex field to be
18637 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
18640 * This bit must be '1' for the auto_pause field to be
18643 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
18646 * This bit must be '1' for the auto_link_speed field to be
18649 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
18652 * This bit must be '1' for the auto_link_speed_mask field to be
18655 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
18658 * This bit must be '1' for the wirespeed field to be
18661 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
18664 * This bit must be '1' for the lpbk field to be
18667 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
18670 * This bit must be '1' for the preemphasis field to be
18673 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
18676 * This bit must be '1' for the force_pause field to be
18679 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
18682 * This bit must be '1' for the eee_link_speed_mask field to be
18685 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
18688 * This bit must be '1' for the tx_lpi_timer field to be
18691 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
18694 * This bit must be '1' for the force_pam4_link_speed field to be
18697 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED \
18700 * This bit must be '1' for the auto_pam4_link_speed_mask field to
18703 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK \
18705 /* Port ID of port that is to be configured. */
18708 * This is the speed that will be used if the force
18709 * bit is '1'. If unsupported speed is selected, an error
18710 * will be generated.
18712 uint16_t force_link_speed;
18713 /* 100Mb link speed */
18714 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
18715 /* 1Gb link speed */
18716 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
18717 /* 2Gb link speed */
18718 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
18719 /* 25Gb link speed */
18720 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
18721 /* 10Gb link speed */
18722 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
18723 /* 20Mb link speed */
18724 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
18725 /* 25Gb link speed */
18726 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
18727 /* 40Gb link speed */
18728 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
18729 /* 50Gb link speed */
18730 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
18731 /* 100Gb link speed */
18732 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
18733 /* 10Mb link speed */
18734 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
18735 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
18736 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
18738 * This value is used to identify what autoneg mode is
18739 * used when the link speed is not being forced.
18742 /* Disable autoneg or autoneg disabled. No speeds are selected. */
18743 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
18744 /* Select all possible speeds for autoneg mode. */
18745 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
18747 * Select only the auto_link_speed speed for autoneg mode. This mode has
18748 * been DEPRECATED. An HWRM client should not use this mode.
18750 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
18752 * Select the auto_link_speed or any speed below that speed for autoneg.
18753 * This mode has been DEPRECATED. An HWRM client should not use this mode.
18755 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
18757 * Select the speeds based on the corresponding link speed mask values
18758 * that are provided. The included speeds are specified in the
18759 * auto_link_speed and auto_pam4_link_speed fields.
18761 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
18762 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
18763 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
18765 * This is the duplex setting that will be used if the autoneg_mode
18766 * is "one_speed" or "one_or_below".
18768 uint8_t auto_duplex;
18769 /* Half Duplex will be requested. */
18770 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
18771 /* Full duplex will be requested. */
18772 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
18773 /* Both Half and Full dupex will be requested. */
18774 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
18775 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
18776 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
18778 * This value is used to configure the pause that will be
18779 * used for autonegotiation.
18780 * Add text on the usage of auto_pause and force_pause.
18782 uint8_t auto_pause;
18784 * When this bit is '1', Generation of tx pause messages
18785 * has been requested. Disabled otherwise.
18787 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
18790 * When this bit is '1', Reception of rx pause messages
18791 * has been requested. Disabled otherwise.
18793 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
18796 * When set to 1, the advertisement of pause is enabled.
18798 * # When the auto_mode is not set to none and this flag is
18799 * set to 1, then the auto_pause bits on this port are being
18800 * advertised and autoneg pause results are being interpreted.
18801 * # When the auto_mode is not set to none and this
18802 * flag is set to 0, the pause is forced as indicated in
18803 * force_pause, and also advertised as auto_pause bits, but
18804 * the autoneg results are not interpreted since the pause
18805 * configuration is being forced.
18806 * # When the auto_mode is set to none and this flag is set to
18807 * 1, auto_pause bits should be ignored and should be set to 0.
18809 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
18813 * This is the speed that will be used if the autoneg_mode
18814 * is "one_speed" or "one_or_below". If an unsupported speed
18815 * is selected, an error will be generated.
18817 uint16_t auto_link_speed;
18818 /* 100Mb link speed */
18819 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
18820 /* 1Gb link speed */
18821 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
18822 /* 2Gb link speed */
18823 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
18824 /* 25Gb link speed */
18825 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
18826 /* 10Gb link speed */
18827 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
18828 /* 20Mb link speed */
18829 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
18830 /* 25Gb link speed */
18831 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
18832 /* 40Gb link speed */
18833 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
18834 /* 50Gb link speed */
18835 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
18836 /* 100Gb link speed */
18837 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
18838 /* 10Mb link speed */
18839 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
18840 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
18841 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
18843 * This is a mask of link speeds that will be used if
18844 * autoneg_mode is "mask". If unsupported speed is enabled
18845 * an error will be generated.
18847 uint16_t auto_link_speed_mask;
18848 /* 100Mb link speed (Half-duplex) */
18849 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
18851 /* 100Mb link speed (Full-duplex) */
18852 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
18854 /* 1Gb link speed (Half-duplex) */
18855 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
18857 /* 1Gb link speed (Full-duplex) */
18858 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
18860 /* 2Gb link speed */
18861 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
18863 /* 25Gb link speed */
18864 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
18866 /* 10Gb link speed */
18867 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
18869 /* 20Gb link speed */
18870 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
18872 /* 25Gb link speed */
18873 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
18875 /* 40Gb link speed */
18876 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
18878 /* 50Gb link speed */
18879 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
18881 /* 100Gb link speed */
18882 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
18884 /* 10Mb link speed (Half-duplex) */
18885 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
18887 /* 10Mb link speed (Full-duplex) */
18888 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
18890 /* This value controls the wirespeed feature. */
18892 /* Wirespeed feature is disabled. */
18893 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
18894 /* Wirespeed feature is enabled. */
18895 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
18896 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
18897 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
18898 /* This value controls the loopback setting for the PHY. */
18900 /* No loopback is selected. Normal operation. */
18901 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
18903 * The HW will be configured with local loopback such that
18904 * host data is sent back to the host without modification.
18906 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
18908 * The HW will be configured with remote loopback such that
18909 * port logic will send packets back out the transmitter that
18912 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
18914 * The HW will be configured with external loopback such that
18915 * host data is sent on the transmitter and based on the external
18916 * loopback connection the data will be received without modification.
18918 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
18919 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
18920 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
18922 * This value is used to configure the pause that will be
18923 * used for force mode.
18925 uint8_t force_pause;
18927 * When this bit is '1', Generation of tx pause messages
18928 * is supported. Disabled otherwise.
18930 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
18932 * When this bit is '1', Reception of rx pause messages
18933 * is supported. Disabled otherwise.
18935 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
18938 * This value controls the pre-emphasis to be used for the
18939 * link. Driver should not set this value (use
18940 * enable.preemphasis = 0) unless driver is sure of setting.
18941 * Normally HWRM FW will determine proper pre-emphasis.
18943 uint32_t preemphasis;
18945 * Setting for link speed mask that is used to
18946 * advertise speeds during autonegotiation when EEE is enabled.
18947 * This field is valid only when EEE is enabled.
18948 * The speeds specified in this field shall be a subset of
18949 * speeds specified in auto_link_speed_mask.
18950 * If EEE is enabled,then at least one speed shall be provided
18953 uint16_t eee_link_speed_mask;
18955 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
18957 /* 100Mb link speed (Full-duplex) */
18958 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
18961 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
18963 /* 1Gb link speed (Full-duplex) */
18964 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
18967 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
18970 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
18972 /* 10Gb link speed */
18973 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
18976 * This is the speed that will be used if the force and force_pam4
18977 * bits are '1'. If unsupported speed is selected, an error
18978 * will be generated.
18980 uint16_t force_pam4_link_speed;
18981 /* 50Gb link speed */
18982 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
18984 /* 100Gb link speed */
18985 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
18987 /* 200Gb link speed */
18988 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
18990 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
18991 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
18993 * Requested setting of TX LPI timer in microseconds.
18994 * This field is valid only when EEE is enabled and TX LPI is
18997 uint32_t tx_lpi_timer;
18998 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
18999 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
19000 /* This field specifies which PAM4 speeds are enabled for auto mode. */
19001 uint16_t auto_link_pam4_speed_mask;
19002 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G \
19004 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G \
19006 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G \
19008 uint8_t unused_2[2];
19011 /* hwrm_port_phy_cfg_output (size:128b/16B) */
19012 struct hwrm_port_phy_cfg_output {
19013 /* The specific error status for the command. */
19014 uint16_t error_code;
19015 /* The HWRM command request type. */
19017 /* The sequence ID from the original command. */
19019 /* The length of the response data in number of bytes. */
19021 uint8_t unused_0[7];
19023 * This field is used in Output records to indicate that the output
19024 * is completely written to RAM. This field should be read as '1'
19025 * to indicate that the output has been completely written.
19026 * When writing a command completion or response to an internal processor,
19027 * the order of writes has to be such that this field is written last.
19032 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
19033 struct hwrm_port_phy_cfg_cmd_err {
19035 * command specific error codes that goes to
19036 * the cmd_err field in Common HWRM Error Response.
19039 /* Unknown error */
19040 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
19041 /* Unable to complete operation due to invalid speed */
19042 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
19044 * retry the command since the phy is not ready.
19045 * retry count is returned in opaque_0.
19046 * This is only valid for the first command and
19047 * this value will not change for successive calls.
19048 * but if a 0 is returned at any time then this should
19049 * be treated as an un recoverable failure,
19051 * retry interval in milli seconds is returned in opaque_1.
19052 * This specifies the time that user should wait before
19053 * issuing the next port_phy_cfg command.
19055 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
19056 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
19057 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
19058 uint8_t unused_0[7];
19061 /**********************
19062 * hwrm_port_phy_qcfg *
19063 **********************/
19066 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
19067 struct hwrm_port_phy_qcfg_input {
19068 /* The HWRM command request type. */
19071 * The completion ring to send the completion event on. This should
19072 * be the NQ ID returned from the `nq_alloc` HWRM command.
19074 uint16_t cmpl_ring;
19076 * The sequence ID is used by the driver for tracking multiple
19077 * commands. This ID is treated as opaque data by the firmware and
19078 * the value is returned in the `hwrm_resp_hdr` upon completion.
19082 * The target ID of the command:
19083 * * 0x0-0xFFF8 - The function ID
19084 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19085 * * 0xFFFD - Reserved for user-space HWRM interface
19088 uint16_t target_id;
19090 * A physical address pointer pointing to a host buffer that the
19091 * command's response data will be written. This can be either a host
19092 * physical address (HPA) or a guest physical address (GPA) and must
19093 * point to a physically contiguous block of memory.
19095 uint64_t resp_addr;
19096 /* Port ID of port that is to be queried. */
19098 uint8_t unused_0[6];
19101 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
19102 struct hwrm_port_phy_qcfg_output {
19103 /* The specific error status for the command. */
19104 uint16_t error_code;
19105 /* The HWRM command request type. */
19107 /* The sequence ID from the original command. */
19109 /* The length of the response data in number of bytes. */
19111 /* This value indicates the current link status. */
19113 /* There is no link or cable detected. */
19114 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
19115 /* There is no link, but a cable has been detected. */
19116 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
19117 /* There is a link. */
19118 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
19119 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
19120 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
19121 uint8_t active_fec_signal_mode;
19123 * This value indicates the current link signaling mode of the
19126 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK \
19128 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
19129 /* NRZ signaling */
19130 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ \
19132 /* PAM4 signaling */
19133 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 \
19135 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_LAST \
19136 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
19137 /* This value indicates the current active FEC mode. */
19138 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK \
19140 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_SFT 4
19141 /* No active FEC */
19142 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE \
19143 (UINT32_C(0x0) << 4)
19144 /* FEC CLAUSE 74 (Fire Code) active, autonegotiated or forced. */
19145 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE \
19146 (UINT32_C(0x1) << 4)
19147 /* FEC CLAUSE 91 RS(528,514) active, autonegoatiated or forced. */
19148 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE \
19149 (UINT32_C(0x2) << 4)
19150 /* FEC RS544_1XN active, autonegoatiated or forced. */
19151 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE \
19152 (UINT32_C(0x3) << 4)
19153 /* FEC RS(544,528) active, autonegoatiated or forced. */
19154 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE \
19155 (UINT32_C(0x4) << 4)
19156 /* FEC RS272_1XN active, autonegotiated or forced. */
19157 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE \
19158 (UINT32_C(0x5) << 4)
19159 /* FEC RS(272,257) active, autonegoatiated or forced. */
19160 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE \
19161 (UINT32_C(0x6) << 4)
19162 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_LAST \
19163 HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
19165 * This value indicates the current link speed of the connection.
19166 * The signal_mode field indicates if the link is using
19167 * NRZ or PAM4 signaling.
19169 uint16_t link_speed;
19170 /* 100Mb link speed */
19171 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
19172 /* 1Gb link speed */
19173 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
19174 /* 2Gb link speed */
19175 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
19176 /* 25Gb link speed */
19177 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
19178 /* 10Gb link speed */
19179 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
19180 /* 20Mb link speed */
19181 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
19182 /* 25Gb link speed */
19183 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
19184 /* 40Gb link speed */
19185 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
19186 /* 50Gb link speed */
19187 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
19188 /* 100Gb link speed */
19189 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
19190 /* 200Gb link speed */
19191 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
19192 /* 10Mb link speed */
19193 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
19194 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
19195 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
19197 * This value is indicates the duplex of the current
19200 uint8_t duplex_cfg;
19201 /* Half Duplex connection. */
19202 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
19203 /* Full duplex connection. */
19204 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
19205 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
19206 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
19208 * This value is used to indicate the current
19209 * pause configuration. When autoneg is enabled, this value
19210 * represents the autoneg results of pause configuration.
19214 * When this bit is '1', Generation of tx pause messages
19215 * is supported. Disabled otherwise.
19217 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
19219 * When this bit is '1', Reception of rx pause messages
19220 * is supported. Disabled otherwise.
19222 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
19224 * The supported speeds for the port. This is a bit mask.
19225 * For each speed that is supported, the corresponding
19226 * bit will be set to '1'.
19228 uint16_t support_speeds;
19229 /* 100Mb link speed (Half-duplex) */
19230 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
19232 /* 100Mb link speed (Full-duplex) */
19233 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
19235 /* 1Gb link speed (Half-duplex) */
19236 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
19238 /* 1Gb link speed (Full-duplex) */
19239 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
19241 /* 2Gb link speed */
19242 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
19244 /* 25Gb link speed */
19245 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
19247 /* 10Gb link speed */
19248 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
19250 /* 20Gb link speed */
19251 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
19253 /* 25Gb link speed */
19254 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
19256 /* 40Gb link speed */
19257 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
19259 /* 50Gb link speed */
19260 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
19262 /* 100Gb link speed */
19263 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
19265 /* 10Mb link speed (Half-duplex) */
19266 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
19268 /* 10Mb link speed (Full-duplex) */
19269 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
19272 * Current setting of forced link speed.
19273 * When the link speed is not being forced, this
19274 * value shall be set to 0.
19276 uint16_t force_link_speed;
19277 /* 100Mb link speed */
19278 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
19279 /* 1Gb link speed */
19280 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
19281 /* 2Gb link speed */
19282 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
19283 /* 25Gb link speed */
19284 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
19285 /* 10Gb link speed */
19286 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
19287 /* 20Mb link speed */
19288 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
19289 /* 25Gb link speed */
19290 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
19291 /* 40Gb link speed */
19292 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
19294 /* 50Gb link speed */
19295 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
19297 /* 100Gb link speed */
19298 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
19300 /* 10Mb link speed */
19301 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
19303 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
19304 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
19305 /* Current setting of auto negotiation mode. */
19307 /* Disable autoneg or autoneg disabled. No speeds are selected. */
19308 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
19309 /* Select all possible speeds for autoneg mode. */
19310 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
19312 * Select only the auto_link_speed speed for autoneg mode. This mode has
19313 * been DEPRECATED. An HWRM client should not use this mode.
19315 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
19317 * Select the auto_link_speed or any speed below that speed for autoneg.
19318 * This mode has been DEPRECATED. An HWRM client should not use this mode.
19320 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
19322 * Select the speeds based on the corresponding link speed mask value
19323 * that is provided.
19325 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
19326 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
19327 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
19329 * Current setting of pause autonegotiation.
19330 * Move autoneg_pause flag here.
19332 uint8_t auto_pause;
19334 * When this bit is '1', Generation of tx pause messages
19335 * has been requested. Disabled otherwise.
19337 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
19340 * When this bit is '1', Reception of rx pause messages
19341 * has been requested. Disabled otherwise.
19343 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
19346 * When set to 1, the advertisement of pause is enabled.
19348 * # When the auto_mode is not set to none and this flag is
19349 * set to 1, then the auto_pause bits on this port are being
19350 * advertised and autoneg pause results are being interpreted.
19351 * # When the auto_mode is not set to none and this
19352 * flag is set to 0, the pause is forced as indicated in
19353 * force_pause, and also advertised as auto_pause bits, but
19354 * the autoneg results are not interpreted since the pause
19355 * configuration is being forced.
19356 * # When the auto_mode is set to none and this flag is set to
19357 * 1, auto_pause bits should be ignored and should be set to 0.
19359 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
19362 * Current setting for auto_link_speed. This field is only
19363 * valid when auto_mode is set to "one_speed" or "one_or_below".
19365 uint16_t auto_link_speed;
19366 /* 100Mb link speed */
19367 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
19368 /* 1Gb link speed */
19369 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
19370 /* 2Gb link speed */
19371 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
19372 /* 25Gb link speed */
19373 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
19374 /* 10Gb link speed */
19375 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
19376 /* 20Mb link speed */
19377 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
19378 /* 25Gb link speed */
19379 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
19380 /* 40Gb link speed */
19381 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
19382 /* 50Gb link speed */
19383 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
19384 /* 100Gb link speed */
19385 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
19386 /* 10Mb link speed */
19387 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
19389 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
19390 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
19392 * Current setting for auto_link_speed_mask that is used to
19393 * advertise speeds during autonegotiation.
19394 * This field is only valid when auto_mode is set to "mask".
19395 * The speeds specified in this field shall be a subset of
19396 * supported speeds on this port.
19398 uint16_t auto_link_speed_mask;
19399 /* 100Mb link speed (Half-duplex) */
19400 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
19402 /* 100Mb link speed (Full-duplex) */
19403 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
19405 /* 1Gb link speed (Half-duplex) */
19406 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
19408 /* 1Gb link speed (Full-duplex) */
19409 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
19411 /* 2Gb link speed */
19412 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
19414 /* 25Gb link speed */
19415 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
19417 /* 10Gb link speed */
19418 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
19420 /* 20Gb link speed */
19421 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
19423 /* 25Gb link speed */
19424 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
19426 /* 40Gb link speed */
19427 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
19429 /* 50Gb link speed */
19430 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
19432 /* 100Gb link speed */
19433 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
19435 /* 10Mb link speed (Half-duplex) */
19436 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
19438 /* 10Mb link speed (Full-duplex) */
19439 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
19441 /* Current setting for wirespeed. */
19443 /* Wirespeed feature is disabled. */
19444 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
19445 /* Wirespeed feature is enabled. */
19446 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
19447 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
19448 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
19449 /* Current setting for loopback. */
19451 /* No loopback is selected. Normal operation. */
19452 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
19454 * The HW will be configured with local loopback such that
19455 * host data is sent back to the host without modification.
19457 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
19459 * The HW will be configured with remote loopback such that
19460 * port logic will send packets back out the transmitter that
19463 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
19465 * The HW will be configured with external loopback such that
19466 * host data is sent on the transmitter and based on the external
19467 * loopback connection the data will be received without modification.
19469 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
19470 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
19471 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
19473 * Current setting of forced pause.
19474 * When the pause configuration is not being forced, then
19475 * this value shall be set to 0.
19477 uint8_t force_pause;
19479 * When this bit is '1', Generation of tx pause messages
19480 * is supported. Disabled otherwise.
19482 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
19484 * When this bit is '1', Reception of rx pause messages
19485 * is supported. Disabled otherwise.
19487 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
19489 * This value indicates the current status of the optics module on
19492 uint8_t module_status;
19493 /* Module is inserted and accepted */
19494 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
19496 /* Module is rejected and transmit side Laser is disabled. */
19497 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
19499 /* Module mismatch warning. */
19500 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
19502 /* Module is rejected and powered down. */
19503 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
19505 /* Module is not inserted. */
19506 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
19508 /* Module is powered down because of over current fault. */
19509 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
19511 /* Module status is not applicable. */
19512 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
19514 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
19515 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
19516 /* Current setting for preemphasis. */
19517 uint32_t preemphasis;
19518 /* This field represents the major version of the PHY. */
19520 /* This field represents the minor version of the PHY. */
19522 /* This field represents the build version of the PHY. */
19524 /* This value represents a PHY type. */
19527 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
19530 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
19532 /* BASE-KR4 (Deprecated) */
19533 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
19536 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
19539 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
19541 /* BASE-KR2 (Deprecated) */
19542 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
19545 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
19548 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
19551 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
19553 /* EEE capable BASE-T */
19554 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
19556 /* SGMII connected external PHY */
19557 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
19559 /* 25G_BASECR_CA_L */
19560 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
19562 /* 25G_BASECR_CA_S */
19563 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
19565 /* 25G_BASECR_CA_N */
19566 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
19569 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
19572 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
19575 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
19578 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
19581 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
19583 /* 100G_BASESR10 */
19584 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
19587 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
19590 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
19593 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
19596 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
19598 /* 40G_ACTIVE_CABLE */
19599 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
19602 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
19605 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
19608 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
19611 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
19614 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
19617 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
19620 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
19622 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
19623 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
19624 /* This value represents a media type. */
19625 uint8_t media_type;
19627 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
19629 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
19630 /* Direct Attached Copper */
19631 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
19633 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
19634 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
19635 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
19636 /* This value represents a transceiver type. */
19637 uint8_t xcvr_pkg_type;
19638 /* PHY and MAC are in the same package */
19639 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
19641 /* PHY and MAC are in different packages */
19642 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
19644 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
19645 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
19646 uint8_t eee_config_phy_addr;
19647 /* This field represents PHY address. */
19648 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
19650 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
19652 * This field represents flags related to EEE configuration.
19653 * These EEE configuration flags are valid only when the
19654 * auto_mode is not set to none (in other words autonegotiation
19657 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
19659 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
19661 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
19662 * Speeds for autoneg with EEE mode enabled
19663 * are based on eee_link_speed_mask.
19665 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
19668 * This flag is valid only when eee_enabled is set to 1.
19670 * # If eee_enabled is set to 0, then EEE mode is disabled
19671 * and this flag shall be ignored.
19672 * # If eee_enabled is set to 1 and this flag is set to 1,
19673 * then Energy Efficient Ethernet (EEE) mode is enabled
19675 * # If eee_enabled is set to 1 and this flag is set to 0,
19676 * then Energy Efficient Ethernet (EEE) mode is enabled
19677 * but is currently not in use.
19679 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
19682 * This flag is valid only when eee_enabled is set to 1.
19684 * # If eee_enabled is set to 0, then EEE mode is disabled
19685 * and this flag shall be ignored.
19686 * # If eee_enabled is set to 1 and this flag is set to 1,
19687 * then Energy Efficient Ethernet (EEE) mode is enabled
19688 * and TX LPI is enabled.
19689 * # If eee_enabled is set to 1 and this flag is set to 0,
19690 * then Energy Efficient Ethernet (EEE) mode is enabled
19691 * but TX LPI is disabled.
19693 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
19696 * When set to 1, the parallel detection is used to determine
19697 * the speed of the link partner.
19699 * Parallel detection is used when a autonegotiation capable
19700 * device is connected to a link parter that is not capable
19701 * of autonegotiation.
19703 uint8_t parallel_detect;
19705 * When set to 1, the parallel detection is used to determine
19706 * the speed of the link partner.
19708 * Parallel detection is used when a autonegotiation capable
19709 * device is connected to a link parter that is not capable
19710 * of autonegotiation.
19712 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
19714 * The advertised speeds for the port by the link partner.
19715 * Each advertised speed will be set to '1'.
19717 uint16_t link_partner_adv_speeds;
19718 /* 100Mb link speed (Half-duplex) */
19719 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
19721 /* 100Mb link speed (Full-duplex) */
19722 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
19724 /* 1Gb link speed (Half-duplex) */
19725 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
19727 /* 1Gb link speed (Full-duplex) */
19728 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
19730 /* 2Gb link speed */
19731 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
19733 /* 25Gb link speed */
19734 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
19736 /* 10Gb link speed */
19737 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
19739 /* 20Gb link speed */
19740 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
19742 /* 25Gb link speed */
19743 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
19745 /* 40Gb link speed */
19746 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
19748 /* 50Gb link speed */
19749 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
19751 /* 100Gb link speed */
19752 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
19754 /* 10Mb link speed (Half-duplex) */
19755 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
19757 /* 10Mb link speed (Full-duplex) */
19758 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
19761 * The advertised autoneg for the port by the link partner.
19762 * This field is deprecated and should be set to 0.
19764 uint8_t link_partner_adv_auto_mode;
19765 /* Disable autoneg or autoneg disabled. No speeds are selected. */
19766 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
19768 /* Select all possible speeds for autoneg mode. */
19769 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
19772 * Select only the auto_link_speed speed for autoneg mode. This mode has
19773 * been DEPRECATED. An HWRM client should not use this mode.
19775 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
19778 * Select the auto_link_speed or any speed below that speed for autoneg.
19779 * This mode has been DEPRECATED. An HWRM client should not use this mode.
19781 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
19784 * Select the speeds based on the corresponding link speed mask value
19785 * that is provided.
19787 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
19789 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
19790 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
19791 /* The advertised pause settings on the port by the link partner. */
19792 uint8_t link_partner_adv_pause;
19794 * When this bit is '1', Generation of tx pause messages
19795 * is supported. Disabled otherwise.
19797 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
19800 * When this bit is '1', Reception of rx pause messages
19801 * is supported. Disabled otherwise.
19803 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
19806 * Current setting for link speed mask that is used to
19807 * advertise speeds during autonegotiation when EEE is enabled.
19808 * This field is valid only when eee_enabled flags is set to 1.
19809 * The speeds specified in this field shall be a subset of
19810 * speeds specified in auto_link_speed_mask.
19812 uint16_t adv_eee_link_speed_mask;
19814 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
19816 /* 100Mb link speed (Full-duplex) */
19817 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
19820 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
19822 /* 1Gb link speed (Full-duplex) */
19823 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
19826 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
19829 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
19831 /* 10Gb link speed */
19832 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
19835 * Current setting for link speed mask that is advertised by
19836 * the link partner when EEE is enabled.
19837 * This field is valid only when eee_enabled flags is set to 1.
19839 uint16_t link_partner_adv_eee_link_speed_mask;
19841 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
19843 /* 100Mb link speed (Full-duplex) */
19844 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
19847 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
19849 /* 1Gb link speed (Full-duplex) */
19850 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
19853 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
19856 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
19858 /* 10Gb link speed */
19859 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
19861 uint32_t xcvr_identifier_type_tx_lpi_timer;
19863 * Current setting of TX LPI timer in microseconds.
19864 * This field is valid only when_eee_enabled flag is set to 1
19865 * and tx_lpi_enabled is set to 1.
19867 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
19869 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
19870 /* This value represents transceiver identifier type. */
19871 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
19872 UINT32_C(0xff000000)
19873 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
19875 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
19876 (UINT32_C(0x0) << 24)
19877 /* SFP/SFP+/SFP28 */
19878 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
19879 (UINT32_C(0x3) << 24)
19881 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
19882 (UINT32_C(0xc) << 24)
19884 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
19885 (UINT32_C(0xd) << 24)
19887 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
19888 (UINT32_C(0x11) << 24)
19889 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
19890 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
19892 * This value represents the current configuration of
19893 * Forward Error Correction (FEC) on the port.
19897 * When set to 1, then FEC is not supported on this port. If this flag
19898 * is set to 1, then all other FEC configuration flags shall be ignored.
19899 * When set to 0, then FEC is supported as indicated by other
19900 * configuration flags.
19902 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
19905 * When set to 1, then FEC autonegotiation is supported on this port.
19906 * When set to 0, then FEC autonegotiation is not supported on this port.
19908 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
19911 * When set to 1, then FEC autonegotiation is enabled on this port.
19912 * When set to 0, then FEC autonegotiation is disabled if supported.
19913 * This flag should be ignored if FEC autonegotiation is not supported on this port.
19915 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
19918 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
19919 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
19921 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
19924 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
19925 * port. This means that FEC CLAUSE 74 is either advertised if
19926 * FEC autonegotiation is enabled or FEC CLAUSE 74 is force enabled.
19927 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
19928 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
19930 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
19933 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
19934 * NRZ) is supported on this port.
19935 * When set to 0, then FEC RS(528,418) is not supported on this port.
19937 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
19940 * When set to 1, then FEC CLAUSE 91 (Reed Solomon RS(528,514) for
19941 * NRZ) is enabled on this port. This means that FEC RS(528,514) is
19942 * either advertised if FEC autonegotiation is enabled or FEC
19943 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
19944 * is disabled if supported.
19945 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
19947 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
19950 * When set to 1, then FEC RS544_1XN is supported on this port.
19951 * When set to 0, then FEC RS544_1XN is not supported on this port.
19953 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED \
19956 * When set to 1, then RS544_1XN is enabled on this
19957 * port. This means that FEC RS544_1XN is either advertised if
19958 * FEC autonegotiation is enabled or FEC RS544_1XN is force enabled.
19959 * When set to 0, then FEC RS544_1XN is disabled if supported.
19960 * This flag should be ignored if FEC RS544_1XN is not supported on this port.
19962 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED \
19965 * When set to 1, then FEC RS(544,514) is supported on this port.
19966 * When set to 0, then FEC RS(544,514) is not supported on this port.
19968 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED \
19971 * When set to 1, then RS(544,514) is enabled on this
19972 * port. This means that FEC RS(544,514) is either advertised if
19973 * FEC autonegotiation is enabled or FEC RS(544,514) is force
19974 * enabled. When set to 0, then FEC RS(544,514) is disabled if supported.
19975 * This flag should be ignored if FEC RS(544,514) is not supported on this port.
19977 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED \
19980 * When set to 1, then FEC RS272_1XN is supported on this port.
19981 * When set to 0, then FEC RS272_1XN is not supported on this port.
19983 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED \
19986 * When set to 1, then RS272_1XN is enabled on this
19987 * port. This means that FEC RS272_1XN is either advertised if
19988 * FEC autonegotiation is enabled or FEC RS272_1XN is force
19989 * enabled. When set to 0, then FEC RS272_1XN is disabled if supported.
19990 * This flag should be ignored if FEC RS272_1XN is not supported on this port.
19992 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED \
19995 * When set to 1, then FEC RS(272,514) is supported on this port.
19996 * When set to 0, then FEC RS(272,514) is not supported on this port.
19998 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED \
20001 * When set to 1, then RS(272,257) is enabled on this
20002 * port. This means that FEC RS(272,257) is either advertised if
20003 * FEC autonegotiation is enabled or FEC RS(272,257) is force
20004 * enabled. When set to 0, then FEC RS(272,257) is disabled if supported.
20005 * This flag should be ignored if FEC RS(272,257) is not supported on this port.
20007 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED \
20010 * This value is indicates the duplex of the current
20011 * connection state.
20013 uint8_t duplex_state;
20014 /* Half Duplex connection. */
20015 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
20016 /* Full duplex connection. */
20017 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
20018 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
20019 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
20020 /* Option flags fields. */
20021 uint8_t option_flags;
20022 /* When this bit is '1', Media auto detect is enabled. */
20023 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
20026 * When this bit is '1', active_fec_signal_mode can be
20029 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \
20032 * Up to 16 bytes of null padded ASCII string representing
20034 * If the string is set to null, then the vendor name is not
20037 char phy_vendor_name[16];
20039 * Up to 16 bytes of null padded ASCII string that
20040 * identifies vendor specific part number of the PHY.
20041 * If the string is set to null, then the vendor specific
20042 * part number is not available.
20044 char phy_vendor_partnumber[16];
20046 * The supported PAM4 speeds for the port. This is a bit mask.
20047 * For each speed that is supported, the corresponding
20048 * bit will be set to '1'.
20050 uint16_t support_pam4_speeds;
20051 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G \
20053 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G \
20055 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G \
20058 * Current setting of forced PAM4 link speed.
20059 * When the link speed is not being forced, this
20060 * value shall be set to 0.
20062 uint16_t force_pam4_link_speed;
20063 /* 50Gb link speed */
20064 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB \
20066 /* 100Gb link speed */
20067 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB \
20069 /* 200Gb link speed */
20070 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB \
20072 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_LAST \
20073 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB
20075 * Current setting for auto_pam4_link_speed_mask that is used to
20076 * advertise speeds during autonegotiation.
20077 * This field is only valid when auto_mode is set to "mask".
20078 * The speeds specified in this field shall be a subset of
20079 * supported speeds on this port.
20081 uint16_t auto_pam4_link_speed_mask;
20082 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G \
20084 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G \
20086 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G \
20089 * The advertised PAM4 speeds for the port by the link partner.
20090 * Each advertised speed will be set to '1'.
20092 uint8_t link_partner_pam4_adv_speeds;
20093 /* 50Gb link speed */
20094 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB \
20096 /* 100Gb link speed */
20097 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB \
20099 /* 200Gb link speed */
20100 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \
20103 * This field is used in Output records to indicate that the output
20104 * is completely written to RAM. This field should be read as '1'
20105 * to indicate that the output has been completely written.
20106 * When writing a command completion or response to an internal processor,
20107 * the order of writes has to be such that this field is written last.
20112 /*********************
20113 * hwrm_port_mac_cfg *
20114 *********************/
20117 /* hwrm_port_mac_cfg_input (size:384b/48B) */
20118 struct hwrm_port_mac_cfg_input {
20119 /* The HWRM command request type. */
20122 * The completion ring to send the completion event on. This should
20123 * be the NQ ID returned from the `nq_alloc` HWRM command.
20125 uint16_t cmpl_ring;
20127 * The sequence ID is used by the driver for tracking multiple
20128 * commands. This ID is treated as opaque data by the firmware and
20129 * the value is returned in the `hwrm_resp_hdr` upon completion.
20133 * The target ID of the command:
20134 * * 0x0-0xFFF8 - The function ID
20135 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20136 * * 0xFFFD - Reserved for user-space HWRM interface
20139 uint16_t target_id;
20141 * A physical address pointer pointing to a host buffer that the
20142 * command's response data will be written. This can be either a host
20143 * physical address (HPA) or a guest physical address (GPA) and must
20144 * point to a physically contiguous block of memory.
20146 uint64_t resp_addr;
20148 * In this field, there are a number of CoS mappings related flags
20149 * that are used to configure CoS mappings and their corresponding
20150 * priorities in the hardware.
20151 * For the priorities of CoS mappings, the HWRM uses the following
20152 * priority order (high to low) by default:
20155 * # tunnel_vlan_pri
20158 * A subset of CoS mappings can be enabled.
20159 * If a priority is not specified for an enabled CoS mapping, the
20160 * priority will be assigned in the above order for the enabled CoS
20161 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
20162 * enabled and their priorities are not specified, the following
20163 * priority order (high to low) will be used by the HWRM:
20168 * vlan_pri CoS mapping together with default CoS with lower priority
20169 * are enabled by default by the HWRM.
20173 * When this bit is '1', this command will configure
20174 * the MAC to match the current link state of the PHY.
20175 * If the link is not established on the PHY, then this
20176 * bit has no effect.
20178 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
20181 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20182 * is requested to be enabled.
20184 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
20187 * When this bit is set to '1', tunnel VLAN PRI field to
20188 * CoS mapping is requested to be enabled.
20190 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
20193 * When this bit is set to '1', the IP DSCP to CoS mapping is
20194 * requested to be enabled.
20196 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
20199 * When this bit is '1', the HWRM is requested to
20200 * enable timestamp capture capability on the receive side
20203 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
20206 * When this bit is '1', the HWRM is requested to
20207 * disable timestamp capture capability on the receive side
20210 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
20213 * When this bit is '1', the HWRM is requested to
20214 * enable timestamp capture capability on the transmit side
20217 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
20220 * When this bit is '1', the HWRM is requested to
20221 * disable timestamp capture capability on the transmit side
20224 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
20227 * When this bit is '1', the Out-Of-Box WoL is requested to
20228 * be enabled on this port.
20230 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
20233 * When this bit is '1', the Out-Of-Box WoL is requested to
20234 * be disabled on this port.
20236 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
20239 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20240 * is requested to be disabled.
20242 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
20245 * When this bit is set to '1', tunnel VLAN PRI field to
20246 * CoS mapping is requested to be disabled.
20248 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
20251 * When this bit is set to '1', the IP DSCP to CoS mapping is
20252 * requested to be disabled.
20254 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
20257 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
20258 * bit is set, then the device uses one step Tx timestamping.
20259 * This bit is temporary and used for experimental purposes.
20261 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
20265 * This bit must be '1' for the ipg field to be
20268 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
20271 * This bit must be '1' for the lpbk field to be
20274 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
20277 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
20280 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
20283 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
20286 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
20289 * This bit must be '1' for the dscp2cos_map_pri field to be
20292 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
20295 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
20298 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
20301 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
20304 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
20307 * This bit must be '1' for the cos_field_cfg field to be
20310 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
20313 * This bit must be '1' for the ptp_freq_adj_ppb field to be
20316 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
20318 /* Port ID of port that is to be configured. */
20321 * This value is used to configure the minimum IPG that will
20322 * be sent between packets by this port.
20325 /* This value controls the loopback setting for the MAC. */
20327 /* No loopback is selected. Normal operation. */
20328 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
20330 * The HW will be configured with local loopback such that
20331 * host data is sent back to the host without modification.
20333 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
20335 * The HW will be configured with remote loopback such that
20336 * port logic will send packets back out the transmitter that
20339 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
20340 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
20341 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
20343 * This value controls the priority setting of VLAN PRI to CoS
20344 * mapping based on VLAN Tags of inner packet headers of
20345 * tunneled packets or packet headers of non-tunneled packets.
20347 * # Each XXX_pri variable shall have a unique priority value
20348 * when it is being specified.
20349 * # When comparing priorities of mappings, higher value
20350 * indicates higher priority.
20351 * For example, a value of 0-3 is returned where 0 is being
20352 * the lowest priority and 3 is being the highest priority.
20354 uint8_t vlan_pri2cos_map_pri;
20355 /* Reserved field. */
20358 * This value controls the priority setting of VLAN PRI to CoS
20359 * mapping based on VLAN Tags of tunneled header.
20360 * This mapping only applies when tunneled headers
20363 * # Each XXX_pri variable shall have a unique priority value
20364 * when it is being specified.
20365 * # When comparing priorities of mappings, higher value
20366 * indicates higher priority.
20367 * For example, a value of 0-3 is returned where 0 is being
20368 * the lowest priority and 3 is being the highest priority.
20370 uint8_t tunnel_pri2cos_map_pri;
20372 * This value controls the priority setting of IP DSCP to CoS
20373 * mapping based on inner IP header of tunneled packets or
20374 * IP header of non-tunneled packets.
20376 * # Each XXX_pri variable shall have a unique priority value
20377 * when it is being specified.
20378 * # When comparing priorities of mappings, higher value
20379 * indicates higher priority.
20380 * For example, a value of 0-3 is returned where 0 is being
20381 * the lowest priority and 3 is being the highest priority.
20383 uint8_t dscp2pri_map_pri;
20385 * This is a 16-bit bit mask that is used to request a
20386 * specific configuration of time stamp capture of PTP messages
20387 * on the receive side of this port.
20388 * This field shall be ignored if the ptp_rx_ts_capture_enable
20389 * flag is not set in this command.
20390 * Otherwise, if bit 'i' is set, then the HWRM is being
20391 * requested to configure the receive side of the port to
20392 * capture the time stamp of every received PTP message
20393 * with messageType field value set to i.
20395 uint16_t rx_ts_capture_ptp_msg_type;
20397 * This is a 16-bit bit mask that is used to request a
20398 * specific configuration of time stamp capture of PTP messages
20399 * on the transmit side of this port.
20400 * This field shall be ignored if the ptp_tx_ts_capture_enable
20401 * flag is not set in this command.
20402 * Otherwise, if bit 'i' is set, then the HWRM is being
20403 * requested to configure the transmit side of the port to
20404 * capture the time stamp of every transmitted PTP message
20405 * with messageType field value set to i.
20407 uint16_t tx_ts_capture_ptp_msg_type;
20408 /* Configuration of CoS fields. */
20409 uint8_t cos_field_cfg;
20411 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
20414 * This field is used to specify selection of VLAN PRI value
20415 * based on whether one or two VLAN Tags are present in
20416 * the inner packet headers of tunneled packets or
20417 * non-tunneled packets.
20418 * This field is valid only if inner VLAN PRI to CoS mapping
20420 * If VLAN PRI to CoS mapping is not enabled, then this
20421 * field shall be ignored.
20423 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
20425 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
20428 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20429 * present in the inner packet headers
20431 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
20432 (UINT32_C(0x0) << 1)
20434 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20435 * present in the inner packet headers.
20436 * No VLAN PRI shall be selected for this configuration
20437 * if only one VLAN Tag is present in the inner
20440 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
20441 (UINT32_C(0x1) << 1)
20443 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20444 * are present in the inner packet headers
20446 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
20447 (UINT32_C(0x2) << 1)
20449 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
20450 (UINT32_C(0x3) << 1)
20451 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
20452 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
20454 * This field is used to specify selection of tunnel VLAN
20455 * PRI value based on whether one or two VLAN Tags are
20456 * present in tunnel headers.
20457 * This field is valid only if tunnel VLAN PRI to CoS mapping
20459 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
20460 * field shall be ignored.
20462 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
20464 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
20467 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20468 * present in the tunnel packet headers
20470 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
20471 (UINT32_C(0x0) << 3)
20473 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20474 * present in the tunnel packet headers.
20475 * No tunnel VLAN PRI shall be selected for this
20476 * configuration if only one VLAN Tag is present in
20477 * the tunnel packet headers.
20479 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
20480 (UINT32_C(0x1) << 3)
20482 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20483 * are present in the tunnel packet headers
20485 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
20486 (UINT32_C(0x2) << 3)
20488 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
20489 (UINT32_C(0x3) << 3)
20490 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
20491 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
20493 * This field shall be used to provide default CoS value
20494 * that has been configured on this port.
20495 * This field is valid only if default CoS mapping
20497 * If default CoS mapping is not enabled, then this
20498 * field shall be ignored.
20500 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
20502 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
20504 uint8_t unused_0[3];
20506 * This signed field specifies by how much to adjust the frequency
20507 * of sync timer updates (measured in parts per billion).
20509 int32_t ptp_freq_adj_ppb;
20510 uint8_t unused_1[4];
20513 /* hwrm_port_mac_cfg_output (size:128b/16B) */
20514 struct hwrm_port_mac_cfg_output {
20515 /* The specific error status for the command. */
20516 uint16_t error_code;
20517 /* The HWRM command request type. */
20519 /* The sequence ID from the original command. */
20521 /* The length of the response data in number of bytes. */
20524 * This is the configured maximum length of Ethernet packet
20525 * payload that is allowed to be received on the port.
20526 * This value does not include the number of bytes used by
20527 * Ethernet header and trailer (CRC).
20531 * This is the configured maximum length of Ethernet packet
20532 * payload that is allowed to be transmitted on the port.
20533 * This value does not include the number of bytes used by
20534 * Ethernet header and trailer (CRC).
20537 /* Current configuration of the IPG value. */
20539 /* Current value of the loopback value. */
20541 /* No loopback is selected. Normal operation. */
20542 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
20544 * The HW will be configured with local loopback such that
20545 * host data is sent back to the host without modification.
20547 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
20549 * The HW will be configured with remote loopback such that
20550 * port logic will send packets back out the transmitter that
20553 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
20554 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
20555 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
20558 * This field is used in Output records to indicate that the output
20559 * is completely written to RAM. This field should be read as '1'
20560 * to indicate that the output has been completely written.
20561 * When writing a command completion or response to an internal processor,
20562 * the order of writes has to be such that this field is written last.
20567 /**********************
20568 * hwrm_port_mac_qcfg *
20569 **********************/
20572 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
20573 struct hwrm_port_mac_qcfg_input {
20574 /* The HWRM command request type. */
20577 * The completion ring to send the completion event on. This should
20578 * be the NQ ID returned from the `nq_alloc` HWRM command.
20580 uint16_t cmpl_ring;
20582 * The sequence ID is used by the driver for tracking multiple
20583 * commands. This ID is treated as opaque data by the firmware and
20584 * the value is returned in the `hwrm_resp_hdr` upon completion.
20588 * The target ID of the command:
20589 * * 0x0-0xFFF8 - The function ID
20590 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20591 * * 0xFFFD - Reserved for user-space HWRM interface
20594 uint16_t target_id;
20596 * A physical address pointer pointing to a host buffer that the
20597 * command's response data will be written. This can be either a host
20598 * physical address (HPA) or a guest physical address (GPA) and must
20599 * point to a physically contiguous block of memory.
20601 uint64_t resp_addr;
20602 /* Port ID of port that is to be configured. */
20604 uint8_t unused_0[6];
20607 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
20608 struct hwrm_port_mac_qcfg_output {
20609 /* The specific error status for the command. */
20610 uint16_t error_code;
20611 /* The HWRM command request type. */
20613 /* The sequence ID from the original command. */
20615 /* The length of the response data in number of bytes. */
20618 * This is the configured maximum length of Ethernet packet
20619 * payload that is allowed to be received on the port.
20620 * This value does not include the number of bytes used by the
20621 * Ethernet header and trailer (CRC).
20625 * This is the configured maximum length of Ethernet packet
20626 * payload that is allowed to be transmitted on the port.
20627 * This value does not include the number of bytes used by the
20628 * Ethernet header and trailer (CRC).
20632 * The minimum IPG that will
20633 * be sent between packets by this port.
20636 /* The loopback setting for the MAC. */
20638 /* No loopback is selected. Normal operation. */
20639 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
20641 * The HW will be configured with local loopback such that
20642 * host data is sent back to the host without modification.
20644 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
20646 * The HW will be configured with remote loopback such that
20647 * port logic will send packets back out the transmitter that
20650 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
20651 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
20652 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
20654 * Priority setting for VLAN PRI to CoS mapping.
20655 * # Each XXX_pri variable shall have a unique priority value
20656 * when it is being used.
20657 * # When comparing priorities of mappings, higher value
20658 * indicates higher priority.
20659 * For example, a value of 0-3 is returned where 0 is being
20660 * the lowest priority and 3 is being the highest priority.
20661 * # If the correspoding CoS mapping is not enabled, then this
20662 * field should be ignored.
20663 * # This value indicates the normalized priority value retained
20666 uint8_t vlan_pri2cos_map_pri;
20668 * In this field, a number of CoS mappings related flags
20669 * are used to indicate configured CoS mappings.
20673 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
20676 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
20679 * When this bit is set to '1', tunnel VLAN PRI field to
20680 * CoS mapping is enabled.
20682 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
20685 * When this bit is set to '1', the IP DSCP to CoS mapping is
20688 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
20691 * When this bit is '1', the Out-Of-Box WoL is enabled on this
20694 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
20696 /* When this bit is '1', PTP is enabled for RX on this port. */
20697 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
20699 /* When this bit is '1', PTP is enabled for TX on this port. */
20700 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
20703 * Priority setting for tunnel VLAN PRI to CoS mapping.
20704 * # Each XXX_pri variable shall have a unique priority value
20705 * when it is being used.
20706 * # When comparing priorities of mappings, higher value
20707 * indicates higher priority.
20708 * For example, a value of 0-3 is returned where 0 is being
20709 * the lowest priority and 3 is being the highest priority.
20710 * # If the correspoding CoS mapping is not enabled, then this
20711 * field should be ignored.
20712 * # This value indicates the normalized priority value retained
20715 uint8_t tunnel_pri2cos_map_pri;
20717 * Priority setting for DSCP to PRI mapping.
20718 * # Each XXX_pri variable shall have a unique priority value
20719 * when it is being used.
20720 * # When comparing priorities of mappings, higher value
20721 * indicates higher priority.
20722 * For example, a value of 0-3 is returned where 0 is being
20723 * the lowest priority and 3 is being the highest priority.
20724 * # If the correspoding CoS mapping is not enabled, then this
20725 * field should be ignored.
20726 * # This value indicates the normalized priority value retained
20729 uint8_t dscp2pri_map_pri;
20731 * This is a 16-bit bit mask that represents the
20732 * current configuration of time stamp capture of PTP messages
20733 * on the receive side of this port.
20734 * If bit 'i' is set, then the receive side of the port
20735 * is configured to capture the time stamp of every
20736 * received PTP message with messageType field value set
20738 * If all bits are set to 0 (i.e. field value set 0),
20739 * then the receive side of the port is not configured
20740 * to capture timestamp for PTP messages.
20741 * If all bits are set to 1, then the receive side of the
20742 * port is configured to capture timestamp for all PTP
20745 uint16_t rx_ts_capture_ptp_msg_type;
20747 * This is a 16-bit bit mask that represents the
20748 * current configuration of time stamp capture of PTP messages
20749 * on the transmit side of this port.
20750 * If bit 'i' is set, then the transmit side of the port
20751 * is configured to capture the time stamp of every
20752 * received PTP message with messageType field value set
20754 * If all bits are set to 0 (i.e. field value set 0),
20755 * then the transmit side of the port is not configured
20756 * to capture timestamp for PTP messages.
20757 * If all bits are set to 1, then the transmit side of the
20758 * port is configured to capture timestamp for all PTP
20761 uint16_t tx_ts_capture_ptp_msg_type;
20762 /* Configuration of CoS fields. */
20763 uint8_t cos_field_cfg;
20765 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
20768 * This field is used for selecting VLAN PRI value
20769 * based on whether one or two VLAN Tags are present in
20770 * the inner packet headers of tunneled packets or
20771 * non-tunneled packets.
20773 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
20775 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
20778 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20779 * present in the inner packet headers
20781 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
20782 (UINT32_C(0x0) << 1)
20784 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20785 * present in the inner packet headers.
20786 * No VLAN PRI is selected for this configuration
20787 * if only one VLAN Tag is present in the inner
20790 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
20791 (UINT32_C(0x1) << 1)
20793 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20794 * are present in the inner packet headers
20796 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
20797 (UINT32_C(0x2) << 1)
20799 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
20800 (UINT32_C(0x3) << 1)
20801 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
20802 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
20804 * This field is used for selecting tunnel VLAN PRI value
20805 * based on whether one or two VLAN Tags are present in
20806 * the tunnel headers of tunneled packets. This selection
20807 * does not apply to non-tunneled packets.
20809 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
20811 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
20814 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
20815 * present in the tunnel packet headers
20817 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
20818 (UINT32_C(0x0) << 3)
20820 * Select outer VLAN Tag PRI when 2 VLAN Tags are
20821 * present in the tunnel packet headers.
20822 * No VLAN PRI is selected for this configuration
20823 * if only one VLAN Tag is present in the tunnel
20826 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
20827 (UINT32_C(0x1) << 3)
20829 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
20830 * are present in the tunnel packet headers
20832 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
20833 (UINT32_C(0x2) << 3)
20835 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
20836 (UINT32_C(0x3) << 3)
20837 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
20838 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
20840 * This field is used to provide default CoS value that
20841 * has been configured on this port.
20843 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
20845 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
20848 uint16_t port_svif_info;
20850 * This field specifies the source virtual interface of the port being
20851 * queried. Drivers can use this to program port svif field in the
20854 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
20856 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
20857 /* This field specifies whether port_svif is valid or not */
20858 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
20860 uint8_t unused_2[5];
20862 * This field is used in Output records to indicate that the output
20863 * is completely written to RAM. This field should be read as '1'
20864 * to indicate that the output has been completely written.
20865 * When writing a command completion or response to an internal processor,
20866 * the order of writes has to be such that this field is written last.
20871 /**************************
20872 * hwrm_port_mac_ptp_qcfg *
20873 **************************/
20876 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
20877 struct hwrm_port_mac_ptp_qcfg_input {
20878 /* The HWRM command request type. */
20881 * The completion ring to send the completion event on. This should
20882 * be the NQ ID returned from the `nq_alloc` HWRM command.
20884 uint16_t cmpl_ring;
20886 * The sequence ID is used by the driver for tracking multiple
20887 * commands. This ID is treated as opaque data by the firmware and
20888 * the value is returned in the `hwrm_resp_hdr` upon completion.
20892 * The target ID of the command:
20893 * * 0x0-0xFFF8 - The function ID
20894 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20895 * * 0xFFFD - Reserved for user-space HWRM interface
20898 uint16_t target_id;
20900 * A physical address pointer pointing to a host buffer that the
20901 * command's response data will be written. This can be either a host
20902 * physical address (HPA) or a guest physical address (GPA) and must
20903 * point to a physically contiguous block of memory.
20905 uint64_t resp_addr;
20906 /* Port ID of port that is being queried. */
20908 uint8_t unused_0[6];
20911 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
20912 struct hwrm_port_mac_ptp_qcfg_output {
20913 /* The specific error status for the command. */
20914 uint16_t error_code;
20915 /* The HWRM command request type. */
20917 /* The sequence ID from the original command. */
20919 /* The length of the response data in number of bytes. */
20922 * In this field, a number of PTP related flags
20923 * are used to indicate configured PTP capabilities.
20927 * When this bit is set to '1', the PTP related registers are
20928 * directly accessible by the host.
20930 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
20933 * When this bit is set to '1', the device supports one-step
20936 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
20939 * When this bit is set to '1', the PTP information is accessible
20940 * via HWRM commands.
20942 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
20944 uint8_t unused_0[3];
20945 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
20946 uint32_t rx_ts_reg_off_lower;
20947 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
20948 uint32_t rx_ts_reg_off_upper;
20949 /* Offset of the PTP register for the sequence ID for RX. */
20950 uint32_t rx_ts_reg_off_seq_id;
20951 /* Offset of the first PTP source ID for RX. */
20952 uint32_t rx_ts_reg_off_src_id_0;
20953 /* Offset of the second PTP source ID for RX. */
20954 uint32_t rx_ts_reg_off_src_id_1;
20955 /* Offset of the third PTP source ID for RX. */
20956 uint32_t rx_ts_reg_off_src_id_2;
20957 /* Offset of the domain ID for RX. */
20958 uint32_t rx_ts_reg_off_domain_id;
20959 /* Offset of the PTP FIFO register for RX. */
20960 uint32_t rx_ts_reg_off_fifo;
20961 /* Offset of the PTP advance FIFO register for RX. */
20962 uint32_t rx_ts_reg_off_fifo_adv;
20963 /* PTP timestamp granularity for RX. */
20964 uint32_t rx_ts_reg_off_granularity;
20965 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
20966 uint32_t tx_ts_reg_off_lower;
20967 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
20968 uint32_t tx_ts_reg_off_upper;
20969 /* Offset of the PTP register for the sequence ID for TX. */
20970 uint32_t tx_ts_reg_off_seq_id;
20971 /* Offset of the PTP FIFO register for TX. */
20972 uint32_t tx_ts_reg_off_fifo;
20973 /* PTP timestamp granularity for TX. */
20974 uint32_t tx_ts_reg_off_granularity;
20975 uint8_t unused_1[7];
20977 * This field is used in Output records to indicate that the output
20978 * is completely written to RAM. This field should be read as '1'
20979 * to indicate that the output has been completely written.
20980 * When writing a command completion or response to an internal processor,
20981 * the order of writes has to be such that this field is written last.
20986 /* Port Tx Statistics Format */
20987 /* tx_port_stats (size:3264b/408B) */
20988 struct tx_port_stats {
20989 /* Total Number of 64 Bytes frames transmitted */
20990 uint64_t tx_64b_frames;
20991 /* Total Number of 65-127 Bytes frames transmitted */
20992 uint64_t tx_65b_127b_frames;
20993 /* Total Number of 128-255 Bytes frames transmitted */
20994 uint64_t tx_128b_255b_frames;
20995 /* Total Number of 256-511 Bytes frames transmitted */
20996 uint64_t tx_256b_511b_frames;
20997 /* Total Number of 512-1023 Bytes frames transmitted */
20998 uint64_t tx_512b_1023b_frames;
20999 /* Total Number of 1024-1518 Bytes frames transmitted */
21000 uint64_t tx_1024b_1518b_frames;
21002 * Total Number of each good VLAN (exludes FCS errors)
21003 * frame transmitted which is 1519 to 1522 bytes in length
21004 * inclusive (excluding framing bits but including FCS bytes).
21006 uint64_t tx_good_vlan_frames;
21007 /* Total Number of 1519-2047 Bytes frames transmitted */
21008 uint64_t tx_1519b_2047b_frames;
21009 /* Total Number of 2048-4095 Bytes frames transmitted */
21010 uint64_t tx_2048b_4095b_frames;
21011 /* Total Number of 4096-9216 Bytes frames transmitted */
21012 uint64_t tx_4096b_9216b_frames;
21013 /* Total Number of 9217-16383 Bytes frames transmitted */
21014 uint64_t tx_9217b_16383b_frames;
21015 /* Total Number of good frames transmitted */
21016 uint64_t tx_good_frames;
21017 /* Total Number of frames transmitted */
21018 uint64_t tx_total_frames;
21019 /* Total number of unicast frames transmitted */
21020 uint64_t tx_ucast_frames;
21021 /* Total number of multicast frames transmitted */
21022 uint64_t tx_mcast_frames;
21023 /* Total number of broadcast frames transmitted */
21024 uint64_t tx_bcast_frames;
21025 /* Total number of PAUSE control frames transmitted */
21026 uint64_t tx_pause_frames;
21028 * Total number of PFC/per-priority PAUSE
21029 * control frames transmitted
21031 uint64_t tx_pfc_frames;
21032 /* Total number of jabber frames transmitted */
21033 uint64_t tx_jabber_frames;
21034 /* Total number of frames transmitted with FCS error */
21035 uint64_t tx_fcs_err_frames;
21036 /* Total number of control frames transmitted */
21037 uint64_t tx_control_frames;
21038 /* Total number of over-sized frames transmitted */
21039 uint64_t tx_oversz_frames;
21040 /* Total number of frames with single deferral */
21041 uint64_t tx_single_dfrl_frames;
21042 /* Total number of frames with multiple deferrals */
21043 uint64_t tx_multi_dfrl_frames;
21044 /* Total number of frames with single collision */
21045 uint64_t tx_single_coll_frames;
21046 /* Total number of frames with multiple collisions */
21047 uint64_t tx_multi_coll_frames;
21048 /* Total number of frames with late collisions */
21049 uint64_t tx_late_coll_frames;
21050 /* Total number of frames with excessive collisions */
21051 uint64_t tx_excessive_coll_frames;
21052 /* Total number of fragmented frames transmitted */
21053 uint64_t tx_frag_frames;
21054 /* Total number of transmit errors */
21056 /* Total number of single VLAN tagged frames transmitted */
21057 uint64_t tx_tagged_frames;
21058 /* Total number of double VLAN tagged frames transmitted */
21059 uint64_t tx_dbl_tagged_frames;
21060 /* Total number of runt frames transmitted */
21061 uint64_t tx_runt_frames;
21062 /* Total number of TX FIFO under runs */
21063 uint64_t tx_fifo_underruns;
21065 * Total number of PFC frames with PFC enabled bit for
21066 * Pri 0 transmitted
21068 uint64_t tx_pfc_ena_frames_pri0;
21070 * Total number of PFC frames with PFC enabled bit for
21071 * Pri 1 transmitted
21073 uint64_t tx_pfc_ena_frames_pri1;
21075 * Total number of PFC frames with PFC enabled bit for
21076 * Pri 2 transmitted
21078 uint64_t tx_pfc_ena_frames_pri2;
21080 * Total number of PFC frames with PFC enabled bit for
21081 * Pri 3 transmitted
21083 uint64_t tx_pfc_ena_frames_pri3;
21085 * Total number of PFC frames with PFC enabled bit for
21086 * Pri 4 transmitted
21088 uint64_t tx_pfc_ena_frames_pri4;
21090 * Total number of PFC frames with PFC enabled bit for
21091 * Pri 5 transmitted
21093 uint64_t tx_pfc_ena_frames_pri5;
21095 * Total number of PFC frames with PFC enabled bit for
21096 * Pri 6 transmitted
21098 uint64_t tx_pfc_ena_frames_pri6;
21100 * Total number of PFC frames with PFC enabled bit for
21101 * Pri 7 transmitted
21103 uint64_t tx_pfc_ena_frames_pri7;
21104 /* Total number of EEE LPI Events on TX */
21105 uint64_t tx_eee_lpi_events;
21106 /* EEE LPI Duration Counter on TX */
21107 uint64_t tx_eee_lpi_duration;
21109 * Total number of Link Level Flow Control (LLFC) messages
21112 uint64_t tx_llfc_logical_msgs;
21113 /* Total number of HCFC messages transmitted */
21114 uint64_t tx_hcfc_msgs;
21115 /* Total number of TX collisions */
21116 uint64_t tx_total_collisions;
21117 /* Total number of transmitted bytes */
21119 /* Total number of end-to-end HOL frames */
21120 uint64_t tx_xthol_frames;
21121 /* Total Tx Drops per Port reported by STATS block */
21122 uint64_t tx_stat_discard;
21123 /* Total Tx Error Drops per Port reported by STATS block */
21124 uint64_t tx_stat_error;
21127 /* Port Rx Statistics Format */
21128 /* rx_port_stats (size:4224b/528B) */
21129 struct rx_port_stats {
21130 /* Total Number of 64 Bytes frames received */
21131 uint64_t rx_64b_frames;
21132 /* Total Number of 65-127 Bytes frames received */
21133 uint64_t rx_65b_127b_frames;
21134 /* Total Number of 128-255 Bytes frames received */
21135 uint64_t rx_128b_255b_frames;
21136 /* Total Number of 256-511 Bytes frames received */
21137 uint64_t rx_256b_511b_frames;
21138 /* Total Number of 512-1023 Bytes frames received */
21139 uint64_t rx_512b_1023b_frames;
21140 /* Total Number of 1024-1518 Bytes frames received */
21141 uint64_t rx_1024b_1518b_frames;
21143 * Total Number of each good VLAN (exludes FCS errors)
21144 * frame received which is 1519 to 1522 bytes in length
21145 * inclusive (excluding framing bits but including FCS bytes).
21147 uint64_t rx_good_vlan_frames;
21148 /* Total Number of 1519-2047 Bytes frames received */
21149 uint64_t rx_1519b_2047b_frames;
21150 /* Total Number of 2048-4095 Bytes frames received */
21151 uint64_t rx_2048b_4095b_frames;
21152 /* Total Number of 4096-9216 Bytes frames received */
21153 uint64_t rx_4096b_9216b_frames;
21154 /* Total Number of 9217-16383 Bytes frames received */
21155 uint64_t rx_9217b_16383b_frames;
21156 /* Total number of frames received */
21157 uint64_t rx_total_frames;
21158 /* Total number of unicast frames received */
21159 uint64_t rx_ucast_frames;
21160 /* Total number of multicast frames received */
21161 uint64_t rx_mcast_frames;
21162 /* Total number of broadcast frames received */
21163 uint64_t rx_bcast_frames;
21164 /* Total number of received frames with FCS error */
21165 uint64_t rx_fcs_err_frames;
21166 /* Total number of control frames received */
21167 uint64_t rx_ctrl_frames;
21168 /* Total number of PAUSE frames received */
21169 uint64_t rx_pause_frames;
21170 /* Total number of PFC frames received */
21171 uint64_t rx_pfc_frames;
21173 * Total number of frames received with an unsupported
21176 uint64_t rx_unsupported_opcode_frames;
21178 * Total number of frames received with an unsupported
21179 * DA for pause and PFC
21181 uint64_t rx_unsupported_da_pausepfc_frames;
21182 /* Total number of frames received with an unsupported SA */
21183 uint64_t rx_wrong_sa_frames;
21184 /* Total number of received packets with alignment error */
21185 uint64_t rx_align_err_frames;
21186 /* Total number of received frames with out-of-range length */
21187 uint64_t rx_oor_len_frames;
21188 /* Total number of received frames with error termination */
21189 uint64_t rx_code_err_frames;
21191 * Total number of received frames with a false carrier is
21192 * detected during idle, as defined by RX_ER samples active
21193 * and RXD is 0xE. The event is reported along with the
21194 * statistics generated on the next received frame. Only
21195 * one false carrier condition can be detected and logged
21198 * Carrier event, valid for 10M/100M speed modes only.
21200 uint64_t rx_false_carrier_frames;
21201 /* Total number of over-sized frames received */
21202 uint64_t rx_ovrsz_frames;
21203 /* Total number of jabber packets received */
21204 uint64_t rx_jbr_frames;
21205 /* Total number of received frames with MTU error */
21206 uint64_t rx_mtu_err_frames;
21207 /* Total number of received frames with CRC match */
21208 uint64_t rx_match_crc_frames;
21209 /* Total number of frames received promiscuously */
21210 uint64_t rx_promiscuous_frames;
21212 * Total number of received frames with one or two VLAN
21215 uint64_t rx_tagged_frames;
21216 /* Total number of received frames with two VLAN tags */
21217 uint64_t rx_double_tagged_frames;
21218 /* Total number of truncated frames received */
21219 uint64_t rx_trunc_frames;
21220 /* Total number of good frames (without errors) received */
21221 uint64_t rx_good_frames;
21223 * Total number of received PFC frames with transition from
21224 * XON to XOFF on Pri 0
21226 uint64_t rx_pfc_xon2xoff_frames_pri0;
21228 * Total number of received PFC frames with transition from
21229 * XON to XOFF on Pri 1
21231 uint64_t rx_pfc_xon2xoff_frames_pri1;
21233 * Total number of received PFC frames with transition from
21234 * XON to XOFF on Pri 2
21236 uint64_t rx_pfc_xon2xoff_frames_pri2;
21238 * Total number of received PFC frames with transition from
21239 * XON to XOFF on Pri 3
21241 uint64_t rx_pfc_xon2xoff_frames_pri3;
21243 * Total number of received PFC frames with transition from
21244 * XON to XOFF on Pri 4
21246 uint64_t rx_pfc_xon2xoff_frames_pri4;
21248 * Total number of received PFC frames with transition from
21249 * XON to XOFF on Pri 5
21251 uint64_t rx_pfc_xon2xoff_frames_pri5;
21253 * Total number of received PFC frames with transition from
21254 * XON to XOFF on Pri 6
21256 uint64_t rx_pfc_xon2xoff_frames_pri6;
21258 * Total number of received PFC frames with transition from
21259 * XON to XOFF on Pri 7
21261 uint64_t rx_pfc_xon2xoff_frames_pri7;
21263 * Total number of received PFC frames with PFC enabled
21266 uint64_t rx_pfc_ena_frames_pri0;
21268 * Total number of received PFC frames with PFC enabled
21271 uint64_t rx_pfc_ena_frames_pri1;
21273 * Total number of received PFC frames with PFC enabled
21276 uint64_t rx_pfc_ena_frames_pri2;
21278 * Total number of received PFC frames with PFC enabled
21281 uint64_t rx_pfc_ena_frames_pri3;
21283 * Total number of received PFC frames with PFC enabled
21286 uint64_t rx_pfc_ena_frames_pri4;
21288 * Total number of received PFC frames with PFC enabled
21291 uint64_t rx_pfc_ena_frames_pri5;
21293 * Total number of received PFC frames with PFC enabled
21296 uint64_t rx_pfc_ena_frames_pri6;
21298 * Total number of received PFC frames with PFC enabled
21301 uint64_t rx_pfc_ena_frames_pri7;
21302 /* Total Number of frames received with SCH CRC error */
21303 uint64_t rx_sch_crc_err_frames;
21304 /* Total Number of under-sized frames received */
21305 uint64_t rx_undrsz_frames;
21306 /* Total Number of fragmented frames received */
21307 uint64_t rx_frag_frames;
21308 /* Total number of RX EEE LPI Events */
21309 uint64_t rx_eee_lpi_events;
21310 /* EEE LPI Duration Counter on RX */
21311 uint64_t rx_eee_lpi_duration;
21313 * Total number of physical type Link Level Flow Control
21314 * (LLFC) messages received
21316 uint64_t rx_llfc_physical_msgs;
21318 * Total number of logical type Link Level Flow Control
21319 * (LLFC) messages received
21321 uint64_t rx_llfc_logical_msgs;
21323 * Total number of logical type Link Level Flow Control
21324 * (LLFC) messages received with CRC error
21326 uint64_t rx_llfc_msgs_with_crc_err;
21327 /* Total number of HCFC messages received */
21328 uint64_t rx_hcfc_msgs;
21329 /* Total number of HCFC messages received with CRC error */
21330 uint64_t rx_hcfc_msgs_with_crc_err;
21331 /* Total number of received bytes */
21333 /* Total number of bytes received in runt frames */
21334 uint64_t rx_runt_bytes;
21335 /* Total number of runt frames received */
21336 uint64_t rx_runt_frames;
21337 /* Total Rx Discards per Port reported by STATS block */
21338 uint64_t rx_stat_discard;
21339 uint64_t rx_stat_err;
21342 /********************
21343 * hwrm_port_qstats *
21344 ********************/
21347 /* hwrm_port_qstats_input (size:320b/40B) */
21348 struct hwrm_port_qstats_input {
21349 /* The HWRM command request type. */
21352 * The completion ring to send the completion event on. This should
21353 * be the NQ ID returned from the `nq_alloc` HWRM command.
21355 uint16_t cmpl_ring;
21357 * The sequence ID is used by the driver for tracking multiple
21358 * commands. This ID is treated as opaque data by the firmware and
21359 * the value is returned in the `hwrm_resp_hdr` upon completion.
21363 * The target ID of the command:
21364 * * 0x0-0xFFF8 - The function ID
21365 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21366 * * 0xFFFD - Reserved for user-space HWRM interface
21369 uint16_t target_id;
21371 * A physical address pointer pointing to a host buffer that the
21372 * command's response data will be written. This can be either a host
21373 * physical address (HPA) or a guest physical address (GPA) and must
21374 * point to a physically contiguous block of memory.
21376 uint64_t resp_addr;
21377 /* Port ID of port that is being queried. */
21380 /* This value is not used to avoid backward compatibility issues. */
21381 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
21383 * This bit is set to 1 when request is for a counter mask,
21384 * representing the width of each of the stats counters, rather
21385 * than counters themselves.
21387 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
21388 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
21389 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
21390 uint8_t unused_0[5];
21392 * This is the host address where
21393 * Tx port statistics will be stored
21395 uint64_t tx_stat_host_addr;
21397 * This is the host address where
21398 * Rx port statistics will be stored
21400 uint64_t rx_stat_host_addr;
21403 /* hwrm_port_qstats_output (size:128b/16B) */
21404 struct hwrm_port_qstats_output {
21405 /* The specific error status for the command. */
21406 uint16_t error_code;
21407 /* The HWRM command request type. */
21409 /* The sequence ID from the original command. */
21411 /* The length of the response data in number of bytes. */
21413 /* The size of TX port statistics block in bytes. */
21414 uint16_t tx_stat_size;
21415 /* The size of RX port statistics block in bytes. */
21416 uint16_t rx_stat_size;
21417 uint8_t unused_0[3];
21419 * This field is used in Output records to indicate that the output
21420 * is completely written to RAM. This field should be read as '1'
21421 * to indicate that the output has been completely written.
21422 * When writing a command completion or response to an internal processor,
21423 * the order of writes has to be such that this field is written last.
21428 /* Port Tx Statistics extended Format */
21429 /* tx_port_stats_ext (size:2048b/256B) */
21430 struct tx_port_stats_ext {
21431 /* Total number of tx bytes count on cos queue 0 */
21432 uint64_t tx_bytes_cos0;
21433 /* Total number of tx bytes count on cos queue 1 */
21434 uint64_t tx_bytes_cos1;
21435 /* Total number of tx bytes count on cos queue 2 */
21436 uint64_t tx_bytes_cos2;
21437 /* Total number of tx bytes count on cos queue 3 */
21438 uint64_t tx_bytes_cos3;
21439 /* Total number of tx bytes count on cos queue 4 */
21440 uint64_t tx_bytes_cos4;
21441 /* Total number of tx bytes count on cos queue 5 */
21442 uint64_t tx_bytes_cos5;
21443 /* Total number of tx bytes count on cos queue 6 */
21444 uint64_t tx_bytes_cos6;
21445 /* Total number of tx bytes count on cos queue 7 */
21446 uint64_t tx_bytes_cos7;
21447 /* Total number of tx packets count on cos queue 0 */
21448 uint64_t tx_packets_cos0;
21449 /* Total number of tx packets count on cos queue 1 */
21450 uint64_t tx_packets_cos1;
21451 /* Total number of tx packets count on cos queue 2 */
21452 uint64_t tx_packets_cos2;
21453 /* Total number of tx packets count on cos queue 3 */
21454 uint64_t tx_packets_cos3;
21455 /* Total number of tx packets count on cos queue 4 */
21456 uint64_t tx_packets_cos4;
21457 /* Total number of tx packets count on cos queue 5 */
21458 uint64_t tx_packets_cos5;
21459 /* Total number of tx packets count on cos queue 6 */
21460 uint64_t tx_packets_cos6;
21461 /* Total number of tx packets count on cos queue 7 */
21462 uint64_t tx_packets_cos7;
21463 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
21464 uint64_t pfc_pri0_tx_duration_us;
21465 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
21466 uint64_t pfc_pri0_tx_transitions;
21467 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
21468 uint64_t pfc_pri1_tx_duration_us;
21469 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
21470 uint64_t pfc_pri1_tx_transitions;
21471 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
21472 uint64_t pfc_pri2_tx_duration_us;
21473 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
21474 uint64_t pfc_pri2_tx_transitions;
21475 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
21476 uint64_t pfc_pri3_tx_duration_us;
21477 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
21478 uint64_t pfc_pri3_tx_transitions;
21479 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
21480 uint64_t pfc_pri4_tx_duration_us;
21481 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
21482 uint64_t pfc_pri4_tx_transitions;
21483 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
21484 uint64_t pfc_pri5_tx_duration_us;
21485 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
21486 uint64_t pfc_pri5_tx_transitions;
21487 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
21488 uint64_t pfc_pri6_tx_duration_us;
21489 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
21490 uint64_t pfc_pri6_tx_transitions;
21491 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
21492 uint64_t pfc_pri7_tx_duration_us;
21493 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
21494 uint64_t pfc_pri7_tx_transitions;
21497 /* Port Rx Statistics extended Format */
21498 /* rx_port_stats_ext (size:3648b/456B) */
21499 struct rx_port_stats_ext {
21500 /* Number of times link state changed to down */
21501 uint64_t link_down_events;
21502 /* Number of times the idle rings with pause bit are found */
21503 uint64_t continuous_pause_events;
21504 /* Number of times the active rings pause bit resumed back */
21505 uint64_t resume_pause_events;
21506 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
21507 uint64_t continuous_roce_pause_events;
21508 /* Number of times, the ROCE cos queue PFC is enabled back */
21509 uint64_t resume_roce_pause_events;
21510 /* Total number of rx bytes count on cos queue 0 */
21511 uint64_t rx_bytes_cos0;
21512 /* Total number of rx bytes count on cos queue 1 */
21513 uint64_t rx_bytes_cos1;
21514 /* Total number of rx bytes count on cos queue 2 */
21515 uint64_t rx_bytes_cos2;
21516 /* Total number of rx bytes count on cos queue 3 */
21517 uint64_t rx_bytes_cos3;
21518 /* Total number of rx bytes count on cos queue 4 */
21519 uint64_t rx_bytes_cos4;
21520 /* Total number of rx bytes count on cos queue 5 */
21521 uint64_t rx_bytes_cos5;
21522 /* Total number of rx bytes count on cos queue 6 */
21523 uint64_t rx_bytes_cos6;
21524 /* Total number of rx bytes count on cos queue 7 */
21525 uint64_t rx_bytes_cos7;
21526 /* Total number of rx packets count on cos queue 0 */
21527 uint64_t rx_packets_cos0;
21528 /* Total number of rx packets count on cos queue 1 */
21529 uint64_t rx_packets_cos1;
21530 /* Total number of rx packets count on cos queue 2 */
21531 uint64_t rx_packets_cos2;
21532 /* Total number of rx packets count on cos queue 3 */
21533 uint64_t rx_packets_cos3;
21534 /* Total number of rx packets count on cos queue 4 */
21535 uint64_t rx_packets_cos4;
21536 /* Total number of rx packets count on cos queue 5 */
21537 uint64_t rx_packets_cos5;
21538 /* Total number of rx packets count on cos queue 6 */
21539 uint64_t rx_packets_cos6;
21540 /* Total number of rx packets count on cos queue 7 */
21541 uint64_t rx_packets_cos7;
21542 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
21543 uint64_t pfc_pri0_rx_duration_us;
21544 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
21545 uint64_t pfc_pri0_rx_transitions;
21546 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
21547 uint64_t pfc_pri1_rx_duration_us;
21548 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
21549 uint64_t pfc_pri1_rx_transitions;
21550 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
21551 uint64_t pfc_pri2_rx_duration_us;
21552 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
21553 uint64_t pfc_pri2_rx_transitions;
21554 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
21555 uint64_t pfc_pri3_rx_duration_us;
21556 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
21557 uint64_t pfc_pri3_rx_transitions;
21558 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
21559 uint64_t pfc_pri4_rx_duration_us;
21560 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
21561 uint64_t pfc_pri4_rx_transitions;
21562 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
21563 uint64_t pfc_pri5_rx_duration_us;
21564 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
21565 uint64_t pfc_pri5_rx_transitions;
21566 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
21567 uint64_t pfc_pri6_rx_duration_us;
21568 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
21569 uint64_t pfc_pri6_rx_transitions;
21570 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
21571 uint64_t pfc_pri7_rx_duration_us;
21572 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
21573 uint64_t pfc_pri7_rx_transitions;
21574 /* Total number of received bits */
21576 /* The number of events where the port receive buffer was over 85% full */
21577 uint64_t rx_buffer_passed_threshold;
21579 * The number of symbol errors that wasn't corrected by FEC correction
21582 uint64_t rx_pcs_symbol_err;
21583 /* The number of corrected bits on the port according to active FEC */
21584 uint64_t rx_corrected_bits;
21585 /* Total number of rx discard bytes count on cos queue 0 */
21586 uint64_t rx_discard_bytes_cos0;
21587 /* Total number of rx discard bytes count on cos queue 1 */
21588 uint64_t rx_discard_bytes_cos1;
21589 /* Total number of rx discard bytes count on cos queue 2 */
21590 uint64_t rx_discard_bytes_cos2;
21591 /* Total number of rx discard bytes count on cos queue 3 */
21592 uint64_t rx_discard_bytes_cos3;
21593 /* Total number of rx discard bytes count on cos queue 4 */
21594 uint64_t rx_discard_bytes_cos4;
21595 /* Total number of rx discard bytes count on cos queue 5 */
21596 uint64_t rx_discard_bytes_cos5;
21597 /* Total number of rx discard bytes count on cos queue 6 */
21598 uint64_t rx_discard_bytes_cos6;
21599 /* Total number of rx discard bytes count on cos queue 7 */
21600 uint64_t rx_discard_bytes_cos7;
21601 /* Total number of rx discard packets count on cos queue 0 */
21602 uint64_t rx_discard_packets_cos0;
21603 /* Total number of rx discard packets count on cos queue 1 */
21604 uint64_t rx_discard_packets_cos1;
21605 /* Total number of rx discard packets count on cos queue 2 */
21606 uint64_t rx_discard_packets_cos2;
21607 /* Total number of rx discard packets count on cos queue 3 */
21608 uint64_t rx_discard_packets_cos3;
21609 /* Total number of rx discard packets count on cos queue 4 */
21610 uint64_t rx_discard_packets_cos4;
21611 /* Total number of rx discard packets count on cos queue 5 */
21612 uint64_t rx_discard_packets_cos5;
21613 /* Total number of rx discard packets count on cos queue 6 */
21614 uint64_t rx_discard_packets_cos6;
21615 /* Total number of rx discard packets count on cos queue 7 */
21616 uint64_t rx_discard_packets_cos7;
21620 * Port Rx Statistics extended PFC WatchDog Format.
21621 * StormDetect and StormRevert event determination is based
21622 * on an integration period and a percentage threshold.
21623 * StormDetect event - when percentage of XOFF frames received
21624 * within an integration period exceeds the configured threshold.
21625 * StormRevert event - when percentage of XON frames received
21626 * within an integration period exceeds the configured threshold.
21627 * Actual number of XOFF/XON frames for the events to be triggered
21628 * depends on both configured integration period and sampling rate.
21629 * The statistics in this structure represent counts of specified
21630 * events from the moment the feature (PFC WatchDog) is enabled via
21631 * hwrm_queue_pfc_enable_cfg call.
21633 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
21634 struct rx_port_stats_ext_pfc_wd {
21636 * Total number of PFC WatchDog StormDetect events detected
21639 uint64_t rx_pfc_watchdog_storms_detected_pri0;
21641 * Total number of PFC WatchDog StormDetect events detected
21644 uint64_t rx_pfc_watchdog_storms_detected_pri1;
21646 * Total number of PFC WatchDog StormDetect events detected
21649 uint64_t rx_pfc_watchdog_storms_detected_pri2;
21651 * Total number of PFC WatchDog StormDetect events detected
21654 uint64_t rx_pfc_watchdog_storms_detected_pri3;
21656 * Total number of PFC WatchDog StormDetect events detected
21659 uint64_t rx_pfc_watchdog_storms_detected_pri4;
21661 * Total number of PFC WatchDog StormDetect events detected
21664 uint64_t rx_pfc_watchdog_storms_detected_pri5;
21666 * Total number of PFC WatchDog StormDetect events detected
21669 uint64_t rx_pfc_watchdog_storms_detected_pri6;
21671 * Total number of PFC WatchDog StormDetect events detected
21674 uint64_t rx_pfc_watchdog_storms_detected_pri7;
21676 * Total number of PFC WatchDog StormRevert events detected
21679 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
21681 * Total number of PFC WatchDog StormRevert events detected
21684 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
21686 * Total number of PFC WatchDog StormRevert events detected
21689 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
21691 * Total number of PFC WatchDog StormRevert events detected
21694 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
21696 * Total number of PFC WatchDog StormRevert events detected
21699 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
21701 * Total number of PFC WatchDog StormRevert events detected
21704 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
21706 * Total number of PFC WatchDog StormRevert events detected
21709 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
21711 * Total number of PFC WatchDog StormRevert events detected
21714 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
21716 * Total number of packets received during PFC watchdog storm
21719 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
21721 * Total number of packets received during PFC watchdog storm
21724 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
21726 * Total number of packets received during PFC watchdog storm
21729 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
21731 * Total number of packets received during PFC watchdog storm
21734 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
21736 * Total number of packets received during PFC watchdog storm
21739 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
21741 * Total number of packets received during PFC watchdog storm
21744 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
21746 * Total number of packets received during PFC watchdog storm
21749 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
21751 * Total number of packets received during PFC watchdog storm
21754 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
21756 * Total number of bytes received during PFC watchdog storm
21759 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
21761 * Total number of bytes received during PFC watchdog storm
21764 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
21766 * Total number of bytes received during PFC watchdog storm
21769 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
21771 * Total number of bytes received during PFC watchdog storm
21774 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
21776 * Total number of bytes received during PFC watchdog storm
21779 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
21781 * Total number of bytes received during PFC watchdog storm
21784 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
21786 * Total number of bytes received during PFC watchdog storm
21789 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
21791 * Total number of bytes received during PFC watchdog storm
21794 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
21796 * Total number of packets dropped on rx during PFC watchdog storm
21799 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
21801 * Total number of packets dropped on rx during PFC watchdog storm
21804 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
21806 * Total number of packets dropped on rx during PFC watchdog storm
21809 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
21811 * Total number of packets dropped on rx during PFC watchdog storm
21814 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
21816 * Total number of packets dropped on rx during PFC watchdog storm
21819 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
21821 * Total number of packets dropped on rx during PFC watchdog storm
21824 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
21826 * Total number of packets dropped on rx during PFC watchdog storm
21829 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
21831 * Total number of packets dropped on rx during PFC watchdog storm
21834 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
21836 * Total number of bytes dropped on rx during PFC watchdog storm
21839 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
21841 * Total number of bytes dropped on rx during PFC watchdog storm
21844 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
21846 * Total number of bytes dropped on rx during PFC watchdog storm
21849 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
21851 * Total number of bytes dropped on rx during PFC watchdog storm
21854 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
21856 * Total number of bytes dropped on rx during PFC watchdog storm
21859 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
21861 * Total number of bytes dropped on rx during PFC watchdog storm
21864 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
21866 * Total number of bytes dropped on rx during PFC watchdog storm
21869 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
21871 * Total number of bytes dropped on rx during PFC watchdog storm
21874 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
21876 * Number of packets received during last PFC watchdog storm
21879 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
21881 * Number of packets received during last PFC watchdog storm
21884 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
21886 * Number of packets received during last PFC watchdog storm
21889 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
21891 * Number of packets received during last PFC watchdog storm
21894 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
21896 * Number of packets received during last PFC watchdog storm
21899 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
21901 * Number of packets received during last PFC watchdog storm
21904 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
21906 * Number of packets received during last PFC watchdog storm
21909 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
21911 * Number of packets received during last PFC watchdog storm
21914 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
21916 * Number of bytes received during last PFC watchdog storm
21919 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
21921 * Number of bytes received during last PFC watchdog storm
21924 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
21926 * Number of bytes received during last PFC watchdog storm
21929 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
21931 * Number of bytes received during last PFC watchdog storm
21934 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
21936 * Number of bytes received during last PFC watchdog storm
21939 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
21941 * Number of bytes received during last PFC watchdog storm
21944 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
21946 * Number of bytes received during last PFC watchdog storm
21949 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
21951 * Number of bytes received during last PFC watchdog storm
21954 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
21956 * Number of packets dropped on rx during last PFC watchdog storm
21959 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
21961 * Number of packets dropped on rx during last PFC watchdog storm
21964 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
21966 * Number of packets dropped on rx during last PFC watchdog storm
21969 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
21971 * Number of packets dropped on rx during last PFC watchdog storm
21974 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
21976 * Number of packets dropped on rx during last PFC watchdog storm
21979 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
21981 * Number of packets dropped on rx during last PFC watchdog storm
21984 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
21986 * Number of packets dropped on rx during last PFC watchdog storm
21989 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
21991 * Number of packets dropped on rx during last PFC watchdog storm
21994 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
21996 * Total number of bytes dropped on rx during PFC watchdog storm
21999 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
22001 * Number of bytes dropped on rx during last PFC watchdog storm
22004 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
22006 * Number of bytes dropped on rx during last PFC watchdog storm
22009 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
22011 * Number of bytes dropped on rx during last PFC watchdog storm
22014 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
22016 * Number of bytes dropped on rx during last PFC watchdog storm
22019 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
22021 * Number of bytes dropped on rx during last PFC watchdog storm
22024 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
22026 * Number of bytes dropped on rx during last PFC watchdog storm
22029 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
22031 * Number of bytes dropped on rx during last PFC watchdog storm
22034 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
22037 /************************
22038 * hwrm_port_qstats_ext *
22039 ************************/
22042 /* hwrm_port_qstats_ext_input (size:320b/40B) */
22043 struct hwrm_port_qstats_ext_input {
22044 /* The HWRM command request type. */
22047 * The completion ring to send the completion event on. This should
22048 * be the NQ ID returned from the `nq_alloc` HWRM command.
22050 uint16_t cmpl_ring;
22052 * The sequence ID is used by the driver for tracking multiple
22053 * commands. This ID is treated as opaque data by the firmware and
22054 * the value is returned in the `hwrm_resp_hdr` upon completion.
22058 * The target ID of the command:
22059 * * 0x0-0xFFF8 - The function ID
22060 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22061 * * 0xFFFD - Reserved for user-space HWRM interface
22064 uint16_t target_id;
22066 * A physical address pointer pointing to a host buffer that the
22067 * command's response data will be written. This can be either a host
22068 * physical address (HPA) or a guest physical address (GPA) and must
22069 * point to a physically contiguous block of memory.
22071 uint64_t resp_addr;
22072 /* Port ID of port that is being queried. */
22075 * The size of TX port extended
22076 * statistics block in bytes.
22078 uint16_t tx_stat_size;
22080 * The size of RX port extended
22081 * statistics block in bytes
22083 uint16_t rx_stat_size;
22085 /* This value is not used to avoid backward compatibility issues. */
22086 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
22088 * This bit is set to 1 when request is for the counter mask,
22089 * representing width of each of the stats counters, rather than
22090 * counters themselves.
22092 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
22093 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
22094 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
22097 * This is the host address where
22098 * Tx port statistics will be stored
22100 uint64_t tx_stat_host_addr;
22102 * This is the host address where
22103 * Rx port statistics will be stored
22105 uint64_t rx_stat_host_addr;
22108 /* hwrm_port_qstats_ext_output (size:128b/16B) */
22109 struct hwrm_port_qstats_ext_output {
22110 /* The specific error status for the command. */
22111 uint16_t error_code;
22112 /* The HWRM command request type. */
22114 /* The sequence ID from the original command. */
22116 /* The length of the response data in number of bytes. */
22118 /* The size of TX port statistics block in bytes. */
22119 uint16_t tx_stat_size;
22120 /* The size of RX port statistics block in bytes. */
22121 uint16_t rx_stat_size;
22122 /* Total number of active cos queues available. */
22123 uint16_t total_active_cos_queues;
22126 * If set to 1, then this field indicates that clear
22127 * roce specific counters is supported.
22129 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
22132 * This field is used in Output records to indicate that the output
22133 * is completely written to RAM. This field should be read as '1'
22134 * to indicate that the output has been completely written.
22135 * When writing a command completion or response to an internal processor,
22136 * the order of writes has to be such that this field is written last.
22141 /*******************************
22142 * hwrm_port_qstats_ext_pfc_wd *
22143 *******************************/
22146 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
22147 struct hwrm_port_qstats_ext_pfc_wd_input {
22148 /* The HWRM command request type. */
22151 * The completion ring to send the completion event on. This should
22152 * be the NQ ID returned from the `nq_alloc` HWRM command.
22154 uint16_t cmpl_ring;
22156 * The sequence ID is used by the driver for tracking multiple
22157 * commands. This ID is treated as opaque data by the firmware and
22158 * the value is returned in the `hwrm_resp_hdr` upon completion.
22162 * The target ID of the command:
22163 * * 0x0-0xFFF8 - The function ID
22164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22165 * * 0xFFFD - Reserved for user-space HWRM interface
22168 uint16_t target_id;
22170 * A physical address pointer pointing to a host buffer that the
22171 * command's response data will be written. This can be either a host
22172 * physical address (HPA) or a guest physical address (GPA) and must
22173 * point to a physically contiguous block of memory.
22175 uint64_t resp_addr;
22176 /* Port ID of port that is being queried. */
22179 * The size of rx_port_stats_ext_pfc_wd
22182 uint16_t pfc_wd_stat_size;
22183 uint8_t unused_0[4];
22185 * This is the host address where
22186 * rx_port_stats_ext_pfc_wd will be stored
22188 uint64_t pfc_wd_stat_host_addr;
22191 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
22192 struct hwrm_port_qstats_ext_pfc_wd_output {
22193 /* The specific error status for the command. */
22194 uint16_t error_code;
22195 /* The HWRM command request type. */
22197 /* The sequence ID from the original command. */
22199 /* The length of the response data in number of bytes. */
22202 * The size of rx_port_stats_ext_pfc_wd
22203 * statistics block in bytes.
22205 uint16_t pfc_wd_stat_size;
22208 * This field is used in Output records to indicate that the output
22209 * is completely written to RAM. This field should be read as '1'
22210 * to indicate that the output has been completely written.
22211 * When writing a command completion or response to an internal processor,
22212 * the order of writes has to be such that this field is written last.
22215 uint8_t unused_0[4];
22218 /*************************
22219 * hwrm_port_lpbk_qstats *
22220 *************************/
22223 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
22224 struct hwrm_port_lpbk_qstats_input {
22225 /* The HWRM command request type. */
22228 * The completion ring to send the completion event on. This should
22229 * be the NQ ID returned from the `nq_alloc` HWRM command.
22231 uint16_t cmpl_ring;
22233 * The sequence ID is used by the driver for tracking multiple
22234 * commands. This ID is treated as opaque data by the firmware and
22235 * the value is returned in the `hwrm_resp_hdr` upon completion.
22239 * The target ID of the command:
22240 * * 0x0-0xFFF8 - The function ID
22241 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22242 * * 0xFFFD - Reserved for user-space HWRM interface
22245 uint16_t target_id;
22247 * A physical address pointer pointing to a host buffer that the
22248 * command's response data will be written. This can be either a host
22249 * physical address (HPA) or a guest physical address (GPA) and must
22250 * point to a physically contiguous block of memory.
22252 uint64_t resp_addr;
22255 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
22256 struct hwrm_port_lpbk_qstats_output {
22257 /* The specific error status for the command. */
22258 uint16_t error_code;
22259 /* The HWRM command request type. */
22261 /* The sequence ID from the original command. */
22263 /* The length of the response data in number of bytes. */
22265 /* Number of transmitted unicast frames */
22266 uint64_t lpbk_ucast_frames;
22267 /* Number of transmitted multicast frames */
22268 uint64_t lpbk_mcast_frames;
22269 /* Number of transmitted broadcast frames */
22270 uint64_t lpbk_bcast_frames;
22271 /* Number of transmitted bytes for unicast traffic */
22272 uint64_t lpbk_ucast_bytes;
22273 /* Number of transmitted bytes for multicast traffic */
22274 uint64_t lpbk_mcast_bytes;
22275 /* Number of transmitted bytes for broadcast traffic */
22276 uint64_t lpbk_bcast_bytes;
22277 /* Total Tx Drops for loopback traffic reported by STATS block */
22278 uint64_t tx_stat_discard;
22279 /* Total Tx Error Drops for loopback traffic reported by STATS block */
22280 uint64_t tx_stat_error;
22281 /* Total Rx Drops for loopback traffic reported by STATS block */
22282 uint64_t rx_stat_discard;
22283 /* Total Rx Error Drops for loopback traffic reported by STATS block */
22284 uint64_t rx_stat_error;
22285 uint8_t unused_0[7];
22287 * This field is used in Output records to indicate that the output
22288 * is completely written to RAM. This field should be read as '1'
22289 * to indicate that the output has been completely written.
22290 * When writing a command completion or response to an internal processor,
22291 * the order of writes has to be such that this field is written last.
22296 /************************
22297 * hwrm_port_ecn_qstats *
22298 ************************/
22301 /* hwrm_port_ecn_qstats_input (size:256b/32B) */
22302 struct hwrm_port_ecn_qstats_input {
22303 /* The HWRM command request type. */
22306 * The completion ring to send the completion event on. This should
22307 * be the NQ ID returned from the `nq_alloc` HWRM command.
22309 uint16_t cmpl_ring;
22311 * The sequence ID is used by the driver for tracking multiple
22312 * commands. This ID is treated as opaque data by the firmware and
22313 * the value is returned in the `hwrm_resp_hdr` upon completion.
22317 * The target ID of the command:
22318 * * 0x0-0xFFF8 - The function ID
22319 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22320 * * 0xFFFD - Reserved for user-space HWRM interface
22323 uint16_t target_id;
22325 * A physical address pointer pointing to a host buffer that the
22326 * command's response data will be written. This can be either a host
22327 * physical address (HPA) or a guest physical address (GPA) and must
22328 * point to a physically contiguous block of memory.
22330 uint64_t resp_addr;
22332 * Port ID of port that is being queried. Unused if NIC is in
22337 * Size of the DMA buffer the caller has allocated for the firmware to
22340 uint16_t ecn_stat_buf_size;
22342 /* This value is not used to avoid backward compatibility issues. */
22343 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
22345 * This bit is set to 1 when request is for a counter mask,
22346 * representing the width of each of the stats counters, rather
22347 * than counters themselves.
22349 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
22350 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \
22351 HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK
22352 uint8_t unused_0[3];
22354 * This is the host address where
22355 * ECN port statistics will be stored
22357 uint64_t ecn_stat_host_addr;
22360 /* hwrm_port_ecn_qstats_output (size:128b/16B) */
22361 struct hwrm_port_ecn_qstats_output {
22362 /* The specific error status for the command. */
22363 uint16_t error_code;
22364 /* The HWRM command request type. */
22366 /* The sequence ID from the original command. */
22368 /* The length of the response data in number of bytes. */
22370 /* Number of bytes of stats the firmware wrote to the DMA buffer. */
22371 uint16_t ecn_stat_buf_size;
22373 * Bitmask that indicates which CoS queues have ECN marking enabled.
22374 * Bit i corresponds to CoS queue i.
22377 uint8_t unused_0[4];
22379 * This field is used in Output records to indicate that the output
22380 * is completely written to RAM. This field should be read as '1'
22381 * to indicate that the output has been completely written.
22382 * When writing a command completion or response to an internal processor,
22383 * the order of writes has to be such that this field is written last.
22388 /* ECN mark statistics format */
22389 /* port_stats_ecn (size:512b/64B) */
22390 struct port_stats_ecn {
22392 * Number of packets marked in CoS queue 0.
22393 * Or, if the driver requested counter masks, a mask to indicate the size
22396 uint64_t mark_cnt_cos0;
22398 * Number of packets marked in CoS queue 1.
22399 * Or, if the driver requested counter masks, a mask to indicate the size
22402 uint64_t mark_cnt_cos1;
22404 * Number of packets marked in CoS queue 2.
22405 * Or, if the driver requested counter masks, a mask to indicate the size
22408 uint64_t mark_cnt_cos2;
22410 * Number of packets marked in CoS queue 3.
22411 * Or, if the driver requested counter masks, a mask to indicate the size
22414 uint64_t mark_cnt_cos3;
22416 * Number of packets marked in CoS queue 4.
22417 * Or, if the driver requested counter masks, a mask to indicate the size
22420 uint64_t mark_cnt_cos4;
22422 * Number of packets marked in CoS queue 5.
22423 * Or, if the driver requested counter masks, a mask to indicate the size
22426 uint64_t mark_cnt_cos5;
22428 * Number of packets marked in CoS queue 6.
22429 * Or, if the driver requested counter masks, a mask to indicate the size
22432 uint64_t mark_cnt_cos6;
22434 * Number of packets marked in CoS queue 7.
22435 * Or, if the driver requested counter masks, a mask to indicate the size
22438 uint64_t mark_cnt_cos7;
22441 /***********************
22442 * hwrm_port_clr_stats *
22443 ***********************/
22446 /* hwrm_port_clr_stats_input (size:192b/24B) */
22447 struct hwrm_port_clr_stats_input {
22448 /* The HWRM command request type. */
22451 * The completion ring to send the completion event on. This should
22452 * be the NQ ID returned from the `nq_alloc` HWRM command.
22454 uint16_t cmpl_ring;
22456 * The sequence ID is used by the driver for tracking multiple
22457 * commands. This ID is treated as opaque data by the firmware and
22458 * the value is returned in the `hwrm_resp_hdr` upon completion.
22462 * The target ID of the command:
22463 * * 0x0-0xFFF8 - The function ID
22464 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22465 * * 0xFFFD - Reserved for user-space HWRM interface
22468 uint16_t target_id;
22470 * A physical address pointer pointing to a host buffer that the
22471 * command's response data will be written. This can be either a host
22472 * physical address (HPA) or a guest physical address (GPA) and must
22473 * point to a physically contiguous block of memory.
22475 uint64_t resp_addr;
22476 /* Port ID of port that is being queried. */
22480 * If set to 1, then this field indicates clear the following RoCE
22481 * specific counters.
22482 * RoCE associated TX/RX cos counters
22483 * CNP associated TX/RX cos counters
22484 * RoCE/CNP specific TX/RX flow counters
22485 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
22486 * This flag is honored only when RoCE is enabled on that port.
22488 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
22489 uint8_t unused_0[5];
22492 /* hwrm_port_clr_stats_output (size:128b/16B) */
22493 struct hwrm_port_clr_stats_output {
22494 /* The specific error status for the command. */
22495 uint16_t error_code;
22496 /* The HWRM command request type. */
22498 /* The sequence ID from the original command. */
22500 /* The length of the response data in number of bytes. */
22502 uint8_t unused_0[7];
22504 * This field is used in Output records to indicate that the output
22505 * is completely written to RAM. This field should be read as '1'
22506 * to indicate that the output has been completely written.
22507 * When writing a command completion or response to an internal processor,
22508 * the order of writes has to be such that this field is written last.
22513 /***********************
22514 * hwrm_port_phy_qcaps *
22515 ***********************/
22518 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
22519 struct hwrm_port_phy_qcaps_input {
22520 /* The HWRM command request type. */
22523 * The completion ring to send the completion event on. This should
22524 * be the NQ ID returned from the `nq_alloc` HWRM command.
22526 uint16_t cmpl_ring;
22528 * The sequence ID is used by the driver for tracking multiple
22529 * commands. This ID is treated as opaque data by the firmware and
22530 * the value is returned in the `hwrm_resp_hdr` upon completion.
22534 * The target ID of the command:
22535 * * 0x0-0xFFF8 - The function ID
22536 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22537 * * 0xFFFD - Reserved for user-space HWRM interface
22540 uint16_t target_id;
22542 * A physical address pointer pointing to a host buffer that the
22543 * command's response data will be written. This can be either a host
22544 * physical address (HPA) or a guest physical address (GPA) and must
22545 * point to a physically contiguous block of memory.
22547 uint64_t resp_addr;
22548 /* Port ID of port that is being queried. */
22550 uint8_t unused_0[6];
22553 /* hwrm_port_phy_qcaps_output (size:256b/32B) */
22554 struct hwrm_port_phy_qcaps_output {
22555 /* The specific error status for the command. */
22556 uint16_t error_code;
22557 /* The HWRM command request type. */
22559 /* The sequence ID from the original command. */
22561 /* The length of the response data in number of bytes. */
22563 /* PHY capability flags */
22566 * If set to 1, then this field indicates that the
22567 * link is capable of supporting EEE.
22569 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
22572 * If set to 1, then this field indicates that the
22573 * PHY is capable of supporting external loopback.
22575 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
22578 * If set to 1, then this field indicates that the
22579 * PHY is capable of supporting loopback in autoneg mode.
22581 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
22584 * Indicates if the configuration of shared PHY settings is supported.
22585 * In cases where a physical port is shared by multiple functions
22586 * (e.g. NPAR, multihost, etc), the configuration of PHY
22587 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
22588 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
22590 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
22593 * If set to 1, it indicates that the port counters and extended
22594 * port counters will not reset when the firmware shuts down or
22595 * resets the PHY. These counters will only be reset during power
22596 * cycle or by calling HWRM_PORT_CLR_STATS.
22597 * If set to 0, the state of the counters is unspecified when
22598 * firmware shuts down or resets the PHY.
22600 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET \
22603 * If set to 1, then this field indicates that the
22604 * local loopback is not supported on this controller.
22606 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \
22609 * If set to 1, then this field indicates that the
22610 * PHY/Link down policy during PF shutdown is totally
22611 * controlled by the firmware. It can shutdown the link
22612 * even when there are active VFs associated with the PF.
22613 * Host PF driver can send HWRM_PHY_CFG command to bring
22614 * down the PHY even when the port is shared between VFs
22617 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \
22620 * If set to 1, this field indicates that the FCS may
22621 * be disabled for a given packet via the transmit
22622 * buffer descriptor.
22624 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \
22626 /* Number of front panel ports for this device. */
22628 /* Not supported or unknown */
22629 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
22630 /* single port device */
22631 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
22632 /* 2-port device */
22633 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
22634 /* 3-port device */
22635 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
22636 /* 4-port device */
22637 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
22638 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
22639 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
22641 * This is a bit mask to indicate what speeds are supported
22642 * as forced speeds on this link.
22643 * For each speed that can be forced on this link, the
22644 * corresponding mask bit shall be set to '1'.
22646 uint16_t supported_speeds_force_mode;
22647 /* 100Mb link speed (Half-duplex) */
22648 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
22650 /* 100Mb link speed (Full-duplex) */
22651 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
22653 /* 1Gb link speed (Half-duplex) */
22654 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
22656 /* 1Gb link speed (Full-duplex) */
22657 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
22659 /* 2Gb link speed */
22660 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
22662 /* 25Gb link speed */
22663 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
22665 /* 10Gb link speed */
22666 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
22668 /* 20Gb link speed */
22669 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
22671 /* 25Gb link speed */
22672 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
22674 /* 40Gb link speed */
22675 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
22677 /* 50Gb link speed */
22678 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
22680 /* 100Gb link speed */
22681 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
22683 /* 10Mb link speed (Half-duplex) */
22684 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
22686 /* 10Mb link speed (Full-duplex) */
22687 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
22690 * This is a bit mask to indicate what speeds are supported
22691 * for autonegotiation on this link.
22692 * For each speed that can be autonegotiated on this link, the
22693 * corresponding mask bit shall be set to '1'.
22695 uint16_t supported_speeds_auto_mode;
22696 /* 100Mb link speed (Half-duplex) */
22697 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
22699 /* 100Mb link speed (Full-duplex) */
22700 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
22702 /* 1Gb link speed (Half-duplex) */
22703 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
22705 /* 1Gb link speed (Full-duplex) */
22706 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
22708 /* 2Gb link speed */
22709 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
22711 /* 25Gb link speed */
22712 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
22714 /* 10Gb link speed */
22715 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
22717 /* 20Gb link speed */
22718 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
22720 /* 25Gb link speed */
22721 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
22723 /* 40Gb link speed */
22724 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
22726 /* 50Gb link speed */
22727 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
22729 /* 100Gb link speed */
22730 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
22732 /* 10Mb link speed (Half-duplex) */
22733 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
22735 /* 10Mb link speed (Full-duplex) */
22736 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
22739 * This is a bit mask to indicate what speeds are supported
22740 * for EEE on this link.
22741 * For each speed that can be autonegotiated when EEE is enabled
22742 * on this link, the corresponding mask bit shall be set to '1'.
22743 * This field is only valid when the eee_suppotred is set to '1'.
22745 uint16_t supported_speeds_eee_mode;
22747 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
22749 /* 100Mb link speed (Full-duplex) */
22750 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
22753 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
22755 /* 1Gb link speed (Full-duplex) */
22756 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
22759 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
22762 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
22764 /* 10Gb link speed */
22765 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
22767 uint32_t tx_lpi_timer_low;
22769 * The lowest value of TX LPI timer that can be set on this link
22770 * when EEE is enabled. This value is in microseconds.
22771 * This field is valid only when_eee_supported is set to '1'.
22773 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
22775 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
22777 * Reserved field. The HWRM shall set this field to 0.
22778 * An HWRM client shall ignore this field.
22780 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
22781 UINT32_C(0xff000000)
22782 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
22783 uint32_t valid_tx_lpi_timer_high;
22785 * The highest value of TX LPI timer that can be set on this link
22786 * when EEE is enabled. This value is in microseconds.
22787 * This field is valid only when_eee_supported is set to '1'.
22789 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
22791 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
22793 * Reserved field. The HWRM shall set this field to 0.
22794 * An HWRM client shall ignore this field.
22796 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK \
22797 UINT32_C(0xff000000)
22798 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_SFT 24
22800 * This field is used to advertise which PAM4 speeds are supported
22803 uint16_t supported_pam4_speeds_auto_mode;
22804 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G \
22806 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G \
22808 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G \
22811 * This field is used to advertise which PAM4 speeds are supported
22814 uint16_t supported_pam4_speeds_force_mode;
22815 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G \
22817 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G \
22819 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G \
22821 uint8_t unused_0[3];
22823 * This field is used in Output records to indicate that the output
22824 * is completely written to RAM. This field should be read as '1'
22825 * to indicate that the output has been completely written.
22826 * When writing a command completion or response to an internal processor,
22827 * the order of writes has to be such that this field is written last.
22832 /****************************
22833 * hwrm_port_phy_mdio_write *
22834 ****************************/
22837 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
22838 struct hwrm_port_phy_mdio_write_input {
22839 /* The HWRM command request type. */
22842 * The completion ring to send the completion event on. This should
22843 * be the NQ ID returned from the `nq_alloc` HWRM command.
22845 uint16_t cmpl_ring;
22847 * The sequence ID is used by the driver for tracking multiple
22848 * commands. This ID is treated as opaque data by the firmware and
22849 * the value is returned in the `hwrm_resp_hdr` upon completion.
22853 * The target ID of the command:
22854 * * 0x0-0xFFF8 - The function ID
22855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22856 * * 0xFFFD - Reserved for user-space HWRM interface
22859 uint16_t target_id;
22861 * A physical address pointer pointing to a host buffer that the
22862 * command's response data will be written. This can be either a host
22863 * physical address (HPA) or a guest physical address (GPA) and must
22864 * point to a physically contiguous block of memory.
22866 uint64_t resp_addr;
22867 /* Reserved for future use. */
22868 uint32_t unused_0[2];
22869 /* Port ID of port. */
22871 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
22873 /* 8-bit device address. */
22875 /* 16-bit register address. */
22877 /* 16-bit register data. */
22880 * When this bit is set to 1 a Clause 45 mdio access is done.
22881 * when this bit is set to 0 a Clause 22 mdio access is done.
22885 uint8_t unused_1[7];
22888 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
22889 struct hwrm_port_phy_mdio_write_output {
22890 /* The specific error status for the command. */
22891 uint16_t error_code;
22892 /* The HWRM command request type. */
22894 /* The sequence ID from the original command. */
22896 /* The length of the response data in number of bytes. */
22898 uint8_t unused_0[7];
22900 * This field is used in Output records to indicate that the output
22901 * is completely written to RAM. This field should be read as '1'
22902 * to indicate that the output has been completely written.
22903 * When writing a command completion or response to an internal processor,
22904 * the order of writes has to be such that this field is written last.
22909 /***************************
22910 * hwrm_port_phy_mdio_read *
22911 ***************************/
22914 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
22915 struct hwrm_port_phy_mdio_read_input {
22916 /* The HWRM command request type. */
22919 * The completion ring to send the completion event on. This should
22920 * be the NQ ID returned from the `nq_alloc` HWRM command.
22922 uint16_t cmpl_ring;
22924 * The sequence ID is used by the driver for tracking multiple
22925 * commands. This ID is treated as opaque data by the firmware and
22926 * the value is returned in the `hwrm_resp_hdr` upon completion.
22930 * The target ID of the command:
22931 * * 0x0-0xFFF8 - The function ID
22932 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22933 * * 0xFFFD - Reserved for user-space HWRM interface
22936 uint16_t target_id;
22938 * A physical address pointer pointing to a host buffer that the
22939 * command's response data will be written. This can be either a host
22940 * physical address (HPA) or a guest physical address (GPA) and must
22941 * point to a physically contiguous block of memory.
22943 uint64_t resp_addr;
22944 /* Reserved for future use. */
22945 uint32_t unused_0[2];
22946 /* Port ID of port. */
22948 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
22950 /* 8-bit device address. */
22952 /* 16-bit register address. */
22955 * When this bit is set to 1 a Clause 45 mdio access is done.
22956 * when this bit is set to 0 a Clause 22 mdio access is done.
22963 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
22964 struct hwrm_port_phy_mdio_read_output {
22965 /* The specific error status for the command. */
22966 uint16_t error_code;
22967 /* The HWRM command request type. */
22969 /* The sequence ID from the original command. */
22971 /* The length of the response data in number of bytes. */
22973 /* 16-bit register data. */
22975 uint8_t unused_0[5];
22977 * This field is used in Output records to indicate that the output
22978 * is completely written to RAM. This field should be read as '1'
22979 * to indicate that the output has been completely written.
22980 * When writing a command completion or response to an internal processor,
22981 * the order of writes has to be such that this field is written last.
22986 /*********************
22987 * hwrm_port_led_cfg *
22988 *********************/
22991 /* hwrm_port_led_cfg_input (size:512b/64B) */
22992 struct hwrm_port_led_cfg_input {
22993 /* The HWRM command request type. */
22996 * The completion ring to send the completion event on. This should
22997 * be the NQ ID returned from the `nq_alloc` HWRM command.
22999 uint16_t cmpl_ring;
23001 * The sequence ID is used by the driver for tracking multiple
23002 * commands. This ID is treated as opaque data by the firmware and
23003 * the value is returned in the `hwrm_resp_hdr` upon completion.
23007 * The target ID of the command:
23008 * * 0x0-0xFFF8 - The function ID
23009 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23010 * * 0xFFFD - Reserved for user-space HWRM interface
23013 uint16_t target_id;
23015 * A physical address pointer pointing to a host buffer that the
23016 * command's response data will be written. This can be either a host
23017 * physical address (HPA) or a guest physical address (GPA) and must
23018 * point to a physically contiguous block of memory.
23020 uint64_t resp_addr;
23023 * This bit must be '1' for the led0_id field to be
23026 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
23029 * This bit must be '1' for the led0_state field to be
23032 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
23035 * This bit must be '1' for the led0_color field to be
23038 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
23041 * This bit must be '1' for the led0_blink_on field to be
23044 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
23047 * This bit must be '1' for the led0_blink_off field to be
23050 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
23053 * This bit must be '1' for the led0_group_id field to be
23056 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
23059 * This bit must be '1' for the led1_id field to be
23062 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
23065 * This bit must be '1' for the led1_state field to be
23068 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
23071 * This bit must be '1' for the led1_color field to be
23074 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
23077 * This bit must be '1' for the led1_blink_on field to be
23080 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
23083 * This bit must be '1' for the led1_blink_off field to be
23086 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
23089 * This bit must be '1' for the led1_group_id field to be
23092 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
23095 * This bit must be '1' for the led2_id field to be
23098 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
23101 * This bit must be '1' for the led2_state field to be
23104 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
23107 * This bit must be '1' for the led2_color field to be
23110 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
23113 * This bit must be '1' for the led2_blink_on field to be
23116 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
23119 * This bit must be '1' for the led2_blink_off field to be
23122 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
23125 * This bit must be '1' for the led2_group_id field to be
23128 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
23131 * This bit must be '1' for the led3_id field to be
23134 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
23137 * This bit must be '1' for the led3_state field to be
23140 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
23143 * This bit must be '1' for the led3_color field to be
23146 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
23149 * This bit must be '1' for the led3_blink_on field to be
23152 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
23155 * This bit must be '1' for the led3_blink_off field to be
23158 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
23161 * This bit must be '1' for the led3_group_id field to be
23164 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
23166 /* Port ID of port whose LEDs are configured. */
23169 * The number of LEDs that are being configured.
23170 * Up to 4 LEDs can be configured with this command.
23173 /* Reserved field. */
23175 /* An identifier for the LED #0. */
23177 /* The requested state of the LED #0. */
23178 uint8_t led0_state;
23179 /* Default state of the LED */
23180 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
23182 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
23184 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
23186 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
23187 /* Blink Alternately */
23188 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
23189 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
23190 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
23191 /* The requested color of LED #0. */
23192 uint8_t led0_color;
23194 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
23196 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
23198 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
23199 /* Green or Amber */
23200 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
23201 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
23202 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
23205 * If the LED #0 state is "blink" or "blinkalt", then
23206 * this field represents the requested time in milliseconds
23207 * to keep LED on between cycles.
23209 uint16_t led0_blink_on;
23211 * If the LED #0 state is "blink" or "blinkalt", then
23212 * this field represents the requested time in milliseconds
23213 * to keep LED off between cycles.
23215 uint16_t led0_blink_off;
23217 * An identifier for the group of LEDs that LED #0 belongs
23219 * If set to 0, then the LED #0 shall not be grouped and
23220 * shall be treated as an individual resource.
23221 * For all other non-zero values of this field, LED #0 shall
23222 * be grouped together with the LEDs with the same group ID
23225 uint8_t led0_group_id;
23226 /* Reserved field. */
23228 /* An identifier for the LED #1. */
23230 /* The requested state of the LED #1. */
23231 uint8_t led1_state;
23232 /* Default state of the LED */
23233 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
23235 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
23237 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
23239 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
23240 /* Blink Alternately */
23241 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
23242 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
23243 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
23244 /* The requested color of LED #1. */
23245 uint8_t led1_color;
23247 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
23249 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
23251 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
23252 /* Green or Amber */
23253 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
23254 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
23255 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
23258 * If the LED #1 state is "blink" or "blinkalt", then
23259 * this field represents the requested time in milliseconds
23260 * to keep LED on between cycles.
23262 uint16_t led1_blink_on;
23264 * If the LED #1 state is "blink" or "blinkalt", then
23265 * this field represents the requested time in milliseconds
23266 * to keep LED off between cycles.
23268 uint16_t led1_blink_off;
23270 * An identifier for the group of LEDs that LED #1 belongs
23272 * If set to 0, then the LED #1 shall not be grouped and
23273 * shall be treated as an individual resource.
23274 * For all other non-zero values of this field, LED #1 shall
23275 * be grouped together with the LEDs with the same group ID
23278 uint8_t led1_group_id;
23279 /* Reserved field. */
23281 /* An identifier for the LED #2. */
23283 /* The requested state of the LED #2. */
23284 uint8_t led2_state;
23285 /* Default state of the LED */
23286 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
23288 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
23290 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
23292 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
23293 /* Blink Alternately */
23294 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
23295 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
23296 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
23297 /* The requested color of LED #2. */
23298 uint8_t led2_color;
23300 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
23302 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
23304 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
23305 /* Green or Amber */
23306 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
23307 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
23308 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
23311 * If the LED #2 state is "blink" or "blinkalt", then
23312 * this field represents the requested time in milliseconds
23313 * to keep LED on between cycles.
23315 uint16_t led2_blink_on;
23317 * If the LED #2 state is "blink" or "blinkalt", then
23318 * this field represents the requested time in milliseconds
23319 * to keep LED off between cycles.
23321 uint16_t led2_blink_off;
23323 * An identifier for the group of LEDs that LED #2 belongs
23325 * If set to 0, then the LED #2 shall not be grouped and
23326 * shall be treated as an individual resource.
23327 * For all other non-zero values of this field, LED #2 shall
23328 * be grouped together with the LEDs with the same group ID
23331 uint8_t led2_group_id;
23332 /* Reserved field. */
23334 /* An identifier for the LED #3. */
23336 /* The requested state of the LED #3. */
23337 uint8_t led3_state;
23338 /* Default state of the LED */
23339 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
23341 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
23343 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
23345 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
23346 /* Blink Alternately */
23347 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
23348 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
23349 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
23350 /* The requested color of LED #3. */
23351 uint8_t led3_color;
23353 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
23355 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
23357 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
23358 /* Green or Amber */
23359 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
23360 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
23361 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
23364 * If the LED #3 state is "blink" or "blinkalt", then
23365 * this field represents the requested time in milliseconds
23366 * to keep LED on between cycles.
23368 uint16_t led3_blink_on;
23370 * If the LED #3 state is "blink" or "blinkalt", then
23371 * this field represents the requested time in milliseconds
23372 * to keep LED off between cycles.
23374 uint16_t led3_blink_off;
23376 * An identifier for the group of LEDs that LED #3 belongs
23378 * If set to 0, then the LED #3 shall not be grouped and
23379 * shall be treated as an individual resource.
23380 * For all other non-zero values of this field, LED #3 shall
23381 * be grouped together with the LEDs with the same group ID
23384 uint8_t led3_group_id;
23385 /* Reserved field. */
23389 /* hwrm_port_led_cfg_output (size:128b/16B) */
23390 struct hwrm_port_led_cfg_output {
23391 /* The specific error status for the command. */
23392 uint16_t error_code;
23393 /* The HWRM command request type. */
23395 /* The sequence ID from the original command. */
23397 /* The length of the response data in number of bytes. */
23399 uint8_t unused_0[7];
23401 * This field is used in Output records to indicate that the output
23402 * is completely written to RAM. This field should be read as '1'
23403 * to indicate that the output has been completely written.
23404 * When writing a command completion or response to an internal processor,
23405 * the order of writes has to be such that this field is written last.
23410 /**********************
23411 * hwrm_port_led_qcfg *
23412 **********************/
23415 /* hwrm_port_led_qcfg_input (size:192b/24B) */
23416 struct hwrm_port_led_qcfg_input {
23417 /* The HWRM command request type. */
23420 * The completion ring to send the completion event on. This should
23421 * be the NQ ID returned from the `nq_alloc` HWRM command.
23423 uint16_t cmpl_ring;
23425 * The sequence ID is used by the driver for tracking multiple
23426 * commands. This ID is treated as opaque data by the firmware and
23427 * the value is returned in the `hwrm_resp_hdr` upon completion.
23431 * The target ID of the command:
23432 * * 0x0-0xFFF8 - The function ID
23433 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23434 * * 0xFFFD - Reserved for user-space HWRM interface
23437 uint16_t target_id;
23439 * A physical address pointer pointing to a host buffer that the
23440 * command's response data will be written. This can be either a host
23441 * physical address (HPA) or a guest physical address (GPA) and must
23442 * point to a physically contiguous block of memory.
23444 uint64_t resp_addr;
23445 /* Port ID of port whose LED configuration is being queried. */
23447 uint8_t unused_0[6];
23450 /* hwrm_port_led_qcfg_output (size:448b/56B) */
23451 struct hwrm_port_led_qcfg_output {
23452 /* The specific error status for the command. */
23453 uint16_t error_code;
23454 /* The HWRM command request type. */
23456 /* The sequence ID from the original command. */
23458 /* The length of the response data in number of bytes. */
23461 * The number of LEDs that are configured on this port.
23462 * Up to 4 LEDs can be returned in the response.
23465 /* An identifier for the LED #0. */
23467 /* The type of LED #0. */
23470 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
23472 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
23474 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
23475 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
23476 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
23477 /* The current state of the LED #0. */
23478 uint8_t led0_state;
23479 /* Default state of the LED */
23480 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
23482 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
23484 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
23486 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
23487 /* Blink Alternately */
23488 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
23489 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
23490 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
23491 /* The color of LED #0. */
23492 uint8_t led0_color;
23494 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
23496 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
23498 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
23499 /* Green or Amber */
23500 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
23501 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
23502 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
23505 * If the LED #0 state is "blink" or "blinkalt", then
23506 * this field represents the requested time in milliseconds
23507 * to keep LED on between cycles.
23509 uint16_t led0_blink_on;
23511 * If the LED #0 state is "blink" or "blinkalt", then
23512 * this field represents the requested time in milliseconds
23513 * to keep LED off between cycles.
23515 uint16_t led0_blink_off;
23517 * An identifier for the group of LEDs that LED #0 belongs
23519 * If set to 0, then the LED #0 is not grouped.
23520 * For all other non-zero values of this field, LED #0 is
23521 * grouped together with the LEDs with the same group ID
23524 uint8_t led0_group_id;
23525 /* An identifier for the LED #1. */
23527 /* The type of LED #1. */
23530 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
23532 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
23534 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
23535 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
23536 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
23537 /* The current state of the LED #1. */
23538 uint8_t led1_state;
23539 /* Default state of the LED */
23540 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
23542 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
23544 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
23546 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
23547 /* Blink Alternately */
23548 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
23549 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
23550 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
23551 /* The color of LED #1. */
23552 uint8_t led1_color;
23554 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
23556 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
23558 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
23559 /* Green or Amber */
23560 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
23561 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
23562 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
23565 * If the LED #1 state is "blink" or "blinkalt", then
23566 * this field represents the requested time in milliseconds
23567 * to keep LED on between cycles.
23569 uint16_t led1_blink_on;
23571 * If the LED #1 state is "blink" or "blinkalt", then
23572 * this field represents the requested time in milliseconds
23573 * to keep LED off between cycles.
23575 uint16_t led1_blink_off;
23577 * An identifier for the group of LEDs that LED #1 belongs
23579 * If set to 0, then the LED #1 is not grouped.
23580 * For all other non-zero values of this field, LED #1 is
23581 * grouped together with the LEDs with the same group ID
23584 uint8_t led1_group_id;
23585 /* An identifier for the LED #2. */
23587 /* The type of LED #2. */
23590 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
23592 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
23594 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
23595 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
23596 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
23597 /* The current state of the LED #2. */
23598 uint8_t led2_state;
23599 /* Default state of the LED */
23600 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
23602 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
23604 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
23606 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
23607 /* Blink Alternately */
23608 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
23609 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
23610 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
23611 /* The color of LED #2. */
23612 uint8_t led2_color;
23614 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
23616 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
23618 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
23619 /* Green or Amber */
23620 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
23621 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
23622 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
23625 * If the LED #2 state is "blink" or "blinkalt", then
23626 * this field represents the requested time in milliseconds
23627 * to keep LED on between cycles.
23629 uint16_t led2_blink_on;
23631 * If the LED #2 state is "blink" or "blinkalt", then
23632 * this field represents the requested time in milliseconds
23633 * to keep LED off between cycles.
23635 uint16_t led2_blink_off;
23637 * An identifier for the group of LEDs that LED #2 belongs
23639 * If set to 0, then the LED #2 is not grouped.
23640 * For all other non-zero values of this field, LED #2 is
23641 * grouped together with the LEDs with the same group ID
23644 uint8_t led2_group_id;
23645 /* An identifier for the LED #3. */
23647 /* The type of LED #3. */
23650 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
23652 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
23654 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
23655 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
23656 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
23657 /* The current state of the LED #3. */
23658 uint8_t led3_state;
23659 /* Default state of the LED */
23660 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
23662 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
23664 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
23666 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
23667 /* Blink Alternately */
23668 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
23669 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
23670 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
23671 /* The color of LED #3. */
23672 uint8_t led3_color;
23674 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
23676 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
23678 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
23679 /* Green or Amber */
23680 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
23681 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
23682 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
23685 * If the LED #3 state is "blink" or "blinkalt", then
23686 * this field represents the requested time in milliseconds
23687 * to keep LED on between cycles.
23689 uint16_t led3_blink_on;
23691 * If the LED #3 state is "blink" or "blinkalt", then
23692 * this field represents the requested time in milliseconds
23693 * to keep LED off between cycles.
23695 uint16_t led3_blink_off;
23697 * An identifier for the group of LEDs that LED #3 belongs
23699 * If set to 0, then the LED #3 is not grouped.
23700 * For all other non-zero values of this field, LED #3 is
23701 * grouped together with the LEDs with the same group ID
23704 uint8_t led3_group_id;
23705 uint8_t unused_4[6];
23707 * This field is used in Output records to indicate that the output
23708 * is completely written to RAM. This field should be read as '1'
23709 * to indicate that the output has been completely written.
23710 * When writing a command completion or response to an internal processor,
23711 * the order of writes has to be such that this field is written last.
23716 /***********************
23717 * hwrm_port_led_qcaps *
23718 ***********************/
23721 /* hwrm_port_led_qcaps_input (size:192b/24B) */
23722 struct hwrm_port_led_qcaps_input {
23723 /* The HWRM command request type. */
23726 * The completion ring to send the completion event on. This should
23727 * be the NQ ID returned from the `nq_alloc` HWRM command.
23729 uint16_t cmpl_ring;
23731 * The sequence ID is used by the driver for tracking multiple
23732 * commands. This ID is treated as opaque data by the firmware and
23733 * the value is returned in the `hwrm_resp_hdr` upon completion.
23737 * The target ID of the command:
23738 * * 0x0-0xFFF8 - The function ID
23739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23740 * * 0xFFFD - Reserved for user-space HWRM interface
23743 uint16_t target_id;
23745 * A physical address pointer pointing to a host buffer that the
23746 * command's response data will be written. This can be either a host
23747 * physical address (HPA) or a guest physical address (GPA) and must
23748 * point to a physically contiguous block of memory.
23750 uint64_t resp_addr;
23751 /* Port ID of port whose LED configuration is being queried. */
23753 uint8_t unused_0[6];
23756 /* hwrm_port_led_qcaps_output (size:384b/48B) */
23757 struct hwrm_port_led_qcaps_output {
23758 /* The specific error status for the command. */
23759 uint16_t error_code;
23760 /* The HWRM command request type. */
23762 /* The sequence ID from the original command. */
23764 /* The length of the response data in number of bytes. */
23767 * The number of LEDs that are configured on this port.
23768 * Up to 4 LEDs can be returned in the response.
23771 /* Reserved for future use. */
23773 /* An identifier for the LED #0. */
23775 /* The type of LED #0. */
23778 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
23780 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
23782 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
23783 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
23784 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
23786 * An identifier for the group of LEDs that LED #0 belongs
23788 * If set to 0, then the LED #0 cannot be grouped.
23789 * For all other non-zero values of this field, LED #0 is
23790 * grouped together with the LEDs with the same group ID
23793 uint8_t led0_group_id;
23795 /* The states supported by LED #0. */
23796 uint16_t led0_state_caps;
23798 * If set to 1, this LED is enabled.
23799 * If set to 0, this LED is disabled.
23801 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
23804 * If set to 1, off state is supported on this LED.
23805 * If set to 0, off state is not supported on this LED.
23807 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
23810 * If set to 1, on state is supported on this LED.
23811 * If set to 0, on state is not supported on this LED.
23813 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
23816 * If set to 1, blink state is supported on this LED.
23817 * If set to 0, blink state is not supported on this LED.
23819 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
23822 * If set to 1, blink_alt state is supported on this LED.
23823 * If set to 0, blink_alt state is not supported on this LED.
23825 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
23827 /* The colors supported by LED #0. */
23828 uint16_t led0_color_caps;
23830 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
23833 * If set to 1, Amber color is supported on this LED.
23834 * If set to 0, Amber color is not supported on this LED.
23836 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
23839 * If set to 1, Green color is supported on this LED.
23840 * If set to 0, Green color is not supported on this LED.
23842 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
23844 /* An identifier for the LED #1. */
23846 /* The type of LED #1. */
23849 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
23851 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
23853 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
23854 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
23855 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
23857 * An identifier for the group of LEDs that LED #1 belongs
23859 * If set to 0, then the LED #0 cannot be grouped.
23860 * For all other non-zero values of this field, LED #0 is
23861 * grouped together with the LEDs with the same group ID
23864 uint8_t led1_group_id;
23866 /* The states supported by LED #1. */
23867 uint16_t led1_state_caps;
23869 * If set to 1, this LED is enabled.
23870 * If set to 0, this LED is disabled.
23872 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
23875 * If set to 1, off state is supported on this LED.
23876 * If set to 0, off state is not supported on this LED.
23878 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
23881 * If set to 1, on state is supported on this LED.
23882 * If set to 0, on state is not supported on this LED.
23884 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
23887 * If set to 1, blink state is supported on this LED.
23888 * If set to 0, blink state is not supported on this LED.
23890 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
23893 * If set to 1, blink_alt state is supported on this LED.
23894 * If set to 0, blink_alt state is not supported on this LED.
23896 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
23898 /* The colors supported by LED #1. */
23899 uint16_t led1_color_caps;
23901 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
23904 * If set to 1, Amber color is supported on this LED.
23905 * If set to 0, Amber color is not supported on this LED.
23907 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
23910 * If set to 1, Green color is supported on this LED.
23911 * If set to 0, Green color is not supported on this LED.
23913 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
23915 /* An identifier for the LED #2. */
23917 /* The type of LED #2. */
23920 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
23922 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
23924 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
23925 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
23926 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
23928 * An identifier for the group of LEDs that LED #0 belongs
23930 * If set to 0, then the LED #0 cannot be grouped.
23931 * For all other non-zero values of this field, LED #0 is
23932 * grouped together with the LEDs with the same group ID
23935 uint8_t led2_group_id;
23937 /* The states supported by LED #2. */
23938 uint16_t led2_state_caps;
23940 * If set to 1, this LED is enabled.
23941 * If set to 0, this LED is disabled.
23943 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
23946 * If set to 1, off state is supported on this LED.
23947 * If set to 0, off state is not supported on this LED.
23949 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
23952 * If set to 1, on state is supported on this LED.
23953 * If set to 0, on state is not supported on this LED.
23955 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
23958 * If set to 1, blink state is supported on this LED.
23959 * If set to 0, blink state is not supported on this LED.
23961 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
23964 * If set to 1, blink_alt state is supported on this LED.
23965 * If set to 0, blink_alt state is not supported on this LED.
23967 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
23969 /* The colors supported by LED #2. */
23970 uint16_t led2_color_caps;
23972 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
23975 * If set to 1, Amber color is supported on this LED.
23976 * If set to 0, Amber color is not supported on this LED.
23978 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
23981 * If set to 1, Green color is supported on this LED.
23982 * If set to 0, Green color is not supported on this LED.
23984 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
23986 /* An identifier for the LED #3. */
23988 /* The type of LED #3. */
23991 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
23993 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
23995 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
23996 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
23997 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
23999 * An identifier for the group of LEDs that LED #3 belongs
24001 * If set to 0, then the LED #0 cannot be grouped.
24002 * For all other non-zero values of this field, LED #0 is
24003 * grouped together with the LEDs with the same group ID
24006 uint8_t led3_group_id;
24008 /* The states supported by LED #3. */
24009 uint16_t led3_state_caps;
24011 * If set to 1, this LED is enabled.
24012 * If set to 0, this LED is disabled.
24014 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
24017 * If set to 1, off state is supported on this LED.
24018 * If set to 0, off state is not supported on this LED.
24020 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
24023 * If set to 1, on state is supported on this LED.
24024 * If set to 0, on state is not supported on this LED.
24026 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
24029 * If set to 1, blink state is supported on this LED.
24030 * If set to 0, blink state is not supported on this LED.
24032 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
24035 * If set to 1, blink_alt state is supported on this LED.
24036 * If set to 0, blink_alt state is not supported on this LED.
24038 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
24040 /* The colors supported by LED #3. */
24041 uint16_t led3_color_caps;
24043 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
24046 * If set to 1, Amber color is supported on this LED.
24047 * If set to 0, Amber color is not supported on this LED.
24049 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
24052 * If set to 1, Green color is supported on this LED.
24053 * If set to 0, Green color is not supported on this LED.
24055 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
24057 uint8_t unused_4[3];
24059 * This field is used in Output records to indicate that the output
24060 * is completely written to RAM. This field should be read as '1'
24061 * to indicate that the output has been completely written.
24062 * When writing a command completion or response to an internal processor,
24063 * the order of writes has to be such that this field is written last.
24068 /***********************
24069 * hwrm_port_prbs_test *
24070 ***********************/
24073 /* hwrm_port_prbs_test_input (size:384b/48B) */
24074 struct hwrm_port_prbs_test_input {
24075 /* The HWRM command request type. */
24078 * The completion ring to send the completion event on. This should
24079 * be the NQ ID returned from the `nq_alloc` HWRM command.
24081 uint16_t cmpl_ring;
24083 * The sequence ID is used by the driver for tracking multiple
24084 * commands. This ID is treated as opaque data by the firmware and
24085 * the value is returned in the `hwrm_resp_hdr` upon completion.
24089 * The target ID of the command:
24090 * * 0x0-0xFFF8 - The function ID
24091 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24092 * * 0xFFFD - Reserved for user-space HWRM interface
24095 uint16_t target_id;
24097 * A physical address pointer pointing to a host buffer that the
24098 * command's response data will be written. This can be either a host
24099 * physical address (HPA) or a guest physical address (GPA) and must
24100 * point to a physically contiguous block of memory.
24102 uint64_t resp_addr;
24103 /* Host address data is to DMA'd to. */
24104 uint64_t resp_data_addr;
24106 * Size of the buffer pointed to by resp_data_addr. The firmware may
24107 * use this entire buffer or less than the entire buffer, but never more.
24112 /* Port ID of port where PRBS test to be run. */
24114 /* Polynomial selection for PRBS test. */
24117 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
24119 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
24121 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
24123 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
24125 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
24127 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
24129 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
24131 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
24132 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
24133 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
24135 * Configuration bits for PRBS test.
24136 * Use enable bit to start/stop test.
24137 * Use tx/rx lane map bits to run test on specific lanes,
24138 * if set to 0 test will be run on all lanes.
24140 uint16_t prbs_config;
24142 * Set 0 to stop test currently in progress
24143 * Set 1 to start test with configuration provided.
24145 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
24148 * If set to 1, tx_lane_map bitmap should have lane bits set.
24149 * If set to 0, test will be run on all lanes for this port.
24151 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
24154 * If set to 1, rx_lane_map bitmap should have lane bits set.
24155 * If set to 0, test will be run on all lanes for this port.
24157 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
24159 /* Duration in seconds to run the PRBS test. */
24162 * If tx_lane_map_valid is set to 1, this field is a bitmap
24163 * of tx lanes to run PRBS test. bit0 = lane0,
24164 * bit1 = lane1 ..bit31 = lane31
24166 uint32_t tx_lane_map;
24168 * If rx_lane_map_valid is set to 1, this field is a bitmap
24169 * of rx lanes to run PRBS test. bit0 = lane0,
24170 * bit1 = lane1 ..bit31 = lane31
24172 uint32_t rx_lane_map;
24175 /* hwrm_port_prbs_test_output (size:128b/16B) */
24176 struct hwrm_port_prbs_test_output {
24177 /* The specific error status for the command. */
24178 uint16_t error_code;
24179 /* The HWRM command request type. */
24181 /* The sequence ID from the original command. */
24183 /* The length of the response data in number of bytes. */
24185 /* Total length of stored data. */
24186 uint16_t total_data_len;
24188 uint8_t unused_1[3];
24190 * This field is used in Output records to indicate that the output
24191 * is completely written to RAM. This field should be read as '1'
24192 * to indicate that the output has been completely written.
24193 * When writing a command completion or response to an internal processor,
24194 * the order of writes has to be such that this field is written last.
24199 /**********************
24200 * hwrm_port_dsc_dump *
24201 **********************/
24204 /* hwrm_port_dsc_dump_input (size:320b/40B) */
24205 struct hwrm_port_dsc_dump_input {
24206 /* The HWRM command request type. */
24209 * The completion ring to send the completion event on. This should
24210 * be the NQ ID returned from the `nq_alloc` HWRM command.
24212 uint16_t cmpl_ring;
24214 * The sequence ID is used by the driver for tracking multiple
24215 * commands. This ID is treated as opaque data by the firmware and
24216 * the value is returned in the `hwrm_resp_hdr` upon completion.
24220 * The target ID of the command:
24221 * * 0x0-0xFFF8 - The function ID
24222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24223 * * 0xFFFD - Reserved for user-space HWRM interface
24226 uint16_t target_id;
24228 * A physical address pointer pointing to a host buffer that the
24229 * command's response data will be written. This can be either a host
24230 * physical address (HPA) or a guest physical address (GPA) and must
24231 * point to a physically contiguous block of memory.
24233 uint64_t resp_addr;
24234 /* Host address where response diagnostic data is returned. */
24235 uint64_t resp_data_addr;
24237 * Size of the buffer pointed to by resp_data_addr. The firmware
24238 * may use this entire buffer or less than the entire buffer, but
24244 /* Port ID of port where dsc dump to be collected. */
24246 /* Diag level specified by the user */
24247 uint16_t diag_level;
24248 /* SRDS_DIAG_LANE */
24249 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
24251 /* SRDS_DIAG_CORE */
24252 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
24254 /* SRDS_DIAG_EVENT */
24255 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
24257 /* SRDS_DIAG_EYE */
24258 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
24260 /* SRDS_DIAG_REG_CORE */
24261 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
24263 /* SRDS_DIAG_REG_LANE */
24264 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
24266 /* SRDS_DIAG_UC_CORE */
24267 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
24269 /* SRDS_DIAG_UC_LANE */
24270 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
24272 /* SRDS_DIAG_LANE_DEBUG */
24273 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
24275 /* SRDS_DIAG_BER_VERT */
24276 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
24278 /* SRDS_DIAG_BER_HORZ */
24279 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
24281 /* SRDS_DIAG_EVENT_SAFE */
24282 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
24284 /* SRDS_DIAG_TIMESTAMP */
24285 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
24287 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
24288 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
24290 * This field is a lane number
24291 * on which to collect the dsc dump
24293 uint16_t lane_number;
24295 * Configuration bits.
24296 * Use enable bit to start dsc dump or retrieve dump
24298 uint16_t dsc_dump_config;
24300 * Set 0 to retrieve the dsc dump
24301 * Set 1 to start the dsc dump
24303 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
24307 /* hwrm_port_dsc_dump_output (size:128b/16B) */
24308 struct hwrm_port_dsc_dump_output {
24309 /* The specific error status for the command. */
24310 uint16_t error_code;
24311 /* The HWRM command request type. */
24313 /* The sequence ID from the original command. */
24315 /* The length of the response data in number of bytes. */
24317 /* Total length of stored data. */
24318 uint16_t total_data_len;
24320 uint8_t unused_1[3];
24322 * This field is used in Output records to indicate that the output
24323 * is completely written to RAM. This field should be read as '1'
24324 * to indicate that the output has been completely written.
24325 * When writing a command completion or response to an internal processor,
24326 * the order of writes has to be such that this field is written last.
24331 /******************************
24332 * hwrm_port_sfp_sideband_cfg *
24333 ******************************/
24336 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
24337 struct hwrm_port_sfp_sideband_cfg_input {
24338 /* The HWRM command request type. */
24341 * The completion ring to send the completion event on. This should
24342 * be the NQ ID returned from the `nq_alloc` HWRM command.
24344 uint16_t cmpl_ring;
24346 * The sequence ID is used by the driver for tracking multiple
24347 * commands. This ID is treated as opaque data by the firmware and
24348 * the value is returned in the `hwrm_resp_hdr` upon completion.
24352 * The target ID of the command:
24353 * * 0x0-0xFFF8 - The function ID
24354 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24355 * * 0xFFFD - Reserved for user-space HWRM interface
24358 uint16_t target_id;
24360 * A physical address pointer pointing to a host buffer that the
24361 * command's response data will be written. This can be either a host
24362 * physical address (HPA) or a guest physical address (GPA) and must
24363 * point to a physically contiguous block of memory.
24365 uint64_t resp_addr;
24366 /* Port ID of port that is to be queried. */
24368 uint8_t unused_0[6];
24370 * This bitfield is used to specify which bits from the 'flags'
24371 * fields are being configured by the caller.
24374 /* This bit must be '1' for rs0 to be configured. */
24375 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
24377 /* This bit must be '1' for rs1 to be configured. */
24378 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
24380 /* This bit must be '1' for tx_disable to be configured. */
24381 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
24384 * This bit must be '1' for mod_sel to be configured.
24385 * Valid only on QSFP modules
24387 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
24389 /* This bit must be '1' for reset_l to be configured. */
24390 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
24392 /* This bit must be '1' for lp_mode to be configured. */
24393 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
24395 /* This bit must be '1' for pwr_disable to be configured. */
24396 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
24399 * Only bits that have corresponding bits in the 'enables'
24400 * bitfield are processed by the firmware, all other bits
24401 * of 'flags' are ignored.
24405 * This bit along with rs1 configures the current speed of the dual
24406 * rate module. If these pins are GNDed then the speed can be changed
24407 * by driectly writing to EEPROM.
24409 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
24412 * This bit along with rs0 configures the current speed of the dual
24413 * rate module. If these pins are GNDed then the speed can be changed
24414 * by driectly writing to EEPROM.
24416 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
24419 * When this bit is set to '1', tx_disable is set.
24420 * On a 1G BASE-T module, if this bit is set,
24421 * module PHY registers will not be accessible.
24423 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
24426 * When this bit is set to '1', this module is selected.
24427 * Valid only on QSFP modules
24429 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
24432 * If reset_l is set to 0, Module will be taken out of reset
24433 * and other signals will be set to their requested state once
24434 * the module is out of reset.
24435 * Valid only on QSFP modules
24437 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
24440 * When this bit is set to '1', the module will be configured
24441 * in low power mode.
24442 * Valid only on QSFP modules
24444 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
24446 /* When this bit is set to '1', the module will be powered down. */
24447 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
24451 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
24452 struct hwrm_port_sfp_sideband_cfg_output {
24453 /* The specific error status for the command. */
24454 uint16_t error_code;
24455 /* The HWRM command request type. */
24457 /* The sequence ID from the original command. */
24459 /* The length of the response data in number of bytes. */
24463 * This field is used in Output records to indicate that the output
24464 * is completely written to RAM. This field should be read as '1'
24465 * to indicate that the output has been completely written. When
24466 * writing a command completion or response to an internal processor,
24467 * the order of writes has to be such that this field is written last.
24472 /*******************************
24473 * hwrm_port_sfp_sideband_qcfg *
24474 *******************************/
24477 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
24478 struct hwrm_port_sfp_sideband_qcfg_input {
24479 /* The HWRM command request type. */
24482 * The completion ring to send the completion event on. This should
24483 * be the NQ ID returned from the `nq_alloc` HWRM command.
24485 uint16_t cmpl_ring;
24487 * The sequence ID is used by the driver for tracking multiple
24488 * commands. This ID is treated as opaque data by the firmware and
24489 * the value is returned in the `hwrm_resp_hdr` upon completion.
24493 * The target ID of the command:
24494 * * 0x0-0xFFF8 - The function ID
24495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24496 * * 0xFFFD - Reserved for user-space HWRM interface
24499 uint16_t target_id;
24501 * A physical address pointer pointing to a host buffer that the
24502 * command's response data will be written. This can be either a host
24503 * physical address (HPA) or a guest physical address (GPA) and must
24504 * point to a physically contiguous block of memory.
24506 uint64_t resp_addr;
24507 /* Port ID of port that is to be queried. */
24509 uint8_t unused_0[6];
24512 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
24513 struct hwrm_port_sfp_sideband_qcfg_output {
24514 /* The specific error status for the command. */
24515 uint16_t error_code;
24516 /* The HWRM command request type. */
24518 /* The sequence ID from the original command. */
24520 /* The length of the response data in number of bytes. */
24523 * Bitmask indicating which sideband signals are valid.
24524 * This is based on the board and nvm cfg that is present on the board.
24526 uint32_t supported_mask;
24527 uint32_t sideband_signals;
24528 /* When this bit is set to '1', the Module is absent. */
24529 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
24532 * When this bit is set to '1', there is no valid signal on RX.
24533 * This signal is a filtered version of Signal Detect.
24535 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
24538 * This bit along with rs1 indiactes the current speed of the dual
24539 * rate module.If these pins are grounded then the speed can be
24540 * changed by driectky writing to EEPROM.
24542 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
24545 * This bit along with rs0 indiactes the current speed of the dual
24546 * rate module.If these pins are grounded then the speed can be
24547 * changed by driectky writing to EEPROM.
24549 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
24552 * When this bit is set to '1', tx_disable is set.
24553 * On a 1G BASE-T module, if this bit is set, module PHY
24554 * registers will not be accessible.
24556 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
24558 /* When this bit is set to '1', tx_fault is set. */
24559 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
24562 * When this bit is set to '1', module is selected.
24563 * Valid only on QSFP modules
24565 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
24568 * When this bit is set to '0', the module is held in reset.
24569 * if reset_l is set to 1,first module is taken out of reset
24570 * and other signals will be set to their requested state.
24571 * Valid only on QSFP modules.
24573 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
24576 * When this bit is set to '1', the module is in low power mode.
24577 * Valid only on QSFP modules
24579 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
24581 /* When this bit is set to '1', module is in power down state. */
24582 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
24586 * This field is used in Output records to indicate that the output
24587 * is completely written to RAM. This field should be read as '1'
24588 * to indicate that the output has been completely written. When
24589 * writing a command completion or response to an internal processor,
24590 * the order of writes has to be such that this field is written last.
24595 /**********************************
24596 * hwrm_port_phy_mdio_bus_acquire *
24597 **********************************/
24600 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
24601 struct hwrm_port_phy_mdio_bus_acquire_input {
24602 /* The HWRM command request type. */
24605 * The completion ring to send the completion event on. This should
24606 * be the NQ ID returned from the `nq_alloc` HWRM command.
24608 uint16_t cmpl_ring;
24610 * The sequence ID is used by the driver for tracking multiple
24611 * commands. This ID is treated as opaque data by the firmware and
24612 * the value is returned in the `hwrm_resp_hdr` upon completion.
24616 * The target ID of the command:
24617 * * 0x0-0xFFF8 - The function ID
24618 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24619 * * 0xFFFD - Reserved for user-space HWRM interface
24622 uint16_t target_id;
24624 * A physical address pointer pointing to a host buffer that the
24625 * command's response data will be written. This can be either a host
24626 * physical address (HPA) or a guest physical address (GPA) and must
24627 * point to a physically contiguous block of memory.
24629 uint64_t resp_addr;
24630 /* Port ID of the port. */
24633 * client_id of the client requesting BUS access.
24634 * Any value from 0x10 to 0xFFFF can be used.
24635 * Client should make sure that the returned client_id
24636 * in response matches the client_id in request.
24637 * 0-0xF are reserved for internal use.
24639 uint16_t client_id;
24641 * Timeout in milli seconds, MDIO BUS will be released automatically
24642 * after this time, if another mdio acquire command is not received
24643 * within the timeout window from the same client.
24644 * A 0xFFFF will hold the bus until this bus is released.
24646 uint16_t mdio_bus_timeout;
24647 uint8_t unused_0[2];
24650 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
24651 struct hwrm_port_phy_mdio_bus_acquire_output {
24652 /* The specific error status for the command. */
24653 uint16_t error_code;
24654 /* The HWRM command request type. */
24656 /* The sequence ID from the original command. */
24658 /* The length of the response data in number of bytes. */
24662 * client_id of the module holding the BUS.
24663 * 0-0xF are reserved for internal use.
24665 uint16_t client_id;
24666 uint8_t unused_1[3];
24668 * This field is used in Output records to indicate that the output
24669 * is completely written to RAM. This field should be read as '1'
24670 * to indicate that the output has been completely written.
24671 * When writing a command completion or response to an internal processor,
24672 * the order of writes has to be such that this field is written last.
24677 /**********************************
24678 * hwrm_port_phy_mdio_bus_release *
24679 **********************************/
24682 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
24683 struct hwrm_port_phy_mdio_bus_release_input {
24684 /* The HWRM command request type. */
24687 * The completion ring to send the completion event on. This should
24688 * be the NQ ID returned from the `nq_alloc` HWRM command.
24690 uint16_t cmpl_ring;
24692 * The sequence ID is used by the driver for tracking multiple
24693 * commands. This ID is treated as opaque data by the firmware and
24694 * the value is returned in the `hwrm_resp_hdr` upon completion.
24698 * The target ID of the command:
24699 * * 0x0-0xFFF8 - The function ID
24700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24701 * * 0xFFFD - Reserved for user-space HWRM interface
24704 uint16_t target_id;
24706 * A physical address pointer pointing to a host buffer that the
24707 * command's response data will be written. This can be either a host
24708 * physical address (HPA) or a guest physical address (GPA) and must
24709 * point to a physically contiguous block of memory.
24711 uint64_t resp_addr;
24712 /* Port ID of the port. */
24715 * client_id of the client requesting BUS release.
24716 * A client should not release any other clients BUS.
24718 uint16_t client_id;
24719 uint8_t unused_0[4];
24722 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
24723 struct hwrm_port_phy_mdio_bus_release_output {
24724 /* The specific error status for the command. */
24725 uint16_t error_code;
24726 /* The HWRM command request type. */
24728 /* The sequence ID from the original command. */
24730 /* The length of the response data in number of bytes. */
24733 /* The BUS is released if client_id matches the client_id in request. */
24734 uint16_t clients_id;
24735 uint8_t unused_1[3];
24737 * This field is used in Output records to indicate that the output
24738 * is completely written to RAM. This field should be read as '1'
24739 * to indicate that the output has been completely written.
24740 * When writing a command completion or response to an internal processor,
24741 * the order of writes has to be such that this field is written last.
24746 /************************
24747 * hwrm_port_tx_fir_cfg *
24748 ************************/
24751 /* hwrm_port_tx_fir_cfg_input (size:320b/40B) */
24752 struct hwrm_port_tx_fir_cfg_input {
24753 /* The HWRM command request type. */
24756 * The completion ring to send the completion event on. This should
24757 * be the NQ ID returned from the `nq_alloc` HWRM command.
24759 uint16_t cmpl_ring;
24761 * The sequence ID is used by the driver for tracking multiple
24762 * commands. This ID is treated as opaque data by the firmware and
24763 * the value is returned in the `hwrm_resp_hdr` upon completion.
24767 * The target ID of the command:
24768 * * 0x0-0xFFF8 - The function ID
24769 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24770 * * 0xFFFD - Reserved for user-space HWRM interface
24773 uint16_t target_id;
24775 * A physical address pointer pointing to a host buffer that the
24776 * command's response data will be written. This can be either a host
24777 * physical address (HPA) or a guest physical address (GPA) and must
24778 * point to a physically contiguous block of memory.
24780 uint64_t resp_addr;
24781 /* Modulation types of TX FIR: NRZ, PAM4. */
24784 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
24786 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
24787 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LAST \
24788 HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4
24789 /* The lane mask of the lane TX FIR will be configured. */
24791 uint8_t unused_0[2];
24792 /* Value1 of TX FIR, required for NRZ or PAM4. */
24793 uint32_t txfir_val_1;
24794 /* Value2 of TX FIR, required for NRZ or PAM4. */
24795 uint32_t txfir_val_2;
24796 /* Value3 of TX FIR, required for PAM4. */
24797 uint32_t txfir_val_3;
24798 /* Value4 of TX FIR, required for PAM4. */
24799 uint32_t txfir_val_4;
24800 uint8_t unused_1[4];
24803 /* hwrm_port_tx_fir_cfg_output (size:128b/16B) */
24804 struct hwrm_port_tx_fir_cfg_output {
24805 /* The specific error status for the command. */
24806 uint16_t error_code;
24807 /* The HWRM command request type. */
24809 /* The sequence ID from the original command. */
24811 /* The length of the response data in number of bytes. */
24815 * This field is used in Output records to indicate that the output
24816 * is completely written to RAM. This field should be read as '1'
24817 * to indicate that the output has been completely written.
24818 * When writing a command completion or response to an internal processor,
24819 * the order of writes has to be such that this field is written last.
24824 /*************************
24825 * hwrm_port_tx_fir_qcfg *
24826 *************************/
24829 /* hwrm_port_tx_fir_qcfg_input (size:192b/24B) */
24830 struct hwrm_port_tx_fir_qcfg_input {
24831 /* The HWRM command request type. */
24834 * The completion ring to send the completion event on. This should
24835 * be the NQ ID returned from the `nq_alloc` HWRM command.
24837 uint16_t cmpl_ring;
24839 * The sequence ID is used by the driver for tracking multiple
24840 * commands. This ID is treated as opaque data by the firmware and
24841 * the value is returned in the `hwrm_resp_hdr` upon completion.
24845 * The target ID of the command:
24846 * * 0x0-0xFFF8 - The function ID
24847 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24848 * * 0xFFFD - Reserved for user-space HWRM interface
24851 uint16_t target_id;
24853 * A physical address pointer pointing to a host buffer that the
24854 * command's response data will be written. This can be either a host
24855 * physical address (HPA) or a guest physical address (GPA) and must
24856 * point to a physically contiguous block of memory.
24858 uint64_t resp_addr;
24859 /* Modulation types of TX FIR: NRZ, PAM4. */
24862 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
24864 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
24865 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LAST \
24866 HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4
24867 /* The ID of the lane TX FIR will be queried. */
24872 /* hwrm_port_tx_fir_qcfg_output (size:256b/32B) */
24873 struct hwrm_port_tx_fir_qcfg_output {
24874 /* The specific error status for the command. */
24875 uint16_t error_code;
24876 /* The HWRM command request type. */
24878 /* The sequence ID from the original command. */
24880 /* The length of the response data in number of bytes. */
24882 /* Value1 of TX FIR, required for NRZ or PAM4. */
24883 uint32_t txfir_val_1;
24884 /* Value2 of TX FIR, required for NRZ or PAM4. */
24885 uint32_t txfir_val_2;
24886 /* Value3 of TX FIR, required for PAM4. */
24887 uint32_t txfir_val_3;
24888 /* Value4 of TX FIR, required for PAM4. */
24889 uint32_t txfir_val_4;
24892 * This field is used in Output records to indicate that the output
24893 * is completely written to RAM. This field should be read as '1'
24894 * to indicate that the output has been completely written.
24895 * When writing a command completion or response to an internal processor,
24896 * the order of writes has to be such that this field is written last.
24901 /***********************
24902 * hwrm_queue_qportcfg *
24903 ***********************/
24906 /* hwrm_queue_qportcfg_input (size:192b/24B) */
24907 struct hwrm_queue_qportcfg_input {
24908 /* The HWRM command request type. */
24911 * The completion ring to send the completion event on. This should
24912 * be the NQ ID returned from the `nq_alloc` HWRM command.
24914 uint16_t cmpl_ring;
24916 * The sequence ID is used by the driver for tracking multiple
24917 * commands. This ID is treated as opaque data by the firmware and
24918 * the value is returned in the `hwrm_resp_hdr` upon completion.
24922 * The target ID of the command:
24923 * * 0x0-0xFFF8 - The function ID
24924 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24925 * * 0xFFFD - Reserved for user-space HWRM interface
24928 uint16_t target_id;
24930 * A physical address pointer pointing to a host buffer that the
24931 * command's response data will be written. This can be either a host
24932 * physical address (HPA) or a guest physical address (GPA) and must
24933 * point to a physically contiguous block of memory.
24935 uint64_t resp_addr;
24938 * Enumeration denoting the RX, TX type of the resource.
24939 * This enumeration is used for resources that are similar for both
24940 * TX and RX paths of the chip.
24942 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
24944 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
24946 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
24947 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
24948 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
24950 * Port ID of port for which the queue configuration is being
24951 * queried. This field is only required when sent by IPC.
24955 * Drivers will set this capability when it can use
24956 * queue_idx_service_profile to map the queues to application.
24958 uint8_t drv_qmap_cap;
24960 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
24962 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
24963 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
24964 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
24968 /* hwrm_queue_qportcfg_output (size:1344b/168B) */
24969 struct hwrm_queue_qportcfg_output {
24970 /* The specific error status for the command. */
24971 uint16_t error_code;
24972 /* The HWRM command request type. */
24974 /* The sequence ID from the original command. */
24976 /* The length of the response data in number of bytes. */
24979 * The maximum number of queues that can be configured on this
24981 * Valid values range from 1 through 8.
24983 uint8_t max_configurable_queues;
24985 * The maximum number of lossless queues that can be configured
24987 * Valid values range from 0 through 8.
24989 uint8_t max_configurable_lossless_queues;
24991 * Bitmask indicating which queues can be configured by the
24992 * hwrm_queue_cfg command.
24994 * Each bit represents a specific queue where bit 0 represents
24995 * queue 0 and bit 7 represents queue 7.
24996 * # A value of 0 indicates that the queue is not configurable
24997 * by the hwrm_queue_cfg command.
24998 * # A value of 1 indicates that the queue is configurable.
24999 * # A hwrm_queue_cfg command shall return error when trying to
25000 * configure a queue not configurable.
25002 uint8_t queue_cfg_allowed;
25003 /* Information about queue configuration. */
25004 uint8_t queue_cfg_info;
25006 * If this flag is set to '1', then the queues are
25007 * configured asymmetrically on TX and RX sides.
25008 * If this flag is set to '0', then the queues are
25009 * configured symmetrically on TX and RX sides. For
25010 * symmetric configuration, the queue configuration
25011 * including queue ids and service profiles on the
25012 * TX side is the same as the corresponding queue
25013 * configuration on the RX side.
25015 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
25018 * Bitmask indicating which queues can be configured by the
25019 * hwrm_queue_pfcenable_cfg command.
25021 * Each bit represents a specific priority where bit 0 represents
25022 * priority 0 and bit 7 represents priority 7.
25023 * # A value of 0 indicates that the priority is not configurable by
25024 * the hwrm_queue_pfcenable_cfg command.
25025 * # A value of 1 indicates that the priority is configurable.
25026 * # A hwrm_queue_pfcenable_cfg command shall return error when
25027 * trying to configure a priority that is not configurable.
25029 uint8_t queue_pfcenable_cfg_allowed;
25031 * Bitmask indicating which queues can be configured by the
25032 * hwrm_queue_pri2cos_cfg command.
25034 * Each bit represents a specific queue where bit 0 represents
25035 * queue 0 and bit 7 represents queue 7.
25036 * # A value of 0 indicates that the queue is not configurable
25037 * by the hwrm_queue_pri2cos_cfg command.
25038 * # A value of 1 indicates that the queue is configurable.
25039 * # A hwrm_queue_pri2cos_cfg command shall return error when
25040 * trying to configure a queue that is not configurable.
25042 uint8_t queue_pri2cos_cfg_allowed;
25044 * Bitmask indicating which queues can be configured by the
25045 * hwrm_queue_pri2cos_cfg command.
25047 * Each bit represents a specific queue where bit 0 represents
25048 * queue 0 and bit 7 represents queue 7.
25049 * # A value of 0 indicates that the queue is not configurable
25050 * by the hwrm_queue_pri2cos_cfg command.
25051 * # A value of 1 indicates that the queue is configurable.
25052 * # A hwrm_queue_pri2cos_cfg command shall return error when
25053 * trying to configure a queue not configurable.
25055 uint8_t queue_cos2bw_cfg_allowed;
25057 * ID of CoS Queue 0.
25060 * # This ID can be used on any subsequent call to an hwrm command
25061 * that takes a queue id.
25062 * # IDs must always be queried by this command before any use
25063 * by the driver or software.
25064 * # The CoS queue index is obtained by applying modulo 10 to the
25065 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25066 * The CoS queue index is used to reference port statistics for the
25068 * # A value of 0xff indicates that the queue is not available.
25069 * # Available queues may not be in sequential order.
25072 /* This value specifies service profile kind for CoS queue */
25073 uint8_t queue_id0_service_profile;
25074 /* Lossy (best-effort) */
25075 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
25078 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
25080 /* Lossless RoCE (deprecated) */
25081 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
25083 /* Lossy RoCE CNP (deprecated) */
25084 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25086 /* Lossless NIC (deprecated) */
25087 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
25089 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25090 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
25092 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
25093 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
25095 * ID of CoS Queue 1.
25098 * # This ID can be used on any subsequent call to an hwrm command
25099 * that takes a queue id.
25100 * # IDs must always be queried by this command before any use
25101 * by the driver or software.
25102 * # The CoS queue index is obtained by applying modulo 10 to the
25103 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25104 * The CoS queue index is used to reference port statistics for the
25106 * # A value of 0xff indicates that the queue is not available.
25107 * # Available queues may not be in sequential order.
25110 /* This value specifies service profile kind for CoS queue */
25111 uint8_t queue_id1_service_profile;
25112 /* Lossy (best-effort) */
25113 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
25116 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
25118 /* Lossless RoCE (deprecated) */
25119 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
25121 /* Lossy RoCE CNP (deprecated) */
25122 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25124 /* Lossless NIC (deprecated) */
25125 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
25127 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25128 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
25130 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
25131 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
25133 * ID of CoS Queue 2.
25136 * # This ID can be used on any subsequent call to an hwrm command
25137 * that takes a queue id.
25138 * # IDs must always be queried by this command before any use
25139 * by the driver or software.
25140 * # The CoS queue index is obtained by applying modulo 10 to the
25141 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25142 * The CoS queue index is used to reference port statistics for the
25144 * # A value of 0xff indicates that the queue is not available.
25145 * # Available queues may not be in sequential order.
25148 /* This value specifies service profile kind for CoS queue */
25149 uint8_t queue_id2_service_profile;
25150 /* Lossy (best-effort) */
25151 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
25154 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
25156 /* Lossless RoCE (deprecated) */
25157 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
25159 /* Lossy RoCE CNP (deprecated) */
25160 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25162 /* Lossless NIC (deprecated) */
25163 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
25165 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25166 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
25168 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
25169 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
25171 * ID of CoS Queue 3.
25174 * # This ID can be used on any subsequent call to an hwrm command
25175 * that takes a queue id.
25176 * # IDs must always be queried by this command before any use
25177 * by the driver or software.
25178 * # The CoS queue index is obtained by applying modulo 10 to the
25179 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25180 * The CoS queue index is used to reference port statistics for the
25182 * # A value of 0xff indicates that the queue is not available.
25183 * # Available queues may not be in sequential order.
25186 /* This value specifies service profile kind for CoS queue */
25187 uint8_t queue_id3_service_profile;
25188 /* Lossy (best-effort) */
25189 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
25192 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
25194 /* Lossless RoCE (deprecated) */
25195 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
25197 /* Lossy RoCE CNP (deprecated) */
25198 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25200 /* Lossless NIC (deprecated) */
25201 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
25203 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25204 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
25206 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
25207 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
25209 * ID of CoS Queue 4.
25212 * # This ID can be used on any subsequent call to an hwrm command
25213 * that takes a queue id.
25214 * # IDs must always be queried by this command before any use
25215 * by the driver or software.
25216 * # The CoS queue index is obtained by applying modulo 10 to the
25217 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25218 * The CoS queue index is used to reference port statistics for the
25220 * # A value of 0xff indicates that the queue is not available.
25221 * # Available queues may not be in sequential order.
25224 /* This value specifies service profile kind for CoS queue */
25225 uint8_t queue_id4_service_profile;
25226 /* Lossy (best-effort) */
25227 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
25230 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
25232 /* Lossless RoCE (deprecated) */
25233 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
25235 /* Lossy RoCE CNP (deprecated) */
25236 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25238 /* Lossless NIC (deprecated) */
25239 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
25241 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25242 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
25244 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
25245 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
25247 * ID of CoS Queue 5.
25250 * # This ID can be used on any subsequent call to an hwrm command
25251 * that takes a queue id.
25252 * # IDs must always be queried by this command before any use
25253 * by the driver or software.
25254 * # The CoS queue index is obtained by applying modulo 10 to the
25255 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25256 * The CoS queue index is used to reference port statistics for the
25258 * # A value of 0xff indicates that the queue is not available.
25259 * # Available queues may not be in sequential order.
25262 /* This value specifies service profile kind for CoS queue */
25263 uint8_t queue_id5_service_profile;
25264 /* Lossy (best-effort) */
25265 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
25268 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
25270 /* Lossless RoCE (deprecated) */
25271 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
25273 /* Lossy RoCE CNP (deprecated) */
25274 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25276 /* Lossless NIC (deprecated) */
25277 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
25279 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25280 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
25282 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
25283 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
25285 * ID of CoS Queue 6.
25288 * # This ID can be used on any subsequent call to an hwrm command
25289 * that takes a queue id.
25290 * # IDs must always be queried by this command before any use
25291 * by the driver or software.
25292 * # The CoS queue index is obtained by applying modulo 10 to the
25293 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25294 * The CoS queue index is used to reference port statistics for the
25296 * # A value of 0xff indicates that the queue is not available.
25297 * # Available queues may not be in sequential order.
25300 /* This value specifies service profile kind for CoS queue */
25301 uint8_t queue_id6_service_profile;
25302 /* Lossy (best-effort) */
25303 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
25306 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
25308 /* Lossless RoCE (deprecated) */
25309 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
25311 /* Lossy RoCE CNP (deprecated) */
25312 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25314 /* Lossless NIC (deprecated) */
25315 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
25317 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25318 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
25320 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
25321 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
25323 * ID of CoS Queue 7.
25326 * # This ID can be used on any subsequent call to an hwrm command
25327 * that takes a queue id.
25328 * # IDs must always be queried by this command before any use
25329 * by the driver or software.
25330 * # The CoS queue index is obtained by applying modulo 10 to the
25331 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
25332 * The CoS queue index is used to reference port statistics for the
25334 * # A value of 0xff indicates that the queue is not available.
25335 * # Available queues may not be in sequential order.
25338 /* This value specifies service profile kind for CoS queue */
25339 uint8_t queue_id7_service_profile;
25340 /* Lossy (best-effort) */
25341 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
25344 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
25346 /* Lossless RoCE (deprecated) */
25347 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
25349 /* Lossy RoCE CNP (deprecated) */
25350 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
25352 /* Lossless NIC (deprecated) */
25353 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
25355 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25356 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
25358 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
25359 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
25361 * This value specifies traffic type for the service profile. We can
25362 * have a TC mapped to multiple traffic types. For example shared
25363 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25364 * A value of zero is considered as invalid.
25366 uint8_t queue_id0_service_profile_type;
25367 /* Recommended to be used for RoCE traffic only. */
25368 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \
25370 /* Recommended to be used for NIC/L2 traffic only. */
25371 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \
25373 /* Recommended to be used for CNP traffic only. */
25374 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \
25377 * Up to 16 bytes of null padded ASCII string describing this queue.
25378 * The queue name includes a CoS queue index and, in some cases, text
25379 * that distinguishes the queue from other queues in the group.
25381 char qid0_name[16];
25382 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25383 char qid1_name[16];
25384 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25385 char qid2_name[16];
25386 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25387 char qid3_name[16];
25388 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25389 char qid4_name[16];
25390 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25391 char qid5_name[16];
25392 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25393 char qid6_name[16];
25394 /* Up to 16 bytes of null padded ASCII string describing this queue. */
25395 char qid7_name[16];
25397 * This value specifies traffic type for the service profile. We can
25398 * have a TC mapped to multiple traffic types. For example shared
25399 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25400 * A value of zero is considered as invalid.
25402 uint8_t queue_id1_service_profile_type;
25403 /* Recommended to be used for RoCE traffic only. */
25404 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \
25406 /* Recommended to be used for NIC/L2 traffic only. */
25407 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \
25409 /* Recommended to be used for CNP traffic only. */
25410 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \
25413 * This value specifies traffic type for the service profile. We can
25414 * have a TC mapped to multiple traffic types. For example shared
25415 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25416 * A value of zero is considered as invalid.
25418 uint8_t queue_id2_service_profile_type;
25419 /* Recommended to be used for RoCE traffic only. */
25420 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \
25422 /* Recommended to be used for NIC/L2 traffic only. */
25423 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \
25425 /* Recommended to be used for CNP traffic only. */
25426 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \
25429 * This value specifies traffic type for the service profile. We can
25430 * have a TC mapped to multiple traffic types. For example shared
25431 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25432 * A value of zero is considered as invalid.
25434 uint8_t queue_id3_service_profile_type;
25435 /* Recommended to be used for RoCE traffic only. */
25436 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \
25438 /* Recommended to be used for NIC/L2 traffic only. */
25439 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \
25441 /* Recommended to be used for CNP traffic only. */
25442 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \
25445 * This value specifies traffic type for the service profile. We can
25446 * have a TC mapped to multiple traffic types. For example shared
25447 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25448 * A value of zero is considered as invalid.
25450 uint8_t queue_id4_service_profile_type;
25451 /* Recommended to be used for RoCE traffic only. */
25452 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \
25454 /* Recommended to be used for NIC/L2 traffic only. */
25455 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \
25457 /* Recommended to be used for CNP traffic only. */
25458 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \
25461 * This value specifies traffic type for the service profile. We can
25462 * have a TC mapped to multiple traffic types. For example shared
25463 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25464 * A value of zero is considered as invalid.
25466 uint8_t queue_id5_service_profile_type;
25467 /* Recommended to be used for RoCE traffic only. */
25468 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \
25470 /* Recommended to be used for NIC/L2 traffic only. */
25471 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \
25473 /* Recommended to be used for CNP traffic only. */
25474 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \
25477 * This value specifies traffic type for the service profile. We can
25478 * have a TC mapped to multiple traffic types. For example shared
25479 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25480 * A value of zero is considered as invalid.
25482 uint8_t queue_id6_service_profile_type;
25483 /* Recommended to be used for RoCE traffic only. */
25484 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \
25486 /* Recommended to be used for NIC/L2 traffic only. */
25487 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \
25489 /* Recommended to be used for CNP traffic only. */
25490 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \
25493 * This value specifies traffic type for the service profile. We can
25494 * have a TC mapped to multiple traffic types. For example shared
25495 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
25496 * A value of zero is considered as invalid.
25498 uint8_t queue_id7_service_profile_type;
25499 /* Recommended to be used for RoCE traffic only. */
25500 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \
25502 /* Recommended to be used for NIC/L2 traffic only. */
25503 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \
25505 /* Recommended to be used for CNP traffic only. */
25506 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \
25509 * This field is used in Output records to indicate that the output
25510 * is completely written to RAM. This field should be read as '1'
25511 * to indicate that the output has been completely written.
25512 * When writing a command completion or response to an internal processor,
25513 * the order of writes has to be such that this field is written last.
25518 /*******************
25519 * hwrm_queue_qcfg *
25520 *******************/
25523 /* hwrm_queue_qcfg_input (size:192b/24B) */
25524 struct hwrm_queue_qcfg_input {
25525 /* The HWRM command request type. */
25528 * The completion ring to send the completion event on. This should
25529 * be the NQ ID returned from the `nq_alloc` HWRM command.
25531 uint16_t cmpl_ring;
25533 * The sequence ID is used by the driver for tracking multiple
25534 * commands. This ID is treated as opaque data by the firmware and
25535 * the value is returned in the `hwrm_resp_hdr` upon completion.
25539 * The target ID of the command:
25540 * * 0x0-0xFFF8 - The function ID
25541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25542 * * 0xFFFD - Reserved for user-space HWRM interface
25545 uint16_t target_id;
25547 * A physical address pointer pointing to a host buffer that the
25548 * command's response data will be written. This can be either a host
25549 * physical address (HPA) or a guest physical address (GPA) and must
25550 * point to a physically contiguous block of memory.
25552 uint64_t resp_addr;
25555 * Enumeration denoting the RX, TX type of the resource.
25556 * This enumeration is used for resources that are similar for both
25557 * TX and RX paths of the chip.
25559 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
25561 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25563 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25564 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
25565 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
25566 /* Queue ID of the queue. */
25570 /* hwrm_queue_qcfg_output (size:128b/16B) */
25571 struct hwrm_queue_qcfg_output {
25572 /* The specific error status for the command. */
25573 uint16_t error_code;
25574 /* The HWRM command request type. */
25576 /* The sequence ID from the original command. */
25578 /* The length of the response data in number of bytes. */
25581 * This value is the estimate packet length used in the
25584 uint32_t queue_len;
25585 /* This value is applicable to CoS queues only. */
25586 uint8_t service_profile;
25587 /* Lossy (best-effort) */
25588 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
25590 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
25591 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25592 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
25593 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
25594 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
25595 /* Information about queue configuration. */
25596 uint8_t queue_cfg_info;
25598 * If this flag is set to '1', then the queue is
25599 * configured asymmetrically on TX and RX sides.
25600 * If this flag is set to '0', then this queue is
25601 * configured symmetrically on TX and RX sides.
25603 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
25607 * This field is used in Output records to indicate that the output
25608 * is completely written to RAM. This field should be read as '1'
25609 * to indicate that the output has been completely written.
25610 * When writing a command completion or response to an internal processor,
25611 * the order of writes has to be such that this field is written last.
25616 /******************
25618 ******************/
25621 /* hwrm_queue_cfg_input (size:320b/40B) */
25622 struct hwrm_queue_cfg_input {
25623 /* The HWRM command request type. */
25626 * The completion ring to send the completion event on. This should
25627 * be the NQ ID returned from the `nq_alloc` HWRM command.
25629 uint16_t cmpl_ring;
25631 * The sequence ID is used by the driver for tracking multiple
25632 * commands. This ID is treated as opaque data by the firmware and
25633 * the value is returned in the `hwrm_resp_hdr` upon completion.
25637 * The target ID of the command:
25638 * * 0x0-0xFFF8 - The function ID
25639 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25640 * * 0xFFFD - Reserved for user-space HWRM interface
25643 uint16_t target_id;
25645 * A physical address pointer pointing to a host buffer that the
25646 * command's response data will be written. This can be either a host
25647 * physical address (HPA) or a guest physical address (GPA) and must
25648 * point to a physically contiguous block of memory.
25650 uint64_t resp_addr;
25653 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
25654 * This enumeration is used for resources that are similar for both
25655 * TX and RX paths of the chip.
25657 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
25658 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
25660 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25662 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25663 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
25664 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
25665 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
25666 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
25669 * This bit must be '1' for the dflt_len field to be
25672 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
25674 * This bit must be '1' for the service_profile field to be
25677 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
25678 /* Queue ID of queue that is to be configured by this function. */
25681 * This value is a the estimate packet length used in the
25683 * Set to 0xFF... (All Fs) to not adjust this value.
25686 /* This value is applicable to CoS queues only. */
25687 uint8_t service_profile;
25688 /* Lossy (best-effort) */
25689 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
25691 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
25692 /* Set to 0xFF... (All Fs) if there is no service profile specified */
25693 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
25694 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
25695 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
25696 uint8_t unused_0[7];
25699 /* hwrm_queue_cfg_output (size:128b/16B) */
25700 struct hwrm_queue_cfg_output {
25701 /* The specific error status for the command. */
25702 uint16_t error_code;
25703 /* The HWRM command request type. */
25705 /* The sequence ID from the original command. */
25707 /* The length of the response data in number of bytes. */
25709 uint8_t unused_0[7];
25711 * This field is used in Output records to indicate that the output
25712 * is completely written to RAM. This field should be read as '1'
25713 * to indicate that the output has been completely written.
25714 * When writing a command completion or response to an internal processor,
25715 * the order of writes has to be such that this field is written last.
25720 /*****************************
25721 * hwrm_queue_pfcenable_qcfg *
25722 *****************************/
25725 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
25726 struct hwrm_queue_pfcenable_qcfg_input {
25727 /* The HWRM command request type. */
25730 * The completion ring to send the completion event on. This should
25731 * be the NQ ID returned from the `nq_alloc` HWRM command.
25733 uint16_t cmpl_ring;
25735 * The sequence ID is used by the driver for tracking multiple
25736 * commands. This ID is treated as opaque data by the firmware and
25737 * the value is returned in the `hwrm_resp_hdr` upon completion.
25741 * The target ID of the command:
25742 * * 0x0-0xFFF8 - The function ID
25743 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25744 * * 0xFFFD - Reserved for user-space HWRM interface
25747 uint16_t target_id;
25749 * A physical address pointer pointing to a host buffer that the
25750 * command's response data will be written. This can be either a host
25751 * physical address (HPA) or a guest physical address (GPA) and must
25752 * point to a physically contiguous block of memory.
25754 uint64_t resp_addr;
25756 * Port ID of port for which the table is being configured.
25757 * The HWRM needs to check whether this function is allowed
25758 * to configure pri2cos mapping on this port.
25761 uint8_t unused_0[6];
25764 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
25765 struct hwrm_queue_pfcenable_qcfg_output {
25766 /* The specific error status for the command. */
25767 uint16_t error_code;
25768 /* The HWRM command request type. */
25770 /* The sequence ID from the original command. */
25772 /* The length of the response data in number of bytes. */
25775 /* If set to 1, then PFC is enabled on PRI 0. */
25776 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
25778 /* If set to 1, then PFC is enabled on PRI 1. */
25779 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
25781 /* If set to 1, then PFC is enabled on PRI 2. */
25782 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
25784 /* If set to 1, then PFC is enabled on PRI 3. */
25785 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
25787 /* If set to 1, then PFC is enabled on PRI 4. */
25788 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
25790 /* If set to 1, then PFC is enabled on PRI 5. */
25791 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
25793 /* If set to 1, then PFC is enabled on PRI 6. */
25794 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
25796 /* If set to 1, then PFC is enabled on PRI 7. */
25797 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
25799 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
25800 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
25802 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
25803 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
25805 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
25806 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
25808 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
25809 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
25811 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
25812 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
25814 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
25815 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
25817 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
25818 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
25820 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
25821 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
25823 uint8_t unused_0[3];
25825 * This field is used in Output records to indicate that the output
25826 * is completely written to RAM. This field should be read as '1'
25827 * to indicate that the output has been completely written.
25828 * When writing a command completion or response to an internal processor,
25829 * the order of writes has to be such that this field is written last.
25834 /****************************
25835 * hwrm_queue_pfcenable_cfg *
25836 ****************************/
25839 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
25840 struct hwrm_queue_pfcenable_cfg_input {
25841 /* The HWRM command request type. */
25844 * The completion ring to send the completion event on. This should
25845 * be the NQ ID returned from the `nq_alloc` HWRM command.
25847 uint16_t cmpl_ring;
25849 * The sequence ID is used by the driver for tracking multiple
25850 * commands. This ID is treated as opaque data by the firmware and
25851 * the value is returned in the `hwrm_resp_hdr` upon completion.
25855 * The target ID of the command:
25856 * * 0x0-0xFFF8 - The function ID
25857 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25858 * * 0xFFFD - Reserved for user-space HWRM interface
25861 uint16_t target_id;
25863 * A physical address pointer pointing to a host buffer that the
25864 * command's response data will be written. This can be either a host
25865 * physical address (HPA) or a guest physical address (GPA) and must
25866 * point to a physically contiguous block of memory.
25868 uint64_t resp_addr;
25870 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
25871 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
25873 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
25874 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
25876 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
25877 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
25879 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
25880 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
25882 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
25883 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
25885 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
25886 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
25888 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
25889 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
25891 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
25892 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
25894 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
25895 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
25897 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
25898 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
25900 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
25901 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
25903 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
25904 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
25906 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
25907 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
25909 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
25910 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
25912 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
25913 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
25915 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
25916 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
25919 * Port ID of port for which the table is being configured.
25920 * The HWRM needs to check whether this function is allowed
25921 * to configure pri2cos mapping on this port.
25924 uint8_t unused_0[2];
25927 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
25928 struct hwrm_queue_pfcenable_cfg_output {
25929 /* The specific error status for the command. */
25930 uint16_t error_code;
25931 /* The HWRM command request type. */
25933 /* The sequence ID from the original command. */
25935 /* The length of the response data in number of bytes. */
25937 uint8_t unused_0[7];
25939 * This field is used in Output records to indicate that the output
25940 * is completely written to RAM. This field should be read as '1'
25941 * to indicate that the output has been completely written.
25942 * When writing a command completion or response to an internal processor,
25943 * the order of writes has to be such that this field is written last.
25948 /***************************
25949 * hwrm_queue_pri2cos_qcfg *
25950 ***************************/
25953 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
25954 struct hwrm_queue_pri2cos_qcfg_input {
25955 /* The HWRM command request type. */
25958 * The completion ring to send the completion event on. This should
25959 * be the NQ ID returned from the `nq_alloc` HWRM command.
25961 uint16_t cmpl_ring;
25963 * The sequence ID is used by the driver for tracking multiple
25964 * commands. This ID is treated as opaque data by the firmware and
25965 * the value is returned in the `hwrm_resp_hdr` upon completion.
25969 * The target ID of the command:
25970 * * 0x0-0xFFF8 - The function ID
25971 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25972 * * 0xFFFD - Reserved for user-space HWRM interface
25975 uint16_t target_id;
25977 * A physical address pointer pointing to a host buffer that the
25978 * command's response data will be written. This can be either a host
25979 * physical address (HPA) or a guest physical address (GPA) and must
25980 * point to a physically contiguous block of memory.
25982 uint64_t resp_addr;
25985 * Enumeration denoting the RX, TX type of the resource.
25986 * This enumeration is used for resources that are similar for both
25987 * TX and RX paths of the chip.
25989 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
25991 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
25993 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
25994 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
25995 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
25997 * When this bit is set to '0', the query is
25998 * for PRI from tunnel headers.
25999 * When this bit is set to '1', the query is
26000 * for PRI from inner packet headers.
26002 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
26004 * Port ID of port for which the table is being configured.
26005 * The HWRM needs to check whether this function is allowed
26006 * to configure pri2cos mapping on this port.
26009 uint8_t unused_0[3];
26012 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
26013 struct hwrm_queue_pri2cos_qcfg_output {
26014 /* The specific error status for the command. */
26015 uint16_t error_code;
26016 /* The HWRM command request type. */
26018 /* The sequence ID from the original command. */
26020 /* The length of the response data in number of bytes. */
26023 * CoS Queue assigned to priority 0. This value can only
26024 * be changed before traffic has started.
26025 * A value of 0xff indicates that no CoS queue is assigned to the
26026 * specified priority.
26028 uint8_t pri0_cos_queue_id;
26030 * CoS Queue assigned to priority 1. This value can only
26031 * be changed before traffic has started.
26032 * A value of 0xff indicates that no CoS queue is assigned to the
26033 * specified priority.
26035 uint8_t pri1_cos_queue_id;
26037 * CoS Queue assigned to priority 2. This value can only
26038 * be changed before traffic has started.
26039 * A value of 0xff indicates that no CoS queue is assigned to the
26040 * specified priority.
26042 uint8_t pri2_cos_queue_id;
26044 * CoS Queue assigned to priority 3. This value can only
26045 * be changed before traffic has started.
26046 * A value of 0xff indicates that no CoS queue is assigned to the
26047 * specified priority.
26049 uint8_t pri3_cos_queue_id;
26051 * CoS Queue assigned to priority 4. This value can only
26052 * be changed before traffic has started.
26053 * A value of 0xff indicates that no CoS queue is assigned to the
26054 * specified priority.
26056 uint8_t pri4_cos_queue_id;
26058 * CoS Queue assigned to priority 5. This value can only
26059 * be changed before traffic has started.
26060 * A value of 0xff indicates that no CoS queue is assigned to the
26061 * specified priority.
26063 uint8_t pri5_cos_queue_id;
26065 * CoS Queue assigned to priority 6. This value can only
26066 * be changed before traffic has started.
26067 * A value of 0xff indicates that no CoS queue is assigned to the
26068 * specified priority.
26070 uint8_t pri6_cos_queue_id;
26072 * CoS Queue assigned to priority 7. This value can only
26073 * be changed before traffic has started.
26074 * A value of 0xff indicates that no CoS queue is assigned to the
26075 * specified priority.
26077 uint8_t pri7_cos_queue_id;
26078 /* Information about queue configuration. */
26079 uint8_t queue_cfg_info;
26081 * If this flag is set to '1', then the PRI to CoS
26082 * configuration is asymmetric on TX and RX sides.
26083 * If this flag is set to '0', then PRI to CoS configuration
26084 * is symmetric on TX and RX sides.
26086 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
26088 uint8_t unused_0[6];
26090 * This field is used in Output records to indicate that the output
26091 * is completely written to RAM. This field should be read as '1'
26092 * to indicate that the output has been completely written.
26093 * When writing a command completion or response to an internal processor,
26094 * the order of writes has to be such that this field is written last.
26099 /**************************
26100 * hwrm_queue_pri2cos_cfg *
26101 **************************/
26104 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
26105 struct hwrm_queue_pri2cos_cfg_input {
26106 /* The HWRM command request type. */
26109 * The completion ring to send the completion event on. This should
26110 * be the NQ ID returned from the `nq_alloc` HWRM command.
26112 uint16_t cmpl_ring;
26114 * The sequence ID is used by the driver for tracking multiple
26115 * commands. This ID is treated as opaque data by the firmware and
26116 * the value is returned in the `hwrm_resp_hdr` upon completion.
26120 * The target ID of the command:
26121 * * 0x0-0xFFF8 - The function ID
26122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26123 * * 0xFFFD - Reserved for user-space HWRM interface
26126 uint16_t target_id;
26128 * A physical address pointer pointing to a host buffer that the
26129 * command's response data will be written. This can be either a host
26130 * physical address (HPA) or a guest physical address (GPA) and must
26131 * point to a physically contiguous block of memory.
26133 uint64_t resp_addr;
26136 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
26137 * This enumeration is used for resources that are similar for both
26138 * TX and RX paths of the chip.
26140 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
26141 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
26143 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
26145 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
26146 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
26147 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
26148 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
26149 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
26151 * When this bit is set to '0', the mapping is requested
26152 * for PRI from tunnel headers.
26153 * When this bit is set to '1', the mapping is requested
26154 * for PRI from inner packet headers.
26156 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
26159 * This bit must be '1' for the pri0_cos_queue_id field to be
26162 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
26165 * This bit must be '1' for the pri1_cos_queue_id field to be
26168 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
26171 * This bit must be '1' for the pri2_cos_queue_id field to be
26174 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
26177 * This bit must be '1' for the pri3_cos_queue_id field to be
26180 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
26183 * This bit must be '1' for the pri4_cos_queue_id field to be
26186 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
26189 * This bit must be '1' for the pri5_cos_queue_id field to be
26192 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
26195 * This bit must be '1' for the pri6_cos_queue_id field to be
26198 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
26201 * This bit must be '1' for the pri7_cos_queue_id field to be
26204 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
26207 * Port ID of port for which the table is being configured.
26208 * The HWRM needs to check whether this function is allowed
26209 * to configure pri2cos mapping on this port.
26213 * CoS Queue assigned to priority 0. This value can only
26214 * be changed before traffic has started.
26216 uint8_t pri0_cos_queue_id;
26218 * CoS Queue assigned to priority 1. This value can only
26219 * be changed before traffic has started.
26221 uint8_t pri1_cos_queue_id;
26223 * CoS Queue assigned to priority 2 This value can only
26224 * be changed before traffic has started.
26226 uint8_t pri2_cos_queue_id;
26228 * CoS Queue assigned to priority 3. This value can only
26229 * be changed before traffic has started.
26231 uint8_t pri3_cos_queue_id;
26233 * CoS Queue assigned to priority 4. This value can only
26234 * be changed before traffic has started.
26236 uint8_t pri4_cos_queue_id;
26238 * CoS Queue assigned to priority 5. This value can only
26239 * be changed before traffic has started.
26241 uint8_t pri5_cos_queue_id;
26243 * CoS Queue assigned to priority 6. This value can only
26244 * be changed before traffic has started.
26246 uint8_t pri6_cos_queue_id;
26248 * CoS Queue assigned to priority 7. This value can only
26249 * be changed before traffic has started.
26251 uint8_t pri7_cos_queue_id;
26252 uint8_t unused_0[7];
26255 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
26256 struct hwrm_queue_pri2cos_cfg_output {
26257 /* The specific error status for the command. */
26258 uint16_t error_code;
26259 /* The HWRM command request type. */
26261 /* The sequence ID from the original command. */
26263 /* The length of the response data in number of bytes. */
26265 uint8_t unused_0[7];
26267 * This field is used in Output records to indicate that the output
26268 * is completely written to RAM. This field should be read as '1'
26269 * to indicate that the output has been completely written.
26270 * When writing a command completion or response to an internal processor,
26271 * the order of writes has to be such that this field is written last.
26276 /**************************
26277 * hwrm_queue_cos2bw_qcfg *
26278 **************************/
26281 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
26282 struct hwrm_queue_cos2bw_qcfg_input {
26283 /* The HWRM command request type. */
26286 * The completion ring to send the completion event on. This should
26287 * be the NQ ID returned from the `nq_alloc` HWRM command.
26289 uint16_t cmpl_ring;
26291 * The sequence ID is used by the driver for tracking multiple
26292 * commands. This ID is treated as opaque data by the firmware and
26293 * the value is returned in the `hwrm_resp_hdr` upon completion.
26297 * The target ID of the command:
26298 * * 0x0-0xFFF8 - The function ID
26299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26300 * * 0xFFFD - Reserved for user-space HWRM interface
26303 uint16_t target_id;
26305 * A physical address pointer pointing to a host buffer that the
26306 * command's response data will be written. This can be either a host
26307 * physical address (HPA) or a guest physical address (GPA) and must
26308 * point to a physically contiguous block of memory.
26310 uint64_t resp_addr;
26312 * Port ID of port for which the table is being configured.
26313 * The HWRM needs to check whether this function is allowed
26314 * to configure TC BW assignment on this port.
26317 uint8_t unused_0[6];
26320 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
26321 struct hwrm_queue_cos2bw_qcfg_output {
26322 /* The specific error status for the command. */
26323 uint16_t error_code;
26324 /* The HWRM command request type. */
26326 /* The sequence ID from the original command. */
26328 /* The length of the response data in number of bytes. */
26330 /* ID of CoS Queue 0. */
26335 * Minimum BW allocated to CoS Queue.
26336 * The HWRM will translate this value into byte counter and
26337 * time interval used for this COS inside the device.
26339 uint32_t queue_id0_min_bw;
26340 /* The bandwidth value. */
26341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
26342 UINT32_C(0xfffffff)
26343 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
26345 /* The granularity of the value (bits or bytes). */
26346 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
26347 UINT32_C(0x10000000)
26348 /* Value is in bits. */
26349 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
26350 (UINT32_C(0x0) << 28)
26351 /* Value is in bytes. */
26352 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
26353 (UINT32_C(0x1) << 28)
26354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
26355 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
26356 /* bw_value_unit is 3 b */
26357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
26358 UINT32_C(0xe0000000)
26359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
26361 /* Value is in Mb or MB (base 10). */
26362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
26363 (UINT32_C(0x0) << 29)
26364 /* Value is in Kb or KB (base 10). */
26365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
26366 (UINT32_C(0x2) << 29)
26367 /* Value is in bits or bytes. */
26368 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
26369 (UINT32_C(0x4) << 29)
26370 /* Value is in Gb or GB (base 10). */
26371 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
26372 (UINT32_C(0x6) << 29)
26373 /* Value is in 1/100th of a percentage of total bandwidth. */
26374 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26375 (UINT32_C(0x1) << 29)
26377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
26378 (UINT32_C(0x7) << 29)
26379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
26380 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
26382 * Maximum BW allocated to CoS Queue.
26383 * The HWRM will translate this value into byte counter and
26384 * time interval used for this COS inside the device.
26386 uint32_t queue_id0_max_bw;
26387 /* The bandwidth value. */
26388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
26389 UINT32_C(0xfffffff)
26390 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
26392 /* The granularity of the value (bits or bytes). */
26393 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
26394 UINT32_C(0x10000000)
26395 /* Value is in bits. */
26396 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
26397 (UINT32_C(0x0) << 28)
26398 /* Value is in bytes. */
26399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
26400 (UINT32_C(0x1) << 28)
26401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
26402 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
26403 /* bw_value_unit is 3 b */
26404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
26405 UINT32_C(0xe0000000)
26406 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
26408 /* Value is in Mb or MB (base 10). */
26409 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
26410 (UINT32_C(0x0) << 29)
26411 /* Value is in Kb or KB (base 10). */
26412 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
26413 (UINT32_C(0x2) << 29)
26414 /* Value is in bits or bytes. */
26415 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
26416 (UINT32_C(0x4) << 29)
26417 /* Value is in Gb or GB (base 10). */
26418 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
26419 (UINT32_C(0x6) << 29)
26420 /* Value is in 1/100th of a percentage of total bandwidth. */
26421 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26422 (UINT32_C(0x1) << 29)
26424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
26425 (UINT32_C(0x7) << 29)
26426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
26427 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
26428 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26429 uint8_t queue_id0_tsa_assign;
26430 /* Strict Priority */
26431 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
26433 /* Enhanced Transmission Selection */
26434 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
26437 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
26440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
26443 * Priority level for strict priority. Valid only when the
26444 * tsa_assign is 0 - Strict Priority (SP)
26445 * 0..7 - Valid values.
26446 * 8..255 - Reserved.
26448 uint8_t queue_id0_pri_lvl;
26450 * Weight used to allocate remaining BW for this COS after
26451 * servicing guaranteed bandwidths for all COS.
26453 uint8_t queue_id0_bw_weight;
26454 /* ID of CoS Queue 1. */
26457 * Minimum BW allocated to CoS Queue.
26458 * The HWRM will translate this value into byte counter and
26459 * time interval used for this COS inside the device.
26461 uint32_t queue_id1_min_bw;
26462 /* The bandwidth value. */
26463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
26464 UINT32_C(0xfffffff)
26465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
26467 /* The granularity of the value (bits or bytes). */
26468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
26469 UINT32_C(0x10000000)
26470 /* Value is in bits. */
26471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
26472 (UINT32_C(0x0) << 28)
26473 /* Value is in bytes. */
26474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
26475 (UINT32_C(0x1) << 28)
26476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
26477 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
26478 /* bw_value_unit is 3 b */
26479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
26480 UINT32_C(0xe0000000)
26481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
26483 /* Value is in Mb or MB (base 10). */
26484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
26485 (UINT32_C(0x0) << 29)
26486 /* Value is in Kb or KB (base 10). */
26487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
26488 (UINT32_C(0x2) << 29)
26489 /* Value is in bits or bytes. */
26490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
26491 (UINT32_C(0x4) << 29)
26492 /* Value is in Gb or GB (base 10). */
26493 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
26494 (UINT32_C(0x6) << 29)
26495 /* Value is in 1/100th of a percentage of total bandwidth. */
26496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26497 (UINT32_C(0x1) << 29)
26499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
26500 (UINT32_C(0x7) << 29)
26501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
26502 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
26504 * Maximum BW allocated to CoS queue.
26505 * The HWRM will translate this value into byte counter and
26506 * time interval used for this COS inside the device.
26508 uint32_t queue_id1_max_bw;
26509 /* The bandwidth value. */
26510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
26511 UINT32_C(0xfffffff)
26512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
26514 /* The granularity of the value (bits or bytes). */
26515 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
26516 UINT32_C(0x10000000)
26517 /* Value is in bits. */
26518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
26519 (UINT32_C(0x0) << 28)
26520 /* Value is in bytes. */
26521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
26522 (UINT32_C(0x1) << 28)
26523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
26524 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
26525 /* bw_value_unit is 3 b */
26526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
26527 UINT32_C(0xe0000000)
26528 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
26530 /* Value is in Mb or MB (base 10). */
26531 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
26532 (UINT32_C(0x0) << 29)
26533 /* Value is in Kb or KB (base 10). */
26534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
26535 (UINT32_C(0x2) << 29)
26536 /* Value is in bits or bytes. */
26537 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
26538 (UINT32_C(0x4) << 29)
26539 /* Value is in Gb or GB (base 10). */
26540 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
26541 (UINT32_C(0x6) << 29)
26542 /* Value is in 1/100th of a percentage of total bandwidth. */
26543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26544 (UINT32_C(0x1) << 29)
26546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
26547 (UINT32_C(0x7) << 29)
26548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
26549 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
26550 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26551 uint8_t queue_id1_tsa_assign;
26552 /* Strict Priority */
26553 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
26555 /* Enhanced Transmission Selection */
26556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
26559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
26562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
26565 * Priority level for strict priority. Valid only when the
26566 * tsa_assign is 0 - Strict Priority (SP)
26567 * 0..7 - Valid values.
26568 * 8..255 - Reserved.
26570 uint8_t queue_id1_pri_lvl;
26572 * Weight used to allocate remaining BW for this COS after
26573 * servicing guaranteed bandwidths for all COS.
26575 uint8_t queue_id1_bw_weight;
26576 /* ID of CoS Queue 2. */
26579 * Minimum BW allocated to CoS Queue.
26580 * The HWRM will translate this value into byte counter and
26581 * time interval used for this COS inside the device.
26583 uint32_t queue_id2_min_bw;
26584 /* The bandwidth value. */
26585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
26586 UINT32_C(0xfffffff)
26587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
26589 /* The granularity of the value (bits or bytes). */
26590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
26591 UINT32_C(0x10000000)
26592 /* Value is in bits. */
26593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
26594 (UINT32_C(0x0) << 28)
26595 /* Value is in bytes. */
26596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
26597 (UINT32_C(0x1) << 28)
26598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
26599 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
26600 /* bw_value_unit is 3 b */
26601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
26602 UINT32_C(0xe0000000)
26603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
26605 /* Value is in Mb or MB (base 10). */
26606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
26607 (UINT32_C(0x0) << 29)
26608 /* Value is in Kb or KB (base 10). */
26609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
26610 (UINT32_C(0x2) << 29)
26611 /* Value is in bits or bytes. */
26612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
26613 (UINT32_C(0x4) << 29)
26614 /* Value is in Gb or GB (base 10). */
26615 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
26616 (UINT32_C(0x6) << 29)
26617 /* Value is in 1/100th of a percentage of total bandwidth. */
26618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26619 (UINT32_C(0x1) << 29)
26621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
26622 (UINT32_C(0x7) << 29)
26623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
26624 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
26626 * Maximum BW allocated to CoS queue.
26627 * The HWRM will translate this value into byte counter and
26628 * time interval used for this COS inside the device.
26630 uint32_t queue_id2_max_bw;
26631 /* The bandwidth value. */
26632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
26633 UINT32_C(0xfffffff)
26634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
26636 /* The granularity of the value (bits or bytes). */
26637 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
26638 UINT32_C(0x10000000)
26639 /* Value is in bits. */
26640 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
26641 (UINT32_C(0x0) << 28)
26642 /* Value is in bytes. */
26643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
26644 (UINT32_C(0x1) << 28)
26645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
26646 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
26647 /* bw_value_unit is 3 b */
26648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
26649 UINT32_C(0xe0000000)
26650 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
26652 /* Value is in Mb or MB (base 10). */
26653 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
26654 (UINT32_C(0x0) << 29)
26655 /* Value is in Kb or KB (base 10). */
26656 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
26657 (UINT32_C(0x2) << 29)
26658 /* Value is in bits or bytes. */
26659 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
26660 (UINT32_C(0x4) << 29)
26661 /* Value is in Gb or GB (base 10). */
26662 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
26663 (UINT32_C(0x6) << 29)
26664 /* Value is in 1/100th of a percentage of total bandwidth. */
26665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26666 (UINT32_C(0x1) << 29)
26668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
26669 (UINT32_C(0x7) << 29)
26670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
26671 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
26672 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26673 uint8_t queue_id2_tsa_assign;
26674 /* Strict Priority */
26675 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
26677 /* Enhanced Transmission Selection */
26678 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
26681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
26684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
26687 * Priority level for strict priority. Valid only when the
26688 * tsa_assign is 0 - Strict Priority (SP)
26689 * 0..7 - Valid values.
26690 * 8..255 - Reserved.
26692 uint8_t queue_id2_pri_lvl;
26694 * Weight used to allocate remaining BW for this COS after
26695 * servicing guaranteed bandwidths for all COS.
26697 uint8_t queue_id2_bw_weight;
26698 /* ID of CoS Queue 3. */
26701 * Minimum BW allocated to CoS Queue.
26702 * The HWRM will translate this value into byte counter and
26703 * time interval used for this COS inside the device.
26705 uint32_t queue_id3_min_bw;
26706 /* The bandwidth value. */
26707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
26708 UINT32_C(0xfffffff)
26709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
26711 /* The granularity of the value (bits or bytes). */
26712 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
26713 UINT32_C(0x10000000)
26714 /* Value is in bits. */
26715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
26716 (UINT32_C(0x0) << 28)
26717 /* Value is in bytes. */
26718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
26719 (UINT32_C(0x1) << 28)
26720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
26721 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
26722 /* bw_value_unit is 3 b */
26723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
26724 UINT32_C(0xe0000000)
26725 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
26727 /* Value is in Mb or MB (base 10). */
26728 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
26729 (UINT32_C(0x0) << 29)
26730 /* Value is in Kb or KB (base 10). */
26731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
26732 (UINT32_C(0x2) << 29)
26733 /* Value is in bits or bytes. */
26734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
26735 (UINT32_C(0x4) << 29)
26736 /* Value is in Gb or GB (base 10). */
26737 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
26738 (UINT32_C(0x6) << 29)
26739 /* Value is in 1/100th of a percentage of total bandwidth. */
26740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26741 (UINT32_C(0x1) << 29)
26743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
26744 (UINT32_C(0x7) << 29)
26745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
26746 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
26748 * Maximum BW allocated to CoS queue.
26749 * The HWRM will translate this value into byte counter and
26750 * time interval used for this COS inside the device.
26752 uint32_t queue_id3_max_bw;
26753 /* The bandwidth value. */
26754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
26755 UINT32_C(0xfffffff)
26756 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
26758 /* The granularity of the value (bits or bytes). */
26759 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
26760 UINT32_C(0x10000000)
26761 /* Value is in bits. */
26762 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
26763 (UINT32_C(0x0) << 28)
26764 /* Value is in bytes. */
26765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
26766 (UINT32_C(0x1) << 28)
26767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
26768 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
26769 /* bw_value_unit is 3 b */
26770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
26771 UINT32_C(0xe0000000)
26772 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
26774 /* Value is in Mb or MB (base 10). */
26775 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
26776 (UINT32_C(0x0) << 29)
26777 /* Value is in Kb or KB (base 10). */
26778 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
26779 (UINT32_C(0x2) << 29)
26780 /* Value is in bits or bytes. */
26781 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
26782 (UINT32_C(0x4) << 29)
26783 /* Value is in Gb or GB (base 10). */
26784 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
26785 (UINT32_C(0x6) << 29)
26786 /* Value is in 1/100th of a percentage of total bandwidth. */
26787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26788 (UINT32_C(0x1) << 29)
26790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
26791 (UINT32_C(0x7) << 29)
26792 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
26793 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
26794 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26795 uint8_t queue_id3_tsa_assign;
26796 /* Strict Priority */
26797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
26799 /* Enhanced Transmission Selection */
26800 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
26803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
26806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
26809 * Priority level for strict priority. Valid only when the
26810 * tsa_assign is 0 - Strict Priority (SP)
26811 * 0..7 - Valid values.
26812 * 8..255 - Reserved.
26814 uint8_t queue_id3_pri_lvl;
26816 * Weight used to allocate remaining BW for this COS after
26817 * servicing guaranteed bandwidths for all COS.
26819 uint8_t queue_id3_bw_weight;
26820 /* ID of CoS Queue 4. */
26823 * Minimum BW allocated to CoS Queue.
26824 * The HWRM will translate this value into byte counter and
26825 * time interval used for this COS inside the device.
26827 uint32_t queue_id4_min_bw;
26828 /* The bandwidth value. */
26829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
26830 UINT32_C(0xfffffff)
26831 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
26833 /* The granularity of the value (bits or bytes). */
26834 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
26835 UINT32_C(0x10000000)
26836 /* Value is in bits. */
26837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
26838 (UINT32_C(0x0) << 28)
26839 /* Value is in bytes. */
26840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
26841 (UINT32_C(0x1) << 28)
26842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
26843 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
26844 /* bw_value_unit is 3 b */
26845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
26846 UINT32_C(0xe0000000)
26847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
26849 /* Value is in Mb or MB (base 10). */
26850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
26851 (UINT32_C(0x0) << 29)
26852 /* Value is in Kb or KB (base 10). */
26853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
26854 (UINT32_C(0x2) << 29)
26855 /* Value is in bits or bytes. */
26856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
26857 (UINT32_C(0x4) << 29)
26858 /* Value is in Gb or GB (base 10). */
26859 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
26860 (UINT32_C(0x6) << 29)
26861 /* Value is in 1/100th of a percentage of total bandwidth. */
26862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26863 (UINT32_C(0x1) << 29)
26865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
26866 (UINT32_C(0x7) << 29)
26867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
26868 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
26870 * Maximum BW allocated to CoS queue.
26871 * The HWRM will translate this value into byte counter and
26872 * time interval used for this COS inside the device.
26874 uint32_t queue_id4_max_bw;
26875 /* The bandwidth value. */
26876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
26877 UINT32_C(0xfffffff)
26878 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
26880 /* The granularity of the value (bits or bytes). */
26881 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
26882 UINT32_C(0x10000000)
26883 /* Value is in bits. */
26884 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
26885 (UINT32_C(0x0) << 28)
26886 /* Value is in bytes. */
26887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
26888 (UINT32_C(0x1) << 28)
26889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
26890 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
26891 /* bw_value_unit is 3 b */
26892 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
26893 UINT32_C(0xe0000000)
26894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
26896 /* Value is in Mb or MB (base 10). */
26897 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
26898 (UINT32_C(0x0) << 29)
26899 /* Value is in Kb or KB (base 10). */
26900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
26901 (UINT32_C(0x2) << 29)
26902 /* Value is in bits or bytes. */
26903 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
26904 (UINT32_C(0x4) << 29)
26905 /* Value is in Gb or GB (base 10). */
26906 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
26907 (UINT32_C(0x6) << 29)
26908 /* Value is in 1/100th of a percentage of total bandwidth. */
26909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
26910 (UINT32_C(0x1) << 29)
26912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
26913 (UINT32_C(0x7) << 29)
26914 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
26915 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
26916 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
26917 uint8_t queue_id4_tsa_assign;
26918 /* Strict Priority */
26919 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
26921 /* Enhanced Transmission Selection */
26922 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
26925 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
26928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
26931 * Priority level for strict priority. Valid only when the
26932 * tsa_assign is 0 - Strict Priority (SP)
26933 * 0..7 - Valid values.
26934 * 8..255 - Reserved.
26936 uint8_t queue_id4_pri_lvl;
26938 * Weight used to allocate remaining BW for this COS after
26939 * servicing guaranteed bandwidths for all COS.
26941 uint8_t queue_id4_bw_weight;
26942 /* ID of CoS Queue 5. */
26945 * Minimum BW allocated to CoS Queue.
26946 * The HWRM will translate this value into byte counter and
26947 * time interval used for this COS inside the device.
26949 uint32_t queue_id5_min_bw;
26950 /* The bandwidth value. */
26951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
26952 UINT32_C(0xfffffff)
26953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
26955 /* The granularity of the value (bits or bytes). */
26956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
26957 UINT32_C(0x10000000)
26958 /* Value is in bits. */
26959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
26960 (UINT32_C(0x0) << 28)
26961 /* Value is in bytes. */
26962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
26963 (UINT32_C(0x1) << 28)
26964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
26965 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
26966 /* bw_value_unit is 3 b */
26967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
26968 UINT32_C(0xe0000000)
26969 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
26971 /* Value is in Mb or MB (base 10). */
26972 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
26973 (UINT32_C(0x0) << 29)
26974 /* Value is in Kb or KB (base 10). */
26975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
26976 (UINT32_C(0x2) << 29)
26977 /* Value is in bits or bytes. */
26978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
26979 (UINT32_C(0x4) << 29)
26980 /* Value is in Gb or GB (base 10). */
26981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
26982 (UINT32_C(0x6) << 29)
26983 /* Value is in 1/100th of a percentage of total bandwidth. */
26984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
26985 (UINT32_C(0x1) << 29)
26987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
26988 (UINT32_C(0x7) << 29)
26989 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
26990 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
26992 * Maximum BW allocated to CoS queue.
26993 * The HWRM will translate this value into byte counter and
26994 * time interval used for this COS inside the device.
26996 uint32_t queue_id5_max_bw;
26997 /* The bandwidth value. */
26998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
26999 UINT32_C(0xfffffff)
27000 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
27002 /* The granularity of the value (bits or bytes). */
27003 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
27004 UINT32_C(0x10000000)
27005 /* Value is in bits. */
27006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
27007 (UINT32_C(0x0) << 28)
27008 /* Value is in bytes. */
27009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
27010 (UINT32_C(0x1) << 28)
27011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
27012 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
27013 /* bw_value_unit is 3 b */
27014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
27015 UINT32_C(0xe0000000)
27016 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
27018 /* Value is in Mb or MB (base 10). */
27019 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
27020 (UINT32_C(0x0) << 29)
27021 /* Value is in Kb or KB (base 10). */
27022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
27023 (UINT32_C(0x2) << 29)
27024 /* Value is in bits or bytes. */
27025 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
27026 (UINT32_C(0x4) << 29)
27027 /* Value is in Gb or GB (base 10). */
27028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
27029 (UINT32_C(0x6) << 29)
27030 /* Value is in 1/100th of a percentage of total bandwidth. */
27031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27032 (UINT32_C(0x1) << 29)
27034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
27035 (UINT32_C(0x7) << 29)
27036 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
27037 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
27038 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27039 uint8_t queue_id5_tsa_assign;
27040 /* Strict Priority */
27041 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
27043 /* Enhanced Transmission Selection */
27044 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
27047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
27050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
27053 * Priority level for strict priority. Valid only when the
27054 * tsa_assign is 0 - Strict Priority (SP)
27055 * 0..7 - Valid values.
27056 * 8..255 - Reserved.
27058 uint8_t queue_id5_pri_lvl;
27060 * Weight used to allocate remaining BW for this COS after
27061 * servicing guaranteed bandwidths for all COS.
27063 uint8_t queue_id5_bw_weight;
27064 /* ID of CoS Queue 6. */
27067 * Minimum BW allocated to CoS Queue.
27068 * The HWRM will translate this value into byte counter and
27069 * time interval used for this COS inside the device.
27071 uint32_t queue_id6_min_bw;
27072 /* The bandwidth value. */
27073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
27074 UINT32_C(0xfffffff)
27075 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
27077 /* The granularity of the value (bits or bytes). */
27078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
27079 UINT32_C(0x10000000)
27080 /* Value is in bits. */
27081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
27082 (UINT32_C(0x0) << 28)
27083 /* Value is in bytes. */
27084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
27085 (UINT32_C(0x1) << 28)
27086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
27087 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
27088 /* bw_value_unit is 3 b */
27089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
27090 UINT32_C(0xe0000000)
27091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
27093 /* Value is in Mb or MB (base 10). */
27094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
27095 (UINT32_C(0x0) << 29)
27096 /* Value is in Kb or KB (base 10). */
27097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
27098 (UINT32_C(0x2) << 29)
27099 /* Value is in bits or bytes. */
27100 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
27101 (UINT32_C(0x4) << 29)
27102 /* Value is in Gb or GB (base 10). */
27103 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
27104 (UINT32_C(0x6) << 29)
27105 /* Value is in 1/100th of a percentage of total bandwidth. */
27106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27107 (UINT32_C(0x1) << 29)
27109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
27110 (UINT32_C(0x7) << 29)
27111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
27112 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
27114 * Maximum BW allocated to CoS queue.
27115 * The HWRM will translate this value into byte counter and
27116 * time interval used for this COS inside the device.
27118 uint32_t queue_id6_max_bw;
27119 /* The bandwidth value. */
27120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
27121 UINT32_C(0xfffffff)
27122 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
27124 /* The granularity of the value (bits or bytes). */
27125 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
27126 UINT32_C(0x10000000)
27127 /* Value is in bits. */
27128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
27129 (UINT32_C(0x0) << 28)
27130 /* Value is in bytes. */
27131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
27132 (UINT32_C(0x1) << 28)
27133 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
27134 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
27135 /* bw_value_unit is 3 b */
27136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
27137 UINT32_C(0xe0000000)
27138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
27140 /* Value is in Mb or MB (base 10). */
27141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
27142 (UINT32_C(0x0) << 29)
27143 /* Value is in Kb or KB (base 10). */
27144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
27145 (UINT32_C(0x2) << 29)
27146 /* Value is in bits or bytes. */
27147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
27148 (UINT32_C(0x4) << 29)
27149 /* Value is in Gb or GB (base 10). */
27150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
27151 (UINT32_C(0x6) << 29)
27152 /* Value is in 1/100th of a percentage of total bandwidth. */
27153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27154 (UINT32_C(0x1) << 29)
27156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
27157 (UINT32_C(0x7) << 29)
27158 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
27159 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
27160 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27161 uint8_t queue_id6_tsa_assign;
27162 /* Strict Priority */
27163 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
27165 /* Enhanced Transmission Selection */
27166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
27169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
27172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
27175 * Priority level for strict priority. Valid only when the
27176 * tsa_assign is 0 - Strict Priority (SP)
27177 * 0..7 - Valid values.
27178 * 8..255 - Reserved.
27180 uint8_t queue_id6_pri_lvl;
27182 * Weight used to allocate remaining BW for this COS after
27183 * servicing guaranteed bandwidths for all COS.
27185 uint8_t queue_id6_bw_weight;
27186 /* ID of CoS Queue 7. */
27189 * Minimum BW allocated to CoS Queue.
27190 * The HWRM will translate this value into byte counter and
27191 * time interval used for this COS inside the device.
27193 uint32_t queue_id7_min_bw;
27194 /* The bandwidth value. */
27195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
27196 UINT32_C(0xfffffff)
27197 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
27199 /* The granularity of the value (bits or bytes). */
27200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
27201 UINT32_C(0x10000000)
27202 /* Value is in bits. */
27203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
27204 (UINT32_C(0x0) << 28)
27205 /* Value is in bytes. */
27206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
27207 (UINT32_C(0x1) << 28)
27208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
27209 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
27210 /* bw_value_unit is 3 b */
27211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
27212 UINT32_C(0xe0000000)
27213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
27215 /* Value is in Mb or MB (base 10). */
27216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
27217 (UINT32_C(0x0) << 29)
27218 /* Value is in Kb or KB (base 10). */
27219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
27220 (UINT32_C(0x2) << 29)
27221 /* Value is in bits or bytes. */
27222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
27223 (UINT32_C(0x4) << 29)
27224 /* Value is in Gb or GB (base 10). */
27225 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
27226 (UINT32_C(0x6) << 29)
27227 /* Value is in 1/100th of a percentage of total bandwidth. */
27228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27229 (UINT32_C(0x1) << 29)
27231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
27232 (UINT32_C(0x7) << 29)
27233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
27234 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
27236 * Maximum BW allocated to CoS queue.
27237 * The HWRM will translate this value into byte counter and
27238 * time interval used for this COS inside the device.
27240 uint32_t queue_id7_max_bw;
27241 /* The bandwidth value. */
27242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
27243 UINT32_C(0xfffffff)
27244 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
27246 /* The granularity of the value (bits or bytes). */
27247 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
27248 UINT32_C(0x10000000)
27249 /* Value is in bits. */
27250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
27251 (UINT32_C(0x0) << 28)
27252 /* Value is in bytes. */
27253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
27254 (UINT32_C(0x1) << 28)
27255 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
27256 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
27257 /* bw_value_unit is 3 b */
27258 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
27259 UINT32_C(0xe0000000)
27260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
27262 /* Value is in Mb or MB (base 10). */
27263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
27264 (UINT32_C(0x0) << 29)
27265 /* Value is in Kb or KB (base 10). */
27266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
27267 (UINT32_C(0x2) << 29)
27268 /* Value is in bits or bytes. */
27269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
27270 (UINT32_C(0x4) << 29)
27271 /* Value is in Gb or GB (base 10). */
27272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
27273 (UINT32_C(0x6) << 29)
27274 /* Value is in 1/100th of a percentage of total bandwidth. */
27275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27276 (UINT32_C(0x1) << 29)
27278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
27279 (UINT32_C(0x7) << 29)
27280 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
27281 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
27282 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27283 uint8_t queue_id7_tsa_assign;
27284 /* Strict Priority */
27285 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
27287 /* Enhanced Transmission Selection */
27288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
27291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
27294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
27297 * Priority level for strict priority. Valid only when the
27298 * tsa_assign is 0 - Strict Priority (SP)
27299 * 0..7 - Valid values.
27300 * 8..255 - Reserved.
27302 uint8_t queue_id7_pri_lvl;
27304 * Weight used to allocate remaining BW for this COS after
27305 * servicing guaranteed bandwidths for all COS.
27307 uint8_t queue_id7_bw_weight;
27308 uint8_t unused_2[4];
27310 * This field is used in Output records to indicate that the output
27311 * is completely written to RAM. This field should be read as '1'
27312 * to indicate that the output has been completely written.
27313 * When writing a command completion or response to an internal processor,
27314 * the order of writes has to be such that this field is written last.
27319 /*************************
27320 * hwrm_queue_cos2bw_cfg *
27321 *************************/
27324 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
27325 struct hwrm_queue_cos2bw_cfg_input {
27326 /* The HWRM command request type. */
27329 * The completion ring to send the completion event on. This should
27330 * be the NQ ID returned from the `nq_alloc` HWRM command.
27332 uint16_t cmpl_ring;
27334 * The sequence ID is used by the driver for tracking multiple
27335 * commands. This ID is treated as opaque data by the firmware and
27336 * the value is returned in the `hwrm_resp_hdr` upon completion.
27340 * The target ID of the command:
27341 * * 0x0-0xFFF8 - The function ID
27342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27343 * * 0xFFFD - Reserved for user-space HWRM interface
27346 uint16_t target_id;
27348 * A physical address pointer pointing to a host buffer that the
27349 * command's response data will be written. This can be either a host
27350 * physical address (HPA) or a guest physical address (GPA) and must
27351 * point to a physically contiguous block of memory.
27353 uint64_t resp_addr;
27357 * If this bit is set to 1, then all queue_id0 related
27358 * parameters in this command are valid.
27360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
27363 * If this bit is set to 1, then all queue_id1 related
27364 * parameters in this command are valid.
27366 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
27369 * If this bit is set to 1, then all queue_id2 related
27370 * parameters in this command are valid.
27372 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
27375 * If this bit is set to 1, then all queue_id3 related
27376 * parameters in this command are valid.
27378 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
27381 * If this bit is set to 1, then all queue_id4 related
27382 * parameters in this command are valid.
27384 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
27387 * If this bit is set to 1, then all queue_id5 related
27388 * parameters in this command are valid.
27390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
27393 * If this bit is set to 1, then all queue_id6 related
27394 * parameters in this command are valid.
27396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
27399 * If this bit is set to 1, then all queue_id7 related
27400 * parameters in this command are valid.
27402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
27405 * Port ID of port for which the table is being configured.
27406 * The HWRM needs to check whether this function is allowed
27407 * to configure TC BW assignment on this port.
27410 /* ID of CoS Queue 0. */
27414 * Minimum BW allocated to CoS Queue.
27415 * The HWRM will translate this value into byte counter and
27416 * time interval used for this COS inside the device.
27418 uint32_t queue_id0_min_bw;
27419 /* The bandwidth value. */
27420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
27421 UINT32_C(0xfffffff)
27422 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
27424 /* The granularity of the value (bits or bytes). */
27425 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
27426 UINT32_C(0x10000000)
27427 /* Value is in bits. */
27428 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
27429 (UINT32_C(0x0) << 28)
27430 /* Value is in bytes. */
27431 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
27432 (UINT32_C(0x1) << 28)
27433 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
27434 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
27435 /* bw_value_unit is 3 b */
27436 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
27437 UINT32_C(0xe0000000)
27438 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
27440 /* Value is in Mb or MB (base 10). */
27441 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
27442 (UINT32_C(0x0) << 29)
27443 /* Value is in Kb or KB (base 10). */
27444 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
27445 (UINT32_C(0x2) << 29)
27446 /* Value is in bits or bytes. */
27447 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
27448 (UINT32_C(0x4) << 29)
27449 /* Value is in Gb or GB (base 10). */
27450 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
27451 (UINT32_C(0x6) << 29)
27452 /* Value is in 1/100th of a percentage of total bandwidth. */
27453 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27454 (UINT32_C(0x1) << 29)
27456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
27457 (UINT32_C(0x7) << 29)
27458 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
27459 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
27461 * Maximum BW allocated to CoS Queue.
27462 * The HWRM will translate this value into byte counter and
27463 * time interval used for this COS inside the device.
27465 uint32_t queue_id0_max_bw;
27466 /* The bandwidth value. */
27467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
27468 UINT32_C(0xfffffff)
27469 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
27471 /* The granularity of the value (bits or bytes). */
27472 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
27473 UINT32_C(0x10000000)
27474 /* Value is in bits. */
27475 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
27476 (UINT32_C(0x0) << 28)
27477 /* Value is in bytes. */
27478 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
27479 (UINT32_C(0x1) << 28)
27480 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
27481 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
27482 /* bw_value_unit is 3 b */
27483 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
27484 UINT32_C(0xe0000000)
27485 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
27487 /* Value is in Mb or MB (base 10). */
27488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
27489 (UINT32_C(0x0) << 29)
27490 /* Value is in Kb or KB (base 10). */
27491 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
27492 (UINT32_C(0x2) << 29)
27493 /* Value is in bits or bytes. */
27494 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
27495 (UINT32_C(0x4) << 29)
27496 /* Value is in Gb or GB (base 10). */
27497 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
27498 (UINT32_C(0x6) << 29)
27499 /* Value is in 1/100th of a percentage of total bandwidth. */
27500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27501 (UINT32_C(0x1) << 29)
27503 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
27504 (UINT32_C(0x7) << 29)
27505 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
27506 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
27507 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27508 uint8_t queue_id0_tsa_assign;
27509 /* Strict Priority */
27510 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
27512 /* Enhanced Transmission Selection */
27513 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
27516 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
27519 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
27522 * Priority level for strict priority. Valid only when the
27523 * tsa_assign is 0 - Strict Priority (SP)
27524 * 0..7 - Valid values.
27525 * 8..255 - Reserved.
27527 uint8_t queue_id0_pri_lvl;
27529 * Weight used to allocate remaining BW for this COS after
27530 * servicing guaranteed bandwidths for all COS.
27532 uint8_t queue_id0_bw_weight;
27533 /* ID of CoS Queue 1. */
27536 * Minimum BW allocated to CoS Queue.
27537 * The HWRM will translate this value into byte counter and
27538 * time interval used for this COS inside the device.
27540 uint32_t queue_id1_min_bw;
27541 /* The bandwidth value. */
27542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
27543 UINT32_C(0xfffffff)
27544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
27546 /* The granularity of the value (bits or bytes). */
27547 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
27548 UINT32_C(0x10000000)
27549 /* Value is in bits. */
27550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
27551 (UINT32_C(0x0) << 28)
27552 /* Value is in bytes. */
27553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
27554 (UINT32_C(0x1) << 28)
27555 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
27556 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
27557 /* bw_value_unit is 3 b */
27558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
27559 UINT32_C(0xe0000000)
27560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
27562 /* Value is in Mb or MB (base 10). */
27563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
27564 (UINT32_C(0x0) << 29)
27565 /* Value is in Kb or KB (base 10). */
27566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
27567 (UINT32_C(0x2) << 29)
27568 /* Value is in bits or bytes. */
27569 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
27570 (UINT32_C(0x4) << 29)
27571 /* Value is in Gb or GB (base 10). */
27572 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
27573 (UINT32_C(0x6) << 29)
27574 /* Value is in 1/100th of a percentage of total bandwidth. */
27575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27576 (UINT32_C(0x1) << 29)
27578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
27579 (UINT32_C(0x7) << 29)
27580 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
27581 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
27583 * Maximum BW allocated to CoS queue.
27584 * The HWRM will translate this value into byte counter and
27585 * time interval used for this COS inside the device.
27587 uint32_t queue_id1_max_bw;
27588 /* The bandwidth value. */
27589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
27590 UINT32_C(0xfffffff)
27591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
27593 /* The granularity of the value (bits or bytes). */
27594 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
27595 UINT32_C(0x10000000)
27596 /* Value is in bits. */
27597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
27598 (UINT32_C(0x0) << 28)
27599 /* Value is in bytes. */
27600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
27601 (UINT32_C(0x1) << 28)
27602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
27603 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
27604 /* bw_value_unit is 3 b */
27605 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
27606 UINT32_C(0xe0000000)
27607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
27609 /* Value is in Mb or MB (base 10). */
27610 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
27611 (UINT32_C(0x0) << 29)
27612 /* Value is in Kb or KB (base 10). */
27613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
27614 (UINT32_C(0x2) << 29)
27615 /* Value is in bits or bytes. */
27616 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
27617 (UINT32_C(0x4) << 29)
27618 /* Value is in Gb or GB (base 10). */
27619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
27620 (UINT32_C(0x6) << 29)
27621 /* Value is in 1/100th of a percentage of total bandwidth. */
27622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27623 (UINT32_C(0x1) << 29)
27625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
27626 (UINT32_C(0x7) << 29)
27627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
27628 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
27629 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27630 uint8_t queue_id1_tsa_assign;
27631 /* Strict Priority */
27632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
27634 /* Enhanced Transmission Selection */
27635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
27638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
27641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
27644 * Priority level for strict priority. Valid only when the
27645 * tsa_assign is 0 - Strict Priority (SP)
27646 * 0..7 - Valid values.
27647 * 8..255 - Reserved.
27649 uint8_t queue_id1_pri_lvl;
27651 * Weight used to allocate remaining BW for this COS after
27652 * servicing guaranteed bandwidths for all COS.
27654 uint8_t queue_id1_bw_weight;
27655 /* ID of CoS Queue 2. */
27658 * Minimum BW allocated to CoS Queue.
27659 * The HWRM will translate this value into byte counter and
27660 * time interval used for this COS inside the device.
27662 uint32_t queue_id2_min_bw;
27663 /* The bandwidth value. */
27664 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
27665 UINT32_C(0xfffffff)
27666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
27668 /* The granularity of the value (bits or bytes). */
27669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
27670 UINT32_C(0x10000000)
27671 /* Value is in bits. */
27672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
27673 (UINT32_C(0x0) << 28)
27674 /* Value is in bytes. */
27675 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
27676 (UINT32_C(0x1) << 28)
27677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
27678 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
27679 /* bw_value_unit is 3 b */
27680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
27681 UINT32_C(0xe0000000)
27682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
27684 /* Value is in Mb or MB (base 10). */
27685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
27686 (UINT32_C(0x0) << 29)
27687 /* Value is in Kb or KB (base 10). */
27688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
27689 (UINT32_C(0x2) << 29)
27690 /* Value is in bits or bytes. */
27691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
27692 (UINT32_C(0x4) << 29)
27693 /* Value is in Gb or GB (base 10). */
27694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
27695 (UINT32_C(0x6) << 29)
27696 /* Value is in 1/100th of a percentage of total bandwidth. */
27697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27698 (UINT32_C(0x1) << 29)
27700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
27701 (UINT32_C(0x7) << 29)
27702 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
27703 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
27705 * Maximum BW allocated to CoS queue.
27706 * The HWRM will translate this value into byte counter and
27707 * time interval used for this COS inside the device.
27709 uint32_t queue_id2_max_bw;
27710 /* The bandwidth value. */
27711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
27712 UINT32_C(0xfffffff)
27713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
27715 /* The granularity of the value (bits or bytes). */
27716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
27717 UINT32_C(0x10000000)
27718 /* Value is in bits. */
27719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
27720 (UINT32_C(0x0) << 28)
27721 /* Value is in bytes. */
27722 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
27723 (UINT32_C(0x1) << 28)
27724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
27725 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
27726 /* bw_value_unit is 3 b */
27727 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
27728 UINT32_C(0xe0000000)
27729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
27731 /* Value is in Mb or MB (base 10). */
27732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
27733 (UINT32_C(0x0) << 29)
27734 /* Value is in Kb or KB (base 10). */
27735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
27736 (UINT32_C(0x2) << 29)
27737 /* Value is in bits or bytes. */
27738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
27739 (UINT32_C(0x4) << 29)
27740 /* Value is in Gb or GB (base 10). */
27741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
27742 (UINT32_C(0x6) << 29)
27743 /* Value is in 1/100th of a percentage of total bandwidth. */
27744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27745 (UINT32_C(0x1) << 29)
27747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
27748 (UINT32_C(0x7) << 29)
27749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
27750 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
27751 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27752 uint8_t queue_id2_tsa_assign;
27753 /* Strict Priority */
27754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
27756 /* Enhanced Transmission Selection */
27757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
27760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
27763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
27766 * Priority level for strict priority. Valid only when the
27767 * tsa_assign is 0 - Strict Priority (SP)
27768 * 0..7 - Valid values.
27769 * 8..255 - Reserved.
27771 uint8_t queue_id2_pri_lvl;
27773 * Weight used to allocate remaining BW for this COS after
27774 * servicing guaranteed bandwidths for all COS.
27776 uint8_t queue_id2_bw_weight;
27777 /* ID of CoS Queue 3. */
27780 * Minimum BW allocated to CoS Queue.
27781 * The HWRM will translate this value into byte counter and
27782 * time interval used for this COS inside the device.
27784 uint32_t queue_id3_min_bw;
27785 /* The bandwidth value. */
27786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
27787 UINT32_C(0xfffffff)
27788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
27790 /* The granularity of the value (bits or bytes). */
27791 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
27792 UINT32_C(0x10000000)
27793 /* Value is in bits. */
27794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
27795 (UINT32_C(0x0) << 28)
27796 /* Value is in bytes. */
27797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
27798 (UINT32_C(0x1) << 28)
27799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
27800 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
27801 /* bw_value_unit is 3 b */
27802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
27803 UINT32_C(0xe0000000)
27804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
27806 /* Value is in Mb or MB (base 10). */
27807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
27808 (UINT32_C(0x0) << 29)
27809 /* Value is in Kb or KB (base 10). */
27810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
27811 (UINT32_C(0x2) << 29)
27812 /* Value is in bits or bytes. */
27813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
27814 (UINT32_C(0x4) << 29)
27815 /* Value is in Gb or GB (base 10). */
27816 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
27817 (UINT32_C(0x6) << 29)
27818 /* Value is in 1/100th of a percentage of total bandwidth. */
27819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27820 (UINT32_C(0x1) << 29)
27822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
27823 (UINT32_C(0x7) << 29)
27824 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
27825 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
27827 * Maximum BW allocated to CoS queue.
27828 * The HWRM will translate this value into byte counter and
27829 * time interval used for this COS inside the device.
27831 uint32_t queue_id3_max_bw;
27832 /* The bandwidth value. */
27833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
27834 UINT32_C(0xfffffff)
27835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
27837 /* The granularity of the value (bits or bytes). */
27838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
27839 UINT32_C(0x10000000)
27840 /* Value is in bits. */
27841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
27842 (UINT32_C(0x0) << 28)
27843 /* Value is in bytes. */
27844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
27845 (UINT32_C(0x1) << 28)
27846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
27847 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
27848 /* bw_value_unit is 3 b */
27849 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
27850 UINT32_C(0xe0000000)
27851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
27853 /* Value is in Mb or MB (base 10). */
27854 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
27855 (UINT32_C(0x0) << 29)
27856 /* Value is in Kb or KB (base 10). */
27857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
27858 (UINT32_C(0x2) << 29)
27859 /* Value is in bits or bytes. */
27860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
27861 (UINT32_C(0x4) << 29)
27862 /* Value is in Gb or GB (base 10). */
27863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
27864 (UINT32_C(0x6) << 29)
27865 /* Value is in 1/100th of a percentage of total bandwidth. */
27866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27867 (UINT32_C(0x1) << 29)
27869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
27870 (UINT32_C(0x7) << 29)
27871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
27872 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
27873 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27874 uint8_t queue_id3_tsa_assign;
27875 /* Strict Priority */
27876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
27878 /* Enhanced Transmission Selection */
27879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
27882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
27885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
27888 * Priority level for strict priority. Valid only when the
27889 * tsa_assign is 0 - Strict Priority (SP)
27890 * 0..7 - Valid values.
27891 * 8..255 - Reserved.
27893 uint8_t queue_id3_pri_lvl;
27895 * Weight used to allocate remaining BW for this COS after
27896 * servicing guaranteed bandwidths for all COS.
27898 uint8_t queue_id3_bw_weight;
27899 /* ID of CoS Queue 4. */
27902 * Minimum BW allocated to CoS Queue.
27903 * The HWRM will translate this value into byte counter and
27904 * time interval used for this COS inside the device.
27906 uint32_t queue_id4_min_bw;
27907 /* The bandwidth value. */
27908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
27909 UINT32_C(0xfffffff)
27910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
27912 /* The granularity of the value (bits or bytes). */
27913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
27914 UINT32_C(0x10000000)
27915 /* Value is in bits. */
27916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
27917 (UINT32_C(0x0) << 28)
27918 /* Value is in bytes. */
27919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
27920 (UINT32_C(0x1) << 28)
27921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
27922 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
27923 /* bw_value_unit is 3 b */
27924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
27925 UINT32_C(0xe0000000)
27926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
27928 /* Value is in Mb or MB (base 10). */
27929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
27930 (UINT32_C(0x0) << 29)
27931 /* Value is in Kb or KB (base 10). */
27932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
27933 (UINT32_C(0x2) << 29)
27934 /* Value is in bits or bytes. */
27935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
27936 (UINT32_C(0x4) << 29)
27937 /* Value is in Gb or GB (base 10). */
27938 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
27939 (UINT32_C(0x6) << 29)
27940 /* Value is in 1/100th of a percentage of total bandwidth. */
27941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
27942 (UINT32_C(0x1) << 29)
27944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
27945 (UINT32_C(0x7) << 29)
27946 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
27947 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
27949 * Maximum BW allocated to CoS queue.
27950 * The HWRM will translate this value into byte counter and
27951 * time interval used for this COS inside the device.
27953 uint32_t queue_id4_max_bw;
27954 /* The bandwidth value. */
27955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
27956 UINT32_C(0xfffffff)
27957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
27959 /* The granularity of the value (bits or bytes). */
27960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
27961 UINT32_C(0x10000000)
27962 /* Value is in bits. */
27963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
27964 (UINT32_C(0x0) << 28)
27965 /* Value is in bytes. */
27966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
27967 (UINT32_C(0x1) << 28)
27968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
27969 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
27970 /* bw_value_unit is 3 b */
27971 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
27972 UINT32_C(0xe0000000)
27973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
27975 /* Value is in Mb or MB (base 10). */
27976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
27977 (UINT32_C(0x0) << 29)
27978 /* Value is in Kb or KB (base 10). */
27979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
27980 (UINT32_C(0x2) << 29)
27981 /* Value is in bits or bytes. */
27982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
27983 (UINT32_C(0x4) << 29)
27984 /* Value is in Gb or GB (base 10). */
27985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
27986 (UINT32_C(0x6) << 29)
27987 /* Value is in 1/100th of a percentage of total bandwidth. */
27988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27989 (UINT32_C(0x1) << 29)
27991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
27992 (UINT32_C(0x7) << 29)
27993 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
27994 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
27995 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
27996 uint8_t queue_id4_tsa_assign;
27997 /* Strict Priority */
27998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
28000 /* Enhanced Transmission Selection */
28001 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
28004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
28007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
28010 * Priority level for strict priority. Valid only when the
28011 * tsa_assign is 0 - Strict Priority (SP)
28012 * 0..7 - Valid values.
28013 * 8..255 - Reserved.
28015 uint8_t queue_id4_pri_lvl;
28017 * Weight used to allocate remaining BW for this COS after
28018 * servicing guaranteed bandwidths for all COS.
28020 uint8_t queue_id4_bw_weight;
28021 /* ID of CoS Queue 5. */
28024 * Minimum BW allocated to CoS Queue.
28025 * The HWRM will translate this value into byte counter and
28026 * time interval used for this COS inside the device.
28028 uint32_t queue_id5_min_bw;
28029 /* The bandwidth value. */
28030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
28031 UINT32_C(0xfffffff)
28032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
28034 /* The granularity of the value (bits or bytes). */
28035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
28036 UINT32_C(0x10000000)
28037 /* Value is in bits. */
28038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
28039 (UINT32_C(0x0) << 28)
28040 /* Value is in bytes. */
28041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
28042 (UINT32_C(0x1) << 28)
28043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
28044 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
28045 /* bw_value_unit is 3 b */
28046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
28047 UINT32_C(0xe0000000)
28048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
28050 /* Value is in Mb or MB (base 10). */
28051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
28052 (UINT32_C(0x0) << 29)
28053 /* Value is in Kb or KB (base 10). */
28054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
28055 (UINT32_C(0x2) << 29)
28056 /* Value is in bits or bytes. */
28057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
28058 (UINT32_C(0x4) << 29)
28059 /* Value is in Gb or GB (base 10). */
28060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
28061 (UINT32_C(0x6) << 29)
28062 /* Value is in 1/100th of a percentage of total bandwidth. */
28063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28064 (UINT32_C(0x1) << 29)
28066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
28067 (UINT32_C(0x7) << 29)
28068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
28069 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
28071 * Maximum BW allocated to CoS queue.
28072 * The HWRM will translate this value into byte counter and
28073 * time interval used for this COS inside the device.
28075 uint32_t queue_id5_max_bw;
28076 /* The bandwidth value. */
28077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
28078 UINT32_C(0xfffffff)
28079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
28081 /* The granularity of the value (bits or bytes). */
28082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
28083 UINT32_C(0x10000000)
28084 /* Value is in bits. */
28085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
28086 (UINT32_C(0x0) << 28)
28087 /* Value is in bytes. */
28088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
28089 (UINT32_C(0x1) << 28)
28090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
28091 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
28092 /* bw_value_unit is 3 b */
28093 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
28094 UINT32_C(0xe0000000)
28095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
28097 /* Value is in Mb or MB (base 10). */
28098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
28099 (UINT32_C(0x0) << 29)
28100 /* Value is in Kb or KB (base 10). */
28101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
28102 (UINT32_C(0x2) << 29)
28103 /* Value is in bits or bytes. */
28104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
28105 (UINT32_C(0x4) << 29)
28106 /* Value is in Gb or GB (base 10). */
28107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
28108 (UINT32_C(0x6) << 29)
28109 /* Value is in 1/100th of a percentage of total bandwidth. */
28110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28111 (UINT32_C(0x1) << 29)
28113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
28114 (UINT32_C(0x7) << 29)
28115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
28116 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
28117 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28118 uint8_t queue_id5_tsa_assign;
28119 /* Strict Priority */
28120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
28122 /* Enhanced Transmission Selection */
28123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
28126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
28129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
28132 * Priority level for strict priority. Valid only when the
28133 * tsa_assign is 0 - Strict Priority (SP)
28134 * 0..7 - Valid values.
28135 * 8..255 - Reserved.
28137 uint8_t queue_id5_pri_lvl;
28139 * Weight used to allocate remaining BW for this COS after
28140 * servicing guaranteed bandwidths for all COS.
28142 uint8_t queue_id5_bw_weight;
28143 /* ID of CoS Queue 6. */
28146 * Minimum BW allocated to CoS Queue.
28147 * The HWRM will translate this value into byte counter and
28148 * time interval used for this COS inside the device.
28150 uint32_t queue_id6_min_bw;
28151 /* The bandwidth value. */
28152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
28153 UINT32_C(0xfffffff)
28154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
28156 /* The granularity of the value (bits or bytes). */
28157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
28158 UINT32_C(0x10000000)
28159 /* Value is in bits. */
28160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
28161 (UINT32_C(0x0) << 28)
28162 /* Value is in bytes. */
28163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
28164 (UINT32_C(0x1) << 28)
28165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
28166 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
28167 /* bw_value_unit is 3 b */
28168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
28169 UINT32_C(0xe0000000)
28170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
28172 /* Value is in Mb or MB (base 10). */
28173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
28174 (UINT32_C(0x0) << 29)
28175 /* Value is in Kb or KB (base 10). */
28176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
28177 (UINT32_C(0x2) << 29)
28178 /* Value is in bits or bytes. */
28179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
28180 (UINT32_C(0x4) << 29)
28181 /* Value is in Gb or GB (base 10). */
28182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
28183 (UINT32_C(0x6) << 29)
28184 /* Value is in 1/100th of a percentage of total bandwidth. */
28185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28186 (UINT32_C(0x1) << 29)
28188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
28189 (UINT32_C(0x7) << 29)
28190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
28191 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
28193 * Maximum BW allocated to CoS queue.
28194 * The HWRM will translate this value into byte counter and
28195 * time interval used for this COS inside the device.
28197 uint32_t queue_id6_max_bw;
28198 /* The bandwidth value. */
28199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
28200 UINT32_C(0xfffffff)
28201 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
28203 /* The granularity of the value (bits or bytes). */
28204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
28205 UINT32_C(0x10000000)
28206 /* Value is in bits. */
28207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
28208 (UINT32_C(0x0) << 28)
28209 /* Value is in bytes. */
28210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
28211 (UINT32_C(0x1) << 28)
28212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
28213 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
28214 /* bw_value_unit is 3 b */
28215 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
28216 UINT32_C(0xe0000000)
28217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
28219 /* Value is in Mb or MB (base 10). */
28220 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
28221 (UINT32_C(0x0) << 29)
28222 /* Value is in Kb or KB (base 10). */
28223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
28224 (UINT32_C(0x2) << 29)
28225 /* Value is in bits or bytes. */
28226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
28227 (UINT32_C(0x4) << 29)
28228 /* Value is in Gb or GB (base 10). */
28229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
28230 (UINT32_C(0x6) << 29)
28231 /* Value is in 1/100th of a percentage of total bandwidth. */
28232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28233 (UINT32_C(0x1) << 29)
28235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
28236 (UINT32_C(0x7) << 29)
28237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
28238 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
28239 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28240 uint8_t queue_id6_tsa_assign;
28241 /* Strict Priority */
28242 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
28244 /* Enhanced Transmission Selection */
28245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
28248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
28251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
28254 * Priority level for strict priority. Valid only when the
28255 * tsa_assign is 0 - Strict Priority (SP)
28256 * 0..7 - Valid values.
28257 * 8..255 - Reserved.
28259 uint8_t queue_id6_pri_lvl;
28261 * Weight used to allocate remaining BW for this COS after
28262 * servicing guaranteed bandwidths for all COS.
28264 uint8_t queue_id6_bw_weight;
28265 /* ID of CoS Queue 7. */
28268 * Minimum BW allocated to CoS Queue.
28269 * The HWRM will translate this value into byte counter and
28270 * time interval used for this COS inside the device.
28272 uint32_t queue_id7_min_bw;
28273 /* The bandwidth value. */
28274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
28275 UINT32_C(0xfffffff)
28276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
28278 /* The granularity of the value (bits or bytes). */
28279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
28280 UINT32_C(0x10000000)
28281 /* Value is in bits. */
28282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
28283 (UINT32_C(0x0) << 28)
28284 /* Value is in bytes. */
28285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
28286 (UINT32_C(0x1) << 28)
28287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
28288 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
28289 /* bw_value_unit is 3 b */
28290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
28291 UINT32_C(0xe0000000)
28292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
28294 /* Value is in Mb or MB (base 10). */
28295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
28296 (UINT32_C(0x0) << 29)
28297 /* Value is in Kb or KB (base 10). */
28298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
28299 (UINT32_C(0x2) << 29)
28300 /* Value is in bits or bytes. */
28301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
28302 (UINT32_C(0x4) << 29)
28303 /* Value is in Gb or GB (base 10). */
28304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
28305 (UINT32_C(0x6) << 29)
28306 /* Value is in 1/100th of a percentage of total bandwidth. */
28307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
28308 (UINT32_C(0x1) << 29)
28310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
28311 (UINT32_C(0x7) << 29)
28312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
28313 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
28315 * Maximum BW allocated to CoS queue.
28316 * The HWRM will translate this value into byte counter and
28317 * time interval used for this COS inside the device.
28319 uint32_t queue_id7_max_bw;
28320 /* The bandwidth value. */
28321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
28322 UINT32_C(0xfffffff)
28323 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
28325 /* The granularity of the value (bits or bytes). */
28326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
28327 UINT32_C(0x10000000)
28328 /* Value is in bits. */
28329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
28330 (UINT32_C(0x0) << 28)
28331 /* Value is in bytes. */
28332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
28333 (UINT32_C(0x1) << 28)
28334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
28335 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
28336 /* bw_value_unit is 3 b */
28337 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
28338 UINT32_C(0xe0000000)
28339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
28341 /* Value is in Mb or MB (base 10). */
28342 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
28343 (UINT32_C(0x0) << 29)
28344 /* Value is in Kb or KB (base 10). */
28345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
28346 (UINT32_C(0x2) << 29)
28347 /* Value is in bits or bytes. */
28348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
28349 (UINT32_C(0x4) << 29)
28350 /* Value is in Gb or GB (base 10). */
28351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
28352 (UINT32_C(0x6) << 29)
28353 /* Value is in 1/100th of a percentage of total bandwidth. */
28354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
28355 (UINT32_C(0x1) << 29)
28357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
28358 (UINT32_C(0x7) << 29)
28359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
28360 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
28361 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
28362 uint8_t queue_id7_tsa_assign;
28363 /* Strict Priority */
28364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
28366 /* Enhanced Transmission Selection */
28367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
28370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
28373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
28376 * Priority level for strict priority. Valid only when the
28377 * tsa_assign is 0 - Strict Priority (SP)
28378 * 0..7 - Valid values.
28379 * 8..255 - Reserved.
28381 uint8_t queue_id7_pri_lvl;
28383 * Weight used to allocate remaining BW for this COS after
28384 * servicing guaranteed bandwidths for all COS.
28386 uint8_t queue_id7_bw_weight;
28387 uint8_t unused_1[5];
28390 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
28391 struct hwrm_queue_cos2bw_cfg_output {
28392 /* The specific error status for the command. */
28393 uint16_t error_code;
28394 /* The HWRM command request type. */
28396 /* The sequence ID from the original command. */
28398 /* The length of the response data in number of bytes. */
28400 uint8_t unused_0[7];
28402 * This field is used in Output records to indicate that the output
28403 * is completely written to RAM. This field should be read as '1'
28404 * to indicate that the output has been completely written.
28405 * When writing a command completion or response to an internal processor,
28406 * the order of writes has to be such that this field is written last.
28411 /*************************
28412 * hwrm_queue_dscp_qcaps *
28413 *************************/
28416 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
28417 struct hwrm_queue_dscp_qcaps_input {
28418 /* The HWRM command request type. */
28421 * The completion ring to send the completion event on. This should
28422 * be the NQ ID returned from the `nq_alloc` HWRM command.
28424 uint16_t cmpl_ring;
28426 * The sequence ID is used by the driver for tracking multiple
28427 * commands. This ID is treated as opaque data by the firmware and
28428 * the value is returned in the `hwrm_resp_hdr` upon completion.
28432 * The target ID of the command:
28433 * * 0x0-0xFFF8 - The function ID
28434 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28435 * * 0xFFFD - Reserved for user-space HWRM interface
28438 uint16_t target_id;
28440 * A physical address pointer pointing to a host buffer that the
28441 * command's response data will be written. This can be either a host
28442 * physical address (HPA) or a guest physical address (GPA) and must
28443 * point to a physically contiguous block of memory.
28445 uint64_t resp_addr;
28447 * Port ID of port for which the table is being configured.
28448 * The HWRM needs to check whether this function is allowed
28449 * to configure pri2cos mapping on this port.
28452 uint8_t unused_0[7];
28455 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
28456 struct hwrm_queue_dscp_qcaps_output {
28457 /* The specific error status for the command. */
28458 uint16_t error_code;
28459 /* The HWRM command request type. */
28461 /* The sequence ID from the original command. */
28463 /* The length of the response data in number of bytes. */
28465 /* The number of bits provided by the hardware for the DSCP value. */
28466 uint8_t num_dscp_bits;
28468 /* Max number of DSCP-MASK-PRI entries supported. */
28469 uint16_t max_entries;
28470 uint8_t unused_1[3];
28472 * This field is used in Output records to indicate that the output
28473 * is completely written to RAM. This field should be read as '1'
28474 * to indicate that the output has been completely written.
28475 * When writing a command completion or response to an internal processor,
28476 * the order of writes has to be such that this field is written last.
28481 /****************************
28482 * hwrm_queue_dscp2pri_qcfg *
28483 ****************************/
28486 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
28487 struct hwrm_queue_dscp2pri_qcfg_input {
28488 /* The HWRM command request type. */
28491 * The completion ring to send the completion event on. This should
28492 * be the NQ ID returned from the `nq_alloc` HWRM command.
28494 uint16_t cmpl_ring;
28496 * The sequence ID is used by the driver for tracking multiple
28497 * commands. This ID is treated as opaque data by the firmware and
28498 * the value is returned in the `hwrm_resp_hdr` upon completion.
28502 * The target ID of the command:
28503 * * 0x0-0xFFF8 - The function ID
28504 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28505 * * 0xFFFD - Reserved for user-space HWRM interface
28508 uint16_t target_id;
28510 * A physical address pointer pointing to a host buffer that the
28511 * command's response data will be written. This can be either a host
28512 * physical address (HPA) or a guest physical address (GPA) and must
28513 * point to a physically contiguous block of memory.
28515 uint64_t resp_addr;
28517 * This is the host address where the 24-bits DSCP-MASK-PRI
28518 * tuple(s) will be copied to.
28520 uint64_t dest_data_addr;
28522 * Port ID of port for which the table is being configured.
28523 * The HWRM needs to check whether this function is allowed
28524 * to configure pri2cos mapping on this port.
28528 /* Size of the buffer pointed to by dest_data_addr. */
28529 uint16_t dest_data_buffer_size;
28530 uint8_t unused_1[4];
28533 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
28534 struct hwrm_queue_dscp2pri_qcfg_output {
28535 /* The specific error status for the command. */
28536 uint16_t error_code;
28537 /* The HWRM command request type. */
28539 /* The sequence ID from the original command. */
28541 /* The length of the response data in number of bytes. */
28544 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
28545 * by the dest_data_addr.
28547 uint16_t entry_cnt;
28549 * This is the default PRI which un-initialized DSCP values are
28552 uint8_t default_pri;
28553 uint8_t unused_0[4];
28555 * This field is used in Output records to indicate that the output
28556 * is completely written to RAM. This field should be read as '1'
28557 * to indicate that the output has been completely written.
28558 * When writing a command completion or response to an internal processor,
28559 * the order of writes has to be such that this field is written last.
28564 /***************************
28565 * hwrm_queue_dscp2pri_cfg *
28566 ***************************/
28569 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
28570 struct hwrm_queue_dscp2pri_cfg_input {
28571 /* The HWRM command request type. */
28574 * The completion ring to send the completion event on. This should
28575 * be the NQ ID returned from the `nq_alloc` HWRM command.
28577 uint16_t cmpl_ring;
28579 * The sequence ID is used by the driver for tracking multiple
28580 * commands. This ID is treated as opaque data by the firmware and
28581 * the value is returned in the `hwrm_resp_hdr` upon completion.
28585 * The target ID of the command:
28586 * * 0x0-0xFFF8 - The function ID
28587 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28588 * * 0xFFFD - Reserved for user-space HWRM interface
28591 uint16_t target_id;
28593 * A physical address pointer pointing to a host buffer that the
28594 * command's response data will be written. This can be either a host
28595 * physical address (HPA) or a guest physical address (GPA) and must
28596 * point to a physically contiguous block of memory.
28598 uint64_t resp_addr;
28600 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
28601 * will be copied from.
28603 uint64_t src_data_addr;
28605 /* use_hw_default_pri is 1 b */
28606 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
28610 * This bit must be '1' for the default_pri field to be
28613 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
28616 * Port ID of port for which the table is being configured.
28617 * The HWRM needs to check whether this function is allowed
28618 * to configure pri2cos mapping on this port.
28622 * This is the default PRI which un-initialized DSCP values will be
28625 uint8_t default_pri;
28627 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
28628 * to by src_data_addr.
28630 uint16_t entry_cnt;
28631 uint8_t unused_0[4];
28634 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
28635 struct hwrm_queue_dscp2pri_cfg_output {
28636 /* The specific error status for the command. */
28637 uint16_t error_code;
28638 /* The HWRM command request type. */
28640 /* The sequence ID from the original command. */
28642 /* The length of the response data in number of bytes. */
28644 uint8_t unused_0[7];
28646 * This field is used in Output records to indicate that the output
28647 * is completely written to RAM. This field should be read as '1'
28648 * to indicate that the output has been completely written.
28649 * When writing a command completion or response to an internal processor,
28650 * the order of writes has to be such that this field is written last.
28655 /*************************
28656 * hwrm_queue_mpls_qcaps *
28657 *************************/
28660 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
28661 struct hwrm_queue_mpls_qcaps_input {
28662 /* The HWRM command request type. */
28665 * The completion ring to send the completion event on. This should
28666 * be the NQ ID returned from the `nq_alloc` HWRM command.
28668 uint16_t cmpl_ring;
28670 * The sequence ID is used by the driver for tracking multiple
28671 * commands. This ID is treated as opaque data by the firmware and
28672 * the value is returned in the `hwrm_resp_hdr` upon completion.
28676 * The target ID of the command:
28677 * * 0x0-0xFFF8 - The function ID
28678 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28679 * * 0xFFFD - Reserved for user-space HWRM interface
28682 uint16_t target_id;
28684 * A physical address pointer pointing to a host buffer that the
28685 * command's response data will be written. This can be either a host
28686 * physical address (HPA) or a guest physical address (GPA) and must
28687 * point to a physically contiguous block of memory.
28689 uint64_t resp_addr;
28691 * Port ID of port for which the table is being configured.
28692 * The HWRM needs to check whether this function is allowed
28693 * to configure MPLS TC(EXP) to pri mapping on this port.
28696 uint8_t unused_0[7];
28699 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
28700 struct hwrm_queue_mpls_qcaps_output {
28701 /* The specific error status for the command. */
28702 uint16_t error_code;
28703 /* The HWRM command request type. */
28705 /* The sequence ID from the original command. */
28707 /* The length of the response data in number of bytes. */
28710 * Bitmask indicating which queues can be configured by the
28711 * hwrm_queue_mplstc2pri_cfg command.
28713 * Each bit represents a specific pri where bit 0 represents
28714 * pri 0 and bit 7 represents pri 7.
28715 * # A value of 0 indicates that the pri is not configurable
28716 * by the hwrm_queue_mplstc2pri_cfg command.
28717 * # A value of 1 indicates that the pri is configurable.
28718 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
28719 * trying to configure a pri that is not configurable.
28721 uint8_t queue_mplstc2pri_cfg_allowed;
28723 * This is the default PRI which un-initialized MPLS values will be
28726 uint8_t hw_default_pri;
28727 uint8_t unused_0[5];
28729 * This field is used in Output records to indicate that the output
28730 * is completely written to RAM. This field should be read as '1'
28731 * to indicate that the output has been completely written.
28732 * When writing a command completion or response to an internal processor,
28733 * the order of writes has to be such that this field is written last.
28738 /******************************
28739 * hwrm_queue_mplstc2pri_qcfg *
28740 ******************************/
28743 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
28744 struct hwrm_queue_mplstc2pri_qcfg_input {
28745 /* The HWRM command request type. */
28748 * The completion ring to send the completion event on. This should
28749 * be the NQ ID returned from the `nq_alloc` HWRM command.
28751 uint16_t cmpl_ring;
28753 * The sequence ID is used by the driver for tracking multiple
28754 * commands. This ID is treated as opaque data by the firmware and
28755 * the value is returned in the `hwrm_resp_hdr` upon completion.
28759 * The target ID of the command:
28760 * * 0x0-0xFFF8 - The function ID
28761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28762 * * 0xFFFD - Reserved for user-space HWRM interface
28765 uint16_t target_id;
28767 * A physical address pointer pointing to a host buffer that the
28768 * command's response data will be written. This can be either a host
28769 * physical address (HPA) or a guest physical address (GPA) and must
28770 * point to a physically contiguous block of memory.
28772 uint64_t resp_addr;
28774 * Port ID of port for which the table is being configured.
28775 * The HWRM needs to check whether this function is allowed
28776 * to configure MPLS TC(EXP) to pri mapping on this port.
28779 uint8_t unused_0[7];
28782 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
28783 struct hwrm_queue_mplstc2pri_qcfg_output {
28784 /* The specific error status for the command. */
28785 uint16_t error_code;
28786 /* The HWRM command request type. */
28788 /* The sequence ID from the original command. */
28790 /* The length of the response data in number of bytes. */
28793 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
28794 * before traffic has started.
28795 * A value of 0xff indicates that no pri is assigned to the
28798 uint8_t tc0_pri_queue_id;
28800 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
28801 * before traffic has started.
28802 * A value of 0xff indicates that no pri is assigned to the
28805 uint8_t tc1_pri_queue_id;
28807 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
28808 * before traffic has started.
28809 * A value of 0xff indicates that no pri is assigned to the
28812 uint8_t tc2_pri_queue_id;
28814 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
28815 * before traffic has started.
28816 * A value of 0xff indicates that no pri is assigned to the
28819 uint8_t tc3_pri_queue_id;
28821 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
28822 * before traffic has started.
28823 * A value of 0xff indicates that no pri is assigned to the
28826 uint8_t tc4_pri_queue_id;
28828 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
28829 * before traffic has started.
28830 * A value of 0xff indicates that no pri is assigned to the
28833 uint8_t tc5_pri_queue_id;
28835 * pri assigned to MPLS TC(EXP) 6. This value can only
28836 * be changed before traffic has started.
28837 * A value of 0xff indicates that no pri is assigned to the
28840 uint8_t tc6_pri_queue_id;
28842 * pri assigned to MPLS TC(EXP) 7. This value can only
28843 * be changed before traffic has started.
28844 * A value of 0xff indicates that no pri is assigned to the
28847 uint8_t tc7_pri_queue_id;
28848 uint8_t unused_0[7];
28850 * This field is used in Output records to indicate that the output
28851 * is completely written to RAM. This field should be read as '1'
28852 * to indicate that the output has been completely written.
28853 * When writing a command completion or response to an internal processor,
28854 * the order of writes has to be such that this field is written last.
28859 /*****************************
28860 * hwrm_queue_mplstc2pri_cfg *
28861 *****************************/
28864 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
28865 struct hwrm_queue_mplstc2pri_cfg_input {
28866 /* The HWRM command request type. */
28869 * The completion ring to send the completion event on. This should
28870 * be the NQ ID returned from the `nq_alloc` HWRM command.
28872 uint16_t cmpl_ring;
28874 * The sequence ID is used by the driver for tracking multiple
28875 * commands. This ID is treated as opaque data by the firmware and
28876 * the value is returned in the `hwrm_resp_hdr` upon completion.
28880 * The target ID of the command:
28881 * * 0x0-0xFFF8 - The function ID
28882 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28883 * * 0xFFFD - Reserved for user-space HWRM interface
28886 uint16_t target_id;
28888 * A physical address pointer pointing to a host buffer that the
28889 * command's response data will be written. This can be either a host
28890 * physical address (HPA) or a guest physical address (GPA) and must
28891 * point to a physically contiguous block of memory.
28893 uint64_t resp_addr;
28896 * This bit must be '1' for the mplstc0_pri_queue_id field to be
28899 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
28902 * This bit must be '1' for the mplstc1_pri_queue_id field to be
28905 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
28908 * This bit must be '1' for the mplstc2_pri_queue_id field to be
28911 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
28914 * This bit must be '1' for the mplstc3_pri_queue_id field to be
28917 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
28920 * This bit must be '1' for the mplstc4_pri_queue_id field to be
28923 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
28926 * This bit must be '1' for the mplstc5_pri_queue_id field to be
28929 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
28932 * This bit must be '1' for the mplstc6_pri_queue_id field to be
28935 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
28938 * This bit must be '1' for the mplstc7_pri_queue_id field to be
28941 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
28944 * Port ID of port for which the table is being configured.
28945 * The HWRM needs to check whether this function is allowed
28946 * to configure MPLS TC(EXP)to pri mapping on this port.
28949 uint8_t unused_0[3];
28951 * pri assigned to MPLS TC(EXP) 0. This value can only
28952 * be changed before traffic has started.
28954 uint8_t tc0_pri_queue_id;
28956 * pri assigned to MPLS TC(EXP) 1. This value can only
28957 * be changed before traffic has started.
28959 uint8_t tc1_pri_queue_id;
28961 * pri assigned to MPLS TC(EXP) 2 This value can only
28962 * be changed before traffic has started.
28964 uint8_t tc2_pri_queue_id;
28966 * pri assigned to MPLS TC(EXP) 3. This value can only
28967 * be changed before traffic has started.
28969 uint8_t tc3_pri_queue_id;
28971 * pri assigned to MPLS TC(EXP) 4. This value can only
28972 * be changed before traffic has started.
28974 uint8_t tc4_pri_queue_id;
28976 * pri assigned to MPLS TC(EXP) 5. This value can only
28977 * be changed before traffic has started.
28979 uint8_t tc5_pri_queue_id;
28981 * pri assigned to MPLS TC(EXP) 6. This value can only
28982 * be changed before traffic has started.
28984 uint8_t tc6_pri_queue_id;
28986 * pri assigned to MPLS TC(EXP) 7. This value can only
28987 * be changed before traffic has started.
28989 uint8_t tc7_pri_queue_id;
28992 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
28993 struct hwrm_queue_mplstc2pri_cfg_output {
28994 /* The specific error status for the command. */
28995 uint16_t error_code;
28996 /* The HWRM command request type. */
28998 /* The sequence ID from the original command. */
29000 /* The length of the response data in number of bytes. */
29002 uint8_t unused_0[7];
29004 * This field is used in Output records to indicate that the output
29005 * is completely written to RAM. This field should be read as '1'
29006 * to indicate that the output has been completely written.
29007 * When writing a command completion or response to an internal processor,
29008 * the order of writes has to be such that this field is written last.
29013 /****************************
29014 * hwrm_queue_vlanpri_qcaps *
29015 ****************************/
29018 /* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */
29019 struct hwrm_queue_vlanpri_qcaps_input {
29020 /* The HWRM command request type. */
29023 * The completion ring to send the completion event on. This should
29024 * be the NQ ID returned from the `nq_alloc` HWRM command.
29026 uint16_t cmpl_ring;
29028 * The sequence ID is used by the driver for tracking multiple
29029 * commands. This ID is treated as opaque data by the firmware and
29030 * the value is returned in the `hwrm_resp_hdr` upon completion.
29034 * The target ID of the command:
29035 * * 0x0-0xFFF8 - The function ID
29036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29037 * * 0xFFFD - Reserved for user-space HWRM interface
29040 uint16_t target_id;
29042 * A physical address pointer pointing to a host buffer that the
29043 * command's response data will be written. This can be either a host
29044 * physical address (HPA) or a guest physical address (GPA) and must
29045 * point to a physically contiguous block of memory.
29047 uint64_t resp_addr;
29049 * Port ID of port for which the table is being configured.
29050 * The HWRM needs to check whether this function is allowed
29051 * to configure VLAN priority to user priority mapping on this port.
29054 uint8_t unused_0[7];
29057 /* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */
29058 struct hwrm_queue_vlanpri_qcaps_output {
29059 /* The specific error status for the command. */
29060 uint16_t error_code;
29061 /* The HWRM command request type. */
29063 /* The sequence ID from the original command. */
29065 /* The length of the response data in number of bytes. */
29068 * This is the default user priority which all VLAN priority values
29069 * are mapped to if there is no VLAN priority to user priority mapping.
29071 uint8_t hw_default_pri;
29072 uint8_t unused_0[6];
29074 * This field is used in Output records to indicate that the output
29075 * is completely written to RAM. This field should be read as '1'
29076 * to indicate that the output has been completely written.
29077 * When writing a command completion or response to an internal processor,
29078 * the order of writes has to be such that this field is written last.
29083 /*******************************
29084 * hwrm_queue_vlanpri2pri_qcfg *
29085 *******************************/
29088 /* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */
29089 struct hwrm_queue_vlanpri2pri_qcfg_input {
29090 /* The HWRM command request type. */
29093 * The completion ring to send the completion event on. This should
29094 * be the NQ ID returned from the `nq_alloc` HWRM command.
29096 uint16_t cmpl_ring;
29098 * The sequence ID is used by the driver for tracking multiple
29099 * commands. This ID is treated as opaque data by the firmware and
29100 * the value is returned in the `hwrm_resp_hdr` upon completion.
29104 * The target ID of the command:
29105 * * 0x0-0xFFF8 - The function ID
29106 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29107 * * 0xFFFD - Reserved for user-space HWRM interface
29110 uint16_t target_id;
29112 * A physical address pointer pointing to a host buffer that the
29113 * command's response data will be written. This can be either a host
29114 * physical address (HPA) or a guest physical address (GPA) and must
29115 * point to a physically contiguous block of memory.
29117 uint64_t resp_addr;
29119 * Port ID of port for which the table is being configured.
29120 * The HWRM needs to check whether this function is allowed
29121 * to configure VLAN priority to user priority mapping on this port.
29124 uint8_t unused_0[7];
29127 /* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */
29128 struct hwrm_queue_vlanpri2pri_qcfg_output {
29129 /* The specific error status for the command. */
29130 uint16_t error_code;
29131 /* The HWRM command request type. */
29133 /* The sequence ID from the original command. */
29135 /* The length of the response data in number of bytes. */
29138 * User priority assigned to VLAN priority 0. A value of 0xff
29139 * indicates that no user priority is assigned. The default user
29140 * priority will be used.
29142 uint8_t vlanpri0_user_pri_id;
29144 * User priority assigned to VLAN priority 1. A value of 0xff
29145 * indicates that no user priority is assigned. The default user
29146 * priority will be used.
29148 uint8_t vlanpri1_user_pri_id;
29150 * User priority assigned to VLAN priority 2. A value of 0xff
29151 * indicates that no user priority is assigned. The default user
29152 * priority will be used.
29154 uint8_t vlanpri2_user_pri_id;
29156 * User priority assigned to VLAN priority 3. A value of 0xff
29157 * indicates that no user priority is assigned. The default user
29158 * priority will be used.
29160 uint8_t vlanpri3_user_pri_id;
29162 * User priority assigned to VLAN priority 4. A value of 0xff
29163 * indicates that no user priority is assigned. The default user
29164 * priority will be used.
29166 uint8_t vlanpri4_user_pri_id;
29168 * User priority assigned to VLAN priority 5. A value of 0xff
29169 * indicates that no user priority is assigned. The default user
29170 * priority will be used.
29172 uint8_t vlanpri5_user_pri_id;
29174 * User priority assigned to VLAN priority 6. A value of 0xff
29175 * indicates that no user priority is assigned. The default user
29176 * priority will be used.
29178 uint8_t vlanpri6_user_pri_id;
29180 * User priority assigned to VLAN priority 7. A value of 0xff
29181 * indicates that no user priority is assigned. The default user
29182 * priority will be used.
29184 uint8_t vlanpri7_user_pri_id;
29185 uint8_t unused_0[7];
29187 * This field is used in Output records to indicate that the output
29188 * is completely written to RAM. This field should be read as '1'
29189 * to indicate that the output has been completely written.
29190 * When writing a command completion or response to an internal processor,
29191 * the order of writes has to be such that this field is written last.
29196 /******************************
29197 * hwrm_queue_vlanpri2pri_cfg *
29198 ******************************/
29201 /* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */
29202 struct hwrm_queue_vlanpri2pri_cfg_input {
29203 /* The HWRM command request type. */
29206 * The completion ring to send the completion event on. This should
29207 * be the NQ ID returned from the `nq_alloc` HWRM command.
29209 uint16_t cmpl_ring;
29211 * The sequence ID is used by the driver for tracking multiple
29212 * commands. This ID is treated as opaque data by the firmware and
29213 * the value is returned in the `hwrm_resp_hdr` upon completion.
29217 * The target ID of the command:
29218 * * 0x0-0xFFF8 - The function ID
29219 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29220 * * 0xFFFD - Reserved for user-space HWRM interface
29223 uint16_t target_id;
29225 * A physical address pointer pointing to a host buffer that the
29226 * command's response data will be written. This can be either a host
29227 * physical address (HPA) or a guest physical address (GPA) and must
29228 * point to a physically contiguous block of memory.
29230 uint64_t resp_addr;
29233 * This bit must be '1' for the vlanpri0_user_pri_id field to be
29236 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \
29239 * This bit must be '1' for the vlanpri1_user_pri_id field to be
29242 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \
29245 * This bit must be '1' for the vlanpri2_user_pri_id field to be
29248 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \
29251 * This bit must be '1' for the vlanpri3_user_pri_id field to be
29254 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \
29257 * This bit must be '1' for the vlanpri4_user_pri_id field to be
29260 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \
29263 * This bit must be '1' for the vlanpri5_user_pri_id field to be
29266 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \
29269 * This bit must be '1' for the vlanpri6_user_pri_id field to be
29272 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \
29275 * This bit must be '1' for the vlanpri7_user_pri_id field to be
29278 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \
29281 * Port ID of port for which the table is being configured.
29282 * The HWRM needs to check whether this function is allowed
29283 * to configure VLAN priority to user priority mapping on this port.
29286 uint8_t unused_0[3];
29288 * User priority assigned to VLAN priority 0. This value can only
29289 * be changed before traffic has started.
29291 uint8_t vlanpri0_user_pri_id;
29293 * User priority assigned to VLAN priority 1. This value can only
29294 * be changed before traffic has started.
29296 uint8_t vlanpri1_user_pri_id;
29298 * User priority assigned to VLAN priority 2. This value can only
29299 * be changed before traffic has started.
29301 uint8_t vlanpri2_user_pri_id;
29303 * User priority assigned to VLAN priority 3. This value can only
29304 * be changed before traffic has started.
29306 uint8_t vlanpri3_user_pri_id;
29308 * User priority assigned to VLAN priority 4. This value can only
29309 * be changed before traffic has started.
29311 uint8_t vlanpri4_user_pri_id;
29313 * User priority assigned to VLAN priority 5. This value can only
29314 * be changed before traffic has started.
29316 uint8_t vlanpri5_user_pri_id;
29318 * User priority assigned to VLAN priority 6. This value can only
29319 * be changed before traffic has started.
29321 uint8_t vlanpri6_user_pri_id;
29323 * User priority assigned to VLAN priority 7. This value can only
29324 * be changed before traffic has started.
29326 uint8_t vlanpri7_user_pri_id;
29329 /* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */
29330 struct hwrm_queue_vlanpri2pri_cfg_output {
29331 /* The specific error status for the command. */
29332 uint16_t error_code;
29333 /* The HWRM command request type. */
29335 /* The sequence ID from the original command. */
29337 /* The length of the response data in number of bytes. */
29339 uint8_t unused_0[7];
29341 * This field is used in Output records to indicate that the output
29342 * is completely written to RAM. This field should be read as '1'
29343 * to indicate that the output has been completely written.
29344 * When writing a command completion or response to an internal processor,
29345 * the order of writes has to be such that this field is written last.
29350 /*******************
29351 * hwrm_vnic_alloc *
29352 *******************/
29355 /* hwrm_vnic_alloc_input (size:192b/24B) */
29356 struct hwrm_vnic_alloc_input {
29357 /* The HWRM command request type. */
29360 * The completion ring to send the completion event on. This should
29361 * be the NQ ID returned from the `nq_alloc` HWRM command.
29363 uint16_t cmpl_ring;
29365 * The sequence ID is used by the driver for tracking multiple
29366 * commands. This ID is treated as opaque data by the firmware and
29367 * the value is returned in the `hwrm_resp_hdr` upon completion.
29371 * The target ID of the command:
29372 * * 0x0-0xFFF8 - The function ID
29373 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29374 * * 0xFFFD - Reserved for user-space HWRM interface
29377 uint16_t target_id;
29379 * A physical address pointer pointing to a host buffer that the
29380 * command's response data will be written. This can be either a host
29381 * physical address (HPA) or a guest physical address (GPA) and must
29382 * point to a physically contiguous block of memory.
29384 uint64_t resp_addr;
29387 * When this bit is '1', this VNIC is requested to
29388 * be the default VNIC for this function.
29390 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \
29393 * When this bit is '1', proxy VEE PF is requesting
29394 * allocation of a default VNIC on behalf of virtio-net
29395 * function given in virtio_net_fid field.
29397 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \
29400 * Virtio-net function's FID.
29401 * This virtio-net function is requesting allocation of default
29402 * VNIC through proxy VEE PF.
29404 uint16_t virtio_net_fid;
29405 uint8_t unused_0[2];
29408 /* hwrm_vnic_alloc_output (size:128b/16B) */
29409 struct hwrm_vnic_alloc_output {
29410 /* The specific error status for the command. */
29411 uint16_t error_code;
29412 /* The HWRM command request type. */
29414 /* The sequence ID from the original command. */
29416 /* The length of the response data in number of bytes. */
29418 /* Logical vnic ID */
29420 uint8_t unused_0[3];
29422 * This field is used in Output records to indicate that the output
29423 * is completely written to RAM. This field should be read as '1'
29424 * to indicate that the output has been completely written.
29425 * When writing a command completion or response to an internal processor,
29426 * the order of writes has to be such that this field is written last.
29431 /********************
29432 * hwrm_vnic_update *
29433 ********************/
29436 /* hwrm_vnic_update_input (size:256b/32B) */
29437 struct hwrm_vnic_update_input {
29438 /* The HWRM command request type. */
29441 * The completion ring to send the completion event on. This should
29442 * be the NQ ID returned from the `nq_alloc` HWRM command.
29444 uint16_t cmpl_ring;
29446 * The sequence ID is used by the driver for tracking multiple
29447 * commands. This ID is treated as opaque data by the firmware and
29448 * the value is returned in the `hwrm_resp_hdr` upon completion.
29452 * The target ID of the command:
29453 * * 0x0-0xFFF8 - The function ID
29454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29455 * * 0xFFFD - Reserved for user-space HWRM interface
29458 uint16_t target_id;
29460 * A physical address pointer pointing to a host buffer that the
29461 * command's response data will be written. This can be either a host
29462 * physical address (HPA) or a guest physical address (GPA) and must
29463 * point to a physically contiguous block of memory.
29465 uint64_t resp_addr;
29466 /* Logical vnic ID */
29470 * This bit must be '1' for the vnic_state field to be
29473 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \
29476 * This bit must be '1' for the mru field to be
29479 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \
29482 * This bit must be '1' for the metadata_format_type field to be
29485 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \
29488 * This will update the context variable with the same name if
29489 * the corresponding enable is set.
29491 uint8_t vnic_state;
29492 /* Normal operation state for the VNIC. */
29493 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
29494 /* All packets are dropped in this state. */
29495 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
29496 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \
29497 HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP
29499 * The metadata format type used in all the RX packet completions
29500 * going through this VNIC.
29502 uint8_t metadata_format_type;
29503 /* No metadata information. */
29504 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \
29507 * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],
29510 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \
29512 /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */
29513 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \
29515 /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */
29516 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \
29518 /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */
29519 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \
29521 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \
29522 HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS
29524 * The maximum receive unit of the vnic.
29525 * Each vnic is associated with a function.
29526 * The vnic mru value overwrites the mru setting of the
29527 * associated function.
29528 * The HWRM shall make sure that vnic mru does not exceed
29529 * the mru of the port the function is associated with.
29532 uint8_t unused_1[4];
29535 /* hwrm_vnic_update_output (size:128b/16B) */
29536 struct hwrm_vnic_update_output {
29537 /* The specific error status for the command. */
29538 uint16_t error_code;
29539 /* The HWRM command request type. */
29541 /* The sequence ID from the original command. */
29543 /* The length of the response data in number of bytes. */
29545 uint8_t unused_0[7];
29547 * This field is used in Output records to indicate that the output
29548 * is completely written to RAM. This field should be read as '1'
29549 * to indicate that the output has been completely written.
29550 * When writing a command completion or response to an internal
29551 * processor, the order of writes has to be such that this field is
29557 /******************
29559 ******************/
29562 /* hwrm_vnic_free_input (size:192b/24B) */
29563 struct hwrm_vnic_free_input {
29564 /* The HWRM command request type. */
29567 * The completion ring to send the completion event on. This should
29568 * be the NQ ID returned from the `nq_alloc` HWRM command.
29570 uint16_t cmpl_ring;
29572 * The sequence ID is used by the driver for tracking multiple
29573 * commands. This ID is treated as opaque data by the firmware and
29574 * the value is returned in the `hwrm_resp_hdr` upon completion.
29578 * The target ID of the command:
29579 * * 0x0-0xFFF8 - The function ID
29580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29581 * * 0xFFFD - Reserved for user-space HWRM interface
29584 uint16_t target_id;
29586 * A physical address pointer pointing to a host buffer that the
29587 * command's response data will be written. This can be either a host
29588 * physical address (HPA) or a guest physical address (GPA) and must
29589 * point to a physically contiguous block of memory.
29591 uint64_t resp_addr;
29592 /* Logical vnic ID */
29594 uint8_t unused_0[4];
29597 /* hwrm_vnic_free_output (size:128b/16B) */
29598 struct hwrm_vnic_free_output {
29599 /* The specific error status for the command. */
29600 uint16_t error_code;
29601 /* The HWRM command request type. */
29603 /* The sequence ID from the original command. */
29605 /* The length of the response data in number of bytes. */
29607 uint8_t unused_0[7];
29609 * This field is used in Output records to indicate that the output
29610 * is completely written to RAM. This field should be read as '1'
29611 * to indicate that the output has been completely written.
29612 * When writing a command completion or response to an internal processor,
29613 * the order of writes has to be such that this field is written last.
29623 /* hwrm_vnic_cfg_input (size:384b/48B) */
29624 struct hwrm_vnic_cfg_input {
29625 /* The HWRM command request type. */
29628 * The completion ring to send the completion event on. This should
29629 * be the NQ ID returned from the `nq_alloc` HWRM command.
29631 uint16_t cmpl_ring;
29633 * The sequence ID is used by the driver for tracking multiple
29634 * commands. This ID is treated as opaque data by the firmware and
29635 * the value is returned in the `hwrm_resp_hdr` upon completion.
29639 * The target ID of the command:
29640 * * 0x0-0xFFF8 - The function ID
29641 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29642 * * 0xFFFD - Reserved for user-space HWRM interface
29645 uint16_t target_id;
29647 * A physical address pointer pointing to a host buffer that the
29648 * command's response data will be written. This can be either a host
29649 * physical address (HPA) or a guest physical address (GPA) and must
29650 * point to a physically contiguous block of memory.
29652 uint64_t resp_addr;
29655 * When this bit is '1', the VNIC is requested to
29656 * be the default VNIC for the function.
29658 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
29661 * When this bit is '1', the VNIC is being configured to
29662 * strip VLAN in the RX path.
29663 * If set to '0', then VLAN stripping is disabled on
29666 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
29669 * When this bit is '1', the VNIC is being configured to
29670 * buffer receive packets in the hardware until the host
29671 * posts new receive buffers.
29672 * If set to '0', then bd_stall is being configured to be
29673 * disabled on this VNIC.
29675 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
29678 * When this bit is '1', the VNIC is being configured to
29679 * receive both RoCE and non-RoCE traffic.
29680 * If set to '0', then this VNIC is not configured to be
29681 * operating in dual VNIC mode.
29683 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
29686 * When this flag is set to '1', the VNIC is requested to
29687 * be configured to receive only RoCE traffic.
29688 * If this flag is set to '0', then this flag shall be
29689 * ignored by the HWRM.
29690 * If roce_dual_vnic_mode flag is set to '1'
29691 * or roce_mirroring_capable_vnic_mode flag to 1,
29692 * then the HWRM client shall not set this flag to '1'.
29694 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
29697 * When a VNIC uses one destination ring group for certain
29698 * application (e.g. Receive Flow Steering) where
29699 * exact match is used to direct packets to a VNIC with one
29700 * destination ring group only, there is no need to configure
29701 * RSS indirection table for that VNIC as only one destination
29702 * ring group is used.
29704 * This flag is used to enable a mode where
29705 * RSS is enabled in the VNIC using a RSS context
29706 * for computing RSS hash but the RSS indirection table is
29707 * not configured using hwrm_vnic_rss_cfg.
29709 * If this mode is enabled, then the driver should not program
29710 * RSS indirection table for the RSS context that is used for
29711 * computing RSS hash only.
29713 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
29716 * When this bit is '1', the VNIC is being configured to
29717 * receive both RoCE and non-RoCE traffic, but forward only the
29718 * RoCE traffic further. Also, RoCE traffic can be mirrored to
29721 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
29725 * This bit must be '1' for the dflt_ring_grp field to be
29728 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
29731 * This bit must be '1' for the rss_rule field to be
29734 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
29737 * This bit must be '1' for the cos_rule field to be
29740 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
29743 * This bit must be '1' for the lb_rule field to be
29746 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
29749 * This bit must be '1' for the mru field to be
29752 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
29755 * This bit must be '1' for the default_rx_ring_id field to be
29758 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
29761 * This bit must be '1' for the default_cmpl_ring_id field to be
29764 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
29766 /* This bit must be '1' for the queue_id field to be configured. */
29767 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
29769 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
29770 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
29772 /* Logical vnic ID */
29775 * Default Completion ring for the VNIC. This ring will
29776 * be chosen if packet does not match any RSS rules and if
29777 * there is no COS rule.
29779 uint16_t dflt_ring_grp;
29781 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
29782 * there is no RSS rule.
29786 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
29787 * there is no COS rule.
29791 * RSS ID for load balancing rule/table structure.
29792 * 0xFF... (All Fs) if there is no LB rule.
29796 * The maximum receive unit of the vnic.
29797 * Each vnic is associated with a function.
29798 * The vnic mru value overwrites the mru setting of the
29799 * associated function.
29800 * The HWRM shall make sure that vnic mru does not exceed
29801 * the mru of the port the function is associated with.
29805 * Default Rx ring for the VNIC. This ring will
29806 * be chosen if packet does not match any RSS rules.
29807 * The aggregation ring associated with the Rx ring is
29808 * implied based on the Rx ring specified when the
29809 * aggregation ring was allocated.
29811 uint16_t default_rx_ring_id;
29813 * Default completion ring for the VNIC. This ring will
29814 * be chosen if packet does not match any RSS rules.
29816 uint16_t default_cmpl_ring_id;
29818 * When specified, only incoming packets classified to the specified CoS
29819 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
29820 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
29821 * ntuple filters with VNIC destination specified are invalid since they
29822 * conflict with the CoS to VNIC steering rules in this mode.
29824 * If this field is not specified, packet to VNIC steering will be
29825 * subject to the standard L2 filter rules and any additional ntuple
29826 * filter rules with destination VNIC specified.
29830 * If the device supports the RX V2 and RX TPA start V2 completion
29831 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
29832 * used to specify the two RX checksum modes supported by these
29833 * completion records.
29835 uint8_t rx_csum_v2_mode;
29837 * When configured with this checksum mode, the number of header
29838 * groups in the delivered packet with a valid IP checksum and
29839 * the number of header groups in the delivered packet with a valid
29840 * L4 checksum are reported. Valid checksums are counted from the
29841 * outermost header group to the innermost header group, stopping at
29842 * the first error. This is the default checksum mode supported if
29843 * the driver doesn't explicitly configure the RX checksum mode.
29845 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
29847 * When configured with this checksum mode, the checksum status is
29848 * reported using 'all ok' mode. In the RX completion record, one
29849 * bit indicates if the IP checksum is valid for all the parsed
29850 * header groups with an IP checksum. Another bit indicates if the
29851 * L4 checksum is valid for all the parsed header groups with an L4
29852 * checksum. The number of header groups that were parsed by the
29853 * chip and passed in the delivered packet is also reported.
29855 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
29857 * Any rx_csum_v2_mode value larger than or equal to this is not
29860 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
29861 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
29862 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
29863 uint8_t unused0[5];
29866 /* hwrm_vnic_cfg_output (size:128b/16B) */
29867 struct hwrm_vnic_cfg_output {
29868 /* The specific error status for the command. */
29869 uint16_t error_code;
29870 /* The HWRM command request type. */
29872 /* The sequence ID from the original command. */
29874 /* The length of the response data in number of bytes. */
29876 uint8_t unused_0[7];
29878 * This field is used in Output records to indicate that the output
29879 * is completely written to RAM. This field should be read as '1'
29880 * to indicate that the output has been completely written.
29881 * When writing a command completion or response to an internal processor,
29882 * the order of writes has to be such that this field is written last.
29887 /******************
29889 ******************/
29892 /* hwrm_vnic_qcfg_input (size:256b/32B) */
29893 struct hwrm_vnic_qcfg_input {
29894 /* The HWRM command request type. */
29897 * The completion ring to send the completion event on. This should
29898 * be the NQ ID returned from the `nq_alloc` HWRM command.
29900 uint16_t cmpl_ring;
29902 * The sequence ID is used by the driver for tracking multiple
29903 * commands. This ID is treated as opaque data by the firmware and
29904 * the value is returned in the `hwrm_resp_hdr` upon completion.
29908 * The target ID of the command:
29909 * * 0x0-0xFFF8 - The function ID
29910 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29911 * * 0xFFFD - Reserved for user-space HWRM interface
29914 uint16_t target_id;
29916 * A physical address pointer pointing to a host buffer that the
29917 * command's response data will be written. This can be either a host
29918 * physical address (HPA) or a guest physical address (GPA) and must
29919 * point to a physically contiguous block of memory.
29921 uint64_t resp_addr;
29924 * This bit must be '1' for the vf_id_valid field to be
29927 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
29928 /* Logical vnic ID */
29930 /* ID of Virtual Function whose VNIC resource is being queried. */
29932 uint8_t unused_0[6];
29935 /* hwrm_vnic_qcfg_output (size:256b/32B) */
29936 struct hwrm_vnic_qcfg_output {
29937 /* The specific error status for the command. */
29938 uint16_t error_code;
29939 /* The HWRM command request type. */
29941 /* The sequence ID from the original command. */
29943 /* The length of the response data in number of bytes. */
29945 /* Default Completion ring for the VNIC. */
29946 uint16_t dflt_ring_grp;
29948 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
29949 * there is no RSS rule.
29953 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
29954 * there is no COS rule.
29958 * RSS ID for load balancing rule/table structure.
29959 * 0xFF... (All Fs) if there is no LB rule.
29962 /* The maximum receive unit of the vnic. */
29964 uint8_t unused_0[2];
29967 * When this bit is '1', the VNIC is the default VNIC for
29970 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
29973 * When this bit is '1', the VNIC is configured to
29974 * strip VLAN in the RX path.
29975 * If set to '0', then VLAN stripping is disabled on
29978 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
29981 * When this bit is '1', the VNIC is configured to
29982 * buffer receive packets in the hardware until the host
29983 * posts new receive buffers.
29984 * If set to '0', then bd_stall is disabled on
29987 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
29990 * When this bit is '1', the VNIC is configured to
29991 * receive both RoCE and non-RoCE traffic.
29992 * If set to '0', then this VNIC is not configured to
29993 * operate in dual VNIC mode.
29995 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
29998 * When this flag is set to '1', the VNIC is configured to
29999 * receive only RoCE traffic.
30000 * When this flag is set to '0', the VNIC is not configured
30001 * to receive only RoCE traffic.
30002 * If roce_dual_vnic_mode flag and this flag both are set
30003 * to '1', then it is an invalid configuration of the
30004 * VNIC. The HWRM should not allow that type of
30005 * mis-configuration by HWRM clients.
30007 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
30010 * When a VNIC uses one destination ring group for certain
30011 * application (e.g. Receive Flow Steering) where
30012 * exact match is used to direct packets to a VNIC with one
30013 * destination ring group only, there is no need to configure
30014 * RSS indirection table for that VNIC as only one destination
30015 * ring group is used.
30017 * When this bit is set to '1', then the VNIC is enabled in a
30018 * mode where RSS is enabled in the VNIC using a RSS context
30019 * for computing RSS hash but the RSS indirection table is
30022 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
30025 * When this bit is '1', the VNIC is configured to
30026 * receive both RoCE and non-RoCE traffic, but forward only
30027 * RoCE traffic further. Also RoCE traffic can be mirrored to
30030 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
30033 * When this bit is '0', VNIC is in normal operation state.
30034 * When this bit is '1', VNIC drops all the received packets.
30036 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \
30039 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
30040 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
30041 * queue association.
30045 * If the device supports the RX V2 and RX TPA start V2 completion
30046 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
30047 * used to specify the current RX checksum mode configured for all the
30048 * RX rings of a VNIC.
30050 uint8_t rx_csum_v2_mode;
30052 * This value indicates that the VNIC is configured to use the
30053 * default RX checksum mode for all the rings associated with this
30056 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
30058 * This value indicates that the VNIC is configured to use the RX
30059 * checksum ‘all_ok’ mode for all the rings associated with this
30062 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
30064 * Any rx_csum_v2_mode value larger than or equal to this is not
30067 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
30068 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
30069 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
30070 uint8_t unused_1[4];
30072 * This field is used in Output records to indicate that the output
30073 * is completely written to RAM. This field should be read as '1'
30074 * to indicate that the output has been completely written.
30075 * When writing a command completion or response to an internal processor,
30076 * the order of writes has to be such that this field is written last.
30081 /*******************
30082 * hwrm_vnic_qcaps *
30083 *******************/
30086 /* hwrm_vnic_qcaps_input (size:192b/24B) */
30087 struct hwrm_vnic_qcaps_input {
30088 /* The HWRM command request type. */
30091 * The completion ring to send the completion event on. This should
30092 * be the NQ ID returned from the `nq_alloc` HWRM command.
30094 uint16_t cmpl_ring;
30096 * The sequence ID is used by the driver for tracking multiple
30097 * commands. This ID is treated as opaque data by the firmware and
30098 * the value is returned in the `hwrm_resp_hdr` upon completion.
30102 * The target ID of the command:
30103 * * 0x0-0xFFF8 - The function ID
30104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30105 * * 0xFFFD - Reserved for user-space HWRM interface
30108 uint16_t target_id;
30110 * A physical address pointer pointing to a host buffer that the
30111 * command's response data will be written. This can be either a host
30112 * physical address (HPA) or a guest physical address (GPA) and must
30113 * point to a physically contiguous block of memory.
30115 uint64_t resp_addr;
30117 uint8_t unused_0[4];
30120 /* hwrm_vnic_qcaps_output (size:192b/24B) */
30121 struct hwrm_vnic_qcaps_output {
30122 /* The specific error status for the command. */
30123 uint16_t error_code;
30124 /* The HWRM command request type. */
30126 /* The sequence ID from the original command. */
30128 /* The length of the response data in number of bytes. */
30130 /* The maximum receive unit that is settable on a vnic. */
30132 uint8_t unused_0[2];
30135 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
30138 * When this bit is '1', the capability of stripping VLAN in
30139 * the RX path is supported on VNIC(s).
30140 * If set to '0', then VLAN stripping capability is
30141 * not supported on VNIC(s).
30143 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
30146 * When this bit is '1', the capability to buffer receive
30147 * packets in the hardware until the host posts new receive buffers
30148 * is supported on VNIC(s).
30149 * If set to '0', then bd_stall capability is not supported
30152 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
30155 * When this bit is '1', the capability to
30156 * receive both RoCE and non-RoCE traffic on VNIC(s) is
30158 * If set to '0', then the capability to receive
30159 * both RoCE and non-RoCE traffic on VNIC(s) is
30162 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
30165 * When this bit is set to '1', the capability to configure
30166 * a VNIC to receive only RoCE traffic is supported.
30167 * When this flag is set to '0', the VNIC capability to
30168 * configure to receive only RoCE traffic is not supported.
30170 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
30173 * When this bit is set to '1', then the capability to enable
30174 * a VNIC in a mode where RSS context without configuring
30175 * RSS indirection table is supported (for RSS hash computation).
30176 * When this bit is set to '0', then a VNIC can not be configured
30177 * with a mode to enable RSS context without configuring RSS
30178 * indirection table.
30180 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
30183 * When this bit is '1', the capability to
30184 * mirror the RoCE traffic is supported.
30185 * If set to '0', then the capability to mirror the
30186 * RoCE traffic is not supported.
30188 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
30191 * When this bit is '1', the outermost RSS hashing capability
30192 * is supported. If set to '0', then the outermost RSS hashing
30193 * capability is not supported.
30195 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
30198 * When this bit is '1', it indicates that firmware supports the
30199 * ability to steer incoming packets from one CoS queue to one
30200 * VNIC. This optional feature can then be enabled
30201 * using HWRM_VNIC_CFG on any VNIC. This feature is only
30202 * available when NVM option “enable_cos_classfication” is set
30203 * to 1. If set to '0', firmware does not support this feature.
30205 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
30208 * When this bit is '1', it indicates that HW and firmware supports
30209 * the use of RX V2 and RX TPA start V2 completion records for all
30210 * the RX rings of a VNIC. Once set, this feature is mandatory to
30211 * be used for the RX rings of the VNIC. Additionally, two new RX
30212 * checksum features supported by these ompletion records can be
30213 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
30214 * HW and the firmware does not support this feature.
30216 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
30219 * When this bit is '1', it indicates that HW and firmware support
30220 * vnic state change. Host drivers can change the vnic state using
30221 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
30222 * support this feature.
30224 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \
30227 * When this bit is '1', it indicates that firmware supports
30228 * virtio-net functions default VNIC allocation using
30230 * This capability is available only on Proxy VEE PF. If set to '0',
30231 * firmware does not support this feature.
30233 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \
30236 * When this bit is set '1', then the capability to configure the
30237 * metadata format in the RX completion is supported for the VNIC.
30238 * When this bit is set to '0', then the capability to configure
30239 * the metadata format in the RX completion is not supported for
30242 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \
30245 * This field advertises the maximum concurrent TPA aggregations
30246 * supported by the VNIC on new devices that support TPA v2.
30247 * '0' means that TPA v2 is not supported.
30249 uint16_t max_aggs_supported;
30250 uint8_t unused_1[5];
30252 * This field is used in Output records to indicate that the output
30253 * is completely written to RAM. This field should be read as '1'
30254 * to indicate that the output has been completely written.
30255 * When writing a command completion or response to an internal processor,
30256 * the order of writes has to be such that this field is written last.
30261 /*********************
30262 * hwrm_vnic_tpa_cfg *
30263 *********************/
30266 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
30267 struct hwrm_vnic_tpa_cfg_input {
30268 /* The HWRM command request type. */
30271 * The completion ring to send the completion event on. This should
30272 * be the NQ ID returned from the `nq_alloc` HWRM command.
30274 uint16_t cmpl_ring;
30276 * The sequence ID is used by the driver for tracking multiple
30277 * commands. This ID is treated as opaque data by the firmware and
30278 * the value is returned in the `hwrm_resp_hdr` upon completion.
30282 * The target ID of the command:
30283 * * 0x0-0xFFF8 - The function ID
30284 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30285 * * 0xFFFD - Reserved for user-space HWRM interface
30288 uint16_t target_id;
30290 * A physical address pointer pointing to a host buffer that the
30291 * command's response data will be written. This can be either a host
30292 * physical address (HPA) or a guest physical address (GPA) and must
30293 * point to a physically contiguous block of memory.
30295 uint64_t resp_addr;
30298 * When this bit is '1', the VNIC shall be configured to
30299 * perform transparent packet aggregation (TPA) of
30300 * non-tunneled TCP packets.
30302 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
30305 * When this bit is '1', the VNIC shall be configured to
30306 * perform transparent packet aggregation (TPA) of
30307 * tunneled TCP packets.
30309 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
30312 * When this bit is '1', the VNIC shall be configured to
30313 * perform transparent packet aggregation (TPA) according
30314 * to Windows Receive Segment Coalescing (RSC) rules.
30316 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
30319 * When this bit is '1', the VNIC shall be configured to
30320 * perform transparent packet aggregation (TPA) according
30321 * to Linux Generic Receive Offload (GRO) rules.
30323 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
30326 * When this bit is '1', the VNIC shall be configured to
30327 * perform transparent packet aggregation (TPA) for TCP
30328 * packets with IP ECN set to non-zero.
30330 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
30333 * When this bit is '1', the VNIC shall be configured to
30334 * perform transparent packet aggregation (TPA) for
30335 * GRE tunneled TCP packets only if all packets have the
30336 * same GRE sequence.
30338 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
30341 * When this bit is '1' and the GRO mode is enabled,
30342 * the VNIC shall be configured to
30343 * perform transparent packet aggregation (TPA) for
30344 * TCP/IPv4 packets with consecutively increasing IPIDs.
30345 * In other words, the last packet that is being
30346 * aggregated to an already existing aggregation context
30347 * shall have IPID 1 more than the IPID of the last packet
30348 * that was aggregated in that aggregation context.
30350 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
30353 * When this bit is '1' and the GRO mode is enabled,
30354 * the VNIC shall be configured to
30355 * perform transparent packet aggregation (TPA) for
30356 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
30359 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
30362 * When this bit is '1' and the GRO mode is enabled,
30363 * the VNIC shall DMA payload data using GRO rules.
30364 * When this bit is '0', the VNIC shall DMA payload data
30365 * using the more efficient LRO rules of filling all
30366 * aggregation buffers.
30368 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
30372 * This bit must be '1' for the max_agg_segs field to be
30375 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
30377 * This bit must be '1' for the max_aggs field to be
30380 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
30382 * This bit must be '1' for the max_agg_timer field to be
30385 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
30386 /* deprecated bit. Do not use!!! */
30387 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
30388 /* Logical vnic ID */
30391 * This is the maximum number of TCP segments that can
30392 * be aggregated (unit is Log2). Max value is 31. On new
30393 * devices supporting TPA v2, the unit is multiples of 4 and
30394 * valid values are > 0 and <= 63.
30396 uint16_t max_agg_segs;
30398 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
30400 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
30402 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
30404 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
30405 /* Any segment size larger than this is not valid */
30406 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
30407 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
30408 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
30410 * This is the maximum number of aggregations this VNIC is
30411 * allowed (unit is Log2). Max value is 7. On new devices
30412 * supporting TPA v2, this is in unit of 1 and must be > 0
30413 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
30414 * to enable TPA v2.
30417 /* 1 aggregation */
30418 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
30419 /* 2 aggregations */
30420 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
30421 /* 4 aggregations */
30422 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
30423 /* 8 aggregations */
30424 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
30425 /* 16 aggregations */
30426 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
30427 /* Any aggregation size larger than this is not valid */
30428 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
30429 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
30430 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
30431 uint8_t unused_0[2];
30433 * This is the maximum amount of time allowed for
30434 * an aggregation context to complete after it was initiated.
30436 uint32_t max_agg_timer;
30438 * This is the minimum amount of payload length required to
30439 * start an aggregation context. This field is deprecated and
30440 * should be set to 0. The minimum length is set by firmware
30441 * and can be queried using hwrm_vnic_tpa_qcfg.
30443 uint32_t min_agg_len;
30446 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
30447 struct hwrm_vnic_tpa_cfg_output {
30448 /* The specific error status for the command. */
30449 uint16_t error_code;
30450 /* The HWRM command request type. */
30452 /* The sequence ID from the original command. */
30454 /* The length of the response data in number of bytes. */
30456 uint8_t unused_0[7];
30458 * This field is used in Output records to indicate that the output
30459 * is completely written to RAM. This field should be read as '1'
30460 * to indicate that the output has been completely written.
30461 * When writing a command completion or response to an internal processor,
30462 * the order of writes has to be such that this field is written last.
30467 /*********************
30468 * hwrm_vnic_rss_cfg *
30469 *********************/
30472 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
30473 struct hwrm_vnic_rss_cfg_input {
30474 /* The HWRM command request type. */
30477 * The completion ring to send the completion event on. This should
30478 * be the NQ ID returned from the `nq_alloc` HWRM command.
30480 uint16_t cmpl_ring;
30482 * The sequence ID is used by the driver for tracking multiple
30483 * commands. This ID is treated as opaque data by the firmware and
30484 * the value is returned in the `hwrm_resp_hdr` upon completion.
30488 * The target ID of the command:
30489 * * 0x0-0xFFF8 - The function ID
30490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30491 * * 0xFFFD - Reserved for user-space HWRM interface
30494 uint16_t target_id;
30496 * A physical address pointer pointing to a host buffer that the
30497 * command's response data will be written. This can be either a host
30498 * physical address (HPA) or a guest physical address (GPA) and must
30499 * point to a physically contiguous block of memory.
30501 uint64_t resp_addr;
30502 uint32_t hash_type;
30504 * When this bit is '1', the RSS hash shall be computed
30505 * over source and destination IPv4 addresses of IPv4
30508 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
30510 * When this bit is '1', the RSS hash shall be computed
30511 * over source/destination IPv4 addresses and
30512 * source/destination ports of TCP/IPv4 packets.
30514 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
30516 * When this bit is '1', the RSS hash shall be computed
30517 * over source/destination IPv4 addresses and
30518 * source/destination ports of UDP/IPv4 packets.
30520 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
30522 * When this bit is '1', the RSS hash shall be computed
30523 * over source and destination IPv4 addresses of IPv6
30526 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
30528 * When this bit is '1', the RSS hash shall be computed
30529 * over source/destination IPv6 addresses and
30530 * source/destination ports of TCP/IPv6 packets.
30532 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
30534 * When this bit is '1', the RSS hash shall be computed
30535 * over source/destination IPv6 addresses and
30536 * source/destination ports of UDP/IPv6 packets.
30538 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
30539 /* VNIC ID of VNIC associated with RSS table being configured. */
30542 * Specifies which VNIC ring table pair to configure.
30543 * Valid values range from 0 to 7.
30545 uint8_t ring_table_pair_index;
30546 /* Flags to specify different RSS hash modes. */
30547 uint8_t hash_mode_flags;
30549 * When this bit is '1', it indicates using current RSS
30550 * hash mode setting configured in the device.
30552 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
30555 * When this bit is '1', it indicates requesting support of
30556 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
30557 * l4.src, l4.dest} for tunnel packets. For none-tunnel
30558 * packets, the RSS hash is computed over the normal
30559 * src/dest l3 and src/dest l4 headers.
30561 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
30564 * When this bit is '1', it indicates requesting support of
30565 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
30566 * tunnel packets. For none-tunnel packets, the RSS hash is
30567 * computed over the normal src/dest l3 headers.
30569 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
30572 * When this bit is '1', it indicates requesting support of
30573 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
30574 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
30575 * packets, the RSS hash is computed over the normal
30576 * src/dest l3 and src/dest l4 headers.
30578 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
30581 * When this bit is '1', it indicates requesting support of
30582 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
30583 * tunnel packets. For none-tunnel packets, the RSS hash is
30584 * computed over the normal src/dest l3 headers.
30586 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
30588 /* This is the address for rss ring group table */
30589 uint64_t ring_grp_tbl_addr;
30590 /* This is the address for rss hash key table */
30591 uint64_t hash_key_tbl_addr;
30592 /* Index to the rss indirection table. */
30593 uint16_t rss_ctx_idx;
30594 uint8_t unused_1[6];
30597 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
30598 struct hwrm_vnic_rss_cfg_output {
30599 /* The specific error status for the command. */
30600 uint16_t error_code;
30601 /* The HWRM command request type. */
30603 /* The sequence ID from the original command. */
30605 /* The length of the response data in number of bytes. */
30607 uint8_t unused_0[7];
30609 * This field is used in Output records to indicate that the output
30610 * is completely written to RAM. This field should be read as '1'
30611 * to indicate that the output has been completely written.
30612 * When writing a command completion or response to an internal processor,
30613 * the order of writes has to be such that this field is written last.
30618 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
30619 struct hwrm_vnic_rss_cfg_cmd_err {
30621 * command specific error codes that goes to
30622 * the cmd_err field in Common HWRM Error Response.
30625 /* Unknown error */
30626 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
30629 * Unable to change global RSS mode to outer due to all active
30630 * interfaces are not ready to support outer RSS hashing.
30632 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
30634 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
30635 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
30636 uint8_t unused_0[7];
30639 /**********************
30640 * hwrm_vnic_rss_qcfg *
30641 **********************/
30644 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
30645 struct hwrm_vnic_rss_qcfg_input {
30646 /* The HWRM command request type. */
30649 * The completion ring to send the completion event on. This should
30650 * be the NQ ID returned from the `nq_alloc` HWRM command.
30652 uint16_t cmpl_ring;
30654 * The sequence ID is used by the driver for tracking multiple
30655 * commands. This ID is treated as opaque data by the firmware and
30656 * the value is returned in the `hwrm_resp_hdr` upon completion.
30660 * The target ID of the command:
30661 * * 0x0-0xFFF8 - The function ID
30662 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30663 * * 0xFFFD - Reserved for user-space HWRM interface
30666 uint16_t target_id;
30668 * A physical address pointer pointing to a host buffer that the
30669 * command's response data will be written. This can be either a host
30670 * physical address (HPA) or a guest physical address (GPA) and must
30671 * point to a physically contiguous block of memory.
30673 uint64_t resp_addr;
30674 /* Index to the rss indirection table. */
30675 uint16_t rss_ctx_idx;
30676 uint8_t unused_0[6];
30679 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
30680 struct hwrm_vnic_rss_qcfg_output {
30681 /* The specific error status for the command. */
30682 uint16_t error_code;
30683 /* The HWRM command request type. */
30685 /* The sequence ID from the original command. */
30687 /* The length of the response data in number of bytes. */
30689 uint32_t hash_type;
30691 * When this bit is '1', the RSS hash shall be computed
30692 * over source and destination IPv4 addresses of IPv4
30695 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
30697 * When this bit is '1', the RSS hash shall be computed
30698 * over source/destination IPv4 addresses and
30699 * source/destination ports of TCP/IPv4 packets.
30701 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
30703 * When this bit is '1', the RSS hash shall be computed
30704 * over source/destination IPv4 addresses and
30705 * source/destination ports of UDP/IPv4 packets.
30707 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
30709 * When this bit is '1', the RSS hash shall be computed
30710 * over source and destination IPv4 addresses of IPv6
30713 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
30715 * When this bit is '1', the RSS hash shall be computed
30716 * over source/destination IPv6 addresses and
30717 * source/destination ports of TCP/IPv6 packets.
30719 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
30721 * When this bit is '1', the RSS hash shall be computed
30722 * over source/destination IPv6 addresses and
30723 * source/destination ports of UDP/IPv6 packets.
30725 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
30726 uint8_t unused_0[4];
30727 /* This is the value of rss hash key */
30728 uint32_t hash_key[10];
30729 /* Flags to specify different RSS hash modes. */
30730 uint8_t hash_mode_flags;
30732 * When this bit is '1', it indicates using current RSS
30733 * hash mode setting configured in the device.
30735 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
30738 * When this bit is '1', it indicates requesting support of
30739 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
30740 * l4.src, l4.dest} for tunnel packets. For none-tunnel
30741 * packets, the RSS hash is computed over the normal
30742 * src/dest l3 and src/dest l4 headers.
30744 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
30747 * When this bit is '1', it indicates requesting support of
30748 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
30749 * tunnel packets. For none-tunnel packets, the RSS hash is
30750 * computed over the normal src/dest l3 headers.
30752 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
30755 * When this bit is '1', it indicates requesting support of
30756 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
30757 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
30758 * packets, the RSS hash is computed over the normal
30759 * src/dest l3 and src/dest l4 headers.
30761 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
30764 * When this bit is '1', it indicates requesting support of
30765 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
30766 * tunnel packets. For none-tunnel packets, the RSS hash is
30767 * computed over the normal src/dest l3 headers.
30769 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
30771 uint8_t unused_1[6];
30773 * This field is used in Output records to indicate that the output
30774 * is completely written to RAM. This field should be read as '1'
30775 * to indicate that the output has been completely written.
30776 * When writing a command completion or response to an internal processor,
30777 * the order of writes has to be such that this field is written last.
30782 /**************************
30783 * hwrm_vnic_plcmodes_cfg *
30784 **************************/
30787 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
30788 struct hwrm_vnic_plcmodes_cfg_input {
30789 /* The HWRM command request type. */
30792 * The completion ring to send the completion event on. This should
30793 * be the NQ ID returned from the `nq_alloc` HWRM command.
30795 uint16_t cmpl_ring;
30797 * The sequence ID is used by the driver for tracking multiple
30798 * commands. This ID is treated as opaque data by the firmware and
30799 * the value is returned in the `hwrm_resp_hdr` upon completion.
30803 * The target ID of the command:
30804 * * 0x0-0xFFF8 - The function ID
30805 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30806 * * 0xFFFD - Reserved for user-space HWRM interface
30809 uint16_t target_id;
30811 * A physical address pointer pointing to a host buffer that the
30812 * command's response data will be written. This can be either a host
30813 * physical address (HPA) or a guest physical address (GPA) and must
30814 * point to a physically contiguous block of memory.
30816 uint64_t resp_addr;
30819 * When this bit is '1', the VNIC shall be configured to
30820 * use regular placement algorithm.
30821 * By default, the regular placement algorithm shall be
30822 * enabled on the VNIC.
30824 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
30827 * When this bit is '1', the VNIC shall be configured
30828 * use the jumbo placement algorithm.
30830 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
30833 * When this bit is '1', the VNIC shall be configured
30834 * to enable Header-Data split for IPv4 packets according
30835 * to the following rules:
30836 * # If the packet is identified as TCP/IPv4, then the
30837 * packet is split at the beginning of the TCP payload.
30838 * # If the packet is identified as UDP/IPv4, then the
30839 * packet is split at the beginning of UDP payload.
30840 * # If the packet is identified as non-TCP and non-UDP
30841 * IPv4 packet, then the packet is split at the beginning
30842 * of the upper layer protocol header carried in the IPv4
30845 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
30848 * When this bit is '1', the VNIC shall be configured
30849 * to enable Header-Data split for IPv6 packets according
30850 * to the following rules:
30851 * # If the packet is identified as TCP/IPv6, then the
30852 * packet is split at the beginning of the TCP payload.
30853 * # If the packet is identified as UDP/IPv6, then the
30854 * packet is split at the beginning of UDP payload.
30855 * # If the packet is identified as non-TCP and non-UDP
30856 * IPv6 packet, then the packet is split at the beginning
30857 * of the upper layer protocol header carried in the IPv6
30860 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
30863 * When this bit is '1', the VNIC shall be configured
30864 * to enable Header-Data split for FCoE packets at the
30865 * beginning of FC payload.
30867 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
30870 * When this bit is '1', the VNIC shall be configured
30871 * to enable Header-Data split for RoCE packets at the
30872 * beginning of RoCE payload (after BTH/GRH headers).
30874 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
30877 * When this bit is '1', the VNIC shall be configured use the virtio
30878 * placement algorithm. This feature can only be configured when
30879 * proxy mode is supported on the function.
30881 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
30885 * This bit must be '1' for the jumbo_thresh_valid field to be
30888 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
30891 * This bit must be '1' for the hds_offset_valid field to be
30894 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
30897 * This bit must be '1' for the hds_threshold_valid field to be
30900 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
30903 * This bit must be '1' for the max_bds_valid field to be
30906 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
30908 /* Logical vnic ID */
30911 * When jumbo placement algorithm is enabled, this value
30912 * is used to determine the threshold for jumbo placement.
30913 * Packets with length larger than this value will be
30914 * placed according to the jumbo placement algorithm.
30916 uint16_t jumbo_thresh;
30918 * This value is used to determine the offset into
30919 * packet buffer where the split data (payload) will be
30920 * placed according to one of HDS placement algorithm.
30922 * The lengths of packet buffers provided for split data
30923 * shall be larger than this value.
30925 uint16_t hds_offset;
30927 * When one of the HDS placement algorithm is enabled, this
30928 * value is used to determine the threshold for HDS
30930 * Packets with length larger than this value will be
30931 * placed according to the HDS placement algorithm.
30932 * This value shall be in multiple of 4 bytes.
30934 uint16_t hds_threshold;
30936 * When virtio placement algorithm is enabled, this
30937 * value is used to determine the maximum number of BDs
30938 * that can be used to place an Rx Packet.
30939 * If an incoming packet does not fit in the buffers described
30940 * by the max BDs, the packet will be dropped and an error
30941 * will be reported in the completion. Valid values for this
30942 * field are between 1 and 8. If the VNIC uses header-data-
30943 * separation and/or TPA with buffer spanning enabled, valid
30944 * values for this field are between 2 and 8.
30945 * This feature can only be configured when proxy mode is
30946 * supported on the function.
30949 uint8_t unused_0[4];
30952 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
30953 struct hwrm_vnic_plcmodes_cfg_output {
30954 /* The specific error status for the command. */
30955 uint16_t error_code;
30956 /* The HWRM command request type. */
30958 /* The sequence ID from the original command. */
30960 /* The length of the response data in number of bytes. */
30962 uint8_t unused_0[7];
30964 * This field is used in Output records to indicate that the output
30965 * is completely written to RAM. This field should be read as '1'
30966 * to indicate that the output has been completely written.
30967 * When writing a command completion or response to an internal
30968 * processor, the order of writes has to be such that this field is
30974 /***************************
30975 * hwrm_vnic_plcmodes_qcfg *
30976 ***************************/
30979 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
30980 struct hwrm_vnic_plcmodes_qcfg_input {
30981 /* The HWRM command request type. */
30984 * The completion ring to send the completion event on. This should
30985 * be the NQ ID returned from the `nq_alloc` HWRM command.
30987 uint16_t cmpl_ring;
30989 * The sequence ID is used by the driver for tracking multiple
30990 * commands. This ID is treated as opaque data by the firmware and
30991 * the value is returned in the `hwrm_resp_hdr` upon completion.
30995 * The target ID of the command:
30996 * * 0x0-0xFFF8 - The function ID
30997 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30998 * * 0xFFFD - Reserved for user-space HWRM interface
31001 uint16_t target_id;
31003 * A physical address pointer pointing to a host buffer that the
31004 * command's response data will be written. This can be either a host
31005 * physical address (HPA) or a guest physical address (GPA) and must
31006 * point to a physically contiguous block of memory.
31008 uint64_t resp_addr;
31009 /* Logical vnic ID */
31011 uint8_t unused_0[4];
31014 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
31015 struct hwrm_vnic_plcmodes_qcfg_output {
31016 /* The specific error status for the command. */
31017 uint16_t error_code;
31018 /* The HWRM command request type. */
31020 /* The sequence ID from the original command. */
31022 /* The length of the response data in number of bytes. */
31026 * When this bit is '1', the VNIC is configured to
31027 * use regular placement algorithm.
31029 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
31032 * When this bit is '1', the VNIC is configured to
31033 * use the jumbo placement algorithm.
31035 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
31038 * When this bit is '1', the VNIC is configured
31039 * to enable Header-Data split for IPv4 packets.
31041 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
31044 * When this bit is '1', the VNIC is configured
31045 * to enable Header-Data split for IPv6 packets.
31047 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
31050 * When this bit is '1', the VNIC is configured
31051 * to enable Header-Data split for FCoE packets.
31053 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
31056 * When this bit is '1', the VNIC is configured
31057 * to enable Header-Data split for RoCE packets.
31059 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
31062 * When this bit is '1', the VNIC is configured
31063 * to be the default VNIC of the requesting function.
31065 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
31068 * When this bit is '1', the VNIC is configured to use the virtio
31069 * placement algorithm. This feature can only be configured when
31070 * proxy mode is supported on the function.
31072 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
31075 * When jumbo placement algorithm is enabled, this value
31076 * is used to determine the threshold for jumbo placement.
31077 * Packets with length larger than this value will be
31078 * placed according to the jumbo placement algorithm.
31080 uint16_t jumbo_thresh;
31082 * This value is used to determine the offset into
31083 * packet buffer where the split data (payload) will be
31084 * placed according to one of HDS placement algorithm.
31086 * The lengths of packet buffers provided for split data
31087 * shall be larger than this value.
31089 uint16_t hds_offset;
31091 * When one of the HDS placement algorithm is enabled, this
31092 * value is used to determine the threshold for HDS
31094 * Packets with length larger than this value will be
31095 * placed according to the HDS placement algorithm.
31096 * This value shall be in multiple of 4 bytes.
31098 uint16_t hds_threshold;
31100 * When virtio placement algorithm is enabled, this
31101 * value is used to determine the maximum number of BDs
31102 * that can be used to place an Rx Packet.
31103 * If an incoming packet does not fit in the buffers described
31104 * by the max BDs, the packet will be dropped and an error
31105 * will be reported in the completion. Valid values for this
31106 * field are between 1 and 8. If the VNIC uses header-data-
31107 * separation and/or TPA with buffer spanning enabled, valid
31108 * values for this field are between 2 and 8.
31109 * This feature can only be configured when proxy mode is supported
31113 uint8_t unused_0[3];
31115 * This field is used in Output records to indicate that the output
31116 * is completely written to RAM. This field should be read as '1'
31117 * to indicate that the output has been completely written.
31118 * When writing a command completion or response to an internal
31119 * processor, the order of writes has to be such that this field is
31125 /**********************************
31126 * hwrm_vnic_rss_cos_lb_ctx_alloc *
31127 **********************************/
31130 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
31131 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
31132 /* The HWRM command request type. */
31135 * The completion ring to send the completion event on. This should
31136 * be the NQ ID returned from the `nq_alloc` HWRM command.
31138 uint16_t cmpl_ring;
31140 * The sequence ID is used by the driver for tracking multiple
31141 * commands. This ID is treated as opaque data by the firmware and
31142 * the value is returned in the `hwrm_resp_hdr` upon completion.
31146 * The target ID of the command:
31147 * * 0x0-0xFFF8 - The function ID
31148 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31149 * * 0xFFFD - Reserved for user-space HWRM interface
31152 uint16_t target_id;
31154 * A physical address pointer pointing to a host buffer that the
31155 * command's response data will be written. This can be either a host
31156 * physical address (HPA) or a guest physical address (GPA) and must
31157 * point to a physically contiguous block of memory.
31159 uint64_t resp_addr;
31162 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
31163 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
31164 /* The specific error status for the command. */
31165 uint16_t error_code;
31166 /* The HWRM command request type. */
31168 /* The sequence ID from the original command. */
31170 /* The length of the response data in number of bytes. */
31172 /* rss_cos_lb_ctx_id is 16 b */
31173 uint16_t rss_cos_lb_ctx_id;
31174 uint8_t unused_0[5];
31176 * This field is used in Output records to indicate that the output
31177 * is completely written to RAM. This field should be read as '1'
31178 * to indicate that the output has been completely written.
31179 * When writing a command completion or response to an internal processor,
31180 * the order of writes has to be such that this field is written last.
31185 /*********************************
31186 * hwrm_vnic_rss_cos_lb_ctx_free *
31187 *********************************/
31190 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
31191 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
31192 /* The HWRM command request type. */
31195 * The completion ring to send the completion event on. This should
31196 * be the NQ ID returned from the `nq_alloc` HWRM command.
31198 uint16_t cmpl_ring;
31200 * The sequence ID is used by the driver for tracking multiple
31201 * commands. This ID is treated as opaque data by the firmware and
31202 * the value is returned in the `hwrm_resp_hdr` upon completion.
31206 * The target ID of the command:
31207 * * 0x0-0xFFF8 - The function ID
31208 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31209 * * 0xFFFD - Reserved for user-space HWRM interface
31212 uint16_t target_id;
31214 * A physical address pointer pointing to a host buffer that the
31215 * command's response data will be written. This can be either a host
31216 * physical address (HPA) or a guest physical address (GPA) and must
31217 * point to a physically contiguous block of memory.
31219 uint64_t resp_addr;
31220 /* rss_cos_lb_ctx_id is 16 b */
31221 uint16_t rss_cos_lb_ctx_id;
31222 uint8_t unused_0[6];
31225 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
31226 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
31227 /* The specific error status for the command. */
31228 uint16_t error_code;
31229 /* The HWRM command request type. */
31231 /* The sequence ID from the original command. */
31233 /* The length of the response data in number of bytes. */
31235 uint8_t unused_0[7];
31237 * This field is used in Output records to indicate that the output
31238 * is completely written to RAM. This field should be read as '1'
31239 * to indicate that the output has been completely written.
31240 * When writing a command completion or response to an internal processor,
31241 * the order of writes has to be such that this field is written last.
31246 /*******************
31247 * hwrm_ring_alloc *
31248 *******************/
31251 /* hwrm_ring_alloc_input (size:704b/88B) */
31252 struct hwrm_ring_alloc_input {
31253 /* The HWRM command request type. */
31256 * The completion ring to send the completion event on. This should
31257 * be the NQ ID returned from the `nq_alloc` HWRM command.
31259 uint16_t cmpl_ring;
31261 * The sequence ID is used by the driver for tracking multiple
31262 * commands. This ID is treated as opaque data by the firmware and
31263 * the value is returned in the `hwrm_resp_hdr` upon completion.
31267 * The target ID of the command:
31268 * * 0x0-0xFFF8 - The function ID
31269 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31270 * * 0xFFFD - Reserved for user-space HWRM interface
31273 uint16_t target_id;
31275 * A physical address pointer pointing to a host buffer that the
31276 * command's response data will be written. This can be either a host
31277 * physical address (HPA) or a guest physical address (GPA) and must
31278 * point to a physically contiguous block of memory.
31280 uint64_t resp_addr;
31283 * This bit must be '1' for the ring_arb_cfg field to be
31286 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
31289 * This bit must be '1' for the stat_ctx_id_valid field to be
31292 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
31295 * This bit must be '1' for the max_bw_valid field to be
31298 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
31301 * This bit must be '1' for the rx_ring_id field to be
31304 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
31307 * This bit must be '1' for the nq_ring_id field to be
31310 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
31313 * This bit must be '1' for the rx_buf_size field to be
31316 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
31319 * This bit must be '1' for the schq_id field to be
31322 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID \
31325 * This bit must be '1' for the mpc_chnls_type field to be
31328 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE \
31332 /* L2 Completion Ring (CR) */
31333 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31335 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
31337 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
31338 /* RoCE Notification Completion Ring (ROCE_CR) */
31339 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31340 /* RX Aggregation Ring */
31341 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
31342 /* Notification Queue */
31343 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
31344 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
31345 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
31347 /* Ring allocation flags. */
31350 * For Rx rings, the incoming packet data can be placed at either
31351 * a 0B or 2B offset from the start of the Rx packet buffer. When
31352 * '1', the received packet will be padded with 2B of zeros at the
31353 * front of the packet. Note that this flag is only used for
31354 * Rx rings and is ignored for all other rings included Rx
31355 * Aggregation rings.
31357 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
31359 * This value is a pointer to the page table for the
31362 uint64_t page_tbl_addr;
31363 /* First Byte Offset of the first entry in the first page. */
31366 * Actual page size in 2^page_size. The supported range is increments
31367 * in powers of 2 from 16 bytes to 1GB.
31369 * Page size is 16 B.
31371 * Page size is 4 KB.
31373 * Page size is 8 KB.
31375 * Page size is 64 KB.
31377 * Page size is 2 MB.
31379 * Page size is 4 MB.
31381 * Page size is 1 GB.
31385 * This value indicates the depth of page table.
31386 * For this version of the specification, value other than 0 or
31387 * 1 shall be considered as an invalid value.
31388 * When the page_tbl_depth = 0, then it is treated as a
31389 * special case with the following.
31390 * 1. FBO and page size fields are not valid.
31391 * 2. page_tbl_addr is the physical address of the first
31392 * element of the ring.
31394 uint8_t page_tbl_depth;
31395 /* Used by a PF driver to associate a SCHQ with one of its TX rings. */
31398 * Number of 16B units in the ring. Minimum size for
31399 * a ring is 16 16B entries.
31403 * Logical ring number for the ring to be allocated.
31404 * This value determines the position in the doorbell
31405 * area where the update to the ring will be made.
31407 * For completion rings, this value is also the MSI-X
31408 * vector number for the function the completion ring is
31411 uint16_t logical_id;
31413 * This field is used only when ring_type is a TX ring.
31414 * This value indicates what completion ring the TX ring
31415 * is associated with.
31417 uint16_t cmpl_ring_id;
31419 * This field is used only when ring_type is a TX ring.
31420 * This value indicates what CoS queue the TX ring
31421 * is associated with.
31425 * When allocating a Rx ring or Rx aggregation ring, this field
31426 * specifies the size of the buffer descriptors posted to the ring.
31428 uint16_t rx_buf_size;
31430 * When allocating an Rx aggregation ring, this field
31431 * specifies the associated Rx ring ID.
31433 uint16_t rx_ring_id;
31435 * When allocating a completion ring, this field
31436 * specifies the associated NQ ring ID.
31438 uint16_t nq_ring_id;
31440 * This field is used only when ring_type is a TX ring.
31441 * This field is used to configure arbitration related
31442 * parameters for a TX ring.
31444 uint16_t ring_arb_cfg;
31445 /* Arbitration policy used for the ring. */
31446 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
31448 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
31450 * Use strict priority for the TX ring.
31451 * Priority value is specified in arb_policy_param
31453 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
31456 * Use weighted fair queue arbitration for the TX ring.
31457 * Weight is specified in arb_policy_param
31459 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
31461 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
31462 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
31463 /* Reserved field. */
31464 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
31466 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
31468 * Arbitration policy specific parameter.
31469 * # For strict priority arbitration policy, this field
31470 * represents a priority value. If set to 0, then the priority
31471 * is not specified and the HWRM is allowed to select
31472 * any priority for this TX ring.
31473 * # For weighted fair queue arbitration policy, this field
31474 * represents a weight value. If set to 0, then the weight
31475 * is not specified and the HWRM is allowed to select
31476 * any weight for this TX ring.
31478 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
31480 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
31483 * This field is reserved for the future use.
31484 * It shall be set to 0.
31486 uint32_t reserved3;
31488 * This field is used only when ring_type is a TX ring.
31489 * This input indicates what statistics context this ring
31490 * should be associated with.
31492 uint32_t stat_ctx_id;
31494 * This field is reserved for the future use.
31495 * It shall be set to 0.
31497 uint32_t reserved4;
31499 * This field is used only when ring_type is a TX ring
31500 * to specify maximum BW allocated to the TX ring.
31501 * The HWRM will translate this value into byte counter and
31502 * time interval used for this ring inside the device.
31505 /* The bandwidth value. */
31506 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
31507 UINT32_C(0xfffffff)
31508 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
31509 /* The granularity of the value (bits or bytes). */
31510 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
31511 UINT32_C(0x10000000)
31512 /* Value is in bits. */
31513 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
31514 (UINT32_C(0x0) << 28)
31515 /* Value is in bytes. */
31516 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
31517 (UINT32_C(0x1) << 28)
31518 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
31519 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
31520 /* bw_value_unit is 3 b */
31521 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
31522 UINT32_C(0xe0000000)
31523 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
31524 /* Value is in Mb or MB (base 10). */
31525 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
31526 (UINT32_C(0x0) << 29)
31527 /* Value is in Kb or KB (base 10). */
31528 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
31529 (UINT32_C(0x2) << 29)
31530 /* Value is in bits or bytes. */
31531 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
31532 (UINT32_C(0x4) << 29)
31533 /* Value is in Gb or GB (base 10). */
31534 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
31535 (UINT32_C(0x6) << 29)
31536 /* Value is in 1/100th of a percentage of total bandwidth. */
31537 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
31538 (UINT32_C(0x1) << 29)
31540 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
31541 (UINT32_C(0x7) << 29)
31542 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
31543 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
31545 * This field is used only when ring_type is a Completion ring.
31546 * This value indicates what interrupt mode should be used
31547 * on this completion ring.
31548 * Note: In the legacy interrupt mode, no more than 16
31549 * completion rings are allowed.
31553 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
31555 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
31557 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
31558 /* No Interrupt - Polled mode */
31559 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
31560 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
31561 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
31562 /* Midpath channel type */
31563 uint8_t mpc_chnls_type;
31565 * Indicate the TX ring alloc MPC channel type is a MPC channel
31566 * with destination to the TX crypto engine block.
31568 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
31570 * Indicate the RX ring alloc MPC channel type is a MPC channel
31571 * with destination to the RX crypto engine block.
31573 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
31575 * Indicate the RX ring alloc MPC channel type is a MPC channel
31576 * with destination to the TX configurable flow processing block.
31578 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
31580 * Indicate the RX ring alloc MPC channel type is a MPC channel
31581 * with destination to the RX configurable flow processing block.
31583 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
31585 * Indicate the RX ring alloc MPC channel type is a MPC channel
31586 * with destination to the primate processor block.
31588 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
31589 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_LAST \
31590 HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE
31591 uint8_t unused_4[2];
31593 * The cq_handle is specified when allocating a completion ring. For
31594 * devices that support NQs, this cq_handle will be included in the
31595 * NQE to specify which CQ should be read to retrieve the completion
31598 uint64_t cq_handle;
31601 /* hwrm_ring_alloc_output (size:128b/16B) */
31602 struct hwrm_ring_alloc_output {
31603 /* The specific error status for the command. */
31604 uint16_t error_code;
31605 /* The HWRM command request type. */
31607 /* The sequence ID from the original command. */
31609 /* The length of the response data in number of bytes. */
31612 * Physical number of ring allocated.
31613 * This value shall be unique for a ring type.
31616 /* Logical number of ring allocated. */
31617 uint16_t logical_ring_id;
31619 * This field will tell whether to use ping or pong buffer
31620 * for first push operation.
31622 uint8_t push_buffer_index;
31623 /* Start push from ping buffer index */
31624 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
31626 /* Start push from pong buffer index */
31627 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
31629 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \
31630 HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
31631 uint8_t unused_0[2];
31633 * This field is used in Output records to indicate that the output
31634 * is completely written to RAM. This field should be read as '1'
31635 * to indicate that the output has been completely written.
31636 * When writing a command completion or response to an internal processor,
31637 * the order of writes has to be such that this field is written last.
31642 /******************
31644 ******************/
31647 /* hwrm_ring_free_input (size:192b/24B) */
31648 struct hwrm_ring_free_input {
31649 /* The HWRM command request type. */
31652 * The completion ring to send the completion event on. This should
31653 * be the NQ ID returned from the `nq_alloc` HWRM command.
31655 uint16_t cmpl_ring;
31657 * The sequence ID is used by the driver for tracking multiple
31658 * commands. This ID is treated as opaque data by the firmware and
31659 * the value is returned in the `hwrm_resp_hdr` upon completion.
31663 * The target ID of the command:
31664 * * 0x0-0xFFF8 - The function ID
31665 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31666 * * 0xFFFD - Reserved for user-space HWRM interface
31669 uint16_t target_id;
31671 * A physical address pointer pointing to a host buffer that the
31672 * command's response data will be written. This can be either a host
31673 * physical address (HPA) or a guest physical address (GPA) and must
31674 * point to a physically contiguous block of memory.
31676 uint64_t resp_addr;
31679 /* L2 Completion Ring (CR) */
31680 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31682 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
31684 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
31685 /* RoCE Notification Completion Ring (ROCE_CR) */
31686 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31687 /* RX Aggregation Ring */
31688 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
31689 /* Notification Queue */
31690 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
31691 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
31692 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
31694 /* Physical number of ring allocated. */
31696 uint8_t unused_1[4];
31699 /* hwrm_ring_free_output (size:128b/16B) */
31700 struct hwrm_ring_free_output {
31701 /* The specific error status for the command. */
31702 uint16_t error_code;
31703 /* The HWRM command request type. */
31705 /* The sequence ID from the original command. */
31707 /* The length of the response data in number of bytes. */
31709 uint8_t unused_0[7];
31711 * This field is used in Output records to indicate that the output
31712 * is completely written to RAM. This field should be read as '1'
31713 * to indicate that the output has been completely written.
31714 * When writing a command completion or response to an internal processor,
31715 * the order of writes has to be such that this field is written last.
31720 /*******************
31721 * hwrm_ring_reset *
31722 *******************/
31725 /* hwrm_ring_reset_input (size:192b/24B) */
31726 struct hwrm_ring_reset_input {
31727 /* The HWRM command request type. */
31730 * The completion ring to send the completion event on. This should
31731 * be the NQ ID returned from the `nq_alloc` HWRM command.
31733 uint16_t cmpl_ring;
31735 * The sequence ID is used by the driver for tracking multiple
31736 * commands. This ID is treated as opaque data by the firmware and
31737 * the value is returned in the `hwrm_resp_hdr` upon completion.
31741 * The target ID of the command:
31742 * * 0x0-0xFFF8 - The function ID
31743 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31744 * * 0xFFFD - Reserved for user-space HWRM interface
31747 uint16_t target_id;
31749 * A physical address pointer pointing to a host buffer that the
31750 * command's response data will be written. This can be either a host
31751 * physical address (HPA) or a guest physical address (GPA) and must
31752 * point to a physically contiguous block of memory.
31754 uint64_t resp_addr;
31757 /* L2 Completion Ring (CR) */
31758 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
31760 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
31762 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
31763 /* RoCE Notification Completion Ring (ROCE_CR) */
31764 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
31766 * Rx Ring Group. This is to reset rx and aggregation in an atomic
31767 * operation. Completion ring associated with this ring group is
31770 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
31771 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
31772 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
31775 * Physical number of the ring. When ring type is rx_ring_grp, ring id
31776 * actually refers to ring group id.
31779 uint8_t unused_1[4];
31782 /* hwrm_ring_reset_output (size:128b/16B) */
31783 struct hwrm_ring_reset_output {
31784 /* The specific error status for the command. */
31785 uint16_t error_code;
31786 /* The HWRM command request type. */
31788 /* The sequence ID from the original command. */
31790 /* The length of the response data in number of bytes. */
31793 * This field will tell whether to use ping or pong buffer
31794 * for first push operation.
31796 uint8_t push_buffer_index;
31797 /* Start push from ping buffer index */
31798 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \
31800 /* Start push from pong buffer index */
31801 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \
31803 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \
31804 HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER
31805 uint8_t unused_0[3];
31806 /* Position of consumer index after ring reset completes. */
31807 uint8_t consumer_idx[3];
31809 * This field is used in Output records to indicate that the output
31810 * is completely written to RAM. This field should be read as '1'
31811 * to indicate that the output has been completely written.
31812 * When writing a command completion or response to an internal processor,
31813 * the order of writes has to be such that this field is written last.
31823 /* hwrm_ring_cfg_input (size:320b/40B) */
31824 struct hwrm_ring_cfg_input {
31825 /* The HWRM command request type. */
31828 * The completion ring to send the completion event on. This should
31829 * be the NQ ID returned from the `nq_alloc` HWRM command.
31831 uint16_t cmpl_ring;
31833 * The sequence ID is used by the driver for tracking multiple
31834 * commands. This ID is treated as opaque data by the firmware and
31835 * the value is returned in the `hwrm_resp_hdr` upon completion.
31839 * The target ID of the command:
31840 * * 0x0-0xFFF8 - The function ID
31841 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31842 * * 0xFFFD - Reserved for user-space HWRM interface
31845 uint16_t target_id;
31847 * A physical address pointer pointing to a host buffer that the
31848 * command's response data will be written. This can be either a host
31849 * physical address (HPA) or a guest physical address (GPA) and must
31850 * point to a physically contiguous block of memory.
31852 uint64_t resp_addr;
31856 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
31858 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
31859 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
31860 HWRM_RING_CFG_INPUT_RING_TYPE_RX
31862 /* Physical number of the ring. */
31864 /* Ring config enable bits. */
31867 * For Rx rings, the incoming packet data can be placed at either
31868 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
31870 * When '1', the received packet will be padded with 2B, 10B or 12B
31871 * of zeros at the front of the packet. The exact offset is specified
31872 * by rx_sop_pad_bytes parameter.
31873 * When '0', the received packet will not be padded.
31874 * Note that this flag is only used for Rx rings and is ignored
31875 * for all other rings included Rx Aggregation rings.
31877 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
31880 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
31881 * When rings are allocated, the PCI function on which driver issues
31882 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
31883 * the buffer descriptors (BDs) from those rings is assumed to issue
31884 * packet payload DMA using same PCI function. When proxy mode is
31885 * enabled, hardware can perform payload DMA using another PCI
31886 * function on same or different host.
31887 * When set to '0', the PCI function on which driver issues
31888 * HWRM_RING_CFG command is used for host payload DMA operation.
31889 * When set to '1', the host PCI function specified by proxy_fid is
31890 * used for host payload DMA operation.
31892 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
31895 * Tx ring packet source interface override, for Tx rings only.
31896 * When TX rings are allocated, the PCI function on which driver
31897 * issues HWRM_RING_CFG is assumed to be source interface of
31898 * packets sent from TX ring.
31899 * When set to '1', the host PCI function specified by proxy_fid
31900 * is used as source interface of the transmitted packets.
31902 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
31904 /* The schq_id field is valid */
31905 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID \
31907 /* Update completion ring ID associated with Tx or Rx ring. */
31908 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
31911 * When set to '1', metadata value provided by tx_metadata
31912 * field in this command is inserted in the lb_header_metadata
31913 * QP context field. When set to '0', no change done to metadata.
31914 * Firmware rejects the tx ring metadata programming with
31915 * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD
31916 * metadata feature is not disabled.
31918 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \
31921 * Proxy function FID value.
31922 * This value is only used when either proxy_mode_enable flag or
31923 * tx_proxy_svif_override is set to '1'.
31924 * When proxy_mode_enable is set to '1', it identifies a host PCI
31925 * function used for host payload DMA operations.
31926 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
31927 * function as source interface for all transmitted packets from
31930 uint16_t proxy_fid;
31932 * Identifies the new scheduler queue (SCHQ) to associate with the
31933 * ring. Only valid for Tx rings.
31934 * A value of zero indicates that the Tx ring should be associated
31935 * with the default scheduler queue (SCHQ).
31939 * This field is valid for TX or Rx rings. This value identifies the
31940 * new completion ring ID to associate with the TX or Rx ring.
31942 uint16_t cmpl_ring_id;
31944 * Rx SOP padding amount in bytes.
31945 * This value is only used when rx_sop_pad_enable flag is set to '1'.
31947 uint8_t rx_sop_pad_bytes;
31948 uint8_t unused_1[3];
31950 * When tx_metadata enable bit is set, value specified in this field
31951 * is copied to lb_header_metadata in the QP context.
31953 uint32_t tx_metadata;
31954 uint8_t unused_2[4];
31957 /* hwrm_ring_cfg_output (size:128b/16B) */
31958 struct hwrm_ring_cfg_output {
31959 /* The specific error status for the command. */
31960 uint16_t error_code;
31961 /* The HWRM command request type. */
31963 /* The sequence ID from the original command. */
31965 /* The length of the response data in number of bytes. */
31967 uint8_t unused_0[7];
31969 * This field is used in Output records to indicate that the output
31970 * is completely written to RAM. This field should be read as '1'
31971 * to indicate that the output has been completely written.
31972 * When writing a command completion or response to an internal
31973 * processor, the order of writes has to be such that this field is
31979 /******************
31981 ******************/
31984 /* hwrm_ring_qcfg_input (size:192b/24B) */
31985 struct hwrm_ring_qcfg_input {
31986 /* The HWRM command request type. */
31989 * The completion ring to send the completion event on. This should
31990 * be the NQ ID returned from the `nq_alloc` HWRM command.
31992 uint16_t cmpl_ring;
31994 * The sequence ID is used by the driver for tracking multiple
31995 * commands. This ID is treated as opaque data by the firmware and
31996 * the value is returned in the `hwrm_resp_hdr` upon completion.
32000 * The target ID of the command:
32001 * * 0x0-0xFFF8 - The function ID
32002 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32003 * * 0xFFFD - Reserved for user-space HWRM interface
32006 uint16_t target_id;
32008 * A physical address pointer pointing to a host buffer that the
32009 * command's response data will be written. This can be either a host
32010 * physical address (HPA) or a guest physical address (GPA) and must
32011 * point to a physically contiguous block of memory.
32013 uint64_t resp_addr;
32017 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
32019 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
32020 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
32021 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
32022 uint8_t unused_0[5];
32023 /* Physical number of the ring. */
32027 /* hwrm_ring_qcfg_output (size:256b/32B) */
32028 struct hwrm_ring_qcfg_output {
32029 /* The specific error status for the command. */
32030 uint16_t error_code;
32031 /* The HWRM command request type. */
32033 /* The sequence ID from the original command. */
32035 /* The length of the response data in number of bytes. */
32037 /* Ring config enable bits. */
32040 * For Rx rings, the incoming packet data can be placed at either
32041 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
32043 * When '1', the received packet will be padded with 2B, 10B or 12B
32044 * of zeros at the front of the packet. The exact offset is specified
32045 * by rx_sop_pad_bytes parameter.
32046 * When '0', the received packet will not be padded.
32047 * Note that this flag is only used for Rx rings and is ignored
32048 * for all other rings included Rx Aggregation rings.
32050 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
32053 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
32054 * When rings are allocated, the PCI function on which driver issues
32055 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
32056 * the buffer descriptors (BDs) from those rings is assumed to issue
32057 * packet payload DMA using same PCI function. When proxy mode is
32058 * enabled, hardware can perform payload DMA using another PCI
32059 * function on same or different host.
32060 * When set to '0', the PCI function on which driver issues
32061 * HWRM_RING_CFG command is used for host payload DMA operation.
32062 * When set to '1', the host PCI function specified by proxy_fid is
32063 * used for host payload DMA operation.
32065 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
32068 * Tx ring packet source interface override, for Tx rings only.
32069 * When TX rings are allocated, the PCI function on which driver
32070 * issues HWRM_RING_CFG is assumed to be source interface of
32071 * packets sent from TX ring.
32072 * When set to '1', the host PCI function specified by proxy_fid is
32073 * used as source interface of the transmitted packets.
32075 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
32078 * Proxy function FID value.
32079 * This value is only used when either proxy_mode_enable flag or
32080 * tx_proxy_svif_override is set to '1'.
32081 * When proxy_mode_enable is set to '1', it identifies a host PCI
32082 * function used for host payload DMA operations.
32083 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
32084 * function as source interface for all transmitted packets from the TX
32087 uint16_t proxy_fid;
32089 * Identifies the new scheduler queue (SCHQ) to associate with the
32090 * ring. Only valid for Tx rings.
32091 * A value of zero indicates that the Tx ring should be associated with
32092 * the default scheduler queue (SCHQ).
32096 * This field is used when ring_type is a TX or Rx ring.
32097 * This value indicates what completion ring the TX or Rx ring
32098 * is associated with.
32100 uint16_t cmpl_ring_id;
32102 * Rx SOP padding amount in bytes.
32103 * This value is only used when rx_sop_pad_enable flag is set to '1'.
32105 uint8_t rx_sop_pad_bytes;
32106 uint8_t unused_0[3];
32107 /* lb_header_metadata in the QP context is copied to this field. */
32108 uint32_t tx_metadata;
32109 uint8_t unused_1[7];
32111 * This field is used in Output records to indicate that the output
32112 * is completely written to RAM. This field should be read as '1'
32113 * to indicate that the output has been completely written.
32114 * When writing a command completion or response to an internal
32115 * processor, the order of writes has to be such that this field is
32121 /**************************
32122 * hwrm_ring_aggint_qcaps *
32123 **************************/
32126 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
32127 struct hwrm_ring_aggint_qcaps_input {
32128 /* The HWRM command request type. */
32131 * The completion ring to send the completion event on. This should
32132 * be the NQ ID returned from the `nq_alloc` HWRM command.
32134 uint16_t cmpl_ring;
32136 * The sequence ID is used by the driver for tracking multiple
32137 * commands. This ID is treated as opaque data by the firmware and
32138 * the value is returned in the `hwrm_resp_hdr` upon completion.
32142 * The target ID of the command:
32143 * * 0x0-0xFFF8 - The function ID
32144 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32145 * * 0xFFFD - Reserved for user-space HWRM interface
32148 uint16_t target_id;
32150 * A physical address pointer pointing to a host buffer that the
32151 * command's response data will be written. This can be either a host
32152 * physical address (HPA) or a guest physical address (GPA) and must
32153 * point to a physically contiguous block of memory.
32155 uint64_t resp_addr;
32158 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
32159 struct hwrm_ring_aggint_qcaps_output {
32160 /* The specific error status for the command. */
32161 uint16_t error_code;
32162 /* The HWRM command request type. */
32164 /* The sequence ID from the original command. */
32166 /* The length of the response data in number of bytes. */
32168 uint32_t cmpl_params;
32170 * When this bit is set to '1', int_lat_tmr_min can be configured
32171 * on completion rings.
32173 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
32176 * When this bit is set to '1', int_lat_tmr_max can be configured
32177 * on completion rings.
32179 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
32182 * When this bit is set to '1', timer_reset can be enabled
32183 * on completion rings.
32185 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
32188 * When this bit is set to '1', ring_idle can be enabled
32189 * on completion rings.
32191 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
32194 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
32195 * on completion rings.
32197 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
32200 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
32201 * on completion rings.
32203 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
32206 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
32207 * on completion rings.
32209 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
32212 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
32213 * on completion rings.
32215 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
32218 * When this bit is set to '1', num_cmpl_aggr_int can be configured
32219 * on completion rings.
32221 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
32223 uint32_t nq_params;
32225 * When this bit is set to '1', int_lat_tmr_min can be configured
32226 * on notification queues.
32228 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
32230 /* Minimum value for num_cmpl_dma_aggr */
32231 uint16_t num_cmpl_dma_aggr_min;
32232 /* Maximum value for num_cmpl_dma_aggr */
32233 uint16_t num_cmpl_dma_aggr_max;
32234 /* Minimum value for num_cmpl_dma_aggr_during_int */
32235 uint16_t num_cmpl_dma_aggr_during_int_min;
32236 /* Maximum value for num_cmpl_dma_aggr_during_int */
32237 uint16_t num_cmpl_dma_aggr_during_int_max;
32238 /* Minimum value for cmpl_aggr_dma_tmr */
32239 uint16_t cmpl_aggr_dma_tmr_min;
32240 /* Maximum value for cmpl_aggr_dma_tmr */
32241 uint16_t cmpl_aggr_dma_tmr_max;
32242 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
32243 uint16_t cmpl_aggr_dma_tmr_during_int_min;
32244 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
32245 uint16_t cmpl_aggr_dma_tmr_during_int_max;
32246 /* Minimum value for int_lat_tmr_min */
32247 uint16_t int_lat_tmr_min_min;
32248 /* Maximum value for int_lat_tmr_min */
32249 uint16_t int_lat_tmr_min_max;
32250 /* Minimum value for int_lat_tmr_max */
32251 uint16_t int_lat_tmr_max_min;
32252 /* Maximum value for int_lat_tmr_max */
32253 uint16_t int_lat_tmr_max_max;
32254 /* Minimum value for num_cmpl_aggr_int */
32255 uint16_t num_cmpl_aggr_int_min;
32256 /* Maximum value for num_cmpl_aggr_int */
32257 uint16_t num_cmpl_aggr_int_max;
32258 /* The units for timer parameters, in nanoseconds. */
32259 uint16_t timer_units;
32260 uint8_t unused_0[1];
32262 * This field is used in Output records to indicate that the output
32263 * is completely written to RAM. This field should be read as '1'
32264 * to indicate that the output has been completely written.
32265 * When writing a command completion or response to an internal processor,
32266 * the order of writes has to be such that this field is written last.
32271 /**************************************
32272 * hwrm_ring_cmpl_ring_qaggint_params *
32273 **************************************/
32276 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
32277 struct hwrm_ring_cmpl_ring_qaggint_params_input {
32278 /* The HWRM command request type. */
32281 * The completion ring to send the completion event on. This should
32282 * be the NQ ID returned from the `nq_alloc` HWRM command.
32284 uint16_t cmpl_ring;
32286 * The sequence ID is used by the driver for tracking multiple
32287 * commands. This ID is treated as opaque data by the firmware and
32288 * the value is returned in the `hwrm_resp_hdr` upon completion.
32292 * The target ID of the command:
32293 * * 0x0-0xFFF8 - The function ID
32294 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32295 * * 0xFFFD - Reserved for user-space HWRM interface
32298 uint16_t target_id;
32300 * A physical address pointer pointing to a host buffer that the
32301 * command's response data will be written. This can be either a host
32302 * physical address (HPA) or a guest physical address (GPA) and must
32303 * point to a physically contiguous block of memory.
32305 uint64_t resp_addr;
32306 /* Physical number of completion ring. */
32309 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
32311 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
32313 * Set this flag to 1 when querying parameters on a notification
32314 * queue. Set this flag to 0 when querying parameters on a
32315 * completion queue or completion ring.
32317 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
32319 uint8_t unused_0[4];
32322 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
32323 struct hwrm_ring_cmpl_ring_qaggint_params_output {
32324 /* The specific error status for the command. */
32325 uint16_t error_code;
32326 /* The HWRM command request type. */
32328 /* The sequence ID from the original command. */
32330 /* The length of the response data in number of bytes. */
32334 * When this bit is set to '1', interrupt max
32335 * timer is reset whenever a completion is received.
32337 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
32340 * When this bit is set to '1', ring idle mode
32341 * aggregation will be enabled.
32343 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
32346 * Number of completions to aggregate before DMA
32347 * during the normal mode.
32349 uint16_t num_cmpl_dma_aggr;
32351 * Number of completions to aggregate before DMA
32352 * during the interrupt mode.
32354 uint16_t num_cmpl_dma_aggr_during_int;
32356 * Timer used to aggregate completions before
32357 * DMA during the normal mode (not in interrupt mode).
32359 uint16_t cmpl_aggr_dma_tmr;
32361 * Timer used to aggregate completions before
32362 * DMA when in interrupt mode.
32364 uint16_t cmpl_aggr_dma_tmr_during_int;
32365 /* Minimum time between two interrupts. */
32366 uint16_t int_lat_tmr_min;
32368 * Maximum wait time spent aggregating
32369 * completions before signaling the interrupt after the
32370 * interrupt is enabled.
32372 uint16_t int_lat_tmr_max;
32374 * Minimum number of completions aggregated before signaling
32377 uint16_t num_cmpl_aggr_int;
32378 uint8_t unused_0[7];
32380 * This field is used in Output records to indicate that the output
32381 * is completely written to RAM. This field should be read as '1'
32382 * to indicate that the output has been completely written.
32383 * When writing a command completion or response to an internal processor,
32384 * the order of writes has to be such that this field is written last.
32389 /*****************************************
32390 * hwrm_ring_cmpl_ring_cfg_aggint_params *
32391 *****************************************/
32394 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
32395 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
32396 /* The HWRM command request type. */
32399 * The completion ring to send the completion event on. This should
32400 * be the NQ ID returned from the `nq_alloc` HWRM command.
32402 uint16_t cmpl_ring;
32404 * The sequence ID is used by the driver for tracking multiple
32405 * commands. This ID is treated as opaque data by the firmware and
32406 * the value is returned in the `hwrm_resp_hdr` upon completion.
32410 * The target ID of the command:
32411 * * 0x0-0xFFF8 - The function ID
32412 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32413 * * 0xFFFD - Reserved for user-space HWRM interface
32416 uint16_t target_id;
32418 * A physical address pointer pointing to a host buffer that the
32419 * command's response data will be written. This can be either a host
32420 * physical address (HPA) or a guest physical address (GPA) and must
32421 * point to a physically contiguous block of memory.
32423 uint64_t resp_addr;
32424 /* Physical number of completion ring. */
32428 * When this bit is set to '1', interrupt latency max
32429 * timer is reset whenever a completion is received.
32431 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
32434 * When this bit is set to '1', ring idle mode
32435 * aggregation will be enabled.
32437 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
32440 * Set this flag to 1 when configuring parameters on a
32441 * notification queue. Set this flag to 0 when configuring
32442 * parameters on a completion queue or completion ring.
32444 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
32447 * Number of completions to aggregate before DMA
32448 * during the normal mode.
32450 uint16_t num_cmpl_dma_aggr;
32452 * Number of completions to aggregate before DMA
32453 * during the interrupt mode.
32455 uint16_t num_cmpl_dma_aggr_during_int;
32457 * Timer used to aggregate completions before
32458 * DMA during the normal mode (not in interrupt mode).
32460 uint16_t cmpl_aggr_dma_tmr;
32462 * Timer used to aggregate completions before
32463 * DMA while in interrupt mode.
32465 uint16_t cmpl_aggr_dma_tmr_during_int;
32466 /* Minimum time between two interrupts. */
32467 uint16_t int_lat_tmr_min;
32469 * Maximum wait time spent aggregating
32470 * completions before signaling the interrupt after the
32471 * interrupt is enabled.
32473 uint16_t int_lat_tmr_max;
32475 * Minimum number of completions aggregated before signaling
32478 uint16_t num_cmpl_aggr_int;
32480 * Bitfield that indicates which parameters are to be applied. Only
32481 * required when configuring devices with notification queues, and
32482 * used in that case to set certain parameters on completion queues
32483 * and others on notification queues.
32487 * This bit must be '1' for the num_cmpl_dma_aggr field to be
32490 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
32493 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
32496 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
32499 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
32502 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
32505 * This bit must be '1' for the int_lat_tmr_min field to be
32508 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
32511 * This bit must be '1' for the int_lat_tmr_max field to be
32514 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
32517 * This bit must be '1' for the num_cmpl_aggr_int field to be
32520 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
32522 uint8_t unused_0[4];
32525 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
32526 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
32527 /* The specific error status for the command. */
32528 uint16_t error_code;
32529 /* The HWRM command request type. */
32531 /* The sequence ID from the original command. */
32533 /* The length of the response data in number of bytes. */
32535 uint8_t unused_0[7];
32537 * This field is used in Output records to indicate that the output
32538 * is completely written to RAM. This field should be read as '1'
32539 * to indicate that the output has been completely written.
32540 * When writing a command completion or response to an internal processor,
32541 * the order of writes has to be such that this field is written last.
32546 /***********************
32547 * hwrm_ring_grp_alloc *
32548 ***********************/
32551 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
32552 struct hwrm_ring_grp_alloc_input {
32553 /* The HWRM command request type. */
32556 * The completion ring to send the completion event on. This should
32557 * be the NQ ID returned from the `nq_alloc` HWRM command.
32559 uint16_t cmpl_ring;
32561 * The sequence ID is used by the driver for tracking multiple
32562 * commands. This ID is treated as opaque data by the firmware and
32563 * the value is returned in the `hwrm_resp_hdr` upon completion.
32567 * The target ID of the command:
32568 * * 0x0-0xFFF8 - The function ID
32569 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32570 * * 0xFFFD - Reserved for user-space HWRM interface
32573 uint16_t target_id;
32575 * A physical address pointer pointing to a host buffer that the
32576 * command's response data will be written. This can be either a host
32577 * physical address (HPA) or a guest physical address (GPA) and must
32578 * point to a physically contiguous block of memory.
32580 uint64_t resp_addr;
32582 * This value identifies the CR associated with the ring
32587 * This value identifies the main RR associated with the ring
32592 * This value identifies the aggregation RR associated with
32593 * the ring group. If this value is 0xFF... (All Fs), then no
32594 * Aggregation ring will be set.
32598 * This value identifies the statistics context associated
32599 * with the ring group.
32604 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
32605 struct hwrm_ring_grp_alloc_output {
32606 /* The specific error status for the command. */
32607 uint16_t error_code;
32608 /* The HWRM command request type. */
32610 /* The sequence ID from the original command. */
32612 /* The length of the response data in number of bytes. */
32615 * This is the ring group ID value. Use this value to program
32616 * the default ring group for the VNIC or as table entries
32617 * in an RSS/COS context.
32619 uint32_t ring_group_id;
32620 uint8_t unused_0[3];
32622 * This field is used in Output records to indicate that the output
32623 * is completely written to RAM. This field should be read as '1'
32624 * to indicate that the output has been completely written.
32625 * When writing a command completion or response to an internal processor,
32626 * the order of writes has to be such that this field is written last.
32631 /**********************
32632 * hwrm_ring_grp_free *
32633 **********************/
32636 /* hwrm_ring_grp_free_input (size:192b/24B) */
32637 struct hwrm_ring_grp_free_input {
32638 /* The HWRM command request type. */
32641 * The completion ring to send the completion event on. This should
32642 * be the NQ ID returned from the `nq_alloc` HWRM command.
32644 uint16_t cmpl_ring;
32646 * The sequence ID is used by the driver for tracking multiple
32647 * commands. This ID is treated as opaque data by the firmware and
32648 * the value is returned in the `hwrm_resp_hdr` upon completion.
32652 * The target ID of the command:
32653 * * 0x0-0xFFF8 - The function ID
32654 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32655 * * 0xFFFD - Reserved for user-space HWRM interface
32658 uint16_t target_id;
32660 * A physical address pointer pointing to a host buffer that the
32661 * command's response data will be written. This can be either a host
32662 * physical address (HPA) or a guest physical address (GPA) and must
32663 * point to a physically contiguous block of memory.
32665 uint64_t resp_addr;
32666 /* This is the ring group ID value. */
32667 uint32_t ring_group_id;
32668 uint8_t unused_0[4];
32671 /* hwrm_ring_grp_free_output (size:128b/16B) */
32672 struct hwrm_ring_grp_free_output {
32673 /* The specific error status for the command. */
32674 uint16_t error_code;
32675 /* The HWRM command request type. */
32677 /* The sequence ID from the original command. */
32679 /* The length of the response data in number of bytes. */
32681 uint8_t unused_0[7];
32683 * This field is used in Output records to indicate that the output
32684 * is completely written to RAM. This field should be read as '1'
32685 * to indicate that the output has been completely written.
32686 * When writing a command completion or response to an internal processor,
32687 * the order of writes has to be such that this field is written last.
32692 /************************
32693 * hwrm_ring_schq_alloc *
32694 ************************/
32697 /* hwrm_ring_schq_alloc_input (size:1088b/136B) */
32698 struct hwrm_ring_schq_alloc_input {
32699 /* The HWRM command request type. */
32702 * The completion ring to send the completion event on. This should
32703 * be the NQ ID returned from the `nq_alloc` HWRM command.
32705 uint16_t cmpl_ring;
32707 * The sequence ID is used by the driver for tracking multiple
32708 * commands. This ID is treated as opaque data by the firmware and
32709 * the value is returned in the `hwrm_resp_hdr` upon completion.
32713 * The target ID of the command:
32714 * * 0x0-0xFFF8 - The function ID
32715 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32716 * * 0xFFFD - Reserved for user-space HWRM interface
32719 uint16_t target_id;
32721 * A physical address pointer pointing to a host buffer that the
32722 * command's response data will be written. This can be either a host
32723 * physical address (HPA) or a guest physical address (GPA) and must
32724 * point to a physically contiguous block of memory.
32726 uint64_t resp_addr;
32729 * This bit must be '1' for the tqm_ring0 fields to be
32732 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
32734 * This bit must be '1' for the tqm_ring1 fields to be
32737 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
32739 * This bit must be '1' for the tqm_ring2 fields to be
32742 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
32744 * This bit must be '1' for the tqm_ring3 fields to be
32747 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
32749 * This bit must be '1' for the tqm_ring4 fields to be
32752 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
32754 * This bit must be '1' for the tqm_ring5 fields to be
32757 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
32759 * This bit must be '1' for the tqm_ring6 fields to be
32762 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
32764 * This bit must be '1' for the tqm_ring7 fields to be
32767 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
32768 /* Reserved for future use. */
32770 /* TQM ring 0 page size and level. */
32771 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
32772 /* TQM ring 0 PBL indirect levels. */
32773 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK \
32775 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
32776 /* PBL pointer is physical start address. */
32777 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
32779 /* PBL pointer points to PTE table. */
32780 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
32783 * PBL pointer points to PDE table with each entry pointing to PTE
32786 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
32788 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
32789 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
32790 /* TQM ring 0 page size. */
32791 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK \
32793 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
32795 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
32796 (UINT32_C(0x0) << 4)
32798 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
32799 (UINT32_C(0x1) << 4)
32801 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
32802 (UINT32_C(0x2) << 4)
32804 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
32805 (UINT32_C(0x3) << 4)
32807 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
32808 (UINT32_C(0x4) << 4)
32810 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
32811 (UINT32_C(0x5) << 4)
32812 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
32813 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
32814 /* TQM ring 1 page size and level. */
32815 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
32816 /* TQM ring 1 PBL indirect levels. */
32817 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK \
32819 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
32820 /* PBL pointer is physical start address. */
32821 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
32823 /* PBL pointer points to PTE table. */
32824 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
32827 * PBL pointer points to PDE table with each entry pointing to PTE
32830 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
32832 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
32833 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
32834 /* TQM ring 1 page size. */
32835 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK \
32837 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
32839 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
32840 (UINT32_C(0x0) << 4)
32842 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
32843 (UINT32_C(0x1) << 4)
32845 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
32846 (UINT32_C(0x2) << 4)
32848 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
32849 (UINT32_C(0x3) << 4)
32851 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
32852 (UINT32_C(0x4) << 4)
32854 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
32855 (UINT32_C(0x5) << 4)
32856 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
32857 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
32858 /* TQM ring 2 page size and level. */
32859 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
32860 /* TQM ring 2 PBL indirect levels. */
32861 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK \
32863 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
32864 /* PBL pointer is physical start address. */
32865 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
32867 /* PBL pointer points to PTE table. */
32868 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
32871 * PBL pointer points to PDE table with each entry pointing to PTE
32874 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
32876 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
32877 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
32878 /* TQM ring 2 page size. */
32879 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK \
32881 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
32883 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
32884 (UINT32_C(0x0) << 4)
32886 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
32887 (UINT32_C(0x1) << 4)
32889 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
32890 (UINT32_C(0x2) << 4)
32892 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
32893 (UINT32_C(0x3) << 4)
32895 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
32896 (UINT32_C(0x4) << 4)
32898 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
32899 (UINT32_C(0x5) << 4)
32900 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
32901 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
32902 /* TQM ring 3 page size and level. */
32903 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
32904 /* TQM ring 3 PBL indirect levels. */
32905 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK \
32907 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
32908 /* PBL pointer is physical start address. */
32909 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
32911 /* PBL pointer points to PTE table. */
32912 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
32915 * PBL pointer points to PDE table with each entry pointing to PTE
32918 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
32920 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
32921 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
32922 /* TQM ring 3 page size. */
32923 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK \
32925 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
32927 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
32928 (UINT32_C(0x0) << 4)
32930 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
32931 (UINT32_C(0x1) << 4)
32933 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
32934 (UINT32_C(0x2) << 4)
32936 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
32937 (UINT32_C(0x3) << 4)
32939 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
32940 (UINT32_C(0x4) << 4)
32942 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
32943 (UINT32_C(0x5) << 4)
32944 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
32945 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
32946 /* TQM ring 4 page size and level. */
32947 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
32948 /* TQM ring 4 PBL indirect levels. */
32949 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK \
32951 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
32952 /* PBL pointer is physical start address. */
32953 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
32955 /* PBL pointer points to PTE table. */
32956 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
32959 * PBL pointer points to PDE table with each entry pointing to PTE
32962 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
32964 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
32965 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
32966 /* TQM ring 4 page size. */
32967 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK \
32969 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
32971 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
32972 (UINT32_C(0x0) << 4)
32974 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
32975 (UINT32_C(0x1) << 4)
32977 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
32978 (UINT32_C(0x2) << 4)
32980 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
32981 (UINT32_C(0x3) << 4)
32983 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
32984 (UINT32_C(0x4) << 4)
32986 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
32987 (UINT32_C(0x5) << 4)
32988 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
32989 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
32990 /* TQM ring 5 page size and level. */
32991 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
32992 /* TQM ring 5 PBL indirect levels. */
32993 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK \
32995 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
32996 /* PBL pointer is physical start address. */
32997 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
32999 /* PBL pointer points to PTE table. */
33000 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
33003 * PBL pointer points to PDE table with each entry pointing to PTE
33006 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
33008 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
33009 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
33010 /* TQM ring 5 page size. */
33011 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK \
33013 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
33015 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
33016 (UINT32_C(0x0) << 4)
33018 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
33019 (UINT32_C(0x1) << 4)
33021 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
33022 (UINT32_C(0x2) << 4)
33024 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
33025 (UINT32_C(0x3) << 4)
33027 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
33028 (UINT32_C(0x4) << 4)
33030 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
33031 (UINT32_C(0x5) << 4)
33032 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
33033 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
33034 /* TQM ring 6 page size and level. */
33035 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
33036 /* TQM ring 6 PBL indirect levels. */
33037 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK \
33039 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
33040 /* PBL pointer is physical start address. */
33041 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
33043 /* PBL pointer points to PTE table. */
33044 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
33047 * PBL pointer points to PDE table with each entry pointing to PTE
33050 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
33052 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
33053 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
33054 /* TQM ring 6 page size. */
33055 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK \
33057 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
33059 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
33060 (UINT32_C(0x0) << 4)
33062 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
33063 (UINT32_C(0x1) << 4)
33065 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
33066 (UINT32_C(0x2) << 4)
33068 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
33069 (UINT32_C(0x3) << 4)
33071 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
33072 (UINT32_C(0x4) << 4)
33074 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
33075 (UINT32_C(0x5) << 4)
33076 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
33077 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
33078 /* TQM ring 7 page size and level. */
33079 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
33080 /* TQM ring 7 PBL indirect levels. */
33081 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK \
33083 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
33084 /* PBL pointer is physical start address. */
33085 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
33087 /* PBL pointer points to PTE table. */
33088 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
33091 * PBL pointer points to PDE table with each entry pointing to PTE
33094 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
33096 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
33097 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
33098 /* TQM ring 7 page size. */
33099 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK \
33101 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
33103 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
33104 (UINT32_C(0x0) << 4)
33106 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
33107 (UINT32_C(0x1) << 4)
33109 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
33110 (UINT32_C(0x2) << 4)
33112 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
33113 (UINT32_C(0x3) << 4)
33115 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
33116 (UINT32_C(0x4) << 4)
33118 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
33119 (UINT32_C(0x5) << 4)
33120 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
33121 HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
33122 /* TQM ring 0 page directory. */
33123 uint64_t tqm_ring0_page_dir;
33124 /* TQM ring 1 page directory. */
33125 uint64_t tqm_ring1_page_dir;
33126 /* TQM ring 2 page directory. */
33127 uint64_t tqm_ring2_page_dir;
33128 /* TQM ring 3 page directory. */
33129 uint64_t tqm_ring3_page_dir;
33130 /* TQM ring 4 page directory. */
33131 uint64_t tqm_ring4_page_dir;
33132 /* TQM ring 5 page directory. */
33133 uint64_t tqm_ring5_page_dir;
33134 /* TQM ring 6 page directory. */
33135 uint64_t tqm_ring6_page_dir;
33136 /* TQM ring 7 page directory. */
33137 uint64_t tqm_ring7_page_dir;
33139 * Number of TQM ring 0 entries.
33141 * TQM fastpath rings should be sized large enough to accommodate the
33142 * maximum number of QPs (either L2 or RoCE, or both if shared)
33143 * that can be enqueued to the TQM ring.
33145 * Note that TQM ring sizes cannot be extended while the system is
33146 * operational. If a PF driver needs to extend a TQM ring, it needs
33147 * to delete the SCHQ and then reallocate it.
33149 uint32_t tqm_ring0_num_entries;
33151 * Number of TQM ring 1 entries.
33153 * TQM fastpath rings should be sized large enough to accommodate the
33154 * maximum number of QPs (either L2 or RoCE, or both if shared)
33155 * that can be enqueued to the TQM ring.
33157 * Note that TQM ring sizes cannot be extended while the system is
33158 * operational. If a PF driver needs to extend a TQM ring, it needs
33159 * to delete the SCHQ and then reallocate it.
33161 uint32_t tqm_ring1_num_entries;
33163 * Number of TQM ring 2 entries.
33165 * TQM fastpath rings should be sized large enough to accommodate the
33166 * maximum number of QPs (either L2 or RoCE, or both if shared)
33167 * that can be enqueued to the TQM ring.
33169 * Note that TQM ring sizes cannot be extended while the system is
33170 * operational. If a PF driver needs to extend a TQM ring, it needs
33171 * to delete the SCHQ and then reallocate it.
33173 uint32_t tqm_ring2_num_entries;
33175 * Number of TQM ring 3 entries.
33177 * TQM fastpath rings should be sized large enough to accommodate the
33178 * maximum number of QPs (either L2 or RoCE, or both if shared)
33179 * that can be enqueued to the TQM ring.
33181 * Note that TQM ring sizes cannot be extended while the system is
33182 * operational. If a PF driver needs to extend a TQM ring, it needs
33183 * to delete the SCHQ and then reallocate it.
33185 uint32_t tqm_ring3_num_entries;
33187 * Number of TQM ring 4 entries.
33189 * TQM fastpath rings should be sized large enough to accommodate the
33190 * maximum number of QPs (either L2 or RoCE, or both if shared)
33191 * that can be enqueued to the TQM ring.
33193 * Note that TQM ring sizes cannot be extended while the system is
33194 * operational. If a PF driver needs to extend a TQM ring, it needs
33195 * to delete the SCHQ and then reallocate it.
33197 uint32_t tqm_ring4_num_entries;
33199 * Number of TQM ring 5 entries.
33201 * TQM fastpath rings should be sized large enough to accommodate the
33202 * maximum number of QPs (either L2 or RoCE, or both if shared)
33203 * that can be enqueued to the TQM ring.
33205 * Note that TQM ring sizes cannot be extended while the system is
33206 * operational. If a PF driver needs to extend a TQM ring, it needs
33207 * to delete the SCHQ and then reallocate it.
33209 uint32_t tqm_ring5_num_entries;
33211 * Number of TQM ring 6 entries.
33213 * TQM fastpath rings should be sized large enough to accommodate the
33214 * maximum number of QPs (either L2 or RoCE, or both if shared)
33215 * that can be enqueued to the TQM ring.
33217 * Note that TQM ring sizes cannot be extended while the system is
33218 * operational. If a PF driver needs to extend a TQM ring, it needs
33219 * to delete the SCHQ and then reallocate it.
33221 uint32_t tqm_ring6_num_entries;
33223 * Number of TQM ring 7 entries.
33225 * TQM fastpath rings should be sized large enough to accommodate the
33226 * maximum number of QPs (either L2 or RoCE, or both if shared)
33227 * that can be enqueued to the TQM ring.
33229 * Note that TQM ring sizes cannot be extended while the system is
33230 * operational. If a PF driver needs to extend a TQM ring, it needs
33231 * to delete the SCHQ and then reallocate it.
33233 uint32_t tqm_ring7_num_entries;
33234 /* Number of bytes that have been allocated for each context entry. */
33235 uint16_t tqm_entry_size;
33236 uint8_t unused_0[6];
33239 /* hwrm_ring_schq_alloc_output (size:128b/16B) */
33240 struct hwrm_ring_schq_alloc_output {
33241 /* The specific error status for the command. */
33242 uint16_t error_code;
33243 /* The HWRM command request type. */
33245 /* The sequence ID from the original command. */
33247 /* The length of the response data in number of bytes. */
33250 * This is an identifier for the SCHQ to be used in other HWRM commands
33251 * that need to reference this SCHQ. This value is greater than zero
33252 * (i.e. a schq_id of zero references the default SCHQ).
33255 uint8_t unused_0[5];
33257 * This field is used in Output records to indicate that the output
33258 * is completely written to RAM. This field should be read as '1'
33259 * to indicate that the output has been completely written.
33260 * When writing a command completion or response to an internal processor,
33261 * the order of writes has to be such that this field is written last.
33266 /**********************
33267 * hwrm_ring_schq_cfg *
33268 **********************/
33271 /* hwrm_ring_schq_cfg_input (size:768b/96B) */
33272 struct hwrm_ring_schq_cfg_input {
33273 /* The HWRM command request type. */
33276 * The completion ring to send the completion event on. This should
33277 * be the NQ ID returned from the `nq_alloc` HWRM command.
33279 uint16_t cmpl_ring;
33281 * The sequence ID is used by the driver for tracking multiple
33282 * commands. This ID is treated as opaque data by the firmware and
33283 * the value is returned in the `hwrm_resp_hdr` upon completion.
33287 * The target ID of the command:
33288 * * 0x0-0xFFF8 - The function ID
33289 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33290 * * 0xFFFD - Reserved for user-space HWRM interface
33293 uint16_t target_id;
33295 * A physical address pointer pointing to a host buffer that the
33296 * command's response data will be written. This can be either a host
33297 * physical address (HPA) or a guest physical address (GPA) and must
33298 * point to a physically contiguous block of memory.
33300 uint64_t resp_addr;
33302 * Identifies the SCHQ being configured. A schq_id of zero refers to
33303 * the default SCHQ.
33307 * This field is an 8 bit bitmap that indicates which TCs are enabled
33308 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
33311 uint8_t tc_enabled;
33314 /* The tc_max_bw array and the max_bw parameters are valid */
33315 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
33317 /* The tc_min_bw array is valid */
33318 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
33320 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33321 uint32_t max_bw_tc0;
33322 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33323 uint32_t max_bw_tc1;
33324 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33325 uint32_t max_bw_tc2;
33326 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33327 uint32_t max_bw_tc3;
33328 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33329 uint32_t max_bw_tc4;
33330 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33331 uint32_t max_bw_tc5;
33332 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33333 uint32_t max_bw_tc6;
33334 /* Maximum bandwidth of the traffic class, specified in Mbps. */
33335 uint32_t max_bw_tc7;
33337 * Bandwidth reservation for the traffic class, specified in Mbps.
33338 * A value of zero signifies that traffic belonging to this class
33339 * shares the bandwidth reservation for the same traffic class of
33340 * the default SCHQ.
33342 uint32_t min_bw_tc0;
33344 * Bandwidth reservation for the traffic class, specified in Mbps.
33345 * A value of zero signifies that traffic belonging to this class
33346 * shares the bandwidth reservation for the same traffic class of
33347 * the default SCHQ.
33349 uint32_t min_bw_tc1;
33351 * Bandwidth reservation for the traffic class, specified in Mbps.
33352 * A value of zero signifies that traffic belonging to this class
33353 * shares the bandwidth reservation for the same traffic class of
33354 * the default SCHQ.
33356 uint32_t min_bw_tc2;
33358 * Bandwidth reservation for the traffic class, specified in Mbps.
33359 * A value of zero signifies that traffic belonging to this class
33360 * shares the bandwidth reservation for the same traffic class of
33361 * the default SCHQ.
33363 uint32_t min_bw_tc3;
33365 * Bandwidth reservation for the traffic class, specified in Mbps.
33366 * A value of zero signifies that traffic belonging to this class
33367 * shares the bandwidth reservation for the same traffic class of
33368 * the default SCHQ.
33370 uint32_t min_bw_tc4;
33372 * Bandwidth reservation for the traffic class, specified in Mbps.
33373 * A value of zero signifies that traffic belonging to this class
33374 * shares the bandwidth reservation for the same traffic class of
33375 * the default SCHQ.
33377 uint32_t min_bw_tc5;
33379 * Bandwidth reservation for the traffic class, specified in Mbps.
33380 * A value of zero signifies that traffic belonging to this class
33381 * shares the bandwidth reservation for the same traffic class of
33382 * the default SCHQ.
33384 uint32_t min_bw_tc6;
33386 * Bandwidth reservation for the traffic class, specified in Mbps.
33387 * A value of zero signifies that traffic belonging to this class
33388 * shares the bandwidth reservation for the same traffic class of
33389 * the default SCHQ.
33391 uint32_t min_bw_tc7;
33393 * Indicates the max bandwidth for all enabled traffic classes in
33394 * this SCHQ, specified in Mbps.
33397 uint8_t unused_1[4];
33400 /* hwrm_ring_schq_cfg_output (size:128b/16B) */
33401 struct hwrm_ring_schq_cfg_output {
33402 /* The specific error status for the command. */
33403 uint16_t error_code;
33404 /* The HWRM command request type. */
33406 /* The sequence ID from the original command. */
33408 /* The length of the response data in number of bytes. */
33410 uint8_t unused_0[7];
33412 * This field is used in Output records to indicate that the output
33413 * is completely written to RAM. This field should be read as '1'
33414 * to indicate that the output has been completely written.
33415 * When writing a command completion or response to an internal processor,
33416 * the order of writes has to be such that this field is written last.
33421 /***********************
33422 * hwrm_ring_schq_free *
33423 ***********************/
33426 /* hwrm_ring_schq_free_input (size:192b/24B) */
33427 struct hwrm_ring_schq_free_input {
33428 /* The HWRM command request type. */
33431 * The completion ring to send the completion event on. This should
33432 * be the NQ ID returned from the `nq_alloc` HWRM command.
33434 uint16_t cmpl_ring;
33436 * The sequence ID is used by the driver for tracking multiple
33437 * commands. This ID is treated as opaque data by the firmware and
33438 * the value is returned in the `hwrm_resp_hdr` upon completion.
33442 * The target ID of the command:
33443 * * 0x0-0xFFF8 - The function ID
33444 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33445 * * 0xFFFD - Reserved for user-space HWRM interface
33448 uint16_t target_id;
33450 * A physical address pointer pointing to a host buffer that the
33451 * command's response data will be written. This can be either a host
33452 * physical address (HPA) or a guest physical address (GPA) and must
33453 * point to a physically contiguous block of memory.
33455 uint64_t resp_addr;
33456 /* Identifies the SCHQ being freed. */
33458 uint8_t unused_0[6];
33461 /* hwrm_ring_schq_free_output (size:128b/16B) */
33462 struct hwrm_ring_schq_free_output {
33463 /* The specific error status for the command. */
33464 uint16_t error_code;
33465 /* The HWRM command request type. */
33467 /* The sequence ID from the original command. */
33469 /* The length of the response data in number of bytes. */
33471 uint8_t unused_0[7];
33473 * This field is used in Output records to indicate that the output
33474 * is completely written to RAM. This field should be read as '1'
33475 * to indicate that the output has been completely written.
33476 * When writing a command completion or response to an internal processor,
33477 * the order of writes has to be such that this field is written last.
33482 * special reserved flow ID to identify per function default
33483 * flows for vSwitch offload
33485 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
33487 * special reserved flow ID to identify per function RoCEv1
33490 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
33492 * special reserved flow ID to identify per function RoCEv2
33495 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
33497 * special reserved flow ID to identify per function RoCEv2
33500 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
33502 /****************************
33503 * hwrm_cfa_l2_filter_alloc *
33504 ****************************/
33507 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
33508 struct hwrm_cfa_l2_filter_alloc_input {
33509 /* The HWRM command request type. */
33512 * The completion ring to send the completion event on. This should
33513 * be the NQ ID returned from the `nq_alloc` HWRM command.
33515 uint16_t cmpl_ring;
33517 * The sequence ID is used by the driver for tracking multiple
33518 * commands. This ID is treated as opaque data by the firmware and
33519 * the value is returned in the `hwrm_resp_hdr` upon completion.
33523 * The target ID of the command:
33524 * * 0x0-0xFFF8 - The function ID
33525 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33526 * * 0xFFFD - Reserved for user-space HWRM interface
33529 uint16_t target_id;
33531 * A physical address pointer pointing to a host buffer that the
33532 * command's response data will be written. This can be either a host
33533 * physical address (HPA) or a guest physical address (GPA) and must
33534 * point to a physically contiguous block of memory.
33536 uint64_t resp_addr;
33539 * Enumeration denoting the RX, TX type of the resource.
33540 * This enumeration is used for resources that are similar for both
33541 * TX and RX paths of the chip.
33543 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
33546 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
33549 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
33551 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
33552 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
33554 * Setting of this flag indicates the applicability to the loopback
33557 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
33560 * Setting of this flag indicates drop action. If this flag is not
33561 * set, then it should be considered accept action.
33563 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
33566 * If this flag is set, all t_l2_* fields are invalid
33567 * and they should not be specified.
33568 * If this flag is set, then l2_* fields refer to
33569 * fields of outermost L2 header.
33571 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
33574 * Enumeration denoting NO_ROCE_L2 to support old drivers.
33575 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
33577 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
33579 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
33580 /* To support old drivers */
33581 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
33582 (UINT32_C(0x0) << 4)
33583 /* Only L2 traffic */
33584 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
33585 (UINT32_C(0x1) << 4)
33586 /* Roce & L2 traffic */
33587 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
33588 (UINT32_C(0x2) << 4)
33589 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
33590 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
33592 * Setting of this flag indicates that no XDP filter is created with
33594 * 0 - legacy behavior, XDP filter is created with L2 filter
33595 * 1 - XDP filter won't be created with L2 filter
33597 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
33600 * Setting this flag to 1 indicate the L2 fields in this command
33601 * pertain to source fields. Setting this flag to 0 indicate the
33602 * L2 fields in this command pertain to the destination fields
33603 * and this is the default/legacy behavior.
33605 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
33609 * This bit must be '1' for the l2_addr field to be
33612 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
33615 * This bit must be '1' for the l2_addr_mask field to be
33618 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
33621 * This bit must be '1' for the l2_ovlan field to be
33624 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
33627 * This bit must be '1' for the l2_ovlan_mask field to be
33630 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
33633 * This bit must be '1' for the l2_ivlan field to be
33636 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
33639 * This bit must be '1' for the l2_ivlan_mask field to be
33642 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
33645 * This bit must be '1' for the t_l2_addr field to be
33648 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
33651 * This bit must be '1' for the t_l2_addr_mask field to be
33654 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
33657 * This bit must be '1' for the t_l2_ovlan field to be
33660 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
33663 * This bit must be '1' for the t_l2_ovlan_mask field to be
33666 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
33669 * This bit must be '1' for the t_l2_ivlan field to be
33672 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
33675 * This bit must be '1' for the t_l2_ivlan_mask field to be
33678 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
33681 * This bit must be '1' for the src_type field to be
33684 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
33687 * This bit must be '1' for the src_id field to be
33690 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
33693 * This bit must be '1' for the tunnel_type field to be
33696 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33699 * This bit must be '1' for the dst_id field to be
33702 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33705 * This bit must be '1' for the mirror_vnic_id field to be
33708 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33711 * This bit must be '1' for the num_vlans field to be
33714 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
33717 * This bit must be '1' for the t_num_vlans field to be
33720 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
33723 * This value sets the match value for the L2 MAC address.
33724 * Destination MAC address for RX path.
33725 * Source MAC address for TX path.
33727 uint8_t l2_addr[6];
33728 /* This value sets the match value for the number of VLANs. */
33731 * This value sets the match value for the number of VLANs
33732 * in the tunnel headers.
33734 uint8_t t_num_vlans;
33736 * This value sets the mask value for the L2 address.
33737 * A value of 0 will mask the corresponding bit from
33740 uint8_t l2_addr_mask[6];
33741 /* This value sets VLAN ID value for outer VLAN. */
33744 * This value sets the mask value for the ovlan id.
33745 * A value of 0 will mask the corresponding bit from
33748 uint16_t l2_ovlan_mask;
33749 /* This value sets VLAN ID value for inner VLAN. */
33752 * This value sets the mask value for the ivlan id.
33753 * A value of 0 will mask the corresponding bit from
33756 uint16_t l2_ivlan_mask;
33757 uint8_t unused_1[2];
33759 * This value sets the match value for the tunnel
33761 * Destination MAC address for RX path.
33762 * Source MAC address for TX path.
33764 uint8_t t_l2_addr[6];
33765 uint8_t unused_2[2];
33767 * This value sets the mask value for the tunnel L2
33769 * A value of 0 will mask the corresponding bit from
33772 uint8_t t_l2_addr_mask[6];
33773 /* This value sets VLAN ID value for tunnel outer VLAN. */
33774 uint16_t t_l2_ovlan;
33776 * This value sets the mask value for the tunnel ovlan id.
33777 * A value of 0 will mask the corresponding bit from
33780 uint16_t t_l2_ovlan_mask;
33781 /* This value sets VLAN ID value for tunnel inner VLAN. */
33782 uint16_t t_l2_ivlan;
33784 * This value sets the mask value for the tunnel ivlan id.
33785 * A value of 0 will mask the corresponding bit from
33788 uint16_t t_l2_ivlan_mask;
33789 /* This value identifies the type of source of the packet. */
33792 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
33793 /* Physical function */
33794 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
33795 /* Virtual function */
33796 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
33797 /* Virtual NIC of a function */
33798 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
33799 /* Embedded processor for CFA management */
33800 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
33801 /* Embedded processor for OOB management */
33802 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
33803 /* Embedded processor for RoCE */
33804 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
33805 /* Embedded processor for network proxy functions */
33806 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
33807 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
33808 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
33811 * This value is the id of the source.
33812 * For a network port, it represents port_id.
33813 * For a physical function, it represents fid.
33814 * For a virtual function, it represents vf_id.
33815 * For a vnic, it represents vnic_id.
33816 * For embedded processors, this id is not valid.
33819 * 1. The function ID is implied if it src_id is
33820 * not provided for a src_type that is either
33824 uint8_t tunnel_type;
33826 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33828 /* Virtual eXtensible Local Area Network (VXLAN) */
33829 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33831 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33832 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33834 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33835 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33838 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33840 /* Generic Network Virtualization Encapsulation (Geneve) */
33841 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33843 /* Multi-Protocol Label Switching (MPLS) */
33844 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33846 /* Stateless Transport Tunnel (STT) */
33847 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33849 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33850 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33852 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33853 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33856 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
33859 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33861 /* Use fixed layer 2 ether type of 0xFFFF */
33862 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33865 * IPV6 over virtual eXtensible Local Area Network with GPE header
33868 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33870 /* Any tunneled traffic */
33871 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33873 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33874 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33877 * If set, this value shall represent the
33878 * Logical VNIC ID of the destination VNIC for the RX
33879 * path and network port id of the destination port for
33884 * Logical VNIC ID of the VNIC where traffic is
33887 uint16_t mirror_vnic_id;
33889 * This hint is provided to help in placing
33890 * the filter in the filter table.
33893 /* No preference */
33894 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
33896 /* Above the given filter */
33897 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
33899 /* Below the given filter */
33900 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
33902 /* As high as possible */
33903 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
33905 /* As low as possible */
33906 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
33908 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
33909 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
33913 * This is the ID of the filter that goes along with
33916 * This field is valid only for the following values.
33917 * 1 - Above the given filter
33918 * 2 - Below the given filter
33920 uint64_t l2_filter_id_hint;
33923 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
33924 struct hwrm_cfa_l2_filter_alloc_output {
33925 /* The specific error status for the command. */
33926 uint16_t error_code;
33927 /* The HWRM command request type. */
33929 /* The sequence ID from the original command. */
33931 /* The length of the response data in number of bytes. */
33934 * This value identifies a set of CFA data structures used for an L2
33937 uint64_t l2_filter_id;
33939 * The flow id value in bit 0-29 is the actual ID of the flow
33940 * associated with this filter and it shall be used to match
33941 * and associate the flow identifier returned in completion
33942 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
33943 * shall indicate no valid flow id.
33946 /* Indicate the flow id value. */
33947 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
33948 UINT32_C(0x3fffffff)
33949 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
33950 /* Indicate type of the flow. */
33951 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
33952 UINT32_C(0x40000000)
33954 * If this bit set to 0, then it indicates that the flow is
33957 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
33958 (UINT32_C(0x0) << 30)
33960 * If this bit is set to 1, then it indicates that the flow is
33963 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
33964 (UINT32_C(0x1) << 30)
33965 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
33966 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
33967 /* Indicate the flow direction. */
33968 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
33969 UINT32_C(0x80000000)
33970 /* If this bit set to 0, then it indicates rx flow. */
33971 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
33972 (UINT32_C(0x0) << 31)
33973 /* If this bit is set to 1, then it indicates that tx flow. */
33974 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
33975 (UINT32_C(0x1) << 31)
33976 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
33977 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
33978 uint8_t unused_0[3];
33980 * This field is used in Output records to indicate that the output
33981 * is completely written to RAM. This field should be read as '1'
33982 * to indicate that the output has been completely written.
33983 * When writing a command completion or response to an internal
33984 * processor, the order of writes has to be such that this field is
33990 /***************************
33991 * hwrm_cfa_l2_filter_free *
33992 ***************************/
33995 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
33996 struct hwrm_cfa_l2_filter_free_input {
33997 /* The HWRM command request type. */
34000 * The completion ring to send the completion event on. This should
34001 * be the NQ ID returned from the `nq_alloc` HWRM command.
34003 uint16_t cmpl_ring;
34005 * The sequence ID is used by the driver for tracking multiple
34006 * commands. This ID is treated as opaque data by the firmware and
34007 * the value is returned in the `hwrm_resp_hdr` upon completion.
34011 * The target ID of the command:
34012 * * 0x0-0xFFF8 - The function ID
34013 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34014 * * 0xFFFD - Reserved for user-space HWRM interface
34017 uint16_t target_id;
34019 * A physical address pointer pointing to a host buffer that the
34020 * command's response data will be written. This can be either a host
34021 * physical address (HPA) or a guest physical address (GPA) and must
34022 * point to a physically contiguous block of memory.
34024 uint64_t resp_addr;
34026 * This value identifies a set of CFA data structures used for an L2
34029 uint64_t l2_filter_id;
34032 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
34033 struct hwrm_cfa_l2_filter_free_output {
34034 /* The specific error status for the command. */
34035 uint16_t error_code;
34036 /* The HWRM command request type. */
34038 /* The sequence ID from the original command. */
34040 /* The length of the response data in number of bytes. */
34042 uint8_t unused_0[7];
34044 * This field is used in Output records to indicate that the output
34045 * is completely written to RAM. This field should be read as '1'
34046 * to indicate that the output has been completely written.
34047 * When writing a command completion or response to an internal
34048 * processor, the order of writes has to be such that this field is
34054 /**************************
34055 * hwrm_cfa_l2_filter_cfg *
34056 **************************/
34059 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
34060 struct hwrm_cfa_l2_filter_cfg_input {
34061 /* The HWRM command request type. */
34064 * The completion ring to send the completion event on. This should
34065 * be the NQ ID returned from the `nq_alloc` HWRM command.
34067 uint16_t cmpl_ring;
34069 * The sequence ID is used by the driver for tracking multiple
34070 * commands. This ID is treated as opaque data by the firmware and
34071 * the value is returned in the `hwrm_resp_hdr` upon completion.
34075 * The target ID of the command:
34076 * * 0x0-0xFFF8 - The function ID
34077 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34078 * * 0xFFFD - Reserved for user-space HWRM interface
34081 uint16_t target_id;
34083 * A physical address pointer pointing to a host buffer that the
34084 * command's response data will be written. This can be either a host
34085 * physical address (HPA) or a guest physical address (GPA) and must
34086 * point to a physically contiguous block of memory.
34088 uint64_t resp_addr;
34091 * Enumeration denoting the RX, TX type of the resource.
34092 * This enumeration is used for resources that are similar for both
34093 * TX and RX paths of the chip.
34095 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
34098 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
34101 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
34103 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
34104 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
34106 * Setting of this flag indicates drop action. If this flag is not
34107 * set, then it should be considered accept action.
34109 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
34112 * Enumeration denoting NO_ROCE_L2 to support old drivers.
34113 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
34115 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
34117 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
34118 /* To support old drivers */
34119 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
34120 (UINT32_C(0x0) << 2)
34121 /* Only L2 traffic */
34122 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
34123 (UINT32_C(0x1) << 2)
34124 /* Roce & L2 traffic */
34125 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
34126 (UINT32_C(0x2) << 2)
34127 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
34128 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
34131 * This bit must be '1' for the dst_id field to be
34134 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
34137 * This bit must be '1' for the new_mirror_vnic_id field to be
34140 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
34143 * This value identifies a set of CFA data structures used for an L2
34146 uint64_t l2_filter_id;
34148 * If set, this value shall represent the
34149 * Logical VNIC ID of the destination VNIC for the RX
34150 * path and network port id of the destination port for
34155 * New Logical VNIC ID of the VNIC where traffic is
34158 uint32_t new_mirror_vnic_id;
34161 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
34162 struct hwrm_cfa_l2_filter_cfg_output {
34163 /* The specific error status for the command. */
34164 uint16_t error_code;
34165 /* The HWRM command request type. */
34167 /* The sequence ID from the original command. */
34169 /* The length of the response data in number of bytes. */
34171 uint8_t unused_0[7];
34173 * This field is used in Output records to indicate that the output
34174 * is completely written to RAM. This field should be read as '1'
34175 * to indicate that the output has been completely written.
34176 * When writing a command completion or response to an internal
34177 * processor, the order of writes has to be such that this field is
34183 /***************************
34184 * hwrm_cfa_l2_set_rx_mask *
34185 ***************************/
34188 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
34189 struct hwrm_cfa_l2_set_rx_mask_input {
34190 /* The HWRM command request type. */
34193 * The completion ring to send the completion event on. This should
34194 * be the NQ ID returned from the `nq_alloc` HWRM command.
34196 uint16_t cmpl_ring;
34198 * The sequence ID is used by the driver for tracking multiple
34199 * commands. This ID is treated as opaque data by the firmware and
34200 * the value is returned in the `hwrm_resp_hdr` upon completion.
34204 * The target ID of the command:
34205 * * 0x0-0xFFF8 - The function ID
34206 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34207 * * 0xFFFD - Reserved for user-space HWRM interface
34210 uint16_t target_id;
34212 * A physical address pointer pointing to a host buffer that the
34213 * command's response data will be written. This can be either a host
34214 * physical address (HPA) or a guest physical address (GPA) and must
34215 * point to a physically contiguous block of memory.
34217 uint64_t resp_addr;
34222 * When this bit is '1', the function is requested to accept
34223 * multi-cast packets specified by the multicast addr table.
34225 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
34228 * When this bit is '1', the function is requested to accept
34229 * all multi-cast packets.
34231 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
34234 * When this bit is '1', the function is requested to accept
34235 * broadcast packets.
34237 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
34240 * When this bit is '1', the function is requested to be
34241 * put in the promiscuous mode.
34243 * The HWRM should accept any function to set up
34244 * promiscuous mode.
34246 * The HWRM shall follow the semantics below for the
34247 * promiscuous mode support.
34248 * # When partitioning is not enabled on a port
34249 * (i.e. single PF on the port), then the PF shall
34250 * be allowed to be in the promiscuous mode. When the
34251 * PF is in the promiscuous mode, then it shall
34252 * receive all host bound traffic on that port.
34253 * # When partitioning is enabled on a port
34254 * (i.e. multiple PFs per port) and a PF on that
34255 * port is in the promiscuous mode, then the PF
34256 * receives all traffic within that partition as
34257 * identified by a unique identifier for the
34258 * PF (e.g. S-Tag). If a unique outer VLAN
34259 * for the PF is specified, then the setting of
34260 * promiscuous mode on that PF shall result in the
34261 * PF receiving all host bound traffic with matching
34263 * # A VF shall can be set in the promiscuous mode.
34264 * In the promiscuous mode, the VF does not receive any
34265 * traffic unless a unique outer VLAN for the
34266 * VF is specified. If a unique outer VLAN
34267 * for the VF is specified, then the setting of
34268 * promiscuous mode on that VF shall result in the
34269 * VF receiving all host bound traffic with the
34270 * matching outer VLAN.
34271 * # The HWRM shall allow the setting of promiscuous
34272 * mode on a function independently from the
34273 * promiscuous mode settings on other functions.
34275 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
34278 * If this flag is set, the corresponding RX
34279 * filters shall be set up to cover multicast/broadcast
34280 * filters for the outermost Layer 2 destination MAC
34283 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
34286 * If this flag is set, the corresponding RX
34287 * filters shall be set up to cover multicast/broadcast
34288 * filters for the VLAN-tagged packets that match the
34289 * TPID and VID fields of VLAN tags in the VLAN tag
34290 * table specified in this command.
34292 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
34295 * If this flag is set, the corresponding RX
34296 * filters shall be set up to cover multicast/broadcast
34297 * filters for non-VLAN tagged packets and VLAN-tagged
34298 * packets that match the TPID and VID fields of VLAN
34299 * tags in the VLAN tag table specified in this command.
34301 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
34304 * If this flag is set, the corresponding RX
34305 * filters shall be set up to cover multicast/broadcast
34306 * filters for non-VLAN tagged packets and VLAN-tagged
34307 * packets matching any VLAN tag.
34309 * If this flag is set, then the HWRM shall ignore
34310 * VLAN tags specified in vlan_tag_tbl.
34312 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
34313 * flags is set, then the HWRM shall ignore
34314 * VLAN tags specified in vlan_tag_tbl.
34316 * The HWRM client shall set at most one flag out of
34317 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
34319 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
34321 /* This is the address for mcast address tbl. */
34322 uint64_t mc_tbl_addr;
34324 * This value indicates how many entries in mc_tbl are valid.
34325 * Each entry is 6 bytes.
34327 uint32_t num_mc_entries;
34328 uint8_t unused_0[4];
34330 * This is the address for VLAN tag table.
34331 * Each VLAN entry in the table is 4 bytes of a VLAN tag
34332 * including TPID, PCP, DEI, and VID fields in network byte
34335 uint64_t vlan_tag_tbl_addr;
34337 * This value indicates how many entries in vlan_tag_tbl are
34338 * valid. Each entry is 4 bytes.
34340 uint32_t num_vlan_tags;
34341 uint8_t unused_1[4];
34344 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
34345 struct hwrm_cfa_l2_set_rx_mask_output {
34346 /* The specific error status for the command. */
34347 uint16_t error_code;
34348 /* The HWRM command request type. */
34350 /* The sequence ID from the original command. */
34352 /* The length of the response data in number of bytes. */
34354 uint8_t unused_0[7];
34356 * This field is used in Output records to indicate that the output
34357 * is completely written to RAM. This field should be read as '1'
34358 * to indicate that the output has been completely written.
34359 * When writing a command completion or response to an internal
34360 * processor, the order of writes has to be such that this field is
34366 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
34367 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
34369 * command specific error codes that goes to
34370 * the cmd_err field in Common HWRM Error Response.
34373 /* Unknown error */
34374 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
34376 /* Unable to complete operation due to conflict with Ntuple Filter */
34377 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
34379 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
34380 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
34381 uint8_t unused_0[7];
34384 /*******************************
34385 * hwrm_cfa_vlan_antispoof_cfg *
34386 *******************************/
34389 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
34390 struct hwrm_cfa_vlan_antispoof_cfg_input {
34391 /* The HWRM command request type. */
34394 * The completion ring to send the completion event on. This should
34395 * be the NQ ID returned from the `nq_alloc` HWRM command.
34397 uint16_t cmpl_ring;
34399 * The sequence ID is used by the driver for tracking multiple
34400 * commands. This ID is treated as opaque data by the firmware and
34401 * the value is returned in the `hwrm_resp_hdr` upon completion.
34405 * The target ID of the command:
34406 * * 0x0-0xFFF8 - The function ID
34407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34408 * * 0xFFFD - Reserved for user-space HWRM interface
34411 uint16_t target_id;
34413 * A physical address pointer pointing to a host buffer that the
34414 * command's response data will be written. This can be either a host
34415 * physical address (HPA) or a guest physical address (GPA) and must
34416 * point to a physically contiguous block of memory.
34418 uint64_t resp_addr;
34420 * Function ID of the function that is being configured.
34421 * Only valid for a VF FID configured by the PF.
34424 uint8_t unused_0[2];
34425 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
34426 uint32_t num_vlan_entries;
34428 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
34429 * antispoof table. Each table entry contains the 16-bit TPID
34430 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
34431 * all in network order to match hwrm_cfa_l2_set_rx_mask.
34432 * For an individual VLAN entry, the mask value should be 0xfff
34433 * for the 12-bit VLAN ID.
34435 uint64_t vlan_tag_mask_tbl_addr;
34438 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
34439 struct hwrm_cfa_vlan_antispoof_cfg_output {
34440 /* The specific error status for the command. */
34441 uint16_t error_code;
34442 /* The HWRM command request type. */
34444 /* The sequence ID from the original command. */
34446 /* The length of the response data in number of bytes. */
34448 uint8_t unused_0[7];
34450 * This field is used in Output records to indicate that the output
34451 * is completely written to RAM. This field should be read as '1'
34452 * to indicate that the output has been completely written.
34453 * When writing a command completion or response to an internal
34454 * processor, the order of writes has to be such that this field is
34460 /********************************
34461 * hwrm_cfa_vlan_antispoof_qcfg *
34462 ********************************/
34465 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
34466 struct hwrm_cfa_vlan_antispoof_qcfg_input {
34467 /* The HWRM command request type. */
34470 * The completion ring to send the completion event on. This should
34471 * be the NQ ID returned from the `nq_alloc` HWRM command.
34473 uint16_t cmpl_ring;
34475 * The sequence ID is used by the driver for tracking multiple
34476 * commands. This ID is treated as opaque data by the firmware and
34477 * the value is returned in the `hwrm_resp_hdr` upon completion.
34481 * The target ID of the command:
34482 * * 0x0-0xFFF8 - The function ID
34483 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34484 * * 0xFFFD - Reserved for user-space HWRM interface
34487 uint16_t target_id;
34489 * A physical address pointer pointing to a host buffer that the
34490 * command's response data will be written. This can be either a host
34491 * physical address (HPA) or a guest physical address (GPA) and must
34492 * point to a physically contiguous block of memory.
34494 uint64_t resp_addr;
34496 * Function ID of the function that is being queried.
34497 * Only valid for a VF FID queried by the PF.
34500 uint8_t unused_0[2];
34502 * Maximum number of VLAN entries the firmware is allowed to DMA
34503 * to vlan_tag_mask_tbl.
34505 uint32_t max_vlan_entries;
34507 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
34508 * antispoof table to which firmware will DMA to. Each table
34509 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
34510 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
34511 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
34512 * the mask value should be 0xfff for the 12-bit VLAN ID.
34514 uint64_t vlan_tag_mask_tbl_addr;
34517 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
34518 struct hwrm_cfa_vlan_antispoof_qcfg_output {
34519 /* The specific error status for the command. */
34520 uint16_t error_code;
34521 /* The HWRM command request type. */
34523 /* The sequence ID from the original command. */
34525 /* The length of the response data in number of bytes. */
34527 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
34528 uint32_t num_vlan_entries;
34529 uint8_t unused_0[3];
34531 * This field is used in Output records to indicate that the output
34532 * is completely written to RAM. This field should be read as '1'
34533 * to indicate that the output has been completely written.
34534 * When writing a command completion or response to an internal
34535 * processor, the order of writes has to be such that this field is
34541 /********************************
34542 * hwrm_cfa_tunnel_filter_alloc *
34543 ********************************/
34546 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
34547 struct hwrm_cfa_tunnel_filter_alloc_input {
34548 /* The HWRM command request type. */
34551 * The completion ring to send the completion event on. This should
34552 * be the NQ ID returned from the `nq_alloc` HWRM command.
34554 uint16_t cmpl_ring;
34556 * The sequence ID is used by the driver for tracking multiple
34557 * commands. This ID is treated as opaque data by the firmware and
34558 * the value is returned in the `hwrm_resp_hdr` upon completion.
34562 * The target ID of the command:
34563 * * 0x0-0xFFF8 - The function ID
34564 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34565 * * 0xFFFD - Reserved for user-space HWRM interface
34568 uint16_t target_id;
34570 * A physical address pointer pointing to a host buffer that the
34571 * command's response data will be written. This can be either a host
34572 * physical address (HPA) or a guest physical address (GPA) and must
34573 * point to a physically contiguous block of memory.
34575 uint64_t resp_addr;
34578 * Setting of this flag indicates the applicability to the loopback
34581 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
34585 * This bit must be '1' for the l2_filter_id field to be
34588 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
34591 * This bit must be '1' for the l2_addr field to be
34594 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
34597 * This bit must be '1' for the l2_ivlan field to be
34600 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
34603 * This bit must be '1' for the l3_addr field to be
34606 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
34609 * This bit must be '1' for the l3_addr_type field to be
34612 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
34615 * This bit must be '1' for the t_l3_addr_type field to be
34618 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
34621 * This bit must be '1' for the t_l3_addr field to be
34624 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
34627 * This bit must be '1' for the tunnel_type field to be
34630 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
34633 * This bit must be '1' for the vni field to be
34636 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
34639 * This bit must be '1' for the dst_vnic_id field to be
34642 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
34645 * This bit must be '1' for the mirror_vnic_id field to be
34648 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
34651 * This value identifies a set of CFA data structures used for an L2
34654 uint64_t l2_filter_id;
34656 * This value sets the match value for the inner L2
34658 * Destination MAC address for RX path.
34659 * Source MAC address for TX path.
34661 uint8_t l2_addr[6];
34663 * This value sets VLAN ID value for inner VLAN.
34664 * Only 12-bits of VLAN ID are used in setting the filter.
34668 * The value of inner destination IP address to be used in filtering.
34669 * For IPv4, first four bytes represent the IP address.
34671 uint32_t l3_addr[4];
34673 * The value of tunnel destination IP address to be used in filtering.
34674 * For IPv4, first four bytes represent the IP address.
34676 uint32_t t_l3_addr[4];
34678 * This value indicates the type of inner IP address.
34681 * All others are invalid.
34683 uint8_t l3_addr_type;
34685 * This value indicates the type of tunnel IP address.
34688 * All others are invalid.
34690 uint8_t t_l3_addr_type;
34692 uint8_t tunnel_type;
34694 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34696 /* Virtual eXtensible Local Area Network (VXLAN) */
34697 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34699 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34700 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34702 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34703 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34706 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34708 /* Generic Network Virtualization Encapsulation (Geneve) */
34709 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34711 /* Multi-Protocol Label Switching (MPLS) */
34712 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34714 /* Stateless Transport Tunnel (STT) */
34715 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
34717 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34718 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34720 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34721 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34724 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
34727 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34729 /* Use fixed layer 2 ether type of 0xFFFF */
34730 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
34733 * IPV6 over virtual eXtensible Local Area Network with GPE header
34736 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
34738 /* Any tunneled traffic */
34739 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
34741 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
34742 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
34744 * tunnel_flags allows the user to indicate the tunnel tag detection
34745 * for the tunnel type specified in tunnel_type.
34747 uint8_t tunnel_flags;
34749 * If the tunnel_type is geneve, then this bit indicates if we
34750 * need to match the geneve OAM packet.
34751 * If the tunnel_type is nvgre or gre, then this bit indicates if
34752 * we need to detect checksum present bit in geneve header.
34753 * If the tunnel_type is mpls, then this bit indicates if we need
34754 * to match mpls packet with explicit IPV4/IPV6 null header.
34756 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
34759 * If the tunnel_type is geneve, then this bit indicates if we
34760 * need to detect the critical option bit set in the oam packet.
34761 * If the tunnel_type is nvgre or gre, then this bit indicates
34762 * if we need to match nvgre packets with key present bit set in
34764 * If the tunnel_type is mpls, then this bit indicates if we
34765 * need to match mpls packet with S bit from inner/second label.
34767 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
34770 * If the tunnel_type is geneve, then this bit indicates if we
34771 * need to match geneve packet with extended header bit set in
34773 * If the tunnel_type is nvgre or gre, then this bit indicates
34774 * if we need to match nvgre packets with sequence number
34775 * present bit set in gre header.
34776 * If the tunnel_type is mpls, then this bit indicates if we
34777 * need to match mpls packet with S bit from out/first label.
34779 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
34782 * Virtual Network Identifier (VNI). Only valid with
34783 * tunnel_types VXLAN, NVGRE, and Geneve.
34784 * Only lower 24-bits of VNI field are used
34785 * in setting up the filter.
34788 /* Logical VNIC ID of the destination VNIC. */
34789 uint32_t dst_vnic_id;
34791 * Logical VNIC ID of the VNIC where traffic is
34794 uint32_t mirror_vnic_id;
34797 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
34798 struct hwrm_cfa_tunnel_filter_alloc_output {
34799 /* The specific error status for the command. */
34800 uint16_t error_code;
34801 /* The HWRM command request type. */
34803 /* The sequence ID from the original command. */
34805 /* The length of the response data in number of bytes. */
34807 /* This value is an opaque id into CFA data structures. */
34808 uint64_t tunnel_filter_id;
34810 * The flow id value in bit 0-29 is the actual ID of the flow
34811 * associated with this filter and it shall be used to match
34812 * and associate the flow identifier returned in completion
34813 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
34814 * shall indicate no valid flow id.
34817 /* Indicate the flow id value. */
34818 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
34819 UINT32_C(0x3fffffff)
34820 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
34821 /* Indicate type of the flow. */
34822 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
34823 UINT32_C(0x40000000)
34825 * If this bit set to 0, then it indicates that the flow is
34828 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
34829 (UINT32_C(0x0) << 30)
34831 * If this bit is set to 1, then it indicates that the flow is
34834 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
34835 (UINT32_C(0x1) << 30)
34836 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
34837 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
34838 /* Indicate the flow direction. */
34839 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
34840 UINT32_C(0x80000000)
34841 /* If this bit set to 0, then it indicates rx flow. */
34842 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
34843 (UINT32_C(0x0) << 31)
34844 /* If this bit is set to 1, then it indicates that tx flow. */
34845 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
34846 (UINT32_C(0x1) << 31)
34847 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
34848 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
34849 uint8_t unused_0[3];
34851 * This field is used in Output records to indicate that the output
34852 * is completely written to RAM. This field should be read as '1'
34853 * to indicate that the output has been completely written.
34854 * When writing a command completion or response to an internal
34855 * processor, the order of writes has to be such that this field is
34861 /*******************************
34862 * hwrm_cfa_tunnel_filter_free *
34863 *******************************/
34866 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
34867 struct hwrm_cfa_tunnel_filter_free_input {
34868 /* The HWRM command request type. */
34871 * The completion ring to send the completion event on. This should
34872 * be the NQ ID returned from the `nq_alloc` HWRM command.
34874 uint16_t cmpl_ring;
34876 * The sequence ID is used by the driver for tracking multiple
34877 * commands. This ID is treated as opaque data by the firmware and
34878 * the value is returned in the `hwrm_resp_hdr` upon completion.
34882 * The target ID of the command:
34883 * * 0x0-0xFFF8 - The function ID
34884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34885 * * 0xFFFD - Reserved for user-space HWRM interface
34888 uint16_t target_id;
34890 * A physical address pointer pointing to a host buffer that the
34891 * command's response data will be written. This can be either a host
34892 * physical address (HPA) or a guest physical address (GPA) and must
34893 * point to a physically contiguous block of memory.
34895 uint64_t resp_addr;
34896 /* This value is an opaque id into CFA data structures. */
34897 uint64_t tunnel_filter_id;
34900 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
34901 struct hwrm_cfa_tunnel_filter_free_output {
34902 /* The specific error status for the command. */
34903 uint16_t error_code;
34904 /* The HWRM command request type. */
34906 /* The sequence ID from the original command. */
34908 /* The length of the response data in number of bytes. */
34910 uint8_t unused_0[7];
34912 * This field is used in Output records to indicate that the output
34913 * is completely written to RAM. This field should be read as '1'
34914 * to indicate that the output has been completely written.
34915 * When writing a command completion or response to an internal
34916 * processor, the order of writes has to be such that this field is
34922 /***************************************
34923 * hwrm_cfa_redirect_tunnel_type_alloc *
34924 ***************************************/
34927 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
34928 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
34929 /* The HWRM command request type. */
34932 * The completion ring to send the completion event on. This should
34933 * be the NQ ID returned from the `nq_alloc` HWRM command.
34935 uint16_t cmpl_ring;
34937 * The sequence ID is used by the driver for tracking multiple
34938 * commands. This ID is treated as opaque data by the firmware and
34939 * the value is returned in the `hwrm_resp_hdr` upon completion.
34943 * The target ID of the command:
34944 * * 0x0-0xFFF8 - The function ID
34945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34946 * * 0xFFFD - Reserved for user-space HWRM interface
34949 uint16_t target_id;
34951 * A physical address pointer pointing to a host buffer that the
34952 * command's response data will be written. This can be either a host
34953 * physical address (HPA) or a guest physical address (GPA) and must
34954 * point to a physically contiguous block of memory.
34956 uint64_t resp_addr;
34957 /* The destination function id, to whom the traffic is redirected. */
34960 uint8_t tunnel_type;
34962 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
34964 /* Virtual eXtensible Local Area Network (VXLAN) */
34965 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
34967 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34968 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
34970 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34971 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
34974 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
34976 /* Generic Network Virtualization Encapsulation (Geneve) */
34977 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
34979 /* Multi-Protocol Label Switching (MPLS) */
34980 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
34982 /* Stateless Transport Tunnel (STT) */
34983 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
34985 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34986 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
34988 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34989 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
34992 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
34995 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
34997 /* Use fixed layer 2 ether type of 0xFFFF */
34998 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35001 * IPV6 over virtual eXtensible Local Area Network with GPE header
35004 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35006 /* Any tunneled traffic */
35007 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35009 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35010 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35011 /* Tunnel alloc flags. */
35014 * Setting of this flag indicates modify existing redirect tunnel
35015 * to new destination function ID.
35017 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
35019 uint8_t unused_0[4];
35022 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
35023 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
35024 /* The specific error status for the command. */
35025 uint16_t error_code;
35026 /* The HWRM command request type. */
35028 /* The sequence ID from the original command. */
35030 /* The length of the response data in number of bytes. */
35032 uint8_t unused_0[7];
35034 * This field is used in Output records to indicate that the output
35035 * is completely written to RAM. This field should be read as '1'
35036 * to indicate that the output has been completely written.
35037 * When writing a command completion or response to an internal
35038 * processor, the order of writes has to be such that this field is
35044 /**************************************
35045 * hwrm_cfa_redirect_tunnel_type_free *
35046 **************************************/
35049 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
35050 struct hwrm_cfa_redirect_tunnel_type_free_input {
35051 /* The HWRM command request type. */
35054 * The completion ring to send the completion event on. This should
35055 * be the NQ ID returned from the `nq_alloc` HWRM command.
35057 uint16_t cmpl_ring;
35059 * The sequence ID is used by the driver for tracking multiple
35060 * commands. This ID is treated as opaque data by the firmware and
35061 * the value is returned in the `hwrm_resp_hdr` upon completion.
35065 * The target ID of the command:
35066 * * 0x0-0xFFF8 - The function ID
35067 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35068 * * 0xFFFD - Reserved for user-space HWRM interface
35071 uint16_t target_id;
35073 * A physical address pointer pointing to a host buffer that the
35074 * command's response data will be written. This can be either a host
35075 * physical address (HPA) or a guest physical address (GPA) and must
35076 * point to a physically contiguous block of memory.
35078 uint64_t resp_addr;
35079 /* The destination function id, to whom the traffic is redirected. */
35082 uint8_t tunnel_type;
35084 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
35086 /* Virtual eXtensible Local Area Network (VXLAN) */
35087 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
35089 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35090 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
35092 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35093 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
35096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
35098 /* Generic Network Virtualization Encapsulation (Geneve) */
35099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
35101 /* Multi-Protocol Label Switching (MPLS) */
35102 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
35104 /* Stateless Transport Tunnel (STT) */
35105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
35107 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
35110 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35111 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35114 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35117 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35119 /* Use fixed layer 2 ether type of 0xFFFF */
35120 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
35123 * IPV6 over virtual eXtensible Local Area Network with GPE header
35126 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35128 /* Any tunneled traffic */
35129 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35131 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
35132 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
35133 uint8_t unused_0[5];
35136 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
35137 struct hwrm_cfa_redirect_tunnel_type_free_output {
35138 /* The specific error status for the command. */
35139 uint16_t error_code;
35140 /* The HWRM command request type. */
35142 /* The sequence ID from the original command. */
35144 /* The length of the response data in number of bytes. */
35146 uint8_t unused_0[7];
35148 * This field is used in Output records to indicate that the output
35149 * is completely written to RAM. This field should be read as '1'
35150 * to indicate that the output has been completely written.
35151 * When writing a command completion or response to an internal
35152 * processor, the order of writes has to be such that this field is
35158 /**************************************
35159 * hwrm_cfa_redirect_tunnel_type_info *
35160 **************************************/
35163 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
35164 struct hwrm_cfa_redirect_tunnel_type_info_input {
35165 /* The HWRM command request type. */
35168 * The completion ring to send the completion event on. This should
35169 * be the NQ ID returned from the `nq_alloc` HWRM command.
35171 uint16_t cmpl_ring;
35173 * The sequence ID is used by the driver for tracking multiple
35174 * commands. This ID is treated as opaque data by the firmware and
35175 * the value is returned in the `hwrm_resp_hdr` upon completion.
35179 * The target ID of the command:
35180 * * 0x0-0xFFF8 - The function ID
35181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35182 * * 0xFFFD - Reserved for user-space HWRM interface
35185 uint16_t target_id;
35187 * A physical address pointer pointing to a host buffer that the
35188 * command's response data will be written. This can be either a host
35189 * physical address (HPA) or a guest physical address (GPA) and must
35190 * point to a physically contiguous block of memory.
35192 uint64_t resp_addr;
35193 /* The source function id. */
35196 uint8_t tunnel_type;
35198 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
35200 /* Virtual eXtensible Local Area Network (VXLAN) */
35201 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
35203 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35204 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
35206 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35207 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
35210 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
35212 /* Generic Network Virtualization Encapsulation (Geneve) */
35213 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
35215 /* Multi-Protocol Label Switching (MPLS) */
35216 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
35218 /* Stateless Transport Tunnel (STT) */
35219 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
35221 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35222 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
35224 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35228 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35233 /* Use fixed layer 2 ether type of 0xFFFF */
35234 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
35237 * IPV6 over virtual eXtensible Local Area Network with GPE header
35240 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35242 /* Any tunneled traffic */
35243 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35245 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
35246 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
35247 uint8_t unused_0[5];
35250 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
35251 struct hwrm_cfa_redirect_tunnel_type_info_output {
35252 /* The specific error status for the command. */
35253 uint16_t error_code;
35254 /* The HWRM command request type. */
35256 /* The sequence ID from the original command. */
35258 /* The length of the response data in number of bytes. */
35260 /* The destination function id, to whom the traffic is redirected. */
35262 uint8_t unused_0[5];
35264 * This field is used in Output records to indicate that the output
35265 * is completely written to RAM. This field should be read as '1'
35266 * to indicate that the output has been completely written.
35267 * When writing a command completion or response to an internal
35268 * processor, the order of writes has to be such that this field is
35274 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
35275 struct hwrm_vxlan_ipv4_hdr {
35276 /* IPv4 version and header length. */
35278 /* IPv4 header length */
35279 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
35280 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
35282 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
35283 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
35284 /* IPv4 type of service. */
35286 /* IPv4 identification. */
35288 /* IPv4 flags and offset. */
35289 uint16_t flags_frag_offset;
35292 /* IPv4 protocol. */
35294 /* IPv4 source address. */
35295 uint32_t src_ip_addr;
35296 /* IPv4 destination address. */
35297 uint32_t dest_ip_addr;
35300 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
35301 struct hwrm_vxlan_ipv6_hdr {
35302 /* IPv6 version, traffic class and flow label. */
35303 uint32_t ver_tc_flow_label;
35304 /* IPv6 version shift */
35305 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
35307 /* IPv6 version mask */
35308 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
35309 UINT32_C(0xf0000000)
35310 /* IPv6 TC shift */
35311 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
35314 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
35315 UINT32_C(0xff00000)
35316 /* IPv6 flow label shift */
35317 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
35319 /* IPv6 flow label mask */
35320 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
35322 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
35323 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
35324 /* IPv6 payload length. */
35325 uint16_t payload_len;
35326 /* IPv6 next header. */
35330 /* IPv6 source address. */
35331 uint32_t src_ip_addr[4];
35332 /* IPv6 destination address. */
35333 uint32_t dest_ip_addr[4];
35336 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
35337 struct hwrm_cfa_encap_data_vxlan {
35338 /* Source MAC address. */
35339 uint8_t src_mac_addr[6];
35342 /* Destination MAC address. */
35343 uint8_t dst_mac_addr[6];
35344 /* Number of VLAN tags. */
35345 uint8_t num_vlan_tags;
35348 /* Outer VLAN TPID. */
35349 uint16_t ovlan_tpid;
35350 /* Outer VLAN TCI. */
35351 uint16_t ovlan_tci;
35352 /* Inner VLAN TPID. */
35353 uint16_t ivlan_tpid;
35354 /* Inner VLAN TCI. */
35355 uint16_t ivlan_tci;
35356 /* L3 header fields. */
35358 /* IP version mask. */
35359 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
35360 /* IP version 4. */
35361 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
35362 /* IP version 6. */
35363 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
35364 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
35365 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
35366 /* UDP source port. */
35368 /* UDP destination port. */
35370 /* VXLAN Network Identifier. */
35373 * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN
35376 uint8_t hdr_rsvd0[3];
35377 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
35379 /* VXLAN header flags field. */
35384 /*******************************
35385 * hwrm_cfa_encap_record_alloc *
35386 *******************************/
35389 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
35390 struct hwrm_cfa_encap_record_alloc_input {
35391 /* The HWRM command request type. */
35394 * The completion ring to send the completion event on. This should
35395 * be the NQ ID returned from the `nq_alloc` HWRM command.
35397 uint16_t cmpl_ring;
35399 * The sequence ID is used by the driver for tracking multiple
35400 * commands. This ID is treated as opaque data by the firmware and
35401 * the value is returned in the `hwrm_resp_hdr` upon completion.
35405 * The target ID of the command:
35406 * * 0x0-0xFFF8 - The function ID
35407 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35408 * * 0xFFFD - Reserved for user-space HWRM interface
35411 uint16_t target_id;
35413 * A physical address pointer pointing to a host buffer that the
35414 * command's response data will be written. This can be either a host
35415 * physical address (HPA) or a guest physical address (GPA) and must
35416 * point to a physically contiguous block of memory.
35418 uint64_t resp_addr;
35421 * Setting of this flag indicates the applicability to the loopback
35424 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
35427 * Setting of this flag indicates this encap record is external
35428 * encap record. Resetting of this flag indicates this flag is
35429 * internal encap record and this is the default setting.
35431 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
35433 /* Encapsulation Type. */
35434 uint8_t encap_type;
35435 /* Virtual eXtensible Local Area Network (VXLAN) */
35436 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
35438 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35439 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
35441 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
35442 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
35445 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
35447 /* Generic Network Virtualization Encapsulation (Geneve) */
35448 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
35450 /* Multi-Protocol Label Switching (MPLS) */
35451 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
35454 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
35456 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35457 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
35459 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35460 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
35463 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35466 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
35468 /* Use fixed layer 2 ether type of 0xFFFF */
35469 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
35472 * IPV6 over virtual eXtensible Local Area Network with GPE header
35475 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
35477 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
35478 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
35479 uint8_t unused_0[3];
35480 /* This value is encap data used for the given encap type. */
35481 uint32_t encap_data[20];
35484 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
35485 struct hwrm_cfa_encap_record_alloc_output {
35486 /* The specific error status for the command. */
35487 uint16_t error_code;
35488 /* The HWRM command request type. */
35490 /* The sequence ID from the original command. */
35492 /* The length of the response data in number of bytes. */
35494 /* This value is an opaque id into CFA data structures. */
35495 uint32_t encap_record_id;
35496 uint8_t unused_0[3];
35498 * This field is used in Output records to indicate that the output
35499 * is completely written to RAM. This field should be read as '1'
35500 * to indicate that the output has been completely written.
35501 * When writing a command completion or response to an internal
35502 * processor, the order of writes has to be such that this field is
35508 /******************************
35509 * hwrm_cfa_encap_record_free *
35510 ******************************/
35513 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
35514 struct hwrm_cfa_encap_record_free_input {
35515 /* The HWRM command request type. */
35518 * The completion ring to send the completion event on. This should
35519 * be the NQ ID returned from the `nq_alloc` HWRM command.
35521 uint16_t cmpl_ring;
35523 * The sequence ID is used by the driver for tracking multiple
35524 * commands. This ID is treated as opaque data by the firmware and
35525 * the value is returned in the `hwrm_resp_hdr` upon completion.
35529 * The target ID of the command:
35530 * * 0x0-0xFFF8 - The function ID
35531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35532 * * 0xFFFD - Reserved for user-space HWRM interface
35535 uint16_t target_id;
35537 * A physical address pointer pointing to a host buffer that the
35538 * command's response data will be written. This can be either a host
35539 * physical address (HPA) or a guest physical address (GPA) and must
35540 * point to a physically contiguous block of memory.
35542 uint64_t resp_addr;
35543 /* This value is an opaque id into CFA data structures. */
35544 uint32_t encap_record_id;
35545 uint8_t unused_0[4];
35548 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
35549 struct hwrm_cfa_encap_record_free_output {
35550 /* The specific error status for the command. */
35551 uint16_t error_code;
35552 /* The HWRM command request type. */
35554 /* The sequence ID from the original command. */
35556 /* The length of the response data in number of bytes. */
35558 uint8_t unused_0[7];
35560 * This field is used in Output records to indicate that the output
35561 * is completely written to RAM. This field should be read as '1'
35562 * to indicate that the output has been completely written.
35563 * When writing a command completion or response to an internal
35564 * processor, the order of writes has to be such that this field is
35570 /********************************
35571 * hwrm_cfa_ntuple_filter_alloc *
35572 ********************************/
35575 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
35576 struct hwrm_cfa_ntuple_filter_alloc_input {
35577 /* The HWRM command request type. */
35580 * The completion ring to send the completion event on. This should
35581 * be the NQ ID returned from the `nq_alloc` HWRM command.
35583 uint16_t cmpl_ring;
35585 * The sequence ID is used by the driver for tracking multiple
35586 * commands. This ID is treated as opaque data by the firmware and
35587 * the value is returned in the `hwrm_resp_hdr` upon completion.
35591 * The target ID of the command:
35592 * * 0x0-0xFFF8 - The function ID
35593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35594 * * 0xFFFD - Reserved for user-space HWRM interface
35597 uint16_t target_id;
35599 * A physical address pointer pointing to a host buffer that the
35600 * command's response data will be written. This can be either a host
35601 * physical address (HPA) or a guest physical address (GPA) and must
35602 * point to a physically contiguous block of memory.
35604 uint64_t resp_addr;
35607 * Setting of this flag indicates the applicability to the loopback
35610 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
35613 * Setting of this flag indicates drop action. If this flag is not
35614 * set, then it should be considered accept action.
35616 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
35619 * Setting of this flag indicates that a meter is expected to be
35620 * attached to this flow. This hint can be used when choosing the
35621 * action record format required for the flow.
35623 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
35626 * Setting of this flag indicates that the dst_id field contains
35627 * function ID. If this is not set it indicates dest_id is VNIC
35630 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
35633 * Setting of this flag indicates match on arp reply when ethertype
35634 * is 0x0806. If this is not set it indicates no specific arp opcode
35637 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
35640 * Setting of this flag indicates that the dst_id field contains RFS
35641 * ring table index. If this is not set it indicates dst_id is VNIC
35642 * or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
35643 * can’t be set at the same time.
35645 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
35649 * This bit must be '1' for the l2_filter_id field to be
35652 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
35655 * This bit must be '1' for the ethertype field to be
35658 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
35661 * This bit must be '1' for the tunnel_type field to be
35664 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
35667 * This bit must be '1' for the src_macaddr field to be
35670 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
35673 * This bit must be '1' for the ipaddr_type field to be
35676 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
35679 * This bit must be '1' for the src_ipaddr field to be
35682 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
35685 * This bit must be '1' for the src_ipaddr_mask field to be
35688 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
35691 * This bit must be '1' for the dst_ipaddr field to be
35694 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
35697 * This bit must be '1' for the dst_ipaddr_mask field to be
35700 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
35703 * This bit must be '1' for the ip_protocol field to be
35706 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
35709 * This bit must be '1' for the src_port field to be
35712 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
35715 * This bit must be '1' for the src_port_mask field to be
35718 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
35721 * This bit must be '1' for the dst_port field to be
35724 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
35727 * This bit must be '1' for the dst_port_mask field to be
35730 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
35733 * This bit must be '1' for the pri_hint field to be
35736 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
35739 * This bit must be '1' for the ntuple_filter_id field to be
35742 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
35745 * This bit must be '1' for the dst_id field to be
35748 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
35751 * This bit must be '1' for the mirror_vnic_id field to be
35754 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
35757 * This bit must be '1' for the dst_macaddr field to be
35760 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
35762 /* This flag is deprecated. */
35763 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
35766 * This value identifies a set of CFA data structures used for an L2
35769 uint64_t l2_filter_id;
35771 * This value indicates the source MAC address in
35772 * the Ethernet header.
35774 uint8_t src_macaddr[6];
35775 /* This value indicates the ethertype in the Ethernet header. */
35776 uint16_t ethertype;
35778 * This value indicates the type of IP address.
35781 * All others are invalid.
35783 uint8_t ip_addr_type;
35785 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
35788 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
35791 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
35793 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
35794 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
35796 * The value of protocol filed in IP header.
35797 * Applies to UDP and TCP traffic.
35801 uint8_t ip_protocol;
35803 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
35806 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
35809 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
35811 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
35812 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
35814 * If set, this value shall represent the
35815 * Logical VNIC ID of the destination VNIC for the RX
35816 * path and network port id of the destination port for
35821 * Logical VNIC ID of the VNIC where traffic is
35824 uint16_t mirror_vnic_id;
35826 * This value indicates the tunnel type for this filter.
35827 * If this field is not specified, then the filter shall
35828 * apply to both non-tunneled and tunneled packets.
35829 * If this field conflicts with the tunnel_type specified
35830 * in the l2_filter_id, then the HWRM shall return an
35831 * error for this command.
35833 uint8_t tunnel_type;
35835 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
35837 /* Virtual eXtensible Local Area Network (VXLAN) */
35838 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
35840 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35841 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
35843 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35844 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
35847 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
35849 /* Generic Network Virtualization Encapsulation (Geneve) */
35850 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
35852 /* Multi-Protocol Label Switching (MPLS) */
35853 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
35855 /* Stateless Transport Tunnel (STT) */
35856 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
35858 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35859 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
35861 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35862 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
35865 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
35868 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
35870 /* Use fixed layer 2 ether type of 0xFFFF */
35871 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
35874 * IPV6 over virtual eXtensible Local Area Network with GPE header
35877 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
35879 /* Any tunneled traffic */
35880 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
35882 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
35883 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
35885 * This hint is provided to help in placing
35886 * the filter in the filter table.
35889 /* No preference */
35890 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
35892 /* Above the given filter */
35893 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
35895 /* Below the given filter */
35896 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
35898 /* As high as possible */
35899 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
35901 /* As low as possible */
35902 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
35904 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
35905 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
35907 * The value of source IP address to be used in filtering.
35908 * For IPv4, first four bytes represent the IP address.
35910 uint32_t src_ipaddr[4];
35912 * The value of source IP address mask to be used in
35914 * For IPv4, first four bytes represent the IP address mask.
35916 uint32_t src_ipaddr_mask[4];
35918 * The value of destination IP address to be used in filtering.
35919 * For IPv4, first four bytes represent the IP address.
35921 uint32_t dst_ipaddr[4];
35923 * The value of destination IP address mask to be used in
35925 * For IPv4, first four bytes represent the IP address mask.
35927 uint32_t dst_ipaddr_mask[4];
35929 * The value of source port to be used in filtering.
35930 * Applies to UDP and TCP traffic.
35934 * The value of source port mask to be used in filtering.
35935 * Applies to UDP and TCP traffic.
35937 uint16_t src_port_mask;
35939 * The value of destination port to be used in filtering.
35940 * Applies to UDP and TCP traffic.
35944 * The value of destination port mask to be used in
35946 * Applies to UDP and TCP traffic.
35948 uint16_t dst_port_mask;
35950 * This is the ID of the filter that goes along with
35953 uint64_t ntuple_filter_id_hint;
35956 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
35957 struct hwrm_cfa_ntuple_filter_alloc_output {
35958 /* The specific error status for the command. */
35959 uint16_t error_code;
35960 /* The HWRM command request type. */
35962 /* The sequence ID from the original command. */
35964 /* The length of the response data in number of bytes. */
35966 /* This value is an opaque id into CFA data structures. */
35967 uint64_t ntuple_filter_id;
35969 * The flow id value in bit 0-29 is the actual ID of the flow
35970 * associated with this filter and it shall be used to match
35971 * and associate the flow identifier returned in completion
35972 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
35973 * shall indicate no valid flow id.
35976 /* Indicate the flow id value. */
35977 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
35978 UINT32_C(0x3fffffff)
35979 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
35980 /* Indicate type of the flow. */
35981 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
35982 UINT32_C(0x40000000)
35984 * If this bit set to 0, then it indicates that the flow is
35987 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
35988 (UINT32_C(0x0) << 30)
35990 * If this bit is set to 1, then it indicates that the flow is
35993 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
35994 (UINT32_C(0x1) << 30)
35995 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
35996 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
35997 /* Indicate the flow direction. */
35998 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
35999 UINT32_C(0x80000000)
36000 /* If this bit set to 0, then it indicates rx flow. */
36001 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
36002 (UINT32_C(0x0) << 31)
36003 /* If this bit is set to 1, then it indicates that tx flow. */
36004 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
36005 (UINT32_C(0x1) << 31)
36006 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
36007 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
36008 uint8_t unused_0[3];
36010 * This field is used in Output records to indicate that the output
36011 * is completely written to RAM. This field should be read as '1'
36012 * to indicate that the output has been completely written.
36013 * When writing a command completion or response to an internal
36014 * processor, the order of writes has to be such that this field is
36020 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
36021 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
36023 * command specific error codes that goes to
36024 * the cmd_err field in Common HWRM Error Response.
36027 /* Unknown error */
36028 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
36030 /* Unable to complete operation due to conflict with Rx Mask VLAN */
36031 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
36033 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
36034 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
36035 uint8_t unused_0[7];
36038 /*******************************
36039 * hwrm_cfa_ntuple_filter_free *
36040 *******************************/
36043 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
36044 struct hwrm_cfa_ntuple_filter_free_input {
36045 /* The HWRM command request type. */
36048 * The completion ring to send the completion event on. This should
36049 * be the NQ ID returned from the `nq_alloc` HWRM command.
36051 uint16_t cmpl_ring;
36053 * The sequence ID is used by the driver for tracking multiple
36054 * commands. This ID is treated as opaque data by the firmware and
36055 * the value is returned in the `hwrm_resp_hdr` upon completion.
36059 * The target ID of the command:
36060 * * 0x0-0xFFF8 - The function ID
36061 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36062 * * 0xFFFD - Reserved for user-space HWRM interface
36065 uint16_t target_id;
36067 * A physical address pointer pointing to a host buffer that the
36068 * command's response data will be written. This can be either a host
36069 * physical address (HPA) or a guest physical address (GPA) and must
36070 * point to a physically contiguous block of memory.
36072 uint64_t resp_addr;
36073 /* This value is an opaque id into CFA data structures. */
36074 uint64_t ntuple_filter_id;
36077 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
36078 struct hwrm_cfa_ntuple_filter_free_output {
36079 /* The specific error status for the command. */
36080 uint16_t error_code;
36081 /* The HWRM command request type. */
36083 /* The sequence ID from the original command. */
36085 /* The length of the response data in number of bytes. */
36087 uint8_t unused_0[7];
36089 * This field is used in Output records to indicate that the output
36090 * is completely written to RAM. This field should be read as '1'
36091 * to indicate that the output has been completely written.
36092 * When writing a command completion or response to an internal
36093 * processor, the order of writes has to be such that this field is
36099 /******************************
36100 * hwrm_cfa_ntuple_filter_cfg *
36101 ******************************/
36104 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
36105 struct hwrm_cfa_ntuple_filter_cfg_input {
36106 /* The HWRM command request type. */
36109 * The completion ring to send the completion event on. This should
36110 * be the NQ ID returned from the `nq_alloc` HWRM command.
36112 uint16_t cmpl_ring;
36114 * The sequence ID is used by the driver for tracking multiple
36115 * commands. This ID is treated as opaque data by the firmware and
36116 * the value is returned in the `hwrm_resp_hdr` upon completion.
36120 * The target ID of the command:
36121 * * 0x0-0xFFF8 - The function ID
36122 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36123 * * 0xFFFD - Reserved for user-space HWRM interface
36126 uint16_t target_id;
36128 * A physical address pointer pointing to a host buffer that the
36129 * command's response data will be written. This can be either a host
36130 * physical address (HPA) or a guest physical address (GPA) and must
36131 * point to a physically contiguous block of memory.
36133 uint64_t resp_addr;
36136 * This bit must be '1' for the new_dst_id field to be
36139 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
36142 * This bit must be '1' for the new_mirror_vnic_id field to be
36145 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
36148 * This bit must be '1' for the new_meter_instance_id field to be
36151 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
36155 * Setting this bit to 1 indicates that dest_id field contains FID.
36156 * Setting this to 0 indicates that dest_id field contains VNIC or
36159 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
36162 * Setting of this flag indicates that the new_dst_id field contains
36163 * RFS ring table index. If this is not set it indicates new_dst_id
36164 * is VNIC or VPORT or function ID. Note dest_fid and
36165 * dest_rfs_ring_idx can’t be set at the same time.
36167 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
36169 /* This value is an opaque id into CFA data structures. */
36170 uint64_t ntuple_filter_id;
36172 * If set, this value shall represent the new
36173 * Logical VNIC ID of the destination VNIC for the RX
36174 * path and new network port id of the destination port for
36177 uint32_t new_dst_id;
36179 * New Logical VNIC ID of the VNIC where traffic is
36182 uint32_t new_mirror_vnic_id;
36184 * New meter to attach to the flow. Specifying the
36185 * invalid instance ID is used to remove any existing
36186 * meter from the flow.
36188 uint16_t new_meter_instance_id;
36190 * A value of 0xfff is considered invalid and implies the
36191 * instance is not configured.
36193 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
36195 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
36196 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
36197 uint8_t unused_1[6];
36200 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
36201 struct hwrm_cfa_ntuple_filter_cfg_output {
36202 /* The specific error status for the command. */
36203 uint16_t error_code;
36204 /* The HWRM command request type. */
36206 /* The sequence ID from the original command. */
36208 /* The length of the response data in number of bytes. */
36210 uint8_t unused_0[7];
36212 * This field is used in Output records to indicate that the output
36213 * is completely written to RAM. This field should be read as '1'
36214 * to indicate that the output has been completely written.
36215 * When writing a command completion or response to an internal
36216 * processor, the order of writes has to be such that this field is
36222 /**************************
36223 * hwrm_cfa_em_flow_alloc *
36224 **************************/
36227 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
36228 struct hwrm_cfa_em_flow_alloc_input {
36229 /* The HWRM command request type. */
36232 * The completion ring to send the completion event on. This should
36233 * be the NQ ID returned from the `nq_alloc` HWRM command.
36235 uint16_t cmpl_ring;
36237 * The sequence ID is used by the driver for tracking multiple
36238 * commands. This ID is treated as opaque data by the firmware and
36239 * the value is returned in the `hwrm_resp_hdr` upon completion.
36243 * The target ID of the command:
36244 * * 0x0-0xFFF8 - The function ID
36245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36246 * * 0xFFFD - Reserved for user-space HWRM interface
36249 uint16_t target_id;
36251 * A physical address pointer pointing to a host buffer that the
36252 * command's response data will be written. This can be either a host
36253 * physical address (HPA) or a guest physical address (GPA) and must
36254 * point to a physically contiguous block of memory.
36256 uint64_t resp_addr;
36259 * Enumeration denoting the RX, TX type of the resource.
36260 * This enumeration is used for resources that are similar for both
36261 * TX and RX paths of the chip.
36263 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
36265 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
36267 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
36268 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
36269 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
36271 * Setting of this flag indicates enabling of a byte counter for a
36274 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
36276 * Setting of this flag indicates enabling of a packet counter for a
36279 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
36281 * Setting of this flag indicates de-capsulation action for the
36284 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
36286 * Setting of this flag indicates encapsulation action for the
36289 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
36291 * Setting of this flag indicates drop action. If this flag is not
36292 * set, then it should be considered accept action.
36294 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
36296 * Setting of this flag indicates that a meter is expected to be
36297 * attached to this flow. This hint can be used when choosing the
36298 * action record format required for the flow.
36300 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
36303 * This bit must be '1' for the l2_filter_id field to be
36306 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
36309 * This bit must be '1' for the tunnel_type field to be
36312 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
36315 * This bit must be '1' for the tunnel_id field to be
36318 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
36321 * This bit must be '1' for the src_macaddr field to be
36324 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
36327 * This bit must be '1' for the dst_macaddr field to be
36330 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
36333 * This bit must be '1' for the ovlan_vid field to be
36336 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
36339 * This bit must be '1' for the ivlan_vid field to be
36342 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
36345 * This bit must be '1' for the ethertype field to be
36348 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
36351 * This bit must be '1' for the src_ipaddr field to be
36354 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
36357 * This bit must be '1' for the dst_ipaddr field to be
36360 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
36363 * This bit must be '1' for the ipaddr_type field to be
36366 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
36369 * This bit must be '1' for the ip_protocol field to be
36372 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
36375 * This bit must be '1' for the src_port field to be
36378 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
36381 * This bit must be '1' for the dst_port field to be
36384 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
36387 * This bit must be '1' for the dst_id field to be
36390 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
36393 * This bit must be '1' for the mirror_vnic_id field to be
36396 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
36399 * This bit must be '1' for the encap_record_id field to be
36402 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
36405 * This bit must be '1' for the meter_instance_id field to be
36408 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
36411 * This value identifies a set of CFA data structures used for an L2
36414 uint64_t l2_filter_id;
36416 uint8_t tunnel_type;
36418 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
36420 /* Virtual eXtensible Local Area Network (VXLAN) */
36421 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
36423 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
36424 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
36426 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
36427 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
36430 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
36432 /* Generic Network Virtualization Encapsulation (Geneve) */
36433 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
36435 /* Multi-Protocol Label Switching (MPLS) */
36436 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
36438 /* Stateless Transport Tunnel (STT) */
36439 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
36441 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
36442 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
36444 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
36445 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
36448 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
36451 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
36453 /* Use fixed layer 2 ether type of 0xFFFF */
36454 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
36457 * IPV6 over virtual eXtensible Local Area Network with GPE header
36460 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
36462 /* Any tunneled traffic */
36463 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
36465 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
36466 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
36467 uint8_t unused_0[3];
36469 * Tunnel identifier.
36470 * Virtual Network Identifier (VNI). Only valid with
36471 * tunnel_types VXLAN, NVGRE, and Geneve.
36472 * Only lower 24-bits of VNI field are used
36473 * in setting up the filter.
36475 uint32_t tunnel_id;
36477 * This value indicates the source MAC address in
36478 * the Ethernet header.
36480 uint8_t src_macaddr[6];
36481 /* The meter instance to attach to the flow. */
36482 uint16_t meter_instance_id;
36484 * A value of 0xfff is considered invalid and implies the
36485 * instance is not configured.
36487 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
36489 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
36490 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
36492 * This value indicates the destination MAC address in
36493 * the Ethernet header.
36495 uint8_t dst_macaddr[6];
36497 * This value indicates the VLAN ID of the outer VLAN tag
36498 * in the Ethernet header.
36500 uint16_t ovlan_vid;
36502 * This value indicates the VLAN ID of the inner VLAN tag
36503 * in the Ethernet header.
36505 uint16_t ivlan_vid;
36506 /* This value indicates the ethertype in the Ethernet header. */
36507 uint16_t ethertype;
36509 * This value indicates the type of IP address.
36512 * All others are invalid.
36514 uint8_t ip_addr_type;
36516 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
36518 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
36520 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
36521 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
36522 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
36524 * The value of protocol filed in IP header.
36525 * Applies to UDP and TCP traffic.
36529 uint8_t ip_protocol;
36531 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
36533 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
36535 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
36536 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
36537 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
36538 uint8_t unused_1[2];
36540 * The value of source IP address to be used in filtering.
36541 * For IPv4, first four bytes represent the IP address.
36543 uint32_t src_ipaddr[4];
36545 * big_endian = True
36546 * The value of destination IP address to be used in filtering.
36547 * For IPv4, first four bytes represent the IP address.
36549 uint32_t dst_ipaddr[4];
36551 * The value of source port to be used in filtering.
36552 * Applies to UDP and TCP traffic.
36556 * The value of destination port to be used in filtering.
36557 * Applies to UDP and TCP traffic.
36561 * If set, this value shall represent the
36562 * Logical VNIC ID of the destination VNIC for the RX
36563 * path and network port id of the destination port for
36568 * Logical VNIC ID of the VNIC where traffic is
36571 uint16_t mirror_vnic_id;
36572 /* Logical ID of the encapsulation record. */
36573 uint32_t encap_record_id;
36574 uint8_t unused_2[4];
36577 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
36578 struct hwrm_cfa_em_flow_alloc_output {
36579 /* The specific error status for the command. */
36580 uint16_t error_code;
36581 /* The HWRM command request type. */
36583 /* The sequence ID from the original command. */
36585 /* The length of the response data in number of bytes. */
36587 /* This value is an opaque id into CFA data structures. */
36588 uint64_t em_filter_id;
36590 * The flow id value in bit 0-29 is the actual ID of the flow
36591 * associated with this filter and it shall be used to match
36592 * and associate the flow identifier returned in completion
36593 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
36594 * shall indicate no valid flow id.
36597 /* Indicate the flow id value. */
36598 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
36599 UINT32_C(0x3fffffff)
36600 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
36601 /* Indicate type of the flow. */
36602 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
36603 UINT32_C(0x40000000)
36605 * If this bit set to 0, then it indicates that the flow is
36608 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
36609 (UINT32_C(0x0) << 30)
36611 * If this bit is set to 1, then it indicates that the flow is
36614 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
36615 (UINT32_C(0x1) << 30)
36616 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
36617 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
36618 /* Indicate the flow direction. */
36619 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
36620 UINT32_C(0x80000000)
36621 /* If this bit set to 0, then it indicates rx flow. */
36622 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
36623 (UINT32_C(0x0) << 31)
36624 /* If this bit is set to 1, then it indicates that tx flow. */
36625 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
36626 (UINT32_C(0x1) << 31)
36627 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
36628 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
36629 uint8_t unused_0[3];
36631 * This field is used in Output records to indicate that the output
36632 * is completely written to RAM. This field should be read as '1'
36633 * to indicate that the output has been completely written.
36634 * When writing a command completion or response to an internal
36635 * processor, the order of writes has to be such that this field is
36641 /*************************
36642 * hwrm_cfa_em_flow_free *
36643 *************************/
36646 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
36647 struct hwrm_cfa_em_flow_free_input {
36648 /* The HWRM command request type. */
36651 * The completion ring to send the completion event on. This should
36652 * be the NQ ID returned from the `nq_alloc` HWRM command.
36654 uint16_t cmpl_ring;
36656 * The sequence ID is used by the driver for tracking multiple
36657 * commands. This ID is treated as opaque data by the firmware and
36658 * the value is returned in the `hwrm_resp_hdr` upon completion.
36662 * The target ID of the command:
36663 * * 0x0-0xFFF8 - The function ID
36664 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36665 * * 0xFFFD - Reserved for user-space HWRM interface
36668 uint16_t target_id;
36670 * A physical address pointer pointing to a host buffer that the
36671 * command's response data will be written. This can be either a host
36672 * physical address (HPA) or a guest physical address (GPA) and must
36673 * point to a physically contiguous block of memory.
36675 uint64_t resp_addr;
36676 /* This value is an opaque id into CFA data structures. */
36677 uint64_t em_filter_id;
36680 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
36681 struct hwrm_cfa_em_flow_free_output {
36682 /* The specific error status for the command. */
36683 uint16_t error_code;
36684 /* The HWRM command request type. */
36686 /* The sequence ID from the original command. */
36688 /* The length of the response data in number of bytes. */
36690 uint8_t unused_0[7];
36692 * This field is used in Output records to indicate that the output
36693 * is completely written to RAM. This field should be read as '1'
36694 * to indicate that the output has been completely written.
36695 * When writing a command completion or response to an internal
36696 * processor, the order of writes has to be such that this field is
36702 /************************
36703 * hwrm_cfa_meter_qcaps *
36704 ************************/
36707 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
36708 struct hwrm_cfa_meter_qcaps_input {
36709 /* The HWRM command request type. */
36712 * The completion ring to send the completion event on. This should
36713 * be the NQ ID returned from the `nq_alloc` HWRM command.
36715 uint16_t cmpl_ring;
36717 * The sequence ID is used by the driver for tracking multiple
36718 * commands. This ID is treated as opaque data by the firmware and
36719 * the value is returned in the `hwrm_resp_hdr` upon completion.
36723 * The target ID of the command:
36724 * * 0x0-0xFFF8 - The function ID
36725 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36726 * * 0xFFFD - Reserved for user-space HWRM interface
36729 uint16_t target_id;
36731 * A physical address pointer pointing to a host buffer that the
36732 * command's response data will be written. This can be either a host
36733 * physical address (HPA) or a guest physical address (GPA) and must
36734 * point to a physically contiguous block of memory.
36736 uint64_t resp_addr;
36739 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
36740 struct hwrm_cfa_meter_qcaps_output {
36741 /* The specific error status for the command. */
36742 uint16_t error_code;
36743 /* The HWRM command request type. */
36745 /* The sequence ID from the original command. */
36747 /* The length of the response data in number of bytes. */
36751 * Enumeration denoting the clock at which the Meter is running
36752 * with. This enumeration is used for resources that are similar
36753 * for both TX and RX paths of the chip.
36755 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
36756 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
36758 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
36760 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
36761 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
36762 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
36763 uint8_t unused_0[4];
36765 * The minimum guaranteed number of tx meter profiles supported
36766 * for this function.
36768 uint16_t min_tx_profile;
36770 * The maximum non-guaranteed number of tx meter profiles supported
36771 * for this function.
36773 uint16_t max_tx_profile;
36775 * The minimum guaranteed number of rx meter profiles supported
36776 * for this function.
36778 uint16_t min_rx_profile;
36780 * The maximum non-guaranteed number of rx meter profiles supported
36781 * for this function.
36783 uint16_t max_rx_profile;
36785 * The minimum guaranteed number of tx meter instances supported
36786 * for this function.
36788 uint16_t min_tx_instance;
36790 * The maximum non-guaranteed number of tx meter instances supported
36791 * for this function.
36793 uint16_t max_tx_instance;
36795 * The minimum guaranteed number of rx meter instances supported
36796 * for this function.
36798 uint16_t min_rx_instance;
36800 * The maximum non-guaranteed number of rx meter instances supported
36801 * for this function.
36803 uint16_t max_rx_instance;
36804 uint8_t unused_1[7];
36806 * This field is used in Output records to indicate that the output
36807 * is completely written to RAM. This field should be read as '1'
36808 * to indicate that the output has been completely written.
36809 * When writing a command completion or response to an internal
36810 * processor, the order of writes has to be such that this field is
36816 /********************************
36817 * hwrm_cfa_meter_profile_alloc *
36818 ********************************/
36821 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
36822 struct hwrm_cfa_meter_profile_alloc_input {
36823 /* The HWRM command request type. */
36826 * The completion ring to send the completion event on. This should
36827 * be the NQ ID returned from the `nq_alloc` HWRM command.
36829 uint16_t cmpl_ring;
36831 * The sequence ID is used by the driver for tracking multiple
36832 * commands. This ID is treated as opaque data by the firmware and
36833 * the value is returned in the `hwrm_resp_hdr` upon completion.
36837 * The target ID of the command:
36838 * * 0x0-0xFFF8 - The function ID
36839 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36840 * * 0xFFFD - Reserved for user-space HWRM interface
36843 uint16_t target_id;
36845 * A physical address pointer pointing to a host buffer that the
36846 * command's response data will be written. This can be either a host
36847 * physical address (HPA) or a guest physical address (GPA) and must
36848 * point to a physically contiguous block of memory.
36850 uint64_t resp_addr;
36853 * Enumeration denoting the RX, TX type of the resource.
36854 * This enumeration is used for resources that are similar for both
36855 * TX and RX paths of the chip.
36857 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
36859 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
36862 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
36864 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
36865 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
36866 /* The meter algorithm type. */
36867 uint8_t meter_type;
36868 /* RFC 2697 (srTCM) */
36869 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
36871 /* RFC 2698 (trTCM) */
36872 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
36874 /* RFC 4115 (trTCM) */
36875 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
36877 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
36878 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
36880 * This field is reserved for the future use.
36881 * It shall be set to 0.
36883 uint16_t reserved1;
36885 * This field is reserved for the future use.
36886 * It shall be set to 0.
36888 uint32_t reserved2;
36889 /* A meter rate specified in bytes-per-second. */
36890 uint32_t commit_rate;
36891 /* The bandwidth value. */
36892 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
36893 UINT32_C(0xfffffff)
36894 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
36896 /* The granularity of the value (bits or bytes). */
36897 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
36898 UINT32_C(0x10000000)
36899 /* Value is in bits. */
36900 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
36901 (UINT32_C(0x0) << 28)
36902 /* Value is in bytes. */
36903 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
36904 (UINT32_C(0x1) << 28)
36905 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
36906 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
36907 /* bw_value_unit is 3 b */
36908 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
36909 UINT32_C(0xe0000000)
36910 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
36912 /* Value is in Mb or MB (base 10). */
36913 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
36914 (UINT32_C(0x0) << 29)
36915 /* Value is in Kb or KB (base 10). */
36916 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
36917 (UINT32_C(0x2) << 29)
36918 /* Value is in bits or bytes. */
36919 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
36920 (UINT32_C(0x4) << 29)
36921 /* Value is in Gb or GB (base 10). */
36922 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
36923 (UINT32_C(0x6) << 29)
36924 /* Value is in 1/100th of a percentage of total bandwidth. */
36925 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
36926 (UINT32_C(0x1) << 29)
36928 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
36929 (UINT32_C(0x7) << 29)
36930 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
36931 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
36932 /* A meter burst size specified in bytes. */
36933 uint32_t commit_burst;
36934 /* The bandwidth value. */
36935 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
36936 UINT32_C(0xfffffff)
36937 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
36939 /* The granularity of the value (bits or bytes). */
36940 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
36941 UINT32_C(0x10000000)
36942 /* Value is in bits. */
36943 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
36944 (UINT32_C(0x0) << 28)
36945 /* Value is in bytes. */
36946 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
36947 (UINT32_C(0x1) << 28)
36948 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
36949 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
36950 /* bw_value_unit is 3 b */
36951 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
36952 UINT32_C(0xe0000000)
36953 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
36955 /* Value is in Mb or MB (base 10). */
36956 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
36957 (UINT32_C(0x0) << 29)
36958 /* Value is in Kb or KB (base 10). */
36959 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
36960 (UINT32_C(0x2) << 29)
36961 /* Value is in bits or bytes. */
36962 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
36963 (UINT32_C(0x4) << 29)
36964 /* Value is in Gb or GB (base 10). */
36965 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
36966 (UINT32_C(0x6) << 29)
36967 /* Value is in 1/100th of a percentage of total bandwidth. */
36968 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
36969 (UINT32_C(0x1) << 29)
36970 /* Invalid value */
36971 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
36972 (UINT32_C(0x7) << 29)
36973 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
36974 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
36975 /* A meter rate specified in bytes-per-second. */
36976 uint32_t excess_peak_rate;
36977 /* The bandwidth value. */
36978 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
36979 UINT32_C(0xfffffff)
36980 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
36982 /* The granularity of the value (bits or bytes). */
36983 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
36984 UINT32_C(0x10000000)
36985 /* Value is in bits. */
36986 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
36987 (UINT32_C(0x0) << 28)
36988 /* Value is in bytes. */
36989 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
36990 (UINT32_C(0x1) << 28)
36991 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
36992 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
36993 /* bw_value_unit is 3 b */
36994 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
36995 UINT32_C(0xe0000000)
36996 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
36998 /* Value is in Mb or MB (base 10). */
36999 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
37000 (UINT32_C(0x0) << 29)
37001 /* Value is in Kb or KB (base 10). */
37002 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
37003 (UINT32_C(0x2) << 29)
37004 /* Value is in bits or bytes. */
37005 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
37006 (UINT32_C(0x4) << 29)
37007 /* Value is in Gb or GB (base 10). */
37008 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
37009 (UINT32_C(0x6) << 29)
37010 /* Value is in 1/100th of a percentage of total bandwidth. */
37011 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37012 (UINT32_C(0x1) << 29)
37014 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
37015 (UINT32_C(0x7) << 29)
37016 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
37017 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
37018 /* A meter burst size specified in bytes. */
37019 uint32_t excess_peak_burst;
37020 /* The bandwidth value. */
37021 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
37022 UINT32_C(0xfffffff)
37023 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
37025 /* The granularity of the value (bits or bytes). */
37026 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
37027 UINT32_C(0x10000000)
37028 /* Value is in bits. */
37029 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
37030 (UINT32_C(0x0) << 28)
37031 /* Value is in bytes. */
37032 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
37033 (UINT32_C(0x1) << 28)
37034 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
37035 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
37036 /* bw_value_unit is 3 b */
37037 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
37038 UINT32_C(0xe0000000)
37039 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
37041 /* Value is in Mb or MB (base 10). */
37042 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
37043 (UINT32_C(0x0) << 29)
37044 /* Value is in Kb or KB (base 10). */
37045 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
37046 (UINT32_C(0x2) << 29)
37047 /* Value is in bits or bytes. */
37048 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
37049 (UINT32_C(0x4) << 29)
37050 /* Value is in Gb or GB (base 10). */
37051 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
37052 (UINT32_C(0x6) << 29)
37053 /* Value is in 1/100th of a percentage of total bandwidth. */
37054 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37055 (UINT32_C(0x1) << 29)
37057 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
37058 (UINT32_C(0x7) << 29)
37059 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
37060 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
37063 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
37064 struct hwrm_cfa_meter_profile_alloc_output {
37065 /* The specific error status for the command. */
37066 uint16_t error_code;
37067 /* The HWRM command request type. */
37069 /* The sequence ID from the original command. */
37071 /* The length of the response data in number of bytes. */
37073 /* This value identifies a meter profile in CFA. */
37074 uint16_t meter_profile_id;
37076 * A value of 0xfff is considered invalid and implies the
37077 * profile is not configured.
37079 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
37081 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
37082 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
37083 uint8_t unused_0[5];
37085 * This field is used in Output records to indicate that the output
37086 * is completely written to RAM. This field should be read as '1'
37087 * to indicate that the output has been completely written.
37088 * When writing a command completion or response to an internal
37089 * processor, the order of writes has to be such that this field is
37095 /*******************************
37096 * hwrm_cfa_meter_profile_free *
37097 *******************************/
37100 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
37101 struct hwrm_cfa_meter_profile_free_input {
37102 /* The HWRM command request type. */
37105 * The completion ring to send the completion event on. This should
37106 * be the NQ ID returned from the `nq_alloc` HWRM command.
37108 uint16_t cmpl_ring;
37110 * The sequence ID is used by the driver for tracking multiple
37111 * commands. This ID is treated as opaque data by the firmware and
37112 * the value is returned in the `hwrm_resp_hdr` upon completion.
37116 * The target ID of the command:
37117 * * 0x0-0xFFF8 - The function ID
37118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37119 * * 0xFFFD - Reserved for user-space HWRM interface
37122 uint16_t target_id;
37124 * A physical address pointer pointing to a host buffer that the
37125 * command's response data will be written. This can be either a host
37126 * physical address (HPA) or a guest physical address (GPA) and must
37127 * point to a physically contiguous block of memory.
37129 uint64_t resp_addr;
37132 * Enumeration denoting the RX, TX type of the resource.
37133 * This enumeration is used for resources that are similar for both
37134 * TX and RX paths of the chip.
37136 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
37138 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
37141 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
37143 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
37144 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
37146 /* This value identifies a meter profile in CFA. */
37147 uint16_t meter_profile_id;
37149 * A value of 0xfff is considered invalid and implies the
37150 * profile is not configured.
37152 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
37154 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
37155 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
37156 uint8_t unused_1[4];
37159 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
37160 struct hwrm_cfa_meter_profile_free_output {
37161 /* The specific error status for the command. */
37162 uint16_t error_code;
37163 /* The HWRM command request type. */
37165 /* The sequence ID from the original command. */
37167 /* The length of the response data in number of bytes. */
37169 uint8_t unused_0[7];
37171 * This field is used in Output records to indicate that the output
37172 * is completely written to RAM. This field should be read as '1'
37173 * to indicate that the output has been completely written.
37174 * When writing a command completion or response to an internal
37175 * processor, the order of writes has to be such that this field is
37181 /******************************
37182 * hwrm_cfa_meter_profile_cfg *
37183 ******************************/
37186 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
37187 struct hwrm_cfa_meter_profile_cfg_input {
37188 /* The HWRM command request type. */
37191 * The completion ring to send the completion event on. This should
37192 * be the NQ ID returned from the `nq_alloc` HWRM command.
37194 uint16_t cmpl_ring;
37196 * The sequence ID is used by the driver for tracking multiple
37197 * commands. This ID is treated as opaque data by the firmware and
37198 * the value is returned in the `hwrm_resp_hdr` upon completion.
37202 * The target ID of the command:
37203 * * 0x0-0xFFF8 - The function ID
37204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37205 * * 0xFFFD - Reserved for user-space HWRM interface
37208 uint16_t target_id;
37210 * A physical address pointer pointing to a host buffer that the
37211 * command's response data will be written. This can be either a host
37212 * physical address (HPA) or a guest physical address (GPA) and must
37213 * point to a physically contiguous block of memory.
37215 uint64_t resp_addr;
37218 * Enumeration denoting the RX, TX type of the resource.
37219 * This enumeration is used for resources that are similar for both
37220 * TX and RX paths of the chip.
37222 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37224 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
37226 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
37227 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
37228 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
37229 /* The meter algorithm type. */
37230 uint8_t meter_type;
37231 /* RFC 2697 (srTCM) */
37232 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
37234 /* RFC 2698 (trTCM) */
37235 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
37237 /* RFC 4115 (trTCM) */
37238 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
37240 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
37241 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
37242 /* This value identifies a meter profile in CFA. */
37243 uint16_t meter_profile_id;
37245 * A value of 0xfff is considered invalid and implies the
37246 * profile is not configured.
37248 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
37250 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
37251 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
37253 * This field is reserved for the future use.
37254 * It shall be set to 0.
37257 /* A meter rate specified in bytes-per-second. */
37258 uint32_t commit_rate;
37259 /* The bandwidth value. */
37260 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
37261 UINT32_C(0xfffffff)
37262 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
37264 /* The granularity of the value (bits or bytes). */
37265 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
37266 UINT32_C(0x10000000)
37267 /* Value is in bits. */
37268 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
37269 (UINT32_C(0x0) << 28)
37270 /* Value is in bytes. */
37271 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
37272 (UINT32_C(0x1) << 28)
37273 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
37274 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
37275 /* bw_value_unit is 3 b */
37276 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
37277 UINT32_C(0xe0000000)
37278 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
37280 /* Value is in Mb or MB (base 10). */
37281 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
37282 (UINT32_C(0x0) << 29)
37283 /* Value is in Kb or KB (base 10). */
37284 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
37285 (UINT32_C(0x2) << 29)
37286 /* Value is in bits or bytes. */
37287 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
37288 (UINT32_C(0x4) << 29)
37289 /* Value is in Gb or GB (base 10). */
37290 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
37291 (UINT32_C(0x6) << 29)
37292 /* Value is in 1/100th of a percentage of total bandwidth. */
37293 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37294 (UINT32_C(0x1) << 29)
37296 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
37297 (UINT32_C(0x7) << 29)
37298 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
37299 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
37300 /* A meter burst size specified in bytes. */
37301 uint32_t commit_burst;
37302 /* The bandwidth value. */
37303 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
37304 UINT32_C(0xfffffff)
37305 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
37307 /* The granularity of the value (bits or bytes). */
37308 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
37309 UINT32_C(0x10000000)
37310 /* Value is in bits. */
37311 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
37312 (UINT32_C(0x0) << 28)
37313 /* Value is in bytes. */
37314 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
37315 (UINT32_C(0x1) << 28)
37316 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
37317 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
37318 /* bw_value_unit is 3 b */
37319 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
37320 UINT32_C(0xe0000000)
37321 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
37323 /* Value is in Mb or MB (base 10). */
37324 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
37325 (UINT32_C(0x0) << 29)
37326 /* Value is in Kb or KB (base 10). */
37327 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
37328 (UINT32_C(0x2) << 29)
37329 /* Value is in bits or bytes. */
37330 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
37331 (UINT32_C(0x4) << 29)
37332 /* Value is in Gb or GB (base 10). */
37333 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
37334 (UINT32_C(0x6) << 29)
37335 /* Value is in 1/100th of a percentage of total bandwidth. */
37336 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37337 (UINT32_C(0x1) << 29)
37338 /* Invalid value */
37339 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
37340 (UINT32_C(0x7) << 29)
37341 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
37342 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
37343 /* A meter rate specified in bytes-per-second. */
37344 uint32_t excess_peak_rate;
37345 /* The bandwidth value. */
37346 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
37347 UINT32_C(0xfffffff)
37348 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
37350 /* The granularity of the value (bits or bytes). */
37351 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
37352 UINT32_C(0x10000000)
37353 /* Value is in bits. */
37354 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
37355 (UINT32_C(0x0) << 28)
37356 /* Value is in bytes. */
37357 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
37358 (UINT32_C(0x1) << 28)
37359 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
37360 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
37361 /* bw_value_unit is 3 b */
37362 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
37363 UINT32_C(0xe0000000)
37364 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
37366 /* Value is in Mb or MB (base 10). */
37367 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
37368 (UINT32_C(0x0) << 29)
37369 /* Value is in Kb or KB (base 10). */
37370 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
37371 (UINT32_C(0x2) << 29)
37372 /* Value is in bits or bytes. */
37373 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
37374 (UINT32_C(0x4) << 29)
37375 /* Value is in Gb or GB (base 10). */
37376 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
37377 (UINT32_C(0x6) << 29)
37378 /* Value is in 1/100th of a percentage of total bandwidth. */
37379 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
37380 (UINT32_C(0x1) << 29)
37382 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
37383 (UINT32_C(0x7) << 29)
37384 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
37385 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
37386 /* A meter burst size specified in bytes. */
37387 uint32_t excess_peak_burst;
37388 /* The bandwidth value. */
37389 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
37390 UINT32_C(0xfffffff)
37391 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
37393 /* The granularity of the value (bits or bytes). */
37394 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
37395 UINT32_C(0x10000000)
37396 /* Value is in bits. */
37397 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
37398 (UINT32_C(0x0) << 28)
37399 /* Value is in bytes. */
37400 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
37401 (UINT32_C(0x1) << 28)
37402 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
37403 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
37404 /* bw_value_unit is 3 b */
37405 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
37406 UINT32_C(0xe0000000)
37407 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
37409 /* Value is in Mb or MB (base 10). */
37410 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
37411 (UINT32_C(0x0) << 29)
37412 /* Value is in Kb or KB (base 10). */
37413 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
37414 (UINT32_C(0x2) << 29)
37415 /* Value is in bits or bytes. */
37416 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
37417 (UINT32_C(0x4) << 29)
37418 /* Value is in Gb or GB (base 10). */
37419 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
37420 (UINT32_C(0x6) << 29)
37421 /* Value is in 1/100th of a percentage of total bandwidth. */
37422 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
37423 (UINT32_C(0x1) << 29)
37425 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
37426 (UINT32_C(0x7) << 29)
37427 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
37428 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
37431 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
37432 struct hwrm_cfa_meter_profile_cfg_output {
37433 /* The specific error status for the command. */
37434 uint16_t error_code;
37435 /* The HWRM command request type. */
37437 /* The sequence ID from the original command. */
37439 /* The length of the response data in number of bytes. */
37441 uint8_t unused_0[7];
37443 * This field is used in Output records to indicate that the output
37444 * is completely written to RAM. This field should be read as '1'
37445 * to indicate that the output has been completely written.
37446 * When writing a command completion or response to an internal
37447 * processor, the order of writes has to be such that this field is
37453 /*********************************
37454 * hwrm_cfa_meter_instance_alloc *
37455 *********************************/
37458 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
37459 struct hwrm_cfa_meter_instance_alloc_input {
37460 /* The HWRM command request type. */
37463 * The completion ring to send the completion event on. This should
37464 * be the NQ ID returned from the `nq_alloc` HWRM command.
37466 uint16_t cmpl_ring;
37468 * The sequence ID is used by the driver for tracking multiple
37469 * commands. This ID is treated as opaque data by the firmware and
37470 * the value is returned in the `hwrm_resp_hdr` upon completion.
37474 * The target ID of the command:
37475 * * 0x0-0xFFF8 - The function ID
37476 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37477 * * 0xFFFD - Reserved for user-space HWRM interface
37480 uint16_t target_id;
37482 * A physical address pointer pointing to a host buffer that the
37483 * command's response data will be written. This can be either a host
37484 * physical address (HPA) or a guest physical address (GPA) and must
37485 * point to a physically contiguous block of memory.
37487 uint64_t resp_addr;
37490 * Enumeration denoting the RX, TX type of the resource.
37491 * This enumeration is used for resources that are similar for both
37492 * TX and RX paths of the chip.
37494 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
37497 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
37500 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
37502 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
37503 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
37505 /* This value identifies a meter profile in CFA. */
37506 uint16_t meter_profile_id;
37508 * A value of 0xffff is considered invalid and implies the
37509 * profile is not configured.
37511 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
37513 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
37514 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
37515 uint8_t unused_1[4];
37518 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
37519 struct hwrm_cfa_meter_instance_alloc_output {
37520 /* The specific error status for the command. */
37521 uint16_t error_code;
37522 /* The HWRM command request type. */
37524 /* The sequence ID from the original command. */
37526 /* The length of the response data in number of bytes. */
37528 /* This value identifies a meter instance in CFA. */
37529 uint16_t meter_instance_id;
37531 * A value of 0xffff is considered invalid and implies the
37532 * instance is not configured.
37534 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
37536 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
37537 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
37538 uint8_t unused_0[5];
37540 * This field is used in Output records to indicate that the output
37541 * is completely written to RAM. This field should be read as '1'
37542 * to indicate that the output has been completely written.
37543 * When writing a command completion or response to an internal
37544 * processor, the order of writes has to be such that this field is
37550 /*******************************
37551 * hwrm_cfa_meter_instance_cfg *
37552 *******************************/
37555 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
37556 struct hwrm_cfa_meter_instance_cfg_input {
37557 /* The HWRM command request type. */
37560 * The completion ring to send the completion event on. This should
37561 * be the NQ ID returned from the `nq_alloc` HWRM command.
37563 uint16_t cmpl_ring;
37565 * The sequence ID is used by the driver for tracking multiple
37566 * commands. This ID is treated as opaque data by the firmware and
37567 * the value is returned in the `hwrm_resp_hdr` upon completion.
37571 * The target ID of the command:
37572 * * 0x0-0xFFF8 - The function ID
37573 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37574 * * 0xFFFD - Reserved for user-space HWRM interface
37577 uint16_t target_id;
37579 * A physical address pointer pointing to a host buffer that the
37580 * command's response data will be written. This can be either a host
37581 * physical address (HPA) or a guest physical address (GPA) and must
37582 * point to a physically contiguous block of memory.
37584 uint64_t resp_addr;
37587 * Enumeration denoting the RX, TX type of the resource.
37588 * This enumeration is used for resources that are similar for both
37589 * TX and RX paths of the chip.
37591 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
37593 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
37596 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
37598 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
37599 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
37602 * This value identifies a new meter profile to be associated with
37603 * the meter instance specified in this command.
37605 uint16_t meter_profile_id;
37607 * A value of 0xffff is considered invalid and implies the
37608 * profile is not configured.
37610 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
37612 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
37613 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
37615 * This value identifies the ID of a meter instance that needs to be
37616 * updated with a new meter profile specified in this command.
37618 uint16_t meter_instance_id;
37619 uint8_t unused_1[2];
37622 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
37623 struct hwrm_cfa_meter_instance_cfg_output {
37624 /* The specific error status for the command. */
37625 uint16_t error_code;
37626 /* The HWRM command request type. */
37628 /* The sequence ID from the original command. */
37630 /* The length of the response data in number of bytes. */
37632 uint8_t unused_0[7];
37634 * This field is used in Output records to indicate that the output
37635 * is completely written to RAM. This field should be read as '1'
37636 * to indicate that the output has been completely written.
37637 * When writing a command completion or response to an internal
37638 * processor, the order of writes has to be such that this field is
37644 /********************************
37645 * hwrm_cfa_meter_instance_free *
37646 ********************************/
37649 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
37650 struct hwrm_cfa_meter_instance_free_input {
37651 /* The HWRM command request type. */
37654 * The completion ring to send the completion event on. This should
37655 * be the NQ ID returned from the `nq_alloc` HWRM command.
37657 uint16_t cmpl_ring;
37659 * The sequence ID is used by the driver for tracking multiple
37660 * commands. This ID is treated as opaque data by the firmware and
37661 * the value is returned in the `hwrm_resp_hdr` upon completion.
37665 * The target ID of the command:
37666 * * 0x0-0xFFF8 - The function ID
37667 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37668 * * 0xFFFD - Reserved for user-space HWRM interface
37671 uint16_t target_id;
37673 * A physical address pointer pointing to a host buffer that the
37674 * command's response data will be written. This can be either a host
37675 * physical address (HPA) or a guest physical address (GPA) and must
37676 * point to a physically contiguous block of memory.
37678 uint64_t resp_addr;
37681 * Enumeration denoting the RX, TX type of the resource.
37682 * This enumeration is used for resources that are similar for both
37683 * TX and RX paths of the chip.
37685 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
37687 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
37690 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
37692 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
37693 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
37695 /* This value identifies a meter instance in CFA. */
37696 uint16_t meter_instance_id;
37698 * A value of 0xfff is considered invalid and implies the
37699 * instance is not configured.
37701 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
37703 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
37704 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
37705 uint8_t unused_1[4];
37708 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
37709 struct hwrm_cfa_meter_instance_free_output {
37710 /* The specific error status for the command. */
37711 uint16_t error_code;
37712 /* The HWRM command request type. */
37714 /* The sequence ID from the original command. */
37716 /* The length of the response data in number of bytes. */
37718 uint8_t unused_0[7];
37720 * This field is used in Output records to indicate that the output
37721 * is completely written to RAM. This field should be read as '1'
37722 * to indicate that the output has been completely written.
37723 * When writing a command completion or response to an internal
37724 * processor, the order of writes has to be such that this field is
37730 /*******************************
37731 * hwrm_cfa_decap_filter_alloc *
37732 *******************************/
37735 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
37736 struct hwrm_cfa_decap_filter_alloc_input {
37737 /* The HWRM command request type. */
37740 * The completion ring to send the completion event on. This should
37741 * be the NQ ID returned from the `nq_alloc` HWRM command.
37743 uint16_t cmpl_ring;
37745 * The sequence ID is used by the driver for tracking multiple
37746 * commands. This ID is treated as opaque data by the firmware and
37747 * the value is returned in the `hwrm_resp_hdr` upon completion.
37751 * The target ID of the command:
37752 * * 0x0-0xFFF8 - The function ID
37753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37754 * * 0xFFFD - Reserved for user-space HWRM interface
37757 uint16_t target_id;
37759 * A physical address pointer pointing to a host buffer that the
37760 * command's response data will be written. This can be either a host
37761 * physical address (HPA) or a guest physical address (GPA) and must
37762 * point to a physically contiguous block of memory.
37764 uint64_t resp_addr;
37766 /* ovs_tunnel is 1 b */
37767 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
37771 * This bit must be '1' for the tunnel_type field to be
37774 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
37777 * This bit must be '1' for the tunnel_id field to be
37780 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
37783 * This bit must be '1' for the src_macaddr field to be
37786 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
37789 * This bit must be '1' for the dst_macaddr field to be
37792 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
37795 * This bit must be '1' for the ovlan_vid field to be
37798 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
37801 * This bit must be '1' for the ivlan_vid field to be
37804 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
37807 * This bit must be '1' for the t_ovlan_vid field to be
37810 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
37813 * This bit must be '1' for the t_ivlan_vid field to be
37816 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
37819 * This bit must be '1' for the ethertype field to be
37822 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
37825 * This bit must be '1' for the src_ipaddr field to be
37828 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
37831 * This bit must be '1' for the dst_ipaddr field to be
37834 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
37837 * This bit must be '1' for the ipaddr_type field to be
37840 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
37843 * This bit must be '1' for the ip_protocol field to be
37846 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
37849 * This bit must be '1' for the src_port field to be
37852 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
37855 * This bit must be '1' for the dst_port field to be
37858 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
37861 * This bit must be '1' for the dst_id field to be
37864 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
37867 * This bit must be '1' for the mirror_vnic_id field to be
37870 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
37873 * Tunnel identifier.
37874 * Virtual Network Identifier (VNI). Only valid with
37875 * tunnel_types VXLAN, NVGRE, and Geneve.
37876 * Only lower 24-bits of VNI field are used
37877 * in setting up the filter.
37879 uint32_t tunnel_id;
37881 uint8_t tunnel_type;
37883 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
37885 /* Virtual eXtensible Local Area Network (VXLAN) */
37886 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
37888 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
37889 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
37891 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
37892 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
37895 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
37897 /* Generic Network Virtualization Encapsulation (Geneve) */
37898 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
37900 /* Multi-Protocol Label Switching (MPLS) */
37901 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
37903 /* Stateless Transport Tunnel (STT) */
37904 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
37906 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
37907 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
37909 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
37910 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
37913 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
37916 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
37918 /* Use fixed layer 2 ether type of 0xFFFF */
37919 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
37922 * IPV6 over virtual eXtensible Local Area Network with GPE header
37925 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
37927 /* Any tunneled traffic */
37928 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
37930 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
37931 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
37935 * This value indicates the source MAC address in
37936 * the Ethernet header.
37938 uint8_t src_macaddr[6];
37939 uint8_t unused_2[2];
37941 * This value indicates the destination MAC address in
37942 * the Ethernet header.
37944 uint8_t dst_macaddr[6];
37946 * This value indicates the VLAN ID of the outer VLAN tag
37947 * in the Ethernet header.
37949 uint16_t ovlan_vid;
37951 * This value indicates the VLAN ID of the inner VLAN tag
37952 * in the Ethernet header.
37954 uint16_t ivlan_vid;
37956 * This value indicates the VLAN ID of the outer VLAN tag
37957 * in the tunnel Ethernet header.
37959 uint16_t t_ovlan_vid;
37961 * This value indicates the VLAN ID of the inner VLAN tag
37962 * in the tunnel Ethernet header.
37964 uint16_t t_ivlan_vid;
37965 /* This value indicates the ethertype in the Ethernet header. */
37966 uint16_t ethertype;
37968 * This value indicates the type of IP address.
37971 * All others are invalid.
37973 uint8_t ip_addr_type;
37975 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
37978 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
37981 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
37983 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
37984 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
37986 * The value of protocol filed in IP header.
37987 * Applies to UDP and TCP traffic.
37991 uint8_t ip_protocol;
37993 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
37996 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
37999 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
38001 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
38002 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
38006 * The value of source IP address to be used in filtering.
38007 * For IPv4, first four bytes represent the IP address.
38009 uint32_t src_ipaddr[4];
38011 * The value of destination IP address to be used in filtering.
38012 * For IPv4, first four bytes represent the IP address.
38014 uint32_t dst_ipaddr[4];
38016 * The value of source port to be used in filtering.
38017 * Applies to UDP and TCP traffic.
38021 * The value of destination port to be used in filtering.
38022 * Applies to UDP and TCP traffic.
38026 * If set, this value shall represent the
38027 * Logical VNIC ID of the destination VNIC for the RX
38032 * If set, this value shall represent the L2 context that matches the
38033 * L2 information of the decap filter.
38035 uint16_t l2_ctxt_ref_id;
38038 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
38039 struct hwrm_cfa_decap_filter_alloc_output {
38040 /* The specific error status for the command. */
38041 uint16_t error_code;
38042 /* The HWRM command request type. */
38044 /* The sequence ID from the original command. */
38046 /* The length of the response data in number of bytes. */
38048 /* This value is an opaque id into CFA data structures. */
38049 uint32_t decap_filter_id;
38050 uint8_t unused_0[3];
38052 * This field is used in Output records to indicate that the output
38053 * is completely written to RAM. This field should be read as '1'
38054 * to indicate that the output has been completely written.
38055 * When writing a command completion or response to an internal
38056 * processor, the order of writes has to be such that this field is
38062 /******************************
38063 * hwrm_cfa_decap_filter_free *
38064 ******************************/
38067 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
38068 struct hwrm_cfa_decap_filter_free_input {
38069 /* The HWRM command request type. */
38072 * The completion ring to send the completion event on. This should
38073 * be the NQ ID returned from the `nq_alloc` HWRM command.
38075 uint16_t cmpl_ring;
38077 * The sequence ID is used by the driver for tracking multiple
38078 * commands. This ID is treated as opaque data by the firmware and
38079 * the value is returned in the `hwrm_resp_hdr` upon completion.
38083 * The target ID of the command:
38084 * * 0x0-0xFFF8 - The function ID
38085 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38086 * * 0xFFFD - Reserved for user-space HWRM interface
38089 uint16_t target_id;
38091 * A physical address pointer pointing to a host buffer that the
38092 * command's response data will be written. This can be either a host
38093 * physical address (HPA) or a guest physical address (GPA) and must
38094 * point to a physically contiguous block of memory.
38096 uint64_t resp_addr;
38097 /* This value is an opaque id into CFA data structures. */
38098 uint32_t decap_filter_id;
38099 uint8_t unused_0[4];
38102 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
38103 struct hwrm_cfa_decap_filter_free_output {
38104 /* The specific error status for the command. */
38105 uint16_t error_code;
38106 /* The HWRM command request type. */
38108 /* The sequence ID from the original command. */
38110 /* The length of the response data in number of bytes. */
38112 uint8_t unused_0[7];
38114 * This field is used in Output records to indicate that the output
38115 * is completely written to RAM. This field should be read as '1'
38116 * to indicate that the output has been completely written.
38117 * When writing a command completion or response to an internal
38118 * processor, the order of writes has to be such that this field is
38124 /***********************
38125 * hwrm_cfa_flow_alloc *
38126 ***********************/
38129 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
38130 struct hwrm_cfa_flow_alloc_input {
38131 /* The HWRM command request type. */
38134 * The completion ring to send the completion event on. This should
38135 * be the NQ ID returned from the `nq_alloc` HWRM command.
38137 uint16_t cmpl_ring;
38139 * The sequence ID is used by the driver for tracking multiple
38140 * commands. This ID is treated as opaque data by the firmware and
38141 * the value is returned in the `hwrm_resp_hdr` upon completion.
38145 * The target ID of the command:
38146 * * 0x0-0xFFF8 - The function ID
38147 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38148 * * 0xFFFD - Reserved for user-space HWRM interface
38151 uint16_t target_id;
38153 * A physical address pointer pointing to a host buffer that the
38154 * command's response data will be written. This can be either a host
38155 * physical address (HPA) or a guest physical address (GPA) and must
38156 * point to a physically contiguous block of memory.
38158 uint64_t resp_addr;
38160 /* tunnel is 1 b */
38161 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
38163 /* num_vlan is 2 b */
38164 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
38166 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
38168 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
38169 (UINT32_C(0x0) << 1)
38171 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
38172 (UINT32_C(0x1) << 1)
38174 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
38175 (UINT32_C(0x2) << 1)
38176 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
38177 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
38178 /* Enumeration denoting the Flow Type. */
38179 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
38181 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
38183 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
38184 (UINT32_C(0x0) << 3)
38186 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
38187 (UINT32_C(0x1) << 3)
38189 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
38190 (UINT32_C(0x2) << 3)
38191 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
38192 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
38194 * when set to 1, indicates TX flow offload for function specified
38195 * in src_fid and the dst_fid should be set to invalid value. To
38196 * indicate a VM to VM flow, both of the path_tx and path_rx flags
38197 * need to be set. For virtio vSwitch offload case, the src_fid and
38198 * dst_fid is set to the same fid value. For the SRIOV vSwitch
38199 * offload case, the src_fid and dst_fid must be set to the same VF
38200 * FID belong to the children VFs of the same PF to indicate VM to
38203 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
38206 * when set to 1, indicates RX flow offload for function specified
38207 * in dst_fid and the src_fid should be set to invalid value.
38209 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
38212 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan
38213 * header is required and the VXLAN VNI value is stored in the first
38214 * 24 bits of the dmac field. This flag is only valid when the flow
38217 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
38220 * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci
38223 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
38230 /* Tunnel handle valid when tunnel flag is set. */
38231 uint32_t tunnel_handle;
38232 uint16_t action_flags;
38234 * Setting of this flag indicates drop action. If this flag is not
38235 * set, then it should be considered accept action.
38237 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
38239 /* recycle is 1 b */
38240 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
38243 * Setting of this flag indicates drop action. If this flag is not
38244 * set, then it should be considered accept action.
38246 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
38249 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
38251 /* tunnel is 1 b */
38252 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
38254 /* nat_src is 1 b */
38255 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
38257 /* nat_dest is 1 b */
38258 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
38260 /* nat_ipv4_address is 1 b */
38261 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
38263 /* l2_header_rewrite is 1 b */
38264 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
38266 /* ttl_decrement is 1 b */
38267 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
38270 * If set to 1 and flow direction is TX, it indicates decap of L2
38271 * header and encap of tunnel header. If set to 1 and flow direction
38272 * is RX, it indicates decap of tunnel header and encap L2 header.
38273 * The type of tunnel is specified in the tunnel_type field.
38275 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
38277 /* If set to 1, flow aging is enabled for this flow. */
38278 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
38281 * If set to 1 an attempt will be made to try to offload this flow
38282 * to the most optimal flow table resource. If set to 0, the flow
38283 * will be placed to the default flow table resource.
38285 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
38288 * If set to 1 there will be no attempt to allocate an on-chip try
38289 * to offload this flow. If set to 0, which will keep compatibility
38290 * with the older drivers, will cause the FW to attempt to allocate
38291 * an on-chip flow counter for the newly created flow. This will
38292 * keep the existing behavior with EM flows which always had an
38293 * associated flow counter.
38295 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
38298 * Tx Flow: pf or vf fid.
38302 /* VLAN tpid, valid when push_vlan flag is set. */
38303 uint16_t l2_rewrite_vlan_tpid;
38304 /* VLAN tci, valid when push_vlan flag is set. */
38305 uint16_t l2_rewrite_vlan_tci;
38306 /* Meter id, valid when meter flag is set. */
38307 uint16_t act_meter_id;
38308 /* Flow with the same l2 context tcam key. */
38309 uint16_t ref_flow_handle;
38310 /* This value sets the match value for the ethertype. */
38311 uint16_t ethertype;
38312 /* valid when num tags is 1 or 2. */
38313 uint16_t outer_vlan_tci;
38314 /* This value sets the match value for the Destination MAC address. */
38316 /* valid when num tags is 2. */
38317 uint16_t inner_vlan_tci;
38318 /* This value sets the match value for the Source MAC address. */
38320 /* The bit length of destination IP address mask. */
38321 uint8_t ip_dst_mask_len;
38322 /* The bit length of source IP address mask. */
38323 uint8_t ip_src_mask_len;
38324 /* The value of destination IPv4/IPv6 address. */
38325 uint32_t ip_dst[4];
38326 /* The source IPv4/IPv6 address. */
38327 uint32_t ip_src[4];
38329 * The value of source port.
38330 * Applies to UDP and TCP traffic.
38332 uint16_t l4_src_port;
38334 * The value of source port mask.
38335 * Applies to UDP and TCP traffic.
38337 uint16_t l4_src_port_mask;
38339 * The value of destination port.
38340 * Applies to UDP and TCP traffic.
38342 uint16_t l4_dst_port;
38344 * The value of destination port mask.
38345 * Applies to UDP and TCP traffic.
38347 uint16_t l4_dst_port_mask;
38349 * NAT IPv4/6 address based on address type flag.
38350 * 0 values are ignored.
38352 uint32_t nat_ip_address[4];
38353 /* L2 header re-write Destination MAC address. */
38354 uint16_t l2_rewrite_dmac[3];
38356 * The NAT source/destination port based on direction flag.
38357 * Applies to UDP and TCP traffic.
38358 * 0 values are ignored.
38361 /* L2 header re-write Source MAC address. */
38362 uint16_t l2_rewrite_smac[3];
38363 /* The value of ip protocol. */
38366 uint8_t tunnel_type;
38368 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
38370 /* Virtual eXtensible Local Area Network (VXLAN) */
38371 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
38373 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38374 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
38376 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38377 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
38380 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
38382 /* Generic Network Virtualization Encapsulation (Geneve) */
38383 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
38385 /* Multi-Protocol Label Switching (MPLS) */
38386 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
38388 /* Stateless Transport Tunnel (STT) */
38389 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
38391 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38392 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
38394 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38395 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38398 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38401 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38403 /* Use fixed layer 2 ether type of 0xFFFF */
38404 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
38407 * IPV6 over virtual eXtensible Local Area Network with GPE header
38410 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38412 /* Any tunneled traffic */
38413 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
38415 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
38416 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
38419 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
38420 struct hwrm_cfa_flow_alloc_output {
38421 /* The specific error status for the command. */
38422 uint16_t error_code;
38423 /* The HWRM command request type. */
38425 /* The sequence ID from the original command. */
38427 /* The length of the response data in number of bytes. */
38429 /* Flow record index. */
38430 uint16_t flow_handle;
38431 uint8_t unused_0[2];
38433 * The flow id value in bit 0-29 is the actual ID of the flow
38434 * associated with this filter and it shall be used to match
38435 * and associate the flow identifier returned in completion
38436 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
38437 * shall indicate no valid flow id.
38440 /* Indicate the flow id value. */
38441 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
38442 UINT32_C(0x3fffffff)
38443 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
38444 /* Indicate type of the flow. */
38445 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
38446 UINT32_C(0x40000000)
38448 * If this bit set to 0, then it indicates that the flow is
38451 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
38452 (UINT32_C(0x0) << 30)
38454 * If this bit is set to 1, then it indicates that the flow is
38457 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
38458 (UINT32_C(0x1) << 30)
38459 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
38460 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
38461 /* Indicate the flow direction. */
38462 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
38463 UINT32_C(0x80000000)
38464 /* If this bit set to 0, then it indicates rx flow. */
38465 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
38466 (UINT32_C(0x0) << 31)
38467 /* If this bit is set to 1, then it indicates that tx flow. */
38468 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
38469 (UINT32_C(0x1) << 31)
38470 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
38471 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
38472 /* This value identifies a set of CFA data structures used for a flow. */
38473 uint64_t ext_flow_handle;
38474 uint32_t flow_counter_id;
38475 uint8_t unused_1[3];
38477 * This field is used in Output records to indicate that the output
38478 * is completely written to RAM. This field should be read as '1'
38479 * to indicate that the output has been completely written.
38480 * When writing a command completion or response to an internal
38481 * processor, the order of writes has to be such that this field is
38487 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
38488 struct hwrm_cfa_flow_alloc_cmd_err {
38490 * command specific error codes that goes to
38491 * the cmd_err field in Common HWRM Error Response.
38494 /* Unknown error */
38495 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
38496 /* No more L2 Context TCAM */
38497 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
38498 /* No more action records */
38499 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
38500 /* No more flow counters */
38501 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
38502 /* No more wild-card TCAM */
38503 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
38504 /* Hash collsion in exact match tables */
38505 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
38506 /* Key is already installed */
38507 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
38508 /* Flow Context DB is out of resource */
38509 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
38510 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
38511 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
38512 uint8_t unused_0[7];
38515 /**********************
38516 * hwrm_cfa_flow_free *
38517 **********************/
38520 /* hwrm_cfa_flow_free_input (size:256b/32B) */
38521 struct hwrm_cfa_flow_free_input {
38522 /* The HWRM command request type. */
38525 * The completion ring to send the completion event on. This should
38526 * be the NQ ID returned from the `nq_alloc` HWRM command.
38528 uint16_t cmpl_ring;
38530 * The sequence ID is used by the driver for tracking multiple
38531 * commands. This ID is treated as opaque data by the firmware and
38532 * the value is returned in the `hwrm_resp_hdr` upon completion.
38536 * The target ID of the command:
38537 * * 0x0-0xFFF8 - The function ID
38538 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38539 * * 0xFFFD - Reserved for user-space HWRM interface
38542 uint16_t target_id;
38544 * A physical address pointer pointing to a host buffer that the
38545 * command's response data will be written. This can be either a host
38546 * physical address (HPA) or a guest physical address (GPA) and must
38547 * point to a physically contiguous block of memory.
38549 uint64_t resp_addr;
38550 /* Flow record index. */
38551 uint16_t flow_handle;
38553 /* Flow counter id to be freed. */
38554 uint32_t flow_counter_id;
38555 /* This value identifies a set of CFA data structures used for a flow. */
38556 uint64_t ext_flow_handle;
38559 /* hwrm_cfa_flow_free_output (size:256b/32B) */
38560 struct hwrm_cfa_flow_free_output {
38561 /* The specific error status for the command. */
38562 uint16_t error_code;
38563 /* The HWRM command request type. */
38565 /* The sequence ID from the original command. */
38567 /* The length of the response data in number of bytes. */
38569 /* packet is 64 b */
38573 uint8_t unused_0[7];
38575 * This field is used in Output records to indicate that the output
38576 * is completely written to RAM. This field should be read as '1'
38577 * to indicate that the output has been completely written.
38578 * When writing a command completion or response to an internal
38579 * processor, the order of writes has to be such that this field is
38585 /* hwrm_cfa_flow_action_data (size:960b/120B) */
38586 struct hwrm_cfa_flow_action_data {
38587 uint16_t action_flags;
38588 /* Setting of this flag indicates accept action. */
38589 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
38591 /* Setting of this flag indicates recycle action. */
38592 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
38594 /* Setting of this flag indicates drop action. */
38595 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
38597 /* Setting of this flag indicates meter action. */
38598 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
38600 /* Setting of this flag indicates tunnel action. */
38601 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
38604 * If set to 1 and flow direction is TX, it indicates decap of L2
38605 * header and encap of tunnel header. If set to 1 and flow direction
38606 * is RX, it indicates decap of tunnel header and encap L2 header.
38608 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
38610 /* Setting of this flag indicates ttl decrement action. */
38611 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
38613 /* If set to 1, flow aging is enabled for this flow. */
38614 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
38616 /* Setting of this flag indicates encap action. */
38617 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
38619 /* Setting of this flag indicates decap action. */
38620 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
38623 uint16_t act_meter_id;
38626 /* vport number. */
38628 /* The NAT source/destination. */
38630 uint16_t unused_0[3];
38631 /* NAT IPv4/IPv6 address. */
38632 uint32_t nat_ip_address[4];
38633 /* Encapsulation Type. */
38634 uint8_t encap_type;
38635 /* Virtual eXtensible Local Area Network (VXLAN) */
38636 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
38637 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38638 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
38639 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
38640 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
38642 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
38643 /* Generic Network Virtualization Encapsulation (Geneve) */
38644 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
38645 /* Multi-Protocol Label Switching (MPLS) */
38646 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
38648 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
38649 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38650 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
38651 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38652 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
38654 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38657 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
38658 /* Use fixed layer 2 ether type of 0xFFFF */
38659 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
38661 * IPV6 over virtual eXtensible Local Area Network with GPE header
38664 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
38665 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
38666 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
38668 /* This value is encap data for the associated encap type. */
38669 uint32_t encap_data[20];
38672 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
38673 struct hwrm_cfa_flow_tunnel_hdr_data {
38675 uint8_t tunnel_type;
38677 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
38679 /* Virtual eXtensible Local Area Network (VXLAN) */
38680 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
38682 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
38683 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
38685 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
38686 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
38689 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
38691 /* Generic Network Virtualization Encapsulation (Geneve) */
38692 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
38694 /* Multi-Protocol Label Switching (MPLS) */
38695 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
38697 /* Stateless Transport Tunnel (STT) */
38698 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
38700 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
38701 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
38703 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38704 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
38707 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
38710 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
38712 /* Use fixed layer 2 ether type of 0xFFFF */
38713 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
38716 * IPV6 over virtual eXtensible Local Area Network with GPE header
38719 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
38721 /* Any tunneled traffic */
38722 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
38724 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
38725 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
38728 * Tunnel identifier.
38729 * Virtual Network Identifier (VNI).
38731 uint32_t tunnel_id;
38734 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
38735 struct hwrm_cfa_flow_l4_key_data {
38736 /* The value of source port. */
38737 uint16_t l4_src_port;
38738 /* The value of destination port. */
38739 uint16_t l4_dst_port;
38743 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
38744 struct hwrm_cfa_flow_l3_key_data {
38745 /* The value of ip protocol. */
38746 uint8_t ip_protocol;
38747 uint8_t unused_0[7];
38748 /* The value of destination IPv4/IPv6 address. */
38749 uint32_t ip_dst[4];
38750 /* The source IPv4/IPv6 address. */
38751 uint32_t ip_src[4];
38752 /* NAT IPv4/IPv6 address. */
38753 uint32_t nat_ip_address[4];
38754 uint32_t unused[2];
38757 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
38758 struct hwrm_cfa_flow_l2_key_data {
38759 /* Destination MAC address. */
38762 /* Source MAC address. */
38765 /* L2 header re-write Destination MAC address. */
38766 uint16_t l2_rewrite_dmac[3];
38768 /* L2 header re-write Source MAC address. */
38769 uint16_t l2_rewrite_smac[3];
38771 uint16_t ethertype;
38772 /* Number of VLAN tags. */
38773 uint16_t num_vlan_tags;
38775 uint16_t l2_rewrite_vlan_tpid;
38777 uint16_t l2_rewrite_vlan_tci;
38778 uint8_t unused_3[2];
38779 /* Outer VLAN TPID. */
38780 uint16_t ovlan_tpid;
38781 /* Outer VLAN TCI. */
38782 uint16_t ovlan_tci;
38783 /* Inner VLAN TPID. */
38784 uint16_t ivlan_tpid;
38785 /* Inner VLAN TCI. */
38786 uint16_t ivlan_tci;
38790 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
38791 struct hwrm_cfa_flow_key_data {
38792 /* Flow associated tunnel L2 header key info. */
38793 uint32_t t_l2_key_data[14];
38794 /* Flow associated tunnel L2 header mask info. */
38795 uint32_t t_l2_key_mask[14];
38796 /* Flow associated tunnel L3 header key info. */
38797 uint32_t t_l3_key_data[16];
38798 /* Flow associated tunnel L3 header mask info. */
38799 uint32_t t_l3_key_mask[16];
38800 /* Flow associated tunnel L4 header key info. */
38801 uint32_t t_l4_key_data[2];
38802 /* Flow associated tunnel L4 header mask info. */
38803 uint32_t t_l4_key_mask[2];
38804 /* Flow associated tunnel header info. */
38805 uint32_t tunnel_hdr[2];
38806 /* Flow associated L2 header key info. */
38807 uint32_t l2_key_data[14];
38808 /* Flow associated L2 header mask info. */
38809 uint32_t l2_key_mask[14];
38810 /* Flow associated L3 header key info. */
38811 uint32_t l3_key_data[16];
38812 /* Flow associated L3 header mask info. */
38813 uint32_t l3_key_mask[16];
38814 /* Flow associated L4 header key info. */
38815 uint32_t l4_key_data[2];
38816 /* Flow associated L4 header mask info. */
38817 uint32_t l4_key_mask[2];
38820 /**********************
38821 * hwrm_cfa_flow_info *
38822 **********************/
38825 /* hwrm_cfa_flow_info_input (size:256b/32B) */
38826 struct hwrm_cfa_flow_info_input {
38827 /* The HWRM command request type. */
38830 * The completion ring to send the completion event on. This should
38831 * be the NQ ID returned from the `nq_alloc` HWRM command.
38833 uint16_t cmpl_ring;
38835 * The sequence ID is used by the driver for tracking multiple
38836 * commands. This ID is treated as opaque data by the firmware and
38837 * the value is returned in the `hwrm_resp_hdr` upon completion.
38841 * The target ID of the command:
38842 * * 0x0-0xFFF8 - The function ID
38843 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38844 * * 0xFFFD - Reserved for user-space HWRM interface
38847 uint16_t target_id;
38849 * A physical address pointer pointing to a host buffer that the
38850 * command's response data will be written. This can be either a host
38851 * physical address (HPA) or a guest physical address (GPA) and must
38852 * point to a physically contiguous block of memory.
38854 uint64_t resp_addr;
38855 /* Flow record index. */
38856 uint16_t flow_handle;
38857 /* Max flow handle */
38858 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
38860 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
38861 /* CNP flow handle */
38862 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
38864 /* RoCEv1 flow handle */
38865 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
38867 /* RoCEv2 flow handle */
38868 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
38870 /* Direction rx = 1 */
38871 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
38873 uint8_t unused_0[6];
38874 /* This value identifies a set of CFA data structures used for a flow. */
38875 uint64_t ext_flow_handle;
38878 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
38879 struct hwrm_cfa_flow_info_output {
38880 /* The specific error status for the command. */
38881 uint16_t error_code;
38882 /* The HWRM command request type. */
38884 /* The sequence ID from the original command. */
38886 /* The length of the response data in number of bytes. */
38889 /* When set to 1, indicates the configuration is the TX flow. */
38890 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
38891 /* When set to 1, indicates the configuration is the RX flow. */
38892 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
38893 /* profile is 8 b */
38895 /* src_fid is 16 b */
38897 /* dst_fid is 16 b */
38899 /* l2_ctxt_id is 16 b */
38900 uint16_t l2_ctxt_id;
38901 /* em_info is 64 b */
38903 /* tcam_info is 64 b */
38904 uint64_t tcam_info;
38905 /* vfp_tcam_info is 64 b */
38906 uint64_t vfp_tcam_info;
38907 /* ar_id is 16 b */
38909 /* flow_handle is 16 b */
38910 uint16_t flow_handle;
38911 /* tunnel_handle is 32 b */
38912 uint32_t tunnel_handle;
38913 /* The flow aging timer for the flow, the unit is 100 milliseconds */
38914 uint16_t flow_timer;
38915 uint8_t unused_0[6];
38916 /* Flow associated L2, L3 and L4 headers info. */
38917 uint32_t flow_key_data[130];
38918 /* Flow associated action record info. */
38919 uint32_t flow_action_info[30];
38920 uint8_t unused_1[7];
38922 * This field is used in Output records to indicate that the output
38923 * is completely written to RAM. This field should be read as '1'
38924 * to indicate that the output has been completely written.
38925 * When writing a command completion or response to an internal
38926 * processor, the order of writes has to be such that this field is
38932 /***********************
38933 * hwrm_cfa_flow_flush *
38934 ***********************/
38937 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
38938 struct hwrm_cfa_flow_flush_input {
38939 /* The HWRM command request type. */
38942 * The completion ring to send the completion event on. This should
38943 * be the NQ ID returned from the `nq_alloc` HWRM command.
38945 uint16_t cmpl_ring;
38947 * The sequence ID is used by the driver for tracking multiple
38948 * commands. This ID is treated as opaque data by the firmware and
38949 * the value is returned in the `hwrm_resp_hdr` upon completion.
38953 * The target ID of the command:
38954 * * 0x0-0xFFF8 - The function ID
38955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38956 * * 0xFFFD - Reserved for user-space HWRM interface
38959 uint16_t target_id;
38961 * A physical address pointer pointing to a host buffer that the
38962 * command's response data will be written. This can be either a host
38963 * physical address (HPA) or a guest physical address (GPA) and must
38964 * point to a physically contiguous block of memory.
38966 uint64_t resp_addr;
38967 /* flags is 32 b */
38970 * Set to 1 to indicate the page size, page layers, and
38971 * flow_handle_table_dma_addr fields are valid. The flow flush
38972 * operation should only flush the flows from the flow table
38973 * specified. This flag is set to 0 by older driver. For older
38974 * firmware, setting this flag has no effect.
38976 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
38979 * Set to 1 to indicate flow flush operation to cleanup all the
38980 * flows, meters, CFA context memory tables etc. This flag is set to
38981 * 0 by older driver. For older firmware, setting this flag has no
38984 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
38987 * Set to 1 to indicate flow flush operation to cleanup all the
38988 * flows by the caller. This flag is set to 0 by older driver. For
38989 * older firmware, setting this flag has no effect.
38991 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
38994 * Set to 1 to indicate the flow counter IDs are included in the
38997 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
38998 UINT32_C(0x8000000)
39000 * This specifies the size of flow handle entries provided by the
39001 * driver in the flow table specified below. Only two flow handle
39002 * size enums are defined.
39004 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
39005 UINT32_C(0xc0000000)
39006 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
39008 /* The flow handle is 16bit */
39009 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
39010 (UINT32_C(0x0) << 30)
39011 /* The flow handle is 64bit */
39012 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
39013 (UINT32_C(0x1) << 30)
39014 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
39015 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
39016 /* Specify page size of the flow table memory. */
39018 /* The page size is 4K */
39019 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
39020 /* The page size is 8K */
39021 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
39022 /* The page size is 64K */
39023 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
39024 /* The page size is 256K */
39025 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
39026 /* The page size is 1M */
39027 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
39028 /* The page size is 2M */
39029 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
39030 /* The page size is 4M */
39031 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
39032 /* The page size is 1G */
39033 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
39034 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
39035 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
39036 /* FLow table memory indirect levels. */
39037 uint8_t page_level;
39038 /* PBL pointer is physical start address. */
39039 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
39040 /* PBL pointer points to PTE table. */
39041 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
39043 * PBL pointer points to PDE table with each entry pointing to PTE
39046 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
39047 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
39048 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
39049 /* number of flows in the flow table */
39050 uint16_t num_flows;
39051 /* Pointer to the PBL, or PDL depending on number of levels */
39055 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
39056 struct hwrm_cfa_flow_flush_output {
39057 /* The specific error status for the command. */
39058 uint16_t error_code;
39059 /* The HWRM command request type. */
39061 /* The sequence ID from the original command. */
39063 /* The length of the response data in number of bytes. */
39065 uint8_t unused_0[7];
39067 * This field is used in Output records to indicate that the output
39068 * is completely written to RAM. This field should be read as '1'
39069 * to indicate that the output has been completely written.
39070 * When writing a command completion or response to an internal
39071 * processor, the order of writes has to be such that this field is
39077 /***********************
39078 * hwrm_cfa_flow_stats *
39079 ***********************/
39082 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
39083 struct hwrm_cfa_flow_stats_input {
39084 /* The HWRM command request type. */
39087 * The completion ring to send the completion event on. This should
39088 * be the NQ ID returned from the `nq_alloc` HWRM command.
39090 uint16_t cmpl_ring;
39092 * The sequence ID is used by the driver for tracking multiple
39093 * commands. This ID is treated as opaque data by the firmware and
39094 * the value is returned in the `hwrm_resp_hdr` upon completion.
39098 * The target ID of the command:
39099 * * 0x0-0xFFF8 - The function ID
39100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39101 * * 0xFFFD - Reserved for user-space HWRM interface
39104 uint16_t target_id;
39106 * A physical address pointer pointing to a host buffer that the
39107 * command's response data will be written. This can be either a host
39108 * physical address (HPA) or a guest physical address (GPA) and must
39109 * point to a physically contiguous block of memory.
39111 uint64_t resp_addr;
39113 uint16_t num_flows;
39115 uint16_t flow_handle_0;
39117 uint16_t flow_handle_1;
39119 uint16_t flow_handle_2;
39121 uint16_t flow_handle_3;
39123 uint16_t flow_handle_4;
39125 uint16_t flow_handle_5;
39127 uint16_t flow_handle_6;
39129 uint16_t flow_handle_7;
39131 uint16_t flow_handle_8;
39133 uint16_t flow_handle_9;
39134 uint8_t unused_0[2];
39135 /* Flow ID of a flow. */
39136 uint32_t flow_id_0;
39137 /* Flow ID of a flow. */
39138 uint32_t flow_id_1;
39139 /* Flow ID of a flow. */
39140 uint32_t flow_id_2;
39141 /* Flow ID of a flow. */
39142 uint32_t flow_id_3;
39143 /* Flow ID of a flow. */
39144 uint32_t flow_id_4;
39145 /* Flow ID of a flow. */
39146 uint32_t flow_id_5;
39147 /* Flow ID of a flow. */
39148 uint32_t flow_id_6;
39149 /* Flow ID of a flow. */
39150 uint32_t flow_id_7;
39151 /* Flow ID of a flow. */
39152 uint32_t flow_id_8;
39153 /* Flow ID of a flow. */
39154 uint32_t flow_id_9;
39157 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
39158 struct hwrm_cfa_flow_stats_output {
39159 /* The specific error status for the command. */
39160 uint16_t error_code;
39161 /* The HWRM command request type. */
39163 /* The sequence ID from the original command. */
39165 /* The length of the response data in number of bytes. */
39167 /* packet_0 is 64 b */
39169 /* packet_1 is 64 b */
39171 /* packet_2 is 64 b */
39173 /* packet_3 is 64 b */
39175 /* packet_4 is 64 b */
39177 /* packet_5 is 64 b */
39179 /* packet_6 is 64 b */
39181 /* packet_7 is 64 b */
39183 /* packet_8 is 64 b */
39185 /* packet_9 is 64 b */
39187 /* byte_0 is 64 b */
39189 /* byte_1 is 64 b */
39191 /* byte_2 is 64 b */
39193 /* byte_3 is 64 b */
39195 /* byte_4 is 64 b */
39197 /* byte_5 is 64 b */
39199 /* byte_6 is 64 b */
39201 /* byte_7 is 64 b */
39203 /* byte_8 is 64 b */
39205 /* byte_9 is 64 b */
39207 uint8_t unused_0[7];
39209 * This field is used in Output records to indicate that the output
39210 * is completely written to RAM. This field should be read as '1'
39211 * to indicate that the output has been completely written.
39212 * When writing a command completion or response to an internal
39213 * processor, the order of writes has to be such that this field is
39219 /***********************************
39220 * hwrm_cfa_flow_aging_timer_reset *
39221 ***********************************/
39224 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
39225 struct hwrm_cfa_flow_aging_timer_reset_input {
39226 /* The HWRM command request type. */
39229 * The completion ring to send the completion event on. This should
39230 * be the NQ ID returned from the `nq_alloc` HWRM command.
39232 uint16_t cmpl_ring;
39234 * The sequence ID is used by the driver for tracking multiple
39235 * commands. This ID is treated as opaque data by the firmware and
39236 * the value is returned in the `hwrm_resp_hdr` upon completion.
39240 * The target ID of the command:
39241 * * 0x0-0xFFF8 - The function ID
39242 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39243 * * 0xFFFD - Reserved for user-space HWRM interface
39246 uint16_t target_id;
39248 * A physical address pointer pointing to a host buffer that the
39249 * command's response data will be written. This can be either a host
39250 * physical address (HPA) or a guest physical address (GPA) and must
39251 * point to a physically contiguous block of memory.
39253 uint64_t resp_addr;
39254 /* Flow record index. */
39255 uint16_t flow_handle;
39256 uint8_t unused_0[2];
39258 * New flow timer value for the flow specified in the ext_flow_handle.
39259 * The flow timer unit is 100ms.
39261 uint32_t flow_timer;
39262 /* This value identifies a set of CFA data structures used for a flow. */
39263 uint64_t ext_flow_handle;
39266 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
39267 struct hwrm_cfa_flow_aging_timer_reset_output {
39268 /* The specific error status for the command. */
39269 uint16_t error_code;
39270 /* The HWRM command request type. */
39272 /* The sequence ID from the original command. */
39274 /* The length of the response data in number of bytes. */
39276 uint8_t unused_0[7];
39278 * This field is used in Output records to indicate that the output
39279 * is completely written to RAM. This field should be read as '1'
39280 * to indicate that the output has been completely written.
39281 * When writing a command completion or response to an internal
39282 * processor, the order of writes has to be such that this field is
39288 /***************************
39289 * hwrm_cfa_flow_aging_cfg *
39290 ***************************/
39293 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
39294 struct hwrm_cfa_flow_aging_cfg_input {
39295 /* The HWRM command request type. */
39298 * The completion ring to send the completion event on. This should
39299 * be the NQ ID returned from the `nq_alloc` HWRM command.
39301 uint16_t cmpl_ring;
39303 * The sequence ID is used by the driver for tracking multiple
39304 * commands. This ID is treated as opaque data by the firmware and
39305 * the value is returned in the `hwrm_resp_hdr` upon completion.
39309 * The target ID of the command:
39310 * * 0x0-0xFFF8 - The function ID
39311 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39312 * * 0xFFFD - Reserved for user-space HWRM interface
39315 uint16_t target_id;
39317 * A physical address pointer pointing to a host buffer that the
39318 * command's response data will be written. This can be either a host
39319 * physical address (HPA) or a guest physical address (GPA) and must
39320 * point to a physically contiguous block of memory.
39322 uint64_t resp_addr;
39323 /* The bit field to enable per flow aging configuration. */
39326 * This bit must be '1' for the tcp flow timer field to be
39329 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
39332 * This bit must be '1' for the tcp finish timer field to be
39335 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
39338 * This bit must be '1' for the udp flow timer field to be
39341 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
39344 * This bit must be '1' for the eem dma interval field to be
39347 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
39350 * This bit must be '1' for the eem notice interval field to be
39353 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
39356 * This bit must be '1' for the eem context memory maximum entries
39357 * field to be configured
39359 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
39362 * This bit must be '1' for the eem context memory ID field to be
39365 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
39368 * This bit must be '1' for the eem context memory type field to be
39371 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
39374 /* Enumeration denoting the RX, TX type of the resource. */
39375 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
39377 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39379 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39380 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
39381 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
39383 * Enumeration denoting the enable, disable eem flow aging
39386 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
39388 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
39389 (UINT32_C(0x0) << 1)
39391 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
39392 (UINT32_C(0x1) << 1)
39393 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
39394 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
39397 * The flow aging timer for all TCP flows, the unit is 100
39400 uint32_t tcp_flow_timer;
39402 * The TCP finished timer for all TCP flows, the unit is 100
39405 uint32_t tcp_fin_timer;
39407 * The flow aging timer for all UDP flows, the unit is 100
39410 uint32_t udp_flow_timer;
39412 * The interval to dma eem ejection data to host memory, the unit is
39415 uint16_t eem_dma_interval;
39417 * The interval to notify driver to read the eem ejection data, the
39418 * unit is milliseconds.
39420 uint16_t eem_notice_interval;
39421 /* The maximum entries number in the eem context memory. */
39422 uint32_t eem_ctx_max_entries;
39423 /* The context memory ID for eem flow aging. */
39424 uint16_t eem_ctx_id;
39425 uint16_t eem_ctx_mem_type;
39427 * The content of context memory is eem ejection data, the size of
39428 * each entry is 4 bytes.
39430 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
39432 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
39433 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
39434 uint8_t unused_1[4];
39437 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
39438 struct hwrm_cfa_flow_aging_cfg_output {
39439 /* The specific error status for the command. */
39440 uint16_t error_code;
39441 /* The HWRM command request type. */
39443 /* The sequence ID from the original command. */
39445 /* The length of the response data in number of bytes. */
39447 uint8_t unused_0[7];
39449 * This field is used in Output records to indicate that the output
39450 * is completely written to RAM. This field should be read as '1'
39451 * to indicate that the output has been completely written.
39452 * When writing a command completion or response to an internal
39453 * processor, the order of writes has to be such that this field is
39459 /****************************
39460 * hwrm_cfa_flow_aging_qcfg *
39461 ****************************/
39464 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
39465 struct hwrm_cfa_flow_aging_qcfg_input {
39466 /* The HWRM command request type. */
39469 * The completion ring to send the completion event on. This should
39470 * be the NQ ID returned from the `nq_alloc` HWRM command.
39472 uint16_t cmpl_ring;
39474 * The sequence ID is used by the driver for tracking multiple
39475 * commands. This ID is treated as opaque data by the firmware and
39476 * the value is returned in the `hwrm_resp_hdr` upon completion.
39480 * The target ID of the command:
39481 * * 0x0-0xFFF8 - The function ID
39482 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39483 * * 0xFFFD - Reserved for user-space HWRM interface
39486 uint16_t target_id;
39488 * A physical address pointer pointing to a host buffer that the
39489 * command's response data will be written. This can be either a host
39490 * physical address (HPA) or a guest physical address (GPA) and must
39491 * point to a physically contiguous block of memory.
39493 uint64_t resp_addr;
39495 * The direction for the flow aging configuration, 1 is rx path, 2 is
39499 /* Enumeration denoting the RX, TX type of the resource. */
39500 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
39502 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39504 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39505 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
39506 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
39507 uint8_t unused_0[7];
39510 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
39511 struct hwrm_cfa_flow_aging_qcfg_output {
39512 /* The specific error status for the command. */
39513 uint16_t error_code;
39514 /* The HWRM command request type. */
39516 /* The sequence ID from the original command. */
39518 /* The length of the response data in number of bytes. */
39521 * The current flow aging timer for all TCP flows, the unit is 100
39524 uint32_t tcp_flow_timer;
39526 * The current TCP finished timer for all TCP flows, the unit is 100
39529 uint32_t tcp_fin_timer;
39531 * The current flow aging timer for all UDP flows, the unit is 100
39534 uint32_t udp_flow_timer;
39536 * The interval to dma eem ejection data to host memory, the unit is
39539 uint16_t eem_dma_interval;
39541 * The interval to notify driver to read the eem ejection data, the
39542 * unit is milliseconds.
39544 uint16_t eem_notice_interval;
39545 /* The maximum entries number in the eem context memory. */
39546 uint32_t eem_ctx_max_entries;
39547 /* The context memory ID for eem flow aging. */
39548 uint16_t eem_ctx_id;
39549 /* The context memory type for eem flow aging. */
39550 uint16_t eem_ctx_mem_type;
39551 uint8_t unused_0[7];
39553 * This field is used in Output records to indicate that the output
39554 * is completely written to RAM. This field should be read as '1'
39555 * to indicate that the output has been completely written.
39556 * When writing a command completion or response to an internal
39557 * processor, the order of writes has to be such that this field is
39563 /*****************************
39564 * hwrm_cfa_flow_aging_qcaps *
39565 *****************************/
39568 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
39569 struct hwrm_cfa_flow_aging_qcaps_input {
39570 /* The HWRM command request type. */
39573 * The completion ring to send the completion event on. This should
39574 * be the NQ ID returned from the `nq_alloc` HWRM command.
39576 uint16_t cmpl_ring;
39578 * The sequence ID is used by the driver for tracking multiple
39579 * commands. This ID is treated as opaque data by the firmware and
39580 * the value is returned in the `hwrm_resp_hdr` upon completion.
39584 * The target ID of the command:
39585 * * 0x0-0xFFF8 - The function ID
39586 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39587 * * 0xFFFD - Reserved for user-space HWRM interface
39590 uint16_t target_id;
39592 * A physical address pointer pointing to a host buffer that the
39593 * command's response data will be written. This can be either a host
39594 * physical address (HPA) or a guest physical address (GPA) and must
39595 * point to a physically contiguous block of memory.
39597 uint64_t resp_addr;
39599 * The direction for the flow aging configuration, 1 is rx path, 2 is
39603 /* Enumeration denoting the RX, TX type of the resource. */
39604 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
39606 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
39608 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
39609 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
39610 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
39611 uint8_t unused_0[7];
39614 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
39615 struct hwrm_cfa_flow_aging_qcaps_output {
39616 /* The specific error status for the command. */
39617 uint16_t error_code;
39618 /* The HWRM command request type. */
39620 /* The sequence ID from the original command. */
39622 /* The length of the response data in number of bytes. */
39625 * The maximum flow aging timer for all TCP flows, the unit is 100
39628 uint32_t max_tcp_flow_timer;
39630 * The maximum TCP finished timer for all TCP flows, the unit is 100
39633 uint32_t max_tcp_fin_timer;
39635 * The maximum flow aging timer for all UDP flows, the unit is 100
39638 uint32_t max_udp_flow_timer;
39639 /* The maximum aging flows that HW can support. */
39640 uint32_t max_aging_flows;
39641 uint8_t unused_0[7];
39643 * This field is used in Output records to indicate that the output
39644 * is completely written to RAM. This field should be read as '1'
39645 * to indicate that the output has been completely written.
39646 * When writing a command completion or response to an internal
39647 * processor, the order of writes has to be such that this field is
39653 /**********************************
39654 * hwrm_cfa_tcp_flag_process_qcfg *
39655 **********************************/
39658 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
39659 struct hwrm_cfa_tcp_flag_process_qcfg_input {
39660 /* The HWRM command request type. */
39663 * The completion ring to send the completion event on. This should
39664 * be the NQ ID returned from the `nq_alloc` HWRM command.
39666 uint16_t cmpl_ring;
39668 * The sequence ID is used by the driver for tracking multiple
39669 * commands. This ID is treated as opaque data by the firmware and
39670 * the value is returned in the `hwrm_resp_hdr` upon completion.
39674 * The target ID of the command:
39675 * * 0x0-0xFFF8 - The function ID
39676 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39677 * * 0xFFFD - Reserved for user-space HWRM interface
39680 uint16_t target_id;
39682 * A physical address pointer pointing to a host buffer that the
39683 * command's response data will be written. This can be either a host
39684 * physical address (HPA) or a guest physical address (GPA) and must
39685 * point to a physically contiguous block of memory.
39687 uint64_t resp_addr;
39690 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
39691 struct hwrm_cfa_tcp_flag_process_qcfg_output {
39692 /* The specific error status for the command. */
39693 uint16_t error_code;
39694 /* The HWRM command request type. */
39696 /* The sequence ID from the original command. */
39698 /* The length of the response data in number of bytes. */
39700 /* The port 0 RX mirror action record ID. */
39701 uint16_t rx_ar_id_port0;
39702 /* The port 1 RX mirror action record ID. */
39703 uint16_t rx_ar_id_port1;
39705 * The port 0 RX action record ID for TX TCP flag packets from
39708 uint16_t tx_ar_id_port0;
39710 * The port 1 RX action record ID for TX TCP flag packets from
39713 uint16_t tx_ar_id_port1;
39714 uint8_t unused_0[7];
39716 * This field is used in Output records to indicate that the output
39717 * is completely written to RAM. This field should be read as '1'
39718 * to indicate that the output has been completely written.
39719 * When writing a command completion or response to an internal
39720 * processor, the order of writes has to be such that this field is
39726 /**************************
39727 * hwrm_cfa_vf_pair_alloc *
39728 **************************/
39731 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
39732 struct hwrm_cfa_vf_pair_alloc_input {
39733 /* The HWRM command request type. */
39736 * The completion ring to send the completion event on. This should
39737 * be the NQ ID returned from the `nq_alloc` HWRM command.
39739 uint16_t cmpl_ring;
39741 * The sequence ID is used by the driver for tracking multiple
39742 * commands. This ID is treated as opaque data by the firmware and
39743 * the value is returned in the `hwrm_resp_hdr` upon completion.
39747 * The target ID of the command:
39748 * * 0x0-0xFFF8 - The function ID
39749 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39750 * * 0xFFFD - Reserved for user-space HWRM interface
39753 uint16_t target_id;
39755 * A physical address pointer pointing to a host buffer that the
39756 * command's response data will be written. This can be either a host
39757 * physical address (HPA) or a guest physical address (GPA) and must
39758 * point to a physically contiguous block of memory.
39760 uint64_t resp_addr;
39761 /* Logical VF number (range: 0 -> MAX_VFS -1). */
39763 /* Logical VF number (range: 0 -> MAX_VFS -1). */
39765 uint8_t unused_0[4];
39766 /* VF Pair name (32 byte string). */
39767 char pair_name[32];
39770 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
39771 struct hwrm_cfa_vf_pair_alloc_output {
39772 /* The specific error status for the command. */
39773 uint16_t error_code;
39774 /* The HWRM command request type. */
39776 /* The sequence ID from the original command. */
39778 /* The length of the response data in number of bytes. */
39780 uint8_t unused_0[7];
39782 * This field is used in Output records to indicate that the output
39783 * is completely written to RAM. This field should be read as '1'
39784 * to indicate that the output has been completely written.
39785 * When writing a command completion or response to an internal
39786 * processor, the order of writes has to be such that this field is
39792 /*************************
39793 * hwrm_cfa_vf_pair_free *
39794 *************************/
39797 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
39798 struct hwrm_cfa_vf_pair_free_input {
39799 /* The HWRM command request type. */
39802 * The completion ring to send the completion event on. This should
39803 * be the NQ ID returned from the `nq_alloc` HWRM command.
39805 uint16_t cmpl_ring;
39807 * The sequence ID is used by the driver for tracking multiple
39808 * commands. This ID is treated as opaque data by the firmware and
39809 * the value is returned in the `hwrm_resp_hdr` upon completion.
39813 * The target ID of the command:
39814 * * 0x0-0xFFF8 - The function ID
39815 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39816 * * 0xFFFD - Reserved for user-space HWRM interface
39819 uint16_t target_id;
39821 * A physical address pointer pointing to a host buffer that the
39822 * command's response data will be written. This can be either a host
39823 * physical address (HPA) or a guest physical address (GPA) and must
39824 * point to a physically contiguous block of memory.
39826 uint64_t resp_addr;
39827 /* VF Pair name (32 byte string). */
39828 char pair_name[32];
39831 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
39832 struct hwrm_cfa_vf_pair_free_output {
39833 /* The specific error status for the command. */
39834 uint16_t error_code;
39835 /* The HWRM command request type. */
39837 /* The sequence ID from the original command. */
39839 /* The length of the response data in number of bytes. */
39841 uint8_t unused_0[7];
39843 * This field is used in Output records to indicate that the output
39844 * is completely written to RAM. This field should be read as '1'
39845 * to indicate that the output has been completely written.
39846 * When writing a command completion or response to an internal
39847 * processor, the order of writes has to be such that this field is
39853 /*************************
39854 * hwrm_cfa_vf_pair_info *
39855 *************************/
39858 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
39859 struct hwrm_cfa_vf_pair_info_input {
39860 /* The HWRM command request type. */
39863 * The completion ring to send the completion event on. This should
39864 * be the NQ ID returned from the `nq_alloc` HWRM command.
39866 uint16_t cmpl_ring;
39868 * The sequence ID is used by the driver for tracking multiple
39869 * commands. This ID is treated as opaque data by the firmware and
39870 * the value is returned in the `hwrm_resp_hdr` upon completion.
39874 * The target ID of the command:
39875 * * 0x0-0xFFF8 - The function ID
39876 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39877 * * 0xFFFD - Reserved for user-space HWRM interface
39880 uint16_t target_id;
39882 * A physical address pointer pointing to a host buffer that the
39883 * command's response data will be written. This can be either a host
39884 * physical address (HPA) or a guest physical address (GPA) and must
39885 * point to a physically contiguous block of memory.
39887 uint64_t resp_addr;
39889 /* If this flag is set, lookup by name else lookup by index. */
39890 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
39891 /* vf pair table index. */
39892 uint16_t vf_pair_index;
39893 uint8_t unused_0[2];
39894 /* VF Pair name (32 byte string). */
39895 char vf_pair_name[32];
39898 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
39899 struct hwrm_cfa_vf_pair_info_output {
39900 /* The specific error status for the command. */
39901 uint16_t error_code;
39902 /* The HWRM command request type. */
39904 /* The sequence ID from the original command. */
39906 /* The length of the response data in number of bytes. */
39908 /* vf pair table index. */
39909 uint16_t next_vf_pair_index;
39910 /* vf pair member a's vf_fid. */
39912 /* vf pair member a's Linux logical VF number. */
39913 uint16_t vf_a_index;
39914 /* vf pair member b's vf_fid. */
39916 /* vf pair member a's Linux logical VF number. */
39917 uint16_t vf_b_index;
39918 /* vf pair state. */
39919 uint8_t pair_state;
39920 /* Pair has been allocated */
39921 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
39922 /* Both pair members are active */
39923 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
39924 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
39925 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
39926 uint8_t unused_0[5];
39927 /* VF Pair name (32 byte string). */
39928 char pair_name[32];
39929 uint8_t unused_1[7];
39931 * This field is used in Output records to indicate that the output
39932 * is completely written to RAM. This field should be read as '1'
39933 * to indicate that the output has been completely written.
39934 * When writing a command completion or response to an internal
39935 * processor, the order of writes has to be such that this field is
39941 /***********************
39942 * hwrm_cfa_pair_alloc *
39943 ***********************/
39946 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
39947 struct hwrm_cfa_pair_alloc_input {
39948 /* The HWRM command request type. */
39951 * The completion ring to send the completion event on. This should
39952 * be the NQ ID returned from the `nq_alloc` HWRM command.
39954 uint16_t cmpl_ring;
39956 * The sequence ID is used by the driver for tracking multiple
39957 * commands. This ID is treated as opaque data by the firmware and
39958 * the value is returned in the `hwrm_resp_hdr` upon completion.
39962 * The target ID of the command:
39963 * * 0x0-0xFFF8 - The function ID
39964 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39965 * * 0xFFFD - Reserved for user-space HWRM interface
39968 uint16_t target_id;
39970 * A physical address pointer pointing to a host buffer that the
39971 * command's response data will be written. This can be either a host
39972 * physical address (HPA) or a guest physical address (GPA) and must
39973 * point to a physically contiguous block of memory.
39975 uint64_t resp_addr;
39977 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
39978 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
39980 uint16_t pair_mode;
39981 /* Pair between VF on local host with PF or VF on specified host. */
39982 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \
39984 /* Pair between REP on local host with PF or VF on specified host. */
39985 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \
39987 /* Pair between REP on local host with REP on specified host. */
39988 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \
39990 /* Pair for the proxy interface. */
39991 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \
39993 /* Pair for the PF interface. */
39994 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \
39996 /* Modify existing rep2fn pair and move pair to new PF. */
39997 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \
40000 * Modify existing rep2fn pairs paired with same PF and move pairs
40003 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \
40006 * Truflow pair between REP on local host with PF or VF on specified
40009 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \
40011 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
40012 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW
40013 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40015 /* Logical Host (0xff-local host). */
40017 /* Logical PF (0xff-PF for command channel). */
40019 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40021 /* Loopback port (0xff-internal loopback), valid for mode-3. */
40023 /* Priority used for encap of loopback packets valid for mode-3. */
40025 /* New PF for rep2fn modify, valid for mode 5. */
40026 uint16_t new_pf_fid;
40029 * This bit must be '1' for the q_ab field to be
40032 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
40034 * This bit must be '1' for the q_ba field to be
40037 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
40039 * This bit must be '1' for the fc_ab field to be
40042 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
40044 * This bit must be '1' for the fc_ba field to be
40047 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
40048 /* VF Pair name (32 byte string). */
40049 char pair_name[32];
40051 * The q_ab value specifies the logical index of the TX/RX CoS
40052 * queue to be assigned for traffic in the A to B direction of
40053 * the interface pair. The default value is 0.
40057 * The q_ba value specifies the logical index of the TX/RX CoS
40058 * queue to be assigned for traffic in the B to A direction of
40059 * the interface pair. The default value is 1.
40063 * Specifies whether RX ring flow control is disabled (0) or enabled
40064 * (1) in the A to B direction. The default value is 0, meaning that
40065 * packets will be dropped when the B-side RX rings are full.
40069 * Specifies whether RX ring flow control is disabled (0) or enabled
40070 * (1) in the B to A direction. The default value is 1, meaning that
40071 * the RX CoS queue will be flow controlled when the A-side RX rings
40075 uint8_t unused_1[4];
40078 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
40079 struct hwrm_cfa_pair_alloc_output {
40080 /* The specific error status for the command. */
40081 uint16_t error_code;
40082 /* The HWRM command request type. */
40084 /* The sequence ID from the original command. */
40086 /* The length of the response data in number of bytes. */
40088 /* Only valid for modes 1 and 2. */
40089 uint16_t rx_cfa_code_a;
40090 /* Only valid for modes 1 and 2. */
40091 uint16_t tx_cfa_action_a;
40092 /* Only valid for mode 2. */
40093 uint16_t rx_cfa_code_b;
40094 /* Only valid for mode 2. */
40095 uint16_t tx_cfa_action_b;
40096 uint8_t unused_0[7];
40098 * This field is used in Output records to indicate that the output
40099 * is completely written to RAM. This field should be read as '1'
40100 * to indicate that the output has been completely written.
40101 * When writing a command completion or response to an internal
40102 * processor, the order of writes has to be such that this field is
40108 /**********************
40109 * hwrm_cfa_pair_free *
40110 **********************/
40113 /* hwrm_cfa_pair_free_input (size:448b/56B) */
40114 struct hwrm_cfa_pair_free_input {
40115 /* The HWRM command request type. */
40118 * The completion ring to send the completion event on. This should
40119 * be the NQ ID returned from the `nq_alloc` HWRM command.
40121 uint16_t cmpl_ring;
40123 * The sequence ID is used by the driver for tracking multiple
40124 * commands. This ID is treated as opaque data by the firmware and
40125 * the value is returned in the `hwrm_resp_hdr` upon completion.
40129 * The target ID of the command:
40130 * * 0x0-0xFFF8 - The function ID
40131 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40132 * * 0xFFFD - Reserved for user-space HWRM interface
40135 uint16_t target_id;
40137 * A physical address pointer pointing to a host buffer that the
40138 * command's response data will be written. This can be either a host
40139 * physical address (HPA) or a guest physical address (GPA) and must
40140 * point to a physically contiguous block of memory.
40142 uint64_t resp_addr;
40143 /* VF Pair name (32 byte string). */
40144 char pair_name[32];
40145 /* Logical PF (0xff-PF for command channel). */
40147 uint8_t unused_0[3];
40148 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40151 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
40152 * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow).
40154 uint16_t pair_mode;
40155 /* Pair between VF on local host with PF or VF on specified host. */
40156 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
40157 /* Pair between REP on local host with PF or VF on specified host. */
40158 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
40159 /* Pair between REP on local host with REP on specified host. */
40160 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
40161 /* Pair for the proxy interface. */
40162 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
40163 /* Pair for the PF interface. */
40164 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
40165 /* Modify existing rep2fn pair and move pair to new PF. */
40166 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
40168 * Modify existing rep2fn pairs paired with same PF and move pairs
40171 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
40173 * Truflow pair between REP on local host with PF or VF on
40176 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
40177 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \
40178 HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW
40181 /* hwrm_cfa_pair_free_output (size:128b/16B) */
40182 struct hwrm_cfa_pair_free_output {
40183 /* The specific error status for the command. */
40184 uint16_t error_code;
40185 /* The HWRM command request type. */
40187 /* The sequence ID from the original command. */
40189 /* The length of the response data in number of bytes. */
40191 uint8_t unused_0[7];
40193 * This field is used in Output records to indicate that the output
40194 * is completely written to RAM. This field should be read as '1'
40195 * to indicate that the output has been completely written.
40196 * When writing a command completion or response to an internal
40197 * processor, the order of writes has to be such that this field is
40203 /**********************
40204 * hwrm_cfa_pair_info *
40205 **********************/
40208 /* hwrm_cfa_pair_info_input (size:448b/56B) */
40209 struct hwrm_cfa_pair_info_input {
40210 /* The HWRM command request type. */
40213 * The completion ring to send the completion event on. This should
40214 * be the NQ ID returned from the `nq_alloc` HWRM command.
40216 uint16_t cmpl_ring;
40218 * The sequence ID is used by the driver for tracking multiple
40219 * commands. This ID is treated as opaque data by the firmware and
40220 * the value is returned in the `hwrm_resp_hdr` upon completion.
40224 * The target ID of the command:
40225 * * 0x0-0xFFF8 - The function ID
40226 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40227 * * 0xFFFD - Reserved for user-space HWRM interface
40230 uint16_t target_id;
40232 * A physical address pointer pointing to a host buffer that the
40233 * command's response data will be written. This can be either a host
40234 * physical address (HPA) or a guest physical address (GPA) and must
40235 * point to a physically contiguous block of memory.
40237 uint64_t resp_addr;
40239 /* If this flag is set, lookup by name else lookup by index. */
40240 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
40241 /* If this flag is set, lookup by PF id and VF id. */
40242 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
40243 /* Pair table index. */
40244 uint16_t pair_index;
40245 /* Pair pf index. */
40247 /* Pair vf index. */
40249 /* Pair name (32 byte string). */
40250 char pair_name[32];
40253 /* hwrm_cfa_pair_info_output (size:576b/72B) */
40254 struct hwrm_cfa_pair_info_output {
40255 /* The specific error status for the command. */
40256 uint16_t error_code;
40257 /* The HWRM command request type. */
40259 /* The sequence ID from the original command. */
40261 /* The length of the response data in number of bytes. */
40263 /* Pair table index. */
40264 uint16_t next_pair_index;
40265 /* Pair member a's fid. */
40267 /* Logical host number. */
40268 uint8_t host_a_index;
40269 /* Logical PF number. */
40270 uint8_t pf_a_index;
40271 /* Pair member a's Linux logical VF number. */
40272 uint16_t vf_a_index;
40274 uint16_t rx_cfa_code_a;
40275 /* Tx CFA action. */
40276 uint16_t tx_cfa_action_a;
40277 /* Pair member b's fid. */
40279 /* Logical host number. */
40280 uint8_t host_b_index;
40281 /* Logical PF number. */
40282 uint8_t pf_b_index;
40283 /* Pair member a's Linux logical VF number. */
40284 uint16_t vf_b_index;
40286 uint16_t rx_cfa_code_b;
40287 /* Tx CFA action. */
40288 uint16_t tx_cfa_action_b;
40289 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
40291 /* Pair between VF on local host with PF or VF on specified host. */
40292 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
40293 /* Pair between REP on local host with PF or VF on specified host. */
40294 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
40295 /* Pair between REP on local host with REP on specified host. */
40296 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
40297 /* Pair for the proxy interface. */
40298 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
40299 /* Pair for the PF interface. */
40300 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
40301 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
40302 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
40304 uint8_t pair_state;
40305 /* Pair has been allocated */
40306 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
40307 /* Both pair members are active */
40308 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
40309 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
40310 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
40311 /* Pair name (32 byte string). */
40312 char pair_name[32];
40313 uint8_t unused_0[7];
40315 * This field is used in Output records to indicate that the output
40316 * is completely written to RAM. This field should be read as '1'
40317 * to indicate that the output has been completely written.
40318 * When writing a command completion or response to an internal
40319 * processor, the order of writes has to be such that this field is
40325 /**********************
40326 * hwrm_cfa_vfr_alloc *
40327 **********************/
40330 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
40331 struct hwrm_cfa_vfr_alloc_input {
40332 /* The HWRM command request type. */
40335 * The completion ring to send the completion event on. This should
40336 * be the NQ ID returned from the `nq_alloc` HWRM command.
40338 uint16_t cmpl_ring;
40340 * The sequence ID is used by the driver for tracking multiple
40341 * commands. This ID is treated as opaque data by the firmware and
40342 * the value is returned in the `hwrm_resp_hdr` upon completion.
40346 * The target ID of the command:
40347 * * 0x0-0xFFF8 - The function ID
40348 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40349 * * 0xFFFD - Reserved for user-space HWRM interface
40352 uint16_t target_id;
40354 * A physical address pointer pointing to a host buffer that the
40355 * command's response data will be written. This can be either a host
40356 * physical address (HPA) or a guest physical address (GPA) and must
40357 * point to a physically contiguous block of memory.
40359 uint64_t resp_addr;
40360 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40363 * This field is reserved for the future use.
40364 * It shall be set to 0.
40367 uint8_t unused_0[4];
40368 /* VF Representor name (32 byte string). */
40372 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
40373 struct hwrm_cfa_vfr_alloc_output {
40374 /* The specific error status for the command. */
40375 uint16_t error_code;
40376 /* The HWRM command request type. */
40378 /* The sequence ID from the original command. */
40380 /* The length of the response data in number of bytes. */
40383 uint16_t rx_cfa_code;
40384 /* Tx CFA action. */
40385 uint16_t tx_cfa_action;
40386 uint8_t unused_0[3];
40388 * This field is used in Output records to indicate that the output
40389 * is completely written to RAM. This field should be read as '1'
40390 * to indicate that the output has been completely written.
40391 * When writing a command completion or response to an internal
40392 * processor, the order of writes has to be such that this field is
40398 /*********************
40399 * hwrm_cfa_vfr_free *
40400 *********************/
40403 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
40404 struct hwrm_cfa_vfr_free_input {
40405 /* The HWRM command request type. */
40408 * The completion ring to send the completion event on. This should
40409 * be the NQ ID returned from the `nq_alloc` HWRM command.
40411 uint16_t cmpl_ring;
40413 * The sequence ID is used by the driver for tracking multiple
40414 * commands. This ID is treated as opaque data by the firmware and
40415 * the value is returned in the `hwrm_resp_hdr` upon completion.
40419 * The target ID of the command:
40420 * * 0x0-0xFFF8 - The function ID
40421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40422 * * 0xFFFD - Reserved for user-space HWRM interface
40425 uint16_t target_id;
40427 * A physical address pointer pointing to a host buffer that the
40428 * command's response data will be written. This can be either a host
40429 * physical address (HPA) or a guest physical address (GPA) and must
40430 * point to a physically contiguous block of memory.
40432 uint64_t resp_addr;
40433 /* VF Representor name (32 byte string). */
40435 /* Logical VF number (range: 0 -> MAX_VFS -1). */
40438 * This field is reserved for the future use.
40439 * It shall be set to 0.
40442 uint8_t unused_0[4];
40445 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
40446 struct hwrm_cfa_vfr_free_output {
40447 /* The specific error status for the command. */
40448 uint16_t error_code;
40449 /* The HWRM command request type. */
40451 /* The sequence ID from the original command. */
40453 /* The length of the response data in number of bytes. */
40455 uint8_t unused_0[7];
40457 * This field is used in Output records to indicate that the output
40458 * is completely written to RAM. This field should be read as '1'
40459 * to indicate that the output has been completely written.
40460 * When writing a command completion or response to an internal
40461 * processor, the order of writes has to be such that this field is
40467 /***************************************
40468 * hwrm_cfa_redirect_query_tunnel_type *
40469 ***************************************/
40472 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
40473 struct hwrm_cfa_redirect_query_tunnel_type_input {
40474 /* The HWRM command request type. */
40477 * The completion ring to send the completion event on. This should
40478 * be the NQ ID returned from the `nq_alloc` HWRM command.
40480 uint16_t cmpl_ring;
40482 * The sequence ID is used by the driver for tracking multiple
40483 * commands. This ID is treated as opaque data by the firmware and
40484 * the value is returned in the `hwrm_resp_hdr` upon completion.
40488 * The target ID of the command:
40489 * * 0x0-0xFFF8 - The function ID
40490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40491 * * 0xFFFD - Reserved for user-space HWRM interface
40494 uint16_t target_id;
40496 * A physical address pointer pointing to a host buffer that the
40497 * command's response data will be written. This can be either a host
40498 * physical address (HPA) or a guest physical address (GPA) and must
40499 * point to a physically contiguous block of memory.
40501 uint64_t resp_addr;
40502 /* The source function id. */
40504 uint8_t unused_0[6];
40507 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
40508 struct hwrm_cfa_redirect_query_tunnel_type_output {
40509 /* The specific error status for the command. */
40510 uint16_t error_code;
40511 /* The HWRM command request type. */
40513 /* The sequence ID from the original command. */
40515 /* The length of the response data in number of bytes. */
40518 uint32_t tunnel_mask;
40520 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
40522 /* Virtual eXtensible Local Area Network (VXLAN) */
40523 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
40525 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
40526 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
40528 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
40529 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
40532 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
40534 /* Generic Network Virtualization Encapsulation (Geneve) */
40535 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
40537 /* Multi-Protocol Label Switching (MPLS) */
40538 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
40540 /* Stateless Transport Tunnel (STT) */
40541 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
40543 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
40544 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
40546 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
40547 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
40550 * Enhance Generic Routing Encapsulation (GRE version 1) inside IP
40553 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
40555 /* Any tunneled traffic */
40556 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
40558 /* Use fixed layer 2 ether type of 0xFFFF */
40559 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
40562 * IPV6 over virtual eXtensible Local Area Network with GPE header
40565 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
40567 uint8_t unused_0[3];
40569 * This field is used in Output records to indicate that the output
40570 * is completely written to RAM. This field should be read as '1'
40571 * to indicate that the output has been completely written.
40572 * When writing a command completion or response to an internal
40573 * processor, the order of writes has to be such that this field is
40579 /*************************
40580 * hwrm_cfa_ctx_mem_rgtr *
40581 *************************/
40584 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
40585 struct hwrm_cfa_ctx_mem_rgtr_input {
40586 /* The HWRM command request type. */
40589 * The completion ring to send the completion event on. This should
40590 * be the NQ ID returned from the `nq_alloc` HWRM command.
40592 uint16_t cmpl_ring;
40594 * The sequence ID is used by the driver for tracking multiple
40595 * commands. This ID is treated as opaque data by the firmware and
40596 * the value is returned in the `hwrm_resp_hdr` upon completion.
40600 * The target ID of the command:
40601 * * 0x0-0xFFF8 - The function ID
40602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40603 * * 0xFFFD - Reserved for user-space HWRM interface
40606 uint16_t target_id;
40608 * A physical address pointer pointing to a host buffer that the
40609 * command's response data will be written. This can be either a host
40610 * physical address (HPA) or a guest physical address (GPA) and must
40611 * point to a physically contiguous block of memory.
40613 uint64_t resp_addr;
40615 /* Counter PBL indirect levels. */
40616 uint8_t page_level;
40617 /* PBL pointer is physical start address. */
40618 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
40619 /* PBL pointer points to PTE table. */
40620 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
40622 * PBL pointer points to PDE table with each entry pointing to PTE
40625 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
40626 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
40627 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
40630 /* 4KB page size. */
40631 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
40632 /* 8KB page size. */
40633 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
40634 /* 64KB page size. */
40635 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
40636 /* 256KB page size. */
40637 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
40638 /* 1MB page size. */
40639 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
40640 /* 2MB page size. */
40641 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
40642 /* 4MB page size. */
40643 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
40644 /* 1GB page size. */
40645 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
40646 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
40647 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
40649 /* Pointer to the PBL, or PDL depending on number of levels */
40653 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
40654 struct hwrm_cfa_ctx_mem_rgtr_output {
40655 /* The specific error status for the command. */
40656 uint16_t error_code;
40657 /* The HWRM command request type. */
40659 /* The sequence ID from the original command. */
40661 /* The length of the response data in number of bytes. */
40664 * Id/Handle to the recently register context memory. This handle is
40665 * passed to the CFA feature.
40668 uint8_t unused_0[5];
40670 * This field is used in Output records to indicate that the output
40671 * is completely written to RAM. This field should be read as '1'
40672 * to indicate that the output has been completely written.
40673 * When writing a command completion or response to an internal
40674 * processor, the order of writes has to be such that this field is
40680 /***************************
40681 * hwrm_cfa_ctx_mem_unrgtr *
40682 ***************************/
40685 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
40686 struct hwrm_cfa_ctx_mem_unrgtr_input {
40687 /* The HWRM command request type. */
40690 * The completion ring to send the completion event on. This should
40691 * be the NQ ID returned from the `nq_alloc` HWRM command.
40693 uint16_t cmpl_ring;
40695 * The sequence ID is used by the driver for tracking multiple
40696 * commands. This ID is treated as opaque data by the firmware and
40697 * the value is returned in the `hwrm_resp_hdr` upon completion.
40701 * The target ID of the command:
40702 * * 0x0-0xFFF8 - The function ID
40703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40704 * * 0xFFFD - Reserved for user-space HWRM interface
40707 uint16_t target_id;
40709 * A physical address pointer pointing to a host buffer that the
40710 * command's response data will be written. This can be either a host
40711 * physical address (HPA) or a guest physical address (GPA) and must
40712 * point to a physically contiguous block of memory.
40714 uint64_t resp_addr;
40716 * Id/Handle to the recently register context memory. This handle is
40717 * passed to the CFA feature.
40720 uint8_t unused_0[6];
40723 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
40724 struct hwrm_cfa_ctx_mem_unrgtr_output {
40725 /* The specific error status for the command. */
40726 uint16_t error_code;
40727 /* The HWRM command request type. */
40729 /* The sequence ID from the original command. */
40731 /* The length of the response data in number of bytes. */
40733 uint8_t unused_0[7];
40735 * This field is used in Output records to indicate that the output
40736 * is completely written to RAM. This field should be read as '1'
40737 * to indicate that the output has been completely written.
40738 * When writing a command completion or response to an internal
40739 * processor, the order of writes has to be such that this field is
40745 /*************************
40746 * hwrm_cfa_ctx_mem_qctx *
40747 *************************/
40750 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
40751 struct hwrm_cfa_ctx_mem_qctx_input {
40752 /* The HWRM command request type. */
40755 * The completion ring to send the completion event on. This should
40756 * be the NQ ID returned from the `nq_alloc` HWRM command.
40758 uint16_t cmpl_ring;
40760 * The sequence ID is used by the driver for tracking multiple
40761 * commands. This ID is treated as opaque data by the firmware and
40762 * the value is returned in the `hwrm_resp_hdr` upon completion.
40766 * The target ID of the command:
40767 * * 0x0-0xFFF8 - The function ID
40768 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40769 * * 0xFFFD - Reserved for user-space HWRM interface
40772 uint16_t target_id;
40774 * A physical address pointer pointing to a host buffer that the
40775 * command's response data will be written. This can be either a host
40776 * physical address (HPA) or a guest physical address (GPA) and must
40777 * point to a physically contiguous block of memory.
40779 uint64_t resp_addr;
40781 * Id/Handle to the recently register context memory. This handle is
40782 * passed to the CFA feature.
40785 uint8_t unused_0[6];
40788 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
40789 struct hwrm_cfa_ctx_mem_qctx_output {
40790 /* The specific error status for the command. */
40791 uint16_t error_code;
40792 /* The HWRM command request type. */
40794 /* The sequence ID from the original command. */
40796 /* The length of the response data in number of bytes. */
40799 /* Counter PBL indirect levels. */
40800 uint8_t page_level;
40801 /* PBL pointer is physical start address. */
40802 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
40803 /* PBL pointer points to PTE table. */
40804 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
40806 * PBL pointer points to PDE table with each entry pointing to PTE
40809 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
40810 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
40811 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
40814 /* 4KB page size. */
40815 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
40816 /* 8KB page size. */
40817 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
40818 /* 64KB page size. */
40819 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
40820 /* 256KB page size. */
40821 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
40822 /* 1MB page size. */
40823 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
40824 /* 2MB page size. */
40825 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
40826 /* 4MB page size. */
40827 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
40828 /* 1GB page size. */
40829 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
40830 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
40831 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
40832 uint8_t unused_0[4];
40833 /* Pointer to the PBL, or PDL depending on number of levels */
40835 uint8_t unused_1[7];
40837 * This field is used in Output records to indicate that the output
40838 * is completely written to RAM. This field should be read as '1'
40839 * to indicate that the output has been completely written.
40840 * When writing a command completion or response to an internal
40841 * processor, the order of writes has to be such that this field is
40847 /**************************
40848 * hwrm_cfa_ctx_mem_qcaps *
40849 **************************/
40852 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
40853 struct hwrm_cfa_ctx_mem_qcaps_input {
40854 /* The HWRM command request type. */
40857 * The completion ring to send the completion event on. This should
40858 * be the NQ ID returned from the `nq_alloc` HWRM command.
40860 uint16_t cmpl_ring;
40862 * The sequence ID is used by the driver for tracking multiple
40863 * commands. This ID is treated as opaque data by the firmware and
40864 * the value is returned in the `hwrm_resp_hdr` upon completion.
40868 * The target ID of the command:
40869 * * 0x0-0xFFF8 - The function ID
40870 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40871 * * 0xFFFD - Reserved for user-space HWRM interface
40874 uint16_t target_id;
40876 * A physical address pointer pointing to a host buffer that the
40877 * command's response data will be written. This can be either a host
40878 * physical address (HPA) or a guest physical address (GPA) and must
40879 * point to a physically contiguous block of memory.
40881 uint64_t resp_addr;
40884 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
40885 struct hwrm_cfa_ctx_mem_qcaps_output {
40886 /* The specific error status for the command. */
40887 uint16_t error_code;
40888 /* The HWRM command request type. */
40890 /* The sequence ID from the original command. */
40892 /* The length of the response data in number of bytes. */
40895 * Indicates the maximum number of context memory which can be
40898 uint16_t max_entries;
40899 uint8_t unused_0[5];
40901 * This field is used in Output records to indicate that the output
40902 * is completely written to RAM. This field should be read as '1'
40903 * to indicate that the output has been completely written.
40904 * When writing a command completion or response to an internal
40905 * processor, the order of writes has to be such that this field is
40911 /**************************
40912 * hwrm_cfa_counter_qcaps *
40913 **************************/
40916 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
40917 struct hwrm_cfa_counter_qcaps_input {
40918 /* The HWRM command request type. */
40921 * The completion ring to send the completion event on. This should
40922 * be the NQ ID returned from the `nq_alloc` HWRM command.
40924 uint16_t cmpl_ring;
40926 * The sequence ID is used by the driver for tracking multiple
40927 * commands. This ID is treated as opaque data by the firmware and
40928 * the value is returned in the `hwrm_resp_hdr` upon completion.
40932 * The target ID of the command:
40933 * * 0x0-0xFFF8 - The function ID
40934 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40935 * * 0xFFFD - Reserved for user-space HWRM interface
40938 uint16_t target_id;
40940 * A physical address pointer pointing to a host buffer that the
40941 * command's response data will be written. This can be either a host
40942 * physical address (HPA) or a guest physical address (GPA) and must
40943 * point to a physically contiguous block of memory.
40945 uint64_t resp_addr;
40948 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
40949 struct hwrm_cfa_counter_qcaps_output {
40950 /* The specific error status for the command. */
40951 uint16_t error_code;
40952 /* The HWRM command request type. */
40954 /* The sequence ID from the original command. */
40956 /* The length of the response data in number of bytes. */
40959 /* Enumeration denoting the supported CFA counter format. */
40960 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
40962 /* CFA counter types are not supported. */
40963 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
40965 /* 64-bit packet counters followed by 64-bit byte counters format. */
40966 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
40968 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
40969 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
40972 * Minimum guaranteed number of flow counters supported for this
40973 * function, in RX direction.
40975 uint32_t min_rx_fc;
40977 * Maximum non-guaranteed number of flow counters supported for this
40978 * function, in RX direction.
40980 uint32_t max_rx_fc;
40982 * Minimum guaranteed number of flow counters supported for this
40983 * function, in TX direction.
40985 uint32_t min_tx_fc;
40987 * Maximum non-guaranteed number of flow counters supported for this
40988 * function, in TX direction.
40990 uint32_t max_tx_fc;
40992 * Minimum guaranteed number of extension flow counters supported for
40993 * this function, in RX direction.
40995 uint32_t min_rx_efc;
40997 * Maximum non-guaranteed number of extension flow counters supported
40998 * for this function, in RX direction.
41000 uint32_t max_rx_efc;
41002 * Minimum guaranteed number of extension flow counters supported for
41003 * this function, in TX direction.
41005 uint32_t min_tx_efc;
41007 * Maximum non-guaranteed number of extension flow counters supported
41008 * for this function, in TX direction.
41010 uint32_t max_tx_efc;
41012 * Minimum guaranteed number of meter drop counters supported for
41013 * this function, in RX direction.
41015 uint32_t min_rx_mdc;
41017 * Maximum non-guaranteed number of meter drop counters supported for
41018 * this function, in RX direction.
41020 uint32_t max_rx_mdc;
41022 * Minimum guaranteed number of meter drop counters supported for this
41023 * function, in TX direction.
41025 uint32_t min_tx_mdc;
41027 * Maximum non-guaranteed number of meter drop counters supported for
41028 * this function, in TX direction.
41030 uint32_t max_tx_mdc;
41032 * Maximum guaranteed number of flow counters which can be used during
41035 uint32_t max_flow_alloc_fc;
41036 uint8_t unused_1[3];
41038 * This field is used in Output records to indicate that the output
41039 * is completely written to RAM. This field should be read as '1'
41040 * to indicate that the output has been completely written.
41041 * When writing a command completion or response to an internal
41042 * processor, the order of writes has to be such that this field is
41048 /************************
41049 * hwrm_cfa_counter_cfg *
41050 ************************/
41053 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
41054 struct hwrm_cfa_counter_cfg_input {
41055 /* The HWRM command request type. */
41058 * The completion ring to send the completion event on. This should
41059 * be the NQ ID returned from the `nq_alloc` HWRM command.
41061 uint16_t cmpl_ring;
41063 * The sequence ID is used by the driver for tracking multiple
41064 * commands. This ID is treated as opaque data by the firmware and
41065 * the value is returned in the `hwrm_resp_hdr` upon completion.
41069 * The target ID of the command:
41070 * * 0x0-0xFFF8 - The function ID
41071 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41072 * * 0xFFFD - Reserved for user-space HWRM interface
41075 uint16_t target_id;
41077 * A physical address pointer pointing to a host buffer that the
41078 * command's response data will be written. This can be either a host
41079 * physical address (HPA) or a guest physical address (GPA) and must
41080 * point to a physically contiguous block of memory.
41082 uint64_t resp_addr;
41084 /* Enumeration denoting the configuration mode. */
41085 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
41087 /* Disable the configuration mode. */
41088 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
41090 /* Enable the configuration mode. */
41091 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
41093 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
41094 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
41095 /* Enumeration denoting the RX, TX type of the resource. */
41096 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
41099 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
41100 (UINT32_C(0x0) << 1)
41102 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
41103 (UINT32_C(0x1) << 1)
41104 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
41105 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
41106 /* Enumeration denoting the data transfer mode. */
41107 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
41109 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
41111 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
41112 (UINT32_C(0x0) << 2)
41114 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
41115 (UINT32_C(0x1) << 2)
41116 /* Pull on async update. */
41117 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
41118 (UINT32_C(0x2) << 2)
41119 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
41120 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
41121 uint16_t counter_type;
41122 /* Flow counters. */
41123 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
41124 /* Extended flow counters. */
41125 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
41126 /* Meter drop counters. */
41127 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
41128 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
41129 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
41130 /* Ctx memory handle to be used for the counter. */
41132 /* Counter update cadence hint (only in Push mode). */
41133 uint16_t update_tmr_ms;
41134 /* Total number of entries. */
41135 uint32_t num_entries;
41139 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
41140 struct hwrm_cfa_counter_cfg_output {
41141 /* The specific error status for the command. */
41142 uint16_t error_code;
41143 /* The HWRM command request type. */
41145 /* The sequence ID from the original command. */
41147 /* The length of the response data in number of bytes. */
41149 uint8_t unused_0[7];
41151 * This field is used in Output records to indicate that the output
41152 * is completely written to RAM. This field should be read as '1'
41153 * to indicate that the output has been completely written.
41154 * When writing a command completion or response to an internal
41155 * processor, the order of writes has to be such that this field is
41161 /***************************
41162 * hwrm_cfa_counter_qstats *
41163 ***************************/
41166 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
41167 struct hwrm_cfa_counter_qstats_input {
41168 /* The HWRM command request type. */
41171 * The completion ring to send the completion event on. This should
41172 * be the NQ ID returned from the `nq_alloc` HWRM command.
41174 uint16_t cmpl_ring;
41176 * The sequence ID is used by the driver for tracking multiple
41177 * commands. This ID is treated as opaque data by the firmware and
41178 * the value is returned in the `hwrm_resp_hdr` upon completion.
41182 * The target ID of the command:
41183 * * 0x0-0xFFF8 - The function ID
41184 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41185 * * 0xFFFD - Reserved for user-space HWRM interface
41188 uint16_t target_id;
41190 * A physical address pointer pointing to a host buffer that the
41191 * command's response data will be written. This can be either a host
41192 * physical address (HPA) or a guest physical address (GPA) and must
41193 * point to a physically contiguous block of memory.
41195 uint64_t resp_addr;
41197 /* Enumeration denoting the RX, TX type of the resource. */
41198 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
41200 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
41202 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
41203 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
41204 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
41205 uint16_t counter_type;
41206 uint16_t input_flow_ctx_id;
41207 uint16_t num_entries;
41208 uint16_t delta_time_ms;
41209 uint16_t meter_instance_id;
41210 uint16_t mdc_ctx_id;
41211 uint8_t unused_0[2];
41212 uint64_t expected_count;
41215 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
41216 struct hwrm_cfa_counter_qstats_output {
41217 /* The specific error status for the command. */
41218 uint16_t error_code;
41219 /* The HWRM command request type. */
41221 /* The sequence ID from the original command. */
41223 /* The length of the response data in number of bytes. */
41225 uint8_t unused_0[7];
41227 * This field is used in Output records to indicate that the output
41228 * is completely written to RAM. This field should be read as '1'
41229 * to indicate that the output has been completely written.
41230 * When writing a command completion or response to an internal
41231 * processor, the order of writes has to be such that this field is
41237 /**********************
41238 * hwrm_cfa_eem_qcaps *
41239 **********************/
41242 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
41243 struct hwrm_cfa_eem_qcaps_input {
41244 /* The HWRM command request type. */
41247 * The completion ring to send the completion event on. This should
41248 * be the NQ ID returned from the `nq_alloc` HWRM command.
41250 uint16_t cmpl_ring;
41252 * The sequence ID is used by the driver for tracking multiple
41253 * commands. This ID is treated as opaque data by the firmware and
41254 * the value is returned in the `hwrm_resp_hdr` upon completion.
41258 * The target ID of the command:
41259 * * 0x0-0xFFF8 - The function ID
41260 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41261 * * 0xFFFD - Reserved for user-space HWRM interface
41264 uint16_t target_id;
41266 * A physical address pointer pointing to a host buffer that the
41267 * command's response data will be written. This can be either a host
41268 * physical address (HPA) or a guest physical address (GPA) and must
41269 * point to a physically contiguous block of memory.
41271 uint64_t resp_addr;
41274 * When set to 1, indicates the configuration will apply to TX flows
41275 * which are to be offloaded.
41276 * Note if this bit is set then the path_rx bit can't be set.
41278 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
41281 * When set to 1, indicates the configuration will apply to RX flows
41282 * which are to be offloaded.
41283 * Note if this bit is set then the path_tx bit can't be set.
41285 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
41287 /* When set to 1, all offloaded flows will be sent to EEM. */
41288 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
41293 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
41294 struct hwrm_cfa_eem_qcaps_output {
41295 /* The specific error status for the command. */
41296 uint16_t error_code;
41297 /* The HWRM command request type. */
41299 /* The sequence ID from the original command. */
41301 /* The length of the response data in number of bytes. */
41305 * When set to 1, indicates the configuration will apply to TX flows
41306 * which are to be offloaded.
41307 * Note if this bit is set then the path_rx bit can't be set.
41309 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
41312 * When set to 1, indicates the configuration will apply to RX flows
41313 * which are to be offloaded.
41314 * Note if this bit is set then the path_tx bit can't be set.
41316 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
41319 * When set to 1, indicates the FW supports the Centralized
41320 * Memory Model. The concept designates one entity for the
41321 * memory allocation while all others ‘subscribe’ to it.
41323 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41326 * When set to 1, indicates the FW supports the Detached
41327 * Centralized Memory Model. The memory is allocated and managed
41328 * as a separate entity. All PFs and VFs will be granted direct
41329 * or semi-direct access to the allocated memory while none of
41330 * which can interfere with the management of the memory.
41332 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
41335 uint32_t supported;
41337 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
41338 * If set to 0, EEM KEY0 table is not supported.
41340 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
41343 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
41344 * If set to 0, EEM KEY1 table is not supported.
41346 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
41349 * If set to 1, then EEM External Record table is supported.
41350 * If set to 0, EEM External Record table is not supported.
41351 * (This table includes action record, EFC pointers, encap pointers)
41353 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
41356 * If set to 1, then EEM External Flow Counters table is supported.
41357 * If set to 0, EEM External Flow Counters table is not supported.
41359 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
41362 * If set to 1, then FID table used for implicit flow flush is
41364 * If set to 0, then FID table used for implicit flow flush is
41367 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
41370 * The maximum number of entries supported by EEM. When configuring
41371 * the host memory, the number of numbers of entries that can
41373 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M
41375 * Any value that are not these values, the FW will round down to the
41376 * closest support number of entries.
41378 uint32_t max_entries_supported;
41379 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
41380 uint16_t key_entry_size;
41381 /* The entry size in bytes of each entry in the EEM RECORD tables. */
41382 uint16_t record_entry_size;
41383 /* The entry size in bytes of each entry in the EEM EFC tables. */
41384 uint16_t efc_entry_size;
41385 /* The FID size in bytes of each entry in the EEM FID tables. */
41386 uint16_t fid_entry_size;
41387 uint8_t unused_1[7];
41389 * This field is used in Output records to indicate that the output
41390 * is completely written to RAM. This field should be read as '1'
41391 * to indicate that the output has been completely written.
41392 * When writing a command completion or response to an internal
41393 * processor, the order of writes has to be such that this field is
41399 /********************
41400 * hwrm_cfa_eem_cfg *
41401 ********************/
41404 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
41405 struct hwrm_cfa_eem_cfg_input {
41406 /* The HWRM command request type. */
41409 * The completion ring to send the completion event on. This should
41410 * be the NQ ID returned from the `nq_alloc` HWRM command.
41412 uint16_t cmpl_ring;
41414 * The sequence ID is used by the driver for tracking multiple
41415 * commands. This ID is treated as opaque data by the firmware and
41416 * the value is returned in the `hwrm_resp_hdr` upon completion.
41420 * The target ID of the command:
41421 * * 0x0-0xFFF8 - The function ID
41422 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41423 * * 0xFFFD - Reserved for user-space HWRM interface
41426 uint16_t target_id;
41428 * A physical address pointer pointing to a host buffer that the
41429 * command's response data will be written. This can be either a host
41430 * physical address (HPA) or a guest physical address (GPA) and must
41431 * point to a physically contiguous block of memory.
41433 uint64_t resp_addr;
41436 * When set to 1, indicates the configuration will apply to TX flows
41437 * which are to be offloaded.
41438 * Note if this bit is set then the path_rx bit can't be set.
41440 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
41443 * When set to 1, indicates the configuration will apply to RX flows
41444 * which are to be offloaded.
41445 * Note if this bit is set then the path_tx bit can't be set.
41447 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
41449 /* When set to 1, all offloaded flows will be sent to EEM. */
41450 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
41452 /* When set to 1, secondary, 0 means primary. */
41453 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
41456 * Group_id which used by Firmware to identify memory pools belonging
41457 * to certain group.
41462 * Configured EEM with the given number of entries. All the EEM tables
41463 * KEY0, KEY1, RECORD, EFC all have the same number of entries and all
41464 * tables will be configured using this value. Current minimum value
41465 * is 32k. Current maximum value is 128M.
41467 uint32_t num_entries;
41469 /* Configured EEM with the given context if for KEY0 table. */
41470 uint16_t key0_ctx_id;
41471 /* Configured EEM with the given context if for KEY1 table. */
41472 uint16_t key1_ctx_id;
41473 /* Configured EEM with the given context if for RECORD table. */
41474 uint16_t record_ctx_id;
41475 /* Configured EEM with the given context if for EFC table. */
41476 uint16_t efc_ctx_id;
41477 /* Configured EEM with the given context if for EFC table. */
41478 uint16_t fid_ctx_id;
41483 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
41484 struct hwrm_cfa_eem_cfg_output {
41485 /* The specific error status for the command. */
41486 uint16_t error_code;
41487 /* The HWRM command request type. */
41489 /* The sequence ID from the original command. */
41491 /* The length of the response data in number of bytes. */
41493 uint8_t unused_0[7];
41495 * This field is used in Output records to indicate that the output
41496 * is completely written to RAM. This field should be read as '1'
41497 * to indicate that the output has been completely written.
41498 * When writing a command completion or response to an internal
41499 * processor, the order of writes has to be such that this field is
41505 /*********************
41506 * hwrm_cfa_eem_qcfg *
41507 *********************/
41510 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
41511 struct hwrm_cfa_eem_qcfg_input {
41512 /* The HWRM command request type. */
41515 * The completion ring to send the completion event on. This should
41516 * be the NQ ID returned from the `nq_alloc` HWRM command.
41518 uint16_t cmpl_ring;
41520 * The sequence ID is used by the driver for tracking multiple
41521 * commands. This ID is treated as opaque data by the firmware and
41522 * the value is returned in the `hwrm_resp_hdr` upon completion.
41526 * The target ID of the command:
41527 * * 0x0-0xFFF8 - The function ID
41528 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41529 * * 0xFFFD - Reserved for user-space HWRM interface
41532 uint16_t target_id;
41534 * A physical address pointer pointing to a host buffer that the
41535 * command's response data will be written. This can be either a host
41536 * physical address (HPA) or a guest physical address (GPA) and must
41537 * point to a physically contiguous block of memory.
41539 uint64_t resp_addr;
41541 /* When set to 1, indicates the configuration is the TX flow. */
41542 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
41543 /* When set to 1, indicates the configuration is the RX flow. */
41544 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
41548 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
41549 struct hwrm_cfa_eem_qcfg_output {
41550 /* The specific error status for the command. */
41551 uint16_t error_code;
41552 /* The HWRM command request type. */
41554 /* The sequence ID from the original command. */
41556 /* The length of the response data in number of bytes. */
41559 /* When set to 1, indicates the configuration is the TX flow. */
41560 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
41562 /* When set to 1, indicates the configuration is the RX flow. */
41563 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
41565 /* When set to 1, all offloaded flows will be sent to EEM. */
41566 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
41568 /* The number of entries the FW has configured for EEM. */
41569 uint32_t num_entries;
41570 /* Configured EEM with the given context if for KEY0 table. */
41571 uint16_t key0_ctx_id;
41572 /* Configured EEM with the given context if for KEY1 table. */
41573 uint16_t key1_ctx_id;
41574 /* Configured EEM with the given context if for RECORD table. */
41575 uint16_t record_ctx_id;
41576 /* Configured EEM with the given context if for EFC table. */
41577 uint16_t efc_ctx_id;
41578 /* Configured EEM with the given context if for EFC table. */
41579 uint16_t fid_ctx_id;
41580 uint8_t unused_2[5];
41582 * This field is used in Output records to indicate that the output
41583 * is completely written to RAM. This field should be read as '1'
41584 * to indicate that the output has been completely written.
41585 * When writing a command completion or response to an internal
41586 * processor, the order of writes has to be such that this field is
41592 /*******************
41593 * hwrm_cfa_eem_op *
41594 *******************/
41597 /* hwrm_cfa_eem_op_input (size:192b/24B) */
41598 struct hwrm_cfa_eem_op_input {
41599 /* The HWRM command request type. */
41602 * The completion ring to send the completion event on. This should
41603 * be the NQ ID returned from the `nq_alloc` HWRM command.
41605 uint16_t cmpl_ring;
41607 * The sequence ID is used by the driver for tracking multiple
41608 * commands. This ID is treated as opaque data by the firmware and
41609 * the value is returned in the `hwrm_resp_hdr` upon completion.
41613 * The target ID of the command:
41614 * * 0x0-0xFFF8 - The function ID
41615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41616 * * 0xFFFD - Reserved for user-space HWRM interface
41619 uint16_t target_id;
41621 * A physical address pointer pointing to a host buffer that the
41622 * command's response data will be written. This can be either a host
41623 * physical address (HPA) or a guest physical address (GPA) and must
41624 * point to a physically contiguous block of memory.
41626 uint64_t resp_addr;
41629 * When set to 1, indicates the host memory which is passed will be
41630 * used for the TX flow offload function specified in fid.
41631 * Note if this bit is set then the path_rx bit can't be set.
41633 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
41635 * When set to 1, indicates the host memory which is passed will be
41636 * used for the RX flow offload function specified in fid.
41637 * Note if this bit is set then the path_tx bit can't be set.
41639 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
41641 /* The number of EEM key table entries to be configured. */
41643 /* This value is reserved and should not be used. */
41644 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
41646 * To properly stop EEM and ensure there are no DMA's, the caller
41647 * must disable EEM for the given PF, using this call. This will
41648 * safely disable EEM and ensure that all DMA'ed to the
41649 * keys/records/efc have been completed.
41651 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
41653 * Once the EEM host memory has been configured, EEM options have
41654 * been configured. Then the caller should enable EEM for the given
41655 * PF. Note once this call has been made, then the EEM mechanism
41656 * will be active and DMA's will occur as packets are processed.
41658 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
41660 * Clear EEM settings for the given PF so that the register values
41661 * are reset back to there initial state.
41663 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
41664 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
41665 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
41668 /* hwrm_cfa_eem_op_output (size:128b/16B) */
41669 struct hwrm_cfa_eem_op_output {
41670 /* The specific error status for the command. */
41671 uint16_t error_code;
41672 /* The HWRM command request type. */
41674 /* The sequence ID from the original command. */
41676 /* The length of the response data in number of bytes. */
41678 uint8_t unused_0[7];
41680 * This field is used in Output records to indicate that the output
41681 * is completely written to RAM. This field should be read as '1'
41682 * to indicate that the output has been completely written.
41683 * When writing a command completion or response to an internal
41684 * processor, the order of writes has to be such that this field is
41690 /********************************
41691 * hwrm_cfa_adv_flow_mgnt_qcaps *
41692 ********************************/
41695 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
41696 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
41697 /* The HWRM command request type. */
41700 * The completion ring to send the completion event on. This should
41701 * be the NQ ID returned from the `nq_alloc` HWRM command.
41703 uint16_t cmpl_ring;
41705 * The sequence ID is used by the driver for tracking multiple
41706 * commands. This ID is treated as opaque data by the firmware and
41707 * the value is returned in the `hwrm_resp_hdr` upon completion.
41711 * The target ID of the command:
41712 * * 0x0-0xFFF8 - The function ID
41713 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41714 * * 0xFFFD - Reserved for user-space HWRM interface
41717 uint16_t target_id;
41719 * A physical address pointer pointing to a host buffer that the
41720 * command's response data will be written. This can be either a host
41721 * physical address (HPA) or a guest physical address (GPA) and must
41722 * point to a physically contiguous block of memory.
41724 uint64_t resp_addr;
41725 uint32_t unused_0[4];
41728 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
41729 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
41730 /* The specific error status for the command. */
41731 uint16_t error_code;
41732 /* The HWRM command request type. */
41734 /* The sequence ID from the original command. */
41736 /* The length of the response data in number of bytes. */
41740 * Value of 1 to indicate firmware support 16-bit flow handle.
41741 * Value of 0 to indicate firmware not support 16-bit flow handle.
41743 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
41746 * Value of 1 to indicate firmware support 64-bit flow handle.
41747 * Value of 0 to indicate firmware not support 64-bit flow handle.
41749 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
41752 * Value of 1 to indicate firmware support flow batch delete
41753 * operation through HWRM_CFA_FLOW_FLUSH command.
41754 * Value of 0 to indicate that the firmware does not support flow
41755 * batch delete operation.
41757 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
41760 * Value of 1 to indicate that the firmware support flow reset all
41761 * operation through HWRM_CFA_FLOW_FLUSH command.
41762 * Value of 0 indicates firmware does not support flow reset all
41765 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
41768 * Value of 1 to indicate that firmware supports use of FID as
41769 * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.
41770 * Value of 0 indicates firmware does not support use of FID as
41773 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
41776 * Value of 1 to indicate that firmware supports TX EEM flows.
41777 * Value of 0 indicates firmware does not support TX EEM flows.
41779 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
41782 * Value of 1 to indicate that firmware supports RX EEM flows.
41783 * Value of 0 indicates firmware does not support RX EEM flows.
41785 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
41788 * Value of 1 to indicate that firmware supports the dynamic
41789 * allocation of an on-chip flow counter which can be used for EEM
41790 * flows. Value of 0 indicates firmware does not support the dynamic
41791 * allocation of an on-chip flow counter.
41793 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
41796 * Value of 1 to indicate that firmware supports setting of
41797 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
41798 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
41800 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
41803 * Value of 1 to indicate that firmware supports untagged matching
41804 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
41805 * indicates firmware does not support untagged matching.
41807 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
41810 * Value of 1 to indicate that firmware supports XDP filter. Value
41811 * of 0 indicates firmware does not support XDP filter.
41813 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
41816 * Value of 1 to indicate that the firmware support L2 header source
41817 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
41818 * Value of 0 indicates firmware does not support L2 header source
41821 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
41824 * If set to 1, firmware is capable of supporting ARP ethertype as
41825 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
41826 * RX direction. By default, this flag should be 0 for older version
41829 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
41832 * Value of 1 to indicate that firmware supports setting of
41833 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
41834 * command. Value of 0 indicates firmware does not support
41835 * rfs_ring_tbl_idx in dst_id field.
41837 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
41840 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
41841 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
41842 * direction. By default, this flag should be 0 for older version
41845 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
41848 * When this bit is '1', it indicates that core firmware is
41849 * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX
41850 * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.
41852 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \
41855 * If set to 1, firmware is capable of supporting L2/ROCE as
41856 * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.
41857 * By default, this flag should be 0 for older version of firmware.
41859 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \
41861 uint8_t unused_0[3];
41863 * This field is used in Output records to indicate that the output
41864 * is completely written to RAM. This field should be read as '1'
41865 * to indicate that the output has been completely written.
41866 * When writing a command completion or response to an internal
41867 * processor, the order of writes has to be such that this field is
41873 /******************
41875 ******************/
41878 /* hwrm_cfa_tflib_input (size:1024b/128B) */
41879 struct hwrm_cfa_tflib_input {
41880 /* The HWRM command request type. */
41883 * The completion ring to send the completion event on. This should
41884 * be the NQ ID returned from the `nq_alloc` HWRM command.
41886 uint16_t cmpl_ring;
41888 * The sequence ID is used by the driver for tracking multiple
41889 * commands. This ID is treated as opaque data by the firmware and
41890 * the value is returned in the `hwrm_resp_hdr` upon completion.
41894 * The target ID of the command:
41895 * * 0x0-0xFFF8 - The function ID
41896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41897 * * 0xFFFD - Reserved for user-space HWRM interface
41900 uint16_t target_id;
41902 * A physical address pointer pointing to a host buffer that the
41903 * command's response data will be written. This can be either a host
41904 * physical address (HPA) or a guest physical address (GPA) and must
41905 * point to a physically contiguous block of memory.
41907 uint64_t resp_addr;
41908 /* TFLIB message type. */
41910 /* TFLIB message subtype. */
41911 uint16_t tf_subtype;
41913 uint8_t unused0[4];
41914 /* TFLIB request data. */
41915 uint32_t tf_req[26];
41918 /* hwrm_cfa_tflib_output (size:5632b/704B) */
41919 struct hwrm_cfa_tflib_output {
41920 /* The specific error status for the command. */
41921 uint16_t error_code;
41922 /* The HWRM command request type. */
41924 /* The sequence ID from the original command. */
41926 /* The length of the response data in number of bytes. */
41928 /* TFLIB message type. */
41930 /* TFLIB message subtype. */
41931 uint16_t tf_subtype;
41932 /* TFLIB response code */
41933 uint32_t tf_resp_code;
41934 /* TFLIB response data. */
41935 uint32_t tf_resp[170];
41937 uint8_t unused1[7];
41939 * This field is used in Output records to indicate that the output
41940 * is completely written to RAM. This field should be read as '1'
41941 * to indicate that the output has been completely written.
41942 * When writing a command completion or response to an internal
41943 * processor, the order of writes has to be such that this field is
41954 /* hwrm_tf_input (size:1024b/128B) */
41955 struct hwrm_tf_input {
41956 /* The HWRM command request type. */
41959 * The completion ring to send the completion event on. This should
41960 * be the NQ ID returned from the `nq_alloc` HWRM command.
41962 uint16_t cmpl_ring;
41964 * The sequence ID is used by the driver for tracking multiple
41965 * commands. This ID is treated as opaque data by the firmware and
41966 * the value is returned in the `hwrm_resp_hdr` upon completion.
41970 * The target ID of the command:
41971 * * 0x0-0xFFF8 - The function ID
41972 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41973 * * 0xFFFD - Reserved for user-space HWRM interface
41976 uint16_t target_id;
41978 * A physical address pointer pointing to a host buffer that the
41979 * command's response data will be written. This can be either a host
41980 * physical address (HPA) or a guest physical address (GPA) and must
41981 * point to a physically contiguous block of memory.
41983 uint64_t resp_addr;
41984 /* TF message type. */
41986 /* TF message subtype. */
41989 uint8_t unused0[4];
41990 /* TF request data. */
41994 /* hwrm_tf_output (size:5632b/704B) */
41995 struct hwrm_tf_output {
41996 /* The specific error status for the command. */
41997 uint16_t error_code;
41998 /* The HWRM command request type. */
42000 /* The sequence ID from the original command. */
42002 /* The length of the response data in number of bytes. */
42004 /* TF message type. */
42006 /* TF message subtype. */
42008 /* TF response code */
42009 uint32_t resp_code;
42010 /* TF response data. */
42011 uint32_t resp[170];
42013 uint8_t unused1[7];
42015 * This field is used in Output records to indicate that the
42016 * output is completely written to RAM. This field should be
42017 * read as '1' to indicate that the output has been
42018 * completely written. When writing a command completion or
42019 * response to an internal processor, the order of writes has
42020 * to be such that this field is written last.
42025 /***********************
42026 * hwrm_tf_version_get *
42027 ***********************/
42030 /* hwrm_tf_version_get_input (size:128b/16B) */
42031 struct hwrm_tf_version_get_input {
42032 /* The HWRM command request type. */
42035 * The completion ring to send the completion event on. This should
42036 * be the NQ ID returned from the `nq_alloc` HWRM command.
42038 uint16_t cmpl_ring;
42040 * The sequence ID is used by the driver for tracking multiple
42041 * commands. This ID is treated as opaque data by the firmware and
42042 * the value is returned in the `hwrm_resp_hdr` upon completion.
42046 * The target ID of the command:
42047 * * 0x0-0xFFF8 - The function ID
42048 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42049 * * 0xFFFD - Reserved for user-space HWRM interface
42052 uint16_t target_id;
42054 * A physical address pointer pointing to a host buffer that the
42055 * command's response data will be written. This can be either a host
42056 * physical address (HPA) or a guest physical address (GPA) and must
42057 * point to a physically contiguous block of memory.
42059 uint64_t resp_addr;
42062 /* hwrm_tf_version_get_output (size:128b/16B) */
42063 struct hwrm_tf_version_get_output {
42064 /* The specific error status for the command. */
42065 uint16_t error_code;
42066 /* The HWRM command request type. */
42068 /* The sequence ID from the original command. */
42070 /* The length of the response data in number of bytes. */
42072 /* Version Major number. */
42074 /* Version Minor number. */
42076 /* Version Update number. */
42079 uint8_t unused0[4];
42081 * This field is used in Output records to indicate that the output
42082 * is completely written to RAM. This field should be read as '1'
42083 * to indicate that the output has been completely written.
42084 * When writing a command completion or response to an internal
42085 * processor, the order of writes has to be such that this field is
42091 /************************
42092 * hwrm_tf_session_open *
42093 ************************/
42096 /* hwrm_tf_session_open_input (size:640b/80B) */
42097 struct hwrm_tf_session_open_input {
42098 /* The HWRM command request type. */
42101 * The completion ring to send the completion event on. This should
42102 * be the NQ ID returned from the `nq_alloc` HWRM command.
42104 uint16_t cmpl_ring;
42106 * The sequence ID is used by the driver for tracking multiple
42107 * commands. This ID is treated as opaque data by the firmware and
42108 * the value is returned in the `hwrm_resp_hdr` upon completion.
42112 * The target ID of the command:
42113 * * 0x0-0xFFF8 - The function ID
42114 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42115 * * 0xFFFD - Reserved for user-space HWRM interface
42118 uint16_t target_id;
42120 * A physical address pointer pointing to a host buffer that the
42121 * command's response data will be written. This can be either a host
42122 * physical address (HPA) or a guest physical address (GPA) and must
42123 * point to a physically contiguous block of memory.
42125 uint64_t resp_addr;
42126 /* Name of the session. */
42127 uint8_t session_name[64];
42130 /* hwrm_tf_session_open_output (size:192b/24B) */
42131 struct hwrm_tf_session_open_output {
42132 /* The specific error status for the command. */
42133 uint16_t error_code;
42134 /* The HWRM command request type. */
42136 /* The sequence ID from the original command. */
42138 /* The length of the response data in number of bytes. */
42141 * Unique session identifier for the session created by the
42144 uint32_t fw_session_id;
42146 * Unique session client identifier for the first client on
42147 * the newly created session.
42149 uint32_t fw_session_client_id;
42151 /* Indicates if the shared session has been created. */
42152 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION \
42155 * If this bit set to 0, then it indicates the shared session
42156 * has been created by another session.
42158 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR \
42161 * If this bit is set to 1, then it indicates the shared session
42162 * is created by this session.
42164 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR \
42166 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_LAST \
42167 HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR
42169 uint8_t unused1[3];
42171 * This field is used in Output records to indicate that the output
42172 * is completely written to RAM. This field should be read as '1'
42173 * to indicate that the output has been completely written.
42174 * When writing a command completion or response to an internal
42175 * processor, the order of writes has to be such that this field is
42181 /**************************
42182 * hwrm_tf_session_attach *
42183 **************************/
42186 /* hwrm_tf_session_attach_input (size:704b/88B) */
42187 struct hwrm_tf_session_attach_input {
42188 /* The HWRM command request type. */
42191 * The completion ring to send the completion event on. This should
42192 * be the NQ ID returned from the `nq_alloc` HWRM command.
42194 uint16_t cmpl_ring;
42196 * The sequence ID is used by the driver for tracking multiple
42197 * commands. This ID is treated as opaque data by the firmware and
42198 * the value is returned in the `hwrm_resp_hdr` upon completion.
42202 * The target ID of the command:
42203 * * 0x0-0xFFF8 - The function ID
42204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42205 * * 0xFFFD - Reserved for user-space HWRM interface
42208 uint16_t target_id;
42210 * A physical address pointer pointing to a host buffer that the
42211 * command's response data will be written. This can be either a host
42212 * physical address (HPA) or a guest physical address (GPA) and must
42213 * point to a physically contiguous block of memory.
42215 uint64_t resp_addr;
42217 * Unique session identifier for the session that the attach
42218 * request want to attach to. This value originates from the
42219 * shared session memory that the attach request opened by
42220 * way of the 'attach name' that was passed in to the core
42222 * The fw_session_id of the attach session includes PCIe bus
42223 * info to distinguish the PF and session info to identify
42224 * the associated TruFlow session.
42226 uint32_t attach_fw_session_id;
42229 /* Name of the session it self. */
42230 uint8_t session_name[64];
42233 /* hwrm_tf_session_attach_output (size:128b/16B) */
42234 struct hwrm_tf_session_attach_output {
42235 /* The specific error status for the command. */
42236 uint16_t error_code;
42237 /* The HWRM command request type. */
42239 /* The sequence ID from the original command. */
42241 /* The length of the response data in number of bytes. */
42244 * Unique session identifier for the session created by the
42245 * firmware. It includes PCIe bus info to distinguish the PF
42246 * and session info to identify the associated TruFlow
42247 * session. This fw_session_id is unique to the attach
42250 uint32_t fw_session_id;
42252 uint8_t unused0[3];
42254 * This field is used in Output records to indicate that the output
42255 * is completely written to RAM. This field should be read as '1'
42256 * to indicate that the output has been completely written.
42257 * When writing a command completion or response to an internal
42258 * processor, the order of writes has to be such that this field is
42264 /****************************
42265 * hwrm_tf_session_register *
42266 ****************************/
42269 /* hwrm_tf_session_register_input (size:704b/88B) */
42270 struct hwrm_tf_session_register_input {
42271 /* The HWRM command request type. */
42274 * The completion ring to send the completion event on. This should
42275 * be the NQ ID returned from the `nq_alloc` HWRM command.
42277 uint16_t cmpl_ring;
42279 * The sequence ID is used by the driver for tracking multiple
42280 * commands. This ID is treated as opaque data by the firmware and
42281 * the value is returned in the `hwrm_resp_hdr` upon completion.
42285 * The target ID of the command:
42286 * * 0x0-0xFFF8 - The function ID
42287 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42288 * * 0xFFFD - Reserved for user-space HWRM interface
42291 uint16_t target_id;
42293 * A physical address pointer pointing to a host buffer that the
42294 * command's response data will be written. This can be either a host
42295 * physical address (HPA) or a guest physical address (GPA) and must
42296 * point to a physically contiguous block of memory.
42298 uint64_t resp_addr;
42300 * Unique session identifier for the session that the
42301 * register request want to create a new client on. This
42302 * value originates from the first open request.
42303 * The fw_session_id of the attach session includes PCIe bus
42304 * info to distinguish the PF and session info to identify
42305 * the associated TruFlow session.
42307 uint32_t fw_session_id;
42310 /* Name of the session client. */
42311 uint8_t session_client_name[64];
42314 /* hwrm_tf_session_register_output (size:128b/16B) */
42315 struct hwrm_tf_session_register_output {
42316 /* The specific error status for the command. */
42317 uint16_t error_code;
42318 /* The HWRM command request type. */
42320 /* The sequence ID from the original command. */
42322 /* The length of the response data in number of bytes. */
42325 * Unique session client identifier for the session created
42326 * by the firmware. It includes the session the client it
42327 * attached to and session client info.
42329 uint32_t fw_session_client_id;
42331 uint8_t unused0[3];
42333 * This field is used in Output records to indicate that the output
42334 * is completely written to RAM. This field should be read as '1'
42335 * to indicate that the output has been completely written.
42336 * When writing a command completion or response to an internal
42337 * processor, the order of writes has to be such that this field is
42343 /******************************
42344 * hwrm_tf_session_unregister *
42345 ******************************/
42348 /* hwrm_tf_session_unregister_input (size:192b/24B) */
42349 struct hwrm_tf_session_unregister_input {
42350 /* The HWRM command request type. */
42353 * The completion ring to send the completion event on. This should
42354 * be the NQ ID returned from the `nq_alloc` HWRM command.
42356 uint16_t cmpl_ring;
42358 * The sequence ID is used by the driver for tracking multiple
42359 * commands. This ID is treated as opaque data by the firmware and
42360 * the value is returned in the `hwrm_resp_hdr` upon completion.
42364 * The target ID of the command:
42365 * * 0x0-0xFFF8 - The function ID
42366 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42367 * * 0xFFFD - Reserved for user-space HWRM interface
42370 uint16_t target_id;
42372 * A physical address pointer pointing to a host buffer that the
42373 * command's response data will be written. This can be either a host
42374 * physical address (HPA) or a guest physical address (GPA) and must
42375 * point to a physically contiguous block of memory.
42377 uint64_t resp_addr;
42379 * Unique session identifier for the session that the
42380 * unregister request want to close a session client on.
42382 uint32_t fw_session_id;
42384 * Unique session client identifier for the session that the
42385 * unregister request want to close.
42387 uint32_t fw_session_client_id;
42390 /* hwrm_tf_session_unregister_output (size:128b/16B) */
42391 struct hwrm_tf_session_unregister_output {
42392 /* The specific error status for the command. */
42393 uint16_t error_code;
42394 /* The HWRM command request type. */
42396 /* The sequence ID from the original command. */
42398 /* The length of the response data in number of bytes. */
42401 uint8_t unused0[7];
42403 * This field is used in Output records to indicate that the output
42404 * is completely written to RAM. This field should be read as '1'
42405 * to indicate that the output has been completely written.
42406 * When writing a command completion or response to an internal
42407 * processor, the order of writes has to be such that this field is
42413 /*************************
42414 * hwrm_tf_session_close *
42415 *************************/
42418 /* hwrm_tf_session_close_input (size:192b/24B) */
42419 struct hwrm_tf_session_close_input {
42420 /* The HWRM command request type. */
42423 * The completion ring to send the completion event on. This should
42424 * be the NQ ID returned from the `nq_alloc` HWRM command.
42426 uint16_t cmpl_ring;
42428 * The sequence ID is used by the driver for tracking multiple
42429 * commands. This ID is treated as opaque data by the firmware and
42430 * the value is returned in the `hwrm_resp_hdr` upon completion.
42434 * The target ID of the command:
42435 * * 0x0-0xFFF8 - The function ID
42436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42437 * * 0xFFFD - Reserved for user-space HWRM interface
42440 uint16_t target_id;
42442 * A physical address pointer pointing to a host buffer that the
42443 * command's response data will be written. This can be either a host
42444 * physical address (HPA) or a guest physical address (GPA) and must
42445 * point to a physically contiguous block of memory.
42447 uint64_t resp_addr;
42448 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42449 uint32_t fw_session_id;
42451 uint8_t unused0[4];
42454 /* hwrm_tf_session_close_output (size:128b/16B) */
42455 struct hwrm_tf_session_close_output {
42456 /* The specific error status for the command. */
42457 uint16_t error_code;
42458 /* The HWRM command request type. */
42460 /* The sequence ID from the original command. */
42462 /* The length of the response data in number of bytes. */
42465 uint8_t unused0[7];
42467 * This field is used in Output records to indicate that the output
42468 * is completely written to RAM. This field should be read as '1'
42469 * to indicate that the output has been completely written.
42470 * When writing a command completion or response to an internal
42471 * processor, the order of writes has to be such that this field
42477 /************************
42478 * hwrm_tf_session_qcfg *
42479 ************************/
42482 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
42483 struct hwrm_tf_session_qcfg_input {
42484 /* The HWRM command request type. */
42487 * The completion ring to send the completion event on. This should
42488 * be the NQ ID returned from the `nq_alloc` HWRM command.
42490 uint16_t cmpl_ring;
42492 * The sequence ID is used by the driver for tracking multiple
42493 * commands. This ID is treated as opaque data by the firmware and
42494 * the value is returned in the `hwrm_resp_hdr` upon completion.
42498 * The target ID of the command:
42499 * * 0x0-0xFFF8 - The function ID
42500 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42501 * * 0xFFFD - Reserved for user-space HWRM interface
42504 uint16_t target_id;
42506 * A physical address pointer pointing to a host buffer that the
42507 * command's response data will be written. This can be either a host
42508 * physical address (HPA) or a guest physical address (GPA) and must
42509 * point to a physically contiguous block of memory.
42511 uint64_t resp_addr;
42512 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42513 uint32_t fw_session_id;
42515 uint8_t unused0[4];
42518 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
42519 struct hwrm_tf_session_qcfg_output {
42520 /* The specific error status for the command. */
42521 uint16_t error_code;
42522 /* The HWRM command request type. */
42524 /* The sequence ID from the original command. */
42526 /* The length of the response data in number of bytes. */
42528 /* RX action control settings flags. */
42529 uint8_t rx_act_flags;
42531 * A value of 1 in this field indicates that Global Flow ID
42532 * reporting into cfa_code and cfa_metadata is enabled.
42534 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
42537 * A value of 1 in this field indicates that both inner and outer
42538 * are stripped and inner tag is passed.
42541 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
42544 * A value of 1 in this field indicates that the re-use of
42545 * existing tunnel L2 header SMAC is enabled for
42546 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
42548 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
42550 /* TX Action control settings flags. */
42551 uint8_t tx_act_flags;
42553 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
42556 * When set to 1 any GRE tunnels will include the
42557 * optional Key field.
42559 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
42562 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
42563 * field of the outer header is inherited from the inner header
42564 * (if present) or the fixed value as taken from the encap
42567 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
42570 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
42571 * field of the outer header is inherited from the inner header
42572 * (if present) or the fixed value as taken from the encap record.
42574 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
42577 uint8_t unused0[5];
42579 * This field is used in Output records to indicate that the output
42580 * is completely written to RAM. This field should be read as '1'
42581 * to indicate that the output has been completely written.
42582 * When writing a command completion or response to an internal
42583 * processor, the order of writes has to be such that this field
42589 /******************************
42590 * hwrm_tf_session_resc_qcaps *
42591 ******************************/
42594 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
42595 struct hwrm_tf_session_resc_qcaps_input {
42596 /* The HWRM command request type. */
42599 * The completion ring to send the completion event on. This should
42600 * be the NQ ID returned from the `nq_alloc` HWRM command.
42602 uint16_t cmpl_ring;
42604 * The sequence ID is used by the driver for tracking multiple
42605 * commands. This ID is treated as opaque data by the firmware and
42606 * the value is returned in the `hwrm_resp_hdr` upon completion.
42610 * The target ID of the command:
42611 * * 0x0-0xFFF8 - The function ID
42612 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42613 * * 0xFFFD - Reserved for user-space HWRM interface
42616 uint16_t target_id;
42618 * A physical address pointer pointing to a host buffer that the
42619 * command's response data will be written. This can be either a host
42620 * physical address (HPA) or a guest physical address (GPA) and must
42621 * point to a physically contiguous block of memory.
42623 uint64_t resp_addr;
42624 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42625 uint32_t fw_session_id;
42626 /* Control flags. */
42628 /* Indicates the flow direction. */
42629 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
42630 /* If this bit set to 0, then it indicates rx flow. */
42631 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42632 /* If this bit is set to 1, then it indicates that tx flow. */
42633 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42634 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
42635 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
42637 * Defines the size of the provided qcaps_addr array
42638 * buffer. The size should be set to the Resource Manager
42639 * provided max number of qcaps entries which is device
42640 * specific. Resource Manager gets the max size from HCAPI
42643 uint16_t qcaps_size;
42645 * This is the DMA address for the qcaps output data array
42646 * buffer. Array is of tf_rm_resc_req_entry type and is
42649 uint64_t qcaps_addr;
42652 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
42653 struct hwrm_tf_session_resc_qcaps_output {
42654 /* The specific error status for the command. */
42655 uint16_t error_code;
42656 /* The HWRM command request type. */
42658 /* The sequence ID from the original command. */
42660 /* The length of the response data in number of bytes. */
42662 /* Control flags. */
42664 /* Session reservation strategy. */
42665 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
42667 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
42669 /* Static partitioning. */
42670 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
42673 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
42676 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
42679 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
42681 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
42682 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
42684 * Size of the returned qcaps_addr data array buffer. The
42685 * value cannot exceed the size defined by the input msg,
42692 uint8_t unused1[7];
42694 * This field is used in Output records to indicate that the output
42695 * is completely written to RAM. This field should be read as '1'
42696 * to indicate that the output has been completely written.
42697 * When writing a command completion or response to an internal
42698 * processor, the order of writes has to be such that this field is
42704 /******************************
42705 * hwrm_tf_session_resc_alloc *
42706 ******************************/
42709 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
42710 struct hwrm_tf_session_resc_alloc_input {
42711 /* The HWRM command request type. */
42714 * The completion ring to send the completion event on. This should
42715 * be the NQ ID returned from the `nq_alloc` HWRM command.
42717 uint16_t cmpl_ring;
42719 * The sequence ID is used by the driver for tracking multiple
42720 * commands. This ID is treated as opaque data by the firmware and
42721 * the value is returned in the `hwrm_resp_hdr` upon completion.
42725 * The target ID of the command:
42726 * * 0x0-0xFFF8 - The function ID
42727 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42728 * * 0xFFFD - Reserved for user-space HWRM interface
42731 uint16_t target_id;
42733 * A physical address pointer pointing to a host buffer that the
42734 * command's response data will be written. This can be either a host
42735 * physical address (HPA) or a guest physical address (GPA) and must
42736 * point to a physically contiguous block of memory.
42738 uint64_t resp_addr;
42739 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42740 uint32_t fw_session_id;
42741 /* Control flags. */
42743 /* Indicates the flow direction. */
42744 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
42745 /* If this bit set to 0, then it indicates rx flow. */
42746 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42747 /* If this bit is set to 1, then it indicates that tx flow. */
42748 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42749 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
42750 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
42752 * Defines the array size of the provided req_addr and
42753 * resv_addr array buffers. Should be set to the number of
42758 * This is the DMA address for the request input data array
42759 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
42760 * array buffer is provided by the 'req_size' field in this
42765 * This is the DMA address for the resc output data array
42766 * buffer. Array is of tf_rm_resc_entry type. Size of the array
42767 * buffer is provided by the 'req_size' field in this
42770 uint64_t resc_addr;
42773 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
42774 struct hwrm_tf_session_resc_alloc_output {
42775 /* The specific error status for the command. */
42776 uint16_t error_code;
42777 /* The HWRM command request type. */
42779 /* The sequence ID from the original command. */
42781 /* The length of the response data in number of bytes. */
42784 * Size of the returned tf_rm_resc_entry data array. The value
42785 * cannot exceed the req_size defined by the input msg. The data
42786 * array is returned using the resv_addr specified DMA
42787 * address also provided by the input msg.
42791 uint8_t unused0[5];
42793 * This field is used in Output records to indicate that the output
42794 * is completely written to RAM. This field should be read as '1'
42795 * to indicate that the output has been completely written.
42796 * When writing a command completion or response to an internal
42797 * processor, the order of writes has to be such that this field is
42803 /*****************************
42804 * hwrm_tf_session_resc_free *
42805 *****************************/
42808 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
42809 struct hwrm_tf_session_resc_free_input {
42810 /* The HWRM command request type. */
42813 * The completion ring to send the completion event on. This should
42814 * be the NQ ID returned from the `nq_alloc` HWRM command.
42816 uint16_t cmpl_ring;
42818 * The sequence ID is used by the driver for tracking multiple
42819 * commands. This ID is treated as opaque data by the firmware and
42820 * the value is returned in the `hwrm_resp_hdr` upon completion.
42824 * The target ID of the command:
42825 * * 0x0-0xFFF8 - The function ID
42826 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42827 * * 0xFFFD - Reserved for user-space HWRM interface
42830 uint16_t target_id;
42832 * A physical address pointer pointing to a host buffer that the
42833 * command's response data will be written. This can be either a host
42834 * physical address (HPA) or a guest physical address (GPA) and must
42835 * point to a physically contiguous block of memory.
42837 uint64_t resp_addr;
42838 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42839 uint32_t fw_session_id;
42840 /* Control flags. */
42842 /* Indicates the flow direction. */
42843 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
42844 /* If this bit set to 0, then it indicates rx flow. */
42845 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42846 /* If this bit is set to 1, then it indicates that tx flow. */
42847 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42848 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
42849 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
42851 * Defines the size, in bytes, of the provided free_addr
42854 uint16_t free_size;
42856 * This is the DMA address for the free input data array
42857 * buffer. Array is of tf_rm_resc_entry type. Size of the
42858 * buffer is provided by the 'free_size' field of this
42861 uint64_t free_addr;
42864 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
42865 struct hwrm_tf_session_resc_free_output {
42866 /* The specific error status for the command. */
42867 uint16_t error_code;
42868 /* The HWRM command request type. */
42870 /* The sequence ID from the original command. */
42872 /* The length of the response data in number of bytes. */
42875 uint8_t unused0[7];
42877 * This field is used in Output records to indicate that the output
42878 * is completely written to RAM. This field should be read as '1'
42879 * to indicate that the output has been completely written.
42880 * When writing a command completion or response to an internal
42881 * processor, the order of writes has to be such that this field is
42887 /******************************
42888 * hwrm_tf_session_resc_flush *
42889 ******************************/
42892 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
42893 struct hwrm_tf_session_resc_flush_input {
42894 /* The HWRM command request type. */
42897 * The completion ring to send the completion event on. This should
42898 * be the NQ ID returned from the `nq_alloc` HWRM command.
42900 uint16_t cmpl_ring;
42902 * The sequence ID is used by the driver for tracking multiple
42903 * commands. This ID is treated as opaque data by the firmware and
42904 * the value is returned in the `hwrm_resp_hdr` upon completion.
42908 * The target ID of the command:
42909 * * 0x0-0xFFF8 - The function ID
42910 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42911 * * 0xFFFD - Reserved for user-space HWRM interface
42914 uint16_t target_id;
42916 * A physical address pointer pointing to a host buffer that the
42917 * command's response data will be written. This can be either a host
42918 * physical address (HPA) or a guest physical address (GPA) and must
42919 * point to a physically contiguous block of memory.
42921 uint64_t resp_addr;
42922 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
42923 uint32_t fw_session_id;
42924 /* Control flags. */
42926 /* Indicates the flow direction. */
42927 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
42928 /* If this bit set to 0, then it indicates rx flow. */
42929 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
42930 /* If this bit is set to 1, then it indicates that tx flow. */
42931 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
42932 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
42933 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
42935 * Defines the size, in bytes, of the provided flush_addr
42938 uint16_t flush_size;
42940 * This is the DMA address for the flush input data array
42941 * buffer. Array of tf_rm_resc_entry type. Size of the
42942 * buffer is provided by the 'flush_size' field in this
42945 uint64_t flush_addr;
42948 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
42949 struct hwrm_tf_session_resc_flush_output {
42950 /* The specific error status for the command. */
42951 uint16_t error_code;
42952 /* The HWRM command request type. */
42954 /* The sequence ID from the original command. */
42956 /* The length of the response data in number of bytes. */
42959 uint8_t unused0[7];
42961 * This field is used in Output records to indicate that the output
42962 * is completely written to RAM. This field should be read as '1'
42963 * to indicate that the output has been completely written.
42964 * When writing a command completion or response to an internal
42965 * processor, the order of writes has to be such that this field is
42971 /*****************************
42972 * hwrm_tf_session_resc_info *
42973 *****************************/
42976 /* hwrm_tf_session_resc_info_input (size:320b/40B) */
42977 struct hwrm_tf_session_resc_info_input {
42978 /* The HWRM command request type. */
42981 * The completion ring to send the completion event on. This should
42982 * be the NQ ID returned from the `nq_alloc` HWRM command.
42984 uint16_t cmpl_ring;
42986 * The sequence ID is used by the driver for tracking multiple
42987 * commands. This ID is treated as opaque data by the firmware and
42988 * the value is returned in the `hwrm_resp_hdr` upon completion.
42992 * The target ID of the command:
42993 * * 0x0-0xFFF8 - The function ID
42994 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42995 * * 0xFFFD - Reserved for user-space HWRM interface
42998 uint16_t target_id;
43000 * A physical address pointer pointing to a host buffer that the
43001 * command's response data will be written. This can be either a host
43002 * physical address (HPA) or a guest physical address (GPA) and must
43003 * point to a physically contiguous block of memory.
43005 uint64_t resp_addr;
43006 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43007 uint32_t fw_session_id;
43008 /* Control flags. */
43010 /* Indicates the flow direction. */
43011 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
43012 /* If this bit set to 0, then it indicates rx flow. */
43013 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43014 /* If this bit is set to 1, then it indicates tx flow. */
43015 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43016 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_LAST \
43017 HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX
43019 * Defines the array size of the provided req_addr and
43020 * resv_addr array buffers. Should be set to the number of
43025 * This is the DMA address for the request input data array
43026 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
43027 * array buffer is provided by the 'req_size' field in this
43032 * This is the DMA address for the resc output data array
43033 * buffer. Array is of tf_rm_resc_entry type. Size of the array
43034 * buffer is provided by the 'req_size' field in this
43037 uint64_t resc_addr;
43040 /* hwrm_tf_session_resc_info_output (size:128b/16B) */
43041 struct hwrm_tf_session_resc_info_output {
43042 /* The specific error status for the command. */
43043 uint16_t error_code;
43044 /* The HWRM command request type. */
43046 /* The sequence ID from the original command. */
43048 /* The length of the response data in number of bytes. */
43051 * Size of the returned tf_rm_resc_entry data array. The value
43052 * cannot exceed the req_size defined by the input msg. The data
43053 * array is returned using the resv_addr specified DMA
43054 * address also provided by the input msg.
43058 uint8_t unused0[5];
43060 * This field is used in Output records to indicate that the output
43061 * is completely written to RAM. This field should be read as '1'
43062 * to indicate that the output has been completely written.
43063 * When writing a command completion or response to an internal
43064 * processor, the order of writes has to be such that this field is
43070 /* TruFlow RM capability of a resource. */
43071 /* tf_rm_resc_req_entry (size:64b/8B) */
43072 struct tf_rm_resc_req_entry {
43073 /* Type of the resource, defined globally in HCAPI RM. */
43075 /* Minimum value. */
43077 /* Maximum value. */
43081 /* TruFlow RM reservation information. */
43082 /* tf_rm_resc_entry (size:64b/8B) */
43083 struct tf_rm_resc_entry {
43084 /* Type of the resource, defined globally in HCAPI RM. */
43086 /* Start offset. */
43088 /* Number of resources. */
43092 /************************
43093 * hwrm_tf_tbl_type_get *
43094 ************************/
43097 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
43098 struct hwrm_tf_tbl_type_get_input {
43099 /* The HWRM command request type. */
43102 * The completion ring to send the completion event on. This should
43103 * be the NQ ID returned from the `nq_alloc` HWRM command.
43105 uint16_t cmpl_ring;
43107 * The sequence ID is used by the driver for tracking multiple
43108 * commands. This ID is treated as opaque data by the firmware and
43109 * the value is returned in the `hwrm_resp_hdr` upon completion.
43113 * The target ID of the command:
43114 * * 0x0-0xFFF8 - The function ID
43115 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43116 * * 0xFFFD - Reserved for user-space HWRM interface
43119 uint16_t target_id;
43121 * A physical address pointer pointing to a host buffer that the
43122 * command's response data will be written. This can be either a host
43123 * physical address (HPA) or a guest physical address (GPA) and must
43124 * point to a physically contiguous block of memory.
43126 uint64_t resp_addr;
43127 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43128 uint32_t fw_session_id;
43129 /* Control flags. */
43131 /* Indicates the flow direction. */
43132 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
43133 /* If this bit set to 0, then it indicates rx flow. */
43134 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43135 /* If this bit is set to 1, then it indicates that tx flow. */
43136 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43137 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
43138 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
43140 uint8_t unused0[2];
43142 * Type of the resource, defined globally in the
43143 * hwrm_tf_resc_type enum.
43146 /* Index of the type to retrieve. */
43150 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
43151 struct hwrm_tf_tbl_type_get_output {
43152 /* The specific error status for the command. */
43153 uint16_t error_code;
43154 /* The HWRM command request type. */
43156 /* The sequence ID from the original command. */
43158 /* The length of the response data in number of bytes. */
43160 /* Response code. */
43161 uint32_t resp_code;
43162 /* Response size. */
43166 /* Response data. */
43169 uint8_t unused1[7];
43171 * This field is used in Output records to indicate that the output
43172 * is completely written to RAM. This field should be read as '1'
43173 * to indicate that the output has been completely written.
43174 * When writing a command completion or response to an internal
43175 * processor, the order of writes has to be such that this field
43181 /************************
43182 * hwrm_tf_tbl_type_set *
43183 ************************/
43186 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
43187 struct hwrm_tf_tbl_type_set_input {
43188 /* The HWRM command request type. */
43191 * The completion ring to send the completion event on. This should
43192 * be the NQ ID returned from the `nq_alloc` HWRM command.
43194 uint16_t cmpl_ring;
43196 * The sequence ID is used by the driver for tracking multiple
43197 * commands. This ID is treated as opaque data by the firmware and
43198 * the value is returned in the `hwrm_resp_hdr` upon completion.
43202 * The target ID of the command:
43203 * * 0x0-0xFFF8 - The function ID
43204 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43205 * * 0xFFFD - Reserved for user-space HWRM interface
43208 uint16_t target_id;
43210 * A physical address pointer pointing to a host buffer that the
43211 * command's response data will be written. This can be either a host
43212 * physical address (HPA) or a guest physical address (GPA) and must
43213 * point to a physically contiguous block of memory.
43215 uint64_t resp_addr;
43216 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43217 uint32_t fw_session_id;
43218 /* Control flags. */
43220 /* Indicates the flow direction. */
43221 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
43222 /* If this bit set to 0, then it indicates rx flow. */
43223 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43224 /* If this bit is set to 1, then it indicates that tx flow. */
43225 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43226 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
43227 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
43229 uint8_t unused0[2];
43231 * Type of the resource, defined globally in the
43232 * hwrm_tf_resc_type enum.
43235 /* Index of the type to retrieve. */
43237 /* Size of the data to set. */
43240 uint8_t unused1[6];
43241 /* Data to be set. */
43245 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
43246 struct hwrm_tf_tbl_type_set_output {
43247 /* The specific error status for the command. */
43248 uint16_t error_code;
43249 /* The HWRM command request type. */
43251 /* The sequence ID from the original command. */
43253 /* The length of the response data in number of bytes. */
43256 uint8_t unused0[7];
43258 * This field is used in Output records to indicate that the output
43259 * is completely written to RAM. This field should be read as '1'
43260 * to indicate that the output has been completely written.
43261 * When writing a command completion or response to an internal
43262 * processor, the order of writes has to be such that this field
43268 /**************************
43269 * hwrm_tf_ctxt_mem_alloc *
43270 **************************/
43273 /* hwrm_tf_ctxt_mem_alloc_input (size:192b/24B) */
43274 struct hwrm_tf_ctxt_mem_alloc_input {
43275 /* The HWRM command request type. */
43278 * The completion ring to send the completion event on. This should
43279 * be the NQ ID returned from the `nq_alloc` HWRM command.
43281 uint16_t cmpl_ring;
43283 * The sequence ID is used by the driver for tracking multiple
43284 * commands. This ID is treated as opaque data by the firmware and
43285 * the value is returned in the `hwrm_resp_hdr` upon completion.
43289 * The target ID of the command:
43290 * * 0x0-0xFFF8 - The function ID
43291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43292 * * 0xFFFD - Reserved for user-space HWRM interface
43295 uint16_t target_id;
43297 * A physical address pointer pointing to a host buffer that the
43298 * command's response data will be written. This can be either a host
43299 * physical address (HPA) or a guest physical address (GPA) and must
43300 * point to a physically contiguous block of memory.
43302 uint64_t resp_addr;
43303 /* Size in KB of memory to be allocated. */
43305 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43306 uint32_t fw_session_id;
43309 /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */
43310 struct hwrm_tf_ctxt_mem_alloc_output {
43311 /* The specific error status for the command. */
43312 uint16_t error_code;
43313 /* The HWRM command request type. */
43315 /* The sequence ID from the original command. */
43317 /* The length of the response data in number of bytes. */
43319 /* Pointer to the PBL, or PDL depending on number of levels */
43321 /* Size of memory allocated. */
43323 /* Counter PBL indirect levels. */
43324 uint8_t page_level;
43325 /* PBL pointer is physical start address. */
43326 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43327 /* PBL pointer points to PTE table. */
43328 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43330 * PBL pointer points to PDE table with each entry pointing
43333 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43334 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LAST \
43335 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_LEVEL_LVL_2
43338 /* 4KB page size. */
43339 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
43340 /* 8KB page size. */
43341 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
43342 /* 64KB page size. */
43343 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
43344 /* 128KB page size. */
43345 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_128K UINT32_C(0x5)
43346 /* 256KB page size. */
43347 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
43348 /* 512KB page size. */
43349 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_512K UINT32_C(0x7)
43350 /* 1MB page size. */
43351 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
43352 /* 2MB page size. */
43353 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
43354 /* 4MB page size. */
43355 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
43356 /* 8MB page size. */
43357 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_8M UINT32_C(0xb)
43358 /* 1GB page size. */
43359 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
43360 #define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \
43361 HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G
43365 * This field is used in Output records to indicate that the
43366 * output is completely written to RAM. This field should be
43367 * read as '1' to indicate that the output has been
43368 * completely written. When writing a command completion or
43369 * response to an internal processor, the order of writes has
43370 * to be such that this field is written last.
43375 /*************************
43376 * hwrm_tf_ctxt_mem_free *
43377 *************************/
43380 /* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */
43381 struct hwrm_tf_ctxt_mem_free_input {
43382 /* The HWRM command request type. */
43385 * The completion ring to send the completion event on. This should
43386 * be the NQ ID returned from the `nq_alloc` HWRM command.
43388 uint16_t cmpl_ring;
43390 * The sequence ID is used by the driver for tracking multiple
43391 * commands. This ID is treated as opaque data by the firmware and
43392 * the value is returned in the `hwrm_resp_hdr` upon completion.
43396 * The target ID of the command:
43397 * * 0x0-0xFFF8 - The function ID
43398 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43399 * * 0xFFFD - Reserved for user-space HWRM interface
43402 uint16_t target_id;
43404 * A physical address pointer pointing to a host buffer that the
43405 * command's response data will be written. This can be either a host
43406 * physical address (HPA) or a guest physical address (GPA) and must
43407 * point to a physically contiguous block of memory.
43409 uint64_t resp_addr;
43410 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43411 uint32_t fw_session_id;
43412 /* Counter PBL indirect levels. */
43413 uint8_t page_level;
43414 /* PBL pointer is physical start address. */
43415 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43416 /* PBL pointer points to PTE table. */
43417 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43419 * PBL pointer points to PDE table with each entry pointing
43422 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43423 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LAST \
43424 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_LEVEL_LVL_2
43427 /* 4KB page size. */
43428 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
43429 /* 8KB page size. */
43430 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
43431 /* 64KB page size. */
43432 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
43433 /* 128KB page size. */
43434 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
43435 /* 256KB page size. */
43436 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
43437 /* 512KB page size. */
43438 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
43439 /* 1MB page size. */
43440 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
43441 /* 2MB page size. */
43442 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
43443 /* 4MB page size. */
43444 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
43445 /* 8MB page size. */
43446 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
43447 /* 1GB page size. */
43448 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
43449 #define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \
43450 HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G
43452 uint8_t unused0[2];
43453 /* Pointer to the PBL, or PDL depending on number of levels */
43455 /* Size of memory allocated. */
43458 uint8_t unused1[4];
43461 /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */
43462 struct hwrm_tf_ctxt_mem_free_output {
43463 /* The specific error status for the command. */
43464 uint16_t error_code;
43465 /* The HWRM command request type. */
43467 /* The sequence ID from the original command. */
43469 /* The length of the response data in number of bytes. */
43472 uint8_t unused0[7];
43474 * This field is used in Output records to indicate that the
43475 * output is completely written to RAM. This field should be
43476 * read as '1' to indicate that the output has been
43477 * completely written. When writing a command completion or
43478 * response to an internal processor, the order of writes has
43479 * to be such that this field is written last.
43484 /*************************
43485 * hwrm_tf_ctxt_mem_rgtr *
43486 *************************/
43489 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
43490 struct hwrm_tf_ctxt_mem_rgtr_input {
43491 /* The HWRM command request type. */
43494 * The completion ring to send the completion event on. This should
43495 * be the NQ ID returned from the `nq_alloc` HWRM command.
43497 uint16_t cmpl_ring;
43499 * The sequence ID is used by the driver for tracking multiple
43500 * commands. This ID is treated as opaque data by the firmware and
43501 * the value is returned in the `hwrm_resp_hdr` upon completion.
43505 * The target ID of the command:
43506 * * 0x0-0xFFF8 - The function ID
43507 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43508 * * 0xFFFD - Reserved for user-space HWRM interface
43511 uint16_t target_id;
43513 * A physical address pointer pointing to a host buffer that the
43514 * command's response data will be written. This can be either a host
43515 * physical address (HPA) or a guest physical address (GPA) and must
43516 * point to a physically contiguous block of memory.
43518 uint64_t resp_addr;
43519 /* Control flags. */
43521 /* Counter PBL indirect levels. */
43522 uint8_t page_level;
43523 /* PBL pointer is physical start address. */
43524 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
43525 /* PBL pointer points to PTE table. */
43526 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
43528 * PBL pointer points to PDE table with each entry pointing
43531 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
43532 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
43533 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
43536 /* 4KB page size. */
43537 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
43538 /* 8KB page size. */
43539 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
43540 /* 64KB page size. */
43541 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
43542 /* 128KB page size. */
43543 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_128K UINT32_C(0x5)
43544 /* 256KB page size. */
43545 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
43546 /* 512KB page size. */
43547 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_512K UINT32_C(0x7)
43548 /* 1MB page size. */
43549 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
43550 /* 2MB page size. */
43551 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
43552 /* 4MB page size. */
43553 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
43554 /* 8MB page size. */
43555 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8M UINT32_C(0xb)
43556 /* 1GB page size. */
43557 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
43558 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
43559 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
43560 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43561 uint32_t fw_session_id;
43562 /* Pointer to the PBL, or PDL depending on number of levels */
43566 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
43567 struct hwrm_tf_ctxt_mem_rgtr_output {
43568 /* The specific error status for the command. */
43569 uint16_t error_code;
43570 /* The HWRM command request type. */
43572 /* The sequence ID from the original command. */
43574 /* The length of the response data in number of bytes. */
43577 * Id/Handle to the recently register context memory. This
43578 * handle is passed to the TF session.
43582 uint8_t unused0[5];
43584 * This field is used in Output records to indicate that the
43585 * output is completely written to RAM. This field should be
43586 * read as '1' to indicate that the output has been
43587 * completely written. When writing a command completion or
43588 * response to an internal processor, the order of writes has
43589 * to be such that this field is written last.
43594 /***************************
43595 * hwrm_tf_ctxt_mem_unrgtr *
43596 ***************************/
43599 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
43600 struct hwrm_tf_ctxt_mem_unrgtr_input {
43601 /* The HWRM command request type. */
43604 * The completion ring to send the completion event on. This should
43605 * be the NQ ID returned from the `nq_alloc` HWRM command.
43607 uint16_t cmpl_ring;
43609 * The sequence ID is used by the driver for tracking multiple
43610 * commands. This ID is treated as opaque data by the firmware and
43611 * the value is returned in the `hwrm_resp_hdr` upon completion.
43615 * The target ID of the command:
43616 * * 0x0-0xFFF8 - The function ID
43617 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43618 * * 0xFFFD - Reserved for user-space HWRM interface
43621 uint16_t target_id;
43623 * A physical address pointer pointing to a host buffer that the
43624 * command's response data will be written. This can be either a host
43625 * physical address (HPA) or a guest physical address (GPA) and must
43626 * point to a physically contiguous block of memory.
43628 uint64_t resp_addr;
43630 * Id/Handle to the recently register context memory. This
43631 * handle is passed to the TF session.
43635 uint8_t unused0[2];
43636 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43637 uint32_t fw_session_id;
43640 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
43641 struct hwrm_tf_ctxt_mem_unrgtr_output {
43642 /* The specific error status for the command. */
43643 uint16_t error_code;
43644 /* The HWRM command request type. */
43646 /* The sequence ID from the original command. */
43648 /* The length of the response data in number of bytes. */
43651 uint8_t unused0[7];
43653 * This field is used in Output records to indicate that the
43654 * output is completely written to RAM. This field should be
43655 * read as '1' to indicate that the output has been
43656 * completely written. When writing a command completion or
43657 * response to an internal processor, the order of writes has
43658 * to be such that this field is written last.
43663 /************************
43664 * hwrm_tf_ext_em_qcaps *
43665 ************************/
43668 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
43669 struct hwrm_tf_ext_em_qcaps_input {
43670 /* The HWRM command request type. */
43673 * The completion ring to send the completion event on. This should
43674 * be the NQ ID returned from the `nq_alloc` HWRM command.
43676 uint16_t cmpl_ring;
43678 * The sequence ID is used by the driver for tracking multiple
43679 * commands. This ID is treated as opaque data by the firmware and
43680 * the value is returned in the `hwrm_resp_hdr` upon completion.
43684 * The target ID of the command:
43685 * * 0x0-0xFFF8 - The function ID
43686 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43687 * * 0xFFFD - Reserved for user-space HWRM interface
43690 uint16_t target_id;
43692 * A physical address pointer pointing to a host buffer that the
43693 * command's response data will be written. This can be either a host
43694 * physical address (HPA) or a guest physical address (GPA) and must
43695 * point to a physically contiguous block of memory.
43697 uint64_t resp_addr;
43698 /* Control flags. */
43700 /* Indicates the flow direction. */
43701 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
43703 /* If this bit set to 0, then it indicates rx flow. */
43704 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
43706 /* If this bit is set to 1, then it indicates that tx flow. */
43707 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
43709 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
43710 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
43711 /* When set to 1, all offloaded flows will be sent to EXT EM. */
43712 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
43714 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43715 uint32_t fw_session_id;
43718 /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */
43719 struct hwrm_tf_ext_em_qcaps_output {
43720 /* The specific error status for the command. */
43721 uint16_t error_code;
43722 /* The HWRM command request type. */
43724 /* The sequence ID from the original command. */
43726 /* The length of the response data in number of bytes. */
43730 * When set to 1, indicates the FW supports the Centralized
43731 * Memory Model. The concept designates one entity for the
43732 * memory allocation while all others ‘subscribe’ to it.
43734 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
43737 * When set to 1, indicates the FW supports the Detached
43738 * Centralized Memory Model. The memory is allocated and managed
43739 * as a separate entity. All PFs and VFs will be granted direct
43740 * or semi-direct access to the allocated memory while none of
43741 * which can interfere with the management of the memory.
43743 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
43745 /* When set to 1, indicates FW support for host based EEM memory. */
43746 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_HOST_MEMORY_SUPPORTED \
43748 /* When set to 1, indicates FW support for on-chip based EEM memory. */
43749 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_FW_MEMORY_SUPPORTED \
43753 /* Support flags. */
43754 uint32_t supported;
43756 * If set to 1, then EXT EM KEY0 table is supported using
43758 * If set to 0, EXT EM KEY0 table is not supported.
43760 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
43763 * If set to 1, then EXT EM KEY1 table is supported using
43765 * If set to 0, EXT EM KEY1 table is not supported.
43767 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
43770 * If set to 1, then EXT EM External Record table is supported.
43771 * If set to 0, EXT EM External Record table is not
43772 * supported. (This table includes action record, EFC
43773 * pointers, encap pointers)
43775 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
43778 * If set to 1, then EXT EM External Flow Counters table is
43780 * If set to 0, EXT EM External Flow Counters table is not
43783 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
43786 * If set to 1, then FID table used for implicit flow flush
43788 * If set to 0, then FID table used for implicit flow flush
43789 * is not supported.
43791 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
43794 * If set to 1, then table scopes are supported.
43795 * If set to 0, then table scopes are not supported.
43797 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_TBL_SCOPES \
43800 * The maximum number of entries supported by EXT EM. When
43801 * configuring the host memory the number of numbers of
43802 * entries that can supported are -
43803 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
43805 * Any value that are not these values, the FW will round
43806 * down to the closest support number of entries.
43808 uint32_t max_entries_supported;
43810 * The entry size in bytes of each entry in the EXT EM
43811 * KEY0/KEY1 tables.
43813 uint16_t key_entry_size;
43815 * The entry size in bytes of each entry in the EXT EM RECORD
43818 uint16_t record_entry_size;
43819 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
43820 uint16_t efc_entry_size;
43821 /* The FID size in bytes of each entry in the EXT EM FID tables. */
43822 uint16_t fid_entry_size;
43823 /* Maximum number of ctxt mem allocations allowed. */
43824 uint32_t max_ctxt_mem_allocs;
43826 * Maximum number of static buckets that can be assigned to lookup
43829 uint32_t max_static_buckets;
43831 uint8_t unused1[7];
43833 * This field is used in Output records to indicate that the
43834 * output is completely written to RAM. This field should be
43835 * read as '1' to indicate that the output has been
43836 * completely written. When writing a command completion or
43837 * response to an internal processor, the order of writes has
43838 * to be such that this field is written last.
43843 /*********************
43844 * hwrm_tf_ext_em_op *
43845 *********************/
43848 /* hwrm_tf_ext_em_op_input (size:256b/32B) */
43849 struct hwrm_tf_ext_em_op_input {
43850 /* The HWRM command request type. */
43853 * The completion ring to send the completion event on. This should
43854 * be the NQ ID returned from the `nq_alloc` HWRM command.
43856 uint16_t cmpl_ring;
43858 * The sequence ID is used by the driver for tracking multiple
43859 * commands. This ID is treated as opaque data by the firmware and
43860 * the value is returned in the `hwrm_resp_hdr` upon completion.
43864 * The target ID of the command:
43865 * * 0x0-0xFFF8 - The function ID
43866 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43867 * * 0xFFFD - Reserved for user-space HWRM interface
43870 uint16_t target_id;
43872 * A physical address pointer pointing to a host buffer that the
43873 * command's response data will be written. This can be either a host
43874 * physical address (HPA) or a guest physical address (GPA) and must
43875 * point to a physically contiguous block of memory.
43877 uint64_t resp_addr;
43878 /* Control flags. */
43880 /* Indicates the flow direction. */
43881 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
43882 /* If this bit set to 0, then it indicates rx flow. */
43883 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
43884 /* If this bit is set to 1, then it indicates that tx flow. */
43885 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
43886 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
43887 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
43890 /* The number of EXT EM key table entries to be configured. */
43892 /* This value is reserved and should not be used. */
43893 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
43895 * To properly stop EXT EM and ensure there are no DMA's,
43896 * the caller must disable EXT EM for the given PF, using
43897 * this call. This will safely disable EXT EM and ensure
43898 * that all DMA'ed to the keys/records/efc have been
43901 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
43903 * Once the EXT EM host memory has been configured, EXT EM
43904 * options have been configured. Then the caller should
43905 * enable EXT EM for the given PF. Note once this call has
43906 * been made, then the EXT EM mechanism will be active and
43907 * DMA's will occur as packets are processed.
43909 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
43911 * Clear EXT EM settings for the given PF so that the
43912 * register values are reset back to their initial state.
43914 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
43915 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
43916 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
43919 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
43920 uint32_t fw_session_id;
43925 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
43926 struct hwrm_tf_ext_em_op_output {
43927 /* The specific error status for the command. */
43928 uint16_t error_code;
43929 /* The HWRM command request type. */
43931 /* The sequence ID from the original command. */
43933 /* The length of the response data in number of bytes. */
43936 uint8_t unused0[7];
43938 * This field is used in Output records to indicate that the
43939 * output is completely written to RAM. This field should be
43940 * read as '1' to indicate that the output has been
43941 * completely written. When writing a command completion or
43942 * response to an internal processor, the order of writes has
43943 * to be such that this field is written last.
43948 /**********************
43949 * hwrm_tf_ext_em_cfg *
43950 **********************/
43953 /* hwrm_tf_ext_em_cfg_input (size:512b/64B) */
43954 struct hwrm_tf_ext_em_cfg_input {
43955 /* The HWRM command request type. */
43958 * The completion ring to send the completion event on. This should
43959 * be the NQ ID returned from the `nq_alloc` HWRM command.
43961 uint16_t cmpl_ring;
43963 * The sequence ID is used by the driver for tracking multiple
43964 * commands. This ID is treated as opaque data by the firmware and
43965 * the value is returned in the `hwrm_resp_hdr` upon completion.
43969 * The target ID of the command:
43970 * * 0x0-0xFFF8 - The function ID
43971 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43972 * * 0xFFFD - Reserved for user-space HWRM interface
43975 uint16_t target_id;
43977 * A physical address pointer pointing to a host buffer that the
43978 * command's response data will be written. This can be either a host
43979 * physical address (HPA) or a guest physical address (GPA) and must
43980 * point to a physically contiguous block of memory.
43982 uint64_t resp_addr;
43983 /* Control flags. */
43985 /* Indicates the flow direction. */
43986 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
43988 /* If this bit set to 0, then it indicates rx flow. */
43989 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
43991 /* If this bit is set to 1, then it indicates that tx flow. */
43992 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
43994 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
43995 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
43996 /* When set to 1, all offloaded flows will be sent to EXT EM. */
43997 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
43999 /* When set to 1, secondary, 0 means primary. */
44000 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
44003 * Group_id which used by Firmware to identify memory pools belonging
44004 * to certain group.
44008 * Dynamically reconfigure EEM pending cache every 1/10th of second.
44009 * If set to 0 it will disable the EEM HW flush of the pending cache.
44011 uint8_t flush_interval;
44015 * Configured EXT EM with the given number of entries. All
44016 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
44017 * same number of entries and all tables will be configured
44018 * using this value. Current minimum value is 32k. Current
44019 * maximum value is 128M.
44021 uint32_t num_entries;
44024 * This bit must be '1' for the group_id field to be
44027 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_GROUP_ID \
44030 * This bit must be '1' for the flush_interval field to be
44033 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FLUSH_INTERVAL \
44036 * This bit must be '1' for the num_entries field to be
44039 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_NUM_ENTRIES \
44042 * This bit must be '1' for the key0_ctx_id field to be
44045 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY0_CTX_ID \
44048 * This bit must be '1' for the key1_ctx_id field to be
44051 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_KEY1_CTX_ID \
44054 * This bit must be '1' for the record_ctx_id field to be
44057 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_RECORD_CTX_ID \
44060 * This bit must be '1' for the efc_ctx_id field to be
44063 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_EFC_CTX_ID \
44066 * This bit must be '1' for the fid_ctx_id field to be
44069 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_FID_CTX_ID \
44072 * This bit must be '1' for the action_ctx_id field to be
44075 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_CTX_ID \
44078 * This bit must be '1' for the action_tbl_scope field to be
44081 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_ACTION_TBL_SCOPE \
44084 * This bit must be '1' for the lkup_ctx_id field to be
44087 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_CTX_ID \
44090 * This bit must be '1' for the lkup_tbl_scope field to be
44093 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_TBL_SCOPE \
44096 * This bit must be '1' for the lkup_static_buckets field to be
44099 #define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \
44101 /* Configured EXT EM with the given context if for KEY0 table. */
44102 uint16_t key0_ctx_id;
44103 /* Configured EXT EM with the given context if for KEY1 table. */
44104 uint16_t key1_ctx_id;
44105 /* Configured EXT EM with the given context if for RECORD table. */
44106 uint16_t record_ctx_id;
44107 /* Configured EXT EM with the given context if for EFC table. */
44108 uint16_t efc_ctx_id;
44109 /* Configured EXT EM with the given context if for EFC table. */
44110 uint16_t fid_ctx_id;
44111 /* Context id of action table scope. */
44112 uint16_t action_ctx_id;
44113 /* Table scope id used for action record entries. */
44114 uint16_t action_tbl_scope;
44115 /* Context id of lookup table scope. */
44116 uint16_t lkup_ctx_id;
44117 /* Table scope id used for EM lookup entries. */
44118 uint16_t lkup_tbl_scope;
44122 * Number of 32B static buckets to be allocated at the beginning
44125 uint32_t lkup_static_buckets;
44126 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44127 uint32_t fw_session_id;
44132 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
44133 struct hwrm_tf_ext_em_cfg_output {
44134 /* The specific error status for the command. */
44135 uint16_t error_code;
44136 /* The HWRM command request type. */
44138 /* The sequence ID from the original command. */
44140 /* The length of the response data in number of bytes. */
44143 uint8_t unused0[7];
44145 * This field is used in Output records to indicate that the
44146 * output is completely written to RAM. This field should be
44147 * read as '1' to indicate that the output has been
44148 * completely written. When writing a command completion or
44149 * response to an internal processor, the order of writes has
44150 * to be such that this field is written last.
44155 /***********************
44156 * hwrm_tf_ext_em_qcfg *
44157 ***********************/
44160 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
44161 struct hwrm_tf_ext_em_qcfg_input {
44162 /* The HWRM command request type. */
44165 * The completion ring to send the completion event on. This should
44166 * be the NQ ID returned from the `nq_alloc` HWRM command.
44168 uint16_t cmpl_ring;
44170 * The sequence ID is used by the driver for tracking multiple
44171 * commands. This ID is treated as opaque data by the firmware and
44172 * the value is returned in the `hwrm_resp_hdr` upon completion.
44176 * The target ID of the command:
44177 * * 0x0-0xFFF8 - The function ID
44178 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44179 * * 0xFFFD - Reserved for user-space HWRM interface
44182 uint16_t target_id;
44184 * A physical address pointer pointing to a host buffer that the
44185 * command's response data will be written. This can be either a host
44186 * physical address (HPA) or a guest physical address (GPA) and must
44187 * point to a physically contiguous block of memory.
44189 uint64_t resp_addr;
44190 /* Control flags. */
44192 /* Indicates the flow direction. */
44193 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
44194 /* If this bit set to 0, then it indicates rx flow. */
44195 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44196 /* If this bit is set to 1, then it indicates that tx flow. */
44197 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44198 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
44199 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
44200 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44201 uint32_t fw_session_id;
44204 /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */
44205 struct hwrm_tf_ext_em_qcfg_output {
44206 /* The specific error status for the command. */
44207 uint16_t error_code;
44208 /* The HWRM command request type. */
44210 /* The sequence ID from the original command. */
44212 /* The length of the response data in number of bytes. */
44214 /* Control flags. */
44216 /* Indicates the flow direction. */
44217 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
44219 /* If this bit set to 0, then it indicates rx flow. */
44220 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
44222 /* If this bit is set to 1, then it indicates that tx flow. */
44223 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
44225 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
44226 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
44227 /* When set to 1, all offloaded flows will be sent to EXT EM. */
44228 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
44230 /* The number of entries the FW has configured for EXT EM. */
44231 uint32_t num_entries;
44232 /* Configured EXT EM with the given context if for KEY0 table. */
44233 uint16_t key0_ctx_id;
44234 /* Configured EXT EM with the given context if for KEY1 table. */
44235 uint16_t key1_ctx_id;
44236 /* Configured EXT EM with the given context if for RECORD table. */
44237 uint16_t record_ctx_id;
44238 /* Configured EXT EM with the given context if for EFC table. */
44239 uint16_t efc_ctx_id;
44240 /* Configured EXT EM with the given context if for EFC table. */
44241 uint16_t fid_ctx_id;
44244 uint32_t supported;
44245 /* This bit must be '1' for the group_id field is set. */
44246 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_GROUP_ID \
44248 /* This bit must be '1' for the flush_interval field is set. */
44249 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FLUSH_INTERVAL \
44251 /* This bit must be '1' for the num_entries field is set. */
44252 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_NUM_ENTRIES \
44254 /* This bit must be '1' for the key0_ctx_id field is set. */
44255 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY0_CTX_ID \
44257 /* This bit must be '1' for the key1_ctx_id field is set. */
44258 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_KEY1_CTX_ID \
44260 /* This bit must be '1' for the record_ctx_id field is set. */
44261 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_RECORD_CTX_ID \
44263 /* This bit must be '1' for the efc_ctx_id field is set. */
44264 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_EFC_CTX_ID \
44266 /* This bit must be '1' for the fid_ctx_id field is set. */
44267 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_FID_CTX_ID \
44269 /* This bit must be '1' for the action_ctx_id field is set. */
44270 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_CTX_ID \
44272 /* This bit must be '1' for the action_tbl_scope field is set. */
44273 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_ACTION_TBL_SCOPE \
44275 /* This bit must be '1' for the lkup_ctx_id field is set. */
44276 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_CTX_ID \
44278 /* This bit must be '1' for the lkup_tbl_scope field is set. */
44279 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_TBL_SCOPE \
44281 /* This bit must be '1' for the lkup_static_buckets field is set. */
44282 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \
44285 * Group id is used by firmware to identify memory pools belonging
44286 * to certain group.
44289 /* EEM pending cache flush interval in 1/10th of second. */
44290 uint8_t flush_interval;
44293 /* Context id of action table scope. */
44294 uint16_t action_ctx_id;
44295 /* Table scope id used for action record entries. */
44296 uint16_t action_tbl_scope;
44297 /* Context id of lookup table scope. */
44298 uint16_t lkup_ctx_id;
44299 /* Table scope id used for EM lookup entries. */
44300 uint16_t lkup_tbl_scope;
44302 * Number of 32B static buckets to be allocated at the beginning
44305 uint32_t lkup_static_buckets;
44307 uint8_t unused2[7];
44309 * This field is used in Output records to indicate that the
44310 * output is completely written to RAM. This field should be
44311 * read as '1' to indicate that the output has been
44312 * completely written. When writing a command completion or
44313 * response to an internal processor, the order of writes has
44314 * to be such that this field is written last.
44319 /*********************
44320 * hwrm_tf_em_insert *
44321 *********************/
44324 /* hwrm_tf_em_insert_input (size:832b/104B) */
44325 struct hwrm_tf_em_insert_input {
44326 /* The HWRM command request type. */
44329 * The completion ring to send the completion event on. This should
44330 * be the NQ ID returned from the `nq_alloc` HWRM command.
44332 uint16_t cmpl_ring;
44334 * The sequence ID is used by the driver for tracking multiple
44335 * commands. This ID is treated as opaque data by the firmware and
44336 * the value is returned in the `hwrm_resp_hdr` upon completion.
44340 * The target ID of the command:
44341 * * 0x0-0xFFF8 - The function ID
44342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44343 * * 0xFFFD - Reserved for user-space HWRM interface
44346 uint16_t target_id;
44348 * A physical address pointer pointing to a host buffer that the
44349 * command's response data will be written. This can be either a host
44350 * physical address (HPA) or a guest physical address (GPA) and must
44351 * point to a physically contiguous block of memory.
44353 uint64_t resp_addr;
44354 /* Firmware Session Id. */
44355 uint32_t fw_session_id;
44356 /* Control Flags. */
44358 /* Indicates the flow direction. */
44359 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
44360 /* If this bit set to 0, then it indicates rx flow. */
44361 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44362 /* If this bit is set to 1, then it indicates that tx flow. */
44363 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44364 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
44365 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
44366 /* Reported match strength. */
44368 /* Index to action. */
44369 uint32_t action_ptr;
44370 /* Index of EM record. */
44371 uint32_t em_record_idx;
44372 /* EM Key value. */
44373 uint64_t em_key[8];
44374 /* Number of bits in em_key. */
44375 uint16_t em_key_bitlen;
44377 uint16_t unused0[3];
44380 /* hwrm_tf_em_insert_output (size:128b/16B) */
44381 struct hwrm_tf_em_insert_output {
44382 /* The specific error status for the command. */
44383 uint16_t error_code;
44384 /* The HWRM command request type. */
44386 /* The sequence ID from the original command. */
44388 /* The length of the response data in number of bytes. */
44390 /* EM record pointer index. */
44391 uint16_t rptr_index;
44392 /* EM record offset 0~3. */
44393 uint8_t rptr_entry;
44394 /* Number of word entries consumed by the key. */
44395 uint8_t num_of_entries;
44400 /**************************
44401 * hwrm_tf_em_hash_insert *
44402 **************************/
44405 /* hwrm_tf_em_hash_insert_input (size:1024b/128B) */
44406 struct hwrm_tf_em_hash_insert_input {
44407 /* The HWRM command request type. */
44410 * The completion ring to send the completion event on. This should
44411 * be the NQ ID returned from the `nq_alloc` HWRM command.
44413 uint16_t cmpl_ring;
44415 * The sequence ID is used by the driver for tracking multiple
44416 * commands. This ID is treated as opaque data by the firmware and
44417 * the value is returned in the `hwrm_resp_hdr` upon completion.
44421 * The target ID of the command:
44422 * * 0x0-0xFFF8 - The function ID
44423 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44424 * * 0xFFFD - Reserved for user-space HWRM interface
44427 uint16_t target_id;
44429 * A physical address pointer pointing to a host buffer that the
44430 * command's response data will be written. This can be either a host
44431 * physical address (HPA) or a guest physical address (GPA) and must
44432 * point to a physically contiguous block of memory.
44434 uint64_t resp_addr;
44435 /* Firmware Session Id. */
44436 uint32_t fw_session_id;
44437 /* Control Flags. */
44439 /* Indicates the flow direction. */
44440 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
44441 /* If this bit set to 0, then it indicates rx flow. */
44442 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44443 /* If this bit is set to 1, then it indicates that tx flow. */
44444 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44445 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \
44446 HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX
44447 /* Number of bits in the EM record. */
44448 uint16_t em_record_size_bits;
44449 /* CRC32 hash of key. */
44450 uint32_t key0_hash;
44451 /* Lookup3 hash of key. */
44452 uint32_t key1_hash;
44453 /* Index of EM record. */
44454 uint32_t em_record_idx;
44458 uint64_t em_record[11];
44461 /* hwrm_tf_em_hash_insert_output (size:128b/16B) */
44462 struct hwrm_tf_em_hash_insert_output {
44463 /* The specific error status for the command. */
44464 uint16_t error_code;
44465 /* The HWRM command request type. */
44467 /* The sequence ID from the original command. */
44469 /* The length of the response data in number of bytes. */
44471 /* EM record pointer index. */
44472 uint16_t rptr_index;
44473 /* EM record offset 0~3. */
44474 uint8_t rptr_entry;
44475 /* Number of word entries consumed by the key. */
44476 uint8_t num_of_entries;
44481 /*********************
44482 * hwrm_tf_em_delete *
44483 *********************/
44486 /* hwrm_tf_em_delete_input (size:832b/104B) */
44487 struct hwrm_tf_em_delete_input {
44488 /* The HWRM command request type. */
44491 * The completion ring to send the completion event on. This should
44492 * be the NQ ID returned from the `nq_alloc` HWRM command.
44494 uint16_t cmpl_ring;
44496 * The sequence ID is used by the driver for tracking multiple
44497 * commands. This ID is treated as opaque data by the firmware and
44498 * the value is returned in the `hwrm_resp_hdr` upon completion.
44502 * The target ID of the command:
44503 * * 0x0-0xFFF8 - The function ID
44504 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44505 * * 0xFFFD - Reserved for user-space HWRM interface
44508 uint16_t target_id;
44510 * A physical address pointer pointing to a host buffer that the
44511 * command's response data will be written. This can be either a host
44512 * physical address (HPA) or a guest physical address (GPA) and must
44513 * point to a physically contiguous block of memory.
44515 uint64_t resp_addr;
44517 uint32_t fw_session_id;
44518 /* Control flags. */
44520 /* Indicates the flow direction. */
44521 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
44522 /* If this bit set to 0, then it indicates rx flow. */
44523 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44524 /* If this bit is set to 1, then it indicates that tx flow. */
44525 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44526 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
44527 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
44530 /* EM internal flow hanndle. */
44531 uint64_t flow_handle;
44533 uint64_t em_key[8];
44534 /* Number of bits in em_key. */
44535 uint16_t em_key_bitlen;
44537 uint16_t unused1[3];
44540 /* hwrm_tf_em_delete_output (size:128b/16B) */
44541 struct hwrm_tf_em_delete_output {
44542 /* The specific error status for the command. */
44543 uint16_t error_code;
44544 /* The HWRM command request type. */
44546 /* The sequence ID from the original command. */
44548 /* The length of the response data in number of bytes. */
44550 /* Original stack allocation index. */
44553 uint16_t unused0[3];
44556 /*******************
44557 * hwrm_tf_em_move *
44558 *******************/
44561 /* hwrm_tf_em_move_input (size:320b/40B) */
44562 struct hwrm_tf_em_move_input {
44563 /* The HWRM command request type. */
44566 * The completion ring to send the completion event on. This should
44567 * be the NQ ID returned from the `nq_alloc` HWRM command.
44569 uint16_t cmpl_ring;
44571 * The sequence ID is used by the driver for tracking multiple
44572 * commands. This ID is treated as opaque data by the firmware and
44573 * the value is returned in the `hwrm_resp_hdr` upon completion.
44577 * The target ID of the command:
44578 * * 0x0-0xFFF8 - The function ID
44579 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44580 * * 0xFFFD - Reserved for user-space HWRM interface
44583 uint16_t target_id;
44585 * A physical address pointer pointing to a host buffer that the
44586 * command's response data will be written. This can be either a host
44587 * physical address (HPA) or a guest physical address (GPA) and must
44588 * point to a physically contiguous block of memory.
44590 uint64_t resp_addr;
44592 uint32_t fw_session_id;
44593 /* Control flags. */
44595 /* Indicates the flow direction. */
44596 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
44597 /* If this bit set to 0, then it indicates rx flow. */
44598 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44599 /* If this bit is set to 1, then it indicates tx flow. */
44600 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44601 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_LAST \
44602 HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX
44603 /* Number of EM entry blocks */
44604 uint16_t num_blocks;
44605 /* New index for entry */
44606 uint32_t new_index;
44609 /* EM internal flow handle. */
44610 uint64_t flow_handle;
44613 /* hwrm_tf_em_move_output (size:128b/16B) */
44614 struct hwrm_tf_em_move_output {
44615 /* The specific error status for the command. */
44616 uint16_t error_code;
44617 /* The HWRM command request type. */
44619 /* The sequence ID from the original command. */
44621 /* The length of the response data in number of bytes. */
44623 /* Index of old entry. */
44626 uint16_t unused0[3];
44629 /********************
44630 * hwrm_tf_tcam_set *
44631 ********************/
44634 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
44635 struct hwrm_tf_tcam_set_input {
44636 /* The HWRM command request type. */
44639 * The completion ring to send the completion event on. This should
44640 * be the NQ ID returned from the `nq_alloc` HWRM command.
44642 uint16_t cmpl_ring;
44644 * The sequence ID is used by the driver for tracking multiple
44645 * commands. This ID is treated as opaque data by the firmware and
44646 * the value is returned in the `hwrm_resp_hdr` upon completion.
44650 * The target ID of the command:
44651 * * 0x0-0xFFF8 - The function ID
44652 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44653 * * 0xFFFD - Reserved for user-space HWRM interface
44656 uint16_t target_id;
44658 * A physical address pointer pointing to a host buffer that the
44659 * command's response data will be written. This can be either a host
44660 * physical address (HPA) or a guest physical address (GPA) and must
44661 * point to a physically contiguous block of memory.
44663 uint64_t resp_addr;
44664 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44665 uint32_t fw_session_id;
44666 /* Control flags. */
44668 /* Indicates the flow direction. */
44669 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
44670 /* If this bit set to 0, then it indicates rx flow. */
44671 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44672 /* If this bit is set to 1, then it indicates that tx flow. */
44673 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44674 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
44675 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
44677 * Indicate device data is being sent via DMA, the device
44678 * data is packing does not change.
44680 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
44682 * TCAM type of the resource, defined globally in the
44683 * hwrm_tf_resc_type enum.
44686 /* Index of TCAM entry. */
44688 /* Number of bytes in the TCAM key. */
44690 /* Number of bytes in the TCAM result. */
44691 uint8_t result_size;
44693 * Offset from which the mask bytes start in the device data
44694 * array, key offset is always 0.
44696 uint8_t mask_offset;
44697 /* Offset from which the result bytes start in the device data array. */
44698 uint8_t result_offset;
44700 uint8_t unused0[6];
44702 * TCAM key located at offset 0, mask located at mask_offsec
44703 * and result at result_offsec for the device.
44705 uint8_t dev_data[88];
44708 /* hwrm_tf_tcam_set_output (size:128b/16B) */
44709 struct hwrm_tf_tcam_set_output {
44710 /* The specific error status for the command. */
44711 uint16_t error_code;
44712 /* The HWRM command request type. */
44714 /* The sequence ID from the original command. */
44716 /* The length of the response data in number of bytes. */
44719 uint8_t unused0[7];
44721 * This field is used in Output records to indicate that the
44722 * output is completely written to RAM. This field should be
44723 * read as '1' to indicate that the output has been
44724 * completely written. When writing a command completion or
44725 * response to an internal processor, the order of writes has
44726 * to be such that this field is written last.
44731 /********************
44732 * hwrm_tf_tcam_get *
44733 ********************/
44736 /* hwrm_tf_tcam_get_input (size:256b/32B) */
44737 struct hwrm_tf_tcam_get_input {
44738 /* The HWRM command request type. */
44741 * The completion ring to send the completion event on. This should
44742 * be the NQ ID returned from the `nq_alloc` HWRM command.
44744 uint16_t cmpl_ring;
44746 * The sequence ID is used by the driver for tracking multiple
44747 * commands. This ID is treated as opaque data by the firmware and
44748 * the value is returned in the `hwrm_resp_hdr` upon completion.
44752 * The target ID of the command:
44753 * * 0x0-0xFFF8 - The function ID
44754 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44755 * * 0xFFFD - Reserved for user-space HWRM interface
44758 uint16_t target_id;
44760 * A physical address pointer pointing to a host buffer that the
44761 * command's response data will be written. This can be either a host
44762 * physical address (HPA) or a guest physical address (GPA) and must
44763 * point to a physically contiguous block of memory.
44765 uint64_t resp_addr;
44766 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44767 uint32_t fw_session_id;
44768 /* Control flags. */
44770 /* Indicates the flow direction. */
44771 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
44772 /* If this bit set to 0, then it indicates rx flow. */
44773 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44774 /* If this bit is set to 1, then it indicates that tx flow. */
44775 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44776 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
44777 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
44779 * TCAM type of the resource, defined globally in the
44780 * hwrm_tf_resc_type enum.
44783 /* Index of a TCAM entry. */
44789 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
44790 struct hwrm_tf_tcam_get_output {
44791 /* The specific error status for the command. */
44792 uint16_t error_code;
44793 /* The HWRM command request type. */
44795 /* The sequence ID from the original command. */
44797 /* The length of the response data in number of bytes. */
44799 /* Number of bytes in the TCAM key. */
44801 /* Number of bytes in the TCAM entry. */
44802 uint8_t result_size;
44803 /* Offset from which the mask bytes start in the device data array. */
44804 uint8_t mask_offset;
44805 /* Offset from which the result bytes start in the device data array. */
44806 uint8_t result_offset;
44808 uint8_t unused0[4];
44810 * TCAM key located at offset 0, mask located at mask_offsec
44811 * and result at result_offsec for the device.
44813 uint8_t dev_data[272];
44815 uint8_t unused1[7];
44817 * This field is used in Output records to indicate that the
44818 * output is completely written to RAM. This field should be
44819 * read as '1' to indicate that the output has been
44820 * completely written. When writing a command completion or
44821 * response to an internal processor, the order of writes has
44822 * to be such that this field is written last.
44827 /*********************
44828 * hwrm_tf_tcam_move *
44829 *********************/
44832 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
44833 struct hwrm_tf_tcam_move_input {
44834 /* The HWRM command request type. */
44837 * The completion ring to send the completion event on. This should
44838 * be the NQ ID returned from the `nq_alloc` HWRM command.
44840 uint16_t cmpl_ring;
44842 * The sequence ID is used by the driver for tracking multiple
44843 * commands. This ID is treated as opaque data by the firmware and
44844 * the value is returned in the `hwrm_resp_hdr` upon completion.
44848 * The target ID of the command:
44849 * * 0x0-0xFFF8 - The function ID
44850 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44851 * * 0xFFFD - Reserved for user-space HWRM interface
44854 uint16_t target_id;
44856 * A physical address pointer pointing to a host buffer that the
44857 * command's response data will be written. This can be either a host
44858 * physical address (HPA) or a guest physical address (GPA) and must
44859 * point to a physically contiguous block of memory.
44861 uint64_t resp_addr;
44862 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44863 uint32_t fw_session_id;
44864 /* Control flags. */
44866 /* Indicates the flow direction. */
44867 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
44868 /* If this bit set to 0, then it indicates rx flow. */
44869 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44870 /* If this bit is set to 1, then it indicates that tx flow. */
44871 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44872 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
44873 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
44875 * TCAM type of the resource, defined globally in the
44876 * hwrm_tf_resc_type enum.
44879 /* Number of TCAM index pairs to be swapped for the device. */
44883 /* TCAM index pairs to be swapped for the device. */
44884 uint16_t idx_pairs[48];
44887 /* hwrm_tf_tcam_move_output (size:128b/16B) */
44888 struct hwrm_tf_tcam_move_output {
44889 /* The specific error status for the command. */
44890 uint16_t error_code;
44891 /* The HWRM command request type. */
44893 /* The sequence ID from the original command. */
44895 /* The length of the response data in number of bytes. */
44898 uint8_t unused0[7];
44900 * This field is used in Output records to indicate that the
44901 * output is completely written to RAM. This field should be
44902 * read as '1' to indicate that the output has been
44903 * completely written. When writing a command completion or
44904 * response to an internal processor, the order of writes has
44905 * to be such that this field is written last.
44910 /*********************
44911 * hwrm_tf_tcam_free *
44912 *********************/
44915 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
44916 struct hwrm_tf_tcam_free_input {
44917 /* The HWRM command request type. */
44920 * The completion ring to send the completion event on. This should
44921 * be the NQ ID returned from the `nq_alloc` HWRM command.
44923 uint16_t cmpl_ring;
44925 * The sequence ID is used by the driver for tracking multiple
44926 * commands. This ID is treated as opaque data by the firmware and
44927 * the value is returned in the `hwrm_resp_hdr` upon completion.
44931 * The target ID of the command:
44932 * * 0x0-0xFFF8 - The function ID
44933 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44934 * * 0xFFFD - Reserved for user-space HWRM interface
44937 uint16_t target_id;
44939 * A physical address pointer pointing to a host buffer that the
44940 * command's response data will be written. This can be either a host
44941 * physical address (HPA) or a guest physical address (GPA) and must
44942 * point to a physically contiguous block of memory.
44944 uint64_t resp_addr;
44945 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
44946 uint32_t fw_session_id;
44947 /* Control flags. */
44949 /* Indicates the flow direction. */
44950 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
44951 /* If this bit set to 0, then it indicates rx flow. */
44952 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
44953 /* If this bit is set to 1, then it indicates that tx flow. */
44954 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
44955 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
44956 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
44958 * TCAM type of the resource, defined globally in the
44959 * hwrm_tf_resc_type enum.
44962 /* Number of TCAM index to be deleted for the device. */
44966 /* TCAM index list to be deleted for the device. */
44967 uint16_t idx_list[48];
44970 /* hwrm_tf_tcam_free_output (size:128b/16B) */
44971 struct hwrm_tf_tcam_free_output {
44972 /* The specific error status for the command. */
44973 uint16_t error_code;
44974 /* The HWRM command request type. */
44976 /* The sequence ID from the original command. */
44978 /* The length of the response data in number of bytes. */
44981 uint8_t unused0[7];
44983 * This field is used in Output records to indicate that the
44984 * output is completely written to RAM. This field should be
44985 * read as '1' to indicate that the output has been
44986 * completely written. When writing a command completion or
44987 * response to an internal processor, the order of writes has
44988 * to be such that this field is written last.
44993 /**************************
44994 * hwrm_tf_global_cfg_set *
44995 **************************/
44998 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
44999 struct hwrm_tf_global_cfg_set_input {
45000 /* The HWRM command request type. */
45003 * The completion ring to send the completion event on. This should
45004 * be the NQ ID returned from the `nq_alloc` HWRM command.
45006 uint16_t cmpl_ring;
45008 * The sequence ID is used by the driver for tracking multiple
45009 * commands. This ID is treated as opaque data by the firmware and
45010 * the value is returned in the `hwrm_resp_hdr` upon completion.
45014 * The target ID of the command:
45015 * * 0x0-0xFFF8 - The function ID
45016 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45017 * * 0xFFFD - Reserved for user-space HWRM interface
45020 uint16_t target_id;
45022 * A physical address pointer pointing to a host buffer that the
45023 * command's response data will be written. This can be either a host
45024 * physical address (HPA) or a guest physical address (GPA) and must
45025 * point to a physically contiguous block of memory.
45027 uint64_t resp_addr;
45028 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45029 uint32_t fw_session_id;
45030 /* Control flags. */
45032 /* Indicates the flow direction. */
45033 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
45034 /* If this bit set to 0, then it indicates rx flow. */
45035 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45036 /* If this bit is set to 1, then it indicates that tx flow. */
45037 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45038 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
45039 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
45040 /* Global Cfg type */
45042 /* Offset of the type */
45044 /* Size of the data to set in bytes */
45047 uint8_t unused0[6];
45050 /* Mask of data to set, 0 indicates no mask */
45054 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
45055 struct hwrm_tf_global_cfg_set_output {
45056 /* The specific error status for the command. */
45057 uint16_t error_code;
45058 /* The HWRM command request type. */
45060 /* The sequence ID from the original command. */
45062 /* The length of the response data in number of bytes. */
45065 uint8_t unused0[7];
45067 * This field is used in Output records to indicate that the
45068 * output is completely written to RAM. This field should be
45069 * read as '1' to indicate that the output has been
45070 * completely written. When writing a command completion or
45071 * response to an internal processor, the order of writes has
45072 * to be such that this field is written last.
45077 /**************************
45078 * hwrm_tf_global_cfg_get *
45079 **************************/
45082 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
45083 struct hwrm_tf_global_cfg_get_input {
45084 /* The HWRM command request type. */
45087 * The completion ring to send the completion event on. This should
45088 * be the NQ ID returned from the `nq_alloc` HWRM command.
45090 uint16_t cmpl_ring;
45092 * The sequence ID is used by the driver for tracking multiple
45093 * commands. This ID is treated as opaque data by the firmware and
45094 * the value is returned in the `hwrm_resp_hdr` upon completion.
45098 * The target ID of the command:
45099 * * 0x0-0xFFF8 - The function ID
45100 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45101 * * 0xFFFD - Reserved for user-space HWRM interface
45104 uint16_t target_id;
45106 * A physical address pointer pointing to a host buffer that the
45107 * command's response data will be written. This can be either a host
45108 * physical address (HPA) or a guest physical address (GPA) and must
45109 * point to a physically contiguous block of memory.
45111 uint64_t resp_addr;
45112 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45113 uint32_t fw_session_id;
45114 /* Control flags. */
45116 /* Indicates the flow direction. */
45117 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45118 /* If this bit set to 0, then it indicates rx flow. */
45119 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45120 /* If this bit is set to 1, then it indicates that tx flow. */
45121 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45122 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
45123 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
45124 /* Global Cfg type */
45126 /* Offset of the type */
45128 /* Size of the data to set in bytes */
45131 uint8_t unused0[6];
45134 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
45135 struct hwrm_tf_global_cfg_get_output {
45136 /* The specific error status for the command. */
45137 uint16_t error_code;
45138 /* The HWRM command request type. */
45140 /* The sequence ID from the original command. */
45142 /* The length of the response data in number of bytes. */
45144 /* Size of the data read in bytes */
45147 uint8_t unused0[6];
45152 /**********************
45153 * hwrm_tf_if_tbl_get *
45154 **********************/
45157 /* hwrm_tf_if_tbl_get_input (size:256b/32B) */
45158 struct hwrm_tf_if_tbl_get_input {
45159 /* The HWRM command request type. */
45162 * The completion ring to send the completion event on. This should
45163 * be the NQ ID returned from the `nq_alloc` HWRM command.
45165 uint16_t cmpl_ring;
45167 * The sequence ID is used by the driver for tracking multiple
45168 * commands. This ID is treated as opaque data by the firmware and
45169 * the value is returned in the `hwrm_resp_hdr` upon completion.
45173 * The target ID of the command:
45174 * * 0x0-0xFFF8 - The function ID
45175 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45176 * * 0xFFFD - Reserved for user-space HWRM interface
45179 uint16_t target_id;
45181 * A physical address pointer pointing to a host buffer that the
45182 * command's response data will be written. This can be either a host
45183 * physical address (HPA) or a guest physical address (GPA) and must
45184 * point to a physically contiguous block of memory.
45186 uint64_t resp_addr;
45187 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45188 uint32_t fw_session_id;
45189 /* Control flags. */
45191 /* Indicates the flow direction. */
45192 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45193 /* If this bit set to 0, then it indicates rx flow. */
45194 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45195 /* If this bit is set to 1, then it indicates that tx flow. */
45196 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45197 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_LAST \
45198 HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX
45199 /* Size of the data to set. */
45202 * Type of the resource, defined globally in the
45203 * hwrm_tf_resc_type enum.
45206 /* Index of the type to retrieve. */
45210 /* hwrm_tf_if_tbl_get_output (size:256b/32B) */
45211 struct hwrm_tf_if_tbl_get_output {
45212 /* The specific error status for the command. */
45213 uint16_t error_code;
45214 /* The HWRM command request type. */
45216 /* The sequence ID from the original command. */
45218 /* The length of the response data in number of bytes. */
45220 /* Response code. */
45221 uint32_t resp_code;
45222 /* Response size. */
45226 /* Response data. */
45229 uint8_t unused1[7];
45231 * This field is used in Output records to indicate that the output
45232 * is completely written to RAM. This field should be read as '1'
45233 * to indicate that the output has been completely written.
45234 * When writing a command completion or response to an internal
45235 * processor, the order of writes has to be such that this field
45241 /***************************
45242 * hwrm_tf_if_tbl_type_set *
45243 ***************************/
45246 /* hwrm_tf_if_tbl_set_input (size:384b/48B) */
45247 struct hwrm_tf_if_tbl_set_input {
45248 /* The HWRM command request type. */
45251 * The completion ring to send the completion event on. This should
45252 * be the NQ ID returned from the `nq_alloc` HWRM command.
45254 uint16_t cmpl_ring;
45256 * The sequence ID is used by the driver for tracking multiple
45257 * commands. This ID is treated as opaque data by the firmware and
45258 * the value is returned in the `hwrm_resp_hdr` upon completion.
45262 * The target ID of the command:
45263 * * 0x0-0xFFF8 - The function ID
45264 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45265 * * 0xFFFD - Reserved for user-space HWRM interface
45268 uint16_t target_id;
45270 * A physical address pointer pointing to a host buffer that the
45271 * command's response data will be written. This can be either a host
45272 * physical address (HPA) or a guest physical address (GPA) and must
45273 * point to a physically contiguous block of memory.
45275 uint64_t resp_addr;
45276 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45277 uint32_t fw_session_id;
45278 /* Control flags. */
45280 /* Indicates the flow direction. */
45281 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
45282 /* If this bit set to 0, then it indicates rx flow. */
45283 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45284 /* If this bit is set to 1, then it indicates that tx flow. */
45285 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45286 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \
45287 HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX
45289 uint8_t unused0[2];
45291 * Type of the resource, defined globally in the
45292 * hwrm_tf_resc_type enum.
45295 /* Index of the type to set. */
45297 /* Size of the data to set. */
45300 uint8_t unused1[6];
45301 /* Data to be set. */
45305 /* hwrm_tf_if_tbl_set_output (size:128b/16B) */
45306 struct hwrm_tf_if_tbl_set_output {
45307 /* The specific error status for the command. */
45308 uint16_t error_code;
45309 /* The HWRM command request type. */
45311 /* The sequence ID from the original command. */
45313 /* The length of the response data in number of bytes. */
45316 uint8_t unused0[7];
45318 * This field is used in Output records to indicate that the output
45319 * is completely written to RAM. This field should be read as '1'
45320 * to indicate that the output has been completely written.
45321 * When writing a command completion or response to an internal
45322 * processor, the order of writes has to be such that this field
45328 /*****************************
45329 * hwrm_tf_tbl_type_bulk_get *
45330 *****************************/
45333 /* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */
45334 struct hwrm_tf_tbl_type_bulk_get_input {
45335 /* The HWRM command request type. */
45338 * The completion ring to send the completion event on. This should
45339 * be the NQ ID returned from the `nq_alloc` HWRM command.
45341 uint16_t cmpl_ring;
45343 * The sequence ID is used by the driver for tracking multiple
45344 * commands. This ID is treated as opaque data by the firmware and
45345 * the value is returned in the `hwrm_resp_hdr` upon completion.
45349 * The target ID of the command:
45350 * * 0x0-0xFFF8 - The function ID
45351 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45352 * * 0xFFFD - Reserved for user-space HWRM interface
45355 uint16_t target_id;
45357 * A physical address pointer pointing to a host buffer that the
45358 * command's response data will be written. This can be either a host
45359 * physical address (HPA) or a guest physical address (GPA) and must
45360 * point to a physically contiguous block of memory.
45362 uint64_t resp_addr;
45363 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
45364 uint32_t fw_session_id;
45365 /* Control flags. */
45367 /* Indicates the flow direction. */
45368 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
45369 /* If this bit set to 0, then it indicates rx flow. */
45370 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
45371 /* If this bit is set to 1, then it indicates that tx flow. */
45372 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
45373 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \
45374 HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX
45376 uint8_t unused0[2];
45378 * Type of the resource, defined globally in the
45379 * hwrm_tf_resc_type enum.
45382 /* Starting index of the type to retrieve. */
45383 uint32_t start_index;
45384 /* Number of entries to retrieve. */
45385 uint32_t num_entries;
45386 /* Number of entries to retrieve. */
45388 /* Host memory where data will be stored. */
45389 uint64_t host_addr;
45392 /* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */
45393 struct hwrm_tf_tbl_type_bulk_get_output {
45394 /* The specific error status for the command. */
45395 uint16_t error_code;
45396 /* The HWRM command request type. */
45398 /* The sequence ID from the original command. */
45400 /* The length of the response data in number of bytes. */
45402 /* Response code. */
45403 uint32_t resp_code;
45404 /* Response size. */
45409 * This field is used in Output records to indicate that the output
45410 * is completely written to RAM. This field should be read as '1'
45411 * to indicate that the output has been completely written.
45412 * When writing a command completion or response to an internal
45413 * processor, the order of writes has to be such that this field
45419 /******************************
45420 * hwrm_tunnel_dst_port_query *
45421 ******************************/
45424 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
45425 struct hwrm_tunnel_dst_port_query_input {
45426 /* The HWRM command request type. */
45429 * The completion ring to send the completion event on. This should
45430 * be the NQ ID returned from the `nq_alloc` HWRM command.
45432 uint16_t cmpl_ring;
45434 * The sequence ID is used by the driver for tracking multiple
45435 * commands. This ID is treated as opaque data by the firmware and
45436 * the value is returned in the `hwrm_resp_hdr` upon completion.
45440 * The target ID of the command:
45441 * * 0x0-0xFFF8 - The function ID
45442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45443 * * 0xFFFD - Reserved for user-space HWRM interface
45446 uint16_t target_id;
45448 * A physical address pointer pointing to a host buffer that the
45449 * command's response data will be written. This can be either a host
45450 * physical address (HPA) or a guest physical address (GPA) and must
45451 * point to a physically contiguous block of memory.
45453 uint64_t resp_addr;
45455 uint8_t tunnel_type;
45456 /* Virtual eXtensible Local Area Network (VXLAN) */
45457 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
45459 /* Generic Network Virtualization Encapsulation (Geneve) */
45460 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
45462 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45463 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45465 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45466 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45468 /* Use fixed layer 2 ether type of 0xFFFF */
45469 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
45471 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45472 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45474 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
45475 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45476 uint8_t unused_0[7];
45479 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
45480 struct hwrm_tunnel_dst_port_query_output {
45481 /* The specific error status for the command. */
45482 uint16_t error_code;
45483 /* The HWRM command request type. */
45485 /* The sequence ID from the original command. */
45487 /* The length of the response data in number of bytes. */
45490 * This field represents the identifier of L4 destination port
45491 * used for the given tunnel type. This field is valid for
45492 * specific tunnel types that use layer 4 (e.g. UDP)
45493 * transports for tunneling.
45495 uint16_t tunnel_dst_port_id;
45497 * This field represents the value of L4 destination port
45498 * identified by tunnel_dst_port_id. This field is valid for
45499 * specific tunnel types that use layer 4 (e.g. UDP)
45500 * transports for tunneling.
45501 * This field is in network byte order.
45503 * A value of 0 means that the destination port is not
45506 uint16_t tunnel_dst_port_val;
45507 uint8_t unused_0[3];
45509 * This field is used in Output records to indicate that the output
45510 * is completely written to RAM. This field should be read as '1'
45511 * to indicate that the output has been completely written.
45512 * When writing a command completion or response to an internal processor,
45513 * the order of writes has to be such that this field is written last.
45518 /******************************
45519 * hwrm_tunnel_dst_port_alloc *
45520 ******************************/
45523 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
45524 struct hwrm_tunnel_dst_port_alloc_input {
45525 /* The HWRM command request type. */
45528 * The completion ring to send the completion event on. This should
45529 * be the NQ ID returned from the `nq_alloc` HWRM command.
45531 uint16_t cmpl_ring;
45533 * The sequence ID is used by the driver for tracking multiple
45534 * commands. This ID is treated as opaque data by the firmware and
45535 * the value is returned in the `hwrm_resp_hdr` upon completion.
45539 * The target ID of the command:
45540 * * 0x0-0xFFF8 - The function ID
45541 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45542 * * 0xFFFD - Reserved for user-space HWRM interface
45545 uint16_t target_id;
45547 * A physical address pointer pointing to a host buffer that the
45548 * command's response data will be written. This can be either a host
45549 * physical address (HPA) or a guest physical address (GPA) and must
45550 * point to a physically contiguous block of memory.
45552 uint64_t resp_addr;
45554 uint8_t tunnel_type;
45555 /* Virtual eXtensible Local Area Network (VXLAN) */
45556 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
45558 /* Generic Network Virtualization Encapsulation (Geneve) */
45559 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
45561 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45562 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45564 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45565 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45567 /* Use fixed layer 2 ether type of 0xFFFF */
45568 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
45570 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45571 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45573 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
45574 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45577 * This field represents the value of L4 destination port used
45578 * for the given tunnel type. This field is valid for
45579 * specific tunnel types that use layer 4 (e.g. UDP)
45580 * transports for tunneling.
45582 * This field is in network byte order.
45584 * A value of 0 shall fail the command.
45586 uint16_t tunnel_dst_port_val;
45587 uint8_t unused_1[4];
45590 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
45591 struct hwrm_tunnel_dst_port_alloc_output {
45592 /* The specific error status for the command. */
45593 uint16_t error_code;
45594 /* The HWRM command request type. */
45596 /* The sequence ID from the original command. */
45598 /* The length of the response data in number of bytes. */
45601 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
45602 * types that has l4 destination port parameters.
45604 uint16_t tunnel_dst_port_id;
45605 uint8_t unused_0[5];
45607 * This field is used in Output records to indicate that the output
45608 * is completely written to RAM. This field should be read as '1'
45609 * to indicate that the output has been completely written.
45610 * When writing a command completion or response to an internal processor,
45611 * the order of writes has to be such that this field is written last.
45616 /*****************************
45617 * hwrm_tunnel_dst_port_free *
45618 *****************************/
45621 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
45622 struct hwrm_tunnel_dst_port_free_input {
45623 /* The HWRM command request type. */
45626 * The completion ring to send the completion event on. This should
45627 * be the NQ ID returned from the `nq_alloc` HWRM command.
45629 uint16_t cmpl_ring;
45631 * The sequence ID is used by the driver for tracking multiple
45632 * commands. This ID is treated as opaque data by the firmware and
45633 * the value is returned in the `hwrm_resp_hdr` upon completion.
45637 * The target ID of the command:
45638 * * 0x0-0xFFF8 - The function ID
45639 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45640 * * 0xFFFD - Reserved for user-space HWRM interface
45643 uint16_t target_id;
45645 * A physical address pointer pointing to a host buffer that the
45646 * command's response data will be written. This can be either a host
45647 * physical address (HPA) or a guest physical address (GPA) and must
45648 * point to a physically contiguous block of memory.
45650 uint64_t resp_addr;
45652 uint8_t tunnel_type;
45653 /* Virtual eXtensible Local Area Network (VXLAN) */
45654 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
45656 /* Generic Network Virtualization Encapsulation (Geneve) */
45657 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
45659 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
45660 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
45662 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
45663 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
45665 /* Use fixed layer 2 ether type of 0xFFFF */
45666 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
45668 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
45669 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
45671 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
45672 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
45675 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
45676 * types that has l4 destination port parameters.
45678 uint16_t tunnel_dst_port_id;
45679 uint8_t unused_1[4];
45682 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
45683 struct hwrm_tunnel_dst_port_free_output {
45684 /* The specific error status for the command. */
45685 uint16_t error_code;
45686 /* The HWRM command request type. */
45688 /* The sequence ID from the original command. */
45690 /* The length of the response data in number of bytes. */
45692 uint8_t unused_1[7];
45694 * This field is used in Output records to indicate that the output
45695 * is completely written to RAM. This field should be read as '1'
45696 * to indicate that the output has been completely written.
45697 * When writing a command completion or response to an internal processor,
45698 * the order of writes has to be such that this field is written last.
45703 /* Periodic statistics context DMA to host. */
45704 /* ctx_hw_stats (size:1280b/160B) */
45705 struct ctx_hw_stats {
45706 /* Number of received unicast packets */
45707 uint64_t rx_ucast_pkts;
45708 /* Number of received multicast packets */
45709 uint64_t rx_mcast_pkts;
45710 /* Number of received broadcast packets */
45711 uint64_t rx_bcast_pkts;
45712 /* Number of discarded packets on receive path */
45713 uint64_t rx_discard_pkts;
45714 /* Number of packets on receive path with error */
45715 uint64_t rx_error_pkts;
45716 /* Number of received bytes for unicast traffic */
45717 uint64_t rx_ucast_bytes;
45718 /* Number of received bytes for multicast traffic */
45719 uint64_t rx_mcast_bytes;
45720 /* Number of received bytes for broadcast traffic */
45721 uint64_t rx_bcast_bytes;
45722 /* Number of transmitted unicast packets */
45723 uint64_t tx_ucast_pkts;
45724 /* Number of transmitted multicast packets */
45725 uint64_t tx_mcast_pkts;
45726 /* Number of transmitted broadcast packets */
45727 uint64_t tx_bcast_pkts;
45728 /* Number of packets on transmit path with error */
45729 uint64_t tx_error_pkts;
45730 /* Number of discarded packets on transmit path */
45731 uint64_t tx_discard_pkts;
45732 /* Number of transmitted bytes for unicast traffic */
45733 uint64_t tx_ucast_bytes;
45734 /* Number of transmitted bytes for multicast traffic */
45735 uint64_t tx_mcast_bytes;
45736 /* Number of transmitted bytes for broadcast traffic */
45737 uint64_t tx_bcast_bytes;
45738 /* Number of TPA packets */
45740 /* Number of TPA bytes */
45741 uint64_t tpa_bytes;
45742 /* Number of TPA events */
45743 uint64_t tpa_events;
45744 /* Number of TPA aborts */
45745 uint64_t tpa_aborts;
45749 * Extended periodic statistics context DMA to host. On cards that
45750 * support TPA v2, additional TPA related stats exist and can be retrieved
45751 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
45753 /* ctx_hw_stats_ext (size:1408b/176B) */
45754 struct ctx_hw_stats_ext {
45755 /* Number of received unicast packets */
45756 uint64_t rx_ucast_pkts;
45757 /* Number of received multicast packets */
45758 uint64_t rx_mcast_pkts;
45759 /* Number of received broadcast packets */
45760 uint64_t rx_bcast_pkts;
45761 /* Number of discarded packets on receive path */
45762 uint64_t rx_discard_pkts;
45763 /* Number of packets on receive path with error */
45764 uint64_t rx_error_pkts;
45765 /* Number of received bytes for unicast traffic */
45766 uint64_t rx_ucast_bytes;
45767 /* Number of received bytes for multicast traffic */
45768 uint64_t rx_mcast_bytes;
45769 /* Number of received bytes for broadcast traffic */
45770 uint64_t rx_bcast_bytes;
45771 /* Number of transmitted unicast packets */
45772 uint64_t tx_ucast_pkts;
45773 /* Number of transmitted multicast packets */
45774 uint64_t tx_mcast_pkts;
45775 /* Number of transmitted broadcast packets */
45776 uint64_t tx_bcast_pkts;
45777 /* Number of packets on transmit path with error */
45778 uint64_t tx_error_pkts;
45779 /* Number of discarded packets on transmit path */
45780 uint64_t tx_discard_pkts;
45781 /* Number of transmitted bytes for unicast traffic */
45782 uint64_t tx_ucast_bytes;
45783 /* Number of transmitted bytes for multicast traffic */
45784 uint64_t tx_mcast_bytes;
45785 /* Number of transmitted bytes for broadcast traffic */
45786 uint64_t tx_bcast_bytes;
45787 /* Number of TPA eligible packets */
45788 uint64_t rx_tpa_eligible_pkt;
45789 /* Number of TPA eligible bytes */
45790 uint64_t rx_tpa_eligible_bytes;
45791 /* Number of TPA packets */
45792 uint64_t rx_tpa_pkt;
45793 /* Number of TPA bytes */
45794 uint64_t rx_tpa_bytes;
45795 /* Number of TPA errors */
45796 uint64_t rx_tpa_errors;
45797 /* Number of TPA events */
45798 uint64_t rx_tpa_events;
45801 /* Periodic Engine statistics context DMA to host. */
45802 /* ctx_eng_stats (size:512b/64B) */
45803 struct ctx_eng_stats {
45805 * Count of data bytes into the Engine.
45806 * This includes any user supplied prefix,
45807 * but does not include any predefined
45810 uint64_t eng_bytes_in;
45811 /* Count of data bytes out of the Engine. */
45812 uint64_t eng_bytes_out;
45814 * Count, in 4-byte (dword) units, of bytes
45815 * that are input as auxiliary data.
45816 * This includes the aux_cmd data.
45818 uint64_t aux_bytes_in;
45820 * Count, in 4-byte (dword) units, of bytes
45821 * that are output as auxiliary data.
45822 * This count is the buffer space for aux_data
45823 * output provided in the RQE, not the actual
45826 uint64_t aux_bytes_out;
45827 /* Count of number of commands executed. */
45830 * Count of number of error commands.
45831 * These are the commands with a
45832 * non-zero status value.
45834 uint64_t error_commands;
45836 * Compression/Encryption Engine usage,
45837 * the unit is count of clock cycles
45839 uint64_t cce_engine_usage;
45841 * De-Compression/De-cryption Engine usage,
45842 * the unit is count of clock cycles
45844 uint64_t cdd_engine_usage;
45847 /***********************
45848 * hwrm_stat_ctx_alloc *
45849 ***********************/
45852 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
45853 struct hwrm_stat_ctx_alloc_input {
45854 /* The HWRM command request type. */
45857 * The completion ring to send the completion event on. This should
45858 * be the NQ ID returned from the `nq_alloc` HWRM command.
45860 uint16_t cmpl_ring;
45862 * The sequence ID is used by the driver for tracking multiple
45863 * commands. This ID is treated as opaque data by the firmware and
45864 * the value is returned in the `hwrm_resp_hdr` upon completion.
45868 * The target ID of the command:
45869 * * 0x0-0xFFF8 - The function ID
45870 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45871 * * 0xFFFD - Reserved for user-space HWRM interface
45874 uint16_t target_id;
45876 * A physical address pointer pointing to a host buffer that the
45877 * command's response data will be written. This can be either a host
45878 * physical address (HPA) or a guest physical address (GPA) and must
45879 * point to a physically contiguous block of memory.
45881 uint64_t resp_addr;
45883 * This is the address for statistic block.
45884 * > For new versions of the chip, this address should be 128B
45887 uint64_t stats_dma_addr;
45889 * The statistic block update period in ms.
45890 * e.g. 250ms, 500ms, 750ms, 1000ms.
45891 * If update_period_ms is 0, then the stats update
45892 * shall be never done and the DMA address shall not be used.
45893 * In this case, the stat block can only be read by
45894 * hwrm_stat_ctx_query command.
45895 * On Ethernet/L2 based devices:
45896 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
45897 * ctx_hw_stats_ext is used for DMA,
45899 * ctx_hw_stats is used for DMA.
45901 uint32_t update_period_ms;
45903 * This field is used to specify statistics context specific
45904 * configuration flags.
45906 uint8_t stat_ctx_flags;
45908 * When this bit is set to '1', the statistics context shall be
45909 * allocated for RoCE traffic only. In this case, traffic other
45910 * than offloaded RoCE traffic shall not be included in this
45911 * statistic context.
45912 * When this bit is set to '0', the statistics context shall be
45913 * used for network traffic or engine traffic.
45915 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
45918 * This is the size of the structure (ctx_hw_stats or
45919 * ctx_hw_stats_ext) that the driver has allocated to be used
45920 * for the periodic DMA updates.
45922 uint16_t stats_dma_length;
45925 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
45926 struct hwrm_stat_ctx_alloc_output {
45927 /* The specific error status for the command. */
45928 uint16_t error_code;
45929 /* The HWRM command request type. */
45931 /* The sequence ID from the original command. */
45933 /* The length of the response data in number of bytes. */
45935 /* This is the statistics context ID value. */
45936 uint32_t stat_ctx_id;
45937 uint8_t unused_0[3];
45939 * This field is used in Output records to indicate that the output
45940 * is completely written to RAM. This field should be read as '1'
45941 * to indicate that the output has been completely written.
45942 * When writing a command completion or response to an internal processor,
45943 * the order of writes has to be such that this field is written last.
45948 /**********************
45949 * hwrm_stat_ctx_free *
45950 **********************/
45953 /* hwrm_stat_ctx_free_input (size:192b/24B) */
45954 struct hwrm_stat_ctx_free_input {
45955 /* The HWRM command request type. */
45958 * The completion ring to send the completion event on. This should
45959 * be the NQ ID returned from the `nq_alloc` HWRM command.
45961 uint16_t cmpl_ring;
45963 * The sequence ID is used by the driver for tracking multiple
45964 * commands. This ID is treated as opaque data by the firmware and
45965 * the value is returned in the `hwrm_resp_hdr` upon completion.
45969 * The target ID of the command:
45970 * * 0x0-0xFFF8 - The function ID
45971 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45972 * * 0xFFFD - Reserved for user-space HWRM interface
45975 uint16_t target_id;
45977 * A physical address pointer pointing to a host buffer that the
45978 * command's response data will be written. This can be either a host
45979 * physical address (HPA) or a guest physical address (GPA) and must
45980 * point to a physically contiguous block of memory.
45982 uint64_t resp_addr;
45983 /* ID of the statistics context that is being queried. */
45984 uint32_t stat_ctx_id;
45985 uint8_t unused_0[4];
45988 /* hwrm_stat_ctx_free_output (size:128b/16B) */
45989 struct hwrm_stat_ctx_free_output {
45990 /* The specific error status for the command. */
45991 uint16_t error_code;
45992 /* The HWRM command request type. */
45994 /* The sequence ID from the original command. */
45996 /* The length of the response data in number of bytes. */
45998 /* This is the statistics context ID value. */
45999 uint32_t stat_ctx_id;
46000 uint8_t unused_0[3];
46002 * This field is used in Output records to indicate that the output
46003 * is completely written to RAM. This field should be read as '1'
46004 * to indicate that the output has been completely written.
46005 * When writing a command completion or response to an internal processor,
46006 * the order of writes has to be such that this field is written last.
46011 /***********************
46012 * hwrm_stat_ctx_query *
46013 ***********************/
46016 /* hwrm_stat_ctx_query_input (size:192b/24B) */
46017 struct hwrm_stat_ctx_query_input {
46018 /* The HWRM command request type. */
46021 * The completion ring to send the completion event on. This should
46022 * be the NQ ID returned from the `nq_alloc` HWRM command.
46024 uint16_t cmpl_ring;
46026 * The sequence ID is used by the driver for tracking multiple
46027 * commands. This ID is treated as opaque data by the firmware and
46028 * the value is returned in the `hwrm_resp_hdr` upon completion.
46032 * The target ID of the command:
46033 * * 0x0-0xFFF8 - The function ID
46034 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46035 * * 0xFFFD - Reserved for user-space HWRM interface
46038 uint16_t target_id;
46040 * A physical address pointer pointing to a host buffer that the
46041 * command's response data will be written. This can be either a host
46042 * physical address (HPA) or a guest physical address (GPA) and must
46043 * point to a physically contiguous block of memory.
46045 uint64_t resp_addr;
46046 /* ID of the statistics context that is being queried. */
46047 uint32_t stat_ctx_id;
46050 * This bit is set to 1 when request is for a counter mask,
46051 * representing the width of each of the stats counters, rather
46052 * than counters themselves.
46054 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
46055 uint8_t unused_0[3];
46058 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
46059 struct hwrm_stat_ctx_query_output {
46060 /* The specific error status for the command. */
46061 uint16_t error_code;
46062 /* The HWRM command request type. */
46064 /* The sequence ID from the original command. */
46066 /* The length of the response data in number of bytes. */
46068 /* Number of transmitted unicast packets */
46069 uint64_t tx_ucast_pkts;
46070 /* Number of transmitted multicast packets */
46071 uint64_t tx_mcast_pkts;
46072 /* Number of transmitted broadcast packets */
46073 uint64_t tx_bcast_pkts;
46074 /* Number of packets discarded in transmit path */
46075 uint64_t tx_discard_pkts;
46076 /* Number of packets in transmit path with error */
46077 uint64_t tx_error_pkts;
46078 /* Number of transmitted bytes for unicast traffic */
46079 uint64_t tx_ucast_bytes;
46080 /* Number of transmitted bytes for multicast traffic */
46081 uint64_t tx_mcast_bytes;
46082 /* Number of transmitted bytes for broadcast traffic */
46083 uint64_t tx_bcast_bytes;
46084 /* Number of received unicast packets */
46085 uint64_t rx_ucast_pkts;
46086 /* Number of received multicast packets */
46087 uint64_t rx_mcast_pkts;
46088 /* Number of received broadcast packets */
46089 uint64_t rx_bcast_pkts;
46090 /* Number of packets discarded in receive path */
46091 uint64_t rx_discard_pkts;
46092 /* Number of packets in receive path with errors */
46093 uint64_t rx_error_pkts;
46094 /* Number of received bytes for unicast traffic */
46095 uint64_t rx_ucast_bytes;
46096 /* Number of received bytes for multicast traffic */
46097 uint64_t rx_mcast_bytes;
46098 /* Number of received bytes for broadcast traffic */
46099 uint64_t rx_bcast_bytes;
46100 /* Number of aggregated unicast packets */
46101 uint64_t rx_agg_pkts;
46102 /* Number of aggregated unicast bytes */
46103 uint64_t rx_agg_bytes;
46104 /* Number of aggregation events */
46105 uint64_t rx_agg_events;
46106 /* Number of aborted aggregations */
46107 uint64_t rx_agg_aborts;
46108 uint8_t unused_0[7];
46110 * This field is used in Output records to indicate that the output
46111 * is completely written to RAM. This field should be read as '1'
46112 * to indicate that the output has been completely written.
46113 * When writing a command completion or response to an internal processor,
46114 * the order of writes has to be such that this field is written last.
46119 /***************************
46120 * hwrm_stat_ext_ctx_query *
46121 ***************************/
46124 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
46125 struct hwrm_stat_ext_ctx_query_input {
46126 /* The HWRM command request type. */
46129 * The completion ring to send the completion event on. This should
46130 * be the NQ ID returned from the `nq_alloc` HWRM command.
46132 uint16_t cmpl_ring;
46134 * The sequence ID is used by the driver for tracking multiple
46135 * commands. This ID is treated as opaque data by the firmware and
46136 * the value is returned in the `hwrm_resp_hdr` upon completion.
46140 * The target ID of the command:
46141 * * 0x0-0xFFF8 - The function ID
46142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46143 * * 0xFFFD - Reserved for user-space HWRM interface
46146 uint16_t target_id;
46148 * A physical address pointer pointing to a host buffer that the
46149 * command's response data will be written. This can be either a host
46150 * physical address (HPA) or a guest physical address (GPA) and must
46151 * point to a physically contiguous block of memory.
46153 uint64_t resp_addr;
46154 /* ID of the extended statistics context that is being queried. */
46155 uint32_t stat_ctx_id;
46158 * This bit is set to 1 when request is for a counter mask,
46159 * representing the width of each of the stats counters, rather
46160 * than counters themselves.
46162 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
46164 uint8_t unused_0[3];
46167 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */
46168 struct hwrm_stat_ext_ctx_query_output {
46169 /* The specific error status for the command. */
46170 uint16_t error_code;
46171 /* The HWRM command request type. */
46173 /* The sequence ID from the original command. */
46175 /* The length of the response data in number of bytes. */
46177 /* Number of received unicast packets */
46178 uint64_t rx_ucast_pkts;
46179 /* Number of received multicast packets */
46180 uint64_t rx_mcast_pkts;
46181 /* Number of received broadcast packets */
46182 uint64_t rx_bcast_pkts;
46183 /* Number of discarded packets on receive path */
46184 uint64_t rx_discard_pkts;
46185 /* Number of packets on receive path with error */
46186 uint64_t rx_error_pkts;
46187 /* Number of received bytes for unicast traffic */
46188 uint64_t rx_ucast_bytes;
46189 /* Number of received bytes for multicast traffic */
46190 uint64_t rx_mcast_bytes;
46191 /* Number of received bytes for broadcast traffic */
46192 uint64_t rx_bcast_bytes;
46193 /* Number of transmitted unicast packets */
46194 uint64_t tx_ucast_pkts;
46195 /* Number of transmitted multicast packets */
46196 uint64_t tx_mcast_pkts;
46197 /* Number of transmitted broadcast packets */
46198 uint64_t tx_bcast_pkts;
46199 /* Number of packets on transmit path with error */
46200 uint64_t tx_error_pkts;
46201 /* Number of discarded packets on transmit path */
46202 uint64_t tx_discard_pkts;
46203 /* Number of transmitted bytes for unicast traffic */
46204 uint64_t tx_ucast_bytes;
46205 /* Number of transmitted bytes for multicast traffic */
46206 uint64_t tx_mcast_bytes;
46207 /* Number of transmitted bytes for broadcast traffic */
46208 uint64_t tx_bcast_bytes;
46209 /* Number of TPA eligible packets */
46210 uint64_t rx_tpa_eligible_pkt;
46211 /* Number of TPA eligible bytes */
46212 uint64_t rx_tpa_eligible_bytes;
46213 /* Number of TPA packets */
46214 uint64_t rx_tpa_pkt;
46215 /* Number of TPA bytes */
46216 uint64_t rx_tpa_bytes;
46217 /* Number of TPA errors */
46218 uint64_t rx_tpa_errors;
46219 /* Number of TPA events */
46220 uint64_t rx_tpa_events;
46221 uint8_t unused_0[7];
46223 * This field is used in Output records to indicate that the output
46224 * is completely written to RAM. This field should be read as '1'
46225 * to indicate that the output has been completely written.
46226 * When writing a command completion or response to an internal processor,
46227 * the order of writes has to be such that this field is written last.
46232 /***************************
46233 * hwrm_stat_ctx_eng_query *
46234 ***************************/
46237 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
46238 struct hwrm_stat_ctx_eng_query_input {
46239 /* The HWRM command request type. */
46242 * The completion ring to send the completion event on. This should
46243 * be the NQ ID returned from the `nq_alloc` HWRM command.
46245 uint16_t cmpl_ring;
46247 * The sequence ID is used by the driver for tracking multiple
46248 * commands. This ID is treated as opaque data by the firmware and
46249 * the value is returned in the `hwrm_resp_hdr` upon completion.
46253 * The target ID of the command:
46254 * * 0x0-0xFFF8 - The function ID
46255 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46256 * * 0xFFFD - Reserved for user-space HWRM interface
46259 uint16_t target_id;
46261 * A physical address pointer pointing to a host buffer that the
46262 * command's response data will be written. This can be either a host
46263 * physical address (HPA) or a guest physical address (GPA) and must
46264 * point to a physically contiguous block of memory.
46266 uint64_t resp_addr;
46267 /* ID of the statistics context that is being queried. */
46268 uint32_t stat_ctx_id;
46269 uint8_t unused_0[4];
46272 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
46273 struct hwrm_stat_ctx_eng_query_output {
46274 /* The specific error status for the command. */
46275 uint16_t error_code;
46276 /* The HWRM command request type. */
46278 /* The sequence ID from the original command. */
46280 /* The length of the response data in number of bytes. */
46283 * Count of data bytes into the Engine.
46284 * This includes any user supplied prefix,
46285 * but does not include any predefined
46288 uint64_t eng_bytes_in;
46289 /* Count of data bytes out of the Engine. */
46290 uint64_t eng_bytes_out;
46292 * Count, in 4-byte (dword) units, of bytes
46293 * that are input as auxiliary data.
46294 * This includes the aux_cmd data.
46296 uint64_t aux_bytes_in;
46298 * Count, in 4-byte (dword) units, of bytes
46299 * that are output as auxiliary data.
46300 * This count is the buffer space for aux_data
46301 * output provided in the RQE, not the actual
46304 uint64_t aux_bytes_out;
46305 /* Count of number of commands executed. */
46308 * Count of number of error commands.
46309 * These are the commands with a
46310 * non-zero status value.
46312 uint64_t error_commands;
46314 * Compression/Encryption Engine usage,
46315 * the unit is count of clock cycles
46317 uint64_t cce_engine_usage;
46319 * De-Compression/De-cryption Engine usage,
46320 * the unit is count of clock cycles
46322 uint64_t cdd_engine_usage;
46323 uint8_t unused_0[7];
46325 * This field is used in Output records to indicate that the output
46326 * is completely written to RAM. This field should be read as '1'
46327 * to indicate that the output has been completely written.
46328 * When writing a command completion or response to an internal processor,
46329 * the order of writes has to be such that this field is written last.
46334 /***************************
46335 * hwrm_stat_ctx_clr_stats *
46336 ***************************/
46339 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
46340 struct hwrm_stat_ctx_clr_stats_input {
46341 /* The HWRM command request type. */
46344 * The completion ring to send the completion event on. This should
46345 * be the NQ ID returned from the `nq_alloc` HWRM command.
46347 uint16_t cmpl_ring;
46349 * The sequence ID is used by the driver for tracking multiple
46350 * commands. This ID is treated as opaque data by the firmware and
46351 * the value is returned in the `hwrm_resp_hdr` upon completion.
46355 * The target ID of the command:
46356 * * 0x0-0xFFF8 - The function ID
46357 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46358 * * 0xFFFD - Reserved for user-space HWRM interface
46361 uint16_t target_id;
46363 * A physical address pointer pointing to a host buffer that the
46364 * command's response data will be written. This can be either a host
46365 * physical address (HPA) or a guest physical address (GPA) and must
46366 * point to a physically contiguous block of memory.
46368 uint64_t resp_addr;
46369 /* ID of the statistics context that is being queried. */
46370 uint32_t stat_ctx_id;
46371 uint8_t unused_0[4];
46374 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
46375 struct hwrm_stat_ctx_clr_stats_output {
46376 /* The specific error status for the command. */
46377 uint16_t error_code;
46378 /* The HWRM command request type. */
46380 /* The sequence ID from the original command. */
46382 /* The length of the response data in number of bytes. */
46384 uint8_t unused_0[7];
46386 * This field is used in Output records to indicate that the output
46387 * is completely written to RAM. This field should be read as '1'
46388 * to indicate that the output has been completely written.
46389 * When writing a command completion or response to an internal processor,
46390 * the order of writes has to be such that this field is written last.
46395 /********************
46396 * hwrm_pcie_qstats *
46397 ********************/
46400 /* hwrm_pcie_qstats_input (size:256b/32B) */
46401 struct hwrm_pcie_qstats_input {
46402 /* The HWRM command request type. */
46405 * The completion ring to send the completion event on. This should
46406 * be the NQ ID returned from the `nq_alloc` HWRM command.
46408 uint16_t cmpl_ring;
46410 * The sequence ID is used by the driver for tracking multiple
46411 * commands. This ID is treated as opaque data by the firmware and
46412 * the value is returned in the `hwrm_resp_hdr` upon completion.
46416 * The target ID of the command:
46417 * * 0x0-0xFFF8 - The function ID
46418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46419 * * 0xFFFD - Reserved for user-space HWRM interface
46422 uint16_t target_id;
46424 * A physical address pointer pointing to a host buffer that the
46425 * command's response data will be written. This can be either a host
46426 * physical address (HPA) or a guest physical address (GPA) and must
46427 * point to a physically contiguous block of memory.
46429 uint64_t resp_addr;
46431 * The size of PCIe statistics block in bytes.
46432 * Firmware will DMA the PCIe statistics to
46433 * the host with this field size in the response.
46435 uint16_t pcie_stat_size;
46436 uint8_t unused_0[6];
46438 * This is the host address where
46439 * PCIe statistics will be stored
46441 uint64_t pcie_stat_host_addr;
46444 /* hwrm_pcie_qstats_output (size:128b/16B) */
46445 struct hwrm_pcie_qstats_output {
46446 /* The specific error status for the command. */
46447 uint16_t error_code;
46448 /* The HWRM command request type. */
46450 /* The sequence ID from the original command. */
46452 /* The length of the response data in number of bytes. */
46454 /* The size of PCIe statistics block in bytes. */
46455 uint16_t pcie_stat_size;
46456 uint8_t unused_0[5];
46458 * This field is used in Output records to indicate that the output
46459 * is completely written to RAM. This field should be read as '1'
46460 * to indicate that the output has been completely written.
46461 * When writing a command completion or response to an internal processor,
46462 * the order of writes has to be such that this field is written last.
46467 /* PCIe Statistics Formats */
46468 /* pcie_ctx_hw_stats (size:768b/96B) */
46469 struct pcie_ctx_hw_stats {
46470 /* Number of physical layer receiver errors */
46471 uint64_t pcie_pl_signal_integrity;
46472 /* Number of DLLP CRC errors detected by Data Link Layer */
46473 uint64_t pcie_dl_signal_integrity;
46475 * Number of TLP LCRC and sequence number errors detected
46476 * by Data Link Layer
46478 uint64_t pcie_tl_signal_integrity;
46479 /* Number of times LTSSM entered Recovery state */
46480 uint64_t pcie_link_integrity;
46481 /* Report number of TLP bits that have been transmitted in Mbps */
46482 uint64_t pcie_tx_traffic_rate;
46483 /* Report number of TLP bits that have been received in Mbps */
46484 uint64_t pcie_rx_traffic_rate;
46485 /* Number of DLLP bytes that have been transmitted */
46486 uint64_t pcie_tx_dllp_statistics;
46487 /* Number of DLLP bytes that have been received */
46488 uint64_t pcie_rx_dllp_statistics;
46490 * Number of times spent in each phase of gen3
46493 uint64_t pcie_equalization_time;
46494 /* Records the last 16 transitions of the LTSSM */
46495 uint32_t pcie_ltssm_histogram[4];
46497 * Record the last 8 reasons on why LTSSM transitioned
46500 uint64_t pcie_recovery_histogram;
46503 /**********************
46504 * hwrm_exec_fwd_resp *
46505 **********************/
46508 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
46509 struct hwrm_exec_fwd_resp_input {
46510 /* The HWRM command request type. */
46513 * The completion ring to send the completion event on. This should
46514 * be the NQ ID returned from the `nq_alloc` HWRM command.
46516 uint16_t cmpl_ring;
46518 * The sequence ID is used by the driver for tracking multiple
46519 * commands. This ID is treated as opaque data by the firmware and
46520 * the value is returned in the `hwrm_resp_hdr` upon completion.
46524 * The target ID of the command:
46525 * * 0x0-0xFFF8 - The function ID
46526 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46527 * * 0xFFFD - Reserved for user-space HWRM interface
46530 uint16_t target_id;
46532 * A physical address pointer pointing to a host buffer that the
46533 * command's response data will be written. This can be either a host
46534 * physical address (HPA) or a guest physical address (GPA) and must
46535 * point to a physically contiguous block of memory.
46537 uint64_t resp_addr;
46539 * This is an encapsulated request. This request should
46540 * be executed by the HWRM and the response should be
46541 * provided in the response buffer inside the encapsulated
46544 uint32_t encap_request[26];
46546 * This value indicates the target id of the response to
46547 * the encapsulated request.
46548 * 0x0 - 0xFFF8 - Used for function ids
46549 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46552 uint16_t encap_resp_target_id;
46553 uint8_t unused_0[6];
46556 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
46557 struct hwrm_exec_fwd_resp_output {
46558 /* The specific error status for the command. */
46559 uint16_t error_code;
46560 /* The HWRM command request type. */
46562 /* The sequence ID from the original command. */
46564 /* The length of the response data in number of bytes. */
46566 uint8_t unused_0[7];
46568 * This field is used in Output records to indicate that the output
46569 * is completely written to RAM. This field should be read as '1'
46570 * to indicate that the output has been completely written.
46571 * When writing a command completion or response to an internal processor,
46572 * the order of writes has to be such that this field is written last.
46577 /************************
46578 * hwrm_reject_fwd_resp *
46579 ************************/
46582 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
46583 struct hwrm_reject_fwd_resp_input {
46584 /* The HWRM command request type. */
46587 * The completion ring to send the completion event on. This should
46588 * be the NQ ID returned from the `nq_alloc` HWRM command.
46590 uint16_t cmpl_ring;
46592 * The sequence ID is used by the driver for tracking multiple
46593 * commands. This ID is treated as opaque data by the firmware and
46594 * the value is returned in the `hwrm_resp_hdr` upon completion.
46598 * The target ID of the command:
46599 * * 0x0-0xFFF8 - The function ID
46600 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46601 * * 0xFFFD - Reserved for user-space HWRM interface
46604 uint16_t target_id;
46606 * A physical address pointer pointing to a host buffer that the
46607 * command's response data will be written. This can be either a host
46608 * physical address (HPA) or a guest physical address (GPA) and must
46609 * point to a physically contiguous block of memory.
46611 uint64_t resp_addr;
46613 * This is an encapsulated request. This request should
46614 * be rejected by the HWRM and the error response should be
46615 * provided in the response buffer inside the encapsulated
46618 uint32_t encap_request[26];
46620 * This value indicates the target id of the response to
46621 * the encapsulated request.
46622 * 0x0 - 0xFFF8 - Used for function ids
46623 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46626 uint16_t encap_resp_target_id;
46627 uint8_t unused_0[6];
46630 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
46631 struct hwrm_reject_fwd_resp_output {
46632 /* The specific error status for the command. */
46633 uint16_t error_code;
46634 /* The HWRM command request type. */
46636 /* The sequence ID from the original command. */
46638 /* The length of the response data in number of bytes. */
46640 uint8_t unused_0[7];
46642 * This field is used in Output records to indicate that the output
46643 * is completely written to RAM. This field should be read as '1'
46644 * to indicate that the output has been completely written.
46645 * When writing a command completion or response to an internal processor,
46646 * the order of writes has to be such that this field is written last.
46656 /* hwrm_fwd_resp_input (size:1024b/128B) */
46657 struct hwrm_fwd_resp_input {
46658 /* The HWRM command request type. */
46661 * The completion ring to send the completion event on. This should
46662 * be the NQ ID returned from the `nq_alloc` HWRM command.
46664 uint16_t cmpl_ring;
46666 * The sequence ID is used by the driver for tracking multiple
46667 * commands. This ID is treated as opaque data by the firmware and
46668 * the value is returned in the `hwrm_resp_hdr` upon completion.
46672 * The target ID of the command:
46673 * * 0x0-0xFFF8 - The function ID
46674 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46675 * * 0xFFFD - Reserved for user-space HWRM interface
46678 uint16_t target_id;
46680 * A physical address pointer pointing to a host buffer that the
46681 * command's response data will be written. This can be either a host
46682 * physical address (HPA) or a guest physical address (GPA) and must
46683 * point to a physically contiguous block of memory.
46685 uint64_t resp_addr;
46687 * This value indicates the target id of the encapsulated
46689 * 0x0 - 0xFFF8 - Used for function ids
46690 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46693 uint16_t encap_resp_target_id;
46695 * This value indicates the completion ring the encapsulated
46696 * response will be optionally completed on. If the value is
46697 * -1, then no CR completion shall be generated for the
46698 * encapsulated response. Any other value must be a
46699 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
46700 * is provided, then a CR completion shall be generated for
46701 * the encapsulated response.
46703 uint16_t encap_resp_cmpl_ring;
46704 /* This field indicates the length of encapsulated response. */
46705 uint16_t encap_resp_len;
46709 * This is the host address where the encapsulated response
46711 * This area must be 16B aligned and must be cleared to zero
46712 * before the original request is made.
46714 uint64_t encap_resp_addr;
46715 /* This is an encapsulated response. */
46716 uint32_t encap_resp[24];
46719 /* hwrm_fwd_resp_output (size:128b/16B) */
46720 struct hwrm_fwd_resp_output {
46721 /* The specific error status for the command. */
46722 uint16_t error_code;
46723 /* The HWRM command request type. */
46725 /* The sequence ID from the original command. */
46727 /* The length of the response data in number of bytes. */
46729 uint8_t unused_0[7];
46731 * This field is used in Output records to indicate that the output
46732 * is completely written to RAM. This field should be read as '1'
46733 * to indicate that the output has been completely written.
46734 * When writing a command completion or response to an internal processor,
46735 * the order of writes has to be such that this field is written last.
46740 /*****************************
46741 * hwrm_fwd_async_event_cmpl *
46742 *****************************/
46745 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
46746 struct hwrm_fwd_async_event_cmpl_input {
46747 /* The HWRM command request type. */
46750 * The completion ring to send the completion event on. This should
46751 * be the NQ ID returned from the `nq_alloc` HWRM command.
46753 uint16_t cmpl_ring;
46755 * The sequence ID is used by the driver for tracking multiple
46756 * commands. This ID is treated as opaque data by the firmware and
46757 * the value is returned in the `hwrm_resp_hdr` upon completion.
46761 * The target ID of the command:
46762 * * 0x0-0xFFF8 - The function ID
46763 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46764 * * 0xFFFD - Reserved for user-space HWRM interface
46767 uint16_t target_id;
46769 * A physical address pointer pointing to a host buffer that the
46770 * command's response data will be written. This can be either a host
46771 * physical address (HPA) or a guest physical address (GPA) and must
46772 * point to a physically contiguous block of memory.
46774 uint64_t resp_addr;
46776 * This value indicates the target id of the encapsulated
46777 * asynchronous event.
46778 * 0x0 - 0xFFF8 - Used for function ids
46779 * 0xFFF8 - 0xFFFE - Reserved for internal processors
46780 * 0xFFFF - Broadcast to all children VFs (only applicable when
46781 * a PF is the requester)
46783 uint16_t encap_async_event_target_id;
46784 uint8_t unused_0[6];
46785 /* This is an encapsulated asynchronous event completion. */
46786 uint32_t encap_async_event_cmpl[4];
46789 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
46790 struct hwrm_fwd_async_event_cmpl_output {
46791 /* The specific error status for the command. */
46792 uint16_t error_code;
46793 /* The HWRM command request type. */
46795 /* The sequence ID from the original command. */
46797 /* The length of the response data in number of bytes. */
46799 uint8_t unused_0[7];
46801 * This field is used in Output records to indicate that the output
46802 * is completely written to RAM. This field should be read as '1'
46803 * to indicate that the output has been completely written.
46804 * When writing a command completion or response to an internal processor,
46805 * the order of writes has to be such that this field is written last.
46810 /**************************
46811 * hwrm_nvm_raw_write_blk *
46812 **************************/
46815 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
46816 struct hwrm_nvm_raw_write_blk_input {
46817 /* The HWRM command request type. */
46820 * The completion ring to send the completion event on. This should
46821 * be the NQ ID returned from the `nq_alloc` HWRM command.
46823 uint16_t cmpl_ring;
46825 * The sequence ID is used by the driver for tracking multiple
46826 * commands. This ID is treated as opaque data by the firmware and
46827 * the value is returned in the `hwrm_resp_hdr` upon completion.
46831 * The target ID of the command:
46832 * * 0x0-0xFFF8 - The function ID
46833 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46834 * * 0xFFFD - Reserved for user-space HWRM interface
46837 uint16_t target_id;
46839 * A physical address pointer pointing to a host buffer that the
46840 * command's response data will be written. This can be either a host
46841 * physical address (HPA) or a guest physical address (GPA) and must
46842 * point to a physically contiguous block of memory.
46844 uint64_t resp_addr;
46846 * 64-bit Host Source Address.
46847 * This is the location of the source data to be written.
46849 uint64_t host_src_addr;
46851 * 32-bit Destination Address.
46852 * This is the NVRAM byte-offset where the source data will be written to.
46854 uint32_t dest_addr;
46855 /* Length of data to be written, in bytes. */
46859 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
46860 struct hwrm_nvm_raw_write_blk_output {
46861 /* The specific error status for the command. */
46862 uint16_t error_code;
46863 /* The HWRM command request type. */
46865 /* The sequence ID from the original command. */
46867 /* The length of the response data in number of bytes. */
46869 uint8_t unused_0[7];
46871 * This field is used in Output records to indicate that the output
46872 * is completely written to RAM. This field should be read as '1'
46873 * to indicate that the output has been completely written.
46874 * When writing a command completion or response to an internal processor,
46875 * the order of writes has to be such that this field is written last.
46885 /* hwrm_nvm_read_input (size:320b/40B) */
46886 struct hwrm_nvm_read_input {
46887 /* The HWRM command request type. */
46890 * The completion ring to send the completion event on. This should
46891 * be the NQ ID returned from the `nq_alloc` HWRM command.
46893 uint16_t cmpl_ring;
46895 * The sequence ID is used by the driver for tracking multiple
46896 * commands. This ID is treated as opaque data by the firmware and
46897 * the value is returned in the `hwrm_resp_hdr` upon completion.
46901 * The target ID of the command:
46902 * * 0x0-0xFFF8 - The function ID
46903 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46904 * * 0xFFFD - Reserved for user-space HWRM interface
46907 uint16_t target_id;
46909 * A physical address pointer pointing to a host buffer that the
46910 * command's response data will be written. This can be either a host
46911 * physical address (HPA) or a guest physical address (GPA) and must
46912 * point to a physically contiguous block of memory.
46914 uint64_t resp_addr;
46916 * 64-bit Host Destination Address.
46917 * This is the host address where the data will be written to.
46919 uint64_t host_dest_addr;
46920 /* The 0-based index of the directory entry. */
46922 uint8_t unused_0[2];
46923 /* The NVRAM byte-offset to read from. */
46925 /* The length of the data to be read, in bytes. */
46927 uint8_t unused_1[4];
46930 /* hwrm_nvm_read_output (size:128b/16B) */
46931 struct hwrm_nvm_read_output {
46932 /* The specific error status for the command. */
46933 uint16_t error_code;
46934 /* The HWRM command request type. */
46936 /* The sequence ID from the original command. */
46938 /* The length of the response data in number of bytes. */
46940 uint8_t unused_0[7];
46942 * This field is used in Output records to indicate that the output
46943 * is completely written to RAM. This field should be read as '1'
46944 * to indicate that the output has been completely written.
46945 * When writing a command completion or response to an internal processor,
46946 * the order of writes has to be such that this field is written last.
46951 /*********************
46952 * hwrm_nvm_raw_dump *
46953 *********************/
46956 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
46957 struct hwrm_nvm_raw_dump_input {
46958 /* The HWRM command request type. */
46961 * The completion ring to send the completion event on. This should
46962 * be the NQ ID returned from the `nq_alloc` HWRM command.
46964 uint16_t cmpl_ring;
46966 * The sequence ID is used by the driver for tracking multiple
46967 * commands. This ID is treated as opaque data by the firmware and
46968 * the value is returned in the `hwrm_resp_hdr` upon completion.
46972 * The target ID of the command:
46973 * * 0x0-0xFFF8 - The function ID
46974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46975 * * 0xFFFD - Reserved for user-space HWRM interface
46978 uint16_t target_id;
46980 * A physical address pointer pointing to a host buffer that the
46981 * command's response data will be written. This can be either a host
46982 * physical address (HPA) or a guest physical address (GPA) and must
46983 * point to a physically contiguous block of memory.
46985 uint64_t resp_addr;
46987 * 64-bit Host Destination Address.
46988 * This is the host address where the data will be written to.
46990 uint64_t host_dest_addr;
46991 /* 32-bit NVRAM byte-offset to read from. */
46993 /* Total length of NVRAM contents to be read, in bytes. */
46997 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
46998 struct hwrm_nvm_raw_dump_output {
46999 /* The specific error status for the command. */
47000 uint16_t error_code;
47001 /* The HWRM command request type. */
47003 /* The sequence ID from the original command. */
47005 /* The length of the response data in number of bytes. */
47007 uint8_t unused_0[7];
47009 * This field is used in Output records to indicate that the output
47010 * is completely written to RAM. This field should be read as '1'
47011 * to indicate that the output has been completely written.
47012 * When writing a command completion or response to an internal processor,
47013 * the order of writes has to be such that this field is written last.
47018 /****************************
47019 * hwrm_nvm_get_dir_entries *
47020 ****************************/
47023 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
47024 struct hwrm_nvm_get_dir_entries_input {
47025 /* The HWRM command request type. */
47028 * The completion ring to send the completion event on. This should
47029 * be the NQ ID returned from the `nq_alloc` HWRM command.
47031 uint16_t cmpl_ring;
47033 * The sequence ID is used by the driver for tracking multiple
47034 * commands. This ID is treated as opaque data by the firmware and
47035 * the value is returned in the `hwrm_resp_hdr` upon completion.
47039 * The target ID of the command:
47040 * * 0x0-0xFFF8 - The function ID
47041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47042 * * 0xFFFD - Reserved for user-space HWRM interface
47045 uint16_t target_id;
47047 * A physical address pointer pointing to a host buffer that the
47048 * command's response data will be written. This can be either a host
47049 * physical address (HPA) or a guest physical address (GPA) and must
47050 * point to a physically contiguous block of memory.
47052 uint64_t resp_addr;
47054 * 64-bit Host Destination Address.
47055 * This is the host address where the directory will be written.
47057 uint64_t host_dest_addr;
47060 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
47061 struct hwrm_nvm_get_dir_entries_output {
47062 /* The specific error status for the command. */
47063 uint16_t error_code;
47064 /* The HWRM command request type. */
47066 /* The sequence ID from the original command. */
47068 /* The length of the response data in number of bytes. */
47070 uint8_t unused_0[7];
47072 * This field is used in Output records to indicate that the output
47073 * is completely written to RAM. This field should be read as '1'
47074 * to indicate that the output has been completely written.
47075 * When writing a command completion or response to an internal processor,
47076 * the order of writes has to be such that this field is written last.
47081 /*************************
47082 * hwrm_nvm_get_dir_info *
47083 *************************/
47086 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
47087 struct hwrm_nvm_get_dir_info_input {
47088 /* The HWRM command request type. */
47091 * The completion ring to send the completion event on. This should
47092 * be the NQ ID returned from the `nq_alloc` HWRM command.
47094 uint16_t cmpl_ring;
47096 * The sequence ID is used by the driver for tracking multiple
47097 * commands. This ID is treated as opaque data by the firmware and
47098 * the value is returned in the `hwrm_resp_hdr` upon completion.
47102 * The target ID of the command:
47103 * * 0x0-0xFFF8 - The function ID
47104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47105 * * 0xFFFD - Reserved for user-space HWRM interface
47108 uint16_t target_id;
47110 * A physical address pointer pointing to a host buffer that the
47111 * command's response data will be written. This can be either a host
47112 * physical address (HPA) or a guest physical address (GPA) and must
47113 * point to a physically contiguous block of memory.
47115 uint64_t resp_addr;
47118 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
47119 struct hwrm_nvm_get_dir_info_output {
47120 /* The specific error status for the command. */
47121 uint16_t error_code;
47122 /* The HWRM command request type. */
47124 /* The sequence ID from the original command. */
47126 /* The length of the response data in number of bytes. */
47128 /* Number of directory entries in the directory. */
47130 /* Size of each directory entry, in bytes. */
47131 uint32_t entry_length;
47132 uint8_t unused_0[7];
47134 * This field is used in Output records to indicate that the output
47135 * is completely written to RAM. This field should be read as '1'
47136 * to indicate that the output has been completely written.
47137 * When writing a command completion or response to an internal processor,
47138 * the order of writes has to be such that this field is written last.
47143 /******************
47145 ******************/
47148 /* hwrm_nvm_write_input (size:384b/48B) */
47149 struct hwrm_nvm_write_input {
47150 /* The HWRM command request type. */
47153 * The completion ring to send the completion event on. This should
47154 * be the NQ ID returned from the `nq_alloc` HWRM command.
47156 uint16_t cmpl_ring;
47158 * The sequence ID is used by the driver for tracking multiple
47159 * commands. This ID is treated as opaque data by the firmware and
47160 * the value is returned in the `hwrm_resp_hdr` upon completion.
47164 * The target ID of the command:
47165 * * 0x0-0xFFF8 - The function ID
47166 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47167 * * 0xFFFD - Reserved for user-space HWRM interface
47170 uint16_t target_id;
47172 * A physical address pointer pointing to a host buffer that the
47173 * command's response data will be written. This can be either a host
47174 * physical address (HPA) or a guest physical address (GPA) and must
47175 * point to a physically contiguous block of memory.
47177 uint64_t resp_addr;
47179 * 64-bit Host Source Address.
47180 * This is where the source data is.
47182 uint64_t host_src_addr;
47184 * The Directory Entry Type (valid values are defined in the
47185 * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
47189 * Directory ordinal.
47190 * The 0-based instance of the combined Directory Entry Type and Extension.
47192 uint16_t dir_ordinal;
47193 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
47195 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
47198 * Length of data to write, in bytes.May be
47199 * less than or equal to the allocated size for the directory entry.
47200 * The data length stored in the directory entry will be updated to
47201 * reflect this value once the write is complete.
47203 uint32_t dir_data_length;
47208 * When this bit is '1', the original active image
47209 * will not be removed. TBD: what purpose is this?
47211 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
47214 * The requested length of the allocated NVM for the item, in bytes.
47215 * This value may be greater than or equal to the specified data length (dir_data_length).
47216 * If this value is less than the specified data length, it will be ignored.
47217 * The response will contain the actual allocated item length, which may
47218 * be greater than the requested item length.
47219 * The purpose for allocating more than the required number of bytes for
47220 * an item's data is to pre-allocate extra storage (padding) to accommodate
47221 * the potential future growth of an item (e.g. upgraded firmware with
47222 * a size increase, log growth, expanded configuration data).
47224 uint32_t dir_item_length;
47228 /* hwrm_nvm_write_output (size:128b/16B) */
47229 struct hwrm_nvm_write_output {
47230 /* The specific error status for the command. */
47231 uint16_t error_code;
47232 /* The HWRM command request type. */
47234 /* The sequence ID from the original command. */
47236 /* The length of the response data in number of bytes. */
47239 * Length of the allocated NVM for the item, in bytes. The value may be
47240 * greater than or equal to the specified data length or the requested item length.
47241 * The actual item length used when creating a new directory entry will
47242 * be a multiple of an NVM block size.
47244 uint32_t dir_item_length;
47245 /* The directory index of the created or modified item. */
47249 * This field is used in Output records to indicate that the output
47250 * is completely written to RAM. This field should be read as '1'
47251 * to indicate that the output has been completely written.
47252 * When writing a command completion or response to an internal processor,
47253 * the order of writes has to be such that this field is written last.
47258 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
47259 struct hwrm_nvm_write_cmd_err {
47261 * command specific error codes that goes to
47262 * the cmd_err field in Common HWRM Error Response.
47265 /* Unknown error */
47266 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
47267 /* Unable to complete operation due to fragmentation */
47268 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
47269 /* nvm is completely full. */
47270 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
47271 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
47272 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
47273 uint8_t unused_0[7];
47276 /*******************
47277 * hwrm_nvm_modify *
47278 *******************/
47281 /* hwrm_nvm_modify_input (size:320b/40B) */
47282 struct hwrm_nvm_modify_input {
47283 /* The HWRM command request type. */
47286 * The completion ring to send the completion event on. This should
47287 * be the NQ ID returned from the `nq_alloc` HWRM command.
47289 uint16_t cmpl_ring;
47291 * The sequence ID is used by the driver for tracking multiple
47292 * commands. This ID is treated as opaque data by the firmware and
47293 * the value is returned in the `hwrm_resp_hdr` upon completion.
47297 * The target ID of the command:
47298 * * 0x0-0xFFF8 - The function ID
47299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47300 * * 0xFFFD - Reserved for user-space HWRM interface
47303 uint16_t target_id;
47305 * A physical address pointer pointing to a host buffer that the
47306 * command's response data will be written. This can be either a host
47307 * physical address (HPA) or a guest physical address (GPA) and must
47308 * point to a physically contiguous block of memory.
47310 uint64_t resp_addr;
47312 * 64-bit Host Source Address.
47313 * This is where the modified data is.
47315 uint64_t host_src_addr;
47316 /* 16-bit directory entry index. */
47320 * This flag indicates the sender wants to modify a continuous NVRAM
47321 * area using a batch of this HWRM requests. The offset of a request
47322 * must be continuous to the end of previous request's. Firmware does
47323 * not update the directory entry until receiving the last request,
47324 * which is indicated by the batch_last flag.
47325 * This flag is set usually when a sender does not have a block of
47326 * memory that is big enough to hold the entire NVRAM data for send
47329 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
47331 * This flag can be used only when the batch_mode flag is set.
47332 * It indicates this request is the last of batch requests.
47334 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
47335 /* 32-bit NVRAM byte-offset to modify content from. */
47338 * Length of data to be modified, in bytes. The length shall
47342 uint8_t unused_1[4];
47345 /* hwrm_nvm_modify_output (size:128b/16B) */
47346 struct hwrm_nvm_modify_output {
47347 /* The specific error status for the command. */
47348 uint16_t error_code;
47349 /* The HWRM command request type. */
47351 /* The sequence ID from the original command. */
47353 /* The length of the response data in number of bytes. */
47355 uint8_t unused_0[7];
47357 * This field is used in Output records to indicate that the output
47358 * is completely written to RAM. This field should be read as '1'
47359 * to indicate that the output has been completely written.
47360 * When writing a command completion or response to an internal processor,
47361 * the order of writes has to be such that this field is written last.
47366 /***************************
47367 * hwrm_nvm_find_dir_entry *
47368 ***************************/
47371 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
47372 struct hwrm_nvm_find_dir_entry_input {
47373 /* The HWRM command request type. */
47376 * The completion ring to send the completion event on. This should
47377 * be the NQ ID returned from the `nq_alloc` HWRM command.
47379 uint16_t cmpl_ring;
47381 * The sequence ID is used by the driver for tracking multiple
47382 * commands. This ID is treated as opaque data by the firmware and
47383 * the value is returned in the `hwrm_resp_hdr` upon completion.
47387 * The target ID of the command:
47388 * * 0x0-0xFFF8 - The function ID
47389 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47390 * * 0xFFFD - Reserved for user-space HWRM interface
47393 uint16_t target_id;
47395 * A physical address pointer pointing to a host buffer that the
47396 * command's response data will be written. This can be either a host
47397 * physical address (HPA) or a guest physical address (GPA) and must
47398 * point to a physically contiguous block of memory.
47400 uint64_t resp_addr;
47403 * This bit must be '1' for the dir_idx_valid field to be
47406 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
47408 /* Directory Entry Index */
47410 /* Directory Entry (Image) Type */
47413 * Directory ordinal.
47414 * The instance of this Directory Type
47416 uint16_t dir_ordinal;
47417 /* The Directory Entry Extension flags. */
47419 /* This value indicates the search option using dir_ordinal. */
47420 uint8_t opt_ordinal;
47421 /* This value indicates the search option using dir_ordinal. */
47422 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
47423 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
47424 /* Equal to specified ordinal value. */
47425 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
47426 /* Greater than or equal to specified ordinal value */
47427 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
47428 /* Greater than specified ordinal value */
47429 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
47430 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
47431 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
47432 uint8_t unused_0[3];
47435 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
47436 struct hwrm_nvm_find_dir_entry_output {
47437 /* The specific error status for the command. */
47438 uint16_t error_code;
47439 /* The HWRM command request type. */
47441 /* The sequence ID from the original command. */
47443 /* The length of the response data in number of bytes. */
47445 /* Allocated NVRAM for this directory entry, in bytes. */
47446 uint32_t dir_item_length;
47447 /* Size of the stored data for this directory entry, in bytes. */
47448 uint32_t dir_data_length;
47450 * Firmware version.
47451 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
47454 /* Directory ordinal. */
47455 uint16_t dir_ordinal;
47456 /* Directory Entry Index */
47458 uint8_t unused_0[7];
47460 * This field is used in Output records to indicate that the output
47461 * is completely written to RAM. This field should be read as '1'
47462 * to indicate that the output has been completely written.
47463 * When writing a command completion or response to an internal processor,
47464 * the order of writes has to be such that this field is written last.
47469 /****************************
47470 * hwrm_nvm_erase_dir_entry *
47471 ****************************/
47474 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
47475 struct hwrm_nvm_erase_dir_entry_input {
47476 /* The HWRM command request type. */
47479 * The completion ring to send the completion event on. This should
47480 * be the NQ ID returned from the `nq_alloc` HWRM command.
47482 uint16_t cmpl_ring;
47484 * The sequence ID is used by the driver for tracking multiple
47485 * commands. This ID is treated as opaque data by the firmware and
47486 * the value is returned in the `hwrm_resp_hdr` upon completion.
47490 * The target ID of the command:
47491 * * 0x0-0xFFF8 - The function ID
47492 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47493 * * 0xFFFD - Reserved for user-space HWRM interface
47496 uint16_t target_id;
47498 * A physical address pointer pointing to a host buffer that the
47499 * command's response data will be written. This can be either a host
47500 * physical address (HPA) or a guest physical address (GPA) and must
47501 * point to a physically contiguous block of memory.
47503 uint64_t resp_addr;
47504 /* Directory Entry Index */
47506 uint8_t unused_0[6];
47509 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
47510 struct hwrm_nvm_erase_dir_entry_output {
47511 /* The specific error status for the command. */
47512 uint16_t error_code;
47513 /* The HWRM command request type. */
47515 /* The sequence ID from the original command. */
47517 /* The length of the response data in number of bytes. */
47519 uint8_t unused_0[7];
47521 * This field is used in Output records to indicate that the output
47522 * is completely written to RAM. This field should be read as '1'
47523 * to indicate that the output has been completely written.
47524 * When writing a command completion or response to an internal processor,
47525 * the order of writes has to be such that this field is written last.
47530 /*************************
47531 * hwrm_nvm_get_dev_info *
47532 *************************/
47535 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
47536 struct hwrm_nvm_get_dev_info_input {
47537 /* The HWRM command request type. */
47540 * The completion ring to send the completion event on. This should
47541 * be the NQ ID returned from the `nq_alloc` HWRM command.
47543 uint16_t cmpl_ring;
47545 * The sequence ID is used by the driver for tracking multiple
47546 * commands. This ID is treated as opaque data by the firmware and
47547 * the value is returned in the `hwrm_resp_hdr` upon completion.
47551 * The target ID of the command:
47552 * * 0x0-0xFFF8 - The function ID
47553 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47554 * * 0xFFFD - Reserved for user-space HWRM interface
47557 uint16_t target_id;
47559 * A physical address pointer pointing to a host buffer that the
47560 * command's response data will be written. This can be either a host
47561 * physical address (HPA) or a guest physical address (GPA) and must
47562 * point to a physically contiguous block of memory.
47564 uint64_t resp_addr;
47567 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */
47568 struct hwrm_nvm_get_dev_info_output {
47569 /* The specific error status for the command. */
47570 uint16_t error_code;
47571 /* The HWRM command request type. */
47573 /* The sequence ID from the original command. */
47575 /* The length of the response data in number of bytes. */
47577 /* Manufacturer ID. */
47578 uint16_t manufacturer_id;
47580 uint16_t device_id;
47581 /* Sector size of the NVRAM device. */
47582 uint32_t sector_size;
47583 /* Total size, in bytes of the NVRAM device. */
47584 uint32_t nvram_size;
47585 uint32_t reserved_size;
47587 * Available size that can be used, in bytes. Available size is the
47588 * NVRAM size take away the used size and reserved size.
47590 uint32_t available_size;
47591 /* This field represents the major version of NVM cfg */
47592 uint8_t nvm_cfg_ver_maj;
47593 /* This field represents the minor version of NVM cfg */
47594 uint8_t nvm_cfg_ver_min;
47595 /* This field represents the update version of NVM cfg */
47596 uint8_t nvm_cfg_ver_upd;
47599 * If set to 1, firmware will provide various firmware version
47600 * information stored in the flash.
47602 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID \
47605 * This field represents the board package name stored in the flash.
47606 * (ASCII chars with NULL at the end).
47610 * This field represents the major version of HWRM firmware, stored in
47613 uint16_t hwrm_fw_major;
47615 * This field represents the minor version of HWRM firmware, stored in
47618 uint16_t hwrm_fw_minor;
47620 * This field represents the build version of HWRM firmware, stored in
47623 uint16_t hwrm_fw_build;
47625 * This field can be used to represent firmware branches or customer
47626 * specific releases tied to a specific (major, minor, build) version
47627 * of the HWRM firmware.
47629 uint16_t hwrm_fw_patch;
47631 * This field represents the major version of mgmt firmware, stored in
47634 uint16_t mgmt_fw_major;
47636 * This field represents the minor version of mgmt firmware, stored in
47639 uint16_t mgmt_fw_minor;
47641 * This field represents the build version of mgmt firmware, stored in
47644 uint16_t mgmt_fw_build;
47646 * This field can be used to represent firmware branches or customer
47647 * specific releases tied to a specific (major, minor, build) version
47648 * of the mgmt firmware.
47650 uint16_t mgmt_fw_patch;
47652 * This field represents the major version of roce firmware, stored in
47655 uint16_t roce_fw_major;
47657 * This field represents the minor version of roce firmware, stored in
47660 uint16_t roce_fw_minor;
47662 * This field represents the build version of roce firmware, stored in
47665 uint16_t roce_fw_build;
47667 * This field can be used to represent firmware branches or customer
47668 * specific releases tied to a specific (major, minor, build) version
47669 * of the roce firmware.
47671 uint16_t roce_fw_patch;
47672 uint8_t unused_0[7];
47674 * This field is used in Output records to indicate that the output
47675 * is completely written to RAM. This field should be read as '1'
47676 * to indicate that the output has been completely written.
47677 * When writing a command completion or response to an internal processor,
47678 * the order of writes has to be such that this field is written last.
47683 /**************************
47684 * hwrm_nvm_mod_dir_entry *
47685 **************************/
47688 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
47689 struct hwrm_nvm_mod_dir_entry_input {
47690 /* The HWRM command request type. */
47693 * The completion ring to send the completion event on. This should
47694 * be the NQ ID returned from the `nq_alloc` HWRM command.
47696 uint16_t cmpl_ring;
47698 * The sequence ID is used by the driver for tracking multiple
47699 * commands. This ID is treated as opaque data by the firmware and
47700 * the value is returned in the `hwrm_resp_hdr` upon completion.
47704 * The target ID of the command:
47705 * * 0x0-0xFFF8 - The function ID
47706 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47707 * * 0xFFFD - Reserved for user-space HWRM interface
47710 uint16_t target_id;
47712 * A physical address pointer pointing to a host buffer that the
47713 * command's response data will be written. This can be either a host
47714 * physical address (HPA) or a guest physical address (GPA) and must
47715 * point to a physically contiguous block of memory.
47717 uint64_t resp_addr;
47720 * This bit must be '1' for the checksum field to be
47723 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
47724 /* Directory Entry Index */
47727 * Directory ordinal.
47728 * The (0-based) instance of this Directory Type.
47730 uint16_t dir_ordinal;
47732 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for
47733 * extension flag definitions).
47736 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
47739 * If valid, then this field updates the checksum
47740 * value of the content in the directory entry.
47745 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
47746 struct hwrm_nvm_mod_dir_entry_output {
47747 /* The specific error status for the command. */
47748 uint16_t error_code;
47749 /* The HWRM command request type. */
47751 /* The sequence ID from the original command. */
47753 /* The length of the response data in number of bytes. */
47755 uint8_t unused_0[7];
47757 * This field is used in Output records to indicate that the output
47758 * is completely written to RAM. This field should be read as '1'
47759 * to indicate that the output has been completely written.
47760 * When writing a command completion or response to an internal processor,
47761 * the order of writes has to be such that this field is written last.
47766 /**************************
47767 * hwrm_nvm_verify_update *
47768 **************************/
47771 /* hwrm_nvm_verify_update_input (size:192b/24B) */
47772 struct hwrm_nvm_verify_update_input {
47773 /* The HWRM command request type. */
47776 * The completion ring to send the completion event on. This should
47777 * be the NQ ID returned from the `nq_alloc` HWRM command.
47779 uint16_t cmpl_ring;
47781 * The sequence ID is used by the driver for tracking multiple
47782 * commands. This ID is treated as opaque data by the firmware and
47783 * the value is returned in the `hwrm_resp_hdr` upon completion.
47787 * The target ID of the command:
47788 * * 0x0-0xFFF8 - The function ID
47789 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47790 * * 0xFFFD - Reserved for user-space HWRM interface
47793 uint16_t target_id;
47795 * A physical address pointer pointing to a host buffer that the
47796 * command's response data will be written. This can be either a host
47797 * physical address (HPA) or a guest physical address (GPA) and must
47798 * point to a physically contiguous block of memory.
47800 uint64_t resp_addr;
47801 /* Directory Entry Type, to be verified. */
47804 * Directory ordinal.
47805 * The instance of the Directory Type to be verified.
47807 uint16_t dir_ordinal;
47809 * The Directory Entry Extension flags.
47810 * The "UPDATE" extension flag must be set in this value.
47811 * A corresponding directory entry with the same type and ordinal values but *without*
47812 * the "UPDATE" extension flag must also exist. The other flags of the extension must
47813 * be identical between the active and update entries.
47816 uint8_t unused_0[2];
47819 /* hwrm_nvm_verify_update_output (size:128b/16B) */
47820 struct hwrm_nvm_verify_update_output {
47821 /* The specific error status for the command. */
47822 uint16_t error_code;
47823 /* The HWRM command request type. */
47825 /* The sequence ID from the original command. */
47827 /* The length of the response data in number of bytes. */
47829 uint8_t unused_0[7];
47831 * This field is used in Output records to indicate that the output
47832 * is completely written to RAM. This field should be read as '1'
47833 * to indicate that the output has been completely written.
47834 * When writing a command completion or response to an internal processor,
47835 * the order of writes has to be such that this field is written last.
47840 /***************************
47841 * hwrm_nvm_install_update *
47842 ***************************/
47845 /* hwrm_nvm_install_update_input (size:192b/24B) */
47846 struct hwrm_nvm_install_update_input {
47847 /* The HWRM command request type. */
47850 * The completion ring to send the completion event on. This should
47851 * be the NQ ID returned from the `nq_alloc` HWRM command.
47853 uint16_t cmpl_ring;
47855 * The sequence ID is used by the driver for tracking multiple
47856 * commands. This ID is treated as opaque data by the firmware and
47857 * the value is returned in the `hwrm_resp_hdr` upon completion.
47861 * The target ID of the command:
47862 * * 0x0-0xFFF8 - The function ID
47863 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47864 * * 0xFFFD - Reserved for user-space HWRM interface
47867 uint16_t target_id;
47869 * A physical address pointer pointing to a host buffer that the
47870 * command's response data will be written. This can be either a host
47871 * physical address (HPA) or a guest physical address (GPA) and must
47872 * point to a physically contiguous block of memory.
47874 uint64_t resp_addr;
47876 * Installation type. If the value 3 through 0xffff is used,
47877 * only packaged items with that type value will be installed and
47878 * conditional installation directives for those packaged items
47879 * will be over-ridden (i.e. 'create' or 'replace' will be treated
47882 uint32_t install_type;
47884 * Perform a normal package installation. Conditional installation
47885 * directives (e.g. 'create' and 'replace') of packaged items
47886 * will be followed.
47888 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
47890 * Install all packaged items regardless of installation directive
47891 * (i.e. treat all packaged items as though they have an installation
47892 * directive of 'install').
47894 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
47895 UINT32_C(0xffffffff)
47896 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
47897 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
47899 /* If set to 1, then securely erase all unused locations in persistent storage. */
47900 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
47903 * If set to 1, then unspecified images, images not in the package file,
47904 * will be safely deleted.
47905 * When combined with erase_unused_space then unspecified images will be
47908 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
47911 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
47912 * Allow additional time for this command to complete if this bit is set to 1.
47914 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
47917 * If set to 1, FW will verify the package in the "UPDATE" NVM item
47918 * without installing it. This flag is for FW internal use only.
47919 * Users should not set this flag. The request will otherwise fail.
47921 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
47923 uint8_t unused_0[2];
47926 /* hwrm_nvm_install_update_output (size:192b/24B) */
47927 struct hwrm_nvm_install_update_output {
47928 /* The specific error status for the command. */
47929 uint16_t error_code;
47930 /* The HWRM command request type. */
47932 /* The sequence ID from the original command. */
47934 /* The length of the response data in number of bytes. */
47937 * Bit-mask of successfully installed items.
47938 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
47939 * A value of 0 indicates that no items were successfully installed.
47941 uint64_t installed_items;
47942 /* result is 8 b */
47944 /* There was no problem with the package installation. */
47945 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
47946 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
47947 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
47948 /* problem_item is 8 b */
47949 uint8_t problem_item;
47950 /* There was no problem with any packaged items. */
47951 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
47953 /* There was a problem with the NVM package itself. */
47954 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
47956 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
47957 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
47958 /* reset_required is 8 b */
47959 uint8_t reset_required;
47961 * No reset is required for installed/updated firmware or
47962 * microcode to take effect.
47964 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
47967 * A PCIe reset (e.g. system reboot) is
47968 * required for newly installed/updated firmware or
47969 * microcode to take effect.
47971 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
47974 * A controller power reset (e.g. system power-cycle) is
47975 * required for newly installed/updated firmware or
47976 * microcode to take effect. Some newly installed/updated
47977 * firmware or microcode may still take effect upon the
47980 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
47982 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
47983 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
47984 uint8_t unused_0[4];
47986 * This field is used in Output records to indicate that the output
47987 * is completely written to RAM. This field should be read as '1'
47988 * to indicate that the output has been completely written.
47989 * When writing a command completion or response to an internal processor,
47990 * the order of writes has to be such that this field is written last.
47995 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
47996 struct hwrm_nvm_install_update_cmd_err {
47998 * command specific error codes that goes to
47999 * the cmd_err field in Common HWRM Error Response.
48002 /* Unknown error */
48003 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48004 /* Unable to complete operation due to fragmentation */
48005 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
48006 /* nvm is completely full. */
48007 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
48008 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
48009 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
48010 uint8_t unused_0[7];
48013 /******************
48015 ******************/
48018 /* hwrm_nvm_flush_input (size:128b/16B) */
48019 struct hwrm_nvm_flush_input {
48020 /* The HWRM command request type. */
48023 * The completion ring to send the completion event on. This should
48024 * be the NQ ID returned from the `nq_alloc` HWRM command.
48026 uint16_t cmpl_ring;
48028 * The sequence ID is used by the driver for tracking multiple
48029 * commands. This ID is treated as opaque data by the firmware and
48030 * the value is returned in the `hwrm_resp_hdr` upon completion.
48034 * The target ID of the command:
48035 * * 0x0-0xFFF8 - The function ID
48036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48037 * * 0xFFFD - Reserved for user-space HWRM interface
48040 uint16_t target_id;
48042 * A physical address pointer pointing to a host buffer that the
48043 * command's response data will be written. This can be either a host
48044 * physical address (HPA) or a guest physical address (GPA) and must
48045 * point to a physically contiguous block of memory.
48047 uint64_t resp_addr;
48050 /* hwrm_nvm_flush_output (size:128b/16B) */
48051 struct hwrm_nvm_flush_output {
48052 /* The specific error status for the command. */
48053 uint16_t error_code;
48054 /* The HWRM command request type. */
48056 /* The sequence ID from the original command. */
48058 /* The length of the response data in number of bytes. */
48060 uint8_t unused_0[7];
48062 * This field is used in Output records to indicate that the output
48063 * is completely written to RAM. This field should be read as '1'
48064 * to indicate that the output has been completely written.
48065 * When writing a command completion or response to an internal processor,
48066 * the order of writes has to be such that this field is written last.
48071 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
48072 struct hwrm_nvm_flush_cmd_err {
48074 * command specific error codes that goes to
48075 * the cmd_err field in Common HWRM Error Response.
48078 /* Unknown error */
48079 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48080 /* flush could not be performed */
48081 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
48082 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
48083 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
48084 uint8_t unused_0[7];
48087 /*************************
48088 * hwrm_nvm_get_variable *
48089 *************************/
48092 /* hwrm_nvm_get_variable_input (size:320b/40B) */
48093 struct hwrm_nvm_get_variable_input {
48094 /* The HWRM command request type. */
48097 * The completion ring to send the completion event on. This should
48098 * be the NQ ID returned from the `nq_alloc` HWRM command.
48100 uint16_t cmpl_ring;
48102 * The sequence ID is used by the driver for tracking multiple
48103 * commands. This ID is treated as opaque data by the firmware and
48104 * the value is returned in the `hwrm_resp_hdr` upon completion.
48108 * The target ID of the command:
48109 * * 0x0-0xFFF8 - The function ID
48110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48111 * * 0xFFFD - Reserved for user-space HWRM interface
48114 uint16_t target_id;
48116 * A physical address pointer pointing to a host buffer that the
48117 * command's response data will be written. This can be either a host
48118 * physical address (HPA) or a guest physical address (GPA) and must
48119 * point to a physically contiguous block of memory.
48121 uint64_t resp_addr;
48123 * This is the host address where
48124 * nvm variable will be stored
48126 uint64_t dest_data_addr;
48127 /* size of data in bits */
48129 /* nvm cfg option number */
48130 uint16_t option_num;
48132 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
48134 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
48136 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
48137 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
48139 * Number of dimensions for this nvm configuration variable.
48140 * This value indicates how many of the indexN values to use.
48141 * A value of 0 means that none of the indexN values are valid.
48142 * A value of 1 requires at index0 is valued, a value of 2
48143 * requires that index0 and index1 are valid, and so forth
48145 uint16_t dimensions;
48146 /* index for the 1st dimensions */
48148 /* index for the 2nd dimensions */
48150 /* index for the 3rd dimensions */
48152 /* index for the 4th dimensions */
48156 * When this bit is set to 1, the factory default value will be returned,
48157 * 0 returns the operational value.
48159 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
48164 /* hwrm_nvm_get_variable_output (size:128b/16B) */
48165 struct hwrm_nvm_get_variable_output {
48166 /* The specific error status for the command. */
48167 uint16_t error_code;
48168 /* The HWRM command request type. */
48170 /* The sequence ID from the original command. */
48172 /* The length of the response data in number of bytes. */
48174 /* size of data of the actual variable retrieved in bits */
48177 * option_num is the option number for the data retrieved. It is possible in the
48178 * future that the option number returned would be different than requested. This
48179 * condition could occur if an option is deprecated and a new option id is defined
48180 * with similar characteristics, but has a slightly different definition. This
48181 * also makes it convenient for the caller to identify the variable result with
48182 * the option id from the response.
48184 uint16_t option_num;
48186 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
48188 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
48190 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
48191 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
48192 uint8_t unused_0[3];
48194 * This field is used in Output records to indicate that the output
48195 * is completely written to RAM. This field should be read as '1'
48196 * to indicate that the output has been completely written.
48197 * When writing a command completion or response to an internal processor,
48198 * the order of writes has to be such that this field is written last.
48203 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
48204 struct hwrm_nvm_get_variable_cmd_err {
48206 * command specific error codes that goes to
48207 * the cmd_err field in Common HWRM Error Response.
48210 /* Unknown error */
48211 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48212 /* variable does not exist */
48213 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
48214 /* configuration is corrupted and the variable cannot be saved */
48215 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
48216 /* length specified is too small */
48217 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
48218 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
48219 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
48220 uint8_t unused_0[7];
48223 /*************************
48224 * hwrm_nvm_set_variable *
48225 *************************/
48228 /* hwrm_nvm_set_variable_input (size:320b/40B) */
48229 struct hwrm_nvm_set_variable_input {
48230 /* The HWRM command request type. */
48233 * The completion ring to send the completion event on. This should
48234 * be the NQ ID returned from the `nq_alloc` HWRM command.
48236 uint16_t cmpl_ring;
48238 * The sequence ID is used by the driver for tracking multiple
48239 * commands. This ID is treated as opaque data by the firmware and
48240 * the value is returned in the `hwrm_resp_hdr` upon completion.
48244 * The target ID of the command:
48245 * * 0x0-0xFFF8 - The function ID
48246 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48247 * * 0xFFFD - Reserved for user-space HWRM interface
48250 uint16_t target_id;
48252 * A physical address pointer pointing to a host buffer that the
48253 * command's response data will be written. This can be either a host
48254 * physical address (HPA) or a guest physical address (GPA) and must
48255 * point to a physically contiguous block of memory.
48257 uint64_t resp_addr;
48259 * This is the host address where
48260 * nvm variable will be copied from
48262 uint64_t src_data_addr;
48263 /* size of data in bits */
48265 /* nvm cfg option number */
48266 uint16_t option_num;
48268 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
48270 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
48272 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
48273 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
48275 * Number of dimensions for this nvm configuration variable.
48276 * This value indicates how many of the indexN values to use.
48277 * A value of 0 means that none of the indexN values are valid.
48278 * A value of 1 requires at index0 is valued, a value of 2
48279 * requires that index0 and index1 are valid, and so forth
48281 uint16_t dimensions;
48282 /* index for the 1st dimensions */
48284 /* index for the 2nd dimensions */
48286 /* index for the 3rd dimensions */
48288 /* index for the 4th dimensions */
48292 * When this bit is 1, flush internal cache after this write operation
48293 * (see hwrm_nvm_flush command.)
48295 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
48297 /* encryption method */
48298 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
48300 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
48301 /* No encryption. */
48302 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
48303 (UINT32_C(0x0) << 1)
48304 /* one-way encryption. */
48305 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
48306 (UINT32_C(0x1) << 1)
48307 /* symmetric AES256 encryption. */
48308 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
48309 (UINT32_C(0x2) << 1)
48310 /* SHA1 digest appended to plaintext contents, for authentication */
48311 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
48312 (UINT32_C(0x3) << 1)
48313 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
48314 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
48315 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
48317 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
48318 /* When this bit is 1, update the factory default region */
48319 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
48324 /* hwrm_nvm_set_variable_output (size:128b/16B) */
48325 struct hwrm_nvm_set_variable_output {
48326 /* The specific error status for the command. */
48327 uint16_t error_code;
48328 /* The HWRM command request type. */
48330 /* The sequence ID from the original command. */
48332 /* The length of the response data in number of bytes. */
48334 uint8_t unused_0[7];
48336 * This field is used in Output records to indicate that the output
48337 * is completely written to RAM. This field should be read as '1'
48338 * to indicate that the output has been completely written.
48339 * When writing a command completion or response to an internal processor,
48340 * the order of writes has to be such that this field is written last.
48345 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
48346 struct hwrm_nvm_set_variable_cmd_err {
48348 * command specific error codes that goes to
48349 * the cmd_err field in Common HWRM Error Response.
48352 /* Unknown error */
48353 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48354 /* variable does not exist */
48355 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
48356 /* configuration is corrupted and the variable cannot be saved */
48357 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
48358 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
48359 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
48360 uint8_t unused_0[7];
48363 /****************************
48364 * hwrm_nvm_validate_option *
48365 ****************************/
48368 /* hwrm_nvm_validate_option_input (size:320b/40B) */
48369 struct hwrm_nvm_validate_option_input {
48370 /* The HWRM command request type. */
48373 * The completion ring to send the completion event on. This should
48374 * be the NQ ID returned from the `nq_alloc` HWRM command.
48376 uint16_t cmpl_ring;
48378 * The sequence ID is used by the driver for tracking multiple
48379 * commands. This ID is treated as opaque data by the firmware and
48380 * the value is returned in the `hwrm_resp_hdr` upon completion.
48384 * The target ID of the command:
48385 * * 0x0-0xFFF8 - The function ID
48386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48387 * * 0xFFFD - Reserved for user-space HWRM interface
48390 uint16_t target_id;
48392 * A physical address pointer pointing to a host buffer that the
48393 * command's response data will be written. This can be either a host
48394 * physical address (HPA) or a guest physical address (GPA) and must
48395 * point to a physically contiguous block of memory.
48397 uint64_t resp_addr;
48399 * This is the host address where
48400 * nvm variable will be copied from
48402 uint64_t src_data_addr;
48403 /* size of data in bits */
48405 /* nvm cfg option number */
48406 uint16_t option_num;
48408 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
48411 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
48413 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
48414 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
48416 * Number of dimensions for this nvm configuration variable.
48417 * This value indicates how many of the indexN values to use.
48418 * A value of 0 means that none of the indexN values are valid.
48419 * A value of 1 requires at index0 is valued, a value of 2
48420 * requires that index0 and index1 are valid, and so forth
48422 uint16_t dimensions;
48423 /* index for the 1st dimensions */
48425 /* index for the 2nd dimensions */
48427 /* index for the 3rd dimensions */
48429 /* index for the 4th dimensions */
48431 uint8_t unused_0[2];
48434 /* hwrm_nvm_validate_option_output (size:128b/16B) */
48435 struct hwrm_nvm_validate_option_output {
48436 /* The specific error status for the command. */
48437 uint16_t error_code;
48438 /* The HWRM command request type. */
48440 /* The sequence ID from the original command. */
48442 /* The length of the response data in number of bytes. */
48445 /* indicates that the value provided for the option is not matching with the saved data. */
48446 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
48447 /* indicates that the value provided for the option is matching the saved data. */
48448 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
48449 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
48450 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
48451 uint8_t unused_0[6];
48453 * This field is used in Output records to indicate that the output
48454 * is completely written to RAM. This field should be read as '1'
48455 * to indicate that the output has been completely written.
48456 * When writing a command completion or response to an internal processor,
48457 * the order of writes has to be such that this field is written last.
48462 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
48463 struct hwrm_nvm_validate_option_cmd_err {
48465 * command specific error codes that goes to
48466 * the cmd_err field in Common HWRM Error Response.
48469 /* Unknown error */
48470 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48471 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
48472 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
48473 uint8_t unused_0[7];
48481 /* hwrm_oem_cmd_input (size:1024b/128B) */
48482 struct hwrm_oem_cmd_input {
48483 /* The HWRM command request type. */
48486 * The completion ring to send the completion event on. This should
48487 * be the NQ ID returned from the `nq_alloc` HWRM command.
48489 uint16_t cmpl_ring;
48491 * The sequence ID is used by the driver for tracking multiple
48492 * commands. This ID is treated as opaque data by the firmware and
48493 * the value is returned in the `hwrm_resp_hdr` upon completion.
48497 * The target ID of the command:
48498 * * 0x0-0xFFF8 - The function ID
48499 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48500 * * 0xFFFD - Reserved for user-space HWRM interface
48503 uint16_t target_id;
48505 * A physical address pointer pointing to a host buffer that the
48506 * command's response data will be written. This can be either a host
48507 * physical address (HPA) or a guest physical address (GPA) and must
48508 * point to a physically contiguous block of memory.
48510 uint64_t resp_addr;
48513 /* This field contains the vendor specific command data. */
48514 uint32_t oem_data[26];
48517 /* hwrm_oem_cmd_output (size:768b/96B) */
48518 struct hwrm_oem_cmd_output {
48519 /* The specific error status for the command. */
48520 uint16_t error_code;
48521 /* The HWRM command request type. */
48523 /* The sequence ID from the original command. */
48525 /* The length of the response data in number of bytes. */
48529 /* This field contains the vendor specific response data. */
48530 uint32_t oem_data[18];
48531 uint8_t unused_1[7];
48533 * This field is used in Output records to indicate that the output
48534 * is completely written to RAM. This field should be read as '1'
48535 * to indicate that the output has been completely written.
48536 * When writing a command completion or response to an internal processor,
48537 * the order of writes has to be such that this field is written last.
48544 ******************/
48547 /* hwrm_fw_reset_input (size:192b/24B) */
48548 struct hwrm_fw_reset_input {
48549 /* The HWRM command request type. */
48552 * The completion ring to send the completion event on. This should
48553 * be the NQ ID returned from the `nq_alloc` HWRM command.
48555 uint16_t cmpl_ring;
48557 * The sequence ID is used by the driver for tracking multiple
48558 * commands. This ID is treated as opaque data by the firmware and
48559 * the value is returned in the `hwrm_resp_hdr` upon completion.
48563 * The target ID of the command:
48564 * * 0x0-0xFFF8 - The function ID
48565 * * 0xFFF8-0xFFFE - Reserved for internal processors
48568 uint16_t target_id;
48570 * A physical address pointer pointing to a host buffer that the
48571 * command's response data will be written. This can be either a host
48572 * physical address (HPA) or a guest physical address (GPA) and must
48573 * point to a physically contiguous block of memory.
48575 uint64_t resp_addr;
48576 /* Type of embedded processor. */
48577 uint8_t embedded_proc_type;
48578 /* Boot Processor */
48579 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
48581 /* Management Processor */
48582 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
48584 /* Network control processor */
48585 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
48587 /* RoCE control processor */
48588 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
48591 * Host (in multi-host environment): This is only valid if requester is IPC.
48592 * Reinit host hardware resources and PCIe.
48594 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
48597 * AP processor complex (in multi-host environment).
48598 * Use host_idx to control which core is reset
48600 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
48602 /* Reset all blocks of the chip (including all processors) */
48603 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
48606 * Host (in multi-host environment): This is only valid if requester is IPC.
48607 * Reinit host hardware resources.
48609 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
48611 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
48612 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
48613 /* Type of self reset. */
48614 uint8_t selfrst_status;
48615 /* No Self Reset */
48616 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
48618 /* Self Reset as soon as possible to do so safely */
48619 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
48621 /* Self Reset on PCIe Reset */
48622 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
48624 /* Self Reset immediately after notification to all clients. */
48625 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
48627 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
48628 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
48630 * Indicate which host is being reset. 0 means first host.
48631 * Only valid when embedded_proc_type is host in multihost
48637 * When this bit is '1', then the core firmware initiates
48638 * the reset only after graceful shut down of all registered instances.
48639 * If not, the device will continue with the existing firmware.
48641 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
48642 uint8_t unused_0[4];
48645 /* hwrm_fw_reset_output (size:128b/16B) */
48646 struct hwrm_fw_reset_output {
48647 /* The specific error status for the command. */
48648 uint16_t error_code;
48649 /* The HWRM command request type. */
48651 /* The sequence ID from the original command. */
48653 /* The length of the response data in number of bytes. */
48655 /* Type of self reset. */
48656 uint8_t selfrst_status;
48657 /* No Self Reset */
48658 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
48660 /* Self Reset as soon as possible to do so safely */
48661 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
48663 /* Self Reset on PCIe Reset */
48664 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
48666 /* Self Reset immediately after notification to all clients. */
48667 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
48669 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
48670 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
48671 uint8_t unused_0[6];
48673 * This field is used in Output records to indicate that the output
48674 * is completely written to RAM. This field should be read as '1'
48675 * to indicate that the output has been completely written.
48676 * When writing a command completion or response to an internal processor,
48677 * the order of writes has to be such that this field is written last.
48682 /**********************
48683 * hwrm_port_ts_query *
48684 ***********************/
48687 /* hwrm_port_ts_query_input (size:192b/24B) */
48688 struct hwrm_port_ts_query_input {
48689 /* The HWRM command request type. */
48692 * The completion ring to send the completion event on. This should
48693 * be the NQ ID returned from the `nq_alloc` HWRM command.
48695 uint16_t cmpl_ring;
48697 * The sequence ID is used by the driver for tracking multiple
48698 * commands. This ID is treated as opaque data by the firmware and
48699 * the value is returned in the `hwrm_resp_hdr` upon completion.
48703 * The target ID of the command:
48704 * * 0x0-0xFFF8 - The function ID
48705 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48706 * * 0xFFFD - Reserved for user-space HWRM interface
48709 uint16_t target_id;
48711 * A physical address pointer pointing to a host buffer that the
48712 * command's response data will be written. This can be either a host
48713 * physical address (HPA) or a guest physical address (GPA) and must
48714 * point to a physically contiguous block of memory.
48716 uint64_t resp_addr;
48719 * Enumeration denoting the RX, TX type of the resource.
48720 * This enumeration is used for resources that are similar for both
48721 * TX and RX paths of the chip.
48723 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
48725 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
48727 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
48728 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
48729 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
48731 * If set, the response includes the current value of the free
48734 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
48735 /* Port ID of port that is being queried. */
48737 uint8_t unused_0[2];
48740 /* hwrm_port_ts_query_output (size:192b/24B) */
48741 struct hwrm_port_ts_query_output {
48742 /* The specific error status for the command. */
48743 uint16_t error_code;
48744 /* The HWRM command request type. */
48746 /* The sequence ID from the original command. */
48748 /* The length of the response data in number of bytes. */
48751 * Timestamp value of PTP message captured, or current value of
48752 * free running timer.
48754 uint32_t ptp_msg_ts[2];
48755 /* Sequence ID of the PTP message captured. */
48756 uint16_t ptp_msg_seqid;
48757 uint8_t unused_0[5];
48759 * This field is used in Output records to indicate that the output
48760 * is completely written to RAM. This field should be read as '1'
48761 * to indicate that the output has been completely written.
48762 * When writing a command completion or response to an internal processor,
48763 * the order of writes has to be such that this field is written last.
48769 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
48770 * offset: 0x31001F0). Host software is expected to read from this
48771 * location for a defined signature. If it exists, the software can
48772 * assume the presence of this structure and the validity of the
48773 * FW_STATUS location in the next field.
48775 /* hcomm_status (size:64b/8B) */
48776 struct hcomm_status {
48779 * This field defines the version of the structure. The latest
48780 * version value is 1.
48782 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
48783 #define HCOMM_STATUS_VER_SFT 0
48784 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
48785 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
48787 * This field is to store the signature value to indicate the
48788 * presence of the structure.
48790 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
48791 #define HCOMM_STATUS_SIGNATURE_SFT 8
48792 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
48793 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
48794 uint32_t fw_status_loc;
48795 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
48796 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
48797 /* PCIE configuration space */
48798 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
48800 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
48802 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
48804 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
48805 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
48806 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
48808 * This offset where the fw_status register is located. The value
48809 * is generally 4-byte aligned.
48811 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
48812 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
48814 /* This is the GRC offset where the hcomm_status struct resides. */
48815 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
48817 /**************************
48818 * hwrm_port_phy_i2c_read *
48819 **************************/
48822 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
48823 struct hwrm_port_phy_i2c_read_input {
48824 /* The HWRM command request type. */
48827 * The completion ring to send the completion event on. This should
48828 * be the NQ ID returned from the `nq_alloc` HWRM command.
48830 uint16_t cmpl_ring;
48832 * The sequence ID is used by the driver for tracking multiple
48833 * commands. This ID is treated as opaque data by the firmware and
48834 * the value is returned in the `hwrm_resp_hdr` upon completion.
48838 * The target ID of the command:
48839 * * 0x0-0xFFF8 - The function ID
48840 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48841 * * 0xFFFD - Reserved for user-space HWRM interface
48844 uint16_t target_id;
48846 * A physical address pointer pointing to a host buffer that the
48847 * command's response data will be written. This can be either a host
48848 * physical address (HPA) or a guest physical address (GPA) and must
48849 * point to a physically contiguous block of memory.
48851 uint64_t resp_addr;
48855 * This bit must be '1' for the page_offset field to be
48858 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET 0x1UL
48859 /* Port ID of port. */
48861 /* 8-bit I2C slave address. */
48862 uint8_t i2c_slave_addr;
48864 /* The page number that is being accessed over I2C. */
48865 uint16_t page_number;
48866 /* Offset within the page that is being accessed over I2C. */
48867 uint16_t page_offset;
48869 * Length of data to read, in bytes starting at the offset
48870 * specified above. If the offset is not specified, then
48871 * the data shall be read from the beginning of the page.
48873 uint8_t data_length;
48874 uint8_t unused_1[7];
48877 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
48878 struct hwrm_port_phy_i2c_read_output {
48879 /* The specific error status for the command. */
48880 uint16_t error_code;
48881 /* The HWRM command request type. */
48883 /* The sequence ID from the original command. */
48885 /* The length of the response data in number of bytes. */
48887 /* Up to 64B of data. */
48889 uint8_t unused_0[7];
48891 * This field is used in Output records to indicate that the output
48892 * is completely written to RAM. This field should be read as '1'
48893 * to indicate that the output has been completely written.
48894 * When writing a command completion or response to an internal processor,
48895 * the order of writes has to be such that this field is written last.
48899 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */