1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2020 Broadcom Inc.
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31 * * 0xFFFD - Reserved for user-space HWRM interface
36 * A physical address pointer pointing to a host buffer that the
37 * command's response data will be written. This can be either a host
38 * physical address (HPA) or a guest physical address (GPA) and must
39 * point to a physically contiguous block of memory.
44 /* This is the HWRM response header. */
45 /* hwrm_resp_hdr (size:64b/8B) */
46 struct hwrm_resp_hdr {
47 /* The specific error status for the command. */
49 /* The HWRM command request type. */
51 /* The sequence ID from the original command. */
53 /* The length of the response data in number of bytes. */
58 * TLV encapsulated message. Use the TLV type field of the
59 * TLV to determine the type of message encapsulated.
61 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
62 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
65 /* HWRM request message */
66 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
67 /* HWRM response message */
68 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
69 /* RoCE slow path command */
70 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
71 /* RoCE slow path command to query CC Gen1 support. */
72 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
73 /* RoCE slow path command to modify CC Gen1 support. */
74 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
75 /* Engine CKV - The Alias key EC curve and ECC public key information. */
76 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
77 /* Engine CKV - Initialization vector. */
78 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
79 /* Engine CKV - Authentication tag. */
80 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
81 /* Engine CKV - The encrypted data. */
82 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
83 /* Engine CKV - Supported host_algorithms. */
84 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
85 /* Engine CKV - The Host EC curve name and ECC public key information. */
86 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
87 /* Engine CKV - The ECDSA signature. */
88 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
89 /* Engine CKV - The firmware EC curve name and ECC public key information. */
90 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
91 /* Engine CKV - Supported firmware algorithms. */
92 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
93 #define TLV_TYPE_LAST \
94 TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
97 /* tlv (size:64b/8B) */
100 * The command discriminator is used to differentiate between various
101 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
102 * command messages as well as newer TLV encapsulated HWRM commands.
104 * For TLV encapsulated messages this field must be 0x8000.
110 * Indicates the presence of additional TLV encapsulated data
113 #define TLV_FLAGS_MORE UINT32_C(0x1)
114 /* Last TLV in a sequence of TLVs. */
115 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
116 /* More TLVs follow this TLV. */
117 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
119 * When an HWRM receiver detects a TLV type that it does not
120 * support with the TLV required flag set, the receiver must
121 * reject the HWRM message with an error code indicating an
122 * unsupported TLV type.
124 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
126 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
128 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
129 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
131 * This field defines the TLV type value which is divided into
132 * two ranges to differentiate between global and local TLV types.
133 * Global TLV types must be unique across all defined TLV types.
134 * Local TLV types are valid only for extensions to a given
135 * HWRM message and may be repeated across different HWRM message
136 * types. There is a direct correlation of each HWRM message type
137 * to a single global TLV type value.
139 * Global TLV range: `0 - (63k-1)`
141 * Local TLV range: `63k - (64k-1)`
145 * Length of the message data encapsulated by this TLV in bytes.
146 * This length does not include the size of the TLV header itself
147 * and it must be an integer multiple of 8B.
153 /* input (size:128b/16B) */
156 * This value indicates what type of request this is. The format
157 * for the rest of the command is determined by this field.
161 * This value indicates the what completion ring the request will
162 * be optionally completed on. If the value is -1, then no
163 * CR completion will be generated. Any other value must be a
164 * valid CR ring_id value for this function.
167 /* This value indicates the command sequence number. */
170 * Target ID of this command.
172 * 0x0 - 0xFFF8 - Used for function ids
173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
178 * This is the host address where the response will be written
179 * when the request is complete. This area must be 16B aligned
180 * and must be cleared to zero before the request is made.
186 /* output (size:64b/8B) */
189 * Pass/Fail or error type
191 * Note: receiver to verify the in parameters, and fail the call
192 * with an error when appropriate
195 /* This field returns the type of original request. */
197 /* This field provides original sequence number of the command. */
200 * This field is the length of the response in bytes. The
201 * last byte of the response is a valid flag that will read
202 * as '1' when the command has been completely written to
208 /* Short Command Structure */
209 /* hwrm_short_input (size:128b/16B) */
210 struct hwrm_short_input {
212 * This field indicates the type of request in the request buffer.
213 * The format for the rest of the command (request) is determined
218 * This field indicates a signature that is used to identify short
219 * form of the command listed here. This field shall be set to
223 /* Signature indicating this is a short form of HWRM command */
224 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
225 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
226 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
227 /* The target ID of the command */
229 /* Default target_id (0x0) to maintain compatibility with old driver */
230 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
231 /* Reserved for user-space HWRM interface */
232 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
233 #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
234 HWRM_SHORT_INPUT_TARGET_ID_TOOLS
235 /* This value indicates the length of the request. */
238 * This is the host address where the request was written.
239 * This area must be 16B aligned.
246 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
247 * # So only structure definition is provided here.
249 /* cmd_nums (size:64b/8B) */
252 * This version of the specification defines the commands listed in
253 * the table below. The following are general implementation
254 * requirements for these commands:
256 * # All commands listed below that are marked neither
257 * reserved nor experimental shall be implemented by the HWRM.
258 * # A HWRM client compliant to this specification should not use
259 * commands outside of the list below.
260 * # A HWRM client compliant to this specification should not use
261 * command numbers marked reserved below.
262 * # A command marked experimental below may not be implemented
264 * # A command marked experimental may change in the
265 * future version of the HWRM specification.
266 * # A command not listed below may be implemented by the HWRM.
267 * The behavior of commands that are not listed below is outside
268 * the scope of this specification.
271 #define HWRM_VER_GET UINT32_C(0x0)
272 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
273 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
274 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
275 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
276 /* Reserved for future use. */
277 #define HWRM_RESERVED1 UINT32_C(0x10)
278 #define HWRM_FUNC_RESET UINT32_C(0x11)
279 #define HWRM_FUNC_GETFID UINT32_C(0x12)
280 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
281 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
282 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
283 #define HWRM_FUNC_QCFG UINT32_C(0x16)
284 #define HWRM_FUNC_CFG UINT32_C(0x17)
285 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
286 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
287 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
288 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
289 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
290 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
291 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
292 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
293 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
294 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
296 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
297 #define HWRM_PORT_QSTATS UINT32_C(0x23)
298 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
300 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
302 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
303 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
304 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
306 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
307 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
308 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
309 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
310 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
311 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
312 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
313 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
314 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
315 #define HWRM_QUEUE_CFG UINT32_C(0x32)
316 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
317 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
318 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
319 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
320 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
321 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
322 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
323 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
324 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
325 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
326 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
327 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
328 #define HWRM_VNIC_FREE UINT32_C(0x41)
329 #define HWRM_VNIC_CFG UINT32_C(0x42)
330 #define HWRM_VNIC_QCFG UINT32_C(0x43)
331 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
333 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
334 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
335 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
336 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
337 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
338 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
339 #define HWRM_RING_ALLOC UINT32_C(0x50)
340 #define HWRM_RING_FREE UINT32_C(0x51)
341 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
342 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
343 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
344 #define HWRM_RING_SQ_ALLOC UINT32_C(0x55)
345 #define HWRM_RING_SQ_CFG UINT32_C(0x56)
346 #define HWRM_RING_SQ_FREE UINT32_C(0x57)
347 #define HWRM_RING_RESET UINT32_C(0x5e)
348 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
349 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
350 #define HWRM_RING_CFG UINT32_C(0x62)
351 #define HWRM_RING_QCFG UINT32_C(0x63)
352 /* Reserved for future use. */
353 #define HWRM_RESERVED5 UINT32_C(0x64)
354 /* Reserved for future use. */
355 #define HWRM_RESERVED6 UINT32_C(0x65)
356 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
357 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
358 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
359 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
360 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
361 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
362 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
363 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
364 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
365 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
366 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
367 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
369 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
371 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
372 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
373 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
374 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
376 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
378 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
380 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
381 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
382 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
383 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
384 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
385 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
386 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
387 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
388 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
389 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
390 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
391 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
392 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
393 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
394 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
395 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba)
396 #define HWRM_FW_RESET UINT32_C(0xc0)
397 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
398 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
399 #define HWRM_FW_SYNC UINT32_C(0xc3)
400 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
401 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
402 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
403 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
405 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
407 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
409 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
411 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
413 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
414 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
415 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
416 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
417 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
418 #define HWRM_FWD_RESP UINT32_C(0xd2)
419 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
420 #define HWRM_OEM_CMD UINT32_C(0xd4)
421 /* Tells the fw to run PRBS test on a given port and lane. */
422 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
423 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
424 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
425 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
426 /* Tells the fw to collect dsc dump on a given port and lane. */
427 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
428 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
429 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
430 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
431 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
432 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
433 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
434 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
435 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
437 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
439 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
441 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
443 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
445 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
447 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
449 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
451 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
453 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
455 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
457 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
459 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
461 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
463 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
465 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
467 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
469 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
471 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
473 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
474 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
476 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
478 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
480 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
482 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
484 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
485 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
486 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
488 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
490 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
492 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
494 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
496 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
498 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
500 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
502 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
504 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
506 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
508 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
510 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
512 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
514 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
516 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
518 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
520 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
522 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
523 /* Experimental - DEPRECATED */
524 #define HWRM_CFA_TFLIB UINT32_C(0x125)
525 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
526 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
527 /* Engine CKV - Add a new CKEK used to encrypt keys. */
528 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
529 /* Engine CKV - Delete a previously added CKEK. */
530 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
531 /* Engine CKV - Add a new key to the key vault. */
532 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
533 /* Engine CKV - Delete a key from the key vault. */
534 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
535 /* Engine CKV - Delete all keys from the key vault. */
536 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
537 /* Engine CKV - Get random data. */
538 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
539 /* Engine CKV - Generate and encrypt a new AES key. */
540 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
541 /* Engine CKV - Configure a label index with a label value. */
542 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
543 /* Engine CKV - Query a label */
544 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
545 /* Engine - Query the available queue groups configuration. */
546 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
547 /* Engine - Query the queue groups assigned to a function. */
548 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
549 /* Engine - Query the available queue group meter profile configuration. */
550 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
551 /* Engine - Query the configuration of a queue group meter profile. */
552 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
553 /* Engine - Allocate a queue group meter profile. */
554 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
555 /* Engine - Free a queue group meter profile. */
556 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
557 /* Engine - Query the meters assigned to a queue group. */
558 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
559 /* Engine - Bind a queue group meter profile to a queue group. */
560 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
561 /* Engine - Unbind a queue group meter profile from a queue group. */
562 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
563 /* Engine - Bind a queue group to a function. */
564 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
565 /* Engine - Query the scheduling group configuration. */
566 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
567 /* Engine - Query the queue groups assigned to a scheduling group. */
568 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
569 /* Engine - Query the configuration of a scheduling group's meter profiles. */
570 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
571 /* Engine - Configure a scheduling group's meter profiles. */
572 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
573 /* Engine - Bind a queue group to a scheduling group. */
574 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
575 /* Engine - Unbind a queue group from its scheduling group. */
576 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
577 /* Engine - Query the Engine configuration. */
578 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
579 /* Engine - Configure the statistics accumulator for an Engine. */
580 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
581 /* Engine - Clear the statistics accumulator for an Engine. */
582 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
583 /* Engine - Query the statistics accumulator for an Engine. */
584 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
585 /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
586 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
587 /* Engine - Allocate an Engine RQ. */
588 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
589 /* Engine - Free an Engine RQ. */
590 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
591 /* Engine - Allocate an Engine CQ. */
592 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
593 /* Engine - Free an Engine CQ. */
594 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
595 /* Engine - Allocate an NQ. */
596 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
597 /* Engine - Free an NQ. */
598 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
599 /* Engine - Set the on-die RQE credit update location. */
600 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
601 /* Engine - Query the engine function configuration. */
602 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
604 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
606 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
608 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
610 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
612 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
613 /* Configures the BW of any VF */
614 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
615 /* Queries the BW of any VF */
616 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
617 /* Queries pf ids belong to specified host(s) */
618 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
619 /* Queries extended stats per function */
620 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
621 /* Queries extended statistics context */
622 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
624 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
626 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
628 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
630 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
632 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
634 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
635 /* Returns the current value of a free running counter from the device. */
636 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
638 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
640 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
642 * Tells the fw to run the DMA read from the host and DMA write
645 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
646 /* Tells the fw to program the fru memory */
647 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
648 /* Tells the fw to read the fru memory */
649 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
651 #define HWRM_TF UINT32_C(0x2bc)
653 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
655 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
657 #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
659 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
661 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
663 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
665 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
667 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
669 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
671 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
673 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
675 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
677 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
679 #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
681 #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
683 #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
685 #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
687 #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
689 #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
691 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
693 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
695 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
697 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
699 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
701 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
703 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
705 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
707 #define HWRM_SV UINT32_C(0x400)
709 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
711 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
713 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
715 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
716 #define HWRM_DBG_DUMP UINT32_C(0xff14)
718 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
720 #define HWRM_DBG_CFG UINT32_C(0xff16)
722 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
724 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
726 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
728 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
730 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
732 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
734 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
736 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
737 /* Send driver debug information to firmware */
738 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
739 /* Query debug capabilities of firmware */
740 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
741 /* Retrieve debug settings of firmware */
742 #define HWRM_DBG_QCFG UINT32_C(0xff21)
743 /* Set destination parameters for crashdump medium */
744 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
745 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
747 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
748 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
749 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
750 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
751 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
752 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
753 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
754 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
755 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
756 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
757 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
758 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
759 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
760 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
761 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
762 #define HWRM_NVM_READ UINT32_C(0xfffd)
763 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
764 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
765 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
766 uint16_t unused_0[3];
770 /* ret_codes (size:64b/8B) */
773 /* Request was successfully executed by the HWRM. */
774 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
775 /* The HWRM failed to execute the request. */
776 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
778 * The request contains invalid argument(s) or input
781 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
783 * The requester is not allowed to access the requested
784 * resource. This error code shall be provided in a
785 * response to a request to query or modify an existing
786 * resource that is not accessible by the requester.
788 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
790 * The HWRM is unable to allocate the requested resource.
791 * This code only applies to requests for HWRM resource
794 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
796 * Invalid combination of flags is specified in the
799 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
801 * Invalid combination of enables fields is specified in
804 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
806 * Request contains a required TLV that is not supported by
807 * the installed version of firmware.
809 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
811 * No firmware buffer available to accept the request. Driver
812 * should retry the request.
814 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
816 * This error code is only reported by firmware when some
817 * sub-option of a supported HWRM command is unsupported.
819 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
821 * This error code is only reported by firmware when the specific
822 * request is not able to process when the HOT reset in progress.
824 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
826 * This error code is only reported by firmware when the registered
827 * driver instances are not capable of hot reset.
829 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
831 * This error code is only reported by the firmware when during
832 * flow allocation when a request for a flow counter fails because
833 * the number of flow counters are exhausted.
835 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
837 * This error code is only reported by firmware when the registered
838 * driver instances requested to offloaded a flow but was unable to because
839 * the requested key's hash collides with the installed keys.
841 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
843 * This error code is only reported by firmware when the registered
844 * driver instances requested to offloaded a flow but was unable to because
845 * the same key has already been installed.
847 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
849 * Generic HWRM execution error that represents an
852 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
854 * Firmware is unable to service the request at the present time. Caller
855 * may try again later.
857 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
859 * This value indicates that the HWRM response is in TLV format and
860 * should be interpreted as one or more TLVs starting with the
861 * hwrm_resp_hdr TLV. This value is not an indication of any error
862 * by itself, just an indication that the response should be parsed
863 * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
865 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
867 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
868 /* Unsupported or invalid command */
869 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
870 #define HWRM_ERR_CODE_LAST \
871 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
872 uint16_t unused_0[3];
876 /* hwrm_err_output (size:128b/16B) */
877 struct hwrm_err_output {
879 * Pass/Fail or error type
881 * Note: receiver to verify the in parameters, and fail the call
882 * with an error when appropriate
885 /* This field returns the type of original request. */
887 /* This field provides original sequence number of the command. */
890 * This field is the length of the response in bytes. The
891 * last byte of the response is a valid flag that will read
892 * as '1' when the command has been completely written to
896 /* debug info for this error response. */
898 /* debug info for this error response. */
901 * In the case of an error response, command specific error
902 * code is returned in this field.
906 * This field is used in Output records to indicate that the output
907 * is completely written to RAM. This field should be read as '1'
908 * to indicate that the output has been completely written.
909 * When writing a command completion or response to an internal processor,
910 * the order of writes has to be such that this field is written last.
915 * Following is the signature for HWRM message field that indicates not
916 * applicable (All F's). Need to cast it the size of the field if needed.
918 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
919 /* hwrm_func_buf_rgtr */
920 #define HWRM_MAX_REQ_LEN 128
921 /* hwrm_cfa_flow_info */
922 #define HWRM_MAX_RESP_LEN 704
923 /* 7 bit indirection table index. */
924 #define HW_HASH_INDEX_SIZE 0x80
925 #define HW_HASH_KEY_SIZE 40
926 /* valid key for HWRM response */
927 #define HWRM_RESP_VALID_KEY 1
928 /* Reserved for BONO processor */
929 #define HWRM_TARGET_ID_BONO 0xFFF8
930 /* Reserved for KONG processor */
931 #define HWRM_TARGET_ID_KONG 0xFFF9
932 /* Reserved for APE processor */
933 #define HWRM_TARGET_ID_APE 0xFFFA
935 * This value will be used by tools for User-space HWRM Interface.
936 * When tool execute any HWRM command with this target_id, firmware
937 * will copy the response and/or data payload via register space instead
940 #define HWRM_TARGET_ID_TOOLS 0xFFFD
941 #define HWRM_VERSION_MAJOR 1
942 #define HWRM_VERSION_MINOR 10
943 #define HWRM_VERSION_UPDATE 1
944 /* non-zero means beta version */
945 #define HWRM_VERSION_RSVD 48
946 #define HWRM_VERSION_STR "1.10.1.48"
953 /* hwrm_ver_get_input (size:192b/24B) */
954 struct hwrm_ver_get_input {
955 /* The HWRM command request type. */
958 * The completion ring to send the completion event on. This should
959 * be the NQ ID returned from the `nq_alloc` HWRM command.
963 * The sequence ID is used by the driver for tracking multiple
964 * commands. This ID is treated as opaque data by the firmware and
965 * the value is returned in the `hwrm_resp_hdr` upon completion.
969 * The target ID of the command:
970 * * 0x0-0xFFF8 - The function ID
971 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
972 * * 0xFFFD - Reserved for user-space HWRM interface
977 * A physical address pointer pointing to a host buffer that the
978 * command's response data will be written. This can be either a host
979 * physical address (HPA) or a guest physical address (GPA) and must
980 * point to a physically contiguous block of memory.
984 * This field represents the major version of HWRM interface
985 * specification supported by the driver HWRM implementation.
986 * The interface major version is intended to change only when
987 * non backward compatible changes are made to the HWRM
988 * interface specification.
990 uint8_t hwrm_intf_maj;
992 * This field represents the minor version of HWRM interface
993 * specification supported by the driver HWRM implementation.
994 * A change in interface minor version is used to reflect
995 * significant backward compatible modification to HWRM
996 * interface specification.
997 * This can be due to addition or removal of functionality.
998 * HWRM interface specifications with the same major version
999 * but different minor versions are compatible.
1001 uint8_t hwrm_intf_min;
1003 * This field represents the update version of HWRM interface
1004 * specification supported by the driver HWRM implementation.
1005 * The interface update version is used to reflect minor
1006 * changes or bug fixes to a released HWRM interface
1009 uint8_t hwrm_intf_upd;
1010 uint8_t unused_0[5];
1013 /* hwrm_ver_get_output (size:1408b/176B) */
1014 struct hwrm_ver_get_output {
1015 /* The specific error status for the command. */
1016 uint16_t error_code;
1017 /* The HWRM command request type. */
1019 /* The sequence ID from the original command. */
1021 /* The length of the response data in number of bytes. */
1024 * This field represents the major version of HWRM interface
1025 * specification supported by the HWRM implementation.
1026 * The interface major version is intended to change only when
1027 * non backward compatible changes are made to the HWRM
1028 * interface specification.
1029 * A HWRM implementation that is compliant with this
1030 * specification shall provide value of 1 in this field.
1032 uint8_t hwrm_intf_maj_8b;
1034 * This field represents the minor version of HWRM interface
1035 * specification supported by the HWRM implementation.
1036 * A change in interface minor version is used to reflect
1037 * significant backward compatible modification to HWRM
1038 * interface specification.
1039 * This can be due to addition or removal of functionality.
1040 * HWRM interface specifications with the same major version
1041 * but different minor versions are compatible.
1042 * A HWRM implementation that is compliant with this
1043 * specification shall provide value of 2 in this field.
1045 uint8_t hwrm_intf_min_8b;
1047 * This field represents the update version of HWRM interface
1048 * specification supported by the HWRM implementation.
1049 * The interface update version is used to reflect minor
1050 * changes or bug fixes to a released HWRM interface
1052 * A HWRM implementation that is compliant with this
1053 * specification shall provide value of 2 in this field.
1055 uint8_t hwrm_intf_upd_8b;
1056 uint8_t hwrm_intf_rsvd_8b;
1058 * This field represents the major version of HWRM firmware.
1059 * A change in firmware major version represents a major
1062 uint8_t hwrm_fw_maj_8b;
1064 * This field represents the minor version of HWRM firmware.
1065 * A change in firmware minor version represents significant
1066 * firmware functionality changes.
1068 uint8_t hwrm_fw_min_8b;
1070 * This field represents the build version of HWRM firmware.
1071 * A change in firmware build version represents bug fixes
1072 * to a released firmware.
1074 uint8_t hwrm_fw_bld_8b;
1076 * This field is a reserved field. This field can be used to
1077 * represent firmware branches or customer specific releases
1078 * tied to a specific (major,minor,update) version of the
1081 uint8_t hwrm_fw_rsvd_8b;
1083 * This field represents the major version of mgmt firmware.
1084 * A change in major version represents a major release.
1086 uint8_t mgmt_fw_maj_8b;
1088 * This field represents the minor version of mgmt firmware.
1089 * A change in minor version represents significant
1090 * functionality changes.
1092 uint8_t mgmt_fw_min_8b;
1094 * This field represents the build version of mgmt firmware.
1095 * A change in update version represents bug fixes.
1097 uint8_t mgmt_fw_bld_8b;
1099 * This field is a reserved field. This field can be used to
1100 * represent firmware branches or customer specific releases
1101 * tied to a specific (major,minor,update) version
1103 uint8_t mgmt_fw_rsvd_8b;
1105 * This field represents the major version of network
1107 * A change in major version represents a major release.
1109 uint8_t netctrl_fw_maj_8b;
1111 * This field represents the minor version of network
1113 * A change in minor version represents significant
1114 * functionality changes.
1116 uint8_t netctrl_fw_min_8b;
1118 * This field represents the build version of network
1120 * A change in update version represents bug fixes.
1122 uint8_t netctrl_fw_bld_8b;
1124 * This field is a reserved field. This field can be used to
1125 * represent firmware branches or customer specific releases
1126 * tied to a specific (major,minor,update) version
1128 uint8_t netctrl_fw_rsvd_8b;
1130 * This field is used to indicate device's capabilities and
1133 uint32_t dev_caps_cfg;
1135 * If set to 1, then secure firmware update behavior
1137 * If set to 0, then secure firmware update behavior is
1140 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
1143 * If set to 1, then firmware based DCBX agent is supported.
1144 * If set to 0, then firmware based DCBX agent capability
1145 * is not supported on this device.
1147 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
1150 * If set to 1, then HWRM short command format is supported.
1151 * If set to 0, then HWRM short command format is not supported.
1153 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
1156 * If set to 1, then HWRM short command format is required.
1157 * If set to 0, then HWRM short command format is not required.
1159 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
1162 * If set to 1, then the KONG host mailbox channel is supported.
1163 * If set to 0, then the KONG host mailbox channel is not supported.
1164 * By default, this flag should be 0 for older version of core firmware.
1166 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \
1169 * If set to 1, then the 64bit flow handle is supported in addition to the
1170 * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
1171 * supported. By default, this flag should be 0 for older version of core firmware.
1173 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \
1176 * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
1177 * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
1178 * If set to 0, then filter types not supported.
1179 * By default, this flag should be 0 for older version of core firmware.
1181 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \
1184 * If set to 1, firmware is capable to support virtio vSwitch offload model.
1185 * If set to 0, firmware can't supported virtio vSwitch offload model.
1186 * By default, this flag should be 0 for older version of core firmware.
1188 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \
1191 * If set to 1, firmware is capable to support trusted VF.
1192 * If set to 0, firmware is not capable to support trusted VF.
1193 * By default, this flag should be 0 for older version of core firmware.
1195 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
1198 * If set to 1, firmware is capable to support flow aging.
1199 * If set to 0, firmware is not capable to support flow aging.
1200 * By default, this flag should be 0 for older version of core firmware.
1202 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
1205 * If set to 1, firmware is capable to support advanced flow counters like,
1206 * Meter drop counters and EEM counters.
1207 * If set to 0, firmware is not capable to support advanced flow counters.
1208 * By default, this flag should be 0 for older version of core firmware.
1210 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
1213 * If set to 1, the firmware is able to support the use of the CFA
1214 * Extended Exact Match(EEM) feature.
1215 * If set to 0, firmware is not capable to support the use of the
1217 * By default, this flag should be 0 for older version of core firmware.
1219 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
1222 * If set to 1, the firmware is able to support advance CFA flow management
1223 * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
1224 * If set to 0, then the firmware doesn’t support the advance CFA flow management
1226 * By default, this flag should be 0 for older version of core firmware.
1228 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
1231 * Deprecated and replaced with cfa_truflow_supported.
1232 * If set to 1, the firmware is able to support TFLIB features.
1233 * If set to 0, then the firmware doesn’t support TFLIB features.
1234 * By default, this flag should be 0 for older version of core firmware.
1236 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
1239 * If set to 1, the firmware is able to support TruFlow features.
1240 * If set to 0, then the firmware doesn’t support TruFlow features.
1241 * By default, this flag should be 0 for older version of
1244 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \
1247 * This field represents the major version of RoCE firmware.
1248 * A change in major version represents a major release.
1250 uint8_t roce_fw_maj_8b;
1252 * This field represents the minor version of RoCE firmware.
1253 * A change in minor version represents significant
1254 * functionality changes.
1256 uint8_t roce_fw_min_8b;
1258 * This field represents the build version of RoCE firmware.
1259 * A change in update version represents bug fixes.
1261 uint8_t roce_fw_bld_8b;
1263 * This field is a reserved field. This field can be used to
1264 * represent firmware branches or customer specific releases
1265 * tied to a specific (major,minor,update) version
1267 uint8_t roce_fw_rsvd_8b;
1269 * This field represents the name of HWRM FW (ASCII chars
1270 * with NULL at the end).
1272 char hwrm_fw_name[16];
1274 * This field represents the name of mgmt FW (ASCII chars
1275 * with NULL at the end).
1277 char mgmt_fw_name[16];
1279 * This field represents the name of network control
1280 * firmware (ASCII chars with NULL at the end).
1282 char netctrl_fw_name[16];
1283 /* This field represents the active board package name. */
1284 char active_pkg_name[16];
1286 * This field represents the name of RoCE FW (ASCII chars
1287 * with NULL at the end).
1289 char roce_fw_name[16];
1290 /* This field returns the chip number. */
1292 /* This field returns the revision of chip. */
1294 /* This field returns the chip metal number. */
1296 /* This field returns the bond id of the chip. */
1297 uint8_t chip_bond_id;
1298 /* This value indicates the type of platform used for chip implementation. */
1299 uint8_t chip_platform_type;
1301 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
1302 /* FPGA platform of the chip. */
1303 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
1304 /* Palladium platform of the chip. */
1305 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
1306 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
1307 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
1309 * This field returns the maximum value of request window that
1310 * is supported by the HWRM. The request window is mapped
1311 * into device address space using MMIO.
1313 uint16_t max_req_win_len;
1315 * This field returns the maximum value of response buffer in
1318 uint16_t max_resp_len;
1320 * This field returns the default request timeout value in
1323 uint16_t def_req_timeout;
1325 * This field will indicate if any subsystems is not fully
1330 * If set to 1, it will indicate to host drivers that firmware is
1331 * not ready to start full blown HWRM commands. Host drivers should
1332 * re-try HWRM_VER_GET with some timeout period. The timeout period
1333 * can be selected up to 5 seconds.
1334 * For Example, PCIe hot-plug:
1335 * Hot plug timing is system dependent. It generally takes up to
1336 * 600 miliseconds for firmware to clear DEV_NOT_RDY flag.
1337 * If set to 0, device is ready to accept all HWRM commands.
1339 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
1341 * If set to 1, external version present.
1342 * If set to 0, external version not present.
1344 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1345 uint8_t unused_0[2];
1347 * For backward compatibility this field must be set to 1.
1348 * Older drivers might look for this field to be 1 before
1349 * processing the message.
1353 * This field represents the major version of HWRM interface
1354 * specification supported by the HWRM implementation.
1355 * The interface major version is intended to change only when
1356 * non backward compatible changes are made to the HWRM
1357 * interface specification. A HWRM implementation that is
1358 * compliant with this specification shall provide value of 1
1361 uint16_t hwrm_intf_major;
1363 * This field represents the minor version of HWRM interface
1364 * specification supported by the HWRM implementation.
1365 * A change in interface minor version is used to reflect
1366 * significant backward compatible modification to HWRM
1367 * interface specification. This can be due to addition or
1368 * removal of functionality. HWRM interface specifications
1369 * with the same major version but different minor versions are
1370 * compatible. A HWRM implementation that is compliant with
1371 * this specification shall provide value of 2 in this field.
1373 uint16_t hwrm_intf_minor;
1375 * This field represents the update version of HWRM interface
1376 * specification supported by the HWRM implementation. The
1377 * interface update version is used to reflect minor changes or
1378 * bug fixes to a released HWRM interface specification.
1379 * A HWRM implementation that is compliant with this
1380 * specification shall provide value of 2 in this field.
1382 uint16_t hwrm_intf_build;
1384 * This field represents the patch version of HWRM interface
1385 * specification supported by the HWRM implementation.
1387 uint16_t hwrm_intf_patch;
1389 * This field represents the major version of HWRM firmware.
1390 * A change in firmware major version represents a major
1393 uint16_t hwrm_fw_major;
1395 * This field represents the minor version of HWRM firmware.
1396 * A change in firmware minor version represents significant
1397 * firmware functionality changes.
1399 uint16_t hwrm_fw_minor;
1401 * This field represents the build version of HWRM firmware.
1402 * A change in firmware build version represents bug fixes to
1403 * a released firmware.
1405 uint16_t hwrm_fw_build;
1407 * This field is a reserved field.
1408 * This field can be used to represent firmware branches or customer
1409 * specific releases tied to a specific (major,minor,update) version
1410 * of the HWRM firmware.
1412 uint16_t hwrm_fw_patch;
1414 * This field represents the major version of mgmt firmware.
1415 * A change in major version represents a major release.
1417 uint16_t mgmt_fw_major;
1419 * This field represents the minor version of HWRM firmware.
1420 * A change in firmware minor version represents significant
1421 * firmware functionality changes.
1423 uint16_t mgmt_fw_minor;
1425 * This field represents the build version of mgmt firmware.
1426 * A change in update version represents bug fixes.
1428 uint16_t mgmt_fw_build;
1430 * This field is a reserved field. This field can be used to
1431 * represent firmware branches or customer specific releases
1432 * tied to a specific (major,minor,update) version.
1434 uint16_t mgmt_fw_patch;
1436 * This field represents the major version of network control
1437 * firmware. A change in major version represents
1440 uint16_t netctrl_fw_major;
1442 * This field represents the minor version of network control
1443 * firmware. A change in minor version represents significant
1444 * functionality changes.
1446 uint16_t netctrl_fw_minor;
1448 * This field represents the build version of network control
1449 * firmware. A change in update version represents bug fixes.
1451 uint16_t netctrl_fw_build;
1453 * This field is a reserved field. This field can be used to
1454 * represent firmware branches or customer specific releases
1455 * tied to a specific (major,minor,update) version
1457 uint16_t netctrl_fw_patch;
1459 * This field represents the major version of RoCE firmware.
1460 * A change in major version represents a major release.
1462 uint16_t roce_fw_major;
1464 * This field represents the minor version of RoCE firmware.
1465 * A change in minor version represents significant
1466 * functionality changes.
1468 uint16_t roce_fw_minor;
1470 * This field represents the build version of RoCE firmware.
1471 * A change in update version represents bug fixes.
1473 uint16_t roce_fw_build;
1475 * This field is a reserved field. This field can be used to
1476 * represent firmware branches or customer specific releases
1477 * tied to a specific (major,minor,update) version
1479 uint16_t roce_fw_patch;
1481 * This field returns the maximum extended request length acceptable
1482 * by the device which allows requests greater than mailbox size when
1483 * used with the short cmd request format.
1485 uint16_t max_ext_req_len;
1486 uint8_t unused_1[5];
1488 * This field is used in Output records to indicate that the output
1489 * is completely written to RAM. This field should be read as '1'
1490 * to indicate that the output has been completely written.
1491 * When writing a command completion or response to an internal processor,
1492 * the order of writes has to be such that this field is written last.
1497 /* bd_base (size:64b/8B) */
1500 /* This value identifies the type of buffer descriptor. */
1501 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1502 #define BD_BASE_TYPE_SFT 0
1504 * Indicates that this BD is 16B long and is used for
1505 * normal L2 packet transmission.
1507 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1509 * Indicates that this BD is 1BB long and is an empty
1510 * TX BD. Not valid for use by the driver.
1512 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1514 * Indicates that this BD is 16B long and is an RX Producer
1515 * (i.e. empty) buffer descriptor.
1517 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1519 * Indicates that this BD is 16B long and is an RX
1520 * Producer Buffer BD.
1522 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1524 * Indicates that this BD is 16B long and is an
1525 * RX Producer Assembly Buffer Descriptor.
1527 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1529 * Indicates that this BD is 32B long and is used for
1530 * normal L2 packet transmission.
1532 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1534 * Indicates that this BD is 32B long and is used for
1535 * L2 packet transmission for small packets that require
1538 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1539 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
1540 uint8_t unused_1[7];
1543 /* tx_bd_short (size:128b/16B) */
1544 struct tx_bd_short {
1546 * All bits in this field must be valid on the first BD of a packet.
1547 * Only the packet_end bit must be valid for the remaining BDs
1550 uint16_t flags_type;
1551 /* This value identifies the type of buffer descriptor. */
1552 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1553 #define TX_BD_SHORT_TYPE_SFT 0
1555 * Indicates that this BD is 16B long and is used for
1556 * normal L2 packet transmission.
1558 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1559 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1561 * All bits in this field must be valid on the first BD of a packet.
1562 * Only the packet_end bit must be valid for the remaining BDs
1565 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1566 #define TX_BD_SHORT_FLAGS_SFT 6
1568 * If set to 1, the packet ends with the data in the buffer
1569 * pointed to by this descriptor. This flag must be
1570 * valid on every BD.
1572 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1574 * If set to 1, the device will not generate a completion for
1575 * this transmit packet unless there is an error in it's
1578 * is set to 0, then the packet will be completed normally.
1580 * This bit must be valid only on the first BD of a packet.
1582 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1584 * This value indicates how many 16B BD locations are consumed
1585 * in the ring by this packet.
1586 * A value of 1 indicates that this BD is the only BD (and that
1587 * it is a short BD). A value
1588 * of 3 indicates either 3 short BDs or 1 long BD and one short
1589 * BD in the packet. A value of 0 indicates
1590 * that there are 32 BD locations in the packet (the maximum).
1592 * This field is valid only on the first BD of a packet.
1594 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1595 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1597 * This value is a hint for the length of the entire packet.
1598 * It is used by the chip to optimize internal processing.
1600 * The packet will be dropped if the hint is too short.
1602 * This field is valid only on the first BD of a packet.
1604 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1605 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1606 /* indicates packet length < 512B */
1607 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1608 /* indicates 512 <= packet length < 1KB */
1609 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1610 /* indicates 1KB <= packet length < 2KB */
1611 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1612 /* indicates packet length >= 2KB */
1613 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1614 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1615 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1617 * If set to 1, the device immediately updates the Send Consumer
1618 * Index after the buffer associated with this descriptor has
1619 * been transferred via DMA to NIC memory from host memory. An
1620 * interrupt may or may not be generated according to the state
1621 * of the interrupt avoidance mechanisms. If this bit
1622 * is set to 0, then the Consumer Index is only updated as soon
1623 * as one of the host interrupt coalescing conditions has been met.
1625 * This bit must be valid on the first BD of a packet.
1627 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1629 * This is the length of the host physical buffer this BD describes
1632 * This field must be valid on all BDs of a packet.
1636 * The opaque data field is pass through to the completion and can be
1637 * used for any data that the driver wants to associate with the
1640 * This field must be valid on the first BD of a packet.
1644 * This is the host physical address for the portion of the packet
1645 * described by this TX BD.
1647 * This value must be valid on all BDs of a packet.
1652 /* tx_bd_long (size:128b/16B) */
1654 /* This value identifies the type of buffer descriptor. */
1655 uint16_t flags_type;
1657 * This value indicates the type of buffer descriptor.
1660 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1661 #define TX_BD_LONG_TYPE_SFT 0
1663 * Indicates that this BD is 32B long and is used for
1664 * normal L2 packet transmission.
1666 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1667 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1669 * All bits in this field must be valid on the first BD of a packet.
1670 * Only the packet_end bit must be valid for the remaining BDs
1673 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1674 #define TX_BD_LONG_FLAGS_SFT 6
1676 * If set to 1, the packet ends with the data in the buffer
1677 * pointed to by this descriptor. This flag must be
1678 * valid on every BD.
1680 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1682 * If set to 1, the device will not generate a completion for
1683 * this transmit packet unless there is an error in it's
1686 * is set to 0, then the packet will be completed normally.
1688 * This bit must be valid only on the first BD of a packet.
1690 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1692 * This value indicates how many 16B BD locations are consumed
1693 * in the ring by this packet.
1694 * A value of 1 indicates that this BD is the only BD (and that
1695 * it is a short BD). A value
1696 * of 3 indicates either 3 short BDs or 1 long BD and one short
1697 * BD in the packet. A value of 0 indicates
1698 * that there are 32 BD locations in the packet (the maximum).
1700 * This field is valid only on the first BD of a packet.
1702 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1703 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1705 * This value is a hint for the length of the entire packet.
1706 * It is used by the chip to optimize internal processing.
1708 * The packet will be dropped if the hint is too short.
1710 * This field is valid only on the first BD of a packet.
1712 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1713 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1714 /* indicates packet length < 512B */
1715 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1716 /* indicates 512 <= packet length < 1KB */
1717 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1718 /* indicates 1KB <= packet length < 2KB */
1719 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1720 /* indicates packet length >= 2KB */
1721 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1722 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1724 * If set to 1, the device immediately updates the Send Consumer
1725 * Index after the buffer associated with this descriptor has
1726 * been transferred via DMA to NIC memory from host memory. An
1727 * interrupt may or may not be generated according to the state
1728 * of the interrupt avoidance mechanisms. If this bit
1729 * is set to 0, then the Consumer Index is only updated as soon
1730 * as one of the host interrupt coalescing conditions has been met.
1732 * This bit must be valid on the first BD of a packet.
1734 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1736 * This is the length of the host physical buffer this BD describes
1739 * This field must be valid on all BDs of a packet.
1743 * The opaque data field is pass through to the completion and can be
1744 * used for any data that the driver wants to associate with the
1747 * This field must be valid on the first BD of a packet.
1751 * This is the host physical address for the portion of the packet
1752 * described by this TX BD.
1754 * This value must be valid on all BDs of a packet.
1759 /* Last 16 bytes of tx_bd_long. */
1760 /* tx_bd_long_hi (size:128b/16B) */
1761 struct tx_bd_long_hi {
1763 * All bits in this field must be valid on the first BD of a packet.
1764 * Their value on other BDs of the packet will be ignored.
1768 * If set to 1, the controller replaces the TCP/UPD checksum
1769 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1770 * checksum field of the encapsulated TCP/UDP packets with the
1771 * hardware calculated TCP/UDP checksum for the packet associated
1772 * with this descriptor. The flag is ignored if the LSO flag is set.
1774 * This bit must be valid on the first BD of a packet.
1776 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1778 * If set to 1, the controller replaces the IP checksum of the
1779 * normal packets, or the inner IP checksum of the encapsulated
1780 * packets with the hardware calculated IP checksum for the
1781 * packet associated with this descriptor.
1783 * This bit must be valid on the first BD of a packet.
1785 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1787 * If set to 1, the controller will not append an Ethernet CRC
1788 * to the end of the frame.
1790 * This bit must be valid on the first BD of a packet.
1792 * Packet must be 64B or longer when this flag is set. It is not
1793 * useful to use this bit with any form of TX offload such as
1794 * CSO or LSO. The intent is that the packet from the host already
1795 * has a valid Ethernet CRC on the packet.
1797 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1799 * If set to 1, the device will record the time at which the packet
1800 * was actually transmitted at the TX MAC.
1802 * This bit must be valid on the first BD of a packet.
1804 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1806 * If set to 1, The controller replaces the tunnel IP checksum
1807 * field with hardware calculated IP checksum for the IP header
1808 * of the packet associated with this descriptor.
1810 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1811 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1812 * bit is set, outer UDP checksum will be calculated for the following
1814 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1815 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1816 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1817 * checksum will not be calculated.
1818 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1819 * as part of LSO operation.
1821 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1823 * If set to 1, the device will treat this packet with LSO(Large
1824 * Send Offload) processing for both normal or encapsulated
1825 * packets, which is a form of TCP segmentation. When this bit
1826 * is 1, the hdr_size and mss fields must be valid. The driver
1827 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1828 * flags since the controller will replace the appropriate
1829 * checksum fields for segmented packets.
1831 * When this bit is 1, the hdr_size and mss fields must be valid.
1833 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1835 * If set to zero when LSO is '1', then the IPID will be treated
1836 * as a 16b number and will be wrapped if it exceeds a value of
1839 * If set to one when LSO is '1', then the IPID will be treated
1840 * as a 15b number and will be wrapped if it exceeds a value 0f
1843 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1845 * If set to zero when LSO is '1', then the IPID of the tunnel
1846 * IP header will not be modified during LSO operations.
1848 * If set to one when LSO is '1', then the IPID of the tunnel
1849 * IP header will be incremented for each subsequent segment of an
1852 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1855 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1857 * If set to '1', then the RoCE ICRC will be appended to the
1858 * packet. Packet must be a valid RoCE format packet.
1860 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1862 * If set to '1', then the FCoE CRC will be appended to the
1863 * packet. Packet must be a valid FCoE format packet.
1865 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1868 * When LSO is '1', this field must contain the offset of the
1869 * TCP payload from the beginning of the packet in as
1870 * 16b words. In case of encapsulated/tunneling packet, this field
1871 * contains the offset of the inner TCP payload from beginning of the
1872 * packet as 16-bit words.
1874 * This value must be valid on the first BD of a packet.
1876 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1877 #define TX_BD_LONG_HDR_SIZE_SFT 0
1880 * This is the MSS value that will be used to do the LSO processing.
1881 * The value is the length in bytes of the TCP payload for each
1882 * segment generated by the LSO operation.
1884 * This value must be valid on the first BD of a packet.
1886 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1887 #define TX_BD_LONG_MSS_SFT 0
1890 * This value selects a CFA action to perform on the packet.
1891 * Set this value to zero if no CFA action is desired.
1893 * This value must be valid on the first BD of a packet.
1895 uint16_t cfa_action;
1897 * This value is action meta-data that defines CFA edit operations
1898 * that are done in addition to any action editing.
1901 /* When key=1, This is the VLAN tag VID value. */
1902 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1903 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1904 /* When key=1, This is the VLAN tag DE value. */
1905 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1906 /* When key=1, This is the VLAN tag PRI value. */
1907 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1908 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1909 /* When key=1, This is the VLAN tag TPID select value. */
1910 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1911 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1913 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1915 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1917 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1919 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1921 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1922 /* Value programmed in CFA VLANTPID register. */
1923 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1924 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1925 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1926 /* When key=1, This is the VLAN tag TPID select value. */
1927 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1928 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1930 * This field identifies the type of edit to be performed
1933 * This value must be valid on the first BD of a packet.
1935 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1936 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1938 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1940 * - meta[17:16] - TPID select value (0 = 0x8100).
1941 * - meta[15:12] - PRI/DE value.
1942 * - meta[11:0] - VID value.
1944 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1945 #define TX_BD_LONG_CFA_META_KEY_LAST \
1946 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1950 * This structure is used to inform the NIC of packet data that needs to be
1951 * transmitted with additional processing that requires extra data such as
1952 * VLAN insertion plus attached inline data. This BD type may be used to
1953 * improve latency for small packets needing the additional extended features
1954 * supported by long BDs.
1956 /* tx_bd_long_inline (size:256b/32B) */
1957 struct tx_bd_long_inline {
1958 uint16_t flags_type;
1959 /* This value identifies the type of buffer descriptor. */
1960 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
1961 #define TX_BD_LONG_INLINE_TYPE_SFT 0
1963 * This type of BD is 32B long and is used for inline L2 packet
1966 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
1967 #define TX_BD_LONG_INLINE_TYPE_LAST \
1968 TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
1970 * All bits in this field may be set on the first BD of a packet.
1971 * Only the packet_end bit may be set in non-first BDs.
1973 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
1974 #define TX_BD_LONG_INLINE_FLAGS_SFT 6
1976 * If set to 1, the packet ends with the data in the buffer
1977 * pointed to by this descriptor. This flag must be
1978 * valid on every BD.
1980 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
1982 * If set to 1, the device will not generate a completion for
1983 * this transmit packet unless there is an error in its processing.
1984 * If this bit is set to 0, then the packet will be completed
1987 * This bit may be set only on the first BD of a packet.
1989 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
1991 * This value indicates how many 16B BD locations are consumed
1992 * in the ring by this packet, including the BD and inline
1995 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1996 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
1997 /* This field is deprecated. */
1998 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
1999 #define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
2001 * If set to 1, the device immediately updates the Send Consumer
2002 * Index after the buffer associated with this descriptor has
2003 * been transferred via DMA to NIC memory from host memory. An
2004 * interrupt may or may not be generated according to the state
2005 * of the interrupt avoidance mechanisms. If this bit
2006 * is set to 0, then the Consumer Index is only updated as soon
2007 * as one of the host interrupt coalescing conditions has been met.
2009 * This bit must be valid on the first BD of a packet.
2011 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
2013 * This is the length of the inline data, not including BD length, in
2015 * The maximum value is 480.
2017 * This field must be valid on all BDs of a packet.
2021 * The opaque data field is passed through to the completion and can be
2022 * used for any data that the driver wants to associate with the transmit
2025 * This field must be valid on the first BD of a packet.
2030 * All bits in this field must be valid on the first BD of a packet.
2031 * Their value on other BDs of the packet is ignored.
2035 * If set to 1, the controller replaces the TCP/UPD checksum
2036 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
2037 * checksum field of the encapsulated TCP/UDP packets with the
2038 * hardware calculated TCP/UDP checksum for the packet associated
2039 * with this descriptor. The flag is ignored if the LSO flag is set.
2041 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
2043 * If set to 1, the controller replaces the IP checksum of the
2044 * normal packets, or the inner IP checksum of the encapsulated
2045 * packets with the hardware calculated IP checksum for the
2046 * packet associated with this descriptor.
2048 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
2050 * If set to 1, the controller will not append an Ethernet CRC
2051 * to the end of the frame.
2053 * Packet must be 64B or longer when this flag is set. It is not
2054 * useful to use this bit with any form of TX offload such as
2055 * CSO or LSO. The intent is that the packet from the host already
2056 * has a valid Ethernet CRC on the packet.
2058 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
2060 * If set to 1, the device will record the time at which the packet
2061 * was actually transmitted at the TX MAC.
2063 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
2065 * If set to 1, the controller replaces the tunnel IP checksum
2066 * field with hardware calculated IP checksum for the IP header
2067 * of the packet associated with this descriptor. The hardware
2068 * updates an outer UDP checksum if it is non-zero.
2070 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
2072 * This bit must be 0 for BDs of this type. LSO is not supported with
2075 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
2076 /* Since LSO is not supported with inline BDs, this bit is not used. */
2077 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
2078 /* Since LSO is not supported with inline BDs, this bit is not used. */
2079 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
2081 * If set to '1', then the RoCE ICRC will be appended to the
2082 * packet. Packet must be a valid RoCE format packet.
2084 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
2086 * If set to '1', then the FCoE CRC will be appended to the
2087 * packet. Packet must be a valid FCoE format packet.
2089 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
2094 * This value selects a CFA action to perform on the packet.
2095 * Set this value to zero if no CFA action is desired.
2097 * This value must be valid on the first BD of a packet.
2099 uint16_t cfa_action;
2101 * This value is action meta-data that defines CFA edit operations
2102 * that are done in addition to any action editing.
2105 /* When key = 1, this is the VLAN tag VID value. */
2106 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
2107 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
2108 /* When key = 1, this is the VLAN tag DE value. */
2109 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
2110 /* When key = 1, this is the VLAN tag PRI value. */
2111 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
2112 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
2113 /* When key = 1, this is the VLAN tag TPID select value. */
2114 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
2115 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
2117 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \
2118 (UINT32_C(0x0) << 16)
2120 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \
2121 (UINT32_C(0x1) << 16)
2123 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \
2124 (UINT32_C(0x2) << 16)
2126 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \
2127 (UINT32_C(0x3) << 16)
2129 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \
2130 (UINT32_C(0x4) << 16)
2131 /* Value programmed in CFA VLANTPID register. */
2132 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \
2133 (UINT32_C(0x5) << 16)
2134 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \
2135 TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
2136 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \
2138 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
2140 * This field identifies the type of edit to be performed
2143 * This value must be valid on the first BD of a packet.
2145 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \
2146 UINT32_C(0xf0000000)
2147 #define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
2149 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \
2150 (UINT32_C(0x0) << 28)
2152 * - meta[17:16] - TPID select value (0 = 0x8100).
2153 * - meta[15:12] - PRI/DE value.
2154 * - meta[11:0] - VID value.
2156 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \
2157 (UINT32_C(0x1) << 28)
2158 #define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \
2159 TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG
2162 /* tx_bd_empty (size:128b/16B) */
2163 struct tx_bd_empty {
2164 /* This value identifies the type of buffer descriptor. */
2166 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
2167 #define TX_BD_EMPTY_TYPE_SFT 0
2169 * Indicates that this BD is 1BB long and is an empty
2170 * TX BD. Not valid for use by the driver.
2172 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
2173 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
2174 uint8_t unused_1[3];
2176 uint8_t unused_3[3];
2177 uint8_t unused_4[8];
2180 /* rx_prod_pkt_bd (size:128b/16B) */
2181 struct rx_prod_pkt_bd {
2182 /* This value identifies the type of buffer descriptor. */
2183 uint16_t flags_type;
2184 /* This value identifies the type of buffer descriptor. */
2185 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
2186 #define RX_PROD_PKT_BD_TYPE_SFT 0
2188 * Indicates that this BD is 16B long and is an RX Producer
2189 * (i.e. empty) buffer descriptor.
2191 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
2192 #define RX_PROD_PKT_BD_TYPE_LAST \
2193 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
2194 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
2195 #define RX_PROD_PKT_BD_FLAGS_SFT 6
2197 * If set to 1, the packet will be placed at the address plus
2198 * 2B. The 2 Bytes of padding will be written as zero.
2200 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
2202 * If set to 1, the packet write will be padded out to the
2203 * nearest cache-line with zero value padding.
2205 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
2207 * This value is the number of additional buffers in the ring that
2208 * describe the buffer space to be consumed for this packet.
2209 * If the value is zero, then the packet must fit within the
2210 * space described by this BD. If this value is 1 or more, it
2211 * indicates how many additional "buffer" BDs are in the ring
2212 * immediately following this BD to be used for the same
2215 * Even if the packet to be placed does not need all the
2216 * additional buffers, they will be consumed anyway.
2218 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
2219 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
2221 * This is the length in Bytes of the host physical buffer where
2222 * data for the packet may be placed in host memory.
2226 * The opaque data field is pass through to the completion and can be
2227 * used for any data that the driver wants to associate with this
2228 * receive buffer set.
2232 * This is the host physical address where data for the packet may
2233 * be placed in host memory.
2238 /* rx_prod_bfr_bd (size:128b/16B) */
2239 struct rx_prod_bfr_bd {
2240 /* This value identifies the type of buffer descriptor. */
2241 uint16_t flags_type;
2242 /* This value identifies the type of buffer descriptor. */
2243 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
2244 #define RX_PROD_BFR_BD_TYPE_SFT 0
2246 * Indicates that this BD is 16B long and is an RX
2247 * Producer Buffer BD.
2249 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
2250 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
2251 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
2252 #define RX_PROD_BFR_BD_FLAGS_SFT 6
2254 * This is the length in Bytes of the host physical buffer where
2255 * data for the packet may be placed in host memory.
2258 /* This field is not used. */
2261 * This is the host physical address where data for the packet may
2262 * be placed in host memory.
2267 /* rx_prod_agg_bd (size:128b/16B) */
2268 struct rx_prod_agg_bd {
2269 /* This value identifies the type of buffer descriptor. */
2270 uint16_t flags_type;
2271 /* This value identifies the type of buffer descriptor. */
2272 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
2273 #define RX_PROD_AGG_BD_TYPE_SFT 0
2275 * Indicates that this BD is 16B long and is an
2276 * RX Producer Assembly Buffer Descriptor.
2278 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
2279 #define RX_PROD_AGG_BD_TYPE_LAST \
2280 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
2281 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
2282 #define RX_PROD_AGG_BD_FLAGS_SFT 6
2284 * If set to 1, the packet write will be padded out to the
2285 * nearest cache-line with zero value padding.
2287 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
2289 * This is the length in Bytes of the host physical buffer where
2290 * data for the packet may be placed in host memory.
2294 * The opaque data field is pass through to the completion and can be
2295 * used for any data that the driver wants to associate with this
2296 * receive assembly buffer.
2300 * This is the host physical address where data for the packet may
2301 * be placed in host memory.
2306 /* cmpl_base (size:128b/16B) */
2310 * This field indicates the exact type of the completion.
2311 * By convention, the LSB identifies the length of the
2312 * record in 16B units. Even values indicate 16B
2313 * records. Odd values indicate 32B
2316 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
2317 #define CMPL_BASE_TYPE_SFT 0
2320 * Completion of TX packet. Length = 16B
2322 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
2325 * Completion of NO-OP. Length = 16B
2327 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
2329 * TX L2 coalesced completion:
2330 * Completion of coalesced TX packet. Length = 16B
2332 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
2334 * TX L2 PTP completion:
2335 * Completion of PTP TX packet. Length = 32B
2337 #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)
2339 * RX L2 TPA Start V2 Completion:
2340 * Completion of and L2 RX packet. Length = 32B
2341 * This is the new version of the RX_TPA_START completion used
2342 * in SR2 and later chips.
2344 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
2346 * RX L2 V2 completion:
2347 * Completion of and L2 RX packet. Length = 32B
2348 * This is the new version of the RX_L2 completion used in SR2
2351 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
2354 * Completion of and L2 RX packet. Length = 32B
2356 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
2358 * RX Aggregation Buffer completion :
2359 * Completion of an L2 aggregation buffer in support of
2360 * TPA, HDS, or Jumbo packet completion. Length = 16B
2362 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
2364 * RX L2 TPA Start Completion:
2365 * Completion at the beginning of a TPA operation.
2368 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
2370 * RX L2 TPA End Completion:
2371 * Completion at the end of a TPA operation.
2374 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
2376 * Statistics Ejection Completion:
2377 * Completion of statistics data ejection buffer.
2380 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
2382 * VEE Flush Completion:
2383 * This completion is inserted manually by
2384 * the Primate and processed by the VEE hardware to ensure that
2385 * all completions on a VEE function have been processed by the
2386 * VEE hardware before FLR process is completed.
2388 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
2390 * Mid Path Short Completion :
2391 * Completion of a Mid Path Command. Length = 16B
2393 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
2395 * Mid Path Long Completion :
2396 * Completion of a Mid Path Command. Length = 32B
2398 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
2400 * HWRM Command Completion:
2401 * Completion of an HWRM command.
2403 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
2404 /* Forwarded HWRM Request */
2405 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
2406 /* Forwarded HWRM Response */
2407 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
2408 /* HWRM Asynchronous Event Information */
2409 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2410 /* CQ Notification */
2411 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
2412 /* SRQ Threshold Event */
2413 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
2414 /* DBQ Threshold Event */
2415 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
2416 /* QP Async Notification */
2417 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
2418 /* Function Async Notification */
2419 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
2420 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
2426 * This value is written by the NIC such that it will be different
2427 * for each pass through the completion queue. The even passes
2428 * will write 1. The odd passes will write 0.
2431 #define CMPL_BASE_V UINT32_C(0x1)
2432 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
2433 #define CMPL_BASE_INFO3_SFT 1
2438 /* tx_cmpl (size:128b/16B) */
2440 uint16_t flags_type;
2442 * This field indicates the exact type of the completion.
2443 * By convention, the LSB identifies the length of the
2444 * record in 16B units. Even values indicate 16B
2445 * records. Odd values indicate 32B
2448 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
2449 #define TX_CMPL_TYPE_SFT 0
2452 * Completion of TX packet. Length = 16B
2454 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
2455 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
2456 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2457 #define TX_CMPL_FLAGS_SFT 6
2459 * When this bit is '1', it indicates a packet that has an
2460 * error of some type. Type of error is indicated in
2463 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
2465 * When this bit is '1', it indicates that the packet completed
2466 * was transmitted using the push acceleration data provided
2467 * by the driver. When this bit is '0', it indicates that the
2468 * packet had not push acceleration data written or was executed
2469 * as a normal packet even though push data was provided.
2471 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
2472 /* unused1 is 16 b */
2475 * This is a copy of the opaque field from the first TX BD of this
2476 * transmitted packet. Note that, if the packet was described by a short
2477 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2478 * short CSO BD will appear in the bottom 16 bits of this field.
2483 * This value is written by the NIC such that it will be different
2484 * for each pass through the completion queue. The even passes
2485 * will write 1. The odd passes will write 0.
2487 #define TX_CMPL_V UINT32_C(0x1)
2488 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2489 #define TX_CMPL_ERRORS_SFT 1
2491 * This error indicates that there was some sort of problem
2492 * with the BDs for the packet.
2494 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2495 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2497 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \
2498 (UINT32_C(0x0) << 1)
2501 * BDs were not formatted correctly.
2503 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \
2504 (UINT32_C(0x2) << 1)
2505 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
2506 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
2508 * When this bit is '1', it indicates that the length of
2509 * the packet was zero. No packet was transmitted.
2511 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2513 * When this bit is '1', it indicates that the packet
2514 * was longer than the programmed limit in TDI. No
2515 * packet was transmitted.
2517 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2519 * When this bit is '1', it indicates that one or more of the
2520 * BDs associated with this packet generated a PCI error.
2521 * This probably means the address was not valid.
2523 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
2525 * When this bit is '1', it indicates that the packet was longer
2526 * than indicated by the hint. No packet was transmitted.
2528 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2530 * When this bit is '1', it indicates that the packet was
2531 * dropped due to Poison TLP error on one or more of the
2532 * TLPs in the PXP completion.
2534 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2536 * When this bit is '1', it indicates that the packet was dropped
2537 * due to a transient internal error in TDC. The packet or LSO can
2538 * be retried and may transmit successfully on a subsequent attempt.
2540 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2542 * When this bit is '1', it was not possible to collect a a timestamp
2543 * for a PTP completion, in which case the timestamp_hi and
2544 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2545 * completion, the timestamp_hi and timestamp_lo fields are valid.
2546 * RJRN will copy the value of this bit into the field of the same
2547 * name in all TX completions, regardless of whether such completions
2548 * are PTP completions or other TX completions.
2550 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2551 /* unused2 is 16 b */
2553 /* unused3 is 32 b */
2557 /* tx_cmpl_coal (size:128b/16B) */
2558 struct tx_cmpl_coal {
2559 uint16_t flags_type;
2561 * This field indicates the exact type of the completion.
2562 * By convention, the LSB identifies the length of the
2563 * record in 16B units. Even values indicate 16B
2564 * records. Odd values indicate 32B
2567 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
2568 #define TX_CMPL_COAL_TYPE_SFT 0
2570 * TX L2 coalesced completion:
2571 * Completion of TX packet. Length = 16B
2573 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
2574 #define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
2575 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
2576 #define TX_CMPL_COAL_FLAGS_SFT 6
2578 * When this bit is '1', it indicates a packet that has an
2579 * error of some type. Type of error is indicated in
2582 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
2584 * When this bit is '1', it indicates that the packet completed
2585 * was transmitted using the push acceleration data provided
2586 * by the driver. When this bit is '0', it indicates that the
2587 * packet had not push acceleration data written or was executed
2588 * as a normal packet even though push data was provided.
2590 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
2591 /* unused1 is 16 b */
2594 * This is a copy of the opaque field from the first TX BD of the packet
2595 * which corresponds with the reported sq_cons_idx. Note that, with
2596 * coalesced completions, completions are generated for only some of the
2597 * packets. The driver will see the opaque field for only those packets.
2598 * Note that, if the packet was described by a short CSO or short CSO
2599 * inline BD, then the 16-bit opaque field from the short CSO BD will
2600 * appear in the bottom 16 bits of this field. For TX rings with
2601 * completion coalescing enabled (which would use the coalesced
2602 * completion record), it is suggested that the driver populate the
2603 * opaque field to indicate the specific TX ring with which the
2604 * completion is associated, then utilize the opaque and sq_cons_idx
2605 * fields in the coalesced completion record to determine the specific
2606 * packets that are to be completed on that ring.
2611 * This value is written by the NIC such that it will be different
2612 * for each pass through the completion queue. The even passes
2613 * will write 1. The odd passes will write 0.
2615 #define TX_CMPL_COAL_V UINT32_C(0x1)
2616 #define TX_CMPL_COAL_ERRORS_MASK \
2618 #define TX_CMPL_COAL_ERRORS_SFT 1
2620 * This error indicates that there was some sort of problem
2621 * with the BDs for the packet.
2623 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2624 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
2626 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \
2627 (UINT32_C(0x0) << 1)
2630 * BDs were not formatted correctly.
2632 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \
2633 (UINT32_C(0x2) << 1)
2634 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \
2635 TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
2637 * When this bit is '1', it indicates that the length of
2638 * the packet was zero. No packet was transmitted.
2640 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2642 * When this bit is '1', it indicates that the packet
2643 * was longer than the programmed limit in TDI. No
2644 * packet was transmitted.
2646 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2648 * When this bit is '1', it indicates that one or more of the
2649 * BDs associated with this packet generated a PCI error.
2650 * This probably means the address was not valid.
2652 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
2654 * When this bit is '1', it indicates that the packet was longer
2655 * than indicated by the hint. No packet was transmitted.
2657 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2659 * When this bit is '1', it indicates that the packet was
2660 * dropped due to Poison TLP error on one or more of the
2661 * TLPs in the PXP completion.
2663 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \
2666 * When this bit is '1', it indicates that the packet was dropped
2667 * due to a transient internal error in TDC. The packet or LSO can
2668 * be retried and may transmit successfully on a subsequent attempt.
2670 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \
2673 * When this bit is '1', it was not possible to collect a a timestamp
2674 * for a PTP completion, in which case the timestamp_hi and
2675 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2676 * completion, the timestamp_hi and timestamp_lo fields are valid.
2677 * RJRN will copy the value of this bit into the field of the same
2678 * name in all TX completions, regardless of whether such
2679 * completions are PTP completions or other TX completions.
2681 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \
2683 /* unused2 is 16 b */
2685 uint32_t sq_cons_idx;
2687 * This value is SQ index for the start of the packet following the
2688 * last completed packet.
2690 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
2691 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
2694 /* tx_cmpl_ptp (size:128b/16B) */
2695 struct tx_cmpl_ptp {
2696 uint16_t flags_type;
2698 * This field indicates the exact type of the completion.
2699 * By convention, the LSB identifies the length of the
2700 * record in 16B units. Even values indicate 16B
2701 * records. Odd values indicate 32B
2704 #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)
2705 #define TX_CMPL_PTP_TYPE_SFT 0
2707 * TX L2 PTP completion:
2708 * Completion of TX packet. Length = 32B
2710 #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)
2711 #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP
2712 #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)
2713 #define TX_CMPL_PTP_FLAGS_SFT 6
2715 * When this bit is '1', it indicates a packet that has an
2716 * error of some type. Type of error is indicated in
2719 #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)
2721 * When this bit is '1', it indicates that the packet completed
2722 * was transmitted using the push acceleration data provided
2723 * by the driver. When this bit is '0', it indicates that the
2724 * packet had not push acceleration data written or was executed
2725 * as a normal packet even though push data was provided.
2727 #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)
2728 /* unused1 is 16 b */
2731 * This is a copy of the opaque field from the first TX BD of this
2732 * transmitted packet. Note that, if the packet was described by a short
2733 * CSO or short CSO inline BD, then the 16-bit opaque field from the
2734 * short CSO BD will appear in the bottom 16 bits of this field.
2739 * This value is written by the NIC such that it will be different
2740 * for each pass through the completion queue. The even passes
2741 * will write 1. The odd passes will write 0.
2743 #define TX_CMPL_PTP_V UINT32_C(0x1)
2744 #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)
2745 #define TX_CMPL_PTP_ERRORS_SFT 1
2747 * This error indicates that there was some sort of problem
2748 * with the BDs for the packet.
2750 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2751 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1
2753 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \
2754 (UINT32_C(0x0) << 1)
2757 * BDs were not formatted correctly.
2759 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \
2760 (UINT32_C(0x2) << 1)
2761 #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \
2762 TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT
2764 * When this bit is '1', it indicates that the length of
2765 * the packet was zero. No packet was transmitted.
2767 #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
2769 * When this bit is '1', it indicates that the packet
2770 * was longer than the programmed limit in TDI. No
2771 * packet was transmitted.
2773 #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
2775 * When this bit is '1', it indicates that one or more of the
2776 * BDs associated with this packet generated a PCI error.
2777 * This probably means the address was not valid.
2779 #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)
2781 * When this bit is '1', it indicates that the packet was longer
2782 * than indicated by the hint. No packet was transmitted.
2784 #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
2786 * When this bit is '1', it indicates that the packet was
2787 * dropped due to Poison TLP error on one or more of the
2788 * TLPs in the PXP completion.
2790 #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
2792 * When this bit is '1', it indicates that the packet was dropped due
2793 * to a transient internal error in TDC. The packet or LSO can be
2794 * retried and may transmit successfully on a subsequent attempt.
2796 #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
2798 * When this bit is '1', it was not possible to collect a a timestamp
2799 * for a PTP completion, in which case the timestamp_hi and
2800 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
2801 * completion, the timestamp_hi and timestamp_lo fields are valid.
2802 * RJRN will copy the value of this bit into the field of the same
2803 * name in all TX completions, regardless of whether such
2804 * completions are PTP completions or other TX completions.
2806 #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
2807 /* unused2 is 16 b */
2810 * This is timestamp value (lower 32bits) read from PM for the PTP
2811 * timestamp enabled packet.
2813 uint32_t timestamp_lo;
2816 /* tx_cmpl_ptp_hi (size:128b/16B) */
2817 struct tx_cmpl_ptp_hi {
2819 * This is timestamp value (lower 32bits) read from PM for the PTP
2820 * timestamp enabled packet.
2822 uint16_t timestamp_hi[3];
2823 uint16_t reserved16;
2826 * This value is written by the NIC such that it will be different for
2827 * each pass through the completion queue.The even passes will write 1.
2828 * The odd passes will write 0
2830 #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)
2833 /* rx_pkt_cmpl (size:128b/16B) */
2834 struct rx_pkt_cmpl {
2835 uint16_t flags_type;
2837 * This field indicates the exact type of the completion.
2838 * By convention, the LSB identifies the length of the
2839 * record in 16B units. Even values indicate 16B
2840 * records. Odd values indicate 32B
2843 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
2844 #define RX_PKT_CMPL_TYPE_SFT 0
2847 * Completion of and L2 RX packet. Length = 32B
2849 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
2850 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
2851 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2852 #define RX_PKT_CMPL_FLAGS_SFT 6
2854 * When this bit is '1', it indicates a packet that has an
2855 * error of some type. Type of error is indicated in
2858 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
2859 /* This field indicates how the packet was placed in the buffer. */
2860 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2861 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
2864 * Packet was placed using normal algorithm.
2866 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
2869 * Packet was placed using jumbo algorithm.
2871 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
2873 * Header/Data Separation:
2874 * Packet was placed using Header/Data separation algorithm.
2875 * The separation location is indicated by the itype field.
2877 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
2878 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
2879 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
2880 /* This bit is '1' if the RSS field in this completion is valid. */
2881 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2883 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2885 * This value indicates what the inner packet determined for the
2888 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2889 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
2892 * Indicates that the packet type was not known.
2894 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
2895 (UINT32_C(0x0) << 12)
2898 * Indicates that the packet was an IP packet, but further
2899 * classification was not possible.
2901 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
2902 (UINT32_C(0x1) << 12)
2905 * Indicates that the packet was IP and TCP.
2906 * This indicates that the payload_offset field is valid.
2908 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2909 (UINT32_C(0x2) << 12)
2912 * Indicates that the packet was IP and UDP.
2913 * This indicates that the payload_offset field is valid.
2915 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2916 (UINT32_C(0x3) << 12)
2919 * Indicates that the packet was recognized as a FCoE.
2920 * This also indicates that the payload_offset field is valid.
2922 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2923 (UINT32_C(0x4) << 12)
2926 * Indicates that the packet was recognized as a RoCE.
2927 * This also indicates that the payload_offset field is valid.
2929 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2930 (UINT32_C(0x5) << 12)
2933 * Indicates that the packet was recognized as ICMP.
2934 * This indicates that the payload_offset field is valid.
2936 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2937 (UINT32_C(0x7) << 12)
2939 * PtP packet wo/timestamp:
2940 * Indicates that the packet was recognized as a PtP
2943 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2944 (UINT32_C(0x8) << 12)
2946 * PtP packet w/timestamp:
2947 * Indicates that the packet was recognized as a PtP
2948 * packet and that a timestamp was taken for the packet.
2950 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2951 (UINT32_C(0x9) << 12)
2952 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2953 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2955 * This is the length of the data for the packet stored in the
2956 * buffer(s) identified by the opaque value. This includes
2957 * the packet BD and any associated buffer BDs. This does not include
2958 * the length of any data places in aggregation BDs.
2962 * This is a copy of the opaque field from the RX BD this completion
2966 uint8_t agg_bufs_v1;
2968 * This value is written by the NIC such that it will be different
2969 * for each pass through the completion queue. The even passes
2970 * will write 1. The odd passes will write 0.
2972 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2974 * This value is the number of aggregation buffers that follow this
2975 * entry in the completion ring that are a part of this packet.
2976 * If the value is zero, then the packet is completely contained
2977 * in the buffer space provided for the packet in the RX ring.
2979 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2980 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2981 /* unused1 is 2 b */
2982 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2983 #define RX_PKT_CMPL_UNUSED1_SFT 6
2985 * This is the RSS hash type for the packet. The value is packed
2986 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2988 * The value of tuple_extrac_op provides the information about
2989 * what fields the hash was computed on.
2990 * * 0: The RSS hash was computed over source IP address,
2991 * destination IP address, source port, and destination port of inner
2992 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2993 * the packet headers are considered inner packet headers for the RSS
2994 * hash computation purpose.
2995 * * 1: The RSS hash was computed over source IP address and destination
2996 * IP address of inner IP header. Note: For non-tunneled packets,
2997 * the packet headers are considered inner packet headers for the RSS
2998 * hash computation purpose.
2999 * * 2: The RSS hash was computed over source IP address,
3000 * destination IP address, source port, and destination port of
3001 * IP and TCP or UDP headers of outer tunnel headers.
3002 * Note: For non-tunneled packets, this value is not applicable.
3003 * * 3: The RSS hash was computed over source IP address and
3004 * destination IP address of IP header of outer tunnel headers.
3005 * Note: For non-tunneled packets, this value is not applicable.
3007 * Note that 4-tuples values listed above are applicable
3008 * for layer 4 protocols supported and enabled for RSS in the hardware,
3009 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3010 * enabled for TCP traffic only, then the values of tuple_extract_op
3011 * corresponding to 4-tuples are only valid for TCP traffic.
3013 uint8_t rss_hash_type;
3015 * This value indicates the offset in bytes from the beginning of the packet
3016 * where the inner payload starts. This value is valid for TCP, UDP,
3017 * FCoE, and RoCE packets.
3019 * A value of zero indicates that header is 256B into the packet.
3021 uint8_t payload_offset;
3022 /* unused2 is 8 b */
3025 * This value is the RSS hash value calculated for the packet
3026 * based on the mode bits and key value in the VNIC.
3031 /* Last 16 bytes of rx_pkt_cmpl. */
3032 /* rx_pkt_cmpl_hi (size:128b/16B) */
3033 struct rx_pkt_cmpl_hi {
3036 * This indicates that the ip checksum was calculated for the
3037 * inner packet and that the ip_cs_error field indicates if there
3040 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
3042 * This indicates that the TCP, UDP or ICMP checksum was
3043 * calculated for the inner packet and that the l4_cs_error field
3044 * indicates if there was an error.
3046 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
3048 * This indicates that the ip checksum was calculated for the
3049 * tunnel header and that the t_ip_cs_error field indicates if there
3052 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
3054 * This indicates that the UDP checksum was
3055 * calculated for the tunnel packet and that the t_l4_cs_error field
3056 * indicates if there was an error.
3058 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
3059 /* This value indicates what format the metadata field is. */
3060 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
3061 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
3062 /* No metadata information. Value is zero. */
3063 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
3064 (UINT32_C(0x0) << 4)
3066 * The metadata field contains the VLAN tag and TPID value.
3067 * - metadata[11:0] contains the vlan VID value.
3068 * - metadata[12] contains the vlan DE value.
3069 * - metadata[15:13] contains the vlan PRI value.
3070 * - metadata[31:16] contains the vlan TPID value.
3072 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
3073 (UINT32_C(0x1) << 4)
3075 * If ext_meta_format is equal to 1, the metadata field
3076 * contains the lower 16b of the tunnel ID value, justified
3078 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3079 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
3080 * - NVGRE = TNI[23:0] -> Tenant Network ID
3081 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
3082 * - IPV4 = 0 (not populated)
3083 * - IPV6 = Flow Label[19:0]
3084 * - PPPoE = sessionID[15:0]
3085 * - MPLs = Outer label[19:0]
3086 * - UPAR = Selected[31:0] with bit mask
3088 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
3089 (UINT32_C(0x2) << 4)
3091 * if ext_meta_format is equal to 1, metadata field contains
3092 * 16b metadata from the prepended header (chdr_data).
3094 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
3095 (UINT32_C(0x3) << 4)
3097 * If ext_meta_format is equal to 1, the metadata field contains
3098 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
3100 * - metadata[8:0] contains the outer_l3_offset.
3101 * - metadata[17:9] contains the inner_l2_offset.
3102 * - metadata[26:18] contains the inner_l3_offset.
3103 * - metadata[31:27] contains the inner_l4_size.
3105 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
3106 (UINT32_C(0x4) << 4)
3107 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
3108 RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
3110 * This field indicates the IP type for the inner-most IP header.
3111 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3112 * This value is only valid if itype indicates a packet
3113 * with an IP header.
3115 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
3117 * This indicates that the complete 1's complement checksum was
3118 * calculated for the packet.
3120 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
3122 * The combination of this value and meta_format indicated what
3123 * format the metadata field is.
3125 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
3126 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
3128 * This value is the complete 1's complement checksum calculated from
3129 * the start of the outer L3 header to the end of the packet (not
3130 * including the ethernet crc). It is valid when the
3131 * 'complete_checksum_calc' flag is set.
3133 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
3134 UINT32_C(0xffff0000)
3135 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3137 * This is data from the CFA block as indicated by the meta_format
3141 /* When meta_format=1, this value is the VLAN VID. */
3142 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
3143 #define RX_PKT_CMPL_METADATA_VID_SFT 0
3144 /* When meta_format=1, this value is the VLAN DE. */
3145 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
3146 /* When meta_format=1, this value is the VLAN PRI. */
3147 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
3148 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
3149 /* When meta_format=1, this value is the VLAN TPID. */
3150 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
3151 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
3154 * This value is written by the NIC such that it will be different
3155 * for each pass through the completion queue. The even passes
3156 * will write 1. The odd passes will write 0.
3158 #define RX_PKT_CMPL_V2 \
3160 #define RX_PKT_CMPL_ERRORS_MASK \
3162 #define RX_PKT_CMPL_ERRORS_SFT 1
3164 * This error indicates that there was some sort of problem with
3165 * the BDs for the packet that was found after part of the
3166 * packet was already placed. The packet should be treated as
3169 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
3171 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
3172 /* No buffer error */
3173 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
3174 (UINT32_C(0x0) << 1)
3177 * Packet did not fit into packet buffer provided.
3178 * For regular placement, this means the packet did not fit
3179 * in the buffer provided. For HDS and jumbo placement, this
3180 * means that the packet could not be placed into 7 physical
3183 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3184 (UINT32_C(0x1) << 1)
3187 * All BDs needed for the packet were not on-chip when
3188 * the packet arrived.
3190 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3191 (UINT32_C(0x2) << 1)
3194 * BDs were not formatted correctly.
3196 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3197 (UINT32_C(0x3) << 1)
3200 * There was a bad_format error on the previous operation
3202 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
3203 (UINT32_C(0x5) << 1)
3204 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
3205 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
3207 * This indicates that there was an error in the IP header
3210 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
3213 * This indicates that there was an error in the TCP, UDP
3216 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
3219 * This indicates that there was an error in the tunnel
3220 * IP header checksum.
3222 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
3225 * This indicates that there was an error in the tunnel
3228 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
3231 * This indicates that there was a CRC error on either an FCoE
3232 * or RoCE packet. The itype indicates the packet type.
3234 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
3237 * This indicates that there was an error in the tunnel
3238 * portion of the packet when this
3239 * field is non-zero.
3241 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
3243 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
3245 * No additional error occurred on the tunnel portion
3246 * or the packet of the packet does not have a tunnel.
3248 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
3249 (UINT32_C(0x0) << 9)
3251 * Indicates that IP header version does not match
3252 * expectation from L2 Ethertype for IPv4 and IPv6
3253 * in the tunnel header.
3255 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3256 (UINT32_C(0x1) << 9)
3258 * Indicates that header length is out of range in the
3259 * tunnel header. Valid for
3262 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3263 (UINT32_C(0x2) << 9)
3265 * Indicates that the physical packet is shorter than that
3266 * claimed by the PPPoE header length for a tunnel PPPoE
3269 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
3270 (UINT32_C(0x3) << 9)
3272 * Indicates that physical packet is shorter than that claimed
3273 * by the tunnel l3 header length. Valid for IPv4, or IPv6
3274 * tunnel packet packets.
3276 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3277 (UINT32_C(0x4) << 9)
3279 * Indicates that the physical packet is shorter than that
3280 * claimed by the tunnel UDP header length for a tunnel
3281 * UDP packet that is not fragmented.
3283 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3284 (UINT32_C(0x5) << 9)
3286 * indicates that the IPv4 TTL or IPv6 hop limit check
3287 * have failed (e.g. TTL = 0) in the tunnel header. Valid
3288 * for IPv4, and IPv6.
3290 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3291 (UINT32_C(0x6) << 9)
3292 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
3293 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
3295 * This indicates that there was an error in the inner
3296 * portion of the packet when this
3297 * field is non-zero.
3299 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
3301 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
3303 * No additional error occurred on the tunnel portion
3304 * or the packet of the packet does not have a tunnel.
3306 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
3307 (UINT32_C(0x0) << 12)
3309 * Indicates that IP header version does not match
3310 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3311 * option other than VFT was parsed on
3314 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3315 (UINT32_C(0x1) << 12)
3317 * indicates that header length is out of range. Valid for
3320 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3321 (UINT32_C(0x2) << 12)
3323 * indicates that the IPv4 TTL or IPv6 hop limit check
3324 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3326 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
3327 (UINT32_C(0x3) << 12)
3329 * Indicates that physical packet is shorter than that
3330 * claimed by the l3 header length. Valid for IPv4,
3331 * IPv6 packet or RoCE packets.
3333 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3334 (UINT32_C(0x4) << 12)
3336 * Indicates that the physical packet is shorter than that
3337 * claimed by the UDP header length for a UDP packet that is
3340 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3341 (UINT32_C(0x5) << 12)
3343 * Indicates that TCP header length > IP payload. Valid for
3346 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3347 (UINT32_C(0x6) << 12)
3348 /* Indicates that TCP header length < 5. Valid for TCP. */
3349 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3350 (UINT32_C(0x7) << 12)
3352 * Indicates that TCP option headers result in a TCP header
3353 * size that does not match data offset in TCP header. Valid
3356 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3357 (UINT32_C(0x8) << 12)
3358 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
3359 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
3361 * This field identifies the CFA action rule that was used for this
3367 * This value holds the reordering sequence number for the packet.
3368 * If the reordering sequence is not valid, then this value is zero.
3369 * The reordering domain for the packet is in the bottom 8 to 10b of
3370 * the rss_hash value. The bottom 20b of this value contain the
3371 * ordering domain value for the packet.
3373 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
3374 #define RX_PKT_CMPL_REORDER_SFT 0
3377 /* rx_pkt_v2_cmpl (size:128b/16B) */
3378 struct rx_pkt_v2_cmpl {
3379 uint16_t flags_type;
3381 * This field indicates the exact type of the completion.
3382 * By convention, the LSB identifies the length of the
3383 * record in 16B units. Even values indicate 16B
3384 * records. Odd values indicate 32B
3387 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
3388 #define RX_PKT_V2_CMPL_TYPE_SFT 0
3390 * RX L2 V2 completion:
3391 * Completion of and L2 RX packet. Length = 32B
3392 * This is the new version of the RX_L2 completion used in SR2
3395 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
3396 #define RX_PKT_V2_CMPL_TYPE_LAST \
3397 RX_PKT_V2_CMPL_TYPE_RX_L2_V2
3398 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
3399 #define RX_PKT_V2_CMPL_FLAGS_SFT 6
3401 * When this bit is '1', it indicates a packet that has an
3402 * error of some type. Type of error is indicated in
3405 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
3406 /* This field indicates how the packet was placed in the buffer. */
3407 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
3408 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7
3411 * Packet was placed using normal algorithm.
3413 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \
3414 (UINT32_C(0x0) << 7)
3417 * Packet was placed using jumbo algorithm.
3419 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
3420 (UINT32_C(0x1) << 7)
3422 * Header/Data Separation:
3423 * Packet was placed using Header/Data separation algorithm.
3424 * The separation location is indicated by the itype field.
3426 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \
3427 (UINT32_C(0x2) << 7)
3430 * Packet was placed using truncation algorithm. The
3431 * placed (truncated) length is indicated in the payload_offset
3432 * field. The original length is indicated in the len field.
3434 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \
3435 (UINT32_C(0x3) << 7)
3436 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \
3437 RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION
3438 /* This bit is '1' if the RSS field in this completion is valid. */
3439 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
3441 * This bit is '1' if metadata has been added to the end of the
3442 * packet in host memory. Metadata starts at the first 32B boundary
3443 * after the end of the packet for regular and jumbo placement.
3444 * It starts at the first 32B boundary after the end of the header
3445 * for HDS placement. The length of the metadata is indicated in the
3448 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
3450 * This value indicates what the inner packet determined for the
3453 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
3454 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12
3457 * Indicates that the packet type was not known.
3459 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \
3460 (UINT32_C(0x0) << 12)
3463 * Indicates that the packet was an IP packet, but further
3464 * classification was not possible.
3466 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \
3467 (UINT32_C(0x1) << 12)
3470 * Indicates that the packet was IP and TCP.
3471 * This indicates that the payload_offset field is valid.
3473 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \
3474 (UINT32_C(0x2) << 12)
3477 * Indicates that the packet was IP and UDP.
3478 * This indicates that the payload_offset field is valid.
3480 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \
3481 (UINT32_C(0x3) << 12)
3484 * Indicates that the packet was recognized as a FCoE.
3485 * This also indicates that the payload_offset field is valid.
3487 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \
3488 (UINT32_C(0x4) << 12)
3491 * Indicates that the packet was recognized as a RoCE.
3492 * This also indicates that the payload_offset field is valid.
3494 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \
3495 (UINT32_C(0x5) << 12)
3498 * Indicates that the packet was recognized as ICMP.
3499 * This indicates that the payload_offset field is valid.
3501 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \
3502 (UINT32_C(0x7) << 12)
3504 * PtP packet wo/timestamp:
3505 * Indicates that the packet was recognized as a PtP
3508 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
3509 (UINT32_C(0x8) << 12)
3511 * PtP packet w/timestamp:
3512 * Indicates that the packet was recognized as a PtP
3513 * packet and that a timestamp was taken for the packet.
3515 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
3516 (UINT32_C(0x9) << 12)
3517 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \
3518 RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
3520 * This is the length of the data for the packet stored in the
3521 * buffer(s) identified by the opaque value. This includes
3522 * the packet BD and any associated buffer BDs. This does not include
3523 * the length of any data places in aggregation BDs.
3527 * This is a copy of the opaque field from the RX BD this completion
3531 uint8_t agg_bufs_v1;
3533 * This value is written by the NIC such that it will be different
3534 * for each pass through the completion queue. The even passes
3535 * will write 1. The odd passes will write 0.
3537 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
3539 * This value is the number of aggregation buffers that follow this
3540 * entry in the completion ring that are a part of this packet.
3541 * If the value is zero, then the packet is completely contained
3542 * in the buffer space provided for the packet in the RX ring.
3544 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
3545 #define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1
3546 /* unused1 is 2 b */
3547 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
3548 #define RX_PKT_V2_CMPL_UNUSED1_SFT 6
3550 * This is the RSS hash type for the packet. The value is packed
3551 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
3553 * The value of tuple_extrac_op provides the information about
3554 * what fields the hash was computed on.
3555 * * 0: The RSS hash was computed over source IP address,
3556 * destination IP address, source port, and destination port of inner
3557 * IP and TCP or UDP headers. Note: For non-tunneled packets,
3558 * the packet headers are considered inner packet headers for the RSS
3559 * hash computation purpose.
3560 * * 1: The RSS hash was computed over source IP address and destination
3561 * IP address of inner IP header. Note: For non-tunneled packets,
3562 * the packet headers are considered inner packet headers for the RSS
3563 * hash computation purpose.
3564 * * 2: The RSS hash was computed over source IP address,
3565 * destination IP address, source port, and destination port of
3566 * IP and TCP or UDP headers of outer tunnel headers.
3567 * Note: For non-tunneled packets, this value is not applicable.
3568 * * 3: The RSS hash was computed over source IP address and
3569 * destination IP address of IP header of outer tunnel headers.
3570 * Note: For non-tunneled packets, this value is not applicable.
3572 * Note that 4-tuples values listed above are applicable
3573 * for layer 4 protocols supported and enabled for RSS in the hardware,
3574 * HWRM firmware, and drivers. For example, if RSS hash is supported and
3575 * enabled for TCP traffic only, then the values of tuple_extract_op
3576 * corresponding to 4-tuples are only valid for TCP traffic.
3578 uint8_t rss_hash_type;
3579 uint16_t metadata1_payload_offset;
3581 * This is data from the CFA as indicated by the meta_format field.
3582 * If truncation placement is not used, this value indicates the offset
3583 * in bytes from the beginning of the packet where the inner payload
3584 * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If
3585 * truncation placement is used, this value represents the placed
3586 * (truncated) length of the packet.
3588 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
3589 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
3590 /* This is data from the CFA as indicated by the meta_format field. */
3591 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
3592 #define RX_PKT_V2_CMPL_METADATA1_SFT 12
3593 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3594 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
3595 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12
3596 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
3597 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
3599 * This value is the RSS hash value calculated for the packet
3600 * based on the mode bits and key value in the VNIC. When vee_cmpl_mode
3601 * is set in VNIC context, this is the lower 32b of the host address
3602 * from the first BD used to place the packet.
3607 /* Last 16 bytes of RX Packet V2 Completion Record */
3608 /* rx_pkt_v2_cmpl_hi (size:128b/16B) */
3609 struct rx_pkt_v2_cmpl_hi {
3612 * When this bit is '0', the cs_ok field has the following definition:-
3613 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
3614 * in the delivered packet, counted from the outer-most header group to
3615 * the inner-most header group, stopping at the first error. -
3616 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
3617 * in the delivered packet, counted from the outer-most header group to
3618 * the inner-most header group, stopping at the first error. When this
3619 * bit is '1', the cs_ok field has the following definition: -
3620 * hdr_cnt[2:0] = The number of header groups that were parsed by the
3621 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
3622 * will be '1' if all the parsed header groups with an IP checksum are
3623 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
3624 * header groups with an L4 checksum are valid.
3626 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \
3628 /* This value indicates what format the metadata field is. */
3629 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \
3631 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4
3632 /* There is no metadata information. Values are zero. */
3633 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \
3634 (UINT32_C(0x0) << 4)
3636 * The {metadata1, metadata0} fields contain the vtag
3637 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
3638 * de, vid[11:0]} The metadata2 field contains the table scope
3639 * and action record pointer. - metadata2[25:0] contains the
3640 * action record pointer. - metadata2[31:26] contains the table
3643 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \
3644 (UINT32_C(0x1) << 4)
3646 * The {metadata1, metadata0} fields contain the vtag
3648 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3649 * The metadata2 field contains the Tunnel ID
3650 * value, justified to LSB. i
3651 * - VXLAN = VNI[23:0] -> VXLAN Network ID
3652 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
3653 * - NVGRE = TNI[23:0] -> Tenant Network ID
3654 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
3655 * - IPv4 = 0 (not populated)
3656 * - IPv6 = Flow Label[19:0]
3657 * - PPPoE = sessionID[15:0]
3658 * - MPLs = Outer label[19:0]
3659 * - UPAR = Selected[31:0] with bit mask
3661 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \
3662 (UINT32_C(0x2) << 4)
3664 * The {metadata1, metadata0} fields contain the vtag
3666 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
3667 * The metadata2 field contains the 32b metadata from the prepended
3668 * header (chdr_data).
3670 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \
3671 (UINT32_C(0x3) << 4)
3673 * The {metadata1, metadata0} fields contain the vtag
3675 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
3676 * The metadata2 field contains the outer_l3_offset,
3677 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
3678 * - metadata2[8:0] contains the outer_l3_offset.
3679 * - metadata2[17:9] contains the inner_l2_offset.
3680 * - metadata2[26:18] contains the inner_l3_offset.
3681 * - metadata2[31:27] contains the inner_l4_size.
3683 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \
3684 (UINT32_C(0x4) << 4)
3685 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \
3686 RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET
3688 * This field indicates the IP type for the inner-most IP header.
3689 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
3690 * This value is only valid if itype indicates a packet
3691 * with an IP header.
3693 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \
3696 * This indicates that the complete 1's complement checksum was
3697 * calculated for the packet.
3699 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \
3702 * This field indicates the status of IP and L4 CS calculations done
3703 * by the chip. The format of this field is indicated by the
3704 * cs_all_ok_mode bit.
3706 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \
3708 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10
3710 * This value is the complete 1's complement checksum calculated from
3711 * the start of the outer L3 header to the end of the packet (not
3712 * including the ethernet crc). It is valid when the
3713 * 'complete_checksum_calc' flag is set.
3715 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \
3716 UINT32_C(0xffff0000)
3717 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16
3719 * This is data from the CFA block as indicated by the meta_format
3721 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
3722 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
3723 * act_rec_ptr[25:0]}
3724 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
3725 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
3726 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
3727 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
3728 * of the host address from the first BD used to place the packet.
3733 * This value is written by the NIC such that it will be different
3734 * for each pass through the completion queue. The even passes
3735 * will write 1. The odd passes will write 0.
3737 #define RX_PKT_V2_CMPL_HI_V2 \
3739 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK \
3741 #define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1
3743 * This error indicates that there was some sort of problem with
3744 * the BDs for the packet that was found after part of the
3745 * packet was already placed. The packet should be treated as
3748 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \
3750 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1
3751 /* No buffer error */
3752 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \
3753 (UINT32_C(0x0) << 1)
3755 * Did Not Fit: Packet did not fit into packet buffer provided.
3756 * For regular placement, this means the packet did not fit in
3757 * the buffer provided. For HDS and jumbo placement, this means
3758 * that the packet could not be placed into 8 physical buffers
3759 * (if fixed-size buffers are used), or that the packet could
3760 * not be placed in the number of physical buffers configured
3761 * for the VNIC (if variable-size buffers are used)
3763 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
3764 (UINT32_C(0x1) << 1)
3766 * Not On Chip: All BDs needed for the packet were not on-chip
3767 * when the packet arrived. For regular placement, this error is
3768 * not valid. For HDS and jumbo placement, this means that not
3769 * enough agg BDs were posted to place the packet.
3771 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
3772 (UINT32_C(0x2) << 1)
3775 * BDs were not formatted correctly.
3777 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \
3778 (UINT32_C(0x3) << 1)
3781 * There was a bad_format error on the previous operation
3783 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \
3784 (UINT32_C(0x5) << 1)
3785 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \
3786 RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH
3788 * This indicates that there was an error in the outer tunnel
3789 * portion of the packet when this field is non-zero.
3791 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \
3793 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4
3795 * No additional error occurred on the outer tunnel portion
3796 * of the packet or the packet does not have a outer tunnel.
3798 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \
3799 (UINT32_C(0x0) << 4)
3801 * Indicates that IP header version does not match expectation
3802 * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.
3804 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \
3805 (UINT32_C(0x1) << 4)
3807 * Indicates that header length is out of range in the outer
3808 * tunnel header. Valid for IPv4.
3810 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \
3811 (UINT32_C(0x2) << 4)
3813 * Indicates that physical packet is shorter than that claimed
3814 * by the outer tunnel l3 header length. Valid for IPv4, or
3815 * IPv6 outer tunnel packets.
3817 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \
3818 (UINT32_C(0x3) << 4)
3820 * Indicates that the physical packet is shorter than that
3821 * claimed by the outer tunnel UDP header length for a outer
3822 * tunnel UDP packet that is not fragmented.
3824 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \
3825 (UINT32_C(0x4) << 4)
3827 * Indicates that the IPv4 TTL or IPv6 hop limit check have
3828 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
3831 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \
3832 (UINT32_C(0x5) << 4)
3834 * Indicates that the IP checksum failed its check in the outer
3837 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \
3838 (UINT32_C(0x6) << 4)
3840 * Indicates that the L4 checksum failed its check in the outer
3843 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \
3844 (UINT32_C(0x7) << 4)
3845 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \
3846 RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR
3848 * This indicates that there was a CRC error on either an FCoE
3849 * or RoCE packet. The itype indicates the packet type.
3851 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \
3854 * This indicates that there was an error in the tunnel portion
3855 * of the packet when this field is non-zero.
3857 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \
3859 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9
3861 * No additional error occurred on the tunnel portion
3862 * of the packet or the packet does not have a tunnel.
3864 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \
3865 (UINT32_C(0x0) << 9)
3867 * Indicates that IP header version does not match expectation
3868 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
3870 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
3871 (UINT32_C(0x1) << 9)
3873 * Indicates that header length is out of range in the tunnel
3874 * header. Valid for IPv4.
3876 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
3877 (UINT32_C(0x2) << 9)
3879 * Indicates that physical packet is shorter than that claimed
3880 * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel
3883 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
3884 (UINT32_C(0x3) << 9)
3886 * Indicates that the physical packet is shorter than that claimed
3887 * by the tunnel UDP header length for a tunnel UDP packet that is
3890 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
3891 (UINT32_C(0x4) << 9)
3893 * Indicates that the IPv4 TTL or IPv6 hop limit check have failed
3894 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
3896 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
3897 (UINT32_C(0x5) << 9)
3899 * Indicates that the IP checksum failed its check in the tunnel
3902 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \
3903 (UINT32_C(0x6) << 9)
3905 * Indicates that the L4 checksum failed its check in the tunnel
3908 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \
3909 (UINT32_C(0x7) << 9)
3910 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \
3911 RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR
3913 * This indicates that there was an error in the inner
3914 * portion of the packet when this
3915 * field is non-zero.
3917 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \
3919 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12
3921 * No additional error occurred on the tunnel portion
3922 * or the packet of the packet does not have a tunnel.
3924 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \
3925 (UINT32_C(0x0) << 12)
3927 * Indicates that IP header version does not match
3928 * expectation from L2 Ethertype for IPv4 and IPv6 or that
3929 * option other than VFT was parsed on
3932 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \
3933 (UINT32_C(0x1) << 12)
3935 * indicates that header length is out of range. Valid for
3938 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
3939 (UINT32_C(0x2) << 12)
3941 * indicates that the IPv4 TTL or IPv6 hop limit check
3942 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
3944 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \
3945 (UINT32_C(0x3) << 12)
3947 * Indicates that physical packet is shorter than that
3948 * claimed by the l3 header length. Valid for IPv4,
3949 * IPv6 packet or RoCE packets.
3951 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
3952 (UINT32_C(0x4) << 12)
3954 * Indicates that the physical packet is shorter than that
3955 * claimed by the UDP header length for a UDP packet that is
3958 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
3959 (UINT32_C(0x5) << 12)
3961 * Indicates that TCP header length > IP payload. Valid for
3964 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
3965 (UINT32_C(0x6) << 12)
3966 /* Indicates that TCP header length < 5. Valid for TCP. */
3967 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
3968 (UINT32_C(0x7) << 12)
3970 * Indicates that TCP option headers result in a TCP header
3971 * size that does not match data offset in TCP header. Valid
3974 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
3975 (UINT32_C(0x8) << 12)
3977 * Indicates that the IP checksum failed its check in the
3980 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \
3981 (UINT32_C(0x9) << 12)
3983 * Indicates that the L4 checksum failed its check in the
3986 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \
3987 (UINT32_C(0xa) << 12)
3988 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \
3989 RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR
3991 * This is data from the CFA block as indicated by the meta_format
3995 /* When meta_format=1, this value is the VLAN VID. */
3996 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
3997 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
3998 /* When meta_format=1, this value is the VLAN DE. */
3999 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
4000 /* When meta_format=1, this value is the VLAN PRI. */
4001 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
4002 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13
4004 * The timestamp field contains the 32b timestamp for the packet from
4011 * This TPA completion structure is used on devices where the
4012 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4014 /* rx_tpa_start_cmpl (size:128b/16B) */
4015 struct rx_tpa_start_cmpl {
4016 uint16_t flags_type;
4018 * This field indicates the exact type of the completion.
4019 * By convention, the LSB identifies the length of the
4020 * record in 16B units. Even values indicate 16B
4021 * records. Odd values indicate 32B
4024 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
4025 #define RX_TPA_START_CMPL_TYPE_SFT 0
4027 * RX L2 TPA Start Completion:
4028 * Completion at the beginning of a TPA operation.
4031 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
4032 #define RX_TPA_START_CMPL_TYPE_LAST \
4033 RX_TPA_START_CMPL_TYPE_RX_TPA_START
4034 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4035 #define RX_TPA_START_CMPL_FLAGS_SFT 6
4036 /* This bit will always be '0' for TPA start completions. */
4037 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
4038 /* This field indicates how the packet was placed in the buffer. */
4039 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4040 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
4043 * TPA Packet was placed using jumbo algorithm. This means
4044 * that the first buffer will be filled with data before
4045 * moving to aggregation buffers. Each aggregation buffer
4046 * will be filled before moving to the next aggregation
4049 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
4050 (UINT32_C(0x1) << 7)
4052 * Header/Data Separation:
4053 * Packet was placed using Header/Data separation algorithm.
4054 * The separation location is indicated by the itype field.
4056 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
4057 (UINT32_C(0x2) << 7)
4060 * Packet will be placed using GRO/Jumbo where the first
4061 * packet is filled with data. Subsequent packets will be
4062 * placed such that any one packet does not span two
4063 * aggregation buffers unless it starts at the beginning of
4064 * an aggregation buffer.
4066 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4067 (UINT32_C(0x5) << 7)
4069 * GRO/Header-Data Separation:
4070 * Packet will be placed using GRO/HDS where the header
4071 * is in the first packet.
4072 * Payload of each packet will be
4073 * placed such that any one packet does not span two
4074 * aggregation buffers unless it starts at the beginning of
4075 * an aggregation buffer.
4077 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4078 (UINT32_C(0x6) << 7)
4079 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
4080 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
4081 /* This bit is '1' if the RSS field in this completion is valid. */
4082 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
4084 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
4086 * This value indicates what the inner packet determined for the
4089 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
4090 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
4093 * Indicates that the packet was IP and TCP.
4095 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
4096 (UINT32_C(0x2) << 12)
4097 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
4098 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
4100 * This value indicates the amount of packet data written to the
4101 * buffer the opaque field in this completion corresponds to.
4105 * This is a copy of the opaque field from the RX BD this completion
4110 * This value is written by the NIC such that it will be different
4111 * for each pass through the completion queue. The even passes
4112 * will write 1. The odd passes will write 0.
4116 * This value is written by the NIC such that it will be different
4117 * for each pass through the completion queue. The even passes
4118 * will write 1. The odd passes will write 0.
4120 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
4121 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
4123 * This is the RSS hash type for the packet. The value is packed
4124 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4126 * The value of tuple_extrac_op provides the information about
4127 * what fields the hash was computed on.
4128 * * 0: The RSS hash was computed over source IP address,
4129 * destination IP address, source port, and destination port of inner
4130 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4131 * the packet headers are considered inner packet headers for the RSS
4132 * hash computation purpose.
4133 * * 1: The RSS hash was computed over source IP address and destination
4134 * IP address of inner IP header. Note: For non-tunneled packets,
4135 * the packet headers are considered inner packet headers for the RSS
4136 * hash computation purpose.
4137 * * 2: The RSS hash was computed over source IP address,
4138 * destination IP address, source port, and destination port of
4139 * IP and TCP or UDP headers of outer tunnel headers.
4140 * Note: For non-tunneled packets, this value is not applicable.
4141 * * 3: The RSS hash was computed over source IP address and
4142 * destination IP address of IP header of outer tunnel headers.
4143 * Note: For non-tunneled packets, this value is not applicable.
4145 * Note that 4-tuples values listed above are applicable
4146 * for layer 4 protocols supported and enabled for RSS in the hardware,
4147 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4148 * enabled for TCP traffic only, then the values of tuple_extract_op
4149 * corresponding to 4-tuples are only valid for TCP traffic.
4151 uint8_t rss_hash_type;
4153 * This is the aggregation ID that the completion is associated
4154 * with. Use this number to correlate the TPA start completion
4155 * with the TPA end completion.
4158 /* unused2 is 9 b */
4159 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
4160 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
4162 * This is the aggregation ID that the completion is associated
4163 * with. Use this number to correlate the TPA start completion
4164 * with the TPA end completion.
4166 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
4167 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
4169 * This value is the RSS hash value calculated for the packet
4170 * based on the mode bits and key value in the VNIC.
4176 * Last 16 bytes of rx_tpa_start_cmpl.
4178 * This TPA completion structure is used on devices where the
4179 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4181 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
4182 struct rx_tpa_start_cmpl_hi {
4185 * This indicates that the ip checksum was calculated for the
4186 * inner packet and that the sum passed for all segments
4187 * included in the aggregation.
4189 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4191 * This indicates that the TCP, UDP or ICMP checksum was
4192 * calculated for the inner packet and that the sum passed
4193 * for all segments included in the aggregation.
4195 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4197 * This indicates that the ip checksum was calculated for the
4198 * tunnel header and that the sum passed for all segments
4199 * included in the aggregation.
4201 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4203 * This indicates that the UDP checksum was
4204 * calculated for the tunnel packet and that the sum passed for
4205 * all segments included in the aggregation.
4207 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4208 /* This value indicates what format the metadata field is. */
4209 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4210 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
4211 /* No metadata information. Value is zero. */
4212 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
4213 (UINT32_C(0x0) << 4)
4215 * The metadata field contains the VLAN tag and TPID value.
4216 * - metadata[11:0] contains the vlan VID value.
4217 * - metadata[12] contains the vlan DE value.
4218 * - metadata[15:13] contains the vlan PRI value.
4219 * - metadata[31:16] contains the vlan TPID value.
4221 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
4222 (UINT32_C(0x1) << 4)
4223 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
4224 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
4226 * This field indicates the IP type for the inner-most IP header.
4227 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4229 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
4231 * This is data from the CFA block as indicated by the meta_format
4235 /* When meta_format=1, this value is the VLAN VID. */
4236 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
4237 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
4238 /* When meta_format=1, this value is the VLAN DE. */
4239 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
4240 /* When meta_format=1, this value is the VLAN PRI. */
4241 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
4242 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
4243 /* When meta_format=1, this value is the VLAN TPID. */
4244 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
4245 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
4248 * This value is written by the NIC such that it will be different
4249 * for each pass through the completion queue. The even passes
4250 * will write 1. The odd passes will write 0.
4252 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
4254 * This field identifies the CFA action rule that was used for this
4259 * This is the size in bytes of the inner most L4 header.
4260 * This can be subtracted from the payload_offset to determine
4261 * the start of the inner most L4 header.
4263 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
4265 * This is the offset from the beginning of the packet in bytes for
4266 * the outer L3 header. If there is no outer L3 header, then this
4269 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
4270 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
4272 * This is the offset from the beginning of the packet in bytes for
4273 * the inner most L2 header.
4275 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
4276 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
4278 * This is the offset from the beginning of the packet in bytes for
4279 * the inner most L3 header.
4281 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
4282 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
4284 * This is the size in bytes of the inner most L4 header.
4285 * This can be subtracted from the payload_offset to determine
4286 * the start of the inner most L4 header.
4288 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
4289 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
4293 * This TPA completion structure is used on devices where the
4294 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4295 * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte
4298 /* rx_tpa_start_v2_cmpl (size:128b/16B) */
4299 struct rx_tpa_start_v2_cmpl {
4300 uint16_t flags_type;
4302 * This field indicates the exact type of the completion.
4303 * By convention, the LSB identifies the length of the
4304 * record in 16B units. Even values indicate 16B
4305 * records. Odd values indicate 32B
4308 #define RX_TPA_START_V2_CMPL_TYPE_MASK \
4310 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
4312 * RX L2 TPA Start V2 Completion:
4313 * Completion at the beginning of a TPA operation.
4315 * This is the new version of the RX_TPA_START completion used
4316 * in SR2 and later chips.
4318 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \
4320 #define RX_TPA_START_V2_CMPL_TYPE_LAST \
4321 RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2
4322 #define RX_TPA_START_V2_CMPL_FLAGS_MASK \
4324 #define RX_TPA_START_V2_CMPL_FLAGS_SFT 6
4326 * When this bit is '1', it indicates a packet that has an error
4327 * of some type. Type of error is indicated in error_flags.
4329 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR \
4331 /* This field indicates how the packet was placed in the buffer. */
4332 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \
4334 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7
4337 * TPA Packet was placed using jumbo algorithm. This means
4338 * that the first buffer will be filled with data before
4339 * moving to aggregation buffers. Each aggregation buffer
4340 * will be filled before moving to the next aggregation
4343 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \
4344 (UINT32_C(0x1) << 7)
4346 * Header/Data Separation:
4347 * Packet was placed using Header/Data separation algorithm.
4348 * The separation location is indicated by the itype field.
4350 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \
4351 (UINT32_C(0x2) << 7)
4354 * Packet will be placed using In-Order Completion/Jumbo where
4355 * the first packet of the aggregation is placed using Jumbo
4356 * Placement. Subsequent packets will be placed such that each
4357 * packet starts at the beginning of an aggregation buffer.
4359 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4360 (UINT32_C(0x4) << 7)
4363 * Packet will be placed using GRO/Jumbo where the first
4364 * packet is filled with data. Subsequent packets will be
4365 * placed such that any one packet does not span two
4366 * aggregation buffers unless it starts at the beginning of
4367 * an aggregation buffer.
4369 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4370 (UINT32_C(0x5) << 7)
4372 * GRO/Header-Data Separation:
4373 * Packet will be placed using GRO/HDS where the header
4374 * is in the first packet.
4375 * Payload of each packet will be
4376 * placed such that any one packet does not span two
4377 * aggregation buffers unless it starts at the beginning of
4378 * an aggregation buffer.
4380 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4381 (UINT32_C(0x6) << 7)
4383 * IOC/Header-Data Separation:
4384 * Packet will be placed using In-Order Completion/HDS where
4385 * the header is in the first packet buffer. Payload of each
4386 * packet will be placed such that each packet starts at the
4387 * beginning of an aggregation buffer.
4389 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4390 (UINT32_C(0x7) << 7)
4391 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \
4392 RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS
4393 /* This bit is '1' if the RSS field in this completion is valid. */
4394 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \
4397 * This bit is '1' if metadata has been added to the end of the
4398 * packet in host memory. Metadata starts at the first 32B boundary
4399 * after the end of the packet for regular and jumbo placement. It
4400 * starts at the first 32B boundary after the end of the header for
4401 * HDS placement. The length of the metadata is indicated in the
4404 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \
4407 * This value indicates what the inner packet determined for the
4410 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \
4412 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12
4415 * Indicates that the packet was IP and TCP.
4417 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \
4418 (UINT32_C(0x2) << 12)
4419 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \
4420 RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP
4422 * This value indicates the amount of packet data written to the
4423 * buffer the opaque field in this completion corresponds to.
4427 * This is a copy of the opaque field from the RX BD this completion
4428 * corresponds to. If the VNIC is configured to not use an Rx BD for
4429 * the TPA Start completion, then this is a copy of the opaque field
4430 * from the first BD used to place the TPA Start packet.
4434 * This value is written by the NIC such that it will be different
4435 * for each pass through the completion queue. The even passes
4436 * will write 1. The odd passes will write 0.
4440 * This value is written by the NIC such that it will be different
4441 * for each pass through the completion queue. The even passes
4442 * will write 1. The odd passes will write 0.
4444 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
4445 #define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1
4447 * This is the RSS hash type for the packet. The value is packed
4448 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
4450 * The value of tuple_extrac_op provides the information about
4451 * what fields the hash was computed on.
4452 * * 0: The RSS hash was computed over source IP address,
4453 * destination IP address, source port, and destination port of inner
4454 * IP and TCP or UDP headers. Note: For non-tunneled packets,
4455 * the packet headers are considered inner packet headers for the RSS
4456 * hash computation purpose.
4457 * * 1: The RSS hash was computed over source IP address and destination
4458 * IP address of inner IP header. Note: For non-tunneled packets,
4459 * the packet headers are considered inner packet headers for the RSS
4460 * hash computation purpose.
4461 * * 2: The RSS hash was computed over source IP address,
4462 * destination IP address, source port, and destination port of
4463 * IP and TCP or UDP headers of outer tunnel headers.
4464 * Note: For non-tunneled packets, this value is not applicable.
4465 * * 3: The RSS hash was computed over source IP address and
4466 * destination IP address of IP header of outer tunnel headers.
4467 * Note: For non-tunneled packets, this value is not applicable.
4469 * Note that 4-tuples values listed above are applicable
4470 * for layer 4 protocols supported and enabled for RSS in the hardware,
4471 * HWRM firmware, and drivers. For example, if RSS hash is supported and
4472 * enabled for TCP traffic only, then the values of tuple_extract_op
4473 * corresponding to 4-tuples are only valid for TCP traffic.
4475 uint8_t rss_hash_type;
4477 * This is the aggregation ID that the completion is associated
4478 * with. Use this number to correlate the TPA start completion
4479 * with the TPA end completion.
4483 * This is the aggregation ID that the completion is associated
4484 * with. Use this number to correlate the TPA start completion
4485 * with the TPA end completion.
4487 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
4488 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
4489 #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
4490 #define RX_TPA_START_V2_CMPL_METADATA1_SFT 12
4491 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
4492 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
4493 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12
4494 /* When meta_format != 0, this value is the VLAN valid. */
4495 #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
4497 * This value is the RSS hash value calculated for the packet
4498 * based on the mode bits and key value in the VNIC.
4499 * When vee_cmpl_mode is set in VNIC context, this is the lower
4500 * 32b of the host address from the first BD used to place the packet.
4506 * Last 16 bytes of RX L2 TPA Start V2 Completion Record
4508 * This TPA completion structure is used on devices where the
4509 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4511 /* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */
4512 struct rx_tpa_start_v2_cmpl_hi {
4514 /* This indicates that the aggregation was done using GRO rules. */
4515 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \
4518 * When this bit is '0', the cs_ok field has the following definition:-
4519 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
4520 * in the delivered packet, counted from the outer-most header group to
4521 * the inner-most header group, stopping at the first error. -
4522 * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum
4523 * in the delivered packet, counted from the outer-most header group to
4524 * the inner-most header group, stopping at the first error. When this
4525 * bit is '1', the cs_ok field has the following definition: -
4526 * hdr_cnt[2:0] = The number of header groups that were parsed by the
4527 * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit
4528 * will be '1' if all the parsed header groups with an IP checksum are
4529 * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed
4530 * header groups with an L4 checksum are valid.
4532 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \
4534 /* This value indicates what format the metadata field is. */
4535 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \
4537 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4
4538 /* There is no metadata information. Values are zero. */
4539 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \
4540 (UINT32_C(0x0) << 4)
4542 * The {metadata1, metadata0} fields contain the vtag
4543 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
4544 * de, vid[11:0]} The metadata2 field contains the table scope
4545 * and action record pointer. - metadata2[25:0] contains the
4546 * action record pointer. - metadata2[31:26] contains the table
4549 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \
4550 (UINT32_C(0x1) << 4)
4552 * The {metadata1, metadata0} fields contain the vtag
4554 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4555 * The metadata2 field contains the Tunnel ID
4556 * value, justified to LSB. i
4557 * - VXLAN = VNI[23:0] -> VXLAN Network ID
4558 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
4559 * - NVGRE = TNI[23:0] -> Tenant Network ID
4560 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
4561 * - IPv4 = 0 (not populated)
4562 * - IPv6 = Flow Label[19:0]
4563 * - PPPoE = sessionID[15:0]
4564 * - MPLs = Outer label[19:0]
4565 * - UPAR = Selected[31:0] with bit mask
4567 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
4568 (UINT32_C(0x2) << 4)
4570 * The {metadata1, metadata0} fields contain the vtag
4572 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
4573 * The metadata2 field contains the 32b metadata from the prepended
4574 * header (chdr_data).
4576 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
4577 (UINT32_C(0x3) << 4)
4579 * The {metadata1, metadata0} fields contain the vtag
4581 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
4582 * The metadata2 field contains the outer_l3_offset,
4583 * inner_l2_offset, inner_l3_offset, and inner_l4_size.
4584 * - metadata2[8:0] contains the outer_l3_offset.
4585 * - metadata2[17:9] contains the inner_l2_offset.
4586 * - metadata2[26:18] contains the inner_l3_offset.
4587 * - metadata2[31:27] contains the inner_l4_size.
4589 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
4590 (UINT32_C(0x4) << 4)
4591 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \
4592 RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
4594 * This field indicates the IP type for the inner-most IP header.
4595 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
4596 * This value is only valid if itype indicates a packet
4597 * with an IP header.
4599 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \
4602 * This indicates that the complete 1's complement checksum was
4603 * calculated for the packet in the affregation.
4605 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
4608 * This field indicates the status of IP and L4 CS calculations done
4609 * by the chip. The format of this field is indicated by the
4610 * cs_all_ok_mode bit.
4611 * CS status for TPA packets is always valid. This means that "all_ok"
4612 * status will always be set. The ok count status will be set
4613 * appropriately for the packet header, such that all existing CS
4616 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \
4618 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10
4620 * This value is the complete 1's complement checksum calculated from
4621 * the start of the outer L3 header to the end of the packet (not
4622 * including the ethernet crc). It is valid when the
4623 * 'complete_checksum_calc' flag is set. For TPA Start completions,
4624 * the complete checksum is calculated for the first packet in the
4627 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
4628 UINT32_C(0xffff0000)
4629 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4631 * This is data from the CFA block as indicated by the meta_format
4633 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
4634 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
4635 * act_rec_ptr[25:0]}
4636 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
4637 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
4638 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
4639 * When vee_cmpl_mode is set in VNIC context, this is the upper 32b
4640 * of the host address from the first BD used to place the packet.
4645 * This value is written by the NIC such that it will be different
4646 * for each pass through the completion queue. The even passes
4647 * will write 1. The odd passes will write 0.
4649 #define RX_TPA_START_V2_CMPL_V2 \
4651 #define RX_TPA_START_V2_CMPL_ERRORS_MASK \
4653 #define RX_TPA_START_V2_CMPL_ERRORS_SFT 1
4655 * This error indicates that there was some sort of problem with
4656 * the BDs for the packetThe packet should be treated as
4659 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \
4661 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4662 /* No buffer error */
4663 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
4664 (UINT32_C(0x0) << 1)
4667 * Packet did not fit into packet buffer provided. This means
4668 * that the TPA Start packet was too big to be placed into the
4669 * per-packet maximum number of physical buffers configured for
4670 * the VNIC, or that it was too big to be placed into the
4671 * per-aggregation maximum number of physical buffers configured
4672 * for the VNIC. This error only occurs when the VNIC is
4673 * configured for variable size receive buffers.
4675 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
4676 (UINT32_C(0x1) << 1)
4679 * BDs were not formatted correctly.
4681 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
4682 (UINT32_C(0x3) << 1)
4685 * There was a bad_format error on the previous operation
4687 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
4688 (UINT32_C(0x5) << 1)
4689 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \
4690 RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH
4692 * This is data from the CFA block as indicated by the meta_format
4696 /* When meta_format != 0, this value is the VLAN VID. */
4697 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
4698 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
4699 /* When meta_format != 0, this value is the VLAN DE. */
4700 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
4701 /* When meta_format != 0, this value is the VLAN PRI. */
4702 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
4703 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13
4705 * This field contains the outer_l3_offset, inner_l2_offset,
4706 * inner_l3_offset, and inner_l4_size.
4708 * hdr_offsets[8:0] contains the outer_l3_offset.
4709 * hdr_offsets[17:9] contains the inner_l2_offset.
4710 * hdr_offsets[26:18] contains the inner_l3_offset.
4711 * hdr_offsets[31:27] contains the inner_l4_size.
4713 uint32_t hdr_offsets;
4717 * This TPA completion structure is used on devices where the
4718 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4720 /* rx_tpa_end_cmpl (size:128b/16B) */
4721 struct rx_tpa_end_cmpl {
4722 uint16_t flags_type;
4724 * This field indicates the exact type of the completion.
4725 * By convention, the LSB identifies the length of the
4726 * record in 16B units. Even values indicate 16B
4727 * records. Odd values indicate 32B
4730 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
4731 #define RX_TPA_END_CMPL_TYPE_SFT 0
4733 * RX L2 TPA End Completion:
4734 * Completion at the end of a TPA operation.
4737 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
4738 #define RX_TPA_END_CMPL_TYPE_LAST \
4739 RX_TPA_END_CMPL_TYPE_RX_TPA_END
4740 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4741 #define RX_TPA_END_CMPL_FLAGS_SFT 6
4743 * When this bit is '1', it indicates a packet that has an
4744 * error of some type. Type of error is indicated in
4747 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
4748 /* This field indicates how the packet was placed in the buffer. */
4749 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
4750 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
4753 * TPA Packet was placed using jumbo algorithm. This means
4754 * that the first buffer will be filled with data before
4755 * moving to aggregation buffers. Each aggregation buffer
4756 * will be filled before moving to the next aggregation
4759 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
4760 (UINT32_C(0x1) << 7)
4762 * Header/Data Separation:
4763 * Packet was placed using Header/Data separation algorithm.
4764 * The separation location is indicated by the itype field.
4766 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
4767 (UINT32_C(0x2) << 7)
4770 * Packet will be placed using In-Order Completion/Jumbo where
4771 * the first packet of the aggregation is placed using Jumbo
4772 * Placement. Subsequent packets will be placed such that each
4773 * packet starts at the beginning of an aggregation buffer.
4775 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \
4776 (UINT32_C(0x4) << 7)
4779 * Packet will be placed using GRO/Jumbo where the first
4780 * packet is filled with data. Subsequent packets will be
4781 * placed such that any one packet does not span two
4782 * aggregation buffers unless it starts at the beginning of
4783 * an aggregation buffer.
4785 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
4786 (UINT32_C(0x5) << 7)
4788 * GRO/Header-Data Separation:
4789 * Packet will be placed using GRO/HDS where the header
4790 * is in the first packet.
4791 * Payload of each packet will be
4792 * placed such that any one packet does not span two
4793 * aggregation buffers unless it starts at the beginning of
4794 * an aggregation buffer.
4796 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
4797 (UINT32_C(0x6) << 7)
4799 * IOC/Header-Data Separation:
4800 * Packet will be placed using In-Order Completion/HDS where
4801 * the header is in the first packet buffer. Payload of each
4802 * packet will be placed such that each packet starts at the
4803 * beginning of an aggregation buffer.
4805 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \
4806 (UINT32_C(0x7) << 7)
4807 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
4808 RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS
4810 #define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
4812 * This bit is '1' if metadata has been added to the end of the
4813 * packet in host memory. Metadata starts at the first 32B boundary
4814 * after the end of the packet for regular and jumbo placement.
4815 * It starts at the first 32B boundary after the end of the header
4816 * for HDS placement. The length of the metadata is indicated in the
4819 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
4821 * This value indicates what the inner packet determined for the
4824 * Indicates that the packet was IP and TCP. This indicates
4825 * that the ip_cs field is valid and that the tcp_udp_cs
4826 * field is valid and contains the TCP checksum.
4827 * This also indicates that the payload_offset field is valid.
4829 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \
4831 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
4833 * This value is zero for TPA End completions.
4834 * There is no data in the buffer that corresponds to the opaque
4835 * value in this completion.
4839 * This is a copy of the opaque field from the RX BD this completion
4844 * This value is written by the NIC such that it will be different
4845 * for each pass through the completion queue. The even passes
4846 * will write 1. The odd passes will write 0.
4848 uint8_t agg_bufs_v1;
4850 * This value is written by the NIC such that it will be different
4851 * for each pass through the completion queue. The even passes
4852 * will write 1. The odd passes will write 0.
4854 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
4856 * This value is the number of aggregation buffers that follow this
4857 * entry in the completion ring that are a part of this aggregation
4859 * If the value is zero, then the packet is completely contained
4860 * in the buffer space provided in the aggregation start completion.
4862 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
4863 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
4864 /* This value is the number of segments in the TPA operation. */
4867 * This value indicates the offset in bytes from the beginning of the packet
4868 * where the inner payload starts. This value is valid for TCP, UDP,
4869 * FCoE, and RoCE packets.
4871 * A value of zero indicates an offset of 256 bytes.
4873 uint8_t payload_offset;
4875 /* unused2 is 1 b */
4876 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
4878 * This is the aggregation ID that the completion is associated
4879 * with. Use this number to correlate the TPA start completion
4880 * with the TPA end completion.
4882 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
4883 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
4885 * For non-GRO packets, this value is the
4886 * timestamp delta between earliest and latest timestamp values for
4887 * TPA packet. If packets were not time stamped, then delta will be
4890 * For GRO packets, this field is zero except for the following
4893 * Timestamp present indication. When '0', no Timestamp
4894 * option is in the packet. When '1', then a Timestamp
4895 * option is present in the packet.
4901 * Last 16 bytes of rx_tpa_end_cmpl.
4903 * This TPA completion structure is used on devices where the
4904 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
4906 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
4907 struct rx_tpa_end_cmpl_hi {
4908 uint32_t tpa_dup_acks;
4910 * This value is the number of duplicate ACKs that have been
4911 * received as part of the TPA operation.
4913 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
4914 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
4916 * This value is the valid when TPA completion is active. It
4917 * indicates the length of the longest segment of the TPA operation
4918 * for LRO mode and the length of the first segment in GRO mode.
4920 * This value may be used by GRO software to re-construct the original
4921 * packet stream from the TPA packet. This is the length of all
4922 * but the last segment for GRO. In LRO mode this value may be used
4923 * to indicate MSS size to the stack.
4925 uint16_t tpa_seg_len;
4926 /* unused4 is 16 b */
4930 * This value is written by the NIC such that it will be different
4931 * for each pass through the completion queue. The even passes
4932 * will write 1. The odd passes will write 0.
4934 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
4935 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4936 #define RX_TPA_END_CMPL_ERRORS_SFT 1
4938 * This error indicates that there was some sort of problem with
4939 * the BDs for the packet that was found after part of the
4940 * packet was already placed. The packet should be treated as
4943 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4944 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
4946 * This error occurs when there is a fatal HW problem in
4947 * the chip only. It indicates that there were not
4948 * BDs on chip but that there was adequate reservation.
4949 * provided by the TPA block.
4951 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
4952 (UINT32_C(0x2) << 1)
4954 * This error occurs when TPA block was not configured to
4955 * reserve adequate BDs for TPA operations on this RX
4956 * ring. All data for the TPA operation was not placed.
4958 * This error can also be generated when the number of
4959 * segments is not programmed correctly in TPA and the
4960 * 33 total aggregation buffers allowed for the TPA
4961 * operation has been exceeded.
4963 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
4964 (UINT32_C(0x4) << 1)
4965 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
4966 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
4967 /* unused5 is 16 b */
4970 * This is the opaque value that was completed for the TPA start
4971 * completion that corresponds to this TPA end completion.
4973 uint32_t start_opaque;
4977 * This TPA completion structure is used on devices where the
4978 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
4980 /* rx_tpa_v2_start_cmpl (size:128b/16B) */
4981 struct rx_tpa_v2_start_cmpl {
4982 uint16_t flags_type;
4984 * This field indicates the exact type of the completion.
4985 * By convention, the LSB identifies the length of the
4986 * record in 16B units. Even values indicate 16B
4987 * records. Odd values indicate 32B
4990 #define RX_TPA_V2_START_CMPL_TYPE_MASK \
4992 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
4994 * RX L2 TPA Start Completion:
4995 * Completion at the beginning of a TPA operation.
4998 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START \
5000 #define RX_TPA_V2_START_CMPL_TYPE_LAST \
5001 RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START
5002 #define RX_TPA_V2_START_CMPL_FLAGS_MASK \
5004 #define RX_TPA_V2_START_CMPL_FLAGS_SFT 6
5005 /* This bit will always be '0' for TPA start completions. */
5006 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR \
5008 /* This field indicates how the packet was placed in the buffer. */
5009 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK \
5011 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_SFT 7
5014 * TPA Packet was placed using jumbo algorithm. This means
5015 * that the first buffer will be filled with data before
5016 * moving to aggregation buffers. Each aggregation buffer
5017 * will be filled before moving to the next aggregation
5020 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO \
5021 (UINT32_C(0x1) << 7)
5023 * Header/Data Separation:
5024 * Packet was placed using Header/Data separation algorithm.
5025 * The separation location is indicated by the itype field.
5027 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS \
5028 (UINT32_C(0x2) << 7)
5031 * Packet will be placed using GRO/Jumbo where the first
5032 * packet is filled with data. Subsequent packets will be
5033 * placed such that any one packet does not span two
5034 * aggregation buffers unless it starts at the beginning of
5035 * an aggregation buffer.
5037 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5038 (UINT32_C(0x5) << 7)
5040 * GRO/Header-Data Separation:
5041 * Packet will be placed using GRO/HDS where the header
5042 * is in the first packet.
5043 * Payload of each packet will be
5044 * placed such that any one packet does not span two
5045 * aggregation buffers unless it starts at the beginning of
5046 * an aggregation buffer.
5048 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5049 (UINT32_C(0x6) << 7)
5050 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_LAST \
5051 RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
5052 /* This bit is '1' if the RSS field in this completion is valid. */
5053 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID \
5056 * For devices that support timestamps, when this bit is cleared the
5057 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5058 * field contains the 32b timestamp for
5059 * the packet from the MAC. When this bit is set, the
5060 * `inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset`
5061 * field contains the outer_l3_offset, inner_l2_offset,
5062 * inner_l3_offset, and inner_l4_size.
5064 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT \
5067 * This value indicates what the inner packet determined for the
5070 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK \
5072 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_SFT 12
5075 * Indicates that the packet was IP and TCP.
5077 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP \
5078 (UINT32_C(0x2) << 12)
5079 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_LAST \
5080 RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP
5082 * This value indicates the amount of packet data written to the
5083 * buffer the opaque field in this completion corresponds to.
5087 * This is a copy of the opaque field from the RX BD this completion
5092 * This value is written by the NIC such that it will be different
5093 * for each pass through the completion queue. The even passes
5094 * will write 1. The odd passes will write 0.
5098 * This value is written by the NIC such that it will be different
5099 * for each pass through the completion queue. The even passes
5100 * will write 1. The odd passes will write 0.
5102 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
5103 #define RX_TPA_V2_START_CMPL_LAST RX_TPA_V2_START_CMPL_V1
5105 * This is the RSS hash type for the packet. The value is packed
5106 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5108 * The value of tuple_extrac_op provides the information about
5109 * what fields the hash was computed on.
5110 * * 0: The RSS hash was computed over source IP address,
5111 * destination IP address, source port, and destination port of inner
5112 * IP and TCP or UDP headers. Note: For non-tunneled packets,
5113 * the packet headers are considered inner packet headers for the RSS
5114 * hash computation purpose.
5115 * * 1: The RSS hash was computed over source IP address and destination
5116 * IP address of inner IP header. Note: For non-tunneled packets,
5117 * the packet headers are considered inner packet headers for the RSS
5118 * hash computation purpose.
5119 * * 2: The RSS hash was computed over source IP address,
5120 * destination IP address, source port, and destination port of
5121 * IP and TCP or UDP headers of outer tunnel headers.
5122 * Note: For non-tunneled packets, this value is not applicable.
5123 * * 3: The RSS hash was computed over source IP address and
5124 * destination IP address of IP header of outer tunnel headers.
5125 * Note: For non-tunneled packets, this value is not applicable.
5127 * Note that 4-tuples values listed above are applicable
5128 * for layer 4 protocols supported and enabled for RSS in the hardware,
5129 * HWRM firmware, and drivers. For example, if RSS hash is supported and
5130 * enabled for TCP traffic only, then the values of tuple_extract_op
5131 * corresponding to 4-tuples are only valid for TCP traffic.
5133 uint8_t rss_hash_type;
5135 * This is the aggregation ID that the completion is associated
5136 * with. Use this number to correlate the TPA start completion
5137 * with the TPA end completion.
5141 * This value is the RSS hash value calculated for the packet
5142 * based on the mode bits and key value in the VNIC.
5148 * Last 16 bytes of rx_tpa_v2_start_cmpl.
5150 * This TPA completion structure is used on devices where the
5151 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5153 /* rx_tpa_v2_start_cmpl_hi (size:128b/16B) */
5154 struct rx_tpa_v2_start_cmpl_hi {
5157 * This indicates that the ip checksum was calculated for the
5158 * inner packet and that the sum passed for all segments
5159 * included in the aggregation.
5161 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC \
5164 * This indicates that the TCP, UDP or ICMP checksum was
5165 * calculated for the inner packet and that the sum passed
5166 * for all segments included in the aggregation.
5168 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC \
5171 * This indicates that the ip checksum was calculated for the
5172 * tunnel header and that the sum passed for all segments
5173 * included in the aggregation.
5175 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC \
5178 * This indicates that the UDP checksum was
5179 * calculated for the tunnel packet and that the sum passed for
5180 * all segments included in the aggregation.
5182 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC \
5184 /* This value indicates what format the metadata field is. */
5185 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK \
5187 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_SFT 4
5188 /* No metadata informtaion. Value is zero. */
5189 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE \
5190 (UINT32_C(0x0) << 4)
5192 * The metadata field contains the VLAN tag and TPID value.
5193 * - metadata[11:0] contains the vlan VID value.
5194 * - metadata[12] contains the vlan DE value.
5195 * - metadata[15:13] contains the vlan PRI value.
5196 * - metadata[31:16] contains the vlan TPID value.
5198 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN \
5199 (UINT32_C(0x1) << 4)
5201 * If ext_meta_format is equal to 1, the metadata field
5202 * contains the lower 16b of the tunnel ID value, justified
5204 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5205 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5206 * - NVGRE = TNI[23:0] -> Tenant Network ID
5207 * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
5208 * - IPV4 = 0 (not populated)
5209 * - IPV6 = Flow Label[19:0]
5210 * - PPPoE = sessionID[15:0]
5211 * - MPLs = Outer label[19:0]
5212 * - UPAR = Selected[31:0] with bit mask
5214 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
5215 (UINT32_C(0x2) << 4)
5217 * if ext_meta_format is equal to 1, metadata field contains
5218 * 16b metadata from the prepended header (chdr_data).
5220 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
5221 (UINT32_C(0x3) << 4)
5223 * If ext_meta_format is equal to 1, the metadata field contains
5224 * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
5226 * - metadata[8:0] contains the outer_l3_offset.
5227 * - metadata[17:9] contains the inner_l2_offset.
5228 * - metadata[26:18] contains the inner_l3_offset.
5229 * - metadata[31:27] contains the inner_l4_size.
5231 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
5232 (UINT32_C(0x4) << 4)
5233 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_LAST \
5234 RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
5236 * This field indicates the IP type for the inner-most IP header.
5237 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5239 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE \
5242 * This indicates that the complete 1's complement checksum was
5243 * calculated for the packet.
5245 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
5248 * The combination of this value and meta_format indicated what
5249 * format the metadata field is.
5251 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
5253 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
5255 * This value is the complete 1's complement checksum calculated from
5256 * the start of the outer L3 header to the end of the packet (not
5257 * including the ethernet crc). It is valid when the
5258 * 'complete_checksum_calc' flag is set. For TPA Start completions,
5259 * the complete checksum is calculated for the first packet in the
5262 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
5263 UINT32_C(0xffff0000)
5264 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
5266 * This is data from the CFA block as indicated by the meta_format
5270 /* When {ext_meta_format,meta_format}=1, this value is the VLAN VID. */
5271 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5272 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
5273 /* When {ext_meta_format,meta_format}=1, this value is the VLAN DE. */
5274 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
5275 /* When {ext_meta_format,meta_format}=1, this value is the VLAN PRI. */
5276 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5277 #define RX_TPA_V2_START_CMPL_METADATA_PRI_SFT 13
5278 /* When {ext_meta_format,meta_format}=1, this value is the VLAN TPID. */
5279 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5280 #define RX_TPA_V2_START_CMPL_METADATA_TPID_SFT 16
5283 * This value is written by the NIC such that it will be different
5284 * for each pass through the completion queue. The even passes
5285 * will write 1. The odd passes will write 0.
5287 #define RX_TPA_V2_START_CMPL_V2 \
5289 #define RX_TPA_V2_START_CMPL_ERRORS_MASK \
5291 #define RX_TPA_V2_START_CMPL_ERRORS_SFT 1
5293 * This error indicates that there was some sort of problem with
5294 * the BDs for the packet that was found after part of the
5295 * packet was already placed. The packet should be treated as
5298 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK \
5300 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5301 /* No buffer error */
5302 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5303 (UINT32_C(0x0) << 1)
5306 * BDs were not formatted correctly.
5308 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5309 (UINT32_C(0x3) << 1)
5312 * There was a bad_format error on the previous operation
5314 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5315 (UINT32_C(0x5) << 1)
5316 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
5317 RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5319 * This field identifies the CFA action rule that was used for this
5324 * For devices that support timestamps this field is overridden
5325 * with the timestamp value. When `flags.timestamp_fld_format` is
5326 * cleared, this field contains the 32b timestamp for the packet from the
5329 * When `flags.timestamp_fld_format` is set, this field contains the
5330 * outer_l3_offset, inner_l2_offset, inner_l3_offset, and inner_l4_size
5333 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
5335 * This is the offset from the beginning of the packet in bytes for
5336 * the outer L3 header. If there is no outer L3 header, then this
5339 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
5340 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
5342 * This is the offset from the beginning of the packet in bytes for
5343 * the inner most L2 header.
5345 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
5346 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_SFT 9
5348 * This is the offset from the beginning of the packet in bytes for
5349 * the inner most L3 header.
5351 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
5352 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_SFT 18
5354 * This is the size in bytes of the inner most L4 header.
5355 * This can be subtracted from the payload_offset to determine
5356 * the start of the inner most L4 header.
5358 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
5359 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_SFT 27
5363 * This TPA completion structure is used on devices where the
5364 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5366 /* rx_tpa_v2_end_cmpl (size:128b/16B) */
5367 struct rx_tpa_v2_end_cmpl {
5368 uint16_t flags_type;
5370 * This field indicates the exact type of the completion.
5371 * By convention, the LSB identifies the length of the
5372 * record in 16B units. Even values indicate 16B
5373 * records. Odd values indicate 32B
5376 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
5377 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
5379 * RX L2 TPA End Completion:
5380 * Completion at the end of a TPA operation.
5383 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
5384 #define RX_TPA_V2_END_CMPL_TYPE_LAST \
5385 RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END
5386 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5387 #define RX_TPA_V2_END_CMPL_FLAGS_SFT 6
5389 * When this bit is '1', it indicates a packet that has an
5390 * error of some type. Type of error is indicated in
5393 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
5394 /* This field indicates how the packet was placed in the buffer. */
5395 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5396 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_SFT 7
5399 * TPA Packet was placed using jumbo algorithm. This means
5400 * that the first buffer will be filled with data before
5401 * moving to aggregation buffers. Each aggregation buffer
5402 * will be filled before moving to the next aggregation
5405 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO \
5406 (UINT32_C(0x1) << 7)
5408 * Header/Data Separation:
5409 * Packet was placed using Header/Data separation algorithm.
5410 * The separation location is indicated by the itype field.
5412 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS \
5413 (UINT32_C(0x2) << 7)
5416 * Packet will be placed using GRO/Jumbo where the first
5417 * packet is filled with data. Subsequent packets will be
5418 * placed such that any one packet does not span two
5419 * aggregation buffers unless it starts at the beginning of
5420 * an aggregation buffer.
5422 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
5423 (UINT32_C(0x5) << 7)
5425 * GRO/Header-Data Separation:
5426 * Packet will be placed using GRO/HDS where the header
5427 * is in the first packet.
5428 * Payload of each packet will be
5429 * placed such that any one packet does not span two
5430 * aggregation buffers unless it starts at the beginning of
5431 * an aggregation buffer.
5433 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
5434 (UINT32_C(0x6) << 7)
5435 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_LAST \
5436 RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
5438 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
5439 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED_SFT 10
5441 * This value indicates what the inner packet determined for the
5444 * Indicates that the packet was IP and TCP. This indicates
5445 * that the ip_cs field is valid and that the tcp_udp_cs
5446 * field is valid and contains the TCP checksum.
5447 * This also indicates that the payload_offset field is valid.
5449 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5450 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_SFT 12
5452 * This value is zero for TPA End completions.
5453 * There is no data in the buffer that corresponds to the opaque
5454 * value in this completion.
5458 * This is a copy of the opaque field from the RX BD this completion
5464 * This value is written by the NIC such that it will be different
5465 * for each pass through the completion queue. The even passes
5466 * will write 1. The odd passes will write 0.
5468 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
5469 /* This value is the number of segments in the TPA operation. */
5472 * This is the aggregation ID that the completion is associated
5473 * with. Use this number to correlate the TPA start completion
5474 * with the TPA end completion.
5478 * For non-GRO packets, this value is the
5479 * timestamp delta between earliest and latest timestamp values for
5480 * TPA packet. If packets were not time stamped, then delta will be
5483 * For GRO packets, this field is zero except for the following
5486 * Timestamp present indication. When '0', no Timestamp
5487 * option is in the packet. When '1', then a Timestamp
5488 * option is present in the packet.
5494 * Last 16 bytes of rx_tpa_v2_end_cmpl.
5496 * This TPA completion structure is used on devices where the
5497 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5499 /* rx_tpa_v2_end_cmpl_hi (size:128b/16B) */
5500 struct rx_tpa_v2_end_cmpl_hi {
5502 * This value is the number of duplicate ACKs that have been
5503 * received as part of the TPA operation.
5505 uint16_t tpa_dup_acks;
5507 * This value is the number of duplicate ACKs that have been
5508 * received as part of the TPA operation.
5510 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
5511 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
5513 * This value indicated the offset in bytes from the beginning of
5514 * the packet where the inner payload starts. This value is valid
5515 * for TCP, UDP, FCoE and RoCE packets
5517 uint8_t payload_offset;
5519 * The value is the total number of aggregation buffers that were
5520 * used in the TPA operation. All TPA aggregation buffer completions
5521 * precede the TPA End completion. If the value is zero, then the
5522 * aggregation is completely contained in the buffer space provided
5523 * in the aggregation start completion.
5524 * Note that the field is simply provided as a cross check.
5526 uint8_t tpa_agg_bufs;
5528 * This value is the valid when TPA completion is active. It
5529 * indicates the length of the longest segment of the TPA operation
5530 * for LRO mode and the length of the first segment in GRO mode.
5532 * This value may be used by GRO software to re-construct the original
5533 * packet stream from the TPA packet. This is the length of all
5534 * but the last segment for GRO. In LRO mode this value may be used
5535 * to indicate MSS size to the stack.
5537 uint16_t tpa_seg_len;
5541 * This value is written by the NIC such that it will be different
5542 * for each pass through the completion queue. The even passes
5543 * will write 1. The odd passes will write 0.
5545 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
5546 #define RX_TPA_V2_END_CMPL_ERRORS_MASK \
5548 #define RX_TPA_V2_END_CMPL_ERRORS_SFT 1
5550 * This error indicates that there was some sort of problem with
5551 * the BDs for the packet that was found after part of the
5552 * packet was already placed. The packet should be treated as
5555 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK \
5557 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5558 /* No buffer error */
5559 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5560 (UINT32_C(0x0) << 1)
5562 * This error occurs when there is a fatal HW problem in
5563 * the chip only. It indicates that there were not
5564 * BDs on chip but that there was adequate reservation.
5565 * provided by the TPA block.
5567 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
5568 (UINT32_C(0x2) << 1)
5571 * BDs were not formatted correctly.
5573 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5574 (UINT32_C(0x3) << 1)
5576 * This error occurs when TPA block was not configured to
5577 * reserve adequate BDs for TPA operations on this RX
5578 * ring. All data for the TPA operation was not placed.
5580 * This error can also be generated when the number of
5581 * segments is not programmed correctly in TPA and the
5582 * 33 total aggregation buffers allowed for the TPA
5583 * operation has been exceeded.
5585 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
5586 (UINT32_C(0x4) << 1)
5589 * There was a bad_format error on the previous operation
5591 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5592 (UINT32_C(0x5) << 1)
5593 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
5594 RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5597 * This is the opaque value that was completed for the TPA start
5598 * completion that corresponds to this TPA end completion.
5600 uint32_t start_opaque;
5604 * This TPA completion structure is used on devices where the
5605 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
5607 /* rx_tpa_v2_abuf_cmpl (size:128b/16B) */
5608 struct rx_tpa_v2_abuf_cmpl {
5611 * This field indicates the exact type of the completion.
5612 * By convention, the LSB identifies the length of the
5613 * record in 16B units. Even values indicate 16B
5614 * records. Odd values indicate 32B
5617 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5618 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
5620 * RX TPA Aggregation Buffer completion :
5621 * Completion of an L2 aggregation buffer in support of
5622 * TPA packet completion. Length = 16B
5624 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
5625 #define RX_TPA_V2_ABUF_CMPL_TYPE_LAST \
5626 RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG
5628 * This is the length of the data for the packet stored in this
5629 * aggregation buffer identified by the opaque value. This does not
5630 * include the length of any
5631 * data placed in other aggregation BDs or in the packet or buffer
5632 * BDs. This length does not include any space added due to
5633 * hdr_offset register during HDS placement mode.
5637 * This is a copy of the opaque field from the RX BD this aggregation
5638 * buffer corresponds to.
5643 * This value is written by the NIC such that it will be different
5644 * for each pass through the completion queue. The even passes
5645 * will write 1. The odd passes will write 0.
5647 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
5649 * This is the aggregation ID that the completion is associated with. Use
5650 * this number to correlate the TPA agg completion with the TPA start
5651 * completion and the TPA end completion.
5657 /* rx_abuf_cmpl (size:128b/16B) */
5658 struct rx_abuf_cmpl {
5661 * This field indicates the exact type of the completion.
5662 * By convention, the LSB identifies the length of the
5663 * record in 16B units. Even values indicate 16B
5664 * records. Odd values indicate 32B
5667 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
5668 #define RX_ABUF_CMPL_TYPE_SFT 0
5670 * RX Aggregation Buffer completion :
5671 * Completion of an L2 aggregation buffer in support of
5672 * TPA, HDS, or Jumbo packet completion. Length = 16B
5674 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
5675 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
5677 * This is the length of the data for the packet stored in this
5678 * aggregation buffer identified by the opaque value. This does not
5679 * include the length of any
5680 * data placed in other aggregation BDs or in the packet or buffer
5681 * BDs. This length does not include any space added due to
5682 * hdr_offset register during HDS placement mode.
5686 * This is a copy of the opaque field from the RX BD this aggregation
5687 * buffer corresponds to.
5692 * This value is written by the NIC such that it will be different
5693 * for each pass through the completion queue. The even passes
5694 * will write 1. The odd passes will write 0.
5696 #define RX_ABUF_CMPL_V UINT32_C(0x1)
5697 /* unused3 is 32 b */
5701 /* VEE FLUSH Completion Record (16 bytes) */
5702 /* vee_flush (size:128b/16B) */
5704 uint32_t downstream_path_type;
5706 * This field indicates the exact type of the completion.
5707 * By convention, the LSB identifies the length of the
5708 * record in 16B units. Even values indicate 16B
5709 * records. Odd values indicate 32B
5712 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
5713 #define VEE_FLUSH_TYPE_SFT 0
5715 * VEE Flush Completion:
5716 * This completion is inserted manually by the Primate and processed
5717 * by the VEE hardware to ensure that all completions on a VEE
5718 * function have been processed by the VEE hardware before FLR
5719 * process is completed.
5721 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
5722 #define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH
5723 /* downstream_path is 1 b */
5724 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
5725 /* This completion is associated with VEE Transmit */
5726 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
5727 /* This completion is associated with VEE Receive */
5728 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
5729 #define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX
5731 * This is an opaque value that is passed through the completion
5732 * to the VEE handler SW and is used to indicate what VEE VQ or
5733 * function has completed FLR processing.
5738 * This value is written by the NIC such that it will be different
5739 * for each pass through the completion queue. The even passes will
5740 * write 1. The odd passes will write 0.
5742 #define VEE_FLUSH_V UINT32_C(0x1)
5743 /* unused3 is 32 b */
5747 /* eject_cmpl (size:128b/16B) */
5751 * This field indicates the exact type of the completion.
5752 * By convention, the LSB identifies the length of the
5753 * record in 16B units. Even values indicate 16B
5754 * records. Odd values indicate 32B
5757 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
5758 #define EJECT_CMPL_TYPE_SFT 0
5760 * Statistics Ejection Completion:
5761 * Completion of statistics data ejection buffer.
5764 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
5765 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
5766 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5767 #define EJECT_CMPL_FLAGS_SFT 6
5769 * When this bit is '1', it indicates a packet that has an
5770 * error of some type. Type of error is indicated in
5773 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
5775 * This is the length of the statistics data stored in this
5780 * This is a copy of the opaque field from the RX BD this ejection
5781 * buffer corresponds to.
5786 * This value is written by the NIC such that it will be different
5787 * for each pass through the completion queue. The even passes
5788 * will write 1. The odd passes will write 0.
5790 #define EJECT_CMPL_V UINT32_C(0x1)
5791 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
5792 #define EJECT_CMPL_ERRORS_SFT 1
5794 * This error indicates that there was some sort of problem with
5795 * the BDs for statistics ejection. The statistics ejection should
5796 * be treated as invalid
5798 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5799 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
5800 /* No buffer error */
5801 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
5802 (UINT32_C(0x0) << 1)
5805 * Statistics did not fit into aggregation buffer provided.
5807 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
5808 (UINT32_C(0x1) << 1)
5811 * BDs were not formatted correctly.
5813 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
5814 (UINT32_C(0x3) << 1)
5817 * There was a bad_format error on the previous operation
5819 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
5820 (UINT32_C(0x5) << 1)
5821 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
5822 EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
5823 /* reserved16 is 16 b */
5824 uint16_t reserved16;
5825 /* unused3 is 32 b */
5829 /* hwrm_cmpl (size:128b/16B) */
5833 * This field indicates the exact type of the completion.
5834 * By convention, the LSB identifies the length of the
5835 * record in 16B units. Even values indicate 16B
5836 * records. Odd values indicate 32B
5839 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
5840 #define HWRM_CMPL_TYPE_SFT 0
5842 * HWRM Command Completion:
5843 * Completion of an HWRM command.
5845 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
5846 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
5847 /* This is the sequence_id of the HWRM command that has completed. */
5848 uint16_t sequence_id;
5849 /* unused2 is 32 b */
5853 * This value is written by the NIC such that it will be different
5854 * for each pass through the completion queue. The even passes
5855 * will write 1. The odd passes will write 0.
5857 #define HWRM_CMPL_V UINT32_C(0x1)
5858 /* unused4 is 32 b */
5862 /* hwrm_fwd_req_cmpl (size:128b/16B) */
5863 struct hwrm_fwd_req_cmpl {
5865 * This field indicates the exact type of the completion.
5866 * By convention, the LSB identifies the length of the
5867 * record in 16B units. Even values indicate 16B
5868 * records. Odd values indicate 32B
5871 uint16_t req_len_type;
5873 * This field indicates the exact type of the completion.
5874 * By convention, the LSB identifies the length of the
5875 * record in 16B units. Even values indicate 16B
5876 * records. Odd values indicate 32B
5879 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
5880 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
5881 /* Forwarded HWRM Request */
5882 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
5883 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
5884 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
5885 /* Length of forwarded request in bytes. */
5886 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
5887 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
5889 * Source ID of this request.
5890 * Typically used in forwarding requests and responses.
5891 * 0x0 - 0xFFF8 - Used for function ids
5892 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5896 /* unused1 is 32 b */
5898 /* Address of forwarded request. */
5899 uint32_t req_buf_addr_v[2];
5901 * This value is written by the NIC such that it will be different
5902 * for each pass through the completion queue. The even passes
5903 * will write 1. The odd passes will write 0.
5905 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
5906 /* Address of forwarded request. */
5907 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5908 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
5911 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
5912 struct hwrm_fwd_resp_cmpl {
5915 * This field indicates the exact type of the completion.
5916 * By convention, the LSB identifies the length of the
5917 * record in 16B units. Even values indicate 16B
5918 * records. Odd values indicate 32B
5921 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
5922 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
5923 /* Forwarded HWRM Response */
5924 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
5925 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
5926 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
5928 * Source ID of this response.
5929 * Typically used in forwarding requests and responses.
5930 * 0x0 - 0xFFF8 - Used for function ids
5931 * 0xFFF8 - 0xFFFE - Reserved for internal processors
5935 /* Length of forwarded response in bytes. */
5937 /* unused2 is 16 b */
5939 /* Address of forwarded request. */
5940 uint32_t resp_buf_addr_v[2];
5942 * This value is written by the NIC such that it will be different
5943 * for each pass through the completion queue. The even passes
5944 * will write 1. The odd passes will write 0.
5946 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
5947 /* Address of forwarded request. */
5948 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
5949 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
5952 /* hwrm_async_event_cmpl (size:128b/16B) */
5953 struct hwrm_async_event_cmpl {
5956 * This field indicates the exact type of the completion.
5957 * By convention, the LSB identifies the length of the
5958 * record in 16B units. Even values indicate 16B
5959 * records. Odd values indicate 32B
5962 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
5963 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
5964 /* HWRM Asynchronous Event Information */
5965 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
5966 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
5967 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
5968 /* Identifiers of events. */
5970 /* Link status changed */
5971 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
5973 /* Link MTU changed */
5974 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
5976 /* Link speed changed */
5977 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
5979 /* DCB Configuration changed */
5980 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
5982 /* Port connection not allowed */
5983 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
5985 /* Link speed configuration was not allowed */
5986 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
5988 /* Link speed configuration change */
5989 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
5991 /* Port PHY configuration change */
5992 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
5994 /* Reset notification to clients */
5995 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
5997 /* Master function selection event */
5998 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
6000 /* Function driver unloaded */
6001 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
6003 /* Function driver loaded */
6004 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
6006 /* Function FLR related processing has completed */
6007 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
6009 /* PF driver unloaded */
6010 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
6012 /* PF driver loaded */
6013 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
6015 /* VF Function Level Reset (FLR) */
6016 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
6018 /* VF MAC Address Change */
6019 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
6021 /* PF-VF communication channel status change. */
6022 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
6024 /* VF Configuration Change */
6025 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
6027 /* LLFC/PFC Configuration Change */
6028 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
6030 /* Default VNIC Configuration Change */
6031 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
6034 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
6037 * A debug notification being posted to the driver. These
6038 * notifications are purely for diagnostic purpose and should not be
6039 * used for functional purpose. The driver is not supposed to act
6040 * on these messages except to log/record it.
6042 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
6045 * An EEM flow cached memory flush for all flows request event being
6046 * posted to the PF driver.
6048 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
6051 * An EEM flow cache memory flush completion event being posted to the
6052 * firmware by the PF driver. This is indication that host EEM flush
6053 * has completed by the PF.
6055 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
6058 * A tcp flag action change event being posted to the PF or trusted VF
6059 * driver by the firmware. The PF or trusted VF driver should query
6060 * the firmware for the new TCP flag action update after receiving
6063 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
6066 * An EEM flow active event being posted to the PF or trusted VF driver
6067 * by the firmware. The PF or trusted VF driver should update the
6068 * flow's aging timer after receiving this async event.
6070 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
6073 * A eem cfg change event being posted to the trusted VF driver by the
6074 * firmware if the parent PF EEM configuration changed.
6076 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
6080 * TFLIB unique default VNIC Configuration Change
6082 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
6086 * TFLIB unique link status changed
6088 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
6091 * An event signifying completion for HWRM_FW_STATE_QUIESCE
6092 * (completion, timeout, or error)
6094 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \
6097 * An event signifying a HWRM command is in progress and its
6098 * response will be deferred. This event is used on crypto controllers
6101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \
6104 * An event signifying that a PFC WatchDog configuration
6105 * has changed on any port / cos.
6107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
6110 * A trace log message. This contains firmware trace logs string
6111 * embedded in the asynchronous message. This is an experimental
6112 * event, not meant for production use at this time.
6114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
6117 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
6119 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
6120 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
6121 /* Event specific data */
6122 uint32_t event_data2;
6125 * This value is written by the NIC such that it will be different
6126 * for each pass through the completion queue. The even passes
6127 * will write 1. The odd passes will write 0.
6129 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
6131 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
6132 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
6133 /* 8-lsb timestamp from POR (100-msec resolution) */
6134 uint8_t timestamp_lo;
6135 /* 16-lsb timestamp from POR (100-msec resolution) */
6136 uint16_t timestamp_hi;
6137 /* Event specific data */
6138 uint32_t event_data1;
6141 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
6142 struct hwrm_async_event_cmpl_link_status_change {
6145 * This field indicates the exact type of the completion.
6146 * By convention, the LSB identifies the length of the
6147 * record in 16B units. Even values indicate 16B
6148 * records. Odd values indicate 32B
6151 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
6153 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
6154 /* HWRM Asynchronous Event Information */
6155 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6157 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
6158 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
6159 /* Identifiers of events. */
6161 /* Link status changed */
6162 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
6164 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
6165 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
6166 /* Event specific data */
6167 uint32_t event_data2;
6170 * This value is written by the NIC such that it will be different
6171 * for each pass through the completion queue. The even passes
6172 * will write 1. The odd passes will write 0.
6174 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
6177 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
6179 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
6180 /* 8-lsb timestamp from POR (100-msec resolution) */
6181 uint8_t timestamp_lo;
6182 /* 16-lsb timestamp from POR (100-msec resolution) */
6183 uint16_t timestamp_hi;
6184 /* Event specific data */
6185 uint32_t event_data1;
6186 /* Indicates link status change */
6187 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
6190 * If this bit set to 0, then it indicates that the link
6191 * was up and it went down.
6193 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
6196 * If this bit is set to 1, then it indicates that the link
6197 * was down and it went up.
6199 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
6201 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
6202 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
6203 /* Indicates the physical port this link status change occur */
6204 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
6206 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
6209 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6211 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6213 /* Indicates the physical function this event occurred on. */
6214 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK \
6216 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT \
6220 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
6221 struct hwrm_async_event_cmpl_link_mtu_change {
6224 * This field indicates the exact type of the completion.
6225 * By convention, the LSB identifies the length of the
6226 * record in 16B units. Even values indicate 16B
6227 * records. Odd values indicate 32B
6230 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
6232 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
6233 /* HWRM Asynchronous Event Information */
6234 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6236 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
6237 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
6238 /* Identifiers of events. */
6240 /* Link MTU changed */
6241 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
6243 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
6244 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
6245 /* Event specific data */
6246 uint32_t event_data2;
6249 * This value is written by the NIC such that it will be different
6250 * for each pass through the completion queue. The even passes
6251 * will write 1. The odd passes will write 0.
6253 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
6255 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
6257 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
6258 /* 8-lsb timestamp from POR (100-msec resolution) */
6259 uint8_t timestamp_lo;
6260 /* 16-lsb timestamp from POR (100-msec resolution) */
6261 uint16_t timestamp_hi;
6262 /* Event specific data */
6263 uint32_t event_data1;
6264 /* The new MTU of the link in bytes. */
6265 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
6267 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
6270 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
6271 struct hwrm_async_event_cmpl_link_speed_change {
6274 * This field indicates the exact type of the completion.
6275 * By convention, the LSB identifies the length of the
6276 * record in 16B units. Even values indicate 16B
6277 * records. Odd values indicate 32B
6280 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
6282 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
6283 /* HWRM Asynchronous Event Information */
6284 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6286 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
6287 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
6288 /* Identifiers of events. */
6290 /* Link speed changed */
6291 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
6293 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
6294 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
6295 /* Event specific data */
6296 uint32_t event_data2;
6299 * This value is written by the NIC such that it will be different
6300 * for each pass through the completion queue. The even passes
6301 * will write 1. The odd passes will write 0.
6303 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
6306 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
6308 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
6309 /* 8-lsb timestamp from POR (100-msec resolution) */
6310 uint8_t timestamp_lo;
6311 /* 16-lsb timestamp from POR (100-msec resolution) */
6312 uint16_t timestamp_hi;
6313 /* Event specific data */
6314 uint32_t event_data1;
6316 * When this bit is '1', the link was forced to the
6317 * force_link_speed value.
6319 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
6321 /* The new link speed in 100 Mbps units. */
6322 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
6324 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
6326 /* 100Mb link speed */
6327 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
6328 (UINT32_C(0x1) << 1)
6329 /* 1Gb link speed */
6330 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
6331 (UINT32_C(0xa) << 1)
6332 /* 2Gb link speed */
6333 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
6334 (UINT32_C(0x14) << 1)
6335 /* 25Gb link speed */
6336 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
6337 (UINT32_C(0x19) << 1)
6338 /* 10Gb link speed */
6339 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
6340 (UINT32_C(0x64) << 1)
6341 /* 20Mb link speed */
6342 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
6343 (UINT32_C(0xc8) << 1)
6344 /* 25Gb link speed */
6345 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
6346 (UINT32_C(0xfa) << 1)
6347 /* 40Gb link speed */
6348 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
6349 (UINT32_C(0x190) << 1)
6350 /* 50Gb link speed */
6351 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
6352 (UINT32_C(0x1f4) << 1)
6353 /* 100Gb link speed */
6354 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
6355 (UINT32_C(0x3e8) << 1)
6356 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
6357 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
6359 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6360 UINT32_C(0xffff0000)
6361 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6365 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
6366 struct hwrm_async_event_cmpl_dcb_config_change {
6369 * This field indicates the exact type of the completion.
6370 * By convention, the LSB identifies the length of the
6371 * record in 16B units. Even values indicate 16B
6372 * records. Odd values indicate 32B
6375 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
6377 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
6378 /* HWRM Asynchronous Event Information */
6379 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6381 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
6382 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6383 /* Identifiers of events. */
6385 /* DCB Configuration changed */
6386 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
6388 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
6389 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
6390 /* Event specific data */
6391 uint32_t event_data2;
6392 /* ETS configuration change */
6393 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
6395 /* PFC configuration change */
6396 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
6398 /* APP configuration change */
6399 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
6403 * This value is written by the NIC such that it will be different
6404 * for each pass through the completion queue. The even passes
6405 * will write 1. The odd passes will write 0.
6407 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
6410 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
6412 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
6413 /* 8-lsb timestamp from POR (100-msec resolution) */
6414 uint8_t timestamp_lo;
6415 /* 16-lsb timestamp from POR (100-msec resolution) */
6416 uint16_t timestamp_hi;
6417 /* Event specific data */
6418 uint32_t event_data1;
6420 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6422 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6424 /* Priority recommended for RoCE traffic */
6425 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
6427 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
6430 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
6431 (UINT32_C(0xff) << 16)
6432 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
6433 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
6434 /* Priority recommended for L2 traffic */
6435 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
6436 UINT32_C(0xff000000)
6437 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
6440 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
6441 (UINT32_C(0xff) << 24)
6442 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
6443 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
6446 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
6447 struct hwrm_async_event_cmpl_port_conn_not_allowed {
6450 * This field indicates the exact type of the completion.
6451 * By convention, the LSB identifies the length of the
6452 * record in 16B units. Even values indicate 16B
6453 * records. Odd values indicate 32B
6456 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
6458 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
6460 /* HWRM Asynchronous Event Information */
6461 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6463 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
6464 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6465 /* Identifiers of events. */
6467 /* Port connection not allowed */
6468 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
6470 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
6471 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
6472 /* Event specific data */
6473 uint32_t event_data2;
6476 * This value is written by the NIC such that it will be different
6477 * for each pass through the completion queue. The even passes
6478 * will write 1. The odd passes will write 0.
6480 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
6483 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
6485 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
6486 /* 8-lsb timestamp from POR (100-msec resolution) */
6487 uint8_t timestamp_lo;
6488 /* 16-lsb timestamp from POR (100-msec resolution) */
6489 uint16_t timestamp_hi;
6490 /* Event specific data */
6491 uint32_t event_data1;
6493 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6495 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6498 * This value indicates the current port level enforcement policy
6499 * for the optics module when there is an optical module mismatch
6500 * and port is not connected.
6502 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
6504 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
6506 /* No enforcement */
6507 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
6508 (UINT32_C(0x0) << 16)
6509 /* Disable Transmit side Laser. */
6510 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
6511 (UINT32_C(0x1) << 16)
6512 /* Raise a warning message. */
6513 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
6514 (UINT32_C(0x2) << 16)
6515 /* Power down the module. */
6516 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
6517 (UINT32_C(0x3) << 16)
6518 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
6519 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
6522 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
6523 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
6526 * This field indicates the exact type of the completion.
6527 * By convention, the LSB identifies the length of the
6528 * record in 16B units. Even values indicate 16B
6529 * records. Odd values indicate 32B
6532 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
6534 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
6536 /* HWRM Asynchronous Event Information */
6537 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
6539 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
6540 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
6541 /* Identifiers of events. */
6543 /* Link speed configuration was not allowed */
6544 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
6546 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
6547 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
6548 /* Event specific data */
6549 uint32_t event_data2;
6552 * This value is written by the NIC such that it will be different
6553 * for each pass through the completion queue. The even passes
6554 * will write 1. The odd passes will write 0.
6556 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
6559 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
6561 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
6562 /* 8-lsb timestamp from POR (100-msec resolution) */
6563 uint8_t timestamp_lo;
6564 /* 16-lsb timestamp from POR (100-msec resolution) */
6565 uint16_t timestamp_hi;
6566 /* Event specific data */
6567 uint32_t event_data1;
6569 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
6571 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
6575 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
6576 struct hwrm_async_event_cmpl_link_speed_cfg_change {
6579 * This field indicates the exact type of the completion.
6580 * By convention, the LSB identifies the length of the
6581 * record in 16B units. Even values indicate 16B
6582 * records. Odd values indicate 32B
6585 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
6587 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
6589 /* HWRM Asynchronous Event Information */
6590 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6592 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
6593 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6594 /* Identifiers of events. */
6596 /* Link speed configuration change */
6597 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
6599 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
6600 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
6601 /* Event specific data */
6602 uint32_t event_data2;
6605 * This value is written by the NIC such that it will be different
6606 * for each pass through the completion queue. The even passes
6607 * will write 1. The odd passes will write 0.
6609 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
6612 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
6614 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
6615 /* 8-lsb timestamp from POR (100-msec resolution) */
6616 uint8_t timestamp_lo;
6617 /* 16-lsb timestamp from POR (100-msec resolution) */
6618 uint16_t timestamp_hi;
6619 /* Event specific data */
6620 uint32_t event_data1;
6622 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6624 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6627 * If set to 1, it indicates that the supported link speeds
6628 * configuration on the port has changed.
6629 * If set to 0, then there is no change in supported link speeds
6632 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
6635 * If set to 1, it indicates that the link speed configuration
6636 * on the port has become illegal or invalid.
6637 * If set to 0, then the link speed configuration on the port is
6640 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
6644 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
6645 struct hwrm_async_event_cmpl_port_phy_cfg_change {
6648 * This field indicates the exact type of the completion.
6649 * By convention, the LSB identifies the length of the
6650 * record in 16B units. Even values indicate 16B
6651 * records. Odd values indicate 32B
6654 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
6656 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
6658 /* HWRM Asynchronous Event Information */
6659 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
6661 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
6662 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
6663 /* Identifiers of events. */
6665 /* Port PHY configuration change */
6666 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
6668 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
6669 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
6670 /* Event specific data */
6671 uint32_t event_data2;
6674 * This value is written by the NIC such that it will be different
6675 * for each pass through the completion queue. The even passes
6676 * will write 1. The odd passes will write 0.
6678 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
6681 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
6683 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
6684 /* 8-lsb timestamp from POR (100-msec resolution) */
6685 uint8_t timestamp_lo;
6686 /* 16-lsb timestamp from POR (100-msec resolution) */
6687 uint16_t timestamp_hi;
6688 /* Event specific data */
6689 uint32_t event_data1;
6691 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
6693 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
6696 * If set to 1, it indicates that the FEC
6697 * configuration on the port has changed.
6698 * If set to 0, then there is no change in FEC configuration.
6700 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
6703 * If set to 1, it indicates that the EEE configuration
6704 * on the port has changed.
6705 * If set to 0, then there is no change in EEE configuration
6708 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
6711 * If set to 1, it indicates that the pause configuration
6712 * on the PHY has changed.
6713 * If set to 0, then there is no change in the pause
6714 * configuration on the PHY.
6716 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
6720 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
6721 struct hwrm_async_event_cmpl_reset_notify {
6724 * This field indicates the exact type of the completion.
6725 * By convention, the LSB identifies the length of the
6726 * record in 16B units. Even values indicate 16B
6727 * records. Odd values indicate 32B
6730 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \
6732 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
6733 /* HWRM Asynchronous Event Information */
6734 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \
6736 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \
6737 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
6738 /* Identifiers of events. */
6740 /* Notify clients of imminent reset. */
6741 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \
6743 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \
6744 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
6745 /* Event specific data */
6746 uint32_t event_data2;
6749 * This value is written by the NIC such that it will be different
6750 * for each pass through the completion queue. The even passes
6751 * will write 1. The odd passes will write 0.
6753 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
6755 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
6756 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
6758 * 8-lsb timestamp (100-msec resolution)
6759 * The Minimum time required for the Firmware readiness after sending this
6760 * notification to the driver instances.
6762 uint8_t timestamp_lo;
6764 * 16-lsb timestamp (100-msec resolution)
6765 * The Maximum Firmware Reset bail out value in the order of 100
6766 * milli seconds. The driver instances will use this value to re-initiate the
6767 * registration process again if the core firmware didn’t set the ready
6770 uint16_t timestamp_hi;
6771 /* Event specific data */
6772 uint32_t event_data1;
6773 /* Indicates driver action requested */
6774 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \
6776 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \
6779 * If set to 1, it indicates that the l2 client should
6780 * stop sending in band traffic to Nitro.
6781 * if set to 0, there is no change in L2 client behavior.
6783 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \
6786 * If set to 1, it indicates that the L2 client should
6787 * bring down the interface.
6788 * If set to 0, then there is no change in L2 client behavior.
6790 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \
6792 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \
6793 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
6794 /* Indicates reason for reset. */
6795 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \
6797 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \
6799 /* A management client has requested reset. */
6800 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \
6801 (UINT32_C(0x1) << 8)
6802 /* A fatal firmware exception has occurred. */
6803 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \
6804 (UINT32_C(0x2) << 8)
6805 /* A non-fatal firmware exception has occurred. */
6806 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \
6807 (UINT32_C(0x3) << 8)
6808 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \
6809 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
6811 * Minimum time before driver should attempt access - units 100ms ticks.
6814 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \
6815 UINT32_C(0xffff0000)
6816 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \
6820 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
6821 struct hwrm_async_event_cmpl_error_recovery {
6824 * This field indicates the exact type of the completion.
6825 * By convention, the LSB identifies the length of the
6826 * record in 16B units. Even values indicate 16B
6827 * records. Odd values indicate 32B
6830 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
6832 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
6833 /* HWRM Asynchronous Event Information */
6834 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
6836 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
6837 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
6838 /* Identifiers of events. */
6841 * This async notification message can be used for selecting or
6842 * deselecting master function for error recovery,
6843 * and to communicate to all the functions whether error recovery
6844 * was enabled/disabled.
6846 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
6848 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
6849 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
6850 /* Event specific data */
6851 uint32_t event_data2;
6854 * This value is written by the NIC such that it will be different
6855 * for each pass through the completion queue. The even passes
6856 * will write 1. The odd passes will write 0.
6858 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
6860 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
6861 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
6862 /* 8-lsb timestamp (100-msec resolution) */
6863 uint8_t timestamp_lo;
6864 /* 16-lsb timestamp (100-msec resolution) */
6865 uint16_t timestamp_hi;
6866 /* Event specific data */
6867 uint32_t event_data1;
6868 /* Indicates driver action requested */
6869 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
6871 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
6874 * If set to 1, this function is selected as Master function.
6875 * This function has responsibility to do 'chip reset' when it
6876 * detects a fatal error. If set to 0, master function functionality
6877 * is disabled on this function.
6879 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
6882 * If set to 1, error recovery is enabled.
6883 * If set to 0, error recovery is disabled.
6885 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
6889 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
6890 struct hwrm_async_event_cmpl_func_drvr_unload {
6893 * This field indicates the exact type of the completion.
6894 * By convention, the LSB identifies the length of the
6895 * record in 16B units. Even values indicate 16B
6896 * records. Odd values indicate 32B
6899 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
6901 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
6902 /* HWRM Asynchronous Event Information */
6903 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
6905 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
6906 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
6907 /* Identifiers of events. */
6909 /* Function driver unloaded */
6910 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
6912 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
6913 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
6914 /* Event specific data */
6915 uint32_t event_data2;
6918 * This value is written by the NIC such that it will be different
6919 * for each pass through the completion queue. The even passes
6920 * will write 1. The odd passes will write 0.
6922 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
6924 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
6926 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
6927 /* 8-lsb timestamp from POR (100-msec resolution) */
6928 uint8_t timestamp_lo;
6929 /* 16-lsb timestamp from POR (100-msec resolution) */
6930 uint16_t timestamp_hi;
6931 /* Event specific data */
6932 uint32_t event_data1;
6934 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
6936 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
6940 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
6941 struct hwrm_async_event_cmpl_func_drvr_load {
6944 * This field indicates the exact type of the completion.
6945 * By convention, the LSB identifies the length of the
6946 * record in 16B units. Even values indicate 16B
6947 * records. Odd values indicate 32B
6950 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
6952 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
6953 /* HWRM Asynchronous Event Information */
6954 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
6956 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
6957 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
6958 /* Identifiers of events. */
6960 /* Function driver loaded */
6961 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
6963 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
6964 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
6965 /* Event specific data */
6966 uint32_t event_data2;
6969 * This value is written by the NIC such that it will be different
6970 * for each pass through the completion queue. The even passes
6971 * will write 1. The odd passes will write 0.
6973 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
6975 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
6976 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
6977 /* 8-lsb timestamp from POR (100-msec resolution) */
6978 uint8_t timestamp_lo;
6979 /* 16-lsb timestamp from POR (100-msec resolution) */
6980 uint16_t timestamp_hi;
6981 /* Event specific data */
6982 uint32_t event_data1;
6984 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
6986 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
6989 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
6990 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
6993 * This field indicates the exact type of the completion.
6994 * By convention, the LSB identifies the length of the
6995 * record in 16B units. Even values indicate 16B
6996 * records. Odd values indicate 32B
6999 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
7001 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
7003 /* HWRM Asynchronous Event Information */
7004 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
7006 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
7007 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
7008 /* Identifiers of events. */
7010 /* Function FLR related processing has completed */
7011 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
7013 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
7014 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
7015 /* Event specific data */
7016 uint32_t event_data2;
7019 * This value is written by the NIC such that it will be different
7020 * for each pass through the completion queue. The even passes
7021 * will write 1. The odd passes will write 0.
7023 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
7026 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
7028 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
7029 /* 8-lsb timestamp from POR (100-msec resolution) */
7030 uint8_t timestamp_lo;
7031 /* 16-lsb timestamp from POR (100-msec resolution) */
7032 uint16_t timestamp_hi;
7033 /* Event specific data */
7034 uint32_t event_data1;
7036 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
7038 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
7042 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
7043 struct hwrm_async_event_cmpl_pf_drvr_unload {
7046 * This field indicates the exact type of the completion.
7047 * By convention, the LSB identifies the length of the
7048 * record in 16B units. Even values indicate 16B
7049 * records. Odd values indicate 32B
7052 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
7054 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
7055 /* HWRM Asynchronous Event Information */
7056 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
7058 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
7059 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
7060 /* Identifiers of events. */
7062 /* PF driver unloaded */
7063 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
7065 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
7066 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
7067 /* Event specific data */
7068 uint32_t event_data2;
7071 * This value is written by the NIC such that it will be different
7072 * for each pass through the completion queue. The even passes
7073 * will write 1. The odd passes will write 0.
7075 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
7077 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
7078 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
7079 /* 8-lsb timestamp from POR (100-msec resolution) */
7080 uint8_t timestamp_lo;
7081 /* 16-lsb timestamp from POR (100-msec resolution) */
7082 uint16_t timestamp_hi;
7083 /* Event specific data */
7084 uint32_t event_data1;
7086 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
7088 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
7089 /* Indicates the physical port this pf belongs to */
7090 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
7092 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
7095 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
7096 struct hwrm_async_event_cmpl_pf_drvr_load {
7099 * This field indicates the exact type of the completion.
7100 * By convention, the LSB identifies the length of the
7101 * record in 16B units. Even values indicate 16B
7102 * records. Odd values indicate 32B
7105 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
7107 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
7108 /* HWRM Asynchronous Event Information */
7109 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
7111 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
7112 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
7113 /* Identifiers of events. */
7115 /* PF driver loaded */
7116 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
7118 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
7119 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
7120 /* Event specific data */
7121 uint32_t event_data2;
7124 * This value is written by the NIC such that it will be different
7125 * for each pass through the completion queue. The even passes
7126 * will write 1. The odd passes will write 0.
7128 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
7130 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
7131 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
7132 /* 8-lsb timestamp from POR (100-msec resolution) */
7133 uint8_t timestamp_lo;
7134 /* 16-lsb timestamp from POR (100-msec resolution) */
7135 uint16_t timestamp_hi;
7136 /* Event specific data */
7137 uint32_t event_data1;
7139 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
7141 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
7142 /* Indicates the physical port this pf belongs to */
7143 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
7145 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
7148 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
7149 struct hwrm_async_event_cmpl_vf_flr {
7152 * This field indicates the exact type of the completion.
7153 * By convention, the LSB identifies the length of the
7154 * record in 16B units. Even values indicate 16B
7155 * records. Odd values indicate 32B
7158 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
7160 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
7161 /* HWRM Asynchronous Event Information */
7162 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
7164 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
7165 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
7166 /* Identifiers of events. */
7168 /* VF Function Level Reset (FLR) */
7169 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
7170 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
7171 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
7172 /* Event specific data */
7173 uint32_t event_data2;
7176 * This value is written by the NIC such that it will be different
7177 * for each pass through the completion queue. The even passes
7178 * will write 1. The odd passes will write 0.
7180 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
7182 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
7183 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
7184 /* 8-lsb timestamp from POR (100-msec resolution) */
7185 uint8_t timestamp_lo;
7186 /* 16-lsb timestamp from POR (100-msec resolution) */
7187 uint16_t timestamp_hi;
7188 /* Event specific data */
7189 uint32_t event_data1;
7191 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
7193 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
7194 /* Indicates the physical function this event occurred on. */
7195 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK \
7197 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_SFT 16
7200 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
7201 struct hwrm_async_event_cmpl_vf_mac_addr_change {
7204 * This field indicates the exact type of the completion.
7205 * By convention, the LSB identifies the length of the
7206 * record in 16B units. Even values indicate 16B
7207 * records. Odd values indicate 32B
7210 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
7212 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
7213 /* HWRM Asynchronous Event Information */
7214 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7216 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
7217 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
7218 /* Identifiers of events. */
7220 /* VF MAC Address Change */
7221 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
7223 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
7224 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
7225 /* Event specific data */
7226 uint32_t event_data2;
7229 * This value is written by the NIC such that it will be different
7230 * for each pass through the completion queue. The even passes
7231 * will write 1. The odd passes will write 0.
7233 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
7236 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
7238 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
7239 /* 8-lsb timestamp from POR (100-msec resolution) */
7240 uint8_t timestamp_lo;
7241 /* 16-lsb timestamp from POR (100-msec resolution) */
7242 uint16_t timestamp_hi;
7243 /* Event specific data */
7244 uint32_t event_data1;
7246 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
7248 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
7252 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
7253 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
7256 * This field indicates the exact type of the completion.
7257 * By convention, the LSB identifies the length of the
7258 * record in 16B units. Even values indicate 16B
7259 * records. Odd values indicate 32B
7262 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
7264 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
7266 /* HWRM Asynchronous Event Information */
7267 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7269 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
7270 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
7271 /* Identifiers of events. */
7273 /* PF-VF communication channel status change. */
7274 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
7276 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
7277 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
7278 /* Event specific data */
7279 uint32_t event_data2;
7282 * This value is written by the NIC such that it will be different
7283 * for each pass through the completion queue. The even passes
7284 * will write 1. The odd passes will write 0.
7286 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
7289 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
7291 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
7292 /* 8-lsb timestamp from POR (100-msec resolution) */
7293 uint8_t timestamp_lo;
7294 /* 16-lsb timestamp from POR (100-msec resolution) */
7295 uint16_t timestamp_hi;
7296 /* Event specific data */
7297 uint32_t event_data1;
7299 * If this bit is set to 1, then it indicates that the PF-VF
7300 * communication was lost and it is established.
7301 * If this bit set to 0, then it indicates that the PF-VF
7302 * communication was established and it is lost.
7304 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
7308 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
7309 struct hwrm_async_event_cmpl_vf_cfg_change {
7312 * This field indicates the exact type of the completion.
7313 * By convention, the LSB identifies the length of the
7314 * record in 16B units. Even values indicate 16B
7315 * records. Odd values indicate 32B
7318 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
7320 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
7321 /* HWRM Asynchronous Event Information */
7322 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7324 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
7325 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7326 /* Identifiers of events. */
7328 /* VF Configuration Change */
7329 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
7331 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
7332 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
7333 /* Event specific data */
7334 uint32_t event_data2;
7337 * This value is written by the NIC such that it will be different
7338 * for each pass through the completion queue. The even passes
7339 * will write 1. The odd passes will write 0.
7341 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
7343 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7344 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
7345 /* 8-lsb timestamp from POR (100-msec resolution) */
7346 uint8_t timestamp_lo;
7347 /* 16-lsb timestamp from POR (100-msec resolution) */
7348 uint16_t timestamp_hi;
7350 * Each flag provided in this field indicates a specific VF
7351 * configuration change. At least one of these flags shall be set to 1
7352 * when an asynchronous event completion of this type is provided
7355 uint32_t event_data1;
7357 * If this bit is set to 1, then the value of MTU
7358 * was changed on this VF.
7359 * If set to 0, then this bit should be ignored.
7361 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
7364 * If this bit is set to 1, then the value of MRU
7365 * was changed on this VF.
7366 * If set to 0, then this bit should be ignored.
7368 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
7371 * If this bit is set to 1, then the value of default MAC
7372 * address was changed on this VF.
7373 * If set to 0, then this bit should be ignored.
7375 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
7378 * If this bit is set to 1, then the value of default VLAN
7379 * was changed on this VF.
7380 * If set to 0, then this bit should be ignored.
7382 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
7385 * If this bit is set to 1, then the value of trusted VF enable
7386 * was changed on this VF.
7387 * If set to 0, then this bit should be ignored.
7389 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \
7393 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
7394 struct hwrm_async_event_cmpl_llfc_pfc_change {
7397 * This field indicates the exact type of the completion.
7398 * By convention, the LSB identifies the length of the
7399 * record in 16B units. Even values indicate 16B
7400 * records. Odd values indicate 32B
7403 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
7405 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
7406 /* HWRM Asynchronous Event Information */
7407 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7409 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
7410 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7411 /* unused1 is 10 b */
7412 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
7414 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
7415 /* Identifiers of events. */
7417 /* LLFC/PFC Configuration Change */
7418 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
7420 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
7421 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
7422 /* Event specific data */
7423 uint32_t event_data2;
7426 * This value is written by the NIC such that it will be different
7427 * for each pass through the completion queue. The even passes
7428 * will write 1. The odd passes will write 0.
7430 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
7432 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
7434 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
7435 /* 8-lsb timestamp from POR (100-msec resolution) */
7436 uint8_t timestamp_lo;
7437 /* 16-lsb timestamp from POR (100-msec resolution) */
7438 uint16_t timestamp_hi;
7439 /* Event specific data */
7440 uint32_t event_data1;
7441 /* Indicates llfc pfc status change */
7442 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
7444 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
7447 * If this field set to 1, then it indicates that llfc is
7450 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
7453 * If this field is set to 2, then it indicates that pfc
7456 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
7458 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
7459 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
7460 /* Indicates the physical port this llfc pfc change occur */
7461 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
7463 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
7466 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
7468 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
7472 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
7473 struct hwrm_async_event_cmpl_default_vnic_change {
7476 * This field indicates the exact type of the completion.
7477 * By convention, the LSB identifies the length of the
7478 * record in 16B units. Even values indicate 16B
7479 * records. Odd values indicate 32B
7482 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK \
7484 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT \
7486 /* HWRM Asynchronous Event Information */
7487 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7489 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST \
7490 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
7491 /* unused1 is 10 b */
7492 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK \
7494 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT \
7496 /* Identifiers of events. */
7498 /* Notification of a default vnic allocation or free */
7499 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION \
7501 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST \
7502 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
7503 /* Event specific data */
7504 uint32_t event_data2;
7507 * This value is written by the NIC such that it will be different
7508 * for each pass through the completion queue. The even passes
7509 * will write 1. The odd passes will write 0.
7511 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V \
7514 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK \
7516 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
7517 /* 8-lsb timestamp from POR (100-msec resolution) */
7518 uint8_t timestamp_lo;
7519 /* 16-lsb timestamp from POR (100-msec resolution) */
7520 uint16_t timestamp_hi;
7521 /* Event specific data */
7522 uint32_t event_data1;
7523 /* Indicates default vnic configuration change */
7524 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK \
7526 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT \
7529 * If this field is set to 1, then it indicates that
7530 * a default VNIC has been allocate.
7532 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC \
7535 * If this field is set to 2, then it indicates that
7536 * a default VNIC has been freed.
7538 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE \
7540 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST \
7541 HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
7542 /* Indicates the physical function this event occurred on. */
7543 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK \
7545 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT \
7547 /* Indicates the virtual function this event occurred on */
7548 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK \
7550 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT \
7554 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
7555 struct hwrm_async_event_cmpl_hw_flow_aged {
7558 * This field indicates the exact type of the completion.
7559 * By convention, the LSB identifies the length of the
7560 * record in 16B units. Even values indicate 16B
7561 * records. Odd values indicate 32B
7564 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
7566 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
7567 /* HWRM Asynchronous Event Information */
7568 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
7570 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
7571 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
7572 /* Identifiers of events. */
7574 /* Notification of a hw flow aged */
7575 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
7577 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
7578 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
7579 /* Event specific data */
7580 uint32_t event_data2;
7583 * This value is written by the NIC such that it will be different
7584 * for each pass through the completion queue. The even passes
7585 * will write 1. The odd passes will write 0.
7587 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
7589 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
7590 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
7591 /* 8-lsb timestamp from POR (100-msec resolution) */
7592 uint8_t timestamp_lo;
7593 /* 16-lsb timestamp from POR (100-msec resolution) */
7594 uint16_t timestamp_hi;
7595 /* Event specific data */
7596 uint32_t event_data1;
7597 /* Indicates flow ID this event occurred on. */
7598 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
7599 UINT32_C(0x7fffffff)
7600 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
7602 /* Indicates flow direction this event occurred on. */
7603 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
7604 UINT32_C(0x80000000)
7606 * If this bit set to 0, then it indicates that the aged
7607 * event was rx flow.
7609 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
7610 (UINT32_C(0x0) << 31)
7612 * If this bit is set to 1, then it indicates that the aged
7613 * event was tx flow.
7615 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
7616 (UINT32_C(0x1) << 31)
7617 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
7618 HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
7621 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
7622 struct hwrm_async_event_cmpl_eem_cache_flush_req {
7625 * This field indicates the exact type of the completion.
7626 * By convention, the LSB identifies the length of the
7627 * record in 16B units. Even values indicate 16B
7628 * records. Odd values indicate 32B
7631 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
7633 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
7635 /* HWRM Asynchronous Event Information */
7636 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
7638 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
7639 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
7640 /* Identifiers of events. */
7642 /* Notification of a eem_cache_flush request */
7643 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
7645 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
7646 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
7647 /* Event specific data */
7648 uint32_t event_data2;
7651 * This value is written by the NIC such that it will be different
7652 * for each pass through the completion queue. The even passes
7653 * will write 1. The odd passes will write 0.
7655 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
7658 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
7660 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
7661 /* 8-lsb timestamp from POR (100-msec resolution) */
7662 uint8_t timestamp_lo;
7663 /* 16-lsb timestamp from POR (100-msec resolution) */
7664 uint16_t timestamp_hi;
7665 /* Event specific data */
7666 uint32_t event_data1;
7669 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
7670 struct hwrm_async_event_cmpl_eem_cache_flush_done {
7673 * This field indicates the exact type of the completion.
7674 * By convention, the LSB identifies the length of the
7675 * record in 16B units. Even values indicate 16B
7676 * records. Odd values indicate 32B
7679 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
7681 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
7683 /* HWRM Asynchronous Event Information */
7684 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
7686 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
7687 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
7688 /* Identifiers of events. */
7691 * Notification of a host eem_cache_flush has completed. This event
7692 * is generated by the host driver.
7694 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
7696 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
7697 HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
7698 /* Event specific data */
7699 uint32_t event_data2;
7702 * This value is written by the NIC such that it will be different
7703 * for each pass through the completion queue. The even passes
7704 * will write 1. The odd passes will write 0.
7706 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
7709 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
7711 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
7712 /* 8-lsb timestamp from POR (100-msec resolution) */
7713 uint8_t timestamp_lo;
7714 /* 16-lsb timestamp from POR (100-msec resolution) */
7715 uint16_t timestamp_hi;
7716 /* Event specific data */
7717 uint32_t event_data1;
7718 /* Indicates function ID that this event occurred on. */
7719 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
7721 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
7725 /* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
7726 struct hwrm_async_event_cmpl_tcp_flag_action_change {
7729 * This field indicates the exact type of the completion.
7730 * By convention, the LSB identifies the length of the
7731 * record in 16B units. Even values indicate 16B
7732 * records. Odd values indicate 32B
7735 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
7737 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
7739 /* HWRM Asynchronous Event Information */
7740 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7742 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
7743 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
7744 /* Identifiers of events. */
7746 /* Notification of tcp flag action change */
7747 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
7749 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
7750 HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
7751 /* Event specific data */
7752 uint32_t event_data2;
7755 * This value is written by the NIC such that it will be different
7756 * for each pass through the completion queue. The even passes
7757 * will write 1. The odd passes will write 0.
7759 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
7762 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
7764 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
7765 /* 8-lsb timestamp from POR (100-msec resolution) */
7766 uint8_t timestamp_lo;
7767 /* 16-lsb timestamp from POR (100-msec resolution) */
7768 uint16_t timestamp_hi;
7769 /* Event specific data */
7770 uint32_t event_data1;
7773 /* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
7774 struct hwrm_async_event_cmpl_eem_flow_active {
7777 * This field indicates the exact type of the completion.
7778 * By convention, the LSB identifies the length of the
7779 * record in 16B units. Even values indicate 16B
7780 * records. Odd values indicate 32B
7783 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
7785 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
7786 /* HWRM Asynchronous Event Information */
7787 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
7789 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
7790 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
7791 /* Identifiers of events. */
7793 /* Notification of an active eem flow */
7794 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
7796 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
7797 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
7798 /* Event specific data */
7799 uint32_t event_data2;
7800 /* Indicates the 2nd global id this event occurred on. */
7801 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
7802 UINT32_C(0x3fffffff)
7803 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
7806 * Indicates flow direction of the flow identified by
7809 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
7810 UINT32_C(0x40000000)
7811 /* If this bit is set to 0, then it indicates that this rx flow. */
7812 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
7813 (UINT32_C(0x0) << 30)
7814 /* If this bit is set to 1, then it indicates that this tx flow. */
7815 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
7816 (UINT32_C(0x1) << 30)
7817 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
7818 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
7821 * This value is written by the NIC such that it will be different
7822 * for each pass through the completion queue. The even passes
7823 * will write 1. The odd passes will write 0.
7825 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
7827 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
7829 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
7830 /* 8-lsb timestamp from POR (100-msec resolution) */
7831 uint8_t timestamp_lo;
7832 /* 16-lsb timestamp from POR (100-msec resolution) */
7833 uint16_t timestamp_hi;
7834 /* Event specific data */
7835 uint32_t event_data1;
7836 /* Indicates the 1st global id this event occurred on. */
7837 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
7838 UINT32_C(0x3fffffff)
7839 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
7842 * Indicates flow direction of the flow identified by the
7845 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
7846 UINT32_C(0x40000000)
7847 /* If this bit is set to 0, then it indicates that this is rx flow. */
7848 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
7849 (UINT32_C(0x0) << 30)
7850 /* If this bit is set to 1, then it indicates that this is tx flow. */
7851 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
7852 (UINT32_C(0x1) << 30)
7853 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
7854 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
7856 * Indicates EEM flow aging mode this event occurred on. If
7857 * this bit is set to 0, the event_data1 is the EEM global
7858 * ID. If this bit is set to 1, the event_data1 is the number
7859 * of global ID in the context memory.
7861 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
7862 UINT32_C(0x80000000)
7863 /* EEM flow aging mode 0. */
7864 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
7865 (UINT32_C(0x0) << 31)
7866 /* EEM flow aging mode 1. */
7867 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
7868 (UINT32_C(0x1) << 31)
7869 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
7870 HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
7873 /* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
7874 struct hwrm_async_event_cmpl_eem_cfg_change {
7877 * This field indicates the exact type of the completion.
7878 * By convention, the LSB identifies the length of the
7879 * record in 16B units. Even values indicate 16B
7880 * records. Odd values indicate 32B
7883 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
7885 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
7886 /* HWRM Asynchronous Event Information */
7887 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
7889 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
7890 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
7891 /* Identifiers of events. */
7893 /* Notification of EEM configuration change */
7894 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
7896 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
7897 HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
7898 /* Event specific data */
7899 uint32_t event_data2;
7902 * This value is written by the NIC such that it will be different
7903 * for each pass through the completion queue. The even passes
7904 * will write 1. The odd passes will write 0.
7906 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
7908 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
7909 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
7910 /* 8-lsb timestamp from POR (100-msec resolution) */
7911 uint8_t timestamp_lo;
7912 /* 16-lsb timestamp from POR (100-msec resolution) */
7913 uint16_t timestamp_hi;
7914 /* Event specific data */
7915 uint32_t event_data1;
7917 * Value of 1 to indicate EEM TX configuration is enabled. Value of
7918 * 0 to indicate the EEM TX configuration is disabled.
7920 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
7923 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
7924 * to indicate the EEM RX configuration is disabled.
7926 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
7930 /* hwrm_async_event_cmpl_quiesce_done (size:128b/16B) */
7931 struct hwrm_async_event_cmpl_quiesce_done {
7934 * This field indicates the exact type of the completion.
7935 * By convention, the LSB identifies the length of the
7936 * record in 16B units. Even values indicate 16B
7937 * records. Odd values indicate 32B
7940 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK \
7942 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
7943 /* HWRM Asynchronous Event Information */
7944 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT \
7946 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_LAST \
7947 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT
7948 /* Identifiers of events. */
7950 /* An event signifying completion of HWRM_FW_STATE_QUIESCE */
7951 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE \
7953 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_LAST \
7954 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE
7955 /* Event specific data */
7956 uint32_t event_data2;
7957 /* Status of HWRM_FW_STATE_QUIESCE completion */
7958 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK \
7960 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT \
7963 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
7964 * completed successfully.
7966 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS \
7969 * The quiesce operation started by HWRM_FW_STATE_QUIESCE timed
7972 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT \
7975 * The quiesce operation started by HWRM_FW_STATE_QUIESCE
7976 * encountered an error.
7978 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR \
7980 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \
7981 HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR
7983 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \
7985 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \
7988 * Additional information about internal hardware state related to
7989 * idle/quiesce state. QUIESCE may succeed per quiesce_status
7990 * regardless of idle_state_flags. If QUIESCE fails, the host may
7991 * inspect idle_state_flags to determine whether a retry is warranted.
7993 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \
7995 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \
7998 * Failure to quiesce is caused by host not updating the NQ consumer
8001 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \
8003 /* Flag 1 indicating partial non-idle state. */
8004 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \
8006 /* Flag 2 indicating partial non-idle state. */
8007 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \
8009 /* Flag 3 indicating partial non-idle state. */
8010 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \
8014 * This value is written by the NIC such that it will be different
8015 * for each pass through the completion queue. The even passes
8016 * will write 1. The odd passes will write 0.
8018 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
8020 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
8021 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_SFT 1
8022 /* 8-lsb timestamp from POR (100-msec resolution) */
8023 uint8_t timestamp_lo;
8024 /* 16-lsb timestamp from POR (100-msec resolution) */
8025 uint16_t timestamp_hi;
8026 /* Event specific data */
8027 uint32_t event_data1;
8028 /* Time stamp for error event */
8029 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP \
8033 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
8034 struct hwrm_async_event_cmpl_deferred_response {
8037 * This field indicates the exact type of the completion.
8038 * By convention, the LSB identifies the length of the
8039 * record in 16B units. Even values indicate 16B
8040 * records. Odd values indicate 32B
8043 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \
8045 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
8046 /* HWRM Asynchronous Event Information */
8047 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \
8049 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \
8050 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
8051 /* Identifiers of events. */
8054 * An event signifying a HWRM command is in progress and its
8055 * response will be deferred
8057 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \
8059 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \
8060 HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
8061 /* Event specific data */
8062 uint32_t event_data2;
8064 * The PF's mailbox is clear to issue another command.
8065 * A command with this seq_id is still in progress
8066 * and will return a regular HWRM completion when done.
8067 * 'event_data1' field, if non-zero, contains the estimated
8068 * execution time for the command.
8070 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \
8072 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \
8076 * This value is written by the NIC such that it will be different
8077 * for each pass through the completion queue. The even passes
8078 * will write 1. The odd passes will write 0.
8080 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \
8083 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \
8085 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
8086 /* 8-lsb timestamp from POR (100-msec resolution) */
8087 uint8_t timestamp_lo;
8088 /* 16-lsb timestamp from POR (100-msec resolution) */
8089 uint16_t timestamp_hi;
8090 /* Estimated remaining time of command execution in ms (if not zero) */
8091 uint32_t event_data1;
8094 /* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */
8095 struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {
8098 * This field indicates the exact type of the completion.
8099 * By convention, the LSB identifies the length of the
8100 * record in 16B units. Even values indicate 16B
8101 * records. Odd values indicate 32B
8104 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \
8106 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \
8108 /* HWRM Asynchronous Event Information */
8109 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
8111 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \
8112 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
8113 /* Identifiers of events. */
8115 /* PFC watchdog configuration change for given port/cos */
8116 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \
8118 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \
8119 HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE
8120 /* Event specific data */
8121 uint32_t event_data2;
8124 * This value is written by the NIC such that it will be different
8125 * for each pass through the completion queue. The even passes
8126 * will write 1. The odd passes will write 0.
8128 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \
8131 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \
8133 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1
8134 /* 8-lsb timestamp from POR (100-msec resolution) */
8135 uint8_t timestamp_lo;
8136 /* 16-lsb timestamp from POR (100-msec resolution) */
8137 uint16_t timestamp_hi;
8138 /* Event specific data */
8139 uint32_t event_data1;
8141 * 1 in bit position X indicates PFC watchdog should
8144 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \
8146 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \
8148 /* 1 means PFC WD for COS0 is on, 0 - off. */
8149 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \
8151 /* 1 means PFC WD for COS1 is on, 0 - off. */
8152 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \
8154 /* 1 means PFC WD for COS2 is on, 0 - off. */
8155 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \
8157 /* 1 means PFC WD for COS3 is on, 0 - off. */
8158 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \
8160 /* 1 means PFC WD for COS4 is on, 0 - off. */
8161 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \
8163 /* 1 means PFC WD for COS5 is on, 0 - off. */
8164 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \
8166 /* 1 means PFC WD for COS6 is on, 0 - off. */
8167 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \
8169 /* 1 means PFC WD for COS7 is on, 0 - off. */
8170 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \
8173 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
8175 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
8179 /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
8180 struct hwrm_async_event_cmpl_fw_trace_msg {
8183 * This field indicates the exact type of the completion.
8184 * By convention, the LSB identifies the length of the
8185 * record in 16B units. Even values indicate 16B
8186 * records. Odd values indicate 32B
8189 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
8191 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
8192 /* HWRM Asynchronous Event Information */
8193 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
8195 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
8196 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
8197 /* Identifiers of events. */
8199 /* Firmware trace log message */
8200 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
8202 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
8203 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
8204 /* Trace byte 0 to 3 */
8205 uint32_t event_data2;
8207 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
8209 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
8211 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
8213 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
8215 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
8217 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
8219 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
8220 UINT32_C(0xff000000)
8221 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
8224 * This value is written by the NIC such that it will be different
8225 * for each pass through the completion queue. The even passes
8226 * will write 1. The odd passes will write 0.
8228 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
8230 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
8231 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
8233 uint8_t timestamp_lo;
8234 /* Indicates if the string is partial or complete. */
8235 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
8237 /* Complete string */
8238 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
8240 /* Partial string */
8241 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
8243 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
8244 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
8245 /* Indicates the firmware that sent the trace message. */
8246 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
8248 /* Primary firmware */
8249 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
8250 (UINT32_C(0x0) << 1)
8251 /* Secondary firmware */
8252 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
8253 (UINT32_C(0x1) << 1)
8254 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
8255 HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
8256 /* Trace byte 4 to 5 */
8257 uint16_t timestamp_hi;
8259 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
8261 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
8263 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
8265 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
8266 /* Trace byte 6 to 9 */
8267 uint32_t event_data1;
8269 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
8271 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
8273 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
8275 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
8277 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
8279 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
8281 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
8282 UINT32_C(0xff000000)
8283 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
8286 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
8287 struct hwrm_async_event_cmpl_hwrm_error {
8290 * This field indicates the exact type of the completion.
8291 * By convention, the LSB identifies the length of the
8292 * record in 16B units. Even values indicate 16B
8293 * records. Odd values indicate 32B
8296 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
8298 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
8299 /* HWRM Asynchronous Event Information */
8300 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
8302 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
8303 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
8304 /* Identifiers of events. */
8307 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
8309 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
8310 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
8311 /* Event specific data */
8312 uint32_t event_data2;
8313 /* Severity of HWRM Error */
8314 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
8316 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
8318 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
8320 /* Non-fatal Error */
8321 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
8324 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
8326 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
8327 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
8330 * This value is written by the NIC such that it will be different
8331 * for each pass through the completion queue. The even passes
8332 * will write 1. The odd passes will write 0.
8334 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
8336 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
8337 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
8338 /* 8-lsb timestamp from POR (100-msec resolution) */
8339 uint8_t timestamp_lo;
8340 /* 16-lsb timestamp from POR (100-msec resolution) */
8341 uint16_t timestamp_hi;
8342 /* Event specific data */
8343 uint32_t event_data1;
8344 /* Time stamp for error event */
8345 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
8349 /*******************
8351 *******************/
8354 /* hwrm_func_reset_input (size:192b/24B) */
8355 struct hwrm_func_reset_input {
8356 /* The HWRM command request type. */
8359 * The completion ring to send the completion event on. This should
8360 * be the NQ ID returned from the `nq_alloc` HWRM command.
8364 * The sequence ID is used by the driver for tracking multiple
8365 * commands. This ID is treated as opaque data by the firmware and
8366 * the value is returned in the `hwrm_resp_hdr` upon completion.
8370 * The target ID of the command:
8371 * * 0x0-0xFFF8 - The function ID
8372 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8373 * * 0xFFFD - Reserved for user-space HWRM interface
8378 * A physical address pointer pointing to a host buffer that the
8379 * command's response data will be written. This can be either a host
8380 * physical address (HPA) or a guest physical address (GPA) and must
8381 * point to a physically contiguous block of memory.
8386 * This bit must be '1' for the vf_id_valid field to be
8389 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
8391 * The ID of the VF that this PF is trying to reset.
8392 * Only the parent PF shall be allowed to reset a child VF.
8394 * A parent PF driver shall use this field only when a specific child VF
8395 * is requested to be reset.
8398 /* This value indicates the level of a function reset. */
8399 uint8_t func_reset_level;
8401 * Reset the caller function and its children VFs (if any). If no
8402 * children functions exist, then reset the caller function only.
8404 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
8406 /* Reset the caller function only */
8407 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
8410 * Reset all children VFs of the caller function driver if the
8411 * caller is a PF driver.
8412 * It is an error to specify this level by a VF driver.
8413 * It is an error to specify this level by a PF driver with
8416 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
8419 * Reset a specific VF of the caller function driver if the caller
8420 * is the parent PF driver.
8421 * It is an error to specify this level by a VF driver.
8422 * It is an error to specify this level by a PF driver that is not
8423 * the parent of the VF that is being requested to reset.
8425 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
8427 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
8428 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
8432 /* hwrm_func_reset_output (size:128b/16B) */
8433 struct hwrm_func_reset_output {
8434 /* The specific error status for the command. */
8435 uint16_t error_code;
8436 /* The HWRM command request type. */
8438 /* The sequence ID from the original command. */
8440 /* The length of the response data in number of bytes. */
8442 uint8_t unused_0[7];
8444 * This field is used in Output records to indicate that the output
8445 * is completely written to RAM. This field should be read as '1'
8446 * to indicate that the output has been completely written.
8447 * When writing a command completion or response to an internal processor,
8448 * the order of writes has to be such that this field is written last.
8453 /********************
8454 * hwrm_func_getfid *
8455 ********************/
8458 /* hwrm_func_getfid_input (size:192b/24B) */
8459 struct hwrm_func_getfid_input {
8460 /* The HWRM command request type. */
8463 * The completion ring to send the completion event on. This should
8464 * be the NQ ID returned from the `nq_alloc` HWRM command.
8468 * The sequence ID is used by the driver for tracking multiple
8469 * commands. This ID is treated as opaque data by the firmware and
8470 * the value is returned in the `hwrm_resp_hdr` upon completion.
8474 * The target ID of the command:
8475 * * 0x0-0xFFF8 - The function ID
8476 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8477 * * 0xFFFD - Reserved for user-space HWRM interface
8482 * A physical address pointer pointing to a host buffer that the
8483 * command's response data will be written. This can be either a host
8484 * physical address (HPA) or a guest physical address (GPA) and must
8485 * point to a physically contiguous block of memory.
8490 * This bit must be '1' for the pci_id field to be
8493 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
8495 * This value is the PCI ID of the queried function.
8496 * If ARI is enabled, then it is
8497 * Bus Number (8b):Function Number(8b). Otherwise, it is
8498 * Bus Number (8b):Device Number (5b):Function Number(3b).
8501 uint8_t unused_0[2];
8504 /* hwrm_func_getfid_output (size:128b/16B) */
8505 struct hwrm_func_getfid_output {
8506 /* The specific error status for the command. */
8507 uint16_t error_code;
8508 /* The HWRM command request type. */
8510 /* The sequence ID from the original command. */
8512 /* The length of the response data in number of bytes. */
8515 * FID value. This value is used to identify operations on the PCI
8516 * bus as belonging to a particular PCI function.
8519 uint8_t unused_0[5];
8521 * This field is used in Output records to indicate that the output
8522 * is completely written to RAM. This field should be read as '1'
8523 * to indicate that the output has been completely written.
8524 * When writing a command completion or response to an internal processor,
8525 * the order of writes has to be such that this field is written last.
8530 /**********************
8531 * hwrm_func_vf_alloc *
8532 **********************/
8535 /* hwrm_func_vf_alloc_input (size:192b/24B) */
8536 struct hwrm_func_vf_alloc_input {
8537 /* The HWRM command request type. */
8540 * The completion ring to send the completion event on. This should
8541 * be the NQ ID returned from the `nq_alloc` HWRM command.
8545 * The sequence ID is used by the driver for tracking multiple
8546 * commands. This ID is treated as opaque data by the firmware and
8547 * the value is returned in the `hwrm_resp_hdr` upon completion.
8551 * The target ID of the command:
8552 * * 0x0-0xFFF8 - The function ID
8553 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8554 * * 0xFFFD - Reserved for user-space HWRM interface
8559 * A physical address pointer pointing to a host buffer that the
8560 * command's response data will be written. This can be either a host
8561 * physical address (HPA) or a guest physical address (GPA) and must
8562 * point to a physically contiguous block of memory.
8567 * This bit must be '1' for the first_vf_id field to be
8570 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8572 * This value is used to identify a Virtual Function (VF).
8573 * The scope of VF ID is local within a PF.
8575 uint16_t first_vf_id;
8576 /* The number of virtual functions requested. */
8580 /* hwrm_func_vf_alloc_output (size:128b/16B) */
8581 struct hwrm_func_vf_alloc_output {
8582 /* The specific error status for the command. */
8583 uint16_t error_code;
8584 /* The HWRM command request type. */
8586 /* The sequence ID from the original command. */
8588 /* The length of the response data in number of bytes. */
8590 /* The ID of the first VF allocated. */
8591 uint16_t first_vf_id;
8592 uint8_t unused_0[5];
8594 * This field is used in Output records to indicate that the output
8595 * is completely written to RAM. This field should be read as '1'
8596 * to indicate that the output has been completely written.
8597 * When writing a command completion or response to an internal processor,
8598 * the order of writes has to be such that this field is written last.
8603 /*********************
8604 * hwrm_func_vf_free *
8605 *********************/
8608 /* hwrm_func_vf_free_input (size:192b/24B) */
8609 struct hwrm_func_vf_free_input {
8610 /* The HWRM command request type. */
8613 * The completion ring to send the completion event on. This should
8614 * be the NQ ID returned from the `nq_alloc` HWRM command.
8618 * The sequence ID is used by the driver for tracking multiple
8619 * commands. This ID is treated as opaque data by the firmware and
8620 * the value is returned in the `hwrm_resp_hdr` upon completion.
8624 * The target ID of the command:
8625 * * 0x0-0xFFF8 - The function ID
8626 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8627 * * 0xFFFD - Reserved for user-space HWRM interface
8632 * A physical address pointer pointing to a host buffer that the
8633 * command's response data will be written. This can be either a host
8634 * physical address (HPA) or a guest physical address (GPA) and must
8635 * point to a physically contiguous block of memory.
8640 * This bit must be '1' for the first_vf_id field to be
8643 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
8645 * This value is used to identify a Virtual Function (VF).
8646 * The scope of VF ID is local within a PF.
8648 uint16_t first_vf_id;
8650 * The number of virtual functions requested.
8651 * 0xFFFF - Cleanup all children of this PF.
8656 /* hwrm_func_vf_free_output (size:128b/16B) */
8657 struct hwrm_func_vf_free_output {
8658 /* The specific error status for the command. */
8659 uint16_t error_code;
8660 /* The HWRM command request type. */
8662 /* The sequence ID from the original command. */
8664 /* The length of the response data in number of bytes. */
8666 uint8_t unused_0[7];
8668 * This field is used in Output records to indicate that the output
8669 * is completely written to RAM. This field should be read as '1'
8670 * to indicate that the output has been completely written.
8671 * When writing a command completion or response to an internal processor,
8672 * the order of writes has to be such that this field is written last.
8677 /********************
8678 * hwrm_func_vf_cfg *
8679 ********************/
8682 /* hwrm_func_vf_cfg_input (size:448b/56B) */
8683 struct hwrm_func_vf_cfg_input {
8684 /* The HWRM command request type. */
8687 * The completion ring to send the completion event on. This should
8688 * be the NQ ID returned from the `nq_alloc` HWRM command.
8692 * The sequence ID is used by the driver for tracking multiple
8693 * commands. This ID is treated as opaque data by the firmware and
8694 * the value is returned in the `hwrm_resp_hdr` upon completion.
8698 * The target ID of the command:
8699 * * 0x0-0xFFF8 - The function ID
8700 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8701 * * 0xFFFD - Reserved for user-space HWRM interface
8706 * A physical address pointer pointing to a host buffer that the
8707 * command's response data will be written. This can be either a host
8708 * physical address (HPA) or a guest physical address (GPA) and must
8709 * point to a physically contiguous block of memory.
8714 * This bit must be '1' for the mtu field to be
8717 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
8720 * This bit must be '1' for the guest_vlan field to be
8723 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
8726 * This bit must be '1' for the async_event_cr field to be
8729 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
8732 * This bit must be '1' for the dflt_mac_addr field to be
8735 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
8738 * This bit must be '1' for the num_rsscos_ctxs field to be
8741 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
8744 * This bit must be '1' for the num_cmpl_rings field to be
8747 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
8750 * This bit must be '1' for the num_tx_rings field to be
8753 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
8756 * This bit must be '1' for the num_rx_rings field to be
8759 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
8762 * This bit must be '1' for the num_l2_ctxs field to be
8765 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
8768 * This bit must be '1' for the num_vnics field to be
8771 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
8774 * This bit must be '1' for the num_stat_ctxs field to be
8777 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
8780 * This bit must be '1' for the num_hw_ring_grps field to be
8783 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
8786 * The maximum transmission unit requested on the function.
8787 * The HWRM should make sure that the mtu of
8788 * the function does not exceed the mtu of the physical
8789 * port that this function is associated with.
8791 * In addition to requesting mtu per function, it is
8792 * possible to configure mtu per transmit ring.
8793 * By default, the mtu of each transmit ring associated
8794 * with a function is equal to the mtu of the function.
8795 * The HWRM should make sure that the mtu of each transmit
8796 * ring that is assigned to a function has a valid mtu.
8800 * The guest VLAN for the function being configured.
8801 * This field's format is same as 802.1Q Tag's
8802 * Tag Control Information (TCI) format that includes both
8803 * Priority Code Point (PCP) and VLAN Identifier (VID).
8805 uint16_t guest_vlan;
8807 * ID of the target completion ring for receiving asynchronous
8808 * event completions. If this field is not valid, then the
8809 * HWRM shall use the default completion ring of the function
8810 * that is being configured as the target completion ring for
8811 * providing any asynchronous event completions for that
8813 * If this field is valid, then the HWRM shall use the
8814 * completion ring identified by this ID as the target
8815 * completion ring for providing any asynchronous event
8816 * completions for the function that is being configured.
8818 uint16_t async_event_cr;
8820 * This value is the current MAC address requested by the VF
8821 * driver to be configured on this VF. A value of
8822 * 00-00-00-00-00-00 indicates no MAC address configuration
8823 * is requested by the VF driver.
8824 * The parent PF driver may reject or overwrite this
8827 uint8_t dflt_mac_addr[6];
8830 * This bit requests that the firmware test to see if all the assets
8831 * requested in this command (i.e. number of TX rings) are available.
8832 * The firmware will return an error if the requested assets are
8833 * not available. The firwmare will NOT reserve the assets if they
8836 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
8839 * This bit requests that the firmware test to see if all the assets
8840 * requested in this command (i.e. number of RX rings) are available.
8841 * The firmware will return an error if the requested assets are
8842 * not available. The firwmare will NOT reserve the assets if they
8845 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
8848 * This bit requests that the firmware test to see if all the assets
8849 * requested in this command (i.e. number of CMPL rings) are available.
8850 * The firmware will return an error if the requested assets are
8851 * not available. The firwmare will NOT reserve the assets if they
8854 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
8857 * This bit requests that the firmware test to see if all the assets
8858 * requested in this command (i.e. number of RSS ctx) are available.
8859 * The firmware will return an error if the requested assets are
8860 * not available. The firwmare will NOT reserve the assets if they
8863 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
8866 * This bit requests that the firmware test to see if all the assets
8867 * requested in this command (i.e. number of ring groups) are available.
8868 * The firmware will return an error if the requested assets are
8869 * not available. The firwmare will NOT reserve the assets if they
8872 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
8875 * This bit requests that the firmware test to see if all the assets
8876 * requested in this command (i.e. number of stat ctx) are available.
8877 * The firmware will return an error if the requested assets are
8878 * not available. The firwmare will NOT reserve the assets if they
8881 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
8884 * This bit requests that the firmware test to see if all the assets
8885 * requested in this command (i.e. number of VNICs) are available.
8886 * The firmware will return an error if the requested assets are
8887 * not available. The firwmare will NOT reserve the assets if they
8890 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
8893 * This bit requests that the firmware test to see if all the assets
8894 * requested in this command (i.e. number of L2 ctx) are available.
8895 * The firmware will return an error if the requested assets are
8896 * not available. The firwmare will NOT reserve the assets if they
8899 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
8902 * If this bit is set to 1, the VF driver is requesting FW to enable
8903 * PPP TX PUSH feature on all the TX rings specified in the
8904 * num_tx_rings field. By default, the PPP TX push feature is
8905 * disabled for all the TX rings of the VF. This flag is ignored if
8906 * the num_tx_rings field is not specified or the VF doesn't support
8907 * PPP tx push feature.
8909 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
8911 /* The number of RSS/COS contexts requested for the VF. */
8912 uint16_t num_rsscos_ctxs;
8913 /* The number of completion rings requested for the VF. */
8914 uint16_t num_cmpl_rings;
8915 /* The number of transmit rings requested for the VF. */
8916 uint16_t num_tx_rings;
8917 /* The number of receive rings requested for the VF. */
8918 uint16_t num_rx_rings;
8919 /* The number of L2 contexts requested for the VF. */
8920 uint16_t num_l2_ctxs;
8921 /* The number of vnics requested for the VF. */
8923 /* The number of statistic contexts requested for the VF. */
8924 uint16_t num_stat_ctxs;
8925 /* The number of HW ring groups requested for the VF. */
8926 uint16_t num_hw_ring_grps;
8927 uint8_t unused_0[4];
8930 /* hwrm_func_vf_cfg_output (size:128b/16B) */
8931 struct hwrm_func_vf_cfg_output {
8932 /* The specific error status for the command. */
8933 uint16_t error_code;
8934 /* The HWRM command request type. */
8936 /* The sequence ID from the original command. */
8938 /* The length of the response data in number of bytes. */
8940 uint8_t unused_0[7];
8942 * This field is used in Output records to indicate that the output
8943 * is completely written to RAM. This field should be read as '1'
8944 * to indicate that the output has been completely written.
8945 * When writing a command completion or response to an internal processor,
8946 * the order of writes has to be such that this field is written last.
8951 /*******************
8953 *******************/
8956 /* hwrm_func_qcaps_input (size:192b/24B) */
8957 struct hwrm_func_qcaps_input {
8958 /* The HWRM command request type. */
8961 * The completion ring to send the completion event on. This should
8962 * be the NQ ID returned from the `nq_alloc` HWRM command.
8966 * The sequence ID is used by the driver for tracking multiple
8967 * commands. This ID is treated as opaque data by the firmware and
8968 * the value is returned in the `hwrm_resp_hdr` upon completion.
8972 * The target ID of the command:
8973 * * 0x0-0xFFF8 - The function ID
8974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
8975 * * 0xFFFD - Reserved for user-space HWRM interface
8980 * A physical address pointer pointing to a host buffer that the
8981 * command's response data will be written. This can be either a host
8982 * physical address (HPA) or a guest physical address (GPA) and must
8983 * point to a physically contiguous block of memory.
8987 * Function ID of the function that is being queried.
8988 * 0xFF... (All Fs) if the query is for the requesting
8990 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
8991 * to be used by a trusted VF to query its parent PF.
8994 uint8_t unused_0[6];
8997 /* hwrm_func_qcaps_output (size:704b/88B) */
8998 struct hwrm_func_qcaps_output {
8999 /* The specific error status for the command. */
9000 uint16_t error_code;
9001 /* The HWRM command request type. */
9003 /* The sequence ID from the original command. */
9005 /* The length of the response data in number of bytes. */
9008 * FID value. This value is used to identify operations on the PCI
9009 * bus as belonging to a particular PCI function.
9013 * Port ID of port that this function is associated with.
9014 * Valid only for the PF.
9015 * 0xFF... (All Fs) if this function is not associated with
9017 * 0xFF... (All Fs) if this function is called from a VF.
9021 /* If 1, then Push mode is supported on this function. */
9022 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
9025 * If 1, then the global MSI-X auto-masking is enabled for the
9028 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
9031 * If 1, then the Precision Time Protocol (PTP) processing
9032 * is supported on this function.
9033 * The HWRM should enable PTP on only a single Physical
9034 * Function (PF) per port.
9036 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
9039 * If 1, then RDMA over Converged Ethernet (RoCE) v1
9040 * is supported on this function.
9042 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
9045 * If 1, then RDMA over Converged Ethernet (RoCE) v2
9046 * is supported on this function.
9048 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
9051 * If 1, then control and configuration of WoL magic packet
9052 * are supported on this function.
9054 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
9057 * If 1, then control and configuration of bitmap pattern
9058 * packet are supported on this function.
9060 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
9063 * If set to 1, then the control and configuration of rate limit
9064 * of an allocated TX ring on the queried function is supported.
9066 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
9069 * If 1, then control and configuration of minimum and
9070 * maximum bandwidths are supported on the queried function.
9072 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
9075 * If the query is for a VF, then this flag shall be ignored.
9076 * If this query is for a PF and this flag is set to 1,
9077 * then the PF has the capability to set the rate limits
9078 * on the TX rings of its children VFs.
9079 * If this query is for a PF and this flag is set to 0, then
9080 * the PF does not have the capability to set the rate limits
9081 * on the TX rings of its children VFs.
9083 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
9086 * If the query is for a VF, then this flag shall be ignored.
9087 * If this query is for a PF and this flag is set to 1,
9088 * then the PF has the capability to set the minimum and/or
9089 * maximum bandwidths for its children VFs.
9090 * If this query is for a PF and this flag is set to 0, then
9091 * the PF does not have the capability to set the minimum or
9092 * maximum bandwidths for its children VFs.
9094 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
9097 * Standard TX Ring mode is used for the allocation of TX ring
9098 * and underlying scheduling resources that allow bandwidth
9099 * reservation and limit settings on the queried function.
9100 * If set to 1, then standard TX ring mode is supported
9101 * on the queried function.
9102 * If set to 0, then standard TX ring mode is not available
9103 * on the queried function.
9105 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
9108 * If the query is for a VF, then this flag shall be ignored,
9109 * If this query is for a PF and this flag is set to 1,
9110 * then the PF has the capability to detect GENEVE tunnel
9113 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
9116 * If the query is for a VF, then this flag shall be ignored,
9117 * If this query is for a PF and this flag is set to 1,
9118 * then the PF has the capability to detect NVGRE tunnel
9121 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
9124 * If the query is for a VF, then this flag shall be ignored,
9125 * If this query is for a PF and this flag is set to 1,
9126 * then the PF has the capability to detect GRE tunnel
9129 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
9132 * If the query is for a VF, then this flag shall be ignored,
9133 * If this query is for a PF and this flag is set to 1,
9134 * then the PF has the capability to detect MPLS tunnel
9137 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
9140 * If the query is for a VF, then this flag shall be ignored,
9141 * If this query is for a PF and this flag is set to 1,
9142 * then the PF has the capability to support pcie stats.
9144 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
9147 * If the query is for a VF, then this flag shall be ignored,
9148 * If this query is for a PF and this flag is set to 1,
9149 * then the PF has the capability to adopt the VF's belonging
9152 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED \
9155 * If the query is for a VF, then this flag shall be ignored,
9156 * If this query is for a PF and this flag is set to 1,
9157 * then the PF has the administrative privilege to configure another PF
9159 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
9162 * If the query is for a VF, then this flag shall be ignored.
9163 * If this query is for a PF and this flag is set to 1, then
9164 * the PF will know that the firmware has the capability to track
9165 * the virtual link status.
9167 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \
9170 * If 1, then this function supports the push mode that uses
9171 * write combine buffers and the long inline tx buffer descriptor.
9173 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
9176 * If 1, then FW has capability to allocate TX rings dynamically
9177 * in ring alloc even if PF reserved pool is zero.
9178 * This bit will be used only for PFs.
9180 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
9183 * When this bit is '1', it indicates that core firmware is
9184 * capable of Hot Reset.
9186 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
9189 * This flag will be set to 1 by the FW if FW supports adapter error
9192 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
9195 * If the query is for a VF, then this flag shall be ignored.
9196 * If this query is for a PF and this flag is set to 1, then
9197 * the PF has the capability to support extended stats.
9199 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
9202 * If the query is for a VF, then this flag shall be ignored.
9203 * If this query is for a PF and this flag is set to 1, then host
9204 * must initiate reset or reload (or fastboot) the firmware image
9205 * upon detection of device shutdown state.
9207 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD \
9210 * If the query is for a VF, then this flag (always set to 0) shall
9211 * be ignored. If this query is for a PF and this flag is set to 1,
9212 * host, when registered for the default vnic change async event,
9213 * receives async notification whenever a default vnic state is
9214 * changed for any of child or adopted VFs.
9216 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \
9218 /* If set to 1, then the vlan acceleration for TX is disabled. */
9219 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \
9222 * When this bit is '1', it indicates that core firmware supports
9223 * DBG_COREDUMP_XXX commands.
9225 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \
9226 UINT32_C(0x10000000)
9228 * When this bit is '1', it indicates that core firmware supports
9229 * DBG_CRASHDUMP_XXX commands.
9231 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \
9232 UINT32_C(0x20000000)
9234 * If the query is for a VF, then this flag should be ignored.
9235 * If the query is for a PF and this flag is set to 1, then
9236 * the PF has the capability to support retrieval of
9237 * rx_port_stats_ext_pfc_wd statistics (supported by the PFC
9238 * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.
9239 * If this flag is set to 1, only that (supported) command should
9240 * be used for retrieval of PFC related statistics (rather than
9241 * hwrm_port_qstats_ext command, which could previously be used).
9243 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \
9244 UINT32_C(0x40000000)
9246 * When this bit is '1', it indicates that core firmware supports
9249 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \
9250 UINT32_C(0x80000000)
9252 * This value is current MAC address configured for this
9253 * function. A value of 00-00-00-00-00-00 indicates no
9254 * MAC address is currently configured.
9256 uint8_t mac_address[6];
9258 * The maximum number of RSS/COS contexts that can be
9259 * allocated to the function.
9261 uint16_t max_rsscos_ctx;
9263 * The maximum number of completion rings that can be
9264 * allocated to the function.
9266 uint16_t max_cmpl_rings;
9268 * The maximum number of transmit rings that can be
9269 * allocated to the function.
9271 uint16_t max_tx_rings;
9273 * The maximum number of receive rings that can be
9274 * allocated to the function.
9276 uint16_t max_rx_rings;
9278 * The maximum number of L2 contexts that can be
9279 * allocated to the function.
9281 uint16_t max_l2_ctxs;
9283 * The maximum number of VNICs that can be
9284 * allocated to the function.
9288 * The identifier for the first VF enabled on a PF. This
9289 * is valid only on the PF with SR-IOV enabled.
9290 * 0xFF... (All Fs) if this command is called on a PF with
9291 * SR-IOV disabled or on a VF.
9293 uint16_t first_vf_id;
9295 * The maximum number of VFs that can be
9296 * allocated to the function. This is valid only on the
9297 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
9298 * command is called on a PF with SR-IOV disabled or
9303 * The maximum number of statistic contexts that can be
9304 * allocated to the function.
9306 uint16_t max_stat_ctx;
9308 * The maximum number of Encapsulation records that can be
9309 * offloaded by this function.
9311 uint32_t max_encap_records;
9313 * The maximum number of decapsulation records that can
9314 * be offloaded by this function.
9316 uint32_t max_decap_records;
9318 * The maximum number of Exact Match (EM) flows that can be
9319 * offloaded by this function on the TX side.
9321 uint32_t max_tx_em_flows;
9323 * The maximum number of Wildcard Match (WM) flows that can
9324 * be offloaded by this function on the TX side.
9326 uint32_t max_tx_wm_flows;
9328 * The maximum number of Exact Match (EM) flows that can be
9329 * offloaded by this function on the RX side.
9331 uint32_t max_rx_em_flows;
9333 * The maximum number of Wildcard Match (WM) flows that can
9334 * be offloaded by this function on the RX side.
9336 uint32_t max_rx_wm_flows;
9338 * The maximum number of multicast filters that can
9339 * be supported by this function on the RX side.
9341 uint32_t max_mcast_filters;
9343 * The maximum value of flow_id that can be supported
9344 * in completion records.
9346 uint32_t max_flow_id;
9348 * The maximum number of HW ring groups that can be
9349 * supported on this function.
9351 uint32_t max_hw_ring_grps;
9353 * The maximum number of strict priority transmit rings
9354 * that can be allocated to the function.
9355 * This number indicates the maximum number of TX rings
9356 * that can be assigned strict priorities out of the
9357 * maximum number of TX rings that can be allocated
9358 * (max_tx_rings) to the function.
9360 uint16_t max_sp_tx_rings;
9361 uint8_t unused_0[2];
9364 * If 1, the device can be configured to set the ECN bits in the
9365 * IP header of received packets if the receive queue length
9366 * exceeds a given threshold.
9368 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \
9371 * If 1, the device can report the number of received packets
9372 * that it marked as having experienced congestion.
9374 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \
9377 * If 1, the device can report extended hw statistics (including
9378 * additional tpa statistics).
9380 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \
9383 * If set to 1, then the core firmware has support to enable/
9384 * disable hot reset support for interface dynamically through
9387 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \
9389 /* If 1, the proxy mode is supported on this function */
9390 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT \
9393 * If 1, the tx rings source interface override feature is supported
9396 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT \
9399 * If 1, the device supports scheduler queues. SQs can be managed
9400 * using RING_SQ_ALLOC/CFG/FREE commands.
9402 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SQ_SUPPORTED \
9405 * If set to 1, then this function supports the TX push mode that
9406 * uses ping-pong buffers from the push pages.
9408 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \
9410 /* The maximum number of SQs supported by this device. */
9412 uint8_t unused_1[2];
9414 * This field is used in Output records to indicate that the output
9415 * is completely written to RAM. This field should be read as '1'
9416 * to indicate that the output has been completely written.
9417 * When writing a command completion or response to an internal processor,
9418 * the order of writes has to be such that this field is written last.
9428 /* hwrm_func_qcfg_input (size:192b/24B) */
9429 struct hwrm_func_qcfg_input {
9430 /* The HWRM command request type. */
9433 * The completion ring to send the completion event on. This should
9434 * be the NQ ID returned from the `nq_alloc` HWRM command.
9438 * The sequence ID is used by the driver for tracking multiple
9439 * commands. This ID is treated as opaque data by the firmware and
9440 * the value is returned in the `hwrm_resp_hdr` upon completion.
9444 * The target ID of the command:
9445 * * 0x0-0xFFF8 - The function ID
9446 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9447 * * 0xFFFD - Reserved for user-space HWRM interface
9452 * A physical address pointer pointing to a host buffer that the
9453 * command's response data will be written. This can be either a host
9454 * physical address (HPA) or a guest physical address (GPA) and must
9455 * point to a physically contiguous block of memory.
9459 * Function ID of the function that is being queried.
9460 * 0xFF... (All Fs) if the query is for the requesting
9462 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
9463 * to be used by a trusted VF to query its parent PF.
9466 uint8_t unused_0[6];
9469 /* hwrm_func_qcfg_output (size:768b/96B) */
9470 struct hwrm_func_qcfg_output {
9471 /* The specific error status for the command. */
9472 uint16_t error_code;
9473 /* The HWRM command request type. */
9475 /* The sequence ID from the original command. */
9477 /* The length of the response data in number of bytes. */
9480 * FID value. This value is used to identify operations on the PCI
9481 * bus as belonging to a particular PCI function.
9485 * Port ID of port that this function is associated with.
9486 * 0xFF... (All Fs) if this function is not associated with
9491 * This value is the current VLAN setting for this
9492 * function. The value of 0 for this field indicates
9493 * no priority tagging or VLAN is used.
9494 * This field's format is same as 802.1Q Tag's
9495 * Tag Control Information (TCI) format that includes both
9496 * Priority Code Point (PCP) and VLAN Identifier (VID).
9501 * If 1, then magic packet based Out-Of-Box WoL is enabled on
9502 * the port associated with this function.
9504 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
9507 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
9508 * on the port associated with this function.
9510 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
9513 * If set to 1, then FW based DCBX agent is enabled and running on
9514 * the port associated with this function.
9515 * If set to 0, then DCBX agent is not running in the firmware.
9517 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
9520 * Standard TX Ring mode is used for the allocation of TX ring
9521 * and underlying scheduling resources that allow bandwidth
9522 * reservation and limit settings on the queried function.
9523 * If set to 1, then standard TX ring mode is enabled
9524 * on the queried function.
9525 * If set to 0, then the standard TX ring mode is disabled
9526 * on the queried function. In this extended TX ring resource
9527 * mode, the minimum and maximum bandwidth settings are not
9528 * supported to allow the allocation of TX rings to span multiple
9531 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
9534 * If set to 1 then FW based LLDP agent is enabled and running on
9535 * the port associated with this function.
9536 * If set to 0 then the LLDP agent is not running in the firmware.
9538 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
9541 * If set to 1, then multi-host mode is active for this function.
9542 * If set to 0, then multi-host mode is inactive for this function
9543 * or not applicable for this device.
9545 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
9548 * If the function that is being queried is a PF, then the HWRM shall
9549 * set this field to 0 and the HWRM client shall ignore this field.
9550 * If the function that is being queried is a VF, then the HWRM shall
9551 * set this field to 1 if the queried VF is trusted, otherwise the HWRM
9552 * shall set this field to 0.
9554 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
9557 * If set to 1, then secure mode is enabled for this function or device.
9558 * If set to 0, then secure mode is disabled (or normal mode) for this
9559 * function or device.
9561 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
9564 * If set to 1, then this PF is enabled with a preboot driver that
9565 * requires access to the legacy L2 ring model and legacy 32b
9566 * doorbells. If set to 0, then this PF is not allowed to use
9567 * the legacy L2 rings. This feature is not allowed on VFs and
9568 * is only relevant for devices that require a context backing
9571 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
9574 * If set to 1, then the firmware and all currently registered driver
9575 * instances support hot reset. The hot reset support will be updated
9576 * dynamically based on the driver interface advertisement.
9577 * If set to 0, then the adapter is not currently able to initiate
9580 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \
9583 * If set to 1, then the PPP tx push mode is enabled for all the
9584 * reserved TX rings of this function. If set to 0, then PPP tx push
9585 * mode is disabled for all the reserved TX rings of this function.
9587 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED \
9590 * This value is current MAC address configured for this
9591 * function. A value of 00-00-00-00-00-00 indicates no
9592 * MAC address is currently configured.
9594 uint8_t mac_address[6];
9596 * This value is current PCI ID of this
9597 * function. If ARI is enabled, then it is
9598 * Bus Number (8b):Function Number(8b). Otherwise, it is
9599 * Bus Number (8b):Device Number (4b):Function Number(4b).
9600 * If multi-host mode is active, the 4 lsb will indicate
9601 * the PF index for this function.
9605 * The number of RSS/COS contexts currently
9606 * allocated to the function.
9608 uint16_t alloc_rsscos_ctx;
9610 * The number of completion rings currently allocated to
9611 * the function. This does not include the rings allocated
9612 * to any children functions if any.
9614 uint16_t alloc_cmpl_rings;
9616 * The number of transmit rings currently allocated to
9617 * the function. This does not include the rings allocated
9618 * to any children functions if any.
9620 uint16_t alloc_tx_rings;
9622 * The number of receive rings currently allocated to
9623 * the function. This does not include the rings allocated
9624 * to any children functions if any.
9626 uint16_t alloc_rx_rings;
9627 /* The allocated number of L2 contexts to the function. */
9628 uint16_t alloc_l2_ctx;
9629 /* The allocated number of vnics to the function. */
9630 uint16_t alloc_vnics;
9632 * The maximum transmission unit of the function.
9633 * If the reported mtu value is non-zero then it will used for the
9634 * rings allocated on this function. otherwise the default
9635 * value is used if ring MTU is not specified.
9639 * The maximum receive unit of the function.
9640 * For vnics allocated on this function, this default
9641 * value is used if vnic MRU is not specified.
9644 /* The statistics context assigned to a function. */
9645 uint16_t stat_ctx_id;
9647 * The HWRM shall return Unknown value for this field
9648 * when this command is used to query VF's configuration.
9650 uint8_t port_partition_type;
9651 /* Single physical function */
9652 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
9653 /* Multiple physical functions */
9654 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
9655 /* Network Partitioning 1.0 */
9656 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
9657 /* Network Partitioning 1.5 */
9658 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
9659 /* Network Partitioning 2.0 */
9660 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
9662 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
9664 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
9665 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
9667 * This field will indicate number of physical functions on this port_partition.
9668 * HWRM shall return unavail (i.e. value of 0) for this field
9669 * when this command is used to query VF's configuration or
9670 * from older firmware that doesn't support this field.
9672 uint8_t port_pf_cnt;
9673 /* number of PFs is not available */
9674 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
9675 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
9676 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
9678 * The default VNIC ID assigned to a function that is
9681 uint16_t dflt_vnic_id;
9682 uint16_t max_mtu_configured;
9684 * Minimum BW allocated for this function.
9685 * The HWRM will translate this value into byte counter and
9686 * time interval used for the scheduler inside the device.
9687 * A value of 0 indicates the minimum bandwidth is not
9691 /* The bandwidth value. */
9692 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
9694 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
9695 /* The granularity of the value (bits or bytes). */
9696 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
9697 UINT32_C(0x10000000)
9698 /* Value is in bits. */
9699 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
9700 (UINT32_C(0x0) << 28)
9701 /* Value is in bytes. */
9702 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
9703 (UINT32_C(0x1) << 28)
9704 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
9705 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
9706 /* bw_value_unit is 3 b */
9707 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
9708 UINT32_C(0xe0000000)
9709 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
9710 /* Value is in Mb or MB (base 10). */
9711 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
9712 (UINT32_C(0x0) << 29)
9713 /* Value is in Kb or KB (base 10). */
9714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
9715 (UINT32_C(0x2) << 29)
9716 /* Value is in bits or bytes. */
9717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
9718 (UINT32_C(0x4) << 29)
9719 /* Value is in Gb or GB (base 10). */
9720 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
9721 (UINT32_C(0x6) << 29)
9722 /* Value is in 1/100th of a percentage of total bandwidth. */
9723 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
9724 (UINT32_C(0x1) << 29)
9726 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
9727 (UINT32_C(0x7) << 29)
9728 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
9729 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
9731 * Maximum BW allocated for this function.
9732 * The HWRM will translate this value into byte counter and
9733 * time interval used for the scheduler inside the device.
9734 * A value of 0 indicates that the maximum bandwidth is not
9738 /* The bandwidth value. */
9739 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
9741 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
9742 /* The granularity of the value (bits or bytes). */
9743 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
9744 UINT32_C(0x10000000)
9745 /* Value is in bits. */
9746 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
9747 (UINT32_C(0x0) << 28)
9748 /* Value is in bytes. */
9749 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
9750 (UINT32_C(0x1) << 28)
9751 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
9752 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
9753 /* bw_value_unit is 3 b */
9754 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
9755 UINT32_C(0xe0000000)
9756 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
9757 /* Value is in Mb or MB (base 10). */
9758 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
9759 (UINT32_C(0x0) << 29)
9760 /* Value is in Kb or KB (base 10). */
9761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
9762 (UINT32_C(0x2) << 29)
9763 /* Value is in bits or bytes. */
9764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
9765 (UINT32_C(0x4) << 29)
9766 /* Value is in Gb or GB (base 10). */
9767 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
9768 (UINT32_C(0x6) << 29)
9769 /* Value is in 1/100th of a percentage of total bandwidth. */
9770 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
9771 (UINT32_C(0x1) << 29)
9773 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
9774 (UINT32_C(0x7) << 29)
9775 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
9776 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
9778 * This value indicates the Edge virtual bridge mode for the
9779 * domain that this function belongs to.
9782 /* No Edge Virtual Bridging (EVB) */
9783 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
9784 /* Virtual Ethernet Bridge (VEB) */
9785 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
9786 /* Virtual Ethernet Port Aggregator (VEPA) */
9787 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
9788 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
9789 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
9792 * This value indicates the PCIE device cache line size.
9793 * The cache line size allows the DMA writes to terminate and
9794 * start at the cache boundary.
9796 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
9798 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
9799 /* Cache Line Size 64 bytes */
9800 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
9802 /* Cache Line Size 128 bytes */
9803 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
9805 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
9806 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
9807 /* This value is the virtual link admin state setting. */
9808 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
9810 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
9811 /* Admin link state is in forced down mode. */
9812 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
9813 (UINT32_C(0x0) << 2)
9814 /* Admin link state is in forced up mode. */
9815 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
9816 (UINT32_C(0x1) << 2)
9817 /* Admin link state is in auto mode - follows the physical link state. */
9818 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
9819 (UINT32_C(0x2) << 2)
9820 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
9821 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
9822 /* Reserved for future. */
9823 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
9825 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4
9827 * The number of VFs that are allocated to the function.
9828 * This is valid only on the PF with SR-IOV enabled.
9829 * 0xFF... (All Fs) if this command is called on a PF with
9830 * SR-IOV disabled or on a VF.
9834 * The number of allocated multicast filters for this
9835 * function on the RX side.
9837 uint32_t alloc_mcast_filters;
9839 * The number of allocated HW ring groups for this
9842 uint32_t alloc_hw_ring_grps;
9844 * The number of strict priority transmit rings out of
9845 * currently allocated TX rings to the function
9848 uint16_t alloc_sp_tx_rings;
9850 * The number of statistics contexts
9851 * currently reserved for the function.
9853 uint16_t alloc_stat_ctx;
9855 * This field specifies how many NQs are reserved for the PF.
9856 * Remaining NQs that belong to the PF are available for VFs.
9857 * Once a PF has created VFs, it cannot change how many NQs are
9858 * reserved for itself (since the NQs must be contiguous in HW).
9860 uint16_t alloc_msix;
9862 * The number of registered VF’s associated with the PF. This field
9863 * should be ignored when the request received on the VF interface.
9864 * This field will be updated on the PF interface to initiate
9865 * the unregister request on PF in the HOT Reset Process.
9867 uint16_t registered_vfs;
9869 * The size of the doorbell BAR in KBytes reserved for L2 including
9870 * any area that is shared between L2 and RoCE. The L2 driver
9871 * should only map the L2 portion of the doorbell BAR. Any rounding
9872 * of the BAR size to the native CPU page size should be performed
9873 * by the driver. If the value is zero, no special partitioning
9874 * of the doorbell BAR between L2 and RoCE is required.
9876 uint16_t l2_doorbell_bar_size_kb;
9879 * For backward compatibility this field must be set to 1.
9880 * Older drivers might look for this field to be 1 before
9881 * processing the message.
9885 * This GRC address location is used by the Host driver interfaces to poll
9886 * the adapter ready state to re-initiate the registration process again
9887 * after receiving the RESET Notify event.
9889 uint32_t reset_addr_poll;
9891 * This field specifies legacy L2 doorbell size in KBytes. Drivers should use
9892 * this value to find out the doorbell page offset from the BAR.
9894 uint16_t legacy_l2_db_size_kb;
9897 * This field specifies the source virtual interface of the function being
9898 * queried. Drivers can use this to program svif field in the L2 context
9901 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
9902 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
9903 /* This field specifies whether svif is valid or not */
9904 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
9905 uint8_t unused_2[7];
9907 * This field is used in Output records to indicate that the output
9908 * is completely written to RAM. This field should be read as '1'
9909 * to indicate that the output has been completely written.
9910 * When writing a command completion or response to an internal processor,
9911 * the order of writes has to be such that this field is written last.
9921 /* hwrm_func_cfg_input (size:768b/96B) */
9922 struct hwrm_func_cfg_input {
9923 /* The HWRM command request type. */
9926 * The completion ring to send the completion event on. This should
9927 * be the NQ ID returned from the `nq_alloc` HWRM command.
9931 * The sequence ID is used by the driver for tracking multiple
9932 * commands. This ID is treated as opaque data by the firmware and
9933 * the value is returned in the `hwrm_resp_hdr` upon completion.
9937 * The target ID of the command:
9938 * * 0x0-0xFFF8 - The function ID
9939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
9940 * * 0xFFFD - Reserved for user-space HWRM interface
9945 * A physical address pointer pointing to a host buffer that the
9946 * command's response data will be written. This can be either a host
9947 * physical address (HPA) or a guest physical address (GPA) and must
9948 * point to a physically contiguous block of memory.
9952 * Function ID of the function that is being
9954 * If set to 0xFF... (All Fs), then the the configuration is
9955 * for the requesting function.
9959 * This field specifies how many NQs will be reserved for the PF.
9960 * Remaining NQs that belong to the PF become available for VFs.
9961 * Once a PF has created VFs, it cannot change how many NQs are
9962 * reserved for itself (since the NQs must be contiguous in HW).
9967 * When this bit is '1', the function is disabled with
9968 * source MAC address check.
9969 * This is an anti-spoofing check. If this flag is set,
9970 * then the function shall be configured to disallow
9971 * transmission of frames with the source MAC address that
9972 * is configured for this function.
9974 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
9977 * When this bit is '1', the function is enabled with
9978 * source MAC address check.
9979 * This is an anti-spoofing check. If this flag is set,
9980 * then the function shall be configured to allow
9981 * transmission of frames with the source MAC address that
9982 * is configured for this function.
9984 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
9987 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
9989 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
9991 * Standard TX Ring mode is used for the allocation of TX ring
9992 * and underlying scheduling resources that allow bandwidth
9993 * reservation and limit settings on the queried function.
9994 * If set to 1, then standard TX ring mode is requested to be
9995 * enabled on the function being configured.
9997 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
10000 * Standard TX Ring mode is used for the allocation of TX ring
10001 * and underlying scheduling resources that allow bandwidth
10002 * reservation and limit settings on the queried function.
10003 * If set to 1, then the standard TX ring mode is requested to
10004 * be disabled on the function being configured. In this extended
10005 * TX ring resource mode, the minimum and maximum bandwidth settings
10006 * are not supported to allow the allocation of TX rings to
10007 * span multiple scheduler nodes.
10009 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
10012 * If this bit is set, virtual mac address configured
10013 * in this command will be persistent over warm boot.
10015 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
10018 * This bit only applies to the VF. If this bit is set, the statistic
10019 * context counters will not be cleared when the statistic context is freed
10020 * or a function reset is called on VF. This bit will be cleared when the PF
10021 * is unloaded or a function reset is called on the PF.
10023 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
10026 * This bit requests that the firmware test to see if all the assets
10027 * requested in this command (i.e. number of TX rings) are available.
10028 * The firmware will return an error if the requested assets are
10029 * not available. The firwmare will NOT reserve the assets if they
10032 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
10035 * This bit requests that the firmware test to see if all the assets
10036 * requested in this command (i.e. number of RX rings) are available.
10037 * The firmware will return an error if the requested assets are
10038 * not available. The firwmare will NOT reserve the assets if they
10041 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
10044 * This bit requests that the firmware test to see if all the assets
10045 * requested in this command (i.e. number of CMPL rings) are available.
10046 * The firmware will return an error if the requested assets are
10047 * not available. The firwmare will NOT reserve the assets if they
10050 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
10053 * This bit requests that the firmware test to see if all the assets
10054 * requested in this command (i.e. number of RSS ctx) are available.
10055 * The firmware will return an error if the requested assets are
10056 * not available. The firwmare will NOT reserve the assets if they
10059 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
10062 * This bit requests that the firmware test to see if all the assets
10063 * requested in this command (i.e. number of ring groups) are available.
10064 * The firmware will return an error if the requested assets are
10065 * not available. The firwmare will NOT reserve the assets if they
10068 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
10071 * This bit requests that the firmware test to see if all the assets
10072 * requested in this command (i.e. number of stat ctx) are available.
10073 * The firmware will return an error if the requested assets are
10074 * not available. The firwmare will NOT reserve the assets if they
10077 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
10080 * This bit requests that the firmware test to see if all the assets
10081 * requested in this command (i.e. number of VNICs) are available.
10082 * The firmware will return an error if the requested assets are
10083 * not available. The firwmare will NOT reserve the assets if they
10086 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
10089 * This bit requests that the firmware test to see if all the assets
10090 * requested in this command (i.e. number of L2 ctx) are available.
10091 * The firmware will return an error if the requested assets are
10092 * not available. The firwmare will NOT reserve the assets if they
10095 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
10098 * This configuration change can be initiated by a PF driver. This
10099 * configuration request shall be targeted to a VF. From local host
10100 * resident HWRM clients, only the parent PF driver shall be allowed
10101 * to initiate this change on one of its children VFs. If this bit is
10102 * set to 1, then the VF that is being configured is requested to be
10105 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
10108 * When this bit it set, even if PF reserved pool size is zero,
10109 * FW will allow driver to create TX rings in ring alloc,
10110 * by reserving TX ring, S3 node dynamically.
10112 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
10115 * This bit requests that the firmware test to see if all the assets
10116 * requested in this command (i.e. number of NQ rings) are available.
10117 * The firmware will return an error if the requested assets are
10118 * not available. The firwmare will NOT reserve the assets if they
10121 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
10124 * This configuration change can be initiated by a PF driver. This
10125 * configuration request shall be targeted to a VF. From local host
10126 * resident HWRM clients, only the parent PF driver shall be allowed
10127 * to initiate this change on one of its children VFs. If this bit is
10128 * set to 1, then the VF that is being configured is requested to be
10131 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
10132 UINT32_C(0x1000000)
10134 * This bit is used by preboot drivers on a PF that require access
10135 * to the legacy L2 ring model and legacy 32b doorbells. This
10136 * feature is not allowed on VFs and is only relevant for devices
10137 * that require a context backing store.
10139 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \
10140 UINT32_C(0x2000000)
10142 * If this bit is set to 0, then the interface does not support hot
10143 * reset capability which it advertised with the hot_reset_support
10144 * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this
10145 * flag to 0, adapter cannot do the hot reset. In this state, if the
10146 * firmware receives a hot reset request, firmware must fail the
10147 * request. If this bit is set to 1, then interface is renabling the
10148 * hot reset capability.
10150 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \
10151 UINT32_C(0x4000000)
10153 * If this bit is set to 1, the PF driver is requesting FW
10154 * to enable PPP TX PUSH feature on all the TX rings specified in
10155 * the num_tx_rings field. By default, the PPP TX push feature is
10156 * disabled for all the TX rings of the function. This flag is
10157 * ignored if num_tx_rings field is not specified or the function
10158 * doesn't support PPP tx push feature.
10160 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE \
10161 UINT32_C(0x8000000)
10164 * This bit must be '1' for the mtu field to be
10167 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
10170 * This bit must be '1' for the mru field to be
10173 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
10176 * This bit must be '1' for the num_rsscos_ctxs field to be
10179 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
10182 * This bit must be '1' for the num_cmpl_rings field to be
10185 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
10188 * This bit must be '1' for the num_tx_rings field to be
10191 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
10194 * This bit must be '1' for the num_rx_rings field to be
10197 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
10200 * This bit must be '1' for the num_l2_ctxs field to be
10203 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
10206 * This bit must be '1' for the num_vnics field to be
10209 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
10212 * This bit must be '1' for the num_stat_ctxs field to be
10215 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
10218 * This bit must be '1' for the dflt_mac_addr field to be
10221 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
10224 * This bit must be '1' for the dflt_vlan field to be
10227 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
10230 * This bit must be '1' for the dflt_ip_addr field to be
10233 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
10236 * This bit must be '1' for the min_bw field to be
10239 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
10242 * This bit must be '1' for the max_bw field to be
10245 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
10248 * This bit must be '1' for the async_event_cr field to be
10251 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
10254 * This bit must be '1' for the vlan_antispoof_mode field to be
10257 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
10260 * This bit must be '1' for the allowed_vlan_pris field to be
10263 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
10266 * This bit must be '1' for the evb_mode field to be
10269 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
10272 * This bit must be '1' for the num_mcast_filters field to be
10275 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
10278 * This bit must be '1' for the num_hw_ring_grps field to be
10281 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
10284 * This bit must be '1' for the cache_linesize field to be
10287 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
10290 * This bit must be '1' for the num_msix field to be
10293 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
10296 * This bit must be '1' for the link admin state field to be
10299 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \
10302 * This bit must be '1' for the hot_reset_if_en_dis field to be
10305 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \
10308 * This bit must be '1' for the sq_id field to be
10311 #define HWRM_FUNC_CFG_INPUT_ENABLES_SQ_ID \
10312 UINT32_C(0x1000000)
10314 * The maximum transmission unit of the function.
10315 * The HWRM should make sure that the mtu of
10316 * the function does not exceed the mtu of the physical
10317 * port that this function is associated with.
10319 * In addition to configuring mtu per function, it is
10320 * possible to configure mtu per transmit ring.
10321 * By default, the mtu of each transmit ring associated
10322 * with a function is equal to the mtu of the function.
10323 * The HWRM should make sure that the mtu of each transmit
10324 * ring that is assigned to a function has a valid mtu.
10328 * The maximum receive unit of the function.
10329 * The HWRM should make sure that the mru of
10330 * the function does not exceed the mru of the physical
10331 * port that this function is associated with.
10333 * In addition to configuring mru per function, it is
10334 * possible to configure mru per vnic.
10335 * By default, the mru of each vnic associated
10336 * with a function is equal to the mru of the function.
10337 * The HWRM should make sure that the mru of each vnic
10338 * that is assigned to a function has a valid mru.
10342 * The number of RSS/COS contexts requested for the
10345 uint16_t num_rsscos_ctxs;
10347 * The number of completion rings requested for the
10348 * function. This does not include the rings allocated
10349 * to any children functions if any.
10351 uint16_t num_cmpl_rings;
10353 * The number of transmit rings requested for the function.
10354 * This does not include the rings allocated to any
10355 * children functions if any.
10357 uint16_t num_tx_rings;
10359 * The number of receive rings requested for the function.
10360 * This does not include the rings allocated
10361 * to any children functions if any.
10363 uint16_t num_rx_rings;
10364 /* The requested number of L2 contexts for the function. */
10365 uint16_t num_l2_ctxs;
10366 /* The requested number of vnics for the function. */
10367 uint16_t num_vnics;
10368 /* The requested number of statistic contexts for the function. */
10369 uint16_t num_stat_ctxs;
10371 * The number of HW ring groups that should
10372 * be reserved for this function.
10374 uint16_t num_hw_ring_grps;
10375 /* The default MAC address for the function being configured. */
10376 uint8_t dflt_mac_addr[6];
10378 * The default VLAN for the function being configured.
10379 * This field's format is same as 802.1Q Tag's
10380 * Tag Control Information (TCI) format that includes both
10381 * Priority Code Point (PCP) and VLAN Identifier (VID).
10383 uint16_t dflt_vlan;
10385 * The default IP address for the function being configured.
10386 * This address is only used in enabling source property check.
10388 uint32_t dflt_ip_addr[4];
10390 * Minimum BW allocated for this function.
10391 * The HWRM will translate this value into byte counter and
10392 * time interval used for the scheduler inside the device.
10395 /* The bandwidth value. */
10396 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
10397 UINT32_C(0xfffffff)
10398 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
10399 /* The granularity of the value (bits or bytes). */
10400 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
10401 UINT32_C(0x10000000)
10402 /* Value is in bits. */
10403 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
10404 (UINT32_C(0x0) << 28)
10405 /* Value is in bytes. */
10406 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
10407 (UINT32_C(0x1) << 28)
10408 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
10409 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
10410 /* bw_value_unit is 3 b */
10411 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
10412 UINT32_C(0xe0000000)
10413 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
10414 /* Value is in Mb or MB (base 10). */
10415 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
10416 (UINT32_C(0x0) << 29)
10417 /* Value is in Kb or KB (base 10). */
10418 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
10419 (UINT32_C(0x2) << 29)
10420 /* Value is in bits or bytes. */
10421 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
10422 (UINT32_C(0x4) << 29)
10423 /* Value is in Gb or GB (base 10). */
10424 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
10425 (UINT32_C(0x6) << 29)
10426 /* Value is in 1/100th of a percentage of total bandwidth. */
10427 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
10428 (UINT32_C(0x1) << 29)
10430 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
10431 (UINT32_C(0x7) << 29)
10432 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
10433 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
10435 * Maximum BW allocated for this function.
10436 * The HWRM will translate this value into byte counter and
10437 * time interval used for the scheduler inside the device.
10440 /* The bandwidth value. */
10441 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
10442 UINT32_C(0xfffffff)
10443 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
10444 /* The granularity of the value (bits or bytes). */
10445 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
10446 UINT32_C(0x10000000)
10447 /* Value is in bits. */
10448 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
10449 (UINT32_C(0x0) << 28)
10450 /* Value is in bytes. */
10451 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
10452 (UINT32_C(0x1) << 28)
10453 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
10454 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
10455 /* bw_value_unit is 3 b */
10456 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
10457 UINT32_C(0xe0000000)
10458 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
10459 /* Value is in Mb or MB (base 10). */
10460 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
10461 (UINT32_C(0x0) << 29)
10462 /* Value is in Kb or KB (base 10). */
10463 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
10464 (UINT32_C(0x2) << 29)
10465 /* Value is in bits or bytes. */
10466 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
10467 (UINT32_C(0x4) << 29)
10468 /* Value is in Gb or GB (base 10). */
10469 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
10470 (UINT32_C(0x6) << 29)
10471 /* Value is in 1/100th of a percentage of total bandwidth. */
10472 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
10473 (UINT32_C(0x1) << 29)
10475 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
10476 (UINT32_C(0x7) << 29)
10477 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
10478 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
10480 * ID of the target completion ring for receiving asynchronous
10481 * event completions. If this field is not valid, then the
10482 * HWRM shall use the default completion ring of the function
10483 * that is being configured as the target completion ring for
10484 * providing any asynchronous event completions for that
10486 * If this field is valid, then the HWRM shall use the
10487 * completion ring identified by this ID as the target
10488 * completion ring for providing any asynchronous event
10489 * completions for the function that is being configured.
10491 uint16_t async_event_cr;
10492 /* VLAN Anti-spoofing mode. */
10493 uint8_t vlan_antispoof_mode;
10494 /* No VLAN anti-spoofing checks are enabled */
10495 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
10497 /* Validate VLAN against the configured VLAN(s) */
10498 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
10500 /* Insert VLAN if it does not exist, otherwise discard */
10501 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
10503 /* Insert VLAN if it does not exist, override VLAN if it exists */
10504 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
10506 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
10507 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
10509 * This bit field defines VLAN PRIs that are allowed on
10511 * If nth bit is set, then VLAN PRI n is allowed on this
10514 uint8_t allowed_vlan_pris;
10516 * The HWRM shall allow a PF driver to change EVB mode for the
10517 * partition it belongs to.
10518 * The HWRM shall not allow a VF driver to change the EVB mode.
10519 * The HWRM shall take into account the switching of EVB mode
10520 * from one to another and reconfigure hardware resources as
10522 * The switching from VEB to VEPA mode requires
10523 * the disabling of the loopback traffic. Additionally,
10524 * source knock outs are handled differently in VEB and VEPA
10528 /* No Edge Virtual Bridging (EVB) */
10529 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
10530 /* Virtual Ethernet Bridge (VEB) */
10531 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
10532 /* Virtual Ethernet Port Aggregator (VEPA) */
10533 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
10534 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
10535 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
10538 * This value indicates the PCIE device cache line size.
10539 * The cache line size allows the DMA writes to terminate and
10540 * start at the cache boundary.
10542 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
10544 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
10545 /* Cache Line Size 64 bytes */
10546 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
10548 /* Cache Line Size 128 bytes */
10549 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
10551 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
10552 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
10553 /* This value is the virtual link admin state setting. */
10554 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \
10556 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2
10557 /* Admin state is forced down. */
10558 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \
10559 (UINT32_C(0x0) << 2)
10560 /* Admin state is forced up. */
10561 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \
10562 (UINT32_C(0x1) << 2)
10563 /* Admin state is in auto mode - is to follow the physical link state. */
10564 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \
10565 (UINT32_C(0x2) << 2)
10566 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \
10567 HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO
10568 /* Reserved for future. */
10569 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
10571 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4
10573 * The number of multicast filters that should
10574 * be reserved for this function on the RX side.
10576 uint16_t num_mcast_filters;
10577 /* Used by a PF driver to associate a SQ with a VF. */
10579 uint8_t unused_0[6];
10582 /* hwrm_func_cfg_output (size:128b/16B) */
10583 struct hwrm_func_cfg_output {
10584 /* The specific error status for the command. */
10585 uint16_t error_code;
10586 /* The HWRM command request type. */
10588 /* The sequence ID from the original command. */
10590 /* The length of the response data in number of bytes. */
10592 uint8_t unused_0[7];
10594 * This field is used in Output records to indicate that the output
10595 * is completely written to RAM. This field should be read as '1'
10596 * to indicate that the output has been completely written.
10597 * When writing a command completion or response to an internal processor,
10598 * the order of writes has to be such that this field is written last.
10603 /********************
10604 * hwrm_func_qstats *
10605 ********************/
10608 /* hwrm_func_qstats_input (size:192b/24B) */
10609 struct hwrm_func_qstats_input {
10610 /* The HWRM command request type. */
10613 * The completion ring to send the completion event on. This should
10614 * be the NQ ID returned from the `nq_alloc` HWRM command.
10616 uint16_t cmpl_ring;
10618 * The sequence ID is used by the driver for tracking multiple
10619 * commands. This ID is treated as opaque data by the firmware and
10620 * the value is returned in the `hwrm_resp_hdr` upon completion.
10624 * The target ID of the command:
10625 * * 0x0-0xFFF8 - The function ID
10626 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10627 * * 0xFFFD - Reserved for user-space HWRM interface
10630 uint16_t target_id;
10632 * A physical address pointer pointing to a host buffer that the
10633 * command's response data will be written. This can be either a host
10634 * physical address (HPA) or a guest physical address (GPA) and must
10635 * point to a physically contiguous block of memory.
10637 uint64_t resp_addr;
10639 * Function ID of the function that is being queried.
10640 * 0xFF... (All Fs) if the query is for the requesting
10642 * A privileged PF can query for other function's statistics.
10645 /* This flags indicates the type of statistics request. */
10647 /* This value is not used to avoid backward compatibility issues. */
10648 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10650 * flags should be set to 1 when request is for only RoCE statistics.
10651 * This will be honored only if the caller_fid is a privileged PF.
10652 * In all other cases FID and caller_fid should be the same.
10654 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10656 * flags should be set to 2 when request is for the counter mask,
10657 * representing the width of each of the stats counters, rather
10658 * than counters themselves.
10660 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10661 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \
10662 HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK
10663 uint8_t unused_0[5];
10666 /* hwrm_func_qstats_output (size:1408b/176B) */
10667 struct hwrm_func_qstats_output {
10668 /* The specific error status for the command. */
10669 uint16_t error_code;
10670 /* The HWRM command request type. */
10672 /* The sequence ID from the original command. */
10674 /* The length of the response data in number of bytes. */
10676 /* Number of transmitted unicast packets on the function. */
10677 uint64_t tx_ucast_pkts;
10678 /* Number of transmitted multicast packets on the function. */
10679 uint64_t tx_mcast_pkts;
10680 /* Number of transmitted broadcast packets on the function. */
10681 uint64_t tx_bcast_pkts;
10683 * Number of transmitted packets that were discarded due to
10684 * internal NIC resource problems. For transmit, this
10685 * can only happen if TMP is configured to allow dropping
10686 * in HOL blocking conditions, which is not a normal
10689 uint64_t tx_discard_pkts;
10691 * Number of dropped packets on transmit path on the function.
10692 * These are packets that have been marked for drop by
10693 * the TE CFA block or are packets that exceeded the
10694 * transmit MTU limit for the function.
10696 uint64_t tx_drop_pkts;
10697 /* Number of transmitted bytes for unicast traffic on the function. */
10698 uint64_t tx_ucast_bytes;
10699 /* Number of transmitted bytes for multicast traffic on the function. */
10700 uint64_t tx_mcast_bytes;
10701 /* Number of transmitted bytes for broadcast traffic on the function. */
10702 uint64_t tx_bcast_bytes;
10703 /* Number of received unicast packets on the function. */
10704 uint64_t rx_ucast_pkts;
10705 /* Number of received multicast packets on the function. */
10706 uint64_t rx_mcast_pkts;
10707 /* Number of received broadcast packets on the function. */
10708 uint64_t rx_bcast_pkts;
10710 * Number of received packets that were discarded on the function
10711 * due to resource limitations. This can happen for 3 reasons.
10712 * # The BD used for the packet has a bad format.
10713 * # There were no BDs available in the ring for the packet.
10714 * # There were no BDs available on-chip for the packet.
10716 uint64_t rx_discard_pkts;
10718 * Number of dropped packets on received path on the function.
10719 * These are packets that have been marked for drop by the
10722 uint64_t rx_drop_pkts;
10723 /* Number of received bytes for unicast traffic on the function. */
10724 uint64_t rx_ucast_bytes;
10725 /* Number of received bytes for multicast traffic on the function. */
10726 uint64_t rx_mcast_bytes;
10727 /* Number of received bytes for broadcast traffic on the function. */
10728 uint64_t rx_bcast_bytes;
10729 /* Number of aggregated unicast packets on the function. */
10730 uint64_t rx_agg_pkts;
10731 /* Number of aggregated unicast bytes on the function. */
10732 uint64_t rx_agg_bytes;
10733 /* Number of aggregation events on the function. */
10734 uint64_t rx_agg_events;
10735 /* Number of aborted aggregations on the function. */
10736 uint64_t rx_agg_aborts;
10737 uint8_t unused_0[7];
10739 * This field is used in Output records to indicate that the output
10740 * is completely written to RAM. This field should be read as '1'
10741 * to indicate that the output has been completely written.
10742 * When writing a command completion or response to an internal processor,
10743 * the order of writes has to be such that this field is written last.
10748 /************************
10749 * hwrm_func_qstats_ext *
10750 ************************/
10753 /* hwrm_func_qstats_ext_input (size:256b/32B) */
10754 struct hwrm_func_qstats_ext_input {
10755 /* The HWRM command request type. */
10758 * The completion ring to send the completion event on. This should
10759 * be the NQ ID returned from the `nq_alloc` HWRM command.
10761 uint16_t cmpl_ring;
10763 * The sequence ID is used by the driver for tracking multiple
10764 * commands. This ID is treated as opaque data by the firmware and
10765 * the value is returned in the `hwrm_resp_hdr` upon completion.
10769 * The target ID of the command:
10770 * * 0x0-0xFFF8 - The function ID
10771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10772 * * 0xFFFD - Reserved for user-space HWRM interface
10775 uint16_t target_id;
10777 * A physical address pointer pointing to a host buffer that the
10778 * command's response data will be written. This can be either a host
10779 * physical address (HPA) or a guest physical address (GPA) and must
10780 * point to a physically contiguous block of memory.
10782 uint64_t resp_addr;
10784 * Function ID of the function that is being queried.
10785 * 0xFF... (All Fs) if the query is for the requesting
10787 * A privileged PF can query for other function's statistics.
10790 /* This flags indicates the type of statistics request. */
10792 /* This value is not used to avoid backward compatibility issues. */
10793 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
10795 * flags should be set to 1 when request is for only RoCE statistics.
10796 * This will be honored only if the caller_fid is a privileged PF.
10797 * In all other cases FID and caller_fid should be the same.
10799 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
10801 * flags should be set to 2 when request is for the counter mask
10802 * representing the width of each of the stats counters, rather
10803 * than counters themselves.
10805 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
10806 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \
10807 HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
10808 uint8_t unused_0[1];
10811 * This bit must be '1' for the sq_id and traffic_class fields to be
10814 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SQ_ID UINT32_C(0x1)
10815 /* Specifies the SQ for which to gather statistics */
10818 * Specifies the traffic class for which to gather statistics. Valid
10819 * values are 0 through (max_configurable_queues - 1), where
10820 * max_configurable_queues is in the response of HWRM_QUEUE_QPORTCFG
10822 uint16_t traffic_class;
10823 uint8_t unused_1[4];
10826 /* hwrm_func_qstats_ext_output (size:1472b/184B) */
10827 struct hwrm_func_qstats_ext_output {
10828 /* The specific error status for the command. */
10829 uint16_t error_code;
10830 /* The HWRM command request type. */
10832 /* The sequence ID from the original command. */
10834 /* The length of the response data in number of bytes. */
10836 /* Number of received unicast packets */
10837 uint64_t rx_ucast_pkts;
10838 /* Number of received multicast packets */
10839 uint64_t rx_mcast_pkts;
10840 /* Number of received broadcast packets */
10841 uint64_t rx_bcast_pkts;
10842 /* Number of discarded packets on received path */
10843 uint64_t rx_discard_pkts;
10844 /* Number of packets on receive path with error */
10845 uint64_t rx_error_pkts;
10846 /* Number of received bytes for unicast traffic */
10847 uint64_t rx_ucast_bytes;
10848 /* Number of received bytes for multicast traffic */
10849 uint64_t rx_mcast_bytes;
10850 /* Number of received bytes for broadcast traffic */
10851 uint64_t rx_bcast_bytes;
10852 /* Number of transmitted unicast packets */
10853 uint64_t tx_ucast_pkts;
10854 /* Number of transmitted multicast packets */
10855 uint64_t tx_mcast_pkts;
10856 /* Number of transmitted broadcast packets */
10857 uint64_t tx_bcast_pkts;
10858 /* Number of packets on transmit path with error */
10859 uint64_t tx_error_pkts;
10860 /* Number of discarded packets on transmit path */
10861 uint64_t tx_discard_pkts;
10862 /* Number of transmitted bytes for unicast traffic */
10863 uint64_t tx_ucast_bytes;
10864 /* Number of transmitted bytes for multicast traffic */
10865 uint64_t tx_mcast_bytes;
10866 /* Number of transmitted bytes for broadcast traffic */
10867 uint64_t tx_bcast_bytes;
10868 /* Number of TPA eligible packets */
10869 uint64_t rx_tpa_eligible_pkt;
10870 /* Number of TPA eligible bytes */
10871 uint64_t rx_tpa_eligible_bytes;
10872 /* Number of TPA packets */
10873 uint64_t rx_tpa_pkt;
10874 /* Number of TPA bytes */
10875 uint64_t rx_tpa_bytes;
10876 /* Number of TPA errors */
10877 uint64_t rx_tpa_errors;
10878 uint8_t unused_0[7];
10880 * This field is used in Output records to indicate that the output
10881 * is completely written to RAM. This field should be read as '1'
10882 * to indicate that the output has been completely written.
10883 * When writing a command completion or response to an internal processor,
10884 * the order of writes has to be such that this field is written last.
10889 /***********************
10890 * hwrm_func_clr_stats *
10891 ***********************/
10894 /* hwrm_func_clr_stats_input (size:192b/24B) */
10895 struct hwrm_func_clr_stats_input {
10896 /* The HWRM command request type. */
10899 * The completion ring to send the completion event on. This should
10900 * be the NQ ID returned from the `nq_alloc` HWRM command.
10902 uint16_t cmpl_ring;
10904 * The sequence ID is used by the driver for tracking multiple
10905 * commands. This ID is treated as opaque data by the firmware and
10906 * the value is returned in the `hwrm_resp_hdr` upon completion.
10910 * The target ID of the command:
10911 * * 0x0-0xFFF8 - The function ID
10912 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10913 * * 0xFFFD - Reserved for user-space HWRM interface
10916 uint16_t target_id;
10918 * A physical address pointer pointing to a host buffer that the
10919 * command's response data will be written. This can be either a host
10920 * physical address (HPA) or a guest physical address (GPA) and must
10921 * point to a physically contiguous block of memory.
10923 uint64_t resp_addr;
10925 * Function ID of the function.
10926 * 0xFF... (All Fs) if the query is for the requesting
10930 uint8_t unused_0[6];
10933 /* hwrm_func_clr_stats_output (size:128b/16B) */
10934 struct hwrm_func_clr_stats_output {
10935 /* The specific error status for the command. */
10936 uint16_t error_code;
10937 /* The HWRM command request type. */
10939 /* The sequence ID from the original command. */
10941 /* The length of the response data in number of bytes. */
10943 uint8_t unused_0[7];
10945 * This field is used in Output records to indicate that the output
10946 * is completely written to RAM. This field should be read as '1'
10947 * to indicate that the output has been completely written.
10948 * When writing a command completion or response to an internal processor,
10949 * the order of writes has to be such that this field is written last.
10954 /**************************
10955 * hwrm_func_vf_resc_free *
10956 **************************/
10959 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
10960 struct hwrm_func_vf_resc_free_input {
10961 /* The HWRM command request type. */
10964 * The completion ring to send the completion event on. This should
10965 * be the NQ ID returned from the `nq_alloc` HWRM command.
10967 uint16_t cmpl_ring;
10969 * The sequence ID is used by the driver for tracking multiple
10970 * commands. This ID is treated as opaque data by the firmware and
10971 * the value is returned in the `hwrm_resp_hdr` upon completion.
10975 * The target ID of the command:
10976 * * 0x0-0xFFF8 - The function ID
10977 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
10978 * * 0xFFFD - Reserved for user-space HWRM interface
10981 uint16_t target_id;
10983 * A physical address pointer pointing to a host buffer that the
10984 * command's response data will be written. This can be either a host
10985 * physical address (HPA) or a guest physical address (GPA) and must
10986 * point to a physically contiguous block of memory.
10988 uint64_t resp_addr;
10990 * This value is used to identify a Virtual Function (VF).
10991 * The scope of VF ID is local within a PF.
10994 uint8_t unused_0[6];
10997 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
10998 struct hwrm_func_vf_resc_free_output {
10999 /* The specific error status for the command. */
11000 uint16_t error_code;
11001 /* The HWRM command request type. */
11003 /* The sequence ID from the original command. */
11005 /* The length of the response data in number of bytes. */
11007 uint8_t unused_0[7];
11009 * This field is used in Output records to indicate that the output
11010 * is completely written to RAM. This field should be read as '1'
11011 * to indicate that the output has been completely written.
11012 * When writing a command completion or response to an internal processor,
11013 * the order of writes has to be such that this field is written last.
11018 /**********************
11019 * hwrm_func_drv_rgtr *
11020 **********************/
11023 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
11024 struct hwrm_func_drv_rgtr_input {
11025 /* The HWRM command request type. */
11028 * The completion ring to send the completion event on. This should
11029 * be the NQ ID returned from the `nq_alloc` HWRM command.
11031 uint16_t cmpl_ring;
11033 * The sequence ID is used by the driver for tracking multiple
11034 * commands. This ID is treated as opaque data by the firmware and
11035 * the value is returned in the `hwrm_resp_hdr` upon completion.
11039 * The target ID of the command:
11040 * * 0x0-0xFFF8 - The function ID
11041 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11042 * * 0xFFFD - Reserved for user-space HWRM interface
11045 uint16_t target_id;
11047 * A physical address pointer pointing to a host buffer that the
11048 * command's response data will be written. This can be either a host
11049 * physical address (HPA) or a guest physical address (GPA) and must
11050 * point to a physically contiguous block of memory.
11052 uint64_t resp_addr;
11055 * When this bit is '1', the function driver is requesting
11056 * all requests from its children VF drivers to be
11057 * forwarded to itself.
11058 * This flag can only be set by the PF driver.
11059 * If a VF driver sets this flag, it should be ignored
11062 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \
11065 * When this bit is '1', the function is requesting none of
11066 * the requests from its children VF drivers to be
11067 * forwarded to itself.
11068 * This flag can only be set by the PF driver.
11069 * If a VF driver sets this flag, it should be ignored
11072 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \
11075 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
11076 * fields shall be ignored and ver_maj, ver_min, ver_upd
11077 * and ver_patch shall be used for the driver version information.
11078 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
11079 * fields shall be used for the driver version information and
11080 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
11082 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \
11085 * When this bit is '1', the function is indicating support of
11086 * 64bit flow handle. The firmware that only supports 64bit flow
11087 * handle should check this bit before allowing processing of
11088 * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware
11089 * with 64bit flow handle support can only be compatible with drivers
11090 * that support 64bit flow handle. The legacy drivers that don't support
11091 * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when
11092 * running with new firmware that only supports 64bit flow handle. The new
11093 * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED
11094 * status to the legacy driver when encounters these commands.
11096 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
11099 * When this bit is '1', the function is indicating support of
11100 * Hot Reset. The driver interface will destroy the resources,
11101 * unregister the function and register again up on receiving
11102 * the RESET_NOTIFY Async notification from the core firmware.
11103 * The core firmware will this use flag and trigger the Hot Reset
11104 * process only if all the registered driver instances are capable
11107 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
11110 * When this bit is 1, the function is indicating the support of the
11111 * error recovery capability. Error recovery support will be used by
11112 * firmware only if all the driver instances support error recovery
11113 * process. By setting this bit, driver is indicating support for
11114 * corresponding async event completion message. These will be
11115 * delivered to the driver even if they did not register for it.
11116 * If supported, after receiving reset notify async event with fatal
11117 * flag set in event data1, then all the drivers have to tear down
11118 * their resources without sending any HWRM commands to FW.
11120 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
11123 * When this bit is 1, the function is indicating the support of the
11124 * Master capability. The Firmware will use this capability to select the
11125 * Master function. The master function will be used to initiate
11126 * designated functionality like error recovery etc… If none of the
11127 * registered PF’s or trusted VF’s indicate this support, then
11128 * firmware will select the 1st registered PF as Master capable instance.
11130 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \
11134 * This bit must be '1' for the os_type field to be
11137 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
11140 * This bit must be '1' for the ver field to be
11143 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
11146 * This bit must be '1' for the timestamp field to be
11149 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
11152 * This bit must be '1' for the vf_req_fwd field to be
11155 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
11158 * This bit must be '1' for the async_event_fwd field to be
11161 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
11163 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11166 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11167 /* Other OS not listed below. */
11168 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
11170 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11172 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11174 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11176 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
11178 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11179 /* VMware ESXi OS. */
11180 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
11181 /* Microsoft Windows 8 64-bit OS. */
11182 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11183 /* Microsoft Windows Server 2012 R2 OS. */
11184 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11186 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11187 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
11188 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
11189 /* This is the 8bit major version of the driver. */
11190 uint8_t ver_maj_8b;
11191 /* This is the 8bit minor version of the driver. */
11192 uint8_t ver_min_8b;
11193 /* This is the 8bit update version of the driver. */
11194 uint8_t ver_upd_8b;
11195 uint8_t unused_0[3];
11197 * This is a 32-bit timestamp provided by the driver for
11199 * The timestamp is in multiples of 1ms.
11201 uint32_t timestamp;
11202 uint8_t unused_1[4];
11204 * This is a 256-bit bit mask provided by the PF driver for
11205 * letting the HWRM know what commands issued by the VF driver
11206 * to the HWRM should be forwarded to the PF driver.
11207 * Nth bit refers to the Nth req_type.
11209 * Setting Nth bit to 1 indicates that requests from the
11210 * VF driver with req_type equal to N shall be forwarded to
11211 * the parent PF driver.
11213 * This field is not valid for the VF driver.
11215 uint32_t vf_req_fwd[8];
11217 * This is a 256-bit bit mask provided by the function driver
11218 * (PF or VF driver) to indicate the list of asynchronous event
11219 * completions to be forwarded.
11221 * Nth bit refers to the Nth event_id.
11223 * Setting Nth bit to 1 by the function driver shall result in
11224 * the HWRM forwarding asynchronous event completion with
11225 * event_id equal to N.
11227 * If all bits are set to 0 (value of 0), then the HWRM shall
11228 * not forward any asynchronous event completion to this
11231 uint32_t async_event_fwd[8];
11232 /* This is the 16bit major version of the driver. */
11234 /* This is the 16bit minor version of the driver. */
11236 /* This is the 16bit update version of the driver. */
11238 /* This is the 16bit patch version of the driver. */
11239 uint16_t ver_patch;
11242 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
11243 struct hwrm_func_drv_rgtr_output {
11244 /* The specific error status for the command. */
11245 uint16_t error_code;
11246 /* The HWRM command request type. */
11248 /* The sequence ID from the original command. */
11250 /* The length of the response data in number of bytes. */
11254 * When this bit is '1', it indicates that the
11255 * HWRM_FUNC_DRV_IF_CHANGE call is supported.
11257 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \
11259 uint8_t unused_0[3];
11261 * This field is used in Output records to indicate that the output
11262 * is completely written to RAM. This field should be read as '1'
11263 * to indicate that the output has been completely written.
11264 * When writing a command completion or response to an internal processor,
11265 * the order of writes has to be such that this field is written last.
11270 /************************
11271 * hwrm_func_drv_unrgtr *
11272 ************************/
11275 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
11276 struct hwrm_func_drv_unrgtr_input {
11277 /* The HWRM command request type. */
11280 * The completion ring to send the completion event on. This should
11281 * be the NQ ID returned from the `nq_alloc` HWRM command.
11283 uint16_t cmpl_ring;
11285 * The sequence ID is used by the driver for tracking multiple
11286 * commands. This ID is treated as opaque data by the firmware and
11287 * the value is returned in the `hwrm_resp_hdr` upon completion.
11291 * The target ID of the command:
11292 * * 0x0-0xFFF8 - The function ID
11293 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11294 * * 0xFFFD - Reserved for user-space HWRM interface
11297 uint16_t target_id;
11299 * A physical address pointer pointing to a host buffer that the
11300 * command's response data will be written. This can be either a host
11301 * physical address (HPA) or a guest physical address (GPA) and must
11302 * point to a physically contiguous block of memory.
11304 uint64_t resp_addr;
11307 * When this bit is '1', the function driver is notifying
11308 * the HWRM to prepare for the shutdown.
11310 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
11312 uint8_t unused_0[4];
11315 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
11316 struct hwrm_func_drv_unrgtr_output {
11317 /* The specific error status for the command. */
11318 uint16_t error_code;
11319 /* The HWRM command request type. */
11321 /* The sequence ID from the original command. */
11323 /* The length of the response data in number of bytes. */
11325 uint8_t unused_0[7];
11327 * This field is used in Output records to indicate that the output
11328 * is completely written to RAM. This field should be read as '1'
11329 * to indicate that the output has been completely written.
11330 * When writing a command completion or response to an internal processor,
11331 * the order of writes has to be such that this field is written last.
11336 /**********************
11337 * hwrm_func_buf_rgtr *
11338 **********************/
11341 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
11342 struct hwrm_func_buf_rgtr_input {
11343 /* The HWRM command request type. */
11346 * The completion ring to send the completion event on. This should
11347 * be the NQ ID returned from the `nq_alloc` HWRM command.
11349 uint16_t cmpl_ring;
11351 * The sequence ID is used by the driver for tracking multiple
11352 * commands. This ID is treated as opaque data by the firmware and
11353 * the value is returned in the `hwrm_resp_hdr` upon completion.
11357 * The target ID of the command:
11358 * * 0x0-0xFFF8 - The function ID
11359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11360 * * 0xFFFD - Reserved for user-space HWRM interface
11363 uint16_t target_id;
11365 * A physical address pointer pointing to a host buffer that the
11366 * command's response data will be written. This can be either a host
11367 * physical address (HPA) or a guest physical address (GPA) and must
11368 * point to a physically contiguous block of memory.
11370 uint64_t resp_addr;
11373 * This bit must be '1' for the vf_id field to be
11376 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11378 * This bit must be '1' for the err_buf_addr field to be
11381 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
11383 * This value is used to identify a Virtual Function (VF).
11384 * The scope of VF ID is local within a PF.
11388 * This field represents the number of pages used for request
11391 uint16_t req_buf_num_pages;
11393 * This field represents the page size used for request
11396 uint16_t req_buf_page_size;
11398 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
11400 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
11402 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
11404 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
11406 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
11408 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
11410 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
11411 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
11412 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
11413 /* The length of the request buffer per VF in bytes. */
11414 uint16_t req_buf_len;
11415 /* The length of the response buffer in bytes. */
11416 uint16_t resp_buf_len;
11417 uint8_t unused_0[2];
11418 /* This field represents the page address of page #0. */
11419 uint64_t req_buf_page_addr0;
11420 /* This field represents the page address of page #1. */
11421 uint64_t req_buf_page_addr1;
11422 /* This field represents the page address of page #2. */
11423 uint64_t req_buf_page_addr2;
11424 /* This field represents the page address of page #3. */
11425 uint64_t req_buf_page_addr3;
11426 /* This field represents the page address of page #4. */
11427 uint64_t req_buf_page_addr4;
11428 /* This field represents the page address of page #5. */
11429 uint64_t req_buf_page_addr5;
11430 /* This field represents the page address of page #6. */
11431 uint64_t req_buf_page_addr6;
11432 /* This field represents the page address of page #7. */
11433 uint64_t req_buf_page_addr7;
11434 /* This field represents the page address of page #8. */
11435 uint64_t req_buf_page_addr8;
11436 /* This field represents the page address of page #9. */
11437 uint64_t req_buf_page_addr9;
11439 * This field is used to receive the error reporting from
11440 * the chipset. Only applicable for PFs.
11442 uint64_t error_buf_addr;
11444 * This field is used to receive the response forwarded by the
11447 uint64_t resp_buf_addr;
11450 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
11451 struct hwrm_func_buf_rgtr_output {
11452 /* The specific error status for the command. */
11453 uint16_t error_code;
11454 /* The HWRM command request type. */
11456 /* The sequence ID from the original command. */
11458 /* The length of the response data in number of bytes. */
11460 uint8_t unused_0[7];
11462 * This field is used in Output records to indicate that the output
11463 * is completely written to RAM. This field should be read as '1'
11464 * to indicate that the output has been completely written.
11465 * When writing a command completion or response to an internal processor,
11466 * the order of writes has to be such that this field is written last.
11471 /************************
11472 * hwrm_func_buf_unrgtr *
11473 ************************/
11476 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
11477 struct hwrm_func_buf_unrgtr_input {
11478 /* The HWRM command request type. */
11481 * The completion ring to send the completion event on. This should
11482 * be the NQ ID returned from the `nq_alloc` HWRM command.
11484 uint16_t cmpl_ring;
11486 * The sequence ID is used by the driver for tracking multiple
11487 * commands. This ID is treated as opaque data by the firmware and
11488 * the value is returned in the `hwrm_resp_hdr` upon completion.
11492 * The target ID of the command:
11493 * * 0x0-0xFFF8 - The function ID
11494 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11495 * * 0xFFFD - Reserved for user-space HWRM interface
11498 uint16_t target_id;
11500 * A physical address pointer pointing to a host buffer that the
11501 * command's response data will be written. This can be either a host
11502 * physical address (HPA) or a guest physical address (GPA) and must
11503 * point to a physically contiguous block of memory.
11505 uint64_t resp_addr;
11508 * This bit must be '1' for the vf_id field to be
11511 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
11513 * This value is used to identify a Virtual Function (VF).
11514 * The scope of VF ID is local within a PF.
11517 uint8_t unused_0[2];
11520 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
11521 struct hwrm_func_buf_unrgtr_output {
11522 /* The specific error status for the command. */
11523 uint16_t error_code;
11524 /* The HWRM command request type. */
11526 /* The sequence ID from the original command. */
11528 /* The length of the response data in number of bytes. */
11530 uint8_t unused_0[7];
11532 * This field is used in Output records to indicate that the output
11533 * is completely written to RAM. This field should be read as '1'
11534 * to indicate that the output has been completely written.
11535 * When writing a command completion or response to an internal processor,
11536 * the order of writes has to be such that this field is written last.
11541 /**********************
11542 * hwrm_func_drv_qver *
11543 **********************/
11546 /* hwrm_func_drv_qver_input (size:192b/24B) */
11547 struct hwrm_func_drv_qver_input {
11548 /* The HWRM command request type. */
11551 * The completion ring to send the completion event on. This should
11552 * be the NQ ID returned from the `nq_alloc` HWRM command.
11554 uint16_t cmpl_ring;
11556 * The sequence ID is used by the driver for tracking multiple
11557 * commands. This ID is treated as opaque data by the firmware and
11558 * the value is returned in the `hwrm_resp_hdr` upon completion.
11562 * The target ID of the command:
11563 * * 0x0-0xFFF8 - The function ID
11564 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11565 * * 0xFFFD - Reserved for user-space HWRM interface
11568 uint16_t target_id;
11570 * A physical address pointer pointing to a host buffer that the
11571 * command's response data will be written. This can be either a host
11572 * physical address (HPA) or a guest physical address (GPA) and must
11573 * point to a physically contiguous block of memory.
11575 uint64_t resp_addr;
11576 /* Reserved for future use. */
11579 * Function ID of the function that is being queried.
11580 * 0xFF... (All Fs) if the query is for the requesting
11584 uint8_t unused_0[2];
11587 /* hwrm_func_drv_qver_output (size:256b/32B) */
11588 struct hwrm_func_drv_qver_output {
11589 /* The specific error status for the command. */
11590 uint16_t error_code;
11591 /* The HWRM command request type. */
11593 /* The sequence ID from the original command. */
11595 /* The length of the response data in number of bytes. */
11597 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
11600 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
11601 /* Other OS not listed below. */
11602 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
11604 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
11606 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
11608 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
11610 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
11612 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
11613 /* VMware ESXi OS. */
11614 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
11615 /* Microsoft Windows 8 64-bit OS. */
11616 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
11617 /* Microsoft Windows Server 2012 R2 OS. */
11618 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
11620 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
11621 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
11622 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
11623 /* This is the 8bit major version of the driver. */
11624 uint8_t ver_maj_8b;
11625 /* This is the 8bit minor version of the driver. */
11626 uint8_t ver_min_8b;
11627 /* This is the 8bit update version of the driver. */
11628 uint8_t ver_upd_8b;
11629 uint8_t unused_0[3];
11630 /* This is the 16bit major version of the driver. */
11632 /* This is the 16bit minor version of the driver. */
11634 /* This is the 16bit update version of the driver. */
11636 /* This is the 16bit patch version of the driver. */
11637 uint16_t ver_patch;
11638 uint8_t unused_1[7];
11640 * This field is used in Output records to indicate that the output
11641 * is completely written to RAM. This field should be read as '1'
11642 * to indicate that the output has been completely written.
11643 * When writing a command completion or response to an internal processor,
11644 * the order of writes has to be such that this field is written last.
11649 /****************************
11650 * hwrm_func_resource_qcaps *
11651 ****************************/
11654 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
11655 struct hwrm_func_resource_qcaps_input {
11656 /* The HWRM command request type. */
11659 * The completion ring to send the completion event on. This should
11660 * be the NQ ID returned from the `nq_alloc` HWRM command.
11662 uint16_t cmpl_ring;
11664 * The sequence ID is used by the driver for tracking multiple
11665 * commands. This ID is treated as opaque data by the firmware and
11666 * the value is returned in the `hwrm_resp_hdr` upon completion.
11670 * The target ID of the command:
11671 * * 0x0-0xFFF8 - The function ID
11672 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11673 * * 0xFFFD - Reserved for user-space HWRM interface
11676 uint16_t target_id;
11678 * A physical address pointer pointing to a host buffer that the
11679 * command's response data will be written. This can be either a host
11680 * physical address (HPA) or a guest physical address (GPA) and must
11681 * point to a physically contiguous block of memory.
11683 uint64_t resp_addr;
11685 * Function ID of the function that is being queried.
11686 * 0xFF... (All Fs) if the query is for the requesting
11690 uint8_t unused_0[6];
11693 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
11694 struct hwrm_func_resource_qcaps_output {
11695 /* The specific error status for the command. */
11696 uint16_t error_code;
11697 /* The HWRM command request type. */
11699 /* The sequence ID from the original command. */
11701 /* The length of the response data in number of bytes. */
11703 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
11705 /* Maximum guaranteed number of MSI-X vectors supported by function */
11707 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
11708 uint16_t vf_reservation_strategy;
11709 /* The PF driver should evenly divide its remaining resources among all VFs. */
11710 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
11712 /* The PF driver should only reserve minimal resources for each VF. */
11713 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
11716 * The PF driver should not reserve any resources for each VF until the
11717 * the VF interface is brought up.
11719 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
11721 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
11722 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
11723 /* Minimum guaranteed number of RSS/COS contexts */
11724 uint16_t min_rsscos_ctx;
11725 /* Maximum non-guaranteed number of RSS/COS contexts */
11726 uint16_t max_rsscos_ctx;
11727 /* Minimum guaranteed number of completion rings */
11728 uint16_t min_cmpl_rings;
11729 /* Maximum non-guaranteed number of completion rings */
11730 uint16_t max_cmpl_rings;
11731 /* Minimum guaranteed number of transmit rings */
11732 uint16_t min_tx_rings;
11733 /* Maximum non-guaranteed number of transmit rings */
11734 uint16_t max_tx_rings;
11735 /* Minimum guaranteed number of receive rings */
11736 uint16_t min_rx_rings;
11737 /* Maximum non-guaranteed number of receive rings */
11738 uint16_t max_rx_rings;
11739 /* Minimum guaranteed number of L2 contexts */
11740 uint16_t min_l2_ctxs;
11741 /* Maximum non-guaranteed number of L2 contexts */
11742 uint16_t max_l2_ctxs;
11743 /* Minimum guaranteed number of VNICs */
11744 uint16_t min_vnics;
11745 /* Maximum non-guaranteed number of VNICs */
11746 uint16_t max_vnics;
11747 /* Minimum guaranteed number of statistic contexts */
11748 uint16_t min_stat_ctx;
11749 /* Maximum non-guaranteed number of statistic contexts */
11750 uint16_t max_stat_ctx;
11751 /* Minimum guaranteed number of ring groups */
11752 uint16_t min_hw_ring_grps;
11753 /* Maximum non-guaranteed number of ring groups */
11754 uint16_t max_hw_ring_grps;
11756 * Maximum number of inputs into the transmit scheduler for this function.
11757 * The number of TX rings assigned to the function cannot exceed this value.
11759 uint16_t max_tx_scheduler_inputs;
11762 * When this bit is '1', it indicates that VF_RESOURCE_CFG supports
11763 * feature to reserve all minimum resources when minimum >= 1, otherwise
11764 * returns an error.
11766 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \
11768 uint8_t unused_0[5];
11770 * This field is used in Output records to indicate that the output
11771 * is completely written to RAM. This field should be read as '1'
11772 * to indicate that the output has been completely written.
11773 * When writing a command completion or response to an internal processor,
11774 * the order of writes has to be such that this field is written last.
11779 /*********************************
11780 * hwrm_func_backing_store_qcaps *
11781 *********************************/
11784 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
11785 struct hwrm_func_backing_store_qcaps_input {
11786 /* The HWRM command request type. */
11789 * The completion ring to send the completion event on. This should
11790 * be the NQ ID returned from the `nq_alloc` HWRM command.
11792 uint16_t cmpl_ring;
11794 * The sequence ID is used by the driver for tracking multiple
11795 * commands. This ID is treated as opaque data by the firmware and
11796 * the value is returned in the `hwrm_resp_hdr` upon completion.
11800 * The target ID of the command:
11801 * * 0x0-0xFFF8 - The function ID
11802 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11803 * * 0xFFFD - Reserved for user-space HWRM interface
11806 uint16_t target_id;
11808 * A physical address pointer pointing to a host buffer that the
11809 * command's response data will be written. This can be either a host
11810 * physical address (HPA) or a guest physical address (GPA) and must
11811 * point to a physically contiguous block of memory.
11813 uint64_t resp_addr;
11816 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */
11817 struct hwrm_func_backing_store_qcaps_output {
11818 /* The specific error status for the command. */
11819 uint16_t error_code;
11820 /* The HWRM command request type. */
11822 /* The sequence ID from the original command. */
11824 /* The length of the response data in number of bytes. */
11826 /* Maximum number of QP context entries supported for this function. */
11827 uint32_t qp_max_entries;
11829 * Minimum number of QP context entries that are needed to be reserved
11830 * for QP1 for the PF and its VFs. PF drivers must allocate at least
11831 * this many QP context entries, even if RoCE will not be used.
11833 uint16_t qp_min_qp1_entries;
11834 /* Maximum number of QP context entries that can be used for L2. */
11835 uint16_t qp_max_l2_entries;
11836 /* Number of bytes that must be allocated for each context entry. */
11837 uint16_t qp_entry_size;
11838 /* Maximum number of SRQ context entries that can be used for L2. */
11839 uint16_t srq_max_l2_entries;
11840 /* Maximum number of SRQ context entries supported for this function. */
11841 uint32_t srq_max_entries;
11842 /* Number of bytes that must be allocated for each context entry. */
11843 uint16_t srq_entry_size;
11844 /* Maximum number of CQ context entries that can be used for L2. */
11845 uint16_t cq_max_l2_entries;
11846 /* Maximum number of CQ context entries supported for this function. */
11847 uint32_t cq_max_entries;
11848 /* Number of bytes that must be allocated for each context entry. */
11849 uint16_t cq_entry_size;
11850 /* Maximum number of VNIC context entries supported for this function. */
11851 uint16_t vnic_max_vnic_entries;
11852 /* Maximum number of Ring table context entries supported for this function. */
11853 uint16_t vnic_max_ring_table_entries;
11854 /* Number of bytes that must be allocated for each context entry. */
11855 uint16_t vnic_entry_size;
11856 /* Maximum number of statistic context entries supported for this function. */
11857 uint32_t stat_max_entries;
11858 /* Number of bytes that must be allocated for each context entry. */
11859 uint16_t stat_entry_size;
11860 /* Number of bytes that must be allocated for each context entry. */
11861 uint16_t tqm_entry_size;
11862 /* Minimum number of TQM context entries required per ring. */
11863 uint32_t tqm_min_entries_per_ring;
11865 * Maximum number of TQM context entries supported per ring. This is
11866 * actually a recommended TQM queue size based on worst case usage of
11869 * TQM fastpath rings should be sized large enough to accommodate the
11870 * maximum number of QPs (either L2 or RoCE, or both if shared)
11871 * that can be enqueued to the TQM ring.
11873 * TQM slowpath rings should be sized as follows:
11875 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
11878 * num_vnics is the number of VNICs allocated in the VNIC backing store
11879 * num_l2_tx_rings is the number of L2 rings in the QP backing store
11880 * num_roce_qps is the number of RoCE QPs in the QP backing store
11881 * tqm_min_size is tqm_min_entries_per_ring reported by
11882 * HWRM_FUNC_BACKING_STORE_QCAPS
11884 * Note that TQM ring sizes cannot be extended while the system is
11885 * operational. If a PF driver needs to extend a TQM ring, it needs
11886 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
11887 * the backing store.
11889 uint32_t tqm_max_entries_per_ring;
11891 * Maximum number of MR plus AV context entries supported for this
11894 uint32_t mrav_max_entries;
11895 /* Number of bytes that must be allocated for each context entry. */
11896 uint16_t mrav_entry_size;
11897 /* Number of bytes that must be allocated for each context entry. */
11898 uint16_t tim_entry_size;
11899 /* Maximum number of Timer context entries supported for this function. */
11900 uint32_t tim_max_entries;
11902 * When this field is zero, the 32b `mrav_num_entries` field in the
11903 * `backing_store_cfg` and `backing_store_qcfg` commands represents
11904 * the total number of MR plus AV entries allowed in the MR/AV backing
11907 * When this field is non-zero, the 32b `mrav_num_entries` field in
11908 * the `backing_store_cfg` and `backing_store_qcfg` commands is
11909 * logically divided into two 16b fields. Bits `[31:16]` represents
11910 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
11911 * Both of these values are represented in a unit granularity
11912 * specified by this field. For example, if this field is 16 and
11913 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
11914 * is 8192 and the number of AV entries is 4096.
11916 uint16_t mrav_num_entries_units;
11918 * The number of entries specified for any TQM ring must be a
11919 * multiple of this value to prevent any resource allocation
11922 uint8_t tqm_entries_multiple;
11924 * Initializer to be used by drivers
11925 * to initialize context memory to ensure
11926 * context subsystem flags an error for an attack
11927 * before the first time context load.
11929 uint8_t ctx_kind_initializer;
11930 /* Reserved for future. */
11932 /* Reserved for future. */
11935 * Count of TQM fastpath rings to be used for allocating backing store.
11936 * Backing store configuration must be specified for each TQM ring from
11937 * this count in `backing_store_cfg`.
11939 uint8_t tqm_fp_rings_count;
11941 * This field is used in Output records to indicate that the output
11942 * is completely written to RAM. This field should be read as '1'
11943 * to indicate that the output has been completely written.
11944 * When writing a command completion or response to an internal processor,
11945 * the order of writes has to be such that this field is written last.
11950 /*******************************
11951 * hwrm_func_backing_store_cfg *
11952 *******************************/
11955 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
11956 struct hwrm_func_backing_store_cfg_input {
11957 /* The HWRM command request type. */
11960 * The completion ring to send the completion event on. This should
11961 * be the NQ ID returned from the `nq_alloc` HWRM command.
11963 uint16_t cmpl_ring;
11965 * The sequence ID is used by the driver for tracking multiple
11966 * commands. This ID is treated as opaque data by the firmware and
11967 * the value is returned in the `hwrm_resp_hdr` upon completion.
11971 * The target ID of the command:
11972 * * 0x0-0xFFF8 - The function ID
11973 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
11974 * * 0xFFFD - Reserved for user-space HWRM interface
11977 uint16_t target_id;
11979 * A physical address pointer pointing to a host buffer that the
11980 * command's response data will be written. This can be either a host
11981 * physical address (HPA) or a guest physical address (GPA) and must
11982 * point to a physically contiguous block of memory.
11984 uint64_t resp_addr;
11987 * When set, the firmware only uses on-chip resources and does not
11988 * expect any backing store to be provided by the host driver. This
11989 * mode provides minimal L2 functionality (e.g. limited L2 resources,
11992 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
11995 * When set, the 32b `mrav_num_entries` field is logically divided
11996 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
11998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
12002 * This bit must be '1' for the qp fields to be
12005 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
12008 * This bit must be '1' for the srq fields to be
12011 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
12014 * This bit must be '1' for the cq fields to be
12017 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
12020 * This bit must be '1' for the vnic fields to be
12023 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
12026 * This bit must be '1' for the stat fields to be
12029 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
12032 * This bit must be '1' for the tqm_sp fields to be
12035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
12038 * This bit must be '1' for the tqm_ring0 fields to be
12041 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
12044 * This bit must be '1' for the tqm_ring1 fields to be
12047 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
12050 * This bit must be '1' for the tqm_ring2 fields to be
12053 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
12056 * This bit must be '1' for the tqm_ring3 fields to be
12059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
12062 * This bit must be '1' for the tqm_ring4 fields to be
12065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
12068 * This bit must be '1' for the tqm_ring5 fields to be
12071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
12074 * This bit must be '1' for the tqm_ring6 fields to be
12077 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
12080 * This bit must be '1' for the tqm_ring7 fields to be
12083 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
12086 * This bit must be '1' for the mrav fields to be
12089 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
12092 * This bit must be '1' for the tim fields to be
12095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
12097 /* QPC page size and level. */
12098 uint8_t qpc_pg_size_qpc_lvl;
12099 /* QPC PBL indirect levels. */
12100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
12102 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
12103 /* PBL pointer is physical start address. */
12104 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
12106 /* PBL pointer points to PTE table. */
12107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
12109 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12110 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
12112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
12113 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
12114 /* QPC page size. */
12115 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
12117 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
12119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
12120 (UINT32_C(0x0) << 4)
12122 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
12123 (UINT32_C(0x1) << 4)
12125 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
12126 (UINT32_C(0x2) << 4)
12128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
12129 (UINT32_C(0x3) << 4)
12131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
12132 (UINT32_C(0x4) << 4)
12134 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
12135 (UINT32_C(0x5) << 4)
12136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
12137 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
12138 /* SRQ page size and level. */
12139 uint8_t srq_pg_size_srq_lvl;
12140 /* SRQ PBL indirect levels. */
12141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
12143 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
12144 /* PBL pointer is physical start address. */
12145 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
12147 /* PBL pointer points to PTE table. */
12148 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
12150 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12151 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
12153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
12154 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
12155 /* SRQ page size. */
12156 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
12158 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
12160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
12161 (UINT32_C(0x0) << 4)
12163 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
12164 (UINT32_C(0x1) << 4)
12166 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
12167 (UINT32_C(0x2) << 4)
12169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
12170 (UINT32_C(0x3) << 4)
12172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
12173 (UINT32_C(0x4) << 4)
12175 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
12176 (UINT32_C(0x5) << 4)
12177 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
12178 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
12179 /* CQ page size and level. */
12180 uint8_t cq_pg_size_cq_lvl;
12181 /* CQ PBL indirect levels. */
12182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
12184 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
12185 /* PBL pointer is physical start address. */
12186 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
12188 /* PBL pointer points to PTE table. */
12189 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
12191 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12192 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
12194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
12195 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
12196 /* CQ page size. */
12197 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
12199 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
12201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
12202 (UINT32_C(0x0) << 4)
12204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
12205 (UINT32_C(0x1) << 4)
12207 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
12208 (UINT32_C(0x2) << 4)
12210 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
12211 (UINT32_C(0x3) << 4)
12213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
12214 (UINT32_C(0x4) << 4)
12216 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
12217 (UINT32_C(0x5) << 4)
12218 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
12219 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
12220 /* VNIC page size and level. */
12221 uint8_t vnic_pg_size_vnic_lvl;
12222 /* VNIC PBL indirect levels. */
12223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
12225 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
12226 /* PBL pointer is physical start address. */
12227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
12229 /* PBL pointer points to PTE table. */
12230 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
12232 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12233 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
12235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
12236 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
12237 /* VNIC page size. */
12238 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
12240 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
12242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
12243 (UINT32_C(0x0) << 4)
12245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
12246 (UINT32_C(0x1) << 4)
12248 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
12249 (UINT32_C(0x2) << 4)
12251 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
12252 (UINT32_C(0x3) << 4)
12254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
12255 (UINT32_C(0x4) << 4)
12257 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
12258 (UINT32_C(0x5) << 4)
12259 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
12260 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
12261 /* Stat page size and level. */
12262 uint8_t stat_pg_size_stat_lvl;
12263 /* Stat PBL indirect levels. */
12264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
12266 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
12267 /* PBL pointer is physical start address. */
12268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
12270 /* PBL pointer points to PTE table. */
12271 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
12273 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12274 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
12276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
12277 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
12278 /* Stat page size. */
12279 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
12281 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
12283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
12284 (UINT32_C(0x0) << 4)
12286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
12287 (UINT32_C(0x1) << 4)
12289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
12290 (UINT32_C(0x2) << 4)
12292 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
12293 (UINT32_C(0x3) << 4)
12295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
12296 (UINT32_C(0x4) << 4)
12298 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
12299 (UINT32_C(0x5) << 4)
12300 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
12301 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
12302 /* TQM slow path page size and level. */
12303 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
12304 /* TQM slow path PBL indirect levels. */
12305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
12307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
12308 /* PBL pointer is physical start address. */
12309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
12311 /* PBL pointer points to PTE table. */
12312 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
12314 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12315 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
12317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
12318 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
12319 /* TQM slow path page size. */
12320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
12322 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
12324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
12325 (UINT32_C(0x0) << 4)
12327 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
12328 (UINT32_C(0x1) << 4)
12330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
12331 (UINT32_C(0x2) << 4)
12333 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
12334 (UINT32_C(0x3) << 4)
12336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
12337 (UINT32_C(0x4) << 4)
12339 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
12340 (UINT32_C(0x5) << 4)
12341 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
12342 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
12343 /* TQM ring 0 page size and level. */
12344 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
12345 /* TQM ring 0 PBL indirect levels. */
12346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
12348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
12349 /* PBL pointer is physical start address. */
12350 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
12352 /* PBL pointer points to PTE table. */
12353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
12355 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12356 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
12358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
12359 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
12360 /* TQM ring 0 page size. */
12361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
12363 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
12365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
12366 (UINT32_C(0x0) << 4)
12368 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
12369 (UINT32_C(0x1) << 4)
12371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
12372 (UINT32_C(0x2) << 4)
12374 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
12375 (UINT32_C(0x3) << 4)
12377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
12378 (UINT32_C(0x4) << 4)
12380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
12381 (UINT32_C(0x5) << 4)
12382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
12383 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
12384 /* TQM ring 1 page size and level. */
12385 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
12386 /* TQM ring 1 PBL indirect levels. */
12387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
12389 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
12390 /* PBL pointer is physical start address. */
12391 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
12393 /* PBL pointer points to PTE table. */
12394 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
12396 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
12399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
12400 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
12401 /* TQM ring 1 page size. */
12402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
12404 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
12406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
12407 (UINT32_C(0x0) << 4)
12409 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
12410 (UINT32_C(0x1) << 4)
12412 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
12413 (UINT32_C(0x2) << 4)
12415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
12416 (UINT32_C(0x3) << 4)
12418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
12419 (UINT32_C(0x4) << 4)
12421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
12422 (UINT32_C(0x5) << 4)
12423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
12424 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
12425 /* TQM ring 2 page size and level. */
12426 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
12427 /* TQM ring 2 PBL indirect levels. */
12428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
12430 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
12431 /* PBL pointer is physical start address. */
12432 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
12434 /* PBL pointer points to PTE table. */
12435 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
12437 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
12440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
12441 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
12442 /* TQM ring 2 page size. */
12443 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
12445 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
12447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
12448 (UINT32_C(0x0) << 4)
12450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
12451 (UINT32_C(0x1) << 4)
12453 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
12454 (UINT32_C(0x2) << 4)
12456 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
12457 (UINT32_C(0x3) << 4)
12459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
12460 (UINT32_C(0x4) << 4)
12462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
12463 (UINT32_C(0x5) << 4)
12464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
12465 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
12466 /* TQM ring 3 page size and level. */
12467 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
12468 /* TQM ring 3 PBL indirect levels. */
12469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
12471 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
12472 /* PBL pointer is physical start address. */
12473 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
12475 /* PBL pointer points to PTE table. */
12476 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
12478 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12479 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
12481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
12482 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
12483 /* TQM ring 3 page size. */
12484 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
12486 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
12488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
12489 (UINT32_C(0x0) << 4)
12491 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
12492 (UINT32_C(0x1) << 4)
12494 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
12495 (UINT32_C(0x2) << 4)
12497 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
12498 (UINT32_C(0x3) << 4)
12500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
12501 (UINT32_C(0x4) << 4)
12503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
12504 (UINT32_C(0x5) << 4)
12505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
12506 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
12507 /* TQM ring 4 page size and level. */
12508 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
12509 /* TQM ring 4 PBL indirect levels. */
12510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
12512 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
12513 /* PBL pointer is physical start address. */
12514 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
12516 /* PBL pointer points to PTE table. */
12517 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
12519 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12520 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
12522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
12523 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
12524 /* TQM ring 4 page size. */
12525 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
12527 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
12529 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
12530 (UINT32_C(0x0) << 4)
12532 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
12533 (UINT32_C(0x1) << 4)
12535 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
12536 (UINT32_C(0x2) << 4)
12538 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
12539 (UINT32_C(0x3) << 4)
12541 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
12542 (UINT32_C(0x4) << 4)
12544 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
12545 (UINT32_C(0x5) << 4)
12546 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
12547 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
12548 /* TQM ring 5 page size and level. */
12549 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
12550 /* TQM ring 5 PBL indirect levels. */
12551 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
12553 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
12554 /* PBL pointer is physical start address. */
12555 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
12557 /* PBL pointer points to PTE table. */
12558 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
12560 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12561 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
12563 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
12564 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
12565 /* TQM ring 5 page size. */
12566 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
12568 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
12570 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
12571 (UINT32_C(0x0) << 4)
12573 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
12574 (UINT32_C(0x1) << 4)
12576 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
12577 (UINT32_C(0x2) << 4)
12579 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
12580 (UINT32_C(0x3) << 4)
12582 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
12583 (UINT32_C(0x4) << 4)
12585 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
12586 (UINT32_C(0x5) << 4)
12587 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
12588 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
12589 /* TQM ring 6 page size and level. */
12590 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
12591 /* TQM ring 6 PBL indirect levels. */
12592 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
12594 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
12595 /* PBL pointer is physical start address. */
12596 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
12598 /* PBL pointer points to PTE table. */
12599 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
12601 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12602 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
12604 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
12605 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
12606 /* TQM ring 6 page size. */
12607 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
12609 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
12611 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
12612 (UINT32_C(0x0) << 4)
12614 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
12615 (UINT32_C(0x1) << 4)
12617 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
12618 (UINT32_C(0x2) << 4)
12620 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
12621 (UINT32_C(0x3) << 4)
12623 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
12624 (UINT32_C(0x4) << 4)
12626 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
12627 (UINT32_C(0x5) << 4)
12628 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
12629 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
12630 /* TQM ring 7 page size and level. */
12631 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
12632 /* TQM ring 7 PBL indirect levels. */
12633 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
12635 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
12636 /* PBL pointer is physical start address. */
12637 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
12639 /* PBL pointer points to PTE table. */
12640 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
12642 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12643 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
12645 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
12646 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
12647 /* TQM ring 7 page size. */
12648 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
12650 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
12652 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
12653 (UINT32_C(0x0) << 4)
12655 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
12656 (UINT32_C(0x1) << 4)
12658 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
12659 (UINT32_C(0x2) << 4)
12661 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
12662 (UINT32_C(0x3) << 4)
12664 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
12665 (UINT32_C(0x4) << 4)
12667 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
12668 (UINT32_C(0x5) << 4)
12669 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
12670 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
12671 /* MR/AV page size and level. */
12672 uint8_t mrav_pg_size_mrav_lvl;
12673 /* MR/AV PBL indirect levels. */
12674 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
12676 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
12677 /* PBL pointer is physical start address. */
12678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
12680 /* PBL pointer points to PTE table. */
12681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
12683 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
12686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
12687 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
12688 /* MR/AV page size. */
12689 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
12691 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
12693 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
12694 (UINT32_C(0x0) << 4)
12696 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
12697 (UINT32_C(0x1) << 4)
12699 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
12700 (UINT32_C(0x2) << 4)
12702 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
12703 (UINT32_C(0x3) << 4)
12705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
12706 (UINT32_C(0x4) << 4)
12708 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
12709 (UINT32_C(0x5) << 4)
12710 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
12711 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
12712 /* Timer page size and level. */
12713 uint8_t tim_pg_size_tim_lvl;
12714 /* Timer PBL indirect levels. */
12715 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
12717 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
12718 /* PBL pointer is physical start address. */
12719 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
12721 /* PBL pointer points to PTE table. */
12722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
12724 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
12725 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
12727 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
12728 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
12729 /* Timer page size. */
12730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
12732 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
12734 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
12735 (UINT32_C(0x0) << 4)
12737 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
12738 (UINT32_C(0x1) << 4)
12740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
12741 (UINT32_C(0x2) << 4)
12743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
12744 (UINT32_C(0x3) << 4)
12746 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
12747 (UINT32_C(0x4) << 4)
12749 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
12750 (UINT32_C(0x5) << 4)
12751 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
12752 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
12753 /* QP page directory. */
12754 uint64_t qpc_page_dir;
12755 /* SRQ page directory. */
12756 uint64_t srq_page_dir;
12757 /* CQ page directory. */
12758 uint64_t cq_page_dir;
12759 /* VNIC page directory. */
12760 uint64_t vnic_page_dir;
12761 /* Stat page directory. */
12762 uint64_t stat_page_dir;
12763 /* TQM slowpath page directory. */
12764 uint64_t tqm_sp_page_dir;
12765 /* TQM ring 0 page directory. */
12766 uint64_t tqm_ring0_page_dir;
12767 /* TQM ring 1 page directory. */
12768 uint64_t tqm_ring1_page_dir;
12769 /* TQM ring 2 page directory. */
12770 uint64_t tqm_ring2_page_dir;
12771 /* TQM ring 3 page directory. */
12772 uint64_t tqm_ring3_page_dir;
12773 /* TQM ring 4 page directory. */
12774 uint64_t tqm_ring4_page_dir;
12775 /* TQM ring 5 page directory. */
12776 uint64_t tqm_ring5_page_dir;
12777 /* TQM ring 6 page directory. */
12778 uint64_t tqm_ring6_page_dir;
12779 /* TQM ring 7 page directory. */
12780 uint64_t tqm_ring7_page_dir;
12781 /* MR/AV page directory. */
12782 uint64_t mrav_page_dir;
12783 /* Timer page directory. */
12784 uint64_t tim_page_dir;
12785 /* Number of QPs. */
12786 uint32_t qp_num_entries;
12787 /* Number of SRQs. */
12788 uint32_t srq_num_entries;
12789 /* Number of CQs. */
12790 uint32_t cq_num_entries;
12791 /* Number of Stats. */
12792 uint32_t stat_num_entries;
12794 * Number of TQM slowpath entries.
12796 * TQM slowpath rings should be sized as follows:
12798 * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size
12801 * num_vnics is the number of VNICs allocated in the VNIC backing store
12802 * num_l2_tx_rings is the number of L2 rings in the QP backing store
12803 * num_roce_qps is the number of RoCE QPs in the QP backing store
12804 * tqm_min_size is tqm_min_entries_per_ring reported by
12805 * HWRM_FUNC_BACKING_STORE_QCAPS
12807 * Note that TQM ring sizes cannot be extended while the system is
12808 * operational. If a PF driver needs to extend a TQM ring, it needs
12809 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12810 * the backing store.
12812 uint32_t tqm_sp_num_entries;
12814 * Number of TQM ring 0 entries.
12816 * TQM fastpath rings should be sized large enough to accommodate the
12817 * maximum number of QPs (either L2 or RoCE, or both if shared)
12818 * that can be enqueued to the TQM ring.
12820 * Note that TQM ring sizes cannot be extended while the system is
12821 * operational. If a PF driver needs to extend a TQM ring, it needs
12822 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12823 * the backing store.
12825 uint32_t tqm_ring0_num_entries;
12827 * Number of TQM ring 1 entries.
12829 * TQM fastpath rings should be sized large enough to accommodate the
12830 * maximum number of QPs (either L2 or RoCE, or both if shared)
12831 * that can be enqueued to the TQM ring.
12833 * Note that TQM ring sizes cannot be extended while the system is
12834 * operational. If a PF driver needs to extend a TQM ring, it needs
12835 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12836 * the backing store.
12838 uint32_t tqm_ring1_num_entries;
12840 * Number of TQM ring 2 entries.
12842 * TQM fastpath rings should be sized large enough to accommodate the
12843 * maximum number of QPs (either L2 or RoCE, or both if shared)
12844 * that can be enqueued to the TQM ring.
12846 * Note that TQM ring sizes cannot be extended while the system is
12847 * operational. If a PF driver needs to extend a TQM ring, it needs
12848 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12849 * the backing store.
12851 uint32_t tqm_ring2_num_entries;
12853 * Number of TQM ring 3 entries.
12855 * TQM fastpath rings should be sized large enough to accommodate the
12856 * maximum number of QPs (either L2 or RoCE, or both if shared)
12857 * that can be enqueued to the TQM ring.
12859 * Note that TQM ring sizes cannot be extended while the system is
12860 * operational. If a PF driver needs to extend a TQM ring, it needs
12861 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12862 * the backing store.
12864 uint32_t tqm_ring3_num_entries;
12866 * Number of TQM ring 4 entries.
12868 * TQM fastpath rings should be sized large enough to accommodate the
12869 * maximum number of QPs (either L2 or RoCE, or both if shared)
12870 * that can be enqueued to the TQM ring.
12872 * Note that TQM ring sizes cannot be extended while the system is
12873 * operational. If a PF driver needs to extend a TQM ring, it needs
12874 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12875 * the backing store.
12877 uint32_t tqm_ring4_num_entries;
12879 * Number of TQM ring 5 entries.
12881 * TQM fastpath rings should be sized large enough to accommodate the
12882 * maximum number of QPs (either L2 or RoCE, or both if shared)
12883 * that can be enqueued to the TQM ring.
12885 * Note that TQM ring sizes cannot be extended while the system is
12886 * operational. If a PF driver needs to extend a TQM ring, it needs
12887 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12888 * the backing store.
12890 uint32_t tqm_ring5_num_entries;
12892 * Number of TQM ring 6 entries.
12894 * TQM fastpath rings should be sized large enough to accommodate the
12895 * maximum number of QPs (either L2 or RoCE, or both if shared)
12896 * that can be enqueued to the TQM ring.
12898 * Note that TQM ring sizes cannot be extended while the system is
12899 * operational. If a PF driver needs to extend a TQM ring, it needs
12900 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12901 * the backing store.
12903 uint32_t tqm_ring6_num_entries;
12905 * Number of TQM ring 7 entries.
12907 * TQM fastpath rings should be sized large enough to accommodate the
12908 * maximum number of QPs (either L2 or RoCE, or both if shared)
12909 * that can be enqueued to the TQM ring.
12911 * Note that TQM ring sizes cannot be extended while the system is
12912 * operational. If a PF driver needs to extend a TQM ring, it needs
12913 * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate
12914 * the backing store.
12916 uint32_t tqm_ring7_num_entries;
12918 * If the MR/AV split reservation flag is not set, then this field
12919 * represents the total number of MR plus AV entries. For versions
12920 * of firmware that support the split reservation, when it is not
12921 * specified half of the entries will be reserved for MRs and the
12922 * other half for AVs.
12924 * If the MR/AV split reservation flag is set, then this
12925 * field is logically divided into two 16b fields. Bits `[31:16]`
12926 * represents the `mr_num_entries` and bits `[15:0]` represents
12927 * `av_num_entries`. The granularity of these values is defined by
12928 * the `mrav_num_entries_unit` field returned by the
12929 * `backing_store_qcaps` command.
12931 uint32_t mrav_num_entries;
12932 /* Number of Timer entries. */
12933 uint32_t tim_num_entries;
12934 /* Number of entries to reserve for QP1 */
12935 uint16_t qp_num_qp1_entries;
12936 /* Number of entries to reserve for L2 */
12937 uint16_t qp_num_l2_entries;
12938 /* Number of bytes that have been allocated for each context entry. */
12939 uint16_t qp_entry_size;
12940 /* Number of entries to reserve for L2 */
12941 uint16_t srq_num_l2_entries;
12942 /* Number of bytes that have been allocated for each context entry. */
12943 uint16_t srq_entry_size;
12944 /* Number of entries to reserve for L2 */
12945 uint16_t cq_num_l2_entries;
12946 /* Number of bytes that have been allocated for each context entry. */
12947 uint16_t cq_entry_size;
12948 /* Number of entries to reserve for VNIC entries */
12949 uint16_t vnic_num_vnic_entries;
12950 /* Number of entries to reserve for Ring table entries */
12951 uint16_t vnic_num_ring_table_entries;
12952 /* Number of bytes that have been allocated for each context entry. */
12953 uint16_t vnic_entry_size;
12954 /* Number of bytes that have been allocated for each context entry. */
12955 uint16_t stat_entry_size;
12956 /* Number of bytes that have been allocated for each context entry. */
12957 uint16_t tqm_entry_size;
12958 /* Number of bytes that have been allocated for each context entry. */
12959 uint16_t mrav_entry_size;
12960 /* Number of bytes that have been allocated for each context entry. */
12961 uint16_t tim_entry_size;
12964 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
12965 struct hwrm_func_backing_store_cfg_output {
12966 /* The specific error status for the command. */
12967 uint16_t error_code;
12968 /* The HWRM command request type. */
12970 /* The sequence ID from the original command. */
12972 /* The length of the response data in number of bytes. */
12974 uint8_t unused_0[7];
12976 * This field is used in Output records to indicate that the output
12977 * is completely written to RAM. This field should be read as '1'
12978 * to indicate that the output has been completely written.
12979 * When writing a command completion or response to an internal processor,
12980 * the order of writes has to be such that this field is written last.
12985 /********************************
12986 * hwrm_func_backing_store_qcfg *
12987 ********************************/
12990 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
12991 struct hwrm_func_backing_store_qcfg_input {
12992 /* The HWRM command request type. */
12995 * The completion ring to send the completion event on. This should
12996 * be the NQ ID returned from the `nq_alloc` HWRM command.
12998 uint16_t cmpl_ring;
13000 * The sequence ID is used by the driver for tracking multiple
13001 * commands. This ID is treated as opaque data by the firmware and
13002 * the value is returned in the `hwrm_resp_hdr` upon completion.
13006 * The target ID of the command:
13007 * * 0x0-0xFFF8 - The function ID
13008 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13009 * * 0xFFFD - Reserved for user-space HWRM interface
13012 uint16_t target_id;
13014 * A physical address pointer pointing to a host buffer that the
13015 * command's response data will be written. This can be either a host
13016 * physical address (HPA) or a guest physical address (GPA) and must
13017 * point to a physically contiguous block of memory.
13019 uint64_t resp_addr;
13022 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
13023 struct hwrm_func_backing_store_qcfg_output {
13024 /* The specific error status for the command. */
13025 uint16_t error_code;
13026 /* The HWRM command request type. */
13028 /* The sequence ID from the original command. */
13030 /* The length of the response data in number of bytes. */
13034 * When set, the firmware only uses on-chip resources and does not
13035 * expect any backing store to be provided by the host driver. This
13036 * mode provides minimal L2 functionality (e.g. limited L2 resources,
13039 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
13042 * When set, the 32b `mrav_num_entries` field is logically divided
13043 * into two 16b fields, `mr_num_entries` and `av_num_entries`.
13045 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
13047 uint8_t unused_0[4];
13049 * This bit must be '1' for the qp fields to be
13052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
13055 * This bit must be '1' for the srq fields to be
13058 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
13061 * This bit must be '1' for the cq fields to be
13064 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
13067 * This bit must be '1' for the vnic fields to be
13070 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
13073 * This bit must be '1' for the stat fields to be
13076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
13079 * This bit must be '1' for the tqm_sp fields to be
13082 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
13085 * This bit must be '1' for the tqm_ring0 fields to be
13088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
13091 * This bit must be '1' for the tqm_ring1 fields to be
13094 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
13097 * This bit must be '1' for the tqm_ring2 fields to be
13100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
13103 * This bit must be '1' for the tqm_ring3 fields to be
13106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
13109 * This bit must be '1' for the tqm_ring4 fields to be
13112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
13115 * This bit must be '1' for the tqm_ring5 fields to be
13118 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
13121 * This bit must be '1' for the tqm_ring6 fields to be
13124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
13127 * This bit must be '1' for the tqm_ring7 fields to be
13130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
13133 * This bit must be '1' for the mrav fields to be
13136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
13139 * This bit must be '1' for the tim fields to be
13142 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
13144 /* QPC page size and level. */
13145 uint8_t qpc_pg_size_qpc_lvl;
13146 /* QPC PBL indirect levels. */
13147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
13149 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
13150 /* PBL pointer is physical start address. */
13151 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
13153 /* PBL pointer points to PTE table. */
13154 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
13156 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13157 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
13159 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
13160 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
13161 /* QPC page size. */
13162 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
13164 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
13166 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
13167 (UINT32_C(0x0) << 4)
13169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
13170 (UINT32_C(0x1) << 4)
13172 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
13173 (UINT32_C(0x2) << 4)
13175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
13176 (UINT32_C(0x3) << 4)
13178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
13179 (UINT32_C(0x4) << 4)
13181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
13182 (UINT32_C(0x5) << 4)
13183 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
13184 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
13185 /* SRQ page size and level. */
13186 uint8_t srq_pg_size_srq_lvl;
13187 /* SRQ PBL indirect levels. */
13188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
13190 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
13191 /* PBL pointer is physical start address. */
13192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
13194 /* PBL pointer points to PTE table. */
13195 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
13197 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13198 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
13200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
13201 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
13202 /* SRQ page size. */
13203 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
13205 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
13207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
13208 (UINT32_C(0x0) << 4)
13210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
13211 (UINT32_C(0x1) << 4)
13213 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
13214 (UINT32_C(0x2) << 4)
13216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
13217 (UINT32_C(0x3) << 4)
13219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
13220 (UINT32_C(0x4) << 4)
13222 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
13223 (UINT32_C(0x5) << 4)
13224 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
13225 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
13226 /* CQ page size and level. */
13227 uint8_t cq_pg_size_cq_lvl;
13228 /* CQ PBL indirect levels. */
13229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
13231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
13232 /* PBL pointer is physical start address. */
13233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
13235 /* PBL pointer points to PTE table. */
13236 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
13238 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13239 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
13241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
13242 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
13243 /* CQ page size. */
13244 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
13246 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
13248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
13249 (UINT32_C(0x0) << 4)
13251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
13252 (UINT32_C(0x1) << 4)
13254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
13255 (UINT32_C(0x2) << 4)
13257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
13258 (UINT32_C(0x3) << 4)
13260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
13261 (UINT32_C(0x4) << 4)
13263 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
13264 (UINT32_C(0x5) << 4)
13265 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
13266 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
13267 /* VNIC page size and level. */
13268 uint8_t vnic_pg_size_vnic_lvl;
13269 /* VNIC PBL indirect levels. */
13270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
13272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
13273 /* PBL pointer is physical start address. */
13274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
13276 /* PBL pointer points to PTE table. */
13277 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
13279 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13280 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
13282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
13283 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
13284 /* VNIC page size. */
13285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
13287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
13289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
13290 (UINT32_C(0x0) << 4)
13292 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
13293 (UINT32_C(0x1) << 4)
13295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
13296 (UINT32_C(0x2) << 4)
13298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
13299 (UINT32_C(0x3) << 4)
13301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
13302 (UINT32_C(0x4) << 4)
13304 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
13305 (UINT32_C(0x5) << 4)
13306 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
13307 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
13308 /* Stat page size and level. */
13309 uint8_t stat_pg_size_stat_lvl;
13310 /* Stat PBL indirect levels. */
13311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
13313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
13314 /* PBL pointer is physical start address. */
13315 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
13317 /* PBL pointer points to PTE table. */
13318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
13320 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13321 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
13323 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
13324 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
13325 /* Stat page size. */
13326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
13328 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
13330 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
13331 (UINT32_C(0x0) << 4)
13333 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
13334 (UINT32_C(0x1) << 4)
13336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
13337 (UINT32_C(0x2) << 4)
13339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
13340 (UINT32_C(0x3) << 4)
13342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
13343 (UINT32_C(0x4) << 4)
13345 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
13346 (UINT32_C(0x5) << 4)
13347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
13348 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
13349 /* TQM slow path page size and level. */
13350 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
13351 /* TQM slow path PBL indirect levels. */
13352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
13354 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
13355 /* PBL pointer is physical start address. */
13356 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
13358 /* PBL pointer points to PTE table. */
13359 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
13361 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13362 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
13364 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
13365 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
13366 /* TQM slow path page size. */
13367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
13369 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
13371 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
13372 (UINT32_C(0x0) << 4)
13374 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
13375 (UINT32_C(0x1) << 4)
13377 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
13378 (UINT32_C(0x2) << 4)
13380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
13381 (UINT32_C(0x3) << 4)
13383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
13384 (UINT32_C(0x4) << 4)
13386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
13387 (UINT32_C(0x5) << 4)
13388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
13389 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
13390 /* TQM ring 0 page size and level. */
13391 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
13392 /* TQM ring 0 PBL indirect levels. */
13393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
13395 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
13396 /* PBL pointer is physical start address. */
13397 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
13399 /* PBL pointer points to PTE table. */
13400 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
13402 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13403 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
13405 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
13406 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
13407 /* TQM ring 0 page size. */
13408 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
13410 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
13412 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
13413 (UINT32_C(0x0) << 4)
13415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
13416 (UINT32_C(0x1) << 4)
13418 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
13419 (UINT32_C(0x2) << 4)
13421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
13422 (UINT32_C(0x3) << 4)
13424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
13425 (UINT32_C(0x4) << 4)
13427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
13428 (UINT32_C(0x5) << 4)
13429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
13430 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
13431 /* TQM ring 1 page size and level. */
13432 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
13433 /* TQM ring 1 PBL indirect levels. */
13434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
13436 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
13437 /* PBL pointer is physical start address. */
13438 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
13440 /* PBL pointer points to PTE table. */
13441 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
13443 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13444 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
13446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
13447 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
13448 /* TQM ring 1 page size. */
13449 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
13451 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
13453 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
13454 (UINT32_C(0x0) << 4)
13456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
13457 (UINT32_C(0x1) << 4)
13459 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
13460 (UINT32_C(0x2) << 4)
13462 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
13463 (UINT32_C(0x3) << 4)
13465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
13466 (UINT32_C(0x4) << 4)
13468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
13469 (UINT32_C(0x5) << 4)
13470 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
13471 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
13472 /* TQM ring 2 page size and level. */
13473 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
13474 /* TQM ring 2 PBL indirect levels. */
13475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
13477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
13478 /* PBL pointer is physical start address. */
13479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
13481 /* PBL pointer points to PTE table. */
13482 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
13484 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13485 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
13487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
13488 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
13489 /* TQM ring 2 page size. */
13490 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
13492 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
13494 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
13495 (UINT32_C(0x0) << 4)
13497 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
13498 (UINT32_C(0x1) << 4)
13500 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
13501 (UINT32_C(0x2) << 4)
13503 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
13504 (UINT32_C(0x3) << 4)
13506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
13507 (UINT32_C(0x4) << 4)
13509 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
13510 (UINT32_C(0x5) << 4)
13511 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
13512 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
13513 /* TQM ring 3 page size and level. */
13514 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
13515 /* TQM ring 3 PBL indirect levels. */
13516 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
13518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
13519 /* PBL pointer is physical start address. */
13520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
13522 /* PBL pointer points to PTE table. */
13523 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
13525 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13526 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
13528 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
13529 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
13530 /* TQM ring 3 page size. */
13531 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
13533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
13535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
13536 (UINT32_C(0x0) << 4)
13538 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
13539 (UINT32_C(0x1) << 4)
13541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
13542 (UINT32_C(0x2) << 4)
13544 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
13545 (UINT32_C(0x3) << 4)
13547 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
13548 (UINT32_C(0x4) << 4)
13550 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
13551 (UINT32_C(0x5) << 4)
13552 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
13553 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
13554 /* TQM ring 4 page size and level. */
13555 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
13556 /* TQM ring 4 PBL indirect levels. */
13557 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
13559 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
13560 /* PBL pointer is physical start address. */
13561 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
13563 /* PBL pointer points to PTE table. */
13564 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
13566 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13567 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
13569 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
13570 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
13571 /* TQM ring 4 page size. */
13572 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
13574 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
13576 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
13577 (UINT32_C(0x0) << 4)
13579 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
13580 (UINT32_C(0x1) << 4)
13582 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
13583 (UINT32_C(0x2) << 4)
13585 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
13586 (UINT32_C(0x3) << 4)
13588 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
13589 (UINT32_C(0x4) << 4)
13591 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
13592 (UINT32_C(0x5) << 4)
13593 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
13594 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
13595 /* TQM ring 5 page size and level. */
13596 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
13597 /* TQM ring 5 PBL indirect levels. */
13598 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
13600 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
13601 /* PBL pointer is physical start address. */
13602 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
13604 /* PBL pointer points to PTE table. */
13605 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
13607 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13608 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
13610 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
13611 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
13612 /* TQM ring 5 page size. */
13613 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
13615 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
13617 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
13618 (UINT32_C(0x0) << 4)
13620 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
13621 (UINT32_C(0x1) << 4)
13623 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
13624 (UINT32_C(0x2) << 4)
13626 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
13627 (UINT32_C(0x3) << 4)
13629 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
13630 (UINT32_C(0x4) << 4)
13632 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
13633 (UINT32_C(0x5) << 4)
13634 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
13635 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
13636 /* TQM ring 6 page size and level. */
13637 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
13638 /* TQM ring 6 PBL indirect levels. */
13639 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
13641 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
13642 /* PBL pointer is physical start address. */
13643 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
13645 /* PBL pointer points to PTE table. */
13646 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
13648 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13649 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
13651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
13652 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
13653 /* TQM ring 6 page size. */
13654 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
13656 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
13658 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
13659 (UINT32_C(0x0) << 4)
13661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
13662 (UINT32_C(0x1) << 4)
13664 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
13665 (UINT32_C(0x2) << 4)
13667 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
13668 (UINT32_C(0x3) << 4)
13670 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
13671 (UINT32_C(0x4) << 4)
13673 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
13674 (UINT32_C(0x5) << 4)
13675 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
13676 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
13677 /* TQM ring 7 page size and level. */
13678 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
13679 /* TQM ring 7 PBL indirect levels. */
13680 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
13682 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
13683 /* PBL pointer is physical start address. */
13684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
13686 /* PBL pointer points to PTE table. */
13687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
13689 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13690 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
13692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
13693 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
13694 /* TQM ring 7 page size. */
13695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
13697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
13699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
13700 (UINT32_C(0x0) << 4)
13702 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
13703 (UINT32_C(0x1) << 4)
13705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
13706 (UINT32_C(0x2) << 4)
13708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
13709 (UINT32_C(0x3) << 4)
13711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
13712 (UINT32_C(0x4) << 4)
13714 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
13715 (UINT32_C(0x5) << 4)
13716 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
13717 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
13718 /* MR/AV page size and level. */
13719 uint8_t mrav_pg_size_mrav_lvl;
13720 /* MR/AV PBL indirect levels. */
13721 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
13723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
13724 /* PBL pointer is physical start address. */
13725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
13727 /* PBL pointer points to PTE table. */
13728 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
13730 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
13733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
13734 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
13735 /* MR/AV page size. */
13736 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
13738 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
13740 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
13741 (UINT32_C(0x0) << 4)
13743 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
13744 (UINT32_C(0x1) << 4)
13746 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
13747 (UINT32_C(0x2) << 4)
13749 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
13750 (UINT32_C(0x3) << 4)
13752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
13753 (UINT32_C(0x4) << 4)
13755 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
13756 (UINT32_C(0x5) << 4)
13757 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
13758 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
13759 /* Timer page size and level. */
13760 uint8_t tim_pg_size_tim_lvl;
13761 /* Timer PBL indirect levels. */
13762 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
13764 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
13765 /* PBL pointer is physical start address. */
13766 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
13768 /* PBL pointer points to PTE table. */
13769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
13771 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
13772 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
13774 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
13775 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
13776 /* Timer page size. */
13777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
13779 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
13781 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
13782 (UINT32_C(0x0) << 4)
13784 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
13785 (UINT32_C(0x1) << 4)
13787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
13788 (UINT32_C(0x2) << 4)
13790 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
13791 (UINT32_C(0x3) << 4)
13793 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
13794 (UINT32_C(0x4) << 4)
13796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
13797 (UINT32_C(0x5) << 4)
13798 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
13799 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
13800 /* QP page directory. */
13801 uint64_t qpc_page_dir;
13802 /* SRQ page directory. */
13803 uint64_t srq_page_dir;
13804 /* CQ page directory. */
13805 uint64_t cq_page_dir;
13806 /* VNIC page directory. */
13807 uint64_t vnic_page_dir;
13808 /* Stat page directory. */
13809 uint64_t stat_page_dir;
13810 /* TQM slowpath page directory. */
13811 uint64_t tqm_sp_page_dir;
13812 /* TQM ring 0 page directory. */
13813 uint64_t tqm_ring0_page_dir;
13814 /* TQM ring 1 page directory. */
13815 uint64_t tqm_ring1_page_dir;
13816 /* TQM ring 2 page directory. */
13817 uint64_t tqm_ring2_page_dir;
13818 /* TQM ring 3 page directory. */
13819 uint64_t tqm_ring3_page_dir;
13820 /* TQM ring 4 page directory. */
13821 uint64_t tqm_ring4_page_dir;
13822 /* TQM ring 5 page directory. */
13823 uint64_t tqm_ring5_page_dir;
13824 /* TQM ring 6 page directory. */
13825 uint64_t tqm_ring6_page_dir;
13826 /* TQM ring 7 page directory. */
13827 uint64_t tqm_ring7_page_dir;
13828 /* MR/AV page directory. */
13829 uint64_t mrav_page_dir;
13830 /* Timer page directory. */
13831 uint64_t tim_page_dir;
13832 /* Number of entries to reserve for QP1 */
13833 uint16_t qp_num_qp1_entries;
13834 /* Number of entries to reserve for L2 */
13835 uint16_t qp_num_l2_entries;
13836 /* Number of QPs. */
13837 uint32_t qp_num_entries;
13838 /* Number of SRQs. */
13839 uint32_t srq_num_entries;
13840 /* Number of entries to reserve for L2 */
13841 uint16_t srq_num_l2_entries;
13842 /* Number of entries to reserve for L2 */
13843 uint16_t cq_num_l2_entries;
13844 /* Number of CQs. */
13845 uint32_t cq_num_entries;
13846 /* Number of entries to reserve for VNIC entries */
13847 uint16_t vnic_num_vnic_entries;
13848 /* Number of entries to reserve for Ring table entries */
13849 uint16_t vnic_num_ring_table_entries;
13850 /* Number of Stats. */
13851 uint32_t stat_num_entries;
13852 /* Number of TQM slowpath entries. */
13853 uint32_t tqm_sp_num_entries;
13854 /* Number of TQM ring 0 entries. */
13855 uint32_t tqm_ring0_num_entries;
13856 /* Number of TQM ring 1 entries. */
13857 uint32_t tqm_ring1_num_entries;
13858 /* Number of TQM ring 2 entries. */
13859 uint32_t tqm_ring2_num_entries;
13860 /* Number of TQM ring 3 entries. */
13861 uint32_t tqm_ring3_num_entries;
13862 /* Number of TQM ring 4 entries. */
13863 uint32_t tqm_ring4_num_entries;
13864 /* Number of TQM ring 5 entries. */
13865 uint32_t tqm_ring5_num_entries;
13866 /* Number of TQM ring 6 entries. */
13867 uint32_t tqm_ring6_num_entries;
13868 /* Number of TQM ring 7 entries. */
13869 uint32_t tqm_ring7_num_entries;
13871 * If the MR/AV split reservation flag is not set, then this field
13872 * represents the total number of MR plus AV entries. For versions
13873 * of firmware that support the split reservation, when it is not
13874 * specified half of the entries will be reserved for MRs and the
13875 * other half for AVs.
13877 * If the MR/AV split reservation flag is set, then this
13878 * field is logically divided into two 16b fields. Bits `[31:16]`
13879 * represents the `mr_num_entries` and bits `[15:0]` represents
13880 * `av_num_entries`. The granularity of these values is defined by
13881 * the `mrav_num_entries_unit` field returned by the
13882 * `backing_store_qcaps` command.
13884 uint32_t mrav_num_entries;
13885 /* Number of Timer entries. */
13886 uint32_t tim_num_entries;
13887 uint8_t unused_1[7];
13889 * This field is used in Output records to indicate that the output
13890 * is completely written to RAM. This field should be read as 1
13891 * to indicate that the output has been completely written.
13892 * When writing a command completion or response to an internal
13893 * processor, the order of writes has to be such that this field
13899 /****************************
13900 * hwrm_error_recovery_qcfg *
13901 ****************************/
13904 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */
13905 struct hwrm_error_recovery_qcfg_input {
13906 /* The HWRM command request type. */
13909 * The completion ring to send the completion event on. This should
13910 * be the NQ ID returned from the `nq_alloc` HWRM command.
13912 uint16_t cmpl_ring;
13914 * The sequence ID is used by the driver for tracking multiple
13915 * commands. This ID is treated as opaque data by the firmware and
13916 * the value is returned in the `hwrm_resp_hdr` upon completion.
13920 * The target ID of the command:
13921 * * 0x0-0xFFF8 - The function ID
13922 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13923 * * 0xFFFD - Reserved for user-space HWRM interface
13926 uint16_t target_id;
13928 * A physical address pointer pointing to a host buffer that the
13929 * command's response data will be written. This can be either a host
13930 * physical address (HPA) or a guest physical address (GPA) and must
13931 * point to a physically contiguous block of memory.
13933 uint64_t resp_addr;
13934 uint8_t unused_0[8];
13937 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
13938 struct hwrm_error_recovery_qcfg_output {
13939 /* The specific error status for the command. */
13940 uint16_t error_code;
13941 /* The HWRM command request type. */
13943 /* The sequence ID from the original command. */
13945 /* The length of the response data in number of bytes. */
13949 * When this flag is set to 1, error recovery will be initiated
13950 * through master function driver.
13952 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
13954 * When this flag is set to 1, error recovery will be performed
13955 * through Co processor.
13957 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
13959 * Driver Polling frequency. This value is in units of 100msec.
13960 * Typical value would be 10 to indicate 1sec.
13961 * Drivers can poll FW health status, Heartbeat, reset_counter with
13964 uint32_t driver_polling_freq;
13966 * This value is in units of 100msec.
13967 * Typical value would be 30 to indicate 3sec.
13968 * Master function wait period from detecting a fatal error to
13969 * initiating reset. In this time period Master PF expects every
13970 * active driver will detect fatal error.
13972 uint32_t master_func_wait_period;
13974 * This value is in units of 100msec.
13975 * Typical value would be 50 to indicate 5sec.
13976 * Normal function wait period from fatal error detection to
13977 * polling FW health status. In this time period, drivers should not
13978 * do any PCIe MMIO transaction and should not send any HWRM commands.
13980 uint32_t normal_func_wait_period;
13982 * This value is in units of 100msec.
13983 * Typical value would be 20 to indicate 2sec.
13984 * This field indicates that, master function wait period after chip
13985 * reset. After this time, master function should reinitialize with
13988 uint32_t master_func_wait_period_after_reset;
13990 * This value is in units of 100msec.
13991 * Typical value would be 60 to indicate 6sec.
13992 * This field is applicable to both master and normal functions.
13993 * Even after chip reset, if FW status not changed to ready,
13994 * then all the functions can poll for this much time and bailout.
13996 uint32_t max_bailout_time_after_reset;
13998 * FW health status register.
13999 * Lower 2 bits indicates address space location and upper 30 bits
14000 * indicates upper 30bits of the register address.
14001 * A value of 0xFFFF-FFFF indicates this register does not exist.
14003 uint32_t fw_health_status_reg;
14004 /* Lower 2 bits indicates address space location. */
14005 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
14007 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
14010 * If value is 0, this register is located in PCIe config space.
14011 * Drivers have to map appropriate window to access this
14014 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
14017 * If value is 1, this register is located in GRC address space.
14018 * Drivers have to map appropriate window to access this
14021 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
14024 * If value is 2, this register is located in first BAR address
14025 * space. Drivers have to map appropriate window to access this
14028 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
14031 * If value is 3, this register is located in second BAR address
14032 * space. Drivers have to map appropriate window to access this
14033 * Drivers have to map appropriate window to access this
14036 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
14038 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
14039 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
14040 /* Upper 30bits of the register address. */
14041 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
14042 UINT32_C(0xfffffffc)
14043 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
14046 * FW HeartBeat register.
14047 * Lower 2 bits indicates address space location and upper 30 bits
14048 * indicates actual address.
14049 * A value of 0xFFFF-FFFF indicates this register does not exist.
14051 uint32_t fw_heartbeat_reg;
14052 /* Lower 2 bits indicates address space location. */
14053 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
14055 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
14058 * If value is 0, this register is located in PCIe config space.
14059 * Drivers have to map appropriate window to access this
14062 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
14065 * If value is 1, this register is located in GRC address space.
14066 * Drivers have to map appropriate window to access this
14069 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
14072 * If value is 2, this register is located in first BAR address
14073 * space. Drivers have to map appropriate window to access this
14076 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
14079 * If value is 3, this register is located in second BAR address
14080 * space. Drivers have to map appropriate window to access this
14083 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
14085 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
14086 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
14087 /* Upper 30bits of the register address. */
14088 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
14089 UINT32_C(0xfffffffc)
14090 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
14093 * FW reset counter.
14094 * Lower 2 bits indicates address space location and upper 30 bits
14095 * indicates actual address.
14096 * A value of 0xFFFF-FFFF indicates this register does not exist.
14098 uint32_t fw_reset_cnt_reg;
14099 /* Lower 2 bits indicates address space location. */
14100 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
14102 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
14105 * If value is 0, this register is located in PCIe config space.
14106 * Drivers have to map appropriate window to access this
14109 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
14112 * If value is 1, this register is located in GRC address space.
14113 * Drivers have to map appropriate window to access this
14116 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
14119 * If value is 2, this register is located in first BAR address
14120 * space. Drivers have to map appropriate window to access this
14123 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
14126 * If value is 3, this register is located in second BAR address
14127 * space. Drivers have to map appropriate window to access this
14130 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
14132 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
14133 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
14134 /* Upper 30bits of the register address. */
14135 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
14136 UINT32_C(0xfffffffc)
14137 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
14140 * Reset Inprogress Register address for PFs.
14141 * Lower 2 bits indicates address space location and upper 30 bits
14142 * indicates actual address.
14143 * A value of 0xFFFF-FFFF indicates this register does not exist.
14145 uint32_t reset_inprogress_reg;
14146 /* Lower 2 bits indicates address space location. */
14147 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
14149 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
14152 * If value is 0, this register is located in PCIe config space.
14153 * Drivers have to map appropriate window to access this
14156 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
14159 * If value is 1, this register is located in GRC address space.
14160 * Drivers have to map appropriate window to access this
14163 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
14166 * If value is 2, this register is located in first BAR address
14167 * space. Drivers have to map appropriate window to access this
14170 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
14173 * If value is 3, this register is located in second BAR address
14174 * space. Drivers have to map appropriate window to access this
14177 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
14179 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
14180 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
14181 /* Upper 30bits of the register address. */
14182 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
14183 UINT32_C(0xfffffffc)
14184 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
14186 /* This field indicates the mask value for reset_inprogress_reg. */
14187 uint32_t reset_inprogress_reg_mask;
14188 uint8_t unused_0[3];
14190 * Array of registers and value count to reset the Chip
14191 * Each array count has reset_reg, reset_reg_val, delay_after_reset
14192 * in TLV format. Depending upon Chip type, number of reset registers
14193 * will vary. Drivers have to write reset_reg_val in the reset_reg
14194 * location in the same sequence in order to recover from a fatal
14197 uint8_t reg_array_cnt;
14200 * Lower 2 bits indicates address space location and upper 30 bits
14201 * indicates actual address.
14202 * A value of 0xFFFF-FFFF indicates this register does not exist.
14204 uint32_t reset_reg[16];
14205 /* Lower 2 bits indicates address space location. */
14206 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
14208 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
14210 * If value is 0, this register is located in PCIe config space.
14211 * Drivers have to map appropriate window to access this
14214 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
14217 * If value is 1, this register is located in GRC address space.
14218 * Drivers have to map appropriate window to access this
14221 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
14224 * If value is 2, this register is located in first BAR address
14225 * space. Drivers have to map appropriate window to access this
14228 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
14231 * If value is 3, this register is located in second BAR address
14232 * space. Drivers have to map appropriate window to access this
14235 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
14237 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
14238 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
14239 /* Upper 30bits of the register address. */
14240 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
14241 UINT32_C(0xfffffffc)
14242 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
14243 /* Value to be written in reset_reg to reset the controller. */
14244 uint32_t reset_reg_val[16];
14246 * This value is in units of 1msec.
14247 * Typical value would be 10 to indicate 10msec.
14248 * Some of the operations like Core reset require delay before
14249 * accessing PCIE MMIO register space.
14250 * If this value is non-zero, drivers have to wait for
14251 * this much time after writing reset_reg_val in reset_reg.
14253 uint8_t delay_after_reset[16];
14255 * Error recovery counter.
14256 * Lower 2 bits indicates address space location and upper 30 bits
14257 * indicates actual address.
14258 * A value of 0xFFFF-FFFF indicates this register does not exist.
14260 uint32_t err_recovery_cnt_reg;
14261 /* Lower 2 bits indicates address space location. */
14262 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \
14264 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \
14267 * If value is 0, this register is located in PCIe config space.
14268 * Drivers have to map appropriate window to access this
14271 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \
14274 * If value is 1, this register is located in GRC address space.
14275 * Drivers have to map appropriate window to access this
14278 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \
14281 * If value is 2, this register is located in first BAR address
14282 * space. Drivers have to map appropriate window to access this
14285 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \
14288 * If value is 3, this register is located in second BAR address
14289 * space. Drivers have to map appropriate window to access this
14292 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \
14294 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \
14295 HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
14296 /* Upper 30bits of the register address. */
14297 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \
14298 UINT32_C(0xfffffffc)
14299 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \
14301 uint8_t unused_1[3];
14303 * This field is used in Output records to indicate that the output
14304 * is completely written to RAM. This field should be read as '1'
14305 * to indicate that the output has been completely written.
14306 * When writing a command completion or response to an internal
14307 * processor, the order of writes has to be such that this field
14313 /***********************
14314 * hwrm_func_vlan_qcfg *
14315 ***********************/
14318 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
14319 struct hwrm_func_vlan_qcfg_input {
14320 /* The HWRM command request type. */
14323 * The completion ring to send the completion event on. This should
14324 * be the NQ ID returned from the `nq_alloc` HWRM command.
14326 uint16_t cmpl_ring;
14328 * The sequence ID is used by the driver for tracking multiple
14329 * commands. This ID is treated as opaque data by the firmware and
14330 * the value is returned in the `hwrm_resp_hdr` upon completion.
14334 * The target ID of the command:
14335 * * 0x0-0xFFF8 - The function ID
14336 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14337 * * 0xFFFD - Reserved for user-space HWRM interface
14340 uint16_t target_id;
14342 * A physical address pointer pointing to a host buffer that the
14343 * command's response data will be written. This can be either a host
14344 * physical address (HPA) or a guest physical address (GPA) and must
14345 * point to a physically contiguous block of memory.
14347 uint64_t resp_addr;
14349 * Function ID of the function that is being
14351 * If set to 0xFF... (All Fs), then the configuration is
14352 * for the requesting function.
14355 uint8_t unused_0[6];
14358 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
14359 struct hwrm_func_vlan_qcfg_output {
14360 /* The specific error status for the command. */
14361 uint16_t error_code;
14362 /* The HWRM command request type. */
14364 /* The sequence ID from the original command. */
14366 /* The length of the response data in number of bytes. */
14369 /* S-TAG VLAN identifier configured for the function. */
14371 /* S-TAG PCP value configured for the function. */
14375 * S-TAG TPID value configured for the function. This field is specified in
14376 * network byte order.
14378 uint16_t stag_tpid;
14379 /* C-TAG VLAN identifier configured for the function. */
14381 /* C-TAG PCP value configured for the function. */
14385 * C-TAG TPID value configured for the function. This field is specified in
14386 * network byte order.
14388 uint16_t ctag_tpid;
14393 uint8_t unused_3[3];
14395 * This field is used in Output records to indicate that the output
14396 * is completely written to RAM. This field should be read as '1'
14397 * to indicate that the output has been completely written.
14398 * When writing a command completion or response to an internal processor,
14399 * the order of writes has to be such that this field is written last.
14404 /**********************
14405 * hwrm_func_vlan_cfg *
14406 **********************/
14409 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
14410 struct hwrm_func_vlan_cfg_input {
14411 /* The HWRM command request type. */
14414 * The completion ring to send the completion event on. This should
14415 * be the NQ ID returned from the `nq_alloc` HWRM command.
14417 uint16_t cmpl_ring;
14419 * The sequence ID is used by the driver for tracking multiple
14420 * commands. This ID is treated as opaque data by the firmware and
14421 * the value is returned in the `hwrm_resp_hdr` upon completion.
14425 * The target ID of the command:
14426 * * 0x0-0xFFF8 - The function ID
14427 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14428 * * 0xFFFD - Reserved for user-space HWRM interface
14431 uint16_t target_id;
14433 * A physical address pointer pointing to a host buffer that the
14434 * command's response data will be written. This can be either a host
14435 * physical address (HPA) or a guest physical address (GPA) and must
14436 * point to a physically contiguous block of memory.
14438 uint64_t resp_addr;
14440 * Function ID of the function that is being
14442 * If set to 0xFF... (All Fs), then the configuration is
14443 * for the requesting function.
14446 uint8_t unused_0[2];
14449 * This bit must be '1' for the stag_vid field to be
14452 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
14454 * This bit must be '1' for the ctag_vid field to be
14457 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
14459 * This bit must be '1' for the stag_pcp field to be
14462 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
14464 * This bit must be '1' for the ctag_pcp field to be
14467 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
14469 * This bit must be '1' for the stag_tpid field to be
14472 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
14474 * This bit must be '1' for the ctag_tpid field to be
14477 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
14478 /* S-TAG VLAN identifier configured for the function. */
14480 /* S-TAG PCP value configured for the function. */
14484 * S-TAG TPID value configured for the function. This field is specified in
14485 * network byte order.
14487 uint16_t stag_tpid;
14488 /* C-TAG VLAN identifier configured for the function. */
14490 /* C-TAG PCP value configured for the function. */
14494 * C-TAG TPID value configured for the function. This field is specified in
14495 * network byte order.
14497 uint16_t ctag_tpid;
14502 uint8_t unused_3[4];
14505 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
14506 struct hwrm_func_vlan_cfg_output {
14507 /* The specific error status for the command. */
14508 uint16_t error_code;
14509 /* The HWRM command request type. */
14511 /* The sequence ID from the original command. */
14513 /* The length of the response data in number of bytes. */
14515 uint8_t unused_0[7];
14517 * This field is used in Output records to indicate that the output
14518 * is completely written to RAM. This field should be read as '1'
14519 * to indicate that the output has been completely written.
14520 * When writing a command completion or response to an internal processor,
14521 * the order of writes has to be such that this field is written last.
14526 /*******************************
14527 * hwrm_func_vf_vnic_ids_query *
14528 *******************************/
14531 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
14532 struct hwrm_func_vf_vnic_ids_query_input {
14533 /* The HWRM command request type. */
14536 * The completion ring to send the completion event on. This should
14537 * be the NQ ID returned from the `nq_alloc` HWRM command.
14539 uint16_t cmpl_ring;
14541 * The sequence ID is used by the driver for tracking multiple
14542 * commands. This ID is treated as opaque data by the firmware and
14543 * the value is returned in the `hwrm_resp_hdr` upon completion.
14547 * The target ID of the command:
14548 * * 0x0-0xFFF8 - The function ID
14549 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14550 * * 0xFFFD - Reserved for user-space HWRM interface
14553 uint16_t target_id;
14555 * A physical address pointer pointing to a host buffer that the
14556 * command's response data will be written. This can be either a host
14557 * physical address (HPA) or a guest physical address (GPA) and must
14558 * point to a physically contiguous block of memory.
14560 uint64_t resp_addr;
14562 * This value is used to identify a Virtual Function (VF).
14563 * The scope of VF ID is local within a PF.
14566 uint8_t unused_0[2];
14567 /* Max number of vnic ids in vnic id table */
14568 uint32_t max_vnic_id_cnt;
14569 /* This is the address for VF VNIC ID table */
14570 uint64_t vnic_id_tbl_addr;
14573 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
14574 struct hwrm_func_vf_vnic_ids_query_output {
14575 /* The specific error status for the command. */
14576 uint16_t error_code;
14577 /* The HWRM command request type. */
14579 /* The sequence ID from the original command. */
14581 /* The length of the response data in number of bytes. */
14584 * Actual number of vnic ids
14586 * Each VNIC ID is written as a 32-bit number.
14588 uint32_t vnic_id_cnt;
14589 uint8_t unused_0[3];
14591 * This field is used in Output records to indicate that the output
14592 * is completely written to RAM. This field should be read as '1'
14593 * to indicate that the output has been completely written.
14594 * When writing a command completion or response to an internal processor,
14595 * the order of writes has to be such that this field is written last.
14600 /***********************
14601 * hwrm_func_vf_bw_cfg *
14602 ***********************/
14605 /* hwrm_func_vf_bw_cfg_input (size:960b/120B) */
14606 struct hwrm_func_vf_bw_cfg_input {
14607 /* The HWRM command request type. */
14610 * The completion ring to send the completion event on. This should
14611 * be the NQ ID returned from the `nq_alloc` HWRM command.
14613 uint16_t cmpl_ring;
14615 * The sequence ID is used by the driver for tracking multiple
14616 * commands. This ID is treated as opaque data by the firmware and
14617 * the value is returned in the `hwrm_resp_hdr` upon completion.
14621 * The target ID of the command:
14622 * * 0x0-0xFFF8 - The function ID
14623 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14624 * * 0xFFFD - Reserved for user-space HWRM interface
14627 uint16_t target_id;
14629 * A physical address pointer pointing to a host buffer that the
14630 * command's response data will be written. This can be either a host
14631 * physical address (HPA) or a guest physical address (GPA) and must
14632 * point to a physically contiguous block of memory.
14634 uint64_t resp_addr;
14636 * The number of VF functions that are being configured.
14637 * The cmd space allows up to 50 VFs' BW to be configured with one cmd.
14640 uint16_t unused[3];
14641 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14643 /* The physical VF id the adjustment will be made to. */
14644 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14645 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
14647 * This field configures the rate scale percentage of the VF as specified
14648 * by the physical VF id.
14650 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
14651 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12
14652 /* 0% of the max tx rate */
14653 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \
14654 (UINT32_C(0x0) << 12)
14655 /* 6.66% of the max tx rate */
14656 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \
14657 (UINT32_C(0x1) << 12)
14658 /* 13.33% of the max tx rate */
14659 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \
14660 (UINT32_C(0x2) << 12)
14661 /* 20% of the max tx rate */
14662 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \
14663 (UINT32_C(0x3) << 12)
14664 /* 26.66% of the max tx rate */
14665 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \
14666 (UINT32_C(0x4) << 12)
14667 /* 33% of the max tx rate */
14668 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \
14669 (UINT32_C(0x5) << 12)
14670 /* 40% of the max tx rate */
14671 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \
14672 (UINT32_C(0x6) << 12)
14673 /* 46.66% of the max tx rate */
14674 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \
14675 (UINT32_C(0x7) << 12)
14676 /* 53.33% of the max tx rate */
14677 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \
14678 (UINT32_C(0x8) << 12)
14679 /* 60% of the max tx rate */
14680 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \
14681 (UINT32_C(0x9) << 12)
14682 /* 66.66% of the max tx rate */
14683 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \
14684 (UINT32_C(0xa) << 12)
14685 /* 53.33% of the max tx rate */
14686 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \
14687 (UINT32_C(0xb) << 12)
14688 /* 80% of the max tx rate */
14689 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \
14690 (UINT32_C(0xc) << 12)
14691 /* 86.66% of the max tx rate */
14692 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \
14693 (UINT32_C(0xd) << 12)
14694 /* 93.33% of the max tx rate */
14695 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \
14696 (UINT32_C(0xe) << 12)
14697 /* 100% of the max tx rate */
14698 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \
14699 (UINT32_C(0xf) << 12)
14700 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \
14701 HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100
14704 /* hwrm_func_vf_bw_cfg_output (size:128b/16B) */
14705 struct hwrm_func_vf_bw_cfg_output {
14706 /* The specific error status for the command. */
14707 uint16_t error_code;
14708 /* The HWRM command request type. */
14710 /* The sequence ID from the original command. */
14712 /* The length of the response data in number of bytes. */
14714 uint8_t unused_0[7];
14716 * This field is used in Output records to indicate that the output
14717 * is completely written to RAM. This field should be read as '1'
14718 * to indicate that the output has been completely written.
14719 * When writing a command completion or response to an internal processor,
14720 * the order of writes has to be such that this field is written last.
14725 /************************
14726 * hwrm_func_vf_bw_qcfg *
14727 ************************/
14730 /* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */
14731 struct hwrm_func_vf_bw_qcfg_input {
14732 /* The HWRM command request type. */
14735 * The completion ring to send the completion event on. This should
14736 * be the NQ ID returned from the `nq_alloc` HWRM command.
14738 uint16_t cmpl_ring;
14740 * The sequence ID is used by the driver for tracking multiple
14741 * commands. This ID is treated as opaque data by the firmware and
14742 * the value is returned in the `hwrm_resp_hdr` upon completion.
14746 * The target ID of the command:
14747 * * 0x0-0xFFF8 - The function ID
14748 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14749 * * 0xFFFD - Reserved for user-space HWRM interface
14752 uint16_t target_id;
14754 * A physical address pointer pointing to a host buffer that the
14755 * command's response data will be written. This can be either a host
14756 * physical address (HPA) or a guest physical address (GPA) and must
14757 * point to a physically contiguous block of memory.
14759 uint64_t resp_addr;
14761 * The number of VF functions that are being queried.
14762 * The inline response space allows the host to query up to 50 VFs'
14763 * rate scale percentage
14766 uint16_t unused[3];
14767 /* These 16-bit fields contain the VF fid */
14769 /* The physical VF id of interest */
14770 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
14771 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
14774 /* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */
14775 struct hwrm_func_vf_bw_qcfg_output {
14776 /* The specific error status for the command. */
14777 uint16_t error_code;
14778 /* The HWRM command request type. */
14780 /* The sequence ID from the original command. */
14782 /* The length of the response data in number of bytes. */
14785 * The number of VF functions that are being queried.
14786 * The inline response space allows the host to query up to 50 VFs' rate
14790 uint16_t unused[3];
14791 /* These 16-bit fields contain the VF fid and the rate scale percentage. */
14793 /* The physical VF id the adjustment will be made to. */
14794 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
14795 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
14797 * This field configures the rate scale percentage of the VF as specified
14798 * by the physical VF id.
14800 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
14801 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12
14802 /* 0% of the max tx rate */
14803 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \
14804 (UINT32_C(0x0) << 12)
14805 /* 6.66% of the max tx rate */
14806 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \
14807 (UINT32_C(0x1) << 12)
14808 /* 13.33% of the max tx rate */
14809 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \
14810 (UINT32_C(0x2) << 12)
14811 /* 20% of the max tx rate */
14812 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \
14813 (UINT32_C(0x3) << 12)
14814 /* 26.66% of the max tx rate */
14815 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \
14816 (UINT32_C(0x4) << 12)
14817 /* 33% of the max tx rate */
14818 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \
14819 (UINT32_C(0x5) << 12)
14820 /* 40% of the max tx rate */
14821 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \
14822 (UINT32_C(0x6) << 12)
14823 /* 46.66% of the max tx rate */
14824 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \
14825 (UINT32_C(0x7) << 12)
14826 /* 53.33% of the max tx rate */
14827 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \
14828 (UINT32_C(0x8) << 12)
14829 /* 60% of the max tx rate */
14830 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \
14831 (UINT32_C(0x9) << 12)
14832 /* 66.66% of the max tx rate */
14833 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \
14834 (UINT32_C(0xa) << 12)
14835 /* 53.33% of the max tx rate */
14836 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \
14837 (UINT32_C(0xb) << 12)
14838 /* 80% of the max tx rate */
14839 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \
14840 (UINT32_C(0xc) << 12)
14841 /* 86.66% of the max tx rate */
14842 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \
14843 (UINT32_C(0xd) << 12)
14844 /* 93.33% of the max tx rate */
14845 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \
14846 (UINT32_C(0xe) << 12)
14847 /* 100% of the max tx rate */
14848 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \
14849 (UINT32_C(0xf) << 12)
14850 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \
14851 HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100
14852 uint8_t unused_0[7];
14854 * This field is used in Output records to indicate that the output
14855 * is completely written to RAM. This field should be read as '1'
14856 * to indicate that the output has been completely written.
14857 * When writing a command completion or response to an internal processor,
14858 * the order of writes has to be such that this field is written last.
14863 /***************************
14864 * hwrm_func_drv_if_change *
14865 ***************************/
14868 /* hwrm_func_drv_if_change_input (size:192b/24B) */
14869 struct hwrm_func_drv_if_change_input {
14870 /* The HWRM command request type. */
14873 * The completion ring to send the completion event on. This should
14874 * be the NQ ID returned from the `nq_alloc` HWRM command.
14876 uint16_t cmpl_ring;
14878 * The sequence ID is used by the driver for tracking multiple
14879 * commands. This ID is treated as opaque data by the firmware and
14880 * the value is returned in the `hwrm_resp_hdr` upon completion.
14884 * The target ID of the command:
14885 * * 0x0-0xFFF8 - The function ID
14886 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14887 * * 0xFFFD - Reserved for user-space HWRM interface
14890 uint16_t target_id;
14892 * A physical address pointer pointing to a host buffer that the
14893 * command's response data will be written. This can be either a host
14894 * physical address (HPA) or a guest physical address (GPA) and must
14895 * point to a physically contiguous block of memory.
14897 uint64_t resp_addr;
14900 * When this bit is '1', the function driver is indicating
14901 * that the IF state is changing to UP state. The call should
14902 * be made at the beginning of the driver's open call before
14903 * resources are allocated. After making the call, the driver
14904 * should check the response to see if any resources may have
14905 * changed (see the response below). If the driver fails
14906 * the open call, the driver should make this call again with
14907 * this bit cleared to indicate that the IF state is not UP.
14908 * During the driver's close call when the IF state is changing
14909 * to DOWN, the driver should make this call with the bit cleared
14910 * after all resources have been freed.
14912 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
14916 /* hwrm_func_drv_if_change_output (size:128b/16B) */
14917 struct hwrm_func_drv_if_change_output {
14918 /* The specific error status for the command. */
14919 uint16_t error_code;
14920 /* The HWRM command request type. */
14922 /* The sequence ID from the original command. */
14924 /* The length of the response data in number of bytes. */
14928 * When this bit is '1', it indicates that the resources reserved
14929 * for this function may have changed. The driver should check
14930 * resource capabilities and reserve resources again before
14931 * allocating resources.
14933 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
14936 * When this bit is '1', it indicates that the firmware got changed / reset.
14937 * The driver should do complete re-initialization when that bit is set.
14939 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
14941 uint8_t unused_0[3];
14943 * This field is used in Output records to indicate that the output
14944 * is completely written to RAM. This field should be read as '1'
14945 * to indicate that the output has been completely written.
14946 * When writing a command completion or response to an internal processor,
14947 * the order of writes has to be such that this field is written last.
14952 /*******************************
14953 * hwrm_func_host_pf_ids_query *
14954 *******************************/
14957 /* hwrm_func_host_pf_ids_query_input (size:192b/24B) */
14958 struct hwrm_func_host_pf_ids_query_input {
14959 /* The HWRM command request type. */
14962 * The completion ring to send the completion event on. This should
14963 * be the NQ ID returned from the `nq_alloc` HWRM command.
14965 uint16_t cmpl_ring;
14967 * The sequence ID is used by the driver for tracking multiple
14968 * commands. This ID is treated as opaque data by the firmware and
14969 * the value is returned in the `hwrm_resp_hdr` upon completion.
14973 * The target ID of the command:
14974 * * 0x0-0xFFF8 - The function ID
14975 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14976 * * 0xFFFD - Reserved for user-space HWRM interface
14979 uint16_t target_id;
14981 * A physical address pointer pointing to a host buffer that the
14982 * command's response data will be written. This can be either a host
14983 * physical address (HPA) or a guest physical address (GPA) and must
14984 * point to a physically contiguous block of memory.
14986 uint64_t resp_addr;
14989 * # If this bit is set to '1', the query will contain PF(s)
14990 * belongs to SOC host.
14992 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
14994 * # If this bit is set to '1', the query will contain PF(s)
14995 * belongs to EP0 host.
14997 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
14999 * # If this bit is set to '1', the query will contain PF(s)
15000 * belongs to EP1 host.
15002 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
15004 * # If this bit is set to '1', the query will contain PF(s)
15005 * belongs to EP2 host.
15007 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
15009 * # If this bit is set to '1', the query will contain PF(s)
15010 * belongs to EP3 host.
15012 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
15014 * This provides a filter of what PF(s) will be returned in the
15019 * all available PF(s) belong to the host(s) (defined in the
15020 * host field). This includes the hidden PFs.
15022 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
15024 * all available PF(s) belong to the host(s) (defined in the
15025 * host field) that is available for L2 traffic.
15027 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
15029 * all available PF(s) belong to the host(s) (defined in the
15030 * host field) that is available for ROCE traffic.
15032 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
15033 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_LAST \
15034 HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE
15035 uint8_t unused_1[6];
15038 /* hwrm_func_host_pf_ids_query_output (size:128b/16B) */
15039 struct hwrm_func_host_pf_ids_query_output {
15040 /* The specific error status for the command. */
15041 uint16_t error_code;
15042 /* The HWRM command request type. */
15044 /* The sequence ID from the original command. */
15046 /* The length of the response data in number of bytes. */
15048 /* This provides the first PF ID of the device. */
15049 uint16_t first_pf_id;
15050 uint16_t pf_ordinal_mask;
15052 * When this bit is '1', it indicates first PF belongs to one of
15053 * the hosts defined in the input request.
15055 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 \
15058 * When this bit is '1', it indicates 2nd PF belongs to one of the
15059 * hosts defined in the input request.
15061 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 \
15064 * When this bit is '1', it indicates 3rd PF belongs to one of the
15065 * hosts defined in the input request.
15067 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 \
15070 * When this bit is '1', it indicates 4th PF belongs to one of the
15071 * hosts defined in the input request.
15073 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 \
15076 * When this bit is '1', it indicates 5th PF belongs to one of the
15077 * hosts defined in the input request.
15079 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 \
15082 * When this bit is '1', it indicates 6th PF belongs to one of the
15083 * hosts defined in the input request.
15085 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 \
15088 * When this bit is '1', it indicates 7th PF belongs to one of the
15089 * hosts defined in the input request.
15091 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 \
15094 * When this bit is '1', it indicates 8th PF belongs to one of the
15095 * hosts defined in the input request.
15097 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 \
15100 * When this bit is '1', it indicates 9th PF belongs to one of the
15101 * hosts defined in the input request.
15103 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 \
15106 * When this bit is '1', it indicates 10th PF belongs to one of the
15107 * hosts defined in the input request.
15109 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 \
15112 * When this bit is '1', it indicates 11th PF belongs to one of the
15113 * hosts defined in the input request.
15115 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 \
15118 * When this bit is '1', it indicates 12th PF belongs to one of the
15119 * hosts defined in the input request.
15121 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 \
15124 * When this bit is '1', it indicates 13th PF belongs to one of the
15125 * hosts defined in the input request.
15127 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 \
15130 * When this bit is '1', it indicates 14th PF belongs to one of the
15131 * hosts defined in the input request.
15133 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 \
15136 * When this bit is '1', it indicates 15th PF belongs to one of the
15137 * hosts defined in the input request.
15139 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 \
15142 * When this bit is '1', it indicates 16th PF belongs to one of the
15143 * hosts defined in the input request.
15145 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 \
15147 uint8_t unused_1[3];
15149 * This field is used in Output records to indicate that the output
15150 * is completely written to RAM. This field should be read as '1'
15151 * to indicate that the output has been completely written.
15152 * When writing a command completion or response to an internal processor,
15153 * the order of writes has to be such that this field is written last.
15158 /*********************
15159 * hwrm_port_phy_cfg *
15160 *********************/
15163 /* hwrm_port_phy_cfg_input (size:448b/56B) */
15164 struct hwrm_port_phy_cfg_input {
15165 /* The HWRM command request type. */
15168 * The completion ring to send the completion event on. This should
15169 * be the NQ ID returned from the `nq_alloc` HWRM command.
15171 uint16_t cmpl_ring;
15173 * The sequence ID is used by the driver for tracking multiple
15174 * commands. This ID is treated as opaque data by the firmware and
15175 * the value is returned in the `hwrm_resp_hdr` upon completion.
15179 * The target ID of the command:
15180 * * 0x0-0xFFF8 - The function ID
15181 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15182 * * 0xFFFD - Reserved for user-space HWRM interface
15185 uint16_t target_id;
15187 * A physical address pointer pointing to a host buffer that the
15188 * command's response data will be written. This can be either a host
15189 * physical address (HPA) or a guest physical address (GPA) and must
15190 * point to a physically contiguous block of memory.
15192 uint64_t resp_addr;
15195 * When this bit is set to '1', the PHY for the port shall
15198 * # If this bit is set to 1, then the HWRM shall reset the
15199 * PHY after applying PHY configuration changes specified
15201 * # In order to guarantee that PHY configuration changes
15202 * specified in this command take effect, the HWRM
15203 * client should set this flag to 1.
15204 * # If this bit is not set to 1, then the HWRM may reset
15205 * the PHY depending on the current PHY configuration and
15206 * settings specified in this command.
15208 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
15210 /* deprecated bit. Do not use!!! */
15211 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
15214 * When this bit is set to '1', and the force_pam4_link_speed
15215 * bit in the 'enables' field is '0', the link shall be forced
15216 * to the force_link_speed value.
15218 * When this bit is set to '1', and the force_pam4_link_speed
15219 * bit in the 'enables' field is '1', the link shall be forced
15220 * to the force_pam4_link_speed value.
15222 * When this bit is set to '1', the HWRM client should
15223 * not enable any of the auto negotiation related
15224 * fields represented by auto_XXX fields in this command.
15225 * When this bit is set to '1' and the HWRM client has
15226 * enabled a auto_XXX field in this command, then the
15227 * HWRM shall ignore the enabled auto_XXX field.
15229 * When this bit is set to zero, the link
15230 * shall be allowed to autoneg.
15232 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
15235 * When this bit is set to '1', the auto-negotiation process
15236 * shall be restarted on the link.
15238 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
15241 * When this bit is set to '1', Energy Efficient Ethernet
15242 * (EEE) is requested to be enabled on this link.
15243 * If EEE is not supported on this port, then this flag
15244 * shall be ignored by the HWRM.
15246 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
15249 * When this bit is set to '1', Energy Efficient Ethernet
15250 * (EEE) is requested to be disabled on this link.
15251 * If EEE is not supported on this port, then this flag
15252 * shall be ignored by the HWRM.
15254 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
15257 * When this bit is set to '1' and EEE is enabled on this
15258 * link, then TX LPI is requested to be enabled on the link.
15259 * If EEE is not supported on this port, then this flag
15260 * shall be ignored by the HWRM.
15261 * If EEE is disabled on this port, then this flag shall be
15262 * ignored by the HWRM.
15264 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
15267 * When this bit is set to '1' and EEE is enabled on this
15268 * link, then TX LPI is requested to be disabled on the link.
15269 * If EEE is not supported on this port, then this flag
15270 * shall be ignored by the HWRM.
15271 * If EEE is disabled on this port, then this flag shall be
15272 * ignored by the HWRM.
15274 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
15277 * When set to 1, then the HWRM shall enable FEC autonegotitation
15278 * on this port if supported.
15279 * When set to 0, then this flag shall be ignored.
15280 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15283 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
15286 * When set to 1, then the HWRM shall disable FEC autonegotiation
15287 * on this port if supported.
15288 * When set to 0, then this flag shall be ignored.
15289 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
15292 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
15295 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
15296 * on this port if supported.
15297 * When set to 0, then this flag shall be ignored.
15298 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15301 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
15304 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
15305 * on this port if supported.
15306 * When set to 0, then this flag shall be ignored.
15307 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
15310 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
15313 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
15314 * on this port if supported.
15315 * When set to 0, then this flag shall be ignored.
15316 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15319 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
15322 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
15323 * on this port if supported.
15324 * When set to 0, then this flag shall be ignored.
15325 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
15328 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
15331 * When this bit is set to '1', the link shall be forced to
15334 * # When this bit is set to '1", all other
15335 * command input settings related to the link speed shall
15337 * Once the link state is forced down, it can be
15338 * explicitly cleared from that state by setting this flag
15340 * # If this flag is set to '0', then the link shall be
15341 * cleared from forced down state if the link is in forced
15343 * There may be conditions (e.g. out-of-band or sideband
15344 * configuration changes for the link) outside the scope
15345 * of the HWRM implementation that may clear forced down
15348 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
15352 * This bit must be '1' for the auto_mode field to be
15355 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
15358 * This bit must be '1' for the auto_duplex field to be
15361 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
15364 * This bit must be '1' for the auto_pause field to be
15367 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
15370 * This bit must be '1' for the auto_link_speed field to be
15373 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
15376 * This bit must be '1' for the auto_link_speed_mask field to be
15379 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
15382 * This bit must be '1' for the wirespeed field to be
15385 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
15388 * This bit must be '1' for the lpbk field to be
15391 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
15394 * This bit must be '1' for the preemphasis field to be
15397 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
15400 * This bit must be '1' for the force_pause field to be
15403 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
15406 * This bit must be '1' for the eee_link_speed_mask field to be
15409 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
15412 * This bit must be '1' for the tx_lpi_timer field to be
15415 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
15417 /* Port ID of port that is to be configured. */
15420 * This is the speed that will be used if the force
15421 * bit is '1'. If unsupported speed is selected, an error
15422 * will be generated.
15424 uint16_t force_link_speed;
15425 /* 100Mb link speed */
15426 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15427 /* 1Gb link speed */
15428 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15429 /* 2Gb link speed */
15430 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15431 /* 25Gb link speed */
15432 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15433 /* 10Gb link speed */
15434 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15435 /* 20Mb link speed */
15436 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15437 /* 25Gb link speed */
15438 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15439 /* 40Gb link speed */
15440 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
15441 /* 50Gb link speed */
15442 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
15443 /* 100Gb link speed */
15444 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
15445 /* 200Gb link speed */
15446 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
15447 /* 10Mb link speed */
15448 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
15449 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
15450 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
15452 * This value is used to identify what autoneg mode is
15453 * used when the link speed is not being forced.
15456 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15457 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
15458 /* Select all possible speeds for autoneg mode. */
15459 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15461 * Select only the auto_link_speed speed for autoneg mode. This mode has
15462 * been DEPRECATED. An HWRM client should not use this mode.
15464 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15466 * Select the auto_link_speed or any speed below that speed for autoneg.
15467 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15469 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15471 * Select the speeds based on the corresponding link speed mask value
15472 * that is provided.
15474 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15475 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
15476 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
15478 * This is the duplex setting that will be used if the autoneg_mode
15479 * is "one_speed" or "one_or_below".
15481 uint8_t auto_duplex;
15482 /* Half Duplex will be requested. */
15483 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
15484 /* Full duplex will be requested. */
15485 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
15486 /* Both Half and Full dupex will be requested. */
15487 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
15488 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
15489 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
15491 * This value is used to configure the pause that will be
15492 * used for autonegotiation.
15493 * Add text on the usage of auto_pause and force_pause.
15495 uint8_t auto_pause;
15497 * When this bit is '1', Generation of tx pause messages
15498 * has been requested. Disabled otherwise.
15500 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
15503 * When this bit is '1', Reception of rx pause messages
15504 * has been requested. Disabled otherwise.
15506 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
15509 * When set to 1, the advertisement of pause is enabled.
15511 * # When the auto_mode is not set to none and this flag is
15512 * set to 1, then the auto_pause bits on this port are being
15513 * advertised and autoneg pause results are being interpreted.
15514 * # When the auto_mode is not set to none and this
15515 * flag is set to 0, the pause is forced as indicated in
15516 * force_pause, and also advertised as auto_pause bits, but
15517 * the autoneg results are not interpreted since the pause
15518 * configuration is being forced.
15519 * # When the auto_mode is set to none and this flag is set to
15520 * 1, auto_pause bits should be ignored and should be set to 0.
15522 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
15526 * This is the speed that will be used if the autoneg_mode
15527 * is "one_speed" or "one_or_below". If an unsupported speed
15528 * is selected, an error will be generated.
15530 uint16_t auto_link_speed;
15531 /* 100Mb link speed */
15532 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
15533 /* 1Gb link speed */
15534 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
15535 /* 2Gb link speed */
15536 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
15537 /* 25Gb link speed */
15538 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
15539 /* 10Gb link speed */
15540 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
15541 /* 20Mb link speed */
15542 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
15543 /* 25Gb link speed */
15544 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
15545 /* 40Gb link speed */
15546 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
15547 /* 50Gb link speed */
15548 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
15549 /* 100Gb link speed */
15550 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
15551 /* 200Gb link speed */
15552 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
15553 /* 10Mb link speed */
15554 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
15555 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
15556 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
15558 * This is a mask of link speeds that will be used if
15559 * autoneg_mode is "mask". If unsupported speed is enabled
15560 * an error will be generated.
15562 uint16_t auto_link_speed_mask;
15563 /* 100Mb link speed (Half-duplex) */
15564 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
15566 /* 100Mb link speed (Full-duplex) */
15567 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
15569 /* 1Gb link speed (Half-duplex) */
15570 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
15572 /* 1Gb link speed (Full-duplex) */
15573 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
15575 /* 2Gb link speed */
15576 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
15578 /* 25Gb link speed */
15579 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
15581 /* 10Gb link speed */
15582 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
15584 /* 20Gb link speed */
15585 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
15587 /* 25Gb link speed */
15588 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
15590 /* 40Gb link speed */
15591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
15593 /* 50Gb link speed */
15594 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
15596 /* 100Gb link speed */
15597 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
15599 /* 10Mb link speed (Half-duplex) */
15600 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
15602 /* 10Mb link speed (Full-duplex) */
15603 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
15605 /* 200Gb link speed */
15606 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
15608 /* This value controls the wirespeed feature. */
15610 /* Wirespeed feature is disabled. */
15611 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
15612 /* Wirespeed feature is enabled. */
15613 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
15614 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
15615 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
15616 /* This value controls the loopback setting for the PHY. */
15618 /* No loopback is selected. Normal operation. */
15619 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
15621 * The HW will be configured with local loopback such that
15622 * host data is sent back to the host without modification.
15624 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
15626 * The HW will be configured with remote loopback such that
15627 * port logic will send packets back out the transmitter that
15630 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
15632 * The HW will be configured with external loopback such that
15633 * host data is sent on the transmitter and based on the external
15634 * loopback connection the data will be received without modification.
15636 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
15637 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
15638 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
15640 * This value is used to configure the pause that will be
15641 * used for force mode.
15643 uint8_t force_pause;
15645 * When this bit is '1', Generation of tx pause messages
15646 * is supported. Disabled otherwise.
15648 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
15650 * When this bit is '1', Reception of rx pause messages
15651 * is supported. Disabled otherwise.
15653 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
15656 * This value controls the pre-emphasis to be used for the
15657 * link. Driver should not set this value (use
15658 * enable.preemphasis = 0) unless driver is sure of setting.
15659 * Normally HWRM FW will determine proper pre-emphasis.
15661 uint32_t preemphasis;
15663 * Setting for link speed mask that is used to
15664 * advertise speeds during autonegotiation when EEE is enabled.
15665 * This field is valid only when EEE is enabled.
15666 * The speeds specified in this field shall be a subset of
15667 * speeds specified in auto_link_speed_mask.
15668 * If EEE is enabled,then at least one speed shall be provided
15671 uint16_t eee_link_speed_mask;
15673 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
15675 /* 100Mb link speed (Full-duplex) */
15676 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
15679 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
15681 /* 1Gb link speed (Full-duplex) */
15682 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
15685 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
15688 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
15690 /* 10Gb link speed */
15691 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
15694 * This is the speed that will be used if the force and force_pam4
15695 * bits are '1'. If unsupported speed is selected, an error
15696 * will be generated.
15698 uint16_t force_pam4_link_speed;
15699 /* 50Gb link speed */
15700 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB \
15702 /* 100Gb link speed */
15703 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB \
15705 /* 200Gb link speed */
15706 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB \
15708 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_LAST \
15709 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB
15711 * Requested setting of TX LPI timer in microseconds.
15712 * This field is valid only when EEE is enabled and TX LPI is
15715 uint32_t tx_lpi_timer;
15716 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
15717 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
15721 /* hwrm_port_phy_cfg_output (size:128b/16B) */
15722 struct hwrm_port_phy_cfg_output {
15723 /* The specific error status for the command. */
15724 uint16_t error_code;
15725 /* The HWRM command request type. */
15727 /* The sequence ID from the original command. */
15729 /* The length of the response data in number of bytes. */
15731 uint8_t unused_0[7];
15733 * This field is used in Output records to indicate that the output
15734 * is completely written to RAM. This field should be read as '1'
15735 * to indicate that the output has been completely written.
15736 * When writing a command completion or response to an internal processor,
15737 * the order of writes has to be such that this field is written last.
15742 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
15743 struct hwrm_port_phy_cfg_cmd_err {
15745 * command specific error codes that goes to
15746 * the cmd_err field in Common HWRM Error Response.
15749 /* Unknown error */
15750 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
15751 /* Unable to complete operation due to invalid speed */
15752 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
15754 * retry the command since the phy is not ready.
15755 * retry count is returned in opaque_0.
15756 * This is only valid for the first command and
15757 * this value will not change for successive calls.
15758 * but if a 0 is returned at any time then this should
15759 * be treated as an un recoverable failure,
15761 * retry interval in milli seconds is returned in opaque_1.
15762 * This specifies the time that user should wait before
15763 * issuing the next port_phy_cfg command.
15765 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
15766 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
15767 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
15768 uint8_t unused_0[7];
15771 /**********************
15772 * hwrm_port_phy_qcfg *
15773 **********************/
15776 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
15777 struct hwrm_port_phy_qcfg_input {
15778 /* The HWRM command request type. */
15781 * The completion ring to send the completion event on. This should
15782 * be the NQ ID returned from the `nq_alloc` HWRM command.
15784 uint16_t cmpl_ring;
15786 * The sequence ID is used by the driver for tracking multiple
15787 * commands. This ID is treated as opaque data by the firmware and
15788 * the value is returned in the `hwrm_resp_hdr` upon completion.
15792 * The target ID of the command:
15793 * * 0x0-0xFFF8 - The function ID
15794 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15795 * * 0xFFFD - Reserved for user-space HWRM interface
15798 uint16_t target_id;
15800 * A physical address pointer pointing to a host buffer that the
15801 * command's response data will be written. This can be either a host
15802 * physical address (HPA) or a guest physical address (GPA) and must
15803 * point to a physically contiguous block of memory.
15805 uint64_t resp_addr;
15806 /* Port ID of port that is to be queried. */
15808 uint8_t unused_0[6];
15811 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
15812 struct hwrm_port_phy_qcfg_output {
15813 /* The specific error status for the command. */
15814 uint16_t error_code;
15815 /* The HWRM command request type. */
15817 /* The sequence ID from the original command. */
15819 /* The length of the response data in number of bytes. */
15821 /* This value indicates the current link status. */
15823 /* There is no link or cable detected. */
15824 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
15825 /* There is no link, but a cable has been detected. */
15826 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
15827 /* There is a link. */
15828 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
15829 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
15830 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
15832 /* This value indicates the current link speed of the connection. */
15833 uint16_t link_speed;
15834 /* 100Mb link speed */
15835 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
15836 /* 1Gb link speed */
15837 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
15838 /* 2Gb link speed */
15839 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
15840 /* 25Gb link speed */
15841 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
15842 /* 10Gb link speed */
15843 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
15844 /* 20Mb link speed */
15845 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
15846 /* 25Gb link speed */
15847 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
15848 /* 40Gb link speed */
15849 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
15850 /* 50Gb link speed */
15851 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
15852 /* 100Gb link speed */
15853 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
15854 /* 200Gb link speed */
15855 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
15856 /* 10Mb link speed */
15857 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
15858 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
15859 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
15861 * This value is indicates the duplex of the current
15864 uint8_t duplex_cfg;
15865 /* Half Duplex connection. */
15866 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
15867 /* Full duplex connection. */
15868 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
15869 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
15870 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
15872 * This value is used to indicate the current
15873 * pause configuration. When autoneg is enabled, this value
15874 * represents the autoneg results of pause configuration.
15878 * When this bit is '1', Generation of tx pause messages
15879 * is supported. Disabled otherwise.
15881 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
15883 * When this bit is '1', Reception of rx pause messages
15884 * is supported. Disabled otherwise.
15886 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
15888 * The supported speeds for the port. This is a bit mask.
15889 * For each speed that is supported, the corrresponding
15890 * bit will be set to '1'.
15892 uint16_t support_speeds;
15893 /* 100Mb link speed (Half-duplex) */
15894 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
15896 /* 100Mb link speed (Full-duplex) */
15897 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
15899 /* 1Gb link speed (Half-duplex) */
15900 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
15902 /* 1Gb link speed (Full-duplex) */
15903 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
15905 /* 2Gb link speed */
15906 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
15908 /* 25Gb link speed */
15909 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
15911 /* 10Gb link speed */
15912 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
15914 /* 20Gb link speed */
15915 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
15917 /* 25Gb link speed */
15918 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
15920 /* 40Gb link speed */
15921 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
15923 /* 50Gb link speed */
15924 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
15926 /* 100Gb link speed */
15927 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
15929 /* 10Mb link speed (Half-duplex) */
15930 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
15932 /* 10Mb link speed (Full-duplex) */
15933 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
15935 /* 200Gb link speed */
15936 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
15939 * Current setting of forced link speed.
15940 * When the link speed is not being forced, this
15941 * value shall be set to 0.
15943 uint16_t force_link_speed;
15944 /* 100Mb link speed */
15945 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
15946 /* 1Gb link speed */
15947 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
15948 /* 2Gb link speed */
15949 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
15950 /* 25Gb link speed */
15951 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
15952 /* 10Gb link speed */
15953 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
15954 /* 20Mb link speed */
15955 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
15956 /* 25Gb link speed */
15957 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
15958 /* 40Gb link speed */
15959 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
15961 /* 50Gb link speed */
15962 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
15964 /* 100Gb link speed */
15965 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
15967 /* 200Gb link speed */
15968 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
15970 /* 10Mb link speed */
15971 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
15973 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
15974 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
15975 /* Current setting of auto negotiation mode. */
15977 /* Disable autoneg or autoneg disabled. No speeds are selected. */
15978 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
15979 /* Select all possible speeds for autoneg mode. */
15980 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
15982 * Select only the auto_link_speed speed for autoneg mode. This mode has
15983 * been DEPRECATED. An HWRM client should not use this mode.
15985 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
15987 * Select the auto_link_speed or any speed below that speed for autoneg.
15988 * This mode has been DEPRECATED. An HWRM client should not use this mode.
15990 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
15992 * Select the speeds based on the corresponding link speed mask value
15993 * that is provided.
15995 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
15996 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
15997 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
15999 * Current setting of pause autonegotiation.
16000 * Move autoneg_pause flag here.
16002 uint8_t auto_pause;
16004 * When this bit is '1', Generation of tx pause messages
16005 * has been requested. Disabled otherwise.
16007 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
16010 * When this bit is '1', Reception of rx pause messages
16011 * has been requested. Disabled otherwise.
16013 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
16016 * When set to 1, the advertisement of pause is enabled.
16018 * # When the auto_mode is not set to none and this flag is
16019 * set to 1, then the auto_pause bits on this port are being
16020 * advertised and autoneg pause results are being interpreted.
16021 * # When the auto_mode is not set to none and this
16022 * flag is set to 0, the pause is forced as indicated in
16023 * force_pause, and also advertised as auto_pause bits, but
16024 * the autoneg results are not interpreted since the pause
16025 * configuration is being forced.
16026 * # When the auto_mode is set to none and this flag is set to
16027 * 1, auto_pause bits should be ignored and should be set to 0.
16029 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
16032 * Current setting for auto_link_speed. This field is only
16033 * valid when auto_mode is set to "one_speed" or "one_or_below".
16035 uint16_t auto_link_speed;
16036 /* 100Mb link speed */
16037 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
16038 /* 1Gb link speed */
16039 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
16040 /* 2Gb link speed */
16041 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
16042 /* 25Gb link speed */
16043 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
16044 /* 10Gb link speed */
16045 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
16046 /* 20Mb link speed */
16047 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
16048 /* 25Gb link speed */
16049 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
16050 /* 40Gb link speed */
16051 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
16052 /* 50Gb link speed */
16053 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
16054 /* 100Gb link speed */
16055 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
16056 /* 200Gb link speed */
16057 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
16058 /* 10Mb link speed */
16059 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
16061 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
16062 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
16064 * Current setting for auto_link_speed_mask that is used to
16065 * advertise speeds during autonegotiation.
16066 * This field is only valid when auto_mode is set to "mask".
16067 * The speeds specified in this field shall be a subset of
16068 * supported speeds on this port.
16070 uint16_t auto_link_speed_mask;
16071 /* 100Mb link speed (Half-duplex) */
16072 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
16074 /* 100Mb link speed (Full-duplex) */
16075 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
16077 /* 1Gb link speed (Half-duplex) */
16078 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
16080 /* 1Gb link speed (Full-duplex) */
16081 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
16083 /* 2Gb link speed */
16084 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
16086 /* 25Gb link speed */
16087 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
16089 /* 10Gb link speed */
16090 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
16092 /* 20Gb link speed */
16093 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
16095 /* 25Gb link speed */
16096 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
16098 /* 40Gb link speed */
16099 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
16101 /* 50Gb link speed */
16102 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
16104 /* 100Gb link speed */
16105 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
16107 /* 10Mb link speed (Half-duplex) */
16108 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
16110 /* 10Mb link speed (Full-duplex) */
16111 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
16113 /* 200Gb link speed */
16114 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
16116 /* Current setting for wirespeed. */
16118 /* Wirespeed feature is disabled. */
16119 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
16120 /* Wirespeed feature is enabled. */
16121 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
16122 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
16123 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
16124 /* Current setting for loopback. */
16126 /* No loopback is selected. Normal operation. */
16127 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
16129 * The HW will be configured with local loopback such that
16130 * host data is sent back to the host without modification.
16132 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
16134 * The HW will be configured with remote loopback such that
16135 * port logic will send packets back out the transmitter that
16138 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
16140 * The HW will be configured with external loopback such that
16141 * host data is sent on the transmitter and based on the external
16142 * loopback connection the data will be received without modification.
16144 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
16145 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
16146 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
16148 * Current setting of forced pause.
16149 * When the pause configuration is not being forced, then
16150 * this value shall be set to 0.
16152 uint8_t force_pause;
16154 * When this bit is '1', Generation of tx pause messages
16155 * is supported. Disabled otherwise.
16157 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
16159 * When this bit is '1', Reception of rx pause messages
16160 * is supported. Disabled otherwise.
16162 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
16164 * This value indicates the current status of the optics module on
16167 uint8_t module_status;
16168 /* Module is inserted and accepted */
16169 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
16171 /* Module is rejected and transmit side Laser is disabled. */
16172 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
16174 /* Module mismatch warning. */
16175 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
16177 /* Module is rejected and powered down. */
16178 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
16180 /* Module is not inserted. */
16181 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
16183 /* Module is powered down because of over current fault. */
16184 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \
16186 /* Module status is not applicable. */
16187 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
16189 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
16190 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
16191 /* Current setting for preemphasis. */
16192 uint32_t preemphasis;
16193 /* This field represents the major version of the PHY. */
16195 /* This field represents the minor version of the PHY. */
16197 /* This field represents the build version of the PHY. */
16199 /* This value represents a PHY type. */
16202 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
16205 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
16207 /* BASE-KR4 (Deprecated) */
16208 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
16211 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
16214 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
16216 /* BASE-KR2 (Deprecated) */
16217 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
16220 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
16223 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
16226 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
16228 /* EEE capable BASE-T */
16229 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
16231 /* SGMII connected external PHY */
16232 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
16234 /* 25G_BASECR_CA_L */
16235 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
16237 /* 25G_BASECR_CA_S */
16238 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
16240 /* 25G_BASECR_CA_N */
16241 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
16244 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
16247 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
16250 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
16253 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
16256 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
16258 /* 100G_BASESR10 */
16259 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
16262 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
16265 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
16268 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
16271 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
16273 /* 40G_ACTIVE_CABLE */
16274 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
16277 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
16280 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
16283 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
16286 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
16289 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
16292 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
16295 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
16297 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
16298 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
16299 /* This value represents a media type. */
16300 uint8_t media_type;
16302 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
16304 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
16305 /* Direct Attached Copper */
16306 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
16308 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
16309 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
16310 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
16311 /* This value represents a transceiver type. */
16312 uint8_t xcvr_pkg_type;
16313 /* PHY and MAC are in the same package */
16314 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
16316 /* PHY and MAC are in different packages */
16317 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
16319 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
16320 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
16321 uint8_t eee_config_phy_addr;
16322 /* This field represents PHY address. */
16323 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
16325 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
16327 * This field represents flags related to EEE configuration.
16328 * These EEE configuration flags are valid only when the
16329 * auto_mode is not set to none (in other words autonegotiation
16332 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
16334 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
16336 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
16337 * Speeds for autoneg with EEE mode enabled
16338 * are based on eee_link_speed_mask.
16340 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
16343 * This flag is valid only when eee_enabled is set to 1.
16345 * # If eee_enabled is set to 0, then EEE mode is disabled
16346 * and this flag shall be ignored.
16347 * # If eee_enabled is set to 1 and this flag is set to 1,
16348 * then Energy Efficient Ethernet (EEE) mode is enabled
16350 * # If eee_enabled is set to 1 and this flag is set to 0,
16351 * then Energy Efficient Ethernet (EEE) mode is enabled
16352 * but is currently not in use.
16354 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
16357 * This flag is valid only when eee_enabled is set to 1.
16359 * # If eee_enabled is set to 0, then EEE mode is disabled
16360 * and this flag shall be ignored.
16361 * # If eee_enabled is set to 1 and this flag is set to 1,
16362 * then Energy Efficient Ethernet (EEE) mode is enabled
16363 * and TX LPI is enabled.
16364 * # If eee_enabled is set to 1 and this flag is set to 0,
16365 * then Energy Efficient Ethernet (EEE) mode is enabled
16366 * but TX LPI is disabled.
16368 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
16371 * When set to 1, the parallel detection is used to determine
16372 * the speed of the link partner.
16374 * Parallel detection is used when a autonegotiation capable
16375 * device is connected to a link parter that is not capable
16376 * of autonegotiation.
16378 uint8_t parallel_detect;
16380 * When set to 1, the parallel detection is used to determine
16381 * the speed of the link partner.
16383 * Parallel detection is used when a autonegotiation capable
16384 * device is connected to a link parter that is not capable
16385 * of autonegotiation.
16387 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
16389 * The advertised speeds for the port by the link partner.
16390 * Each advertised speed will be set to '1'.
16392 uint16_t link_partner_adv_speeds;
16393 /* 100Mb link speed (Half-duplex) */
16394 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
16396 /* 100Mb link speed (Full-duplex) */
16397 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
16399 /* 1Gb link speed (Half-duplex) */
16400 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
16402 /* 1Gb link speed (Full-duplex) */
16403 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
16405 /* 2Gb link speed */
16406 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
16408 /* 25Gb link speed */
16409 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
16411 /* 10Gb link speed */
16412 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
16414 /* 20Gb link speed */
16415 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
16417 /* 25Gb link speed */
16418 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
16420 /* 40Gb link speed */
16421 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
16423 /* 50Gb link speed */
16424 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
16426 /* 100Gb link speed */
16427 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
16429 /* 10Mb link speed (Half-duplex) */
16430 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
16432 /* 10Mb link speed (Full-duplex) */
16433 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
16436 * The advertised autoneg for the port by the link partner.
16437 * This field is deprecated and should be set to 0.
16439 uint8_t link_partner_adv_auto_mode;
16440 /* Disable autoneg or autoneg disabled. No speeds are selected. */
16441 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
16443 /* Select all possible speeds for autoneg mode. */
16444 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
16447 * Select only the auto_link_speed speed for autoneg mode. This mode has
16448 * been DEPRECATED. An HWRM client should not use this mode.
16450 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
16453 * Select the auto_link_speed or any speed below that speed for autoneg.
16454 * This mode has been DEPRECATED. An HWRM client should not use this mode.
16456 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
16459 * Select the speeds based on the corresponding link speed mask value
16460 * that is provided.
16462 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
16464 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
16465 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
16466 /* The advertised pause settings on the port by the link partner. */
16467 uint8_t link_partner_adv_pause;
16469 * When this bit is '1', Generation of tx pause messages
16470 * is supported. Disabled otherwise.
16472 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
16475 * When this bit is '1', Reception of rx pause messages
16476 * is supported. Disabled otherwise.
16478 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
16481 * Current setting for link speed mask that is used to
16482 * advertise speeds during autonegotiation when EEE is enabled.
16483 * This field is valid only when eee_enabled flags is set to 1.
16484 * The speeds specified in this field shall be a subset of
16485 * speeds specified in auto_link_speed_mask.
16487 uint16_t adv_eee_link_speed_mask;
16489 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16491 /* 100Mb link speed (Full-duplex) */
16492 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
16495 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16497 /* 1Gb link speed (Full-duplex) */
16498 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
16501 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16504 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16506 /* 10Gb link speed */
16507 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
16510 * Current setting for link speed mask that is advertised by
16511 * the link partner when EEE is enabled.
16512 * This field is valid only when eee_enabled flags is set to 1.
16514 uint16_t link_partner_adv_eee_link_speed_mask;
16516 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
16518 /* 100Mb link speed (Full-duplex) */
16519 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
16522 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
16524 /* 1Gb link speed (Full-duplex) */
16525 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
16528 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
16531 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
16533 /* 10Gb link speed */
16534 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
16536 uint32_t xcvr_identifier_type_tx_lpi_timer;
16538 * Current setting of TX LPI timer in microseconds.
16539 * This field is valid only when_eee_enabled flag is set to 1
16540 * and tx_lpi_enabled is set to 1.
16542 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
16544 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
16545 /* This value represents transceiver identifier type. */
16546 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
16547 UINT32_C(0xff000000)
16548 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
16550 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
16551 (UINT32_C(0x0) << 24)
16552 /* SFP/SFP+/SFP28 */
16553 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
16554 (UINT32_C(0x3) << 24)
16556 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
16557 (UINT32_C(0xc) << 24)
16559 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
16560 (UINT32_C(0xd) << 24)
16562 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
16563 (UINT32_C(0x11) << 24)
16564 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
16565 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
16567 * This value represents the current configuration of
16568 * Forward Error Correction (FEC) on the port.
16572 * When set to 1, then FEC is not supported on this port. If this flag
16573 * is set to 1, then all other FEC configuration flags shall be ignored.
16574 * When set to 0, then FEC is supported as indicated by other
16575 * configuration flags.
16576 * If no cable is attached and the HWRM does not yet know the FEC
16577 * capability, then the HWRM shall set this flag to 1 when reporting
16580 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
16583 * When set to 1, then FEC autonegotiation is supported on this port.
16584 * When set to 0, then FEC autonegotiation is not supported on this port.
16586 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
16589 * When set to 1, then FEC autonegotiation is enabled on this port.
16590 * When set to 0, then FEC autonegotiation is disabled if supported.
16591 * This flag should be ignored if FEC autonegotiation is not supported on this port.
16593 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
16596 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
16597 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
16599 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
16602 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
16603 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
16604 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
16606 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
16609 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
16610 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
16612 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
16615 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
16616 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
16617 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
16619 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
16622 * This value is indicates the duplex of the current
16623 * connection state.
16625 uint8_t duplex_state;
16626 /* Half Duplex connection. */
16627 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
16628 /* Full duplex connection. */
16629 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
16630 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
16631 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
16632 /* Option flags fields. */
16633 uint8_t option_flags;
16634 /* When this bit is '1', Media auto detect is enabled. */
16635 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
16638 * Up to 16 bytes of null padded ASCII string representing
16640 * If the string is set to null, then the vendor name is not
16643 char phy_vendor_name[16];
16645 * Up to 16 bytes of null padded ASCII string that
16646 * identifies vendor specific part number of the PHY.
16647 * If the string is set to null, then the vendor specific
16648 * part number is not available.
16650 char phy_vendor_partnumber[16];
16651 uint8_t unused_2[7];
16653 * This field is used in Output records to indicate that the output
16654 * is completely written to RAM. This field should be read as '1'
16655 * to indicate that the output has been completely written.
16656 * When writing a command completion or response to an internal processor,
16657 * the order of writes has to be such that this field is written last.
16662 /*********************
16663 * hwrm_port_mac_cfg *
16664 *********************/
16667 /* hwrm_port_mac_cfg_input (size:384b/48B) */
16668 struct hwrm_port_mac_cfg_input {
16669 /* The HWRM command request type. */
16672 * The completion ring to send the completion event on. This should
16673 * be the NQ ID returned from the `nq_alloc` HWRM command.
16675 uint16_t cmpl_ring;
16677 * The sequence ID is used by the driver for tracking multiple
16678 * commands. This ID is treated as opaque data by the firmware and
16679 * the value is returned in the `hwrm_resp_hdr` upon completion.
16683 * The target ID of the command:
16684 * * 0x0-0xFFF8 - The function ID
16685 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16686 * * 0xFFFD - Reserved for user-space HWRM interface
16689 uint16_t target_id;
16691 * A physical address pointer pointing to a host buffer that the
16692 * command's response data will be written. This can be either a host
16693 * physical address (HPA) or a guest physical address (GPA) and must
16694 * point to a physically contiguous block of memory.
16696 uint64_t resp_addr;
16698 * In this field, there are a number of CoS mappings related flags
16699 * that are used to configure CoS mappings and their corresponding
16700 * priorities in the hardware.
16701 * For the priorities of CoS mappings, the HWRM uses the following
16702 * priority order (high to low) by default:
16705 * # tunnel_vlan_pri
16708 * A subset of CoS mappings can be enabled.
16709 * If a priority is not specified for an enabled CoS mapping, the
16710 * priority will be assigned in the above order for the enabled CoS
16711 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
16712 * enabled and their priorities are not specified, the following
16713 * priority order (high to low) will be used by the HWRM:
16718 * vlan_pri CoS mapping together with default CoS with lower priority
16719 * are enabled by default by the HWRM.
16723 * When this bit is '1', this command will configure
16724 * the MAC to match the current link state of the PHY.
16725 * If the link is not established on the PHY, then this
16726 * bit has no effect.
16728 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
16731 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16732 * is requested to be enabled.
16734 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
16737 * When this bit is set to '1', tunnel VLAN PRI field to
16738 * CoS mapping is requested to be enabled.
16740 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
16743 * When this bit is set to '1', the IP DSCP to CoS mapping is
16744 * requested to be enabled.
16746 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
16749 * When this bit is '1', the HWRM is requested to
16750 * enable timestamp capture capability on the receive side
16753 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
16756 * When this bit is '1', the HWRM is requested to
16757 * disable timestamp capture capability on the receive side
16760 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
16763 * When this bit is '1', the HWRM is requested to
16764 * enable timestamp capture capability on the transmit side
16767 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
16770 * When this bit is '1', the HWRM is requested to
16771 * disable timestamp capture capability on the transmit side
16774 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
16777 * When this bit is '1', the Out-Of-Box WoL is requested to
16778 * be enabled on this port.
16780 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
16783 * When this bit is '1', the Out-Of-Box WoL is requested to
16784 * be disabled on this port.
16786 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
16789 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
16790 * is requested to be disabled.
16792 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
16795 * When this bit is set to '1', tunnel VLAN PRI field to
16796 * CoS mapping is requested to be disabled.
16798 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
16801 * When this bit is set to '1', the IP DSCP to CoS mapping is
16802 * requested to be disabled.
16804 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
16807 * When this bit is set to '1', and the ptp_tx_ts_capture_enable
16808 * bit is set, then the device uses one step Tx timestamping.
16809 * This bit is temporary and used for experimental purposes.
16811 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
16815 * This bit must be '1' for the ipg field to be
16818 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
16821 * This bit must be '1' for the lpbk field to be
16824 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
16827 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
16830 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
16833 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
16836 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
16839 * This bit must be '1' for the dscp2cos_map_pri field to be
16842 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
16845 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
16848 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
16851 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
16854 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
16857 * This bit must be '1' for the cos_field_cfg field to be
16860 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
16863 * This bit must be '1' for the ptp_freq_adj_ppb field to be
16866 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
16868 /* Port ID of port that is to be configured. */
16871 * This value is used to configure the minimum IPG that will
16872 * be sent between packets by this port.
16875 /* This value controls the loopback setting for the MAC. */
16877 /* No loopback is selected. Normal operation. */
16878 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
16880 * The HW will be configured with local loopback such that
16881 * host data is sent back to the host without modification.
16883 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
16885 * The HW will be configured with remote loopback such that
16886 * port logic will send packets back out the transmitter that
16889 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
16890 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
16891 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
16893 * This value controls the priority setting of VLAN PRI to CoS
16894 * mapping based on VLAN Tags of inner packet headers of
16895 * tunneled packets or packet headers of non-tunneled packets.
16897 * # Each XXX_pri variable shall have a unique priority value
16898 * when it is being specified.
16899 * # When comparing priorities of mappings, higher value
16900 * indicates higher priority.
16901 * For example, a value of 0-3 is returned where 0 is being
16902 * the lowest priority and 3 is being the highest priority.
16904 uint8_t vlan_pri2cos_map_pri;
16905 /* Reserved field. */
16908 * This value controls the priority setting of VLAN PRI to CoS
16909 * mapping based on VLAN Tags of tunneled header.
16910 * This mapping only applies when tunneled headers
16913 * # Each XXX_pri variable shall have a unique priority value
16914 * when it is being specified.
16915 * # When comparing priorities of mappings, higher value
16916 * indicates higher priority.
16917 * For example, a value of 0-3 is returned where 0 is being
16918 * the lowest priority and 3 is being the highest priority.
16920 uint8_t tunnel_pri2cos_map_pri;
16922 * This value controls the priority setting of IP DSCP to CoS
16923 * mapping based on inner IP header of tunneled packets or
16924 * IP header of non-tunneled packets.
16926 * # Each XXX_pri variable shall have a unique priority value
16927 * when it is being specified.
16928 * # When comparing priorities of mappings, higher value
16929 * indicates higher priority.
16930 * For example, a value of 0-3 is returned where 0 is being
16931 * the lowest priority and 3 is being the highest priority.
16933 uint8_t dscp2pri_map_pri;
16935 * This is a 16-bit bit mask that is used to request a
16936 * specific configuration of time stamp capture of PTP messages
16937 * on the receive side of this port.
16938 * This field shall be ignored if the ptp_rx_ts_capture_enable
16939 * flag is not set in this command.
16940 * Otherwise, if bit 'i' is set, then the HWRM is being
16941 * requested to configure the receive side of the port to
16942 * capture the time stamp of every received PTP message
16943 * with messageType field value set to i.
16945 uint16_t rx_ts_capture_ptp_msg_type;
16947 * This is a 16-bit bit mask that is used to request a
16948 * specific configuration of time stamp capture of PTP messages
16949 * on the transmit side of this port.
16950 * This field shall be ignored if the ptp_tx_ts_capture_enable
16951 * flag is not set in this command.
16952 * Otherwise, if bit 'i' is set, then the HWRM is being
16953 * requested to configure the transmit side of the port to
16954 * capture the time stamp of every transmitted PTP message
16955 * with messageType field value set to i.
16957 uint16_t tx_ts_capture_ptp_msg_type;
16958 /* Configuration of CoS fields. */
16959 uint8_t cos_field_cfg;
16961 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
16964 * This field is used to specify selection of VLAN PRI value
16965 * based on whether one or two VLAN Tags are present in
16966 * the inner packet headers of tunneled packets or
16967 * non-tunneled packets.
16968 * This field is valid only if inner VLAN PRI to CoS mapping
16970 * If VLAN PRI to CoS mapping is not enabled, then this
16971 * field shall be ignored.
16973 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
16975 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
16978 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
16979 * present in the inner packet headers
16981 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
16982 (UINT32_C(0x0) << 1)
16984 * Select outer VLAN Tag PRI when 2 VLAN Tags are
16985 * present in the inner packet headers.
16986 * No VLAN PRI shall be selected for this configuration
16987 * if only one VLAN Tag is present in the inner
16990 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
16991 (UINT32_C(0x1) << 1)
16993 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
16994 * are present in the inner packet headers
16996 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
16997 (UINT32_C(0x2) << 1)
16999 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17000 (UINT32_C(0x3) << 1)
17001 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17002 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17004 * This field is used to specify selection of tunnel VLAN
17005 * PRI value based on whether one or two VLAN Tags are
17006 * present in tunnel headers.
17007 * This field is valid only if tunnel VLAN PRI to CoS mapping
17009 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
17010 * field shall be ignored.
17012 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17014 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17017 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17018 * present in the tunnel packet headers
17020 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17021 (UINT32_C(0x0) << 3)
17023 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17024 * present in the tunnel packet headers.
17025 * No tunnel VLAN PRI shall be selected for this
17026 * configuration if only one VLAN Tag is present in
17027 * the tunnel packet headers.
17029 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17030 (UINT32_C(0x1) << 3)
17032 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17033 * are present in the tunnel packet headers
17035 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17036 (UINT32_C(0x2) << 3)
17038 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17039 (UINT32_C(0x3) << 3)
17040 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17041 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17043 * This field shall be used to provide default CoS value
17044 * that has been configured on this port.
17045 * This field is valid only if default CoS mapping
17047 * If default CoS mapping is not enabled, then this
17048 * field shall be ignored.
17050 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17052 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17054 uint8_t unused_0[3];
17056 * This signed field specifies by how much to adjust the frequency
17057 * of sync timer updates (measured in parts per billion).
17059 int32_t ptp_freq_adj_ppb;
17060 uint8_t unused_1[4];
17063 /* hwrm_port_mac_cfg_output (size:128b/16B) */
17064 struct hwrm_port_mac_cfg_output {
17065 /* The specific error status for the command. */
17066 uint16_t error_code;
17067 /* The HWRM command request type. */
17069 /* The sequence ID from the original command. */
17071 /* The length of the response data in number of bytes. */
17074 * This is the configured maximum length of Ethernet packet
17075 * payload that is allowed to be received on the port.
17076 * This value does not include the number of bytes used by
17077 * Ethernet header and trailer (CRC).
17081 * This is the configured maximum length of Ethernet packet
17082 * payload that is allowed to be transmitted on the port.
17083 * This value does not include the number of bytes used by
17084 * Ethernet header and trailer (CRC).
17087 /* Current configuration of the IPG value. */
17089 /* Current value of the loopback value. */
17091 /* No loopback is selected. Normal operation. */
17092 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17094 * The HW will be configured with local loopback such that
17095 * host data is sent back to the host without modification.
17097 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17099 * The HW will be configured with remote loopback such that
17100 * port logic will send packets back out the transmitter that
17103 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17104 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
17105 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
17108 * This field is used in Output records to indicate that the output
17109 * is completely written to RAM. This field should be read as '1'
17110 * to indicate that the output has been completely written.
17111 * When writing a command completion or response to an internal processor,
17112 * the order of writes has to be such that this field is written last.
17117 /**********************
17118 * hwrm_port_mac_qcfg *
17119 **********************/
17122 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
17123 struct hwrm_port_mac_qcfg_input {
17124 /* The HWRM command request type. */
17127 * The completion ring to send the completion event on. This should
17128 * be the NQ ID returned from the `nq_alloc` HWRM command.
17130 uint16_t cmpl_ring;
17132 * The sequence ID is used by the driver for tracking multiple
17133 * commands. This ID is treated as opaque data by the firmware and
17134 * the value is returned in the `hwrm_resp_hdr` upon completion.
17138 * The target ID of the command:
17139 * * 0x0-0xFFF8 - The function ID
17140 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17141 * * 0xFFFD - Reserved for user-space HWRM interface
17144 uint16_t target_id;
17146 * A physical address pointer pointing to a host buffer that the
17147 * command's response data will be written. This can be either a host
17148 * physical address (HPA) or a guest physical address (GPA) and must
17149 * point to a physically contiguous block of memory.
17151 uint64_t resp_addr;
17152 /* Port ID of port that is to be configured. */
17154 uint8_t unused_0[6];
17157 /* hwrm_port_mac_qcfg_output (size:256b/32B) */
17158 struct hwrm_port_mac_qcfg_output {
17159 /* The specific error status for the command. */
17160 uint16_t error_code;
17161 /* The HWRM command request type. */
17163 /* The sequence ID from the original command. */
17165 /* The length of the response data in number of bytes. */
17168 * This is the configured maximum length of Ethernet packet
17169 * payload that is allowed to be received on the port.
17170 * This value does not include the number of bytes used by the
17171 * Ethernet header and trailer (CRC).
17175 * This is the configured maximum length of Ethernet packet
17176 * payload that is allowed to be transmitted on the port.
17177 * This value does not include the number of bytes used by the
17178 * Ethernet header and trailer (CRC).
17182 * The minimum IPG that will
17183 * be sent between packets by this port.
17186 /* The loopback setting for the MAC. */
17188 /* No loopback is selected. Normal operation. */
17189 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
17191 * The HW will be configured with local loopback such that
17192 * host data is sent back to the host without modification.
17194 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
17196 * The HW will be configured with remote loopback such that
17197 * port logic will send packets back out the transmitter that
17200 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
17201 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
17202 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
17204 * Priority setting for VLAN PRI to CoS mapping.
17205 * # Each XXX_pri variable shall have a unique priority value
17206 * when it is being used.
17207 * # When comparing priorities of mappings, higher value
17208 * indicates higher priority.
17209 * For example, a value of 0-3 is returned where 0 is being
17210 * the lowest priority and 3 is being the highest priority.
17211 * # If the correspoding CoS mapping is not enabled, then this
17212 * field should be ignored.
17213 * # This value indicates the normalized priority value retained
17216 uint8_t vlan_pri2cos_map_pri;
17218 * In this field, a number of CoS mappings related flags
17219 * are used to indicate configured CoS mappings.
17223 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
17226 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
17229 * When this bit is set to '1', tunnel VLAN PRI field to
17230 * CoS mapping is enabled.
17232 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
17235 * When this bit is set to '1', the IP DSCP to CoS mapping is
17238 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
17241 * When this bit is '1', the Out-Of-Box WoL is enabled on this
17244 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
17246 /* When this bit is '1', PTP is enabled for RX on this port. */
17247 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
17249 /* When this bit is '1', PTP is enabled for TX on this port. */
17250 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
17253 * Priority setting for tunnel VLAN PRI to CoS mapping.
17254 * # Each XXX_pri variable shall have a unique priority value
17255 * when it is being used.
17256 * # When comparing priorities of mappings, higher value
17257 * indicates higher priority.
17258 * For example, a value of 0-3 is returned where 0 is being
17259 * the lowest priority and 3 is being the highest priority.
17260 * # If the correspoding CoS mapping is not enabled, then this
17261 * field should be ignored.
17262 * # This value indicates the normalized priority value retained
17265 uint8_t tunnel_pri2cos_map_pri;
17267 * Priority setting for DSCP to PRI mapping.
17268 * # Each XXX_pri variable shall have a unique priority value
17269 * when it is being used.
17270 * # When comparing priorities of mappings, higher value
17271 * indicates higher priority.
17272 * For example, a value of 0-3 is returned where 0 is being
17273 * the lowest priority and 3 is being the highest priority.
17274 * # If the correspoding CoS mapping is not enabled, then this
17275 * field should be ignored.
17276 * # This value indicates the normalized priority value retained
17279 uint8_t dscp2pri_map_pri;
17281 * This is a 16-bit bit mask that represents the
17282 * current configuration of time stamp capture of PTP messages
17283 * on the receive side of this port.
17284 * If bit 'i' is set, then the receive side of the port
17285 * is configured to capture the time stamp of every
17286 * received PTP message with messageType field value set
17288 * If all bits are set to 0 (i.e. field value set 0),
17289 * then the receive side of the port is not configured
17290 * to capture timestamp for PTP messages.
17291 * If all bits are set to 1, then the receive side of the
17292 * port is configured to capture timestamp for all PTP
17295 uint16_t rx_ts_capture_ptp_msg_type;
17297 * This is a 16-bit bit mask that represents the
17298 * current configuration of time stamp capture of PTP messages
17299 * on the transmit side of this port.
17300 * If bit 'i' is set, then the transmit side of the port
17301 * is configured to capture the time stamp of every
17302 * received PTP message with messageType field value set
17304 * If all bits are set to 0 (i.e. field value set 0),
17305 * then the transmit side of the port is not configured
17306 * to capture timestamp for PTP messages.
17307 * If all bits are set to 1, then the transmit side of the
17308 * port is configured to capture timestamp for all PTP
17311 uint16_t tx_ts_capture_ptp_msg_type;
17312 /* Configuration of CoS fields. */
17313 uint8_t cos_field_cfg;
17315 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
17318 * This field is used for selecting VLAN PRI value
17319 * based on whether one or two VLAN Tags are present in
17320 * the inner packet headers of tunneled packets or
17321 * non-tunneled packets.
17323 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
17325 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
17328 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17329 * present in the inner packet headers
17331 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
17332 (UINT32_C(0x0) << 1)
17334 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17335 * present in the inner packet headers.
17336 * No VLAN PRI is selected for this configuration
17337 * if only one VLAN Tag is present in the inner
17340 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
17341 (UINT32_C(0x1) << 1)
17343 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17344 * are present in the inner packet headers
17346 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
17347 (UINT32_C(0x2) << 1)
17349 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
17350 (UINT32_C(0x3) << 1)
17351 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
17352 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
17354 * This field is used for selecting tunnel VLAN PRI value
17355 * based on whether one or two VLAN Tags are present in
17356 * the tunnel headers of tunneled packets. This selection
17357 * does not apply to non-tunneled packets.
17359 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
17361 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
17364 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
17365 * present in the tunnel packet headers
17367 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
17368 (UINT32_C(0x0) << 3)
17370 * Select outer VLAN Tag PRI when 2 VLAN Tags are
17371 * present in the tunnel packet headers.
17372 * No VLAN PRI is selected for this configuration
17373 * if only one VLAN Tag is present in the tunnel
17376 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
17377 (UINT32_C(0x1) << 3)
17379 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
17380 * are present in the tunnel packet headers
17382 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
17383 (UINT32_C(0x2) << 3)
17385 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
17386 (UINT32_C(0x3) << 3)
17387 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
17388 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
17390 * This field is used to provide default CoS value that
17391 * has been configured on this port.
17393 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
17395 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
17398 uint16_t port_svif_info;
17400 * This field specifies the source virtual interface of the port being
17401 * queried. Drivers can use this to program port svif field in the
17404 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \
17406 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
17407 /* This field specifies whether port_svif is valid or not */
17408 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \
17410 uint8_t unused_2[5];
17412 * This field is used in Output records to indicate that the output
17413 * is completely written to RAM. This field should be read as '1'
17414 * to indicate that the output has been completely written.
17415 * When writing a command completion or response to an internal processor,
17416 * the order of writes has to be such that this field is written last.
17421 /**************************
17422 * hwrm_port_mac_ptp_qcfg *
17423 **************************/
17426 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
17427 struct hwrm_port_mac_ptp_qcfg_input {
17428 /* The HWRM command request type. */
17431 * The completion ring to send the completion event on. This should
17432 * be the NQ ID returned from the `nq_alloc` HWRM command.
17434 uint16_t cmpl_ring;
17436 * The sequence ID is used by the driver for tracking multiple
17437 * commands. This ID is treated as opaque data by the firmware and
17438 * the value is returned in the `hwrm_resp_hdr` upon completion.
17442 * The target ID of the command:
17443 * * 0x0-0xFFF8 - The function ID
17444 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17445 * * 0xFFFD - Reserved for user-space HWRM interface
17448 uint16_t target_id;
17450 * A physical address pointer pointing to a host buffer that the
17451 * command's response data will be written. This can be either a host
17452 * physical address (HPA) or a guest physical address (GPA) and must
17453 * point to a physically contiguous block of memory.
17455 uint64_t resp_addr;
17456 /* Port ID of port that is being queried. */
17458 uint8_t unused_0[6];
17461 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
17462 struct hwrm_port_mac_ptp_qcfg_output {
17463 /* The specific error status for the command. */
17464 uint16_t error_code;
17465 /* The HWRM command request type. */
17467 /* The sequence ID from the original command. */
17469 /* The length of the response data in number of bytes. */
17472 * In this field, a number of PTP related flags
17473 * are used to indicate configured PTP capabilities.
17477 * When this bit is set to '1', the PTP related registers are
17478 * directly accessible by the host.
17480 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
17483 * When this bit is set to '1', the device supports one-step
17486 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
17489 * When this bit is set to '1', the PTP information is accessible
17490 * via HWRM commands.
17492 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
17494 uint8_t unused_0[3];
17495 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
17496 uint32_t rx_ts_reg_off_lower;
17497 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
17498 uint32_t rx_ts_reg_off_upper;
17499 /* Offset of the PTP register for the sequence ID for RX. */
17500 uint32_t rx_ts_reg_off_seq_id;
17501 /* Offset of the first PTP source ID for RX. */
17502 uint32_t rx_ts_reg_off_src_id_0;
17503 /* Offset of the second PTP source ID for RX. */
17504 uint32_t rx_ts_reg_off_src_id_1;
17505 /* Offset of the third PTP source ID for RX. */
17506 uint32_t rx_ts_reg_off_src_id_2;
17507 /* Offset of the domain ID for RX. */
17508 uint32_t rx_ts_reg_off_domain_id;
17509 /* Offset of the PTP FIFO register for RX. */
17510 uint32_t rx_ts_reg_off_fifo;
17511 /* Offset of the PTP advance FIFO register for RX. */
17512 uint32_t rx_ts_reg_off_fifo_adv;
17513 /* PTP timestamp granularity for RX. */
17514 uint32_t rx_ts_reg_off_granularity;
17515 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
17516 uint32_t tx_ts_reg_off_lower;
17517 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
17518 uint32_t tx_ts_reg_off_upper;
17519 /* Offset of the PTP register for the sequence ID for TX. */
17520 uint32_t tx_ts_reg_off_seq_id;
17521 /* Offset of the PTP FIFO register for TX. */
17522 uint32_t tx_ts_reg_off_fifo;
17523 /* PTP timestamp granularity for TX. */
17524 uint32_t tx_ts_reg_off_granularity;
17525 uint8_t unused_1[7];
17527 * This field is used in Output records to indicate that the output
17528 * is completely written to RAM. This field should be read as '1'
17529 * to indicate that the output has been completely written.
17530 * When writing a command completion or response to an internal processor,
17531 * the order of writes has to be such that this field is written last.
17536 /* Port Tx Statistics Format */
17537 /* tx_port_stats (size:3264b/408B) */
17538 struct tx_port_stats {
17539 /* Total Number of 64 Bytes frames transmitted */
17540 uint64_t tx_64b_frames;
17541 /* Total Number of 65-127 Bytes frames transmitted */
17542 uint64_t tx_65b_127b_frames;
17543 /* Total Number of 128-255 Bytes frames transmitted */
17544 uint64_t tx_128b_255b_frames;
17545 /* Total Number of 256-511 Bytes frames transmitted */
17546 uint64_t tx_256b_511b_frames;
17547 /* Total Number of 512-1023 Bytes frames transmitted */
17548 uint64_t tx_512b_1023b_frames;
17549 /* Total Number of 1024-1518 Bytes frames transmitted */
17550 uint64_t tx_1024b_1518b_frames;
17552 * Total Number of each good VLAN (exludes FCS errors)
17553 * frame transmitted which is 1519 to 1522 bytes in length
17554 * inclusive (excluding framing bits but including FCS bytes).
17556 uint64_t tx_good_vlan_frames;
17557 /* Total Number of 1519-2047 Bytes frames transmitted */
17558 uint64_t tx_1519b_2047b_frames;
17559 /* Total Number of 2048-4095 Bytes frames transmitted */
17560 uint64_t tx_2048b_4095b_frames;
17561 /* Total Number of 4096-9216 Bytes frames transmitted */
17562 uint64_t tx_4096b_9216b_frames;
17563 /* Total Number of 9217-16383 Bytes frames transmitted */
17564 uint64_t tx_9217b_16383b_frames;
17565 /* Total Number of good frames transmitted */
17566 uint64_t tx_good_frames;
17567 /* Total Number of frames transmitted */
17568 uint64_t tx_total_frames;
17569 /* Total number of unicast frames transmitted */
17570 uint64_t tx_ucast_frames;
17571 /* Total number of multicast frames transmitted */
17572 uint64_t tx_mcast_frames;
17573 /* Total number of broadcast frames transmitted */
17574 uint64_t tx_bcast_frames;
17575 /* Total number of PAUSE control frames transmitted */
17576 uint64_t tx_pause_frames;
17578 * Total number of PFC/per-priority PAUSE
17579 * control frames transmitted
17581 uint64_t tx_pfc_frames;
17582 /* Total number of jabber frames transmitted */
17583 uint64_t tx_jabber_frames;
17584 /* Total number of frames transmitted with FCS error */
17585 uint64_t tx_fcs_err_frames;
17586 /* Total number of control frames transmitted */
17587 uint64_t tx_control_frames;
17588 /* Total number of over-sized frames transmitted */
17589 uint64_t tx_oversz_frames;
17590 /* Total number of frames with single deferral */
17591 uint64_t tx_single_dfrl_frames;
17592 /* Total number of frames with multiple deferrals */
17593 uint64_t tx_multi_dfrl_frames;
17594 /* Total number of frames with single collision */
17595 uint64_t tx_single_coll_frames;
17596 /* Total number of frames with multiple collisions */
17597 uint64_t tx_multi_coll_frames;
17598 /* Total number of frames with late collisions */
17599 uint64_t tx_late_coll_frames;
17600 /* Total number of frames with excessive collisions */
17601 uint64_t tx_excessive_coll_frames;
17602 /* Total number of fragmented frames transmitted */
17603 uint64_t tx_frag_frames;
17604 /* Total number of transmit errors */
17606 /* Total number of single VLAN tagged frames transmitted */
17607 uint64_t tx_tagged_frames;
17608 /* Total number of double VLAN tagged frames transmitted */
17609 uint64_t tx_dbl_tagged_frames;
17610 /* Total number of runt frames transmitted */
17611 uint64_t tx_runt_frames;
17612 /* Total number of TX FIFO under runs */
17613 uint64_t tx_fifo_underruns;
17615 * Total number of PFC frames with PFC enabled bit for
17616 * Pri 0 transmitted
17618 uint64_t tx_pfc_ena_frames_pri0;
17620 * Total number of PFC frames with PFC enabled bit for
17621 * Pri 1 transmitted
17623 uint64_t tx_pfc_ena_frames_pri1;
17625 * Total number of PFC frames with PFC enabled bit for
17626 * Pri 2 transmitted
17628 uint64_t tx_pfc_ena_frames_pri2;
17630 * Total number of PFC frames with PFC enabled bit for
17631 * Pri 3 transmitted
17633 uint64_t tx_pfc_ena_frames_pri3;
17635 * Total number of PFC frames with PFC enabled bit for
17636 * Pri 4 transmitted
17638 uint64_t tx_pfc_ena_frames_pri4;
17640 * Total number of PFC frames with PFC enabled bit for
17641 * Pri 5 transmitted
17643 uint64_t tx_pfc_ena_frames_pri5;
17645 * Total number of PFC frames with PFC enabled bit for
17646 * Pri 6 transmitted
17648 uint64_t tx_pfc_ena_frames_pri6;
17650 * Total number of PFC frames with PFC enabled bit for
17651 * Pri 7 transmitted
17653 uint64_t tx_pfc_ena_frames_pri7;
17654 /* Total number of EEE LPI Events on TX */
17655 uint64_t tx_eee_lpi_events;
17656 /* EEE LPI Duration Counter on TX */
17657 uint64_t tx_eee_lpi_duration;
17659 * Total number of Link Level Flow Control (LLFC) messages
17662 uint64_t tx_llfc_logical_msgs;
17663 /* Total number of HCFC messages transmitted */
17664 uint64_t tx_hcfc_msgs;
17665 /* Total number of TX collisions */
17666 uint64_t tx_total_collisions;
17667 /* Total number of transmitted bytes */
17669 /* Total number of end-to-end HOL frames */
17670 uint64_t tx_xthol_frames;
17671 /* Total Tx Drops per Port reported by STATS block */
17672 uint64_t tx_stat_discard;
17673 /* Total Tx Error Drops per Port reported by STATS block */
17674 uint64_t tx_stat_error;
17677 /* Port Rx Statistics Format */
17678 /* rx_port_stats (size:4224b/528B) */
17679 struct rx_port_stats {
17680 /* Total Number of 64 Bytes frames received */
17681 uint64_t rx_64b_frames;
17682 /* Total Number of 65-127 Bytes frames received */
17683 uint64_t rx_65b_127b_frames;
17684 /* Total Number of 128-255 Bytes frames received */
17685 uint64_t rx_128b_255b_frames;
17686 /* Total Number of 256-511 Bytes frames received */
17687 uint64_t rx_256b_511b_frames;
17688 /* Total Number of 512-1023 Bytes frames received */
17689 uint64_t rx_512b_1023b_frames;
17690 /* Total Number of 1024-1518 Bytes frames received */
17691 uint64_t rx_1024b_1518b_frames;
17693 * Total Number of each good VLAN (exludes FCS errors)
17694 * frame received which is 1519 to 1522 bytes in length
17695 * inclusive (excluding framing bits but including FCS bytes).
17697 uint64_t rx_good_vlan_frames;
17698 /* Total Number of 1519-2047 Bytes frames received */
17699 uint64_t rx_1519b_2047b_frames;
17700 /* Total Number of 2048-4095 Bytes frames received */
17701 uint64_t rx_2048b_4095b_frames;
17702 /* Total Number of 4096-9216 Bytes frames received */
17703 uint64_t rx_4096b_9216b_frames;
17704 /* Total Number of 9217-16383 Bytes frames received */
17705 uint64_t rx_9217b_16383b_frames;
17706 /* Total number of frames received */
17707 uint64_t rx_total_frames;
17708 /* Total number of unicast frames received */
17709 uint64_t rx_ucast_frames;
17710 /* Total number of multicast frames received */
17711 uint64_t rx_mcast_frames;
17712 /* Total number of broadcast frames received */
17713 uint64_t rx_bcast_frames;
17714 /* Total number of received frames with FCS error */
17715 uint64_t rx_fcs_err_frames;
17716 /* Total number of control frames received */
17717 uint64_t rx_ctrl_frames;
17718 /* Total number of PAUSE frames received */
17719 uint64_t rx_pause_frames;
17720 /* Total number of PFC frames received */
17721 uint64_t rx_pfc_frames;
17723 * Total number of frames received with an unsupported
17726 uint64_t rx_unsupported_opcode_frames;
17728 * Total number of frames received with an unsupported
17729 * DA for pause and PFC
17731 uint64_t rx_unsupported_da_pausepfc_frames;
17732 /* Total number of frames received with an unsupported SA */
17733 uint64_t rx_wrong_sa_frames;
17734 /* Total number of received packets with alignment error */
17735 uint64_t rx_align_err_frames;
17736 /* Total number of received frames with out-of-range length */
17737 uint64_t rx_oor_len_frames;
17738 /* Total number of received frames with error termination */
17739 uint64_t rx_code_err_frames;
17741 * Total number of received frames with a false carrier is
17742 * detected during idle, as defined by RX_ER samples active
17743 * and RXD is 0xE. The event is reported along with the
17744 * statistics generated on the next received frame. Only
17745 * one false carrier condition can be detected and logged
17748 * Carrier event, valid for 10M/100M speed modes only.
17750 uint64_t rx_false_carrier_frames;
17751 /* Total number of over-sized frames received */
17752 uint64_t rx_ovrsz_frames;
17753 /* Total number of jabber packets received */
17754 uint64_t rx_jbr_frames;
17755 /* Total number of received frames with MTU error */
17756 uint64_t rx_mtu_err_frames;
17757 /* Total number of received frames with CRC match */
17758 uint64_t rx_match_crc_frames;
17759 /* Total number of frames received promiscuously */
17760 uint64_t rx_promiscuous_frames;
17762 * Total number of received frames with one or two VLAN
17765 uint64_t rx_tagged_frames;
17766 /* Total number of received frames with two VLAN tags */
17767 uint64_t rx_double_tagged_frames;
17768 /* Total number of truncated frames received */
17769 uint64_t rx_trunc_frames;
17770 /* Total number of good frames (without errors) received */
17771 uint64_t rx_good_frames;
17773 * Total number of received PFC frames with transition from
17774 * XON to XOFF on Pri 0
17776 uint64_t rx_pfc_xon2xoff_frames_pri0;
17778 * Total number of received PFC frames with transition from
17779 * XON to XOFF on Pri 1
17781 uint64_t rx_pfc_xon2xoff_frames_pri1;
17783 * Total number of received PFC frames with transition from
17784 * XON to XOFF on Pri 2
17786 uint64_t rx_pfc_xon2xoff_frames_pri2;
17788 * Total number of received PFC frames with transition from
17789 * XON to XOFF on Pri 3
17791 uint64_t rx_pfc_xon2xoff_frames_pri3;
17793 * Total number of received PFC frames with transition from
17794 * XON to XOFF on Pri 4
17796 uint64_t rx_pfc_xon2xoff_frames_pri4;
17798 * Total number of received PFC frames with transition from
17799 * XON to XOFF on Pri 5
17801 uint64_t rx_pfc_xon2xoff_frames_pri5;
17803 * Total number of received PFC frames with transition from
17804 * XON to XOFF on Pri 6
17806 uint64_t rx_pfc_xon2xoff_frames_pri6;
17808 * Total number of received PFC frames with transition from
17809 * XON to XOFF on Pri 7
17811 uint64_t rx_pfc_xon2xoff_frames_pri7;
17813 * Total number of received PFC frames with PFC enabled
17816 uint64_t rx_pfc_ena_frames_pri0;
17818 * Total number of received PFC frames with PFC enabled
17821 uint64_t rx_pfc_ena_frames_pri1;
17823 * Total number of received PFC frames with PFC enabled
17826 uint64_t rx_pfc_ena_frames_pri2;
17828 * Total number of received PFC frames with PFC enabled
17831 uint64_t rx_pfc_ena_frames_pri3;
17833 * Total number of received PFC frames with PFC enabled
17836 uint64_t rx_pfc_ena_frames_pri4;
17838 * Total number of received PFC frames with PFC enabled
17841 uint64_t rx_pfc_ena_frames_pri5;
17843 * Total number of received PFC frames with PFC enabled
17846 uint64_t rx_pfc_ena_frames_pri6;
17848 * Total number of received PFC frames with PFC enabled
17851 uint64_t rx_pfc_ena_frames_pri7;
17852 /* Total Number of frames received with SCH CRC error */
17853 uint64_t rx_sch_crc_err_frames;
17854 /* Total Number of under-sized frames received */
17855 uint64_t rx_undrsz_frames;
17856 /* Total Number of fragmented frames received */
17857 uint64_t rx_frag_frames;
17858 /* Total number of RX EEE LPI Events */
17859 uint64_t rx_eee_lpi_events;
17860 /* EEE LPI Duration Counter on RX */
17861 uint64_t rx_eee_lpi_duration;
17863 * Total number of physical type Link Level Flow Control
17864 * (LLFC) messages received
17866 uint64_t rx_llfc_physical_msgs;
17868 * Total number of logical type Link Level Flow Control
17869 * (LLFC) messages received
17871 uint64_t rx_llfc_logical_msgs;
17873 * Total number of logical type Link Level Flow Control
17874 * (LLFC) messages received with CRC error
17876 uint64_t rx_llfc_msgs_with_crc_err;
17877 /* Total number of HCFC messages received */
17878 uint64_t rx_hcfc_msgs;
17879 /* Total number of HCFC messages received with CRC error */
17880 uint64_t rx_hcfc_msgs_with_crc_err;
17881 /* Total number of received bytes */
17883 /* Total number of bytes received in runt frames */
17884 uint64_t rx_runt_bytes;
17885 /* Total number of runt frames received */
17886 uint64_t rx_runt_frames;
17887 /* Total Rx Discards per Port reported by STATS block */
17888 uint64_t rx_stat_discard;
17889 uint64_t rx_stat_err;
17892 /********************
17893 * hwrm_port_qstats *
17894 ********************/
17897 /* hwrm_port_qstats_input (size:320b/40B) */
17898 struct hwrm_port_qstats_input {
17899 /* The HWRM command request type. */
17902 * The completion ring to send the completion event on. This should
17903 * be the NQ ID returned from the `nq_alloc` HWRM command.
17905 uint16_t cmpl_ring;
17907 * The sequence ID is used by the driver for tracking multiple
17908 * commands. This ID is treated as opaque data by the firmware and
17909 * the value is returned in the `hwrm_resp_hdr` upon completion.
17913 * The target ID of the command:
17914 * * 0x0-0xFFF8 - The function ID
17915 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17916 * * 0xFFFD - Reserved for user-space HWRM interface
17919 uint16_t target_id;
17921 * A physical address pointer pointing to a host buffer that the
17922 * command's response data will be written. This can be either a host
17923 * physical address (HPA) or a guest physical address (GPA) and must
17924 * point to a physically contiguous block of memory.
17926 uint64_t resp_addr;
17927 /* Port ID of port that is being queried. */
17930 /* This value is not used to avoid backward compatibility issues. */
17931 #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)
17933 * This bit is set to 1 when request is for a counter mask,
17934 * representing the width of each of the stats counters, rather
17935 * than counters themselves.
17937 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
17938 #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \
17939 HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK
17940 uint8_t unused_0[5];
17942 * This is the host address where
17943 * Tx port statistics will be stored
17945 uint64_t tx_stat_host_addr;
17947 * This is the host address where
17948 * Rx port statistics will be stored
17950 uint64_t rx_stat_host_addr;
17953 /* hwrm_port_qstats_output (size:128b/16B) */
17954 struct hwrm_port_qstats_output {
17955 /* The specific error status for the command. */
17956 uint16_t error_code;
17957 /* The HWRM command request type. */
17959 /* The sequence ID from the original command. */
17961 /* The length of the response data in number of bytes. */
17963 /* The size of TX port statistics block in bytes. */
17964 uint16_t tx_stat_size;
17965 /* The size of RX port statistics block in bytes. */
17966 uint16_t rx_stat_size;
17967 uint8_t unused_0[3];
17969 * This field is used in Output records to indicate that the output
17970 * is completely written to RAM. This field should be read as '1'
17971 * to indicate that the output has been completely written.
17972 * When writing a command completion or response to an internal processor,
17973 * the order of writes has to be such that this field is written last.
17978 /* Port Tx Statistics extended Format */
17979 /* tx_port_stats_ext (size:2048b/256B) */
17980 struct tx_port_stats_ext {
17981 /* Total number of tx bytes count on cos queue 0 */
17982 uint64_t tx_bytes_cos0;
17983 /* Total number of tx bytes count on cos queue 1 */
17984 uint64_t tx_bytes_cos1;
17985 /* Total number of tx bytes count on cos queue 2 */
17986 uint64_t tx_bytes_cos2;
17987 /* Total number of tx bytes count on cos queue 3 */
17988 uint64_t tx_bytes_cos3;
17989 /* Total number of tx bytes count on cos queue 4 */
17990 uint64_t tx_bytes_cos4;
17991 /* Total number of tx bytes count on cos queue 5 */
17992 uint64_t tx_bytes_cos5;
17993 /* Total number of tx bytes count on cos queue 6 */
17994 uint64_t tx_bytes_cos6;
17995 /* Total number of tx bytes count on cos queue 7 */
17996 uint64_t tx_bytes_cos7;
17997 /* Total number of tx packets count on cos queue 0 */
17998 uint64_t tx_packets_cos0;
17999 /* Total number of tx packets count on cos queue 1 */
18000 uint64_t tx_packets_cos1;
18001 /* Total number of tx packets count on cos queue 2 */
18002 uint64_t tx_packets_cos2;
18003 /* Total number of tx packets count on cos queue 3 */
18004 uint64_t tx_packets_cos3;
18005 /* Total number of tx packets count on cos queue 4 */
18006 uint64_t tx_packets_cos4;
18007 /* Total number of tx packets count on cos queue 5 */
18008 uint64_t tx_packets_cos5;
18009 /* Total number of tx packets count on cos queue 6 */
18010 uint64_t tx_packets_cos6;
18011 /* Total number of tx packets count on cos queue 7 */
18012 uint64_t tx_packets_cos7;
18013 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18014 uint64_t pfc_pri0_tx_duration_us;
18015 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18016 uint64_t pfc_pri0_tx_transitions;
18017 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18018 uint64_t pfc_pri1_tx_duration_us;
18019 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18020 uint64_t pfc_pri1_tx_transitions;
18021 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18022 uint64_t pfc_pri2_tx_duration_us;
18023 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18024 uint64_t pfc_pri2_tx_transitions;
18025 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18026 uint64_t pfc_pri3_tx_duration_us;
18027 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18028 uint64_t pfc_pri3_tx_transitions;
18029 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18030 uint64_t pfc_pri4_tx_duration_us;
18031 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18032 uint64_t pfc_pri4_tx_transitions;
18033 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18034 uint64_t pfc_pri5_tx_duration_us;
18035 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18036 uint64_t pfc_pri5_tx_transitions;
18037 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18038 uint64_t pfc_pri6_tx_duration_us;
18039 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18040 uint64_t pfc_pri6_tx_transitions;
18041 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18042 uint64_t pfc_pri7_tx_duration_us;
18043 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18044 uint64_t pfc_pri7_tx_transitions;
18047 /* Port Rx Statistics extended Format */
18048 /* rx_port_stats_ext (size:3648b/456B) */
18049 struct rx_port_stats_ext {
18050 /* Number of times link state changed to down */
18051 uint64_t link_down_events;
18052 /* Number of times the idle rings with pause bit are found */
18053 uint64_t continuous_pause_events;
18054 /* Number of times the active rings pause bit resumed back */
18055 uint64_t resume_pause_events;
18056 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
18057 uint64_t continuous_roce_pause_events;
18058 /* Number of times, the ROCE cos queue PFC is enabled back */
18059 uint64_t resume_roce_pause_events;
18060 /* Total number of rx bytes count on cos queue 0 */
18061 uint64_t rx_bytes_cos0;
18062 /* Total number of rx bytes count on cos queue 1 */
18063 uint64_t rx_bytes_cos1;
18064 /* Total number of rx bytes count on cos queue 2 */
18065 uint64_t rx_bytes_cos2;
18066 /* Total number of rx bytes count on cos queue 3 */
18067 uint64_t rx_bytes_cos3;
18068 /* Total number of rx bytes count on cos queue 4 */
18069 uint64_t rx_bytes_cos4;
18070 /* Total number of rx bytes count on cos queue 5 */
18071 uint64_t rx_bytes_cos5;
18072 /* Total number of rx bytes count on cos queue 6 */
18073 uint64_t rx_bytes_cos6;
18074 /* Total number of rx bytes count on cos queue 7 */
18075 uint64_t rx_bytes_cos7;
18076 /* Total number of rx packets count on cos queue 0 */
18077 uint64_t rx_packets_cos0;
18078 /* Total number of rx packets count on cos queue 1 */
18079 uint64_t rx_packets_cos1;
18080 /* Total number of rx packets count on cos queue 2 */
18081 uint64_t rx_packets_cos2;
18082 /* Total number of rx packets count on cos queue 3 */
18083 uint64_t rx_packets_cos3;
18084 /* Total number of rx packets count on cos queue 4 */
18085 uint64_t rx_packets_cos4;
18086 /* Total number of rx packets count on cos queue 5 */
18087 uint64_t rx_packets_cos5;
18088 /* Total number of rx packets count on cos queue 6 */
18089 uint64_t rx_packets_cos6;
18090 /* Total number of rx packets count on cos queue 7 */
18091 uint64_t rx_packets_cos7;
18092 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
18093 uint64_t pfc_pri0_rx_duration_us;
18094 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
18095 uint64_t pfc_pri0_rx_transitions;
18096 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */
18097 uint64_t pfc_pri1_rx_duration_us;
18098 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */
18099 uint64_t pfc_pri1_rx_transitions;
18100 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */
18101 uint64_t pfc_pri2_rx_duration_us;
18102 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */
18103 uint64_t pfc_pri2_rx_transitions;
18104 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */
18105 uint64_t pfc_pri3_rx_duration_us;
18106 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */
18107 uint64_t pfc_pri3_rx_transitions;
18108 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */
18109 uint64_t pfc_pri4_rx_duration_us;
18110 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */
18111 uint64_t pfc_pri4_rx_transitions;
18112 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */
18113 uint64_t pfc_pri5_rx_duration_us;
18114 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */
18115 uint64_t pfc_pri5_rx_transitions;
18116 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */
18117 uint64_t pfc_pri6_rx_duration_us;
18118 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */
18119 uint64_t pfc_pri6_rx_transitions;
18120 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */
18121 uint64_t pfc_pri7_rx_duration_us;
18122 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
18123 uint64_t pfc_pri7_rx_transitions;
18124 /* Total number of received bits */
18126 /* The number of events where the port receive buffer was over 85% full */
18127 uint64_t rx_buffer_passed_threshold;
18129 * The number of symbol errors that wasn't corrected by FEC correction
18132 uint64_t rx_pcs_symbol_err;
18133 /* The number of corrected bits on the port according to active FEC */
18134 uint64_t rx_corrected_bits;
18135 /* Total number of rx discard bytes count on cos queue 0 */
18136 uint64_t rx_discard_bytes_cos0;
18137 /* Total number of rx discard bytes count on cos queue 1 */
18138 uint64_t rx_discard_bytes_cos1;
18139 /* Total number of rx discard bytes count on cos queue 2 */
18140 uint64_t rx_discard_bytes_cos2;
18141 /* Total number of rx discard bytes count on cos queue 3 */
18142 uint64_t rx_discard_bytes_cos3;
18143 /* Total number of rx discard bytes count on cos queue 4 */
18144 uint64_t rx_discard_bytes_cos4;
18145 /* Total number of rx discard bytes count on cos queue 5 */
18146 uint64_t rx_discard_bytes_cos5;
18147 /* Total number of rx discard bytes count on cos queue 6 */
18148 uint64_t rx_discard_bytes_cos6;
18149 /* Total number of rx discard bytes count on cos queue 7 */
18150 uint64_t rx_discard_bytes_cos7;
18151 /* Total number of rx discard packets count on cos queue 0 */
18152 uint64_t rx_discard_packets_cos0;
18153 /* Total number of rx discard packets count on cos queue 1 */
18154 uint64_t rx_discard_packets_cos1;
18155 /* Total number of rx discard packets count on cos queue 2 */
18156 uint64_t rx_discard_packets_cos2;
18157 /* Total number of rx discard packets count on cos queue 3 */
18158 uint64_t rx_discard_packets_cos3;
18159 /* Total number of rx discard packets count on cos queue 4 */
18160 uint64_t rx_discard_packets_cos4;
18161 /* Total number of rx discard packets count on cos queue 5 */
18162 uint64_t rx_discard_packets_cos5;
18163 /* Total number of rx discard packets count on cos queue 6 */
18164 uint64_t rx_discard_packets_cos6;
18165 /* Total number of rx discard packets count on cos queue 7 */
18166 uint64_t rx_discard_packets_cos7;
18170 * Port Rx Statistics extended PFC WatchDog Format.
18171 * StormDetect and StormRevert event determination is based
18172 * on an integration period and a percentage threshold.
18173 * StormDetect event - when percentage of XOFF frames received
18174 * within an integration period exceeds the configured threshold.
18175 * StormRevert event - when percentage of XON frames received
18176 * within an integration period exceeds the configured threshold.
18177 * Actual number of XOFF/XON frames for the events to be triggered
18178 * depends on both configured integration period and sampling rate.
18179 * The statistics in this structure represent counts of specified
18180 * events from the moment the feature (PFC WatchDog) is enabled via
18181 * hwrm_queue_pfc_enable_cfg call.
18183 /* rx_port_stats_ext_pfc_wd (size:5120b/640B) */
18184 struct rx_port_stats_ext_pfc_wd {
18186 * Total number of PFC WatchDog StormDetect events detected
18189 uint64_t rx_pfc_watchdog_storms_detected_pri0;
18191 * Total number of PFC WatchDog StormDetect events detected
18194 uint64_t rx_pfc_watchdog_storms_detected_pri1;
18196 * Total number of PFC WatchDog StormDetect events detected
18199 uint64_t rx_pfc_watchdog_storms_detected_pri2;
18201 * Total number of PFC WatchDog StormDetect events detected
18204 uint64_t rx_pfc_watchdog_storms_detected_pri3;
18206 * Total number of PFC WatchDog StormDetect events detected
18209 uint64_t rx_pfc_watchdog_storms_detected_pri4;
18211 * Total number of PFC WatchDog StormDetect events detected
18214 uint64_t rx_pfc_watchdog_storms_detected_pri5;
18216 * Total number of PFC WatchDog StormDetect events detected
18219 uint64_t rx_pfc_watchdog_storms_detected_pri6;
18221 * Total number of PFC WatchDog StormDetect events detected
18224 uint64_t rx_pfc_watchdog_storms_detected_pri7;
18226 * Total number of PFC WatchDog StormRevert events detected
18229 uint64_t rx_pfc_watchdog_storms_reverted_pri0;
18231 * Total number of PFC WatchDog StormRevert events detected
18234 uint64_t rx_pfc_watchdog_storms_reverted_pri1;
18236 * Total number of PFC WatchDog StormRevert events detected
18239 uint64_t rx_pfc_watchdog_storms_reverted_pri2;
18241 * Total number of PFC WatchDog StormRevert events detected
18244 uint64_t rx_pfc_watchdog_storms_reverted_pri3;
18246 * Total number of PFC WatchDog StormRevert events detected
18249 uint64_t rx_pfc_watchdog_storms_reverted_pri4;
18251 * Total number of PFC WatchDog StormRevert events detected
18254 uint64_t rx_pfc_watchdog_storms_reverted_pri5;
18256 * Total number of PFC WatchDog StormRevert events detected
18259 uint64_t rx_pfc_watchdog_storms_reverted_pri6;
18261 * Total number of PFC WatchDog StormRevert events detected
18264 uint64_t rx_pfc_watchdog_storms_reverted_pri7;
18266 * Total number of packets received during PFC watchdog storm
18269 uint64_t rx_pfc_watchdog_storms_rx_packets_pri0;
18271 * Total number of packets received during PFC watchdog storm
18274 uint64_t rx_pfc_watchdog_storms_rx_packets_pri1;
18276 * Total number of packets received during PFC watchdog storm
18279 uint64_t rx_pfc_watchdog_storms_rx_packets_pri2;
18281 * Total number of packets received during PFC watchdog storm
18284 uint64_t rx_pfc_watchdog_storms_rx_packets_pri3;
18286 * Total number of packets received during PFC watchdog storm
18289 uint64_t rx_pfc_watchdog_storms_rx_packets_pri4;
18291 * Total number of packets received during PFC watchdog storm
18294 uint64_t rx_pfc_watchdog_storms_rx_packets_pri5;
18296 * Total number of packets received during PFC watchdog storm
18299 uint64_t rx_pfc_watchdog_storms_rx_packets_pri6;
18301 * Total number of packets received during PFC watchdog storm
18304 uint64_t rx_pfc_watchdog_storms_rx_packets_pri7;
18306 * Total number of bytes received during PFC watchdog storm
18309 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0;
18311 * Total number of bytes received during PFC watchdog storm
18314 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1;
18316 * Total number of bytes received during PFC watchdog storm
18319 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2;
18321 * Total number of bytes received during PFC watchdog storm
18324 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3;
18326 * Total number of bytes received during PFC watchdog storm
18329 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4;
18331 * Total number of bytes received during PFC watchdog storm
18334 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5;
18336 * Total number of bytes received during PFC watchdog storm
18339 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6;
18341 * Total number of bytes received during PFC watchdog storm
18344 uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7;
18346 * Total number of packets dropped on rx during PFC watchdog storm
18349 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0;
18351 * Total number of packets dropped on rx during PFC watchdog storm
18354 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1;
18356 * Total number of packets dropped on rx during PFC watchdog storm
18359 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2;
18361 * Total number of packets dropped on rx during PFC watchdog storm
18364 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3;
18366 * Total number of packets dropped on rx during PFC watchdog storm
18369 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4;
18371 * Total number of packets dropped on rx during PFC watchdog storm
18374 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5;
18376 * Total number of packets dropped on rx during PFC watchdog storm
18379 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6;
18381 * Total number of packets dropped on rx during PFC watchdog storm
18384 uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7;
18386 * Total number of bytes dropped on rx during PFC watchdog storm
18389 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0;
18391 * Total number of bytes dropped on rx during PFC watchdog storm
18394 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1;
18396 * Total number of bytes dropped on rx during PFC watchdog storm
18399 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2;
18401 * Total number of bytes dropped on rx during PFC watchdog storm
18404 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3;
18406 * Total number of bytes dropped on rx during PFC watchdog storm
18409 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4;
18411 * Total number of bytes dropped on rx during PFC watchdog storm
18414 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5;
18416 * Total number of bytes dropped on rx during PFC watchdog storm
18419 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6;
18421 * Total number of bytes dropped on rx during PFC watchdog storm
18424 uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7;
18426 * Number of packets received during last PFC watchdog storm
18429 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0;
18431 * Number of packets received during last PFC watchdog storm
18434 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1;
18436 * Number of packets received during last PFC watchdog storm
18439 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2;
18441 * Number of packets received during last PFC watchdog storm
18444 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3;
18446 * Number of packets received during last PFC watchdog storm
18449 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4;
18451 * Number of packets received during last PFC watchdog storm
18454 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5;
18456 * Number of packets received during last PFC watchdog storm
18459 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6;
18461 * Number of packets received during last PFC watchdog storm
18464 uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7;
18466 * Number of bytes received during last PFC watchdog storm
18469 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0;
18471 * Number of bytes received during last PFC watchdog storm
18474 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1;
18476 * Number of bytes received during last PFC watchdog storm
18479 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2;
18481 * Number of bytes received during last PFC watchdog storm
18484 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3;
18486 * Number of bytes received during last PFC watchdog storm
18489 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4;
18491 * Number of bytes received during last PFC watchdog storm
18494 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5;
18496 * Number of bytes received during last PFC watchdog storm
18499 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6;
18501 * Number of bytes received during last PFC watchdog storm
18504 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7;
18506 * Number of packets dropped on rx during last PFC watchdog storm
18509 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;
18511 * Number of packets dropped on rx during last PFC watchdog storm
18514 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;
18516 * Number of packets dropped on rx during last PFC watchdog storm
18519 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;
18521 * Number of packets dropped on rx during last PFC watchdog storm
18524 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;
18526 * Number of packets dropped on rx during last PFC watchdog storm
18529 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;
18531 * Number of packets dropped on rx during last PFC watchdog storm
18534 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;
18536 * Number of packets dropped on rx during last PFC watchdog storm
18539 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;
18541 * Number of packets dropped on rx during last PFC watchdog storm
18544 uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;
18546 * Total number of bytes dropped on rx during PFC watchdog storm
18549 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;
18551 * Number of bytes dropped on rx during last PFC watchdog storm
18554 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;
18556 * Number of bytes dropped on rx during last PFC watchdog storm
18559 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;
18561 * Number of bytes dropped on rx during last PFC watchdog storm
18564 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;
18566 * Number of bytes dropped on rx during last PFC watchdog storm
18569 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;
18571 * Number of bytes dropped on rx during last PFC watchdog storm
18574 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;
18576 * Number of bytes dropped on rx during last PFC watchdog storm
18579 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;
18581 * Number of bytes dropped on rx during last PFC watchdog storm
18584 uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;
18587 /************************
18588 * hwrm_port_qstats_ext *
18589 ************************/
18592 /* hwrm_port_qstats_ext_input (size:320b/40B) */
18593 struct hwrm_port_qstats_ext_input {
18594 /* The HWRM command request type. */
18597 * The completion ring to send the completion event on. This should
18598 * be the NQ ID returned from the `nq_alloc` HWRM command.
18600 uint16_t cmpl_ring;
18602 * The sequence ID is used by the driver for tracking multiple
18603 * commands. This ID is treated as opaque data by the firmware and
18604 * the value is returned in the `hwrm_resp_hdr` upon completion.
18608 * The target ID of the command:
18609 * * 0x0-0xFFF8 - The function ID
18610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18611 * * 0xFFFD - Reserved for user-space HWRM interface
18614 uint16_t target_id;
18616 * A physical address pointer pointing to a host buffer that the
18617 * command's response data will be written. This can be either a host
18618 * physical address (HPA) or a guest physical address (GPA) and must
18619 * point to a physically contiguous block of memory.
18621 uint64_t resp_addr;
18622 /* Port ID of port that is being queried. */
18625 * The size of TX port extended
18626 * statistics block in bytes.
18628 uint16_t tx_stat_size;
18630 * The size of RX port extended
18631 * statistics block in bytes
18633 uint16_t rx_stat_size;
18635 /* This value is not used to avoid backward compatibility issues. */
18636 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)
18638 * This bit is set to 1 when request is for the counter mask,
18639 * representing width of each of the stats counters, rather than
18640 * counters themselves.
18642 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
18643 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \
18644 HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK
18647 * This is the host address where
18648 * Tx port statistics will be stored
18650 uint64_t tx_stat_host_addr;
18652 * This is the host address where
18653 * Rx port statistics will be stored
18655 uint64_t rx_stat_host_addr;
18658 /* hwrm_port_qstats_ext_output (size:128b/16B) */
18659 struct hwrm_port_qstats_ext_output {
18660 /* The specific error status for the command. */
18661 uint16_t error_code;
18662 /* The HWRM command request type. */
18664 /* The sequence ID from the original command. */
18666 /* The length of the response data in number of bytes. */
18668 /* The size of TX port statistics block in bytes. */
18669 uint16_t tx_stat_size;
18670 /* The size of RX port statistics block in bytes. */
18671 uint16_t rx_stat_size;
18672 /* Total number of active cos queues available. */
18673 uint16_t total_active_cos_queues;
18676 * If set to 1, then this field indicates that clear
18677 * roce specific counters is supported.
18679 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \
18682 * This field is used in Output records to indicate that the output
18683 * is completely written to RAM. This field should be read as '1'
18684 * to indicate that the output has been completely written.
18685 * When writing a command completion or response to an internal processor,
18686 * the order of writes has to be such that this field is written last.
18691 /*******************************
18692 * hwrm_port_qstats_ext_pfc_wd *
18693 *******************************/
18696 /* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */
18697 struct hwrm_port_qstats_ext_pfc_wd_input {
18698 /* The HWRM command request type. */
18701 * The completion ring to send the completion event on. This should
18702 * be the NQ ID returned from the `nq_alloc` HWRM command.
18704 uint16_t cmpl_ring;
18706 * The sequence ID is used by the driver for tracking multiple
18707 * commands. This ID is treated as opaque data by the firmware and
18708 * the value is returned in the `hwrm_resp_hdr` upon completion.
18712 * The target ID of the command:
18713 * * 0x0-0xFFF8 - The function ID
18714 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18715 * * 0xFFFD - Reserved for user-space HWRM interface
18718 uint16_t target_id;
18720 * A physical address pointer pointing to a host buffer that the
18721 * command's response data will be written. This can be either a host
18722 * physical address (HPA) or a guest physical address (GPA) and must
18723 * point to a physically contiguous block of memory.
18725 uint64_t resp_addr;
18726 /* Port ID of port that is being queried. */
18729 * The size of rx_port_stats_ext_pfc_wd
18732 uint16_t pfc_wd_stat_size;
18733 uint8_t unused_0[4];
18735 * This is the host address where
18736 * rx_port_stats_ext_pfc_wd will be stored
18738 uint64_t pfc_wd_stat_host_addr;
18741 /* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */
18742 struct hwrm_port_qstats_ext_pfc_wd_output {
18743 /* The specific error status for the command. */
18744 uint16_t error_code;
18745 /* The HWRM command request type. */
18747 /* The sequence ID from the original command. */
18749 /* The length of the response data in number of bytes. */
18752 * The size of rx_port_stats_ext_pfc_wd
18753 * statistics block in bytes.
18755 uint16_t pfc_wd_stat_size;
18758 * This field is used in Output records to indicate that the output
18759 * is completely written to RAM. This field should be read as '1'
18760 * to indicate that the output has been completely written.
18761 * When writing a command completion or response to an internal processor,
18762 * the order of writes has to be such that this field is written last.
18765 uint8_t unused_0[4];
18768 /*************************
18769 * hwrm_port_lpbk_qstats *
18770 *************************/
18773 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
18774 struct hwrm_port_lpbk_qstats_input {
18775 /* The HWRM command request type. */
18778 * The completion ring to send the completion event on. This should
18779 * be the NQ ID returned from the `nq_alloc` HWRM command.
18781 uint16_t cmpl_ring;
18783 * The sequence ID is used by the driver for tracking multiple
18784 * commands. This ID is treated as opaque data by the firmware and
18785 * the value is returned in the `hwrm_resp_hdr` upon completion.
18789 * The target ID of the command:
18790 * * 0x0-0xFFF8 - The function ID
18791 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18792 * * 0xFFFD - Reserved for user-space HWRM interface
18795 uint16_t target_id;
18797 * A physical address pointer pointing to a host buffer that the
18798 * command's response data will be written. This can be either a host
18799 * physical address (HPA) or a guest physical address (GPA) and must
18800 * point to a physically contiguous block of memory.
18802 uint64_t resp_addr;
18805 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
18806 struct hwrm_port_lpbk_qstats_output {
18807 /* The specific error status for the command. */
18808 uint16_t error_code;
18809 /* The HWRM command request type. */
18811 /* The sequence ID from the original command. */
18813 /* The length of the response data in number of bytes. */
18815 /* Number of transmitted unicast frames */
18816 uint64_t lpbk_ucast_frames;
18817 /* Number of transmitted multicast frames */
18818 uint64_t lpbk_mcast_frames;
18819 /* Number of transmitted broadcast frames */
18820 uint64_t lpbk_bcast_frames;
18821 /* Number of transmitted bytes for unicast traffic */
18822 uint64_t lpbk_ucast_bytes;
18823 /* Number of transmitted bytes for multicast traffic */
18824 uint64_t lpbk_mcast_bytes;
18825 /* Number of transmitted bytes for broadcast traffic */
18826 uint64_t lpbk_bcast_bytes;
18827 /* Total Tx Drops for loopback traffic reported by STATS block */
18828 uint64_t tx_stat_discard;
18829 /* Total Tx Error Drops for loopback traffic reported by STATS block */
18830 uint64_t tx_stat_error;
18831 /* Total Rx Drops for loopback traffic reported by STATS block */
18832 uint64_t rx_stat_discard;
18833 /* Total Rx Error Drops for loopback traffic reported by STATS block */
18834 uint64_t rx_stat_error;
18835 uint8_t unused_0[7];
18837 * This field is used in Output records to indicate that the output
18838 * is completely written to RAM. This field should be read as '1'
18839 * to indicate that the output has been completely written.
18840 * When writing a command completion or response to an internal processor,
18841 * the order of writes has to be such that this field is written last.
18846 /************************
18847 * hwrm_port_ecn_qstats *
18848 ************************/
18851 /* hwrm_port_ecn_qstats_input (size:192b/24B) */
18852 struct hwrm_port_ecn_qstats_input {
18853 /* The HWRM command request type. */
18856 * The completion ring to send the completion event on. This should
18857 * be the NQ ID returned from the `nq_alloc` HWRM command.
18859 uint16_t cmpl_ring;
18861 * The sequence ID is used by the driver for tracking multiple
18862 * commands. This ID is treated as opaque data by the firmware and
18863 * the value is returned in the `hwrm_resp_hdr` upon completion.
18867 * The target ID of the command:
18868 * * 0x0-0xFFF8 - The function ID
18869 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18870 * * 0xFFFD - Reserved for user-space HWRM interface
18873 uint16_t target_id;
18875 * A physical address pointer pointing to a host buffer that the
18876 * command's response data will be written. This can be either a host
18877 * physical address (HPA) or a guest physical address (GPA) and must
18878 * point to a physically contiguous block of memory.
18880 uint64_t resp_addr;
18882 * Port ID of port that is being queried. Unused if NIC is in
18886 uint8_t unused_0[6];
18889 /* hwrm_port_ecn_qstats_output (size:384b/48B) */
18890 struct hwrm_port_ecn_qstats_output {
18891 /* The specific error status for the command. */
18892 uint16_t error_code;
18893 /* The HWRM command request type. */
18895 /* The sequence ID from the original command. */
18897 /* The length of the response data in number of bytes. */
18899 /* Number of packets marked in CoS queue 0. */
18900 uint32_t mark_cnt_cos0;
18901 /* Number of packets marked in CoS queue 1. */
18902 uint32_t mark_cnt_cos1;
18903 /* Number of packets marked in CoS queue 2. */
18904 uint32_t mark_cnt_cos2;
18905 /* Number of packets marked in CoS queue 3. */
18906 uint32_t mark_cnt_cos3;
18907 /* Number of packets marked in CoS queue 4. */
18908 uint32_t mark_cnt_cos4;
18909 /* Number of packets marked in CoS queue 5. */
18910 uint32_t mark_cnt_cos5;
18911 /* Number of packets marked in CoS queue 6. */
18912 uint32_t mark_cnt_cos6;
18913 /* Number of packets marked in CoS queue 7. */
18914 uint32_t mark_cnt_cos7;
18916 * Bitmask that indicates which CoS queues have ECN marking enabled.
18917 * Bit i corresponds to CoS queue i.
18920 uint8_t unused_0[6];
18922 * This field is used in Output records to indicate that the output
18923 * is completely written to RAM. This field should be read as '1'
18924 * to indicate that the output has been completely written.
18925 * When writing a command completion or response to an internal processor,
18926 * the order of writes has to be such that this field is written last.
18931 /***********************
18932 * hwrm_port_clr_stats *
18933 ***********************/
18936 /* hwrm_port_clr_stats_input (size:192b/24B) */
18937 struct hwrm_port_clr_stats_input {
18938 /* The HWRM command request type. */
18941 * The completion ring to send the completion event on. This should
18942 * be the NQ ID returned from the `nq_alloc` HWRM command.
18944 uint16_t cmpl_ring;
18946 * The sequence ID is used by the driver for tracking multiple
18947 * commands. This ID is treated as opaque data by the firmware and
18948 * the value is returned in the `hwrm_resp_hdr` upon completion.
18952 * The target ID of the command:
18953 * * 0x0-0xFFF8 - The function ID
18954 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18955 * * 0xFFFD - Reserved for user-space HWRM interface
18958 uint16_t target_id;
18960 * A physical address pointer pointing to a host buffer that the
18961 * command's response data will be written. This can be either a host
18962 * physical address (HPA) or a guest physical address (GPA) and must
18963 * point to a physically contiguous block of memory.
18965 uint64_t resp_addr;
18966 /* Port ID of port that is being queried. */
18970 * If set to 1, then this field indicates clear the following RoCE
18971 * specific counters.
18972 * RoCE associated TX/RX cos counters
18973 * CNP associated TX/RX cos counters
18974 * RoCE/CNP specific TX/RX flow counters
18975 * Firmware will determine the RoCE/CNP cos queue based on qos profile.
18976 * This flag is honored only when RoCE is enabled on that port.
18978 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
18979 uint8_t unused_0[5];
18982 /* hwrm_port_clr_stats_output (size:128b/16B) */
18983 struct hwrm_port_clr_stats_output {
18984 /* The specific error status for the command. */
18985 uint16_t error_code;
18986 /* The HWRM command request type. */
18988 /* The sequence ID from the original command. */
18990 /* The length of the response data in number of bytes. */
18992 uint8_t unused_0[7];
18994 * This field is used in Output records to indicate that the output
18995 * is completely written to RAM. This field should be read as '1'
18996 * to indicate that the output has been completely written.
18997 * When writing a command completion or response to an internal processor,
18998 * the order of writes has to be such that this field is written last.
19003 /***********************
19004 * hwrm_port_phy_qcaps *
19005 ***********************/
19008 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
19009 struct hwrm_port_phy_qcaps_input {
19010 /* The HWRM command request type. */
19013 * The completion ring to send the completion event on. This should
19014 * be the NQ ID returned from the `nq_alloc` HWRM command.
19016 uint16_t cmpl_ring;
19018 * The sequence ID is used by the driver for tracking multiple
19019 * commands. This ID is treated as opaque data by the firmware and
19020 * the value is returned in the `hwrm_resp_hdr` upon completion.
19024 * The target ID of the command:
19025 * * 0x0-0xFFF8 - The function ID
19026 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19027 * * 0xFFFD - Reserved for user-space HWRM interface
19030 uint16_t target_id;
19032 * A physical address pointer pointing to a host buffer that the
19033 * command's response data will be written. This can be either a host
19034 * physical address (HPA) or a guest physical address (GPA) and must
19035 * point to a physically contiguous block of memory.
19037 uint64_t resp_addr;
19038 /* Port ID of port that is being queried. */
19040 uint8_t unused_0[6];
19043 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
19044 struct hwrm_port_phy_qcaps_output {
19045 /* The specific error status for the command. */
19046 uint16_t error_code;
19047 /* The HWRM command request type. */
19049 /* The sequence ID from the original command. */
19051 /* The length of the response data in number of bytes. */
19053 /* PHY capability flags */
19056 * If set to 1, then this field indicates that the
19057 * link is capable of supporting EEE.
19059 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
19062 * If set to 1, then this field indicates that the
19063 * PHY is capable of supporting external loopback.
19065 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
19068 * If set to 1, then this field indicates that the
19069 * PHY is capable of supporting loopback in autoneg mode.
19071 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED \
19074 * Indicates if the configuration of shared PHY settings is supported.
19075 * In cases where a physical port is shared by multiple functions
19076 * (e.g. NPAR, multihost, etc), the configuration of PHY
19077 * settings may not be allowed. Callers to HWRM_PORT_PHY_CFG will
19078 * get an HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED error in this case.
19080 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED \
19083 * Reserved field. The HWRM shall set this field to 0.
19084 * An HWRM client shall ignore this field.
19086 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
19088 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 4
19089 /* Number of front panel ports for this device. */
19091 /* Not supported or unknown */
19092 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
19093 /* single port device */
19094 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
19095 /* 2-port device */
19096 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
19097 /* 3-port device */
19098 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
19099 /* 4-port device */
19100 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
19101 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
19102 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
19104 * This is a bit mask to indicate what speeds are supported
19105 * as forced speeds on this link.
19106 * For each speed that can be forced on this link, the
19107 * corresponding mask bit shall be set to '1'.
19109 uint16_t supported_speeds_force_mode;
19110 /* 100Mb link speed (Half-duplex) */
19111 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
19113 /* 100Mb link speed (Full-duplex) */
19114 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
19116 /* 1Gb link speed (Half-duplex) */
19117 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
19119 /* 1Gb link speed (Full-duplex) */
19120 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
19122 /* 2Gb link speed */
19123 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
19125 /* 25Gb link speed */
19126 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
19128 /* 10Gb link speed */
19129 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
19131 /* 20Gb link speed */
19132 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
19134 /* 25Gb link speed */
19135 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
19137 /* 40Gb link speed */
19138 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
19140 /* 50Gb link speed */
19141 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
19143 /* 100Gb link speed */
19144 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
19146 /* 10Mb link speed (Half-duplex) */
19147 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
19149 /* 10Mb link speed (Full-duplex) */
19150 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
19152 /* 200Gb link speed */
19153 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
19156 * This is a bit mask to indicate what speeds are supported
19157 * for autonegotiation on this link.
19158 * For each speed that can be autonegotiated on this link, the
19159 * corresponding mask bit shall be set to '1'.
19161 uint16_t supported_speeds_auto_mode;
19162 /* 100Mb link speed (Half-duplex) */
19163 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
19165 /* 100Mb link speed (Full-duplex) */
19166 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
19168 /* 1Gb link speed (Half-duplex) */
19169 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
19171 /* 1Gb link speed (Full-duplex) */
19172 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
19174 /* 2Gb link speed */
19175 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
19177 /* 25Gb link speed */
19178 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
19180 /* 10Gb link speed */
19181 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
19183 /* 20Gb link speed */
19184 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
19186 /* 25Gb link speed */
19187 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
19189 /* 40Gb link speed */
19190 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
19192 /* 50Gb link speed */
19193 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
19195 /* 100Gb link speed */
19196 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
19198 /* 10Mb link speed (Half-duplex) */
19199 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
19201 /* 10Mb link speed (Full-duplex) */
19202 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
19204 /* 200Gb link speed */
19205 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
19208 * This is a bit mask to indicate what speeds are supported
19209 * for EEE on this link.
19210 * For each speed that can be autonegotiated when EEE is enabled
19211 * on this link, the corresponding mask bit shall be set to '1'.
19212 * This field is only valid when the eee_suppotred is set to '1'.
19214 uint16_t supported_speeds_eee_mode;
19216 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
19218 /* 100Mb link speed (Full-duplex) */
19219 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
19222 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
19224 /* 1Gb link speed (Full-duplex) */
19225 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
19228 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
19231 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
19233 /* 10Gb link speed */
19234 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
19236 uint32_t tx_lpi_timer_low;
19238 * The lowest value of TX LPI timer that can be set on this link
19239 * when EEE is enabled. This value is in microseconds.
19240 * This field is valid only when_eee_supported is set to '1'.
19242 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
19244 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
19246 * Reserved field. The HWRM shall set this field to 0.
19247 * An HWRM client shall ignore this field.
19249 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
19250 UINT32_C(0xff000000)
19251 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
19252 uint32_t valid_tx_lpi_timer_high;
19254 * The highest value of TX LPI timer that can be set on this link
19255 * when EEE is enabled. This value is in microseconds.
19256 * This field is valid only when_eee_supported is set to '1'.
19258 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
19260 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
19262 * This field is used in Output records to indicate that the output
19263 * is completely written to RAM. This field should be read as '1'
19264 * to indicate that the output has been completely written.
19265 * When writing a command completion or response to an internal processor,
19266 * the order of writes has to be such that this field is written last.
19268 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
19269 UINT32_C(0xff000000)
19270 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
19273 /****************************
19274 * hwrm_port_phy_mdio_write *
19275 ****************************/
19278 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */
19279 struct hwrm_port_phy_mdio_write_input {
19280 /* The HWRM command request type. */
19283 * The completion ring to send the completion event on. This should
19284 * be the NQ ID returned from the `nq_alloc` HWRM command.
19286 uint16_t cmpl_ring;
19288 * The sequence ID is used by the driver for tracking multiple
19289 * commands. This ID is treated as opaque data by the firmware and
19290 * the value is returned in the `hwrm_resp_hdr` upon completion.
19294 * The target ID of the command:
19295 * * 0x0-0xFFF8 - The function ID
19296 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19297 * * 0xFFFD - Reserved for user-space HWRM interface
19300 uint16_t target_id;
19302 * A physical address pointer pointing to a host buffer that the
19303 * command's response data will be written. This can be either a host
19304 * physical address (HPA) or a guest physical address (GPA) and must
19305 * point to a physically contiguous block of memory.
19307 uint64_t resp_addr;
19308 /* Reserved for future use. */
19309 uint32_t unused_0[2];
19310 /* Port ID of port. */
19312 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19314 /* 8-bit device address. */
19316 /* 16-bit register address. */
19318 /* 16-bit register data. */
19321 * When this bit is set to 1 a Clause 45 mdio access is done.
19322 * when this bit is set to 0 a Clause 22 mdio access is done.
19326 uint8_t unused_1[7];
19329 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */
19330 struct hwrm_port_phy_mdio_write_output {
19331 /* The specific error status for the command. */
19332 uint16_t error_code;
19333 /* The HWRM command request type. */
19335 /* The sequence ID from the original command. */
19337 /* The length of the response data in number of bytes. */
19339 uint8_t unused_0[7];
19341 * This field is used in Output records to indicate that the output
19342 * is completely written to RAM. This field should be read as '1'
19343 * to indicate that the output has been completely written.
19344 * When writing a command completion or response to an internal processor,
19345 * the order of writes has to be such that this field is written last.
19350 /***************************
19351 * hwrm_port_phy_mdio_read *
19352 ***************************/
19355 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */
19356 struct hwrm_port_phy_mdio_read_input {
19357 /* The HWRM command request type. */
19360 * The completion ring to send the completion event on. This should
19361 * be the NQ ID returned from the `nq_alloc` HWRM command.
19363 uint16_t cmpl_ring;
19365 * The sequence ID is used by the driver for tracking multiple
19366 * commands. This ID is treated as opaque data by the firmware and
19367 * the value is returned in the `hwrm_resp_hdr` upon completion.
19371 * The target ID of the command:
19372 * * 0x0-0xFFF8 - The function ID
19373 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19374 * * 0xFFFD - Reserved for user-space HWRM interface
19377 uint16_t target_id;
19379 * A physical address pointer pointing to a host buffer that the
19380 * command's response data will be written. This can be either a host
19381 * physical address (HPA) or a guest physical address (GPA) and must
19382 * point to a physically contiguous block of memory.
19384 uint64_t resp_addr;
19385 /* Reserved for future use. */
19386 uint32_t unused_0[2];
19387 /* Port ID of port. */
19389 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
19391 /* 8-bit device address. */
19393 /* 16-bit register address. */
19396 * When this bit is set to 1 a Clause 45 mdio access is done.
19397 * when this bit is set to 0 a Clause 22 mdio access is done.
19404 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */
19405 struct hwrm_port_phy_mdio_read_output {
19406 /* The specific error status for the command. */
19407 uint16_t error_code;
19408 /* The HWRM command request type. */
19410 /* The sequence ID from the original command. */
19412 /* The length of the response data in number of bytes. */
19414 /* 16-bit register data. */
19416 uint8_t unused_0[5];
19418 * This field is used in Output records to indicate that the output
19419 * is completely written to RAM. This field should be read as '1'
19420 * to indicate that the output has been completely written.
19421 * When writing a command completion or response to an internal processor,
19422 * the order of writes has to be such that this field is written last.
19427 /*********************
19428 * hwrm_port_led_cfg *
19429 *********************/
19432 /* hwrm_port_led_cfg_input (size:512b/64B) */
19433 struct hwrm_port_led_cfg_input {
19434 /* The HWRM command request type. */
19437 * The completion ring to send the completion event on. This should
19438 * be the NQ ID returned from the `nq_alloc` HWRM command.
19440 uint16_t cmpl_ring;
19442 * The sequence ID is used by the driver for tracking multiple
19443 * commands. This ID is treated as opaque data by the firmware and
19444 * the value is returned in the `hwrm_resp_hdr` upon completion.
19448 * The target ID of the command:
19449 * * 0x0-0xFFF8 - The function ID
19450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19451 * * 0xFFFD - Reserved for user-space HWRM interface
19454 uint16_t target_id;
19456 * A physical address pointer pointing to a host buffer that the
19457 * command's response data will be written. This can be either a host
19458 * physical address (HPA) or a guest physical address (GPA) and must
19459 * point to a physically contiguous block of memory.
19461 uint64_t resp_addr;
19464 * This bit must be '1' for the led0_id field to be
19467 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
19470 * This bit must be '1' for the led0_state field to be
19473 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
19476 * This bit must be '1' for the led0_color field to be
19479 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
19482 * This bit must be '1' for the led0_blink_on field to be
19485 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
19488 * This bit must be '1' for the led0_blink_off field to be
19491 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
19494 * This bit must be '1' for the led0_group_id field to be
19497 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
19500 * This bit must be '1' for the led1_id field to be
19503 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
19506 * This bit must be '1' for the led1_state field to be
19509 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
19512 * This bit must be '1' for the led1_color field to be
19515 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
19518 * This bit must be '1' for the led1_blink_on field to be
19521 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
19524 * This bit must be '1' for the led1_blink_off field to be
19527 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
19530 * This bit must be '1' for the led1_group_id field to be
19533 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
19536 * This bit must be '1' for the led2_id field to be
19539 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
19542 * This bit must be '1' for the led2_state field to be
19545 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
19548 * This bit must be '1' for the led2_color field to be
19551 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
19554 * This bit must be '1' for the led2_blink_on field to be
19557 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
19560 * This bit must be '1' for the led2_blink_off field to be
19563 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
19566 * This bit must be '1' for the led2_group_id field to be
19569 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
19572 * This bit must be '1' for the led3_id field to be
19575 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
19578 * This bit must be '1' for the led3_state field to be
19581 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
19584 * This bit must be '1' for the led3_color field to be
19587 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
19590 * This bit must be '1' for the led3_blink_on field to be
19593 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
19596 * This bit must be '1' for the led3_blink_off field to be
19599 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
19602 * This bit must be '1' for the led3_group_id field to be
19605 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
19607 /* Port ID of port whose LEDs are configured. */
19610 * The number of LEDs that are being configured.
19611 * Up to 4 LEDs can be configured with this command.
19614 /* Reserved field. */
19616 /* An identifier for the LED #0. */
19618 /* The requested state of the LED #0. */
19619 uint8_t led0_state;
19620 /* Default state of the LED */
19621 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19623 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
19625 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
19627 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
19628 /* Blink Alternately */
19629 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19630 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
19631 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
19632 /* The requested color of LED #0. */
19633 uint8_t led0_color;
19635 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19637 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19639 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19640 /* Green or Amber */
19641 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19642 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
19643 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
19646 * If the LED #0 state is "blink" or "blinkalt", then
19647 * this field represents the requested time in milliseconds
19648 * to keep LED on between cycles.
19650 uint16_t led0_blink_on;
19652 * If the LED #0 state is "blink" or "blinkalt", then
19653 * this field represents the requested time in milliseconds
19654 * to keep LED off between cycles.
19656 uint16_t led0_blink_off;
19658 * An identifier for the group of LEDs that LED #0 belongs
19660 * If set to 0, then the LED #0 shall not be grouped and
19661 * shall be treated as an individual resource.
19662 * For all other non-zero values of this field, LED #0 shall
19663 * be grouped together with the LEDs with the same group ID
19666 uint8_t led0_group_id;
19667 /* Reserved field. */
19669 /* An identifier for the LED #1. */
19671 /* The requested state of the LED #1. */
19672 uint8_t led1_state;
19673 /* Default state of the LED */
19674 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19676 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
19678 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
19680 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
19681 /* Blink Alternately */
19682 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19683 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
19684 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
19685 /* The requested color of LED #1. */
19686 uint8_t led1_color;
19688 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19690 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19692 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
19693 /* Green or Amber */
19694 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
19695 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
19696 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
19699 * If the LED #1 state is "blink" or "blinkalt", then
19700 * this field represents the requested time in milliseconds
19701 * to keep LED on between cycles.
19703 uint16_t led1_blink_on;
19705 * If the LED #1 state is "blink" or "blinkalt", then
19706 * this field represents the requested time in milliseconds
19707 * to keep LED off between cycles.
19709 uint16_t led1_blink_off;
19711 * An identifier for the group of LEDs that LED #1 belongs
19713 * If set to 0, then the LED #1 shall not be grouped and
19714 * shall be treated as an individual resource.
19715 * For all other non-zero values of this field, LED #1 shall
19716 * be grouped together with the LEDs with the same group ID
19719 uint8_t led1_group_id;
19720 /* Reserved field. */
19722 /* An identifier for the LED #2. */
19724 /* The requested state of the LED #2. */
19725 uint8_t led2_state;
19726 /* Default state of the LED */
19727 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
19729 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
19731 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
19733 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
19734 /* Blink Alternately */
19735 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
19736 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
19737 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
19738 /* The requested color of LED #2. */
19739 uint8_t led2_color;
19741 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
19743 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
19745 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
19746 /* Green or Amber */
19747 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
19748 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
19749 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
19752 * If the LED #2 state is "blink" or "blinkalt", then
19753 * this field represents the requested time in milliseconds
19754 * to keep LED on between cycles.
19756 uint16_t led2_blink_on;
19758 * If the LED #2 state is "blink" or "blinkalt", then
19759 * this field represents the requested time in milliseconds
19760 * to keep LED off between cycles.
19762 uint16_t led2_blink_off;
19764 * An identifier for the group of LEDs that LED #2 belongs
19766 * If set to 0, then the LED #2 shall not be grouped and
19767 * shall be treated as an individual resource.
19768 * For all other non-zero values of this field, LED #2 shall
19769 * be grouped together with the LEDs with the same group ID
19772 uint8_t led2_group_id;
19773 /* Reserved field. */
19775 /* An identifier for the LED #3. */
19777 /* The requested state of the LED #3. */
19778 uint8_t led3_state;
19779 /* Default state of the LED */
19780 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
19782 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
19784 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
19786 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
19787 /* Blink Alternately */
19788 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
19789 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
19790 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
19791 /* The requested color of LED #3. */
19792 uint8_t led3_color;
19794 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
19796 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
19798 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
19799 /* Green or Amber */
19800 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
19801 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
19802 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
19805 * If the LED #3 state is "blink" or "blinkalt", then
19806 * this field represents the requested time in milliseconds
19807 * to keep LED on between cycles.
19809 uint16_t led3_blink_on;
19811 * If the LED #3 state is "blink" or "blinkalt", then
19812 * this field represents the requested time in milliseconds
19813 * to keep LED off between cycles.
19815 uint16_t led3_blink_off;
19817 * An identifier for the group of LEDs that LED #3 belongs
19819 * If set to 0, then the LED #3 shall not be grouped and
19820 * shall be treated as an individual resource.
19821 * For all other non-zero values of this field, LED #3 shall
19822 * be grouped together with the LEDs with the same group ID
19825 uint8_t led3_group_id;
19826 /* Reserved field. */
19830 /* hwrm_port_led_cfg_output (size:128b/16B) */
19831 struct hwrm_port_led_cfg_output {
19832 /* The specific error status for the command. */
19833 uint16_t error_code;
19834 /* The HWRM command request type. */
19836 /* The sequence ID from the original command. */
19838 /* The length of the response data in number of bytes. */
19840 uint8_t unused_0[7];
19842 * This field is used in Output records to indicate that the output
19843 * is completely written to RAM. This field should be read as '1'
19844 * to indicate that the output has been completely written.
19845 * When writing a command completion or response to an internal processor,
19846 * the order of writes has to be such that this field is written last.
19851 /**********************
19852 * hwrm_port_led_qcfg *
19853 **********************/
19856 /* hwrm_port_led_qcfg_input (size:192b/24B) */
19857 struct hwrm_port_led_qcfg_input {
19858 /* The HWRM command request type. */
19861 * The completion ring to send the completion event on. This should
19862 * be the NQ ID returned from the `nq_alloc` HWRM command.
19864 uint16_t cmpl_ring;
19866 * The sequence ID is used by the driver for tracking multiple
19867 * commands. This ID is treated as opaque data by the firmware and
19868 * the value is returned in the `hwrm_resp_hdr` upon completion.
19872 * The target ID of the command:
19873 * * 0x0-0xFFF8 - The function ID
19874 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19875 * * 0xFFFD - Reserved for user-space HWRM interface
19878 uint16_t target_id;
19880 * A physical address pointer pointing to a host buffer that the
19881 * command's response data will be written. This can be either a host
19882 * physical address (HPA) or a guest physical address (GPA) and must
19883 * point to a physically contiguous block of memory.
19885 uint64_t resp_addr;
19886 /* Port ID of port whose LED configuration is being queried. */
19888 uint8_t unused_0[6];
19891 /* hwrm_port_led_qcfg_output (size:448b/56B) */
19892 struct hwrm_port_led_qcfg_output {
19893 /* The specific error status for the command. */
19894 uint16_t error_code;
19895 /* The HWRM command request type. */
19897 /* The sequence ID from the original command. */
19899 /* The length of the response data in number of bytes. */
19902 * The number of LEDs that are configured on this port.
19903 * Up to 4 LEDs can be returned in the response.
19906 /* An identifier for the LED #0. */
19908 /* The type of LED #0. */
19911 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
19913 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
19915 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
19916 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
19917 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
19918 /* The current state of the LED #0. */
19919 uint8_t led0_state;
19920 /* Default state of the LED */
19921 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
19923 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
19925 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
19927 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
19928 /* Blink Alternately */
19929 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
19930 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
19931 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
19932 /* The color of LED #0. */
19933 uint8_t led0_color;
19935 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
19937 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
19939 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
19940 /* Green or Amber */
19941 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
19942 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
19943 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
19946 * If the LED #0 state is "blink" or "blinkalt", then
19947 * this field represents the requested time in milliseconds
19948 * to keep LED on between cycles.
19950 uint16_t led0_blink_on;
19952 * If the LED #0 state is "blink" or "blinkalt", then
19953 * this field represents the requested time in milliseconds
19954 * to keep LED off between cycles.
19956 uint16_t led0_blink_off;
19958 * An identifier for the group of LEDs that LED #0 belongs
19960 * If set to 0, then the LED #0 is not grouped.
19961 * For all other non-zero values of this field, LED #0 is
19962 * grouped together with the LEDs with the same group ID
19965 uint8_t led0_group_id;
19966 /* An identifier for the LED #1. */
19968 /* The type of LED #1. */
19971 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
19973 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
19975 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
19976 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
19977 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
19978 /* The current state of the LED #1. */
19979 uint8_t led1_state;
19980 /* Default state of the LED */
19981 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
19983 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
19985 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
19987 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
19988 /* Blink Alternately */
19989 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
19990 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
19991 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
19992 /* The color of LED #1. */
19993 uint8_t led1_color;
19995 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
19997 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
19999 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
20000 /* Green or Amber */
20001 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
20002 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
20003 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
20006 * If the LED #1 state is "blink" or "blinkalt", then
20007 * this field represents the requested time in milliseconds
20008 * to keep LED on between cycles.
20010 uint16_t led1_blink_on;
20012 * If the LED #1 state is "blink" or "blinkalt", then
20013 * this field represents the requested time in milliseconds
20014 * to keep LED off between cycles.
20016 uint16_t led1_blink_off;
20018 * An identifier for the group of LEDs that LED #1 belongs
20020 * If set to 0, then the LED #1 is not grouped.
20021 * For all other non-zero values of this field, LED #1 is
20022 * grouped together with the LEDs with the same group ID
20025 uint8_t led1_group_id;
20026 /* An identifier for the LED #2. */
20028 /* The type of LED #2. */
20031 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20033 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20035 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20036 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
20037 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
20038 /* The current state of the LED #2. */
20039 uint8_t led2_state;
20040 /* Default state of the LED */
20041 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
20043 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
20045 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
20047 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
20048 /* Blink Alternately */
20049 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
20050 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
20051 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
20052 /* The color of LED #2. */
20053 uint8_t led2_color;
20055 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
20057 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
20059 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
20060 /* Green or Amber */
20061 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
20062 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
20063 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
20066 * If the LED #2 state is "blink" or "blinkalt", then
20067 * this field represents the requested time in milliseconds
20068 * to keep LED on between cycles.
20070 uint16_t led2_blink_on;
20072 * If the LED #2 state is "blink" or "blinkalt", then
20073 * this field represents the requested time in milliseconds
20074 * to keep LED off between cycles.
20076 uint16_t led2_blink_off;
20078 * An identifier for the group of LEDs that LED #2 belongs
20080 * If set to 0, then the LED #2 is not grouped.
20081 * For all other non-zero values of this field, LED #2 is
20082 * grouped together with the LEDs with the same group ID
20085 uint8_t led2_group_id;
20086 /* An identifier for the LED #3. */
20088 /* The type of LED #3. */
20091 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20093 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20095 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20096 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
20097 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
20098 /* The current state of the LED #3. */
20099 uint8_t led3_state;
20100 /* Default state of the LED */
20101 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
20103 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
20105 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
20107 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
20108 /* Blink Alternately */
20109 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
20110 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
20111 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
20112 /* The color of LED #3. */
20113 uint8_t led3_color;
20115 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
20117 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
20119 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
20120 /* Green or Amber */
20121 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
20122 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
20123 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
20126 * If the LED #3 state is "blink" or "blinkalt", then
20127 * this field represents the requested time in milliseconds
20128 * to keep LED on between cycles.
20130 uint16_t led3_blink_on;
20132 * If the LED #3 state is "blink" or "blinkalt", then
20133 * this field represents the requested time in milliseconds
20134 * to keep LED off between cycles.
20136 uint16_t led3_blink_off;
20138 * An identifier for the group of LEDs that LED #3 belongs
20140 * If set to 0, then the LED #3 is not grouped.
20141 * For all other non-zero values of this field, LED #3 is
20142 * grouped together with the LEDs with the same group ID
20145 uint8_t led3_group_id;
20146 uint8_t unused_4[6];
20148 * This field is used in Output records to indicate that the output
20149 * is completely written to RAM. This field should be read as '1'
20150 * to indicate that the output has been completely written.
20151 * When writing a command completion or response to an internal processor,
20152 * the order of writes has to be such that this field is written last.
20157 /***********************
20158 * hwrm_port_led_qcaps *
20159 ***********************/
20162 /* hwrm_port_led_qcaps_input (size:192b/24B) */
20163 struct hwrm_port_led_qcaps_input {
20164 /* The HWRM command request type. */
20167 * The completion ring to send the completion event on. This should
20168 * be the NQ ID returned from the `nq_alloc` HWRM command.
20170 uint16_t cmpl_ring;
20172 * The sequence ID is used by the driver for tracking multiple
20173 * commands. This ID is treated as opaque data by the firmware and
20174 * the value is returned in the `hwrm_resp_hdr` upon completion.
20178 * The target ID of the command:
20179 * * 0x0-0xFFF8 - The function ID
20180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20181 * * 0xFFFD - Reserved for user-space HWRM interface
20184 uint16_t target_id;
20186 * A physical address pointer pointing to a host buffer that the
20187 * command's response data will be written. This can be either a host
20188 * physical address (HPA) or a guest physical address (GPA) and must
20189 * point to a physically contiguous block of memory.
20191 uint64_t resp_addr;
20192 /* Port ID of port whose LED configuration is being queried. */
20194 uint8_t unused_0[6];
20197 /* hwrm_port_led_qcaps_output (size:384b/48B) */
20198 struct hwrm_port_led_qcaps_output {
20199 /* The specific error status for the command. */
20200 uint16_t error_code;
20201 /* The HWRM command request type. */
20203 /* The sequence ID from the original command. */
20205 /* The length of the response data in number of bytes. */
20208 * The number of LEDs that are configured on this port.
20209 * Up to 4 LEDs can be returned in the response.
20212 /* Reserved for future use. */
20214 /* An identifier for the LED #0. */
20216 /* The type of LED #0. */
20219 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
20221 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
20223 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
20224 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
20225 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
20227 * An identifier for the group of LEDs that LED #0 belongs
20229 * If set to 0, then the LED #0 cannot be grouped.
20230 * For all other non-zero values of this field, LED #0 is
20231 * grouped together with the LEDs with the same group ID
20234 uint8_t led0_group_id;
20236 /* The states supported by LED #0. */
20237 uint16_t led0_state_caps;
20239 * If set to 1, this LED is enabled.
20240 * If set to 0, this LED is disabled.
20242 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
20245 * If set to 1, off state is supported on this LED.
20246 * If set to 0, off state is not supported on this LED.
20248 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
20251 * If set to 1, on state is supported on this LED.
20252 * If set to 0, on state is not supported on this LED.
20254 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
20257 * If set to 1, blink state is supported on this LED.
20258 * If set to 0, blink state is not supported on this LED.
20260 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
20263 * If set to 1, blink_alt state is supported on this LED.
20264 * If set to 0, blink_alt state is not supported on this LED.
20266 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
20268 /* The colors supported by LED #0. */
20269 uint16_t led0_color_caps;
20271 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
20274 * If set to 1, Amber color is supported on this LED.
20275 * If set to 0, Amber color is not supported on this LED.
20277 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
20280 * If set to 1, Green color is supported on this LED.
20281 * If set to 0, Green color is not supported on this LED.
20283 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
20285 /* An identifier for the LED #1. */
20287 /* The type of LED #1. */
20290 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
20292 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
20294 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
20295 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
20296 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
20298 * An identifier for the group of LEDs that LED #1 belongs
20300 * If set to 0, then the LED #0 cannot be grouped.
20301 * For all other non-zero values of this field, LED #0 is
20302 * grouped together with the LEDs with the same group ID
20305 uint8_t led1_group_id;
20307 /* The states supported by LED #1. */
20308 uint16_t led1_state_caps;
20310 * If set to 1, this LED is enabled.
20311 * If set to 0, this LED is disabled.
20313 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
20316 * If set to 1, off state is supported on this LED.
20317 * If set to 0, off state is not supported on this LED.
20319 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
20322 * If set to 1, on state is supported on this LED.
20323 * If set to 0, on state is not supported on this LED.
20325 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
20328 * If set to 1, blink state is supported on this LED.
20329 * If set to 0, blink state is not supported on this LED.
20331 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
20334 * If set to 1, blink_alt state is supported on this LED.
20335 * If set to 0, blink_alt state is not supported on this LED.
20337 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
20339 /* The colors supported by LED #1. */
20340 uint16_t led1_color_caps;
20342 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
20345 * If set to 1, Amber color is supported on this LED.
20346 * If set to 0, Amber color is not supported on this LED.
20348 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
20351 * If set to 1, Green color is supported on this LED.
20352 * If set to 0, Green color is not supported on this LED.
20354 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
20356 /* An identifier for the LED #2. */
20358 /* The type of LED #2. */
20361 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
20363 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
20365 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
20366 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
20367 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
20369 * An identifier for the group of LEDs that LED #0 belongs
20371 * If set to 0, then the LED #0 cannot be grouped.
20372 * For all other non-zero values of this field, LED #0 is
20373 * grouped together with the LEDs with the same group ID
20376 uint8_t led2_group_id;
20378 /* The states supported by LED #2. */
20379 uint16_t led2_state_caps;
20381 * If set to 1, this LED is enabled.
20382 * If set to 0, this LED is disabled.
20384 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
20387 * If set to 1, off state is supported on this LED.
20388 * If set to 0, off state is not supported on this LED.
20390 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
20393 * If set to 1, on state is supported on this LED.
20394 * If set to 0, on state is not supported on this LED.
20396 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
20399 * If set to 1, blink state is supported on this LED.
20400 * If set to 0, blink state is not supported on this LED.
20402 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
20405 * If set to 1, blink_alt state is supported on this LED.
20406 * If set to 0, blink_alt state is not supported on this LED.
20408 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
20410 /* The colors supported by LED #2. */
20411 uint16_t led2_color_caps;
20413 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
20416 * If set to 1, Amber color is supported on this LED.
20417 * If set to 0, Amber color is not supported on this LED.
20419 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
20422 * If set to 1, Green color is supported on this LED.
20423 * If set to 0, Green color is not supported on this LED.
20425 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
20427 /* An identifier for the LED #3. */
20429 /* The type of LED #3. */
20432 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
20434 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
20436 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
20437 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
20438 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
20440 * An identifier for the group of LEDs that LED #3 belongs
20442 * If set to 0, then the LED #0 cannot be grouped.
20443 * For all other non-zero values of this field, LED #0 is
20444 * grouped together with the LEDs with the same group ID
20447 uint8_t led3_group_id;
20449 /* The states supported by LED #3. */
20450 uint16_t led3_state_caps;
20452 * If set to 1, this LED is enabled.
20453 * If set to 0, this LED is disabled.
20455 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
20458 * If set to 1, off state is supported on this LED.
20459 * If set to 0, off state is not supported on this LED.
20461 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
20464 * If set to 1, on state is supported on this LED.
20465 * If set to 0, on state is not supported on this LED.
20467 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
20470 * If set to 1, blink state is supported on this LED.
20471 * If set to 0, blink state is not supported on this LED.
20473 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
20476 * If set to 1, blink_alt state is supported on this LED.
20477 * If set to 0, blink_alt state is not supported on this LED.
20479 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
20481 /* The colors supported by LED #3. */
20482 uint16_t led3_color_caps;
20484 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
20487 * If set to 1, Amber color is supported on this LED.
20488 * If set to 0, Amber color is not supported on this LED.
20490 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
20493 * If set to 1, Green color is supported on this LED.
20494 * If set to 0, Green color is not supported on this LED.
20496 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
20498 uint8_t unused_4[3];
20500 * This field is used in Output records to indicate that the output
20501 * is completely written to RAM. This field should be read as '1'
20502 * to indicate that the output has been completely written.
20503 * When writing a command completion or response to an internal processor,
20504 * the order of writes has to be such that this field is written last.
20509 /***********************
20510 * hwrm_port_prbs_test *
20511 ***********************/
20514 /* hwrm_port_prbs_test_input (size:384b/48B) */
20515 struct hwrm_port_prbs_test_input {
20516 /* The HWRM command request type. */
20519 * The completion ring to send the completion event on. This should
20520 * be the NQ ID returned from the `nq_alloc` HWRM command.
20522 uint16_t cmpl_ring;
20524 * The sequence ID is used by the driver for tracking multiple
20525 * commands. This ID is treated as opaque data by the firmware and
20526 * the value is returned in the `hwrm_resp_hdr` upon completion.
20530 * The target ID of the command:
20531 * * 0x0-0xFFF8 - The function ID
20532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20533 * * 0xFFFD - Reserved for user-space HWRM interface
20536 uint16_t target_id;
20538 * A physical address pointer pointing to a host buffer that the
20539 * command's response data will be written. This can be either a host
20540 * physical address (HPA) or a guest physical address (GPA) and must
20541 * point to a physically contiguous block of memory.
20543 uint64_t resp_addr;
20544 /* Host address data is to DMA'd to. */
20545 uint64_t resp_data_addr;
20547 * Size of the buffer pointed to by resp_data_addr. The firmware may
20548 * use this entire buffer or less than the entire buffer, but never more.
20553 /* Port ID of port where PRBS test to be run. */
20555 /* Polynomial selection for PRBS test. */
20558 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
20560 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
20562 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
20564 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
20566 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
20568 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
20570 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
20572 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
20573 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
20574 HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
20576 * Configuration bits for PRBS test.
20577 * Use enable bit to start/stop test.
20578 * Use tx/rx lane map bits to run test on specific lanes,
20579 * if set to 0 test will be run on all lanes.
20581 uint16_t prbs_config;
20583 * Set 0 to stop test currently in progress
20584 * Set 1 to start test with configuration provided.
20586 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
20589 * If set to 1, tx_lane_map bitmap should have lane bits set.
20590 * If set to 0, test will be run on all lanes for this port.
20592 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
20595 * If set to 1, rx_lane_map bitmap should have lane bits set.
20596 * If set to 0, test will be run on all lanes for this port.
20598 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
20600 /* Duration in seconds to run the PRBS test. */
20603 * If tx_lane_map_valid is set to 1, this field is a bitmap
20604 * of tx lanes to run PRBS test. bit0 = lane0,
20605 * bit1 = lane1 ..bit31 = lane31
20607 uint32_t tx_lane_map;
20609 * If rx_lane_map_valid is set to 1, this field is a bitmap
20610 * of rx lanes to run PRBS test. bit0 = lane0,
20611 * bit1 = lane1 ..bit31 = lane31
20613 uint32_t rx_lane_map;
20616 /* hwrm_port_prbs_test_output (size:128b/16B) */
20617 struct hwrm_port_prbs_test_output {
20618 /* The specific error status for the command. */
20619 uint16_t error_code;
20620 /* The HWRM command request type. */
20622 /* The sequence ID from the original command. */
20624 /* The length of the response data in number of bytes. */
20626 /* Total length of stored data. */
20627 uint16_t total_data_len;
20629 uint8_t unused_1[3];
20631 * This field is used in Output records to indicate that the output
20632 * is completely written to RAM. This field should be read as '1'
20633 * to indicate that the output has been completely written.
20634 * When writing a command completion or response to an internal processor,
20635 * the order of writes has to be such that this field is written last.
20640 /**********************
20641 * hwrm_port_dsc_dump *
20642 **********************/
20645 /* hwrm_port_dsc_dump_input (size:320b/40B) */
20646 struct hwrm_port_dsc_dump_input {
20647 /* The HWRM command request type. */
20650 * The completion ring to send the completion event on. This should
20651 * be the NQ ID returned from the `nq_alloc` HWRM command.
20653 uint16_t cmpl_ring;
20655 * The sequence ID is used by the driver for tracking multiple
20656 * commands. This ID is treated as opaque data by the firmware and
20657 * the value is returned in the `hwrm_resp_hdr` upon completion.
20661 * The target ID of the command:
20662 * * 0x0-0xFFF8 - The function ID
20663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20664 * * 0xFFFD - Reserved for user-space HWRM interface
20667 uint16_t target_id;
20669 * A physical address pointer pointing to a host buffer that the
20670 * command's response data will be written. This can be either a host
20671 * physical address (HPA) or a guest physical address (GPA) and must
20672 * point to a physically contiguous block of memory.
20674 uint64_t resp_addr;
20675 /* Host address where response diagnostic data is returned. */
20676 uint64_t resp_data_addr;
20678 * Size of the buffer pointed to by resp_data_addr. The firmware
20679 * may use this entire buffer or less than the entire buffer, but
20685 /* Port ID of port where dsc dump to be collected. */
20687 /* Diag level specified by the user */
20688 uint16_t diag_level;
20689 /* SRDS_DIAG_LANE */
20690 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE \
20692 /* SRDS_DIAG_CORE */
20693 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE \
20695 /* SRDS_DIAG_EVENT */
20696 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT \
20698 /* SRDS_DIAG_EYE */
20699 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE \
20701 /* SRDS_DIAG_REG_CORE */
20702 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE \
20704 /* SRDS_DIAG_REG_LANE */
20705 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE \
20707 /* SRDS_DIAG_UC_CORE */
20708 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE \
20710 /* SRDS_DIAG_UC_LANE */
20711 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE \
20713 /* SRDS_DIAG_LANE_DEBUG */
20714 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG \
20716 /* SRDS_DIAG_BER_VERT */
20717 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT \
20719 /* SRDS_DIAG_BER_HORZ */
20720 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ \
20722 /* SRDS_DIAG_EVENT_SAFE */
20723 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE \
20725 /* SRDS_DIAG_TIMESTAMP */
20726 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP \
20728 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_LAST \
20729 HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP
20731 * This field is a lane number
20732 * on which to collect the dsc dump
20734 uint16_t lane_number;
20736 * Configuration bits.
20737 * Use enable bit to start dsc dump or retrieve dump
20739 uint16_t dsc_dump_config;
20741 * Set 0 to retrieve the dsc dump
20742 * Set 1 to start the dsc dump
20744 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE \
20748 /* hwrm_port_dsc_dump_output (size:128b/16B) */
20749 struct hwrm_port_dsc_dump_output {
20750 /* The specific error status for the command. */
20751 uint16_t error_code;
20752 /* The HWRM command request type. */
20754 /* The sequence ID from the original command. */
20756 /* The length of the response data in number of bytes. */
20758 /* Total length of stored data. */
20759 uint16_t total_data_len;
20761 uint8_t unused_1[3];
20763 * This field is used in Output records to indicate that the output
20764 * is completely written to RAM. This field should be read as '1'
20765 * to indicate that the output has been completely written.
20766 * When writing a command completion or response to an internal processor,
20767 * the order of writes has to be such that this field is written last.
20772 /******************************
20773 * hwrm_port_sfp_sideband_cfg *
20774 ******************************/
20777 /* hwrm_port_sfp_sideband_cfg_input (size:256b/32B) */
20778 struct hwrm_port_sfp_sideband_cfg_input {
20779 /* The HWRM command request type. */
20782 * The completion ring to send the completion event on. This should
20783 * be the NQ ID returned from the `nq_alloc` HWRM command.
20785 uint16_t cmpl_ring;
20787 * The sequence ID is used by the driver for tracking multiple
20788 * commands. This ID is treated as opaque data by the firmware and
20789 * the value is returned in the `hwrm_resp_hdr` upon completion.
20793 * The target ID of the command:
20794 * * 0x0-0xFFF8 - The function ID
20795 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20796 * * 0xFFFD - Reserved for user-space HWRM interface
20799 uint16_t target_id;
20801 * A physical address pointer pointing to a host buffer that the
20802 * command's response data will be written. This can be either a host
20803 * physical address (HPA) or a guest physical address (GPA) and must
20804 * point to a physically contiguous block of memory.
20806 uint64_t resp_addr;
20807 /* Port ID of port that is to be queried. */
20809 uint8_t unused_0[6];
20811 * This bitfield is used to specify which bits from the 'flags'
20812 * fields are being configured by the caller.
20815 /* This bit must be '1' for rs0 to be configured. */
20816 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 \
20818 /* This bit must be '1' for rs1 to be configured. */
20819 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 \
20821 /* This bit must be '1' for tx_disable to be configured. */
20822 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS \
20825 * This bit must be '1' for mod_sel to be configured.
20826 * Valid only on QSFP modules
20828 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL \
20830 /* This bit must be '1' for reset_l to be configured. */
20831 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L \
20833 /* This bit must be '1' for lp_mode to be configured. */
20834 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE \
20836 /* This bit must be '1' for pwr_disable to be configured. */
20837 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS \
20840 * Only bits that have corresponding bits in the 'enables'
20841 * bitfield are processed by the firmware, all other bits
20842 * of 'flags' are ignored.
20846 * This bit along with rs1 configures the current speed of the dual
20847 * rate module. If these pins are GNDed then the speed can be changed
20848 * by driectly writing to EEPROM.
20850 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 \
20853 * This bit along with rs0 configures the current speed of the dual
20854 * rate module. If these pins are GNDed then the speed can be changed
20855 * by driectly writing to EEPROM.
20857 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 \
20860 * When this bit is set to '1', tx_disable is set.
20861 * On a 1G BASE-T module, if this bit is set,
20862 * module PHY registers will not be accessible.
20864 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS \
20867 * When this bit is set to '1', this module is selected.
20868 * Valid only on QSFP modules
20870 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL \
20873 * If reset_l is set to 0, Module will be taken out of reset
20874 * and other signals will be set to their requested state once
20875 * the module is out of reset.
20876 * Valid only on QSFP modules
20878 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L \
20881 * When this bit is set to '1', the module will be configured
20882 * in low power mode.
20883 * Valid only on QSFP modules
20885 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE \
20887 /* When this bit is set to '1', the module will be powered down. */
20888 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS \
20892 /* hwrm_port_sfp_sideband_cfg_output (size:128b/16B) */
20893 struct hwrm_port_sfp_sideband_cfg_output {
20894 /* The specific error status for the command. */
20895 uint16_t error_code;
20896 /* The HWRM command request type. */
20898 /* The sequence ID from the original command. */
20900 /* The length of the response data in number of bytes. */
20904 * This field is used in Output records to indicate that the output
20905 * is completely written to RAM. This field should be read as '1'
20906 * to indicate that the output has been completely written. When
20907 * writing a command completion or response to an internal processor,
20908 * the order of writes has to be such that this field is written last.
20913 /*******************************
20914 * hwrm_port_sfp_sideband_qcfg *
20915 *******************************/
20918 /* hwrm_port_sfp_sideband_qcfg_input (size:192b/24B) */
20919 struct hwrm_port_sfp_sideband_qcfg_input {
20920 /* The HWRM command request type. */
20923 * The completion ring to send the completion event on. This should
20924 * be the NQ ID returned from the `nq_alloc` HWRM command.
20926 uint16_t cmpl_ring;
20928 * The sequence ID is used by the driver for tracking multiple
20929 * commands. This ID is treated as opaque data by the firmware and
20930 * the value is returned in the `hwrm_resp_hdr` upon completion.
20934 * The target ID of the command:
20935 * * 0x0-0xFFF8 - The function ID
20936 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20937 * * 0xFFFD - Reserved for user-space HWRM interface
20940 uint16_t target_id;
20942 * A physical address pointer pointing to a host buffer that the
20943 * command's response data will be written. This can be either a host
20944 * physical address (HPA) or a guest physical address (GPA) and must
20945 * point to a physically contiguous block of memory.
20947 uint64_t resp_addr;
20948 /* Port ID of port that is to be queried. */
20950 uint8_t unused_0[6];
20953 /* hwrm_port_sfp_sideband_qcfg_output (size:192b/24B) */
20954 struct hwrm_port_sfp_sideband_qcfg_output {
20955 /* The specific error status for the command. */
20956 uint16_t error_code;
20957 /* The HWRM command request type. */
20959 /* The sequence ID from the original command. */
20961 /* The length of the response data in number of bytes. */
20964 * Bitmask indicating which sideband signals are valid.
20965 * This is based on the board and nvm cfg that is present on the board.
20967 uint32_t supported_mask;
20968 uint32_t sideband_signals;
20969 /* When this bit is set to '1', the Module is absent. */
20970 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS \
20973 * When this bit is set to '1', there is no valid signal on RX.
20974 * This signal is a filtered version of Signal Detect.
20976 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS \
20979 * This bit along with rs1 indiactes the current speed of the dual
20980 * rate module.If these pins are grounded then the speed can be
20981 * changed by driectky writing to EEPROM.
20983 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 \
20986 * This bit along with rs0 indiactes the current speed of the dual
20987 * rate module.If these pins are grounded then the speed can be
20988 * changed by driectky writing to EEPROM.
20990 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 \
20993 * When this bit is set to '1', tx_disable is set.
20994 * On a 1G BASE-T module, if this bit is set, module PHY
20995 * registers will not be accessible.
20997 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS \
20999 /* When this bit is set to '1', tx_fault is set. */
21000 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT \
21003 * When this bit is set to '1', module is selected.
21004 * Valid only on QSFP modules
21006 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL \
21009 * When this bit is set to '0', the module is held in reset.
21010 * if reset_l is set to 1,first module is taken out of reset
21011 * and other signals will be set to their requested state.
21012 * Valid only on QSFP modules.
21014 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L \
21017 * When this bit is set to '1', the module is in low power mode.
21018 * Valid only on QSFP modules
21020 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE \
21022 /* When this bit is set to '1', module is in power down state. */
21023 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS \
21027 * This field is used in Output records to indicate that the output
21028 * is completely written to RAM. This field should be read as '1'
21029 * to indicate that the output has been completely written. When
21030 * writing a command completion or response to an internal processor,
21031 * the order of writes has to be such that this field is written last.
21036 /**********************************
21037 * hwrm_port_phy_mdio_bus_acquire *
21038 **********************************/
21041 /* hwrm_port_phy_mdio_bus_acquire_input (size:192b/24B) */
21042 struct hwrm_port_phy_mdio_bus_acquire_input {
21043 /* The HWRM command request type. */
21046 * The completion ring to send the completion event on. This should
21047 * be the NQ ID returned from the `nq_alloc` HWRM command.
21049 uint16_t cmpl_ring;
21051 * The sequence ID is used by the driver for tracking multiple
21052 * commands. This ID is treated as opaque data by the firmware and
21053 * the value is returned in the `hwrm_resp_hdr` upon completion.
21057 * The target ID of the command:
21058 * * 0x0-0xFFF8 - The function ID
21059 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21060 * * 0xFFFD - Reserved for user-space HWRM interface
21063 uint16_t target_id;
21065 * A physical address pointer pointing to a host buffer that the
21066 * command's response data will be written. This can be either a host
21067 * physical address (HPA) or a guest physical address (GPA) and must
21068 * point to a physically contiguous block of memory.
21070 uint64_t resp_addr;
21071 /* Port ID of the port. */
21074 * client_id of the client requesting BUS access.
21075 * Any value from 0x10 to 0xFFFF can be used.
21076 * Client should make sure that the returned client_id
21077 * in response matches the client_id in request.
21078 * 0-0xF are reserved for internal use.
21080 uint16_t client_id;
21082 * Timeout in milli seconds, MDIO BUS will be released automatically
21083 * after this time, if another mdio acquire command is not received
21084 * within the timeout window from the same client.
21085 * A 0xFFFF will hold the bus until this bus is released.
21087 uint16_t mdio_bus_timeout;
21088 uint8_t unused_0[2];
21091 /* hwrm_port_phy_mdio_bus_acquire_output (size:128b/16B) */
21092 struct hwrm_port_phy_mdio_bus_acquire_output {
21093 /* The specific error status for the command. */
21094 uint16_t error_code;
21095 /* The HWRM command request type. */
21097 /* The sequence ID from the original command. */
21099 /* The length of the response data in number of bytes. */
21103 * client_id of the module holding the BUS.
21104 * 0-0xF are reserved for internal use.
21106 uint16_t client_id;
21107 uint8_t unused_1[3];
21109 * This field is used in Output records to indicate that the output
21110 * is completely written to RAM. This field should be read as '1'
21111 * to indicate that the output has been completely written.
21112 * When writing a command completion or response to an internal processor,
21113 * the order of writes has to be such that this field is written last.
21118 /**********************************
21119 * hwrm_port_phy_mdio_bus_release *
21120 **********************************/
21123 /* hwrm_port_phy_mdio_bus_release_input (size:192b/24B) */
21124 struct hwrm_port_phy_mdio_bus_release_input {
21125 /* The HWRM command request type. */
21128 * The completion ring to send the completion event on. This should
21129 * be the NQ ID returned from the `nq_alloc` HWRM command.
21131 uint16_t cmpl_ring;
21133 * The sequence ID is used by the driver for tracking multiple
21134 * commands. This ID is treated as opaque data by the firmware and
21135 * the value is returned in the `hwrm_resp_hdr` upon completion.
21139 * The target ID of the command:
21140 * * 0x0-0xFFF8 - The function ID
21141 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21142 * * 0xFFFD - Reserved for user-space HWRM interface
21145 uint16_t target_id;
21147 * A physical address pointer pointing to a host buffer that the
21148 * command's response data will be written. This can be either a host
21149 * physical address (HPA) or a guest physical address (GPA) and must
21150 * point to a physically contiguous block of memory.
21152 uint64_t resp_addr;
21153 /* Port ID of the port. */
21156 * client_id of the client requesting BUS release.
21157 * A client should not release any other clients BUS.
21159 uint16_t client_id;
21160 uint8_t unused_0[4];
21163 /* hwrm_port_phy_mdio_bus_release_output (size:128b/16B) */
21164 struct hwrm_port_phy_mdio_bus_release_output {
21165 /* The specific error status for the command. */
21166 uint16_t error_code;
21167 /* The HWRM command request type. */
21169 /* The sequence ID from the original command. */
21171 /* The length of the response data in number of bytes. */
21174 /* The BUS is released if client_id matches the client_id in request. */
21175 uint16_t clients_id;
21176 uint8_t unused_1[3];
21178 * This field is used in Output records to indicate that the output
21179 * is completely written to RAM. This field should be read as '1'
21180 * to indicate that the output has been completely written.
21181 * When writing a command completion or response to an internal processor,
21182 * the order of writes has to be such that this field is written last.
21187 /***********************
21188 * hwrm_queue_qportcfg *
21189 ***********************/
21192 /* hwrm_queue_qportcfg_input (size:192b/24B) */
21193 struct hwrm_queue_qportcfg_input {
21194 /* The HWRM command request type. */
21197 * The completion ring to send the completion event on. This should
21198 * be the NQ ID returned from the `nq_alloc` HWRM command.
21200 uint16_t cmpl_ring;
21202 * The sequence ID is used by the driver for tracking multiple
21203 * commands. This ID is treated as opaque data by the firmware and
21204 * the value is returned in the `hwrm_resp_hdr` upon completion.
21208 * The target ID of the command:
21209 * * 0x0-0xFFF8 - The function ID
21210 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21211 * * 0xFFFD - Reserved for user-space HWRM interface
21214 uint16_t target_id;
21216 * A physical address pointer pointing to a host buffer that the
21217 * command's response data will be written. This can be either a host
21218 * physical address (HPA) or a guest physical address (GPA) and must
21219 * point to a physically contiguous block of memory.
21221 uint64_t resp_addr;
21224 * Enumeration denoting the RX, TX type of the resource.
21225 * This enumeration is used for resources that are similar for both
21226 * TX and RX paths of the chip.
21228 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21230 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21232 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21233 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
21234 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
21236 * Port ID of port for which the queue configuration is being
21237 * queried. This field is only required when sent by IPC.
21241 * Drivers will set this capability when it can use
21242 * queue_idx_service_profile to map the queues to application.
21244 uint8_t drv_qmap_cap;
21246 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
21248 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
21249 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
21250 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
21254 /* hwrm_queue_qportcfg_output (size:256b/32B) */
21255 struct hwrm_queue_qportcfg_output {
21256 /* The specific error status for the command. */
21257 uint16_t error_code;
21258 /* The HWRM command request type. */
21260 /* The sequence ID from the original command. */
21262 /* The length of the response data in number of bytes. */
21265 * The maximum number of queues that can be configured on this
21267 * Valid values range from 1 through 8.
21269 uint8_t max_configurable_queues;
21271 * The maximum number of lossless queues that can be configured
21273 * Valid values range from 0 through 8.
21275 uint8_t max_configurable_lossless_queues;
21277 * Bitmask indicating which queues can be configured by the
21278 * hwrm_queue_cfg command.
21280 * Each bit represents a specific queue where bit 0 represents
21281 * queue 0 and bit 7 represents queue 7.
21282 * # A value of 0 indicates that the queue is not configurable
21283 * by the hwrm_queue_cfg command.
21284 * # A value of 1 indicates that the queue is configurable.
21285 * # A hwrm_queue_cfg command shall return error when trying to
21286 * configure a queue not configurable.
21288 uint8_t queue_cfg_allowed;
21289 /* Information about queue configuration. */
21290 uint8_t queue_cfg_info;
21292 * If this flag is set to '1', then the queues are
21293 * configured asymmetrically on TX and RX sides.
21294 * If this flag is set to '0', then the queues are
21295 * configured symmetrically on TX and RX sides. For
21296 * symmetric configuration, the queue configuration
21297 * including queue ids and service profiles on the
21298 * TX side is the same as the corresponding queue
21299 * configuration on the RX side.
21301 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21304 * Bitmask indicating which queues can be configured by the
21305 * hwrm_queue_pfcenable_cfg command.
21307 * Each bit represents a specific priority where bit 0 represents
21308 * priority 0 and bit 7 represents priority 7.
21309 * # A value of 0 indicates that the priority is not configurable by
21310 * the hwrm_queue_pfcenable_cfg command.
21311 * # A value of 1 indicates that the priority is configurable.
21312 * # A hwrm_queue_pfcenable_cfg command shall return error when
21313 * trying to configure a priority that is not configurable.
21315 uint8_t queue_pfcenable_cfg_allowed;
21317 * Bitmask indicating which queues can be configured by the
21318 * hwrm_queue_pri2cos_cfg command.
21320 * Each bit represents a specific queue where bit 0 represents
21321 * queue 0 and bit 7 represents queue 7.
21322 * # A value of 0 indicates that the queue is not configurable
21323 * by the hwrm_queue_pri2cos_cfg command.
21324 * # A value of 1 indicates that the queue is configurable.
21325 * # A hwrm_queue_pri2cos_cfg command shall return error when
21326 * trying to configure a queue that is not configurable.
21328 uint8_t queue_pri2cos_cfg_allowed;
21330 * Bitmask indicating which queues can be configured by the
21331 * hwrm_queue_pri2cos_cfg command.
21333 * Each bit represents a specific queue where bit 0 represents
21334 * queue 0 and bit 7 represents queue 7.
21335 * # A value of 0 indicates that the queue is not configurable
21336 * by the hwrm_queue_pri2cos_cfg command.
21337 * # A value of 1 indicates that the queue is configurable.
21338 * # A hwrm_queue_pri2cos_cfg command shall return error when
21339 * trying to configure a queue not configurable.
21341 uint8_t queue_cos2bw_cfg_allowed;
21343 * ID of CoS Queue 0.
21346 * # This ID can be used on any subsequent call to an hwrm command
21347 * that takes a queue id.
21348 * # IDs must always be queried by this command before any use
21349 * by the driver or software.
21350 * # Any driver or software should not make any assumptions about
21352 * # A value of 0xff indicates that the queue is not available.
21353 * # Available queues may not be in sequential order.
21356 /* This value is applicable to CoS queues only. */
21357 uint8_t queue_id0_service_profile;
21358 /* Lossy (best-effort) */
21359 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
21361 /* Lossless (legacy) */
21362 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
21364 /* Lossless RoCE */
21365 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
21367 /* Lossy RoCE CNP */
21368 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21371 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
21373 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21374 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
21376 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
21377 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
21379 * ID of CoS Queue 1.
21382 * # This ID can be used on any subsequent call to an hwrm command
21383 * that takes a queue id.
21384 * # IDs must always be queried by this command before any use
21385 * by the driver or software.
21386 * # Any driver or software should not make any assumptions about
21388 * # A value of 0xff indicates that the queue is not available.
21389 * # Available queues may not be in sequential order.
21392 /* This value is applicable to CoS queues only. */
21393 uint8_t queue_id1_service_profile;
21394 /* Lossy (best-effort) */
21395 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
21397 /* Lossless (legacy) */
21398 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
21400 /* Lossless RoCE */
21401 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
21403 /* Lossy RoCE CNP */
21404 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21407 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
21409 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21410 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
21412 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
21413 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
21415 * ID of CoS Queue 2.
21418 * # This ID can be used on any subsequent call to an hwrm command
21419 * that takes a queue id.
21420 * # IDs must always be queried by this command before any use
21421 * by the driver or software.
21422 * # Any driver or software should not make any assumptions about
21424 * # A value of 0xff indicates that the queue is not available.
21425 * # Available queues may not be in sequential order.
21428 /* This value is applicable to CoS queues only. */
21429 uint8_t queue_id2_service_profile;
21430 /* Lossy (best-effort) */
21431 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
21433 /* Lossless (legacy) */
21434 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
21436 /* Lossless RoCE */
21437 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
21439 /* Lossy RoCE CNP */
21440 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21443 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
21445 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21446 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
21448 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
21449 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
21451 * ID of CoS Queue 3.
21454 * # This ID can be used on any subsequent call to an hwrm command
21455 * that takes a queue id.
21456 * # IDs must always be queried by this command before any use
21457 * by the driver or software.
21458 * # Any driver or software should not make any assumptions about
21460 * # A value of 0xff indicates that the queue is not available.
21461 * # Available queues may not be in sequential order.
21464 /* This value is applicable to CoS queues only. */
21465 uint8_t queue_id3_service_profile;
21466 /* Lossy (best-effort) */
21467 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
21469 /* Lossless (legacy) */
21470 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
21472 /* Lossless RoCE */
21473 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
21475 /* Lossy RoCE CNP */
21476 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21479 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
21481 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21482 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
21484 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
21485 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
21487 * ID of CoS Queue 4.
21490 * # This ID can be used on any subsequent call to an hwrm command
21491 * that takes a queue id.
21492 * # IDs must always be queried by this command before any use
21493 * by the driver or software.
21494 * # Any driver or software should not make any assumptions about
21496 * # A value of 0xff indicates that the queue is not available.
21497 * # Available queues may not be in sequential order.
21500 /* This value is applicable to CoS queues only. */
21501 uint8_t queue_id4_service_profile;
21502 /* Lossy (best-effort) */
21503 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
21505 /* Lossless (legacy) */
21506 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
21508 /* Lossless RoCE */
21509 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
21511 /* Lossy RoCE CNP */
21512 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21515 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
21517 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21518 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
21520 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
21521 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
21523 * ID of CoS Queue 5.
21526 * # This ID can be used on any subsequent call to an hwrm command
21527 * that takes a queue id.
21528 * # IDs must always be queried by this command before any use
21529 * by the driver or software.
21530 * # Any driver or software should not make any assumptions about
21532 * # A value of 0xff indicates that the queue is not available.
21533 * # Available queues may not be in sequential order.
21536 /* This value is applicable to CoS queues only. */
21537 uint8_t queue_id5_service_profile;
21538 /* Lossy (best-effort) */
21539 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
21541 /* Lossless (legacy) */
21542 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
21544 /* Lossless RoCE */
21545 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
21547 /* Lossy RoCE CNP */
21548 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21551 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
21553 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21554 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
21556 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
21557 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
21559 * ID of CoS Queue 6.
21562 * # This ID can be used on any subsequent call to an hwrm command
21563 * that takes a queue id.
21564 * # IDs must always be queried by this command before any use
21565 * by the driver or software.
21566 * # Any driver or software should not make any assumptions about
21568 * # A value of 0xff indicates that the queue is not available.
21569 * # Available queues may not be in sequential order.
21572 /* This value is applicable to CoS queues only. */
21573 uint8_t queue_id6_service_profile;
21574 /* Lossy (best-effort) */
21575 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
21577 /* Lossless (legacy) */
21578 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
21580 /* Lossless RoCE */
21581 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
21583 /* Lossy RoCE CNP */
21584 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21587 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
21589 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21590 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
21592 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
21593 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
21595 * ID of CoS Queue 7.
21598 * # This ID can be used on any subsequent call to an hwrm command
21599 * that takes a queue id.
21600 * # IDs must always be queried by this command before any use
21601 * by the driver or software.
21602 * # Any driver or software should not make any assumptions about
21604 * # A value of 0xff indicates that the queue is not available.
21605 * # Available queues may not be in sequential order.
21608 /* This value is applicable to CoS queues only. */
21609 uint8_t queue_id7_service_profile;
21610 /* Lossy (best-effort) */
21611 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
21613 /* Lossless (legacy) */
21614 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
21616 /* Lossless RoCE */
21617 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
21619 /* Lossy RoCE CNP */
21620 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
21623 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
21625 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21626 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
21628 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
21629 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
21631 * This field is used in Output records to indicate that the output
21632 * is completely written to RAM. This field should be read as '1'
21633 * to indicate that the output has been completely written.
21634 * When writing a command completion or response to an internal processor,
21635 * the order of writes has to be such that this field is written last.
21640 /*******************
21641 * hwrm_queue_qcfg *
21642 *******************/
21645 /* hwrm_queue_qcfg_input (size:192b/24B) */
21646 struct hwrm_queue_qcfg_input {
21647 /* The HWRM command request type. */
21650 * The completion ring to send the completion event on. This should
21651 * be the NQ ID returned from the `nq_alloc` HWRM command.
21653 uint16_t cmpl_ring;
21655 * The sequence ID is used by the driver for tracking multiple
21656 * commands. This ID is treated as opaque data by the firmware and
21657 * the value is returned in the `hwrm_resp_hdr` upon completion.
21661 * The target ID of the command:
21662 * * 0x0-0xFFF8 - The function ID
21663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21664 * * 0xFFFD - Reserved for user-space HWRM interface
21667 uint16_t target_id;
21669 * A physical address pointer pointing to a host buffer that the
21670 * command's response data will be written. This can be either a host
21671 * physical address (HPA) or a guest physical address (GPA) and must
21672 * point to a physically contiguous block of memory.
21674 uint64_t resp_addr;
21677 * Enumeration denoting the RX, TX type of the resource.
21678 * This enumeration is used for resources that are similar for both
21679 * TX and RX paths of the chip.
21681 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
21683 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21685 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21686 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
21687 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
21688 /* Queue ID of the queue. */
21692 /* hwrm_queue_qcfg_output (size:128b/16B) */
21693 struct hwrm_queue_qcfg_output {
21694 /* The specific error status for the command. */
21695 uint16_t error_code;
21696 /* The HWRM command request type. */
21698 /* The sequence ID from the original command. */
21700 /* The length of the response data in number of bytes. */
21703 * This value is the estimate packet length used in the
21706 uint32_t queue_len;
21707 /* This value is applicable to CoS queues only. */
21708 uint8_t service_profile;
21709 /* Lossy (best-effort) */
21710 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
21712 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
21713 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21714 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
21715 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
21716 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
21717 /* Information about queue configuration. */
21718 uint8_t queue_cfg_info;
21720 * If this flag is set to '1', then the queue is
21721 * configured asymmetrically on TX and RX sides.
21722 * If this flag is set to '0', then this queue is
21723 * configured symmetrically on TX and RX sides.
21725 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
21729 * This field is used in Output records to indicate that the output
21730 * is completely written to RAM. This field should be read as '1'
21731 * to indicate that the output has been completely written.
21732 * When writing a command completion or response to an internal processor,
21733 * the order of writes has to be such that this field is written last.
21738 /******************
21740 ******************/
21743 /* hwrm_queue_cfg_input (size:320b/40B) */
21744 struct hwrm_queue_cfg_input {
21745 /* The HWRM command request type. */
21748 * The completion ring to send the completion event on. This should
21749 * be the NQ ID returned from the `nq_alloc` HWRM command.
21751 uint16_t cmpl_ring;
21753 * The sequence ID is used by the driver for tracking multiple
21754 * commands. This ID is treated as opaque data by the firmware and
21755 * the value is returned in the `hwrm_resp_hdr` upon completion.
21759 * The target ID of the command:
21760 * * 0x0-0xFFF8 - The function ID
21761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21762 * * 0xFFFD - Reserved for user-space HWRM interface
21765 uint16_t target_id;
21767 * A physical address pointer pointing to a host buffer that the
21768 * command's response data will be written. This can be either a host
21769 * physical address (HPA) or a guest physical address (GPA) and must
21770 * point to a physically contiguous block of memory.
21772 uint64_t resp_addr;
21775 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
21776 * This enumeration is used for resources that are similar for both
21777 * TX and RX paths of the chip.
21779 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
21780 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
21782 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
21784 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
21785 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
21786 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
21787 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
21788 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
21791 * This bit must be '1' for the dflt_len field to be
21794 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
21796 * This bit must be '1' for the service_profile field to be
21799 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
21800 /* Queue ID of queue that is to be configured by this function. */
21803 * This value is a the estimate packet length used in the
21805 * Set to 0xFF... (All Fs) to not adjust this value.
21808 /* This value is applicable to CoS queues only. */
21809 uint8_t service_profile;
21810 /* Lossy (best-effort) */
21811 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
21813 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
21814 /* Set to 0xFF... (All Fs) if there is no service profile specified */
21815 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
21816 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
21817 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
21818 uint8_t unused_0[7];
21821 /* hwrm_queue_cfg_output (size:128b/16B) */
21822 struct hwrm_queue_cfg_output {
21823 /* The specific error status for the command. */
21824 uint16_t error_code;
21825 /* The HWRM command request type. */
21827 /* The sequence ID from the original command. */
21829 /* The length of the response data in number of bytes. */
21831 uint8_t unused_0[7];
21833 * This field is used in Output records to indicate that the output
21834 * is completely written to RAM. This field should be read as '1'
21835 * to indicate that the output has been completely written.
21836 * When writing a command completion or response to an internal processor,
21837 * the order of writes has to be such that this field is written last.
21842 /*****************************
21843 * hwrm_queue_pfcenable_qcfg *
21844 *****************************/
21847 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
21848 struct hwrm_queue_pfcenable_qcfg_input {
21849 /* The HWRM command request type. */
21852 * The completion ring to send the completion event on. This should
21853 * be the NQ ID returned from the `nq_alloc` HWRM command.
21855 uint16_t cmpl_ring;
21857 * The sequence ID is used by the driver for tracking multiple
21858 * commands. This ID is treated as opaque data by the firmware and
21859 * the value is returned in the `hwrm_resp_hdr` upon completion.
21863 * The target ID of the command:
21864 * * 0x0-0xFFF8 - The function ID
21865 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21866 * * 0xFFFD - Reserved for user-space HWRM interface
21869 uint16_t target_id;
21871 * A physical address pointer pointing to a host buffer that the
21872 * command's response data will be written. This can be either a host
21873 * physical address (HPA) or a guest physical address (GPA) and must
21874 * point to a physically contiguous block of memory.
21876 uint64_t resp_addr;
21878 * Port ID of port for which the table is being configured.
21879 * The HWRM needs to check whether this function is allowed
21880 * to configure pri2cos mapping on this port.
21883 uint8_t unused_0[6];
21886 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
21887 struct hwrm_queue_pfcenable_qcfg_output {
21888 /* The specific error status for the command. */
21889 uint16_t error_code;
21890 /* The HWRM command request type. */
21892 /* The sequence ID from the original command. */
21894 /* The length of the response data in number of bytes. */
21897 /* If set to 1, then PFC is enabled on PRI 0. */
21898 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
21900 /* If set to 1, then PFC is enabled on PRI 1. */
21901 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
21903 /* If set to 1, then PFC is enabled on PRI 2. */
21904 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
21906 /* If set to 1, then PFC is enabled on PRI 3. */
21907 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
21909 /* If set to 1, then PFC is enabled on PRI 4. */
21910 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
21912 /* If set to 1, then PFC is enabled on PRI 5. */
21913 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
21915 /* If set to 1, then PFC is enabled on PRI 6. */
21916 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
21918 /* If set to 1, then PFC is enabled on PRI 7. */
21919 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
21921 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
21922 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
21924 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
21925 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
21927 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
21928 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
21930 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
21931 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
21933 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
21934 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
21936 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
21937 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
21939 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
21940 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
21942 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
21943 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
21945 uint8_t unused_0[3];
21947 * This field is used in Output records to indicate that the output
21948 * is completely written to RAM. This field should be read as '1'
21949 * to indicate that the output has been completely written.
21950 * When writing a command completion or response to an internal processor,
21951 * the order of writes has to be such that this field is written last.
21956 /****************************
21957 * hwrm_queue_pfcenable_cfg *
21958 ****************************/
21961 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
21962 struct hwrm_queue_pfcenable_cfg_input {
21963 /* The HWRM command request type. */
21966 * The completion ring to send the completion event on. This should
21967 * be the NQ ID returned from the `nq_alloc` HWRM command.
21969 uint16_t cmpl_ring;
21971 * The sequence ID is used by the driver for tracking multiple
21972 * commands. This ID is treated as opaque data by the firmware and
21973 * the value is returned in the `hwrm_resp_hdr` upon completion.
21977 * The target ID of the command:
21978 * * 0x0-0xFFF8 - The function ID
21979 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21980 * * 0xFFFD - Reserved for user-space HWRM interface
21983 uint16_t target_id;
21985 * A physical address pointer pointing to a host buffer that the
21986 * command's response data will be written. This can be either a host
21987 * physical address (HPA) or a guest physical address (GPA) and must
21988 * point to a physically contiguous block of memory.
21990 uint64_t resp_addr;
21992 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
21993 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
21995 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
21996 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
21998 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
21999 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
22001 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
22002 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
22004 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
22005 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
22007 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
22008 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
22010 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
22011 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
22013 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
22014 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
22016 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */
22017 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \
22019 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */
22020 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \
22022 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */
22023 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \
22025 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */
22026 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \
22028 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */
22029 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \
22031 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */
22032 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \
22034 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */
22035 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \
22037 /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */
22038 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \
22041 * Port ID of port for which the table is being configured.
22042 * The HWRM needs to check whether this function is allowed
22043 * to configure pri2cos mapping on this port.
22046 uint8_t unused_0[2];
22049 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
22050 struct hwrm_queue_pfcenable_cfg_output {
22051 /* The specific error status for the command. */
22052 uint16_t error_code;
22053 /* The HWRM command request type. */
22055 /* The sequence ID from the original command. */
22057 /* The length of the response data in number of bytes. */
22059 uint8_t unused_0[7];
22061 * This field is used in Output records to indicate that the output
22062 * is completely written to RAM. This field should be read as '1'
22063 * to indicate that the output has been completely written.
22064 * When writing a command completion or response to an internal processor,
22065 * the order of writes has to be such that this field is written last.
22070 /***************************
22071 * hwrm_queue_pri2cos_qcfg *
22072 ***************************/
22075 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
22076 struct hwrm_queue_pri2cos_qcfg_input {
22077 /* The HWRM command request type. */
22080 * The completion ring to send the completion event on. This should
22081 * be the NQ ID returned from the `nq_alloc` HWRM command.
22083 uint16_t cmpl_ring;
22085 * The sequence ID is used by the driver for tracking multiple
22086 * commands. This ID is treated as opaque data by the firmware and
22087 * the value is returned in the `hwrm_resp_hdr` upon completion.
22091 * The target ID of the command:
22092 * * 0x0-0xFFF8 - The function ID
22093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22094 * * 0xFFFD - Reserved for user-space HWRM interface
22097 uint16_t target_id;
22099 * A physical address pointer pointing to a host buffer that the
22100 * command's response data will be written. This can be either a host
22101 * physical address (HPA) or a guest physical address (GPA) and must
22102 * point to a physically contiguous block of memory.
22104 uint64_t resp_addr;
22107 * Enumeration denoting the RX, TX type of the resource.
22108 * This enumeration is used for resources that are similar for both
22109 * TX and RX paths of the chip.
22111 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
22113 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22115 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22116 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
22117 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
22119 * When this bit is set to '0', the query is
22120 * for PRI from tunnel headers.
22121 * When this bit is set to '1', the query is
22122 * for PRI from inner packet headers.
22124 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
22126 * Port ID of port for which the table is being configured.
22127 * The HWRM needs to check whether this function is allowed
22128 * to configure pri2cos mapping on this port.
22131 uint8_t unused_0[3];
22134 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
22135 struct hwrm_queue_pri2cos_qcfg_output {
22136 /* The specific error status for the command. */
22137 uint16_t error_code;
22138 /* The HWRM command request type. */
22140 /* The sequence ID from the original command. */
22142 /* The length of the response data in number of bytes. */
22145 * CoS Queue assigned to priority 0. This value can only
22146 * be changed before traffic has started.
22147 * A value of 0xff indicates that no CoS queue is assigned to the
22148 * specified priority.
22150 uint8_t pri0_cos_queue_id;
22152 * CoS Queue assigned to priority 1. This value can only
22153 * be changed before traffic has started.
22154 * A value of 0xff indicates that no CoS queue is assigned to the
22155 * specified priority.
22157 uint8_t pri1_cos_queue_id;
22159 * CoS Queue assigned to priority 2. This value can only
22160 * be changed before traffic has started.
22161 * A value of 0xff indicates that no CoS queue is assigned to the
22162 * specified priority.
22164 uint8_t pri2_cos_queue_id;
22166 * CoS Queue assigned to priority 3. This value can only
22167 * be changed before traffic has started.
22168 * A value of 0xff indicates that no CoS queue is assigned to the
22169 * specified priority.
22171 uint8_t pri3_cos_queue_id;
22173 * CoS Queue assigned to priority 4. This value can only
22174 * be changed before traffic has started.
22175 * A value of 0xff indicates that no CoS queue is assigned to the
22176 * specified priority.
22178 uint8_t pri4_cos_queue_id;
22180 * CoS Queue assigned to priority 5. This value can only
22181 * be changed before traffic has started.
22182 * A value of 0xff indicates that no CoS queue is assigned to the
22183 * specified priority.
22185 uint8_t pri5_cos_queue_id;
22187 * CoS Queue assigned to priority 6. This value can only
22188 * be changed before traffic has started.
22189 * A value of 0xff indicates that no CoS queue is assigned to the
22190 * specified priority.
22192 uint8_t pri6_cos_queue_id;
22194 * CoS Queue assigned to priority 7. This value can only
22195 * be changed before traffic has started.
22196 * A value of 0xff indicates that no CoS queue is assigned to the
22197 * specified priority.
22199 uint8_t pri7_cos_queue_id;
22200 /* Information about queue configuration. */
22201 uint8_t queue_cfg_info;
22203 * If this flag is set to '1', then the PRI to CoS
22204 * configuration is asymmetric on TX and RX sides.
22205 * If this flag is set to '0', then PRI to CoS configuration
22206 * is symmetric on TX and RX sides.
22208 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
22210 uint8_t unused_0[6];
22212 * This field is used in Output records to indicate that the output
22213 * is completely written to RAM. This field should be read as '1'
22214 * to indicate that the output has been completely written.
22215 * When writing a command completion or response to an internal processor,
22216 * the order of writes has to be such that this field is written last.
22221 /**************************
22222 * hwrm_queue_pri2cos_cfg *
22223 **************************/
22226 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
22227 struct hwrm_queue_pri2cos_cfg_input {
22228 /* The HWRM command request type. */
22231 * The completion ring to send the completion event on. This should
22232 * be the NQ ID returned from the `nq_alloc` HWRM command.
22234 uint16_t cmpl_ring;
22236 * The sequence ID is used by the driver for tracking multiple
22237 * commands. This ID is treated as opaque data by the firmware and
22238 * the value is returned in the `hwrm_resp_hdr` upon completion.
22242 * The target ID of the command:
22243 * * 0x0-0xFFF8 - The function ID
22244 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22245 * * 0xFFFD - Reserved for user-space HWRM interface
22248 uint16_t target_id;
22250 * A physical address pointer pointing to a host buffer that the
22251 * command's response data will be written. This can be either a host
22252 * physical address (HPA) or a guest physical address (GPA) and must
22253 * point to a physically contiguous block of memory.
22255 uint64_t resp_addr;
22258 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
22259 * This enumeration is used for resources that are similar for both
22260 * TX and RX paths of the chip.
22262 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
22263 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
22265 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22267 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22268 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
22269 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
22270 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
22271 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
22273 * When this bit is set to '0', the mapping is requested
22274 * for PRI from tunnel headers.
22275 * When this bit is set to '1', the mapping is requested
22276 * for PRI from inner packet headers.
22278 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
22281 * This bit must be '1' for the pri0_cos_queue_id field to be
22284 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
22287 * This bit must be '1' for the pri1_cos_queue_id field to be
22290 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
22293 * This bit must be '1' for the pri2_cos_queue_id field to be
22296 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
22299 * This bit must be '1' for the pri3_cos_queue_id field to be
22302 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
22305 * This bit must be '1' for the pri4_cos_queue_id field to be
22308 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
22311 * This bit must be '1' for the pri5_cos_queue_id field to be
22314 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
22317 * This bit must be '1' for the pri6_cos_queue_id field to be
22320 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
22323 * This bit must be '1' for the pri7_cos_queue_id field to be
22326 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
22329 * Port ID of port for which the table is being configured.
22330 * The HWRM needs to check whether this function is allowed
22331 * to configure pri2cos mapping on this port.
22335 * CoS Queue assigned to priority 0. This value can only
22336 * be changed before traffic has started.
22338 uint8_t pri0_cos_queue_id;
22340 * CoS Queue assigned to priority 1. This value can only
22341 * be changed before traffic has started.
22343 uint8_t pri1_cos_queue_id;
22345 * CoS Queue assigned to priority 2 This value can only
22346 * be changed before traffic has started.
22348 uint8_t pri2_cos_queue_id;
22350 * CoS Queue assigned to priority 3. This value can only
22351 * be changed before traffic has started.
22353 uint8_t pri3_cos_queue_id;
22355 * CoS Queue assigned to priority 4. This value can only
22356 * be changed before traffic has started.
22358 uint8_t pri4_cos_queue_id;
22360 * CoS Queue assigned to priority 5. This value can only
22361 * be changed before traffic has started.
22363 uint8_t pri5_cos_queue_id;
22365 * CoS Queue assigned to priority 6. This value can only
22366 * be changed before traffic has started.
22368 uint8_t pri6_cos_queue_id;
22370 * CoS Queue assigned to priority 7. This value can only
22371 * be changed before traffic has started.
22373 uint8_t pri7_cos_queue_id;
22374 uint8_t unused_0[7];
22377 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
22378 struct hwrm_queue_pri2cos_cfg_output {
22379 /* The specific error status for the command. */
22380 uint16_t error_code;
22381 /* The HWRM command request type. */
22383 /* The sequence ID from the original command. */
22385 /* The length of the response data in number of bytes. */
22387 uint8_t unused_0[7];
22389 * This field is used in Output records to indicate that the output
22390 * is completely written to RAM. This field should be read as '1'
22391 * to indicate that the output has been completely written.
22392 * When writing a command completion or response to an internal processor,
22393 * the order of writes has to be such that this field is written last.
22398 /**************************
22399 * hwrm_queue_cos2bw_qcfg *
22400 **************************/
22403 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
22404 struct hwrm_queue_cos2bw_qcfg_input {
22405 /* The HWRM command request type. */
22408 * The completion ring to send the completion event on. This should
22409 * be the NQ ID returned from the `nq_alloc` HWRM command.
22411 uint16_t cmpl_ring;
22413 * The sequence ID is used by the driver for tracking multiple
22414 * commands. This ID is treated as opaque data by the firmware and
22415 * the value is returned in the `hwrm_resp_hdr` upon completion.
22419 * The target ID of the command:
22420 * * 0x0-0xFFF8 - The function ID
22421 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22422 * * 0xFFFD - Reserved for user-space HWRM interface
22425 uint16_t target_id;
22427 * A physical address pointer pointing to a host buffer that the
22428 * command's response data will be written. This can be either a host
22429 * physical address (HPA) or a guest physical address (GPA) and must
22430 * point to a physically contiguous block of memory.
22432 uint64_t resp_addr;
22434 * Port ID of port for which the table is being configured.
22435 * The HWRM needs to check whether this function is allowed
22436 * to configure TC BW assignment on this port.
22439 uint8_t unused_0[6];
22442 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
22443 struct hwrm_queue_cos2bw_qcfg_output {
22444 /* The specific error status for the command. */
22445 uint16_t error_code;
22446 /* The HWRM command request type. */
22448 /* The sequence ID from the original command. */
22450 /* The length of the response data in number of bytes. */
22452 /* ID of CoS Queue 0. */
22457 * Minimum BW allocated to CoS Queue.
22458 * The HWRM will translate this value into byte counter and
22459 * time interval used for this COS inside the device.
22461 uint32_t queue_id0_min_bw;
22462 /* The bandwidth value. */
22463 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
22464 UINT32_C(0xfffffff)
22465 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
22467 /* The granularity of the value (bits or bytes). */
22468 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
22469 UINT32_C(0x10000000)
22470 /* Value is in bits. */
22471 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
22472 (UINT32_C(0x0) << 28)
22473 /* Value is in bytes. */
22474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
22475 (UINT32_C(0x1) << 28)
22476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
22477 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
22478 /* bw_value_unit is 3 b */
22479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
22480 UINT32_C(0xe0000000)
22481 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
22483 /* Value is in Mb or MB (base 10). */
22484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
22485 (UINT32_C(0x0) << 29)
22486 /* Value is in Kb or KB (base 10). */
22487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
22488 (UINT32_C(0x2) << 29)
22489 /* Value is in bits or bytes. */
22490 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
22491 (UINT32_C(0x4) << 29)
22492 /* Value is in Gb or GB (base 10). */
22493 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
22494 (UINT32_C(0x6) << 29)
22495 /* Value is in 1/100th of a percentage of total bandwidth. */
22496 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22497 (UINT32_C(0x1) << 29)
22499 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
22500 (UINT32_C(0x7) << 29)
22501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
22502 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
22504 * Maximum BW allocated to CoS Queue.
22505 * The HWRM will translate this value into byte counter and
22506 * time interval used for this COS inside the device.
22508 uint32_t queue_id0_max_bw;
22509 /* The bandwidth value. */
22510 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
22511 UINT32_C(0xfffffff)
22512 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
22514 /* The granularity of the value (bits or bytes). */
22515 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
22516 UINT32_C(0x10000000)
22517 /* Value is in bits. */
22518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
22519 (UINT32_C(0x0) << 28)
22520 /* Value is in bytes. */
22521 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
22522 (UINT32_C(0x1) << 28)
22523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
22524 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
22525 /* bw_value_unit is 3 b */
22526 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
22527 UINT32_C(0xe0000000)
22528 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
22530 /* Value is in Mb or MB (base 10). */
22531 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
22532 (UINT32_C(0x0) << 29)
22533 /* Value is in Kb or KB (base 10). */
22534 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
22535 (UINT32_C(0x2) << 29)
22536 /* Value is in bits or bytes. */
22537 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
22538 (UINT32_C(0x4) << 29)
22539 /* Value is in Gb or GB (base 10). */
22540 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
22541 (UINT32_C(0x6) << 29)
22542 /* Value is in 1/100th of a percentage of total bandwidth. */
22543 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22544 (UINT32_C(0x1) << 29)
22546 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
22547 (UINT32_C(0x7) << 29)
22548 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
22549 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
22550 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22551 uint8_t queue_id0_tsa_assign;
22552 /* Strict Priority */
22553 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
22555 /* Enhanced Transmission Selection */
22556 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
22559 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
22562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
22565 * Priority level for strict priority. Valid only when the
22566 * tsa_assign is 0 - Strict Priority (SP)
22567 * 0..7 - Valid values.
22568 * 8..255 - Reserved.
22570 uint8_t queue_id0_pri_lvl;
22572 * Weight used to allocate remaining BW for this COS after
22573 * servicing guaranteed bandwidths for all COS.
22575 uint8_t queue_id0_bw_weight;
22576 /* ID of CoS Queue 1. */
22579 * Minimum BW allocated to CoS Queue.
22580 * The HWRM will translate this value into byte counter and
22581 * time interval used for this COS inside the device.
22583 uint32_t queue_id1_min_bw;
22584 /* The bandwidth value. */
22585 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
22586 UINT32_C(0xfffffff)
22587 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
22589 /* The granularity of the value (bits or bytes). */
22590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
22591 UINT32_C(0x10000000)
22592 /* Value is in bits. */
22593 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
22594 (UINT32_C(0x0) << 28)
22595 /* Value is in bytes. */
22596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
22597 (UINT32_C(0x1) << 28)
22598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
22599 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
22600 /* bw_value_unit is 3 b */
22601 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
22602 UINT32_C(0xe0000000)
22603 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
22605 /* Value is in Mb or MB (base 10). */
22606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
22607 (UINT32_C(0x0) << 29)
22608 /* Value is in Kb or KB (base 10). */
22609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
22610 (UINT32_C(0x2) << 29)
22611 /* Value is in bits or bytes. */
22612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
22613 (UINT32_C(0x4) << 29)
22614 /* Value is in Gb or GB (base 10). */
22615 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
22616 (UINT32_C(0x6) << 29)
22617 /* Value is in 1/100th of a percentage of total bandwidth. */
22618 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22619 (UINT32_C(0x1) << 29)
22621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
22622 (UINT32_C(0x7) << 29)
22623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
22624 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
22626 * Maximum BW allocated to CoS queue.
22627 * The HWRM will translate this value into byte counter and
22628 * time interval used for this COS inside the device.
22630 uint32_t queue_id1_max_bw;
22631 /* The bandwidth value. */
22632 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
22633 UINT32_C(0xfffffff)
22634 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
22636 /* The granularity of the value (bits or bytes). */
22637 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
22638 UINT32_C(0x10000000)
22639 /* Value is in bits. */
22640 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
22641 (UINT32_C(0x0) << 28)
22642 /* Value is in bytes. */
22643 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
22644 (UINT32_C(0x1) << 28)
22645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
22646 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
22647 /* bw_value_unit is 3 b */
22648 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
22649 UINT32_C(0xe0000000)
22650 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
22652 /* Value is in Mb or MB (base 10). */
22653 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
22654 (UINT32_C(0x0) << 29)
22655 /* Value is in Kb or KB (base 10). */
22656 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
22657 (UINT32_C(0x2) << 29)
22658 /* Value is in bits or bytes. */
22659 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
22660 (UINT32_C(0x4) << 29)
22661 /* Value is in Gb or GB (base 10). */
22662 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
22663 (UINT32_C(0x6) << 29)
22664 /* Value is in 1/100th of a percentage of total bandwidth. */
22665 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22666 (UINT32_C(0x1) << 29)
22668 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
22669 (UINT32_C(0x7) << 29)
22670 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
22671 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
22672 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22673 uint8_t queue_id1_tsa_assign;
22674 /* Strict Priority */
22675 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
22677 /* Enhanced Transmission Selection */
22678 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
22681 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
22684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
22687 * Priority level for strict priority. Valid only when the
22688 * tsa_assign is 0 - Strict Priority (SP)
22689 * 0..7 - Valid values.
22690 * 8..255 - Reserved.
22692 uint8_t queue_id1_pri_lvl;
22694 * Weight used to allocate remaining BW for this COS after
22695 * servicing guaranteed bandwidths for all COS.
22697 uint8_t queue_id1_bw_weight;
22698 /* ID of CoS Queue 2. */
22701 * Minimum BW allocated to CoS Queue.
22702 * The HWRM will translate this value into byte counter and
22703 * time interval used for this COS inside the device.
22705 uint32_t queue_id2_min_bw;
22706 /* The bandwidth value. */
22707 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
22708 UINT32_C(0xfffffff)
22709 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
22711 /* The granularity of the value (bits or bytes). */
22712 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
22713 UINT32_C(0x10000000)
22714 /* Value is in bits. */
22715 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
22716 (UINT32_C(0x0) << 28)
22717 /* Value is in bytes. */
22718 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
22719 (UINT32_C(0x1) << 28)
22720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
22721 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
22722 /* bw_value_unit is 3 b */
22723 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
22724 UINT32_C(0xe0000000)
22725 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
22727 /* Value is in Mb or MB (base 10). */
22728 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
22729 (UINT32_C(0x0) << 29)
22730 /* Value is in Kb or KB (base 10). */
22731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
22732 (UINT32_C(0x2) << 29)
22733 /* Value is in bits or bytes. */
22734 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
22735 (UINT32_C(0x4) << 29)
22736 /* Value is in Gb or GB (base 10). */
22737 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
22738 (UINT32_C(0x6) << 29)
22739 /* Value is in 1/100th of a percentage of total bandwidth. */
22740 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22741 (UINT32_C(0x1) << 29)
22743 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
22744 (UINT32_C(0x7) << 29)
22745 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
22746 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
22748 * Maximum BW allocated to CoS queue.
22749 * The HWRM will translate this value into byte counter and
22750 * time interval used for this COS inside the device.
22752 uint32_t queue_id2_max_bw;
22753 /* The bandwidth value. */
22754 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
22755 UINT32_C(0xfffffff)
22756 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
22758 /* The granularity of the value (bits or bytes). */
22759 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
22760 UINT32_C(0x10000000)
22761 /* Value is in bits. */
22762 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
22763 (UINT32_C(0x0) << 28)
22764 /* Value is in bytes. */
22765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
22766 (UINT32_C(0x1) << 28)
22767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
22768 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
22769 /* bw_value_unit is 3 b */
22770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
22771 UINT32_C(0xe0000000)
22772 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
22774 /* Value is in Mb or MB (base 10). */
22775 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
22776 (UINT32_C(0x0) << 29)
22777 /* Value is in Kb or KB (base 10). */
22778 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
22779 (UINT32_C(0x2) << 29)
22780 /* Value is in bits or bytes. */
22781 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
22782 (UINT32_C(0x4) << 29)
22783 /* Value is in Gb or GB (base 10). */
22784 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
22785 (UINT32_C(0x6) << 29)
22786 /* Value is in 1/100th of a percentage of total bandwidth. */
22787 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22788 (UINT32_C(0x1) << 29)
22790 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
22791 (UINT32_C(0x7) << 29)
22792 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
22793 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
22794 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22795 uint8_t queue_id2_tsa_assign;
22796 /* Strict Priority */
22797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
22799 /* Enhanced Transmission Selection */
22800 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
22803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
22806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
22809 * Priority level for strict priority. Valid only when the
22810 * tsa_assign is 0 - Strict Priority (SP)
22811 * 0..7 - Valid values.
22812 * 8..255 - Reserved.
22814 uint8_t queue_id2_pri_lvl;
22816 * Weight used to allocate remaining BW for this COS after
22817 * servicing guaranteed bandwidths for all COS.
22819 uint8_t queue_id2_bw_weight;
22820 /* ID of CoS Queue 3. */
22823 * Minimum BW allocated to CoS Queue.
22824 * The HWRM will translate this value into byte counter and
22825 * time interval used for this COS inside the device.
22827 uint32_t queue_id3_min_bw;
22828 /* The bandwidth value. */
22829 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
22830 UINT32_C(0xfffffff)
22831 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
22833 /* The granularity of the value (bits or bytes). */
22834 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
22835 UINT32_C(0x10000000)
22836 /* Value is in bits. */
22837 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
22838 (UINT32_C(0x0) << 28)
22839 /* Value is in bytes. */
22840 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
22841 (UINT32_C(0x1) << 28)
22842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
22843 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
22844 /* bw_value_unit is 3 b */
22845 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
22846 UINT32_C(0xe0000000)
22847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
22849 /* Value is in Mb or MB (base 10). */
22850 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
22851 (UINT32_C(0x0) << 29)
22852 /* Value is in Kb or KB (base 10). */
22853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
22854 (UINT32_C(0x2) << 29)
22855 /* Value is in bits or bytes. */
22856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
22857 (UINT32_C(0x4) << 29)
22858 /* Value is in Gb or GB (base 10). */
22859 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
22860 (UINT32_C(0x6) << 29)
22861 /* Value is in 1/100th of a percentage of total bandwidth. */
22862 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22863 (UINT32_C(0x1) << 29)
22865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
22866 (UINT32_C(0x7) << 29)
22867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
22868 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
22870 * Maximum BW allocated to CoS queue.
22871 * The HWRM will translate this value into byte counter and
22872 * time interval used for this COS inside the device.
22874 uint32_t queue_id3_max_bw;
22875 /* The bandwidth value. */
22876 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
22877 UINT32_C(0xfffffff)
22878 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
22880 /* The granularity of the value (bits or bytes). */
22881 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
22882 UINT32_C(0x10000000)
22883 /* Value is in bits. */
22884 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
22885 (UINT32_C(0x0) << 28)
22886 /* Value is in bytes. */
22887 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
22888 (UINT32_C(0x1) << 28)
22889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
22890 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
22891 /* bw_value_unit is 3 b */
22892 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
22893 UINT32_C(0xe0000000)
22894 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
22896 /* Value is in Mb or MB (base 10). */
22897 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
22898 (UINT32_C(0x0) << 29)
22899 /* Value is in Kb or KB (base 10). */
22900 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
22901 (UINT32_C(0x2) << 29)
22902 /* Value is in bits or bytes. */
22903 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
22904 (UINT32_C(0x4) << 29)
22905 /* Value is in Gb or GB (base 10). */
22906 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
22907 (UINT32_C(0x6) << 29)
22908 /* Value is in 1/100th of a percentage of total bandwidth. */
22909 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
22910 (UINT32_C(0x1) << 29)
22912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
22913 (UINT32_C(0x7) << 29)
22914 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
22915 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
22916 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
22917 uint8_t queue_id3_tsa_assign;
22918 /* Strict Priority */
22919 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
22921 /* Enhanced Transmission Selection */
22922 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
22925 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
22928 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
22931 * Priority level for strict priority. Valid only when the
22932 * tsa_assign is 0 - Strict Priority (SP)
22933 * 0..7 - Valid values.
22934 * 8..255 - Reserved.
22936 uint8_t queue_id3_pri_lvl;
22938 * Weight used to allocate remaining BW for this COS after
22939 * servicing guaranteed bandwidths for all COS.
22941 uint8_t queue_id3_bw_weight;
22942 /* ID of CoS Queue 4. */
22945 * Minimum BW allocated to CoS Queue.
22946 * The HWRM will translate this value into byte counter and
22947 * time interval used for this COS inside the device.
22949 uint32_t queue_id4_min_bw;
22950 /* The bandwidth value. */
22951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
22952 UINT32_C(0xfffffff)
22953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
22955 /* The granularity of the value (bits or bytes). */
22956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
22957 UINT32_C(0x10000000)
22958 /* Value is in bits. */
22959 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
22960 (UINT32_C(0x0) << 28)
22961 /* Value is in bytes. */
22962 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
22963 (UINT32_C(0x1) << 28)
22964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
22965 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
22966 /* bw_value_unit is 3 b */
22967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
22968 UINT32_C(0xe0000000)
22969 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
22971 /* Value is in Mb or MB (base 10). */
22972 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
22973 (UINT32_C(0x0) << 29)
22974 /* Value is in Kb or KB (base 10). */
22975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
22976 (UINT32_C(0x2) << 29)
22977 /* Value is in bits or bytes. */
22978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
22979 (UINT32_C(0x4) << 29)
22980 /* Value is in Gb or GB (base 10). */
22981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
22982 (UINT32_C(0x6) << 29)
22983 /* Value is in 1/100th of a percentage of total bandwidth. */
22984 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
22985 (UINT32_C(0x1) << 29)
22987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
22988 (UINT32_C(0x7) << 29)
22989 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
22990 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
22992 * Maximum BW allocated to CoS queue.
22993 * The HWRM will translate this value into byte counter and
22994 * time interval used for this COS inside the device.
22996 uint32_t queue_id4_max_bw;
22997 /* The bandwidth value. */
22998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
22999 UINT32_C(0xfffffff)
23000 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
23002 /* The granularity of the value (bits or bytes). */
23003 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
23004 UINT32_C(0x10000000)
23005 /* Value is in bits. */
23006 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
23007 (UINT32_C(0x0) << 28)
23008 /* Value is in bytes. */
23009 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
23010 (UINT32_C(0x1) << 28)
23011 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
23012 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
23013 /* bw_value_unit is 3 b */
23014 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
23015 UINT32_C(0xe0000000)
23016 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
23018 /* Value is in Mb or MB (base 10). */
23019 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
23020 (UINT32_C(0x0) << 29)
23021 /* Value is in Kb or KB (base 10). */
23022 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
23023 (UINT32_C(0x2) << 29)
23024 /* Value is in bits or bytes. */
23025 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
23026 (UINT32_C(0x4) << 29)
23027 /* Value is in Gb or GB (base 10). */
23028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
23029 (UINT32_C(0x6) << 29)
23030 /* Value is in 1/100th of a percentage of total bandwidth. */
23031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23032 (UINT32_C(0x1) << 29)
23034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
23035 (UINT32_C(0x7) << 29)
23036 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
23037 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
23038 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23039 uint8_t queue_id4_tsa_assign;
23040 /* Strict Priority */
23041 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
23043 /* Enhanced Transmission Selection */
23044 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
23047 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
23050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
23053 * Priority level for strict priority. Valid only when the
23054 * tsa_assign is 0 - Strict Priority (SP)
23055 * 0..7 - Valid values.
23056 * 8..255 - Reserved.
23058 uint8_t queue_id4_pri_lvl;
23060 * Weight used to allocate remaining BW for this COS after
23061 * servicing guaranteed bandwidths for all COS.
23063 uint8_t queue_id4_bw_weight;
23064 /* ID of CoS Queue 5. */
23067 * Minimum BW allocated to CoS Queue.
23068 * The HWRM will translate this value into byte counter and
23069 * time interval used for this COS inside the device.
23071 uint32_t queue_id5_min_bw;
23072 /* The bandwidth value. */
23073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
23074 UINT32_C(0xfffffff)
23075 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
23077 /* The granularity of the value (bits or bytes). */
23078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
23079 UINT32_C(0x10000000)
23080 /* Value is in bits. */
23081 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
23082 (UINT32_C(0x0) << 28)
23083 /* Value is in bytes. */
23084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
23085 (UINT32_C(0x1) << 28)
23086 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
23087 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
23088 /* bw_value_unit is 3 b */
23089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
23090 UINT32_C(0xe0000000)
23091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
23093 /* Value is in Mb or MB (base 10). */
23094 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
23095 (UINT32_C(0x0) << 29)
23096 /* Value is in Kb or KB (base 10). */
23097 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
23098 (UINT32_C(0x2) << 29)
23099 /* Value is in bits or bytes. */
23100 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
23101 (UINT32_C(0x4) << 29)
23102 /* Value is in Gb or GB (base 10). */
23103 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
23104 (UINT32_C(0x6) << 29)
23105 /* Value is in 1/100th of a percentage of total bandwidth. */
23106 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23107 (UINT32_C(0x1) << 29)
23109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
23110 (UINT32_C(0x7) << 29)
23111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
23112 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
23114 * Maximum BW allocated to CoS queue.
23115 * The HWRM will translate this value into byte counter and
23116 * time interval used for this COS inside the device.
23118 uint32_t queue_id5_max_bw;
23119 /* The bandwidth value. */
23120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
23121 UINT32_C(0xfffffff)
23122 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
23124 /* The granularity of the value (bits or bytes). */
23125 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
23126 UINT32_C(0x10000000)
23127 /* Value is in bits. */
23128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
23129 (UINT32_C(0x0) << 28)
23130 /* Value is in bytes. */
23131 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
23132 (UINT32_C(0x1) << 28)
23133 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
23134 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
23135 /* bw_value_unit is 3 b */
23136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
23137 UINT32_C(0xe0000000)
23138 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
23140 /* Value is in Mb or MB (base 10). */
23141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
23142 (UINT32_C(0x0) << 29)
23143 /* Value is in Kb or KB (base 10). */
23144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
23145 (UINT32_C(0x2) << 29)
23146 /* Value is in bits or bytes. */
23147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
23148 (UINT32_C(0x4) << 29)
23149 /* Value is in Gb or GB (base 10). */
23150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
23151 (UINT32_C(0x6) << 29)
23152 /* Value is in 1/100th of a percentage of total bandwidth. */
23153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23154 (UINT32_C(0x1) << 29)
23156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
23157 (UINT32_C(0x7) << 29)
23158 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
23159 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
23160 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23161 uint8_t queue_id5_tsa_assign;
23162 /* Strict Priority */
23163 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
23165 /* Enhanced Transmission Selection */
23166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
23169 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
23172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
23175 * Priority level for strict priority. Valid only when the
23176 * tsa_assign is 0 - Strict Priority (SP)
23177 * 0..7 - Valid values.
23178 * 8..255 - Reserved.
23180 uint8_t queue_id5_pri_lvl;
23182 * Weight used to allocate remaining BW for this COS after
23183 * servicing guaranteed bandwidths for all COS.
23185 uint8_t queue_id5_bw_weight;
23186 /* ID of CoS Queue 6. */
23189 * Minimum BW allocated to CoS Queue.
23190 * The HWRM will translate this value into byte counter and
23191 * time interval used for this COS inside the device.
23193 uint32_t queue_id6_min_bw;
23194 /* The bandwidth value. */
23195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
23196 UINT32_C(0xfffffff)
23197 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
23199 /* The granularity of the value (bits or bytes). */
23200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
23201 UINT32_C(0x10000000)
23202 /* Value is in bits. */
23203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
23204 (UINT32_C(0x0) << 28)
23205 /* Value is in bytes. */
23206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
23207 (UINT32_C(0x1) << 28)
23208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
23209 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
23210 /* bw_value_unit is 3 b */
23211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
23212 UINT32_C(0xe0000000)
23213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
23215 /* Value is in Mb or MB (base 10). */
23216 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
23217 (UINT32_C(0x0) << 29)
23218 /* Value is in Kb or KB (base 10). */
23219 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
23220 (UINT32_C(0x2) << 29)
23221 /* Value is in bits or bytes. */
23222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
23223 (UINT32_C(0x4) << 29)
23224 /* Value is in Gb or GB (base 10). */
23225 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
23226 (UINT32_C(0x6) << 29)
23227 /* Value is in 1/100th of a percentage of total bandwidth. */
23228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23229 (UINT32_C(0x1) << 29)
23231 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
23232 (UINT32_C(0x7) << 29)
23233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
23234 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
23236 * Maximum BW allocated to CoS queue.
23237 * The HWRM will translate this value into byte counter and
23238 * time interval used for this COS inside the device.
23240 uint32_t queue_id6_max_bw;
23241 /* The bandwidth value. */
23242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
23243 UINT32_C(0xfffffff)
23244 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
23246 /* The granularity of the value (bits or bytes). */
23247 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
23248 UINT32_C(0x10000000)
23249 /* Value is in bits. */
23250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
23251 (UINT32_C(0x0) << 28)
23252 /* Value is in bytes. */
23253 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
23254 (UINT32_C(0x1) << 28)
23255 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
23256 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
23257 /* bw_value_unit is 3 b */
23258 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
23259 UINT32_C(0xe0000000)
23260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
23262 /* Value is in Mb or MB (base 10). */
23263 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
23264 (UINT32_C(0x0) << 29)
23265 /* Value is in Kb or KB (base 10). */
23266 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
23267 (UINT32_C(0x2) << 29)
23268 /* Value is in bits or bytes. */
23269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
23270 (UINT32_C(0x4) << 29)
23271 /* Value is in Gb or GB (base 10). */
23272 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
23273 (UINT32_C(0x6) << 29)
23274 /* Value is in 1/100th of a percentage of total bandwidth. */
23275 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23276 (UINT32_C(0x1) << 29)
23278 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
23279 (UINT32_C(0x7) << 29)
23280 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
23281 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
23282 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23283 uint8_t queue_id6_tsa_assign;
23284 /* Strict Priority */
23285 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
23287 /* Enhanced Transmission Selection */
23288 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
23291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
23294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
23297 * Priority level for strict priority. Valid only when the
23298 * tsa_assign is 0 - Strict Priority (SP)
23299 * 0..7 - Valid values.
23300 * 8..255 - Reserved.
23302 uint8_t queue_id6_pri_lvl;
23304 * Weight used to allocate remaining BW for this COS after
23305 * servicing guaranteed bandwidths for all COS.
23307 uint8_t queue_id6_bw_weight;
23308 /* ID of CoS Queue 7. */
23311 * Minimum BW allocated to CoS Queue.
23312 * The HWRM will translate this value into byte counter and
23313 * time interval used for this COS inside the device.
23315 uint32_t queue_id7_min_bw;
23316 /* The bandwidth value. */
23317 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
23318 UINT32_C(0xfffffff)
23319 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
23321 /* The granularity of the value (bits or bytes). */
23322 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
23323 UINT32_C(0x10000000)
23324 /* Value is in bits. */
23325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
23326 (UINT32_C(0x0) << 28)
23327 /* Value is in bytes. */
23328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
23329 (UINT32_C(0x1) << 28)
23330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
23331 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
23332 /* bw_value_unit is 3 b */
23333 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
23334 UINT32_C(0xe0000000)
23335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
23337 /* Value is in Mb or MB (base 10). */
23338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
23339 (UINT32_C(0x0) << 29)
23340 /* Value is in Kb or KB (base 10). */
23341 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
23342 (UINT32_C(0x2) << 29)
23343 /* Value is in bits or bytes. */
23344 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
23345 (UINT32_C(0x4) << 29)
23346 /* Value is in Gb or GB (base 10). */
23347 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
23348 (UINT32_C(0x6) << 29)
23349 /* Value is in 1/100th of a percentage of total bandwidth. */
23350 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23351 (UINT32_C(0x1) << 29)
23353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
23354 (UINT32_C(0x7) << 29)
23355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
23356 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
23358 * Maximum BW allocated to CoS queue.
23359 * The HWRM will translate this value into byte counter and
23360 * time interval used for this COS inside the device.
23362 uint32_t queue_id7_max_bw;
23363 /* The bandwidth value. */
23364 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
23365 UINT32_C(0xfffffff)
23366 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
23368 /* The granularity of the value (bits or bytes). */
23369 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
23370 UINT32_C(0x10000000)
23371 /* Value is in bits. */
23372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
23373 (UINT32_C(0x0) << 28)
23374 /* Value is in bytes. */
23375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
23376 (UINT32_C(0x1) << 28)
23377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
23378 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
23379 /* bw_value_unit is 3 b */
23380 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
23381 UINT32_C(0xe0000000)
23382 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
23384 /* Value is in Mb or MB (base 10). */
23385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
23386 (UINT32_C(0x0) << 29)
23387 /* Value is in Kb or KB (base 10). */
23388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
23389 (UINT32_C(0x2) << 29)
23390 /* Value is in bits or bytes. */
23391 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
23392 (UINT32_C(0x4) << 29)
23393 /* Value is in Gb or GB (base 10). */
23394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
23395 (UINT32_C(0x6) << 29)
23396 /* Value is in 1/100th of a percentage of total bandwidth. */
23397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23398 (UINT32_C(0x1) << 29)
23400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
23401 (UINT32_C(0x7) << 29)
23402 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
23403 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
23404 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23405 uint8_t queue_id7_tsa_assign;
23406 /* Strict Priority */
23407 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
23409 /* Enhanced Transmission Selection */
23410 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
23413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
23416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
23419 * Priority level for strict priority. Valid only when the
23420 * tsa_assign is 0 - Strict Priority (SP)
23421 * 0..7 - Valid values.
23422 * 8..255 - Reserved.
23424 uint8_t queue_id7_pri_lvl;
23426 * Weight used to allocate remaining BW for this COS after
23427 * servicing guaranteed bandwidths for all COS.
23429 uint8_t queue_id7_bw_weight;
23430 uint8_t unused_2[4];
23432 * This field is used in Output records to indicate that the output
23433 * is completely written to RAM. This field should be read as '1'
23434 * to indicate that the output has been completely written.
23435 * When writing a command completion or response to an internal processor,
23436 * the order of writes has to be such that this field is written last.
23441 /*************************
23442 * hwrm_queue_cos2bw_cfg *
23443 *************************/
23446 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
23447 struct hwrm_queue_cos2bw_cfg_input {
23448 /* The HWRM command request type. */
23451 * The completion ring to send the completion event on. This should
23452 * be the NQ ID returned from the `nq_alloc` HWRM command.
23454 uint16_t cmpl_ring;
23456 * The sequence ID is used by the driver for tracking multiple
23457 * commands. This ID is treated as opaque data by the firmware and
23458 * the value is returned in the `hwrm_resp_hdr` upon completion.
23462 * The target ID of the command:
23463 * * 0x0-0xFFF8 - The function ID
23464 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23465 * * 0xFFFD - Reserved for user-space HWRM interface
23468 uint16_t target_id;
23470 * A physical address pointer pointing to a host buffer that the
23471 * command's response data will be written. This can be either a host
23472 * physical address (HPA) or a guest physical address (GPA) and must
23473 * point to a physically contiguous block of memory.
23475 uint64_t resp_addr;
23479 * If this bit is set to 1, then all queue_id0 related
23480 * parameters in this command are valid.
23482 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
23485 * If this bit is set to 1, then all queue_id1 related
23486 * parameters in this command are valid.
23488 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
23491 * If this bit is set to 1, then all queue_id2 related
23492 * parameters in this command are valid.
23494 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
23497 * If this bit is set to 1, then all queue_id3 related
23498 * parameters in this command are valid.
23500 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
23503 * If this bit is set to 1, then all queue_id4 related
23504 * parameters in this command are valid.
23506 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
23509 * If this bit is set to 1, then all queue_id5 related
23510 * parameters in this command are valid.
23512 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
23515 * If this bit is set to 1, then all queue_id6 related
23516 * parameters in this command are valid.
23518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
23521 * If this bit is set to 1, then all queue_id7 related
23522 * parameters in this command are valid.
23524 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
23527 * Port ID of port for which the table is being configured.
23528 * The HWRM needs to check whether this function is allowed
23529 * to configure TC BW assignment on this port.
23532 /* ID of CoS Queue 0. */
23536 * Minimum BW allocated to CoS Queue.
23537 * The HWRM will translate this value into byte counter and
23538 * time interval used for this COS inside the device.
23540 uint32_t queue_id0_min_bw;
23541 /* The bandwidth value. */
23542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
23543 UINT32_C(0xfffffff)
23544 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
23546 /* The granularity of the value (bits or bytes). */
23547 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
23548 UINT32_C(0x10000000)
23549 /* Value is in bits. */
23550 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
23551 (UINT32_C(0x0) << 28)
23552 /* Value is in bytes. */
23553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
23554 (UINT32_C(0x1) << 28)
23555 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
23556 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
23557 /* bw_value_unit is 3 b */
23558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
23559 UINT32_C(0xe0000000)
23560 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
23562 /* Value is in Mb or MB (base 10). */
23563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
23564 (UINT32_C(0x0) << 29)
23565 /* Value is in Kb or KB (base 10). */
23566 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
23567 (UINT32_C(0x2) << 29)
23568 /* Value is in bits or bytes. */
23569 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
23570 (UINT32_C(0x4) << 29)
23571 /* Value is in Gb or GB (base 10). */
23572 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
23573 (UINT32_C(0x6) << 29)
23574 /* Value is in 1/100th of a percentage of total bandwidth. */
23575 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23576 (UINT32_C(0x1) << 29)
23578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
23579 (UINT32_C(0x7) << 29)
23580 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
23581 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
23583 * Maximum BW allocated to CoS Queue.
23584 * The HWRM will translate this value into byte counter and
23585 * time interval used for this COS inside the device.
23587 uint32_t queue_id0_max_bw;
23588 /* The bandwidth value. */
23589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
23590 UINT32_C(0xfffffff)
23591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
23593 /* The granularity of the value (bits or bytes). */
23594 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
23595 UINT32_C(0x10000000)
23596 /* Value is in bits. */
23597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
23598 (UINT32_C(0x0) << 28)
23599 /* Value is in bytes. */
23600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
23601 (UINT32_C(0x1) << 28)
23602 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
23603 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
23604 /* bw_value_unit is 3 b */
23605 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
23606 UINT32_C(0xe0000000)
23607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
23609 /* Value is in Mb or MB (base 10). */
23610 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
23611 (UINT32_C(0x0) << 29)
23612 /* Value is in Kb or KB (base 10). */
23613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
23614 (UINT32_C(0x2) << 29)
23615 /* Value is in bits or bytes. */
23616 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
23617 (UINT32_C(0x4) << 29)
23618 /* Value is in Gb or GB (base 10). */
23619 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
23620 (UINT32_C(0x6) << 29)
23621 /* Value is in 1/100th of a percentage of total bandwidth. */
23622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23623 (UINT32_C(0x1) << 29)
23625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
23626 (UINT32_C(0x7) << 29)
23627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
23628 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
23629 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23630 uint8_t queue_id0_tsa_assign;
23631 /* Strict Priority */
23632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
23634 /* Enhanced Transmission Selection */
23635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
23638 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
23641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
23644 * Priority level for strict priority. Valid only when the
23645 * tsa_assign is 0 - Strict Priority (SP)
23646 * 0..7 - Valid values.
23647 * 8..255 - Reserved.
23649 uint8_t queue_id0_pri_lvl;
23651 * Weight used to allocate remaining BW for this COS after
23652 * servicing guaranteed bandwidths for all COS.
23654 uint8_t queue_id0_bw_weight;
23655 /* ID of CoS Queue 1. */
23658 * Minimum BW allocated to CoS Queue.
23659 * The HWRM will translate this value into byte counter and
23660 * time interval used for this COS inside the device.
23662 uint32_t queue_id1_min_bw;
23663 /* The bandwidth value. */
23664 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
23665 UINT32_C(0xfffffff)
23666 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
23668 /* The granularity of the value (bits or bytes). */
23669 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
23670 UINT32_C(0x10000000)
23671 /* Value is in bits. */
23672 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
23673 (UINT32_C(0x0) << 28)
23674 /* Value is in bytes. */
23675 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
23676 (UINT32_C(0x1) << 28)
23677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
23678 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
23679 /* bw_value_unit is 3 b */
23680 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
23681 UINT32_C(0xe0000000)
23682 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
23684 /* Value is in Mb or MB (base 10). */
23685 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
23686 (UINT32_C(0x0) << 29)
23687 /* Value is in Kb or KB (base 10). */
23688 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
23689 (UINT32_C(0x2) << 29)
23690 /* Value is in bits or bytes. */
23691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
23692 (UINT32_C(0x4) << 29)
23693 /* Value is in Gb or GB (base 10). */
23694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
23695 (UINT32_C(0x6) << 29)
23696 /* Value is in 1/100th of a percentage of total bandwidth. */
23697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23698 (UINT32_C(0x1) << 29)
23700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
23701 (UINT32_C(0x7) << 29)
23702 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
23703 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
23705 * Maximum BW allocated to CoS queue.
23706 * The HWRM will translate this value into byte counter and
23707 * time interval used for this COS inside the device.
23709 uint32_t queue_id1_max_bw;
23710 /* The bandwidth value. */
23711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
23712 UINT32_C(0xfffffff)
23713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
23715 /* The granularity of the value (bits or bytes). */
23716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
23717 UINT32_C(0x10000000)
23718 /* Value is in bits. */
23719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
23720 (UINT32_C(0x0) << 28)
23721 /* Value is in bytes. */
23722 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
23723 (UINT32_C(0x1) << 28)
23724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
23725 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
23726 /* bw_value_unit is 3 b */
23727 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
23728 UINT32_C(0xe0000000)
23729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
23731 /* Value is in Mb or MB (base 10). */
23732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
23733 (UINT32_C(0x0) << 29)
23734 /* Value is in Kb or KB (base 10). */
23735 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
23736 (UINT32_C(0x2) << 29)
23737 /* Value is in bits or bytes. */
23738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
23739 (UINT32_C(0x4) << 29)
23740 /* Value is in Gb or GB (base 10). */
23741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
23742 (UINT32_C(0x6) << 29)
23743 /* Value is in 1/100th of a percentage of total bandwidth. */
23744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23745 (UINT32_C(0x1) << 29)
23747 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
23748 (UINT32_C(0x7) << 29)
23749 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
23750 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
23751 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23752 uint8_t queue_id1_tsa_assign;
23753 /* Strict Priority */
23754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
23756 /* Enhanced Transmission Selection */
23757 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
23760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
23763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
23766 * Priority level for strict priority. Valid only when the
23767 * tsa_assign is 0 - Strict Priority (SP)
23768 * 0..7 - Valid values.
23769 * 8..255 - Reserved.
23771 uint8_t queue_id1_pri_lvl;
23773 * Weight used to allocate remaining BW for this COS after
23774 * servicing guaranteed bandwidths for all COS.
23776 uint8_t queue_id1_bw_weight;
23777 /* ID of CoS Queue 2. */
23780 * Minimum BW allocated to CoS Queue.
23781 * The HWRM will translate this value into byte counter and
23782 * time interval used for this COS inside the device.
23784 uint32_t queue_id2_min_bw;
23785 /* The bandwidth value. */
23786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
23787 UINT32_C(0xfffffff)
23788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
23790 /* The granularity of the value (bits or bytes). */
23791 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
23792 UINT32_C(0x10000000)
23793 /* Value is in bits. */
23794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
23795 (UINT32_C(0x0) << 28)
23796 /* Value is in bytes. */
23797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
23798 (UINT32_C(0x1) << 28)
23799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
23800 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
23801 /* bw_value_unit is 3 b */
23802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
23803 UINT32_C(0xe0000000)
23804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
23806 /* Value is in Mb or MB (base 10). */
23807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
23808 (UINT32_C(0x0) << 29)
23809 /* Value is in Kb or KB (base 10). */
23810 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
23811 (UINT32_C(0x2) << 29)
23812 /* Value is in bits or bytes. */
23813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
23814 (UINT32_C(0x4) << 29)
23815 /* Value is in Gb or GB (base 10). */
23816 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
23817 (UINT32_C(0x6) << 29)
23818 /* Value is in 1/100th of a percentage of total bandwidth. */
23819 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23820 (UINT32_C(0x1) << 29)
23822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
23823 (UINT32_C(0x7) << 29)
23824 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
23825 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
23827 * Maximum BW allocated to CoS queue.
23828 * The HWRM will translate this value into byte counter and
23829 * time interval used for this COS inside the device.
23831 uint32_t queue_id2_max_bw;
23832 /* The bandwidth value. */
23833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
23834 UINT32_C(0xfffffff)
23835 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
23837 /* The granularity of the value (bits or bytes). */
23838 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
23839 UINT32_C(0x10000000)
23840 /* Value is in bits. */
23841 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
23842 (UINT32_C(0x0) << 28)
23843 /* Value is in bytes. */
23844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
23845 (UINT32_C(0x1) << 28)
23846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
23847 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
23848 /* bw_value_unit is 3 b */
23849 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
23850 UINT32_C(0xe0000000)
23851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
23853 /* Value is in Mb or MB (base 10). */
23854 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
23855 (UINT32_C(0x0) << 29)
23856 /* Value is in Kb or KB (base 10). */
23857 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
23858 (UINT32_C(0x2) << 29)
23859 /* Value is in bits or bytes. */
23860 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
23861 (UINT32_C(0x4) << 29)
23862 /* Value is in Gb or GB (base 10). */
23863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
23864 (UINT32_C(0x6) << 29)
23865 /* Value is in 1/100th of a percentage of total bandwidth. */
23866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23867 (UINT32_C(0x1) << 29)
23869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
23870 (UINT32_C(0x7) << 29)
23871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
23872 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
23873 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23874 uint8_t queue_id2_tsa_assign;
23875 /* Strict Priority */
23876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
23878 /* Enhanced Transmission Selection */
23879 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
23882 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
23885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
23888 * Priority level for strict priority. Valid only when the
23889 * tsa_assign is 0 - Strict Priority (SP)
23890 * 0..7 - Valid values.
23891 * 8..255 - Reserved.
23893 uint8_t queue_id2_pri_lvl;
23895 * Weight used to allocate remaining BW for this COS after
23896 * servicing guaranteed bandwidths for all COS.
23898 uint8_t queue_id2_bw_weight;
23899 /* ID of CoS Queue 3. */
23902 * Minimum BW allocated to CoS Queue.
23903 * The HWRM will translate this value into byte counter and
23904 * time interval used for this COS inside the device.
23906 uint32_t queue_id3_min_bw;
23907 /* The bandwidth value. */
23908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
23909 UINT32_C(0xfffffff)
23910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
23912 /* The granularity of the value (bits or bytes). */
23913 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
23914 UINT32_C(0x10000000)
23915 /* Value is in bits. */
23916 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
23917 (UINT32_C(0x0) << 28)
23918 /* Value is in bytes. */
23919 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
23920 (UINT32_C(0x1) << 28)
23921 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
23922 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
23923 /* bw_value_unit is 3 b */
23924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
23925 UINT32_C(0xe0000000)
23926 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
23928 /* Value is in Mb or MB (base 10). */
23929 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
23930 (UINT32_C(0x0) << 29)
23931 /* Value is in Kb or KB (base 10). */
23932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
23933 (UINT32_C(0x2) << 29)
23934 /* Value is in bits or bytes. */
23935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
23936 (UINT32_C(0x4) << 29)
23937 /* Value is in Gb or GB (base 10). */
23938 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
23939 (UINT32_C(0x6) << 29)
23940 /* Value is in 1/100th of a percentage of total bandwidth. */
23941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
23942 (UINT32_C(0x1) << 29)
23944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
23945 (UINT32_C(0x7) << 29)
23946 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
23947 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
23949 * Maximum BW allocated to CoS queue.
23950 * The HWRM will translate this value into byte counter and
23951 * time interval used for this COS inside the device.
23953 uint32_t queue_id3_max_bw;
23954 /* The bandwidth value. */
23955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
23956 UINT32_C(0xfffffff)
23957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
23959 /* The granularity of the value (bits or bytes). */
23960 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
23961 UINT32_C(0x10000000)
23962 /* Value is in bits. */
23963 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
23964 (UINT32_C(0x0) << 28)
23965 /* Value is in bytes. */
23966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
23967 (UINT32_C(0x1) << 28)
23968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
23969 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
23970 /* bw_value_unit is 3 b */
23971 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
23972 UINT32_C(0xe0000000)
23973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
23975 /* Value is in Mb or MB (base 10). */
23976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
23977 (UINT32_C(0x0) << 29)
23978 /* Value is in Kb or KB (base 10). */
23979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
23980 (UINT32_C(0x2) << 29)
23981 /* Value is in bits or bytes. */
23982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
23983 (UINT32_C(0x4) << 29)
23984 /* Value is in Gb or GB (base 10). */
23985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
23986 (UINT32_C(0x6) << 29)
23987 /* Value is in 1/100th of a percentage of total bandwidth. */
23988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
23989 (UINT32_C(0x1) << 29)
23991 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
23992 (UINT32_C(0x7) << 29)
23993 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
23994 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
23995 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
23996 uint8_t queue_id3_tsa_assign;
23997 /* Strict Priority */
23998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
24000 /* Enhanced Transmission Selection */
24001 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
24004 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
24007 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
24010 * Priority level for strict priority. Valid only when the
24011 * tsa_assign is 0 - Strict Priority (SP)
24012 * 0..7 - Valid values.
24013 * 8..255 - Reserved.
24015 uint8_t queue_id3_pri_lvl;
24017 * Weight used to allocate remaining BW for this COS after
24018 * servicing guaranteed bandwidths for all COS.
24020 uint8_t queue_id3_bw_weight;
24021 /* ID of CoS Queue 4. */
24024 * Minimum BW allocated to CoS Queue.
24025 * The HWRM will translate this value into byte counter and
24026 * time interval used for this COS inside the device.
24028 uint32_t queue_id4_min_bw;
24029 /* The bandwidth value. */
24030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
24031 UINT32_C(0xfffffff)
24032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
24034 /* The granularity of the value (bits or bytes). */
24035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
24036 UINT32_C(0x10000000)
24037 /* Value is in bits. */
24038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
24039 (UINT32_C(0x0) << 28)
24040 /* Value is in bytes. */
24041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
24042 (UINT32_C(0x1) << 28)
24043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
24044 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
24045 /* bw_value_unit is 3 b */
24046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
24047 UINT32_C(0xe0000000)
24048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
24050 /* Value is in Mb or MB (base 10). */
24051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
24052 (UINT32_C(0x0) << 29)
24053 /* Value is in Kb or KB (base 10). */
24054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
24055 (UINT32_C(0x2) << 29)
24056 /* Value is in bits or bytes. */
24057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
24058 (UINT32_C(0x4) << 29)
24059 /* Value is in Gb or GB (base 10). */
24060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
24061 (UINT32_C(0x6) << 29)
24062 /* Value is in 1/100th of a percentage of total bandwidth. */
24063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24064 (UINT32_C(0x1) << 29)
24066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
24067 (UINT32_C(0x7) << 29)
24068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
24069 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
24071 * Maximum BW allocated to CoS queue.
24072 * The HWRM will translate this value into byte counter and
24073 * time interval used for this COS inside the device.
24075 uint32_t queue_id4_max_bw;
24076 /* The bandwidth value. */
24077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
24078 UINT32_C(0xfffffff)
24079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
24081 /* The granularity of the value (bits or bytes). */
24082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
24083 UINT32_C(0x10000000)
24084 /* Value is in bits. */
24085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
24086 (UINT32_C(0x0) << 28)
24087 /* Value is in bytes. */
24088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
24089 (UINT32_C(0x1) << 28)
24090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
24091 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
24092 /* bw_value_unit is 3 b */
24093 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
24094 UINT32_C(0xe0000000)
24095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
24097 /* Value is in Mb or MB (base 10). */
24098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
24099 (UINT32_C(0x0) << 29)
24100 /* Value is in Kb or KB (base 10). */
24101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
24102 (UINT32_C(0x2) << 29)
24103 /* Value is in bits or bytes. */
24104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
24105 (UINT32_C(0x4) << 29)
24106 /* Value is in Gb or GB (base 10). */
24107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
24108 (UINT32_C(0x6) << 29)
24109 /* Value is in 1/100th of a percentage of total bandwidth. */
24110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24111 (UINT32_C(0x1) << 29)
24113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
24114 (UINT32_C(0x7) << 29)
24115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
24116 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
24117 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24118 uint8_t queue_id4_tsa_assign;
24119 /* Strict Priority */
24120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
24122 /* Enhanced Transmission Selection */
24123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
24126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
24129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
24132 * Priority level for strict priority. Valid only when the
24133 * tsa_assign is 0 - Strict Priority (SP)
24134 * 0..7 - Valid values.
24135 * 8..255 - Reserved.
24137 uint8_t queue_id4_pri_lvl;
24139 * Weight used to allocate remaining BW for this COS after
24140 * servicing guaranteed bandwidths for all COS.
24142 uint8_t queue_id4_bw_weight;
24143 /* ID of CoS Queue 5. */
24146 * Minimum BW allocated to CoS Queue.
24147 * The HWRM will translate this value into byte counter and
24148 * time interval used for this COS inside the device.
24150 uint32_t queue_id5_min_bw;
24151 /* The bandwidth value. */
24152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
24153 UINT32_C(0xfffffff)
24154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
24156 /* The granularity of the value (bits or bytes). */
24157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
24158 UINT32_C(0x10000000)
24159 /* Value is in bits. */
24160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
24161 (UINT32_C(0x0) << 28)
24162 /* Value is in bytes. */
24163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
24164 (UINT32_C(0x1) << 28)
24165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
24166 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
24167 /* bw_value_unit is 3 b */
24168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
24169 UINT32_C(0xe0000000)
24170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
24172 /* Value is in Mb or MB (base 10). */
24173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
24174 (UINT32_C(0x0) << 29)
24175 /* Value is in Kb or KB (base 10). */
24176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
24177 (UINT32_C(0x2) << 29)
24178 /* Value is in bits or bytes. */
24179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
24180 (UINT32_C(0x4) << 29)
24181 /* Value is in Gb or GB (base 10). */
24182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
24183 (UINT32_C(0x6) << 29)
24184 /* Value is in 1/100th of a percentage of total bandwidth. */
24185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24186 (UINT32_C(0x1) << 29)
24188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
24189 (UINT32_C(0x7) << 29)
24190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
24191 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
24193 * Maximum BW allocated to CoS queue.
24194 * The HWRM will translate this value into byte counter and
24195 * time interval used for this COS inside the device.
24197 uint32_t queue_id5_max_bw;
24198 /* The bandwidth value. */
24199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
24200 UINT32_C(0xfffffff)
24201 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
24203 /* The granularity of the value (bits or bytes). */
24204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
24205 UINT32_C(0x10000000)
24206 /* Value is in bits. */
24207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
24208 (UINT32_C(0x0) << 28)
24209 /* Value is in bytes. */
24210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
24211 (UINT32_C(0x1) << 28)
24212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
24213 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
24214 /* bw_value_unit is 3 b */
24215 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
24216 UINT32_C(0xe0000000)
24217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
24219 /* Value is in Mb or MB (base 10). */
24220 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
24221 (UINT32_C(0x0) << 29)
24222 /* Value is in Kb or KB (base 10). */
24223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
24224 (UINT32_C(0x2) << 29)
24225 /* Value is in bits or bytes. */
24226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
24227 (UINT32_C(0x4) << 29)
24228 /* Value is in Gb or GB (base 10). */
24229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
24230 (UINT32_C(0x6) << 29)
24231 /* Value is in 1/100th of a percentage of total bandwidth. */
24232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24233 (UINT32_C(0x1) << 29)
24235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
24236 (UINT32_C(0x7) << 29)
24237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
24238 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
24239 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24240 uint8_t queue_id5_tsa_assign;
24241 /* Strict Priority */
24242 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
24244 /* Enhanced Transmission Selection */
24245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
24248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
24251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
24254 * Priority level for strict priority. Valid only when the
24255 * tsa_assign is 0 - Strict Priority (SP)
24256 * 0..7 - Valid values.
24257 * 8..255 - Reserved.
24259 uint8_t queue_id5_pri_lvl;
24261 * Weight used to allocate remaining BW for this COS after
24262 * servicing guaranteed bandwidths for all COS.
24264 uint8_t queue_id5_bw_weight;
24265 /* ID of CoS Queue 6. */
24268 * Minimum BW allocated to CoS Queue.
24269 * The HWRM will translate this value into byte counter and
24270 * time interval used for this COS inside the device.
24272 uint32_t queue_id6_min_bw;
24273 /* The bandwidth value. */
24274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
24275 UINT32_C(0xfffffff)
24276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
24278 /* The granularity of the value (bits or bytes). */
24279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
24280 UINT32_C(0x10000000)
24281 /* Value is in bits. */
24282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
24283 (UINT32_C(0x0) << 28)
24284 /* Value is in bytes. */
24285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
24286 (UINT32_C(0x1) << 28)
24287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
24288 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
24289 /* bw_value_unit is 3 b */
24290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
24291 UINT32_C(0xe0000000)
24292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
24294 /* Value is in Mb or MB (base 10). */
24295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
24296 (UINT32_C(0x0) << 29)
24297 /* Value is in Kb or KB (base 10). */
24298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
24299 (UINT32_C(0x2) << 29)
24300 /* Value is in bits or bytes. */
24301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
24302 (UINT32_C(0x4) << 29)
24303 /* Value is in Gb or GB (base 10). */
24304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
24305 (UINT32_C(0x6) << 29)
24306 /* Value is in 1/100th of a percentage of total bandwidth. */
24307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24308 (UINT32_C(0x1) << 29)
24310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
24311 (UINT32_C(0x7) << 29)
24312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
24313 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
24315 * Maximum BW allocated to CoS queue.
24316 * The HWRM will translate this value into byte counter and
24317 * time interval used for this COS inside the device.
24319 uint32_t queue_id6_max_bw;
24320 /* The bandwidth value. */
24321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
24322 UINT32_C(0xfffffff)
24323 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
24325 /* The granularity of the value (bits or bytes). */
24326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
24327 UINT32_C(0x10000000)
24328 /* Value is in bits. */
24329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
24330 (UINT32_C(0x0) << 28)
24331 /* Value is in bytes. */
24332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
24333 (UINT32_C(0x1) << 28)
24334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
24335 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
24336 /* bw_value_unit is 3 b */
24337 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
24338 UINT32_C(0xe0000000)
24339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
24341 /* Value is in Mb or MB (base 10). */
24342 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
24343 (UINT32_C(0x0) << 29)
24344 /* Value is in Kb or KB (base 10). */
24345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
24346 (UINT32_C(0x2) << 29)
24347 /* Value is in bits or bytes. */
24348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
24349 (UINT32_C(0x4) << 29)
24350 /* Value is in Gb or GB (base 10). */
24351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
24352 (UINT32_C(0x6) << 29)
24353 /* Value is in 1/100th of a percentage of total bandwidth. */
24354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24355 (UINT32_C(0x1) << 29)
24357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
24358 (UINT32_C(0x7) << 29)
24359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
24360 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
24361 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24362 uint8_t queue_id6_tsa_assign;
24363 /* Strict Priority */
24364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
24366 /* Enhanced Transmission Selection */
24367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
24370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
24373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
24376 * Priority level for strict priority. Valid only when the
24377 * tsa_assign is 0 - Strict Priority (SP)
24378 * 0..7 - Valid values.
24379 * 8..255 - Reserved.
24381 uint8_t queue_id6_pri_lvl;
24383 * Weight used to allocate remaining BW for this COS after
24384 * servicing guaranteed bandwidths for all COS.
24386 uint8_t queue_id6_bw_weight;
24387 /* ID of CoS Queue 7. */
24390 * Minimum BW allocated to CoS Queue.
24391 * The HWRM will translate this value into byte counter and
24392 * time interval used for this COS inside the device.
24394 uint32_t queue_id7_min_bw;
24395 /* The bandwidth value. */
24396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
24397 UINT32_C(0xfffffff)
24398 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
24400 /* The granularity of the value (bits or bytes). */
24401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
24402 UINT32_C(0x10000000)
24403 /* Value is in bits. */
24404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
24405 (UINT32_C(0x0) << 28)
24406 /* Value is in bytes. */
24407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
24408 (UINT32_C(0x1) << 28)
24409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
24410 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
24411 /* bw_value_unit is 3 b */
24412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
24413 UINT32_C(0xe0000000)
24414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
24416 /* Value is in Mb or MB (base 10). */
24417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
24418 (UINT32_C(0x0) << 29)
24419 /* Value is in Kb or KB (base 10). */
24420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
24421 (UINT32_C(0x2) << 29)
24422 /* Value is in bits or bytes. */
24423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
24424 (UINT32_C(0x4) << 29)
24425 /* Value is in Gb or GB (base 10). */
24426 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
24427 (UINT32_C(0x6) << 29)
24428 /* Value is in 1/100th of a percentage of total bandwidth. */
24429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
24430 (UINT32_C(0x1) << 29)
24432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
24433 (UINT32_C(0x7) << 29)
24434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
24435 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
24437 * Maximum BW allocated to CoS queue.
24438 * The HWRM will translate this value into byte counter and
24439 * time interval used for this COS inside the device.
24441 uint32_t queue_id7_max_bw;
24442 /* The bandwidth value. */
24443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
24444 UINT32_C(0xfffffff)
24445 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
24447 /* The granularity of the value (bits or bytes). */
24448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
24449 UINT32_C(0x10000000)
24450 /* Value is in bits. */
24451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
24452 (UINT32_C(0x0) << 28)
24453 /* Value is in bytes. */
24454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
24455 (UINT32_C(0x1) << 28)
24456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
24457 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
24458 /* bw_value_unit is 3 b */
24459 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
24460 UINT32_C(0xe0000000)
24461 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
24463 /* Value is in Mb or MB (base 10). */
24464 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
24465 (UINT32_C(0x0) << 29)
24466 /* Value is in Kb or KB (base 10). */
24467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
24468 (UINT32_C(0x2) << 29)
24469 /* Value is in bits or bytes. */
24470 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
24471 (UINT32_C(0x4) << 29)
24472 /* Value is in Gb or GB (base 10). */
24473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
24474 (UINT32_C(0x6) << 29)
24475 /* Value is in 1/100th of a percentage of total bandwidth. */
24476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
24477 (UINT32_C(0x1) << 29)
24479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
24480 (UINT32_C(0x7) << 29)
24481 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
24482 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
24483 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
24484 uint8_t queue_id7_tsa_assign;
24485 /* Strict Priority */
24486 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
24488 /* Enhanced Transmission Selection */
24489 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
24492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
24495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
24498 * Priority level for strict priority. Valid only when the
24499 * tsa_assign is 0 - Strict Priority (SP)
24500 * 0..7 - Valid values.
24501 * 8..255 - Reserved.
24503 uint8_t queue_id7_pri_lvl;
24505 * Weight used to allocate remaining BW for this COS after
24506 * servicing guaranteed bandwidths for all COS.
24508 uint8_t queue_id7_bw_weight;
24509 uint8_t unused_1[5];
24512 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
24513 struct hwrm_queue_cos2bw_cfg_output {
24514 /* The specific error status for the command. */
24515 uint16_t error_code;
24516 /* The HWRM command request type. */
24518 /* The sequence ID from the original command. */
24520 /* The length of the response data in number of bytes. */
24522 uint8_t unused_0[7];
24524 * This field is used in Output records to indicate that the output
24525 * is completely written to RAM. This field should be read as '1'
24526 * to indicate that the output has been completely written.
24527 * When writing a command completion or response to an internal processor,
24528 * the order of writes has to be such that this field is written last.
24533 /*************************
24534 * hwrm_queue_dscp_qcaps *
24535 *************************/
24538 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
24539 struct hwrm_queue_dscp_qcaps_input {
24540 /* The HWRM command request type. */
24543 * The completion ring to send the completion event on. This should
24544 * be the NQ ID returned from the `nq_alloc` HWRM command.
24546 uint16_t cmpl_ring;
24548 * The sequence ID is used by the driver for tracking multiple
24549 * commands. This ID is treated as opaque data by the firmware and
24550 * the value is returned in the `hwrm_resp_hdr` upon completion.
24554 * The target ID of the command:
24555 * * 0x0-0xFFF8 - The function ID
24556 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24557 * * 0xFFFD - Reserved for user-space HWRM interface
24560 uint16_t target_id;
24562 * A physical address pointer pointing to a host buffer that the
24563 * command's response data will be written. This can be either a host
24564 * physical address (HPA) or a guest physical address (GPA) and must
24565 * point to a physically contiguous block of memory.
24567 uint64_t resp_addr;
24569 * Port ID of port for which the table is being configured.
24570 * The HWRM needs to check whether this function is allowed
24571 * to configure pri2cos mapping on this port.
24574 uint8_t unused_0[7];
24577 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
24578 struct hwrm_queue_dscp_qcaps_output {
24579 /* The specific error status for the command. */
24580 uint16_t error_code;
24581 /* The HWRM command request type. */
24583 /* The sequence ID from the original command. */
24585 /* The length of the response data in number of bytes. */
24587 /* The number of bits provided by the hardware for the DSCP value. */
24588 uint8_t num_dscp_bits;
24590 /* Max number of DSCP-MASK-PRI entries supported. */
24591 uint16_t max_entries;
24592 uint8_t unused_1[3];
24594 * This field is used in Output records to indicate that the output
24595 * is completely written to RAM. This field should be read as '1'
24596 * to indicate that the output has been completely written.
24597 * When writing a command completion or response to an internal processor,
24598 * the order of writes has to be such that this field is written last.
24603 /****************************
24604 * hwrm_queue_dscp2pri_qcfg *
24605 ****************************/
24608 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
24609 struct hwrm_queue_dscp2pri_qcfg_input {
24610 /* The HWRM command request type. */
24613 * The completion ring to send the completion event on. This should
24614 * be the NQ ID returned from the `nq_alloc` HWRM command.
24616 uint16_t cmpl_ring;
24618 * The sequence ID is used by the driver for tracking multiple
24619 * commands. This ID is treated as opaque data by the firmware and
24620 * the value is returned in the `hwrm_resp_hdr` upon completion.
24624 * The target ID of the command:
24625 * * 0x0-0xFFF8 - The function ID
24626 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24627 * * 0xFFFD - Reserved for user-space HWRM interface
24630 uint16_t target_id;
24632 * A physical address pointer pointing to a host buffer that the
24633 * command's response data will be written. This can be either a host
24634 * physical address (HPA) or a guest physical address (GPA) and must
24635 * point to a physically contiguous block of memory.
24637 uint64_t resp_addr;
24639 * This is the host address where the 24-bits DSCP-MASK-PRI
24640 * tuple(s) will be copied to.
24642 uint64_t dest_data_addr;
24644 * Port ID of port for which the table is being configured.
24645 * The HWRM needs to check whether this function is allowed
24646 * to configure pri2cos mapping on this port.
24650 /* Size of the buffer pointed to by dest_data_addr. */
24651 uint16_t dest_data_buffer_size;
24652 uint8_t unused_1[4];
24655 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
24656 struct hwrm_queue_dscp2pri_qcfg_output {
24657 /* The specific error status for the command. */
24658 uint16_t error_code;
24659 /* The HWRM command request type. */
24661 /* The sequence ID from the original command. */
24663 /* The length of the response data in number of bytes. */
24666 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
24667 * by the dest_data_addr.
24669 uint16_t entry_cnt;
24671 * This is the default PRI which un-initialized DSCP values are
24674 uint8_t default_pri;
24675 uint8_t unused_0[4];
24677 * This field is used in Output records to indicate that the output
24678 * is completely written to RAM. This field should be read as '1'
24679 * to indicate that the output has been completely written.
24680 * When writing a command completion or response to an internal processor,
24681 * the order of writes has to be such that this field is written last.
24686 /***************************
24687 * hwrm_queue_dscp2pri_cfg *
24688 ***************************/
24691 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
24692 struct hwrm_queue_dscp2pri_cfg_input {
24693 /* The HWRM command request type. */
24696 * The completion ring to send the completion event on. This should
24697 * be the NQ ID returned from the `nq_alloc` HWRM command.
24699 uint16_t cmpl_ring;
24701 * The sequence ID is used by the driver for tracking multiple
24702 * commands. This ID is treated as opaque data by the firmware and
24703 * the value is returned in the `hwrm_resp_hdr` upon completion.
24707 * The target ID of the command:
24708 * * 0x0-0xFFF8 - The function ID
24709 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24710 * * 0xFFFD - Reserved for user-space HWRM interface
24713 uint16_t target_id;
24715 * A physical address pointer pointing to a host buffer that the
24716 * command's response data will be written. This can be either a host
24717 * physical address (HPA) or a guest physical address (GPA) and must
24718 * point to a physically contiguous block of memory.
24720 uint64_t resp_addr;
24722 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
24723 * will be copied from.
24725 uint64_t src_data_addr;
24727 /* use_hw_default_pri is 1 b */
24728 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
24732 * This bit must be '1' for the default_pri field to be
24735 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
24738 * Port ID of port for which the table is being configured.
24739 * The HWRM needs to check whether this function is allowed
24740 * to configure pri2cos mapping on this port.
24744 * This is the default PRI which un-initialized DSCP values will be
24747 uint8_t default_pri;
24749 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
24750 * to by src_data_addr.
24752 uint16_t entry_cnt;
24753 uint8_t unused_0[4];
24756 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
24757 struct hwrm_queue_dscp2pri_cfg_output {
24758 /* The specific error status for the command. */
24759 uint16_t error_code;
24760 /* The HWRM command request type. */
24762 /* The sequence ID from the original command. */
24764 /* The length of the response data in number of bytes. */
24766 uint8_t unused_0[7];
24768 * This field is used in Output records to indicate that the output
24769 * is completely written to RAM. This field should be read as '1'
24770 * to indicate that the output has been completely written.
24771 * When writing a command completion or response to an internal processor,
24772 * the order of writes has to be such that this field is written last.
24777 /*************************
24778 * hwrm_queue_mpls_qcaps *
24779 *************************/
24782 /* hwrm_queue_mpls_qcaps_input (size:192b/24B) */
24783 struct hwrm_queue_mpls_qcaps_input {
24784 /* The HWRM command request type. */
24787 * The completion ring to send the completion event on. This should
24788 * be the NQ ID returned from the `nq_alloc` HWRM command.
24790 uint16_t cmpl_ring;
24792 * The sequence ID is used by the driver for tracking multiple
24793 * commands. This ID is treated as opaque data by the firmware and
24794 * the value is returned in the `hwrm_resp_hdr` upon completion.
24798 * The target ID of the command:
24799 * * 0x0-0xFFF8 - The function ID
24800 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24801 * * 0xFFFD - Reserved for user-space HWRM interface
24804 uint16_t target_id;
24806 * A physical address pointer pointing to a host buffer that the
24807 * command's response data will be written. This can be either a host
24808 * physical address (HPA) or a guest physical address (GPA) and must
24809 * point to a physically contiguous block of memory.
24811 uint64_t resp_addr;
24813 * Port ID of port for which the table is being configured.
24814 * The HWRM needs to check whether this function is allowed
24815 * to configure MPLS TC(EXP) to pri mapping on this port.
24818 uint8_t unused_0[7];
24821 /* hwrm_queue_mpls_qcaps_output (size:128b/16B) */
24822 struct hwrm_queue_mpls_qcaps_output {
24823 /* The specific error status for the command. */
24824 uint16_t error_code;
24825 /* The HWRM command request type. */
24827 /* The sequence ID from the original command. */
24829 /* The length of the response data in number of bytes. */
24832 * Bitmask indicating which queues can be configured by the
24833 * hwrm_queue_mplstc2pri_cfg command.
24835 * Each bit represents a specific pri where bit 0 represents
24836 * pri 0 and bit 7 represents pri 7.
24837 * # A value of 0 indicates that the pri is not configurable
24838 * by the hwrm_queue_mplstc2pri_cfg command.
24839 * # A value of 1 indicates that the pri is configurable.
24840 * # A hwrm_queue_mplstc2pri_cfg command shall return error when
24841 * trying to configure a pri that is not configurable.
24843 uint8_t queue_mplstc2pri_cfg_allowed;
24845 * This is the default PRI which un-initialized MPLS values will be
24848 uint8_t hw_default_pri;
24849 uint8_t unused_0[5];
24851 * This field is used in Output records to indicate that the output
24852 * is completely written to RAM. This field should be read as '1'
24853 * to indicate that the output has been completely written.
24854 * When writing a command completion or response to an internal processor,
24855 * the order of writes has to be such that this field is written last.
24860 /******************************
24861 * hwrm_queue_mplstc2pri_qcfg *
24862 ******************************/
24865 /* hwrm_queue_mplstc2pri_qcfg_input (size:192b/24B) */
24866 struct hwrm_queue_mplstc2pri_qcfg_input {
24867 /* The HWRM command request type. */
24870 * The completion ring to send the completion event on. This should
24871 * be the NQ ID returned from the `nq_alloc` HWRM command.
24873 uint16_t cmpl_ring;
24875 * The sequence ID is used by the driver for tracking multiple
24876 * commands. This ID is treated as opaque data by the firmware and
24877 * the value is returned in the `hwrm_resp_hdr` upon completion.
24881 * The target ID of the command:
24882 * * 0x0-0xFFF8 - The function ID
24883 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24884 * * 0xFFFD - Reserved for user-space HWRM interface
24887 uint16_t target_id;
24889 * A physical address pointer pointing to a host buffer that the
24890 * command's response data will be written. This can be either a host
24891 * physical address (HPA) or a guest physical address (GPA) and must
24892 * point to a physically contiguous block of memory.
24894 uint64_t resp_addr;
24896 * Port ID of port for which the table is being configured.
24897 * The HWRM needs to check whether this function is allowed
24898 * to configure MPLS TC(EXP) to pri mapping on this port.
24901 uint8_t unused_0[7];
24904 /* hwrm_queue_mplstc2pri_qcfg_output (size:192b/24B) */
24905 struct hwrm_queue_mplstc2pri_qcfg_output {
24906 /* The specific error status for the command. */
24907 uint16_t error_code;
24908 /* The HWRM command request type. */
24910 /* The sequence ID from the original command. */
24912 /* The length of the response data in number of bytes. */
24915 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
24916 * before traffic has started.
24917 * A value of 0xff indicates that no pri is assigned to the
24920 uint8_t tc0_pri_queue_id;
24922 * pri assigned to MPLS TC(EXP) 1. This value can only be changed
24923 * before traffic has started.
24924 * A value of 0xff indicates that no pri is assigned to the
24927 uint8_t tc1_pri_queue_id;
24929 * pri assigned to MPLS TC(EXP) 2. This value can only be changed
24930 * before traffic has started.
24931 * A value of 0xff indicates that no pri is assigned to the
24934 uint8_t tc2_pri_queue_id;
24936 * pri assigned to MPLS TC(EXP) 3. This value can only be changed
24937 * before traffic has started.
24938 * A value of 0xff indicates that no pri is assigned to the
24941 uint8_t tc3_pri_queue_id;
24943 * pri assigned to MPLS TC(EXP) 4. This value can only be changed
24944 * before traffic has started.
24945 * A value of 0xff indicates that no pri is assigned to the
24948 uint8_t tc4_pri_queue_id;
24950 * pri assigned to MPLS TC(EXP) 5. This value can only be changed
24951 * before traffic has started.
24952 * A value of 0xff indicates that no pri is assigned to the
24955 uint8_t tc5_pri_queue_id;
24957 * pri assigned to MPLS TC(EXP) 6. This value can only
24958 * be changed before traffic has started.
24959 * A value of 0xff indicates that no pri is assigned to the
24962 uint8_t tc6_pri_queue_id;
24964 * pri assigned to MPLS TC(EXP) 7. This value can only
24965 * be changed before traffic has started.
24966 * A value of 0xff indicates that no pri is assigned to the
24969 uint8_t tc7_pri_queue_id;
24970 uint8_t unused_0[7];
24972 * This field is used in Output records to indicate that the output
24973 * is completely written to RAM. This field should be read as '1'
24974 * to indicate that the output has been completely written.
24975 * When writing a command completion or response to an internal processor,
24976 * the order of writes has to be such that this field is written last.
24981 /*****************************
24982 * hwrm_queue_mplstc2pri_cfg *
24983 *****************************/
24986 /* hwrm_queue_mplstc2pri_cfg_input (size:256b/32B) */
24987 struct hwrm_queue_mplstc2pri_cfg_input {
24988 /* The HWRM command request type. */
24991 * The completion ring to send the completion event on. This should
24992 * be the NQ ID returned from the `nq_alloc` HWRM command.
24994 uint16_t cmpl_ring;
24996 * The sequence ID is used by the driver for tracking multiple
24997 * commands. This ID is treated as opaque data by the firmware and
24998 * the value is returned in the `hwrm_resp_hdr` upon completion.
25002 * The target ID of the command:
25003 * * 0x0-0xFFF8 - The function ID
25004 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25005 * * 0xFFFD - Reserved for user-space HWRM interface
25008 uint16_t target_id;
25010 * A physical address pointer pointing to a host buffer that the
25011 * command's response data will be written. This can be either a host
25012 * physical address (HPA) or a guest physical address (GPA) and must
25013 * point to a physically contiguous block of memory.
25015 uint64_t resp_addr;
25018 * This bit must be '1' for the mplstc0_pri_queue_id field to be
25021 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \
25024 * This bit must be '1' for the mplstc1_pri_queue_id field to be
25027 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \
25030 * This bit must be '1' for the mplstc2_pri_queue_id field to be
25033 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \
25036 * This bit must be '1' for the mplstc3_pri_queue_id field to be
25039 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \
25042 * This bit must be '1' for the mplstc4_pri_queue_id field to be
25045 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \
25048 * This bit must be '1' for the mplstc5_pri_queue_id field to be
25051 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \
25054 * This bit must be '1' for the mplstc6_pri_queue_id field to be
25057 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \
25060 * This bit must be '1' for the mplstc7_pri_queue_id field to be
25063 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \
25066 * Port ID of port for which the table is being configured.
25067 * The HWRM needs to check whether this function is allowed
25068 * to configure MPLS TC(EXP)to pri mapping on this port.
25071 uint8_t unused_0[3];
25073 * pri assigned to MPLS TC(EXP) 0. This value can only
25074 * be changed before traffic has started.
25076 uint8_t tc0_pri_queue_id;
25078 * pri assigned to MPLS TC(EXP) 1. This value can only
25079 * be changed before traffic has started.
25081 uint8_t tc1_pri_queue_id;
25083 * pri assigned to MPLS TC(EXP) 2 This value can only
25084 * be changed before traffic has started.
25086 uint8_t tc2_pri_queue_id;
25088 * pri assigned to MPLS TC(EXP) 3. This value can only
25089 * be changed before traffic has started.
25091 uint8_t tc3_pri_queue_id;
25093 * pri assigned to MPLS TC(EXP) 4. This value can only
25094 * be changed before traffic has started.
25096 uint8_t tc4_pri_queue_id;
25098 * pri assigned to MPLS TC(EXP) 5. This value can only
25099 * be changed before traffic has started.
25101 uint8_t tc5_pri_queue_id;
25103 * pri assigned to MPLS TC(EXP) 6. This value can only
25104 * be changed before traffic has started.
25106 uint8_t tc6_pri_queue_id;
25108 * pri assigned to MPLS TC(EXP) 7. This value can only
25109 * be changed before traffic has started.
25111 uint8_t tc7_pri_queue_id;
25114 /* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */
25115 struct hwrm_queue_mplstc2pri_cfg_output {
25116 /* The specific error status for the command. */
25117 uint16_t error_code;
25118 /* The HWRM command request type. */
25120 /* The sequence ID from the original command. */
25122 /* The length of the response data in number of bytes. */
25124 uint8_t unused_0[7];
25126 * This field is used in Output records to indicate that the output
25127 * is completely written to RAM. This field should be read as '1'
25128 * to indicate that the output has been completely written.
25129 * When writing a command completion or response to an internal processor,
25130 * the order of writes has to be such that this field is written last.
25135 /*******************
25136 * hwrm_vnic_alloc *
25137 *******************/
25140 /* hwrm_vnic_alloc_input (size:192b/24B) */
25141 struct hwrm_vnic_alloc_input {
25142 /* The HWRM command request type. */
25145 * The completion ring to send the completion event on. This should
25146 * be the NQ ID returned from the `nq_alloc` HWRM command.
25148 uint16_t cmpl_ring;
25150 * The sequence ID is used by the driver for tracking multiple
25151 * commands. This ID is treated as opaque data by the firmware and
25152 * the value is returned in the `hwrm_resp_hdr` upon completion.
25156 * The target ID of the command:
25157 * * 0x0-0xFFF8 - The function ID
25158 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25159 * * 0xFFFD - Reserved for user-space HWRM interface
25162 uint16_t target_id;
25164 * A physical address pointer pointing to a host buffer that the
25165 * command's response data will be written. This can be either a host
25166 * physical address (HPA) or a guest physical address (GPA) and must
25167 * point to a physically contiguous block of memory.
25169 uint64_t resp_addr;
25172 * When this bit is '1', this VNIC is requested to
25173 * be the default VNIC for this function.
25175 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
25176 uint8_t unused_0[4];
25179 /* hwrm_vnic_alloc_output (size:128b/16B) */
25180 struct hwrm_vnic_alloc_output {
25181 /* The specific error status for the command. */
25182 uint16_t error_code;
25183 /* The HWRM command request type. */
25185 /* The sequence ID from the original command. */
25187 /* The length of the response data in number of bytes. */
25189 /* Logical vnic ID */
25191 uint8_t unused_0[3];
25193 * This field is used in Output records to indicate that the output
25194 * is completely written to RAM. This field should be read as '1'
25195 * to indicate that the output has been completely written.
25196 * When writing a command completion or response to an internal processor,
25197 * the order of writes has to be such that this field is written last.
25202 /******************
25204 ******************/
25207 /* hwrm_vnic_free_input (size:192b/24B) */
25208 struct hwrm_vnic_free_input {
25209 /* The HWRM command request type. */
25212 * The completion ring to send the completion event on. This should
25213 * be the NQ ID returned from the `nq_alloc` HWRM command.
25215 uint16_t cmpl_ring;
25217 * The sequence ID is used by the driver for tracking multiple
25218 * commands. This ID is treated as opaque data by the firmware and
25219 * the value is returned in the `hwrm_resp_hdr` upon completion.
25223 * The target ID of the command:
25224 * * 0x0-0xFFF8 - The function ID
25225 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25226 * * 0xFFFD - Reserved for user-space HWRM interface
25229 uint16_t target_id;
25231 * A physical address pointer pointing to a host buffer that the
25232 * command's response data will be written. This can be either a host
25233 * physical address (HPA) or a guest physical address (GPA) and must
25234 * point to a physically contiguous block of memory.
25236 uint64_t resp_addr;
25237 /* Logical vnic ID */
25239 uint8_t unused_0[4];
25242 /* hwrm_vnic_free_output (size:128b/16B) */
25243 struct hwrm_vnic_free_output {
25244 /* The specific error status for the command. */
25245 uint16_t error_code;
25246 /* The HWRM command request type. */
25248 /* The sequence ID from the original command. */
25250 /* The length of the response data in number of bytes. */
25252 uint8_t unused_0[7];
25254 * This field is used in Output records to indicate that the output
25255 * is completely written to RAM. This field should be read as '1'
25256 * to indicate that the output has been completely written.
25257 * When writing a command completion or response to an internal processor,
25258 * the order of writes has to be such that this field is written last.
25268 /* hwrm_vnic_cfg_input (size:384b/48B) */
25269 struct hwrm_vnic_cfg_input {
25270 /* The HWRM command request type. */
25273 * The completion ring to send the completion event on. This should
25274 * be the NQ ID returned from the `nq_alloc` HWRM command.
25276 uint16_t cmpl_ring;
25278 * The sequence ID is used by the driver for tracking multiple
25279 * commands. This ID is treated as opaque data by the firmware and
25280 * the value is returned in the `hwrm_resp_hdr` upon completion.
25284 * The target ID of the command:
25285 * * 0x0-0xFFF8 - The function ID
25286 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25287 * * 0xFFFD - Reserved for user-space HWRM interface
25290 uint16_t target_id;
25292 * A physical address pointer pointing to a host buffer that the
25293 * command's response data will be written. This can be either a host
25294 * physical address (HPA) or a guest physical address (GPA) and must
25295 * point to a physically contiguous block of memory.
25297 uint64_t resp_addr;
25300 * When this bit is '1', the VNIC is requested to
25301 * be the default VNIC for the function.
25303 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
25306 * When this bit is '1', the VNIC is being configured to
25307 * strip VLAN in the RX path.
25308 * If set to '0', then VLAN stripping is disabled on
25311 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
25314 * When this bit is '1', the VNIC is being configured to
25315 * buffer receive packets in the hardware until the host
25316 * posts new receive buffers.
25317 * If set to '0', then bd_stall is being configured to be
25318 * disabled on this VNIC.
25320 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
25323 * When this bit is '1', the VNIC is being configured to
25324 * receive both RoCE and non-RoCE traffic.
25325 * If set to '0', then this VNIC is not configured to be
25326 * operating in dual VNIC mode.
25328 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25331 * When this flag is set to '1', the VNIC is requested to
25332 * be configured to receive only RoCE traffic.
25333 * If this flag is set to '0', then this flag shall be
25334 * ignored by the HWRM.
25335 * If roce_dual_vnic_mode flag is set to '1'
25336 * or roce_mirroring_capable_vnic_mode flag to 1,
25337 * then the HWRM client shall not set this flag to '1'.
25339 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25342 * When a VNIC uses one destination ring group for certain
25343 * application (e.g. Receive Flow Steering) where
25344 * exact match is used to direct packets to a VNIC with one
25345 * destination ring group only, there is no need to configure
25346 * RSS indirection table for that VNIC as only one destination
25347 * ring group is used.
25349 * This flag is used to enable a mode where
25350 * RSS is enabled in the VNIC using a RSS context
25351 * for computing RSS hash but the RSS indirection table is
25352 * not configured using hwrm_vnic_rss_cfg.
25354 * If this mode is enabled, then the driver should not program
25355 * RSS indirection table for the RSS context that is used for
25356 * computing RSS hash only.
25358 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
25361 * When this bit is '1', the VNIC is being configured to
25362 * receive both RoCE and non-RoCE traffic, but forward only the
25363 * RoCE traffic further. Also, RoCE traffic can be mirrored to
25366 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25370 * This bit must be '1' for the dflt_ring_grp field to be
25373 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
25376 * This bit must be '1' for the rss_rule field to be
25379 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
25382 * This bit must be '1' for the cos_rule field to be
25385 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
25388 * This bit must be '1' for the lb_rule field to be
25391 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
25394 * This bit must be '1' for the mru field to be
25397 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
25400 * This bit must be '1' for the default_rx_ring_id field to be
25403 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
25406 * This bit must be '1' for the default_cmpl_ring_id field to be
25409 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
25411 /* This bit must be '1' for the queue_id field to be configured. */
25412 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID \
25414 /* This bit must be '1' for the rx_csum_v2_mode field to be configured. */
25415 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE \
25417 /* Logical vnic ID */
25420 * Default Completion ring for the VNIC. This ring will
25421 * be chosen if packet does not match any RSS rules and if
25422 * there is no COS rule.
25424 uint16_t dflt_ring_grp;
25426 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25427 * there is no RSS rule.
25431 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25432 * there is no COS rule.
25436 * RSS ID for load balancing rule/table structure.
25437 * 0xFF... (All Fs) if there is no LB rule.
25441 * The maximum receive unit of the vnic.
25442 * Each vnic is associated with a function.
25443 * The vnic mru value overwrites the mru setting of the
25444 * associated function.
25445 * The HWRM shall make sure that vnic mru does not exceed
25446 * the mru of the port the function is associated with.
25450 * Default Rx ring for the VNIC. This ring will
25451 * be chosen if packet does not match any RSS rules.
25452 * The aggregation ring associated with the Rx ring is
25453 * implied based on the Rx ring specified when the
25454 * aggregation ring was allocated.
25456 uint16_t default_rx_ring_id;
25458 * Default completion ring for the VNIC. This ring will
25459 * be chosen if packet does not match any RSS rules.
25461 uint16_t default_cmpl_ring_id;
25463 * When specified, only incoming packets classified to the specified CoS
25464 * queue ID will be arriving on this VNIC. Packet priority to CoS mapping
25465 * rules can be specified using HWRM_QUEUE_PRI2COS_CFG. In this mode,
25466 * ntuple filters with VNIC destination specified are invalid since they
25467 * conflict with the the CoS to VNIC steering rules in this mode.
25469 * If this field is not specified, packet to VNIC steering will be
25470 * subject to the standard L2 filter rules and any additional ntuple
25471 * filter rules with destination VNIC specified.
25475 * If the device supports the RX V2 and RX TPA start V2 completion
25476 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
25477 * used to specify the two RX checksum modes supported by these
25478 * completion records.
25480 uint8_t rx_csum_v2_mode;
25482 * When configured with this checksum mode, the number of header
25483 * groups in the delivered packet with a valid IP checksum and
25484 * the number of header groups in the delivered packet with a valid
25485 * L4 checksum are reported. Valid checksums are counted from the
25486 * outermost header group to the innermost header group, stopping at
25487 * the first error. This is the default checksum mode supported if
25488 * the driver doesn't explicitly configure the RX checksum mode.
25490 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
25492 * When configured with this checksum mode, the checksum status is
25493 * reported using 'all ok' mode. In the RX completion record, one
25494 * bit indicates if the IP checksum is valid for all the parsed
25495 * header groups with an IP checksum. Another bit indicates if the
25496 * L4 checksum is valid for all the parsed header groups with an L4
25497 * checksum. The number of header groups that were parsed by the
25498 * chip and passed in the delivered packet is also reported.
25500 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
25502 * Any rx_csum_v2_mode value larger than or equal to this is not
25505 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
25506 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_LAST \
25507 HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX
25508 uint8_t unused0[5];
25511 /* hwrm_vnic_cfg_output (size:128b/16B) */
25512 struct hwrm_vnic_cfg_output {
25513 /* The specific error status for the command. */
25514 uint16_t error_code;
25515 /* The HWRM command request type. */
25517 /* The sequence ID from the original command. */
25519 /* The length of the response data in number of bytes. */
25521 uint8_t unused_0[7];
25523 * This field is used in Output records to indicate that the output
25524 * is completely written to RAM. This field should be read as '1'
25525 * to indicate that the output has been completely written.
25526 * When writing a command completion or response to an internal processor,
25527 * the order of writes has to be such that this field is written last.
25532 /******************
25534 ******************/
25537 /* hwrm_vnic_qcfg_input (size:256b/32B) */
25538 struct hwrm_vnic_qcfg_input {
25539 /* The HWRM command request type. */
25542 * The completion ring to send the completion event on. This should
25543 * be the NQ ID returned from the `nq_alloc` HWRM command.
25545 uint16_t cmpl_ring;
25547 * The sequence ID is used by the driver for tracking multiple
25548 * commands. This ID is treated as opaque data by the firmware and
25549 * the value is returned in the `hwrm_resp_hdr` upon completion.
25553 * The target ID of the command:
25554 * * 0x0-0xFFF8 - The function ID
25555 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25556 * * 0xFFFD - Reserved for user-space HWRM interface
25559 uint16_t target_id;
25561 * A physical address pointer pointing to a host buffer that the
25562 * command's response data will be written. This can be either a host
25563 * physical address (HPA) or a guest physical address (GPA) and must
25564 * point to a physically contiguous block of memory.
25566 uint64_t resp_addr;
25569 * This bit must be '1' for the vf_id_valid field to be
25572 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
25573 /* Logical vnic ID */
25575 /* ID of Virtual Function whose VNIC resource is being queried. */
25577 uint8_t unused_0[6];
25580 /* hwrm_vnic_qcfg_output (size:256b/32B) */
25581 struct hwrm_vnic_qcfg_output {
25582 /* The specific error status for the command. */
25583 uint16_t error_code;
25584 /* The HWRM command request type. */
25586 /* The sequence ID from the original command. */
25588 /* The length of the response data in number of bytes. */
25590 /* Default Completion ring for the VNIC. */
25591 uint16_t dflt_ring_grp;
25593 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
25594 * there is no RSS rule.
25598 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
25599 * there is no COS rule.
25603 * RSS ID for load balancing rule/table structure.
25604 * 0xFF... (All Fs) if there is no LB rule.
25607 /* The maximum receive unit of the vnic. */
25609 uint8_t unused_0[2];
25612 * When this bit is '1', the VNIC is the default VNIC for
25615 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
25618 * When this bit is '1', the VNIC is configured to
25619 * strip VLAN in the RX path.
25620 * If set to '0', then VLAN stripping is disabled on
25623 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
25626 * When this bit is '1', the VNIC is configured to
25627 * buffer receive packets in the hardware until the host
25628 * posts new receive buffers.
25629 * If set to '0', then bd_stall is disabled on
25632 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
25635 * When this bit is '1', the VNIC is configured to
25636 * receive both RoCE and non-RoCE traffic.
25637 * If set to '0', then this VNIC is not configured to
25638 * operate in dual VNIC mode.
25640 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
25643 * When this flag is set to '1', the VNIC is configured to
25644 * receive only RoCE traffic.
25645 * When this flag is set to '0', the VNIC is not configured
25646 * to receive only RoCE traffic.
25647 * If roce_dual_vnic_mode flag and this flag both are set
25648 * to '1', then it is an invalid configuration of the
25649 * VNIC. The HWRM should not allow that type of
25650 * mis-configuration by HWRM clients.
25652 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
25655 * When a VNIC uses one destination ring group for certain
25656 * application (e.g. Receive Flow Steering) where
25657 * exact match is used to direct packets to a VNIC with one
25658 * destination ring group only, there is no need to configure
25659 * RSS indirection table for that VNIC as only one destination
25660 * ring group is used.
25662 * When this bit is set to '1', then the VNIC is enabled in a
25663 * mode where RSS is enabled in the VNIC using a RSS context
25664 * for computing RSS hash but the RSS indirection table is
25667 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
25670 * When this bit is '1', the VNIC is configured to
25671 * receive both RoCE and non-RoCE traffic, but forward only
25672 * RoCE traffic further. Also RoCE traffic can be mirrored to
25675 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
25678 * When returned with a valid CoS Queue id, the CoS Queue/VNIC association
25679 * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS
25680 * queue association.
25684 * If the device supports the RX V2 and RX TPA start V2 completion
25685 * records as indicated by the HWRM_VNIC_QCAPS command, this field is
25686 * used to specify the current RX checksum mode configured for all the
25687 * RX rings of a VNIC.
25689 uint8_t rx_csum_v2_mode;
25691 * This value indicates that the VNIC is configured to use the
25692 * default RX checksum mode for all the rings associated with this
25695 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
25697 * This value indicates that the VNIC is configured to use the RX
25698 * checksum ‘all_ok’ mode for all the rings associated with this
25701 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
25703 * Any rx_csum_v2_mode value larger than or equal to this is not
25706 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
25707 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_LAST \
25708 HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX
25709 uint8_t unused_1[4];
25711 * This field is used in Output records to indicate that the output
25712 * is completely written to RAM. This field should be read as '1'
25713 * to indicate that the output has been completely written.
25714 * When writing a command completion or response to an internal processor,
25715 * the order of writes has to be such that this field is written last.
25720 /*******************
25721 * hwrm_vnic_qcaps *
25722 *******************/
25725 /* hwrm_vnic_qcaps_input (size:192b/24B) */
25726 struct hwrm_vnic_qcaps_input {
25727 /* The HWRM command request type. */
25730 * The completion ring to send the completion event on. This should
25731 * be the NQ ID returned from the `nq_alloc` HWRM command.
25733 uint16_t cmpl_ring;
25735 * The sequence ID is used by the driver for tracking multiple
25736 * commands. This ID is treated as opaque data by the firmware and
25737 * the value is returned in the `hwrm_resp_hdr` upon completion.
25741 * The target ID of the command:
25742 * * 0x0-0xFFF8 - The function ID
25743 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25744 * * 0xFFFD - Reserved for user-space HWRM interface
25747 uint16_t target_id;
25749 * A physical address pointer pointing to a host buffer that the
25750 * command's response data will be written. This can be either a host
25751 * physical address (HPA) or a guest physical address (GPA) and must
25752 * point to a physically contiguous block of memory.
25754 uint64_t resp_addr;
25756 uint8_t unused_0[4];
25759 /* hwrm_vnic_qcaps_output (size:192b/24B) */
25760 struct hwrm_vnic_qcaps_output {
25761 /* The specific error status for the command. */
25762 uint16_t error_code;
25763 /* The HWRM command request type. */
25765 /* The sequence ID from the original command. */
25767 /* The length of the response data in number of bytes. */
25769 /* The maximum receive unit that is settable on a vnic. */
25771 uint8_t unused_0[2];
25774 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
25777 * When this bit is '1', the capability of stripping VLAN in
25778 * the RX path is supported on VNIC(s).
25779 * If set to '0', then VLAN stripping capability is
25780 * not supported on VNIC(s).
25782 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
25785 * When this bit is '1', the capability to buffer receive
25786 * packets in the hardware until the host posts new receive buffers
25787 * is supported on VNIC(s).
25788 * If set to '0', then bd_stall capability is not supported
25791 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
25794 * When this bit is '1', the capability to
25795 * receive both RoCE and non-RoCE traffic on VNIC(s) is
25797 * If set to '0', then the capability to receive
25798 * both RoCE and non-RoCE traffic on VNIC(s) is
25801 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
25804 * When this bit is set to '1', the capability to configure
25805 * a VNIC to receive only RoCE traffic is supported.
25806 * When this flag is set to '0', the VNIC capability to
25807 * configure to receive only RoCE traffic is not supported.
25809 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
25812 * When this bit is set to '1', then the capability to enable
25813 * a VNIC in a mode where RSS context without configuring
25814 * RSS indirection table is supported (for RSS hash computation).
25815 * When this bit is set to '0', then a VNIC can not be configured
25816 * with a mode to enable RSS context without configuring RSS
25817 * indirection table.
25819 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
25822 * When this bit is '1', the capability to
25823 * mirror the the RoCE traffic is supported.
25824 * If set to '0', then the capability to mirror the
25825 * RoCE traffic is not supported.
25827 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
25830 * When this bit is '1', the outermost RSS hashing capability
25831 * is supported. If set to '0', then the outermost RSS hashing
25832 * capability is not supported.
25834 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
25837 * When this bit is '1', it indicates that firmware supports the
25838 * ability to steer incoming packets from one CoS queue to one
25839 * VNIC. This optional feature can then be enabled
25840 * using HWRM_VNIC_CFG on any VNIC. This feature is only
25841 * available when NVM option “enable_cos_classfication” is set
25842 * to 1. If set to '0', firmware does not support this feature.
25844 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP \
25847 * When this bit is '1', it indicates that HW and firmware supports
25848 * the use of RX V2 and RX TPA start V2 completion records for all
25849 * the RX rings of a VNIC. Once set, this feature is mandatory to
25850 * be used for the RX rings of the VNIC. Additionally, two new RX
25851 * checksum features supported by these ompletion records can be
25852 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
25853 * HW and the firmware does not support this feature.
25855 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \
25858 * This field advertises the maximum concurrent TPA aggregations
25859 * supported by the VNIC on new devices that support TPA v2.
25860 * '0' means that TPA v2 is not supported.
25862 uint16_t max_aggs_supported;
25863 uint8_t unused_1[5];
25865 * This field is used in Output records to indicate that the output
25866 * is completely written to RAM. This field should be read as '1'
25867 * to indicate that the output has been completely written.
25868 * When writing a command completion or response to an internal processor,
25869 * the order of writes has to be such that this field is written last.
25874 /*********************
25875 * hwrm_vnic_tpa_cfg *
25876 *********************/
25879 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
25880 struct hwrm_vnic_tpa_cfg_input {
25881 /* The HWRM command request type. */
25884 * The completion ring to send the completion event on. This should
25885 * be the NQ ID returned from the `nq_alloc` HWRM command.
25887 uint16_t cmpl_ring;
25889 * The sequence ID is used by the driver for tracking multiple
25890 * commands. This ID is treated as opaque data by the firmware and
25891 * the value is returned in the `hwrm_resp_hdr` upon completion.
25895 * The target ID of the command:
25896 * * 0x0-0xFFF8 - The function ID
25897 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25898 * * 0xFFFD - Reserved for user-space HWRM interface
25901 uint16_t target_id;
25903 * A physical address pointer pointing to a host buffer that the
25904 * command's response data will be written. This can be either a host
25905 * physical address (HPA) or a guest physical address (GPA) and must
25906 * point to a physically contiguous block of memory.
25908 uint64_t resp_addr;
25911 * When this bit is '1', the VNIC shall be configured to
25912 * perform transparent packet aggregation (TPA) of
25913 * non-tunneled TCP packets.
25915 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
25918 * When this bit is '1', the VNIC shall be configured to
25919 * perform transparent packet aggregation (TPA) of
25920 * tunneled TCP packets.
25922 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
25925 * When this bit is '1', the VNIC shall be configured to
25926 * perform transparent packet aggregation (TPA) according
25927 * to Windows Receive Segment Coalescing (RSC) rules.
25929 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
25932 * When this bit is '1', the VNIC shall be configured to
25933 * perform transparent packet aggregation (TPA) according
25934 * to Linux Generic Receive Offload (GRO) rules.
25936 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
25939 * When this bit is '1', the VNIC shall be configured to
25940 * perform transparent packet aggregation (TPA) for TCP
25941 * packets with IP ECN set to non-zero.
25943 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
25946 * When this bit is '1', the VNIC shall be configured to
25947 * perform transparent packet aggregation (TPA) for
25948 * GRE tunneled TCP packets only if all packets have the
25949 * same GRE sequence.
25951 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
25954 * When this bit is '1' and the GRO mode is enabled,
25955 * the VNIC shall be configured to
25956 * perform transparent packet aggregation (TPA) for
25957 * TCP/IPv4 packets with consecutively increasing IPIDs.
25958 * In other words, the last packet that is being
25959 * aggregated to an already existing aggregation context
25960 * shall have IPID 1 more than the IPID of the last packet
25961 * that was aggregated in that aggregation context.
25963 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
25966 * When this bit is '1' and the GRO mode is enabled,
25967 * the VNIC shall be configured to
25968 * perform transparent packet aggregation (TPA) for
25969 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
25972 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
25975 * When this bit is '1' and the GRO mode is enabled,
25976 * the VNIC shall DMA payload data using GRO rules.
25977 * When this bit is '0', the VNIC shall DMA payload data
25978 * using the more efficient LRO rules of filling all
25979 * aggregation buffers.
25981 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
25985 * This bit must be '1' for the max_agg_segs field to be
25988 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
25990 * This bit must be '1' for the max_aggs field to be
25993 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
25995 * This bit must be '1' for the max_agg_timer field to be
25998 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
25999 /* deprecated bit. Do not use!!! */
26000 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
26001 /* Logical vnic ID */
26004 * This is the maximum number of TCP segments that can
26005 * be aggregated (unit is Log2). Max value is 31. On new
26006 * devices supporting TPA v2, the unit is multiples of 4 and
26007 * valid values are > 0 and <= 63.
26009 uint16_t max_agg_segs;
26011 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
26013 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
26015 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
26017 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
26018 /* Any segment size larger than this is not valid */
26019 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
26020 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
26021 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
26023 * This is the maximum number of aggregations this VNIC is
26024 * allowed (unit is Log2). Max value is 7. On new devices
26025 * supporting TPA v2, this is in unit of 1 and must be > 0
26026 * and <= max_aggs_supported in the hwrm_vnic_qcaps response
26027 * to enable TPA v2.
26030 /* 1 aggregation */
26031 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
26032 /* 2 aggregations */
26033 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
26034 /* 4 aggregations */
26035 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
26036 /* 8 aggregations */
26037 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
26038 /* 16 aggregations */
26039 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
26040 /* Any aggregation size larger than this is not valid */
26041 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
26042 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
26043 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
26044 uint8_t unused_0[2];
26046 * This is the maximum amount of time allowed for
26047 * an aggregation context to complete after it was initiated.
26049 uint32_t max_agg_timer;
26051 * This is the minimum amount of payload length required to
26052 * start an aggregation context. This field is deprecated and
26053 * should be set to 0. The minimum length is set by firmware
26054 * and can be queried using hwrm_vnic_tpa_qcfg.
26056 uint32_t min_agg_len;
26059 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
26060 struct hwrm_vnic_tpa_cfg_output {
26061 /* The specific error status for the command. */
26062 uint16_t error_code;
26063 /* The HWRM command request type. */
26065 /* The sequence ID from the original command. */
26067 /* The length of the response data in number of bytes. */
26069 uint8_t unused_0[7];
26071 * This field is used in Output records to indicate that the output
26072 * is completely written to RAM. This field should be read as '1'
26073 * to indicate that the output has been completely written.
26074 * When writing a command completion or response to an internal processor,
26075 * the order of writes has to be such that this field is written last.
26080 /*********************
26081 * hwrm_vnic_rss_cfg *
26082 *********************/
26085 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
26086 struct hwrm_vnic_rss_cfg_input {
26087 /* The HWRM command request type. */
26090 * The completion ring to send the completion event on. This should
26091 * be the NQ ID returned from the `nq_alloc` HWRM command.
26093 uint16_t cmpl_ring;
26095 * The sequence ID is used by the driver for tracking multiple
26096 * commands. This ID is treated as opaque data by the firmware and
26097 * the value is returned in the `hwrm_resp_hdr` upon completion.
26101 * The target ID of the command:
26102 * * 0x0-0xFFF8 - The function ID
26103 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26104 * * 0xFFFD - Reserved for user-space HWRM interface
26107 uint16_t target_id;
26109 * A physical address pointer pointing to a host buffer that the
26110 * command's response data will be written. This can be either a host
26111 * physical address (HPA) or a guest physical address (GPA) and must
26112 * point to a physically contiguous block of memory.
26114 uint64_t resp_addr;
26115 uint32_t hash_type;
26117 * When this bit is '1', the RSS hash shall be computed
26118 * over source and destination IPv4 addresses of IPv4
26121 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26123 * When this bit is '1', the RSS hash shall be computed
26124 * over source/destination IPv4 addresses and
26125 * source/destination ports of TCP/IPv4 packets.
26127 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26129 * When this bit is '1', the RSS hash shall be computed
26130 * over source/destination IPv4 addresses and
26131 * source/destination ports of UDP/IPv4 packets.
26133 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26135 * When this bit is '1', the RSS hash shall be computed
26136 * over source and destination IPv4 addresses of IPv6
26139 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26141 * When this bit is '1', the RSS hash shall be computed
26142 * over source/destination IPv6 addresses and
26143 * source/destination ports of TCP/IPv6 packets.
26145 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26147 * When this bit is '1', the RSS hash shall be computed
26148 * over source/destination IPv6 addresses and
26149 * source/destination ports of UDP/IPv6 packets.
26151 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26152 /* VNIC ID of VNIC associated with RSS table being configured. */
26155 * Specifies which VNIC ring table pair to configure.
26156 * Valid values range from 0 to 7.
26158 uint8_t ring_table_pair_index;
26159 /* Flags to specify different RSS hash modes. */
26160 uint8_t hash_mode_flags;
26162 * When this bit is '1', it indicates using current RSS
26163 * hash mode setting configured in the device.
26165 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
26168 * When this bit is '1', it indicates requesting support of
26169 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26170 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26171 * packets, the RSS hash is computed over the normal
26172 * src/dest l3 and src/dest l4 headers.
26174 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26177 * When this bit is '1', it indicates requesting support of
26178 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26179 * tunnel packets. For none-tunnel packets, the RSS hash is
26180 * computed over the normal src/dest l3 headers.
26182 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26185 * When this bit is '1', it indicates requesting support of
26186 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26187 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26188 * packets, the RSS hash is computed over the normal
26189 * src/dest l3 and src/dest l4 headers.
26191 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26194 * When this bit is '1', it indicates requesting support of
26195 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26196 * tunnel packets. For none-tunnel packets, the RSS hash is
26197 * computed over the normal src/dest l3 headers.
26199 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26201 /* This is the address for rss ring group table */
26202 uint64_t ring_grp_tbl_addr;
26203 /* This is the address for rss hash key table */
26204 uint64_t hash_key_tbl_addr;
26205 /* Index to the rss indirection table. */
26206 uint16_t rss_ctx_idx;
26207 uint8_t unused_1[6];
26210 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
26211 struct hwrm_vnic_rss_cfg_output {
26212 /* The specific error status for the command. */
26213 uint16_t error_code;
26214 /* The HWRM command request type. */
26216 /* The sequence ID from the original command. */
26218 /* The length of the response data in number of bytes. */
26220 uint8_t unused_0[7];
26222 * This field is used in Output records to indicate that the output
26223 * is completely written to RAM. This field should be read as '1'
26224 * to indicate that the output has been completely written.
26225 * When writing a command completion or response to an internal processor,
26226 * the order of writes has to be such that this field is written last.
26231 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */
26232 struct hwrm_vnic_rss_cfg_cmd_err {
26234 * command specific error codes that goes to
26235 * the cmd_err field in Common HWRM Error Response.
26238 /* Unknown error */
26239 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN \
26242 * Unable to change global RSS mode to outer due to all active
26243 * interfaces are not ready to support outer RSS hashing.
26245 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY \
26247 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_LAST \
26248 HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY
26249 uint8_t unused_0[7];
26252 /**********************
26253 * hwrm_vnic_rss_qcfg *
26254 **********************/
26257 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
26258 struct hwrm_vnic_rss_qcfg_input {
26259 /* The HWRM command request type. */
26262 * The completion ring to send the completion event on. This should
26263 * be the NQ ID returned from the `nq_alloc` HWRM command.
26265 uint16_t cmpl_ring;
26267 * The sequence ID is used by the driver for tracking multiple
26268 * commands. This ID is treated as opaque data by the firmware and
26269 * the value is returned in the `hwrm_resp_hdr` upon completion.
26273 * The target ID of the command:
26274 * * 0x0-0xFFF8 - The function ID
26275 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26276 * * 0xFFFD - Reserved for user-space HWRM interface
26279 uint16_t target_id;
26281 * A physical address pointer pointing to a host buffer that the
26282 * command's response data will be written. This can be either a host
26283 * physical address (HPA) or a guest physical address (GPA) and must
26284 * point to a physically contiguous block of memory.
26286 uint64_t resp_addr;
26287 /* Index to the rss indirection table. */
26288 uint16_t rss_ctx_idx;
26289 uint8_t unused_0[6];
26292 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
26293 struct hwrm_vnic_rss_qcfg_output {
26294 /* The specific error status for the command. */
26295 uint16_t error_code;
26296 /* The HWRM command request type. */
26298 /* The sequence ID from the original command. */
26300 /* The length of the response data in number of bytes. */
26302 uint32_t hash_type;
26304 * When this bit is '1', the RSS hash shall be computed
26305 * over source and destination IPv4 addresses of IPv4
26308 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
26310 * When this bit is '1', the RSS hash shall be computed
26311 * over source/destination IPv4 addresses and
26312 * source/destination ports of TCP/IPv4 packets.
26314 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
26316 * When this bit is '1', the RSS hash shall be computed
26317 * over source/destination IPv4 addresses and
26318 * source/destination ports of UDP/IPv4 packets.
26320 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
26322 * When this bit is '1', the RSS hash shall be computed
26323 * over source and destination IPv4 addresses of IPv6
26326 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
26328 * When this bit is '1', the RSS hash shall be computed
26329 * over source/destination IPv6 addresses and
26330 * source/destination ports of TCP/IPv6 packets.
26332 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
26334 * When this bit is '1', the RSS hash shall be computed
26335 * over source/destination IPv6 addresses and
26336 * source/destination ports of UDP/IPv6 packets.
26338 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
26339 uint8_t unused_0[4];
26340 /* This is the value of rss hash key */
26341 uint32_t hash_key[10];
26342 /* Flags to specify different RSS hash modes. */
26343 uint8_t hash_mode_flags;
26345 * When this bit is '1', it indicates using current RSS
26346 * hash mode setting configured in the device.
26348 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
26351 * When this bit is '1', it indicates requesting support of
26352 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
26353 * l4.src, l4.dest} for tunnel packets. For none-tunnel
26354 * packets, the RSS hash is computed over the normal
26355 * src/dest l3 and src/dest l4 headers.
26357 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
26360 * When this bit is '1', it indicates requesting support of
26361 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
26362 * tunnel packets. For none-tunnel packets, the RSS hash is
26363 * computed over the normal src/dest l3 headers.
26365 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
26368 * When this bit is '1', it indicates requesting support of
26369 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
26370 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
26371 * packets, the RSS hash is computed over the normal
26372 * src/dest l3 and src/dest l4 headers.
26374 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
26377 * When this bit is '1', it indicates requesting support of
26378 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
26379 * tunnel packets. For none-tunnel packets, the RSS hash is
26380 * computed over the normal src/dest l3 headers.
26382 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
26384 uint8_t unused_1[6];
26386 * This field is used in Output records to indicate that the output
26387 * is completely written to RAM. This field should be read as '1'
26388 * to indicate that the output has been completely written.
26389 * When writing a command completion or response to an internal processor,
26390 * the order of writes has to be such that this field is written last.
26395 /**************************
26396 * hwrm_vnic_plcmodes_cfg *
26397 **************************/
26400 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
26401 struct hwrm_vnic_plcmodes_cfg_input {
26402 /* The HWRM command request type. */
26405 * The completion ring to send the completion event on. This should
26406 * be the NQ ID returned from the `nq_alloc` HWRM command.
26408 uint16_t cmpl_ring;
26410 * The sequence ID is used by the driver for tracking multiple
26411 * commands. This ID is treated as opaque data by the firmware and
26412 * the value is returned in the `hwrm_resp_hdr` upon completion.
26416 * The target ID of the command:
26417 * * 0x0-0xFFF8 - The function ID
26418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26419 * * 0xFFFD - Reserved for user-space HWRM interface
26422 uint16_t target_id;
26424 * A physical address pointer pointing to a host buffer that the
26425 * command's response data will be written. This can be either a host
26426 * physical address (HPA) or a guest physical address (GPA) and must
26427 * point to a physically contiguous block of memory.
26429 uint64_t resp_addr;
26432 * When this bit is '1', the VNIC shall be configured to
26433 * use regular placement algorithm.
26434 * By default, the regular placement algorithm shall be
26435 * enabled on the VNIC.
26437 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
26440 * When this bit is '1', the VNIC shall be configured
26441 * use the jumbo placement algorithm.
26443 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
26446 * When this bit is '1', the VNIC shall be configured
26447 * to enable Header-Data split for IPv4 packets according
26448 * to the following rules:
26449 * # If the packet is identified as TCP/IPv4, then the
26450 * packet is split at the beginning of the TCP payload.
26451 * # If the packet is identified as UDP/IPv4, then the
26452 * packet is split at the beginning of UDP payload.
26453 * # If the packet is identified as non-TCP and non-UDP
26454 * IPv4 packet, then the packet is split at the beginning
26455 * of the upper layer protocol header carried in the IPv4
26458 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
26461 * When this bit is '1', the VNIC shall be configured
26462 * to enable Header-Data split for IPv6 packets according
26463 * to the following rules:
26464 * # If the packet is identified as TCP/IPv6, then the
26465 * packet is split at the beginning of the TCP payload.
26466 * # If the packet is identified as UDP/IPv6, then the
26467 * packet is split at the beginning of UDP payload.
26468 * # If the packet is identified as non-TCP and non-UDP
26469 * IPv6 packet, then the packet is split at the beginning
26470 * of the upper layer protocol header carried in the IPv6
26473 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
26476 * When this bit is '1', the VNIC shall be configured
26477 * to enable Header-Data split for FCoE packets at the
26478 * beginning of FC payload.
26480 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
26483 * When this bit is '1', the VNIC shall be configured
26484 * to enable Header-Data split for RoCE packets at the
26485 * beginning of RoCE payload (after BTH/GRH headers).
26487 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
26490 * When this bit is '1', the VNIC shall be configured use the virtio
26491 * placement algorithm. This feature can only be configured when
26492 * proxy mode is supported on the function.
26494 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT \
26498 * This bit must be '1' for the jumbo_thresh_valid field to be
26501 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
26504 * This bit must be '1' for the hds_offset_valid field to be
26507 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
26510 * This bit must be '1' for the hds_threshold_valid field to be
26513 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
26516 * This bit must be '1' for the max_bds_valid field to be
26519 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID \
26521 /* Logical vnic ID */
26524 * When jumbo placement algorithm is enabled, this value
26525 * is used to determine the threshold for jumbo placement.
26526 * Packets with length larger than this value will be
26527 * placed according to the jumbo placement algorithm.
26529 uint16_t jumbo_thresh;
26531 * This value is used to determine the offset into
26532 * packet buffer where the split data (payload) will be
26533 * placed according to one of HDS placement algorithm.
26535 * The lengths of packet buffers provided for split data
26536 * shall be larger than this value.
26538 uint16_t hds_offset;
26540 * When one of the HDS placement algorithm is enabled, this
26541 * value is used to determine the threshold for HDS
26543 * Packets with length larger than this value will be
26544 * placed according to the HDS placement algorithm.
26545 * This value shall be in multiple of 4 bytes.
26547 uint16_t hds_threshold;
26549 * When virtio placement algorithm is enabled, this
26550 * value is used to determine the the maximum number of BDs
26551 * that can be used to place an Rx Packet.
26552 * If an incoming packet does not fit in the buffers described
26553 * by the max BDs, the packet will be dropped and an error
26554 * will be reported in the completion. Valid values for this
26555 * field are between 1 and 8. If the VNIC uses header-data-
26556 * separation and/or TPA with buffer spanning enabled, valid
26557 * values for this field are between 2 and 8.
26558 * This feature can only be configured when proxy mode is
26559 * supported on the function.
26562 uint8_t unused_0[4];
26565 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
26566 struct hwrm_vnic_plcmodes_cfg_output {
26567 /* The specific error status for the command. */
26568 uint16_t error_code;
26569 /* The HWRM command request type. */
26571 /* The sequence ID from the original command. */
26573 /* The length of the response data in number of bytes. */
26575 uint8_t unused_0[7];
26577 * This field is used in Output records to indicate that the output
26578 * is completely written to RAM. This field should be read as '1'
26579 * to indicate that the output has been completely written.
26580 * When writing a command completion or response to an internal
26581 * processor, the order of writes has to be such that this field is
26587 /***************************
26588 * hwrm_vnic_plcmodes_qcfg *
26589 ***************************/
26592 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
26593 struct hwrm_vnic_plcmodes_qcfg_input {
26594 /* The HWRM command request type. */
26597 * The completion ring to send the completion event on. This should
26598 * be the NQ ID returned from the `nq_alloc` HWRM command.
26600 uint16_t cmpl_ring;
26602 * The sequence ID is used by the driver for tracking multiple
26603 * commands. This ID is treated as opaque data by the firmware and
26604 * the value is returned in the `hwrm_resp_hdr` upon completion.
26608 * The target ID of the command:
26609 * * 0x0-0xFFF8 - The function ID
26610 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26611 * * 0xFFFD - Reserved for user-space HWRM interface
26614 uint16_t target_id;
26616 * A physical address pointer pointing to a host buffer that the
26617 * command's response data will be written. This can be either a host
26618 * physical address (HPA) or a guest physical address (GPA) and must
26619 * point to a physically contiguous block of memory.
26621 uint64_t resp_addr;
26622 /* Logical vnic ID */
26624 uint8_t unused_0[4];
26627 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
26628 struct hwrm_vnic_plcmodes_qcfg_output {
26629 /* The specific error status for the command. */
26630 uint16_t error_code;
26631 /* The HWRM command request type. */
26633 /* The sequence ID from the original command. */
26635 /* The length of the response data in number of bytes. */
26639 * When this bit is '1', the VNIC is configured to
26640 * use regular placement algorithm.
26642 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
26645 * When this bit is '1', the VNIC is configured to
26646 * use the jumbo placement algorithm.
26648 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
26651 * When this bit is '1', the VNIC is configured
26652 * to enable Header-Data split for IPv4 packets.
26654 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
26657 * When this bit is '1', the VNIC is configured
26658 * to enable Header-Data split for IPv6 packets.
26660 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
26663 * When this bit is '1', the VNIC is configured
26664 * to enable Header-Data split for FCoE packets.
26666 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
26669 * When this bit is '1', the VNIC is configured
26670 * to enable Header-Data split for RoCE packets.
26672 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
26675 * When this bit is '1', the VNIC is configured
26676 * to be the default VNIC of the requesting function.
26678 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
26681 * When this bit is '1', the VNIC is configured to use the virtio
26682 * placement algorithm. This feature can only be configured when
26683 * proxy mode is supported on the function.
26685 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT \
26688 * When jumbo placement algorithm is enabled, this value
26689 * is used to determine the threshold for jumbo placement.
26690 * Packets with length larger than this value will be
26691 * placed according to the jumbo placement algorithm.
26693 uint16_t jumbo_thresh;
26695 * This value is used to determine the offset into
26696 * packet buffer where the split data (payload) will be
26697 * placed according to one of HDS placement algorithm.
26699 * The lengths of packet buffers provided for split data
26700 * shall be larger than this value.
26702 uint16_t hds_offset;
26704 * When one of the HDS placement algorithm is enabled, this
26705 * value is used to determine the threshold for HDS
26707 * Packets with length larger than this value will be
26708 * placed according to the HDS placement algorithm.
26709 * This value shall be in multiple of 4 bytes.
26711 uint16_t hds_threshold;
26713 * When virtio placement algorithm is enabled, this
26714 * value is used to determine the the maximum number of BDs
26715 * that can be used to place an Rx Packet.
26716 * If an incoming packet does not fit in the buffers described
26717 * by the max BDs, the packet will be dropped and an error
26718 * will be reported in the completion. Valid values for this
26719 * field are between 1 and 8. If the VNIC uses header-data-
26720 * separation and/or TPA with buffer spanning enabled, valid
26721 * values for this field are between 2 and 8.
26722 * This feature can only be configured when proxy mode is supported
26726 uint8_t unused_0[3];
26728 * This field is used in Output records to indicate that the output
26729 * is completely written to RAM. This field should be read as '1'
26730 * to indicate that the output has been completely written.
26731 * When writing a command completion or response to an internal
26732 * processor, the order of writes has to be such that this field is
26738 /**********************************
26739 * hwrm_vnic_rss_cos_lb_ctx_alloc *
26740 **********************************/
26743 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
26744 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
26745 /* The HWRM command request type. */
26748 * The completion ring to send the completion event on. This should
26749 * be the NQ ID returned from the `nq_alloc` HWRM command.
26751 uint16_t cmpl_ring;
26753 * The sequence ID is used by the driver for tracking multiple
26754 * commands. This ID is treated as opaque data by the firmware and
26755 * the value is returned in the `hwrm_resp_hdr` upon completion.
26759 * The target ID of the command:
26760 * * 0x0-0xFFF8 - The function ID
26761 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26762 * * 0xFFFD - Reserved for user-space HWRM interface
26765 uint16_t target_id;
26767 * A physical address pointer pointing to a host buffer that the
26768 * command's response data will be written. This can be either a host
26769 * physical address (HPA) or a guest physical address (GPA) and must
26770 * point to a physically contiguous block of memory.
26772 uint64_t resp_addr;
26775 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
26776 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
26777 /* The specific error status for the command. */
26778 uint16_t error_code;
26779 /* The HWRM command request type. */
26781 /* The sequence ID from the original command. */
26783 /* The length of the response data in number of bytes. */
26785 /* rss_cos_lb_ctx_id is 16 b */
26786 uint16_t rss_cos_lb_ctx_id;
26787 uint8_t unused_0[5];
26789 * This field is used in Output records to indicate that the output
26790 * is completely written to RAM. This field should be read as '1'
26791 * to indicate that the output has been completely written.
26792 * When writing a command completion or response to an internal processor,
26793 * the order of writes has to be such that this field is written last.
26798 /*********************************
26799 * hwrm_vnic_rss_cos_lb_ctx_free *
26800 *********************************/
26803 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
26804 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
26805 /* The HWRM command request type. */
26808 * The completion ring to send the completion event on. This should
26809 * be the NQ ID returned from the `nq_alloc` HWRM command.
26811 uint16_t cmpl_ring;
26813 * The sequence ID is used by the driver for tracking multiple
26814 * commands. This ID is treated as opaque data by the firmware and
26815 * the value is returned in the `hwrm_resp_hdr` upon completion.
26819 * The target ID of the command:
26820 * * 0x0-0xFFF8 - The function ID
26821 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26822 * * 0xFFFD - Reserved for user-space HWRM interface
26825 uint16_t target_id;
26827 * A physical address pointer pointing to a host buffer that the
26828 * command's response data will be written. This can be either a host
26829 * physical address (HPA) or a guest physical address (GPA) and must
26830 * point to a physically contiguous block of memory.
26832 uint64_t resp_addr;
26833 /* rss_cos_lb_ctx_id is 16 b */
26834 uint16_t rss_cos_lb_ctx_id;
26835 uint8_t unused_0[6];
26838 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
26839 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
26840 /* The specific error status for the command. */
26841 uint16_t error_code;
26842 /* The HWRM command request type. */
26844 /* The sequence ID from the original command. */
26846 /* The length of the response data in number of bytes. */
26848 uint8_t unused_0[7];
26850 * This field is used in Output records to indicate that the output
26851 * is completely written to RAM. This field should be read as '1'
26852 * to indicate that the output has been completely written.
26853 * When writing a command completion or response to an internal processor,
26854 * the order of writes has to be such that this field is written last.
26859 /*******************
26860 * hwrm_ring_alloc *
26861 *******************/
26864 /* hwrm_ring_alloc_input (size:704b/88B) */
26865 struct hwrm_ring_alloc_input {
26866 /* The HWRM command request type. */
26869 * The completion ring to send the completion event on. This should
26870 * be the NQ ID returned from the `nq_alloc` HWRM command.
26872 uint16_t cmpl_ring;
26874 * The sequence ID is used by the driver for tracking multiple
26875 * commands. This ID is treated as opaque data by the firmware and
26876 * the value is returned in the `hwrm_resp_hdr` upon completion.
26880 * The target ID of the command:
26881 * * 0x0-0xFFF8 - The function ID
26882 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26883 * * 0xFFFD - Reserved for user-space HWRM interface
26886 uint16_t target_id;
26888 * A physical address pointer pointing to a host buffer that the
26889 * command's response data will be written. This can be either a host
26890 * physical address (HPA) or a guest physical address (GPA) and must
26891 * point to a physically contiguous block of memory.
26893 uint64_t resp_addr;
26896 * This bit must be '1' for the ring_arb_cfg field to be
26899 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
26902 * This bit must be '1' for the stat_ctx_id_valid field to be
26905 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
26908 * This bit must be '1' for the max_bw_valid field to be
26911 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
26914 * This bit must be '1' for the rx_ring_id field to be
26917 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
26920 * This bit must be '1' for the nq_ring_id field to be
26923 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
26926 * This bit must be '1' for the rx_buf_size field to be
26929 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
26932 * This bit must be '1' for the sq_id field to be
26935 #define HWRM_RING_ALLOC_INPUT_ENABLES_SQ_ID \
26939 /* L2 Completion Ring (CR) */
26940 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
26942 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
26944 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
26945 /* RoCE Notification Completion Ring (ROCE_CR) */
26946 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
26947 /* RX Aggregation Ring */
26948 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
26949 /* Notification Queue */
26950 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
26951 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
26952 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
26954 /* Ring allocation flags. */
26957 * For Rx rings, the incoming packet data can be placed at either
26958 * a 0B or 2B offset from the start of the Rx packet buffer. When
26959 * '1', the received packet will be padded with 2B of zeros at the
26960 * front of the packet. Note that this flag is only used for
26961 * Rx rings and is ignored for all other rings included Rx
26962 * Aggregation rings.
26964 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
26966 * This value is a pointer to the page table for the
26969 uint64_t page_tbl_addr;
26970 /* First Byte Offset of the first entry in the first page. */
26973 * Actual page size in 2^page_size. The supported range is increments
26974 * in powers of 2 from 16 bytes to 1GB.
26976 * Page size is 16 B.
26978 * Page size is 4 KB.
26980 * Page size is 8 KB.
26982 * Page size is 64 KB.
26984 * Page size is 2 MB.
26986 * Page size is 4 MB.
26988 * Page size is 1 GB.
26992 * This value indicates the depth of page table.
26993 * For this version of the specification, value other than 0 or
26994 * 1 shall be considered as an invalid value.
26995 * When the page_tbl_depth = 0, then it is treated as a
26996 * special case with the following.
26997 * 1. FBO and page size fields are not valid.
26998 * 2. page_tbl_addr is the physical address of the first
26999 * element of the ring.
27001 uint8_t page_tbl_depth;
27002 /* Used by a PF driver to associate a SQ with one of its TX rings. */
27005 * Number of 16B units in the ring. Minimum size for
27006 * a ring is 16 16B entries.
27010 * Logical ring number for the ring to be allocated.
27011 * This value determines the position in the doorbell
27012 * area where the update to the ring will be made.
27014 * For completion rings, this value is also the MSI-X
27015 * vector number for the function the completion ring is
27018 uint16_t logical_id;
27020 * This field is used only when ring_type is a TX ring.
27021 * This value indicates what completion ring the TX ring
27022 * is associated with.
27024 uint16_t cmpl_ring_id;
27026 * This field is used only when ring_type is a TX ring.
27027 * This value indicates what CoS queue the TX ring
27028 * is associated with.
27032 * When allocating a Rx ring or Rx aggregation ring, this field
27033 * specifies the size of the buffer descriptors posted to the ring.
27035 uint16_t rx_buf_size;
27037 * When allocating an Rx aggregation ring, this field
27038 * specifies the associated Rx ring ID.
27040 uint16_t rx_ring_id;
27042 * When allocating a completion ring, this field
27043 * specifies the associated NQ ring ID.
27045 uint16_t nq_ring_id;
27047 * This field is used only when ring_type is a TX ring.
27048 * This field is used to configure arbitration related
27049 * parameters for a TX ring.
27051 uint16_t ring_arb_cfg;
27052 /* Arbitration policy used for the ring. */
27053 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
27055 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
27057 * Use strict priority for the TX ring.
27058 * Priority value is specified in arb_policy_param
27060 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
27063 * Use weighted fair queue arbitration for the TX ring.
27064 * Weight is specified in arb_policy_param
27066 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
27068 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
27069 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
27070 /* Reserved field. */
27071 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
27073 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
27075 * Arbitration policy specific parameter.
27076 * # For strict priority arbitration policy, this field
27077 * represents a priority value. If set to 0, then the priority
27078 * is not specified and the HWRM is allowed to select
27079 * any priority for this TX ring.
27080 * # For weighted fair queue arbitration policy, this field
27081 * represents a weight value. If set to 0, then the weight
27082 * is not specified and the HWRM is allowed to select
27083 * any weight for this TX ring.
27085 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
27087 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
27090 * This field is reserved for the future use.
27091 * It shall be set to 0.
27093 uint32_t reserved3;
27095 * This field is used only when ring_type is a TX ring.
27096 * This input indicates what statistics context this ring
27097 * should be associated with.
27099 uint32_t stat_ctx_id;
27101 * This field is reserved for the future use.
27102 * It shall be set to 0.
27104 uint32_t reserved4;
27106 * This field is used only when ring_type is a TX ring
27107 * to specify maximum BW allocated to the TX ring.
27108 * The HWRM will translate this value into byte counter and
27109 * time interval used for this ring inside the device.
27112 /* The bandwidth value. */
27113 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
27114 UINT32_C(0xfffffff)
27115 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
27116 /* The granularity of the value (bits or bytes). */
27117 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
27118 UINT32_C(0x10000000)
27119 /* Value is in bits. */
27120 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
27121 (UINT32_C(0x0) << 28)
27122 /* Value is in bytes. */
27123 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
27124 (UINT32_C(0x1) << 28)
27125 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
27126 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
27127 /* bw_value_unit is 3 b */
27128 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
27129 UINT32_C(0xe0000000)
27130 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
27131 /* Value is in Mb or MB (base 10). */
27132 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
27133 (UINT32_C(0x0) << 29)
27134 /* Value is in Kb or KB (base 10). */
27135 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
27136 (UINT32_C(0x2) << 29)
27137 /* Value is in bits or bytes. */
27138 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
27139 (UINT32_C(0x4) << 29)
27140 /* Value is in Gb or GB (base 10). */
27141 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
27142 (UINT32_C(0x6) << 29)
27143 /* Value is in 1/100th of a percentage of total bandwidth. */
27144 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
27145 (UINT32_C(0x1) << 29)
27147 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
27148 (UINT32_C(0x7) << 29)
27149 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
27150 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
27152 * This field is used only when ring_type is a Completion ring.
27153 * This value indicates what interrupt mode should be used
27154 * on this completion ring.
27155 * Note: In the legacy interrupt mode, no more than 16
27156 * completion rings are allowed.
27160 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
27162 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
27164 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
27165 /* No Interrupt - Polled mode */
27166 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
27167 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
27168 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
27169 uint8_t unused_4[3];
27171 * The cq_handle is specified when allocating a completion ring. For
27172 * devices that support NQs, this cq_handle will be included in the
27173 * NQE to specify which CQ should be read to retrieve the completion
27176 uint64_t cq_handle;
27179 /* hwrm_ring_alloc_output (size:128b/16B) */
27180 struct hwrm_ring_alloc_output {
27181 /* The specific error status for the command. */
27182 uint16_t error_code;
27183 /* The HWRM command request type. */
27185 /* The sequence ID from the original command. */
27187 /* The length of the response data in number of bytes. */
27190 * Physical number of ring allocated.
27191 * This value shall be unique for a ring type.
27194 /* Logical number of ring allocated. */
27195 uint16_t logical_ring_id;
27196 uint8_t unused_0[3];
27198 * This field is used in Output records to indicate that the output
27199 * is completely written to RAM. This field should be read as '1'
27200 * to indicate that the output has been completely written.
27201 * When writing a command completion or response to an internal processor,
27202 * the order of writes has to be such that this field is written last.
27207 /******************
27209 ******************/
27212 /* hwrm_ring_free_input (size:192b/24B) */
27213 struct hwrm_ring_free_input {
27214 /* The HWRM command request type. */
27217 * The completion ring to send the completion event on. This should
27218 * be the NQ ID returned from the `nq_alloc` HWRM command.
27220 uint16_t cmpl_ring;
27222 * The sequence ID is used by the driver for tracking multiple
27223 * commands. This ID is treated as opaque data by the firmware and
27224 * the value is returned in the `hwrm_resp_hdr` upon completion.
27228 * The target ID of the command:
27229 * * 0x0-0xFFF8 - The function ID
27230 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27231 * * 0xFFFD - Reserved for user-space HWRM interface
27234 uint16_t target_id;
27236 * A physical address pointer pointing to a host buffer that the
27237 * command's response data will be written. This can be either a host
27238 * physical address (HPA) or a guest physical address (GPA) and must
27239 * point to a physically contiguous block of memory.
27241 uint64_t resp_addr;
27244 /* L2 Completion Ring (CR) */
27245 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27247 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
27249 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
27250 /* RoCE Notification Completion Ring (ROCE_CR) */
27251 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27252 /* RX Aggregation Ring */
27253 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
27254 /* Notification Queue */
27255 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
27256 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
27257 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
27259 /* Physical number of ring allocated. */
27261 uint8_t unused_1[4];
27264 /* hwrm_ring_free_output (size:128b/16B) */
27265 struct hwrm_ring_free_output {
27266 /* The specific error status for the command. */
27267 uint16_t error_code;
27268 /* The HWRM command request type. */
27270 /* The sequence ID from the original command. */
27272 /* The length of the response data in number of bytes. */
27274 uint8_t unused_0[7];
27276 * This field is used in Output records to indicate that the output
27277 * is completely written to RAM. This field should be read as '1'
27278 * to indicate that the output has been completely written.
27279 * When writing a command completion or response to an internal processor,
27280 * the order of writes has to be such that this field is written last.
27285 /*******************
27286 * hwrm_ring_reset *
27287 *******************/
27290 /* hwrm_ring_reset_input (size:192b/24B) */
27291 struct hwrm_ring_reset_input {
27292 /* The HWRM command request type. */
27295 * The completion ring to send the completion event on. This should
27296 * be the NQ ID returned from the `nq_alloc` HWRM command.
27298 uint16_t cmpl_ring;
27300 * The sequence ID is used by the driver for tracking multiple
27301 * commands. This ID is treated as opaque data by the firmware and
27302 * the value is returned in the `hwrm_resp_hdr` upon completion.
27306 * The target ID of the command:
27307 * * 0x0-0xFFF8 - The function ID
27308 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27309 * * 0xFFFD - Reserved for user-space HWRM interface
27312 uint16_t target_id;
27314 * A physical address pointer pointing to a host buffer that the
27315 * command's response data will be written. This can be either a host
27316 * physical address (HPA) or a guest physical address (GPA) and must
27317 * point to a physically contiguous block of memory.
27319 uint64_t resp_addr;
27322 /* L2 Completion Ring (CR) */
27323 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
27325 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
27327 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
27328 /* RoCE Notification Completion Ring (ROCE_CR) */
27329 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
27331 * Rx Ring Group. This is to reset rx and aggregation in an atomic
27332 * operation. Completion ring associated with this ring group is
27335 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
27336 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
27337 HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP
27340 * Physical number of the ring. When ring type is rx_ring_grp, ring id
27341 * actually refers to ring group id.
27344 uint8_t unused_1[4];
27347 /* hwrm_ring_reset_output (size:128b/16B) */
27348 struct hwrm_ring_reset_output {
27349 /* The specific error status for the command. */
27350 uint16_t error_code;
27351 /* The HWRM command request type. */
27353 /* The sequence ID from the original command. */
27355 /* The length of the response data in number of bytes. */
27357 uint8_t unused_0[4];
27358 /* Position of consumer index after ring reset completes. */
27359 uint8_t consumer_idx[3];
27361 * This field is used in Output records to indicate that the output
27362 * is completely written to RAM. This field should be read as '1'
27363 * to indicate that the output has been completely written.
27364 * When writing a command completion or response to an internal processor,
27365 * the order of writes has to be such that this field is written last.
27375 /* hwrm_ring_cfg_input (size:256b/32B) */
27376 struct hwrm_ring_cfg_input {
27377 /* The HWRM command request type. */
27380 * The completion ring to send the completion event on. This should
27381 * be the NQ ID returned from the `nq_alloc` HWRM command.
27383 uint16_t cmpl_ring;
27385 * The sequence ID is used by the driver for tracking multiple
27386 * commands. This ID is treated as opaque data by the firmware and
27387 * the value is returned in the `hwrm_resp_hdr` upon completion.
27391 * The target ID of the command:
27392 * * 0x0-0xFFF8 - The function ID
27393 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27394 * * 0xFFFD - Reserved for user-space HWRM interface
27397 uint16_t target_id;
27399 * A physical address pointer pointing to a host buffer that the
27400 * command's response data will be written. This can be either a host
27401 * physical address (HPA) or a guest physical address (GPA) and must
27402 * point to a physically contiguous block of memory.
27404 uint64_t resp_addr;
27408 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27410 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27411 #define HWRM_RING_CFG_INPUT_RING_TYPE_LAST \
27412 HWRM_RING_CFG_INPUT_RING_TYPE_RX
27414 /* Physical number of the ring. */
27416 /* Ring config enable bits. */
27419 * For Rx rings, the incoming packet data can be placed at either
27420 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27422 * When '1', the received packet will be padded with 2B, 10B or 12B
27423 * of zeros at the front of the packet. The exact offset is specified
27424 * by rx_sop_pad_bytes parameter.
27425 * When '0', the received packet will not be padded.
27426 * Note that this flag is only used for Rx rings and is ignored
27427 * for all other rings included Rx Aggregation rings.
27429 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE \
27432 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27433 * When rings are allocated, the PCI function on which driver issues
27434 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27435 * the buffer descriptors (BDs) from those rings is assumed to issue
27436 * packet payload DMA using same PCI function. When proxy mode is
27437 * enabled, hardware can perform payload DMA using another PCI
27438 * function on same or different host.
27439 * When set to '0', the PCI function on which driver issues
27440 * HWRM_RING_CFG command is used for host payload DMA operation.
27441 * When set to '1', the host PCI function specified by proxy_fid is
27442 * used for host payload DMA operation.
27444 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE \
27447 * Tx ring packet source interface override, for Tx rings only.
27448 * When TX rings are allocated, the PCI function on which driver
27449 * issues HWRM_RING_CFG is assumed to be source interface of
27450 * packets sent from TX ring.
27451 * When set to '1', the host PCI function specified by proxy_fid
27452 * is used as source interface of the transmitted packets.
27454 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27456 /* The sq_id field is valid */
27457 #define HWRM_RING_CFG_INPUT_ENABLES_SQ_ID \
27459 /* Update completion ring ID associated with Tx or Rx ring. */
27460 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \
27463 * Proxy function FID value.
27464 * This value is only used when either proxy_mode_enable flag or
27465 * tx_proxy_svif_override is set to '1'.
27466 * When proxy_mode_enable is set to '1', it identifies a host PCI
27467 * function used for host payload DMA operations.
27468 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27469 * function as source interface for all transmitted packets from
27472 uint16_t proxy_fid;
27474 * Identifies the new scheduler queue (SQ) to associate with the ring.
27475 * Only valid for Tx rings.
27476 * A value of zero indicates that the Tx ring should be associated
27477 * with the default scheduler queue (SQ).
27481 * This field is valid for TX or Rx rings. This value identifies the
27482 * new completion ring ID to associate with the TX or Rx ring.
27484 uint16_t cmpl_ring_id;
27486 * Rx SOP padding amount in bytes.
27487 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27489 uint8_t rx_sop_pad_bytes;
27490 uint8_t unused_1[3];
27493 /* hwrm_ring_cfg_output (size:128b/16B) */
27494 struct hwrm_ring_cfg_output {
27495 /* The specific error status for the command. */
27496 uint16_t error_code;
27497 /* The HWRM command request type. */
27499 /* The sequence ID from the original command. */
27501 /* The length of the response data in number of bytes. */
27503 uint8_t unused_0[7];
27505 * This field is used in Output records to indicate that the output
27506 * is completely written to RAM. This field should be read as '1'
27507 * to indicate that the output has been completely written.
27508 * When writing a command completion or response to an internal
27509 * processor, the order of writes has to be such that this field is
27515 /******************
27517 ******************/
27520 /* hwrm_ring_qcfg_input (size:192b/24B) */
27521 struct hwrm_ring_qcfg_input {
27522 /* The HWRM command request type. */
27525 * The completion ring to send the completion event on. This should
27526 * be the NQ ID returned from the `nq_alloc` HWRM command.
27528 uint16_t cmpl_ring;
27530 * The sequence ID is used by the driver for tracking multiple
27531 * commands. This ID is treated as opaque data by the firmware and
27532 * the value is returned in the `hwrm_resp_hdr` upon completion.
27536 * The target ID of the command:
27537 * * 0x0-0xFFF8 - The function ID
27538 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27539 * * 0xFFFD - Reserved for user-space HWRM interface
27542 uint16_t target_id;
27544 * A physical address pointer pointing to a host buffer that the
27545 * command's response data will be written. This can be either a host
27546 * physical address (HPA) or a guest physical address (GPA) and must
27547 * point to a physically contiguous block of memory.
27549 uint64_t resp_addr;
27553 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
27555 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
27556 #define HWRM_RING_QCFG_INPUT_RING_TYPE_LAST \
27557 HWRM_RING_QCFG_INPUT_RING_TYPE_RX
27558 uint8_t unused_0[5];
27559 /* Physical number of the ring. */
27563 /* hwrm_ring_qcfg_output (size:192b/24B) */
27564 struct hwrm_ring_qcfg_output {
27565 /* The specific error status for the command. */
27566 uint16_t error_code;
27567 /* The HWRM command request type. */
27569 /* The sequence ID from the original command. */
27571 /* The length of the response data in number of bytes. */
27573 /* Ring config enable bits. */
27576 * For Rx rings, the incoming packet data can be placed at either
27577 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
27579 * When '1', the received packet will be padded with 2B, 10B or 12B
27580 * of zeros at the front of the packet. The exact offset is specified
27581 * by rx_sop_pad_bytes parameter.
27582 * When '0', the received packet will not be padded.
27583 * Note that this flag is only used for Rx rings and is ignored
27584 * for all other rings included Rx Aggregation rings.
27586 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE \
27589 * Proxy mode enable, for Tx, Rx and Rx aggregation rings only.
27590 * When rings are allocated, the PCI function on which driver issues
27591 * HWRM_RING_CFG command is assumed to own the rings. Hardware takes
27592 * the buffer descriptors (BDs) from those rings is assumed to issue
27593 * packet payload DMA using same PCI function. When proxy mode is
27594 * enabled, hardware can perform payload DMA using another PCI
27595 * function on same or different host.
27596 * When set to '0', the PCI function on which driver issues
27597 * HWRM_RING_CFG command is used for host payload DMA operation.
27598 * When set to '1', the host PCI function specified by proxy_fid is
27599 * used for host payload DMA operation.
27601 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE \
27604 * Tx ring packet source interface override, for Tx rings only.
27605 * When TX rings are allocated, the PCI function on which driver
27606 * issues HWRM_RING_CFG is assumed to be source interface of
27607 * packets sent from TX ring.
27608 * When set to '1', the host PCI function specified by proxy_fid is
27609 * used as source interface of the transmitted packets.
27611 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE \
27614 * Proxy function FID value.
27615 * This value is only used when either proxy_mode_enable flag or
27616 * tx_proxy_svif_override is set to '1'.
27617 * When proxy_mode_enable is set to '1', it identifies a host PCI
27618 * function used for host payload DMA operations.
27619 * When tx_proxy_src_intf is set to '1', it identifies a host PCI
27620 * function as source interface for all transmitted packets from the TX
27623 uint16_t proxy_fid;
27625 * Identifies the new scheduler queue (SQ) to associate with the ring.
27626 * Only valid for Tx rings.
27627 * A value of zero indicates that the Tx ring should be associated with
27628 * the default scheduler queue (SQ).
27632 * This field is used when ring_type is a TX or Rx ring.
27633 * This value indicates what completion ring the TX or Rx ring
27634 * is associated with.
27636 uint16_t cmpl_ring_id;
27638 * Rx SOP padding amount in bytes.
27639 * This value is only used when rx_sop_pad_enable flag is set to '1'.
27641 uint8_t rx_sop_pad_bytes;
27642 uint8_t unused_0[6];
27644 * This field is used in Output records to indicate that the output
27645 * is completely written to RAM. This field should be read as '1'
27646 * to indicate that the output has been completely written.
27647 * When writing a command completion or response to an internal
27648 * processor, the order of writes has to be such that this field is
27654 /**************************
27655 * hwrm_ring_aggint_qcaps *
27656 **************************/
27659 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */
27660 struct hwrm_ring_aggint_qcaps_input {
27661 /* The HWRM command request type. */
27664 * The completion ring to send the completion event on. This should
27665 * be the NQ ID returned from the `nq_alloc` HWRM command.
27667 uint16_t cmpl_ring;
27669 * The sequence ID is used by the driver for tracking multiple
27670 * commands. This ID is treated as opaque data by the firmware and
27671 * the value is returned in the `hwrm_resp_hdr` upon completion.
27675 * The target ID of the command:
27676 * * 0x0-0xFFF8 - The function ID
27677 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27678 * * 0xFFFD - Reserved for user-space HWRM interface
27681 uint16_t target_id;
27683 * A physical address pointer pointing to a host buffer that the
27684 * command's response data will be written. This can be either a host
27685 * physical address (HPA) or a guest physical address (GPA) and must
27686 * point to a physically contiguous block of memory.
27688 uint64_t resp_addr;
27691 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */
27692 struct hwrm_ring_aggint_qcaps_output {
27693 /* The specific error status for the command. */
27694 uint16_t error_code;
27695 /* The HWRM command request type. */
27697 /* The sequence ID from the original command. */
27699 /* The length of the response data in number of bytes. */
27701 uint32_t cmpl_params;
27703 * When this bit is set to '1', int_lat_tmr_min can be configured
27704 * on completion rings.
27706 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \
27709 * When this bit is set to '1', int_lat_tmr_max can be configured
27710 * on completion rings.
27712 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \
27715 * When this bit is set to '1', timer_reset can be enabled
27716 * on completion rings.
27718 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \
27721 * When this bit is set to '1', ring_idle can be enabled
27722 * on completion rings.
27724 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \
27727 * When this bit is set to '1', num_cmpl_dma_aggr can be configured
27728 * on completion rings.
27730 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \
27733 * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured
27734 * on completion rings.
27736 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \
27739 * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured
27740 * on completion rings.
27742 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \
27745 * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured
27746 * on completion rings.
27748 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \
27751 * When this bit is set to '1', num_cmpl_aggr_int can be configured
27752 * on completion rings.
27754 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \
27756 uint32_t nq_params;
27758 * When this bit is set to '1', int_lat_tmr_min can be configured
27759 * on notification queues.
27761 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \
27763 /* Minimum value for num_cmpl_dma_aggr */
27764 uint16_t num_cmpl_dma_aggr_min;
27765 /* Maximum value for num_cmpl_dma_aggr */
27766 uint16_t num_cmpl_dma_aggr_max;
27767 /* Minimum value for num_cmpl_dma_aggr_during_int */
27768 uint16_t num_cmpl_dma_aggr_during_int_min;
27769 /* Maximum value for num_cmpl_dma_aggr_during_int */
27770 uint16_t num_cmpl_dma_aggr_during_int_max;
27771 /* Minimum value for cmpl_aggr_dma_tmr */
27772 uint16_t cmpl_aggr_dma_tmr_min;
27773 /* Maximum value for cmpl_aggr_dma_tmr */
27774 uint16_t cmpl_aggr_dma_tmr_max;
27775 /* Minimum value for cmpl_aggr_dma_tmr_during_int */
27776 uint16_t cmpl_aggr_dma_tmr_during_int_min;
27777 /* Maximum value for cmpl_aggr_dma_tmr_during_int */
27778 uint16_t cmpl_aggr_dma_tmr_during_int_max;
27779 /* Minimum value for int_lat_tmr_min */
27780 uint16_t int_lat_tmr_min_min;
27781 /* Maximum value for int_lat_tmr_min */
27782 uint16_t int_lat_tmr_min_max;
27783 /* Minimum value for int_lat_tmr_max */
27784 uint16_t int_lat_tmr_max_min;
27785 /* Maximum value for int_lat_tmr_max */
27786 uint16_t int_lat_tmr_max_max;
27787 /* Minimum value for num_cmpl_aggr_int */
27788 uint16_t num_cmpl_aggr_int_min;
27789 /* Maximum value for num_cmpl_aggr_int */
27790 uint16_t num_cmpl_aggr_int_max;
27791 /* The units for timer parameters, in nanoseconds. */
27792 uint16_t timer_units;
27793 uint8_t unused_0[1];
27795 * This field is used in Output records to indicate that the output
27796 * is completely written to RAM. This field should be read as '1'
27797 * to indicate that the output has been completely written.
27798 * When writing a command completion or response to an internal processor,
27799 * the order of writes has to be such that this field is written last.
27804 /**************************************
27805 * hwrm_ring_cmpl_ring_qaggint_params *
27806 **************************************/
27809 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
27810 struct hwrm_ring_cmpl_ring_qaggint_params_input {
27811 /* The HWRM command request type. */
27814 * The completion ring to send the completion event on. This should
27815 * be the NQ ID returned from the `nq_alloc` HWRM command.
27817 uint16_t cmpl_ring;
27819 * The sequence ID is used by the driver for tracking multiple
27820 * commands. This ID is treated as opaque data by the firmware and
27821 * the value is returned in the `hwrm_resp_hdr` upon completion.
27825 * The target ID of the command:
27826 * * 0x0-0xFFF8 - The function ID
27827 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27828 * * 0xFFFD - Reserved for user-space HWRM interface
27831 uint16_t target_id;
27833 * A physical address pointer pointing to a host buffer that the
27834 * command's response data will be written. This can be either a host
27835 * physical address (HPA) or a guest physical address (GPA) and must
27836 * point to a physically contiguous block of memory.
27838 uint64_t resp_addr;
27839 /* Physical number of completion ring. */
27842 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \
27844 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
27846 * Set this flag to 1 when querying parameters on a notification
27847 * queue. Set this flag to 0 when querying parameters on a
27848 * completion queue or completion ring.
27850 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
27852 uint8_t unused_0[4];
27855 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
27856 struct hwrm_ring_cmpl_ring_qaggint_params_output {
27857 /* The specific error status for the command. */
27858 uint16_t error_code;
27859 /* The HWRM command request type. */
27861 /* The sequence ID from the original command. */
27863 /* The length of the response data in number of bytes. */
27867 * When this bit is set to '1', interrupt max
27868 * timer is reset whenever a completion is received.
27870 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
27873 * When this bit is set to '1', ring idle mode
27874 * aggregation will be enabled.
27876 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
27879 * Number of completions to aggregate before DMA
27880 * during the normal mode.
27882 uint16_t num_cmpl_dma_aggr;
27884 * Number of completions to aggregate before DMA
27885 * during the interrupt mode.
27887 uint16_t num_cmpl_dma_aggr_during_int;
27889 * Timer used to aggregate completions before
27890 * DMA during the normal mode (not in interrupt mode).
27892 uint16_t cmpl_aggr_dma_tmr;
27894 * Timer used to aggregate completions before
27895 * DMA when in interrupt mode.
27897 uint16_t cmpl_aggr_dma_tmr_during_int;
27898 /* Minimum time between two interrupts. */
27899 uint16_t int_lat_tmr_min;
27901 * Maximum wait time spent aggregating
27902 * completions before signaling the interrupt after the
27903 * interrupt is enabled.
27905 uint16_t int_lat_tmr_max;
27907 * Minimum number of completions aggregated before signaling
27910 uint16_t num_cmpl_aggr_int;
27911 uint8_t unused_0[7];
27913 * This field is used in Output records to indicate that the output
27914 * is completely written to RAM. This field should be read as '1'
27915 * to indicate that the output has been completely written.
27916 * When writing a command completion or response to an internal processor,
27917 * the order of writes has to be such that this field is written last.
27922 /*****************************************
27923 * hwrm_ring_cmpl_ring_cfg_aggint_params *
27924 *****************************************/
27927 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
27928 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
27929 /* The HWRM command request type. */
27932 * The completion ring to send the completion event on. This should
27933 * be the NQ ID returned from the `nq_alloc` HWRM command.
27935 uint16_t cmpl_ring;
27937 * The sequence ID is used by the driver for tracking multiple
27938 * commands. This ID is treated as opaque data by the firmware and
27939 * the value is returned in the `hwrm_resp_hdr` upon completion.
27943 * The target ID of the command:
27944 * * 0x0-0xFFF8 - The function ID
27945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27946 * * 0xFFFD - Reserved for user-space HWRM interface
27949 uint16_t target_id;
27951 * A physical address pointer pointing to a host buffer that the
27952 * command's response data will be written. This can be either a host
27953 * physical address (HPA) or a guest physical address (GPA) and must
27954 * point to a physically contiguous block of memory.
27956 uint64_t resp_addr;
27957 /* Physical number of completion ring. */
27961 * When this bit is set to '1', interrupt latency max
27962 * timer is reset whenever a completion is received.
27964 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
27967 * When this bit is set to '1', ring idle mode
27968 * aggregation will be enabled.
27970 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
27973 * Set this flag to 1 when configuring parameters on a
27974 * notification queue. Set this flag to 0 when configuring
27975 * parameters on a completion queue or completion ring.
27977 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
27980 * Number of completions to aggregate before DMA
27981 * during the normal mode.
27983 uint16_t num_cmpl_dma_aggr;
27985 * Number of completions to aggregate before DMA
27986 * during the interrupt mode.
27988 uint16_t num_cmpl_dma_aggr_during_int;
27990 * Timer used to aggregate completions before
27991 * DMA during the normal mode (not in interrupt mode).
27993 uint16_t cmpl_aggr_dma_tmr;
27995 * Timer used to aggregate completions before
27996 * DMA while in interrupt mode.
27998 uint16_t cmpl_aggr_dma_tmr_during_int;
27999 /* Minimum time between two interrupts. */
28000 uint16_t int_lat_tmr_min;
28002 * Maximum wait time spent aggregating
28003 * completions before signaling the interrupt after the
28004 * interrupt is enabled.
28006 uint16_t int_lat_tmr_max;
28008 * Minimum number of completions aggregated before signaling
28011 uint16_t num_cmpl_aggr_int;
28013 * Bitfield that indicates which parameters are to be applied. Only
28014 * required when configuring devices with notification queues, and
28015 * used in that case to set certain parameters on completion queues
28016 * and others on notification queues.
28020 * This bit must be '1' for the num_cmpl_dma_aggr field to be
28023 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
28026 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
28029 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
28032 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
28035 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
28038 * This bit must be '1' for the int_lat_tmr_min field to be
28041 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
28044 * This bit must be '1' for the int_lat_tmr_max field to be
28047 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
28050 * This bit must be '1' for the num_cmpl_aggr_int field to be
28053 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
28055 uint8_t unused_0[4];
28058 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
28059 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
28060 /* The specific error status for the command. */
28061 uint16_t error_code;
28062 /* The HWRM command request type. */
28064 /* The sequence ID from the original command. */
28066 /* The length of the response data in number of bytes. */
28068 uint8_t unused_0[7];
28070 * This field is used in Output records to indicate that the output
28071 * is completely written to RAM. This field should be read as '1'
28072 * to indicate that the output has been completely written.
28073 * When writing a command completion or response to an internal processor,
28074 * the order of writes has to be such that this field is written last.
28079 /***********************
28080 * hwrm_ring_grp_alloc *
28081 ***********************/
28084 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
28085 struct hwrm_ring_grp_alloc_input {
28086 /* The HWRM command request type. */
28089 * The completion ring to send the completion event on. This should
28090 * be the NQ ID returned from the `nq_alloc` HWRM command.
28092 uint16_t cmpl_ring;
28094 * The sequence ID is used by the driver for tracking multiple
28095 * commands. This ID is treated as opaque data by the firmware and
28096 * the value is returned in the `hwrm_resp_hdr` upon completion.
28100 * The target ID of the command:
28101 * * 0x0-0xFFF8 - The function ID
28102 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28103 * * 0xFFFD - Reserved for user-space HWRM interface
28106 uint16_t target_id;
28108 * A physical address pointer pointing to a host buffer that the
28109 * command's response data will be written. This can be either a host
28110 * physical address (HPA) or a guest physical address (GPA) and must
28111 * point to a physically contiguous block of memory.
28113 uint64_t resp_addr;
28115 * This value identifies the CR associated with the ring
28120 * This value identifies the main RR associated with the ring
28125 * This value identifies the aggregation RR associated with
28126 * the ring group. If this value is 0xFF... (All Fs), then no
28127 * Aggregation ring will be set.
28131 * This value identifies the statistics context associated
28132 * with the ring group.
28137 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
28138 struct hwrm_ring_grp_alloc_output {
28139 /* The specific error status for the command. */
28140 uint16_t error_code;
28141 /* The HWRM command request type. */
28143 /* The sequence ID from the original command. */
28145 /* The length of the response data in number of bytes. */
28148 * This is the ring group ID value. Use this value to program
28149 * the default ring group for the VNIC or as table entries
28150 * in an RSS/COS context.
28152 uint32_t ring_group_id;
28153 uint8_t unused_0[3];
28155 * This field is used in Output records to indicate that the output
28156 * is completely written to RAM. This field should be read as '1'
28157 * to indicate that the output has been completely written.
28158 * When writing a command completion or response to an internal processor,
28159 * the order of writes has to be such that this field is written last.
28164 /**********************
28165 * hwrm_ring_grp_free *
28166 **********************/
28169 /* hwrm_ring_grp_free_input (size:192b/24B) */
28170 struct hwrm_ring_grp_free_input {
28171 /* The HWRM command request type. */
28174 * The completion ring to send the completion event on. This should
28175 * be the NQ ID returned from the `nq_alloc` HWRM command.
28177 uint16_t cmpl_ring;
28179 * The sequence ID is used by the driver for tracking multiple
28180 * commands. This ID is treated as opaque data by the firmware and
28181 * the value is returned in the `hwrm_resp_hdr` upon completion.
28185 * The target ID of the command:
28186 * * 0x0-0xFFF8 - The function ID
28187 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28188 * * 0xFFFD - Reserved for user-space HWRM interface
28191 uint16_t target_id;
28193 * A physical address pointer pointing to a host buffer that the
28194 * command's response data will be written. This can be either a host
28195 * physical address (HPA) or a guest physical address (GPA) and must
28196 * point to a physically contiguous block of memory.
28198 uint64_t resp_addr;
28199 /* This is the ring group ID value. */
28200 uint32_t ring_group_id;
28201 uint8_t unused_0[4];
28204 /* hwrm_ring_grp_free_output (size:128b/16B) */
28205 struct hwrm_ring_grp_free_output {
28206 /* The specific error status for the command. */
28207 uint16_t error_code;
28208 /* The HWRM command request type. */
28210 /* The sequence ID from the original command. */
28212 /* The length of the response data in number of bytes. */
28214 uint8_t unused_0[7];
28216 * This field is used in Output records to indicate that the output
28217 * is completely written to RAM. This field should be read as '1'
28218 * to indicate that the output has been completely written.
28219 * When writing a command completion or response to an internal processor,
28220 * the order of writes has to be such that this field is written last.
28225 /**********************
28226 * hwrm_ring_sq_alloc *
28227 **********************/
28230 /* hwrm_ring_sq_alloc_input (size:1088b/136B) */
28231 struct hwrm_ring_sq_alloc_input {
28232 /* The HWRM command request type. */
28235 * The completion ring to send the completion event on. This should
28236 * be the NQ ID returned from the `nq_alloc` HWRM command.
28238 uint16_t cmpl_ring;
28240 * The sequence ID is used by the driver for tracking multiple
28241 * commands. This ID is treated as opaque data by the firmware and
28242 * the value is returned in the `hwrm_resp_hdr` upon completion.
28246 * The target ID of the command:
28247 * * 0x0-0xFFF8 - The function ID
28248 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28249 * * 0xFFFD - Reserved for user-space HWRM interface
28252 uint16_t target_id;
28254 * A physical address pointer pointing to a host buffer that the
28255 * command's response data will be written. This can be either a host
28256 * physical address (HPA) or a guest physical address (GPA) and must
28257 * point to a physically contiguous block of memory.
28259 uint64_t resp_addr;
28262 * This bit must be '1' for the tqm_ring0 fields to be
28265 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
28267 * This bit must be '1' for the tqm_ring1 fields to be
28270 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
28272 * This bit must be '1' for the tqm_ring2 fields to be
28275 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
28277 * This bit must be '1' for the tqm_ring3 fields to be
28280 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
28282 * This bit must be '1' for the tqm_ring4 fields to be
28285 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
28287 * This bit must be '1' for the tqm_ring5 fields to be
28290 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
28292 * This bit must be '1' for the tqm_ring6 fields to be
28295 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
28297 * This bit must be '1' for the tqm_ring7 fields to be
28300 #define HWRM_RING_SQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
28301 /* Reserved for future use. */
28303 /* TQM ring 0 page size and level. */
28304 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
28305 /* TQM ring 0 PBL indirect levels. */
28306 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
28307 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
28308 /* PBL pointer is physical start address. */
28309 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 \
28311 /* PBL pointer points to PTE table. */
28312 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 \
28315 * PBL pointer points to PDE table with each entry pointing to PTE
28318 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 \
28320 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LAST \
28321 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2
28322 /* TQM ring 0 page size. */
28323 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
28324 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_SFT 4
28326 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K \
28327 (UINT32_C(0x0) << 4)
28329 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K \
28330 (UINT32_C(0x1) << 4)
28332 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K \
28333 (UINT32_C(0x2) << 4)
28335 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M \
28336 (UINT32_C(0x3) << 4)
28338 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M \
28339 (UINT32_C(0x4) << 4)
28341 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G \
28342 (UINT32_C(0x5) << 4)
28343 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_LAST \
28344 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G
28345 /* TQM ring 1 page size and level. */
28346 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
28347 /* TQM ring 1 PBL indirect levels. */
28348 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
28349 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
28350 /* PBL pointer is physical start address. */
28351 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 \
28353 /* PBL pointer points to PTE table. */
28354 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 \
28357 * PBL pointer points to PDE table with each entry pointing to PTE
28360 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 \
28362 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LAST \
28363 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2
28364 /* TQM ring 1 page size. */
28365 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
28366 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_SFT 4
28368 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K \
28369 (UINT32_C(0x0) << 4)
28371 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K \
28372 (UINT32_C(0x1) << 4)
28374 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K \
28375 (UINT32_C(0x2) << 4)
28377 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M \
28378 (UINT32_C(0x3) << 4)
28380 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M \
28381 (UINT32_C(0x4) << 4)
28383 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G \
28384 (UINT32_C(0x5) << 4)
28385 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_LAST \
28386 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G
28387 /* TQM ring 2 page size and level. */
28388 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
28389 /* TQM ring 2 PBL indirect levels. */
28390 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
28391 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
28392 /* PBL pointer is physical start address. */
28393 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 \
28395 /* PBL pointer points to PTE table. */
28396 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 \
28399 * PBL pointer points to PDE table with each entry pointing to PTE
28402 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 \
28404 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LAST \
28405 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2
28406 /* TQM ring 2 page size. */
28407 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
28408 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_SFT 4
28410 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K \
28411 (UINT32_C(0x0) << 4)
28413 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K \
28414 (UINT32_C(0x1) << 4)
28416 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K \
28417 (UINT32_C(0x2) << 4)
28419 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M \
28420 (UINT32_C(0x3) << 4)
28422 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M \
28423 (UINT32_C(0x4) << 4)
28425 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G \
28426 (UINT32_C(0x5) << 4)
28427 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_LAST \
28428 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G
28429 /* TQM ring 3 page size and level. */
28430 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
28431 /* TQM ring 3 PBL indirect levels. */
28432 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
28433 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
28434 /* PBL pointer is physical start address. */
28435 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 \
28437 /* PBL pointer points to PTE table. */
28438 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 \
28441 * PBL pointer points to PDE table with each entry pointing to PTE
28444 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 \
28446 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LAST \
28447 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2
28448 /* TQM ring 3 page size. */
28449 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
28450 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_SFT 4
28452 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K \
28453 (UINT32_C(0x0) << 4)
28455 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K \
28456 (UINT32_C(0x1) << 4)
28458 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K \
28459 (UINT32_C(0x2) << 4)
28461 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M \
28462 (UINT32_C(0x3) << 4)
28464 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M \
28465 (UINT32_C(0x4) << 4)
28467 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G \
28468 (UINT32_C(0x5) << 4)
28469 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_LAST \
28470 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G
28471 /* TQM ring 4 page size and level. */
28472 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
28473 /* TQM ring 4 PBL indirect levels. */
28474 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
28475 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
28476 /* PBL pointer is physical start address. */
28477 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 \
28479 /* PBL pointer points to PTE table. */
28480 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 \
28483 * PBL pointer points to PDE table with each entry pointing to PTE
28486 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 \
28488 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LAST \
28489 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2
28490 /* TQM ring 4 page size. */
28491 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
28492 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_SFT 4
28494 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K \
28495 (UINT32_C(0x0) << 4)
28497 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K \
28498 (UINT32_C(0x1) << 4)
28500 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K \
28501 (UINT32_C(0x2) << 4)
28503 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M \
28504 (UINT32_C(0x3) << 4)
28506 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M \
28507 (UINT32_C(0x4) << 4)
28509 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G \
28510 (UINT32_C(0x5) << 4)
28511 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_LAST \
28512 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G
28513 /* TQM ring 5 page size and level. */
28514 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
28515 /* TQM ring 5 PBL indirect levels. */
28516 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
28517 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
28518 /* PBL pointer is physical start address. */
28519 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 \
28521 /* PBL pointer points to PTE table. */
28522 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 \
28525 * PBL pointer points to PDE table with each entry pointing to PTE
28528 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 \
28530 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LAST \
28531 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2
28532 /* TQM ring 5 page size. */
28533 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
28534 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_SFT 4
28536 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K \
28537 (UINT32_C(0x0) << 4)
28539 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K \
28540 (UINT32_C(0x1) << 4)
28542 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K \
28543 (UINT32_C(0x2) << 4)
28545 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M \
28546 (UINT32_C(0x3) << 4)
28548 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M \
28549 (UINT32_C(0x4) << 4)
28551 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G \
28552 (UINT32_C(0x5) << 4)
28553 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_LAST \
28554 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G
28555 /* TQM ring 6 page size and level. */
28556 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
28557 /* TQM ring 6 PBL indirect levels. */
28558 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
28559 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
28560 /* PBL pointer is physical start address. */
28561 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 \
28563 /* PBL pointer points to PTE table. */
28564 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 \
28567 * PBL pointer points to PDE table with each entry pointing to PTE
28570 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 \
28572 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LAST \
28573 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2
28574 /* TQM ring 6 page size. */
28575 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
28576 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_SFT 4
28578 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K \
28579 (UINT32_C(0x0) << 4)
28581 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K \
28582 (UINT32_C(0x1) << 4)
28584 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K \
28585 (UINT32_C(0x2) << 4)
28587 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M \
28588 (UINT32_C(0x3) << 4)
28590 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M \
28591 (UINT32_C(0x4) << 4)
28593 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G \
28594 (UINT32_C(0x5) << 4)
28595 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_LAST \
28596 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G
28597 /* TQM ring 7 page size and level. */
28598 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
28599 /* TQM ring 7 PBL indirect levels. */
28600 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
28601 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
28602 /* PBL pointer is physical start address. */
28603 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 \
28605 /* PBL pointer points to PTE table. */
28606 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 \
28609 * PBL pointer points to PDE table with each entry pointing to PTE
28612 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 \
28614 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LAST \
28615 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2
28616 /* TQM ring 7 page size. */
28617 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
28618 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_SFT 4
28620 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K \
28621 (UINT32_C(0x0) << 4)
28623 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K \
28624 (UINT32_C(0x1) << 4)
28626 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K \
28627 (UINT32_C(0x2) << 4)
28629 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M \
28630 (UINT32_C(0x3) << 4)
28632 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M \
28633 (UINT32_C(0x4) << 4)
28635 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G \
28636 (UINT32_C(0x5) << 4)
28637 #define HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_LAST \
28638 HWRM_RING_SQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G
28639 /* TQM ring 0 page directory. */
28640 uint64_t tqm_ring0_page_dir;
28641 /* TQM ring 1 page directory. */
28642 uint64_t tqm_ring1_page_dir;
28643 /* TQM ring 2 page directory. */
28644 uint64_t tqm_ring2_page_dir;
28645 /* TQM ring 3 page directory. */
28646 uint64_t tqm_ring3_page_dir;
28647 /* TQM ring 4 page directory. */
28648 uint64_t tqm_ring4_page_dir;
28649 /* TQM ring 5 page directory. */
28650 uint64_t tqm_ring5_page_dir;
28651 /* TQM ring 6 page directory. */
28652 uint64_t tqm_ring6_page_dir;
28653 /* TQM ring 7 page directory. */
28654 uint64_t tqm_ring7_page_dir;
28656 * Number of TQM ring 0 entries.
28658 * TQM fastpath rings should be sized large enough to accommodate the
28659 * maximum number of QPs (either L2 or RoCE, or both if shared)
28660 * that can be enqueued to the TQM ring.
28662 * Note that TQM ring sizes cannot be extended while the system is
28663 * operational. If a PF driver needs to extend a TQM ring, it needs
28664 * to delete the SQ and then reallocate it.
28666 uint32_t tqm_ring0_num_entries;
28668 * Number of TQM ring 1 entries.
28670 * TQM fastpath rings should be sized large enough to accommodate the
28671 * maximum number of QPs (either L2 or RoCE, or both if shared)
28672 * that can be enqueued to the TQM ring.
28674 * Note that TQM ring sizes cannot be extended while the system is
28675 * operational. If a PF driver needs to extend a TQM ring, it needs
28676 * to delete the SQ and then reallocate it.
28678 uint32_t tqm_ring1_num_entries;
28680 * Number of TQM ring 2 entries.
28682 * TQM fastpath rings should be sized large enough to accommodate the
28683 * maximum number of QPs (either L2 or RoCE, or both if shared)
28684 * that can be enqueued to the TQM ring.
28686 * Note that TQM ring sizes cannot be extended while the system is
28687 * operational. If a PF driver needs to extend a TQM ring, it needs
28688 * to delete the SQ and then reallocate it.
28690 uint32_t tqm_ring2_num_entries;
28692 * Number of TQM ring 3 entries.
28694 * TQM fastpath rings should be sized large enough to accommodate the
28695 * maximum number of QPs (either L2 or RoCE, or both if shared)
28696 * that can be enqueued to the TQM ring.
28698 * Note that TQM ring sizes cannot be extended while the system is
28699 * operational. If a PF driver needs to extend a TQM ring, it needs
28700 * to delete the SQ and then reallocate it.
28702 uint32_t tqm_ring3_num_entries;
28704 * Number of TQM ring 4 entries.
28706 * TQM fastpath rings should be sized large enough to accommodate the
28707 * maximum number of QPs (either L2 or RoCE, or both if shared)
28708 * that can be enqueued to the TQM ring.
28710 * Note that TQM ring sizes cannot be extended while the system is
28711 * operational. If a PF driver needs to extend a TQM ring, it needs
28712 * to delete the SQ and then reallocate it.
28714 uint32_t tqm_ring4_num_entries;
28716 * Number of TQM ring 5 entries.
28718 * TQM fastpath rings should be sized large enough to accommodate the
28719 * maximum number of QPs (either L2 or RoCE, or both if shared)
28720 * that can be enqueued to the TQM ring.
28722 * Note that TQM ring sizes cannot be extended while the system is
28723 * operational. If a PF driver needs to extend a TQM ring, it needs
28724 * to delete the SQ and then reallocate it.
28726 uint32_t tqm_ring5_num_entries;
28728 * Number of TQM ring 6 entries.
28730 * TQM fastpath rings should be sized large enough to accommodate the
28731 * maximum number of QPs (either L2 or RoCE, or both if shared)
28732 * that can be enqueued to the TQM ring.
28734 * Note that TQM ring sizes cannot be extended while the system is
28735 * operational. If a PF driver needs to extend a TQM ring, it needs
28736 * to delete the SQ and then reallocate it.
28738 uint32_t tqm_ring6_num_entries;
28740 * Number of TQM ring 7 entries.
28742 * TQM fastpath rings should be sized large enough to accommodate the
28743 * maximum number of QPs (either L2 or RoCE, or both if shared)
28744 * that can be enqueued to the TQM ring.
28746 * Note that TQM ring sizes cannot be extended while the system is
28747 * operational. If a PF driver needs to extend a TQM ring, it needs
28748 * to delete the SQ and then reallocate it.
28750 uint32_t tqm_ring7_num_entries;
28751 /* Number of bytes that have been allocated for each context entry. */
28752 uint16_t tqm_entry_size;
28753 uint8_t unused_0[6];
28756 /* hwrm_ring_sq_alloc_output (size:128b/16B) */
28757 struct hwrm_ring_sq_alloc_output {
28758 /* The specific error status for the command. */
28759 uint16_t error_code;
28760 /* The HWRM command request type. */
28762 /* The sequence ID from the original command. */
28764 /* The length of the response data in number of bytes. */
28767 * This is an identifier for the SQ to be used in other HWRM commands
28768 * that need to reference this SQ. This value is greater than zero
28769 * (i.e. a sq_id of zero references the default SQ).
28772 uint8_t unused_0[5];
28774 * This field is used in Output records to indicate that the output
28775 * is completely written to RAM. This field should be read as '1'
28776 * to indicate that the output has been completely written.
28777 * When writing a command completion or response to an internal processor,
28778 * the order of writes has to be such that this field is written last.
28783 /********************
28784 * hwrm_ring_sq_cfg *
28785 ********************/
28788 /* hwrm_ring_sq_cfg_input (size:768b/96B) */
28789 struct hwrm_ring_sq_cfg_input {
28790 /* The HWRM command request type. */
28793 * The completion ring to send the completion event on. This should
28794 * be the NQ ID returned from the `nq_alloc` HWRM command.
28796 uint16_t cmpl_ring;
28798 * The sequence ID is used by the driver for tracking multiple
28799 * commands. This ID is treated as opaque data by the firmware and
28800 * the value is returned in the `hwrm_resp_hdr` upon completion.
28804 * The target ID of the command:
28805 * * 0x0-0xFFF8 - The function ID
28806 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28807 * * 0xFFFD - Reserved for user-space HWRM interface
28810 uint16_t target_id;
28812 * A physical address pointer pointing to a host buffer that the
28813 * command's response data will be written. This can be either a host
28814 * physical address (HPA) or a guest physical address (GPA) and must
28815 * point to a physically contiguous block of memory.
28817 uint64_t resp_addr;
28819 * Identifies the SQ being configured. A sq_id of zero refers to the
28824 * This field is an 8 bit bitmap that indicates which TCs are enabled
28825 * in this SQ. Bit 0 represents traffic class 0 and bit 7 represents
28828 uint8_t tc_enabled;
28831 /* The tc_max_bw array and the max_bw parameters are valid */
28832 #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED \
28834 /* The tc_min_bw array is valid */
28835 #define HWRM_RING_SQ_CFG_INPUT_FLAGS_TC_MIN_BW_ENABLED \
28837 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28838 uint32_t max_bw_tc0;
28839 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28840 uint32_t max_bw_tc1;
28841 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28842 uint32_t max_bw_tc2;
28843 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28844 uint32_t max_bw_tc3;
28845 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28846 uint32_t max_bw_tc4;
28847 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28848 uint32_t max_bw_tc5;
28849 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28850 uint32_t max_bw_tc6;
28851 /* Maximum bandwidth of the traffic class, specified in Mbps. */
28852 uint32_t max_bw_tc7;
28854 * Bandwidth reservation for the traffic class, specified in Mbps.
28855 * A value of zero signifies that traffic belonging to this class
28856 * shares the bandwidth reservation for the same traffic class of
28859 uint32_t min_bw_tc0;
28861 * Bandwidth reservation for the traffic class, specified in Mbps.
28862 * A value of zero signifies that traffic belonging to this class
28863 * shares the bandwidth reservation for the same traffic class of
28866 uint32_t min_bw_tc1;
28868 * Bandwidth reservation for the traffic class, specified in Mbps.
28869 * A value of zero signifies that traffic belonging to this class
28870 * shares the bandwidth reservation for the same traffic class of
28873 uint32_t min_bw_tc2;
28875 * Bandwidth reservation for the traffic class, specified in Mbps.
28876 * A value of zero signifies that traffic belonging to this class
28877 * shares the bandwidth reservation for the same traffic class of
28880 uint32_t min_bw_tc3;
28882 * Bandwidth reservation for the traffic class, specified in Mbps.
28883 * A value of zero signifies that traffic belonging to this class
28884 * shares the bandwidth reservation for the same traffic class of
28887 uint32_t min_bw_tc4;
28889 * Bandwidth reservation for the traffic class, specified in Mbps.
28890 * A value of zero signifies that traffic belonging to this class
28891 * shares the bandwidth reservation for the same traffic class of
28894 uint32_t min_bw_tc5;
28896 * Bandwidth reservation for the traffic class, specified in Mbps.
28897 * A value of zero signifies that traffic belonging to this class
28898 * shares the bandwidth reservation for the same traffic class of
28901 uint32_t min_bw_tc6;
28903 * Bandwidth reservation for the traffic class, specified in Mbps.
28904 * A value of zero signifies that traffic belonging to this class
28905 * shares the bandwidth reservation for the same traffic class of
28908 uint32_t min_bw_tc7;
28910 * Indicates the max bandwidth for all enabled traffic classes in
28911 * this SQ, specified in Mbps.
28914 uint8_t unused_1[4];
28917 /* hwrm_ring_sq_cfg_output (size:128b/16B) */
28918 struct hwrm_ring_sq_cfg_output {
28919 /* The specific error status for the command. */
28920 uint16_t error_code;
28921 /* The HWRM command request type. */
28923 /* The sequence ID from the original command. */
28925 /* The length of the response data in number of bytes. */
28927 uint8_t unused_0[7];
28929 * This field is used in Output records to indicate that the output
28930 * is completely written to RAM. This field should be read as '1'
28931 * to indicate that the output has been completely written.
28932 * When writing a command completion or response to an internal processor,
28933 * the order of writes has to be such that this field is written last.
28938 /*********************
28939 * hwrm_ring_sq_free *
28940 *********************/
28943 /* hwrm_ring_sq_free_input (size:192b/24B) */
28944 struct hwrm_ring_sq_free_input {
28945 /* The HWRM command request type. */
28948 * The completion ring to send the completion event on. This should
28949 * be the NQ ID returned from the `nq_alloc` HWRM command.
28951 uint16_t cmpl_ring;
28953 * The sequence ID is used by the driver for tracking multiple
28954 * commands. This ID is treated as opaque data by the firmware and
28955 * the value is returned in the `hwrm_resp_hdr` upon completion.
28959 * The target ID of the command:
28960 * * 0x0-0xFFF8 - The function ID
28961 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28962 * * 0xFFFD - Reserved for user-space HWRM interface
28965 uint16_t target_id;
28967 * A physical address pointer pointing to a host buffer that the
28968 * command's response data will be written. This can be either a host
28969 * physical address (HPA) or a guest physical address (GPA) and must
28970 * point to a physically contiguous block of memory.
28972 uint64_t resp_addr;
28973 /* Identifies the SQ being freed. */
28975 uint8_t unused_0[6];
28978 /* hwrm_ring_sq_free_output (size:128b/16B) */
28979 struct hwrm_ring_sq_free_output {
28980 /* The specific error status for the command. */
28981 uint16_t error_code;
28982 /* The HWRM command request type. */
28984 /* The sequence ID from the original command. */
28986 /* The length of the response data in number of bytes. */
28988 uint8_t unused_0[7];
28990 * This field is used in Output records to indicate that the output
28991 * is completely written to RAM. This field should be read as '1'
28992 * to indicate that the output has been completely written.
28993 * When writing a command completion or response to an internal processor,
28994 * the order of writes has to be such that this field is written last.
28999 * special reserved flow ID to identify per function default
29000 * flows for vSwitch offload
29002 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
29004 * special reserved flow ID to identify per function RoCEv1
29007 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
29009 * special reserved flow ID to identify per function RoCEv2
29012 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
29014 * special reserved flow ID to identify per function RoCEv2
29017 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
29019 /****************************
29020 * hwrm_cfa_l2_filter_alloc *
29021 ****************************/
29024 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
29025 struct hwrm_cfa_l2_filter_alloc_input {
29026 /* The HWRM command request type. */
29029 * The completion ring to send the completion event on. This should
29030 * be the NQ ID returned from the `nq_alloc` HWRM command.
29032 uint16_t cmpl_ring;
29034 * The sequence ID is used by the driver for tracking multiple
29035 * commands. This ID is treated as opaque data by the firmware and
29036 * the value is returned in the `hwrm_resp_hdr` upon completion.
29040 * The target ID of the command:
29041 * * 0x0-0xFFF8 - The function ID
29042 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29043 * * 0xFFFD - Reserved for user-space HWRM interface
29046 uint16_t target_id;
29048 * A physical address pointer pointing to a host buffer that the
29049 * command's response data will be written. This can be either a host
29050 * physical address (HPA) or a guest physical address (GPA) and must
29051 * point to a physically contiguous block of memory.
29053 uint64_t resp_addr;
29056 * Enumeration denoting the RX, TX type of the resource.
29057 * This enumeration is used for resources that are similar for both
29058 * TX and RX paths of the chip.
29060 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
29063 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
29066 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
29068 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
29069 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
29070 /* Setting of this flag indicates the applicability to the loopback path. */
29071 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
29074 * Setting of this flag indicates drop action. If this flag is not set,
29075 * then it should be considered accept action.
29077 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
29080 * If this flag is set, all t_l2_* fields are invalid
29081 * and they should not be specified.
29082 * If this flag is set, then l2_* fields refer to
29083 * fields of outermost L2 header.
29085 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
29088 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29089 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29091 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \
29093 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4
29094 /* To support old drivers */
29095 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29096 (UINT32_C(0x0) << 4)
29097 /* Only L2 traffic */
29098 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \
29099 (UINT32_C(0x1) << 4)
29100 /* Roce & L2 traffic */
29101 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \
29102 (UINT32_C(0x2) << 4)
29103 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
29104 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
29106 * Setting of this flag indicates that no XDP filter is created with
29108 * 0 - legacy behavior, XDP filter is created with L2 filter
29109 * 1 - XDP filter won't be created with L2 filter
29111 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
29114 * Setting this flag to 1 indicate the L2 fields in this command
29115 * pertain to source fields. Setting this flag to 0 indicate the
29116 * L2 fields in this command pertain to the destination fields
29117 * and this is the default/legacy behavior.
29119 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
29123 * This bit must be '1' for the l2_addr field to be
29126 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
29129 * This bit must be '1' for the l2_addr_mask field to be
29132 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
29135 * This bit must be '1' for the l2_ovlan field to be
29138 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
29141 * This bit must be '1' for the l2_ovlan_mask field to be
29144 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
29147 * This bit must be '1' for the l2_ivlan field to be
29150 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
29153 * This bit must be '1' for the l2_ivlan_mask field to be
29156 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
29159 * This bit must be '1' for the t_l2_addr field to be
29162 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
29165 * This bit must be '1' for the t_l2_addr_mask field to be
29168 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
29171 * This bit must be '1' for the t_l2_ovlan field to be
29174 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
29177 * This bit must be '1' for the t_l2_ovlan_mask field to be
29180 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
29183 * This bit must be '1' for the t_l2_ivlan field to be
29186 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
29189 * This bit must be '1' for the t_l2_ivlan_mask field to be
29192 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
29195 * This bit must be '1' for the src_type field to be
29198 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
29201 * This bit must be '1' for the src_id field to be
29204 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
29207 * This bit must be '1' for the tunnel_type field to be
29210 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
29213 * This bit must be '1' for the dst_id field to be
29216 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
29219 * This bit must be '1' for the mirror_vnic_id field to be
29222 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
29225 * This bit must be '1' for the num_vlans field to be
29228 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
29231 * This bit must be '1' for the t_num_vlans field to be
29234 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
29237 * This value sets the match value for the L2 MAC address.
29238 * Destination MAC address for RX path.
29239 * Source MAC address for TX path.
29241 uint8_t l2_addr[6];
29242 /* This value sets the match value for the number of VLANs. */
29245 * This value sets the match value for the number of VLANs
29246 * in the tunnel headers.
29248 uint8_t t_num_vlans;
29250 * This value sets the mask value for the L2 address.
29251 * A value of 0 will mask the corresponding bit from
29254 uint8_t l2_addr_mask[6];
29255 /* This value sets VLAN ID value for outer VLAN. */
29258 * This value sets the mask value for the ovlan id.
29259 * A value of 0 will mask the corresponding bit from
29262 uint16_t l2_ovlan_mask;
29263 /* This value sets VLAN ID value for inner VLAN. */
29266 * This value sets the mask value for the ivlan id.
29267 * A value of 0 will mask the corresponding bit from
29270 uint16_t l2_ivlan_mask;
29271 uint8_t unused_1[2];
29273 * This value sets the match value for the tunnel
29275 * Destination MAC address for RX path.
29276 * Source MAC address for TX path.
29278 uint8_t t_l2_addr[6];
29279 uint8_t unused_2[2];
29281 * This value sets the mask value for the tunnel L2
29283 * A value of 0 will mask the corresponding bit from
29286 uint8_t t_l2_addr_mask[6];
29287 /* This value sets VLAN ID value for tunnel outer VLAN. */
29288 uint16_t t_l2_ovlan;
29290 * This value sets the mask value for the tunnel ovlan id.
29291 * A value of 0 will mask the corresponding bit from
29294 uint16_t t_l2_ovlan_mask;
29295 /* This value sets VLAN ID value for tunnel inner VLAN. */
29296 uint16_t t_l2_ivlan;
29298 * This value sets the mask value for the tunnel ivlan id.
29299 * A value of 0 will mask the corresponding bit from
29302 uint16_t t_l2_ivlan_mask;
29303 /* This value identifies the type of source of the packet. */
29306 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
29307 /* Physical function */
29308 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
29309 /* Virtual function */
29310 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
29311 /* Virtual NIC of a function */
29312 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
29313 /* Embedded processor for CFA management */
29314 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
29315 /* Embedded processor for OOB management */
29316 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
29317 /* Embedded processor for RoCE */
29318 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
29319 /* Embedded processor for network proxy functions */
29320 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
29321 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
29322 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
29325 * This value is the id of the source.
29326 * For a network port, it represents port_id.
29327 * For a physical function, it represents fid.
29328 * For a virtual function, it represents vf_id.
29329 * For a vnic, it represents vnic_id.
29330 * For embedded processors, this id is not valid.
29333 * 1. The function ID is implied if it src_id is
29334 * not provided for a src_type that is either
29338 uint8_t tunnel_type;
29340 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
29342 /* Virtual eXtensible Local Area Network (VXLAN) */
29343 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
29345 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
29346 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
29348 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
29349 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
29352 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
29354 /* Generic Network Virtualization Encapsulation (Geneve) */
29355 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
29357 /* Multi-Protocol Label Switching (MPLS) */
29358 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
29360 /* Stateless Transport Tunnel (STT) */
29361 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
29363 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
29364 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
29366 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
29367 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
29369 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
29370 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
29372 /* Use fixed layer 2 ether type of 0xFFFF */
29373 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
29375 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
29376 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
29378 /* Any tunneled traffic */
29379 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
29381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
29382 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
29385 * If set, this value shall represent the
29386 * Logical VNIC ID of the destination VNIC for the RX
29387 * path and network port id of the destination port for
29392 * Logical VNIC ID of the VNIC where traffic is
29395 uint16_t mirror_vnic_id;
29397 * This hint is provided to help in placing
29398 * the filter in the filter table.
29401 /* No preference */
29402 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
29404 /* Above the given filter */
29405 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
29407 /* Below the given filter */
29408 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
29410 /* As high as possible */
29411 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
29413 /* As low as possible */
29414 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
29416 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
29417 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
29421 * This is the ID of the filter that goes along with
29424 * This field is valid only for the following values.
29425 * 1 - Above the given filter
29426 * 2 - Below the given filter
29428 uint64_t l2_filter_id_hint;
29431 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
29432 struct hwrm_cfa_l2_filter_alloc_output {
29433 /* The specific error status for the command. */
29434 uint16_t error_code;
29435 /* The HWRM command request type. */
29437 /* The sequence ID from the original command. */
29439 /* The length of the response data in number of bytes. */
29442 * This value identifies a set of CFA data structures used for an L2
29445 uint64_t l2_filter_id;
29447 * The flow id value in bit 0-29 is the actual ID of the flow
29448 * associated with this filter and it shall be used to match
29449 * and associate the flow identifier returned in completion
29450 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
29451 * shall indicate no valid flow id.
29454 /* Indicate the flow id value. */
29455 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
29456 UINT32_C(0x3fffffff)
29457 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
29458 /* Indicate type of the flow. */
29459 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
29460 UINT32_C(0x40000000)
29462 * If this bit set to 0, then it indicates that the flow is
29465 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
29466 (UINT32_C(0x0) << 30)
29468 * If this bit is set to 1, then it indicates that the flow is
29471 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
29472 (UINT32_C(0x1) << 30)
29473 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
29474 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
29475 /* Indicate the flow direction. */
29476 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
29477 UINT32_C(0x80000000)
29478 /* If this bit set to 0, then it indicates rx flow. */
29479 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
29480 (UINT32_C(0x0) << 31)
29481 /* If this bit is set to 1, then it indicates that tx flow. */
29482 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
29483 (UINT32_C(0x1) << 31)
29484 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
29485 HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
29486 uint8_t unused_0[3];
29488 * This field is used in Output records to indicate that the output
29489 * is completely written to RAM. This field should be read as '1'
29490 * to indicate that the output has been completely written.
29491 * When writing a command completion or response to an internal processor,
29492 * the order of writes has to be such that this field is written last.
29497 /***************************
29498 * hwrm_cfa_l2_filter_free *
29499 ***************************/
29502 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
29503 struct hwrm_cfa_l2_filter_free_input {
29504 /* The HWRM command request type. */
29507 * The completion ring to send the completion event on. This should
29508 * be the NQ ID returned from the `nq_alloc` HWRM command.
29510 uint16_t cmpl_ring;
29512 * The sequence ID is used by the driver for tracking multiple
29513 * commands. This ID is treated as opaque data by the firmware and
29514 * the value is returned in the `hwrm_resp_hdr` upon completion.
29518 * The target ID of the command:
29519 * * 0x0-0xFFF8 - The function ID
29520 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29521 * * 0xFFFD - Reserved for user-space HWRM interface
29524 uint16_t target_id;
29526 * A physical address pointer pointing to a host buffer that the
29527 * command's response data will be written. This can be either a host
29528 * physical address (HPA) or a guest physical address (GPA) and must
29529 * point to a physically contiguous block of memory.
29531 uint64_t resp_addr;
29533 * This value identifies a set of CFA data structures used for an L2
29536 uint64_t l2_filter_id;
29539 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
29540 struct hwrm_cfa_l2_filter_free_output {
29541 /* The specific error status for the command. */
29542 uint16_t error_code;
29543 /* The HWRM command request type. */
29545 /* The sequence ID from the original command. */
29547 /* The length of the response data in number of bytes. */
29549 uint8_t unused_0[7];
29551 * This field is used in Output records to indicate that the output
29552 * is completely written to RAM. This field should be read as '1'
29553 * to indicate that the output has been completely written.
29554 * When writing a command completion or response to an internal processor,
29555 * the order of writes has to be such that this field is written last.
29560 /**************************
29561 * hwrm_cfa_l2_filter_cfg *
29562 **************************/
29565 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
29566 struct hwrm_cfa_l2_filter_cfg_input {
29567 /* The HWRM command request type. */
29570 * The completion ring to send the completion event on. This should
29571 * be the NQ ID returned from the `nq_alloc` HWRM command.
29573 uint16_t cmpl_ring;
29575 * The sequence ID is used by the driver for tracking multiple
29576 * commands. This ID is treated as opaque data by the firmware and
29577 * the value is returned in the `hwrm_resp_hdr` upon completion.
29581 * The target ID of the command:
29582 * * 0x0-0xFFF8 - The function ID
29583 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29584 * * 0xFFFD - Reserved for user-space HWRM interface
29587 uint16_t target_id;
29589 * A physical address pointer pointing to a host buffer that the
29590 * command's response data will be written. This can be either a host
29591 * physical address (HPA) or a guest physical address (GPA) and must
29592 * point to a physically contiguous block of memory.
29594 uint64_t resp_addr;
29597 * Enumeration denoting the RX, TX type of the resource.
29598 * This enumeration is used for resources that are similar for both
29599 * TX and RX paths of the chip.
29601 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \
29604 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \
29607 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \
29609 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
29610 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
29612 * Setting of this flag indicates drop action. If this flag is not set,
29613 * then it should be considered accept action.
29615 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \
29618 * Enumeration denoting NO_ROCE_L2 to support old drivers.
29619 * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic
29621 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \
29623 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2
29624 /* To support old drivers */
29625 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \
29626 (UINT32_C(0x0) << 2)
29627 /* Only L2 traffic */
29628 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \
29629 (UINT32_C(0x1) << 2)
29630 /* Roce & L2 traffic */
29631 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \
29632 (UINT32_C(0x2) << 2)
29633 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \
29634 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE
29637 * This bit must be '1' for the dst_id field to be
29640 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
29643 * This bit must be '1' for the new_mirror_vnic_id field to be
29646 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
29649 * This value identifies a set of CFA data structures used for an L2
29652 uint64_t l2_filter_id;
29654 * If set, this value shall represent the
29655 * Logical VNIC ID of the destination VNIC for the RX
29656 * path and network port id of the destination port for
29661 * New Logical VNIC ID of the VNIC where traffic is
29664 uint32_t new_mirror_vnic_id;
29667 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
29668 struct hwrm_cfa_l2_filter_cfg_output {
29669 /* The specific error status for the command. */
29670 uint16_t error_code;
29671 /* The HWRM command request type. */
29673 /* The sequence ID from the original command. */
29675 /* The length of the response data in number of bytes. */
29677 uint8_t unused_0[7];
29679 * This field is used in Output records to indicate that the output
29680 * is completely written to RAM. This field should be read as '1'
29681 * to indicate that the output has been completely written.
29682 * When writing a command completion or response to an internal processor,
29683 * the order of writes has to be such that this field is written last.
29688 /***************************
29689 * hwrm_cfa_l2_set_rx_mask *
29690 ***************************/
29693 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
29694 struct hwrm_cfa_l2_set_rx_mask_input {
29695 /* The HWRM command request type. */
29698 * The completion ring to send the completion event on. This should
29699 * be the NQ ID returned from the `nq_alloc` HWRM command.
29701 uint16_t cmpl_ring;
29703 * The sequence ID is used by the driver for tracking multiple
29704 * commands. This ID is treated as opaque data by the firmware and
29705 * the value is returned in the `hwrm_resp_hdr` upon completion.
29709 * The target ID of the command:
29710 * * 0x0-0xFFF8 - The function ID
29711 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29712 * * 0xFFFD - Reserved for user-space HWRM interface
29715 uint16_t target_id;
29717 * A physical address pointer pointing to a host buffer that the
29718 * command's response data will be written. This can be either a host
29719 * physical address (HPA) or a guest physical address (GPA) and must
29720 * point to a physically contiguous block of memory.
29722 uint64_t resp_addr;
29727 * When this bit is '1', the function is requested to accept
29728 * multi-cast packets specified by the multicast addr table.
29730 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
29733 * When this bit is '1', the function is requested to accept
29734 * all multi-cast packets.
29736 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
29739 * When this bit is '1', the function is requested to accept
29740 * broadcast packets.
29742 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
29745 * When this bit is '1', the function is requested to be
29746 * put in the promiscuous mode.
29748 * The HWRM should accept any function to set up
29749 * promiscuous mode.
29751 * The HWRM shall follow the semantics below for the
29752 * promiscuous mode support.
29753 * # When partitioning is not enabled on a port
29754 * (i.e. single PF on the port), then the PF shall
29755 * be allowed to be in the promiscuous mode. When the
29756 * PF is in the promiscuous mode, then it shall
29757 * receive all host bound traffic on that port.
29758 * # When partitioning is enabled on a port
29759 * (i.e. multiple PFs per port) and a PF on that
29760 * port is in the promiscuous mode, then the PF
29761 * receives all traffic within that partition as
29762 * identified by a unique identifier for the
29763 * PF (e.g. S-Tag). If a unique outer VLAN
29764 * for the PF is specified, then the setting of
29765 * promiscuous mode on that PF shall result in the
29766 * PF receiving all host bound traffic with matching
29768 * # A VF shall can be set in the promiscuous mode.
29769 * In the promiscuous mode, the VF does not receive any
29770 * traffic unless a unique outer VLAN for the
29771 * VF is specified. If a unique outer VLAN
29772 * for the VF is specified, then the setting of
29773 * promiscuous mode on that VF shall result in the
29774 * VF receiving all host bound traffic with the
29775 * matching outer VLAN.
29776 * # The HWRM shall allow the setting of promiscuous
29777 * mode on a function independently from the
29778 * promiscuous mode settings on other functions.
29780 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
29783 * If this flag is set, the corresponding RX
29784 * filters shall be set up to cover multicast/broadcast
29785 * filters for the outermost Layer 2 destination MAC
29788 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
29791 * If this flag is set, the corresponding RX
29792 * filters shall be set up to cover multicast/broadcast
29793 * filters for the VLAN-tagged packets that match the
29794 * TPID and VID fields of VLAN tags in the VLAN tag
29795 * table specified in this command.
29797 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
29800 * If this flag is set, the corresponding RX
29801 * filters shall be set up to cover multicast/broadcast
29802 * filters for non-VLAN tagged packets and VLAN-tagged
29803 * packets that match the TPID and VID fields of VLAN
29804 * tags in the VLAN tag table specified in this command.
29806 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
29809 * If this flag is set, the corresponding RX
29810 * filters shall be set up to cover multicast/broadcast
29811 * filters for non-VLAN tagged packets and VLAN-tagged
29812 * packets matching any VLAN tag.
29814 * If this flag is set, then the HWRM shall ignore
29815 * VLAN tags specified in vlan_tag_tbl.
29817 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
29818 * flags is set, then the HWRM shall ignore
29819 * VLAN tags specified in vlan_tag_tbl.
29821 * The HWRM client shall set at most one flag out of
29822 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
29824 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
29826 /* This is the address for mcast address tbl. */
29827 uint64_t mc_tbl_addr;
29829 * This value indicates how many entries in mc_tbl are valid.
29830 * Each entry is 6 bytes.
29832 uint32_t num_mc_entries;
29833 uint8_t unused_0[4];
29835 * This is the address for VLAN tag table.
29836 * Each VLAN entry in the table is 4 bytes of a VLAN tag
29837 * including TPID, PCP, DEI, and VID fields in network byte
29840 uint64_t vlan_tag_tbl_addr;
29842 * This value indicates how many entries in vlan_tag_tbl are
29843 * valid. Each entry is 4 bytes.
29845 uint32_t num_vlan_tags;
29846 uint8_t unused_1[4];
29849 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
29850 struct hwrm_cfa_l2_set_rx_mask_output {
29851 /* The specific error status for the command. */
29852 uint16_t error_code;
29853 /* The HWRM command request type. */
29855 /* The sequence ID from the original command. */
29857 /* The length of the response data in number of bytes. */
29859 uint8_t unused_0[7];
29861 * This field is used in Output records to indicate that the output
29862 * is completely written to RAM. This field should be read as '1'
29863 * to indicate that the output has been completely written.
29864 * When writing a command completion or response to an internal processor,
29865 * the order of writes has to be such that this field is written last.
29870 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
29871 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
29873 * command specific error codes that goes to
29874 * the cmd_err field in Common HWRM Error Response.
29877 /* Unknown error */
29878 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
29880 /* Unable to complete operation due to conflict with Ntuple Filter */
29881 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
29883 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
29884 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
29885 uint8_t unused_0[7];
29888 /*******************************
29889 * hwrm_cfa_vlan_antispoof_cfg *
29890 *******************************/
29893 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
29894 struct hwrm_cfa_vlan_antispoof_cfg_input {
29895 /* The HWRM command request type. */
29898 * The completion ring to send the completion event on. This should
29899 * be the NQ ID returned from the `nq_alloc` HWRM command.
29901 uint16_t cmpl_ring;
29903 * The sequence ID is used by the driver for tracking multiple
29904 * commands. This ID is treated as opaque data by the firmware and
29905 * the value is returned in the `hwrm_resp_hdr` upon completion.
29909 * The target ID of the command:
29910 * * 0x0-0xFFF8 - The function ID
29911 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29912 * * 0xFFFD - Reserved for user-space HWRM interface
29915 uint16_t target_id;
29917 * A physical address pointer pointing to a host buffer that the
29918 * command's response data will be written. This can be either a host
29919 * physical address (HPA) or a guest physical address (GPA) and must
29920 * point to a physically contiguous block of memory.
29922 uint64_t resp_addr;
29924 * Function ID of the function that is being configured.
29925 * Only valid for a VF FID configured by the PF.
29928 uint8_t unused_0[2];
29929 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
29930 uint32_t num_vlan_entries;
29932 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
29933 * antispoof table. Each table entry contains the 16-bit TPID
29934 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
29935 * all in network order to match hwrm_cfa_l2_set_rx_mask.
29936 * For an individual VLAN entry, the mask value should be 0xfff
29937 * for the 12-bit VLAN ID.
29939 uint64_t vlan_tag_mask_tbl_addr;
29942 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
29943 struct hwrm_cfa_vlan_antispoof_cfg_output {
29944 /* The specific error status for the command. */
29945 uint16_t error_code;
29946 /* The HWRM command request type. */
29948 /* The sequence ID from the original command. */
29950 /* The length of the response data in number of bytes. */
29952 uint8_t unused_0[7];
29954 * This field is used in Output records to indicate that the output
29955 * is completely written to RAM. This field should be read as '1'
29956 * to indicate that the output has been completely written.
29957 * When writing a command completion or response to an internal processor,
29958 * the order of writes has to be such that this field is written last.
29963 /********************************
29964 * hwrm_cfa_vlan_antispoof_qcfg *
29965 ********************************/
29968 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
29969 struct hwrm_cfa_vlan_antispoof_qcfg_input {
29970 /* The HWRM command request type. */
29973 * The completion ring to send the completion event on. This should
29974 * be the NQ ID returned from the `nq_alloc` HWRM command.
29976 uint16_t cmpl_ring;
29978 * The sequence ID is used by the driver for tracking multiple
29979 * commands. This ID is treated as opaque data by the firmware and
29980 * the value is returned in the `hwrm_resp_hdr` upon completion.
29984 * The target ID of the command:
29985 * * 0x0-0xFFF8 - The function ID
29986 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29987 * * 0xFFFD - Reserved for user-space HWRM interface
29990 uint16_t target_id;
29992 * A physical address pointer pointing to a host buffer that the
29993 * command's response data will be written. This can be either a host
29994 * physical address (HPA) or a guest physical address (GPA) and must
29995 * point to a physically contiguous block of memory.
29997 uint64_t resp_addr;
29999 * Function ID of the function that is being queried.
30000 * Only valid for a VF FID queried by the PF.
30003 uint8_t unused_0[2];
30005 * Maximum number of VLAN entries the firmware is allowed to DMA
30006 * to vlan_tag_mask_tbl.
30008 uint32_t max_vlan_entries;
30010 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
30011 * antispoof table to which firmware will DMA to. Each table
30012 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
30013 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
30014 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
30015 * the mask value should be 0xfff for the 12-bit VLAN ID.
30017 uint64_t vlan_tag_mask_tbl_addr;
30020 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
30021 struct hwrm_cfa_vlan_antispoof_qcfg_output {
30022 /* The specific error status for the command. */
30023 uint16_t error_code;
30024 /* The HWRM command request type. */
30026 /* The sequence ID from the original command. */
30028 /* The length of the response data in number of bytes. */
30030 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
30031 uint32_t num_vlan_entries;
30032 uint8_t unused_0[3];
30034 * This field is used in Output records to indicate that the output
30035 * is completely written to RAM. This field should be read as '1'
30036 * to indicate that the output has been completely written.
30037 * When writing a command completion or response to an internal processor,
30038 * the order of writes has to be such that this field is written last.
30043 /********************************
30044 * hwrm_cfa_tunnel_filter_alloc *
30045 ********************************/
30048 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
30049 struct hwrm_cfa_tunnel_filter_alloc_input {
30050 /* The HWRM command request type. */
30053 * The completion ring to send the completion event on. This should
30054 * be the NQ ID returned from the `nq_alloc` HWRM command.
30056 uint16_t cmpl_ring;
30058 * The sequence ID is used by the driver for tracking multiple
30059 * commands. This ID is treated as opaque data by the firmware and
30060 * the value is returned in the `hwrm_resp_hdr` upon completion.
30064 * The target ID of the command:
30065 * * 0x0-0xFFF8 - The function ID
30066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30067 * * 0xFFFD - Reserved for user-space HWRM interface
30070 uint16_t target_id;
30072 * A physical address pointer pointing to a host buffer that the
30073 * command's response data will be written. This can be either a host
30074 * physical address (HPA) or a guest physical address (GPA) and must
30075 * point to a physically contiguous block of memory.
30077 uint64_t resp_addr;
30079 /* Setting of this flag indicates the applicability to the loopback path. */
30080 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
30084 * This bit must be '1' for the l2_filter_id field to be
30087 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
30090 * This bit must be '1' for the l2_addr field to be
30093 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
30096 * This bit must be '1' for the l2_ivlan field to be
30099 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
30102 * This bit must be '1' for the l3_addr field to be
30105 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
30108 * This bit must be '1' for the l3_addr_type field to be
30111 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
30114 * This bit must be '1' for the t_l3_addr_type field to be
30117 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
30120 * This bit must be '1' for the t_l3_addr field to be
30123 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
30126 * This bit must be '1' for the tunnel_type field to be
30129 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
30132 * This bit must be '1' for the vni field to be
30135 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
30138 * This bit must be '1' for the dst_vnic_id field to be
30141 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
30144 * This bit must be '1' for the mirror_vnic_id field to be
30147 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
30150 * This value identifies a set of CFA data structures used for an L2
30153 uint64_t l2_filter_id;
30155 * This value sets the match value for the inner L2
30157 * Destination MAC address for RX path.
30158 * Source MAC address for TX path.
30160 uint8_t l2_addr[6];
30162 * This value sets VLAN ID value for inner VLAN.
30163 * Only 12-bits of VLAN ID are used in setting the filter.
30167 * The value of inner destination IP address to be used in filtering.
30168 * For IPv4, first four bytes represent the IP address.
30170 uint32_t l3_addr[4];
30172 * The value of tunnel destination IP address to be used in filtering.
30173 * For IPv4, first four bytes represent the IP address.
30175 uint32_t t_l3_addr[4];
30177 * This value indicates the type of inner IP address.
30180 * All others are invalid.
30182 uint8_t l3_addr_type;
30184 * This value indicates the type of tunnel IP address.
30187 * All others are invalid.
30189 uint8_t t_l3_addr_type;
30191 uint8_t tunnel_type;
30193 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30195 /* Virtual eXtensible Local Area Network (VXLAN) */
30196 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30198 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30201 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30202 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30205 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30207 /* Generic Network Virtualization Encapsulation (Geneve) */
30208 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30210 /* Multi-Protocol Label Switching (MPLS) */
30211 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30213 /* Stateless Transport Tunnel (STT) */
30214 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
30216 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30217 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30219 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30220 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30222 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30223 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30225 /* Use fixed layer 2 ether type of 0xFFFF */
30226 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30228 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30229 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30231 /* Any tunneled traffic */
30232 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30234 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30235 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30237 * tunnel_flags allows the user to indicate the tunnel tag detection
30238 * for the tunnel type specified in tunnel_type.
30240 uint8_t tunnel_flags;
30242 * If the tunnel_type is geneve, then this bit indicates if we
30243 * need to match the geneve OAM packet.
30244 * If the tunnel_type is nvgre or gre, then this bit indicates if
30245 * we need to detect checksum present bit in geneve header.
30246 * If the tunnel_type is mpls, then this bit indicates if we need
30247 * to match mpls packet with explicit IPV4/IPV6 null header.
30249 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
30252 * If the tunnel_type is geneve, then this bit indicates if we
30253 * need to detect the critical option bit set in the oam packet.
30254 * If the tunnel_type is nvgre or gre, then this bit indicates
30255 * if we need to match nvgre packets with key present bit set in
30257 * If the tunnel_type is mpls, then this bit indicates if we
30258 * need to match mpls packet with S bit from inner/second label.
30260 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
30263 * If the tunnel_type is geneve, then this bit indicates if we
30264 * need to match geneve packet with extended header bit set in
30266 * If the tunnel_type is nvgre or gre, then this bit indicates
30267 * if we need to match nvgre packets with sequence number
30268 * present bit set in gre header.
30269 * If the tunnel_type is mpls, then this bit indicates if we
30270 * need to match mpls packet with S bit from out/first label.
30272 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
30275 * Virtual Network Identifier (VNI). Only valid with
30276 * tunnel_types VXLAN, NVGRE, and Geneve.
30277 * Only lower 24-bits of VNI field are used
30278 * in setting up the filter.
30281 /* Logical VNIC ID of the destination VNIC. */
30282 uint32_t dst_vnic_id;
30284 * Logical VNIC ID of the VNIC where traffic is
30287 uint32_t mirror_vnic_id;
30290 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
30291 struct hwrm_cfa_tunnel_filter_alloc_output {
30292 /* The specific error status for the command. */
30293 uint16_t error_code;
30294 /* The HWRM command request type. */
30296 /* The sequence ID from the original command. */
30298 /* The length of the response data in number of bytes. */
30300 /* This value is an opaque id into CFA data structures. */
30301 uint64_t tunnel_filter_id;
30303 * The flow id value in bit 0-29 is the actual ID of the flow
30304 * associated with this filter and it shall be used to match
30305 * and associate the flow identifier returned in completion
30306 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
30307 * shall indicate no valid flow id.
30310 /* Indicate the flow id value. */
30311 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
30312 UINT32_C(0x3fffffff)
30313 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
30314 /* Indicate type of the flow. */
30315 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
30316 UINT32_C(0x40000000)
30318 * If this bit set to 0, then it indicates that the flow is
30321 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
30322 (UINT32_C(0x0) << 30)
30324 * If this bit is set to 1, then it indicates that the flow is
30327 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
30328 (UINT32_C(0x1) << 30)
30329 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
30330 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
30331 /* Indicate the flow direction. */
30332 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
30333 UINT32_C(0x80000000)
30334 /* If this bit set to 0, then it indicates rx flow. */
30335 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
30336 (UINT32_C(0x0) << 31)
30337 /* If this bit is set to 1, then it indicates that tx flow. */
30338 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
30339 (UINT32_C(0x1) << 31)
30340 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
30341 HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
30342 uint8_t unused_0[3];
30344 * This field is used in Output records to indicate that the output
30345 * is completely written to RAM. This field should be read as '1'
30346 * to indicate that the output has been completely written.
30347 * When writing a command completion or response to an internal processor,
30348 * the order of writes has to be such that this field is written last.
30353 /*******************************
30354 * hwrm_cfa_tunnel_filter_free *
30355 *******************************/
30358 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
30359 struct hwrm_cfa_tunnel_filter_free_input {
30360 /* The HWRM command request type. */
30363 * The completion ring to send the completion event on. This should
30364 * be the NQ ID returned from the `nq_alloc` HWRM command.
30366 uint16_t cmpl_ring;
30368 * The sequence ID is used by the driver for tracking multiple
30369 * commands. This ID is treated as opaque data by the firmware and
30370 * the value is returned in the `hwrm_resp_hdr` upon completion.
30374 * The target ID of the command:
30375 * * 0x0-0xFFF8 - The function ID
30376 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30377 * * 0xFFFD - Reserved for user-space HWRM interface
30380 uint16_t target_id;
30382 * A physical address pointer pointing to a host buffer that the
30383 * command's response data will be written. This can be either a host
30384 * physical address (HPA) or a guest physical address (GPA) and must
30385 * point to a physically contiguous block of memory.
30387 uint64_t resp_addr;
30388 /* This value is an opaque id into CFA data structures. */
30389 uint64_t tunnel_filter_id;
30392 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
30393 struct hwrm_cfa_tunnel_filter_free_output {
30394 /* The specific error status for the command. */
30395 uint16_t error_code;
30396 /* The HWRM command request type. */
30398 /* The sequence ID from the original command. */
30400 /* The length of the response data in number of bytes. */
30402 uint8_t unused_0[7];
30404 * This field is used in Output records to indicate that the output
30405 * is completely written to RAM. This field should be read as '1'
30406 * to indicate that the output has been completely written.
30407 * When writing a command completion or response to an internal processor,
30408 * the order of writes has to be such that this field is written last.
30413 /***************************************
30414 * hwrm_cfa_redirect_tunnel_type_alloc *
30415 ***************************************/
30418 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
30419 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
30420 /* The HWRM command request type. */
30423 * The completion ring to send the completion event on. This should
30424 * be the NQ ID returned from the `nq_alloc` HWRM command.
30426 uint16_t cmpl_ring;
30428 * The sequence ID is used by the driver for tracking multiple
30429 * commands. This ID is treated as opaque data by the firmware and
30430 * the value is returned in the `hwrm_resp_hdr` upon completion.
30434 * The target ID of the command:
30435 * * 0x0-0xFFF8 - The function ID
30436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30437 * * 0xFFFD - Reserved for user-space HWRM interface
30440 uint16_t target_id;
30442 * A physical address pointer pointing to a host buffer that the
30443 * command's response data will be written. This can be either a host
30444 * physical address (HPA) or a guest physical address (GPA) and must
30445 * point to a physically contiguous block of memory.
30447 uint64_t resp_addr;
30448 /* The destination function id, to whom the traffic is redirected. */
30451 uint8_t tunnel_type;
30453 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
30455 /* Virtual eXtensible Local Area Network (VXLAN) */
30456 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
30458 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30459 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
30461 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30462 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
30465 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
30467 /* Generic Network Virtualization Encapsulation (Geneve) */
30468 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
30470 /* Multi-Protocol Label Switching (MPLS) */
30471 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
30473 /* Stateless Transport Tunnel (STT) */
30474 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
30476 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30477 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
30479 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30480 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30482 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30483 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30485 /* Use fixed layer 2 ether type of 0xFFFF */
30486 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
30488 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30489 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30491 /* Any tunneled traffic */
30492 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30494 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
30495 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
30496 /* Tunnel alloc flags. */
30498 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
30499 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
30501 uint8_t unused_0[4];
30504 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
30505 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
30506 /* The specific error status for the command. */
30507 uint16_t error_code;
30508 /* The HWRM command request type. */
30510 /* The sequence ID from the original command. */
30512 /* The length of the response data in number of bytes. */
30514 uint8_t unused_0[7];
30516 * This field is used in Output records to indicate that the output
30517 * is completely written to RAM. This field should be read as '1'
30518 * to indicate that the output has been completely written.
30519 * When writing a command completion or response to an internal processor,
30520 * the order of writes has to be such that this field is written last.
30525 /**************************************
30526 * hwrm_cfa_redirect_tunnel_type_free *
30527 **************************************/
30530 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
30531 struct hwrm_cfa_redirect_tunnel_type_free_input {
30532 /* The HWRM command request type. */
30535 * The completion ring to send the completion event on. This should
30536 * be the NQ ID returned from the `nq_alloc` HWRM command.
30538 uint16_t cmpl_ring;
30540 * The sequence ID is used by the driver for tracking multiple
30541 * commands. This ID is treated as opaque data by the firmware and
30542 * the value is returned in the `hwrm_resp_hdr` upon completion.
30546 * The target ID of the command:
30547 * * 0x0-0xFFF8 - The function ID
30548 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30549 * * 0xFFFD - Reserved for user-space HWRM interface
30552 uint16_t target_id;
30554 * A physical address pointer pointing to a host buffer that the
30555 * command's response data will be written. This can be either a host
30556 * physical address (HPA) or a guest physical address (GPA) and must
30557 * point to a physically contiguous block of memory.
30559 uint64_t resp_addr;
30560 /* The destination function id, to whom the traffic is redirected. */
30563 uint8_t tunnel_type;
30565 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
30567 /* Virtual eXtensible Local Area Network (VXLAN) */
30568 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
30570 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30571 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
30573 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30574 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
30577 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
30579 /* Generic Network Virtualization Encapsulation (Geneve) */
30580 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
30582 /* Multi-Protocol Label Switching (MPLS) */
30583 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
30585 /* Stateless Transport Tunnel (STT) */
30586 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
30588 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30589 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
30591 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30592 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30594 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30595 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30597 /* Use fixed layer 2 ether type of 0xFFFF */
30598 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
30600 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30601 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30603 /* Any tunneled traffic */
30604 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30606 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
30607 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
30608 uint8_t unused_0[5];
30611 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
30612 struct hwrm_cfa_redirect_tunnel_type_free_output {
30613 /* The specific error status for the command. */
30614 uint16_t error_code;
30615 /* The HWRM command request type. */
30617 /* The sequence ID from the original command. */
30619 /* The length of the response data in number of bytes. */
30621 uint8_t unused_0[7];
30623 * This field is used in Output records to indicate that the output
30624 * is completely written to RAM. This field should be read as '1'
30625 * to indicate that the output has been completely written.
30626 * When writing a command completion or response to an internal processor,
30627 * the order of writes has to be such that this field is written last.
30632 /**************************************
30633 * hwrm_cfa_redirect_tunnel_type_info *
30634 **************************************/
30637 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
30638 struct hwrm_cfa_redirect_tunnel_type_info_input {
30639 /* The HWRM command request type. */
30642 * The completion ring to send the completion event on. This should
30643 * be the NQ ID returned from the `nq_alloc` HWRM command.
30645 uint16_t cmpl_ring;
30647 * The sequence ID is used by the driver for tracking multiple
30648 * commands. This ID is treated as opaque data by the firmware and
30649 * the value is returned in the `hwrm_resp_hdr` upon completion.
30653 * The target ID of the command:
30654 * * 0x0-0xFFF8 - The function ID
30655 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30656 * * 0xFFFD - Reserved for user-space HWRM interface
30659 uint16_t target_id;
30661 * A physical address pointer pointing to a host buffer that the
30662 * command's response data will be written. This can be either a host
30663 * physical address (HPA) or a guest physical address (GPA) and must
30664 * point to a physically contiguous block of memory.
30666 uint64_t resp_addr;
30667 /* The source function id. */
30670 uint8_t tunnel_type;
30672 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
30674 /* Virtual eXtensible Local Area Network (VXLAN) */
30675 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
30677 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30678 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
30680 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
30681 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
30684 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
30686 /* Generic Network Virtualization Encapsulation (Geneve) */
30687 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
30689 /* Multi-Protocol Label Switching (MPLS) */
30690 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
30692 /* Stateless Transport Tunnel (STT) */
30693 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
30695 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30696 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
30698 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30699 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
30701 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30702 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
30704 /* Use fixed layer 2 ether type of 0xFFFF */
30705 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
30707 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30708 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
30710 /* Any tunneled traffic */
30711 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
30713 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
30714 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
30715 uint8_t unused_0[5];
30718 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
30719 struct hwrm_cfa_redirect_tunnel_type_info_output {
30720 /* The specific error status for the command. */
30721 uint16_t error_code;
30722 /* The HWRM command request type. */
30724 /* The sequence ID from the original command. */
30726 /* The length of the response data in number of bytes. */
30728 /* The destination function id, to whom the traffic is redirected. */
30730 uint8_t unused_0[5];
30732 * This field is used in Output records to indicate that the output
30733 * is completely written to RAM. This field should be read as '1'
30734 * to indicate that the output has been completely written.
30735 * When writing a command completion or response to an internal processor,
30736 * the order of writes has to be such that this field is written last.
30741 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
30742 struct hwrm_vxlan_ipv4_hdr {
30743 /* IPv4 version and header length. */
30745 /* IPv4 header length */
30746 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
30747 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
30749 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
30750 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
30751 /* IPv4 type of service. */
30753 /* IPv4 identification. */
30755 /* IPv4 flags and offset. */
30756 uint16_t flags_frag_offset;
30759 /* IPv4 protocol. */
30761 /* IPv4 source address. */
30762 uint32_t src_ip_addr;
30763 /* IPv4 destination address. */
30764 uint32_t dest_ip_addr;
30767 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
30768 struct hwrm_vxlan_ipv6_hdr {
30769 /* IPv6 version, traffic class and flow label. */
30770 uint32_t ver_tc_flow_label;
30771 /* IPv6 version shift */
30772 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
30774 /* IPv6 version mask */
30775 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
30776 UINT32_C(0xf0000000)
30777 /* IPv6 TC shift */
30778 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
30781 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
30782 UINT32_C(0xff00000)
30783 /* IPv6 flow label shift */
30784 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
30786 /* IPv6 flow label mask */
30787 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
30789 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
30790 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
30791 /* IPv6 payload length. */
30792 uint16_t payload_len;
30793 /* IPv6 next header. */
30797 /* IPv6 source address. */
30798 uint32_t src_ip_addr[4];
30799 /* IPv6 destination address. */
30800 uint32_t dest_ip_addr[4];
30803 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */
30804 struct hwrm_cfa_encap_data_vxlan {
30805 /* Source MAC address. */
30806 uint8_t src_mac_addr[6];
30809 /* Destination MAC address. */
30810 uint8_t dst_mac_addr[6];
30811 /* Number of VLAN tags. */
30812 uint8_t num_vlan_tags;
30815 /* Outer VLAN TPID. */
30816 uint16_t ovlan_tpid;
30817 /* Outer VLAN TCI. */
30818 uint16_t ovlan_tci;
30819 /* Inner VLAN TPID. */
30820 uint16_t ivlan_tpid;
30821 /* Inner VLAN TCI. */
30822 uint16_t ivlan_tci;
30823 /* L3 header fields. */
30825 /* IP version mask. */
30826 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
30827 /* IP version 4. */
30828 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
30829 /* IP version 6. */
30830 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
30831 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
30832 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
30833 /* UDP source port. */
30835 /* UDP destination port. */
30837 /* VXLAN Network Identifier. */
30839 /* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */
30840 uint8_t hdr_rsvd0[3];
30841 /* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */
30843 /* VXLAN header flags field. */
30848 /*******************************
30849 * hwrm_cfa_encap_record_alloc *
30850 *******************************/
30853 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
30854 struct hwrm_cfa_encap_record_alloc_input {
30855 /* The HWRM command request type. */
30858 * The completion ring to send the completion event on. This should
30859 * be the NQ ID returned from the `nq_alloc` HWRM command.
30861 uint16_t cmpl_ring;
30863 * The sequence ID is used by the driver for tracking multiple
30864 * commands. This ID is treated as opaque data by the firmware and
30865 * the value is returned in the `hwrm_resp_hdr` upon completion.
30869 * The target ID of the command:
30870 * * 0x0-0xFFF8 - The function ID
30871 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30872 * * 0xFFFD - Reserved for user-space HWRM interface
30875 uint16_t target_id;
30877 * A physical address pointer pointing to a host buffer that the
30878 * command's response data will be written. This can be either a host
30879 * physical address (HPA) or a guest physical address (GPA) and must
30880 * point to a physically contiguous block of memory.
30882 uint64_t resp_addr;
30884 /* Setting of this flag indicates the applicability to the loopback path. */
30885 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
30888 * Setting of this flag indicates this encap record is external encap record.
30889 * Resetting of this flag indicates this flag is internal encap record and
30890 * this is the default setting.
30892 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
30894 /* Encapsulation Type. */
30895 uint8_t encap_type;
30896 /* Virtual eXtensible Local Area Network (VXLAN) */
30897 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
30899 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
30900 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
30902 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
30903 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
30906 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
30908 /* Generic Network Virtualization Encapsulation (Geneve) */
30909 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
30911 /* Multi-Protocol Label Switching (MPLS) */
30912 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
30915 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
30917 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
30918 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
30920 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
30921 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
30923 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
30924 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
30926 /* Use fixed layer 2 ether type of 0xFFFF */
30927 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
30929 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
30930 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
30932 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
30933 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
30934 uint8_t unused_0[3];
30935 /* This value is encap data used for the given encap type. */
30936 uint32_t encap_data[20];
30939 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
30940 struct hwrm_cfa_encap_record_alloc_output {
30941 /* The specific error status for the command. */
30942 uint16_t error_code;
30943 /* The HWRM command request type. */
30945 /* The sequence ID from the original command. */
30947 /* The length of the response data in number of bytes. */
30949 /* This value is an opaque id into CFA data structures. */
30950 uint32_t encap_record_id;
30951 uint8_t unused_0[3];
30953 * This field is used in Output records to indicate that the output
30954 * is completely written to RAM. This field should be read as '1'
30955 * to indicate that the output has been completely written.
30956 * When writing a command completion or response to an internal processor,
30957 * the order of writes has to be such that this field is written last.
30962 /******************************
30963 * hwrm_cfa_encap_record_free *
30964 ******************************/
30967 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
30968 struct hwrm_cfa_encap_record_free_input {
30969 /* The HWRM command request type. */
30972 * The completion ring to send the completion event on. This should
30973 * be the NQ ID returned from the `nq_alloc` HWRM command.
30975 uint16_t cmpl_ring;
30977 * The sequence ID is used by the driver for tracking multiple
30978 * commands. This ID is treated as opaque data by the firmware and
30979 * the value is returned in the `hwrm_resp_hdr` upon completion.
30983 * The target ID of the command:
30984 * * 0x0-0xFFF8 - The function ID
30985 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30986 * * 0xFFFD - Reserved for user-space HWRM interface
30989 uint16_t target_id;
30991 * A physical address pointer pointing to a host buffer that the
30992 * command's response data will be written. This can be either a host
30993 * physical address (HPA) or a guest physical address (GPA) and must
30994 * point to a physically contiguous block of memory.
30996 uint64_t resp_addr;
30997 /* This value is an opaque id into CFA data structures. */
30998 uint32_t encap_record_id;
30999 uint8_t unused_0[4];
31002 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
31003 struct hwrm_cfa_encap_record_free_output {
31004 /* The specific error status for the command. */
31005 uint16_t error_code;
31006 /* The HWRM command request type. */
31008 /* The sequence ID from the original command. */
31010 /* The length of the response data in number of bytes. */
31012 uint8_t unused_0[7];
31014 * This field is used in Output records to indicate that the output
31015 * is completely written to RAM. This field should be read as '1'
31016 * to indicate that the output has been completely written.
31017 * When writing a command completion or response to an internal processor,
31018 * the order of writes has to be such that this field is written last.
31023 /********************************
31024 * hwrm_cfa_ntuple_filter_alloc *
31025 ********************************/
31028 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
31029 struct hwrm_cfa_ntuple_filter_alloc_input {
31030 /* The HWRM command request type. */
31033 * The completion ring to send the completion event on. This should
31034 * be the NQ ID returned from the `nq_alloc` HWRM command.
31036 uint16_t cmpl_ring;
31038 * The sequence ID is used by the driver for tracking multiple
31039 * commands. This ID is treated as opaque data by the firmware and
31040 * the value is returned in the `hwrm_resp_hdr` upon completion.
31044 * The target ID of the command:
31045 * * 0x0-0xFFF8 - The function ID
31046 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31047 * * 0xFFFD - Reserved for user-space HWRM interface
31050 uint16_t target_id;
31052 * A physical address pointer pointing to a host buffer that the
31053 * command's response data will be written. This can be either a host
31054 * physical address (HPA) or a guest physical address (GPA) and must
31055 * point to a physically contiguous block of memory.
31057 uint64_t resp_addr;
31059 /* Setting of this flag indicates the applicability to the loopback path. */
31060 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
31063 * Setting of this flag indicates drop action. If this flag is not set,
31064 * then it should be considered accept action.
31066 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
31069 * Setting of this flag indicates that a meter is expected to be attached
31070 * to this flow. This hint can be used when choosing the action record
31071 * format required for the flow.
31073 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
31076 * Setting of this flag indicates that the dst_id field contains function ID.
31077 * If this is not set it indicates dest_id is VNIC or VPORT.
31079 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
31082 * Setting of this flag indicates match on arp reply when ethertype is 0x0806.
31083 * If this is not set it indicates no specific arp opcode matching.
31085 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \
31088 * Setting of this flag indicates that the dst_id field contains RFS ring
31089 * table index. If this is not set it indicates dst_id is VNIC or VPORT
31090 * or function ID. Note dest_fid and dest_rfs_ring_idx can’t be set at
31093 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \
31097 * This bit must be '1' for the l2_filter_id field to be
31100 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
31103 * This bit must be '1' for the ethertype field to be
31106 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
31109 * This bit must be '1' for the tunnel_type field to be
31112 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31115 * This bit must be '1' for the src_macaddr field to be
31118 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31121 * This bit must be '1' for the ipaddr_type field to be
31124 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
31127 * This bit must be '1' for the src_ipaddr field to be
31130 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
31133 * This bit must be '1' for the src_ipaddr_mask field to be
31136 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
31139 * This bit must be '1' for the dst_ipaddr field to be
31142 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
31145 * This bit must be '1' for the dst_ipaddr_mask field to be
31148 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
31151 * This bit must be '1' for the ip_protocol field to be
31154 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
31157 * This bit must be '1' for the src_port field to be
31160 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
31163 * This bit must be '1' for the src_port_mask field to be
31166 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
31169 * This bit must be '1' for the dst_port field to be
31172 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
31175 * This bit must be '1' for the dst_port_mask field to be
31178 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
31181 * This bit must be '1' for the pri_hint field to be
31184 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
31187 * This bit must be '1' for the ntuple_filter_id field to be
31190 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
31193 * This bit must be '1' for the dst_id field to be
31196 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
31199 * This bit must be '1' for the mirror_vnic_id field to be
31202 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31205 * This bit must be '1' for the dst_macaddr field to be
31208 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
31210 /* This flag is deprecated. */
31211 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
31214 * This value identifies a set of CFA data structures used for an L2
31217 uint64_t l2_filter_id;
31219 * This value indicates the source MAC address in
31220 * the Ethernet header.
31222 uint8_t src_macaddr[6];
31223 /* This value indicates the ethertype in the Ethernet header. */
31224 uint16_t ethertype;
31226 * This value indicates the type of IP address.
31229 * All others are invalid.
31231 uint8_t ip_addr_type;
31233 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
31236 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
31239 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
31241 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
31242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
31244 * The value of protocol filed in IP header.
31245 * Applies to UDP and TCP traffic.
31249 uint8_t ip_protocol;
31251 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
31254 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
31257 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
31259 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
31260 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
31262 * If set, this value shall represent the
31263 * Logical VNIC ID of the destination VNIC for the RX
31264 * path and network port id of the destination port for
31269 * Logical VNIC ID of the VNIC where traffic is
31272 uint16_t mirror_vnic_id;
31274 * This value indicates the tunnel type for this filter.
31275 * If this field is not specified, then the filter shall
31276 * apply to both non-tunneled and tunneled packets.
31277 * If this field conflicts with the tunnel_type specified
31278 * in the l2_filter_id, then the HWRM shall return an
31279 * error for this command.
31281 uint8_t tunnel_type;
31283 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
31285 /* Virtual eXtensible Local Area Network (VXLAN) */
31286 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
31288 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31289 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
31291 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31292 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
31295 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
31297 /* Generic Network Virtualization Encapsulation (Geneve) */
31298 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
31300 /* Multi-Protocol Label Switching (MPLS) */
31301 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
31303 /* Stateless Transport Tunnel (STT) */
31304 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
31306 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31307 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
31309 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31310 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31312 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31313 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31315 /* Use fixed layer 2 ether type of 0xFFFF */
31316 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
31318 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31319 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31321 /* Any tunneled traffic */
31322 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
31324 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
31325 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
31327 * This hint is provided to help in placing
31328 * the filter in the filter table.
31331 /* No preference */
31332 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
31334 /* Above the given filter */
31335 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
31337 /* Below the given filter */
31338 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
31340 /* As high as possible */
31341 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
31343 /* As low as possible */
31344 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
31346 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
31347 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
31349 * The value of source IP address to be used in filtering.
31350 * For IPv4, first four bytes represent the IP address.
31352 uint32_t src_ipaddr[4];
31354 * The value of source IP address mask to be used in
31356 * For IPv4, first four bytes represent the IP address mask.
31358 uint32_t src_ipaddr_mask[4];
31360 * The value of destination IP address to be used in filtering.
31361 * For IPv4, first four bytes represent the IP address.
31363 uint32_t dst_ipaddr[4];
31365 * The value of destination IP address mask to be used in
31367 * For IPv4, first four bytes represent the IP address mask.
31369 uint32_t dst_ipaddr_mask[4];
31371 * The value of source port to be used in filtering.
31372 * Applies to UDP and TCP traffic.
31376 * The value of source port mask to be used in filtering.
31377 * Applies to UDP and TCP traffic.
31379 uint16_t src_port_mask;
31381 * The value of destination port to be used in filtering.
31382 * Applies to UDP and TCP traffic.
31386 * The value of destination port mask to be used in
31388 * Applies to UDP and TCP traffic.
31390 uint16_t dst_port_mask;
31392 * This is the ID of the filter that goes along with
31395 uint64_t ntuple_filter_id_hint;
31398 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
31399 struct hwrm_cfa_ntuple_filter_alloc_output {
31400 /* The specific error status for the command. */
31401 uint16_t error_code;
31402 /* The HWRM command request type. */
31404 /* The sequence ID from the original command. */
31406 /* The length of the response data in number of bytes. */
31408 /* This value is an opaque id into CFA data structures. */
31409 uint64_t ntuple_filter_id;
31411 * The flow id value in bit 0-29 is the actual ID of the flow
31412 * associated with this filter and it shall be used to match
31413 * and associate the flow identifier returned in completion
31414 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
31415 * shall indicate no valid flow id.
31418 /* Indicate the flow id value. */
31419 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
31420 UINT32_C(0x3fffffff)
31421 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
31422 /* Indicate type of the flow. */
31423 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
31424 UINT32_C(0x40000000)
31426 * If this bit set to 0, then it indicates that the flow is
31429 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
31430 (UINT32_C(0x0) << 30)
31432 * If this bit is set to 1, then it indicates that the flow is
31435 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
31436 (UINT32_C(0x1) << 30)
31437 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
31438 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
31439 /* Indicate the flow direction. */
31440 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
31441 UINT32_C(0x80000000)
31442 /* If this bit set to 0, then it indicates rx flow. */
31443 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
31444 (UINT32_C(0x0) << 31)
31445 /* If this bit is set to 1, then it indicates that tx flow. */
31446 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
31447 (UINT32_C(0x1) << 31)
31448 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
31449 HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
31450 uint8_t unused_0[3];
31452 * This field is used in Output records to indicate that the output
31453 * is completely written to RAM. This field should be read as '1'
31454 * to indicate that the output has been completely written.
31455 * When writing a command completion or response to an internal processor,
31456 * the order of writes has to be such that this field is written last.
31461 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
31462 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
31464 * command specific error codes that goes to
31465 * the cmd_err field in Common HWRM Error Response.
31468 /* Unknown error */
31469 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
31471 /* Unable to complete operation due to conflict with Rx Mask VLAN */
31472 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
31474 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
31475 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
31476 uint8_t unused_0[7];
31479 /*******************************
31480 * hwrm_cfa_ntuple_filter_free *
31481 *******************************/
31484 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
31485 struct hwrm_cfa_ntuple_filter_free_input {
31486 /* The HWRM command request type. */
31489 * The completion ring to send the completion event on. This should
31490 * be the NQ ID returned from the `nq_alloc` HWRM command.
31492 uint16_t cmpl_ring;
31494 * The sequence ID is used by the driver for tracking multiple
31495 * commands. This ID is treated as opaque data by the firmware and
31496 * the value is returned in the `hwrm_resp_hdr` upon completion.
31500 * The target ID of the command:
31501 * * 0x0-0xFFF8 - The function ID
31502 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31503 * * 0xFFFD - Reserved for user-space HWRM interface
31506 uint16_t target_id;
31508 * A physical address pointer pointing to a host buffer that the
31509 * command's response data will be written. This can be either a host
31510 * physical address (HPA) or a guest physical address (GPA) and must
31511 * point to a physically contiguous block of memory.
31513 uint64_t resp_addr;
31514 /* This value is an opaque id into CFA data structures. */
31515 uint64_t ntuple_filter_id;
31518 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
31519 struct hwrm_cfa_ntuple_filter_free_output {
31520 /* The specific error status for the command. */
31521 uint16_t error_code;
31522 /* The HWRM command request type. */
31524 /* The sequence ID from the original command. */
31526 /* The length of the response data in number of bytes. */
31528 uint8_t unused_0[7];
31530 * This field is used in Output records to indicate that the output
31531 * is completely written to RAM. This field should be read as '1'
31532 * to indicate that the output has been completely written.
31533 * When writing a command completion or response to an internal processor,
31534 * the order of writes has to be such that this field is written last.
31539 /******************************
31540 * hwrm_cfa_ntuple_filter_cfg *
31541 ******************************/
31544 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
31545 struct hwrm_cfa_ntuple_filter_cfg_input {
31546 /* The HWRM command request type. */
31549 * The completion ring to send the completion event on. This should
31550 * be the NQ ID returned from the `nq_alloc` HWRM command.
31552 uint16_t cmpl_ring;
31554 * The sequence ID is used by the driver for tracking multiple
31555 * commands. This ID is treated as opaque data by the firmware and
31556 * the value is returned in the `hwrm_resp_hdr` upon completion.
31560 * The target ID of the command:
31561 * * 0x0-0xFFF8 - The function ID
31562 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31563 * * 0xFFFD - Reserved for user-space HWRM interface
31566 uint16_t target_id;
31568 * A physical address pointer pointing to a host buffer that the
31569 * command's response data will be written. This can be either a host
31570 * physical address (HPA) or a guest physical address (GPA) and must
31571 * point to a physically contiguous block of memory.
31573 uint64_t resp_addr;
31576 * This bit must be '1' for the new_dst_id field to be
31579 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
31582 * This bit must be '1' for the new_mirror_vnic_id field to be
31585 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
31588 * This bit must be '1' for the new_meter_instance_id field to be
31591 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
31595 * Setting this bit to 1 indicates that dest_id field contains FID.
31596 * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
31598 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
31601 * Setting of this flag indicates that the new_dst_id field contains
31602 * RFS ring table index. If this is not set it indicates new_dst_id is
31603 * VNIC or VPORT or function ID. Note dest_fid and dest_rfs_ring_idx
31604 * can’t be set at the same time.
31606 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \
31608 /* This value is an opaque id into CFA data structures. */
31609 uint64_t ntuple_filter_id;
31611 * If set, this value shall represent the new
31612 * Logical VNIC ID of the destination VNIC for the RX
31613 * path and new network port id of the destination port for
31616 uint32_t new_dst_id;
31618 * New Logical VNIC ID of the VNIC where traffic is
31621 uint32_t new_mirror_vnic_id;
31623 * New meter to attach to the flow. Specifying the
31624 * invalid instance ID is used to remove any existing
31625 * meter from the flow.
31627 uint16_t new_meter_instance_id;
31629 * A value of 0xfff is considered invalid and implies the
31630 * instance is not configured.
31632 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
31634 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
31635 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
31636 uint8_t unused_1[6];
31639 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
31640 struct hwrm_cfa_ntuple_filter_cfg_output {
31641 /* The specific error status for the command. */
31642 uint16_t error_code;
31643 /* The HWRM command request type. */
31645 /* The sequence ID from the original command. */
31647 /* The length of the response data in number of bytes. */
31649 uint8_t unused_0[7];
31651 * This field is used in Output records to indicate that the output
31652 * is completely written to RAM. This field should be read as '1'
31653 * to indicate that the output has been completely written.
31654 * When writing a command completion or response to an internal processor,
31655 * the order of writes has to be such that this field is written last.
31660 /**************************
31661 * hwrm_cfa_em_flow_alloc *
31662 **************************/
31665 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
31666 struct hwrm_cfa_em_flow_alloc_input {
31667 /* The HWRM command request type. */
31670 * The completion ring to send the completion event on. This should
31671 * be the NQ ID returned from the `nq_alloc` HWRM command.
31673 uint16_t cmpl_ring;
31675 * The sequence ID is used by the driver for tracking multiple
31676 * commands. This ID is treated as opaque data by the firmware and
31677 * the value is returned in the `hwrm_resp_hdr` upon completion.
31681 * The target ID of the command:
31682 * * 0x0-0xFFF8 - The function ID
31683 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31684 * * 0xFFFD - Reserved for user-space HWRM interface
31687 uint16_t target_id;
31689 * A physical address pointer pointing to a host buffer that the
31690 * command's response data will be written. This can be either a host
31691 * physical address (HPA) or a guest physical address (GPA) and must
31692 * point to a physically contiguous block of memory.
31694 uint64_t resp_addr;
31697 * Enumeration denoting the RX, TX type of the resource.
31698 * This enumeration is used for resources that are similar for both
31699 * TX and RX paths of the chip.
31701 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
31703 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
31705 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
31706 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
31707 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
31709 * Setting of this flag indicates enabling of a byte counter for a given
31712 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
31714 * Setting of this flag indicates enabling of a packet counter for a given
31717 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
31718 /* Setting of this flag indicates de-capsulation action for the given flow. */
31719 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
31720 /* Setting of this flag indicates encapsulation action for the given flow. */
31721 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
31723 * Setting of this flag indicates drop action. If this flag is not set,
31724 * then it should be considered accept action.
31726 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
31728 * Setting of this flag indicates that a meter is expected to be attached
31729 * to this flow. This hint can be used when choosing the action record
31730 * format required for the flow.
31732 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
31735 * This bit must be '1' for the l2_filter_id field to be
31738 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
31741 * This bit must be '1' for the tunnel_type field to be
31744 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
31747 * This bit must be '1' for the tunnel_id field to be
31750 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
31753 * This bit must be '1' for the src_macaddr field to be
31756 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
31759 * This bit must be '1' for the dst_macaddr field to be
31762 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
31765 * This bit must be '1' for the ovlan_vid field to be
31768 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
31771 * This bit must be '1' for the ivlan_vid field to be
31774 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
31777 * This bit must be '1' for the ethertype field to be
31780 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
31783 * This bit must be '1' for the src_ipaddr field to be
31786 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
31789 * This bit must be '1' for the dst_ipaddr field to be
31792 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
31795 * This bit must be '1' for the ipaddr_type field to be
31798 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
31801 * This bit must be '1' for the ip_protocol field to be
31804 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
31807 * This bit must be '1' for the src_port field to be
31810 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
31813 * This bit must be '1' for the dst_port field to be
31816 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
31819 * This bit must be '1' for the dst_id field to be
31822 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
31825 * This bit must be '1' for the mirror_vnic_id field to be
31828 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
31831 * This bit must be '1' for the encap_record_id field to be
31834 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
31837 * This bit must be '1' for the meter_instance_id field to be
31840 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
31843 * This value identifies a set of CFA data structures used for an L2
31846 uint64_t l2_filter_id;
31848 uint8_t tunnel_type;
31850 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
31852 /* Virtual eXtensible Local Area Network (VXLAN) */
31853 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
31855 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
31856 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
31858 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
31859 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
31862 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
31864 /* Generic Network Virtualization Encapsulation (Geneve) */
31865 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
31867 /* Multi-Protocol Label Switching (MPLS) */
31868 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
31870 /* Stateless Transport Tunnel (STT) */
31871 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
31873 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
31874 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
31876 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
31877 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
31879 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
31880 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
31882 /* Use fixed layer 2 ether type of 0xFFFF */
31883 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
31885 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
31886 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
31888 /* Any tunneled traffic */
31889 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
31891 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
31892 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
31893 uint8_t unused_0[3];
31895 * Tunnel identifier.
31896 * Virtual Network Identifier (VNI). Only valid with
31897 * tunnel_types VXLAN, NVGRE, and Geneve.
31898 * Only lower 24-bits of VNI field are used
31899 * in setting up the filter.
31901 uint32_t tunnel_id;
31903 * This value indicates the source MAC address in
31904 * the Ethernet header.
31906 uint8_t src_macaddr[6];
31907 /* The meter instance to attach to the flow. */
31908 uint16_t meter_instance_id;
31910 * A value of 0xfff is considered invalid and implies the
31911 * instance is not configured.
31913 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
31915 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
31916 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
31918 * This value indicates the destination MAC address in
31919 * the Ethernet header.
31921 uint8_t dst_macaddr[6];
31923 * This value indicates the VLAN ID of the outer VLAN tag
31924 * in the Ethernet header.
31926 uint16_t ovlan_vid;
31928 * This value indicates the VLAN ID of the inner VLAN tag
31929 * in the Ethernet header.
31931 uint16_t ivlan_vid;
31932 /* This value indicates the ethertype in the Ethernet header. */
31933 uint16_t ethertype;
31935 * This value indicates the type of IP address.
31938 * All others are invalid.
31940 uint8_t ip_addr_type;
31942 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
31944 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
31946 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
31947 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
31948 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
31950 * The value of protocol filed in IP header.
31951 * Applies to UDP and TCP traffic.
31955 uint8_t ip_protocol;
31957 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
31959 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
31961 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
31962 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
31963 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
31964 uint8_t unused_1[2];
31966 * The value of source IP address to be used in filtering.
31967 * For IPv4, first four bytes represent the IP address.
31969 uint32_t src_ipaddr[4];
31971 * big_endian = True
31972 * The value of destination IP address to be used in filtering.
31973 * For IPv4, first four bytes represent the IP address.
31975 uint32_t dst_ipaddr[4];
31977 * The value of source port to be used in filtering.
31978 * Applies to UDP and TCP traffic.
31982 * The value of destination port to be used in filtering.
31983 * Applies to UDP and TCP traffic.
31987 * If set, this value shall represent the
31988 * Logical VNIC ID of the destination VNIC for the RX
31989 * path and network port id of the destination port for
31994 * Logical VNIC ID of the VNIC where traffic is
31997 uint16_t mirror_vnic_id;
31998 /* Logical ID of the encapsulation record. */
31999 uint32_t encap_record_id;
32000 uint8_t unused_2[4];
32003 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
32004 struct hwrm_cfa_em_flow_alloc_output {
32005 /* The specific error status for the command. */
32006 uint16_t error_code;
32007 /* The HWRM command request type. */
32009 /* The sequence ID from the original command. */
32011 /* The length of the response data in number of bytes. */
32013 /* This value is an opaque id into CFA data structures. */
32014 uint64_t em_filter_id;
32016 * The flow id value in bit 0-29 is the actual ID of the flow
32017 * associated with this filter and it shall be used to match
32018 * and associate the flow identifier returned in completion
32019 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
32020 * shall indicate no valid flow id.
32023 /* Indicate the flow id value. */
32024 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
32025 UINT32_C(0x3fffffff)
32026 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
32027 /* Indicate type of the flow. */
32028 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
32029 UINT32_C(0x40000000)
32031 * If this bit set to 0, then it indicates that the flow is
32034 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
32035 (UINT32_C(0x0) << 30)
32037 * If this bit is set to 1, then it indicates that the flow is
32040 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
32041 (UINT32_C(0x1) << 30)
32042 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
32043 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
32044 /* Indicate the flow direction. */
32045 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
32046 UINT32_C(0x80000000)
32047 /* If this bit set to 0, then it indicates rx flow. */
32048 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
32049 (UINT32_C(0x0) << 31)
32050 /* If this bit is set to 1, then it indicates that tx flow. */
32051 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
32052 (UINT32_C(0x1) << 31)
32053 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
32054 HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
32055 uint8_t unused_0[3];
32057 * This field is used in Output records to indicate that the output
32058 * is completely written to RAM. This field should be read as '1'
32059 * to indicate that the output has been completely written.
32060 * When writing a command completion or response to an internal processor,
32061 * the order of writes has to be such that this field is written last.
32066 /*************************
32067 * hwrm_cfa_em_flow_free *
32068 *************************/
32071 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
32072 struct hwrm_cfa_em_flow_free_input {
32073 /* The HWRM command request type. */
32076 * The completion ring to send the completion event on. This should
32077 * be the NQ ID returned from the `nq_alloc` HWRM command.
32079 uint16_t cmpl_ring;
32081 * The sequence ID is used by the driver for tracking multiple
32082 * commands. This ID is treated as opaque data by the firmware and
32083 * the value is returned in the `hwrm_resp_hdr` upon completion.
32087 * The target ID of the command:
32088 * * 0x0-0xFFF8 - The function ID
32089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32090 * * 0xFFFD - Reserved for user-space HWRM interface
32093 uint16_t target_id;
32095 * A physical address pointer pointing to a host buffer that the
32096 * command's response data will be written. This can be either a host
32097 * physical address (HPA) or a guest physical address (GPA) and must
32098 * point to a physically contiguous block of memory.
32100 uint64_t resp_addr;
32101 /* This value is an opaque id into CFA data structures. */
32102 uint64_t em_filter_id;
32105 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
32106 struct hwrm_cfa_em_flow_free_output {
32107 /* The specific error status for the command. */
32108 uint16_t error_code;
32109 /* The HWRM command request type. */
32111 /* The sequence ID from the original command. */
32113 /* The length of the response data in number of bytes. */
32115 uint8_t unused_0[7];
32117 * This field is used in Output records to indicate that the output
32118 * is completely written to RAM. This field should be read as '1'
32119 * to indicate that the output has been completely written.
32120 * When writing a command completion or response to an internal processor,
32121 * the order of writes has to be such that this field is written last.
32126 /************************
32127 * hwrm_cfa_meter_qcaps *
32128 ************************/
32131 /* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
32132 struct hwrm_cfa_meter_qcaps_input {
32133 /* The HWRM command request type. */
32136 * The completion ring to send the completion event on. This should
32137 * be the NQ ID returned from the `nq_alloc` HWRM command.
32139 uint16_t cmpl_ring;
32141 * The sequence ID is used by the driver for tracking multiple
32142 * commands. This ID is treated as opaque data by the firmware and
32143 * the value is returned in the `hwrm_resp_hdr` upon completion.
32147 * The target ID of the command:
32148 * * 0x0-0xFFF8 - The function ID
32149 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32150 * * 0xFFFD - Reserved for user-space HWRM interface
32153 uint16_t target_id;
32155 * A physical address pointer pointing to a host buffer that the
32156 * command's response data will be written. This can be either a host
32157 * physical address (HPA) or a guest physical address (GPA) and must
32158 * point to a physically contiguous block of memory.
32160 uint64_t resp_addr;
32163 /* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
32164 struct hwrm_cfa_meter_qcaps_output {
32165 /* The specific error status for the command. */
32166 uint16_t error_code;
32167 /* The HWRM command request type. */
32169 /* The sequence ID from the original command. */
32171 /* The length of the response data in number of bytes. */
32175 * Enumeration denoting the clock at which the Meter is running with.
32176 * This enumeration is used for resources that are similar for both
32177 * TX and RX paths of the chip.
32179 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
32180 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
32182 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
32184 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
32185 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
32186 HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
32187 uint8_t unused_0[4];
32189 * The minimum guaranteed number of tx meter profiles supported
32190 * for this function.
32192 uint16_t min_tx_profile;
32194 * The maximum non-guaranteed number of tx meter profiles supported
32195 * for this function.
32197 uint16_t max_tx_profile;
32199 * The minimum guaranteed number of rx meter profiles supported
32200 * for this function.
32202 uint16_t min_rx_profile;
32204 * The maximum non-guaranteed number of rx meter profiles supported
32205 * for this function.
32207 uint16_t max_rx_profile;
32209 * The minimum guaranteed number of tx meter instances supported
32210 * for this function.
32212 uint16_t min_tx_instance;
32214 * The maximum non-guaranteed number of tx meter instances supported
32215 * for this function.
32217 uint16_t max_tx_instance;
32219 * The minimum guaranteed number of rx meter instances supported
32220 * for this function.
32222 uint16_t min_rx_instance;
32224 * The maximum non-guaranteed number of rx meter instances supported
32225 * for this function.
32227 uint16_t max_rx_instance;
32228 uint8_t unused_1[7];
32230 * This field is used in Output records to indicate that the output
32231 * is completely written to RAM. This field should be read as '1'
32232 * to indicate that the output has been completely written.
32233 * When writing a command completion or response to an internal processor,
32234 * the order of writes has to be such that this field is written last.
32239 /********************************
32240 * hwrm_cfa_meter_profile_alloc *
32241 ********************************/
32244 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
32245 struct hwrm_cfa_meter_profile_alloc_input {
32246 /* The HWRM command request type. */
32249 * The completion ring to send the completion event on. This should
32250 * be the NQ ID returned from the `nq_alloc` HWRM command.
32252 uint16_t cmpl_ring;
32254 * The sequence ID is used by the driver for tracking multiple
32255 * commands. This ID is treated as opaque data by the firmware and
32256 * the value is returned in the `hwrm_resp_hdr` upon completion.
32260 * The target ID of the command:
32261 * * 0x0-0xFFF8 - The function ID
32262 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32263 * * 0xFFFD - Reserved for user-space HWRM interface
32266 uint16_t target_id;
32268 * A physical address pointer pointing to a host buffer that the
32269 * command's response data will be written. This can be either a host
32270 * physical address (HPA) or a guest physical address (GPA) and must
32271 * point to a physically contiguous block of memory.
32273 uint64_t resp_addr;
32276 * Enumeration denoting the RX, TX type of the resource.
32277 * This enumeration is used for resources that are similar for both
32278 * TX and RX paths of the chip.
32280 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
32282 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
32285 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
32287 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
32288 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
32289 /* The meter algorithm type. */
32290 uint8_t meter_type;
32291 /* RFC 2697 (srTCM) */
32292 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
32294 /* RFC 2698 (trTCM) */
32295 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
32297 /* RFC 4115 (trTCM) */
32298 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
32300 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
32301 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
32303 * This field is reserved for the future use.
32304 * It shall be set to 0.
32306 uint16_t reserved1;
32308 * This field is reserved for the future use.
32309 * It shall be set to 0.
32311 uint32_t reserved2;
32312 /* A meter rate specified in bytes-per-second. */
32313 uint32_t commit_rate;
32314 /* The bandwidth value. */
32315 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
32316 UINT32_C(0xfffffff)
32317 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
32319 /* The granularity of the value (bits or bytes). */
32320 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
32321 UINT32_C(0x10000000)
32322 /* Value is in bits. */
32323 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
32324 (UINT32_C(0x0) << 28)
32325 /* Value is in bytes. */
32326 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
32327 (UINT32_C(0x1) << 28)
32328 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
32329 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
32330 /* bw_value_unit is 3 b */
32331 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
32332 UINT32_C(0xe0000000)
32333 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
32335 /* Value is in Mb or MB (base 10). */
32336 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
32337 (UINT32_C(0x0) << 29)
32338 /* Value is in Kb or KB (base 10). */
32339 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
32340 (UINT32_C(0x2) << 29)
32341 /* Value is in bits or bytes. */
32342 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
32343 (UINT32_C(0x4) << 29)
32344 /* Value is in Gb or GB (base 10). */
32345 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
32346 (UINT32_C(0x6) << 29)
32347 /* Value is in 1/100th of a percentage of total bandwidth. */
32348 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32349 (UINT32_C(0x1) << 29)
32351 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
32352 (UINT32_C(0x7) << 29)
32353 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
32354 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
32355 /* A meter burst size specified in bytes. */
32356 uint32_t commit_burst;
32357 /* The bandwidth value. */
32358 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
32359 UINT32_C(0xfffffff)
32360 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
32362 /* The granularity of the value (bits or bytes). */
32363 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
32364 UINT32_C(0x10000000)
32365 /* Value is in bits. */
32366 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
32367 (UINT32_C(0x0) << 28)
32368 /* Value is in bytes. */
32369 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
32370 (UINT32_C(0x1) << 28)
32371 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
32372 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
32373 /* bw_value_unit is 3 b */
32374 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
32375 UINT32_C(0xe0000000)
32376 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
32378 /* Value is in Mb or MB (base 10). */
32379 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
32380 (UINT32_C(0x0) << 29)
32381 /* Value is in Kb or KB (base 10). */
32382 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
32383 (UINT32_C(0x2) << 29)
32384 /* Value is in bits or bytes. */
32385 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
32386 (UINT32_C(0x4) << 29)
32387 /* Value is in Gb or GB (base 10). */
32388 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
32389 (UINT32_C(0x6) << 29)
32390 /* Value is in 1/100th of a percentage of total bandwidth. */
32391 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32392 (UINT32_C(0x1) << 29)
32393 /* Invalid value */
32394 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
32395 (UINT32_C(0x7) << 29)
32396 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
32397 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
32398 /* A meter rate specified in bytes-per-second. */
32399 uint32_t excess_peak_rate;
32400 /* The bandwidth value. */
32401 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
32402 UINT32_C(0xfffffff)
32403 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
32405 /* The granularity of the value (bits or bytes). */
32406 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
32407 UINT32_C(0x10000000)
32408 /* Value is in bits. */
32409 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
32410 (UINT32_C(0x0) << 28)
32411 /* Value is in bytes. */
32412 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
32413 (UINT32_C(0x1) << 28)
32414 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
32415 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
32416 /* bw_value_unit is 3 b */
32417 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
32418 UINT32_C(0xe0000000)
32419 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
32421 /* Value is in Mb or MB (base 10). */
32422 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
32423 (UINT32_C(0x0) << 29)
32424 /* Value is in Kb or KB (base 10). */
32425 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
32426 (UINT32_C(0x2) << 29)
32427 /* Value is in bits or bytes. */
32428 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
32429 (UINT32_C(0x4) << 29)
32430 /* Value is in Gb or GB (base 10). */
32431 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
32432 (UINT32_C(0x6) << 29)
32433 /* Value is in 1/100th of a percentage of total bandwidth. */
32434 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32435 (UINT32_C(0x1) << 29)
32437 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
32438 (UINT32_C(0x7) << 29)
32439 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
32440 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
32441 /* A meter burst size specified in bytes. */
32442 uint32_t excess_peak_burst;
32443 /* The bandwidth value. */
32444 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
32445 UINT32_C(0xfffffff)
32446 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
32448 /* The granularity of the value (bits or bytes). */
32449 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
32450 UINT32_C(0x10000000)
32451 /* Value is in bits. */
32452 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
32453 (UINT32_C(0x0) << 28)
32454 /* Value is in bytes. */
32455 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
32456 (UINT32_C(0x1) << 28)
32457 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
32458 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
32459 /* bw_value_unit is 3 b */
32460 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
32461 UINT32_C(0xe0000000)
32462 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
32464 /* Value is in Mb or MB (base 10). */
32465 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
32466 (UINT32_C(0x0) << 29)
32467 /* Value is in Kb or KB (base 10). */
32468 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
32469 (UINT32_C(0x2) << 29)
32470 /* Value is in bits or bytes. */
32471 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
32472 (UINT32_C(0x4) << 29)
32473 /* Value is in Gb or GB (base 10). */
32474 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
32475 (UINT32_C(0x6) << 29)
32476 /* Value is in 1/100th of a percentage of total bandwidth. */
32477 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32478 (UINT32_C(0x1) << 29)
32480 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
32481 (UINT32_C(0x7) << 29)
32482 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
32483 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
32486 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
32487 struct hwrm_cfa_meter_profile_alloc_output {
32488 /* The specific error status for the command. */
32489 uint16_t error_code;
32490 /* The HWRM command request type. */
32492 /* The sequence ID from the original command. */
32494 /* The length of the response data in number of bytes. */
32496 /* This value identifies a meter profile in CFA. */
32497 uint16_t meter_profile_id;
32499 * A value of 0xfff is considered invalid and implies the
32500 * profile is not configured.
32502 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
32504 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
32505 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
32506 uint8_t unused_0[5];
32508 * This field is used in Output records to indicate that the output
32509 * is completely written to RAM. This field should be read as '1'
32510 * to indicate that the output has been completely written.
32511 * When writing a command completion or response to an internal processor,
32512 * the order of writes has to be such that this field is written last.
32517 /*******************************
32518 * hwrm_cfa_meter_profile_free *
32519 *******************************/
32522 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
32523 struct hwrm_cfa_meter_profile_free_input {
32524 /* The HWRM command request type. */
32527 * The completion ring to send the completion event on. This should
32528 * be the NQ ID returned from the `nq_alloc` HWRM command.
32530 uint16_t cmpl_ring;
32532 * The sequence ID is used by the driver for tracking multiple
32533 * commands. This ID is treated as opaque data by the firmware and
32534 * the value is returned in the `hwrm_resp_hdr` upon completion.
32538 * The target ID of the command:
32539 * * 0x0-0xFFF8 - The function ID
32540 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32541 * * 0xFFFD - Reserved for user-space HWRM interface
32544 uint16_t target_id;
32546 * A physical address pointer pointing to a host buffer that the
32547 * command's response data will be written. This can be either a host
32548 * physical address (HPA) or a guest physical address (GPA) and must
32549 * point to a physically contiguous block of memory.
32551 uint64_t resp_addr;
32554 * Enumeration denoting the RX, TX type of the resource.
32555 * This enumeration is used for resources that are similar for both
32556 * TX and RX paths of the chip.
32558 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
32560 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
32563 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
32565 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
32566 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
32568 /* This value identifies a meter profile in CFA. */
32569 uint16_t meter_profile_id;
32571 * A value of 0xfff is considered invalid and implies the
32572 * profile is not configured.
32574 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
32576 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
32577 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
32578 uint8_t unused_1[4];
32581 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
32582 struct hwrm_cfa_meter_profile_free_output {
32583 /* The specific error status for the command. */
32584 uint16_t error_code;
32585 /* The HWRM command request type. */
32587 /* The sequence ID from the original command. */
32589 /* The length of the response data in number of bytes. */
32591 uint8_t unused_0[7];
32593 * This field is used in Output records to indicate that the output
32594 * is completely written to RAM. This field should be read as '1'
32595 * to indicate that the output has been completely written.
32596 * When writing a command completion or response to an internal processor,
32597 * the order of writes has to be such that this field is written last.
32602 /******************************
32603 * hwrm_cfa_meter_profile_cfg *
32604 ******************************/
32607 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
32608 struct hwrm_cfa_meter_profile_cfg_input {
32609 /* The HWRM command request type. */
32612 * The completion ring to send the completion event on. This should
32613 * be the NQ ID returned from the `nq_alloc` HWRM command.
32615 uint16_t cmpl_ring;
32617 * The sequence ID is used by the driver for tracking multiple
32618 * commands. This ID is treated as opaque data by the firmware and
32619 * the value is returned in the `hwrm_resp_hdr` upon completion.
32623 * The target ID of the command:
32624 * * 0x0-0xFFF8 - The function ID
32625 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32626 * * 0xFFFD - Reserved for user-space HWRM interface
32629 uint16_t target_id;
32631 * A physical address pointer pointing to a host buffer that the
32632 * command's response data will be written. This can be either a host
32633 * physical address (HPA) or a guest physical address (GPA) and must
32634 * point to a physically contiguous block of memory.
32636 uint64_t resp_addr;
32639 * Enumeration denoting the RX, TX type of the resource.
32640 * This enumeration is used for resources that are similar for both
32641 * TX and RX paths of the chip.
32643 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
32645 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
32647 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
32648 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
32649 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
32650 /* The meter algorithm type. */
32651 uint8_t meter_type;
32652 /* RFC 2697 (srTCM) */
32653 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
32655 /* RFC 2698 (trTCM) */
32656 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
32658 /* RFC 4115 (trTCM) */
32659 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
32661 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
32662 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
32663 /* This value identifies a meter profile in CFA. */
32664 uint16_t meter_profile_id;
32666 * A value of 0xfff is considered invalid and implies the
32667 * profile is not configured.
32669 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
32671 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
32672 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
32674 * This field is reserved for the future use.
32675 * It shall be set to 0.
32678 /* A meter rate specified in bytes-per-second. */
32679 uint32_t commit_rate;
32680 /* The bandwidth value. */
32681 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
32682 UINT32_C(0xfffffff)
32683 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
32685 /* The granularity of the value (bits or bytes). */
32686 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
32687 UINT32_C(0x10000000)
32688 /* Value is in bits. */
32689 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
32690 (UINT32_C(0x0) << 28)
32691 /* Value is in bytes. */
32692 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
32693 (UINT32_C(0x1) << 28)
32694 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
32695 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
32696 /* bw_value_unit is 3 b */
32697 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
32698 UINT32_C(0xe0000000)
32699 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
32701 /* Value is in Mb or MB (base 10). */
32702 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
32703 (UINT32_C(0x0) << 29)
32704 /* Value is in Kb or KB (base 10). */
32705 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
32706 (UINT32_C(0x2) << 29)
32707 /* Value is in bits or bytes. */
32708 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
32709 (UINT32_C(0x4) << 29)
32710 /* Value is in Gb or GB (base 10). */
32711 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
32712 (UINT32_C(0x6) << 29)
32713 /* Value is in 1/100th of a percentage of total bandwidth. */
32714 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32715 (UINT32_C(0x1) << 29)
32717 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
32718 (UINT32_C(0x7) << 29)
32719 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
32720 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
32721 /* A meter burst size specified in bytes. */
32722 uint32_t commit_burst;
32723 /* The bandwidth value. */
32724 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
32725 UINT32_C(0xfffffff)
32726 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
32728 /* The granularity of the value (bits or bytes). */
32729 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
32730 UINT32_C(0x10000000)
32731 /* Value is in bits. */
32732 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
32733 (UINT32_C(0x0) << 28)
32734 /* Value is in bytes. */
32735 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
32736 (UINT32_C(0x1) << 28)
32737 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
32738 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
32739 /* bw_value_unit is 3 b */
32740 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
32741 UINT32_C(0xe0000000)
32742 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
32744 /* Value is in Mb or MB (base 10). */
32745 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
32746 (UINT32_C(0x0) << 29)
32747 /* Value is in Kb or KB (base 10). */
32748 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
32749 (UINT32_C(0x2) << 29)
32750 /* Value is in bits or bytes. */
32751 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
32752 (UINT32_C(0x4) << 29)
32753 /* Value is in Gb or GB (base 10). */
32754 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
32755 (UINT32_C(0x6) << 29)
32756 /* Value is in 1/100th of a percentage of total bandwidth. */
32757 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32758 (UINT32_C(0x1) << 29)
32759 /* Invalid value */
32760 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
32761 (UINT32_C(0x7) << 29)
32762 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
32763 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
32764 /* A meter rate specified in bytes-per-second. */
32765 uint32_t excess_peak_rate;
32766 /* The bandwidth value. */
32767 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
32768 UINT32_C(0xfffffff)
32769 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
32771 /* The granularity of the value (bits or bytes). */
32772 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
32773 UINT32_C(0x10000000)
32774 /* Value is in bits. */
32775 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
32776 (UINT32_C(0x0) << 28)
32777 /* Value is in bytes. */
32778 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
32779 (UINT32_C(0x1) << 28)
32780 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
32781 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
32782 /* bw_value_unit is 3 b */
32783 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
32784 UINT32_C(0xe0000000)
32785 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
32787 /* Value is in Mb or MB (base 10). */
32788 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
32789 (UINT32_C(0x0) << 29)
32790 /* Value is in Kb or KB (base 10). */
32791 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
32792 (UINT32_C(0x2) << 29)
32793 /* Value is in bits or bytes. */
32794 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
32795 (UINT32_C(0x4) << 29)
32796 /* Value is in Gb or GB (base 10). */
32797 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
32798 (UINT32_C(0x6) << 29)
32799 /* Value is in 1/100th of a percentage of total bandwidth. */
32800 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
32801 (UINT32_C(0x1) << 29)
32803 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
32804 (UINT32_C(0x7) << 29)
32805 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
32806 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
32807 /* A meter burst size specified in bytes. */
32808 uint32_t excess_peak_burst;
32809 /* The bandwidth value. */
32810 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
32811 UINT32_C(0xfffffff)
32812 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
32814 /* The granularity of the value (bits or bytes). */
32815 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
32816 UINT32_C(0x10000000)
32817 /* Value is in bits. */
32818 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
32819 (UINT32_C(0x0) << 28)
32820 /* Value is in bytes. */
32821 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
32822 (UINT32_C(0x1) << 28)
32823 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
32824 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
32825 /* bw_value_unit is 3 b */
32826 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
32827 UINT32_C(0xe0000000)
32828 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
32830 /* Value is in Mb or MB (base 10). */
32831 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
32832 (UINT32_C(0x0) << 29)
32833 /* Value is in Kb or KB (base 10). */
32834 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
32835 (UINT32_C(0x2) << 29)
32836 /* Value is in bits or bytes. */
32837 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
32838 (UINT32_C(0x4) << 29)
32839 /* Value is in Gb or GB (base 10). */
32840 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
32841 (UINT32_C(0x6) << 29)
32842 /* Value is in 1/100th of a percentage of total bandwidth. */
32843 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
32844 (UINT32_C(0x1) << 29)
32846 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
32847 (UINT32_C(0x7) << 29)
32848 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
32849 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
32852 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
32853 struct hwrm_cfa_meter_profile_cfg_output {
32854 /* The specific error status for the command. */
32855 uint16_t error_code;
32856 /* The HWRM command request type. */
32858 /* The sequence ID from the original command. */
32860 /* The length of the response data in number of bytes. */
32862 uint8_t unused_0[7];
32864 * This field is used in Output records to indicate that the output
32865 * is completely written to RAM. This field should be read as '1'
32866 * to indicate that the output has been completely written.
32867 * When writing a command completion or response to an internal processor,
32868 * the order of writes has to be such that this field is written last.
32873 /*********************************
32874 * hwrm_cfa_meter_instance_alloc *
32875 *********************************/
32878 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
32879 struct hwrm_cfa_meter_instance_alloc_input {
32880 /* The HWRM command request type. */
32883 * The completion ring to send the completion event on. This should
32884 * be the NQ ID returned from the `nq_alloc` HWRM command.
32886 uint16_t cmpl_ring;
32888 * The sequence ID is used by the driver for tracking multiple
32889 * commands. This ID is treated as opaque data by the firmware and
32890 * the value is returned in the `hwrm_resp_hdr` upon completion.
32894 * The target ID of the command:
32895 * * 0x0-0xFFF8 - The function ID
32896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32897 * * 0xFFFD - Reserved for user-space HWRM interface
32900 uint16_t target_id;
32902 * A physical address pointer pointing to a host buffer that the
32903 * command's response data will be written. This can be either a host
32904 * physical address (HPA) or a guest physical address (GPA) and must
32905 * point to a physically contiguous block of memory.
32907 uint64_t resp_addr;
32910 * Enumeration denoting the RX, TX type of the resource.
32911 * This enumeration is used for resources that are similar for both
32912 * TX and RX paths of the chip.
32914 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
32917 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
32920 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
32922 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
32923 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
32925 /* This value identifies a meter profile in CFA. */
32926 uint16_t meter_profile_id;
32928 * A value of 0xffff is considered invalid and implies the
32929 * profile is not configured.
32931 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
32933 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
32934 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
32935 uint8_t unused_1[4];
32938 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
32939 struct hwrm_cfa_meter_instance_alloc_output {
32940 /* The specific error status for the command. */
32941 uint16_t error_code;
32942 /* The HWRM command request type. */
32944 /* The sequence ID from the original command. */
32946 /* The length of the response data in number of bytes. */
32948 /* This value identifies a meter instance in CFA. */
32949 uint16_t meter_instance_id;
32951 * A value of 0xffff is considered invalid and implies the
32952 * instance is not configured.
32954 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
32956 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
32957 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
32958 uint8_t unused_0[5];
32960 * This field is used in Output records to indicate that the output
32961 * is completely written to RAM. This field should be read as '1'
32962 * to indicate that the output has been completely written.
32963 * When writing a command completion or response to an internal processor,
32964 * the order of writes has to be such that this field is written last.
32969 /*******************************
32970 * hwrm_cfa_meter_instance_cfg *
32971 *******************************/
32974 /* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
32975 struct hwrm_cfa_meter_instance_cfg_input {
32976 /* The HWRM command request type. */
32979 * The completion ring to send the completion event on. This should
32980 * be the NQ ID returned from the `nq_alloc` HWRM command.
32982 uint16_t cmpl_ring;
32984 * The sequence ID is used by the driver for tracking multiple
32985 * commands. This ID is treated as opaque data by the firmware and
32986 * the value is returned in the `hwrm_resp_hdr` upon completion.
32990 * The target ID of the command:
32991 * * 0x0-0xFFF8 - The function ID
32992 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32993 * * 0xFFFD - Reserved for user-space HWRM interface
32996 uint16_t target_id;
32998 * A physical address pointer pointing to a host buffer that the
32999 * command's response data will be written. This can be either a host
33000 * physical address (HPA) or a guest physical address (GPA) and must
33001 * point to a physically contiguous block of memory.
33003 uint64_t resp_addr;
33006 * Enumeration denoting the RX, TX type of the resource.
33007 * This enumeration is used for resources that are similar for both
33008 * TX and RX paths of the chip.
33010 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33012 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
33015 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
33017 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
33018 HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
33021 * This value identifies a new meter profile to be associated with
33022 * the meter instance specified in this command.
33024 uint16_t meter_profile_id;
33026 * A value of 0xffff is considered invalid and implies the
33027 * profile is not configured.
33029 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
33031 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
33032 HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
33034 * This value identifies the ID of a meter instance that needs to be updated with
33035 * a new meter profile specified in this command.
33037 uint16_t meter_instance_id;
33038 uint8_t unused_1[2];
33041 /* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
33042 struct hwrm_cfa_meter_instance_cfg_output {
33043 /* The specific error status for the command. */
33044 uint16_t error_code;
33045 /* The HWRM command request type. */
33047 /* The sequence ID from the original command. */
33049 /* The length of the response data in number of bytes. */
33051 uint8_t unused_0[7];
33053 * This field is used in Output records to indicate that the output
33054 * is completely written to RAM. This field should be read as '1'
33055 * to indicate that the output has been completely written.
33056 * When writing a command completion or response to an internal processor,
33057 * the order of writes has to be such that this field is written last.
33062 /********************************
33063 * hwrm_cfa_meter_instance_free *
33064 ********************************/
33067 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
33068 struct hwrm_cfa_meter_instance_free_input {
33069 /* The HWRM command request type. */
33072 * The completion ring to send the completion event on. This should
33073 * be the NQ ID returned from the `nq_alloc` HWRM command.
33075 uint16_t cmpl_ring;
33077 * The sequence ID is used by the driver for tracking multiple
33078 * commands. This ID is treated as opaque data by the firmware and
33079 * the value is returned in the `hwrm_resp_hdr` upon completion.
33083 * The target ID of the command:
33084 * * 0x0-0xFFF8 - The function ID
33085 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33086 * * 0xFFFD - Reserved for user-space HWRM interface
33089 uint16_t target_id;
33091 * A physical address pointer pointing to a host buffer that the
33092 * command's response data will be written. This can be either a host
33093 * physical address (HPA) or a guest physical address (GPA) and must
33094 * point to a physically contiguous block of memory.
33096 uint64_t resp_addr;
33099 * Enumeration denoting the RX, TX type of the resource.
33100 * This enumeration is used for resources that are similar for both
33101 * TX and RX paths of the chip.
33103 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
33105 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
33108 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
33110 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
33111 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
33113 /* This value identifies a meter instance in CFA. */
33114 uint16_t meter_instance_id;
33116 * A value of 0xfff is considered invalid and implies the
33117 * instance is not configured.
33119 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
33121 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
33122 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
33123 uint8_t unused_1[4];
33126 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
33127 struct hwrm_cfa_meter_instance_free_output {
33128 /* The specific error status for the command. */
33129 uint16_t error_code;
33130 /* The HWRM command request type. */
33132 /* The sequence ID from the original command. */
33134 /* The length of the response data in number of bytes. */
33136 uint8_t unused_0[7];
33138 * This field is used in Output records to indicate that the output
33139 * is completely written to RAM. This field should be read as '1'
33140 * to indicate that the output has been completely written.
33141 * When writing a command completion or response to an internal processor,
33142 * the order of writes has to be such that this field is written last.
33147 /*******************************
33148 * hwrm_cfa_decap_filter_alloc *
33149 *******************************/
33152 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
33153 struct hwrm_cfa_decap_filter_alloc_input {
33154 /* The HWRM command request type. */
33157 * The completion ring to send the completion event on. This should
33158 * be the NQ ID returned from the `nq_alloc` HWRM command.
33160 uint16_t cmpl_ring;
33162 * The sequence ID is used by the driver for tracking multiple
33163 * commands. This ID is treated as opaque data by the firmware and
33164 * the value is returned in the `hwrm_resp_hdr` upon completion.
33168 * The target ID of the command:
33169 * * 0x0-0xFFF8 - The function ID
33170 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33171 * * 0xFFFD - Reserved for user-space HWRM interface
33174 uint16_t target_id;
33176 * A physical address pointer pointing to a host buffer that the
33177 * command's response data will be written. This can be either a host
33178 * physical address (HPA) or a guest physical address (GPA) and must
33179 * point to a physically contiguous block of memory.
33181 uint64_t resp_addr;
33183 /* ovs_tunnel is 1 b */
33184 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
33188 * This bit must be '1' for the tunnel_type field to be
33191 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
33194 * This bit must be '1' for the tunnel_id field to be
33197 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
33200 * This bit must be '1' for the src_macaddr field to be
33203 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
33206 * This bit must be '1' for the dst_macaddr field to be
33209 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
33212 * This bit must be '1' for the ovlan_vid field to be
33215 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
33218 * This bit must be '1' for the ivlan_vid field to be
33221 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
33224 * This bit must be '1' for the t_ovlan_vid field to be
33227 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
33230 * This bit must be '1' for the t_ivlan_vid field to be
33233 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
33236 * This bit must be '1' for the ethertype field to be
33239 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
33242 * This bit must be '1' for the src_ipaddr field to be
33245 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
33248 * This bit must be '1' for the dst_ipaddr field to be
33251 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
33254 * This bit must be '1' for the ipaddr_type field to be
33257 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
33260 * This bit must be '1' for the ip_protocol field to be
33263 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
33266 * This bit must be '1' for the src_port field to be
33269 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
33272 * This bit must be '1' for the dst_port field to be
33275 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
33278 * This bit must be '1' for the dst_id field to be
33281 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
33284 * This bit must be '1' for the mirror_vnic_id field to be
33287 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
33290 * Tunnel identifier.
33291 * Virtual Network Identifier (VNI). Only valid with
33292 * tunnel_types VXLAN, NVGRE, and Geneve.
33293 * Only lower 24-bits of VNI field are used
33294 * in setting up the filter.
33296 uint32_t tunnel_id;
33298 uint8_t tunnel_type;
33300 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33302 /* Virtual eXtensible Local Area Network (VXLAN) */
33303 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33305 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33306 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33308 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33309 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33312 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33314 /* Generic Network Virtualization Encapsulation (Geneve) */
33315 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33317 /* Multi-Protocol Label Switching (MPLS) */
33318 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33320 /* Stateless Transport Tunnel (STT) */
33321 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
33323 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33324 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33326 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33327 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33329 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33330 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33332 /* Use fixed layer 2 ether type of 0xFFFF */
33333 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33335 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33336 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33338 /* Any tunneled traffic */
33339 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33341 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33342 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33346 * This value indicates the source MAC address in
33347 * the Ethernet header.
33349 uint8_t src_macaddr[6];
33350 uint8_t unused_2[2];
33352 * This value indicates the destination MAC address in
33353 * the Ethernet header.
33355 uint8_t dst_macaddr[6];
33357 * This value indicates the VLAN ID of the outer VLAN tag
33358 * in the Ethernet header.
33360 uint16_t ovlan_vid;
33362 * This value indicates the VLAN ID of the inner VLAN tag
33363 * in the Ethernet header.
33365 uint16_t ivlan_vid;
33367 * This value indicates the VLAN ID of the outer VLAN tag
33368 * in the tunnel Ethernet header.
33370 uint16_t t_ovlan_vid;
33372 * This value indicates the VLAN ID of the inner VLAN tag
33373 * in the tunnel Ethernet header.
33375 uint16_t t_ivlan_vid;
33376 /* This value indicates the ethertype in the Ethernet header. */
33377 uint16_t ethertype;
33379 * This value indicates the type of IP address.
33382 * All others are invalid.
33384 uint8_t ip_addr_type;
33386 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
33389 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
33392 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
33394 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
33395 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
33397 * The value of protocol filed in IP header.
33398 * Applies to UDP and TCP traffic.
33402 uint8_t ip_protocol;
33404 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
33407 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
33410 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
33412 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
33413 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
33417 * The value of source IP address to be used in filtering.
33418 * For IPv4, first four bytes represent the IP address.
33420 uint32_t src_ipaddr[4];
33422 * The value of destination IP address to be used in filtering.
33423 * For IPv4, first four bytes represent the IP address.
33425 uint32_t dst_ipaddr[4];
33427 * The value of source port to be used in filtering.
33428 * Applies to UDP and TCP traffic.
33432 * The value of destination port to be used in filtering.
33433 * Applies to UDP and TCP traffic.
33437 * If set, this value shall represent the
33438 * Logical VNIC ID of the destination VNIC for the RX
33443 * If set, this value shall represent the L2 context that matches the L2
33444 * information of the decap filter.
33446 uint16_t l2_ctxt_ref_id;
33449 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
33450 struct hwrm_cfa_decap_filter_alloc_output {
33451 /* The specific error status for the command. */
33452 uint16_t error_code;
33453 /* The HWRM command request type. */
33455 /* The sequence ID from the original command. */
33457 /* The length of the response data in number of bytes. */
33459 /* This value is an opaque id into CFA data structures. */
33460 uint32_t decap_filter_id;
33461 uint8_t unused_0[3];
33463 * This field is used in Output records to indicate that the output
33464 * is completely written to RAM. This field should be read as '1'
33465 * to indicate that the output has been completely written.
33466 * When writing a command completion or response to an internal processor,
33467 * the order of writes has to be such that this field is written last.
33472 /******************************
33473 * hwrm_cfa_decap_filter_free *
33474 ******************************/
33477 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
33478 struct hwrm_cfa_decap_filter_free_input {
33479 /* The HWRM command request type. */
33482 * The completion ring to send the completion event on. This should
33483 * be the NQ ID returned from the `nq_alloc` HWRM command.
33485 uint16_t cmpl_ring;
33487 * The sequence ID is used by the driver for tracking multiple
33488 * commands. This ID is treated as opaque data by the firmware and
33489 * the value is returned in the `hwrm_resp_hdr` upon completion.
33493 * The target ID of the command:
33494 * * 0x0-0xFFF8 - The function ID
33495 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33496 * * 0xFFFD - Reserved for user-space HWRM interface
33499 uint16_t target_id;
33501 * A physical address pointer pointing to a host buffer that the
33502 * command's response data will be written. This can be either a host
33503 * physical address (HPA) or a guest physical address (GPA) and must
33504 * point to a physically contiguous block of memory.
33506 uint64_t resp_addr;
33507 /* This value is an opaque id into CFA data structures. */
33508 uint32_t decap_filter_id;
33509 uint8_t unused_0[4];
33512 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
33513 struct hwrm_cfa_decap_filter_free_output {
33514 /* The specific error status for the command. */
33515 uint16_t error_code;
33516 /* The HWRM command request type. */
33518 /* The sequence ID from the original command. */
33520 /* The length of the response data in number of bytes. */
33522 uint8_t unused_0[7];
33524 * This field is used in Output records to indicate that the output
33525 * is completely written to RAM. This field should be read as '1'
33526 * to indicate that the output has been completely written.
33527 * When writing a command completion or response to an internal processor,
33528 * the order of writes has to be such that this field is written last.
33533 /***********************
33534 * hwrm_cfa_flow_alloc *
33535 ***********************/
33538 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
33539 struct hwrm_cfa_flow_alloc_input {
33540 /* The HWRM command request type. */
33543 * The completion ring to send the completion event on. This should
33544 * be the NQ ID returned from the `nq_alloc` HWRM command.
33546 uint16_t cmpl_ring;
33548 * The sequence ID is used by the driver for tracking multiple
33549 * commands. This ID is treated as opaque data by the firmware and
33550 * the value is returned in the `hwrm_resp_hdr` upon completion.
33554 * The target ID of the command:
33555 * * 0x0-0xFFF8 - The function ID
33556 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33557 * * 0xFFFD - Reserved for user-space HWRM interface
33560 uint16_t target_id;
33562 * A physical address pointer pointing to a host buffer that the
33563 * command's response data will be written. This can be either a host
33564 * physical address (HPA) or a guest physical address (GPA) and must
33565 * point to a physically contiguous block of memory.
33567 uint64_t resp_addr;
33569 /* tunnel is 1 b */
33570 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
33572 /* num_vlan is 2 b */
33573 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
33575 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
33577 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
33578 (UINT32_C(0x0) << 1)
33580 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
33581 (UINT32_C(0x1) << 1)
33583 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
33584 (UINT32_C(0x2) << 1)
33585 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
33586 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
33587 /* Enumeration denoting the Flow Type. */
33588 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
33590 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
33592 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
33593 (UINT32_C(0x0) << 3)
33595 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
33596 (UINT32_C(0x1) << 3)
33598 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
33599 (UINT32_C(0x2) << 3)
33600 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
33601 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
33603 * when set to 1, indicates TX flow offload for function specified in src_fid and
33604 * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
33605 * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
33606 * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
33607 * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
33608 * belong to the children VFs of the same PF to indicate VM to VM flow.
33610 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
33613 * when set to 1, indicates RX flow offload for function specified in dst_fid and
33614 * the src_fid should be set to invalid value.
33616 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
33619 * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
33620 * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
33621 * This flag is only valid when the flow direction is RX.
33623 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
33625 /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
33626 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
33633 /* Tunnel handle valid when tunnel flag is set. */
33634 uint32_t tunnel_handle;
33635 uint16_t action_flags;
33637 * Setting of this flag indicates drop action. If this flag is not set,
33638 * then it should be considered accept action.
33640 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
33642 /* recycle is 1 b */
33643 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
33646 * Setting of this flag indicates drop action. If this flag is not set,
33647 * then it should be considered accept action.
33649 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
33652 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
33654 /* tunnel is 1 b */
33655 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
33657 /* nat_src is 1 b */
33658 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
33660 /* nat_dest is 1 b */
33661 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
33663 /* nat_ipv4_address is 1 b */
33664 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
33666 /* l2_header_rewrite is 1 b */
33667 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
33669 /* ttl_decrement is 1 b */
33670 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
33673 * If set to 1 and flow direction is TX, it indicates decap of L2 header
33674 * and encap of tunnel header. If set to 1 and flow direction is RX, it
33675 * indicates decap of tunnel header and encap L2 header. The type of tunnel
33676 * is specified in the tunnel_type field.
33678 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
33680 /* If set to 1, flow aging is enabled for this flow. */
33681 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
33684 * If set to 1 an attempt will be made to try to offload this flow to the
33685 * most optimal flow table resource. If set to 0, the flow will be
33686 * placed to the default flow table resource.
33688 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
33691 * If set to 1 there will be no attempt to allocate an on-chip try to
33692 * offload this flow. If set to 0, which will keep compatibility with the
33693 * older drivers, will cause the FW to attempt to allocate an on-chip flow
33694 * counter for the newly created flow. This will keep the existing behavior
33695 * with EM flows which always had an associated flow counter.
33697 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
33700 * Tx Flow: pf or vf fid.
33704 /* VLAN tpid, valid when push_vlan flag is set. */
33705 uint16_t l2_rewrite_vlan_tpid;
33706 /* VLAN tci, valid when push_vlan flag is set. */
33707 uint16_t l2_rewrite_vlan_tci;
33708 /* Meter id, valid when meter flag is set. */
33709 uint16_t act_meter_id;
33710 /* Flow with the same l2 context tcam key. */
33711 uint16_t ref_flow_handle;
33712 /* This value sets the match value for the ethertype. */
33713 uint16_t ethertype;
33714 /* valid when num tags is 1 or 2. */
33715 uint16_t outer_vlan_tci;
33716 /* This value sets the match value for the Destination MAC address. */
33718 /* valid when num tags is 2. */
33719 uint16_t inner_vlan_tci;
33720 /* This value sets the match value for the Source MAC address. */
33722 /* The bit length of destination IP address mask. */
33723 uint8_t ip_dst_mask_len;
33724 /* The bit length of source IP address mask. */
33725 uint8_t ip_src_mask_len;
33726 /* The value of destination IPv4/IPv6 address. */
33727 uint32_t ip_dst[4];
33728 /* The source IPv4/IPv6 address. */
33729 uint32_t ip_src[4];
33731 * The value of source port.
33732 * Applies to UDP and TCP traffic.
33734 uint16_t l4_src_port;
33736 * The value of source port mask.
33737 * Applies to UDP and TCP traffic.
33739 uint16_t l4_src_port_mask;
33741 * The value of destination port.
33742 * Applies to UDP and TCP traffic.
33744 uint16_t l4_dst_port;
33746 * The value of destination port mask.
33747 * Applies to UDP and TCP traffic.
33749 uint16_t l4_dst_port_mask;
33751 * NAT IPv4/6 address based on address type flag.
33752 * 0 values are ignored.
33754 uint32_t nat_ip_address[4];
33755 /* L2 header re-write Destination MAC address. */
33756 uint16_t l2_rewrite_dmac[3];
33758 * The NAT source/destination port based on direction flag.
33759 * Applies to UDP and TCP traffic.
33760 * 0 values are ignored.
33763 /* L2 header re-write Source MAC address. */
33764 uint16_t l2_rewrite_smac[3];
33765 /* The value of ip protocol. */
33768 uint8_t tunnel_type;
33770 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
33772 /* Virtual eXtensible Local Area Network (VXLAN) */
33773 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
33775 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
33776 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
33778 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
33779 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
33782 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
33784 /* Generic Network Virtualization Encapsulation (Geneve) */
33785 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
33787 /* Multi-Protocol Label Switching (MPLS) */
33788 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
33790 /* Stateless Transport Tunnel (STT) */
33791 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
33793 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
33794 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
33796 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
33797 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
33799 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
33800 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
33802 /* Use fixed layer 2 ether type of 0xFFFF */
33803 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
33805 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
33806 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
33808 /* Any tunneled traffic */
33809 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
33811 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
33812 HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
33815 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */
33816 struct hwrm_cfa_flow_alloc_output {
33817 /* The specific error status for the command. */
33818 uint16_t error_code;
33819 /* The HWRM command request type. */
33821 /* The sequence ID from the original command. */
33823 /* The length of the response data in number of bytes. */
33825 /* Flow record index. */
33826 uint16_t flow_handle;
33827 uint8_t unused_0[2];
33829 * The flow id value in bit 0-29 is the actual ID of the flow
33830 * associated with this filter and it shall be used to match
33831 * and associate the flow identifier returned in completion
33832 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
33833 * shall indicate no valid flow id.
33836 /* Indicate the flow id value. */
33837 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
33838 UINT32_C(0x3fffffff)
33839 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
33840 /* Indicate type of the flow. */
33841 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
33842 UINT32_C(0x40000000)
33844 * If this bit set to 0, then it indicates that the flow is
33847 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
33848 (UINT32_C(0x0) << 30)
33850 * If this bit is set to 1, then it indicates that the flow is
33853 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
33854 (UINT32_C(0x1) << 30)
33855 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
33856 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
33857 /* Indicate the flow direction. */
33858 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
33859 UINT32_C(0x80000000)
33860 /* If this bit set to 0, then it indicates rx flow. */
33861 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
33862 (UINT32_C(0x0) << 31)
33863 /* If this bit is set to 1, then it indicates that tx flow. */
33864 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
33865 (UINT32_C(0x1) << 31)
33866 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
33867 HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
33868 /* This value identifies a set of CFA data structures used for a flow. */
33869 uint64_t ext_flow_handle;
33870 uint32_t flow_counter_id;
33871 uint8_t unused_1[3];
33873 * This field is used in Output records to indicate that the output
33874 * is completely written to RAM. This field should be read as '1'
33875 * to indicate that the output has been completely written.
33876 * When writing a command completion or response to an internal processor,
33877 * the order of writes has to be such that this field is written last.
33882 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
33883 struct hwrm_cfa_flow_alloc_cmd_err {
33885 * command specific error codes that goes to
33886 * the cmd_err field in Common HWRM Error Response.
33889 /* Unknown error */
33890 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33891 /* No more L2 Context TCAM */
33892 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
33893 /* No more action records */
33894 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
33895 /* No more flow counters */
33896 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
33897 /* No more wild-card TCAM */
33898 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
33899 /* Hash collsion in exact match tables */
33900 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
33901 /* Key is already installed */
33902 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
33903 /* Flow Context DB is out of resource */
33904 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
33905 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
33906 HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
33907 uint8_t unused_0[7];
33910 /**********************
33911 * hwrm_cfa_flow_free *
33912 **********************/
33915 /* hwrm_cfa_flow_free_input (size:256b/32B) */
33916 struct hwrm_cfa_flow_free_input {
33917 /* The HWRM command request type. */
33920 * The completion ring to send the completion event on. This should
33921 * be the NQ ID returned from the `nq_alloc` HWRM command.
33923 uint16_t cmpl_ring;
33925 * The sequence ID is used by the driver for tracking multiple
33926 * commands. This ID is treated as opaque data by the firmware and
33927 * the value is returned in the `hwrm_resp_hdr` upon completion.
33931 * The target ID of the command:
33932 * * 0x0-0xFFF8 - The function ID
33933 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33934 * * 0xFFFD - Reserved for user-space HWRM interface
33937 uint16_t target_id;
33939 * A physical address pointer pointing to a host buffer that the
33940 * command's response data will be written. This can be either a host
33941 * physical address (HPA) or a guest physical address (GPA) and must
33942 * point to a physically contiguous block of memory.
33944 uint64_t resp_addr;
33945 /* Flow record index. */
33946 uint16_t flow_handle;
33948 /* Flow counter id to be freed. */
33949 uint32_t flow_counter_id;
33950 /* This value identifies a set of CFA data structures used for a flow. */
33951 uint64_t ext_flow_handle;
33954 /* hwrm_cfa_flow_free_output (size:256b/32B) */
33955 struct hwrm_cfa_flow_free_output {
33956 /* The specific error status for the command. */
33957 uint16_t error_code;
33958 /* The HWRM command request type. */
33960 /* The sequence ID from the original command. */
33962 /* The length of the response data in number of bytes. */
33964 /* packet is 64 b */
33968 uint8_t unused_0[7];
33970 * This field is used in Output records to indicate that the output
33971 * is completely written to RAM. This field should be read as '1'
33972 * to indicate that the output has been completely written.
33973 * When writing a command completion or response to an internal processor,
33974 * the order of writes has to be such that this field is written last.
33979 /* hwrm_cfa_flow_action_data (size:960b/120B) */
33980 struct hwrm_cfa_flow_action_data {
33981 uint16_t action_flags;
33982 /* Setting of this flag indicates accept action. */
33983 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
33985 /* Setting of this flag indicates recycle action. */
33986 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
33988 /* Setting of this flag indicates drop action. */
33989 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
33991 /* Setting of this flag indicates meter action. */
33992 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
33994 /* Setting of this flag indicates tunnel action. */
33995 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
33998 * If set to 1 and flow direction is TX, it indicates decap of L2 header
33999 * and encap of tunnel header. If set to 1 and flow direction is RX, it
34000 * indicates decap of tunnel header and encap L2 header.
34002 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
34004 /* Setting of this flag indicates ttl decrement action. */
34005 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
34007 /* If set to 1, flow aging is enabled for this flow. */
34008 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
34010 /* Setting of this flag indicates encap action. */
34011 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
34013 /* Setting of this flag indicates decap action. */
34014 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
34017 uint16_t act_meter_id;
34020 /* vport number. */
34022 /* The NAT source/destination. */
34024 uint16_t unused_0[3];
34025 /* NAT IPv4/IPv6 address. */
34026 uint32_t nat_ip_address[4];
34027 /* Encapsulation Type. */
34028 uint8_t encap_type;
34029 /* Virtual eXtensible Local Area Network (VXLAN) */
34030 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
34031 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34032 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
34033 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
34034 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
34036 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
34037 /* Generic Network Virtualization Encapsulation (Geneve) */
34038 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
34039 /* Multi-Protocol Label Switching (MPLS) */
34040 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
34042 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
34043 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34044 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
34045 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34046 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
34047 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34048 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
34049 /* Use fixed layer 2 ether type of 0xFFFF */
34050 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
34051 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34052 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
34053 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
34054 HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
34056 /* This value is encap data for the associated encap type. */
34057 uint32_t encap_data[20];
34060 /* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
34061 struct hwrm_cfa_flow_tunnel_hdr_data {
34063 uint8_t tunnel_type;
34065 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
34067 /* Virtual eXtensible Local Area Network (VXLAN) */
34068 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
34070 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
34071 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
34073 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
34074 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
34077 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
34079 /* Generic Network Virtualization Encapsulation (Geneve) */
34080 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
34082 /* Multi-Protocol Label Switching (MPLS) */
34083 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
34085 /* Stateless Transport Tunnel (STT) */
34086 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
34088 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
34089 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
34091 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
34092 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
34094 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
34095 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
34097 /* Use fixed layer 2 ether type of 0xFFFF */
34098 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
34100 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
34101 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
34103 /* Any tunneled traffic */
34104 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
34106 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
34107 HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
34110 * Tunnel identifier.
34111 * Virtual Network Identifier (VNI).
34113 uint32_t tunnel_id;
34116 /* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
34117 struct hwrm_cfa_flow_l4_key_data {
34118 /* The value of source port. */
34119 uint16_t l4_src_port;
34120 /* The value of destination port. */
34121 uint16_t l4_dst_port;
34125 /* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
34126 struct hwrm_cfa_flow_l3_key_data {
34127 /* The value of ip protocol. */
34128 uint8_t ip_protocol;
34129 uint8_t unused_0[7];
34130 /* The value of destination IPv4/IPv6 address. */
34131 uint32_t ip_dst[4];
34132 /* The source IPv4/IPv6 address. */
34133 uint32_t ip_src[4];
34134 /* NAT IPv4/IPv6 address. */
34135 uint32_t nat_ip_address[4];
34136 uint32_t unused[2];
34139 /* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
34140 struct hwrm_cfa_flow_l2_key_data {
34141 /* Destination MAC address. */
34144 /* Source MAC address. */
34147 /* L2 header re-write Destination MAC address. */
34148 uint16_t l2_rewrite_dmac[3];
34150 /* L2 header re-write Source MAC address. */
34151 uint16_t l2_rewrite_smac[3];
34153 uint16_t ethertype;
34154 /* Number of VLAN tags. */
34155 uint16_t num_vlan_tags;
34157 uint16_t l2_rewrite_vlan_tpid;
34159 uint16_t l2_rewrite_vlan_tci;
34160 uint8_t unused_3[2];
34161 /* Outer VLAN TPID. */
34162 uint16_t ovlan_tpid;
34163 /* Outer VLAN TCI. */
34164 uint16_t ovlan_tci;
34165 /* Inner VLAN TPID. */
34166 uint16_t ivlan_tpid;
34167 /* Inner VLAN TCI. */
34168 uint16_t ivlan_tci;
34172 /* hwrm_cfa_flow_key_data (size:4160b/520B) */
34173 struct hwrm_cfa_flow_key_data {
34174 /* Flow associated tunnel L2 header key info. */
34175 uint32_t t_l2_key_data[14];
34176 /* Flow associated tunnel L2 header mask info. */
34177 uint32_t t_l2_key_mask[14];
34178 /* Flow associated tunnel L3 header key info. */
34179 uint32_t t_l3_key_data[16];
34180 /* Flow associated tunnel L3 header mask info. */
34181 uint32_t t_l3_key_mask[16];
34182 /* Flow associated tunnel L4 header key info. */
34183 uint32_t t_l4_key_data[2];
34184 /* Flow associated tunnel L4 header mask info. */
34185 uint32_t t_l4_key_mask[2];
34186 /* Flow associated tunnel header info. */
34187 uint32_t tunnel_hdr[2];
34188 /* Flow associated L2 header key info. */
34189 uint32_t l2_key_data[14];
34190 /* Flow associated L2 header mask info. */
34191 uint32_t l2_key_mask[14];
34192 /* Flow associated L3 header key info. */
34193 uint32_t l3_key_data[16];
34194 /* Flow associated L3 header mask info. */
34195 uint32_t l3_key_mask[16];
34196 /* Flow associated L4 header key info. */
34197 uint32_t l4_key_data[2];
34198 /* Flow associated L4 header mask info. */
34199 uint32_t l4_key_mask[2];
34202 /**********************
34203 * hwrm_cfa_flow_info *
34204 **********************/
34207 /* hwrm_cfa_flow_info_input (size:256b/32B) */
34208 struct hwrm_cfa_flow_info_input {
34209 /* The HWRM command request type. */
34212 * The completion ring to send the completion event on. This should
34213 * be the NQ ID returned from the `nq_alloc` HWRM command.
34215 uint16_t cmpl_ring;
34217 * The sequence ID is used by the driver for tracking multiple
34218 * commands. This ID is treated as opaque data by the firmware and
34219 * the value is returned in the `hwrm_resp_hdr` upon completion.
34223 * The target ID of the command:
34224 * * 0x0-0xFFF8 - The function ID
34225 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34226 * * 0xFFFD - Reserved for user-space HWRM interface
34229 uint16_t target_id;
34231 * A physical address pointer pointing to a host buffer that the
34232 * command's response data will be written. This can be either a host
34233 * physical address (HPA) or a guest physical address (GPA) and must
34234 * point to a physically contiguous block of memory.
34236 uint64_t resp_addr;
34237 /* Flow record index. */
34238 uint16_t flow_handle;
34239 /* Max flow handle */
34240 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
34242 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
34243 /* CNP flow handle */
34244 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
34246 /* RoCEv1 flow handle */
34247 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
34249 /* RoCEv2 flow handle */
34250 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
34252 /* Direction rx = 1 */
34253 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
34255 uint8_t unused_0[6];
34256 /* This value identifies a set of CFA data structures used for a flow. */
34257 uint64_t ext_flow_handle;
34260 /* hwrm_cfa_flow_info_output (size:5632b/704B) */
34261 struct hwrm_cfa_flow_info_output {
34262 /* The specific error status for the command. */
34263 uint16_t error_code;
34264 /* The HWRM command request type. */
34266 /* The sequence ID from the original command. */
34268 /* The length of the response data in number of bytes. */
34271 /* When set to 1, indicates the configuration is the TX flow. */
34272 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
34273 /* When set to 1, indicates the configuration is the RX flow. */
34274 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
34275 /* profile is 8 b */
34277 /* src_fid is 16 b */
34279 /* dst_fid is 16 b */
34281 /* l2_ctxt_id is 16 b */
34282 uint16_t l2_ctxt_id;
34283 /* em_info is 64 b */
34285 /* tcam_info is 64 b */
34286 uint64_t tcam_info;
34287 /* vfp_tcam_info is 64 b */
34288 uint64_t vfp_tcam_info;
34289 /* ar_id is 16 b */
34291 /* flow_handle is 16 b */
34292 uint16_t flow_handle;
34293 /* tunnel_handle is 32 b */
34294 uint32_t tunnel_handle;
34295 /* The flow aging timer for the flow, the unit is 100 milliseconds */
34296 uint16_t flow_timer;
34297 uint8_t unused_0[6];
34298 /* Flow associated L2, L3 and L4 headers info. */
34299 uint32_t flow_key_data[130];
34300 /* Flow associated action record info. */
34301 uint32_t flow_action_info[30];
34302 uint8_t unused_1[7];
34304 * This field is used in Output records to indicate that the output
34305 * is completely written to RAM. This field should be read as '1'
34306 * to indicate that the output has been completely written.
34307 * When writing a command completion or response to an internal processor,
34308 * the order of writes has to be such that this field is written last.
34313 /***********************
34314 * hwrm_cfa_flow_flush *
34315 ***********************/
34318 /* hwrm_cfa_flow_flush_input (size:256b/32B) */
34319 struct hwrm_cfa_flow_flush_input {
34320 /* The HWRM command request type. */
34323 * The completion ring to send the completion event on. This should
34324 * be the NQ ID returned from the `nq_alloc` HWRM command.
34326 uint16_t cmpl_ring;
34328 * The sequence ID is used by the driver for tracking multiple
34329 * commands. This ID is treated as opaque data by the firmware and
34330 * the value is returned in the `hwrm_resp_hdr` upon completion.
34334 * The target ID of the command:
34335 * * 0x0-0xFFF8 - The function ID
34336 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34337 * * 0xFFFD - Reserved for user-space HWRM interface
34340 uint16_t target_id;
34342 * A physical address pointer pointing to a host buffer that the
34343 * command's response data will be written. This can be either a host
34344 * physical address (HPA) or a guest physical address (GPA) and must
34345 * point to a physically contiguous block of memory.
34347 uint64_t resp_addr;
34348 /* flags is 32 b */
34351 * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
34352 * fields are valid. The flow flush operation should only flush the flows from the
34353 * flow table specified. This flag is set to 0 by older driver. For older firmware,
34354 * setting this flag has no effect.
34356 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
34359 * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
34360 * context memory tables etc. This flag is set to 0 by older driver. For older firmware,
34361 * setting this flag has no effect.
34363 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
34366 * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.
34367 * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.
34369 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \
34371 /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
34372 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
34373 UINT32_C(0x8000000)
34375 * This specifies the size of flow handle entries provided by the driver
34376 * in the flow table specified below. Only two flow handle size enums are defined.
34378 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
34379 UINT32_C(0xc0000000)
34380 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
34382 /* The flow handle is 16bit */
34383 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
34384 (UINT32_C(0x0) << 30)
34385 /* The flow handle is 64bit */
34386 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
34387 (UINT32_C(0x1) << 30)
34388 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
34389 HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
34390 /* Specify page size of the flow table memory. */
34392 /* The page size is 4K */
34393 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
34394 /* The page size is 8K */
34395 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
34396 /* The page size is 64K */
34397 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
34398 /* The page size is 256K */
34399 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
34400 /* The page size is 1M */
34401 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
34402 /* The page size is 2M */
34403 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
34404 /* The page size is 4M */
34405 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
34406 /* The page size is 1G */
34407 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
34408 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
34409 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
34410 /* FLow table memory indirect levels. */
34411 uint8_t page_level;
34412 /* PBL pointer is physical start address. */
34413 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
34414 /* PBL pointer points to PTE table. */
34415 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
34416 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
34417 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
34418 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
34419 HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
34420 /* number of flows in the flow table */
34421 uint16_t num_flows;
34422 /* Pointer to the PBL, or PDL depending on number of levels */
34426 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
34427 struct hwrm_cfa_flow_flush_output {
34428 /* The specific error status for the command. */
34429 uint16_t error_code;
34430 /* The HWRM command request type. */
34432 /* The sequence ID from the original command. */
34434 /* The length of the response data in number of bytes. */
34436 uint8_t unused_0[7];
34438 * This field is used in Output records to indicate that the output
34439 * is completely written to RAM. This field should be read as '1'
34440 * to indicate that the output has been completely written.
34441 * When writing a command completion or response to an internal processor,
34442 * the order of writes has to be such that this field is written last.
34447 /***********************
34448 * hwrm_cfa_flow_stats *
34449 ***********************/
34452 /* hwrm_cfa_flow_stats_input (size:640b/80B) */
34453 struct hwrm_cfa_flow_stats_input {
34454 /* The HWRM command request type. */
34457 * The completion ring to send the completion event on. This should
34458 * be the NQ ID returned from the `nq_alloc` HWRM command.
34460 uint16_t cmpl_ring;
34462 * The sequence ID is used by the driver for tracking multiple
34463 * commands. This ID is treated as opaque data by the firmware and
34464 * the value is returned in the `hwrm_resp_hdr` upon completion.
34468 * The target ID of the command:
34469 * * 0x0-0xFFF8 - The function ID
34470 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34471 * * 0xFFFD - Reserved for user-space HWRM interface
34474 uint16_t target_id;
34476 * A physical address pointer pointing to a host buffer that the
34477 * command's response data will be written. This can be either a host
34478 * physical address (HPA) or a guest physical address (GPA) and must
34479 * point to a physically contiguous block of memory.
34481 uint64_t resp_addr;
34483 uint16_t num_flows;
34485 uint16_t flow_handle_0;
34487 uint16_t flow_handle_1;
34489 uint16_t flow_handle_2;
34491 uint16_t flow_handle_3;
34493 uint16_t flow_handle_4;
34495 uint16_t flow_handle_5;
34497 uint16_t flow_handle_6;
34499 uint16_t flow_handle_7;
34501 uint16_t flow_handle_8;
34503 uint16_t flow_handle_9;
34504 uint8_t unused_0[2];
34505 /* Flow ID of a flow. */
34506 uint32_t flow_id_0;
34507 /* Flow ID of a flow. */
34508 uint32_t flow_id_1;
34509 /* Flow ID of a flow. */
34510 uint32_t flow_id_2;
34511 /* Flow ID of a flow. */
34512 uint32_t flow_id_3;
34513 /* Flow ID of a flow. */
34514 uint32_t flow_id_4;
34515 /* Flow ID of a flow. */
34516 uint32_t flow_id_5;
34517 /* Flow ID of a flow. */
34518 uint32_t flow_id_6;
34519 /* Flow ID of a flow. */
34520 uint32_t flow_id_7;
34521 /* Flow ID of a flow. */
34522 uint32_t flow_id_8;
34523 /* Flow ID of a flow. */
34524 uint32_t flow_id_9;
34527 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
34528 struct hwrm_cfa_flow_stats_output {
34529 /* The specific error status for the command. */
34530 uint16_t error_code;
34531 /* The HWRM command request type. */
34533 /* The sequence ID from the original command. */
34535 /* The length of the response data in number of bytes. */
34537 /* packet_0 is 64 b */
34539 /* packet_1 is 64 b */
34541 /* packet_2 is 64 b */
34543 /* packet_3 is 64 b */
34545 /* packet_4 is 64 b */
34547 /* packet_5 is 64 b */
34549 /* packet_6 is 64 b */
34551 /* packet_7 is 64 b */
34553 /* packet_8 is 64 b */
34555 /* packet_9 is 64 b */
34557 /* byte_0 is 64 b */
34559 /* byte_1 is 64 b */
34561 /* byte_2 is 64 b */
34563 /* byte_3 is 64 b */
34565 /* byte_4 is 64 b */
34567 /* byte_5 is 64 b */
34569 /* byte_6 is 64 b */
34571 /* byte_7 is 64 b */
34573 /* byte_8 is 64 b */
34575 /* byte_9 is 64 b */
34577 uint8_t unused_0[7];
34579 * This field is used in Output records to indicate that the output
34580 * is completely written to RAM. This field should be read as '1'
34581 * to indicate that the output has been completely written.
34582 * When writing a command completion or response to an internal processor,
34583 * the order of writes has to be such that this field is written last.
34588 /***********************************
34589 * hwrm_cfa_flow_aging_timer_reset *
34590 ***********************************/
34593 /* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
34594 struct hwrm_cfa_flow_aging_timer_reset_input {
34595 /* The HWRM command request type. */
34598 * The completion ring to send the completion event on. This should
34599 * be the NQ ID returned from the `nq_alloc` HWRM command.
34601 uint16_t cmpl_ring;
34603 * The sequence ID is used by the driver for tracking multiple
34604 * commands. This ID is treated as opaque data by the firmware and
34605 * the value is returned in the `hwrm_resp_hdr` upon completion.
34609 * The target ID of the command:
34610 * * 0x0-0xFFF8 - The function ID
34611 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34612 * * 0xFFFD - Reserved for user-space HWRM interface
34615 uint16_t target_id;
34617 * A physical address pointer pointing to a host buffer that the
34618 * command's response data will be written. This can be either a host
34619 * physical address (HPA) or a guest physical address (GPA) and must
34620 * point to a physically contiguous block of memory.
34622 uint64_t resp_addr;
34623 /* Flow record index. */
34624 uint16_t flow_handle;
34625 uint8_t unused_0[2];
34627 * New flow timer value for the flow specified in the ext_flow_handle.
34628 * The flow timer unit is 100ms.
34630 uint32_t flow_timer;
34631 /* This value identifies a set of CFA data structures used for a flow. */
34632 uint64_t ext_flow_handle;
34635 /* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
34636 struct hwrm_cfa_flow_aging_timer_reset_output {
34637 /* The specific error status for the command. */
34638 uint16_t error_code;
34639 /* The HWRM command request type. */
34641 /* The sequence ID from the original command. */
34643 /* The length of the response data in number of bytes. */
34645 uint8_t unused_0[7];
34647 * This field is used in Output records to indicate that the output
34648 * is completely written to RAM. This field should be read as '1'
34649 * to indicate that the output has been completely written.
34650 * When writing a command completion or response to an internal processor,
34651 * the order of writes has to be such that this field is written last.
34656 /***************************
34657 * hwrm_cfa_flow_aging_cfg *
34658 ***************************/
34661 /* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
34662 struct hwrm_cfa_flow_aging_cfg_input {
34663 /* The HWRM command request type. */
34666 * The completion ring to send the completion event on. This should
34667 * be the NQ ID returned from the `nq_alloc` HWRM command.
34669 uint16_t cmpl_ring;
34671 * The sequence ID is used by the driver for tracking multiple
34672 * commands. This ID is treated as opaque data by the firmware and
34673 * the value is returned in the `hwrm_resp_hdr` upon completion.
34677 * The target ID of the command:
34678 * * 0x0-0xFFF8 - The function ID
34679 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34680 * * 0xFFFD - Reserved for user-space HWRM interface
34683 uint16_t target_id;
34685 * A physical address pointer pointing to a host buffer that the
34686 * command's response data will be written. This can be either a host
34687 * physical address (HPA) or a guest physical address (GPA) and must
34688 * point to a physically contiguous block of memory.
34690 uint64_t resp_addr;
34691 /* The bit field to enable per flow aging configuration. */
34693 /* This bit must be '1' for the tcp flow timer field to be configured */
34694 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
34696 /* This bit must be '1' for the tcp finish timer field to be configured */
34697 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
34699 /* This bit must be '1' for the udp flow timer field to be configured */
34700 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
34702 /* This bit must be '1' for the eem dma interval field to be configured */
34703 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
34705 /* This bit must be '1' for the eem notice interval field to be configured */
34706 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
34708 /* This bit must be '1' for the eem context memory maximum entries field to be configured */
34709 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
34711 /* This bit must be '1' for the eem context memory ID field to be configured */
34712 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
34714 /* This bit must be '1' for the eem context memory type field to be configured */
34715 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
34718 /* Enumeration denoting the RX, TX type of the resource. */
34719 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
34721 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34723 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34724 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
34725 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
34726 /* Enumeration denoting the enable, disable eem flow aging configuration. */
34727 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
34729 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
34730 (UINT32_C(0x0) << 1)
34732 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
34733 (UINT32_C(0x1) << 1)
34734 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
34735 HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
34737 /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
34738 uint32_t tcp_flow_timer;
34739 /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
34740 uint32_t tcp_fin_timer;
34741 /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
34742 uint32_t udp_flow_timer;
34743 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
34744 uint16_t eem_dma_interval;
34745 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
34746 uint16_t eem_notice_interval;
34747 /* The maximum entries number in the eem context memory. */
34748 uint32_t eem_ctx_max_entries;
34749 /* The context memory ID for eem flow aging. */
34750 uint16_t eem_ctx_id;
34751 uint16_t eem_ctx_mem_type;
34752 /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
34753 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
34755 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
34756 HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
34757 uint8_t unused_1[4];
34760 /* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
34761 struct hwrm_cfa_flow_aging_cfg_output {
34762 /* The specific error status for the command. */
34763 uint16_t error_code;
34764 /* The HWRM command request type. */
34766 /* The sequence ID from the original command. */
34768 /* The length of the response data in number of bytes. */
34770 uint8_t unused_0[7];
34772 * This field is used in Output records to indicate that the output
34773 * is completely written to RAM. This field should be read as '1'
34774 * to indicate that the output has been completely written.
34775 * When writing a command completion or response to an internal processor,
34776 * the order of writes has to be such that this field is written last.
34781 /****************************
34782 * hwrm_cfa_flow_aging_qcfg *
34783 ****************************/
34786 /* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
34787 struct hwrm_cfa_flow_aging_qcfg_input {
34788 /* The HWRM command request type. */
34791 * The completion ring to send the completion event on. This should
34792 * be the NQ ID returned from the `nq_alloc` HWRM command.
34794 uint16_t cmpl_ring;
34796 * The sequence ID is used by the driver for tracking multiple
34797 * commands. This ID is treated as opaque data by the firmware and
34798 * the value is returned in the `hwrm_resp_hdr` upon completion.
34802 * The target ID of the command:
34803 * * 0x0-0xFFF8 - The function ID
34804 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34805 * * 0xFFFD - Reserved for user-space HWRM interface
34808 uint16_t target_id;
34810 * A physical address pointer pointing to a host buffer that the
34811 * command's response data will be written. This can be either a host
34812 * physical address (HPA) or a guest physical address (GPA) and must
34813 * point to a physically contiguous block of memory.
34815 uint64_t resp_addr;
34816 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
34818 /* Enumeration denoting the RX, TX type of the resource. */
34819 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
34821 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34823 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34824 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
34825 HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
34826 uint8_t unused_0[7];
34829 /* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
34830 struct hwrm_cfa_flow_aging_qcfg_output {
34831 /* The specific error status for the command. */
34832 uint16_t error_code;
34833 /* The HWRM command request type. */
34835 /* The sequence ID from the original command. */
34837 /* The length of the response data in number of bytes. */
34839 /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
34840 uint32_t tcp_flow_timer;
34841 /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
34842 uint32_t tcp_fin_timer;
34843 /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
34844 uint32_t udp_flow_timer;
34845 /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
34846 uint16_t eem_dma_interval;
34847 /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
34848 uint16_t eem_notice_interval;
34849 /* The maximum entries number in the eem context memory. */
34850 uint32_t eem_ctx_max_entries;
34851 /* The context memory ID for eem flow aging. */
34852 uint16_t eem_ctx_id;
34853 /* The context memory type for eem flow aging. */
34854 uint16_t eem_ctx_mem_type;
34855 uint8_t unused_0[7];
34857 * This field is used in Output records to indicate that the output
34858 * is completely written to RAM. This field should be read as '1'
34859 * to indicate that the output has been completely written.
34860 * When writing a command completion or response to an internal processor,
34861 * the order of writes has to be such that this field is written last.
34866 /*****************************
34867 * hwrm_cfa_flow_aging_qcaps *
34868 *****************************/
34871 /* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
34872 struct hwrm_cfa_flow_aging_qcaps_input {
34873 /* The HWRM command request type. */
34876 * The completion ring to send the completion event on. This should
34877 * be the NQ ID returned from the `nq_alloc` HWRM command.
34879 uint16_t cmpl_ring;
34881 * The sequence ID is used by the driver for tracking multiple
34882 * commands. This ID is treated as opaque data by the firmware and
34883 * the value is returned in the `hwrm_resp_hdr` upon completion.
34887 * The target ID of the command:
34888 * * 0x0-0xFFF8 - The function ID
34889 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34890 * * 0xFFFD - Reserved for user-space HWRM interface
34893 uint16_t target_id;
34895 * A physical address pointer pointing to a host buffer that the
34896 * command's response data will be written. This can be either a host
34897 * physical address (HPA) or a guest physical address (GPA) and must
34898 * point to a physically contiguous block of memory.
34900 uint64_t resp_addr;
34901 /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
34903 /* Enumeration denoting the RX, TX type of the resource. */
34904 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
34906 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34908 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34909 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
34910 HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
34911 uint8_t unused_0[7];
34914 /* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
34915 struct hwrm_cfa_flow_aging_qcaps_output {
34916 /* The specific error status for the command. */
34917 uint16_t error_code;
34918 /* The HWRM command request type. */
34920 /* The sequence ID from the original command. */
34922 /* The length of the response data in number of bytes. */
34924 /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
34925 uint32_t max_tcp_flow_timer;
34926 /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
34927 uint32_t max_tcp_fin_timer;
34928 /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
34929 uint32_t max_udp_flow_timer;
34930 /* The maximum aging flows that HW can support. */
34931 uint32_t max_aging_flows;
34932 uint8_t unused_0[7];
34934 * This field is used in Output records to indicate that the output
34935 * is completely written to RAM. This field should be read as '1'
34936 * to indicate that the output has been completely written.
34937 * When writing a command completion or response to an internal processor,
34938 * the order of writes has to be such that this field is written last.
34943 /**********************************
34944 * hwrm_cfa_tcp_flag_process_qcfg *
34945 **********************************/
34948 /* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
34949 struct hwrm_cfa_tcp_flag_process_qcfg_input {
34950 /* The HWRM command request type. */
34953 * The completion ring to send the completion event on. This should
34954 * be the NQ ID returned from the `nq_alloc` HWRM command.
34956 uint16_t cmpl_ring;
34958 * The sequence ID is used by the driver for tracking multiple
34959 * commands. This ID is treated as opaque data by the firmware and
34960 * the value is returned in the `hwrm_resp_hdr` upon completion.
34964 * The target ID of the command:
34965 * * 0x0-0xFFF8 - The function ID
34966 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34967 * * 0xFFFD - Reserved for user-space HWRM interface
34970 uint16_t target_id;
34972 * A physical address pointer pointing to a host buffer that the
34973 * command's response data will be written. This can be either a host
34974 * physical address (HPA) or a guest physical address (GPA) and must
34975 * point to a physically contiguous block of memory.
34977 uint64_t resp_addr;
34980 /* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
34981 struct hwrm_cfa_tcp_flag_process_qcfg_output {
34982 /* The specific error status for the command. */
34983 uint16_t error_code;
34984 /* The HWRM command request type. */
34986 /* The sequence ID from the original command. */
34988 /* The length of the response data in number of bytes. */
34990 /* The port 0 RX mirror action record ID. */
34991 uint16_t rx_ar_id_port0;
34992 /* The port 1 RX mirror action record ID. */
34993 uint16_t rx_ar_id_port1;
34994 /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
34995 uint16_t tx_ar_id_port0;
34996 /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
34997 uint16_t tx_ar_id_port1;
34998 uint8_t unused_0[7];
35000 * This field is used in Output records to indicate that the output
35001 * is completely written to RAM. This field should be read as '1'
35002 * to indicate that the output has been completely written.
35003 * When writing a command completion or response to an internal processor,
35004 * the order of writes has to be such that this field is written last.
35009 /**********************
35010 * hwrm_cfa_pair_info *
35011 **********************/
35014 /* hwrm_cfa_pair_info_input (size:448b/56B) */
35015 struct hwrm_cfa_pair_info_input {
35016 /* The HWRM command request type. */
35019 * The completion ring to send the completion event on. This should
35020 * be the NQ ID returned from the `nq_alloc` HWRM command.
35022 uint16_t cmpl_ring;
35024 * The sequence ID is used by the driver for tracking multiple
35025 * commands. This ID is treated as opaque data by the firmware and
35026 * the value is returned in the `hwrm_resp_hdr` upon completion.
35030 * The target ID of the command:
35031 * * 0x0-0xFFF8 - The function ID
35032 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35033 * * 0xFFFD - Reserved for user-space HWRM interface
35036 uint16_t target_id;
35038 * A physical address pointer pointing to a host buffer that the
35039 * command's response data will be written. This can be either a host
35040 * physical address (HPA) or a guest physical address (GPA) and must
35041 * point to a physically contiguous block of memory.
35043 uint64_t resp_addr;
35045 /* If this flag is set, lookup by name else lookup by index. */
35046 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
35047 /* If this flag is set, lookup by PF id and VF id. */
35048 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
35049 /* Pair table index. */
35050 uint16_t pair_index;
35051 /* Pair pf index. */
35053 /* Pair vf index. */
35055 /* Pair name (32 byte string). */
35056 char pair_name[32];
35059 /* hwrm_cfa_pair_info_output (size:576b/72B) */
35060 struct hwrm_cfa_pair_info_output {
35061 /* The specific error status for the command. */
35062 uint16_t error_code;
35063 /* The HWRM command request type. */
35065 /* The sequence ID from the original command. */
35067 /* The length of the response data in number of bytes. */
35069 /* Pair table index. */
35070 uint16_t next_pair_index;
35071 /* Pair member a's fid. */
35073 /* Logical host number. */
35074 uint8_t host_a_index;
35075 /* Logical PF number. */
35076 uint8_t pf_a_index;
35077 /* Pair member a's Linux logical VF number. */
35078 uint16_t vf_a_index;
35080 uint16_t rx_cfa_code_a;
35081 /* Tx CFA action. */
35082 uint16_t tx_cfa_action_a;
35083 /* Pair member b's fid. */
35085 /* Logical host number. */
35086 uint8_t host_b_index;
35087 /* Logical PF number. */
35088 uint8_t pf_b_index;
35089 /* Pair member a's Linux logical VF number. */
35090 uint16_t vf_b_index;
35092 uint16_t rx_cfa_code_b;
35093 /* Tx CFA action. */
35094 uint16_t tx_cfa_action_b;
35095 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
35097 /* Pair between VF on local host with PF or VF on specified host. */
35098 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
35099 /* Pair between REP on local host with PF or VF on specified host. */
35100 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
35101 /* Pair between REP on local host with REP on specified host. */
35102 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
35103 /* Pair for the proxy interface. */
35104 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
35105 /* Pair for the PF interface. */
35106 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
35107 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
35108 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
35110 uint8_t pair_state;
35111 /* Pair has been allocated */
35112 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
35113 /* Both pair members are active */
35114 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
35115 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
35116 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
35117 /* Pair name (32 byte string). */
35118 char pair_name[32];
35119 uint8_t unused_0[7];
35121 * This field is used in Output records to indicate that the output
35122 * is completely written to RAM. This field should be read as '1'
35123 * to indicate that the output has been completely written.
35124 * When writing a command completion or response to an internal processor,
35125 * the order of writes has to be such that this field is written last.
35130 /**********************
35131 * hwrm_cfa_vfr_alloc *
35132 **********************/
35135 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
35136 struct hwrm_cfa_vfr_alloc_input {
35137 /* The HWRM command request type. */
35140 * The completion ring to send the completion event on. This should
35141 * be the NQ ID returned from the `nq_alloc` HWRM command.
35143 uint16_t cmpl_ring;
35145 * The sequence ID is used by the driver for tracking multiple
35146 * commands. This ID is treated as opaque data by the firmware and
35147 * the value is returned in the `hwrm_resp_hdr` upon completion.
35151 * The target ID of the command:
35152 * * 0x0-0xFFF8 - The function ID
35153 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35154 * * 0xFFFD - Reserved for user-space HWRM interface
35157 uint16_t target_id;
35159 * A physical address pointer pointing to a host buffer that the
35160 * command's response data will be written. This can be either a host
35161 * physical address (HPA) or a guest physical address (GPA) and must
35162 * point to a physically contiguous block of memory.
35164 uint64_t resp_addr;
35165 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35168 * This field is reserved for the future use.
35169 * It shall be set to 0.
35172 uint8_t unused_0[4];
35173 /* VF Representor name (32 byte string). */
35177 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
35178 struct hwrm_cfa_vfr_alloc_output {
35179 /* The specific error status for the command. */
35180 uint16_t error_code;
35181 /* The HWRM command request type. */
35183 /* The sequence ID from the original command. */
35185 /* The length of the response data in number of bytes. */
35188 uint16_t rx_cfa_code;
35189 /* Tx CFA action. */
35190 uint16_t tx_cfa_action;
35191 uint8_t unused_0[3];
35193 * This field is used in Output records to indicate that the output
35194 * is completely written to RAM. This field should be read as '1'
35195 * to indicate that the output has been completely written.
35196 * When writing a command completion or response to an internal processor,
35197 * the order of writes has to be such that this field is written last.
35202 /*********************
35203 * hwrm_cfa_vfr_free *
35204 *********************/
35207 /* hwrm_cfa_vfr_free_input (size:448b/56B) */
35208 struct hwrm_cfa_vfr_free_input {
35209 /* The HWRM command request type. */
35212 * The completion ring to send the completion event on. This should
35213 * be the NQ ID returned from the `nq_alloc` HWRM command.
35215 uint16_t cmpl_ring;
35217 * The sequence ID is used by the driver for tracking multiple
35218 * commands. This ID is treated as opaque data by the firmware and
35219 * the value is returned in the `hwrm_resp_hdr` upon completion.
35223 * The target ID of the command:
35224 * * 0x0-0xFFF8 - The function ID
35225 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35226 * * 0xFFFD - Reserved for user-space HWRM interface
35229 uint16_t target_id;
35231 * A physical address pointer pointing to a host buffer that the
35232 * command's response data will be written. This can be either a host
35233 * physical address (HPA) or a guest physical address (GPA) and must
35234 * point to a physically contiguous block of memory.
35236 uint64_t resp_addr;
35237 /* VF Representor name (32 byte string). */
35239 /* Logical VF number (range: 0 -> MAX_VFS -1). */
35242 uint8_t unused_0[4];
35245 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
35246 struct hwrm_cfa_vfr_free_output {
35247 /* The specific error status for the command. */
35248 uint16_t error_code;
35249 /* The HWRM command request type. */
35251 /* The sequence ID from the original command. */
35253 /* The length of the response data in number of bytes. */
35255 uint8_t unused_0[7];
35257 * This field is used in Output records to indicate that the output
35258 * is completely written to RAM. This field should be read as '1'
35259 * to indicate that the output has been completely written.
35260 * When writing a command completion or response to an internal processor,
35261 * the order of writes has to be such that this field is written last.
35268 /***************************************
35269 * hwrm_cfa_redirect_query_tunnel_type *
35270 ***************************************/
35273 /* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
35274 struct hwrm_cfa_redirect_query_tunnel_type_input {
35275 /* The HWRM command request type. */
35278 * The completion ring to send the completion event on. This should
35279 * be the NQ ID returned from the `nq_alloc` HWRM command.
35281 uint16_t cmpl_ring;
35283 * The sequence ID is used by the driver for tracking multiple
35284 * commands. This ID is treated as opaque data by the firmware and
35285 * the value is returned in the `hwrm_resp_hdr` upon completion.
35289 * The target ID of the command:
35290 * * 0x0-0xFFF8 - The function ID
35291 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35292 * * 0xFFFD - Reserved for user-space HWRM interface
35295 uint16_t target_id;
35297 * A physical address pointer pointing to a host buffer that the
35298 * command's response data will be written. This can be either a host
35299 * physical address (HPA) or a guest physical address (GPA) and must
35300 * point to a physically contiguous block of memory.
35302 uint64_t resp_addr;
35303 /* The source function id. */
35305 uint8_t unused_0[6];
35308 /* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
35309 struct hwrm_cfa_redirect_query_tunnel_type_output {
35310 /* The specific error status for the command. */
35311 uint16_t error_code;
35312 /* The HWRM command request type. */
35314 /* The sequence ID from the original command. */
35316 /* The length of the response data in number of bytes. */
35319 uint32_t tunnel_mask;
35321 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
35323 /* Virtual eXtensible Local Area Network (VXLAN) */
35324 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
35326 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
35327 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
35329 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
35330 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
35333 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
35335 /* Generic Network Virtualization Encapsulation (Geneve) */
35336 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
35338 /* Multi-Protocol Label Switching (MPLS) */
35339 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
35341 /* Stateless Transport Tunnel (STT) */
35342 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
35344 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
35345 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
35347 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
35348 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
35350 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
35351 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
35353 /* Any tunneled traffic */
35354 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
35356 /* Use fixed layer 2 ether type of 0xFFFF */
35357 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
35359 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
35360 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
35362 uint8_t unused_0[3];
35364 * This field is used in Output records to indicate that the output
35365 * is completely written to RAM. This field should be read as '1'
35366 * to indicate that the output has been completely written.
35367 * When writing a command completion or response to an internal processor,
35368 * the order of writes has to be such that this field is written last.
35373 /*************************
35374 * hwrm_cfa_ctx_mem_rgtr *
35375 *************************/
35378 /* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
35379 struct hwrm_cfa_ctx_mem_rgtr_input {
35380 /* The HWRM command request type. */
35383 * The completion ring to send the completion event on. This should
35384 * be the NQ ID returned from the `nq_alloc` HWRM command.
35386 uint16_t cmpl_ring;
35388 * The sequence ID is used by the driver for tracking multiple
35389 * commands. This ID is treated as opaque data by the firmware and
35390 * the value is returned in the `hwrm_resp_hdr` upon completion.
35394 * The target ID of the command:
35395 * * 0x0-0xFFF8 - The function ID
35396 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35397 * * 0xFFFD - Reserved for user-space HWRM interface
35400 uint16_t target_id;
35402 * A physical address pointer pointing to a host buffer that the
35403 * command's response data will be written. This can be either a host
35404 * physical address (HPA) or a guest physical address (GPA) and must
35405 * point to a physically contiguous block of memory.
35407 uint64_t resp_addr;
35409 /* Counter PBL indirect levels. */
35410 uint8_t page_level;
35411 /* PBL pointer is physical start address. */
35412 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35413 /* PBL pointer points to PTE table. */
35414 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35415 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35416 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35417 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
35418 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
35421 /* 4KB page size. */
35422 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
35423 /* 8KB page size. */
35424 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
35425 /* 64KB page size. */
35426 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
35427 /* 256KB page size. */
35428 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
35429 /* 1MB page size. */
35430 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
35431 /* 2MB page size. */
35432 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
35433 /* 4MB page size. */
35434 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
35435 /* 1GB page size. */
35436 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
35437 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
35438 HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
35440 /* Pointer to the PBL, or PDL depending on number of levels */
35444 /* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
35445 struct hwrm_cfa_ctx_mem_rgtr_output {
35446 /* The specific error status for the command. */
35447 uint16_t error_code;
35448 /* The HWRM command request type. */
35450 /* The sequence ID from the original command. */
35452 /* The length of the response data in number of bytes. */
35455 * Id/Handle to the recently register context memory. This handle is passed
35456 * to the CFA feature.
35459 uint8_t unused_0[5];
35461 * This field is used in Output records to indicate that the output
35462 * is completely written to RAM. This field should be read as '1'
35463 * to indicate that the output has been completely written.
35464 * When writing a command completion or response to an internal processor,
35465 * the order of writes has to be such that this field is written last.
35470 /***************************
35471 * hwrm_cfa_ctx_mem_unrgtr *
35472 ***************************/
35475 /* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
35476 struct hwrm_cfa_ctx_mem_unrgtr_input {
35477 /* The HWRM command request type. */
35480 * The completion ring to send the completion event on. This should
35481 * be the NQ ID returned from the `nq_alloc` HWRM command.
35483 uint16_t cmpl_ring;
35485 * The sequence ID is used by the driver for tracking multiple
35486 * commands. This ID is treated as opaque data by the firmware and
35487 * the value is returned in the `hwrm_resp_hdr` upon completion.
35491 * The target ID of the command:
35492 * * 0x0-0xFFF8 - The function ID
35493 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35494 * * 0xFFFD - Reserved for user-space HWRM interface
35497 uint16_t target_id;
35499 * A physical address pointer pointing to a host buffer that the
35500 * command's response data will be written. This can be either a host
35501 * physical address (HPA) or a guest physical address (GPA) and must
35502 * point to a physically contiguous block of memory.
35504 uint64_t resp_addr;
35506 * Id/Handle to the recently register context memory. This handle is passed
35507 * to the CFA feature.
35510 uint8_t unused_0[6];
35513 /* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
35514 struct hwrm_cfa_ctx_mem_unrgtr_output {
35515 /* The specific error status for the command. */
35516 uint16_t error_code;
35517 /* The HWRM command request type. */
35519 /* The sequence ID from the original command. */
35521 /* The length of the response data in number of bytes. */
35523 uint8_t unused_0[7];
35525 * This field is used in Output records to indicate that the output
35526 * is completely written to RAM. This field should be read as '1'
35527 * to indicate that the output has been completely written.
35528 * When writing a command completion or response to an internal processor,
35529 * the order of writes has to be such that this field is written last.
35534 /*************************
35535 * hwrm_cfa_ctx_mem_qctx *
35536 *************************/
35539 /* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
35540 struct hwrm_cfa_ctx_mem_qctx_input {
35541 /* The HWRM command request type. */
35544 * The completion ring to send the completion event on. This should
35545 * be the NQ ID returned from the `nq_alloc` HWRM command.
35547 uint16_t cmpl_ring;
35549 * The sequence ID is used by the driver for tracking multiple
35550 * commands. This ID is treated as opaque data by the firmware and
35551 * the value is returned in the `hwrm_resp_hdr` upon completion.
35555 * The target ID of the command:
35556 * * 0x0-0xFFF8 - The function ID
35557 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35558 * * 0xFFFD - Reserved for user-space HWRM interface
35561 uint16_t target_id;
35563 * A physical address pointer pointing to a host buffer that the
35564 * command's response data will be written. This can be either a host
35565 * physical address (HPA) or a guest physical address (GPA) and must
35566 * point to a physically contiguous block of memory.
35568 uint64_t resp_addr;
35570 * Id/Handle to the recently register context memory. This handle is passed
35571 * to the CFA feature.
35574 uint8_t unused_0[6];
35577 /* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
35578 struct hwrm_cfa_ctx_mem_qctx_output {
35579 /* The specific error status for the command. */
35580 uint16_t error_code;
35581 /* The HWRM command request type. */
35583 /* The sequence ID from the original command. */
35585 /* The length of the response data in number of bytes. */
35588 /* Counter PBL indirect levels. */
35589 uint8_t page_level;
35590 /* PBL pointer is physical start address. */
35591 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
35592 /* PBL pointer points to PTE table. */
35593 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
35594 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
35595 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
35596 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
35597 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
35600 /* 4KB page size. */
35601 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
35602 /* 8KB page size. */
35603 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
35604 /* 64KB page size. */
35605 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
35606 /* 256KB page size. */
35607 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
35608 /* 1MB page size. */
35609 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
35610 /* 2MB page size. */
35611 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
35612 /* 4MB page size. */
35613 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
35614 /* 1GB page size. */
35615 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
35616 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
35617 HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
35618 uint8_t unused_0[4];
35619 /* Pointer to the PBL, or PDL depending on number of levels */
35621 uint8_t unused_1[7];
35623 * This field is used in Output records to indicate that the output
35624 * is completely written to RAM. This field should be read as '1'
35625 * to indicate that the output has been completely written.
35626 * When writing a command completion or response to an internal processor,
35627 * the order of writes has to be such that this field is written last.
35632 /**************************
35633 * hwrm_cfa_ctx_mem_qcaps *
35634 **************************/
35637 /* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
35638 struct hwrm_cfa_ctx_mem_qcaps_input {
35639 /* The HWRM command request type. */
35642 * The completion ring to send the completion event on. This should
35643 * be the NQ ID returned from the `nq_alloc` HWRM command.
35645 uint16_t cmpl_ring;
35647 * The sequence ID is used by the driver for tracking multiple
35648 * commands. This ID is treated as opaque data by the firmware and
35649 * the value is returned in the `hwrm_resp_hdr` upon completion.
35653 * The target ID of the command:
35654 * * 0x0-0xFFF8 - The function ID
35655 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35656 * * 0xFFFD - Reserved for user-space HWRM interface
35659 uint16_t target_id;
35661 * A physical address pointer pointing to a host buffer that the
35662 * command's response data will be written. This can be either a host
35663 * physical address (HPA) or a guest physical address (GPA) and must
35664 * point to a physically contiguous block of memory.
35666 uint64_t resp_addr;
35669 /* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
35670 struct hwrm_cfa_ctx_mem_qcaps_output {
35671 /* The specific error status for the command. */
35672 uint16_t error_code;
35673 /* The HWRM command request type. */
35675 /* The sequence ID from the original command. */
35677 /* The length of the response data in number of bytes. */
35679 /* Indicates the maximum number of context memory which can be registered. */
35680 uint16_t max_entries;
35681 uint8_t unused_0[5];
35683 * This field is used in Output records to indicate that the output
35684 * is completely written to RAM. This field should be read as '1'
35685 * to indicate that the output has been completely written.
35686 * When writing a command completion or response to an internal processor,
35687 * the order of writes has to be such that this field is written last.
35692 /**********************
35693 * hwrm_cfa_eem_qcaps *
35694 **********************/
35697 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
35698 struct hwrm_cfa_eem_qcaps_input {
35699 /* The HWRM command request type. */
35702 * The completion ring to send the completion event on. This should
35703 * be the NQ ID returned from the `nq_alloc` HWRM command.
35705 uint16_t cmpl_ring;
35707 * The sequence ID is used by the driver for tracking multiple
35708 * commands. This ID is treated as opaque data by the firmware and
35709 * the value is returned in the `hwrm_resp_hdr` upon completion.
35713 * The target ID of the command:
35714 * * 0x0-0xFFF8 - The function ID
35715 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35716 * * 0xFFFD - Reserved for user-space HWRM interface
35719 uint16_t target_id;
35721 * A physical address pointer pointing to a host buffer that the
35722 * command's response data will be written. This can be either a host
35723 * physical address (HPA) or a guest physical address (GPA) and must
35724 * point to a physically contiguous block of memory.
35726 uint64_t resp_addr;
35729 * When set to 1, indicates the configuration will apply to TX flows
35730 * which are to be offloaded.
35731 * Note if this bit is set then the path_rx bit can't be set.
35733 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
35736 * When set to 1, indicates the configuration will apply to RX flows
35737 * which are to be offloaded.
35738 * Note if this bit is set then the path_tx bit can't be set.
35740 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
35742 /* When set to 1, all offloaded flows will be sent to EEM. */
35743 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
35748 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */
35749 struct hwrm_cfa_eem_qcaps_output {
35750 /* The specific error status for the command. */
35751 uint16_t error_code;
35752 /* The HWRM command request type. */
35754 /* The sequence ID from the original command. */
35756 /* The length of the response data in number of bytes. */
35760 * When set to 1, indicates the configuration will apply to TX flows
35761 * which are to be offloaded.
35762 * Note if this bit is set then the path_rx bit can't be set.
35764 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
35767 * When set to 1, indicates the configuration will apply to RX flows
35768 * which are to be offloaded.
35769 * Note if this bit is set then the path_tx bit can't be set.
35771 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
35774 * When set to 1, indicates the the FW supports the Centralized
35775 * Memory Model. The concept designates one entity for the
35776 * memory allocation while all others ‘subscribe’ to it.
35778 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
35781 * When set to 1, indicates the the FW supports the Detached
35782 * Centralized Memory Model. The memory is allocated and managed
35783 * as a separate entity. All PFs and VFs will be granted direct
35784 * or semi-direct access to the allocated memory while none of
35785 * which can interfere with the management of the memory.
35787 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
35790 uint32_t supported;
35792 * If set to 1, then EEM KEY0 table is supported using crc32 hash.
35793 * If set to 0, EEM KEY0 table is not supported.
35795 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
35798 * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
35799 * If set to 0, EEM KEY1 table is not supported.
35801 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
35804 * If set to 1, then EEM External Record table is supported.
35805 * If set to 0, EEM External Record table is not supported.
35806 * (This table includes action record, EFC pointers, encap pointers)
35808 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
35811 * If set to 1, then EEM External Flow Counters table is supported.
35812 * If set to 0, EEM External Flow Counters table is not supported.
35814 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
35817 * If set to 1, then FID table used for implicit flow flush is supported.
35818 * If set to 0, then FID table used for implicit flow flush is not supported.
35820 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
35823 * The maximum number of entries supported by EEM. When configuring the host memory
35824 * the number of numbers of entries that can supported are -
35825 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
35826 * Any value that are not these values, the FW will round down to the closest support
35827 * number of entries.
35829 uint32_t max_entries_supported;
35830 /* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */
35831 uint16_t key_entry_size;
35832 /* The entry size in bytes of each entry in the EEM RECORD tables. */
35833 uint16_t record_entry_size;
35834 /* The entry size in bytes of each entry in the EEM EFC tables. */
35835 uint16_t efc_entry_size;
35836 /* The FID size in bytes of each entry in the EEM FID tables. */
35837 uint16_t fid_entry_size;
35838 uint8_t unused_1[7];
35840 * This field is used in Output records to indicate that the output
35841 * is completely written to RAM. This field should be read as '1'
35842 * to indicate that the output has been completely written.
35843 * When writing a command completion or response to an internal processor,
35844 * the order of writes has to be such that this field is written last.
35849 /********************
35850 * hwrm_cfa_eem_cfg *
35851 ********************/
35854 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */
35855 struct hwrm_cfa_eem_cfg_input {
35856 /* The HWRM command request type. */
35859 * The completion ring to send the completion event on. This should
35860 * be the NQ ID returned from the `nq_alloc` HWRM command.
35862 uint16_t cmpl_ring;
35864 * The sequence ID is used by the driver for tracking multiple
35865 * commands. This ID is treated as opaque data by the firmware and
35866 * the value is returned in the `hwrm_resp_hdr` upon completion.
35870 * The target ID of the command:
35871 * * 0x0-0xFFF8 - The function ID
35872 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35873 * * 0xFFFD - Reserved for user-space HWRM interface
35876 uint16_t target_id;
35878 * A physical address pointer pointing to a host buffer that the
35879 * command's response data will be written. This can be either a host
35880 * physical address (HPA) or a guest physical address (GPA) and must
35881 * point to a physically contiguous block of memory.
35883 uint64_t resp_addr;
35886 * When set to 1, indicates the configuration will apply to TX flows
35887 * which are to be offloaded.
35888 * Note if this bit is set then the path_rx bit can't be set.
35890 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
35893 * When set to 1, indicates the configuration will apply to RX flows
35894 * which are to be offloaded.
35895 * Note if this bit is set then the path_tx bit can't be set.
35897 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
35899 /* When set to 1, all offloaded flows will be sent to EEM. */
35900 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
35902 /* When set to 1, secondary, 0 means primary. */
35903 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
35906 * Group_id which used by Firmware to identify memory pools belonging
35907 * to certain group.
35912 * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
35913 * RECORD, EFC all have the same number of entries and all tables will be configured
35914 * using this value. Current minimum value is 32k. Current maximum value is 128M.
35916 uint32_t num_entries;
35918 /* Configured EEM with the given context if for KEY0 table. */
35919 uint16_t key0_ctx_id;
35920 /* Configured EEM with the given context if for KEY1 table. */
35921 uint16_t key1_ctx_id;
35922 /* Configured EEM with the given context if for RECORD table. */
35923 uint16_t record_ctx_id;
35924 /* Configured EEM with the given context if for EFC table. */
35925 uint16_t efc_ctx_id;
35926 /* Configured EEM with the given context if for EFC table. */
35927 uint16_t fid_ctx_id;
35932 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */
35933 struct hwrm_cfa_eem_cfg_output {
35934 /* The specific error status for the command. */
35935 uint16_t error_code;
35936 /* The HWRM command request type. */
35938 /* The sequence ID from the original command. */
35940 /* The length of the response data in number of bytes. */
35942 uint8_t unused_0[7];
35944 * This field is used in Output records to indicate that the output
35945 * is completely written to RAM. This field should be read as '1'
35946 * to indicate that the output has been completely written.
35947 * When writing a command completion or response to an internal processor,
35948 * the order of writes has to be such that this field is written last.
35953 /*********************
35954 * hwrm_cfa_eem_qcfg *
35955 *********************/
35958 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
35959 struct hwrm_cfa_eem_qcfg_input {
35960 /* The HWRM command request type. */
35963 * The completion ring to send the completion event on. This should
35964 * be the NQ ID returned from the `nq_alloc` HWRM command.
35966 uint16_t cmpl_ring;
35968 * The sequence ID is used by the driver for tracking multiple
35969 * commands. This ID is treated as opaque data by the firmware and
35970 * the value is returned in the `hwrm_resp_hdr` upon completion.
35974 * The target ID of the command:
35975 * * 0x0-0xFFF8 - The function ID
35976 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35977 * * 0xFFFD - Reserved for user-space HWRM interface
35980 uint16_t target_id;
35982 * A physical address pointer pointing to a host buffer that the
35983 * command's response data will be written. This can be either a host
35984 * physical address (HPA) or a guest physical address (GPA) and must
35985 * point to a physically contiguous block of memory.
35987 uint64_t resp_addr;
35989 /* When set to 1, indicates the configuration is the TX flow. */
35990 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
35991 /* When set to 1, indicates the configuration is the RX flow. */
35992 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
35996 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */
35997 struct hwrm_cfa_eem_qcfg_output {
35998 /* The specific error status for the command. */
35999 uint16_t error_code;
36000 /* The HWRM command request type. */
36002 /* The sequence ID from the original command. */
36004 /* The length of the response data in number of bytes. */
36007 /* When set to 1, indicates the configuration is the TX flow. */
36008 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
36010 /* When set to 1, indicates the configuration is the RX flow. */
36011 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
36013 /* When set to 1, all offloaded flows will be sent to EEM. */
36014 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
36016 /* The number of entries the FW has configured for EEM. */
36017 uint32_t num_entries;
36018 /* Configured EEM with the given context if for KEY0 table. */
36019 uint16_t key0_ctx_id;
36020 /* Configured EEM with the given context if for KEY1 table. */
36021 uint16_t key1_ctx_id;
36022 /* Configured EEM with the given context if for RECORD table. */
36023 uint16_t record_ctx_id;
36024 /* Configured EEM with the given context if for EFC table. */
36025 uint16_t efc_ctx_id;
36026 /* Configured EEM with the given context if for EFC table. */
36027 uint16_t fid_ctx_id;
36028 uint8_t unused_2[5];
36030 * This field is used in Output records to indicate that the output
36031 * is completely written to RAM. This field should be read as '1'
36032 * to indicate that the output has been completely written.
36033 * When writing a command completion or response to an internal processor,
36034 * the order of writes has to be such that this field is written last.
36039 /*******************
36040 * hwrm_cfa_eem_op *
36041 *******************/
36044 /* hwrm_cfa_eem_op_input (size:192b/24B) */
36045 struct hwrm_cfa_eem_op_input {
36046 /* The HWRM command request type. */
36049 * The completion ring to send the completion event on. This should
36050 * be the NQ ID returned from the `nq_alloc` HWRM command.
36052 uint16_t cmpl_ring;
36054 * The sequence ID is used by the driver for tracking multiple
36055 * commands. This ID is treated as opaque data by the firmware and
36056 * the value is returned in the `hwrm_resp_hdr` upon completion.
36060 * The target ID of the command:
36061 * * 0x0-0xFFF8 - The function ID
36062 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36063 * * 0xFFFD - Reserved for user-space HWRM interface
36066 uint16_t target_id;
36068 * A physical address pointer pointing to a host buffer that the
36069 * command's response data will be written. This can be either a host
36070 * physical address (HPA) or a guest physical address (GPA) and must
36071 * point to a physically contiguous block of memory.
36073 uint64_t resp_addr;
36076 * When set to 1, indicates the host memory which is passed will be
36077 * used for the TX flow offload function specified in fid.
36078 * Note if this bit is set then the path_rx bit can't be set.
36080 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
36082 * When set to 1, indicates the host memory which is passed will be
36083 * used for the RX flow offload function specified in fid.
36084 * Note if this bit is set then the path_tx bit can't be set.
36086 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
36088 /* The number of EEM key table entries to be configured. */
36090 /* This value is reserved and should not be used. */
36091 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
36093 * To properly stop EEM and ensure there are no DMA's, the caller
36094 * must disable EEM for the given PF, using this call. This will
36095 * safely disable EEM and ensure that all DMA'ed to the
36096 * keys/records/efc have been completed.
36098 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
36100 * Once the EEM host memory has been configured, EEM options have
36101 * been configured. Then the caller should enable EEM for the given
36102 * PF. Note once this call has been made, then the EEM mechanism
36103 * will be active and DMA's will occur as packets are processed.
36105 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
36107 * Clear EEM settings for the given PF so that the register values
36108 * are reset back to there initial state.
36110 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
36111 #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
36112 HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
36115 /* hwrm_cfa_eem_op_output (size:128b/16B) */
36116 struct hwrm_cfa_eem_op_output {
36117 /* The specific error status for the command. */
36118 uint16_t error_code;
36119 /* The HWRM command request type. */
36121 /* The sequence ID from the original command. */
36123 /* The length of the response data in number of bytes. */
36125 uint8_t unused_0[7];
36127 * This field is used in Output records to indicate that the output
36128 * is completely written to RAM. This field should be read as '1'
36129 * to indicate that the output has been completely written.
36130 * When writing a command completion or response to an internal processor,
36131 * the order of writes has to be such that this field is written last.
36136 /********************************
36137 * hwrm_cfa_adv_flow_mgnt_qcaps *
36138 ********************************/
36141 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
36142 struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
36143 /* The HWRM command request type. */
36146 * The completion ring to send the completion event on. This should
36147 * be the NQ ID returned from the `nq_alloc` HWRM command.
36149 uint16_t cmpl_ring;
36151 * The sequence ID is used by the driver for tracking multiple
36152 * commands. This ID is treated as opaque data by the firmware and
36153 * the value is returned in the `hwrm_resp_hdr` upon completion.
36157 * The target ID of the command:
36158 * * 0x0-0xFFF8 - The function ID
36159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36160 * * 0xFFFD - Reserved for user-space HWRM interface
36163 uint16_t target_id;
36165 * A physical address pointer pointing to a host buffer that the
36166 * command's response data will be written. This can be either a host
36167 * physical address (HPA) or a guest physical address (GPA) and must
36168 * point to a physically contiguous block of memory.
36170 uint64_t resp_addr;
36171 uint32_t unused_0[4];
36174 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
36175 struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
36176 /* The specific error status for the command. */
36177 uint16_t error_code;
36178 /* The HWRM command request type. */
36180 /* The sequence ID from the original command. */
36182 /* The length of the response data in number of bytes. */
36186 * Value of 1 to indicate firmware support 16-bit flow handle.
36187 * Value of 0 to indicate firmware not support 16-bit flow handle.
36189 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
36192 * Value of 1 to indicate firmware support 64-bit flow handle.
36193 * Value of 0 to indicate firmware not support 64-bit flow handle.
36195 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
36198 * Value of 1 to indicate firmware support flow batch delete operation through
36199 * HWRM_CFA_FLOW_FLUSH command.
36200 * Value of 0 to indicate that the firmware does not support flow batch delete
36203 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
36206 * Value of 1 to indicate that the firmware support flow reset all operation through
36207 * HWRM_CFA_FLOW_FLUSH command.
36208 * Value of 0 indicates firmware does not support flow reset all operation.
36210 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
36213 * Value of 1 to indicate that firmware supports use of FID as dest_id in
36214 * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
36215 * Value of 0 indicates firmware does not support use of FID as dest_id.
36217 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
36220 * Value of 1 to indicate that firmware supports TX EEM flows.
36221 * Value of 0 indicates firmware does not support TX EEM flows.
36223 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
36226 * Value of 1 to indicate that firmware supports RX EEM flows.
36227 * Value of 0 indicates firmware does not support RX EEM flows.
36229 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
36232 * Value of 1 to indicate that firmware supports the dynamic allocation of an
36233 * on-chip flow counter which can be used for EEM flows.
36234 * Value of 0 indicates firmware does not support the dynamic allocation of an
36235 * on-chip flow counter.
36237 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
36240 * Value of 1 to indicate that firmware supports setting of
36241 * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
36242 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
36244 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
36247 * Value of 1 to indicate that firmware supports untagged matching
36248 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
36249 * indicates firmware does not support untagged matching.
36251 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
36254 * Value of 1 to indicate that firmware supports XDP filter. Value
36255 * of 0 indicates firmware does not support XDP filter.
36257 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
36260 * Value of 1 to indicate that the firmware support L2 header source
36261 * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
36262 * Value of 0 indicates firmware does not support L2 header source
36265 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
36268 * If set to 1, firmware is capable of supporting ARP ethertype as
36269 * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the
36270 * RX direction. By default, this flag should be 0 for older version
36273 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \
36276 * Value of 1 to indicate that firmware supports setting of
36277 * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC
36278 * command. Value of 0 indicates firmware does not support
36279 * rfs_ring_tbl_idx in dst_id field.
36281 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \
36284 * If set to 1, firmware is capable of supporting IPv4/IPv6 as
36285 * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX
36286 * direction. By default, this flag should be 0 for older version
36289 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \
36291 uint8_t unused_0[3];
36293 * This field is used in Output records to indicate that the output
36294 * is completely written to RAM. This field should be read as '1'
36295 * to indicate that the output has been completely written.
36296 * When writing a command completion or response to an internal processor,
36297 * the order of writes has to be such that this field is written last.
36302 /******************
36304 ******************/
36307 /* hwrm_cfa_tflib_input (size:1024b/128B) */
36308 struct hwrm_cfa_tflib_input {
36309 /* The HWRM command request type. */
36312 * The completion ring to send the completion event on. This should
36313 * be the NQ ID returned from the `nq_alloc` HWRM command.
36315 uint16_t cmpl_ring;
36317 * The sequence ID is used by the driver for tracking multiple
36318 * commands. This ID is treated as opaque data by the firmware and
36319 * the value is returned in the `hwrm_resp_hdr` upon completion.
36323 * The target ID of the command:
36324 * * 0x0-0xFFF8 - The function ID
36325 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36326 * * 0xFFFD - Reserved for user-space HWRM interface
36329 uint16_t target_id;
36331 * A physical address pointer pointing to a host buffer that the
36332 * command's response data will be written. This can be either a host
36333 * physical address (HPA) or a guest physical address (GPA) and must
36334 * point to a physically contiguous block of memory.
36336 uint64_t resp_addr;
36337 /* TFLIB message type. */
36339 /* TFLIB message subtype. */
36340 uint16_t tf_subtype;
36342 uint8_t unused0[4];
36343 /* TFLIB request data. */
36344 uint32_t tf_req[26];
36347 /* hwrm_cfa_tflib_output (size:5632b/704B) */
36348 struct hwrm_cfa_tflib_output {
36349 /* The specific error status for the command. */
36350 uint16_t error_code;
36351 /* The HWRM command request type. */
36353 /* The sequence ID from the original command. */
36355 /* The length of the response data in number of bytes. */
36357 /* TFLIB message type. */
36359 /* TFLIB message subtype. */
36360 uint16_t tf_subtype;
36361 /* TFLIB response code */
36362 uint32_t tf_resp_code;
36363 /* TFLIB response data. */
36364 uint32_t tf_resp[170];
36366 uint8_t unused1[7];
36368 * This field is used in Output records to indicate that the output
36369 * is completely written to RAM. This field should be read as '1'
36370 * to indicate that the output has been completely written.
36371 * When writing a command completion or response to an internal processor,
36372 * the order of writes has to be such that this field is written last.
36382 /* hwrm_tf_input (size:1024b/128B) */
36383 struct hwrm_tf_input {
36384 /* The HWRM command request type. */
36387 * The completion ring to send the completion event on. This should
36388 * be the NQ ID returned from the `nq_alloc` HWRM command.
36390 uint16_t cmpl_ring;
36392 * The sequence ID is used by the driver for tracking multiple
36393 * commands. This ID is treated as opaque data by the firmware and
36394 * the value is returned in the `hwrm_resp_hdr` upon completion.
36398 * The target ID of the command:
36399 * * 0x0-0xFFF8 - The function ID
36400 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36401 * * 0xFFFD - Reserved for user-space HWRM interface
36404 uint16_t target_id;
36406 * A physical address pointer pointing to a host buffer that the
36407 * command's response data will be written. This can be either a host
36408 * physical address (HPA) or a guest physical address (GPA) and must
36409 * point to a physically contiguous block of memory.
36411 uint64_t resp_addr;
36412 /* TF message type. */
36414 /* TF message subtype. */
36417 uint8_t unused0[4];
36418 /* TF request data. */
36422 /* hwrm_tf_output (size:5632b/704B) */
36423 struct hwrm_tf_output {
36424 /* The specific error status for the command. */
36425 uint16_t error_code;
36426 /* The HWRM command request type. */
36428 /* The sequence ID from the original command. */
36430 /* The length of the response data in number of bytes. */
36432 /* TF message type. */
36434 /* TF message subtype. */
36436 /* TF response code */
36437 uint32_t resp_code;
36438 /* TF response data. */
36439 uint32_t resp[170];
36441 uint8_t unused1[7];
36443 * This field is used in Output records to indicate that the
36444 * output is completely written to RAM. This field should be
36445 * read as '1' to indicate that the output has been
36446 * completely written. When writing a command completion or
36447 * response to an internal processor, the order of writes has
36448 * to be such that this field is written last.
36453 /***********************
36454 * hwrm_tf_version_get *
36455 ***********************/
36458 /* hwrm_tf_version_get_input (size:128b/16B) */
36459 struct hwrm_tf_version_get_input {
36460 /* The HWRM command request type. */
36463 * The completion ring to send the completion event on. This should
36464 * be the NQ ID returned from the `nq_alloc` HWRM command.
36466 uint16_t cmpl_ring;
36468 * The sequence ID is used by the driver for tracking multiple
36469 * commands. This ID is treated as opaque data by the firmware and
36470 * the value is returned in the `hwrm_resp_hdr` upon completion.
36474 * The target ID of the command:
36475 * * 0x0-0xFFF8 - The function ID
36476 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36477 * * 0xFFFD - Reserved for user-space HWRM interface
36480 uint16_t target_id;
36482 * A physical address pointer pointing to a host buffer that the
36483 * command's response data will be written. This can be either a host
36484 * physical address (HPA) or a guest physical address (GPA) and must
36485 * point to a physically contiguous block of memory.
36487 uint64_t resp_addr;
36490 /* hwrm_tf_version_get_output (size:128b/16B) */
36491 struct hwrm_tf_version_get_output {
36492 /* The specific error status for the command. */
36493 uint16_t error_code;
36494 /* The HWRM command request type. */
36496 /* The sequence ID from the original command. */
36498 /* The length of the response data in number of bytes. */
36500 /* Version Major number. */
36502 /* Version Minor number. */
36504 /* Version Update number. */
36507 uint8_t unused0[4];
36509 * This field is used in Output records to indicate that the output
36510 * is completely written to RAM. This field should be read as '1'
36511 * to indicate that the output has been completely written.
36512 * When writing a command completion or response to an internal
36513 * processor, the order of writes has to be such that this field is
36519 /************************
36520 * hwrm_tf_session_open *
36521 ************************/
36524 /* hwrm_tf_session_open_input (size:640b/80B) */
36525 struct hwrm_tf_session_open_input {
36526 /* The HWRM command request type. */
36529 * The completion ring to send the completion event on. This should
36530 * be the NQ ID returned from the `nq_alloc` HWRM command.
36532 uint16_t cmpl_ring;
36534 * The sequence ID is used by the driver for tracking multiple
36535 * commands. This ID is treated as opaque data by the firmware and
36536 * the value is returned in the `hwrm_resp_hdr` upon completion.
36540 * The target ID of the command:
36541 * * 0x0-0xFFF8 - The function ID
36542 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36543 * * 0xFFFD - Reserved for user-space HWRM interface
36546 uint16_t target_id;
36548 * A physical address pointer pointing to a host buffer that the
36549 * command's response data will be written. This can be either a host
36550 * physical address (HPA) or a guest physical address (GPA) and must
36551 * point to a physically contiguous block of memory.
36553 uint64_t resp_addr;
36554 /* Name of the session. */
36555 uint8_t session_name[64];
36558 /* hwrm_tf_session_open_output (size:192b/24B) */
36559 struct hwrm_tf_session_open_output {
36560 /* The specific error status for the command. */
36561 uint16_t error_code;
36562 /* The HWRM command request type. */
36564 /* The sequence ID from the original command. */
36566 /* The length of the response data in number of bytes. */
36569 * Unique session identifier for the session created by the
36572 uint32_t fw_session_id;
36574 * Unique session client identifier for the first client on
36575 * the newly created session.
36577 uint32_t fw_session_client_id;
36581 uint8_t unused1[3];
36583 * This field is used in Output records to indicate that the output
36584 * is completely written to RAM. This field should be read as '1'
36585 * to indicate that the output has been completely written.
36586 * When writing a command completion or response to an internal
36587 * processor, the order of writes has to be such that this field is
36593 /**************************
36594 * hwrm_tf_session_attach *
36595 **************************/
36598 /* hwrm_tf_session_attach_input (size:704b/88B) */
36599 struct hwrm_tf_session_attach_input {
36600 /* The HWRM command request type. */
36603 * The completion ring to send the completion event on. This should
36604 * be the NQ ID returned from the `nq_alloc` HWRM command.
36606 uint16_t cmpl_ring;
36608 * The sequence ID is used by the driver for tracking multiple
36609 * commands. This ID is treated as opaque data by the firmware and
36610 * the value is returned in the `hwrm_resp_hdr` upon completion.
36614 * The target ID of the command:
36615 * * 0x0-0xFFF8 - The function ID
36616 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36617 * * 0xFFFD - Reserved for user-space HWRM interface
36620 uint16_t target_id;
36622 * A physical address pointer pointing to a host buffer that the
36623 * command's response data will be written. This can be either a host
36624 * physical address (HPA) or a guest physical address (GPA) and must
36625 * point to a physically contiguous block of memory.
36627 uint64_t resp_addr;
36629 * Unique session identifier for the session that the attach
36630 * request want to attach to. This value originates from the
36631 * shared session memory that the attach request opened by
36632 * way of the 'attach name' that was passed in to the core
36634 * The fw_session_id of the attach session includes PCIe bus
36635 * info to distinguish the PF and session info to identify
36636 * the associated TruFlow session.
36638 uint32_t attach_fw_session_id;
36641 /* Name of the session it self. */
36642 uint8_t session_name[64];
36645 /* hwrm_tf_session_attach_output (size:128b/16B) */
36646 struct hwrm_tf_session_attach_output {
36647 /* The specific error status for the command. */
36648 uint16_t error_code;
36649 /* The HWRM command request type. */
36651 /* The sequence ID from the original command. */
36653 /* The length of the response data in number of bytes. */
36656 * Unique session identifier for the session created by the
36657 * firmware. It includes PCIe bus info to distinguish the PF
36658 * and session info to identify the associated TruFlow
36659 * session. This fw_session_id is unique to the attach
36662 uint32_t fw_session_id;
36664 uint8_t unused0[3];
36666 * This field is used in Output records to indicate that the output
36667 * is completely written to RAM. This field should be read as '1'
36668 * to indicate that the output has been completely written.
36669 * When writing a command completion or response to an internal
36670 * processor, the order of writes has to be such that this field is
36676 /****************************
36677 * hwrm_tf_session_register *
36678 ****************************/
36681 /* hwrm_tf_session_register_input (size:704b/88B) */
36682 struct hwrm_tf_session_register_input {
36683 /* The HWRM command request type. */
36686 * The completion ring to send the completion event on. This should
36687 * be the NQ ID returned from the `nq_alloc` HWRM command.
36689 uint16_t cmpl_ring;
36691 * The sequence ID is used by the driver for tracking multiple
36692 * commands. This ID is treated as opaque data by the firmware and
36693 * the value is returned in the `hwrm_resp_hdr` upon completion.
36697 * The target ID of the command:
36698 * * 0x0-0xFFF8 - The function ID
36699 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36700 * * 0xFFFD - Reserved for user-space HWRM interface
36703 uint16_t target_id;
36705 * A physical address pointer pointing to a host buffer that the
36706 * command's response data will be written. This can be either a host
36707 * physical address (HPA) or a guest physical address (GPA) and must
36708 * point to a physically contiguous block of memory.
36710 uint64_t resp_addr;
36712 * Unique session identifier for the session that the
36713 * register request want to create a new client on. This
36714 * value originates from the first open request.
36715 * The fw_session_id of the attach session includes PCIe bus
36716 * info to distinguish the PF and session info to identify
36717 * the associated TruFlow session.
36719 uint32_t fw_session_id;
36722 /* Name of the session client. */
36723 uint8_t session_client_name[64];
36726 /* hwrm_tf_session_register_output (size:128b/16B) */
36727 struct hwrm_tf_session_register_output {
36728 /* The specific error status for the command. */
36729 uint16_t error_code;
36730 /* The HWRM command request type. */
36732 /* The sequence ID from the original command. */
36734 /* The length of the response data in number of bytes. */
36737 * Unique session client identifier for the session created
36738 * by the firmware. It includes the session the client it
36739 * attached to and session client info.
36741 uint32_t fw_session_client_id;
36743 uint8_t unused0[3];
36745 * This field is used in Output records to indicate that the output
36746 * is completely written to RAM. This field should be read as '1'
36747 * to indicate that the output has been completely written.
36748 * When writing a command completion or response to an internal
36749 * processor, the order of writes has to be such that this field is
36755 /******************************
36756 * hwrm_tf_session_unregister *
36757 ******************************/
36760 /* hwrm_tf_session_unregister_input (size:192b/24B) */
36761 struct hwrm_tf_session_unregister_input {
36762 /* The HWRM command request type. */
36765 * The completion ring to send the completion event on. This should
36766 * be the NQ ID returned from the `nq_alloc` HWRM command.
36768 uint16_t cmpl_ring;
36770 * The sequence ID is used by the driver for tracking multiple
36771 * commands. This ID is treated as opaque data by the firmware and
36772 * the value is returned in the `hwrm_resp_hdr` upon completion.
36776 * The target ID of the command:
36777 * * 0x0-0xFFF8 - The function ID
36778 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36779 * * 0xFFFD - Reserved for user-space HWRM interface
36782 uint16_t target_id;
36784 * A physical address pointer pointing to a host buffer that the
36785 * command's response data will be written. This can be either a host
36786 * physical address (HPA) or a guest physical address (GPA) and must
36787 * point to a physically contiguous block of memory.
36789 uint64_t resp_addr;
36791 * Unique session identifier for the session that the
36792 * unregister request want to close a session client on.
36794 uint32_t fw_session_id;
36796 * Unique session client identifier for the session that the
36797 * unregister request want to close.
36799 uint32_t fw_session_client_id;
36802 /* hwrm_tf_session_unregister_output (size:128b/16B) */
36803 struct hwrm_tf_session_unregister_output {
36804 /* The specific error status for the command. */
36805 uint16_t error_code;
36806 /* The HWRM command request type. */
36808 /* The sequence ID from the original command. */
36810 /* The length of the response data in number of bytes. */
36813 uint8_t unused0[7];
36815 * This field is used in Output records to indicate that the output
36816 * is completely written to RAM. This field should be read as '1'
36817 * to indicate that the output has been completely written.
36818 * When writing a command completion or response to an internal
36819 * processor, the order of writes has to be such that this field is
36825 /*************************
36826 * hwrm_tf_session_close *
36827 *************************/
36830 /* hwrm_tf_session_close_input (size:192b/24B) */
36831 struct hwrm_tf_session_close_input {
36832 /* The HWRM command request type. */
36835 * The completion ring to send the completion event on. This should
36836 * be the NQ ID returned from the `nq_alloc` HWRM command.
36838 uint16_t cmpl_ring;
36840 * The sequence ID is used by the driver for tracking multiple
36841 * commands. This ID is treated as opaque data by the firmware and
36842 * the value is returned in the `hwrm_resp_hdr` upon completion.
36846 * The target ID of the command:
36847 * * 0x0-0xFFF8 - The function ID
36848 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36849 * * 0xFFFD - Reserved for user-space HWRM interface
36852 uint16_t target_id;
36854 * A physical address pointer pointing to a host buffer that the
36855 * command's response data will be written. This can be either a host
36856 * physical address (HPA) or a guest physical address (GPA) and must
36857 * point to a physically contiguous block of memory.
36859 uint64_t resp_addr;
36860 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
36861 uint32_t fw_session_id;
36863 uint8_t unused0[4];
36866 /* hwrm_tf_session_close_output (size:128b/16B) */
36867 struct hwrm_tf_session_close_output {
36868 /* The specific error status for the command. */
36869 uint16_t error_code;
36870 /* The HWRM command request type. */
36872 /* The sequence ID from the original command. */
36874 /* The length of the response data in number of bytes. */
36877 uint8_t unused0[7];
36879 * This field is used in Output records to indicate that the output
36880 * is completely written to RAM. This field should be read as '1'
36881 * to indicate that the output has been completely written.
36882 * When writing a command completion or response to an internal
36883 * processor, the order of writes has to be such that this field
36889 /************************
36890 * hwrm_tf_session_qcfg *
36891 ************************/
36894 /* hwrm_tf_session_qcfg_input (size:192b/24B) */
36895 struct hwrm_tf_session_qcfg_input {
36896 /* The HWRM command request type. */
36899 * The completion ring to send the completion event on. This should
36900 * be the NQ ID returned from the `nq_alloc` HWRM command.
36902 uint16_t cmpl_ring;
36904 * The sequence ID is used by the driver for tracking multiple
36905 * commands. This ID is treated as opaque data by the firmware and
36906 * the value is returned in the `hwrm_resp_hdr` upon completion.
36910 * The target ID of the command:
36911 * * 0x0-0xFFF8 - The function ID
36912 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36913 * * 0xFFFD - Reserved for user-space HWRM interface
36916 uint16_t target_id;
36918 * A physical address pointer pointing to a host buffer that the
36919 * command's response data will be written. This can be either a host
36920 * physical address (HPA) or a guest physical address (GPA) and must
36921 * point to a physically contiguous block of memory.
36923 uint64_t resp_addr;
36924 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
36925 uint32_t fw_session_id;
36927 uint8_t unused0[4];
36930 /* hwrm_tf_session_qcfg_output (size:128b/16B) */
36931 struct hwrm_tf_session_qcfg_output {
36932 /* The specific error status for the command. */
36933 uint16_t error_code;
36934 /* The HWRM command request type. */
36936 /* The sequence ID from the original command. */
36938 /* The length of the response data in number of bytes. */
36940 /* RX action control settings flags. */
36941 uint8_t rx_act_flags;
36943 * A value of 1 in this field indicates that Global Flow ID
36944 * reporting into cfa_code and cfa_metadata is enabled.
36946 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \
36949 * A value of 1 in this field indicates that both inner and outer
36950 * are stripped and inner tag is passed.
36953 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \
36956 * A value of 1 in this field indicates that the re-use of
36957 * existing tunnel L2 header SMAC is enabled for
36958 * Non-tunnel L2, L2-L3 and IP-IP tunnel.
36960 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \
36962 /* TX Action control settings flags. */
36963 uint8_t tx_act_flags;
36965 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \
36968 * When set to 1 any GRE tunnels will include the
36969 * optional Key field.
36971 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \
36974 * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)
36975 * field of the outer header is inherited from the inner header
36976 * (if present) or the fixed value as taken from the encap
36979 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \
36982 * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)
36983 * field of the outer header is inherited from the inner header
36984 * (if present) or the fixed value as taken from the encap record.
36986 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \
36989 uint8_t unused0[5];
36991 * This field is used in Output records to indicate that the output
36992 * is completely written to RAM. This field should be read as '1'
36993 * to indicate that the output has been completely written.
36994 * When writing a command completion or response to an internal
36995 * processor, the order of writes has to be such that this field
37001 /******************************
37002 * hwrm_tf_session_resc_qcaps *
37003 ******************************/
37006 /* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */
37007 struct hwrm_tf_session_resc_qcaps_input {
37008 /* The HWRM command request type. */
37011 * The completion ring to send the completion event on. This should
37012 * be the NQ ID returned from the `nq_alloc` HWRM command.
37014 uint16_t cmpl_ring;
37016 * The sequence ID is used by the driver for tracking multiple
37017 * commands. This ID is treated as opaque data by the firmware and
37018 * the value is returned in the `hwrm_resp_hdr` upon completion.
37022 * The target ID of the command:
37023 * * 0x0-0xFFF8 - The function ID
37024 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37025 * * 0xFFFD - Reserved for user-space HWRM interface
37028 uint16_t target_id;
37030 * A physical address pointer pointing to a host buffer that the
37031 * command's response data will be written. This can be either a host
37032 * physical address (HPA) or a guest physical address (GPA) and must
37033 * point to a physically contiguous block of memory.
37035 uint64_t resp_addr;
37036 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37037 uint32_t fw_session_id;
37038 /* Control flags. */
37040 /* Indicates the flow direction. */
37041 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
37042 /* If this bit set to 0, then it indicates rx flow. */
37043 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37044 /* If this bit is set to 1, then it indicates that tx flow. */
37045 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37046 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \
37047 HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX
37049 * Defines the size of the provided qcaps_addr array
37050 * buffer. The size should be set to the Resource Manager
37051 * provided max number of qcaps entries which is device
37052 * specific. Resource Manager gets the max size from HCAPI
37055 uint16_t qcaps_size;
37057 * This is the DMA address for the qcaps output data array
37058 * buffer. Array is of tf_rm_resc_req_entry type and is
37061 uint64_t qcaps_addr;
37064 /* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */
37065 struct hwrm_tf_session_resc_qcaps_output {
37066 /* The specific error status for the command. */
37067 uint16_t error_code;
37068 /* The HWRM command request type. */
37070 /* The sequence ID from the original command. */
37072 /* The length of the response data in number of bytes. */
37074 /* Control flags. */
37076 /* Session reservation strategy. */
37077 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \
37079 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \
37081 /* Static partitioning. */
37082 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \
37085 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \
37088 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \
37091 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \
37093 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \
37094 HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3
37096 * Size of the returned qcaps_addr data array buffer. The
37097 * value cannot exceed the size defined by the input msg,
37104 uint8_t unused1[7];
37106 * This field is used in Output records to indicate that the output
37107 * is completely written to RAM. This field should be read as '1'
37108 * to indicate that the output has been completely written.
37109 * When writing a command completion or response to an internal
37110 * processor, the order of writes has to be such that this field is
37116 /******************************
37117 * hwrm_tf_session_resc_alloc *
37118 ******************************/
37121 /* hwrm_tf_session_resc_alloc_input (size:320b/40B) */
37122 struct hwrm_tf_session_resc_alloc_input {
37123 /* The HWRM command request type. */
37126 * The completion ring to send the completion event on. This should
37127 * be the NQ ID returned from the `nq_alloc` HWRM command.
37129 uint16_t cmpl_ring;
37131 * The sequence ID is used by the driver for tracking multiple
37132 * commands. This ID is treated as opaque data by the firmware and
37133 * the value is returned in the `hwrm_resp_hdr` upon completion.
37137 * The target ID of the command:
37138 * * 0x0-0xFFF8 - The function ID
37139 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37140 * * 0xFFFD - Reserved for user-space HWRM interface
37143 uint16_t target_id;
37145 * A physical address pointer pointing to a host buffer that the
37146 * command's response data will be written. This can be either a host
37147 * physical address (HPA) or a guest physical address (GPA) and must
37148 * point to a physically contiguous block of memory.
37150 uint64_t resp_addr;
37151 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37152 uint32_t fw_session_id;
37153 /* Control flags. */
37155 /* Indicates the flow direction. */
37156 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
37157 /* If this bit set to 0, then it indicates rx flow. */
37158 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37159 /* If this bit is set to 1, then it indicates that tx flow. */
37160 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37161 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \
37162 HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX
37164 * Defines the array size of the provided req_addr and
37165 * resv_addr array buffers. Should be set to the number of
37170 * This is the DMA address for the request input data array
37171 * buffer. Array is of tf_rm_resc_req_entry type. Size of the
37172 * array buffer is provided by the 'req_size' field in this
37177 * This is the DMA address for the resc output data array
37178 * buffer. Array is of tf_rm_resc_entry type. Size of the array
37179 * buffer is provided by the 'req_size' field in this
37182 uint64_t resc_addr;
37185 /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */
37186 struct hwrm_tf_session_resc_alloc_output {
37187 /* The specific error status for the command. */
37188 uint16_t error_code;
37189 /* The HWRM command request type. */
37191 /* The sequence ID from the original command. */
37193 /* The length of the response data in number of bytes. */
37196 * Size of the returned tf_rm_resc_entry data array. The value
37197 * cannot exceed the req_size defined by the input msg. The data
37198 * array is returned using the resv_addr specified DMA
37199 * address also provided by the input msg.
37203 uint8_t unused0[5];
37205 * This field is used in Output records to indicate that the output
37206 * is completely written to RAM. This field should be read as '1'
37207 * to indicate that the output has been completely written.
37208 * When writing a command completion or response to an internal
37209 * processor, the order of writes has to be such that this field is
37215 /*****************************
37216 * hwrm_tf_session_resc_free *
37217 *****************************/
37220 /* hwrm_tf_session_resc_free_input (size:256b/32B) */
37221 struct hwrm_tf_session_resc_free_input {
37222 /* The HWRM command request type. */
37225 * The completion ring to send the completion event on. This should
37226 * be the NQ ID returned from the `nq_alloc` HWRM command.
37228 uint16_t cmpl_ring;
37230 * The sequence ID is used by the driver for tracking multiple
37231 * commands. This ID is treated as opaque data by the firmware and
37232 * the value is returned in the `hwrm_resp_hdr` upon completion.
37236 * The target ID of the command:
37237 * * 0x0-0xFFF8 - The function ID
37238 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37239 * * 0xFFFD - Reserved for user-space HWRM interface
37242 uint16_t target_id;
37244 * A physical address pointer pointing to a host buffer that the
37245 * command's response data will be written. This can be either a host
37246 * physical address (HPA) or a guest physical address (GPA) and must
37247 * point to a physically contiguous block of memory.
37249 uint64_t resp_addr;
37250 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37251 uint32_t fw_session_id;
37252 /* Control flags. */
37254 /* Indicates the flow direction. */
37255 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
37256 /* If this bit set to 0, then it indicates rx flow. */
37257 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37258 /* If this bit is set to 1, then it indicates that tx flow. */
37259 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37260 #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \
37261 HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX
37263 * Defines the size, in bytes, of the provided free_addr
37266 uint16_t free_size;
37268 * This is the DMA address for the free input data array
37269 * buffer. Array is of tf_rm_resc_entry type. Size of the
37270 * buffer is provided by the 'free_size' field of this
37273 uint64_t free_addr;
37276 /* hwrm_tf_session_resc_free_output (size:128b/16B) */
37277 struct hwrm_tf_session_resc_free_output {
37278 /* The specific error status for the command. */
37279 uint16_t error_code;
37280 /* The HWRM command request type. */
37282 /* The sequence ID from the original command. */
37284 /* The length of the response data in number of bytes. */
37287 uint8_t unused0[7];
37289 * This field is used in Output records to indicate that the output
37290 * is completely written to RAM. This field should be read as '1'
37291 * to indicate that the output has been completely written.
37292 * When writing a command completion or response to an internal
37293 * processor, the order of writes has to be such that this field is
37299 /******************************
37300 * hwrm_tf_session_resc_flush *
37301 ******************************/
37304 /* hwrm_tf_session_resc_flush_input (size:256b/32B) */
37305 struct hwrm_tf_session_resc_flush_input {
37306 /* The HWRM command request type. */
37309 * The completion ring to send the completion event on. This should
37310 * be the NQ ID returned from the `nq_alloc` HWRM command.
37312 uint16_t cmpl_ring;
37314 * The sequence ID is used by the driver for tracking multiple
37315 * commands. This ID is treated as opaque data by the firmware and
37316 * the value is returned in the `hwrm_resp_hdr` upon completion.
37320 * The target ID of the command:
37321 * * 0x0-0xFFF8 - The function ID
37322 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37323 * * 0xFFFD - Reserved for user-space HWRM interface
37326 uint16_t target_id;
37328 * A physical address pointer pointing to a host buffer that the
37329 * command's response data will be written. This can be either a host
37330 * physical address (HPA) or a guest physical address (GPA) and must
37331 * point to a physically contiguous block of memory.
37333 uint64_t resp_addr;
37334 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37335 uint32_t fw_session_id;
37336 /* Control flags. */
37338 /* Indicates the flow direction. */
37339 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
37340 /* If this bit set to 0, then it indicates rx flow. */
37341 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37342 /* If this bit is set to 1, then it indicates that tx flow. */
37343 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37344 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \
37345 HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX
37347 * Defines the size, in bytes, of the provided flush_addr
37350 uint16_t flush_size;
37352 * This is the DMA address for the flush input data array
37353 * buffer. Array of tf_rm_resc_entry type. Size of the
37354 * buffer is provided by the 'flush_size' field in this
37357 uint64_t flush_addr;
37360 /* hwrm_tf_session_resc_flush_output (size:128b/16B) */
37361 struct hwrm_tf_session_resc_flush_output {
37362 /* The specific error status for the command. */
37363 uint16_t error_code;
37364 /* The HWRM command request type. */
37366 /* The sequence ID from the original command. */
37368 /* The length of the response data in number of bytes. */
37371 uint8_t unused0[7];
37373 * This field is used in Output records to indicate that the output
37374 * is completely written to RAM. This field should be read as '1'
37375 * to indicate that the output has been completely written.
37376 * When writing a command completion or response to an internal
37377 * processor, the order of writes has to be such that this field is
37383 /* TruFlow RM capability of a resource. */
37384 /* tf_rm_resc_req_entry (size:64b/8B) */
37385 struct tf_rm_resc_req_entry {
37386 /* Type of the resource, defined globally in HCAPI RM. */
37388 /* Minimum value. */
37390 /* Maximum value. */
37394 /* TruFlow RM reservation information. */
37395 /* tf_rm_resc_entry (size:64b/8B) */
37396 struct tf_rm_resc_entry {
37397 /* Type of the resource, defined globally in HCAPI RM. */
37399 /* Start offset. */
37401 /* Number of resources. */
37405 /************************
37406 * hwrm_tf_tbl_type_get *
37407 ************************/
37410 /* hwrm_tf_tbl_type_get_input (size:256b/32B) */
37411 struct hwrm_tf_tbl_type_get_input {
37412 /* The HWRM command request type. */
37415 * The completion ring to send the completion event on. This should
37416 * be the NQ ID returned from the `nq_alloc` HWRM command.
37418 uint16_t cmpl_ring;
37420 * The sequence ID is used by the driver for tracking multiple
37421 * commands. This ID is treated as opaque data by the firmware and
37422 * the value is returned in the `hwrm_resp_hdr` upon completion.
37426 * The target ID of the command:
37427 * * 0x0-0xFFF8 - The function ID
37428 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37429 * * 0xFFFD - Reserved for user-space HWRM interface
37432 uint16_t target_id;
37434 * A physical address pointer pointing to a host buffer that the
37435 * command's response data will be written. This can be either a host
37436 * physical address (HPA) or a guest physical address (GPA) and must
37437 * point to a physically contiguous block of memory.
37439 uint64_t resp_addr;
37440 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37441 uint32_t fw_session_id;
37442 /* Control flags. */
37444 /* Indicates the flow direction. */
37445 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
37446 /* If this bit set to 0, then it indicates rx flow. */
37447 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37448 /* If this bit is set to 1, then it indicates that tx flow. */
37449 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37450 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \
37451 HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX
37453 uint8_t unused0[2];
37455 * Type of the resource, defined globally in the
37456 * hwrm_tf_resc_type enum.
37459 /* Index of the type to retrieve. */
37463 /* hwrm_tf_tbl_type_get_output (size:1216b/152B) */
37464 struct hwrm_tf_tbl_type_get_output {
37465 /* The specific error status for the command. */
37466 uint16_t error_code;
37467 /* The HWRM command request type. */
37469 /* The sequence ID from the original command. */
37471 /* The length of the response data in number of bytes. */
37473 /* Response code. */
37474 uint32_t resp_code;
37475 /* Response size. */
37479 /* Response data. */
37482 uint8_t unused1[7];
37484 * This field is used in Output records to indicate that the output
37485 * is completely written to RAM. This field should be read as '1'
37486 * to indicate that the output has been completely written.
37487 * When writing a command completion or response to an internal
37488 * processor, the order of writes has to be such that this field
37494 /************************
37495 * hwrm_tf_tbl_type_set *
37496 ************************/
37499 /* hwrm_tf_tbl_type_set_input (size:1024b/128B) */
37500 struct hwrm_tf_tbl_type_set_input {
37501 /* The HWRM command request type. */
37504 * The completion ring to send the completion event on. This should
37505 * be the NQ ID returned from the `nq_alloc` HWRM command.
37507 uint16_t cmpl_ring;
37509 * The sequence ID is used by the driver for tracking multiple
37510 * commands. This ID is treated as opaque data by the firmware and
37511 * the value is returned in the `hwrm_resp_hdr` upon completion.
37515 * The target ID of the command:
37516 * * 0x0-0xFFF8 - The function ID
37517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37518 * * 0xFFFD - Reserved for user-space HWRM interface
37521 uint16_t target_id;
37523 * A physical address pointer pointing to a host buffer that the
37524 * command's response data will be written. This can be either a host
37525 * physical address (HPA) or a guest physical address (GPA) and must
37526 * point to a physically contiguous block of memory.
37528 uint64_t resp_addr;
37529 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
37530 uint32_t fw_session_id;
37531 /* Control flags. */
37533 /* Indicates the flow direction. */
37534 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
37535 /* If this bit set to 0, then it indicates rx flow. */
37536 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37537 /* If this bit is set to 1, then it indicates that tx flow. */
37538 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37539 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \
37540 HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX
37542 uint8_t unused0[2];
37544 * Type of the resource, defined globally in the
37545 * hwrm_tf_resc_type enum.
37548 /* Index of the type to retrieve. */
37550 /* Size of the data to set. */
37553 uint8_t unused1[6];
37554 /* Data to be set. */
37558 /* hwrm_tf_tbl_type_set_output (size:128b/16B) */
37559 struct hwrm_tf_tbl_type_set_output {
37560 /* The specific error status for the command. */
37561 uint16_t error_code;
37562 /* The HWRM command request type. */
37564 /* The sequence ID from the original command. */
37566 /* The length of the response data in number of bytes. */
37569 uint8_t unused0[7];
37571 * This field is used in Output records to indicate that the output
37572 * is completely written to RAM. This field should be read as '1'
37573 * to indicate that the output has been completely written.
37574 * When writing a command completion or response to an internal
37575 * processor, the order of writes has to be such that this field
37581 /*************************
37582 * hwrm_tf_ctxt_mem_rgtr *
37583 *************************/
37586 /* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */
37587 struct hwrm_tf_ctxt_mem_rgtr_input {
37588 /* The HWRM command request type. */
37591 * The completion ring to send the completion event on. This should
37592 * be the NQ ID returned from the `nq_alloc` HWRM command.
37594 uint16_t cmpl_ring;
37596 * The sequence ID is used by the driver for tracking multiple
37597 * commands. This ID is treated as opaque data by the firmware and
37598 * the value is returned in the `hwrm_resp_hdr` upon completion.
37602 * The target ID of the command:
37603 * * 0x0-0xFFF8 - The function ID
37604 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37605 * * 0xFFFD - Reserved for user-space HWRM interface
37608 uint16_t target_id;
37610 * A physical address pointer pointing to a host buffer that the
37611 * command's response data will be written. This can be either a host
37612 * physical address (HPA) or a guest physical address (GPA) and must
37613 * point to a physically contiguous block of memory.
37615 uint64_t resp_addr;
37616 /* Control flags. */
37618 /* Counter PBL indirect levels. */
37619 uint8_t page_level;
37620 /* PBL pointer is physical start address. */
37621 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
37622 /* PBL pointer points to PTE table. */
37623 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
37625 * PBL pointer points to PDE table with each entry pointing
37628 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
37629 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
37630 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
37633 /* 4KB page size. */
37634 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
37635 /* 8KB page size. */
37636 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
37637 /* 64KB page size. */
37638 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
37639 /* 256KB page size. */
37640 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
37641 /* 1MB page size. */
37642 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
37643 /* 2MB page size. */
37644 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
37645 /* 4MB page size. */
37646 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
37647 /* 1GB page size. */
37648 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
37649 #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
37650 HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G
37653 /* Pointer to the PBL, or PDL depending on number of levels */
37657 /* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */
37658 struct hwrm_tf_ctxt_mem_rgtr_output {
37659 /* The specific error status for the command. */
37660 uint16_t error_code;
37661 /* The HWRM command request type. */
37663 /* The sequence ID from the original command. */
37665 /* The length of the response data in number of bytes. */
37668 * Id/Handle to the recently register context memory. This
37669 * handle is passed to the TF session.
37673 uint8_t unused0[5];
37675 * This field is used in Output records to indicate that the
37676 * output is completely written to RAM. This field should be
37677 * read as '1' to indicate that the output has been
37678 * completely written. When writing a command completion or
37679 * response to an internal processor, the order of writes has
37680 * to be such that this field is written last.
37685 /***************************
37686 * hwrm_tf_ctxt_mem_unrgtr *
37687 ***************************/
37690 /* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */
37691 struct hwrm_tf_ctxt_mem_unrgtr_input {
37692 /* The HWRM command request type. */
37695 * The completion ring to send the completion event on. This should
37696 * be the NQ ID returned from the `nq_alloc` HWRM command.
37698 uint16_t cmpl_ring;
37700 * The sequence ID is used by the driver for tracking multiple
37701 * commands. This ID is treated as opaque data by the firmware and
37702 * the value is returned in the `hwrm_resp_hdr` upon completion.
37706 * The target ID of the command:
37707 * * 0x0-0xFFF8 - The function ID
37708 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37709 * * 0xFFFD - Reserved for user-space HWRM interface
37712 uint16_t target_id;
37714 * A physical address pointer pointing to a host buffer that the
37715 * command's response data will be written. This can be either a host
37716 * physical address (HPA) or a guest physical address (GPA) and must
37717 * point to a physically contiguous block of memory.
37719 uint64_t resp_addr;
37721 * Id/Handle to the recently register context memory. This
37722 * handle is passed to the TF session.
37726 uint8_t unused0[6];
37729 /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */
37730 struct hwrm_tf_ctxt_mem_unrgtr_output {
37731 /* The specific error status for the command. */
37732 uint16_t error_code;
37733 /* The HWRM command request type. */
37735 /* The sequence ID from the original command. */
37737 /* The length of the response data in number of bytes. */
37740 uint8_t unused0[7];
37742 * This field is used in Output records to indicate that the
37743 * output is completely written to RAM. This field should be
37744 * read as '1' to indicate that the output has been
37745 * completely written. When writing a command completion or
37746 * response to an internal processor, the order of writes has
37747 * to be such that this field is written last.
37752 /************************
37753 * hwrm_tf_ext_em_qcaps *
37754 ************************/
37757 /* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */
37758 struct hwrm_tf_ext_em_qcaps_input {
37759 /* The HWRM command request type. */
37762 * The completion ring to send the completion event on. This should
37763 * be the NQ ID returned from the `nq_alloc` HWRM command.
37765 uint16_t cmpl_ring;
37767 * The sequence ID is used by the driver for tracking multiple
37768 * commands. This ID is treated as opaque data by the firmware and
37769 * the value is returned in the `hwrm_resp_hdr` upon completion.
37773 * The target ID of the command:
37774 * * 0x0-0xFFF8 - The function ID
37775 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37776 * * 0xFFFD - Reserved for user-space HWRM interface
37779 uint16_t target_id;
37781 * A physical address pointer pointing to a host buffer that the
37782 * command's response data will be written. This can be either a host
37783 * physical address (HPA) or a guest physical address (GPA) and must
37784 * point to a physically contiguous block of memory.
37786 uint64_t resp_addr;
37787 /* Control flags. */
37789 /* Indicates the flow direction. */
37790 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \
37792 /* If this bit set to 0, then it indicates rx flow. */
37793 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \
37795 /* If this bit is set to 1, then it indicates that tx flow. */
37796 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \
37798 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \
37799 HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX
37800 /* When set to 1, all offloaded flows will be sent to EXT EM. */
37801 #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
37807 /* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */
37808 struct hwrm_tf_ext_em_qcaps_output {
37809 /* The specific error status for the command. */
37810 uint16_t error_code;
37811 /* The HWRM command request type. */
37813 /* The sequence ID from the original command. */
37815 /* The length of the response data in number of bytes. */
37819 * When set to 1, indicates the the FW supports the Centralized
37820 * Memory Model. The concept designates one entity for the
37821 * memory allocation while all others ‘subscribe’ to it.
37823 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
37826 * When set to 1, indicates the the FW supports the Detached
37827 * Centralized Memory Model. The memory is allocated and managed
37828 * as a separate entity. All PFs and VFs will be granted direct
37829 * or semi-direct access to the allocated memory while none of
37830 * which can interfere with the management of the memory.
37832 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
37836 /* Support flags. */
37837 uint32_t supported;
37839 * If set to 1, then EXT EM KEY0 table is supported using
37841 * If set to 0, EXT EM KEY0 table is not supported.
37843 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
37846 * If set to 1, then EXT EM KEY1 table is supported using
37848 * If set to 0, EXT EM KEY1 table is not supported.
37850 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
37853 * If set to 1, then EXT EM External Record table is supported.
37854 * If set to 0, EXT EM External Record table is not
37855 * supported. (This table includes action record, EFC
37856 * pointers, encap pointers)
37858 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
37861 * If set to 1, then EXT EM External Flow Counters table is
37863 * If set to 0, EXT EM External Flow Counters table is not
37866 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
37869 * If set to 1, then FID table used for implicit flow flush
37871 * If set to 0, then FID table used for implicit flow flush
37872 * is not supported.
37874 #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \
37877 * The maximum number of entries supported by EXT EM. When
37878 * configuring the host memory the number of numbers of
37879 * entries that can supported are -
37880 * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,
37882 * Any value that are not these values, the FW will round
37883 * down to the closest support number of entries.
37885 uint32_t max_entries_supported;
37887 * The entry size in bytes of each entry in the EXT EM
37888 * KEY0/KEY1 tables.
37890 uint16_t key_entry_size;
37892 * The entry size in bytes of each entry in the EXT EM RECORD
37895 uint16_t record_entry_size;
37896 /* The entry size in bytes of each entry in the EXT EM EFC tables. */
37897 uint16_t efc_entry_size;
37898 /* The FID size in bytes of each entry in the EXT EM FID tables. */
37899 uint16_t fid_entry_size;
37901 uint8_t unused1[7];
37903 * This field is used in Output records to indicate that the
37904 * output is completely written to RAM. This field should be
37905 * read as '1' to indicate that the output has been
37906 * completely written. When writing a command completion or
37907 * response to an internal processor, the order of writes has
37908 * to be such that this field is written last.
37913 /*********************
37914 * hwrm_tf_ext_em_op *
37915 *********************/
37918 /* hwrm_tf_ext_em_op_input (size:192b/24B) */
37919 struct hwrm_tf_ext_em_op_input {
37920 /* The HWRM command request type. */
37923 * The completion ring to send the completion event on. This should
37924 * be the NQ ID returned from the `nq_alloc` HWRM command.
37926 uint16_t cmpl_ring;
37928 * The sequence ID is used by the driver for tracking multiple
37929 * commands. This ID is treated as opaque data by the firmware and
37930 * the value is returned in the `hwrm_resp_hdr` upon completion.
37934 * The target ID of the command:
37935 * * 0x0-0xFFF8 - The function ID
37936 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37937 * * 0xFFFD - Reserved for user-space HWRM interface
37940 uint16_t target_id;
37942 * A physical address pointer pointing to a host buffer that the
37943 * command's response data will be written. This can be either a host
37944 * physical address (HPA) or a guest physical address (GPA) and must
37945 * point to a physically contiguous block of memory.
37947 uint64_t resp_addr;
37948 /* Control flags. */
37950 /* Indicates the flow direction. */
37951 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1)
37952 /* If this bit set to 0, then it indicates rx flow. */
37953 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
37954 /* If this bit is set to 1, then it indicates that tx flow. */
37955 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
37956 #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \
37957 HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX
37960 /* The number of EXT EM key table entries to be configured. */
37962 /* This value is reserved and should not be used. */
37963 #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
37965 * To properly stop EXT EM and ensure there are no DMA's,
37966 * the caller must disable EXT EM for the given PF, using
37967 * this call. This will safely disable EXT EM and ensure
37968 * that all DMA'ed to the keys/records/efc have been
37971 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)
37973 * Once the EXT EM host memory has been configured, EXT EM
37974 * options have been configured. Then the caller should
37975 * enable EXT EM for the given PF. Note once this call has
37976 * been made, then the EXT EM mechanism will be active and
37977 * DMA's will occur as packets are processed.
37979 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2)
37981 * Clear EXT EM settings for the given PF so that the
37982 * register values are reset back to their initial state.
37984 #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)
37985 #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \
37986 HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP
37991 /* hwrm_tf_ext_em_op_output (size:128b/16B) */
37992 struct hwrm_tf_ext_em_op_output {
37993 /* The specific error status for the command. */
37994 uint16_t error_code;
37995 /* The HWRM command request type. */
37997 /* The sequence ID from the original command. */
37999 /* The length of the response data in number of bytes. */
38002 uint8_t unused0[7];
38004 * This field is used in Output records to indicate that the
38005 * output is completely written to RAM. This field should be
38006 * read as '1' to indicate that the output has been
38007 * completely written. When writing a command completion or
38008 * response to an internal processor, the order of writes has
38009 * to be such that this field is written last.
38014 /**********************
38015 * hwrm_tf_ext_em_cfg *
38016 **********************/
38019 /* hwrm_tf_ext_em_cfg_input (size:384b/48B) */
38020 struct hwrm_tf_ext_em_cfg_input {
38021 /* The HWRM command request type. */
38024 * The completion ring to send the completion event on. This should
38025 * be the NQ ID returned from the `nq_alloc` HWRM command.
38027 uint16_t cmpl_ring;
38029 * The sequence ID is used by the driver for tracking multiple
38030 * commands. This ID is treated as opaque data by the firmware and
38031 * the value is returned in the `hwrm_resp_hdr` upon completion.
38035 * The target ID of the command:
38036 * * 0x0-0xFFF8 - The function ID
38037 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38038 * * 0xFFFD - Reserved for user-space HWRM interface
38041 uint16_t target_id;
38043 * A physical address pointer pointing to a host buffer that the
38044 * command's response data will be written. This can be either a host
38045 * physical address (HPA) or a guest physical address (GPA) and must
38046 * point to a physically contiguous block of memory.
38048 uint64_t resp_addr;
38049 /* Control flags. */
38051 /* Indicates the flow direction. */
38052 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \
38054 /* If this bit set to 0, then it indicates rx flow. */
38055 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \
38057 /* If this bit is set to 1, then it indicates that tx flow. */
38058 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \
38060 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \
38061 HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX
38062 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38063 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
38065 /* When set to 1, secondary, 0 means primary. */
38066 #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \
38069 * Group_id which used by Firmware to identify memory pools belonging
38070 * to certain group.
38074 * Dynamically reconfigure EEM pending cache every 1/10th of second.
38075 * If set to 0 it will disable the EEM HW flush of the pending cache.
38077 uint8_t flush_interval;
38081 * Configured EXT EM with the given number of entries. All
38082 * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the
38083 * same number of entries and all tables will be configured
38084 * using this value. Current minimum value is 32k. Current
38085 * maximum value is 128M.
38087 uint32_t num_entries;
38090 /* Configured EXT EM with the given context if for KEY0 table. */
38091 uint16_t key0_ctx_id;
38092 /* Configured EXT EM with the given context if for KEY1 table. */
38093 uint16_t key1_ctx_id;
38094 /* Configured EXT EM with the given context if for RECORD table. */
38095 uint16_t record_ctx_id;
38096 /* Configured EXT EM with the given context if for EFC table. */
38097 uint16_t efc_ctx_id;
38098 /* Configured EXT EM with the given context if for EFC table. */
38099 uint16_t fid_ctx_id;
38106 /* hwrm_tf_ext_em_cfg_output (size:128b/16B) */
38107 struct hwrm_tf_ext_em_cfg_output {
38108 /* The specific error status for the command. */
38109 uint16_t error_code;
38110 /* The HWRM command request type. */
38112 /* The sequence ID from the original command. */
38114 /* The length of the response data in number of bytes. */
38117 uint8_t unused0[7];
38119 * This field is used in Output records to indicate that the
38120 * output is completely written to RAM. This field should be
38121 * read as '1' to indicate that the output has been
38122 * completely written. When writing a command completion or
38123 * response to an internal processor, the order of writes has
38124 * to be such that this field is written last.
38129 /***********************
38130 * hwrm_tf_ext_em_qcfg *
38131 ***********************/
38134 /* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */
38135 struct hwrm_tf_ext_em_qcfg_input {
38136 /* The HWRM command request type. */
38139 * The completion ring to send the completion event on. This should
38140 * be the NQ ID returned from the `nq_alloc` HWRM command.
38142 uint16_t cmpl_ring;
38144 * The sequence ID is used by the driver for tracking multiple
38145 * commands. This ID is treated as opaque data by the firmware and
38146 * the value is returned in the `hwrm_resp_hdr` upon completion.
38150 * The target ID of the command:
38151 * * 0x0-0xFFF8 - The function ID
38152 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38153 * * 0xFFFD - Reserved for user-space HWRM interface
38156 uint16_t target_id;
38158 * A physical address pointer pointing to a host buffer that the
38159 * command's response data will be written. This can be either a host
38160 * physical address (HPA) or a guest physical address (GPA) and must
38161 * point to a physically contiguous block of memory.
38163 uint64_t resp_addr;
38164 /* Control flags. */
38166 /* Indicates the flow direction. */
38167 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1)
38168 /* If this bit set to 0, then it indicates rx flow. */
38169 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38170 /* If this bit is set to 1, then it indicates that tx flow. */
38171 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38172 #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \
38173 HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX
38178 /* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */
38179 struct hwrm_tf_ext_em_qcfg_output {
38180 /* The specific error status for the command. */
38181 uint16_t error_code;
38182 /* The HWRM command request type. */
38184 /* The sequence ID from the original command. */
38186 /* The length of the response data in number of bytes. */
38188 /* Control flags. */
38190 /* Indicates the flow direction. */
38191 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \
38193 /* If this bit set to 0, then it indicates rx flow. */
38194 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \
38196 /* If this bit is set to 1, then it indicates that tx flow. */
38197 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \
38199 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \
38200 HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX
38201 /* When set to 1, all offloaded flows will be sent to EXT EM. */
38202 #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
38204 /* The number of entries the FW has configured for EXT EM. */
38205 uint32_t num_entries;
38206 /* Configured EXT EM with the given context if for KEY0 table. */
38207 uint16_t key0_ctx_id;
38208 /* Configured EXT EM with the given context if for KEY1 table. */
38209 uint16_t key1_ctx_id;
38210 /* Configured EXT EM with the given context if for RECORD table. */
38211 uint16_t record_ctx_id;
38212 /* Configured EXT EM with the given context if for EFC table. */
38213 uint16_t efc_ctx_id;
38214 /* Configured EXT EM with the given context if for EFC table. */
38215 uint16_t fid_ctx_id;
38217 uint8_t unused0[5];
38219 * This field is used in Output records to indicate that the
38220 * output is completely written to RAM. This field should be
38221 * read as '1' to indicate that the output has been
38222 * completely written. When writing a command completion or
38223 * response to an internal processor, the order of writes has
38224 * to be such that this field is written last.
38229 /*********************
38230 * hwrm_tf_em_insert *
38231 *********************/
38234 /* hwrm_tf_em_insert_input (size:832b/104B) */
38235 struct hwrm_tf_em_insert_input {
38236 /* The HWRM command request type. */
38239 * The completion ring to send the completion event on. This should
38240 * be the NQ ID returned from the `nq_alloc` HWRM command.
38242 uint16_t cmpl_ring;
38244 * The sequence ID is used by the driver for tracking multiple
38245 * commands. This ID is treated as opaque data by the firmware and
38246 * the value is returned in the `hwrm_resp_hdr` upon completion.
38250 * The target ID of the command:
38251 * * 0x0-0xFFF8 - The function ID
38252 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38253 * * 0xFFFD - Reserved for user-space HWRM interface
38256 uint16_t target_id;
38258 * A physical address pointer pointing to a host buffer that the
38259 * command's response data will be written. This can be either a host
38260 * physical address (HPA) or a guest physical address (GPA) and must
38261 * point to a physically contiguous block of memory.
38263 uint64_t resp_addr;
38264 /* Firmware Session Id. */
38265 uint32_t fw_session_id;
38266 /* Control Flags. */
38268 /* Indicates the flow direction. */
38269 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
38270 /* If this bit set to 0, then it indicates rx flow. */
38271 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38272 /* If this bit is set to 1, then it indicates that tx flow. */
38273 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38274 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \
38275 HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX
38276 /* Reported match strength. */
38278 /* Index to action. */
38279 uint32_t action_ptr;
38280 /* Index of EM record. */
38281 uint32_t em_record_idx;
38282 /* EM Key value. */
38283 uint64_t em_key[8];
38284 /* Number of bits in em_key. */
38285 uint16_t em_key_bitlen;
38287 uint16_t unused0[3];
38290 /* hwrm_tf_em_insert_output (size:128b/16B) */
38291 struct hwrm_tf_em_insert_output {
38292 /* The specific error status for the command. */
38293 uint16_t error_code;
38294 /* The HWRM command request type. */
38296 /* The sequence ID from the original command. */
38298 /* The length of the response data in number of bytes. */
38300 /* EM record pointer index. */
38301 uint16_t rptr_index;
38302 /* EM record offset 0~3. */
38303 uint8_t rptr_entry;
38304 /* Number of word entries consumed by the key. */
38305 uint8_t num_of_entries;
38310 /*********************
38311 * hwrm_tf_em_delete *
38312 *********************/
38315 /* hwrm_tf_em_delete_input (size:832b/104B) */
38316 struct hwrm_tf_em_delete_input {
38317 /* The HWRM command request type. */
38320 * The completion ring to send the completion event on. This should
38321 * be the NQ ID returned from the `nq_alloc` HWRM command.
38323 uint16_t cmpl_ring;
38325 * The sequence ID is used by the driver for tracking multiple
38326 * commands. This ID is treated as opaque data by the firmware and
38327 * the value is returned in the `hwrm_resp_hdr` upon completion.
38331 * The target ID of the command:
38332 * * 0x0-0xFFF8 - The function ID
38333 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38334 * * 0xFFFD - Reserved for user-space HWRM interface
38337 uint16_t target_id;
38339 * A physical address pointer pointing to a host buffer that the
38340 * command's response data will be written. This can be either a host
38341 * physical address (HPA) or a guest physical address (GPA) and must
38342 * point to a physically contiguous block of memory.
38344 uint64_t resp_addr;
38346 uint32_t fw_session_id;
38347 /* Control flags. */
38349 /* Indicates the flow direction. */
38350 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
38351 /* If this bit set to 0, then it indicates rx flow. */
38352 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38353 /* If this bit is set to 1, then it indicates that tx flow. */
38354 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38355 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \
38356 HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX
38359 /* EM internal flow hanndle. */
38360 uint64_t flow_handle;
38362 uint64_t em_key[8];
38363 /* Number of bits in em_key. */
38364 uint16_t em_key_bitlen;
38366 uint16_t unused1[3];
38369 /* hwrm_tf_em_delete_output (size:128b/16B) */
38370 struct hwrm_tf_em_delete_output {
38371 /* The specific error status for the command. */
38372 uint16_t error_code;
38373 /* The HWRM command request type. */
38375 /* The sequence ID from the original command. */
38377 /* The length of the response data in number of bytes. */
38379 /* Original stack allocation index. */
38382 uint16_t unused0[3];
38385 /********************
38386 * hwrm_tf_tcam_set *
38387 ********************/
38390 /* hwrm_tf_tcam_set_input (size:1024b/128B) */
38391 struct hwrm_tf_tcam_set_input {
38392 /* The HWRM command request type. */
38395 * The completion ring to send the completion event on. This should
38396 * be the NQ ID returned from the `nq_alloc` HWRM command.
38398 uint16_t cmpl_ring;
38400 * The sequence ID is used by the driver for tracking multiple
38401 * commands. This ID is treated as opaque data by the firmware and
38402 * the value is returned in the `hwrm_resp_hdr` upon completion.
38406 * The target ID of the command:
38407 * * 0x0-0xFFF8 - The function ID
38408 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38409 * * 0xFFFD - Reserved for user-space HWRM interface
38412 uint16_t target_id;
38414 * A physical address pointer pointing to a host buffer that the
38415 * command's response data will be written. This can be either a host
38416 * physical address (HPA) or a guest physical address (GPA) and must
38417 * point to a physically contiguous block of memory.
38419 uint64_t resp_addr;
38420 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38421 uint32_t fw_session_id;
38422 /* Control flags. */
38424 /* Indicates the flow direction. */
38425 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
38426 /* If this bit set to 0, then it indicates rx flow. */
38427 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38428 /* If this bit is set to 1, then it indicates that tx flow. */
38429 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38430 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \
38431 HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX
38433 * Indicate device data is being sent via DMA, the device
38434 * data is packing does not change.
38436 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
38438 * TCAM type of the resource, defined globally in the
38439 * hwrm_tf_resc_type enum.
38442 /* Index of TCAM entry. */
38444 /* Number of bytes in the TCAM key. */
38446 /* Number of bytes in the TCAM result. */
38447 uint8_t result_size;
38449 * Offset from which the mask bytes start in the device data
38450 * array, key offset is always 0.
38452 uint8_t mask_offset;
38453 /* Offset from which the result bytes start in the device data array. */
38454 uint8_t result_offset;
38456 uint8_t unused0[6];
38458 * TCAM key located at offset 0, mask located at mask_offsec
38459 * and result at result_offsec for the device.
38461 uint8_t dev_data[88];
38464 /* hwrm_tf_tcam_set_output (size:128b/16B) */
38465 struct hwrm_tf_tcam_set_output {
38466 /* The specific error status for the command. */
38467 uint16_t error_code;
38468 /* The HWRM command request type. */
38470 /* The sequence ID from the original command. */
38472 /* The length of the response data in number of bytes. */
38475 uint8_t unused0[7];
38477 * This field is used in Output records to indicate that the
38478 * output is completely written to RAM. This field should be
38479 * read as '1' to indicate that the output has been
38480 * completely written. When writing a command completion or
38481 * response to an internal processor, the order of writes has
38482 * to be such that this field is written last.
38487 /********************
38488 * hwrm_tf_tcam_get *
38489 ********************/
38492 /* hwrm_tf_tcam_get_input (size:256b/32B) */
38493 struct hwrm_tf_tcam_get_input {
38494 /* The HWRM command request type. */
38497 * The completion ring to send the completion event on. This should
38498 * be the NQ ID returned from the `nq_alloc` HWRM command.
38500 uint16_t cmpl_ring;
38502 * The sequence ID is used by the driver for tracking multiple
38503 * commands. This ID is treated as opaque data by the firmware and
38504 * the value is returned in the `hwrm_resp_hdr` upon completion.
38508 * The target ID of the command:
38509 * * 0x0-0xFFF8 - The function ID
38510 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38511 * * 0xFFFD - Reserved for user-space HWRM interface
38514 uint16_t target_id;
38516 * A physical address pointer pointing to a host buffer that the
38517 * command's response data will be written. This can be either a host
38518 * physical address (HPA) or a guest physical address (GPA) and must
38519 * point to a physically contiguous block of memory.
38521 uint64_t resp_addr;
38522 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38523 uint32_t fw_session_id;
38524 /* Control flags. */
38526 /* Indicates the flow direction. */
38527 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
38528 /* If this bit set to 0, then it indicates rx flow. */
38529 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38530 /* If this bit is set to 1, then it indicates that tx flow. */
38531 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38532 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \
38533 HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX
38535 * TCAM type of the resource, defined globally in the
38536 * hwrm_tf_resc_type enum.
38539 /* Index of a TCAM entry. */
38545 /* hwrm_tf_tcam_get_output (size:2368b/296B) */
38546 struct hwrm_tf_tcam_get_output {
38547 /* The specific error status for the command. */
38548 uint16_t error_code;
38549 /* The HWRM command request type. */
38551 /* The sequence ID from the original command. */
38553 /* The length of the response data in number of bytes. */
38555 /* Number of bytes in the TCAM key. */
38557 /* Number of bytes in the TCAM entry. */
38558 uint8_t result_size;
38559 /* Offset from which the mask bytes start in the device data array. */
38560 uint8_t mask_offset;
38561 /* Offset from which the result bytes start in the device data array. */
38562 uint8_t result_offset;
38564 uint8_t unused0[4];
38566 * TCAM key located at offset 0, mask located at mask_offsec
38567 * and result at result_offsec for the device.
38569 uint8_t dev_data[272];
38571 uint8_t unused1[7];
38573 * This field is used in Output records to indicate that the
38574 * output is completely written to RAM. This field should be
38575 * read as '1' to indicate that the output has been
38576 * completely written. When writing a command completion or
38577 * response to an internal processor, the order of writes has
38578 * to be such that this field is written last.
38583 /*********************
38584 * hwrm_tf_tcam_move *
38585 *********************/
38588 /* hwrm_tf_tcam_move_input (size:1024b/128B) */
38589 struct hwrm_tf_tcam_move_input {
38590 /* The HWRM command request type. */
38593 * The completion ring to send the completion event on. This should
38594 * be the NQ ID returned from the `nq_alloc` HWRM command.
38596 uint16_t cmpl_ring;
38598 * The sequence ID is used by the driver for tracking multiple
38599 * commands. This ID is treated as opaque data by the firmware and
38600 * the value is returned in the `hwrm_resp_hdr` upon completion.
38604 * The target ID of the command:
38605 * * 0x0-0xFFF8 - The function ID
38606 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38607 * * 0xFFFD - Reserved for user-space HWRM interface
38610 uint16_t target_id;
38612 * A physical address pointer pointing to a host buffer that the
38613 * command's response data will be written. This can be either a host
38614 * physical address (HPA) or a guest physical address (GPA) and must
38615 * point to a physically contiguous block of memory.
38617 uint64_t resp_addr;
38618 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38619 uint32_t fw_session_id;
38620 /* Control flags. */
38622 /* Indicates the flow direction. */
38623 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
38624 /* If this bit set to 0, then it indicates rx flow. */
38625 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38626 /* If this bit is set to 1, then it indicates that tx flow. */
38627 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38628 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \
38629 HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX
38631 * TCAM type of the resource, defined globally in the
38632 * hwrm_tf_resc_type enum.
38635 /* Number of TCAM index pairs to be swapped for the device. */
38639 /* TCAM index pairs to be swapped for the device. */
38640 uint16_t idx_pairs[48];
38643 /* hwrm_tf_tcam_move_output (size:128b/16B) */
38644 struct hwrm_tf_tcam_move_output {
38645 /* The specific error status for the command. */
38646 uint16_t error_code;
38647 /* The HWRM command request type. */
38649 /* The sequence ID from the original command. */
38651 /* The length of the response data in number of bytes. */
38654 uint8_t unused0[7];
38656 * This field is used in Output records to indicate that the
38657 * output is completely written to RAM. This field should be
38658 * read as '1' to indicate that the output has been
38659 * completely written. When writing a command completion or
38660 * response to an internal processor, the order of writes has
38661 * to be such that this field is written last.
38666 /*********************
38667 * hwrm_tf_tcam_free *
38668 *********************/
38671 /* hwrm_tf_tcam_free_input (size:1024b/128B) */
38672 struct hwrm_tf_tcam_free_input {
38673 /* The HWRM command request type. */
38676 * The completion ring to send the completion event on. This should
38677 * be the NQ ID returned from the `nq_alloc` HWRM command.
38679 uint16_t cmpl_ring;
38681 * The sequence ID is used by the driver for tracking multiple
38682 * commands. This ID is treated as opaque data by the firmware and
38683 * the value is returned in the `hwrm_resp_hdr` upon completion.
38687 * The target ID of the command:
38688 * * 0x0-0xFFF8 - The function ID
38689 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38690 * * 0xFFFD - Reserved for user-space HWRM interface
38693 uint16_t target_id;
38695 * A physical address pointer pointing to a host buffer that the
38696 * command's response data will be written. This can be either a host
38697 * physical address (HPA) or a guest physical address (GPA) and must
38698 * point to a physically contiguous block of memory.
38700 uint64_t resp_addr;
38701 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38702 uint32_t fw_session_id;
38703 /* Control flags. */
38705 /* Indicates the flow direction. */
38706 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
38707 /* If this bit set to 0, then it indicates rx flow. */
38708 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38709 /* If this bit is set to 1, then it indicates that tx flow. */
38710 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38711 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \
38712 HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX
38714 * TCAM type of the resource, defined globally in the
38715 * hwrm_tf_resc_type enum.
38718 /* Number of TCAM index to be deleted for the device. */
38722 /* TCAM index list to be deleted for the device. */
38723 uint16_t idx_list[48];
38726 /* hwrm_tf_tcam_free_output (size:128b/16B) */
38727 struct hwrm_tf_tcam_free_output {
38728 /* The specific error status for the command. */
38729 uint16_t error_code;
38730 /* The HWRM command request type. */
38732 /* The sequence ID from the original command. */
38734 /* The length of the response data in number of bytes. */
38737 uint8_t unused0[7];
38739 * This field is used in Output records to indicate that the
38740 * output is completely written to RAM. This field should be
38741 * read as '1' to indicate that the output has been
38742 * completely written. When writing a command completion or
38743 * response to an internal processor, the order of writes has
38744 * to be such that this field is written last.
38749 /**************************
38750 * hwrm_tf_global_cfg_set *
38751 **************************/
38754 /* hwrm_tf_global_cfg_set_input (size:448b/56B) */
38755 struct hwrm_tf_global_cfg_set_input {
38756 /* The HWRM command request type. */
38759 * The completion ring to send the completion event on. This should
38760 * be the NQ ID returned from the `nq_alloc` HWRM command.
38762 uint16_t cmpl_ring;
38764 * The sequence ID is used by the driver for tracking multiple
38765 * commands. This ID is treated as opaque data by the firmware and
38766 * the value is returned in the `hwrm_resp_hdr` upon completion.
38770 * The target ID of the command:
38771 * * 0x0-0xFFF8 - The function ID
38772 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38773 * * 0xFFFD - Reserved for user-space HWRM interface
38776 uint16_t target_id;
38778 * A physical address pointer pointing to a host buffer that the
38779 * command's response data will be written. This can be either a host
38780 * physical address (HPA) or a guest physical address (GPA) and must
38781 * point to a physically contiguous block of memory.
38783 uint64_t resp_addr;
38784 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38785 uint32_t fw_session_id;
38786 /* Control flags. */
38788 /* Indicates the flow direction. */
38789 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
38790 /* If this bit set to 0, then it indicates rx flow. */
38791 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38792 /* If this bit is set to 1, then it indicates that tx flow. */
38793 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38794 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_LAST \
38795 HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX
38796 /* Global Cfg type */
38798 /* Offset of the type */
38800 /* Size of the data to set in bytes */
38803 uint8_t unused0[6];
38808 /* hwrm_tf_global_cfg_set_output (size:128b/16B) */
38809 struct hwrm_tf_global_cfg_set_output {
38810 /* The specific error status for the command. */
38811 uint16_t error_code;
38812 /* The HWRM command request type. */
38814 /* The sequence ID from the original command. */
38816 /* The length of the response data in number of bytes. */
38819 uint8_t unused0[7];
38821 * This field is used in Output records to indicate that the
38822 * output is completely written to RAM. This field should be
38823 * read as '1' to indicate that the output has been
38824 * completely written. When writing a command completion or
38825 * response to an internal processor, the order of writes has
38826 * to be such that this field is written last.
38831 /**************************
38832 * hwrm_tf_global_cfg_get *
38833 **************************/
38836 /* hwrm_tf_global_cfg_get_input (size:320b/40B) */
38837 struct hwrm_tf_global_cfg_get_input {
38838 /* The HWRM command request type. */
38841 * The completion ring to send the completion event on. This should
38842 * be the NQ ID returned from the `nq_alloc` HWRM command.
38844 uint16_t cmpl_ring;
38846 * The sequence ID is used by the driver for tracking multiple
38847 * commands. This ID is treated as opaque data by the firmware and
38848 * the value is returned in the `hwrm_resp_hdr` upon completion.
38852 * The target ID of the command:
38853 * * 0x0-0xFFF8 - The function ID
38854 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38855 * * 0xFFFD - Reserved for user-space HWRM interface
38858 uint16_t target_id;
38860 * A physical address pointer pointing to a host buffer that the
38861 * command's response data will be written. This can be either a host
38862 * physical address (HPA) or a guest physical address (GPA) and must
38863 * point to a physically contiguous block of memory.
38865 uint64_t resp_addr;
38866 /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */
38867 uint32_t fw_session_id;
38868 /* Control flags. */
38870 /* Indicates the flow direction. */
38871 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
38872 /* If this bit set to 0, then it indicates rx flow. */
38873 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
38874 /* If this bit is set to 1, then it indicates that tx flow. */
38875 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
38876 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_LAST \
38877 HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX
38878 /* Global Cfg type */
38880 /* Offset of the type */
38882 /* Size of the data to set in bytes */
38885 uint8_t unused0[6];
38888 /* hwrm_tf_global_cfg_get_output (size:256b/32B) */
38889 struct hwrm_tf_global_cfg_get_output {
38890 /* The specific error status for the command. */
38891 uint16_t error_code;
38892 /* The HWRM command request type. */
38894 /* The sequence ID from the original command. */
38896 /* The length of the response data in number of bytes. */
38898 /* Size of the data read in bytes */
38901 uint8_t unused0[6];
38906 /******************************
38907 * hwrm_tunnel_dst_port_query *
38908 ******************************/
38911 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
38912 struct hwrm_tunnel_dst_port_query_input {
38913 /* The HWRM command request type. */
38916 * The completion ring to send the completion event on. This should
38917 * be the NQ ID returned from the `nq_alloc` HWRM command.
38919 uint16_t cmpl_ring;
38921 * The sequence ID is used by the driver for tracking multiple
38922 * commands. This ID is treated as opaque data by the firmware and
38923 * the value is returned in the `hwrm_resp_hdr` upon completion.
38927 * The target ID of the command:
38928 * * 0x0-0xFFF8 - The function ID
38929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38930 * * 0xFFFD - Reserved for user-space HWRM interface
38933 uint16_t target_id;
38935 * A physical address pointer pointing to a host buffer that the
38936 * command's response data will be written. This can be either a host
38937 * physical address (HPA) or a guest physical address (GPA) and must
38938 * point to a physically contiguous block of memory.
38940 uint64_t resp_addr;
38942 uint8_t tunnel_type;
38943 /* Virtual eXtensible Local Area Network (VXLAN) */
38944 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
38946 /* Generic Network Virtualization Encapsulation (Geneve) */
38947 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
38949 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
38950 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
38952 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
38953 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
38955 /* Use fixed layer 2 ether type of 0xFFFF */
38956 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
38958 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
38959 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
38961 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
38962 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
38963 uint8_t unused_0[7];
38966 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
38967 struct hwrm_tunnel_dst_port_query_output {
38968 /* The specific error status for the command. */
38969 uint16_t error_code;
38970 /* The HWRM command request type. */
38972 /* The sequence ID from the original command. */
38974 /* The length of the response data in number of bytes. */
38977 * This field represents the identifier of L4 destination port
38978 * used for the given tunnel type. This field is valid for
38979 * specific tunnel types that use layer 4 (e.g. UDP)
38980 * transports for tunneling.
38982 uint16_t tunnel_dst_port_id;
38984 * This field represents the value of L4 destination port
38985 * identified by tunnel_dst_port_id. This field is valid for
38986 * specific tunnel types that use layer 4 (e.g. UDP)
38987 * transports for tunneling.
38988 * This field is in network byte order.
38990 * A value of 0 means that the destination port is not
38993 uint16_t tunnel_dst_port_val;
38994 uint8_t unused_0[3];
38996 * This field is used in Output records to indicate that the output
38997 * is completely written to RAM. This field should be read as '1'
38998 * to indicate that the output has been completely written.
38999 * When writing a command completion or response to an internal processor,
39000 * the order of writes has to be such that this field is written last.
39005 /******************************
39006 * hwrm_tunnel_dst_port_alloc *
39007 ******************************/
39010 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
39011 struct hwrm_tunnel_dst_port_alloc_input {
39012 /* The HWRM command request type. */
39015 * The completion ring to send the completion event on. This should
39016 * be the NQ ID returned from the `nq_alloc` HWRM command.
39018 uint16_t cmpl_ring;
39020 * The sequence ID is used by the driver for tracking multiple
39021 * commands. This ID is treated as opaque data by the firmware and
39022 * the value is returned in the `hwrm_resp_hdr` upon completion.
39026 * The target ID of the command:
39027 * * 0x0-0xFFF8 - The function ID
39028 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39029 * * 0xFFFD - Reserved for user-space HWRM interface
39032 uint16_t target_id;
39034 * A physical address pointer pointing to a host buffer that the
39035 * command's response data will be written. This can be either a host
39036 * physical address (HPA) or a guest physical address (GPA) and must
39037 * point to a physically contiguous block of memory.
39039 uint64_t resp_addr;
39041 uint8_t tunnel_type;
39042 /* Virtual eXtensible Local Area Network (VXLAN) */
39043 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
39045 /* Generic Network Virtualization Encapsulation (Geneve) */
39046 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
39048 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39049 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39051 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39052 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39054 /* Use fixed layer 2 ether type of 0xFFFF */
39055 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
39057 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39058 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39060 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
39061 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39064 * This field represents the value of L4 destination port used
39065 * for the given tunnel type. This field is valid for
39066 * specific tunnel types that use layer 4 (e.g. UDP)
39067 * transports for tunneling.
39069 * This field is in network byte order.
39071 * A value of 0 shall fail the command.
39073 uint16_t tunnel_dst_port_val;
39074 uint8_t unused_1[4];
39077 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
39078 struct hwrm_tunnel_dst_port_alloc_output {
39079 /* The specific error status for the command. */
39080 uint16_t error_code;
39081 /* The HWRM command request type. */
39083 /* The sequence ID from the original command. */
39085 /* The length of the response data in number of bytes. */
39088 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39089 * types that has l4 destination port parameters.
39091 uint16_t tunnel_dst_port_id;
39092 uint8_t unused_0[5];
39094 * This field is used in Output records to indicate that the output
39095 * is completely written to RAM. This field should be read as '1'
39096 * to indicate that the output has been completely written.
39097 * When writing a command completion or response to an internal processor,
39098 * the order of writes has to be such that this field is written last.
39103 /*****************************
39104 * hwrm_tunnel_dst_port_free *
39105 *****************************/
39108 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
39109 struct hwrm_tunnel_dst_port_free_input {
39110 /* The HWRM command request type. */
39113 * The completion ring to send the completion event on. This should
39114 * be the NQ ID returned from the `nq_alloc` HWRM command.
39116 uint16_t cmpl_ring;
39118 * The sequence ID is used by the driver for tracking multiple
39119 * commands. This ID is treated as opaque data by the firmware and
39120 * the value is returned in the `hwrm_resp_hdr` upon completion.
39124 * The target ID of the command:
39125 * * 0x0-0xFFF8 - The function ID
39126 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39127 * * 0xFFFD - Reserved for user-space HWRM interface
39130 uint16_t target_id;
39132 * A physical address pointer pointing to a host buffer that the
39133 * command's response data will be written. This can be either a host
39134 * physical address (HPA) or a guest physical address (GPA) and must
39135 * point to a physically contiguous block of memory.
39137 uint64_t resp_addr;
39139 uint8_t tunnel_type;
39140 /* Virtual eXtensible Local Area Network (VXLAN) */
39141 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
39143 /* Generic Network Virtualization Encapsulation (Geneve) */
39144 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
39146 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
39147 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
39149 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
39150 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
39152 /* Use fixed layer 2 ether type of 0xFFFF */
39153 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
39155 /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
39156 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
39158 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
39159 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
39162 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
39163 * types that has l4 destination port parameters.
39165 uint16_t tunnel_dst_port_id;
39166 uint8_t unused_1[4];
39169 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
39170 struct hwrm_tunnel_dst_port_free_output {
39171 /* The specific error status for the command. */
39172 uint16_t error_code;
39173 /* The HWRM command request type. */
39175 /* The sequence ID from the original command. */
39177 /* The length of the response data in number of bytes. */
39179 uint8_t unused_1[7];
39181 * This field is used in Output records to indicate that the output
39182 * is completely written to RAM. This field should be read as '1'
39183 * to indicate that the output has been completely written.
39184 * When writing a command completion or response to an internal processor,
39185 * the order of writes has to be such that this field is written last.
39190 /* Periodic statistics context DMA to host. */
39191 /* ctx_hw_stats (size:1280b/160B) */
39192 struct ctx_hw_stats {
39193 /* Number of received unicast packets */
39194 uint64_t rx_ucast_pkts;
39195 /* Number of received multicast packets */
39196 uint64_t rx_mcast_pkts;
39197 /* Number of received broadcast packets */
39198 uint64_t rx_bcast_pkts;
39199 /* Number of discarded packets on receive path */
39200 uint64_t rx_discard_pkts;
39201 /* Number of packets on receive path with error */
39202 uint64_t rx_error_pkts;
39203 /* Number of received bytes for unicast traffic */
39204 uint64_t rx_ucast_bytes;
39205 /* Number of received bytes for multicast traffic */
39206 uint64_t rx_mcast_bytes;
39207 /* Number of received bytes for broadcast traffic */
39208 uint64_t rx_bcast_bytes;
39209 /* Number of transmitted unicast packets */
39210 uint64_t tx_ucast_pkts;
39211 /* Number of transmitted multicast packets */
39212 uint64_t tx_mcast_pkts;
39213 /* Number of transmitted broadcast packets */
39214 uint64_t tx_bcast_pkts;
39215 /* Number of packets on transmit path with error */
39216 uint64_t tx_error_pkts;
39217 /* Number of discarded packets on transmit path */
39218 uint64_t tx_discard_pkts;
39219 /* Number of transmitted bytes for unicast traffic */
39220 uint64_t tx_ucast_bytes;
39221 /* Number of transmitted bytes for multicast traffic */
39222 uint64_t tx_mcast_bytes;
39223 /* Number of transmitted bytes for broadcast traffic */
39224 uint64_t tx_bcast_bytes;
39225 /* Number of TPA packets */
39227 /* Number of TPA bytes */
39228 uint64_t tpa_bytes;
39229 /* Number of TPA events */
39230 uint64_t tpa_events;
39231 /* Number of TPA aborts */
39232 uint64_t tpa_aborts;
39236 * Extended periodic statistics context DMA to host. On cards that
39237 * support TPA v2, additional TPA related stats exist and can be retrieved
39238 * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.
39240 /* ctx_hw_stats_ext (size:1344b/168B) */
39241 struct ctx_hw_stats_ext {
39242 /* Number of received unicast packets */
39243 uint64_t rx_ucast_pkts;
39244 /* Number of received multicast packets */
39245 uint64_t rx_mcast_pkts;
39246 /* Number of received broadcast packets */
39247 uint64_t rx_bcast_pkts;
39248 /* Number of discarded packets on receive path */
39249 uint64_t rx_discard_pkts;
39250 /* Number of packets on receive path with error */
39251 uint64_t rx_error_pkts;
39252 /* Number of received bytes for unicast traffic */
39253 uint64_t rx_ucast_bytes;
39254 /* Number of received bytes for multicast traffic */
39255 uint64_t rx_mcast_bytes;
39256 /* Number of received bytes for broadcast traffic */
39257 uint64_t rx_bcast_bytes;
39258 /* Number of transmitted unicast packets */
39259 uint64_t tx_ucast_pkts;
39260 /* Number of transmitted multicast packets */
39261 uint64_t tx_mcast_pkts;
39262 /* Number of transmitted broadcast packets */
39263 uint64_t tx_bcast_pkts;
39264 /* Number of packets on transmit path with error */
39265 uint64_t tx_error_pkts;
39266 /* Number of discarded packets on transmit path */
39267 uint64_t tx_discard_pkts;
39268 /* Number of transmitted bytes for unicast traffic */
39269 uint64_t tx_ucast_bytes;
39270 /* Number of transmitted bytes for multicast traffic */
39271 uint64_t tx_mcast_bytes;
39272 /* Number of transmitted bytes for broadcast traffic */
39273 uint64_t tx_bcast_bytes;
39274 /* Number of TPA eligible packets */
39275 uint64_t rx_tpa_eligible_pkt;
39276 /* Number of TPA eligible bytes */
39277 uint64_t rx_tpa_eligible_bytes;
39278 /* Number of TPA packets */
39279 uint64_t rx_tpa_pkt;
39280 /* Number of TPA bytes */
39281 uint64_t rx_tpa_bytes;
39282 /* Number of TPA errors */
39283 uint64_t rx_tpa_errors;
39286 /* Periodic Engine statistics context DMA to host. */
39287 /* ctx_eng_stats (size:512b/64B) */
39288 struct ctx_eng_stats {
39290 * Count of data bytes into the Engine.
39291 * This includes any user supplied prefix,
39292 * but does not include any predefined
39295 uint64_t eng_bytes_in;
39296 /* Count of data bytes out of the Engine. */
39297 uint64_t eng_bytes_out;
39299 * Count, in 4-byte (dword) units, of bytes
39300 * that are input as auxiliary data.
39301 * This includes the aux_cmd data.
39303 uint64_t aux_bytes_in;
39305 * Count, in 4-byte (dword) units, of bytes
39306 * that are output as auxiliary data.
39307 * This count is the buffer space for aux_data
39308 * output provided in the RQE, not the actual
39311 uint64_t aux_bytes_out;
39312 /* Count of number of commands executed. */
39315 * Count of number of error commands.
39316 * These are the commands with a
39317 * non-zero status value.
39319 uint64_t error_commands;
39321 * Compression/Encryption Engine usage,
39322 * the unit is count of clock cycles
39324 uint64_t cce_engine_usage;
39326 * De-Compression/De-cryption Engine usage,
39327 * the unit is count of clock cycles
39329 uint64_t cdd_engine_usage;
39332 /***********************
39333 * hwrm_stat_ctx_alloc *
39334 ***********************/
39337 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
39338 struct hwrm_stat_ctx_alloc_input {
39339 /* The HWRM command request type. */
39342 * The completion ring to send the completion event on. This should
39343 * be the NQ ID returned from the `nq_alloc` HWRM command.
39345 uint16_t cmpl_ring;
39347 * The sequence ID is used by the driver for tracking multiple
39348 * commands. This ID is treated as opaque data by the firmware and
39349 * the value is returned in the `hwrm_resp_hdr` upon completion.
39353 * The target ID of the command:
39354 * * 0x0-0xFFF8 - The function ID
39355 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39356 * * 0xFFFD - Reserved for user-space HWRM interface
39359 uint16_t target_id;
39361 * A physical address pointer pointing to a host buffer that the
39362 * command's response data will be written. This can be either a host
39363 * physical address (HPA) or a guest physical address (GPA) and must
39364 * point to a physically contiguous block of memory.
39366 uint64_t resp_addr;
39368 * This is the address for statistic block.
39369 * > For new versions of the chip, this address should be 128B
39372 uint64_t stats_dma_addr;
39374 * The statistic block update period in ms.
39375 * e.g. 250ms, 500ms, 750ms, 1000ms.
39376 * If update_period_ms is 0, then the stats update
39377 * shall be never done and the DMA address shall not be used.
39378 * In this case, the stat block can only be read by
39379 * hwrm_stat_ctx_query command.
39380 * On Ethernet/L2 based devices:
39381 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
39382 * ctx_hw_stats_ext is used for DMA,
39384 * ctx_hw_stats is used for DMA.
39386 uint32_t update_period_ms;
39388 * This field is used to specify statistics context specific
39389 * configuration flags.
39391 uint8_t stat_ctx_flags;
39393 * When this bit is set to '1', the statistics context shall be
39394 * allocated for RoCE traffic only. In this case, traffic other
39395 * than offloaded RoCE traffic shall not be included in this
39396 * statistic context.
39397 * When this bit is set to '0', the statistics context shall be
39398 * used for network traffic or engine traffic.
39400 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
39403 * This is the size of the structure (ctx_hw_stats or
39404 * ctx_hw_stats_ext) that the driver has allocated to be used
39405 * for the periodic DMA updates.
39407 uint16_t stats_dma_length;
39410 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
39411 struct hwrm_stat_ctx_alloc_output {
39412 /* The specific error status for the command. */
39413 uint16_t error_code;
39414 /* The HWRM command request type. */
39416 /* The sequence ID from the original command. */
39418 /* The length of the response data in number of bytes. */
39420 /* This is the statistics context ID value. */
39421 uint32_t stat_ctx_id;
39422 uint8_t unused_0[3];
39424 * This field is used in Output records to indicate that the output
39425 * is completely written to RAM. This field should be read as '1'
39426 * to indicate that the output has been completely written.
39427 * When writing a command completion or response to an internal processor,
39428 * the order of writes has to be such that this field is written last.
39433 /**********************
39434 * hwrm_stat_ctx_free *
39435 **********************/
39438 /* hwrm_stat_ctx_free_input (size:192b/24B) */
39439 struct hwrm_stat_ctx_free_input {
39440 /* The HWRM command request type. */
39443 * The completion ring to send the completion event on. This should
39444 * be the NQ ID returned from the `nq_alloc` HWRM command.
39446 uint16_t cmpl_ring;
39448 * The sequence ID is used by the driver for tracking multiple
39449 * commands. This ID is treated as opaque data by the firmware and
39450 * the value is returned in the `hwrm_resp_hdr` upon completion.
39454 * The target ID of the command:
39455 * * 0x0-0xFFF8 - The function ID
39456 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39457 * * 0xFFFD - Reserved for user-space HWRM interface
39460 uint16_t target_id;
39462 * A physical address pointer pointing to a host buffer that the
39463 * command's response data will be written. This can be either a host
39464 * physical address (HPA) or a guest physical address (GPA) and must
39465 * point to a physically contiguous block of memory.
39467 uint64_t resp_addr;
39468 /* ID of the statistics context that is being queried. */
39469 uint32_t stat_ctx_id;
39470 uint8_t unused_0[4];
39473 /* hwrm_stat_ctx_free_output (size:128b/16B) */
39474 struct hwrm_stat_ctx_free_output {
39475 /* The specific error status for the command. */
39476 uint16_t error_code;
39477 /* The HWRM command request type. */
39479 /* The sequence ID from the original command. */
39481 /* The length of the response data in number of bytes. */
39483 /* This is the statistics context ID value. */
39484 uint32_t stat_ctx_id;
39485 uint8_t unused_0[3];
39487 * This field is used in Output records to indicate that the output
39488 * is completely written to RAM. This field should be read as '1'
39489 * to indicate that the output has been completely written.
39490 * When writing a command completion or response to an internal processor,
39491 * the order of writes has to be such that this field is written last.
39496 /***********************
39497 * hwrm_stat_ctx_query *
39498 ***********************/
39501 /* hwrm_stat_ctx_query_input (size:192b/24B) */
39502 struct hwrm_stat_ctx_query_input {
39503 /* The HWRM command request type. */
39506 * The completion ring to send the completion event on. This should
39507 * be the NQ ID returned from the `nq_alloc` HWRM command.
39509 uint16_t cmpl_ring;
39511 * The sequence ID is used by the driver for tracking multiple
39512 * commands. This ID is treated as opaque data by the firmware and
39513 * the value is returned in the `hwrm_resp_hdr` upon completion.
39517 * The target ID of the command:
39518 * * 0x0-0xFFF8 - The function ID
39519 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39520 * * 0xFFFD - Reserved for user-space HWRM interface
39523 uint16_t target_id;
39525 * A physical address pointer pointing to a host buffer that the
39526 * command's response data will be written. This can be either a host
39527 * physical address (HPA) or a guest physical address (GPA) and must
39528 * point to a physically contiguous block of memory.
39530 uint64_t resp_addr;
39531 /* ID of the statistics context that is being queried. */
39532 uint32_t stat_ctx_id;
39535 * This bit is set to 1 when request is for a counter mask,
39536 * representing the width of each of the stats counters, rather
39537 * than counters themselves.
39539 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
39540 uint8_t unused_0[3];
39543 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
39544 struct hwrm_stat_ctx_query_output {
39545 /* The specific error status for the command. */
39546 uint16_t error_code;
39547 /* The HWRM command request type. */
39549 /* The sequence ID from the original command. */
39551 /* The length of the response data in number of bytes. */
39553 /* Number of transmitted unicast packets */
39554 uint64_t tx_ucast_pkts;
39555 /* Number of transmitted multicast packets */
39556 uint64_t tx_mcast_pkts;
39557 /* Number of transmitted broadcast packets */
39558 uint64_t tx_bcast_pkts;
39559 /* Number of transmitted packets with error */
39560 uint64_t tx_err_pkts;
39561 /* Number of dropped packets on transmit path */
39562 uint64_t tx_drop_pkts;
39563 /* Number of transmitted bytes for unicast traffic */
39564 uint64_t tx_ucast_bytes;
39565 /* Number of transmitted bytes for multicast traffic */
39566 uint64_t tx_mcast_bytes;
39567 /* Number of transmitted bytes for broadcast traffic */
39568 uint64_t tx_bcast_bytes;
39569 /* Number of received unicast packets */
39570 uint64_t rx_ucast_pkts;
39571 /* Number of received multicast packets */
39572 uint64_t rx_mcast_pkts;
39573 /* Number of received broadcast packets */
39574 uint64_t rx_bcast_pkts;
39575 /* Number of received packets with error */
39576 uint64_t rx_err_pkts;
39577 /* Number of dropped packets on receive path */
39578 uint64_t rx_drop_pkts;
39579 /* Number of received bytes for unicast traffic */
39580 uint64_t rx_ucast_bytes;
39581 /* Number of received bytes for multicast traffic */
39582 uint64_t rx_mcast_bytes;
39583 /* Number of received bytes for broadcast traffic */
39584 uint64_t rx_bcast_bytes;
39585 /* Number of aggregated unicast packets */
39586 uint64_t rx_agg_pkts;
39587 /* Number of aggregated unicast bytes */
39588 uint64_t rx_agg_bytes;
39589 /* Number of aggregation events */
39590 uint64_t rx_agg_events;
39591 /* Number of aborted aggregations */
39592 uint64_t rx_agg_aborts;
39593 uint8_t unused_0[7];
39595 * This field is used in Output records to indicate that the output
39596 * is completely written to RAM. This field should be read as '1'
39597 * to indicate that the output has been completely written.
39598 * When writing a command completion or response to an internal processor,
39599 * the order of writes has to be such that this field is written last.
39604 /***************************
39605 * hwrm_stat_ext_ctx_query *
39606 ***************************/
39609 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */
39610 struct hwrm_stat_ext_ctx_query_input {
39611 /* The HWRM command request type. */
39614 * The completion ring to send the completion event on. This should
39615 * be the NQ ID returned from the `nq_alloc` HWRM command.
39617 uint16_t cmpl_ring;
39619 * The sequence ID is used by the driver for tracking multiple
39620 * commands. This ID is treated as opaque data by the firmware and
39621 * the value is returned in the `hwrm_resp_hdr` upon completion.
39625 * The target ID of the command:
39626 * * 0x0-0xFFF8 - The function ID
39627 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39628 * * 0xFFFD - Reserved for user-space HWRM interface
39631 uint16_t target_id;
39633 * A physical address pointer pointing to a host buffer that the
39634 * command's response data will be written. This can be either a host
39635 * physical address (HPA) or a guest physical address (GPA) and must
39636 * point to a physically contiguous block of memory.
39638 uint64_t resp_addr;
39639 /* ID of the extended statistics context that is being queried. */
39640 uint32_t stat_ctx_id;
39643 * This bit is set to 1 when request is for a counter mask,
39644 * representing the width of each of the stats counters, rather
39645 * than counters themselves.
39647 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \
39649 uint8_t unused_0[3];
39652 /* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */
39653 struct hwrm_stat_ext_ctx_query_output {
39654 /* The specific error status for the command. */
39655 uint16_t error_code;
39656 /* The HWRM command request type. */
39658 /* The sequence ID from the original command. */
39660 /* The length of the response data in number of bytes. */
39662 /* Number of received unicast packets */
39663 uint64_t rx_ucast_pkts;
39664 /* Number of received multicast packets */
39665 uint64_t rx_mcast_pkts;
39666 /* Number of received broadcast packets */
39667 uint64_t rx_bcast_pkts;
39668 /* Number of discarded packets on receive path */
39669 uint64_t rx_discard_pkts;
39670 /* Number of packets on receive path with error */
39671 uint64_t rx_error_pkts;
39672 /* Number of received bytes for unicast traffic */
39673 uint64_t rx_ucast_bytes;
39674 /* Number of received bytes for multicast traffic */
39675 uint64_t rx_mcast_bytes;
39676 /* Number of received bytes for broadcast traffic */
39677 uint64_t rx_bcast_bytes;
39678 /* Number of transmitted unicast packets */
39679 uint64_t tx_ucast_pkts;
39680 /* Number of transmitted multicast packets */
39681 uint64_t tx_mcast_pkts;
39682 /* Number of transmitted broadcast packets */
39683 uint64_t tx_bcast_pkts;
39684 /* Number of packets on transmit path with error */
39685 uint64_t tx_error_pkts;
39686 /* Number of discarded packets on transmit path */
39687 uint64_t tx_discard_pkts;
39688 /* Number of transmitted bytes for unicast traffic */
39689 uint64_t tx_ucast_bytes;
39690 /* Number of transmitted bytes for multicast traffic */
39691 uint64_t tx_mcast_bytes;
39692 /* Number of transmitted bytes for broadcast traffic */
39693 uint64_t tx_bcast_bytes;
39694 /* Number of TPA eligible packets */
39695 uint64_t rx_tpa_eligible_pkt;
39696 /* Number of TPA eligible bytes */
39697 uint64_t rx_tpa_eligible_bytes;
39698 /* Number of TPA packets */
39699 uint64_t rx_tpa_pkt;
39700 /* Number of TPA bytes */
39701 uint64_t rx_tpa_bytes;
39702 /* Number of TPA errors */
39703 uint64_t rx_tpa_errors;
39704 uint8_t unused_0[7];
39706 * This field is used in Output records to indicate that the output
39707 * is completely written to RAM. This field should be read as '1'
39708 * to indicate that the output has been completely written.
39709 * When writing a command completion or response to an internal processor,
39710 * the order of writes has to be such that this field is written last.
39715 /***************************
39716 * hwrm_stat_ctx_eng_query *
39717 ***************************/
39720 /* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
39721 struct hwrm_stat_ctx_eng_query_input {
39722 /* The HWRM command request type. */
39725 * The completion ring to send the completion event on. This should
39726 * be the NQ ID returned from the `nq_alloc` HWRM command.
39728 uint16_t cmpl_ring;
39730 * The sequence ID is used by the driver for tracking multiple
39731 * commands. This ID is treated as opaque data by the firmware and
39732 * the value is returned in the `hwrm_resp_hdr` upon completion.
39736 * The target ID of the command:
39737 * * 0x0-0xFFF8 - The function ID
39738 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39739 * * 0xFFFD - Reserved for user-space HWRM interface
39742 uint16_t target_id;
39744 * A physical address pointer pointing to a host buffer that the
39745 * command's response data will be written. This can be either a host
39746 * physical address (HPA) or a guest physical address (GPA) and must
39747 * point to a physically contiguous block of memory.
39749 uint64_t resp_addr;
39750 /* ID of the statistics context that is being queried. */
39751 uint32_t stat_ctx_id;
39752 uint8_t unused_0[4];
39755 /* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
39756 struct hwrm_stat_ctx_eng_query_output {
39757 /* The specific error status for the command. */
39758 uint16_t error_code;
39759 /* The HWRM command request type. */
39761 /* The sequence ID from the original command. */
39763 /* The length of the response data in number of bytes. */
39766 * Count of data bytes into the Engine.
39767 * This includes any user supplied prefix,
39768 * but does not include any predefined
39771 uint64_t eng_bytes_in;
39772 /* Count of data bytes out of the Engine. */
39773 uint64_t eng_bytes_out;
39775 * Count, in 4-byte (dword) units, of bytes
39776 * that are input as auxiliary data.
39777 * This includes the aux_cmd data.
39779 uint64_t aux_bytes_in;
39781 * Count, in 4-byte (dword) units, of bytes
39782 * that are output as auxiliary data.
39783 * This count is the buffer space for aux_data
39784 * output provided in the RQE, not the actual
39787 uint64_t aux_bytes_out;
39788 /* Count of number of commands executed. */
39791 * Count of number of error commands.
39792 * These are the commands with a
39793 * non-zero status value.
39795 uint64_t error_commands;
39797 * Compression/Encryption Engine usage,
39798 * the unit is count of clock cycles
39800 uint64_t cce_engine_usage;
39802 * De-Compression/De-cryption Engine usage,
39803 * the unit is count of clock cycles
39805 uint64_t cdd_engine_usage;
39806 uint8_t unused_0[7];
39808 * This field is used in Output records to indicate that the output
39809 * is completely written to RAM. This field should be read as '1'
39810 * to indicate that the output has been completely written.
39811 * When writing a command completion or response to an internal processor,
39812 * the order of writes has to be such that this field is written last.
39817 /***************************
39818 * hwrm_stat_ctx_clr_stats *
39819 ***************************/
39822 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
39823 struct hwrm_stat_ctx_clr_stats_input {
39824 /* The HWRM command request type. */
39827 * The completion ring to send the completion event on. This should
39828 * be the NQ ID returned from the `nq_alloc` HWRM command.
39830 uint16_t cmpl_ring;
39832 * The sequence ID is used by the driver for tracking multiple
39833 * commands. This ID is treated as opaque data by the firmware and
39834 * the value is returned in the `hwrm_resp_hdr` upon completion.
39838 * The target ID of the command:
39839 * * 0x0-0xFFF8 - The function ID
39840 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39841 * * 0xFFFD - Reserved for user-space HWRM interface
39844 uint16_t target_id;
39846 * A physical address pointer pointing to a host buffer that the
39847 * command's response data will be written. This can be either a host
39848 * physical address (HPA) or a guest physical address (GPA) and must
39849 * point to a physically contiguous block of memory.
39851 uint64_t resp_addr;
39852 /* ID of the statistics context that is being queried. */
39853 uint32_t stat_ctx_id;
39854 uint8_t unused_0[4];
39857 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
39858 struct hwrm_stat_ctx_clr_stats_output {
39859 /* The specific error status for the command. */
39860 uint16_t error_code;
39861 /* The HWRM command request type. */
39863 /* The sequence ID from the original command. */
39865 /* The length of the response data in number of bytes. */
39867 uint8_t unused_0[7];
39869 * This field is used in Output records to indicate that the output
39870 * is completely written to RAM. This field should be read as '1'
39871 * to indicate that the output has been completely written.
39872 * When writing a command completion or response to an internal processor,
39873 * the order of writes has to be such that this field is written last.
39878 /********************
39879 * hwrm_pcie_qstats *
39880 ********************/
39883 /* hwrm_pcie_qstats_input (size:256b/32B) */
39884 struct hwrm_pcie_qstats_input {
39885 /* The HWRM command request type. */
39888 * The completion ring to send the completion event on. This should
39889 * be the NQ ID returned from the `nq_alloc` HWRM command.
39891 uint16_t cmpl_ring;
39893 * The sequence ID is used by the driver for tracking multiple
39894 * commands. This ID is treated as opaque data by the firmware and
39895 * the value is returned in the `hwrm_resp_hdr` upon completion.
39899 * The target ID of the command:
39900 * * 0x0-0xFFF8 - The function ID
39901 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39902 * * 0xFFFD - Reserved for user-space HWRM interface
39905 uint16_t target_id;
39907 * A physical address pointer pointing to a host buffer that the
39908 * command's response data will be written. This can be either a host
39909 * physical address (HPA) or a guest physical address (GPA) and must
39910 * point to a physically contiguous block of memory.
39912 uint64_t resp_addr;
39914 * The size of PCIe statistics block in bytes.
39915 * Firmware will DMA the PCIe statistics to
39916 * the host with this field size in the response.
39918 uint16_t pcie_stat_size;
39919 uint8_t unused_0[6];
39921 * This is the host address where
39922 * PCIe statistics will be stored
39924 uint64_t pcie_stat_host_addr;
39927 /* hwrm_pcie_qstats_output (size:128b/16B) */
39928 struct hwrm_pcie_qstats_output {
39929 /* The specific error status for the command. */
39930 uint16_t error_code;
39931 /* The HWRM command request type. */
39933 /* The sequence ID from the original command. */
39935 /* The length of the response data in number of bytes. */
39937 /* The size of PCIe statistics block in bytes. */
39938 uint16_t pcie_stat_size;
39939 uint8_t unused_0[5];
39941 * This field is used in Output records to indicate that the output
39942 * is completely written to RAM. This field should be read as '1'
39943 * to indicate that the output has been completely written.
39944 * When writing a command completion or response to an internal processor,
39945 * the order of writes has to be such that this field is written last.
39950 /* PCIe Statistics Formats */
39951 /* pcie_ctx_hw_stats (size:768b/96B) */
39952 struct pcie_ctx_hw_stats {
39953 /* Number of physical layer receiver errors */
39954 uint64_t pcie_pl_signal_integrity;
39955 /* Number of DLLP CRC errors detected by Data Link Layer */
39956 uint64_t pcie_dl_signal_integrity;
39958 * Number of TLP LCRC and sequence number errors detected
39959 * by Data Link Layer
39961 uint64_t pcie_tl_signal_integrity;
39962 /* Number of times LTSSM entered Recovery state */
39963 uint64_t pcie_link_integrity;
39964 /* Report number of TLP bits that have been transmitted in Mbps */
39965 uint64_t pcie_tx_traffic_rate;
39966 /* Report number of TLP bits that have been received in Mbps */
39967 uint64_t pcie_rx_traffic_rate;
39968 /* Number of DLLP bytes that have been transmitted */
39969 uint64_t pcie_tx_dllp_statistics;
39970 /* Number of DLLP bytes that have been received */
39971 uint64_t pcie_rx_dllp_statistics;
39973 * Number of times spent in each phase of gen3
39976 uint64_t pcie_equalization_time;
39977 /* Records the last 16 transitions of the LTSSM */
39978 uint32_t pcie_ltssm_histogram[4];
39980 * Record the last 8 reasons on why LTSSM transitioned
39983 uint64_t pcie_recovery_histogram;
39986 /**********************
39987 * hwrm_exec_fwd_resp *
39988 **********************/
39991 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
39992 struct hwrm_exec_fwd_resp_input {
39993 /* The HWRM command request type. */
39996 * The completion ring to send the completion event on. This should
39997 * be the NQ ID returned from the `nq_alloc` HWRM command.
39999 uint16_t cmpl_ring;
40001 * The sequence ID is used by the driver for tracking multiple
40002 * commands. This ID is treated as opaque data by the firmware and
40003 * the value is returned in the `hwrm_resp_hdr` upon completion.
40007 * The target ID of the command:
40008 * * 0x0-0xFFF8 - The function ID
40009 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40010 * * 0xFFFD - Reserved for user-space HWRM interface
40013 uint16_t target_id;
40015 * A physical address pointer pointing to a host buffer that the
40016 * command's response data will be written. This can be either a host
40017 * physical address (HPA) or a guest physical address (GPA) and must
40018 * point to a physically contiguous block of memory.
40020 uint64_t resp_addr;
40022 * This is an encapsulated request. This request should
40023 * be executed by the HWRM and the response should be
40024 * provided in the response buffer inside the encapsulated
40027 uint32_t encap_request[26];
40029 * This value indicates the target id of the response to
40030 * the encapsulated request.
40031 * 0x0 - 0xFFF8 - Used for function ids
40032 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40035 uint16_t encap_resp_target_id;
40036 uint8_t unused_0[6];
40039 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
40040 struct hwrm_exec_fwd_resp_output {
40041 /* The specific error status for the command. */
40042 uint16_t error_code;
40043 /* The HWRM command request type. */
40045 /* The sequence ID from the original command. */
40047 /* The length of the response data in number of bytes. */
40049 uint8_t unused_0[7];
40051 * This field is used in Output records to indicate that the output
40052 * is completely written to RAM. This field should be read as '1'
40053 * to indicate that the output has been completely written.
40054 * When writing a command completion or response to an internal processor,
40055 * the order of writes has to be such that this field is written last.
40060 /************************
40061 * hwrm_reject_fwd_resp *
40062 ************************/
40065 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
40066 struct hwrm_reject_fwd_resp_input {
40067 /* The HWRM command request type. */
40070 * The completion ring to send the completion event on. This should
40071 * be the NQ ID returned from the `nq_alloc` HWRM command.
40073 uint16_t cmpl_ring;
40075 * The sequence ID is used by the driver for tracking multiple
40076 * commands. This ID is treated as opaque data by the firmware and
40077 * the value is returned in the `hwrm_resp_hdr` upon completion.
40081 * The target ID of the command:
40082 * * 0x0-0xFFF8 - The function ID
40083 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40084 * * 0xFFFD - Reserved for user-space HWRM interface
40087 uint16_t target_id;
40089 * A physical address pointer pointing to a host buffer that the
40090 * command's response data will be written. This can be either a host
40091 * physical address (HPA) or a guest physical address (GPA) and must
40092 * point to a physically contiguous block of memory.
40094 uint64_t resp_addr;
40096 * This is an encapsulated request. This request should
40097 * be rejected by the HWRM and the error response should be
40098 * provided in the response buffer inside the encapsulated
40101 uint32_t encap_request[26];
40103 * This value indicates the target id of the response to
40104 * the encapsulated request.
40105 * 0x0 - 0xFFF8 - Used for function ids
40106 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40109 uint16_t encap_resp_target_id;
40110 uint8_t unused_0[6];
40113 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
40114 struct hwrm_reject_fwd_resp_output {
40115 /* The specific error status for the command. */
40116 uint16_t error_code;
40117 /* The HWRM command request type. */
40119 /* The sequence ID from the original command. */
40121 /* The length of the response data in number of bytes. */
40123 uint8_t unused_0[7];
40125 * This field is used in Output records to indicate that the output
40126 * is completely written to RAM. This field should be read as '1'
40127 * to indicate that the output has been completely written.
40128 * When writing a command completion or response to an internal processor,
40129 * the order of writes has to be such that this field is written last.
40139 /* hwrm_fwd_resp_input (size:1024b/128B) */
40140 struct hwrm_fwd_resp_input {
40141 /* The HWRM command request type. */
40144 * The completion ring to send the completion event on. This should
40145 * be the NQ ID returned from the `nq_alloc` HWRM command.
40147 uint16_t cmpl_ring;
40149 * The sequence ID is used by the driver for tracking multiple
40150 * commands. This ID is treated as opaque data by the firmware and
40151 * the value is returned in the `hwrm_resp_hdr` upon completion.
40155 * The target ID of the command:
40156 * * 0x0-0xFFF8 - The function ID
40157 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40158 * * 0xFFFD - Reserved for user-space HWRM interface
40161 uint16_t target_id;
40163 * A physical address pointer pointing to a host buffer that the
40164 * command's response data will be written. This can be either a host
40165 * physical address (HPA) or a guest physical address (GPA) and must
40166 * point to a physically contiguous block of memory.
40168 uint64_t resp_addr;
40170 * This value indicates the target id of the encapsulated
40172 * 0x0 - 0xFFF8 - Used for function ids
40173 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40176 uint16_t encap_resp_target_id;
40178 * This value indicates the completion ring the encapsulated
40179 * response will be optionally completed on. If the value is
40180 * -1, then no CR completion shall be generated for the
40181 * encapsulated response. Any other value must be a
40182 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
40183 * is provided, then a CR completion shall be generated for
40184 * the encapsulated response.
40186 uint16_t encap_resp_cmpl_ring;
40187 /* This field indicates the length of encapsulated response. */
40188 uint16_t encap_resp_len;
40192 * This is the host address where the encapsulated response
40194 * This area must be 16B aligned and must be cleared to zero
40195 * before the original request is made.
40197 uint64_t encap_resp_addr;
40198 /* This is an encapsulated response. */
40199 uint32_t encap_resp[24];
40202 /* hwrm_fwd_resp_output (size:128b/16B) */
40203 struct hwrm_fwd_resp_output {
40204 /* The specific error status for the command. */
40205 uint16_t error_code;
40206 /* The HWRM command request type. */
40208 /* The sequence ID from the original command. */
40210 /* The length of the response data in number of bytes. */
40212 uint8_t unused_0[7];
40214 * This field is used in Output records to indicate that the output
40215 * is completely written to RAM. This field should be read as '1'
40216 * to indicate that the output has been completely written.
40217 * When writing a command completion or response to an internal processor,
40218 * the order of writes has to be such that this field is written last.
40223 /*****************************
40224 * hwrm_fwd_async_event_cmpl *
40225 *****************************/
40228 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
40229 struct hwrm_fwd_async_event_cmpl_input {
40230 /* The HWRM command request type. */
40233 * The completion ring to send the completion event on. This should
40234 * be the NQ ID returned from the `nq_alloc` HWRM command.
40236 uint16_t cmpl_ring;
40238 * The sequence ID is used by the driver for tracking multiple
40239 * commands. This ID is treated as opaque data by the firmware and
40240 * the value is returned in the `hwrm_resp_hdr` upon completion.
40244 * The target ID of the command:
40245 * * 0x0-0xFFF8 - The function ID
40246 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40247 * * 0xFFFD - Reserved for user-space HWRM interface
40250 uint16_t target_id;
40252 * A physical address pointer pointing to a host buffer that the
40253 * command's response data will be written. This can be either a host
40254 * physical address (HPA) or a guest physical address (GPA) and must
40255 * point to a physically contiguous block of memory.
40257 uint64_t resp_addr;
40259 * This value indicates the target id of the encapsulated
40260 * asynchronous event.
40261 * 0x0 - 0xFFF8 - Used for function ids
40262 * 0xFFF8 - 0xFFFE - Reserved for internal processors
40263 * 0xFFFF - Broadcast to all children VFs (only applicable when
40264 * a PF is the requester)
40266 uint16_t encap_async_event_target_id;
40267 uint8_t unused_0[6];
40268 /* This is an encapsulated asynchronous event completion. */
40269 uint32_t encap_async_event_cmpl[4];
40272 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
40273 struct hwrm_fwd_async_event_cmpl_output {
40274 /* The specific error status for the command. */
40275 uint16_t error_code;
40276 /* The HWRM command request type. */
40278 /* The sequence ID from the original command. */
40280 /* The length of the response data in number of bytes. */
40282 uint8_t unused_0[7];
40284 * This field is used in Output records to indicate that the output
40285 * is completely written to RAM. This field should be read as '1'
40286 * to indicate that the output has been completely written.
40287 * When writing a command completion or response to an internal processor,
40288 * the order of writes has to be such that this field is written last.
40293 /**************************
40294 * hwrm_nvm_raw_write_blk *
40295 **************************/
40298 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
40299 struct hwrm_nvm_raw_write_blk_input {
40300 /* The HWRM command request type. */
40303 * The completion ring to send the completion event on. This should
40304 * be the NQ ID returned from the `nq_alloc` HWRM command.
40306 uint16_t cmpl_ring;
40308 * The sequence ID is used by the driver for tracking multiple
40309 * commands. This ID is treated as opaque data by the firmware and
40310 * the value is returned in the `hwrm_resp_hdr` upon completion.
40314 * The target ID of the command:
40315 * * 0x0-0xFFF8 - The function ID
40316 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40317 * * 0xFFFD - Reserved for user-space HWRM interface
40320 uint16_t target_id;
40322 * A physical address pointer pointing to a host buffer that the
40323 * command's response data will be written. This can be either a host
40324 * physical address (HPA) or a guest physical address (GPA) and must
40325 * point to a physically contiguous block of memory.
40327 uint64_t resp_addr;
40329 * 64-bit Host Source Address.
40330 * This is the location of the source data to be written.
40332 uint64_t host_src_addr;
40334 * 32-bit Destination Address.
40335 * This is the NVRAM byte-offset where the source data will be written to.
40337 uint32_t dest_addr;
40338 /* Length of data to be written, in bytes. */
40342 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
40343 struct hwrm_nvm_raw_write_blk_output {
40344 /* The specific error status for the command. */
40345 uint16_t error_code;
40346 /* The HWRM command request type. */
40348 /* The sequence ID from the original command. */
40350 /* The length of the response data in number of bytes. */
40352 uint8_t unused_0[7];
40354 * This field is used in Output records to indicate that the output
40355 * is completely written to RAM. This field should be read as '1'
40356 * to indicate that the output has been completely written.
40357 * When writing a command completion or response to an internal processor,
40358 * the order of writes has to be such that this field is written last.
40368 /* hwrm_nvm_read_input (size:320b/40B) */
40369 struct hwrm_nvm_read_input {
40370 /* The HWRM command request type. */
40373 * The completion ring to send the completion event on. This should
40374 * be the NQ ID returned from the `nq_alloc` HWRM command.
40376 uint16_t cmpl_ring;
40378 * The sequence ID is used by the driver for tracking multiple
40379 * commands. This ID is treated as opaque data by the firmware and
40380 * the value is returned in the `hwrm_resp_hdr` upon completion.
40384 * The target ID of the command:
40385 * * 0x0-0xFFF8 - The function ID
40386 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40387 * * 0xFFFD - Reserved for user-space HWRM interface
40390 uint16_t target_id;
40392 * A physical address pointer pointing to a host buffer that the
40393 * command's response data will be written. This can be either a host
40394 * physical address (HPA) or a guest physical address (GPA) and must
40395 * point to a physically contiguous block of memory.
40397 uint64_t resp_addr;
40399 * 64-bit Host Destination Address.
40400 * This is the host address where the data will be written to.
40402 uint64_t host_dest_addr;
40403 /* The 0-based index of the directory entry. */
40405 uint8_t unused_0[2];
40406 /* The NVRAM byte-offset to read from. */
40408 /* The length of the data to be read, in bytes. */
40410 uint8_t unused_1[4];
40413 /* hwrm_nvm_read_output (size:128b/16B) */
40414 struct hwrm_nvm_read_output {
40415 /* The specific error status for the command. */
40416 uint16_t error_code;
40417 /* The HWRM command request type. */
40419 /* The sequence ID from the original command. */
40421 /* The length of the response data in number of bytes. */
40423 uint8_t unused_0[7];
40425 * This field is used in Output records to indicate that the output
40426 * is completely written to RAM. This field should be read as '1'
40427 * to indicate that the output has been completely written.
40428 * When writing a command completion or response to an internal processor,
40429 * the order of writes has to be such that this field is written last.
40434 /*********************
40435 * hwrm_nvm_raw_dump *
40436 *********************/
40439 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
40440 struct hwrm_nvm_raw_dump_input {
40441 /* The HWRM command request type. */
40444 * The completion ring to send the completion event on. This should
40445 * be the NQ ID returned from the `nq_alloc` HWRM command.
40447 uint16_t cmpl_ring;
40449 * The sequence ID is used by the driver for tracking multiple
40450 * commands. This ID is treated as opaque data by the firmware and
40451 * the value is returned in the `hwrm_resp_hdr` upon completion.
40455 * The target ID of the command:
40456 * * 0x0-0xFFF8 - The function ID
40457 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40458 * * 0xFFFD - Reserved for user-space HWRM interface
40461 uint16_t target_id;
40463 * A physical address pointer pointing to a host buffer that the
40464 * command's response data will be written. This can be either a host
40465 * physical address (HPA) or a guest physical address (GPA) and must
40466 * point to a physically contiguous block of memory.
40468 uint64_t resp_addr;
40470 * 64-bit Host Destination Address.
40471 * This is the host address where the data will be written to.
40473 uint64_t host_dest_addr;
40474 /* 32-bit NVRAM byte-offset to read from. */
40476 /* Total length of NVRAM contents to be read, in bytes. */
40480 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
40481 struct hwrm_nvm_raw_dump_output {
40482 /* The specific error status for the command. */
40483 uint16_t error_code;
40484 /* The HWRM command request type. */
40486 /* The sequence ID from the original command. */
40488 /* The length of the response data in number of bytes. */
40490 uint8_t unused_0[7];
40492 * This field is used in Output records to indicate that the output
40493 * is completely written to RAM. This field should be read as '1'
40494 * to indicate that the output has been completely written.
40495 * When writing a command completion or response to an internal processor,
40496 * the order of writes has to be such that this field is written last.
40501 /****************************
40502 * hwrm_nvm_get_dir_entries *
40503 ****************************/
40506 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
40507 struct hwrm_nvm_get_dir_entries_input {
40508 /* The HWRM command request type. */
40511 * The completion ring to send the completion event on. This should
40512 * be the NQ ID returned from the `nq_alloc` HWRM command.
40514 uint16_t cmpl_ring;
40516 * The sequence ID is used by the driver for tracking multiple
40517 * commands. This ID is treated as opaque data by the firmware and
40518 * the value is returned in the `hwrm_resp_hdr` upon completion.
40522 * The target ID of the command:
40523 * * 0x0-0xFFF8 - The function ID
40524 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40525 * * 0xFFFD - Reserved for user-space HWRM interface
40528 uint16_t target_id;
40530 * A physical address pointer pointing to a host buffer that the
40531 * command's response data will be written. This can be either a host
40532 * physical address (HPA) or a guest physical address (GPA) and must
40533 * point to a physically contiguous block of memory.
40535 uint64_t resp_addr;
40537 * 64-bit Host Destination Address.
40538 * This is the host address where the directory will be written.
40540 uint64_t host_dest_addr;
40543 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
40544 struct hwrm_nvm_get_dir_entries_output {
40545 /* The specific error status for the command. */
40546 uint16_t error_code;
40547 /* The HWRM command request type. */
40549 /* The sequence ID from the original command. */
40551 /* The length of the response data in number of bytes. */
40553 uint8_t unused_0[7];
40555 * This field is used in Output records to indicate that the output
40556 * is completely written to RAM. This field should be read as '1'
40557 * to indicate that the output has been completely written.
40558 * When writing a command completion or response to an internal processor,
40559 * the order of writes has to be such that this field is written last.
40564 /*************************
40565 * hwrm_nvm_get_dir_info *
40566 *************************/
40569 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
40570 struct hwrm_nvm_get_dir_info_input {
40571 /* The HWRM command request type. */
40574 * The completion ring to send the completion event on. This should
40575 * be the NQ ID returned from the `nq_alloc` HWRM command.
40577 uint16_t cmpl_ring;
40579 * The sequence ID is used by the driver for tracking multiple
40580 * commands. This ID is treated as opaque data by the firmware and
40581 * the value is returned in the `hwrm_resp_hdr` upon completion.
40585 * The target ID of the command:
40586 * * 0x0-0xFFF8 - The function ID
40587 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40588 * * 0xFFFD - Reserved for user-space HWRM interface
40591 uint16_t target_id;
40593 * A physical address pointer pointing to a host buffer that the
40594 * command's response data will be written. This can be either a host
40595 * physical address (HPA) or a guest physical address (GPA) and must
40596 * point to a physically contiguous block of memory.
40598 uint64_t resp_addr;
40601 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
40602 struct hwrm_nvm_get_dir_info_output {
40603 /* The specific error status for the command. */
40604 uint16_t error_code;
40605 /* The HWRM command request type. */
40607 /* The sequence ID from the original command. */
40609 /* The length of the response data in number of bytes. */
40611 /* Number of directory entries in the directory. */
40613 /* Size of each directory entry, in bytes. */
40614 uint32_t entry_length;
40615 uint8_t unused_0[7];
40617 * This field is used in Output records to indicate that the output
40618 * is completely written to RAM. This field should be read as '1'
40619 * to indicate that the output has been completely written.
40620 * When writing a command completion or response to an internal processor,
40621 * the order of writes has to be such that this field is written last.
40626 /******************
40628 ******************/
40631 /* hwrm_nvm_write_input (size:384b/48B) */
40632 struct hwrm_nvm_write_input {
40633 /* The HWRM command request type. */
40636 * The completion ring to send the completion event on. This should
40637 * be the NQ ID returned from the `nq_alloc` HWRM command.
40639 uint16_t cmpl_ring;
40641 * The sequence ID is used by the driver for tracking multiple
40642 * commands. This ID is treated as opaque data by the firmware and
40643 * the value is returned in the `hwrm_resp_hdr` upon completion.
40647 * The target ID of the command:
40648 * * 0x0-0xFFF8 - The function ID
40649 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40650 * * 0xFFFD - Reserved for user-space HWRM interface
40653 uint16_t target_id;
40655 * A physical address pointer pointing to a host buffer that the
40656 * command's response data will be written. This can be either a host
40657 * physical address (HPA) or a guest physical address (GPA) and must
40658 * point to a physically contiguous block of memory.
40660 uint64_t resp_addr;
40662 * 64-bit Host Source Address.
40663 * This is where the source data is.
40665 uint64_t host_src_addr;
40666 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
40669 * Directory ordinal.
40670 * The 0-based instance of the combined Directory Entry Type and Extension.
40672 uint16_t dir_ordinal;
40673 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
40675 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
40678 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
40679 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
40681 uint32_t dir_data_length;
40686 * When this bit is '1', the original active image
40687 * will not be removed. TBD: what purpose is this?
40689 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
40692 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
40693 * If this value is less than the specified data length, it will be ignored.
40694 * The response will contain the actual allocated item length, which may be greater than the requested item length.
40695 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate
40696 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
40698 uint32_t dir_item_length;
40702 /* hwrm_nvm_write_output (size:128b/16B) */
40703 struct hwrm_nvm_write_output {
40704 /* The specific error status for the command. */
40705 uint16_t error_code;
40706 /* The HWRM command request type. */
40708 /* The sequence ID from the original command. */
40710 /* The length of the response data in number of bytes. */
40713 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
40714 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
40716 uint32_t dir_item_length;
40717 /* The directory index of the created or modified item. */
40721 * This field is used in Output records to indicate that the output
40722 * is completely written to RAM. This field should be read as '1'
40723 * to indicate that the output has been completely written.
40724 * When writing a command completion or response to an internal processor,
40725 * the order of writes has to be such that this field is written last.
40730 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
40731 struct hwrm_nvm_write_cmd_err {
40733 * command specific error codes that goes to
40734 * the cmd_err field in Common HWRM Error Response.
40737 /* Unknown error */
40738 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
40739 /* Unable to complete operation due to fragmentation */
40740 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
40741 /* nvm is completely full. */
40742 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
40743 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
40744 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
40745 uint8_t unused_0[7];
40748 /*******************
40749 * hwrm_nvm_modify *
40750 *******************/
40753 /* hwrm_nvm_modify_input (size:320b/40B) */
40754 struct hwrm_nvm_modify_input {
40755 /* The HWRM command request type. */
40758 * The completion ring to send the completion event on. This should
40759 * be the NQ ID returned from the `nq_alloc` HWRM command.
40761 uint16_t cmpl_ring;
40763 * The sequence ID is used by the driver for tracking multiple
40764 * commands. This ID is treated as opaque data by the firmware and
40765 * the value is returned in the `hwrm_resp_hdr` upon completion.
40769 * The target ID of the command:
40770 * * 0x0-0xFFF8 - The function ID
40771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40772 * * 0xFFFD - Reserved for user-space HWRM interface
40775 uint16_t target_id;
40777 * A physical address pointer pointing to a host buffer that the
40778 * command's response data will be written. This can be either a host
40779 * physical address (HPA) or a guest physical address (GPA) and must
40780 * point to a physically contiguous block of memory.
40782 uint64_t resp_addr;
40784 * 64-bit Host Source Address.
40785 * This is where the modified data is.
40787 uint64_t host_src_addr;
40788 /* 16-bit directory entry index. */
40792 * This flag indicates the sender wants to modify a continuous NVRAM
40793 * area using a batch of this HWRM requests. The offset of a request
40794 * must be continuous to the end of previous request's. Firmware does
40795 * not update the directory entry until receiving the last request,
40796 * which is indicated by the batch_last flag.
40797 * This flag is set usually when a sender does not have a block of
40798 * memory that is big enough to hold the entire NVRAM data for send
40801 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
40803 * This flag can be used only when the batch_mode flag is set.
40804 * It indicates this request is the last of batch requests.
40806 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
40807 /* 32-bit NVRAM byte-offset to modify content from. */
40810 * Length of data to be modified, in bytes. The length shall
40814 uint8_t unused_1[4];
40817 /* hwrm_nvm_modify_output (size:128b/16B) */
40818 struct hwrm_nvm_modify_output {
40819 /* The specific error status for the command. */
40820 uint16_t error_code;
40821 /* The HWRM command request type. */
40823 /* The sequence ID from the original command. */
40825 /* The length of the response data in number of bytes. */
40827 uint8_t unused_0[7];
40829 * This field is used in Output records to indicate that the output
40830 * is completely written to RAM. This field should be read as '1'
40831 * to indicate that the output has been completely written.
40832 * When writing a command completion or response to an internal processor,
40833 * the order of writes has to be such that this field is written last.
40838 /***************************
40839 * hwrm_nvm_find_dir_entry *
40840 ***************************/
40843 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
40844 struct hwrm_nvm_find_dir_entry_input {
40845 /* The HWRM command request type. */
40848 * The completion ring to send the completion event on. This should
40849 * be the NQ ID returned from the `nq_alloc` HWRM command.
40851 uint16_t cmpl_ring;
40853 * The sequence ID is used by the driver for tracking multiple
40854 * commands. This ID is treated as opaque data by the firmware and
40855 * the value is returned in the `hwrm_resp_hdr` upon completion.
40859 * The target ID of the command:
40860 * * 0x0-0xFFF8 - The function ID
40861 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40862 * * 0xFFFD - Reserved for user-space HWRM interface
40865 uint16_t target_id;
40867 * A physical address pointer pointing to a host buffer that the
40868 * command's response data will be written. This can be either a host
40869 * physical address (HPA) or a guest physical address (GPA) and must
40870 * point to a physically contiguous block of memory.
40872 uint64_t resp_addr;
40875 * This bit must be '1' for the dir_idx_valid field to be
40878 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
40880 /* Directory Entry Index */
40882 /* Directory Entry (Image) Type */
40885 * Directory ordinal.
40886 * The instance of this Directory Type
40888 uint16_t dir_ordinal;
40889 /* The Directory Entry Extension flags. */
40891 /* This value indicates the search option using dir_ordinal. */
40892 uint8_t opt_ordinal;
40893 /* This value indicates the search option using dir_ordinal. */
40894 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
40895 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
40896 /* Equal to specified ordinal value. */
40897 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
40898 /* Greater than or equal to specified ordinal value */
40899 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
40900 /* Greater than specified ordinal value */
40901 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
40902 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
40903 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
40904 uint8_t unused_0[3];
40907 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
40908 struct hwrm_nvm_find_dir_entry_output {
40909 /* The specific error status for the command. */
40910 uint16_t error_code;
40911 /* The HWRM command request type. */
40913 /* The sequence ID from the original command. */
40915 /* The length of the response data in number of bytes. */
40917 /* Allocated NVRAM for this directory entry, in bytes. */
40918 uint32_t dir_item_length;
40919 /* Size of the stored data for this directory entry, in bytes. */
40920 uint32_t dir_data_length;
40922 * Firmware version.
40923 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
40926 /* Directory ordinal. */
40927 uint16_t dir_ordinal;
40928 /* Directory Entry Index */
40930 uint8_t unused_0[7];
40932 * This field is used in Output records to indicate that the output
40933 * is completely written to RAM. This field should be read as '1'
40934 * to indicate that the output has been completely written.
40935 * When writing a command completion or response to an internal processor,
40936 * the order of writes has to be such that this field is written last.
40941 /****************************
40942 * hwrm_nvm_erase_dir_entry *
40943 ****************************/
40946 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
40947 struct hwrm_nvm_erase_dir_entry_input {
40948 /* The HWRM command request type. */
40951 * The completion ring to send the completion event on. This should
40952 * be the NQ ID returned from the `nq_alloc` HWRM command.
40954 uint16_t cmpl_ring;
40956 * The sequence ID is used by the driver for tracking multiple
40957 * commands. This ID is treated as opaque data by the firmware and
40958 * the value is returned in the `hwrm_resp_hdr` upon completion.
40962 * The target ID of the command:
40963 * * 0x0-0xFFF8 - The function ID
40964 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40965 * * 0xFFFD - Reserved for user-space HWRM interface
40968 uint16_t target_id;
40970 * A physical address pointer pointing to a host buffer that the
40971 * command's response data will be written. This can be either a host
40972 * physical address (HPA) or a guest physical address (GPA) and must
40973 * point to a physically contiguous block of memory.
40975 uint64_t resp_addr;
40976 /* Directory Entry Index */
40978 uint8_t unused_0[6];
40981 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
40982 struct hwrm_nvm_erase_dir_entry_output {
40983 /* The specific error status for the command. */
40984 uint16_t error_code;
40985 /* The HWRM command request type. */
40987 /* The sequence ID from the original command. */
40989 /* The length of the response data in number of bytes. */
40991 uint8_t unused_0[7];
40993 * This field is used in Output records to indicate that the output
40994 * is completely written to RAM. This field should be read as '1'
40995 * to indicate that the output has been completely written.
40996 * When writing a command completion or response to an internal processor,
40997 * the order of writes has to be such that this field is written last.
41002 /*************************
41003 * hwrm_nvm_get_dev_info *
41004 *************************/
41007 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
41008 struct hwrm_nvm_get_dev_info_input {
41009 /* The HWRM command request type. */
41012 * The completion ring to send the completion event on. This should
41013 * be the NQ ID returned from the `nq_alloc` HWRM command.
41015 uint16_t cmpl_ring;
41017 * The sequence ID is used by the driver for tracking multiple
41018 * commands. This ID is treated as opaque data by the firmware and
41019 * the value is returned in the `hwrm_resp_hdr` upon completion.
41023 * The target ID of the command:
41024 * * 0x0-0xFFF8 - The function ID
41025 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41026 * * 0xFFFD - Reserved for user-space HWRM interface
41029 uint16_t target_id;
41031 * A physical address pointer pointing to a host buffer that the
41032 * command's response data will be written. This can be either a host
41033 * physical address (HPA) or a guest physical address (GPA) and must
41034 * point to a physically contiguous block of memory.
41036 uint64_t resp_addr;
41039 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
41040 struct hwrm_nvm_get_dev_info_output {
41041 /* The specific error status for the command. */
41042 uint16_t error_code;
41043 /* The HWRM command request type. */
41045 /* The sequence ID from the original command. */
41047 /* The length of the response data in number of bytes. */
41049 /* Manufacturer ID. */
41050 uint16_t manufacturer_id;
41052 uint16_t device_id;
41053 /* Sector size of the NVRAM device. */
41054 uint32_t sector_size;
41055 /* Total size, in bytes of the NVRAM device. */
41056 uint32_t nvram_size;
41057 uint32_t reserved_size;
41058 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
41059 uint32_t available_size;
41060 /* This field represents the major version of NVM cfg */
41061 uint8_t nvm_cfg_ver_maj;
41062 /* This field represents the minor version of NVM cfg */
41063 uint8_t nvm_cfg_ver_min;
41064 /* This field represents the update version of NVM cfg */
41065 uint8_t nvm_cfg_ver_upd;
41067 * This field is used in Output records to indicate that the output
41068 * is completely written to RAM. This field should be read as '1'
41069 * to indicate that the output has been completely written.
41070 * When writing a command completion or response to an internal processor,
41071 * the order of writes has to be such that this field is written last.
41076 /**************************
41077 * hwrm_nvm_mod_dir_entry *
41078 **************************/
41081 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
41082 struct hwrm_nvm_mod_dir_entry_input {
41083 /* The HWRM command request type. */
41086 * The completion ring to send the completion event on. This should
41087 * be the NQ ID returned from the `nq_alloc` HWRM command.
41089 uint16_t cmpl_ring;
41091 * The sequence ID is used by the driver for tracking multiple
41092 * commands. This ID is treated as opaque data by the firmware and
41093 * the value is returned in the `hwrm_resp_hdr` upon completion.
41097 * The target ID of the command:
41098 * * 0x0-0xFFF8 - The function ID
41099 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41100 * * 0xFFFD - Reserved for user-space HWRM interface
41103 uint16_t target_id;
41105 * A physical address pointer pointing to a host buffer that the
41106 * command's response data will be written. This can be either a host
41107 * physical address (HPA) or a guest physical address (GPA) and must
41108 * point to a physically contiguous block of memory.
41110 uint64_t resp_addr;
41113 * This bit must be '1' for the checksum field to be
41116 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
41117 /* Directory Entry Index */
41120 * Directory ordinal.
41121 * The (0-based) instance of this Directory Type.
41123 uint16_t dir_ordinal;
41124 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
41126 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
41129 * If valid, then this field updates the checksum
41130 * value of the content in the directory entry.
41135 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
41136 struct hwrm_nvm_mod_dir_entry_output {
41137 /* The specific error status for the command. */
41138 uint16_t error_code;
41139 /* The HWRM command request type. */
41141 /* The sequence ID from the original command. */
41143 /* The length of the response data in number of bytes. */
41145 uint8_t unused_0[7];
41147 * This field is used in Output records to indicate that the output
41148 * is completely written to RAM. This field should be read as '1'
41149 * to indicate that the output has been completely written.
41150 * When writing a command completion or response to an internal processor,
41151 * the order of writes has to be such that this field is written last.
41156 /**************************
41157 * hwrm_nvm_verify_update *
41158 **************************/
41161 /* hwrm_nvm_verify_update_input (size:192b/24B) */
41162 struct hwrm_nvm_verify_update_input {
41163 /* The HWRM command request type. */
41166 * The completion ring to send the completion event on. This should
41167 * be the NQ ID returned from the `nq_alloc` HWRM command.
41169 uint16_t cmpl_ring;
41171 * The sequence ID is used by the driver for tracking multiple
41172 * commands. This ID is treated as opaque data by the firmware and
41173 * the value is returned in the `hwrm_resp_hdr` upon completion.
41177 * The target ID of the command:
41178 * * 0x0-0xFFF8 - The function ID
41179 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41180 * * 0xFFFD - Reserved for user-space HWRM interface
41183 uint16_t target_id;
41185 * A physical address pointer pointing to a host buffer that the
41186 * command's response data will be written. This can be either a host
41187 * physical address (HPA) or a guest physical address (GPA) and must
41188 * point to a physically contiguous block of memory.
41190 uint64_t resp_addr;
41191 /* Directory Entry Type, to be verified. */
41194 * Directory ordinal.
41195 * The instance of the Directory Type to be verified.
41197 uint16_t dir_ordinal;
41199 * The Directory Entry Extension flags.
41200 * The "UPDATE" extension flag must be set in this value.
41201 * A corresponding directory entry with the same type and ordinal values but *without*
41202 * the "UPDATE" extension flag must also exist. The other flags of the extension must
41203 * be identical between the active and update entries.
41206 uint8_t unused_0[2];
41209 /* hwrm_nvm_verify_update_output (size:128b/16B) */
41210 struct hwrm_nvm_verify_update_output {
41211 /* The specific error status for the command. */
41212 uint16_t error_code;
41213 /* The HWRM command request type. */
41215 /* The sequence ID from the original command. */
41217 /* The length of the response data in number of bytes. */
41219 uint8_t unused_0[7];
41221 * This field is used in Output records to indicate that the output
41222 * is completely written to RAM. This field should be read as '1'
41223 * to indicate that the output has been completely written.
41224 * When writing a command completion or response to an internal processor,
41225 * the order of writes has to be such that this field is written last.
41230 /***************************
41231 * hwrm_nvm_install_update *
41232 ***************************/
41235 /* hwrm_nvm_install_update_input (size:192b/24B) */
41236 struct hwrm_nvm_install_update_input {
41237 /* The HWRM command request type. */
41240 * The completion ring to send the completion event on. This should
41241 * be the NQ ID returned from the `nq_alloc` HWRM command.
41243 uint16_t cmpl_ring;
41245 * The sequence ID is used by the driver for tracking multiple
41246 * commands. This ID is treated as opaque data by the firmware and
41247 * the value is returned in the `hwrm_resp_hdr` upon completion.
41251 * The target ID of the command:
41252 * * 0x0-0xFFF8 - The function ID
41253 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41254 * * 0xFFFD - Reserved for user-space HWRM interface
41257 uint16_t target_id;
41259 * A physical address pointer pointing to a host buffer that the
41260 * command's response data will be written. This can be either a host
41261 * physical address (HPA) or a guest physical address (GPA) and must
41262 * point to a physically contiguous block of memory.
41264 uint64_t resp_addr;
41266 * Installation type. If the value 3 through 0xffff is used,
41267 * only packaged items with that type value will be installed and
41268 * conditional installation directives for those packaged items
41269 * will be over-ridden (i.e. 'create' or 'replace' will be treated
41272 uint32_t install_type;
41274 * Perform a normal package installation. Conditional installation
41275 * directives (e.g. 'create' and 'replace') of packaged items
41276 * will be followed.
41278 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
41280 * Install all packaged items regardless of installation directive
41281 * (i.e. treat all packaged items as though they have an installation
41282 * directive of 'install').
41284 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
41285 UINT32_C(0xffffffff)
41286 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
41287 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
41289 /* If set to 1, then securely erase all unused locations in persistent storage. */
41290 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
41293 * If set to 1, then unspecified images, images not in the package file, will be safely deleted.
41294 * When combined with erase_unused_space then unspecified images will be securely erased.
41296 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
41299 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
41300 * Allow additional time for this command to complete if this bit is set to 1.
41302 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
41305 * If set to 1, FW will verify the package in the "UPDATE" NVM item
41306 * without installing it. This flag is for FW internal use only.
41307 * Users should not set this flag. The request will otherwise fail.
41309 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \
41311 uint8_t unused_0[2];
41314 /* hwrm_nvm_install_update_output (size:192b/24B) */
41315 struct hwrm_nvm_install_update_output {
41316 /* The specific error status for the command. */
41317 uint16_t error_code;
41318 /* The HWRM command request type. */
41320 /* The sequence ID from the original command. */
41322 /* The length of the response data in number of bytes. */
41325 * Bit-mask of successfully installed items.
41326 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
41327 * A value of 0 indicates that no items were successfully installed.
41329 uint64_t installed_items;
41330 /* result is 8 b */
41332 /* There was no problem with the package installation. */
41333 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
41334 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
41335 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
41336 /* problem_item is 8 b */
41337 uint8_t problem_item;
41338 /* There was no problem with any packaged items. */
41339 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
41341 /* There was a problem with the NVM package itself. */
41342 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
41344 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
41345 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
41346 /* reset_required is 8 b */
41347 uint8_t reset_required;
41349 * No reset is required for installed/updated firmware or
41350 * microcode to take effect.
41352 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
41355 * A PCIe reset (e.g. system reboot) is
41356 * required for newly installed/updated firmware or
41357 * microcode to take effect.
41359 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
41362 * A controller power reset (e.g. system power-cycle) is
41363 * required for newly installed/updated firmware or
41364 * microcode to take effect. Some newly installed/updated
41365 * firmware or microcode may still take effect upon the
41368 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
41370 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
41371 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
41372 uint8_t unused_0[4];
41374 * This field is used in Output records to indicate that the output
41375 * is completely written to RAM. This field should be read as '1'
41376 * to indicate that the output has been completely written.
41377 * When writing a command completion or response to an internal processor,
41378 * the order of writes has to be such that this field is written last.
41383 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
41384 struct hwrm_nvm_install_update_cmd_err {
41386 * command specific error codes that goes to
41387 * the cmd_err field in Common HWRM Error Response.
41390 /* Unknown error */
41391 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41392 /* Unable to complete operation due to fragmentation */
41393 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
41394 /* nvm is completely full. */
41395 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
41396 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
41397 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
41398 uint8_t unused_0[7];
41401 /******************
41403 ******************/
41406 /* hwrm_nvm_flush_input (size:128b/16B) */
41407 struct hwrm_nvm_flush_input {
41408 /* The HWRM command request type. */
41411 * The completion ring to send the completion event on. This should
41412 * be the NQ ID returned from the `nq_alloc` HWRM command.
41414 uint16_t cmpl_ring;
41416 * The sequence ID is used by the driver for tracking multiple
41417 * commands. This ID is treated as opaque data by the firmware and
41418 * the value is returned in the `hwrm_resp_hdr` upon completion.
41422 * The target ID of the command:
41423 * * 0x0-0xFFF8 - The function ID
41424 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41425 * * 0xFFFD - Reserved for user-space HWRM interface
41428 uint16_t target_id;
41430 * A physical address pointer pointing to a host buffer that the
41431 * command's response data will be written. This can be either a host
41432 * physical address (HPA) or a guest physical address (GPA) and must
41433 * point to a physically contiguous block of memory.
41435 uint64_t resp_addr;
41438 /* hwrm_nvm_flush_output (size:128b/16B) */
41439 struct hwrm_nvm_flush_output {
41440 /* The specific error status for the command. */
41441 uint16_t error_code;
41442 /* The HWRM command request type. */
41444 /* The sequence ID from the original command. */
41446 /* The length of the response data in number of bytes. */
41448 uint8_t unused_0[7];
41450 * This field is used in Output records to indicate that the output
41451 * is completely written to RAM. This field should be read as '1'
41452 * to indicate that the output has been completely written.
41453 * When writing a command completion or response to an internal processor,
41454 * the order of writes has to be such that this field is written last.
41459 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
41460 struct hwrm_nvm_flush_cmd_err {
41462 * command specific error codes that goes to
41463 * the cmd_err field in Common HWRM Error Response.
41466 /* Unknown error */
41467 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41468 /* flush could not be performed */
41469 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
41470 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
41471 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
41472 uint8_t unused_0[7];
41475 /*************************
41476 * hwrm_nvm_get_variable *
41477 *************************/
41480 /* hwrm_nvm_get_variable_input (size:320b/40B) */
41481 struct hwrm_nvm_get_variable_input {
41482 /* The HWRM command request type. */
41485 * The completion ring to send the completion event on. This should
41486 * be the NQ ID returned from the `nq_alloc` HWRM command.
41488 uint16_t cmpl_ring;
41490 * The sequence ID is used by the driver for tracking multiple
41491 * commands. This ID is treated as opaque data by the firmware and
41492 * the value is returned in the `hwrm_resp_hdr` upon completion.
41496 * The target ID of the command:
41497 * * 0x0-0xFFF8 - The function ID
41498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41499 * * 0xFFFD - Reserved for user-space HWRM interface
41502 uint16_t target_id;
41504 * A physical address pointer pointing to a host buffer that the
41505 * command's response data will be written. This can be either a host
41506 * physical address (HPA) or a guest physical address (GPA) and must
41507 * point to a physically contiguous block of memory.
41509 uint64_t resp_addr;
41511 * This is the host address where
41512 * nvm variable will be stored
41514 uint64_t dest_data_addr;
41515 /* size of data in bits */
41517 /* nvm cfg option number */
41518 uint16_t option_num;
41520 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
41522 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
41524 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
41525 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
41527 * Number of dimensions for this nvm configuration variable.
41528 * This value indicates how many of the indexN values to use.
41529 * A value of 0 means that none of the indexN values are valid.
41530 * A value of 1 requires at index0 is valued, a value of 2
41531 * requires that index0 and index1 are valid, and so forth
41533 uint16_t dimensions;
41534 /* index for the 1st dimensions */
41536 /* index for the 2nd dimensions */
41538 /* index for the 3rd dimensions */
41540 /* index for the 4th dimensions */
41544 * When this bit is set to 1, the factory default value will be returned,
41545 * 0 returns the operational value.
41547 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
41552 /* hwrm_nvm_get_variable_output (size:128b/16B) */
41553 struct hwrm_nvm_get_variable_output {
41554 /* The specific error status for the command. */
41555 uint16_t error_code;
41556 /* The HWRM command request type. */
41558 /* The sequence ID from the original command. */
41560 /* The length of the response data in number of bytes. */
41562 /* size of data of the actual variable retrieved in bits */
41565 * option_num is the option number for the data retrieved. It is possible in the
41566 * future that the option number returned would be different than requested. This
41567 * condition could occur if an option is deprecated and a new option id is defined
41568 * with similar characteristics, but has a slightly different definition. This
41569 * also makes it convenient for the caller to identify the variable result with
41570 * the option id from the response.
41572 uint16_t option_num;
41574 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
41576 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
41578 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
41579 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
41580 uint8_t unused_0[3];
41582 * This field is used in Output records to indicate that the output
41583 * is completely written to RAM. This field should be read as '1'
41584 * to indicate that the output has been completely written.
41585 * When writing a command completion or response to an internal processor,
41586 * the order of writes has to be such that this field is written last.
41591 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
41592 struct hwrm_nvm_get_variable_cmd_err {
41594 * command specific error codes that goes to
41595 * the cmd_err field in Common HWRM Error Response.
41598 /* Unknown error */
41599 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41600 /* variable does not exist */
41601 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
41602 /* configuration is corrupted and the variable cannot be saved */
41603 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
41604 /* length specified is too small */
41605 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
41606 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
41607 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
41608 uint8_t unused_0[7];
41611 /*************************
41612 * hwrm_nvm_set_variable *
41613 *************************/
41616 /* hwrm_nvm_set_variable_input (size:320b/40B) */
41617 struct hwrm_nvm_set_variable_input {
41618 /* The HWRM command request type. */
41621 * The completion ring to send the completion event on. This should
41622 * be the NQ ID returned from the `nq_alloc` HWRM command.
41624 uint16_t cmpl_ring;
41626 * The sequence ID is used by the driver for tracking multiple
41627 * commands. This ID is treated as opaque data by the firmware and
41628 * the value is returned in the `hwrm_resp_hdr` upon completion.
41632 * The target ID of the command:
41633 * * 0x0-0xFFF8 - The function ID
41634 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41635 * * 0xFFFD - Reserved for user-space HWRM interface
41638 uint16_t target_id;
41640 * A physical address pointer pointing to a host buffer that the
41641 * command's response data will be written. This can be either a host
41642 * physical address (HPA) or a guest physical address (GPA) and must
41643 * point to a physically contiguous block of memory.
41645 uint64_t resp_addr;
41647 * This is the host address where
41648 * nvm variable will be copied from
41650 uint64_t src_data_addr;
41651 /* size of data in bits */
41653 /* nvm cfg option number */
41654 uint16_t option_num;
41656 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
41658 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
41660 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
41661 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
41663 * Number of dimensions for this nvm configuration variable.
41664 * This value indicates how many of the indexN values to use.
41665 * A value of 0 means that none of the indexN values are valid.
41666 * A value of 1 requires at index0 is valued, a value of 2
41667 * requires that index0 and index1 are valid, and so forth
41669 uint16_t dimensions;
41670 /* index for the 1st dimensions */
41672 /* index for the 2nd dimensions */
41674 /* index for the 3rd dimensions */
41676 /* index for the 4th dimensions */
41679 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
41680 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
41682 /* encryption method */
41683 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
41685 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
41686 /* No encryption. */
41687 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
41688 (UINT32_C(0x0) << 1)
41689 /* one-way encryption. */
41690 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
41691 (UINT32_C(0x1) << 1)
41692 /* symmetric AES256 encryption. */
41693 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
41694 (UINT32_C(0x2) << 1)
41695 /* SHA1 digest appended to plaintext contents, for authentication */
41696 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
41697 (UINT32_C(0x3) << 1)
41698 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
41699 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
41700 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK \
41702 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_SFT 4
41703 /* When this bit is 1, update the factory default region */
41704 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT \
41709 /* hwrm_nvm_set_variable_output (size:128b/16B) */
41710 struct hwrm_nvm_set_variable_output {
41711 /* The specific error status for the command. */
41712 uint16_t error_code;
41713 /* The HWRM command request type. */
41715 /* The sequence ID from the original command. */
41717 /* The length of the response data in number of bytes. */
41719 uint8_t unused_0[7];
41721 * This field is used in Output records to indicate that the output
41722 * is completely written to RAM. This field should be read as '1'
41723 * to indicate that the output has been completely written.
41724 * When writing a command completion or response to an internal processor,
41725 * the order of writes has to be such that this field is written last.
41730 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
41731 struct hwrm_nvm_set_variable_cmd_err {
41733 * command specific error codes that goes to
41734 * the cmd_err field in Common HWRM Error Response.
41737 /* Unknown error */
41738 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41739 /* variable does not exist */
41740 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
41741 /* configuration is corrupted and the variable cannot be saved */
41742 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
41743 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
41744 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
41745 uint8_t unused_0[7];
41748 /****************************
41749 * hwrm_nvm_validate_option *
41750 ****************************/
41753 /* hwrm_nvm_validate_option_input (size:320b/40B) */
41754 struct hwrm_nvm_validate_option_input {
41755 /* The HWRM command request type. */
41758 * The completion ring to send the completion event on. This should
41759 * be the NQ ID returned from the `nq_alloc` HWRM command.
41761 uint16_t cmpl_ring;
41763 * The sequence ID is used by the driver for tracking multiple
41764 * commands. This ID is treated as opaque data by the firmware and
41765 * the value is returned in the `hwrm_resp_hdr` upon completion.
41769 * The target ID of the command:
41770 * * 0x0-0xFFF8 - The function ID
41771 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41772 * * 0xFFFD - Reserved for user-space HWRM interface
41775 uint16_t target_id;
41777 * A physical address pointer pointing to a host buffer that the
41778 * command's response data will be written. This can be either a host
41779 * physical address (HPA) or a guest physical address (GPA) and must
41780 * point to a physically contiguous block of memory.
41782 uint64_t resp_addr;
41784 * This is the host address where
41785 * nvm variable will be copied from
41787 uint64_t src_data_addr;
41788 /* size of data in bits */
41790 /* nvm cfg option number */
41791 uint16_t option_num;
41793 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
41796 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
41798 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
41799 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
41801 * Number of dimensions for this nvm configuration variable.
41802 * This value indicates how many of the indexN values to use.
41803 * A value of 0 means that none of the indexN values are valid.
41804 * A value of 1 requires at index0 is valued, a value of 2
41805 * requires that index0 and index1 are valid, and so forth
41807 uint16_t dimensions;
41808 /* index for the 1st dimensions */
41810 /* index for the 2nd dimensions */
41812 /* index for the 3rd dimensions */
41814 /* index for the 4th dimensions */
41816 uint8_t unused_0[2];
41819 /* hwrm_nvm_validate_option_output (size:128b/16B) */
41820 struct hwrm_nvm_validate_option_output {
41821 /* The specific error status for the command. */
41822 uint16_t error_code;
41823 /* The HWRM command request type. */
41825 /* The sequence ID from the original command. */
41827 /* The length of the response data in number of bytes. */
41830 /* indicates that the value provided for the option is not matching with the saved data. */
41831 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
41832 /* indicates that the value provided for the option is matching the saved data. */
41833 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
41834 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
41835 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
41836 uint8_t unused_0[6];
41838 * This field is used in Output records to indicate that the output
41839 * is completely written to RAM. This field should be read as '1'
41840 * to indicate that the output has been completely written.
41841 * When writing a command completion or response to an internal processor,
41842 * the order of writes has to be such that this field is written last.
41847 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
41848 struct hwrm_nvm_validate_option_cmd_err {
41850 * command specific error codes that goes to
41851 * the cmd_err field in Common HWRM Error Response.
41854 /* Unknown error */
41855 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41856 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
41857 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
41858 uint8_t unused_0[7];
41866 /* hwrm_oem_cmd_input (size:1024b/128B) */
41867 struct hwrm_oem_cmd_input {
41868 /* The HWRM command request type. */
41871 * The completion ring to send the completion event on. This should
41872 * be the NQ ID returned from the `nq_alloc` HWRM command.
41874 uint16_t cmpl_ring;
41876 * The sequence ID is used by the driver for tracking multiple
41877 * commands. This ID is treated as opaque data by the firmware and
41878 * the value is returned in the `hwrm_resp_hdr` upon completion.
41882 * The target ID of the command:
41883 * * 0x0-0xFFF8 - The function ID
41884 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41885 * * 0xFFFD - Reserved for user-space HWRM interface
41888 uint16_t target_id;
41890 * A physical address pointer pointing to a host buffer that the
41891 * command's response data will be written. This can be either a host
41892 * physical address (HPA) or a guest physical address (GPA) and must
41893 * point to a physically contiguous block of memory.
41895 uint64_t resp_addr;
41898 /* This field contains the vendor specific command data. */
41899 uint32_t oem_data[26];
41902 /* hwrm_oem_cmd_output (size:768b/96B) */
41903 struct hwrm_oem_cmd_output {
41904 /* The specific error status for the command. */
41905 uint16_t error_code;
41906 /* The HWRM command request type. */
41908 /* The sequence ID from the original command. */
41910 /* The length of the response data in number of bytes. */
41914 /* This field contains the vendor specific response data. */
41915 uint32_t oem_data[18];
41916 uint8_t unused_1[7];
41918 * This field is used in Output records to indicate that the output
41919 * is completely written to RAM. This field should be read as '1'
41920 * to indicate that the output has been completely written.
41921 * When writing a command completion or response to an internal processor,
41922 * the order of writes has to be such that this field is written last.
41929 ******************/
41932 /* hwrm_fw_reset_input (size:192b/24B) */
41933 struct hwrm_fw_reset_input {
41934 /* The HWRM command request type. */
41937 * The completion ring to send the completion event on. This should
41938 * be the NQ ID returned from the `nq_alloc` HWRM command.
41940 uint16_t cmpl_ring;
41942 * The sequence ID is used by the driver for tracking multiple
41943 * commands. This ID is treated as opaque data by the firmware and
41944 * the value is returned in the `hwrm_resp_hdr` upon completion.
41948 * The target ID of the command:
41949 * * 0x0-0xFFF8 - The function ID
41950 * * 0xFFF8-0xFFFE - Reserved for internal processors
41953 uint16_t target_id;
41955 * A physical address pointer pointing to a host buffer that the
41956 * command's response data will be written. This can be either a host
41957 * physical address (HPA) or a guest physical address (GPA) and must
41958 * point to a physically contiguous block of memory.
41960 uint64_t resp_addr;
41961 /* Type of embedded processor. */
41962 uint8_t embedded_proc_type;
41963 /* Boot Processor */
41964 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT \
41966 /* Management Processor */
41967 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT \
41969 /* Network control processor */
41970 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL \
41972 /* RoCE control processor */
41973 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE \
41976 * Host (in multi-host environment): This is only valid if requester is IPC.
41977 * Reinit host hardware resources and PCIe.
41979 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \
41981 /* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */
41982 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \
41984 /* Reset all blocks of the chip (including all processors) */
41985 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP \
41988 * Host (in multi-host environment): This is only valid if requester is IPC.
41989 * Reinit host hardware resources.
41991 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT \
41993 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_LAST \
41994 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT
41995 /* Type of self reset. */
41996 uint8_t selfrst_status;
41997 /* No Self Reset */
41998 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE \
42000 /* Self Reset as soon as possible to do so safely */
42001 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP \
42003 /* Self Reset on PCIe Reset */
42004 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST \
42006 /* Self Reset immediately after notification to all clients. */
42007 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42009 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_LAST \
42010 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42012 * Indicate which host is being reset. 0 means first host.
42013 * Only valid when embedded_proc_type is host in multihost
42019 * When this bit is '1', then the core firmware initiates
42020 * the reset only after graceful shut down of all registered instances.
42021 * If not, the device will continue with the existing firmware.
42023 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
42024 uint8_t unused_0[4];
42027 /* hwrm_fw_reset_output (size:128b/16B) */
42028 struct hwrm_fw_reset_output {
42029 /* The specific error status for the command. */
42030 uint16_t error_code;
42031 /* The HWRM command request type. */
42033 /* The sequence ID from the original command. */
42035 /* The length of the response data in number of bytes. */
42037 /* Type of self reset. */
42038 uint8_t selfrst_status;
42039 /* No Self Reset */
42040 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE \
42042 /* Self Reset as soon as possible to do so safely */
42043 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP \
42045 /* Self Reset on PCIe Reset */
42046 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST \
42048 /* Self Reset immediately after notification to all clients. */
42049 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE \
42051 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_LAST \
42052 HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE
42053 uint8_t unused_0[6];
42055 * This field is used in Output records to indicate that the output
42056 * is completely written to RAM. This field should be read as '1'
42057 * to indicate that the output has been completely written.
42058 * When writing a command completion or response to an internal processor,
42059 * the order of writes has to be such that this field is written last.
42064 /**********************
42065 * hwrm_port_ts_query *
42066 ***********************/
42069 /* hwrm_port_ts_query_input (size:192b/24B) */
42070 struct hwrm_port_ts_query_input {
42071 /* The HWRM command request type. */
42074 * The completion ring to send the completion event on. This should
42075 * be the NQ ID returned from the `nq_alloc` HWRM command.
42077 uint16_t cmpl_ring;
42079 * The sequence ID is used by the driver for tracking multiple
42080 * commands. This ID is treated as opaque data by the firmware and
42081 * the value is returned in the `hwrm_resp_hdr` upon completion.
42085 * The target ID of the command:
42086 * * 0x0-0xFFF8 - The function ID
42087 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42088 * * 0xFFFD - Reserved for user-space HWRM interface
42091 uint16_t target_id;
42093 * A physical address pointer pointing to a host buffer that the
42094 * command's response data will be written. This can be either a host
42095 * physical address (HPA) or a guest physical address (GPA) and must
42096 * point to a physically contiguous block of memory.
42098 uint64_t resp_addr;
42101 * Enumeration denoting the RX, TX type of the resource.
42102 * This enumeration is used for resources that are similar for both
42103 * TX and RX paths of the chip.
42105 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH 0x1UL
42107 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX 0x0UL
42109 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX 0x1UL
42110 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
42111 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
42113 * If set, the response includes the current value of the free
42116 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME 0x2UL
42117 /* Port ID of port that is being queried. */
42119 uint8_t unused_0[2];
42122 /* hwrm_port_ts_query_output (size:192b/24B) */
42123 struct hwrm_port_ts_query_output {
42124 /* The specific error status for the command. */
42125 uint16_t error_code;
42126 /* The HWRM command request type. */
42128 /* The sequence ID from the original command. */
42130 /* The length of the response data in number of bytes. */
42133 * Timestamp value of PTP message captured, or current value of
42134 * free running timer.
42136 uint32_t ptp_msg_ts[2];
42137 /* Sequence ID of the PTP message captured. */
42138 uint16_t ptp_msg_seqid;
42139 uint8_t unused_0[5];
42141 * This field is used in Output records to indicate that the output
42142 * is completely written to RAM. This field should be read as '1'
42143 * to indicate that the output has been completely written.
42144 * When writing a command completion or response to an internal processor,
42145 * the order of writes has to be such that this field is written last.
42151 * This structure is fixed at the beginning of the ChiMP SRAM (GRC
42152 * offset: 0x31001F0). Host software is expected to read from this
42153 * location for a defined signature. If it exists, the software can
42154 * assume the presence of this structure and the validity of the
42155 * FW_STATUS location in the next field.
42157 /* hcomm_status (size:64b/8B) */
42158 struct hcomm_status {
42161 * This field defines the version of the structure. The latest
42162 * version value is 1.
42164 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
42165 #define HCOMM_STATUS_VER_SFT 0
42166 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
42167 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST
42169 * This field is to store the signature value to indicate the
42170 * presence of the structure.
42172 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
42173 #define HCOMM_STATUS_SIGNATURE_SFT 8
42174 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
42175 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL
42176 uint32_t fw_status_loc;
42177 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
42178 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
42179 /* PCIE configuration space */
42180 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
42182 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
42184 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
42186 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
42187 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST \
42188 HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1
42190 * This offset where the fw_status register is located. The value
42191 * is generally 4-byte aligned.
42193 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
42194 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2
42196 /* This is the GRC offset where the hcomm_status struct resides. */
42197 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
42199 /**************************
42200 * hwrm_cfa_counter_qcaps *
42201 **************************/
42204 /* hwrm_cfa_counter_qcaps_input (size:128b/16B) */
42205 struct hwrm_cfa_counter_qcaps_input {
42206 /* The HWRM command request type. */
42209 * The completion ring to send the completion event on. This should
42210 * be the NQ ID returned from the `nq_alloc` HWRM command.
42212 uint16_t cmpl_ring;
42214 * The sequence ID is used by the driver for tracking multiple
42215 * commands. This ID is treated as opaque data by the firmware and
42216 * the value is returned in the `hwrm_resp_hdr` upon completion.
42220 * The target ID of the command:
42221 * * 0x0-0xFFF8 - The function ID
42222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42223 * * 0xFFFD - Reserved for user-space HWRM interface
42226 uint16_t target_id;
42228 * A physical address pointer pointing to a host buffer that the
42229 * command's response data will be written. This can be either a host
42230 * physical address (HPA) or a guest physical address (GPA) and must
42231 * point to a physically contiguous block of memory.
42233 uint64_t resp_addr;
42236 /* hwrm_cfa_counter_qcaps_output (size:576b/72B) */
42237 struct hwrm_cfa_counter_qcaps_output {
42238 /* The specific error status for the command. */
42239 uint16_t error_code;
42240 /* The HWRM command request type. */
42242 /* The sequence ID from the original command. */
42244 /* The length of the response data in number of bytes. */
42247 /* Enumeration denoting the supported CFA counter format. */
42248 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT \
42250 /* CFA counter types are not supported. */
42251 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE \
42253 /* 64-bit packet counters followed by 64-bit byte counters format. */
42254 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT \
42256 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_LAST \
42257 HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT
42259 /* Minimum guaranteed number of flow counters supported for this function, in RX direction. */
42260 uint32_t min_rx_fc;
42261 /* Maximum non-guaranteed number of flow counters supported for this function, in RX direction. */
42262 uint32_t max_rx_fc;
42263 /* Minimum guaranteed number of flow counters supported for this function, in TX direction. */
42264 uint32_t min_tx_fc;
42265 /* Maximum non-guaranteed number of flow counters supported for this function, in TX direction. */
42266 uint32_t max_tx_fc;
42267 /* Minimum guaranteed number of extension flow counters supported for this function, in RX direction. */
42268 uint32_t min_rx_efc;
42269 /* Maximum non-guaranteed number of extension flow counters supported for this function, in RX direction. */
42270 uint32_t max_rx_efc;
42271 /* Minimum guaranteed number of extension flow counters supported for this function, in TX direction. */
42272 uint32_t min_tx_efc;
42273 /* Maximum non-guaranteed number of extension flow counters supported for this function, in TX direction. */
42274 uint32_t max_tx_efc;
42275 /* Minimum guaranteed number of meter drop counters supported for this function, in RX direction. */
42276 uint32_t min_rx_mdc;
42277 /* Maximum non-guaranteed number of meter drop counters supported for this function, in RX direction. */
42278 uint32_t max_rx_mdc;
42279 /* Minimum guaranteed number of meter drop counters supported for this function, in TX direction. */
42280 uint32_t min_tx_mdc;
42281 /* Maximum non-guaranteed number of meter drop counters supported for this function, in TX direction. */
42282 uint32_t max_tx_mdc;
42283 /* Maximum guaranteed number of flow counters which can be used during flow alloc. */
42284 uint32_t max_flow_alloc_fc;
42285 uint8_t unused_1[3];
42287 * This field is used in Output records to indicate that the output
42288 * is completely written to RAM. This field should be read as '1'
42289 * to indicate that the output has been completely written.
42290 * When writing a command completion or response to an internal processor,
42291 * the order of writes has to be such that this field is written last.
42296 /************************
42297 * hwrm_cfa_counter_cfg *
42298 ************************/
42301 /* hwrm_cfa_counter_cfg_input (size:256b/32B) */
42302 struct hwrm_cfa_counter_cfg_input {
42303 /* The HWRM command request type. */
42306 * The completion ring to send the completion event on. This should
42307 * be the NQ ID returned from the `nq_alloc` HWRM command.
42309 uint16_t cmpl_ring;
42311 * The sequence ID is used by the driver for tracking multiple
42312 * commands. This ID is treated as opaque data by the firmware and
42313 * the value is returned in the `hwrm_resp_hdr` upon completion.
42317 * The target ID of the command:
42318 * * 0x0-0xFFF8 - The function ID
42319 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42320 * * 0xFFFD - Reserved for user-space HWRM interface
42323 uint16_t target_id;
42325 * A physical address pointer pointing to a host buffer that the
42326 * command's response data will be written. This can be either a host
42327 * physical address (HPA) or a guest physical address (GPA) and must
42328 * point to a physically contiguous block of memory.
42330 uint64_t resp_addr;
42332 /* Enumeration denoting the configuration mode. */
42333 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE \
42335 /* Disable the configuration mode. */
42336 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE \
42338 /* Enable the configuration mode. */
42339 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE \
42341 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_LAST \
42342 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE
42343 /* Enumeration denoting the RX, TX type of the resource. */
42344 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH \
42347 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX \
42348 (UINT32_C(0x0) << 1)
42350 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX \
42351 (UINT32_C(0x1) << 1)
42352 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_LAST \
42353 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX
42354 /* Enumeration denoting the data transfer mode. */
42355 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK \
42357 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_SFT 2
42359 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH \
42360 (UINT32_C(0x0) << 2)
42362 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL \
42363 (UINT32_C(0x1) << 2)
42364 /* Pull on async update. */
42365 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC \
42366 (UINT32_C(0x2) << 2)
42367 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_LAST \
42368 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC
42369 uint16_t counter_type;
42370 /* Flow counters. */
42371 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
42372 /* Extended flow counters. */
42373 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
42374 /* Meter drop counters. */
42375 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
42376 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_LAST \
42377 HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC
42378 /* Ctx memory handle to be used for the counter. */
42380 /* Counter update cadence hint (only in Push mode). */
42381 uint16_t update_tmr_ms;
42382 /* Total number of entries. */
42383 uint32_t num_entries;
42387 /* hwrm_cfa_counter_cfg_output (size:128b/16B) */
42388 struct hwrm_cfa_counter_cfg_output {
42389 /* The specific error status for the command. */
42390 uint16_t error_code;
42391 /* The HWRM command request type. */
42393 /* The sequence ID from the original command. */
42395 /* The length of the response data in number of bytes. */
42397 uint8_t unused_0[7];
42399 * This field is used in Output records to indicate that the output
42400 * is completely written to RAM. This field should be read as '1'
42401 * to indicate that the output has been completely written.
42402 * When writing a command completion or response to an internal processor,
42403 * the order of writes has to be such that this field is written last.
42408 /***************************
42409 * hwrm_cfa_counter_qstats *
42410 ***************************/
42413 /* hwrm_cfa_counter_qstats_input (size:320b/40B) */
42414 struct hwrm_cfa_counter_qstats_input {
42415 /* The HWRM command request type. */
42418 * The completion ring to send the completion event on. This should
42419 * be the NQ ID returned from the `nq_alloc` HWRM command.
42421 uint16_t cmpl_ring;
42423 * The sequence ID is used by the driver for tracking multiple
42424 * commands. This ID is treated as opaque data by the firmware and
42425 * the value is returned in the `hwrm_resp_hdr` upon completion.
42429 * The target ID of the command:
42430 * * 0x0-0xFFF8 - The function ID
42431 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42432 * * 0xFFFD - Reserved for user-space HWRM interface
42435 uint16_t target_id;
42437 * A physical address pointer pointing to a host buffer that the
42438 * command's response data will be written. This can be either a host
42439 * physical address (HPA) or a guest physical address (GPA) and must
42440 * point to a physically contiguous block of memory.
42442 uint64_t resp_addr;
42444 /* Enumeration denoting the RX, TX type of the resource. */
42445 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
42447 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
42449 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
42450 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_LAST \
42451 HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX
42452 uint16_t counter_type;
42453 uint16_t input_flow_ctx_id;
42454 uint16_t num_entries;
42455 uint16_t delta_time_ms;
42456 uint16_t meter_instance_id;
42457 uint16_t mdc_ctx_id;
42458 uint8_t unused_0[2];
42459 uint64_t expected_count;
42462 /* hwrm_cfa_counter_qstats_output (size:128b/16B) */
42463 struct hwrm_cfa_counter_qstats_output {
42464 /* The specific error status for the command. */
42465 uint16_t error_code;
42466 /* The HWRM command request type. */
42468 /* The sequence ID from the original command. */
42470 /* The length of the response data in number of bytes. */
42472 uint8_t unused_0[7];
42474 * This field is used in Output records to indicate that the output
42475 * is completely written to RAM. This field should be read as '1'
42476 * to indicate that the output has been completely written.
42477 * When writing a command completion or response to an internal processor,
42478 * the order of writes has to be such that this field is written last.
42483 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */