1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2014-2018 Broadcom Limited
5 * DO NOT MODIFY!!! This file is automatically generated.
8 #ifndef _HSI_STRUCT_DEF_DPDK_H_
9 #define _HSI_STRUCT_DEF_DPDK_H_
11 /* This is the HWRM command header. */
12 /* hwrm_cmd_hdr (size:128b/16B) */
14 /* The HWRM command request type. */
17 * The completion ring to send the completion event on. This should
18 * be the NQ ID returned from the `nq_alloc` HWRM command.
22 * The sequence ID is used by the driver for tracking multiple
23 * commands. This ID is treated as opaque data by the firmware and
24 * the value is returned in the `hwrm_resp_hdr` upon completion.
28 * The target ID of the command:
29 * * 0x0-0xFFF8 - The function ID
30 * * 0xFFF8-0xFFFE - Reserved for internal processors
35 * A physical address pointer pointing to a host buffer that the
36 * command's response data will be written. This can be either a host
37 * physical address (HPA) or a guest physical address (GPA) and must
38 * point to a physically contiguous block of memory.
41 } __attribute__((packed));
43 /* This is the HWRM response header. */
44 /* hwrm_resp_hdr (size:64b/8B) */
45 struct hwrm_resp_hdr {
46 /* The specific error status for the command. */
48 /* The HWRM command request type. */
50 /* The sequence ID from the original command. */
52 /* The length of the response data in number of bytes. */
54 } __attribute__((packed));
57 * TLV encapsulated message. Use the TLV type field of the
58 * TLV to determine the type of message encapsulated.
60 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
61 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
64 /* HWRM request message */
65 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
66 /* HWRM response message */
67 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
68 /* RoCE slow path command */
69 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
70 /* Engine CKV - The device's serial number. */
71 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
72 /* Engine CKV - Per-function random nonce data. */
73 #define TLV_TYPE_ENGINE_CKV_NONCE UINT32_C(0x8002)
74 /* Engine CKV - Initialization vector. */
75 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
76 /* Engine CKV - Authentication tag. */
77 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
78 /* Engine CKV - The encrypted data. */
79 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
80 /* Engine CKV - Supported algorithms. */
81 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS UINT32_C(0x8006)
82 /* Engine CKV - The EC curve name and ECC public key information. */
83 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY UINT32_C(0x8007)
84 /* Engine CKV - The ECDSA signature. */
85 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
86 #define TLV_TYPE_LAST \
87 TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
90 /* tlv (size:64b/8B) */
93 * The command discriminator is used to differentiate between various
94 * types of HWRM messages. This includes legacy HWRM and RoCE slowpath
95 * command messages as well as newer TLV encapsulated HWRM commands.
97 * For TLV encapsulated messages this field must be 0x8000.
103 * Indicates the presence of additional TLV encapsulated data
106 #define TLV_FLAGS_MORE UINT32_C(0x1)
107 /* Last TLV in a sequence of TLVs. */
108 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
109 /* More TLVs follow this TLV. */
110 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
112 * When an HWRM receiver detects a TLV type that it does not
113 * support with the TLV required flag set, the receiver must
114 * reject the HWRM message with an error code indicating an
115 * unsupported TLV type.
117 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
119 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
121 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
122 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
124 * This field defines the TLV type value which is divided into
125 * two ranges to differentiate between global and local TLV types.
126 * Global TLV types must be unique across all defined TLV types.
127 * Local TLV types are valid only for extensions to a given
128 * HWRM message and may be repeated across different HWRM message
129 * types. There is a direct correlation of each HWRM message type
130 * to a single global TLV type value.
132 * Global TLV range: `0 - (63k-1)`
134 * Local TLV range: `63k - (64k-1)`
138 * Length of the message data encapsulated by this TLV in bytes.
139 * This length does not include the size of the TLV header itself
140 * and it must be an integer multiple of 8B.
143 } __attribute__((packed));
146 /* input (size:128b/16B) */
149 * This value indicates what type of request this is. The format
150 * for the rest of the command is determined by this field.
154 * This value indicates the what completion ring the request will
155 * be optionally completed on. If the value is -1, then no
156 * CR completion will be generated. Any other value must be a
157 * valid CR ring_id value for this function.
160 /* This value indicates the command sequence number. */
163 * Target ID of this command.
165 * 0x0 - 0xFFF8 - Used for function ids
166 * 0xFFF8 - 0xFFFE - Reserved for internal processors
171 * This is the host address where the response will be written
172 * when the request is complete. This area must be 16B aligned
173 * and must be cleared to zero before the request is made.
176 } __attribute__((packed));
179 /* output (size:64b/8B) */
182 * Pass/Fail or error type
184 * Note: receiver to verify the in parameters, and fail the call
185 * with an error when appropriate
188 /* This field returns the type of original request. */
190 /* This field provides original sequence number of the command. */
193 * This field is the length of the response in bytes. The
194 * last byte of the response is a valid flag that will read
195 * as '1' when the command has been completely written to
199 } __attribute__((packed));
201 /* Short Command Structure */
202 /* hwrm_short_input (size:128b/16B) */
203 struct hwrm_short_input {
205 * This field indicates the type of request in the request buffer.
206 * The format for the rest of the command (request) is determined
211 * This field indicates a signature that is used to identify short
212 * form of the command listed here. This field shall be set to
216 /* Signature indicating this is a short form of HWRM command */
217 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
218 #define HWRM_SHORT_INPUT_SIGNATURE_LAST \
219 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
220 /* Reserved for future use. */
222 /* This value indicates the length of the request. */
225 * This is the host address where the request was written.
226 * This area must be 16B aligned.
229 } __attribute__((packed));
233 * # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
234 * # So only structure definition is provided here.
236 /* cmd_nums (size:64b/8B) */
239 * This version of the specification defines the commands listed in
240 * the table below. The following are general implementation
241 * requirements for these commands:
243 * # All commands listed below that are marked neither
244 * reserved nor experimental shall be implemented by the HWRM.
245 * # A HWRM client compliant to this specification should not use
246 * commands outside of the list below.
247 * # A HWRM client compliant to this specification should not use
248 * command numbers marked reserved below.
249 * # A command marked experimental below may not be implemented
251 * # A command marked experimental may change in the
252 * future version of the HWRM specification.
253 * # A command not listed below may be implemented by the HWRM.
254 * The behavior of commands that are not listed below is outside
255 * the scope of this specification.
258 #define HWRM_VER_GET UINT32_C(0x0)
259 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
260 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
261 /* Reserved for future use. */
262 #define HWRM_RESERVED1 UINT32_C(0x10)
263 #define HWRM_FUNC_RESET UINT32_C(0x11)
264 #define HWRM_FUNC_GETFID UINT32_C(0x12)
265 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
266 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
267 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
268 #define HWRM_FUNC_QCFG UINT32_C(0x16)
269 #define HWRM_FUNC_CFG UINT32_C(0x17)
270 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
271 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
272 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
273 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
274 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
275 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
276 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
277 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
278 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
279 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
281 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
282 #define HWRM_PORT_QSTATS UINT32_C(0x23)
283 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
285 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
287 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
288 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
289 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
291 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
292 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
293 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
294 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
295 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
296 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
297 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
298 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
299 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
300 #define HWRM_QUEUE_CFG UINT32_C(0x32)
301 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
302 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
303 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
304 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
305 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
306 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
307 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
308 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
310 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
312 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
314 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
315 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
316 #define HWRM_VNIC_FREE UINT32_C(0x41)
317 #define HWRM_VNIC_CFG UINT32_C(0x42)
318 #define HWRM_VNIC_QCFG UINT32_C(0x43)
319 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
321 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
322 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
323 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
324 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
325 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
326 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
327 #define HWRM_RING_ALLOC UINT32_C(0x50)
328 #define HWRM_RING_FREE UINT32_C(0x51)
329 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
330 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
331 #define HWRM_RING_RESET UINT32_C(0x5e)
332 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
333 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
334 /* Reserved for future use. */
335 #define HWRM_RESERVED5 UINT32_C(0x64)
336 /* Reserved for future use. */
337 #define HWRM_RESERVED6 UINT32_C(0x65)
338 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
339 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
340 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
341 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
342 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
343 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
344 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
345 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
346 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
348 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
350 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
351 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
352 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
353 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
355 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
357 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
359 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
360 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
361 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
362 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
363 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
364 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
365 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
366 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
367 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
368 #define HWRM_FW_RESET UINT32_C(0xc0)
369 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
371 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
373 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
375 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
377 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
379 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
380 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
381 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
382 #define HWRM_FWD_RESP UINT32_C(0xd2)
383 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
384 #define HWRM_OEM_CMD UINT32_C(0xd4)
385 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
386 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
387 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
388 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
389 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
391 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
393 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
395 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
397 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
399 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
401 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
403 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
405 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
407 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
409 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
411 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
413 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
415 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
417 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
419 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
421 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
423 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
424 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
425 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
426 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
428 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
430 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
432 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
434 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
435 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
436 /* Engine CKV - Ping the device and SRT firmware to get the public key. */
437 #define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
438 /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
439 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
440 /* Engine CKV - Add a new CKEK used to encrypt keys. */
441 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
442 /* Engine CKV - Delete a previously added CKEK. */
443 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
444 /* Engine CKV - Add a new key to the key vault. */
445 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
446 /* Engine CKV - Delete a key from the key vault. */
447 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
448 /* Engine CKV - Delete all keys from the key vault. */
449 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
450 /* Engine CKV - Get random data. */
451 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
452 /* Engine CKV - Generate and encrypt a new AES key. */
453 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
454 /* Engine - Query the available queue groups configuration. */
455 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
456 /* Engine - Query the queue groups assigned to a function. */
457 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
458 /* Engine - Query the available queue group meter profile configuration. */
459 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
460 /* Engine - Query the configuration of a queue group meter profile. */
461 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
462 /* Engine - Allocate a queue group meter profile. */
463 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
464 /* Engine - Free a queue group meter profile. */
465 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
466 /* Engine - Query the meters assigned to a queue group. */
467 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
468 /* Engine - Bind a queue group meter profile to a queue group. */
469 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
470 /* Engine - Unbind a queue group meter profile from a queue group. */
471 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
472 /* Engine - Bind a queue group to a function. */
473 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
474 /* Engine - Query the scheduling group configuration. */
475 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
476 /* Engine - Query the queue groups assigned to a scheduling group. */
477 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
478 /* Engine - Query the configuration of a scheduling group's meter profiles. */
479 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
480 /* Engine - Configure a scheduling group's meter profiles. */
481 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
482 /* Engine - Bind a queue group to a scheduling group. */
483 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
484 /* Engine - Unbind a queue group from its scheduling group. */
485 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
486 /* Engine - Query the Engine configuration. */
487 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
488 /* Engine - Configure the statistics accumulator for an Engine. */
489 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
490 /* Engine - Clear the statistics accumulator for an Engine. */
491 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
492 /* Engine - Query the statistics accumulator for an Engine. */
493 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
494 /* Engine - Allocate an Engine RQ. */
495 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
496 /* Engine - Free an Engine RQ. */
497 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
498 /* Engine - Allocate an Engine CQ. */
499 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
500 /* Engine - Free an Engine CQ. */
501 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
502 /* Engine - Allocate an NQ. */
503 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
504 /* Engine - Free an NQ. */
505 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
506 /* Engine - Set the on-die RQE credit update location. */
507 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
509 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
511 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
513 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
515 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
517 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
519 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
521 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
523 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
525 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
527 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
529 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
531 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
533 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
535 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
536 #define HWRM_DBG_DUMP UINT32_C(0xff14)
538 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
540 #define HWRM_DBG_CFG UINT32_C(0xff16)
542 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
544 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
546 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
548 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
550 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
551 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
552 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
553 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
554 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
555 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
556 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
557 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
558 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
559 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
560 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
561 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
562 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
563 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
564 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
565 #define HWRM_NVM_READ UINT32_C(0xfffd)
566 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
567 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
568 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
569 uint16_t unused_0[3];
570 } __attribute__((packed));
573 /* ret_codes (size:64b/8B) */
576 /* Request was successfully executed by the HWRM. */
577 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
578 /* The HWRM failed to execute the request. */
579 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
581 * The request contains invalid argument(s) or input
584 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
586 * The requester is not allowed to access the requested
587 * resource. This error code shall be provided in a
588 * response to a request to query or modify an existing
589 * resource that is not accessible by the requester.
591 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
593 * The HWRM is unable to allocate the requested resource.
594 * This code only applies to requests for HWRM resource
597 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
599 * Invalid combination of flags is specified in the
602 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
604 * Invalid combination of enables fields is specified in
607 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
609 * Request contains a required TLV that is not supported by
610 * the installed version of firmware.
612 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
614 * No firmware buffer available to accept the request. Driver
615 * should retry the request.
617 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
619 * Generic HWRM execution error that represents an
622 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
624 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
625 /* Unsupported or invalid command */
626 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
627 #define HWRM_ERR_CODE_LAST \
628 HWRM_ERR_CODE_CMD_NOT_SUPPORTED
629 uint16_t unused_0[3];
630 } __attribute__((packed));
633 /* hwrm_err_output (size:128b/16B) */
634 struct hwrm_err_output {
636 * Pass/Fail or error type
638 * Note: receiver to verify the in parameters, and fail the call
639 * with an error when appropriate
642 /* This field returns the type of original request. */
644 /* This field provides original sequence number of the command. */
647 * This field is the length of the response in bytes. The
648 * last byte of the response is a valid flag that will read
649 * as '1' when the command has been completely written to
653 /* debug info for this error response. */
655 /* debug info for this error response. */
658 * In the case of an error response, command specific error
659 * code is returned in this field.
663 * This field is used in Output records to indicate that the output
664 * is completely written to RAM. This field should be read as '1'
665 * to indicate that the output has been completely written.
666 * When writing a command completion or response to an internal processor,
667 * the order of writes has to be such that this field is written last.
670 } __attribute__((packed));
672 * Following is the signature for HWRM message field that indicates not
673 * applicable (All F's). Need to cast it the size of the field if needed.
675 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
676 /* hwrm_func_buf_rgtr */
677 #define HWRM_MAX_REQ_LEN 128
678 /* hwrm_selftest_qlist */
679 #define HWRM_MAX_RESP_LEN 280
680 /* 7 bit indirection table index. */
681 #define HW_HASH_INDEX_SIZE 0x80
682 #define HW_HASH_KEY_SIZE 40
683 /* valid key for HWRM response */
684 #define HWRM_RESP_VALID_KEY 1
685 #define HWRM_VERSION_MAJOR 1
686 #define HWRM_VERSION_MINOR 9
687 #define HWRM_VERSION_UPDATE 2
688 /* non-zero means beta version */
689 #define HWRM_VERSION_RSVD 6
690 #define HWRM_VERSION_STR "1.9.2.6"
697 /* hwrm_ver_get_input (size:192b/24B) */
698 struct hwrm_ver_get_input {
699 /* The HWRM command request type. */
702 * The completion ring to send the completion event on. This should
703 * be the NQ ID returned from the `nq_alloc` HWRM command.
707 * The sequence ID is used by the driver for tracking multiple
708 * commands. This ID is treated as opaque data by the firmware and
709 * the value is returned in the `hwrm_resp_hdr` upon completion.
713 * The target ID of the command:
714 * * 0x0-0xFFF8 - The function ID
715 * * 0xFFF8-0xFFFE - Reserved for internal processors
720 * A physical address pointer pointing to a host buffer that the
721 * command's response data will be written. This can be either a host
722 * physical address (HPA) or a guest physical address (GPA) and must
723 * point to a physically contiguous block of memory.
727 * This field represents the major version of HWRM interface
728 * specification supported by the driver HWRM implementation.
729 * The interface major version is intended to change only when
730 * non backward compatible changes are made to the HWRM
731 * interface specification.
733 uint8_t hwrm_intf_maj;
735 * This field represents the minor version of HWRM interface
736 * specification supported by the driver HWRM implementation.
737 * A change in interface minor version is used to reflect
738 * significant backward compatible modification to HWRM
739 * interface specification.
740 * This can be due to addition or removal of functionality.
741 * HWRM interface specifications with the same major version
742 * but different minor versions are compatible.
744 uint8_t hwrm_intf_min;
746 * This field represents the update version of HWRM interface
747 * specification supported by the driver HWRM implementation.
748 * The interface update version is used to reflect minor
749 * changes or bug fixes to a released HWRM interface
752 uint8_t hwrm_intf_upd;
754 } __attribute__((packed));
756 /* hwrm_ver_get_output (size:1408b/176B) */
757 struct hwrm_ver_get_output {
758 /* The specific error status for the command. */
760 /* The HWRM command request type. */
762 /* The sequence ID from the original command. */
764 /* The length of the response data in number of bytes. */
767 * This field represents the major version of HWRM interface
768 * specification supported by the HWRM implementation.
769 * The interface major version is intended to change only when
770 * non backward compatible changes are made to the HWRM
771 * interface specification.
772 * A HWRM implementation that is compliant with this
773 * specification shall provide value of 1 in this field.
775 uint8_t hwrm_intf_maj_8b;
777 * This field represents the minor version of HWRM interface
778 * specification supported by the HWRM implementation.
779 * A change in interface minor version is used to reflect
780 * significant backward compatible modification to HWRM
781 * interface specification.
782 * This can be due to addition or removal of functionality.
783 * HWRM interface specifications with the same major version
784 * but different minor versions are compatible.
785 * A HWRM implementation that is compliant with this
786 * specification shall provide value of 2 in this field.
788 uint8_t hwrm_intf_min_8b;
790 * This field represents the update version of HWRM interface
791 * specification supported by the HWRM implementation.
792 * The interface update version is used to reflect minor
793 * changes or bug fixes to a released HWRM interface
795 * A HWRM implementation that is compliant with this
796 * specification shall provide value of 2 in this field.
798 uint8_t hwrm_intf_upd_8b;
799 uint8_t hwrm_intf_rsvd_8b;
801 * This field represents the major version of HWRM firmware.
802 * A change in firmware major version represents a major
805 uint8_t hwrm_fw_maj_8b;
807 * This field represents the minor version of HWRM firmware.
808 * A change in firmware minor version represents significant
809 * firmware functionality changes.
811 uint8_t hwrm_fw_min_8b;
813 * This field represents the build version of HWRM firmware.
814 * A change in firmware build version represents bug fixes
815 * to a released firmware.
817 uint8_t hwrm_fw_bld_8b;
819 * This field is a reserved field. This field can be used to
820 * represent firmware branches or customer specific releases
821 * tied to a specific (major,minor,update) version of the
824 uint8_t hwrm_fw_rsvd_8b;
826 * This field represents the major version of mgmt firmware.
827 * A change in major version represents a major release.
829 uint8_t mgmt_fw_maj_8b;
831 * This field represents the minor version of mgmt firmware.
832 * A change in minor version represents significant
833 * functionality changes.
835 uint8_t mgmt_fw_min_8b;
837 * This field represents the build version of mgmt firmware.
838 * A change in update version represents bug fixes.
840 uint8_t mgmt_fw_bld_8b;
842 * This field is a reserved field. This field can be used to
843 * represent firmware branches or customer specific releases
844 * tied to a specific (major,minor,update) version
846 uint8_t mgmt_fw_rsvd_8b;
848 * This field represents the major version of network
850 * A change in major version represents a major release.
852 uint8_t netctrl_fw_maj_8b;
854 * This field represents the minor version of network
856 * A change in minor version represents significant
857 * functionality changes.
859 uint8_t netctrl_fw_min_8b;
861 * This field represents the build version of network
863 * A change in update version represents bug fixes.
865 uint8_t netctrl_fw_bld_8b;
867 * This field is a reserved field. This field can be used to
868 * represent firmware branches or customer specific releases
869 * tied to a specific (major,minor,update) version
871 uint8_t netctrl_fw_rsvd_8b;
873 * This field is used to indicate device's capabilities and
876 uint32_t dev_caps_cfg;
878 * If set to 1, then secure firmware update behavior
880 * If set to 0, then secure firmware update behavior is
883 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED \
886 * If set to 1, then firmware based DCBX agent is supported.
887 * If set to 0, then firmware based DCBX agent capability
888 * is not supported on this device.
890 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED \
893 * If set to 1, then HWRM short command format is supported.
894 * If set to 0, then HWRM short command format is not supported.
896 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED \
899 * If set to 1, then HWRM short command format is required.
900 * If set to 0, then HWRM short command format is not required.
902 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \
905 * This field represents the major version of RoCE firmware.
906 * A change in major version represents a major release.
908 uint8_t roce_fw_maj_8b;
910 * This field represents the minor version of RoCE firmware.
911 * A change in minor version represents significant
912 * functionality changes.
914 uint8_t roce_fw_min_8b;
916 * This field represents the build version of RoCE firmware.
917 * A change in update version represents bug fixes.
919 uint8_t roce_fw_bld_8b;
921 * This field is a reserved field. This field can be used to
922 * represent firmware branches or customer specific releases
923 * tied to a specific (major,minor,update) version
925 uint8_t roce_fw_rsvd_8b;
927 * This field represents the name of HWRM FW (ASCII chars
928 * with NULL at the end).
930 char hwrm_fw_name[16];
932 * This field represents the name of mgmt FW (ASCII chars
933 * with NULL at the end).
935 char mgmt_fw_name[16];
937 * This field represents the name of network control
938 * firmware (ASCII chars with NULL at the end).
940 char netctrl_fw_name[16];
942 * This field is reserved for future use.
943 * The responder should set it to 0.
944 * The requester should ignore this field.
946 uint8_t reserved2[16];
948 * This field represents the name of RoCE FW (ASCII chars
949 * with NULL at the end).
951 char roce_fw_name[16];
952 /* This field returns the chip number. */
954 /* This field returns the revision of chip. */
956 /* This field returns the chip metal number. */
958 /* This field returns the bond id of the chip. */
959 uint8_t chip_bond_id;
960 /* This value indicates the type of platform used for chip implementation. */
961 uint8_t chip_platform_type;
963 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
964 /* FPGA platform of the chip. */
965 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
966 /* Palladium platform of the chip. */
967 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
968 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST \
969 HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
971 * This field returns the maximum value of request window that
972 * is supported by the HWRM. The request window is mapped
973 * into device address space using MMIO.
975 uint16_t max_req_win_len;
977 * This field returns the maximum value of response buffer in
980 uint16_t max_resp_len;
982 * This field returns the default request timeout value in
985 uint16_t def_req_timeout;
987 * This field will indicate if any subsystems is not fully
992 * If set to 1, device is not ready.
993 * If set to 0, device is ready to accept all HWRM commands.
995 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
997 * If set to 1, external version present.
998 * If set to 0, external version not present.
1000 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
1001 uint8_t unused_0[2];
1003 * For backward compatibility this field must be set to 1.
1004 * Older drivers might look for this field to be 1 before
1005 * processing the message.
1009 * This field represents the major version of HWRM interface
1010 * specification supported by the HWRM implementation.
1011 * The interface major version is intended to change only when
1012 * non backward compatible changes are made to the HWRM
1013 * interface specification. A HWRM implementation that is
1014 * compliant with this specification shall provide value of 1
1017 uint16_t hwrm_intf_major;
1019 * This field represents the minor version of HWRM interface
1020 * specification supported by the HWRM implementation.
1021 * A change in interface minor version is used to reflect
1022 * significant backward compatible modification to HWRM
1023 * interface specification. This can be due to addition or
1024 * removal of functionality. HWRM interface specifications
1025 * with the same major version but different minor versions are
1026 * compatible. A HWRM implementation that is compliant with
1027 * this specification shall provide value of 2 in this field.
1029 uint16_t hwrm_intf_minor;
1031 * This field represents the update version of HWRM interface
1032 * specification supported by the HWRM implementation. The
1033 * interface update version is used to reflect minor changes or
1034 * bug fixes to a released HWRM interface specification.
1035 * A HWRM implementation that is compliant with this
1036 * specification shall provide value of 2 in this field.
1038 uint16_t hwrm_intf_build;
1040 * This field represents the patch version of HWRM interface
1041 * specification supported by the HWRM implementation.
1043 uint16_t hwrm_intf_patch;
1045 * This field represents the major version of HWRM firmware.
1046 * A change in firmware major version represents a major
1049 uint16_t hwrm_fw_major;
1051 * This field represents the minor version of HWRM firmware.
1052 * A change in firmware minor version represents significant
1053 * firmware functionality changes.
1055 uint16_t hwrm_fw_minor;
1057 * This field represents the build version of HWRM firmware.
1058 * A change in firmware build version represents bug fixes to
1059 * a released firmware.
1061 uint16_t hwrm_fw_build;
1063 * This field is a reserved field.
1064 * This field can be used to represent firmware branches or customer
1065 * specific releases tied to a specific (major,minor,update) version
1066 * of the HWRM firmware.
1068 uint16_t hwrm_fw_patch;
1070 * This field represents the major version of mgmt firmware.
1071 * A change in major version represents a major release.
1073 uint16_t mgmt_fw_major;
1075 * This field represents the minor version of HWRM firmware.
1076 * A change in firmware minor version represents significant
1077 * firmware functionality changes.
1079 uint16_t mgmt_fw_minor;
1081 * This field represents the build version of mgmt firmware.
1082 * A change in update version represents bug fixes.
1084 uint16_t mgmt_fw_build;
1086 * This field is a reserved field. This field can be used to
1087 * represent firmware branches or customer specific releases
1088 * tied to a specific (major,minor,update) version.
1090 uint16_t mgmt_fw_patch;
1092 * This field represents the major version of network control
1093 * firmware. A change in major version represents
1096 uint16_t netctrl_fw_major;
1098 * This field represents the minor version of network control
1099 * firmware. A change in minor version represents significant
1100 * functionality changes.
1102 uint16_t netctrl_fw_minor;
1104 * This field represents the build version of network control
1105 * firmware. A change in update version represents bug fixes.
1107 uint16_t netctrl_fw_build;
1109 * This field is a reserved field. This field can be used to
1110 * represent firmware branches or customer specific releases
1111 * tied to a specific (major,minor,update) version
1113 uint16_t netctrl_fw_patch;
1115 * This field represents the major version of RoCE firmware.
1116 * A change in major version represents a major release.
1118 uint16_t roce_fw_major;
1120 * This field represents the minor version of RoCE firmware.
1121 * A change in minor version represents significant
1122 * functionality changes.
1124 uint16_t roce_fw_minor;
1126 * This field represents the build version of RoCE firmware.
1127 * A change in update version represents bug fixes.
1129 uint16_t roce_fw_build;
1131 * This field is a reserved field. This field can be used to
1132 * represent firmware branches or customer specific releases
1133 * tied to a specific (major,minor,update) version
1135 uint16_t roce_fw_patch;
1137 * This field returns the maximum extended request length acceptable
1138 * by the device which allows requests greater than mailbox size when
1139 * used with the short cmd request format.
1141 uint16_t max_ext_req_len;
1142 uint8_t unused_1[5];
1144 * This field is used in Output records to indicate that the output
1145 * is completely written to RAM. This field should be read as '1'
1146 * to indicate that the output has been completely written.
1147 * When writing a command completion or response to an internal processor,
1148 * the order of writes has to be such that this field is written last.
1151 } __attribute__((packed));
1153 /* bd_base (size:64b/8B) */
1156 /* This value identifies the type of buffer descriptor. */
1157 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
1158 #define BD_BASE_TYPE_SFT 0
1160 * Indicates that this BD is 16B long and is used for
1161 * normal L2 packet transmission.
1163 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
1165 * Indicates that this BD is 1BB long and is an empty
1166 * TX BD. Not valid for use by the driver.
1168 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1170 * Indicates that this BD is 16B long and is an RX Producer
1171 * (ie. empty) buffer descriptor.
1173 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
1175 * Indicates that this BD is 16B long and is an RX
1176 * Producer Buffer BD.
1178 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
1180 * Indicates that this BD is 16B long and is an
1181 * RX Producer Assembly Buffer Descriptor.
1183 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
1185 * Indicates that this BD is 32B long and is used for
1186 * normal L2 packet transmission.
1188 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
1189 #define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG
1190 uint8_t unused_1[7];
1191 } __attribute__((packed));
1193 /* tx_bd_short (size:128b/16B) */
1194 struct tx_bd_short {
1196 * All bits in this field must be valid on the first BD of a packet.
1197 * Only the packet_end bit must be valid for the remaining BDs
1200 uint16_t flags_type;
1201 /* This value identifies the type of buffer descriptor. */
1202 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
1203 #define TX_BD_SHORT_TYPE_SFT 0
1205 * Indicates that this BD is 16B long and is used for
1206 * normal L2 packet transmission.
1208 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
1209 #define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
1211 * All bits in this field must be valid on the first BD of a packet.
1212 * Only the packet_end bit must be valid for the remaining BDs
1215 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
1216 #define TX_BD_SHORT_FLAGS_SFT 6
1218 * If set to 1, the packet ends with the data in the buffer
1219 * pointed to by this descriptor. This flag must be
1220 * valid on every BD.
1222 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
1224 * If set to 1, the device will not generate a completion for
1225 * this transmit packet unless there is an error in it's
1228 * is set to 0, then the packet will be completed normally.
1230 * This bit must be valid only on the first BD of a packet.
1232 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
1234 * This value indicates how many 16B BD locations are consumed
1235 * in the ring by this packet.
1236 * A value of 1 indicates that this BD is the only BD (and that
1237 * the it is a short BD). A value
1238 * of 3 indicates either 3 short BDs or 1 long BD and one short
1239 * BD in the packet. A value of 0 indicates
1240 * that there are 32 BD locations in the packet (the maximum).
1242 * This field is valid only on the first BD of a packet.
1244 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1245 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
1247 * This value is a hint for the length of the entire packet.
1248 * It is used by the chip to optimize internal processing.
1250 * The packet will be dropped if the hint is too short.
1252 * This field is valid only on the first BD of a packet.
1254 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
1255 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
1256 /* indicates packet length < 512B */
1257 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1258 /* indicates 512 <= packet length < 1KB */
1259 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1260 /* indicates 1KB <= packet length < 2KB */
1261 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1262 /* indicates packet length >= 2KB */
1263 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1264 #define TX_BD_SHORT_FLAGS_LHINT_LAST \
1265 TX_BD_SHORT_FLAGS_LHINT_GTE2K
1267 * If set to 1, the device immediately updates the Send Consumer
1268 * Index after the buffer associated with this descriptor has
1269 * been transferred via DMA to NIC memory from host memory. An
1270 * interrupt may or may not be generated according to the state
1271 * of the interrupt avoidance mechanisms. If this bit
1272 * is set to 0, then the Consumer Index is only updated as soon
1273 * as one of the host interrupt coalescing conditions has been met.
1275 * This bit must be valid on the first BD of a packet.
1277 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
1279 * This is the length of the host physical buffer this BD describes
1282 * This field must be valid on all BDs of a packet.
1286 * The opaque data field is pass through to the completion and can be
1287 * used for any data that the driver wants to associate with the
1290 * This field must be valid on the first BD of a packet.
1294 * This is the host physical address for the portion of the packet
1295 * described by this TX BD.
1297 * This value must be valid on all BDs of a packet.
1300 } __attribute__((packed));
1302 /* tx_bd_long (size:128b/16B) */
1304 /* This value identifies the type of buffer descriptor. */
1305 uint16_t flags_type;
1307 * This value indicates the type of buffer descriptor.
1310 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
1311 #define TX_BD_LONG_TYPE_SFT 0
1313 * Indicates that this BD is 32B long and is used for
1314 * normal L2 packet transmission.
1316 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
1317 #define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
1319 * All bits in this field must be valid on the first BD of a packet.
1320 * Only the packet_end bit must be valid for the remaining BDs
1323 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
1324 #define TX_BD_LONG_FLAGS_SFT 6
1326 * If set to 1, the packet ends with the data in the buffer
1327 * pointed to by this descriptor. This flag must be
1328 * valid on every BD.
1330 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
1332 * If set to 1, the device will not generate a completion for
1333 * this transmit packet unless there is an error in it's
1336 * is set to 0, then the packet will be completed normally.
1338 * This bit must be valid only on the first BD of a packet.
1340 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
1342 * This value indicates how many 16B BD locations are consumed
1343 * in the ring by this packet.
1344 * A value of 1 indicates that this BD is the only BD (and that
1345 * the it is a short BD). A value
1346 * of 3 indicates either 3 short BDs or 1 long BD and one short
1347 * BD in the packet. A value of 0 indicates
1348 * that there are 32 BD locations in the packet (the maximum).
1350 * This field is valid only on the first BD of a packet.
1352 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
1353 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
1355 * This value is a hint for the length of the entire packet.
1356 * It is used by the chip to optimize internal processing.
1358 * The packet will be dropped if the hint is too short.
1360 * This field is valid only on the first BD of a packet.
1362 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
1363 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
1364 /* indicates packet length < 512B */
1365 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
1366 /* indicates 512 <= packet length < 1KB */
1367 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
1368 /* indicates 1KB <= packet length < 2KB */
1369 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
1370 /* indicates packet length >= 2KB */
1371 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
1372 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
1374 * If set to 1, the device immediately updates the Send Consumer
1375 * Index after the buffer associated with this descriptor has
1376 * been transferred via DMA to NIC memory from host memory. An
1377 * interrupt may or may not be generated according to the state
1378 * of the interrupt avoidance mechanisms. If this bit
1379 * is set to 0, then the Consumer Index is only updated as soon
1380 * as one of the host interrupt coalescing conditions has been met.
1382 * This bit must be valid on the first BD of a packet.
1384 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
1386 * This is the length of the host physical buffer this BD describes
1389 * This field must be valid on all BDs of a packet.
1393 * The opaque data field is pass through to the completion and can be
1394 * used for any data that the driver wants to associate with the
1397 * This field must be valid on the first BD of a packet.
1401 * This is the host physical address for the portion of the packet
1402 * described by this TX BD.
1404 * This value must be valid on all BDs of a packet.
1407 } __attribute__((packed));
1409 /* tx_bd_long_hi (size:128b/16B) */
1410 struct tx_bd_long_hi {
1412 * All bits in this field must be valid on the first BD of a packet.
1413 * Their value on other BDs of the packet will be ignored.
1417 * If set to 1, the controller replaces the TCP/UPD checksum
1418 * fields of normal TCP/UPD checksum, or the inner TCP/UDP
1419 * checksum field of the encapsulated TCP/UDP packets with the
1420 * hardware calculated TCP/UDP checksum for the packet associated
1421 * with this descriptor. The flag is ignored if the LSO flag is set.
1423 * This bit must be valid on the first BD of a packet.
1425 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
1427 * If set to 1, the controller replaces the IP checksum of the
1428 * normal packets, or the inner IP checksum of the encapsulated
1429 * packets with the hardware calculated IP checksum for the
1430 * packet associated with this descriptor.
1432 * This bit must be valid on the first BD of a packet.
1434 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
1436 * If set to 1, the controller will not append an Ethernet CRC
1437 * to the end of the frame.
1439 * This bit must be valid on the first BD of a packet.
1441 * Packet must be 64B or longer when this flag is set. It is not
1442 * useful to use this bit with any form of TX offload such as
1443 * CSO or LSO. The intent is that the packet from the host already
1444 * has a valid Ethernet CRC on the packet.
1446 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
1448 * If set to 1, the device will record the time at which the packet
1449 * was actually transmitted at the TX MAC.
1451 * This bit must be valid on the first BD of a packet.
1453 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
1455 * If set to 1, The controller replaces the tunnel IP checksum
1456 * field with hardware calculated IP checksum for the IP header
1457 * of the packet associated with this descriptor.
1459 * For outer UDP checksum, global outer UDP checksum TE_NIC register
1460 * needs to be enabled. If the global outer UDP checksum TE_NIC register
1461 * bit is set, outer UDP checksum will be calculated for the following
1463 * 1. Packets with tcp_udp_chksum flag set to offload checksum for inner
1464 * packet AND the inner packet is TCP/UDP. If the inner packet is ICMP for
1465 * example (non-TCP/UDP), even if the tcp_udp_chksum is set, the outer UDP
1466 * checksum will not be calculated.
1467 * 2. Packets with lso flag set which implies inner TCP checksum calculation
1468 * as part of LSO operation.
1470 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
1472 * If set to 1, the device will treat this packet with LSO(Large
1473 * Send Offload) processing for both normal or encapsulated
1474 * packets, which is a form of TCP segmentation. When this bit
1475 * is 1, the hdr_size and mss fields must be valid. The driver
1476 * doesn't need to set t_ip_chksum, ip_chksum, and tcp_udp_chksum
1477 * flags since the controller will replace the appropriate
1478 * checksum fields for segmented packets.
1480 * When this bit is 1, the hdr_size and mss fields must be valid.
1482 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
1484 * If set to zero when LSO is '1', then the IPID will be treated
1485 * as a 16b number and will be wrapped if it exceeds a value of
1488 * If set to one when LSO is '1', then the IPID will be treated
1489 * as a 15b number and will be wrapped if it exceeds a value 0f
1492 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
1494 * If set to zero when LSO is '1', then the IPID of the tunnel
1495 * IP header will not be modified during LSO operations.
1497 * If set to one when LSO is '1', then the IPID of the tunnel
1498 * IP header will be incremented for each subsequent segment of an
1501 * The flag is ignored if the LSO packet is a normal (non-tunneled)
1504 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
1506 * If set to '1', then the RoCE ICRC will be appended to the
1507 * packet. Packet must be a valid RoCE format packet.
1509 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
1511 * If set to '1', then the FCoE CRC will be appended to the
1512 * packet. Packet must be a valid FCoE format packet.
1514 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
1517 * When LSO is '1', this field must contain the offset of the
1518 * TCP payload from the beginning of the packet in as
1519 * 16b words. In case of encapsulated/tunneling packet, this field
1520 * contains the offset of the inner TCP payload from beginning of the
1521 * packet as 16-bit words.
1523 * This value must be valid on the first BD of a packet.
1525 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
1526 #define TX_BD_LONG_HDR_SIZE_SFT 0
1529 * This is the MSS value that will be used to do the LSO processing.
1530 * The value is the length in bytes of the TCP payload for each
1531 * segment generated by the LSO operation.
1533 * This value must be valid on the first BD of a packet.
1535 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
1536 #define TX_BD_LONG_MSS_SFT 0
1539 * This value selects a CFA action to perform on the packet.
1540 * Set this value to zero if no CFA action is desired.
1542 * This value must be valid on the first BD of a packet.
1544 uint16_t cfa_action;
1546 * This value is action meta-data that defines CFA edit operations
1547 * that are done in addition to any action editing.
1550 /* When key=1, This is the VLAN tag VID value. */
1551 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
1552 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
1553 /* When key=1, This is the VLAN tag DE value. */
1554 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
1555 /* When key=1, This is the VLAN tag PRI value. */
1556 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
1557 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
1558 /* When key=1, This is the VLAN tag TPID select value. */
1559 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
1560 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
1562 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
1564 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
1566 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
1568 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
1570 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
1571 /* Value programmed in CFA VLANTPID register. */
1572 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
1573 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \
1574 TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
1575 /* When key=1, This is the VLAN tag TPID select value. */
1576 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
1577 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
1579 * This field identifies the type of edit to be performed
1582 * This value must be valid on the first BD of a packet.
1584 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
1585 #define TX_BD_LONG_CFA_META_KEY_SFT 28
1587 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
1589 * - meta[17:16] - TPID select value (0 = 0x8100).
1590 * - meta[15:12] - PRI/DE value.
1591 * - meta[11:0] - VID value.
1593 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
1594 #define TX_BD_LONG_CFA_META_KEY_LAST \
1595 TX_BD_LONG_CFA_META_KEY_VLAN_TAG
1596 } __attribute__((packed));
1598 /* tx_bd_empty (size:128b/16B) */
1599 struct tx_bd_empty {
1600 /* This value identifies the type of buffer descriptor. */
1602 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
1603 #define TX_BD_EMPTY_TYPE_SFT 0
1605 * Indicates that this BD is 1BB long and is an empty
1606 * TX BD. Not valid for use by the driver.
1608 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
1609 #define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
1610 uint8_t unused_1[3];
1612 uint8_t unused_3[3];
1613 uint8_t unused_4[8];
1614 } __attribute__((packed));
1616 /* rx_prod_pkt_bd (size:128b/16B) */
1617 struct rx_prod_pkt_bd {
1618 /* This value identifies the type of buffer descriptor. */
1619 uint16_t flags_type;
1620 /* This value identifies the type of buffer descriptor. */
1621 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
1622 #define RX_PROD_PKT_BD_TYPE_SFT 0
1624 * Indicates that this BD is 16B long and is an RX Producer
1625 * (ie. empty) buffer descriptor.
1627 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
1628 #define RX_PROD_PKT_BD_TYPE_LAST \
1629 RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
1630 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
1631 #define RX_PROD_PKT_BD_FLAGS_SFT 6
1633 * If set to 1, the packet will be placed at the address plus
1634 * 2B. The 2 Bytes of padding will be written as zero.
1636 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
1638 * If set to 1, the packet write will be padded out to the
1639 * nearest cache-line with zero value padding.
1641 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
1643 * This value is the number of additional buffers in the ring that
1644 * describe the buffer space to be consumed for the this packet.
1645 * If the value is zero, then the packet must fit within the
1646 * space described by this BD. If this value is 1 or more, it
1647 * indicates how many additional "buffer" BDs are in the ring
1648 * immediately following this BD to be used for the same
1651 * Even if the packet to be placed does not need all the
1652 * additional buffers, they will be consumed anyway.
1654 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
1655 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
1657 * This is the length in Bytes of the host physical buffer where
1658 * data for the packet may be placed in host memory.
1662 * The opaque data field is pass through to the completion and can be
1663 * used for any data that the driver wants to associate with this
1664 * receive buffer set.
1668 * This is the host physical address where data for the packet may
1669 * by placed in host memory.
1672 } __attribute__((packed));
1674 /* rx_prod_bfr_bd (size:128b/16B) */
1675 struct rx_prod_bfr_bd {
1676 /* This value identifies the type of buffer descriptor. */
1677 uint16_t flags_type;
1678 /* This value identifies the type of buffer descriptor. */
1679 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
1680 #define RX_PROD_BFR_BD_TYPE_SFT 0
1682 * Indicates that this BD is 16B long and is an RX
1683 * Producer Buffer BD.
1685 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
1686 #define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
1687 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
1688 #define RX_PROD_BFR_BD_FLAGS_SFT 6
1690 * This is the length in Bytes of the host physical buffer where
1691 * data for the packet may be placed in host memory.
1694 /* This field is not used. */
1697 * This is the host physical address where data for the packet may
1698 * by placed in host memory.
1701 } __attribute__((packed));
1703 /* rx_prod_agg_bd (size:128b/16B) */
1704 struct rx_prod_agg_bd {
1705 /* This value identifies the type of buffer descriptor. */
1706 uint16_t flags_type;
1707 /* This value identifies the type of buffer descriptor. */
1708 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
1709 #define RX_PROD_AGG_BD_TYPE_SFT 0
1711 * Indicates that this BD is 16B long and is an
1712 * RX Producer Assembly Buffer Descriptor.
1714 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
1715 #define RX_PROD_AGG_BD_TYPE_LAST \
1716 RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
1717 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
1718 #define RX_PROD_AGG_BD_FLAGS_SFT 6
1720 * If set to 1, the packet write will be padded out to the
1721 * nearest cache-line with zero value padding.
1723 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
1725 * This is the length in Bytes of the host physical buffer where
1726 * data for the packet may be placed in host memory.
1730 * The opaque data field is pass through to the completion and can be
1731 * used for any data that the driver wants to associate with this
1732 * receive assembly buffer.
1736 * This is the host physical address where data for the packet may
1737 * by placed in host memory.
1740 } __attribute__((packed));
1742 /* cmpl_base (size:128b/16B) */
1746 * This field indicates the exact type of the completion.
1747 * By convention, the LSB identifies the length of the
1748 * record in 16B units. Even values indicate 16B
1749 * records. Odd values indicate 32B
1752 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
1753 #define CMPL_BASE_TYPE_SFT 0
1756 * Completion of TX packet. Length = 16B
1758 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
1761 * Completion of and L2 RX packet. Length = 32B
1763 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
1765 * RX Aggregation Buffer completion :
1766 * Completion of an L2 aggregation buffer in support of
1767 * TPA, HDS, or Jumbo packet completion. Length = 16B
1769 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
1771 * RX L2 TPA Start Completion:
1772 * Completion at the beginning of a TPA operation.
1775 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
1777 * RX L2 TPA End Completion:
1778 * Completion at the end of a TPA operation.
1781 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
1783 * Statistics Ejection Completion:
1784 * Completion of statistics data ejection buffer.
1787 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
1789 * HWRM Command Completion:
1790 * Completion of an HWRM command.
1792 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
1793 /* Forwarded HWRM Request */
1794 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
1795 /* Forwarded HWRM Response */
1796 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
1797 /* HWRM Asynchronous Event Information */
1798 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1799 /* CQ Notification */
1800 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
1801 /* SRQ Threshold Event */
1802 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
1803 /* DBQ Threshold Event */
1804 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
1805 /* QP Async Notification */
1806 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
1807 /* Function Async Notification */
1808 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
1809 #define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
1815 * This value is written by the NIC such that it will be different
1816 * for each pass through the completion queue. The even passes
1817 * will write 1. The odd passes will write 0.
1820 #define CMPL_BASE_V UINT32_C(0x1)
1821 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
1822 #define CMPL_BASE_INFO3_SFT 1
1825 } __attribute__((packed));
1827 /* tx_cmpl (size:128b/16B) */
1829 uint16_t flags_type;
1831 * This field indicates the exact type of the completion.
1832 * By convention, the LSB identifies the length of the
1833 * record in 16B units. Even values indicate 16B
1834 * records. Odd values indicate 32B
1837 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
1838 #define TX_CMPL_TYPE_SFT 0
1841 * Completion of TX packet. Length = 16B
1843 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
1844 #define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
1845 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1846 #define TX_CMPL_FLAGS_SFT 6
1848 * When this bit is '1', it indicates a packet that has an
1849 * error of some type. Type of error is indicated in
1852 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
1854 * When this bit is '1', it indicates that the packet completed
1855 * was transmitted using the push acceleration data provided
1856 * by the driver. When this bit is '0', it indicates that the
1857 * packet had not push acceleration data written or was executed
1858 * as a normal packet even though push data was provided.
1860 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
1861 /* unused1 is 16 b */
1864 * This is a copy of the opaque field from the first TX BD of this
1865 * transmitted packet.
1870 * This value is written by the NIC such that it will be different
1871 * for each pass through the completion queue. The even passes
1872 * will write 1. The odd passes will write 0.
1874 #define TX_CMPL_V UINT32_C(0x1)
1875 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1876 #define TX_CMPL_ERRORS_SFT 1
1878 * This error indicates that there was some sort of problem
1879 * with the BDs for the packet.
1881 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
1882 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
1884 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
1887 * BDs were not formatted correctly.
1889 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
1890 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \
1891 TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
1893 * When this bit is '1', it indicates that the length of
1894 * the packet was zero. No packet was transmitted.
1896 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
1898 * When this bit is '1', it indicates that the packet
1899 * was longer than the programmed limit in TDI. No
1900 * packet was transmitted.
1902 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
1904 * When this bit is '1', it indicates that one or more of the
1905 * BDs associated with this packet generated a PCI error.
1906 * This probably means the address was not valid.
1908 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
1910 * When this bit is '1', it indicates that the packet was longer
1911 * than indicated by the hint. No packet was transmitted.
1913 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
1915 * When this bit is '1', it indicates that the packet was
1916 * dropped due to Poison TLP error on one or more of the
1917 * TLPs in the PXP completion.
1919 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
1920 /* unused2 is 16 b */
1922 /* unused3 is 32 b */
1924 } __attribute__((packed));
1926 /* rx_pkt_cmpl (size:128b/16B) */
1927 struct rx_pkt_cmpl {
1928 uint16_t flags_type;
1930 * This field indicates the exact type of the completion.
1931 * By convention, the LSB identifies the length of the
1932 * record in 16B units. Even values indicate 16B
1933 * records. Odd values indicate 32B
1936 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
1937 #define RX_PKT_CMPL_TYPE_SFT 0
1940 * Completion of and L2 RX packet. Length = 32B
1942 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
1943 #define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
1944 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1945 #define RX_PKT_CMPL_FLAGS_SFT 6
1947 * When this bit is '1', it indicates a packet that has an
1948 * error of some type. Type of error is indicated in
1951 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
1952 /* This field indicates how the packet was placed in the buffer. */
1953 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
1954 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
1957 * Packet was placed using normal algorithm.
1959 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
1962 * Packet was placed using jumbo algorithm.
1964 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
1966 * Header/Data Separation:
1967 * Packet was placed using Header/Data separation algorithm.
1968 * The separation location is indicated by the itype field.
1970 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
1971 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST \
1972 RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
1973 /* This bit is '1' if the RSS field in this completion is valid. */
1974 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
1976 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
1978 * This value indicates what the inner packet determined for the
1981 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
1982 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
1985 * Indicates that the packet type was not known.
1987 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN \
1988 (UINT32_C(0x0) << 12)
1991 * Indicates that the packet was an IP packet, but further
1992 * classification was not possible.
1994 #define RX_PKT_CMPL_FLAGS_ITYPE_IP \
1995 (UINT32_C(0x1) << 12)
1998 * Indicates that the packet was IP and TCP.
1999 * This indicates that the payload_offset field is valid.
2001 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP \
2002 (UINT32_C(0x2) << 12)
2005 * Indicates that the packet was IP and UDP.
2006 * This indicates that the payload_offset field is valid.
2008 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP \
2009 (UINT32_C(0x3) << 12)
2012 * Indicates that the packet was recognized as a FCoE.
2013 * This also indicates that the payload_offset field is valid.
2015 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE \
2016 (UINT32_C(0x4) << 12)
2019 * Indicates that the packet was recognized as a RoCE.
2020 * This also indicates that the payload_offset field is valid.
2022 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE \
2023 (UINT32_C(0x5) << 12)
2026 * Indicates that the packet was recognized as ICMP.
2027 * This indicates that the payload_offset field is valid.
2029 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP \
2030 (UINT32_C(0x7) << 12)
2032 * PtP packet wo/timestamp:
2033 * Indicates that the packet was recognized as a PtP
2036 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \
2037 (UINT32_C(0x8) << 12)
2039 * PtP packet w/timestamp:
2040 * Indicates that the packet was recognized as a PtP
2041 * packet and that a timestamp was taken for the packet.
2043 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \
2044 (UINT32_C(0x9) << 12)
2045 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST \
2046 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
2048 * This is the length of the data for the packet stored in the
2049 * buffer(s) identified by the opaque value. This includes
2050 * the packet BD and any associated buffer BDs. This does not include
2051 * the the length of any data places in aggregation BDs.
2055 * This is a copy of the opaque field from the RX BD this completion
2059 uint8_t agg_bufs_v1;
2061 * This value is written by the NIC such that it will be different
2062 * for each pass through the completion queue. The even passes
2063 * will write 1. The odd passes will write 0.
2065 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
2067 * This value is the number of aggregation buffers that follow this
2068 * entry in the completion ring that are a part of this packet.
2069 * If the value is zero, then the packet is completely contained
2070 * in the buffer space provided for the packet in the RX ring.
2072 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
2073 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
2074 /* unused1 is 2 b */
2075 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
2076 #define RX_PKT_CMPL_UNUSED1_SFT 6
2078 * This is the RSS hash type for the packet. The value is packed
2079 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2081 * The value of tuple_extrac_op provides the information about
2082 * what fields the hash was computed on.
2083 * * 0: The RSS hash was computed over source IP address,
2084 * destination IP address, source port, and destination port of inner
2085 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2086 * the packet headers are considered inner packet headers for the RSS
2087 * hash computation purpose.
2088 * * 1: The RSS hash was computed over source IP address and destination
2089 * IP address of inner IP header. Note: For non-tunneled packets,
2090 * the packet headers are considered inner packet headers for the RSS
2091 * hash computation purpose.
2092 * * 2: The RSS hash was computed over source IP address,
2093 * destination IP address, source port, and destination port of
2094 * IP and TCP or UDP headers of outer tunnel headers.
2095 * Note: For non-tunneled packets, this value is not applicable.
2096 * * 3: The RSS hash was computed over source IP address and
2097 * destination IP address of IP header of outer tunnel headers.
2098 * Note: For non-tunneled packets, this value is not applicable.
2100 * Note that 4-tuples values listed above are applicable
2101 * for layer 4 protocols supported and enabled for RSS in the hardware,
2102 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2103 * enabled for TCP traffic only, then the values of tuple_extract_op
2104 * corresponding to 4-tuples are only valid for TCP traffic.
2106 uint8_t rss_hash_type;
2108 * This value indicates the offset in bytes from the beginning of the packet
2109 * where the inner payload starts. This value is valid for TCP, UDP,
2110 * FCoE, and RoCE packets.
2112 * A value of zero indicates that header is 256B into the packet.
2114 uint8_t payload_offset;
2115 /* unused2 is 8 b */
2118 * This value is the RSS hash value calculated for the packet
2119 * based on the mode bits and key value in the VNIC.
2122 } __attribute__((packed));
2124 /* rx_pkt_cmpl_hi (size:128b/16B) */
2125 struct rx_pkt_cmpl_hi {
2128 * This indicates that the ip checksum was calculated for the
2129 * inner packet and that the ip_cs_error field indicates if there
2132 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2134 * This indicates that the TCP, UDP or ICMP checksum was
2135 * calculated for the inner packet and that the l4_cs_error field
2136 * indicates if there was an error.
2138 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2140 * This indicates that the ip checksum was calculated for the
2141 * tunnel header and that the t_ip_cs_error field indicates if there
2144 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2146 * This indicates that the UDP checksum was
2147 * calculated for the tunnel packet and that the t_l4_cs_error field
2148 * indicates if there was an error.
2150 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2151 /* This value indicates what format the metadata field is. */
2152 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2153 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
2154 /* No metadata informtaion. Value is zero. */
2155 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
2157 * The metadata field contains the VLAN tag and TPID value.
2158 * - metadata[11:0] contains the vlan VID value.
2159 * - metadata[12] contains the vlan DE value.
2160 * - metadata[15:13] contains the vlan PRI value.
2161 * - metadata[31:16] contains the vlan TPID value.
2163 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
2164 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
2165 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
2167 * This field indicates the IP type for the inner-most IP header.
2168 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2169 * This value is only valid if itype indicates a packet
2170 * with an IP header.
2172 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2174 * This is data from the CFA block as indicated by the meta_format
2178 /* When meta_format=1, this value is the VLAN VID. */
2179 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2180 #define RX_PKT_CMPL_METADATA_VID_SFT 0
2181 /* When meta_format=1, this value is the VLAN DE. */
2182 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
2183 /* When meta_format=1, this value is the VLAN PRI. */
2184 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2185 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
2186 /* When meta_format=1, this value is the VLAN TPID. */
2187 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2188 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
2191 * This value is written by the NIC such that it will be different
2192 * for each pass through the completion queue. The even passes
2193 * will write 1. The odd passes will write 0.
2195 #define RX_PKT_CMPL_V2 \
2197 #define RX_PKT_CMPL_ERRORS_MASK \
2199 #define RX_PKT_CMPL_ERRORS_SFT 1
2201 * This error indicates that there was some sort of problem with
2202 * the BDs for the packet that was found after part of the
2203 * packet was already placed. The packet should be treated as
2206 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK \
2208 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2209 /* No buffer error */
2210 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
2211 (UINT32_C(0x0) << 1)
2214 * Packet did not fit into packet buffer provided.
2215 * For regular placement, this means the packet did not fit
2216 * in the buffer provided. For HDS and jumbo placement, this
2217 * means that the packet could not be placed into 7 physical
2220 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
2221 (UINT32_C(0x1) << 1)
2224 * All BDs needed for the packet were not on-chip when
2225 * the packet arrived.
2227 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2228 (UINT32_C(0x2) << 1)
2231 * BDs were not formatted correctly.
2233 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
2234 (UINT32_C(0x3) << 1)
2235 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
2236 RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
2238 * This indicates that there was an error in the IP header
2241 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR \
2244 * This indicates that there was an error in the TCP, UDP
2247 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR \
2250 * This indicates that there was an error in the tunnel
2251 * IP header checksum.
2253 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR \
2256 * This indicates that there was an error in the tunnel
2259 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR \
2262 * This indicates that there was a CRC error on either an FCoE
2263 * or RoCE packet. The itype indicates the packet type.
2265 #define RX_PKT_CMPL_ERRORS_CRC_ERROR \
2268 * This indicates that there was an error in the tunnel
2269 * portion of the packet when this
2270 * field is non-zero.
2272 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK \
2274 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
2276 * No additional error occurred on the tunnel portion
2277 * of the packet of the packet does not have a tunnel.
2279 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
2280 (UINT32_C(0x0) << 9)
2282 * Indicates that IP header version does not match
2283 * expectation from L2 Ethertype for IPv4 and IPv6
2284 * in the tunnel header.
2286 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \
2287 (UINT32_C(0x1) << 9)
2289 * Indicates that header length is out of range in the
2290 * tunnel header. Valid for
2293 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \
2294 (UINT32_C(0x2) << 9)
2296 * Indicates that the physical packet is shorter than that
2297 * claimed by the PPPoE header length for a tunnel PPPoE
2300 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR \
2301 (UINT32_C(0x3) << 9)
2303 * Indicates that physical packet is shorter than that claimed
2304 * by the tunnel l3 header length. Valid for IPv4, or IPv6
2305 * tunnel packet packets.
2307 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \
2308 (UINT32_C(0x4) << 9)
2310 * Indicates that the physical packet is shorter than that
2311 * claimed by the tunnel UDP header length for a tunnel
2312 * UDP packet that is not fragmented.
2314 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \
2315 (UINT32_C(0x5) << 9)
2317 * indicates that the IPv4 TTL or IPv6 hop limit check
2318 * have failed (e.g. TTL = 0) in the tunnel header. Valid
2319 * for IPv4, and IPv6.
2321 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \
2322 (UINT32_C(0x6) << 9)
2323 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST \
2324 RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
2326 * This indicates that there was an error in the inner
2327 * portion of the packet when this
2328 * field is non-zero.
2330 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK \
2332 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
2334 * No additional error occurred on the tunnel portion
2335 * of the packet of the packet does not have a tunnel.
2337 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
2338 (UINT32_C(0x0) << 12)
2340 * Indicates that IP header version does not match
2341 * expectation from L2 Ethertype for IPv4 and IPv6 or that
2342 * option other than VFT was parsed on
2345 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION \
2346 (UINT32_C(0x1) << 12)
2348 * indicates that header length is out of range. Valid for
2351 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \
2352 (UINT32_C(0x2) << 12)
2354 * indicates that the IPv4 TTL or IPv6 hop limit check
2355 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
2357 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL \
2358 (UINT32_C(0x3) << 12)
2360 * Indicates that physical packet is shorter than that
2361 * claimed by the l3 header length. Valid for IPv4,
2362 * IPv6 packet or RoCE packets.
2364 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \
2365 (UINT32_C(0x4) << 12)
2367 * Indicates that the physical packet is shorter than that
2368 * claimed by the UDP header length for a UDP packet that is
2371 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \
2372 (UINT32_C(0x5) << 12)
2374 * Indicates that TCP header length > IP payload. Valid for
2377 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \
2378 (UINT32_C(0x6) << 12)
2379 /* Indicates that TCP header length < 5. Valid for TCP. */
2380 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
2381 (UINT32_C(0x7) << 12)
2383 * Indicates that TCP option headers result in a TCP header
2384 * size that does not match data offset in TCP header. Valid
2387 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
2388 (UINT32_C(0x8) << 12)
2389 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST \
2390 RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
2392 * This field identifies the CFA action rule that was used for this
2398 * This value holds the reordering sequence number for the packet.
2399 * If the reordering sequence is not valid, then this value is zero.
2400 * The reordering domain for the packet is in the bottom 8 to 10b of
2401 * the rss_hash value. The bottom 20b of this value contain the
2402 * ordering domain value for the packet.
2404 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
2405 #define RX_PKT_CMPL_REORDER_SFT 0
2406 } __attribute__((packed));
2408 /* rx_tpa_start_cmpl (size:128b/16B) */
2409 struct rx_tpa_start_cmpl {
2410 uint16_t flags_type;
2412 * This field indicates the exact type of the completion.
2413 * By convention, the LSB identifies the length of the
2414 * record in 16B units. Even values indicate 16B
2415 * records. Odd values indicate 32B
2418 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
2419 #define RX_TPA_START_CMPL_TYPE_SFT 0
2421 * RX L2 TPA Start Completion:
2422 * Completion at the beginning of a TPA operation.
2425 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
2426 #define RX_TPA_START_CMPL_TYPE_LAST \
2427 RX_TPA_START_CMPL_TYPE_RX_TPA_START
2428 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2429 #define RX_TPA_START_CMPL_FLAGS_SFT 6
2430 /* This bit will always be '0' for TPA start completions. */
2431 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
2432 /* This field indicates how the packet was placed in the buffer. */
2433 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2434 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
2437 * TPA Packet was placed using jumbo algorithm. This means
2438 * that the first buffer will be filled with data before
2439 * moving to aggregation buffers. Each aggregation buffer
2440 * will be filled before moving to the next aggregation
2443 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \
2444 (UINT32_C(0x1) << 7)
2446 * Header/Data Separation:
2447 * Packet was placed using Header/Data separation algorithm.
2448 * The separation location is indicated by the itype field.
2450 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \
2451 (UINT32_C(0x2) << 7)
2454 * Packet will be placed using GRO/Jumbo where the first
2455 * packet is filled with data. Subsequent packets will be
2456 * placed such that any one packet does not span two
2457 * aggregation buffers unless it starts at the beginning of
2458 * an aggregation buffer.
2460 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2461 (UINT32_C(0x5) << 7)
2463 * GRO/Header-Data Separation:
2464 * Packet will be placed using GRO/HDS where the header
2465 * is in the first packet.
2466 * Payload of each packet will be
2467 * placed such that any one packet does not span two
2468 * aggregation buffers unless it starts at the beginning of
2469 * an aggregation buffer.
2471 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2472 (UINT32_C(0x6) << 7)
2473 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \
2474 RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
2475 /* This bit is '1' if the RSS field in this completion is valid. */
2476 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
2478 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
2480 * This value indicates what the inner packet determined for the
2483 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2484 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
2487 * Indicates that the packet was IP and TCP.
2489 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \
2490 (UINT32_C(0x2) << 12)
2491 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \
2492 RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
2494 * This value indicates the amount of packet data written to the
2495 * buffer the opaque field in this completion corresponds to.
2499 * This is a copy of the opaque field from the RX BD this completion
2504 * This value is written by the NIC such that it will be different
2505 * for each pass through the completion queue. The even passes
2506 * will write 1. The odd passes will write 0.
2510 * This value is written by the NIC such that it will be different
2511 * for each pass through the completion queue. The even passes
2512 * will write 1. The odd passes will write 0.
2514 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
2515 #define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1
2517 * This is the RSS hash type for the packet. The value is packed
2518 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
2520 * The value of tuple_extrac_op provides the information about
2521 * what fields the hash was computed on.
2522 * * 0: The RSS hash was computed over source IP address,
2523 * destination IP address, source port, and destination port of inner
2524 * IP and TCP or UDP headers. Note: For non-tunneled packets,
2525 * the packet headers are considered inner packet headers for the RSS
2526 * hash computation purpose.
2527 * * 1: The RSS hash was computed over source IP address and destination
2528 * IP address of inner IP header. Note: For non-tunneled packets,
2529 * the packet headers are considered inner packet headers for the RSS
2530 * hash computation purpose.
2531 * * 2: The RSS hash was computed over source IP address,
2532 * destination IP address, source port, and destination port of
2533 * IP and TCP or UDP headers of outer tunnel headers.
2534 * Note: For non-tunneled packets, this value is not applicable.
2535 * * 3: The RSS hash was computed over source IP address and
2536 * destination IP address of IP header of outer tunnel headers.
2537 * Note: For non-tunneled packets, this value is not applicable.
2539 * Note that 4-tuples values listed above are applicable
2540 * for layer 4 protocols supported and enabled for RSS in the hardware,
2541 * HWRM firmware, and drivers. For example, if RSS hash is supported and
2542 * enabled for TCP traffic only, then the values of tuple_extract_op
2543 * corresponding to 4-tuples are only valid for TCP traffic.
2545 uint8_t rss_hash_type;
2547 * This is the aggregation ID that the completion is associated
2548 * with. Use this number to correlate the TPA start completion
2549 * with the TPA end completion.
2552 /* unused2 is 9 b */
2553 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
2554 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
2556 * This is the aggregation ID that the completion is associated
2557 * with. Use this number to correlate the TPA start completion
2558 * with the TPA end completion.
2560 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
2561 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
2563 * This value is the RSS hash value calculated for the packet
2564 * based on the mode bits and key value in the VNIC.
2567 } __attribute__((packed));
2569 /* rx_tpa_start_cmpl_hi (size:128b/16B) */
2570 struct rx_tpa_start_cmpl_hi {
2573 * This indicates that the ip checksum was calculated for the
2574 * inner packet and that the sum passed for all segments
2575 * included in the aggregation.
2577 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
2579 * This indicates that the TCP, UDP or ICMP checksum was
2580 * calculated for the inner packet and that the sum passed
2581 * for all segments included in the aggregation.
2583 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
2585 * This indicates that the ip checksum was calculated for the
2586 * tunnel header and that the sum passed for all segments
2587 * included in the aggregation.
2589 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
2591 * This indicates that the UDP checksum was
2592 * calculated for the tunnel packet and that the sum passed for
2593 * all segments included in the aggregation.
2595 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
2596 /* This value indicates what format the metadata field is. */
2597 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
2598 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
2599 /* No metadata informtaion. Value is zero. */
2600 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
2601 (UINT32_C(0x0) << 4)
2603 * The metadata field contains the VLAN tag and TPID value.
2604 * - metadata[11:0] contains the vlan VID value.
2605 * - metadata[12] contains the vlan DE value.
2606 * - metadata[15:13] contains the vlan PRI value.
2607 * - metadata[31:16] contains the vlan TPID value.
2609 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
2610 (UINT32_C(0x1) << 4)
2611 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
2612 RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
2614 * This field indicates the IP type for the inner-most IP header.
2615 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
2617 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
2619 * This is data from the CFA block as indicated by the meta_format
2623 /* When meta_format=1, this value is the VLAN VID. */
2624 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
2625 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
2626 /* When meta_format=1, this value is the VLAN DE. */
2627 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
2628 /* When meta_format=1, this value is the VLAN PRI. */
2629 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
2630 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
2631 /* When meta_format=1, this value is the VLAN TPID. */
2632 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
2633 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
2636 * This value is written by the NIC such that it will be different
2637 * for each pass through the completion queue. The even passes
2638 * will write 1. The odd passes will write 0.
2640 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
2642 * This field identifies the CFA action rule that was used for this
2647 * This is the size in bytes of the inner most L4 header.
2648 * This can be subtracted from the payload_offset to determine
2649 * the start of the inner most L4 header.
2651 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
2653 * This is the offset from the beginning of the packet in bytes for
2654 * the outer L3 header. If there is no outer L3 header, then this
2657 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
2658 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
2660 * This is the offset from the beginning of the packet in bytes for
2661 * the inner most L2 header.
2663 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
2664 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
2666 * This is the offset from the beginning of the packet in bytes for
2667 * the inner most L3 header.
2669 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
2670 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
2672 * This is the size in bytes of the inner most L4 header.
2673 * This can be subtracted from the payload_offset to determine
2674 * the start of the inner most L4 header.
2676 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
2677 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
2678 } __attribute__((packed));
2680 /* rx_tpa_end_cmpl (size:128b/16B) */
2681 struct rx_tpa_end_cmpl {
2682 uint16_t flags_type;
2684 * This field indicates the exact type of the completion.
2685 * By convention, the LSB identifies the length of the
2686 * record in 16B units. Even values indicate 16B
2687 * records. Odd values indicate 32B
2690 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
2691 #define RX_TPA_END_CMPL_TYPE_SFT 0
2693 * RX L2 TPA End Completion:
2694 * Completion at the end of a TPA operation.
2697 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
2698 #define RX_TPA_END_CMPL_TYPE_LAST \
2699 RX_TPA_END_CMPL_TYPE_RX_TPA_END
2700 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
2701 #define RX_TPA_END_CMPL_FLAGS_SFT 6
2703 * When this bit is '1', it indicates a packet that has an
2704 * error of some type. Type of error is indicated in
2707 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
2708 /* This field indicates how the packet was placed in the buffer. */
2709 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
2710 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
2713 * TPA Packet was placed using jumbo algorithm. This means
2714 * that the first buffer will be filled with data before
2715 * moving to aggregation buffers. Each aggregation buffer
2716 * will be filled before moving to the next aggregation
2719 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO \
2720 (UINT32_C(0x1) << 7)
2722 * Header/Data Separation:
2723 * Packet was placed using Header/Data separation algorithm.
2724 * The separation location is indicated by the itype field.
2726 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \
2727 (UINT32_C(0x2) << 7)
2730 * Packet will be placed using GRO/Jumbo where the first
2731 * packet is filled with data. Subsequent packets will be
2732 * placed such that any one packet does not span two
2733 * aggregation buffers unless it starts at the beginning of
2734 * an aggregation buffer.
2736 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \
2737 (UINT32_C(0x5) << 7)
2739 * GRO/Header-Data Separation:
2740 * Packet will be placed using GRO/HDS where the header
2741 * is in the first packet.
2742 * Payload of each packet will be
2743 * placed such that any one packet does not span two
2744 * aggregation buffers unless it starts at the beginning of
2745 * an aggregation buffer.
2747 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \
2748 (UINT32_C(0x6) << 7)
2749 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \
2750 RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
2752 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
2753 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
2755 * This value indicates what the inner packet determined for the
2758 * Indicates that the packet was IP and TCP. This indicates
2759 * that the ip_cs field is valid and that the tcp_udp_cs
2760 * field is valid and contains the TCP checksum.
2761 * This also indicates that the payload_offset field is valid.
2763 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
2764 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
2766 * This value is zero for TPA End completions.
2767 * There is no data in the buffer that corresponds to the opaque
2768 * value in this completion.
2772 * This is a copy of the opaque field from the RX BD this completion
2777 * This value is written by the NIC such that it will be different
2778 * for each pass through the completion queue. The even passes
2779 * will write 1. The odd passes will write 0.
2781 uint8_t agg_bufs_v1;
2783 * This value is written by the NIC such that it will be different
2784 * for each pass through the completion queue. The even passes
2785 * will write 1. The odd passes will write 0.
2787 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
2789 * This value is the number of aggregation buffers that follow this
2790 * entry in the completion ring that are a part of this aggregation
2792 * If the value is zero, then the packet is completely contained
2793 * in the buffer space provided in the aggregation start completion.
2795 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
2796 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
2797 /* This value is the number of segments in the TPA operation. */
2800 * This value indicates the offset in bytes from the beginning of the packet
2801 * where the inner payload starts. This value is valid for TCP, UDP,
2802 * FCoE, and RoCE packets.
2804 * A value of zero indicates an offset of 256 bytes.
2806 uint8_t payload_offset;
2808 /* unused2 is 1 b */
2809 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
2811 * This is the aggregation ID that the completion is associated
2812 * with. Use this number to correlate the TPA start completion
2813 * with the TPA end completion.
2815 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
2816 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
2818 * For non-GRO packets, this value is the
2819 * timestamp delta between earliest and latest timestamp values for
2820 * TPA packet. If packets were not time stamped, then delta will be
2823 * For GRO packets, this field is zero except for the following
2826 * Timestamp present indication. When '0', no Timestamp
2827 * option is in the packet. When '1', then a Timestamp
2828 * option is present in the packet.
2831 } __attribute__((packed));
2833 /* rx_tpa_end_cmpl_hi (size:128b/16B) */
2834 struct rx_tpa_end_cmpl_hi {
2836 * This value is the number of duplicate ACKs that have been
2837 * received as part of the TPA operation.
2839 uint32_t tpa_dup_acks;
2841 * This value is the number of duplicate ACKs that have been
2842 * received as part of the TPA operation.
2844 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
2845 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
2847 * This value is the valid when TPA completion is active. It
2848 * indicates the length of the longest segment of the TPA operation
2849 * for LRO mode and the length of the first segment in GRO mode.
2851 * This value may be used by GRO software to re-construct the original
2852 * packet stream from the TPA packet. This is the length of all
2853 * but the last segment for GRO. In LRO mode this value may be used
2854 * to indicate MSS size to the stack.
2856 uint16_t tpa_seg_len;
2857 /* unused4 is 16 b */
2861 * This value is written by the NIC such that it will be different
2862 * for each pass through the completion queue. The even passes
2863 * will write 1. The odd passes will write 0.
2865 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
2866 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
2867 #define RX_TPA_END_CMPL_ERRORS_SFT 1
2869 * This error indicates that there was some sort of problem with
2870 * the BDs for the packet that was found after part of the
2871 * packet was already placed. The packet should be treated as
2874 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
2875 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
2877 * This error occurs when there is a fatal HW problem in
2878 * the chip only. It indicates that there were not
2879 * BDs on chip but that there was adequate reservation.
2880 * provided by the TPA block.
2882 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
2883 (UINT32_C(0x2) << 1)
2885 * This error occurs when TPA block was not configured to
2886 * reserve adequate BDs for TPA operations on this RX
2887 * ring. All data for the TPA operation was not placed.
2889 * This error can also be generated when the number of
2890 * segments is not programmed correctly in TPA and the
2891 * 33 total aggregation buffers allowed for the TPA
2892 * operation has been exceeded.
2894 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
2895 (UINT32_C(0x4) << 1)
2896 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
2897 RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
2898 /* unused5 is 16 b */
2901 * This is the opaque value that was completed for the TPA start
2902 * completion that corresponds to this TPA end completion.
2904 uint32_t start_opaque;
2905 } __attribute__((packed));
2907 /* rx_abuf_cmpl (size:128b/16B) */
2908 struct rx_abuf_cmpl {
2911 * This field indicates the exact type of the completion.
2912 * By convention, the LSB identifies the length of the
2913 * record in 16B units. Even values indicate 16B
2914 * records. Odd values indicate 32B
2917 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
2918 #define RX_ABUF_CMPL_TYPE_SFT 0
2920 * RX Aggregation Buffer completion :
2921 * Completion of an L2 aggregation buffer in support of
2922 * TPA, HDS, or Jumbo packet completion. Length = 16B
2924 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
2925 #define RX_ABUF_CMPL_TYPE_LAST RX_ABUF_CMPL_TYPE_RX_AGG
2927 * This is the length of the data for the packet stored in this
2928 * aggregation buffer identified by the opaque value. This does not
2929 * include the length of any
2930 * data placed in other aggregation BDs or in the packet or buffer
2931 * BDs. This length does not include any space added due to
2932 * hdr_offset register during HDS placement mode.
2936 * This is a copy of the opaque field from the RX BD this aggregation
2937 * buffer corresponds to.
2942 * This value is written by the NIC such that it will be different
2943 * for each pass through the completion queue. The even passes
2944 * will write 1. The odd passes will write 0.
2946 #define RX_ABUF_CMPL_V UINT32_C(0x1)
2947 /* unused3 is 32 b */
2949 } __attribute__((packed));
2951 /* eject_cmpl (size:128b/16B) */
2955 * This field indicates the exact type of the completion.
2956 * By convention, the LSB identifies the length of the
2957 * record in 16B units. Even values indicate 16B
2958 * records. Odd values indicate 32B
2961 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
2962 #define EJECT_CMPL_TYPE_SFT 0
2964 * Statistics Ejection Completion:
2965 * Completion of statistics data ejection buffer.
2968 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
2969 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
2971 * This is the length of the statistics data stored in this
2976 * This is a copy of the opaque field from the RX BD this ejection
2977 * buffer corresponds to.
2982 * This value is written by the NIC such that it will be different
2983 * for each pass through the completion queue. The even passes
2984 * will write 1. The odd passes will write 0.
2986 #define EJECT_CMPL_V UINT32_C(0x1)
2987 /* unused3 is 32 b */
2989 } __attribute__((packed));
2991 /* hwrm_cmpl (size:128b/16B) */
2995 * This field indicates the exact type of the completion.
2996 * By convention, the LSB identifies the length of the
2997 * record in 16B units. Even values indicate 16B
2998 * records. Odd values indicate 32B
3001 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
3002 #define HWRM_CMPL_TYPE_SFT 0
3004 * HWRM Command Completion:
3005 * Completion of an HWRM command.
3007 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
3008 #define HWRM_CMPL_TYPE_LAST HWRM_CMPL_TYPE_HWRM_DONE
3009 /* This is the sequence_id of the HWRM command that has completed. */
3010 uint16_t sequence_id;
3011 /* unused2 is 32 b */
3015 * This value is written by the NIC such that it will be different
3016 * for each pass through the completion queue. The even passes
3017 * will write 1. The odd passes will write 0.
3019 #define HWRM_CMPL_V UINT32_C(0x1)
3020 /* unused4 is 32 b */
3022 } __attribute__((packed));
3024 /* hwrm_fwd_req_cmpl (size:128b/16B) */
3025 struct hwrm_fwd_req_cmpl {
3027 * This field indicates the exact type of the completion.
3028 * By convention, the LSB identifies the length of the
3029 * record in 16B units. Even values indicate 16B
3030 * records. Odd values indicate 32B
3033 uint16_t req_len_type;
3035 * This field indicates the exact type of the completion.
3036 * By convention, the LSB identifies the length of the
3037 * record in 16B units. Even values indicate 16B
3038 * records. Odd values indicate 32B
3041 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
3042 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
3043 /* Forwarded HWRM Request */
3044 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
3045 #define HWRM_FWD_REQ_CMPL_TYPE_LAST \
3046 HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
3047 /* Length of forwarded request in bytes. */
3048 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
3049 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
3051 * Source ID of this request.
3052 * Typically used in forwarding requests and responses.
3053 * 0x0 - 0xFFF8 - Used for function ids
3054 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3058 /* unused1 is 32 b */
3060 /* Address of forwarded request. */
3061 uint32_t req_buf_addr_v[2];
3063 * This value is written by the NIC such that it will be different
3064 * for each pass through the completion queue. The even passes
3065 * will write 1. The odd passes will write 0.
3067 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
3068 /* Address of forwarded request. */
3069 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3070 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
3071 } __attribute__((packed));
3073 /* hwrm_fwd_resp_cmpl (size:128b/16B) */
3074 struct hwrm_fwd_resp_cmpl {
3077 * This field indicates the exact type of the completion.
3078 * By convention, the LSB identifies the length of the
3079 * record in 16B units. Even values indicate 16B
3080 * records. Odd values indicate 32B
3083 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
3084 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
3085 /* Forwarded HWRM Response */
3086 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
3087 #define HWRM_FWD_RESP_CMPL_TYPE_LAST \
3088 HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
3090 * Source ID of this response.
3091 * Typically used in forwarding requests and responses.
3092 * 0x0 - 0xFFF8 - Used for function ids
3093 * 0xFFF8 - 0xFFFE - Reserved for internal processors
3097 /* Length of forwarded response in bytes. */
3099 /* unused2 is 16 b */
3101 /* Address of forwarded request. */
3102 uint32_t resp_buf_addr_v[2];
3104 * This value is written by the NIC such that it will be different
3105 * for each pass through the completion queue. The even passes
3106 * will write 1. The odd passes will write 0.
3108 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
3109 /* Address of forwarded request. */
3110 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
3111 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
3112 } __attribute__((packed));
3114 /* hwrm_async_event_cmpl (size:128b/16B) */
3115 struct hwrm_async_event_cmpl {
3118 * This field indicates the exact type of the completion.
3119 * By convention, the LSB identifies the length of the
3120 * record in 16B units. Even values indicate 16B
3121 * records. Odd values indicate 32B
3124 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
3125 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
3126 /* HWRM Asynchronous Event Information */
3127 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
3128 #define HWRM_ASYNC_EVENT_CMPL_TYPE_LAST \
3129 HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
3130 /* Identifiers of events. */
3132 /* Link status changed */
3133 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE \
3135 /* Link MTU changed */
3136 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE \
3138 /* Link speed changed */
3139 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE \
3141 /* DCB Configuration changed */
3142 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE \
3144 /* Port connection not allowed */
3145 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3147 /* Link speed configuration was not allowed */
3148 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3150 /* Link speed configuration change */
3151 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3153 /* Port PHY configuration change */
3154 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \
3156 /* Function driver unloaded */
3157 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
3159 /* Function driver loaded */
3160 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD \
3162 /* Function FLR related processing has completed */
3163 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3165 /* PF driver unloaded */
3166 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD \
3168 /* PF driver loaded */
3169 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD \
3171 /* VF Function Level Reset (FLR) */
3172 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR \
3174 /* VF MAC Address Change */
3175 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE \
3177 /* PF-VF communication channel status change. */
3178 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
3180 /* VF Configuration Change */
3181 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE \
3183 /* LLFC/PFC Configuration Change */
3184 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE \
3187 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
3189 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LAST \
3190 HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
3191 /* Event specific data */
3192 uint32_t event_data2;
3195 * This value is written by the NIC such that it will be different
3196 * for each pass through the completion queue. The even passes
3197 * will write 1. The odd passes will write 0.
3199 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
3201 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
3202 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
3203 /* 8-lsb timestamp from POR (100-msec resolution) */
3204 uint8_t timestamp_lo;
3205 /* 16-lsb timestamp from POR (100-msec resolution) */
3206 uint16_t timestamp_hi;
3207 /* Event specific data */
3208 uint32_t event_data1;
3209 } __attribute__((packed));
3211 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
3212 struct hwrm_async_event_cmpl_link_status_change {
3215 * This field indicates the exact type of the completion.
3216 * By convention, the LSB identifies the length of the
3217 * record in 16B units. Even values indicate 16B
3218 * records. Odd values indicate 32B
3221 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK \
3223 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
3224 /* HWRM Asynchronous Event Information */
3225 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3227 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST \
3228 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
3229 /* Identifiers of events. */
3231 /* Link status changed */
3232 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE \
3234 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST \
3235 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
3236 /* Event specific data */
3237 uint32_t event_data2;
3240 * This value is written by the NIC such that it will be different
3241 * for each pass through the completion queue. The even passes
3242 * will write 1. The odd passes will write 0.
3244 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V \
3247 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK \
3249 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
3250 /* 8-lsb timestamp from POR (100-msec resolution) */
3251 uint8_t timestamp_lo;
3252 /* 16-lsb timestamp from POR (100-msec resolution) */
3253 uint16_t timestamp_hi;
3254 /* Event specific data */
3255 uint32_t event_data1;
3256 /* Indicates link status change */
3257 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE \
3260 * If this bit set to 0, then it indicates that the link
3261 * was up and it went down.
3263 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN \
3266 * If this bit is set to 1, then it indicates that the link
3267 * was down and it went up.
3269 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP \
3271 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST \
3272 HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
3273 /* Indicates the physical port this link status change occur */
3274 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK \
3276 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT \
3279 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3281 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3283 } __attribute__((packed));
3285 /* hwrm_async_event_cmpl_link_mtu_change (size:128b/16B) */
3286 struct hwrm_async_event_cmpl_link_mtu_change {
3289 * This field indicates the exact type of the completion.
3290 * By convention, the LSB identifies the length of the
3291 * record in 16B units. Even values indicate 16B
3292 * records. Odd values indicate 32B
3295 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK \
3297 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
3298 /* HWRM Asynchronous Event Information */
3299 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3301 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_LAST \
3302 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT
3303 /* Identifiers of events. */
3305 /* Link MTU changed */
3306 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE \
3308 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LAST \
3309 HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE
3310 /* Event specific data */
3311 uint32_t event_data2;
3314 * This value is written by the NIC such that it will be different
3315 * for each pass through the completion queue. The even passes
3316 * will write 1. The odd passes will write 0.
3318 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
3320 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK \
3322 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
3323 /* 8-lsb timestamp from POR (100-msec resolution) */
3324 uint8_t timestamp_lo;
3325 /* 16-lsb timestamp from POR (100-msec resolution) */
3326 uint16_t timestamp_hi;
3327 /* Event specific data */
3328 uint32_t event_data1;
3329 /* The new MTU of the link in bytes. */
3330 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK \
3332 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
3333 } __attribute__((packed));
3335 /* hwrm_async_event_cmpl_link_speed_change (size:128b/16B) */
3336 struct hwrm_async_event_cmpl_link_speed_change {
3339 * This field indicates the exact type of the completion.
3340 * By convention, the LSB identifies the length of the
3341 * record in 16B units. Even values indicate 16B
3342 * records. Odd values indicate 32B
3345 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK \
3347 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
3348 /* HWRM Asynchronous Event Information */
3349 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3351 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_LAST \
3352 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT
3353 /* Identifiers of events. */
3355 /* Link speed changed */
3356 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE \
3358 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LAST \
3359 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE
3360 /* Event specific data */
3361 uint32_t event_data2;
3364 * This value is written by the NIC such that it will be different
3365 * for each pass through the completion queue. The even passes
3366 * will write 1. The odd passes will write 0.
3368 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V \
3371 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK \
3373 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
3374 /* 8-lsb timestamp from POR (100-msec resolution) */
3375 uint8_t timestamp_lo;
3376 /* 16-lsb timestamp from POR (100-msec resolution) */
3377 uint16_t timestamp_hi;
3378 /* Event specific data */
3379 uint32_t event_data1;
3381 * When this bit is '1', the link was forced to the
3382 * force_link_speed value.
3384 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE \
3386 /* The new link speed in 100 Mbps units. */
3387 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK \
3389 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT \
3391 /* 100Mb link speed */
3392 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB \
3393 (UINT32_C(0x1) << 1)
3394 /* 1Gb link speed */
3395 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB \
3396 (UINT32_C(0xa) << 1)
3397 /* 2Gb link speed */
3398 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB \
3399 (UINT32_C(0x14) << 1)
3400 /* 25Gb link speed */
3401 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB \
3402 (UINT32_C(0x19) << 1)
3403 /* 10Gb link speed */
3404 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB \
3405 (UINT32_C(0x64) << 1)
3406 /* 20Mb link speed */
3407 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB \
3408 (UINT32_C(0xc8) << 1)
3409 /* 25Gb link speed */
3410 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB \
3411 (UINT32_C(0xfa) << 1)
3412 /* 40Gb link speed */
3413 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB \
3414 (UINT32_C(0x190) << 1)
3415 /* 50Gb link speed */
3416 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB \
3417 (UINT32_C(0x1f4) << 1)
3418 /* 100Gb link speed */
3419 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB \
3420 (UINT32_C(0x3e8) << 1)
3421 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST \
3422 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
3424 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3425 UINT32_C(0xffff0000)
3426 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3428 } __attribute__((packed));
3430 /* hwrm_async_event_cmpl_dcb_config_change (size:128b/16B) */
3431 struct hwrm_async_event_cmpl_dcb_config_change {
3434 * This field indicates the exact type of the completion.
3435 * By convention, the LSB identifies the length of the
3436 * record in 16B units. Even values indicate 16B
3437 * records. Odd values indicate 32B
3440 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK \
3442 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
3443 /* HWRM Asynchronous Event Information */
3444 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3446 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_LAST \
3447 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3448 /* Identifiers of events. */
3450 /* DCB Configuration changed */
3451 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE \
3453 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_LAST \
3454 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE
3455 /* Event specific data */
3456 uint32_t event_data2;
3457 /* ETS configuration change */
3458 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS \
3460 /* PFC configuration change */
3461 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC \
3463 /* APP configuration change */
3464 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP \
3468 * This value is written by the NIC such that it will be different
3469 * for each pass through the completion queue. The even passes
3470 * will write 1. The odd passes will write 0.
3472 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V \
3475 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK \
3477 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
3478 /* 8-lsb timestamp from POR (100-msec resolution) */
3479 uint8_t timestamp_lo;
3480 /* 16-lsb timestamp from POR (100-msec resolution) */
3481 uint16_t timestamp_hi;
3482 /* Event specific data */
3483 uint32_t event_data1;
3485 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3487 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3489 /* Priority recommended for RoCE traffic */
3490 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK \
3492 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT \
3495 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE \
3496 (UINT32_C(0xff) << 16)
3497 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST \
3498 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
3499 /* Priority recommended for L2 traffic */
3500 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK \
3501 UINT32_C(0xff000000)
3502 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT \
3505 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE \
3506 (UINT32_C(0xff) << 24)
3507 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST \
3508 HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
3509 } __attribute__((packed));
3511 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
3512 struct hwrm_async_event_cmpl_port_conn_not_allowed {
3515 * This field indicates the exact type of the completion.
3516 * By convention, the LSB identifies the length of the
3517 * record in 16B units. Even values indicate 16B
3518 * records. Odd values indicate 32B
3521 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK \
3523 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT \
3525 /* HWRM Asynchronous Event Information */
3526 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3528 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST \
3529 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3530 /* Identifiers of events. */
3532 /* Port connection not allowed */
3533 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED \
3535 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST \
3536 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
3537 /* Event specific data */
3538 uint32_t event_data2;
3541 * This value is written by the NIC such that it will be different
3542 * for each pass through the completion queue. The even passes
3543 * will write 1. The odd passes will write 0.
3545 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V \
3548 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK \
3550 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
3551 /* 8-lsb timestamp from POR (100-msec resolution) */
3552 uint8_t timestamp_lo;
3553 /* 16-lsb timestamp from POR (100-msec resolution) */
3554 uint16_t timestamp_hi;
3555 /* Event specific data */
3556 uint32_t event_data1;
3558 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3560 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3563 * This value indicates the current port level enforcement policy
3564 * for the optics module when there is an optical module mismatch
3565 * and port is not connected.
3567 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK \
3569 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT \
3571 /* No enforcement */
3572 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE \
3573 (UINT32_C(0x0) << 16)
3574 /* Disable Transmit side Laser. */
3575 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX \
3576 (UINT32_C(0x1) << 16)
3577 /* Raise a warning message. */
3578 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG \
3579 (UINT32_C(0x2) << 16)
3580 /* Power down the module. */
3581 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN \
3582 (UINT32_C(0x3) << 16)
3583 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST \
3584 HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
3585 } __attribute__((packed));
3587 /* hwrm_async_event_cmpl_link_speed_cfg_not_allowed (size:128b/16B) */
3588 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
3591 * This field indicates the exact type of the completion.
3592 * By convention, the LSB identifies the length of the
3593 * record in 16B units. Even values indicate 16B
3594 * records. Odd values indicate 32B
3597 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK \
3599 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT \
3601 /* HWRM Asynchronous Event Information */
3602 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT \
3604 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_LAST \
3605 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
3606 /* Identifiers of events. */
3608 /* Link speed configuration was not allowed */
3609 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED \
3611 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LAST \
3612 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED
3613 /* Event specific data */
3614 uint32_t event_data2;
3617 * This value is written by the NIC such that it will be different
3618 * for each pass through the completion queue. The even passes
3619 * will write 1. The odd passes will write 0.
3621 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V \
3624 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK \
3626 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
3627 /* 8-lsb timestamp from POR (100-msec resolution) */
3628 uint8_t timestamp_lo;
3629 /* 16-lsb timestamp from POR (100-msec resolution) */
3630 uint16_t timestamp_hi;
3631 /* Event specific data */
3632 uint32_t event_data1;
3634 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK \
3636 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT \
3638 } __attribute__((packed));
3640 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
3641 struct hwrm_async_event_cmpl_link_speed_cfg_change {
3644 * This field indicates the exact type of the completion.
3645 * By convention, the LSB identifies the length of the
3646 * record in 16B units. Even values indicate 16B
3647 * records. Odd values indicate 32B
3650 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK \
3652 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT \
3654 /* HWRM Asynchronous Event Information */
3655 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3657 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST \
3658 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3659 /* Identifiers of events. */
3661 /* Link speed configuration change */
3662 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE \
3664 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST \
3665 HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
3666 /* Event specific data */
3667 uint32_t event_data2;
3670 * This value is written by the NIC such that it will be different
3671 * for each pass through the completion queue. The even passes
3672 * will write 1. The odd passes will write 0.
3674 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V \
3677 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK \
3679 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
3680 /* 8-lsb timestamp from POR (100-msec resolution) */
3681 uint8_t timestamp_lo;
3682 /* 16-lsb timestamp from POR (100-msec resolution) */
3683 uint16_t timestamp_hi;
3684 /* Event specific data */
3685 uint32_t event_data1;
3687 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3689 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3692 * If set to 1, it indicates that the supported link speeds
3693 * configuration on the port has changed.
3694 * If set to 0, then there is no change in supported link speeds
3697 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE \
3700 * If set to 1, it indicates that the link speed configuration
3701 * on the port has become illegal or invalid.
3702 * If set to 0, then the link speed configuration on the port is
3705 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG \
3707 } __attribute__((packed));
3709 /* hwrm_async_event_cmpl_port_phy_cfg_change (size:128b/16B) */
3710 struct hwrm_async_event_cmpl_port_phy_cfg_change {
3713 * This field indicates the exact type of the completion.
3714 * By convention, the LSB identifies the length of the
3715 * record in 16B units. Even values indicate 16B
3716 * records. Odd values indicate 32B
3719 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK \
3721 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT \
3723 /* HWRM Asynchronous Event Information */
3724 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
3726 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_LAST \
3727 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
3728 /* Identifiers of events. */
3730 /* Port PHY configuration change */
3731 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE \
3733 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_LAST \
3734 HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE
3735 /* Event specific data */
3736 uint32_t event_data2;
3739 * This value is written by the NIC such that it will be different
3740 * for each pass through the completion queue. The even passes
3741 * will write 1. The odd passes will write 0.
3743 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V \
3746 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK \
3748 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
3749 /* 8-lsb timestamp from POR (100-msec resolution) */
3750 uint8_t timestamp_lo;
3751 /* 16-lsb timestamp from POR (100-msec resolution) */
3752 uint16_t timestamp_hi;
3753 /* Event specific data */
3754 uint32_t event_data1;
3756 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \
3758 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \
3761 * If set to 1, it indicates that the FEC
3762 * configuration on the port has changed.
3763 * If set to 0, then there is no change in FEC configuration.
3765 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE \
3768 * If set to 1, it indicates that the EEE configuration
3769 * on the port has changed.
3770 * If set to 0, then there is no change in EEE configuration
3773 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE \
3776 * If set to 1, it indicates that the pause configuration
3777 * on the PHY has changed.
3778 * If set to 0, then there is no change in the pause
3779 * configuration on the PHY.
3781 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE \
3783 } __attribute__((packed));
3785 /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
3786 struct hwrm_async_event_cmpl_func_drvr_unload {
3789 * This field indicates the exact type of the completion.
3790 * By convention, the LSB identifies the length of the
3791 * record in 16B units. Even values indicate 16B
3792 * records. Odd values indicate 32B
3795 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK \
3797 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
3798 /* HWRM Asynchronous Event Information */
3799 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
3801 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_LAST \
3802 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
3803 /* Identifiers of events. */
3805 /* Function driver unloaded */
3806 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD \
3808 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_LAST \
3809 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD
3810 /* Event specific data */
3811 uint32_t event_data2;
3814 * This value is written by the NIC such that it will be different
3815 * for each pass through the completion queue. The even passes
3816 * will write 1. The odd passes will write 0.
3818 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
3820 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK \
3822 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
3823 /* 8-lsb timestamp from POR (100-msec resolution) */
3824 uint8_t timestamp_lo;
3825 /* 16-lsb timestamp from POR (100-msec resolution) */
3826 uint16_t timestamp_hi;
3827 /* Event specific data */
3828 uint32_t event_data1;
3830 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
3832 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT \
3834 } __attribute__((packed));
3836 /* hwrm_async_event_cmpl_func_drvr_load (size:128b/16B) */
3837 struct hwrm_async_event_cmpl_func_drvr_load {
3840 * This field indicates the exact type of the completion.
3841 * By convention, the LSB identifies the length of the
3842 * record in 16B units. Even values indicate 16B
3843 * records. Odd values indicate 32B
3846 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK \
3848 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
3849 /* HWRM Asynchronous Event Information */
3850 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
3852 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_LAST \
3853 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
3854 /* Identifiers of events. */
3856 /* Function driver loaded */
3857 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD \
3859 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_LAST \
3860 HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD
3861 /* Event specific data */
3862 uint32_t event_data2;
3865 * This value is written by the NIC such that it will be different
3866 * for each pass through the completion queue. The even passes
3867 * will write 1. The odd passes will write 0.
3869 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
3871 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
3872 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
3873 /* 8-lsb timestamp from POR (100-msec resolution) */
3874 uint8_t timestamp_lo;
3875 /* 16-lsb timestamp from POR (100-msec resolution) */
3876 uint16_t timestamp_hi;
3877 /* Event specific data */
3878 uint32_t event_data1;
3880 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
3882 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
3883 } __attribute__((packed));
3885 /* hwrm_async_event_cmpl_func_flr_proc_cmplt (size:128b/16B) */
3886 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
3889 * This field indicates the exact type of the completion.
3890 * By convention, the LSB identifies the length of the
3891 * record in 16B units. Even values indicate 16B
3892 * records. Odd values indicate 32B
3895 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK \
3897 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT \
3899 /* HWRM Asynchronous Event Information */
3900 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT \
3902 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_LAST \
3903 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT
3904 /* Identifiers of events. */
3906 /* Function FLR related processing has completed */
3907 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT \
3909 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_LAST \
3910 HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT
3911 /* Event specific data */
3912 uint32_t event_data2;
3915 * This value is written by the NIC such that it will be different
3916 * for each pass through the completion queue. The even passes
3917 * will write 1. The odd passes will write 0.
3919 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V \
3922 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK \
3924 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
3925 /* 8-lsb timestamp from POR (100-msec resolution) */
3926 uint8_t timestamp_lo;
3927 /* 16-lsb timestamp from POR (100-msec resolution) */
3928 uint16_t timestamp_hi;
3929 /* Event specific data */
3930 uint32_t event_data1;
3932 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK \
3934 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT \
3936 } __attribute__((packed));
3938 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */
3939 struct hwrm_async_event_cmpl_pf_drvr_unload {
3942 * This field indicates the exact type of the completion.
3943 * By convention, the LSB identifies the length of the
3944 * record in 16B units. Even values indicate 16B
3945 * records. Odd values indicate 32B
3948 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK \
3950 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
3951 /* HWRM Asynchronous Event Information */
3952 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT \
3954 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST \
3955 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT
3956 /* Identifiers of events. */
3958 /* PF driver unloaded */
3959 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD \
3961 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST \
3962 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD
3963 /* Event specific data */
3964 uint32_t event_data2;
3967 * This value is written by the NIC such that it will be different
3968 * for each pass through the completion queue. The even passes
3969 * will write 1. The odd passes will write 0.
3971 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
3973 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
3974 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
3975 /* 8-lsb timestamp from POR (100-msec resolution) */
3976 uint8_t timestamp_lo;
3977 /* 16-lsb timestamp from POR (100-msec resolution) */
3978 uint16_t timestamp_hi;
3979 /* Event specific data */
3980 uint32_t event_data1;
3982 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK \
3984 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
3985 /* Indicates the physical port this pf belongs to */
3986 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK \
3988 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
3989 } __attribute__((packed));
3991 /* hwrm_async_event_cmpl_pf_drvr_load (size:128b/16B) */
3992 struct hwrm_async_event_cmpl_pf_drvr_load {
3995 * This field indicates the exact type of the completion.
3996 * By convention, the LSB identifies the length of the
3997 * record in 16B units. Even values indicate 16B
3998 * records. Odd values indicate 32B
4001 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK \
4003 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
4004 /* HWRM Asynchronous Event Information */
4005 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT \
4007 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_LAST \
4008 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT
4009 /* Identifiers of events. */
4011 /* PF driver loaded */
4012 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD \
4014 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_LAST \
4015 HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD
4016 /* Event specific data */
4017 uint32_t event_data2;
4020 * This value is written by the NIC such that it will be different
4021 * for each pass through the completion queue. The even passes
4022 * will write 1. The odd passes will write 0.
4024 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
4026 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
4027 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
4028 /* 8-lsb timestamp from POR (100-msec resolution) */
4029 uint8_t timestamp_lo;
4030 /* 16-lsb timestamp from POR (100-msec resolution) */
4031 uint16_t timestamp_hi;
4032 /* Event specific data */
4033 uint32_t event_data1;
4035 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK \
4037 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
4038 /* Indicates the physical port this pf belongs to */
4039 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK \
4041 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
4042 } __attribute__((packed));
4044 /* hwrm_async_event_cmpl_vf_flr (size:128b/16B) */
4045 struct hwrm_async_event_cmpl_vf_flr {
4048 * This field indicates the exact type of the completion.
4049 * By convention, the LSB identifies the length of the
4050 * record in 16B units. Even values indicate 16B
4051 * records. Odd values indicate 32B
4054 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK \
4056 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
4057 /* HWRM Asynchronous Event Information */
4058 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT \
4060 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_LAST \
4061 HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT
4062 /* Identifiers of events. */
4064 /* VF Function Level Reset (FLR) */
4065 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
4066 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_LAST \
4067 HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR
4068 /* Event specific data */
4069 uint32_t event_data2;
4072 * This value is written by the NIC such that it will be different
4073 * for each pass through the completion queue. The even passes
4074 * will write 1. The odd passes will write 0.
4076 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
4078 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
4079 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
4080 /* 8-lsb timestamp from POR (100-msec resolution) */
4081 uint8_t timestamp_lo;
4082 /* 16-lsb timestamp from POR (100-msec resolution) */
4083 uint16_t timestamp_hi;
4084 /* Event specific data */
4085 uint32_t event_data1;
4087 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK \
4089 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
4090 } __attribute__((packed));
4092 /* hwrm_async_event_cmpl_vf_mac_addr_change (size:128b/16B) */
4093 struct hwrm_async_event_cmpl_vf_mac_addr_change {
4096 * This field indicates the exact type of the completion.
4097 * By convention, the LSB identifies the length of the
4098 * record in 16B units. Even values indicate 16B
4099 * records. Odd values indicate 32B
4102 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK \
4104 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
4105 /* HWRM Asynchronous Event Information */
4106 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4108 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_LAST \
4109 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT
4110 /* Identifiers of events. */
4112 /* VF MAC Address Change */
4113 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE \
4115 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_LAST \
4116 HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE
4117 /* Event specific data */
4118 uint32_t event_data2;
4121 * This value is written by the NIC such that it will be different
4122 * for each pass through the completion queue. The even passes
4123 * will write 1. The odd passes will write 0.
4125 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V \
4128 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK \
4130 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
4131 /* 8-lsb timestamp from POR (100-msec resolution) */
4132 uint8_t timestamp_lo;
4133 /* 16-lsb timestamp from POR (100-msec resolution) */
4134 uint16_t timestamp_hi;
4135 /* Event specific data */
4136 uint32_t event_data1;
4138 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK \
4140 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT \
4142 } __attribute__((packed));
4144 /* hwrm_async_event_cmpl_pf_vf_comm_status_change (size:128b/16B) */
4145 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
4148 * This field indicates the exact type of the completion.
4149 * By convention, the LSB identifies the length of the
4150 * record in 16B units. Even values indicate 16B
4151 * records. Odd values indicate 32B
4154 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK \
4156 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT \
4158 /* HWRM Asynchronous Event Information */
4159 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4161 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_LAST \
4162 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
4163 /* Identifiers of events. */
4165 /* PF-VF communication channel status change. */
4166 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE \
4168 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_LAST \
4169 HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE
4170 /* Event specific data */
4171 uint32_t event_data2;
4174 * This value is written by the NIC such that it will be different
4175 * for each pass through the completion queue. The even passes
4176 * will write 1. The odd passes will write 0.
4178 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V \
4181 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK \
4183 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
4184 /* 8-lsb timestamp from POR (100-msec resolution) */
4185 uint8_t timestamp_lo;
4186 /* 16-lsb timestamp from POR (100-msec resolution) */
4187 uint16_t timestamp_hi;
4188 /* Event specific data */
4189 uint32_t event_data1;
4191 * If this bit is set to 1, then it indicates that the PF-VF
4192 * communication was lost and it is established.
4193 * If this bit set to 0, then it indicates that the PF-VF
4194 * communication was established and it is lost.
4196 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED \
4198 } __attribute__((packed));
4200 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
4201 struct hwrm_async_event_cmpl_vf_cfg_change {
4204 * This field indicates the exact type of the completion.
4205 * By convention, the LSB identifies the length of the
4206 * record in 16B units. Even values indicate 16B
4207 * records. Odd values indicate 32B
4210 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK \
4212 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
4213 /* HWRM Asynchronous Event Information */
4214 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4216 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST \
4217 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
4218 /* Identifiers of events. */
4220 /* VF Configuration Change */
4221 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE \
4223 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST \
4224 HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
4225 /* Event specific data */
4226 uint32_t event_data2;
4229 * This value is written by the NIC such that it will be different
4230 * for each pass through the completion queue. The even passes
4231 * will write 1. The odd passes will write 0.
4233 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
4235 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
4236 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
4237 /* 8-lsb timestamp from POR (100-msec resolution) */
4238 uint8_t timestamp_lo;
4239 /* 16-lsb timestamp from POR (100-msec resolution) */
4240 uint16_t timestamp_hi;
4242 * Each flag provided in this field indicates a specific VF
4243 * configuration change. At least one of these flags shall be set to 1
4244 * when an asynchronous event completion of this type is provided
4247 uint32_t event_data1;
4249 * If this bit is set to 1, then the value of MTU
4250 * was changed on this VF.
4251 * If set to 0, then this bit should be ignored.
4253 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE \
4256 * If this bit is set to 1, then the value of MRU
4257 * was changed on this VF.
4258 * If set to 0, then this bit should be ignored.
4260 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE \
4263 * If this bit is set to 1, then the value of default MAC
4264 * address was changed on this VF.
4265 * If set to 0, then this bit should be ignored.
4267 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE \
4270 * If this bit is set to 1, then the value of default VLAN
4271 * was changed on this VF.
4272 * If set to 0, then this bit should be ignored.
4274 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \
4276 } __attribute__((packed));
4278 /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */
4279 struct hwrm_async_event_cmpl_llfc_pfc_change {
4282 * This field indicates the exact type of the completion.
4283 * By convention, the LSB identifies the length of the
4284 * record in 16B units. Even values indicate 16B
4285 * records. Odd values indicate 32B
4288 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK \
4290 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
4291 /* HWRM Asynchronous Event Information */
4292 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT \
4294 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_LAST \
4295 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT
4296 /* unused1 is 10 b */
4297 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK \
4299 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_SFT 6
4300 /* Identifiers of events. */
4302 /* LLFC/PFC Configuration Change */
4303 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE \
4305 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LAST \
4306 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE
4307 /* Event specific data */
4308 uint32_t event_data2;
4311 * This value is written by the NIC such that it will be different
4312 * for each pass through the completion queue. The even passes
4313 * will write 1. The odd passes will write 0.
4315 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
4317 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK \
4319 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
4320 /* 8-lsb timestamp from POR (100-msec resolution) */
4321 uint8_t timestamp_lo;
4322 /* 16-lsb timestamp from POR (100-msec resolution) */
4323 uint16_t timestamp_hi;
4324 /* Event specific data */
4325 uint32_t event_data1;
4326 /* Indicates llfc pfc status change */
4327 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK \
4329 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT \
4332 * If this field set to 1, then it indicates that llfc is
4335 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC \
4338 * If this field is set to 2, then it indicates that pfc
4341 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC \
4343 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST \
4344 HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
4345 /* Indicates the physical port this llfc pfc change occur */
4346 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK \
4348 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT \
4351 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK \
4353 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT \
4355 } __attribute__((packed));
4357 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
4358 struct hwrm_async_event_cmpl_hwrm_error {
4361 * This field indicates the exact type of the completion.
4362 * By convention, the LSB identifies the length of the
4363 * record in 16B units. Even values indicate 16B
4364 * records. Odd values indicate 32B
4367 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
4369 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
4370 /* HWRM Asynchronous Event Information */
4371 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
4373 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
4374 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
4375 /* Identifiers of events. */
4378 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
4380 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
4381 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
4382 /* Event specific data */
4383 uint32_t event_data2;
4384 /* Severity of HWRM Error */
4385 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
4387 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
4389 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
4391 /* Non-fatal Error */
4392 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
4395 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
4397 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
4398 HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
4401 * This value is written by the NIC such that it will be different
4402 * for each pass through the completion queue. The even passes
4403 * will write 1. The odd passes will write 0.
4405 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
4407 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
4408 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
4409 /* 8-lsb timestamp from POR (100-msec resolution) */
4410 uint8_t timestamp_lo;
4411 /* 16-lsb timestamp from POR (100-msec resolution) */
4412 uint16_t timestamp_hi;
4413 /* Event specific data */
4414 uint32_t event_data1;
4415 /* Time stamp for error event */
4416 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
4418 } __attribute__((packed));
4420 /*******************
4422 *******************/
4425 /* hwrm_func_reset_input (size:192b/24B) */
4426 struct hwrm_func_reset_input {
4427 /* The HWRM command request type. */
4430 * The completion ring to send the completion event on. This should
4431 * be the NQ ID returned from the `nq_alloc` HWRM command.
4435 * The sequence ID is used by the driver for tracking multiple
4436 * commands. This ID is treated as opaque data by the firmware and
4437 * the value is returned in the `hwrm_resp_hdr` upon completion.
4441 * The target ID of the command:
4442 * * 0x0-0xFFF8 - The function ID
4443 * * 0xFFF8-0xFFFE - Reserved for internal processors
4448 * A physical address pointer pointing to a host buffer that the
4449 * command's response data will be written. This can be either a host
4450 * physical address (HPA) or a guest physical address (GPA) and must
4451 * point to a physically contiguous block of memory.
4456 * This bit must be '1' for the vf_id_valid field to be
4459 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
4461 * The ID of the VF that this PF is trying to reset.
4462 * Only the parent PF shall be allowed to reset a child VF.
4464 * A parent PF driver shall use this field only when a specific child VF
4465 * is requested to be reset.
4468 /* This value indicates the level of a function reset. */
4469 uint8_t func_reset_level;
4471 * Reset the caller function and its children VFs (if any). If no
4472 * children functions exist, then reset the caller function only.
4474 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
4476 /* Reset the caller function only */
4477 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
4480 * Reset all children VFs of the caller function driver if the
4481 * caller is a PF driver.
4482 * It is an error to specify this level by a VF driver.
4483 * It is an error to specify this level by a PF driver with
4486 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
4489 * Reset a specific VF of the caller function driver if the caller
4490 * is the parent PF driver.
4491 * It is an error to specify this level by a VF driver.
4492 * It is an error to specify this level by a PF driver that is not
4493 * the parent of the VF that is being requested to reset.
4495 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
4497 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_LAST \
4498 HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF
4500 } __attribute__((packed));
4502 /* hwrm_func_reset_output (size:128b/16B) */
4503 struct hwrm_func_reset_output {
4504 /* The specific error status for the command. */
4505 uint16_t error_code;
4506 /* The HWRM command request type. */
4508 /* The sequence ID from the original command. */
4510 /* The length of the response data in number of bytes. */
4512 uint8_t unused_0[7];
4514 * This field is used in Output records to indicate that the output
4515 * is completely written to RAM. This field should be read as '1'
4516 * to indicate that the output has been completely written.
4517 * When writing a command completion or response to an internal processor,
4518 * the order of writes has to be such that this field is written last.
4521 } __attribute__((packed));
4523 /********************
4524 * hwrm_func_getfid *
4525 ********************/
4528 /* hwrm_func_getfid_input (size:192b/24B) */
4529 struct hwrm_func_getfid_input {
4530 /* The HWRM command request type. */
4533 * The completion ring to send the completion event on. This should
4534 * be the NQ ID returned from the `nq_alloc` HWRM command.
4538 * The sequence ID is used by the driver for tracking multiple
4539 * commands. This ID is treated as opaque data by the firmware and
4540 * the value is returned in the `hwrm_resp_hdr` upon completion.
4544 * The target ID of the command:
4545 * * 0x0-0xFFF8 - The function ID
4546 * * 0xFFF8-0xFFFE - Reserved for internal processors
4551 * A physical address pointer pointing to a host buffer that the
4552 * command's response data will be written. This can be either a host
4553 * physical address (HPA) or a guest physical address (GPA) and must
4554 * point to a physically contiguous block of memory.
4559 * This bit must be '1' for the pci_id field to be
4562 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
4564 * This value is the PCI ID of the queried function.
4565 * If ARI is enabled, then it is
4566 * Bus Number (8b):Function Number(8b). Otherwise, it is
4567 * Bus Number (8b):Device Number (5b):Function Number(3b).
4570 uint8_t unused_0[2];
4571 } __attribute__((packed));
4573 /* hwrm_func_getfid_output (size:128b/16B) */
4574 struct hwrm_func_getfid_output {
4575 /* The specific error status for the command. */
4576 uint16_t error_code;
4577 /* The HWRM command request type. */
4579 /* The sequence ID from the original command. */
4581 /* The length of the response data in number of bytes. */
4584 * FID value. This value is used to identify operations on the PCI
4585 * bus as belonging to a particular PCI function.
4588 uint8_t unused_0[5];
4590 * This field is used in Output records to indicate that the output
4591 * is completely written to RAM. This field should be read as '1'
4592 * to indicate that the output has been completely written.
4593 * When writing a command completion or response to an internal processor,
4594 * the order of writes has to be such that this field is written last.
4597 } __attribute__((packed));
4599 /**********************
4600 * hwrm_func_vf_alloc *
4601 **********************/
4604 /* hwrm_func_vf_alloc_input (size:192b/24B) */
4605 struct hwrm_func_vf_alloc_input {
4606 /* The HWRM command request type. */
4609 * The completion ring to send the completion event on. This should
4610 * be the NQ ID returned from the `nq_alloc` HWRM command.
4614 * The sequence ID is used by the driver for tracking multiple
4615 * commands. This ID is treated as opaque data by the firmware and
4616 * the value is returned in the `hwrm_resp_hdr` upon completion.
4620 * The target ID of the command:
4621 * * 0x0-0xFFF8 - The function ID
4622 * * 0xFFF8-0xFFFE - Reserved for internal processors
4627 * A physical address pointer pointing to a host buffer that the
4628 * command's response data will be written. This can be either a host
4629 * physical address (HPA) or a guest physical address (GPA) and must
4630 * point to a physically contiguous block of memory.
4635 * This bit must be '1' for the first_vf_id field to be
4638 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
4640 * This value is used to identify a Virtual Function (VF).
4641 * The scope of VF ID is local within a PF.
4643 uint16_t first_vf_id;
4644 /* The number of virtual functions requested. */
4646 } __attribute__((packed));
4648 /* hwrm_func_vf_alloc_output (size:128b/16B) */
4649 struct hwrm_func_vf_alloc_output {
4650 /* The specific error status for the command. */
4651 uint16_t error_code;
4652 /* The HWRM command request type. */
4654 /* The sequence ID from the original command. */
4656 /* The length of the response data in number of bytes. */
4658 /* The ID of the first VF allocated. */
4659 uint16_t first_vf_id;
4660 uint8_t unused_0[5];
4662 * This field is used in Output records to indicate that the output
4663 * is completely written to RAM. This field should be read as '1'
4664 * to indicate that the output has been completely written.
4665 * When writing a command completion or response to an internal processor,
4666 * the order of writes has to be such that this field is written last.
4669 } __attribute__((packed));
4671 /*********************
4672 * hwrm_func_vf_free *
4673 *********************/
4676 /* hwrm_func_vf_free_input (size:192b/24B) */
4677 struct hwrm_func_vf_free_input {
4678 /* The HWRM command request type. */
4681 * The completion ring to send the completion event on. This should
4682 * be the NQ ID returned from the `nq_alloc` HWRM command.
4686 * The sequence ID is used by the driver for tracking multiple
4687 * commands. This ID is treated as opaque data by the firmware and
4688 * the value is returned in the `hwrm_resp_hdr` upon completion.
4692 * The target ID of the command:
4693 * * 0x0-0xFFF8 - The function ID
4694 * * 0xFFF8-0xFFFE - Reserved for internal processors
4699 * A physical address pointer pointing to a host buffer that the
4700 * command's response data will be written. This can be either a host
4701 * physical address (HPA) or a guest physical address (GPA) and must
4702 * point to a physically contiguous block of memory.
4707 * This bit must be '1' for the first_vf_id field to be
4710 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
4712 * This value is used to identify a Virtual Function (VF).
4713 * The scope of VF ID is local within a PF.
4715 uint16_t first_vf_id;
4717 * The number of virtual functions requested.
4718 * 0xFFFF - Cleanup all children of this PF.
4721 } __attribute__((packed));
4723 /* hwrm_func_vf_free_output (size:128b/16B) */
4724 struct hwrm_func_vf_free_output {
4725 /* The specific error status for the command. */
4726 uint16_t error_code;
4727 /* The HWRM command request type. */
4729 /* The sequence ID from the original command. */
4731 /* The length of the response data in number of bytes. */
4733 uint8_t unused_0[7];
4735 * This field is used in Output records to indicate that the output
4736 * is completely written to RAM. This field should be read as '1'
4737 * to indicate that the output has been completely written.
4738 * When writing a command completion or response to an internal processor,
4739 * the order of writes has to be such that this field is written last.
4742 } __attribute__((packed));
4744 /********************
4745 * hwrm_func_vf_cfg *
4746 ********************/
4749 /* hwrm_func_vf_cfg_input (size:448b/56B) */
4750 struct hwrm_func_vf_cfg_input {
4751 /* The HWRM command request type. */
4754 * The completion ring to send the completion event on. This should
4755 * be the NQ ID returned from the `nq_alloc` HWRM command.
4759 * The sequence ID is used by the driver for tracking multiple
4760 * commands. This ID is treated as opaque data by the firmware and
4761 * the value is returned in the `hwrm_resp_hdr` upon completion.
4765 * The target ID of the command:
4766 * * 0x0-0xFFF8 - The function ID
4767 * * 0xFFF8-0xFFFE - Reserved for internal processors
4772 * A physical address pointer pointing to a host buffer that the
4773 * command's response data will be written. This can be either a host
4774 * physical address (HPA) or a guest physical address (GPA) and must
4775 * point to a physically contiguous block of memory.
4780 * This bit must be '1' for the mtu field to be
4783 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU \
4786 * This bit must be '1' for the guest_vlan field to be
4789 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN \
4792 * This bit must be '1' for the async_event_cr field to be
4795 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
4798 * This bit must be '1' for the dflt_mac_addr field to be
4801 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
4804 * This bit must be '1' for the num_rsscos_ctxs field to be
4807 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
4810 * This bit must be '1' for the num_cmpl_rings field to be
4813 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
4816 * This bit must be '1' for the num_tx_rings field to be
4819 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS \
4822 * This bit must be '1' for the num_rx_rings field to be
4825 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS \
4828 * This bit must be '1' for the num_l2_ctxs field to be
4831 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS \
4834 * This bit must be '1' for the num_vnics field to be
4837 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS \
4840 * This bit must be '1' for the num_stat_ctxs field to be
4843 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
4846 * This bit must be '1' for the num_hw_ring_grps field to be
4849 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
4852 * The maximum transmission unit requested on the function.
4853 * The HWRM should make sure that the mtu of
4854 * the function does not exceed the mtu of the physical
4855 * port that this function is associated with.
4857 * In addition to requesting mtu per function, it is
4858 * possible to configure mtu per transmit ring.
4859 * By default, the mtu of each transmit ring associated
4860 * with a function is equal to the mtu of the function.
4861 * The HWRM should make sure that the mtu of each transmit
4862 * ring that is assigned to a function has a valid mtu.
4866 * The guest VLAN for the function being configured.
4867 * This field's format is same as 802.1Q Tag's
4868 * Tag Control Information (TCI) format that includes both
4869 * Priority Code Point (PCP) and VLAN Identifier (VID).
4871 uint16_t guest_vlan;
4873 * ID of the target completion ring for receiving asynchronous
4874 * event completions. If this field is not valid, then the
4875 * HWRM shall use the default completion ring of the function
4876 * that is being configured as the target completion ring for
4877 * providing any asynchronous event completions for that
4879 * If this field is valid, then the HWRM shall use the
4880 * completion ring identified by this ID as the target
4881 * completion ring for providing any asynchronous event
4882 * completions for the function that is being configured.
4884 uint16_t async_event_cr;
4886 * This value is the current MAC address requested by the VF
4887 * driver to be configured on this VF. A value of
4888 * 00-00-00-00-00-00 indicates no MAC address configuration
4889 * is requested by the VF driver.
4890 * The parent PF driver may reject or overwrite this
4893 uint8_t dflt_mac_addr[6];
4896 * This bit requests that the firmware test to see if all the assets
4897 * requested in this command (i.e. number of TX rings) are available.
4898 * The firmware will return an error if the requested assets are
4899 * not available. The firwmare will NOT reserve the assets if they
4902 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
4905 * This bit requests that the firmware test to see if all the assets
4906 * requested in this command (i.e. number of RX rings) are available.
4907 * The firmware will return an error if the requested assets are
4908 * not available. The firwmare will NOT reserve the assets if they
4911 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
4914 * This bit requests that the firmware test to see if all the assets
4915 * requested in this command (i.e. number of CMPL rings) are available.
4916 * The firmware will return an error if the requested assets are
4917 * not available. The firwmare will NOT reserve the assets if they
4920 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
4923 * This bit requests that the firmware test to see if all the assets
4924 * requested in this command (i.e. number of RSS ctx) are available.
4925 * The firmware will return an error if the requested assets are
4926 * not available. The firwmare will NOT reserve the assets if they
4929 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
4932 * This bit requests that the firmware test to see if all the assets
4933 * requested in this command (i.e. number of ring groups) are available.
4934 * The firmware will return an error if the requested assets are
4935 * not available. The firwmare will NOT reserve the assets if they
4938 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
4941 * This bit requests that the firmware test to see if all the assets
4942 * requested in this command (i.e. number of stat ctx) are available.
4943 * The firmware will return an error if the requested assets are
4944 * not available. The firwmare will NOT reserve the assets if they
4947 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
4950 * This bit requests that the firmware test to see if all the assets
4951 * requested in this command (i.e. number of VNICs) are available.
4952 * The firmware will return an error if the requested assets are
4953 * not available. The firwmare will NOT reserve the assets if they
4956 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
4959 * This bit requests that the firmware test to see if all the assets
4960 * requested in this command (i.e. number of L2 ctx) are available.
4961 * The firmware will return an error if the requested assets are
4962 * not available. The firwmare will NOT reserve the assets if they
4965 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
4967 /* The number of RSS/COS contexts requested for the VF. */
4968 uint16_t num_rsscos_ctxs;
4969 /* The number of completion rings requested for the VF. */
4970 uint16_t num_cmpl_rings;
4971 /* The number of transmit rings requested for the VF. */
4972 uint16_t num_tx_rings;
4973 /* The number of receive rings requested for the VF. */
4974 uint16_t num_rx_rings;
4975 /* The number of L2 contexts requested for the VF. */
4976 uint16_t num_l2_ctxs;
4977 /* The number of vnics requested for the VF. */
4979 /* The number of statistic contexts requested for the VF. */
4980 uint16_t num_stat_ctxs;
4981 /* The number of HW ring groups requested for the VF. */
4982 uint16_t num_hw_ring_grps;
4983 uint8_t unused_0[4];
4984 } __attribute__((packed));
4986 /* hwrm_func_vf_cfg_output (size:128b/16B) */
4987 struct hwrm_func_vf_cfg_output {
4988 /* The specific error status for the command. */
4989 uint16_t error_code;
4990 /* The HWRM command request type. */
4992 /* The sequence ID from the original command. */
4994 /* The length of the response data in number of bytes. */
4996 uint8_t unused_0[7];
4998 * This field is used in Output records to indicate that the output
4999 * is completely written to RAM. This field should be read as '1'
5000 * to indicate that the output has been completely written.
5001 * When writing a command completion or response to an internal processor,
5002 * the order of writes has to be such that this field is written last.
5005 } __attribute__((packed));
5007 /*******************
5009 *******************/
5012 /* hwrm_func_qcaps_input (size:192b/24B) */
5013 struct hwrm_func_qcaps_input {
5014 /* The HWRM command request type. */
5017 * The completion ring to send the completion event on. This should
5018 * be the NQ ID returned from the `nq_alloc` HWRM command.
5022 * The sequence ID is used by the driver for tracking multiple
5023 * commands. This ID is treated as opaque data by the firmware and
5024 * the value is returned in the `hwrm_resp_hdr` upon completion.
5028 * The target ID of the command:
5029 * * 0x0-0xFFF8 - The function ID
5030 * * 0xFFF8-0xFFFE - Reserved for internal processors
5035 * A physical address pointer pointing to a host buffer that the
5036 * command's response data will be written. This can be either a host
5037 * physical address (HPA) or a guest physical address (GPA) and must
5038 * point to a physically contiguous block of memory.
5042 * Function ID of the function that is being queried.
5043 * 0xFF... (All Fs) if the query is for the requesting
5047 uint8_t unused_0[6];
5048 } __attribute__((packed));
5050 /* hwrm_func_qcaps_output (size:640b/80B) */
5051 struct hwrm_func_qcaps_output {
5052 /* The specific error status for the command. */
5053 uint16_t error_code;
5054 /* The HWRM command request type. */
5056 /* The sequence ID from the original command. */
5058 /* The length of the response data in number of bytes. */
5061 * FID value. This value is used to identify operations on the PCI
5062 * bus as belonging to a particular PCI function.
5066 * Port ID of port that this function is associated with.
5067 * Valid only for the PF.
5068 * 0xFF... (All Fs) if this function is not associated with
5070 * 0xFF... (All Fs) if this function is called from a VF.
5074 /* If 1, then Push mode is supported on this function. */
5075 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED \
5078 * If 1, then the global MSI-X auto-masking is enabled for the
5081 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING \
5084 * If 1, then the Precision Time Protocol (PTP) processing
5085 * is supported on this function.
5086 * The HWRM should enable PTP on only a single Physical
5087 * Function (PF) per port.
5089 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED \
5092 * If 1, then RDMA over Converged Ethernet (RoCE) v1
5093 * is supported on this function.
5095 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED \
5098 * If 1, then RDMA over Converged Ethernet (RoCE) v2
5099 * is supported on this function.
5101 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED \
5104 * If 1, then control and configuration of WoL magic packet
5105 * are supported on this function.
5107 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED \
5110 * If 1, then control and configuration of bitmap pattern
5111 * packet are supported on this function.
5113 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED \
5116 * If set to 1, then the control and configuration of rate limit
5117 * of an allocated TX ring on the queried function is supported.
5119 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED \
5122 * If 1, then control and configuration of minimum and
5123 * maximum bandwidths are supported on the queried function.
5125 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED \
5128 * If the query is for a VF, then this flag shall be ignored.
5129 * If this query is for a PF and this flag is set to 1,
5130 * then the PF has the capability to set the rate limits
5131 * on the TX rings of its children VFs.
5132 * If this query is for a PF and this flag is set to 0, then
5133 * the PF does not have the capability to set the rate limits
5134 * on the TX rings of its children VFs.
5136 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED \
5139 * If the query is for a VF, then this flag shall be ignored.
5140 * If this query is for a PF and this flag is set to 1,
5141 * then the PF has the capability to set the minimum and/or
5142 * maximum bandwidths for its children VFs.
5143 * If this query is for a PF and this flag is set to 0, then
5144 * the PF does not have the capability to set the minimum or
5145 * maximum bandwidths for its children VFs.
5147 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED \
5150 * Standard TX Ring mode is used for the allocation of TX ring
5151 * and underlying scheduling resources that allow bandwidth
5152 * reservation and limit settings on the queried function.
5153 * If set to 1, then standard TX ring mode is supported
5154 * on the queried function.
5155 * If set to 0, then standard TX ring mode is not available
5156 * on the queried function.
5158 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED \
5161 * If the query is for a VF, then this flag shall be ignored,
5162 * If this query is for a PF and this flag is set to 1,
5163 * then the PF has the capability to detect GENEVE tunnel
5166 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED \
5169 * If the query is for a VF, then this flag shall be ignored,
5170 * If this query is for a PF and this flag is set to 1,
5171 * then the PF has the capability to detect NVGRE tunnel
5174 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED \
5177 * If the query is for a VF, then this flag shall be ignored,
5178 * If this query is for a PF and this flag is set to 1,
5179 * then the PF has the capability to detect GRE tunnel
5182 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED \
5185 * If the query is for a VF, then this flag shall be ignored,
5186 * If this query is for a PF and this flag is set to 1,
5187 * then the PF has the capability to detect MPLS tunnel
5190 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED \
5193 * If the query is for a VF, then this flag shall be ignored,
5194 * If this query is for a PF and this flag is set to 1,
5195 * then the PF has the capability to support pcie stats.
5197 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED \
5200 * This value is current MAC address configured for this
5201 * function. A value of 00-00-00-00-00-00 indicates no
5202 * MAC address is currently configured.
5204 uint8_t mac_address[6];
5206 * The maximum number of RSS/COS contexts that can be
5207 * allocated to the function.
5209 uint16_t max_rsscos_ctx;
5211 * The maximum number of completion rings that can be
5212 * allocated to the function.
5214 uint16_t max_cmpl_rings;
5216 * The maximum number of transmit rings that can be
5217 * allocated to the function.
5219 uint16_t max_tx_rings;
5221 * The maximum number of receive rings that can be
5222 * allocated to the function.
5224 uint16_t max_rx_rings;
5226 * The maximum number of L2 contexts that can be
5227 * allocated to the function.
5229 uint16_t max_l2_ctxs;
5231 * The maximum number of VNICs that can be
5232 * allocated to the function.
5236 * The identifier for the first VF enabled on a PF. This
5237 * is valid only on the PF with SR-IOV enabled.
5238 * 0xFF... (All Fs) if this command is called on a PF with
5239 * SR-IOV disabled or on a VF.
5241 uint16_t first_vf_id;
5243 * The maximum number of VFs that can be
5244 * allocated to the function. This is valid only on the
5245 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
5246 * command is called on a PF with SR-IOV disabled or
5251 * The maximum number of statistic contexts that can be
5252 * allocated to the function.
5254 uint16_t max_stat_ctx;
5256 * The maximum number of Encapsulation records that can be
5257 * offloaded by this function.
5259 uint32_t max_encap_records;
5261 * The maximum number of decapsulation records that can
5262 * be offloaded by this function.
5264 uint32_t max_decap_records;
5266 * The maximum number of Exact Match (EM) flows that can be
5267 * offloaded by this function on the TX side.
5269 uint32_t max_tx_em_flows;
5271 * The maximum number of Wildcard Match (WM) flows that can
5272 * be offloaded by this function on the TX side.
5274 uint32_t max_tx_wm_flows;
5276 * The maximum number of Exact Match (EM) flows that can be
5277 * offloaded by this function on the RX side.
5279 uint32_t max_rx_em_flows;
5281 * The maximum number of Wildcard Match (WM) flows that can
5282 * be offloaded by this function on the RX side.
5284 uint32_t max_rx_wm_flows;
5286 * The maximum number of multicast filters that can
5287 * be supported by this function on the RX side.
5289 uint32_t max_mcast_filters;
5291 * The maximum value of flow_id that can be supported
5292 * in completion records.
5294 uint32_t max_flow_id;
5296 * The maximum number of HW ring groups that can be
5297 * supported on this function.
5299 uint32_t max_hw_ring_grps;
5301 * The maximum number of strict priority transmit rings
5302 * that can be allocated to the function.
5303 * This number indicates the maximum number of TX rings
5304 * that can be assigned strict priorities out of the
5305 * maximum number of TX rings that can be allocated
5306 * (max_tx_rings) to the function.
5308 uint16_t max_sp_tx_rings;
5311 * This field is used in Output records to indicate that the output
5312 * is completely written to RAM. This field should be read as '1'
5313 * to indicate that the output has been completely written.
5314 * When writing a command completion or response to an internal processor,
5315 * the order of writes has to be such that this field is written last.
5318 } __attribute__((packed));
5325 /* hwrm_func_qcfg_input (size:192b/24B) */
5326 struct hwrm_func_qcfg_input {
5327 /* The HWRM command request type. */
5330 * The completion ring to send the completion event on. This should
5331 * be the NQ ID returned from the `nq_alloc` HWRM command.
5335 * The sequence ID is used by the driver for tracking multiple
5336 * commands. This ID is treated as opaque data by the firmware and
5337 * the value is returned in the `hwrm_resp_hdr` upon completion.
5341 * The target ID of the command:
5342 * * 0x0-0xFFF8 - The function ID
5343 * * 0xFFF8-0xFFFE - Reserved for internal processors
5348 * A physical address pointer pointing to a host buffer that the
5349 * command's response data will be written. This can be either a host
5350 * physical address (HPA) or a guest physical address (GPA) and must
5351 * point to a physically contiguous block of memory.
5355 * Function ID of the function that is being queried.
5356 * 0xFF... (All Fs) if the query is for the requesting
5360 uint8_t unused_0[6];
5361 } __attribute__((packed));
5363 /* hwrm_func_qcfg_output (size:640b/80B) */
5364 struct hwrm_func_qcfg_output {
5365 /* The specific error status for the command. */
5366 uint16_t error_code;
5367 /* The HWRM command request type. */
5369 /* The sequence ID from the original command. */
5371 /* The length of the response data in number of bytes. */
5374 * FID value. This value is used to identify operations on the PCI
5375 * bus as belonging to a particular PCI function.
5379 * Port ID of port that this function is associated with.
5380 * 0xFF... (All Fs) if this function is not associated with
5385 * This value is the current VLAN setting for this
5386 * function. The value of 0 for this field indicates
5387 * no priority tagging or VLAN is used.
5388 * This field's format is same as 802.1Q Tag's
5389 * Tag Control Information (TCI) format that includes both
5390 * Priority Code Point (PCP) and VLAN Identifier (VID).
5395 * If 1, then magic packet based Out-Of-Box WoL is enabled on
5396 * the port associated with this function.
5398 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED \
5401 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled
5402 * on the port associated with this function.
5404 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED \
5407 * If set to 1, then FW based DCBX agent is enabled and running on
5408 * the port associated with this function.
5409 * If set to 0, then DCBX agent is not running in the firmware.
5411 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED \
5414 * Standard TX Ring mode is used for the allocation of TX ring
5415 * and underlying scheduling resources that allow bandwidth
5416 * reservation and limit settings on the queried function.
5417 * If set to 1, then standard TX ring mode is enabled
5418 * on the queried function.
5419 * If set to 0, then the standard TX ring mode is disabled
5420 * on the queried function. In this extended TX ring resource
5421 * mode, the minimum and maximum bandwidth settings are not
5422 * supported to allow the allocation of TX rings to span multiple
5425 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED \
5428 * If set to 1 then FW based LLDP agent is enabled and running on
5429 * the port associated with this function.
5430 * If set to 0 then the LLDP agent is not running in the firmware.
5432 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED \
5435 * If set to 1, then multi-host mode is active for this function.
5436 * If set to 0, then multi-host mode is inactive for this function
5437 * or not applicable for this device.
5439 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \
5442 * This value is current MAC address configured for this
5443 * function. A value of 00-00-00-00-00-00 indicates no
5444 * MAC address is currently configured.
5446 uint8_t mac_address[6];
5448 * This value is current PCI ID of this
5449 * function. If ARI is enabled, then it is
5450 * Bus Number (8b):Function Number(8b). Otherwise, it is
5451 * Bus Number (8b):Device Number (4b):Function Number(4b).
5452 * If multi-host mode is active, the 4 lsb will indicate
5453 * the PF index for this function.
5457 * The number of RSS/COS contexts currently
5458 * allocated to the function.
5460 uint16_t alloc_rsscos_ctx;
5462 * The number of completion rings currently allocated to
5463 * the function. This does not include the rings allocated
5464 * to any children functions if any.
5466 uint16_t alloc_cmpl_rings;
5468 * The number of transmit rings currently allocated to
5469 * the function. This does not include the rings allocated
5470 * to any children functions if any.
5472 uint16_t alloc_tx_rings;
5474 * The number of receive rings currently allocated to
5475 * the function. This does not include the rings allocated
5476 * to any children functions if any.
5478 uint16_t alloc_rx_rings;
5479 /* The allocated number of L2 contexts to the function. */
5480 uint16_t alloc_l2_ctx;
5481 /* The allocated number of vnics to the function. */
5482 uint16_t alloc_vnics;
5484 * The maximum transmission unit of the function.
5485 * For rings allocated on this function, this default
5486 * value is used if ring MTU is not specified.
5490 * The maximum receive unit of the function.
5491 * For vnics allocated on this function, this default
5492 * value is used if vnic MRU is not specified.
5495 /* The statistics context assigned to a function. */
5496 uint16_t stat_ctx_id;
5498 * The HWRM shall return Unknown value for this field
5499 * when this command is used to query VF's configuration.
5501 uint8_t port_partition_type;
5502 /* Single physical function */
5503 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
5504 /* Multiple physical functions */
5505 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
5506 /* Network Partitioning 1.0 */
5507 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
5508 /* Network Partitioning 1.5 */
5509 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
5510 /* Network Partitioning 2.0 */
5511 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
5513 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN \
5515 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_LAST \
5516 HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN
5518 * This field will indicate number of physical functions on this port_partition.
5519 * HWRM shall return unavail (i.e. value of 0) for this field
5520 * when this command is used to query VF's configuration or
5521 * from older firmware that doesn't support this field.
5523 uint8_t port_pf_cnt;
5524 /* number of PFs is not available */
5525 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
5526 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_LAST \
5527 HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL
5529 * The default VNIC ID assigned to a function that is
5532 uint16_t dflt_vnic_id;
5533 uint16_t max_mtu_configured;
5535 * Minimum BW allocated for this function.
5536 * The HWRM will translate this value into byte counter and
5537 * time interval used for the scheduler inside the device.
5538 * A value of 0 indicates the minimum bandwidth is not
5542 /* The bandwidth value. */
5543 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK \
5545 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
5546 /* The granularity of the value (bits or bytes). */
5547 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE \
5548 UINT32_C(0x10000000)
5549 /* Value is in bits. */
5550 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS \
5551 (UINT32_C(0x0) << 28)
5552 /* Value is in bytes. */
5553 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES \
5554 (UINT32_C(0x1) << 28)
5555 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST \
5556 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
5557 /* bw_value_unit is 3 b */
5558 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK \
5559 UINT32_C(0xe0000000)
5560 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
5561 /* Value is in Mb or MB (base 10). */
5562 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
5563 (UINT32_C(0x0) << 29)
5564 /* Value is in Kb or KB (base 10). */
5565 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO \
5566 (UINT32_C(0x2) << 29)
5567 /* Value is in bits or bytes. */
5568 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE \
5569 (UINT32_C(0x4) << 29)
5570 /* Value is in Gb or GB (base 10). */
5571 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
5572 (UINT32_C(0x6) << 29)
5573 /* Value is in 1/100th of a percentage of total bandwidth. */
5574 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
5575 (UINT32_C(0x1) << 29)
5577 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
5578 (UINT32_C(0x7) << 29)
5579 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST \
5580 HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
5582 * Maximum BW allocated for this function.
5583 * The HWRM will translate this value into byte counter and
5584 * time interval used for the scheduler inside the device.
5585 * A value of 0 indicates that the maximum bandwidth is not
5589 /* The bandwidth value. */
5590 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK \
5592 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
5593 /* The granularity of the value (bits or bytes). */
5594 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE \
5595 UINT32_C(0x10000000)
5596 /* Value is in bits. */
5597 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS \
5598 (UINT32_C(0x0) << 28)
5599 /* Value is in bytes. */
5600 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES \
5601 (UINT32_C(0x1) << 28)
5602 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST \
5603 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
5604 /* bw_value_unit is 3 b */
5605 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK \
5606 UINT32_C(0xe0000000)
5607 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
5608 /* Value is in Mb or MB (base 10). */
5609 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
5610 (UINT32_C(0x0) << 29)
5611 /* Value is in Kb or KB (base 10). */
5612 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO \
5613 (UINT32_C(0x2) << 29)
5614 /* Value is in bits or bytes. */
5615 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE \
5616 (UINT32_C(0x4) << 29)
5617 /* Value is in Gb or GB (base 10). */
5618 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
5619 (UINT32_C(0x6) << 29)
5620 /* Value is in 1/100th of a percentage of total bandwidth. */
5621 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
5622 (UINT32_C(0x1) << 29)
5624 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
5625 (UINT32_C(0x7) << 29)
5626 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST \
5627 HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
5629 * This value indicates the Edge virtual bridge mode for the
5630 * domain that this function belongs to.
5633 /* No Edge Virtual Bridging (EVB) */
5634 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
5635 /* Virtual Ethernet Bridge (VEB) */
5636 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
5637 /* Virtual Ethernet Port Aggregator (VEPA) */
5638 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
5639 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_LAST \
5640 HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA
5643 * This value indicates the PCIE device cache line size.
5644 * The cache line size allows the DMA writes to terminate and
5645 * start at the cache boundary.
5647 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \
5649 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
5650 /* Cache Line Size 64 bytes */
5651 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
5653 /* Cache Line Size 128 bytes */
5654 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
5656 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \
5657 HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
5658 /* Reserved for future. */
5659 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \
5661 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2
5663 * The number of VFs that are allocated to the function.
5664 * This is valid only on the PF with SR-IOV enabled.
5665 * 0xFF... (All Fs) if this command is called on a PF with
5666 * SR-IOV disabled or on a VF.
5670 * The number of allocated multicast filters for this
5671 * function on the RX side.
5673 uint32_t alloc_mcast_filters;
5675 * The number of allocated HW ring groups for this
5678 uint32_t alloc_hw_ring_grps;
5680 * The number of strict priority transmit rings out of
5681 * currently allocated TX rings to the function
5684 uint16_t alloc_sp_tx_rings;
5686 * The number of statistics contexts
5687 * currently reserved for the function.
5689 uint16_t alloc_stat_ctx;
5691 * This field specifies how many NQs are reserved for the PF.
5692 * Remaining NQs that belong to the PF are available for VFs.
5693 * Once a PF has created VFs, it cannot change how many NQs are
5694 * reserved for itself (since the NQs must be contiguous in HW).
5696 uint16_t alloc_msix;
5697 uint8_t unused_2[5];
5699 * This field is used in Output records to indicate that the output
5700 * is completely written to RAM. This field should be read as '1'
5701 * to indicate that the output has been completely written.
5702 * When writing a command completion or response to an internal processor,
5703 * the order of writes has to be such that this field is written last.
5706 } __attribute__((packed));
5708 /***********************
5709 * hwrm_func_vlan_qcfg *
5710 ***********************/
5713 /* hwrm_func_vlan_qcfg_input (size:192b/24B) */
5714 struct hwrm_func_vlan_qcfg_input {
5715 /* The HWRM command request type. */
5718 * The completion ring to send the completion event on. This should
5719 * be the NQ ID returned from the `nq_alloc` HWRM command.
5723 * The sequence ID is used by the driver for tracking multiple
5724 * commands. This ID is treated as opaque data by the firmware and
5725 * the value is returned in the `hwrm_resp_hdr` upon completion.
5729 * The target ID of the command:
5730 * * 0x0-0xFFF8 - The function ID
5731 * * 0xFFF8-0xFFFE - Reserved for internal processors
5736 * A physical address pointer pointing to a host buffer that the
5737 * command's response data will be written. This can be either a host
5738 * physical address (HPA) or a guest physical address (GPA) and must
5739 * point to a physically contiguous block of memory.
5743 * Function ID of the function that is being
5745 * If set to 0xFF... (All Fs), then the configuration is
5746 * for the requesting function.
5749 uint8_t unused_0[6];
5750 } __attribute__((packed));
5752 /* hwrm_func_vlan_qcfg_output (size:320b/40B) */
5753 struct hwrm_func_vlan_qcfg_output {
5754 /* The specific error status for the command. */
5755 uint16_t error_code;
5756 /* The HWRM command request type. */
5758 /* The sequence ID from the original command. */
5760 /* The length of the response data in number of bytes. */
5762 uint8_t unused_0[7];
5764 * This field is used in Output records to indicate that the output
5765 * is completely written to RAM. This field should be read as '1'
5766 * to indicate that the output has been completely written.
5767 * When writing a command completion or response to an internal processor,
5768 * the order of writes has to be such that this field is written last.
5771 /* S-TAG VLAN identifier configured for the function. */
5773 /* S-TAG PCP value configured for the function. */
5777 * S-TAG TPID value configured for the function. This field is specified in
5778 * network byte order.
5781 /* C-TAG VLAN identifier configured for the function. */
5783 /* C-TAG PCP value configured for the function. */
5787 * C-TAG TPID value configured for the function. This field is specified in
5788 * network byte order.
5796 } __attribute__((packed));
5798 /**********************
5799 * hwrm_func_vlan_cfg *
5800 **********************/
5803 /* hwrm_func_vlan_cfg_input (size:384b/48B) */
5804 struct hwrm_func_vlan_cfg_input {
5805 /* The HWRM command request type. */
5808 * The completion ring to send the completion event on. This should
5809 * be the NQ ID returned from the `nq_alloc` HWRM command.
5813 * The sequence ID is used by the driver for tracking multiple
5814 * commands. This ID is treated as opaque data by the firmware and
5815 * the value is returned in the `hwrm_resp_hdr` upon completion.
5819 * The target ID of the command:
5820 * * 0x0-0xFFF8 - The function ID
5821 * * 0xFFF8-0xFFFE - Reserved for internal processors
5826 * A physical address pointer pointing to a host buffer that the
5827 * command's response data will be written. This can be either a host
5828 * physical address (HPA) or a guest physical address (GPA) and must
5829 * point to a physically contiguous block of memory.
5833 * Function ID of the function that is being
5835 * If set to 0xFF... (All Fs), then the configuration is
5836 * for the requesting function.
5839 uint8_t unused_0[2];
5842 * This bit must be '1' for the stag_vid field to be
5845 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
5847 * This bit must be '1' for the ctag_vid field to be
5850 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
5852 * This bit must be '1' for the stag_pcp field to be
5855 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
5857 * This bit must be '1' for the ctag_pcp field to be
5860 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
5862 * This bit must be '1' for the stag_tpid field to be
5865 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
5867 * This bit must be '1' for the ctag_tpid field to be
5870 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
5871 /* S-TAG VLAN identifier configured for the function. */
5873 /* S-TAG PCP value configured for the function. */
5877 * S-TAG TPID value configured for the function. This field is specified in
5878 * network byte order.
5881 /* C-TAG VLAN identifier configured for the function. */
5883 /* C-TAG PCP value configured for the function. */
5887 * C-TAG TPID value configured for the function. This field is specified in
5888 * network byte order.
5895 uint8_t unused_3[4];
5896 } __attribute__((packed));
5898 /* hwrm_func_vlan_cfg_output (size:128b/16B) */
5899 struct hwrm_func_vlan_cfg_output {
5900 /* The specific error status for the command. */
5901 uint16_t error_code;
5902 /* The HWRM command request type. */
5904 /* The sequence ID from the original command. */
5906 /* The length of the response data in number of bytes. */
5908 uint8_t unused_0[7];
5910 * This field is used in Output records to indicate that the output
5911 * is completely written to RAM. This field should be read as '1'
5912 * to indicate that the output has been completely written.
5913 * When writing a command completion or response to an internal processor,
5914 * the order of writes has to be such that this field is written last.
5917 } __attribute__((packed));
5924 /* hwrm_func_cfg_input (size:704b/88B) */
5925 struct hwrm_func_cfg_input {
5926 /* The HWRM command request type. */
5929 * The completion ring to send the completion event on. This should
5930 * be the NQ ID returned from the `nq_alloc` HWRM command.
5934 * The sequence ID is used by the driver for tracking multiple
5935 * commands. This ID is treated as opaque data by the firmware and
5936 * the value is returned in the `hwrm_resp_hdr` upon completion.
5940 * The target ID of the command:
5941 * * 0x0-0xFFF8 - The function ID
5942 * * 0xFFF8-0xFFFE - Reserved for internal processors
5947 * A physical address pointer pointing to a host buffer that the
5948 * command's response data will be written. This can be either a host
5949 * physical address (HPA) or a guest physical address (GPA) and must
5950 * point to a physically contiguous block of memory.
5954 * Function ID of the function that is being
5956 * If set to 0xFF... (All Fs), then the the configuration is
5957 * for the requesting function.
5961 * This field specifies how many NQs will be reserved for the PF.
5962 * Remaining NQs that belong to the PF become available for VFs.
5963 * Once a PF has created VFs, it cannot change how many NQs are
5964 * reserved for itself (since the NQs must be contiguous in HW).
5969 * When this bit is '1', the function is disabled with
5970 * source MAC address check.
5971 * This is an anti-spoofing check. If this flag is set,
5972 * then the function shall be configured to disallow
5973 * transmission of frames with the source MAC address that
5974 * is configured for this function.
5976 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \
5979 * When this bit is '1', the function is enabled with
5980 * source MAC address check.
5981 * This is an anti-spoofing check. If this flag is set,
5982 * then the function shall be configured to allow
5983 * transmission of frames with the source MAC address that
5984 * is configured for this function.
5986 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE \
5989 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK \
5991 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
5993 * Standard TX Ring mode is used for the allocation of TX ring
5994 * and underlying scheduling resources that allow bandwidth
5995 * reservation and limit settings on the queried function.
5996 * If set to 1, then standard TX ring mode is requested to be
5997 * enabled on the function being configured.
5999 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE \
6002 * Standard TX Ring mode is used for the allocation of TX ring
6003 * and underlying scheduling resources that allow bandwidth
6004 * reservation and limit settings on the queried function.
6005 * If set to 1, then the standard TX ring mode is requested to
6006 * be disabled on the function being configured. In this extended
6007 * TX ring resource mode, the minimum and maximum bandwidth settings
6008 * are not supported to allow the allocation of TX rings to
6009 * span multiple scheduler nodes.
6011 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE \
6014 * If this bit is set, virtual mac address configured
6015 * in this command will be persistent over warm boot.
6017 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST \
6020 * This bit only applies to the VF. If this bit is set, the statistic
6021 * context counters will not be cleared when the statistic context is freed
6022 * or a function reset is called on VF. This bit will be cleared when the PF
6023 * is unloaded or a function reset is called on the PF.
6025 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC \
6028 * This bit requests that the firmware test to see if all the assets
6029 * requested in this command (i.e. number of TX rings) are available.
6030 * The firmware will return an error if the requested assets are
6031 * not available. The firwmare will NOT reserve the assets if they
6034 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \
6037 * This bit requests that the firmware test to see if all the assets
6038 * requested in this command (i.e. number of RX rings) are available.
6039 * The firmware will return an error if the requested assets are
6040 * not available. The firwmare will NOT reserve the assets if they
6043 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \
6046 * This bit requests that the firmware test to see if all the assets
6047 * requested in this command (i.e. number of CMPL rings) are available.
6048 * The firmware will return an error if the requested assets are
6049 * not available. The firwmare will NOT reserve the assets if they
6052 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \
6055 * This bit requests that the firmware test to see if all the assets
6056 * requested in this command (i.e. number of RSS ctx) are available.
6057 * The firmware will return an error if the requested assets are
6058 * not available. The firwmare will NOT reserve the assets if they
6061 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \
6064 * This bit requests that the firmware test to see if all the assets
6065 * requested in this command (i.e. number of ring groups) are available.
6066 * The firmware will return an error if the requested assets are
6067 * not available. The firwmare will NOT reserve the assets if they
6070 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \
6073 * This bit requests that the firmware test to see if all the assets
6074 * requested in this command (i.e. number of stat ctx) are available.
6075 * The firmware will return an error if the requested assets are
6076 * not available. The firwmare will NOT reserve the assets if they
6079 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \
6082 * This bit requests that the firmware test to see if all the assets
6083 * requested in this command (i.e. number of VNICs) are available.
6084 * The firmware will return an error if the requested assets are
6085 * not available. The firwmare will NOT reserve the assets if they
6088 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \
6091 * This bit requests that the firmware test to see if all the assets
6092 * requested in this command (i.e. number of L2 ctx) are available.
6093 * The firmware will return an error if the requested assets are
6094 * not available. The firwmare will NOT reserve the assets if they
6097 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \
6101 * This bit must be '1' for the mtu field to be
6104 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU \
6107 * This bit must be '1' for the mru field to be
6110 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU \
6113 * This bit must be '1' for the num_rsscos_ctxs field to be
6116 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS \
6119 * This bit must be '1' for the num_cmpl_rings field to be
6122 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS \
6125 * This bit must be '1' for the num_tx_rings field to be
6128 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS \
6131 * This bit must be '1' for the num_rx_rings field to be
6134 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS \
6137 * This bit must be '1' for the num_l2_ctxs field to be
6140 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS \
6143 * This bit must be '1' for the num_vnics field to be
6146 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS \
6149 * This bit must be '1' for the num_stat_ctxs field to be
6152 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS \
6155 * This bit must be '1' for the dflt_mac_addr field to be
6158 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR \
6161 * This bit must be '1' for the dflt_vlan field to be
6164 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN \
6167 * This bit must be '1' for the dflt_ip_addr field to be
6170 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR \
6173 * This bit must be '1' for the min_bw field to be
6176 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW \
6179 * This bit must be '1' for the max_bw field to be
6182 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW \
6185 * This bit must be '1' for the async_event_cr field to be
6188 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR \
6191 * This bit must be '1' for the vlan_antispoof_mode field to be
6194 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE \
6197 * This bit must be '1' for the allowed_vlan_pris field to be
6200 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS \
6203 * This bit must be '1' for the evb_mode field to be
6206 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE \
6209 * This bit must be '1' for the num_mcast_filters field to be
6212 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS \
6215 * This bit must be '1' for the num_hw_ring_grps field to be
6218 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS \
6221 * This bit must be '1' for the cache_linesize field to be
6224 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE \
6227 * This bit must be '1' for the num_msix field to be
6230 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \
6233 * The maximum transmission unit of the function.
6234 * The HWRM should make sure that the mtu of
6235 * the function does not exceed the mtu of the physical
6236 * port that this function is associated with.
6238 * In addition to configuring mtu per function, it is
6239 * possible to configure mtu per transmit ring.
6240 * By default, the mtu of each transmit ring associated
6241 * with a function is equal to the mtu of the function.
6242 * The HWRM should make sure that the mtu of each transmit
6243 * ring that is assigned to a function has a valid mtu.
6247 * The maximum receive unit of the function.
6248 * The HWRM should make sure that the mru of
6249 * the function does not exceed the mru of the physical
6250 * port that this function is associated with.
6252 * In addition to configuring mru per function, it is
6253 * possible to configure mru per vnic.
6254 * By default, the mru of each vnic associated
6255 * with a function is equal to the mru of the function.
6256 * The HWRM should make sure that the mru of each vnic
6257 * that is assigned to a function has a valid mru.
6261 * The number of RSS/COS contexts requested for the
6264 uint16_t num_rsscos_ctxs;
6266 * The number of completion rings requested for the
6267 * function. This does not include the rings allocated
6268 * to any children functions if any.
6270 uint16_t num_cmpl_rings;
6272 * The number of transmit rings requested for the function.
6273 * This does not include the rings allocated to any
6274 * children functions if any.
6276 uint16_t num_tx_rings;
6278 * The number of receive rings requested for the function.
6279 * This does not include the rings allocated
6280 * to any children functions if any.
6282 uint16_t num_rx_rings;
6283 /* The requested number of L2 contexts for the function. */
6284 uint16_t num_l2_ctxs;
6285 /* The requested number of vnics for the function. */
6287 /* The requested number of statistic contexts for the function. */
6288 uint16_t num_stat_ctxs;
6290 * The number of HW ring groups that should
6291 * be reserved for this function.
6293 uint16_t num_hw_ring_grps;
6294 /* The default MAC address for the function being configured. */
6295 uint8_t dflt_mac_addr[6];
6297 * The default VLAN for the function being configured.
6298 * This field's format is same as 802.1Q Tag's
6299 * Tag Control Information (TCI) format that includes both
6300 * Priority Code Point (PCP) and VLAN Identifier (VID).
6304 * The default IP address for the function being configured.
6305 * This address is only used in enabling source property check.
6307 uint32_t dflt_ip_addr[4];
6309 * Minimum BW allocated for this function.
6310 * The HWRM will translate this value into byte counter and
6311 * time interval used for the scheduler inside the device.
6314 /* The bandwidth value. */
6315 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK \
6317 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
6318 /* The granularity of the value (bits or bytes). */
6319 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE \
6320 UINT32_C(0x10000000)
6321 /* Value is in bits. */
6322 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS \
6323 (UINT32_C(0x0) << 28)
6324 /* Value is in bytes. */
6325 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES \
6326 (UINT32_C(0x1) << 28)
6327 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST \
6328 HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
6329 /* bw_value_unit is 3 b */
6330 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK \
6331 UINT32_C(0xe0000000)
6332 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6333 /* Value is in Mb or MB (base 10). */
6334 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA \
6335 (UINT32_C(0x0) << 29)
6336 /* Value is in Kb or KB (base 10). */
6337 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO \
6338 (UINT32_C(0x2) << 29)
6339 /* Value is in bits or bytes. */
6340 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE \
6341 (UINT32_C(0x4) << 29)
6342 /* Value is in Gb or GB (base 10). */
6343 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA \
6344 (UINT32_C(0x6) << 29)
6345 /* Value is in 1/100th of a percentage of total bandwidth. */
6346 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
6347 (UINT32_C(0x1) << 29)
6349 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID \
6350 (UINT32_C(0x7) << 29)
6351 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST \
6352 HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6354 * Maximum BW allocated for this function.
6355 * The HWRM will translate this value into byte counter and
6356 * time interval used for the scheduler inside the device.
6359 /* The bandwidth value. */
6360 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK \
6362 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
6363 /* The granularity of the value (bits or bytes). */
6364 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE \
6365 UINT32_C(0x10000000)
6366 /* Value is in bits. */
6367 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS \
6368 (UINT32_C(0x0) << 28)
6369 /* Value is in bytes. */
6370 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES \
6371 (UINT32_C(0x1) << 28)
6372 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST \
6373 HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
6374 /* bw_value_unit is 3 b */
6375 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
6376 UINT32_C(0xe0000000)
6377 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6378 /* Value is in Mb or MB (base 10). */
6379 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
6380 (UINT32_C(0x0) << 29)
6381 /* Value is in Kb or KB (base 10). */
6382 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
6383 (UINT32_C(0x2) << 29)
6384 /* Value is in bits or bytes. */
6385 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
6386 (UINT32_C(0x4) << 29)
6387 /* Value is in Gb or GB (base 10). */
6388 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
6389 (UINT32_C(0x6) << 29)
6390 /* Value is in 1/100th of a percentage of total bandwidth. */
6391 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
6392 (UINT32_C(0x1) << 29)
6394 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
6395 (UINT32_C(0x7) << 29)
6396 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
6397 HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6399 * ID of the target completion ring for receiving asynchronous
6400 * event completions. If this field is not valid, then the
6401 * HWRM shall use the default completion ring of the function
6402 * that is being configured as the target completion ring for
6403 * providing any asynchronous event completions for that
6405 * If this field is valid, then the HWRM shall use the
6406 * completion ring identified by this ID as the target
6407 * completion ring for providing any asynchronous event
6408 * completions for the function that is being configured.
6410 uint16_t async_event_cr;
6411 /* VLAN Anti-spoofing mode. */
6412 uint8_t vlan_antispoof_mode;
6413 /* No VLAN anti-spoofing checks are enabled */
6414 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK \
6416 /* Validate VLAN against the configured VLAN(s) */
6417 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN \
6419 /* Insert VLAN if it does not exist, otherwise discard */
6420 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE \
6422 /* Insert VLAN if it does not exist, override VLAN if it exists */
6423 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN \
6425 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_LAST \
6426 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
6428 * This bit field defines VLAN PRIs that are allowed on
6430 * If nth bit is set, then VLAN PRI n is allowed on this
6433 uint8_t allowed_vlan_pris;
6435 * The HWRM shall allow a PF driver to change EVB mode for the
6436 * partition it belongs to.
6437 * The HWRM shall not allow a VF driver to change the EVB mode.
6438 * The HWRM shall take into account the switching of EVB mode
6439 * from one to another and reconfigure hardware resources as
6441 * The switching from VEB to VEPA mode requires
6442 * the disabling of the loopback traffic. Additionally,
6443 * source knock outs are handled differently in VEB and VEPA
6447 /* No Edge Virtual Bridging (EVB) */
6448 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6449 /* Virtual Ethernet Bridge (VEB) */
6450 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
6451 /* Virtual Ethernet Port Aggregator (VEPA) */
6452 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
6453 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_LAST \
6454 HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA
6457 * This value indicates the PCIE device cache line size.
6458 * The cache line size allows the DMA writes to terminate and
6459 * start at the cache boundary.
6461 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \
6463 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
6464 /* Cache Line Size 64 bytes */
6465 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \
6467 /* Cache Line Size 128 bytes */
6468 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 \
6470 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \
6471 HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128
6472 /* Reserved for future. */
6473 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \
6475 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2
6477 * The number of multicast filters that should
6478 * be reserved for this function on the RX side.
6480 uint16_t num_mcast_filters;
6481 } __attribute__((packed));
6483 /* hwrm_func_cfg_output (size:128b/16B) */
6484 struct hwrm_func_cfg_output {
6485 /* The specific error status for the command. */
6486 uint16_t error_code;
6487 /* The HWRM command request type. */
6489 /* The sequence ID from the original command. */
6491 /* The length of the response data in number of bytes. */
6493 uint8_t unused_0[7];
6495 * This field is used in Output records to indicate that the output
6496 * is completely written to RAM. This field should be read as '1'
6497 * to indicate that the output has been completely written.
6498 * When writing a command completion or response to an internal processor,
6499 * the order of writes has to be such that this field is written last.
6502 } __attribute__((packed));
6504 /********************
6505 * hwrm_func_qstats *
6506 ********************/
6509 /* hwrm_func_qstats_input (size:192b/24B) */
6510 struct hwrm_func_qstats_input {
6511 /* The HWRM command request type. */
6514 * The completion ring to send the completion event on. This should
6515 * be the NQ ID returned from the `nq_alloc` HWRM command.
6519 * The sequence ID is used by the driver for tracking multiple
6520 * commands. This ID is treated as opaque data by the firmware and
6521 * the value is returned in the `hwrm_resp_hdr` upon completion.
6525 * The target ID of the command:
6526 * * 0x0-0xFFF8 - The function ID
6527 * * 0xFFF8-0xFFFE - Reserved for internal processors
6532 * A physical address pointer pointing to a host buffer that the
6533 * command's response data will be written. This can be either a host
6534 * physical address (HPA) or a guest physical address (GPA) and must
6535 * point to a physically contiguous block of memory.
6539 * Function ID of the function that is being queried.
6540 * 0xFF... (All Fs) if the query is for the requesting
6544 uint8_t unused_0[6];
6545 } __attribute__((packed));
6547 /* hwrm_func_qstats_output (size:1408b/176B) */
6548 struct hwrm_func_qstats_output {
6549 /* The specific error status for the command. */
6550 uint16_t error_code;
6551 /* The HWRM command request type. */
6553 /* The sequence ID from the original command. */
6555 /* The length of the response data in number of bytes. */
6557 /* Number of transmitted unicast packets on the function. */
6558 uint64_t tx_ucast_pkts;
6559 /* Number of transmitted multicast packets on the function. */
6560 uint64_t tx_mcast_pkts;
6561 /* Number of transmitted broadcast packets on the function. */
6562 uint64_t tx_bcast_pkts;
6564 * Number of transmitted packets that were discarded due to
6565 * internal NIC resource problems. For transmit, this
6566 * can only happen if TMP is configured to allow dropping
6567 * in HOL blocking conditions, which is not a normal
6570 uint64_t tx_discard_pkts;
6572 * Number of dropped packets on transmit path on the function.
6573 * These are packets that have been marked for drop by
6574 * the TE CFA block or are packets that exceeded the
6575 * transmit MTU limit for the function.
6577 uint64_t tx_drop_pkts;
6578 /* Number of transmitted bytes for unicast traffic on the function. */
6579 uint64_t tx_ucast_bytes;
6580 /* Number of transmitted bytes for multicast traffic on the function. */
6581 uint64_t tx_mcast_bytes;
6582 /* Number of transmitted bytes for broadcast traffic on the function. */
6583 uint64_t tx_bcast_bytes;
6584 /* Number of received unicast packets on the function. */
6585 uint64_t rx_ucast_pkts;
6586 /* Number of received multicast packets on the function. */
6587 uint64_t rx_mcast_pkts;
6588 /* Number of received broadcast packets on the function. */
6589 uint64_t rx_bcast_pkts;
6591 * Number of received packets that were discarded on the function
6592 * due to resource limitations. This can happen for 3 reasons.
6593 * # The BD used for the packet has a bad format.
6594 * # There were no BDs available in the ring for the packet.
6595 * # There were no BDs available on-chip for the packet.
6597 uint64_t rx_discard_pkts;
6599 * Number of dropped packets on received path on the function.
6600 * These are packets that have been marked for drop by the
6603 uint64_t rx_drop_pkts;
6604 /* Number of received bytes for unicast traffic on the function. */
6605 uint64_t rx_ucast_bytes;
6606 /* Number of received bytes for multicast traffic on the function. */
6607 uint64_t rx_mcast_bytes;
6608 /* Number of received bytes for broadcast traffic on the function. */
6609 uint64_t rx_bcast_bytes;
6610 /* Number of aggregated unicast packets on the function. */
6611 uint64_t rx_agg_pkts;
6612 /* Number of aggregated unicast bytes on the function. */
6613 uint64_t rx_agg_bytes;
6614 /* Number of aggregation events on the function. */
6615 uint64_t rx_agg_events;
6616 /* Number of aborted aggregations on the function. */
6617 uint64_t rx_agg_aborts;
6618 uint8_t unused_0[7];
6620 * This field is used in Output records to indicate that the output
6621 * is completely written to RAM. This field should be read as '1'
6622 * to indicate that the output has been completely written.
6623 * When writing a command completion or response to an internal processor,
6624 * the order of writes has to be such that this field is written last.
6627 } __attribute__((packed));
6629 /***********************
6630 * hwrm_func_clr_stats *
6631 ***********************/
6634 /* hwrm_func_clr_stats_input (size:192b/24B) */
6635 struct hwrm_func_clr_stats_input {
6636 /* The HWRM command request type. */
6639 * The completion ring to send the completion event on. This should
6640 * be the NQ ID returned from the `nq_alloc` HWRM command.
6644 * The sequence ID is used by the driver for tracking multiple
6645 * commands. This ID is treated as opaque data by the firmware and
6646 * the value is returned in the `hwrm_resp_hdr` upon completion.
6650 * The target ID of the command:
6651 * * 0x0-0xFFF8 - The function ID
6652 * * 0xFFF8-0xFFFE - Reserved for internal processors
6657 * A physical address pointer pointing to a host buffer that the
6658 * command's response data will be written. This can be either a host
6659 * physical address (HPA) or a guest physical address (GPA) and must
6660 * point to a physically contiguous block of memory.
6664 * Function ID of the function.
6665 * 0xFF... (All Fs) if the query is for the requesting
6669 uint8_t unused_0[6];
6670 } __attribute__((packed));
6672 /* hwrm_func_clr_stats_output (size:128b/16B) */
6673 struct hwrm_func_clr_stats_output {
6674 /* The specific error status for the command. */
6675 uint16_t error_code;
6676 /* The HWRM command request type. */
6678 /* The sequence ID from the original command. */
6680 /* The length of the response data in number of bytes. */
6682 uint8_t unused_0[7];
6684 * This field is used in Output records to indicate that the output
6685 * is completely written to RAM. This field should be read as '1'
6686 * to indicate that the output has been completely written.
6687 * When writing a command completion or response to an internal processor,
6688 * the order of writes has to be such that this field is written last.
6691 } __attribute__((packed));
6693 /**************************
6694 * hwrm_func_vf_resc_free *
6695 **************************/
6698 /* hwrm_func_vf_resc_free_input (size:192b/24B) */
6699 struct hwrm_func_vf_resc_free_input {
6700 /* The HWRM command request type. */
6703 * The completion ring to send the completion event on. This should
6704 * be the NQ ID returned from the `nq_alloc` HWRM command.
6708 * The sequence ID is used by the driver for tracking multiple
6709 * commands. This ID is treated as opaque data by the firmware and
6710 * the value is returned in the `hwrm_resp_hdr` upon completion.
6714 * The target ID of the command:
6715 * * 0x0-0xFFF8 - The function ID
6716 * * 0xFFF8-0xFFFE - Reserved for internal processors
6721 * A physical address pointer pointing to a host buffer that the
6722 * command's response data will be written. This can be either a host
6723 * physical address (HPA) or a guest physical address (GPA) and must
6724 * point to a physically contiguous block of memory.
6728 * This value is used to identify a Virtual Function (VF).
6729 * The scope of VF ID is local within a PF.
6732 uint8_t unused_0[6];
6733 } __attribute__((packed));
6735 /* hwrm_func_vf_resc_free_output (size:128b/16B) */
6736 struct hwrm_func_vf_resc_free_output {
6737 /* The specific error status for the command. */
6738 uint16_t error_code;
6739 /* The HWRM command request type. */
6741 /* The sequence ID from the original command. */
6743 /* The length of the response data in number of bytes. */
6745 uint8_t unused_0[7];
6747 * This field is used in Output records to indicate that the output
6748 * is completely written to RAM. This field should be read as '1'
6749 * to indicate that the output has been completely written.
6750 * When writing a command completion or response to an internal processor,
6751 * the order of writes has to be such that this field is written last.
6754 } __attribute__((packed));
6756 /*******************************
6757 * hwrm_func_vf_vnic_ids_query *
6758 *******************************/
6761 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */
6762 struct hwrm_func_vf_vnic_ids_query_input {
6763 /* The HWRM command request type. */
6766 * The completion ring to send the completion event on. This should
6767 * be the NQ ID returned from the `nq_alloc` HWRM command.
6771 * The sequence ID is used by the driver for tracking multiple
6772 * commands. This ID is treated as opaque data by the firmware and
6773 * the value is returned in the `hwrm_resp_hdr` upon completion.
6777 * The target ID of the command:
6778 * * 0x0-0xFFF8 - The function ID
6779 * * 0xFFF8-0xFFFE - Reserved for internal processors
6784 * A physical address pointer pointing to a host buffer that the
6785 * command's response data will be written. This can be either a host
6786 * physical address (HPA) or a guest physical address (GPA) and must
6787 * point to a physically contiguous block of memory.
6791 * This value is used to identify a Virtual Function (VF).
6792 * The scope of VF ID is local within a PF.
6795 uint8_t unused_0[2];
6796 /* Max number of vnic ids in vnic id table */
6797 uint32_t max_vnic_id_cnt;
6798 /* This is the address for VF VNIC ID table */
6799 uint64_t vnic_id_tbl_addr;
6800 } __attribute__((packed));
6802 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */
6803 struct hwrm_func_vf_vnic_ids_query_output {
6804 /* The specific error status for the command. */
6805 uint16_t error_code;
6806 /* The HWRM command request type. */
6808 /* The sequence ID from the original command. */
6810 /* The length of the response data in number of bytes. */
6813 * Actual number of vnic ids
6815 * Each VNIC ID is written as a 32-bit number.
6817 uint32_t vnic_id_cnt;
6818 uint8_t unused_0[3];
6820 * This field is used in Output records to indicate that the output
6821 * is completely written to RAM. This field should be read as '1'
6822 * to indicate that the output has been completely written.
6823 * When writing a command completion or response to an internal processor,
6824 * the order of writes has to be such that this field is written last.
6827 } __attribute__((packed));
6829 /**********************
6830 * hwrm_func_drv_rgtr *
6831 **********************/
6834 /* hwrm_func_drv_rgtr_input (size:896b/112B) */
6835 struct hwrm_func_drv_rgtr_input {
6836 /* The HWRM command request type. */
6839 * The completion ring to send the completion event on. This should
6840 * be the NQ ID returned from the `nq_alloc` HWRM command.
6844 * The sequence ID is used by the driver for tracking multiple
6845 * commands. This ID is treated as opaque data by the firmware and
6846 * the value is returned in the `hwrm_resp_hdr` upon completion.
6850 * The target ID of the command:
6851 * * 0x0-0xFFF8 - The function ID
6852 * * 0xFFF8-0xFFFE - Reserved for internal processors
6857 * A physical address pointer pointing to a host buffer that the
6858 * command's response data will be written. This can be either a host
6859 * physical address (HPA) or a guest physical address (GPA) and must
6860 * point to a physically contiguous block of memory.
6865 * When this bit is '1', the function driver is requesting
6866 * all requests from its children VF drivers to be
6867 * forwarded to itself.
6868 * This flag can only be set by the PF driver.
6869 * If a VF driver sets this flag, it should be ignored
6872 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
6874 * When this bit is '1', the function is requesting none of
6875 * the requests from its children VF drivers to be
6876 * forwarded to itself.
6877 * This flag can only be set by the PF driver.
6878 * If a VF driver sets this flag, it should be ignored
6881 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
6883 * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b
6884 * fields shall be ignored and ver_maj, ver_min, ver_upd
6885 * and ver_patch shall be used for the driver version information.
6886 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
6887 * fields shall be used for the driver version information and
6888 * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.
6890 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
6893 * This bit must be '1' for the os_type field to be
6896 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE \
6899 * This bit must be '1' for the ver field to be
6902 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER \
6905 * This bit must be '1' for the timestamp field to be
6908 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP \
6911 * This bit must be '1' for the vf_req_fwd field to be
6914 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD \
6917 * This bit must be '1' for the async_event_fwd field to be
6920 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD \
6922 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
6925 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
6926 /* Other OS not listed below. */
6927 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
6929 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
6931 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
6933 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
6935 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
6937 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
6938 /* VMware ESXi OS. */
6939 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
6940 /* Microsoft Windows 8 64-bit OS. */
6941 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
6942 /* Microsoft Windows Server 2012 R2 OS. */
6943 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
6945 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
6946 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LAST \
6947 HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI
6948 /* This is the 8bit major version of the driver. */
6950 /* This is the 8bit minor version of the driver. */
6952 /* This is the 8bit update version of the driver. */
6954 uint8_t unused_0[3];
6956 * This is a 32-bit timestamp provided by the driver for
6958 * The timestamp is in multiples of 1ms.
6961 uint8_t unused_1[4];
6963 * This is a 256-bit bit mask provided by the PF driver for
6964 * letting the HWRM know what commands issued by the VF driver
6965 * to the HWRM should be forwarded to the PF driver.
6966 * Nth bit refers to the Nth req_type.
6968 * Setting Nth bit to 1 indicates that requests from the
6969 * VF driver with req_type equal to N shall be forwarded to
6970 * the parent PF driver.
6972 * This field is not valid for the VF driver.
6974 uint32_t vf_req_fwd[8];
6976 * This is a 256-bit bit mask provided by the function driver
6977 * (PF or VF driver) to indicate the list of asynchronous event
6978 * completions to be forwarded.
6980 * Nth bit refers to the Nth event_id.
6982 * Setting Nth bit to 1 by the function driver shall result in
6983 * the HWRM forwarding asynchronous event completion with
6984 * event_id equal to N.
6986 * If all bits are set to 0 (value of 0), then the HWRM shall
6987 * not forward any asynchronous event completion to this
6990 uint32_t async_event_fwd[8];
6991 /* This is the 16bit major version of the driver. */
6993 /* This is the 16bit minor version of the driver. */
6995 /* This is the 16bit update version of the driver. */
6997 /* This is the 16bit patch version of the driver. */
6999 } __attribute__((packed));
7001 /* hwrm_func_drv_rgtr_output (size:128b/16B) */
7002 struct hwrm_func_drv_rgtr_output {
7003 /* The specific error status for the command. */
7004 uint16_t error_code;
7005 /* The HWRM command request type. */
7007 /* The sequence ID from the original command. */
7009 /* The length of the response data in number of bytes. */
7011 uint8_t unused_0[7];
7013 * This field is used in Output records to indicate that the output
7014 * is completely written to RAM. This field should be read as '1'
7015 * to indicate that the output has been completely written.
7016 * When writing a command completion or response to an internal processor,
7017 * the order of writes has to be such that this field is written last.
7020 } __attribute__((packed));
7022 /************************
7023 * hwrm_func_drv_unrgtr *
7024 ************************/
7027 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */
7028 struct hwrm_func_drv_unrgtr_input {
7029 /* The HWRM command request type. */
7032 * The completion ring to send the completion event on. This should
7033 * be the NQ ID returned from the `nq_alloc` HWRM command.
7037 * The sequence ID is used by the driver for tracking multiple
7038 * commands. This ID is treated as opaque data by the firmware and
7039 * the value is returned in the `hwrm_resp_hdr` upon completion.
7043 * The target ID of the command:
7044 * * 0x0-0xFFF8 - The function ID
7045 * * 0xFFF8-0xFFFE - Reserved for internal processors
7050 * A physical address pointer pointing to a host buffer that the
7051 * command's response data will be written. This can be either a host
7052 * physical address (HPA) or a guest physical address (GPA) and must
7053 * point to a physically contiguous block of memory.
7058 * When this bit is '1', the function driver is notifying
7059 * the HWRM to prepare for the shutdown.
7061 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN \
7063 uint8_t unused_0[4];
7064 } __attribute__((packed));
7066 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */
7067 struct hwrm_func_drv_unrgtr_output {
7068 /* The specific error status for the command. */
7069 uint16_t error_code;
7070 /* The HWRM command request type. */
7072 /* The sequence ID from the original command. */
7074 /* The length of the response data in number of bytes. */
7076 uint8_t unused_0[7];
7078 * This field is used in Output records to indicate that the output
7079 * is completely written to RAM. This field should be read as '1'
7080 * to indicate that the output has been completely written.
7081 * When writing a command completion or response to an internal processor,
7082 * the order of writes has to be such that this field is written last.
7085 } __attribute__((packed));
7087 /**********************
7088 * hwrm_func_buf_rgtr *
7089 **********************/
7092 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */
7093 struct hwrm_func_buf_rgtr_input {
7094 /* The HWRM command request type. */
7097 * The completion ring to send the completion event on. This should
7098 * be the NQ ID returned from the `nq_alloc` HWRM command.
7102 * The sequence ID is used by the driver for tracking multiple
7103 * commands. This ID is treated as opaque data by the firmware and
7104 * the value is returned in the `hwrm_resp_hdr` upon completion.
7108 * The target ID of the command:
7109 * * 0x0-0xFFF8 - The function ID
7110 * * 0xFFF8-0xFFFE - Reserved for internal processors
7115 * A physical address pointer pointing to a host buffer that the
7116 * command's response data will be written. This can be either a host
7117 * physical address (HPA) or a guest physical address (GPA) and must
7118 * point to a physically contiguous block of memory.
7123 * This bit must be '1' for the vf_id field to be
7126 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7128 * This bit must be '1' for the err_buf_addr field to be
7131 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
7133 * This value is used to identify a Virtual Function (VF).
7134 * The scope of VF ID is local within a PF.
7138 * This field represents the number of pages used for request
7141 uint16_t req_buf_num_pages;
7143 * This field represents the page size used for request
7146 uint16_t req_buf_page_size;
7148 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
7150 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
7152 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
7154 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
7156 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
7158 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
7160 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
7161 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_LAST \
7162 HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G
7163 /* The length of the request buffer per VF in bytes. */
7164 uint16_t req_buf_len;
7165 /* The length of the response buffer in bytes. */
7166 uint16_t resp_buf_len;
7167 uint8_t unused_0[2];
7168 /* This field represents the page address of page #0. */
7169 uint64_t req_buf_page_addr0;
7170 /* This field represents the page address of page #1. */
7171 uint64_t req_buf_page_addr1;
7172 /* This field represents the page address of page #2. */
7173 uint64_t req_buf_page_addr2;
7174 /* This field represents the page address of page #3. */
7175 uint64_t req_buf_page_addr3;
7176 /* This field represents the page address of page #4. */
7177 uint64_t req_buf_page_addr4;
7178 /* This field represents the page address of page #5. */
7179 uint64_t req_buf_page_addr5;
7180 /* This field represents the page address of page #6. */
7181 uint64_t req_buf_page_addr6;
7182 /* This field represents the page address of page #7. */
7183 uint64_t req_buf_page_addr7;
7184 /* This field represents the page address of page #8. */
7185 uint64_t req_buf_page_addr8;
7186 /* This field represents the page address of page #9. */
7187 uint64_t req_buf_page_addr9;
7189 * This field is used to receive the error reporting from
7190 * the chipset. Only applicable for PFs.
7192 uint64_t error_buf_addr;
7194 * This field is used to receive the response forwarded by the
7197 uint64_t resp_buf_addr;
7198 } __attribute__((packed));
7200 /* hwrm_func_buf_rgtr_output (size:128b/16B) */
7201 struct hwrm_func_buf_rgtr_output {
7202 /* The specific error status for the command. */
7203 uint16_t error_code;
7204 /* The HWRM command request type. */
7206 /* The sequence ID from the original command. */
7208 /* The length of the response data in number of bytes. */
7210 uint8_t unused_0[7];
7212 * This field is used in Output records to indicate that the output
7213 * is completely written to RAM. This field should be read as '1'
7214 * to indicate that the output has been completely written.
7215 * When writing a command completion or response to an internal processor,
7216 * the order of writes has to be such that this field is written last.
7219 } __attribute__((packed));
7221 /************************
7222 * hwrm_func_buf_unrgtr *
7223 ************************/
7226 /* hwrm_func_buf_unrgtr_input (size:192b/24B) */
7227 struct hwrm_func_buf_unrgtr_input {
7228 /* The HWRM command request type. */
7231 * The completion ring to send the completion event on. This should
7232 * be the NQ ID returned from the `nq_alloc` HWRM command.
7236 * The sequence ID is used by the driver for tracking multiple
7237 * commands. This ID is treated as opaque data by the firmware and
7238 * the value is returned in the `hwrm_resp_hdr` upon completion.
7242 * The target ID of the command:
7243 * * 0x0-0xFFF8 - The function ID
7244 * * 0xFFF8-0xFFFE - Reserved for internal processors
7249 * A physical address pointer pointing to a host buffer that the
7250 * command's response data will be written. This can be either a host
7251 * physical address (HPA) or a guest physical address (GPA) and must
7252 * point to a physically contiguous block of memory.
7257 * This bit must be '1' for the vf_id field to be
7260 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
7262 * This value is used to identify a Virtual Function (VF).
7263 * The scope of VF ID is local within a PF.
7266 uint8_t unused_0[2];
7267 } __attribute__((packed));
7269 /* hwrm_func_buf_unrgtr_output (size:128b/16B) */
7270 struct hwrm_func_buf_unrgtr_output {
7271 /* The specific error status for the command. */
7272 uint16_t error_code;
7273 /* The HWRM command request type. */
7275 /* The sequence ID from the original command. */
7277 /* The length of the response data in number of bytes. */
7279 uint8_t unused_0[7];
7281 * This field is used in Output records to indicate that the output
7282 * is completely written to RAM. This field should be read as '1'
7283 * to indicate that the output has been completely written.
7284 * When writing a command completion or response to an internal processor,
7285 * the order of writes has to be such that this field is written last.
7288 } __attribute__((packed));
7290 /**********************
7291 * hwrm_func_drv_qver *
7292 **********************/
7295 /* hwrm_func_drv_qver_input (size:192b/24B) */
7296 struct hwrm_func_drv_qver_input {
7297 /* The HWRM command request type. */
7300 * The completion ring to send the completion event on. This should
7301 * be the NQ ID returned from the `nq_alloc` HWRM command.
7305 * The sequence ID is used by the driver for tracking multiple
7306 * commands. This ID is treated as opaque data by the firmware and
7307 * the value is returned in the `hwrm_resp_hdr` upon completion.
7311 * The target ID of the command:
7312 * * 0x0-0xFFF8 - The function ID
7313 * * 0xFFF8-0xFFFE - Reserved for internal processors
7318 * A physical address pointer pointing to a host buffer that the
7319 * command's response data will be written. This can be either a host
7320 * physical address (HPA) or a guest physical address (GPA) and must
7321 * point to a physically contiguous block of memory.
7324 /* Reserved for future use. */
7327 * Function ID of the function that is being queried.
7328 * 0xFF... (All Fs) if the query is for the requesting
7332 uint8_t unused_0[2];
7333 } __attribute__((packed));
7335 /* hwrm_func_drv_qver_output (size:192b/24B) */
7336 struct hwrm_func_drv_qver_output {
7337 /* The specific error status for the command. */
7338 uint16_t error_code;
7339 /* The HWRM command request type. */
7341 /* The sequence ID from the original command. */
7343 /* The length of the response data in number of bytes. */
7345 /* This value indicates the type of OS. The values are based on CIM_OperatingSystem.mof file as published by the DMTF. */
7348 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7349 /* Other OS not listed below. */
7350 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
7352 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7354 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7356 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7358 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
7360 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7361 /* VMware ESXi OS. */
7362 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
7363 /* Microsoft Windows 8 64-bit OS. */
7364 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7365 /* Microsoft Windows Server 2012 R2 OS. */
7366 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7368 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
7369 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LAST \
7370 HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI
7371 /* This is the 8bit major version of the driver. */
7373 /* This is the 8bit minor version of the driver. */
7375 /* This is the 8bit update version of the driver. */
7377 uint8_t unused_0[2];
7379 * This field is used in Output records to indicate that the output
7380 * is completely written to RAM. This field should be read as '1'
7381 * to indicate that the output has been completely written.
7382 * When writing a command completion or response to an internal processor,
7383 * the order of writes has to be such that this field is written last.
7386 /* This is the 16bit major version of the driver. */
7388 /* This is the 16bit minor version of the driver. */
7390 /* This is the 16bit update version of the driver. */
7392 /* This is the 16bit patch version of the driver. */
7394 } __attribute__((packed));
7396 /****************************
7397 * hwrm_func_resource_qcaps *
7398 ****************************/
7401 /* hwrm_func_resource_qcaps_input (size:192b/24B) */
7402 struct hwrm_func_resource_qcaps_input {
7403 /* The HWRM command request type. */
7406 * The completion ring to send the completion event on. This should
7407 * be the NQ ID returned from the `nq_alloc` HWRM command.
7411 * The sequence ID is used by the driver for tracking multiple
7412 * commands. This ID is treated as opaque data by the firmware and
7413 * the value is returned in the `hwrm_resp_hdr` upon completion.
7417 * The target ID of the command:
7418 * * 0x0-0xFFF8 - The function ID
7419 * * 0xFFF8-0xFFFE - Reserved for internal processors
7424 * A physical address pointer pointing to a host buffer that the
7425 * command's response data will be written. This can be either a host
7426 * physical address (HPA) or a guest physical address (GPA) and must
7427 * point to a physically contiguous block of memory.
7431 * Function ID of the function that is being queried.
7432 * 0xFF... (All Fs) if the query is for the requesting
7436 uint8_t unused_0[6];
7437 } __attribute__((packed));
7439 /* hwrm_func_resource_qcaps_output (size:448b/56B) */
7440 struct hwrm_func_resource_qcaps_output {
7441 /* The specific error status for the command. */
7442 uint16_t error_code;
7443 /* The HWRM command request type. */
7445 /* The sequence ID from the original command. */
7447 /* The length of the response data in number of bytes. */
7449 /* Maximum guaranteed number of VFs supported by PF. Not applicable for VFs. */
7451 /* Maximum guaranteed number of MSI-X vectors supported by function */
7453 /* Hint of strategy to be used by PF driver to reserve resources for its VF */
7454 uint16_t vf_reservation_strategy;
7455 /* The PF driver should evenly divide its remaining resources among all VFs. */
7456 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL \
7458 /* The PF driver should only reserve minimal resources for each VF. */
7459 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL \
7462 * The PF driver should not reserve any resources for each VF until the
7463 * the VF interface is brought up.
7465 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC \
7467 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_LAST \
7468 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
7469 /* Minimum guaranteed number of RSS/COS contexts */
7470 uint16_t min_rsscos_ctx;
7471 /* Maximum non-guaranteed number of RSS/COS contexts */
7472 uint16_t max_rsscos_ctx;
7473 /* Minimum guaranteed number of completion rings */
7474 uint16_t min_cmpl_rings;
7475 /* Maximum non-guaranteed number of completion rings */
7476 uint16_t max_cmpl_rings;
7477 /* Minimum guaranteed number of transmit rings */
7478 uint16_t min_tx_rings;
7479 /* Maximum non-guaranteed number of transmit rings */
7480 uint16_t max_tx_rings;
7481 /* Minimum guaranteed number of receive rings */
7482 uint16_t min_rx_rings;
7483 /* Maximum non-guaranteed number of receive rings */
7484 uint16_t max_rx_rings;
7485 /* Minimum guaranteed number of L2 contexts */
7486 uint16_t min_l2_ctxs;
7487 /* Maximum non-guaranteed number of L2 contexts */
7488 uint16_t max_l2_ctxs;
7489 /* Minimum guaranteed number of VNICs */
7491 /* Maximum non-guaranteed number of VNICs */
7493 /* Minimum guaranteed number of statistic contexts */
7494 uint16_t min_stat_ctx;
7495 /* Maximum non-guaranteed number of statistic contexts */
7496 uint16_t max_stat_ctx;
7497 /* Minimum guaranteed number of ring groups */
7498 uint16_t min_hw_ring_grps;
7499 /* Maximum non-guaranteed number of ring groups */
7500 uint16_t max_hw_ring_grps;
7502 * Maximum number of inputs into the transmit scheduler for this function.
7503 * The number of TX rings assigned to the function cannot exceed this value.
7505 uint16_t max_tx_scheduler_inputs;
7506 uint8_t unused_0[7];
7508 * This field is used in Output records to indicate that the output
7509 * is completely written to RAM. This field should be read as '1'
7510 * to indicate that the output has been completely written.
7511 * When writing a command completion or response to an internal processor,
7512 * the order of writes has to be such that this field is written last.
7515 } __attribute__((packed));
7517 /*****************************
7518 * hwrm_func_vf_resource_cfg *
7519 *****************************/
7522 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */
7523 struct hwrm_func_vf_resource_cfg_input {
7524 /* The HWRM command request type. */
7527 * The completion ring to send the completion event on. This should
7528 * be the NQ ID returned from the `nq_alloc` HWRM command.
7532 * The sequence ID is used by the driver for tracking multiple
7533 * commands. This ID is treated as opaque data by the firmware and
7534 * the value is returned in the `hwrm_resp_hdr` upon completion.
7538 * The target ID of the command:
7539 * * 0x0-0xFFF8 - The function ID
7540 * * 0xFFF8-0xFFFE - Reserved for internal processors
7545 * A physical address pointer pointing to a host buffer that the
7546 * command's response data will be written. This can be either a host
7547 * physical address (HPA) or a guest physical address (GPA) and must
7548 * point to a physically contiguous block of memory.
7551 /* VF ID that is being configured by PF */
7553 /* Maximum guaranteed number of MSI-X vectors for the function */
7555 /* Minimum guaranteed number of RSS/COS contexts */
7556 uint16_t min_rsscos_ctx;
7557 /* Maximum non-guaranteed number of RSS/COS contexts */
7558 uint16_t max_rsscos_ctx;
7559 /* Minimum guaranteed number of completion rings */
7560 uint16_t min_cmpl_rings;
7561 /* Maximum non-guaranteed number of completion rings */
7562 uint16_t max_cmpl_rings;
7563 /* Minimum guaranteed number of transmit rings */
7564 uint16_t min_tx_rings;
7565 /* Maximum non-guaranteed number of transmit rings */
7566 uint16_t max_tx_rings;
7567 /* Minimum guaranteed number of receive rings */
7568 uint16_t min_rx_rings;
7569 /* Maximum non-guaranteed number of receive rings */
7570 uint16_t max_rx_rings;
7571 /* Minimum guaranteed number of L2 contexts */
7572 uint16_t min_l2_ctxs;
7573 /* Maximum non-guaranteed number of L2 contexts */
7574 uint16_t max_l2_ctxs;
7575 /* Minimum guaranteed number of VNICs */
7577 /* Maximum non-guaranteed number of VNICs */
7579 /* Minimum guaranteed number of statistic contexts */
7580 uint16_t min_stat_ctx;
7581 /* Maximum non-guaranteed number of statistic contexts */
7582 uint16_t max_stat_ctx;
7583 /* Minimum guaranteed number of ring groups */
7584 uint16_t min_hw_ring_grps;
7585 /* Maximum non-guaranteed number of ring groups */
7586 uint16_t max_hw_ring_grps;
7587 uint8_t unused_0[4];
7588 } __attribute__((packed));
7590 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
7591 struct hwrm_func_vf_resource_cfg_output {
7592 /* The specific error status for the command. */
7593 uint16_t error_code;
7594 /* The HWRM command request type. */
7596 /* The sequence ID from the original command. */
7598 /* The length of the response data in number of bytes. */
7600 /* Reserved number of RSS/COS contexts */
7601 uint16_t reserved_rsscos_ctx;
7602 /* Reserved number of completion rings */
7603 uint16_t reserved_cmpl_rings;
7604 /* Reserved number of transmit rings */
7605 uint16_t reserved_tx_rings;
7606 /* Reserved number of receive rings */
7607 uint16_t reserved_rx_rings;
7608 /* Reserved number of L2 contexts */
7609 uint16_t reserved_l2_ctxs;
7610 /* Reserved number of VNICs */
7611 uint16_t reserved_vnics;
7612 /* Reserved number of statistic contexts */
7613 uint16_t reserved_stat_ctx;
7614 /* Reserved number of ring groups */
7615 uint16_t reserved_hw_ring_grps;
7616 uint8_t unused_0[7];
7618 * This field is used in Output records to indicate that the output
7619 * is completely written to RAM. This field should be read as '1'
7620 * to indicate that the output has been completely written.
7621 * When writing a command completion or response to an internal processor,
7622 * the order of writes has to be such that this field is written last.
7625 } __attribute__((packed));
7627 /*********************************
7628 * hwrm_func_backing_store_qcaps *
7629 *********************************/
7632 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
7633 struct hwrm_func_backing_store_qcaps_input {
7634 /* The HWRM command request type. */
7637 * The completion ring to send the completion event on. This should
7638 * be the NQ ID returned from the `nq_alloc` HWRM command.
7642 * The sequence ID is used by the driver for tracking multiple
7643 * commands. This ID is treated as opaque data by the firmware and
7644 * the value is returned in the `hwrm_resp_hdr` upon completion.
7648 * The target ID of the command:
7649 * * 0x0-0xFFF8 - The function ID
7650 * * 0xFFF8-0xFFFE - Reserved for internal processors
7655 * A physical address pointer pointing to a host buffer that the
7656 * command's response data will be written. This can be either a host
7657 * physical address (HPA) or a guest physical address (GPA) and must
7658 * point to a physically contiguous block of memory.
7661 } __attribute__((packed));
7663 /* hwrm_func_backing_store_qcaps_output (size:512b/64B) */
7664 struct hwrm_func_backing_store_qcaps_output {
7665 /* The specific error status for the command. */
7666 uint16_t error_code;
7667 /* The HWRM command request type. */
7669 /* The sequence ID from the original command. */
7671 /* The length of the response data in number of bytes. */
7673 /* Maximum number of QP context entries supported for this function. */
7674 uint32_t qp_max_entries;
7676 * Minimum number of QP context entries that are needed to be reserved
7677 * for QP1 for the PF and its VFs. PF drivers must allocate at least
7678 * this many QP context entries, even if RoCE will not be used.
7680 uint16_t qp_min_qp1_entries;
7681 /* Maximum number of QP context entries that can be used for L2. */
7682 uint16_t qp_max_l2_entries;
7683 /* Number of bytes that must be allocated for each context entry. */
7684 uint16_t qp_entry_size;
7685 /* Maximum number of SRQ context entries that can be used for L2. */
7686 uint16_t srq_max_l2_entries;
7687 /* Maximum number of SRQ context entries supported for this function. */
7688 uint32_t srq_max_entries;
7689 /* Number of bytes that must be allocated for each context entry. */
7690 uint16_t srq_entry_size;
7691 /* Maximum number of CQ context entries that can be used for L2. */
7692 uint16_t cq_max_l2_entries;
7693 /* Maximum number of CQ context entries supported for this function. */
7694 uint32_t cq_max_entries;
7695 /* Number of bytes that must be allocated for each context entry. */
7696 uint16_t cq_entry_size;
7697 /* Maximum number of VNIC context entries supported for this function. */
7698 uint16_t vnic_max_vnic_entries;
7699 /* Maximum number of Ring table context entries supported for this function. */
7700 uint16_t vnic_max_ring_table_entries;
7701 /* Number of bytes that must be allocated for each context entry. */
7702 uint16_t vnic_entry_size;
7703 /* Maximum number of statistic context entries supported for this function. */
7704 uint32_t stat_max_entries;
7705 /* Number of bytes that must be allocated for each context entry. */
7706 uint16_t stat_entry_size;
7707 /* Maximum number of TQM context entries supported per ring. */
7708 uint16_t tqm_max_entries_per_ring;
7709 /* Number of bytes that must be allocated for each context entry. */
7710 uint16_t tqm_entry_size;
7711 /* Number of bytes that must be allocated for each context entry. */
7712 uint16_t mrav_entry_size;
7713 /* Maximum number of MR/AV context entries supported for this function. */
7714 uint32_t mrav_max_entries;
7715 /* Maximum number of Timer context entries supported for this function. */
7716 uint32_t tim_max_entries;
7717 /* Number of bytes that must be allocated for each context entry. */
7718 uint16_t tim_entry_size;
7721 * This field is used in Output records to indicate that the output
7722 * is completely written to RAM. This field should be read as '1'
7723 * to indicate that the output has been completely written.
7724 * When writing a command completion or response to an internal processor,
7725 * the order of writes has to be such that this field is written last.
7728 } __attribute__((packed));
7730 /*******************************
7731 * hwrm_func_backing_store_cfg *
7732 *******************************/
7735 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */
7736 struct hwrm_func_backing_store_cfg_input {
7737 /* The HWRM command request type. */
7740 * The completion ring to send the completion event on. This should
7741 * be the NQ ID returned from the `nq_alloc` HWRM command.
7745 * The sequence ID is used by the driver for tracking multiple
7746 * commands. This ID is treated as opaque data by the firmware and
7747 * the value is returned in the `hwrm_resp_hdr` upon completion.
7751 * The target ID of the command:
7752 * * 0x0-0xFFF8 - The function ID
7753 * * 0xFFF8-0xFFFE - Reserved for internal processors
7758 * A physical address pointer pointing to a host buffer that the
7759 * command's response data will be written. This can be either a host
7760 * physical address (HPA) or a guest physical address (GPA) and must
7761 * point to a physically contiguous block of memory.
7766 * When set, the firmware only uses on-chip resources and does not
7767 * expect any backing store to be provided by the host driver. This
7768 * mode provides minimal L2 functionality (e.g. limited L2 resources,
7771 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
7775 * This bit must be '1' for the qp fields to be
7778 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP \
7781 * This bit must be '1' for the srq fields to be
7784 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ \
7787 * This bit must be '1' for the cq fields to be
7790 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ \
7793 * This bit must be '1' for the vnic fields to be
7796 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC \
7799 * This bit must be '1' for the stat fields to be
7802 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT \
7805 * This bit must be '1' for the tqm_sp fields to be
7808 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP \
7811 * This bit must be '1' for the tqm_ring0 fields to be
7814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 \
7817 * This bit must be '1' for the tqm_ring1 fields to be
7820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 \
7823 * This bit must be '1' for the tqm_ring2 fields to be
7826 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 \
7829 * This bit must be '1' for the tqm_ring3 fields to be
7832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 \
7835 * This bit must be '1' for the tqm_ring4 fields to be
7838 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 \
7841 * This bit must be '1' for the tqm_ring5 fields to be
7844 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 \
7847 * This bit must be '1' for the tqm_ring6 fields to be
7850 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 \
7853 * This bit must be '1' for the tqm_ring7 fields to be
7856 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 \
7859 * This bit must be '1' for the mrav fields to be
7862 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV \
7865 * This bit must be '1' for the tim fields to be
7868 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \
7870 /* QPC page size and level. */
7871 uint8_t qpc_pg_size_qpc_lvl;
7872 /* QPC PBL indirect levels. */
7873 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK \
7875 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
7876 /* PBL pointer is physical start address. */
7877 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 \
7879 /* PBL pointer points to PTE table. */
7880 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 \
7882 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7883 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 \
7885 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LAST \
7886 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2
7887 /* QPC page size. */
7888 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK \
7890 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_SFT 4
7892 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K \
7893 (UINT32_C(0x0) << 4)
7895 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K \
7896 (UINT32_C(0x1) << 4)
7898 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K \
7899 (UINT32_C(0x2) << 4)
7901 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M \
7902 (UINT32_C(0x3) << 4)
7904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M \
7905 (UINT32_C(0x4) << 4)
7907 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G \
7908 (UINT32_C(0x5) << 4)
7909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_LAST \
7910 HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G
7911 /* SRQ page size and level. */
7912 uint8_t srq_pg_size_srq_lvl;
7913 /* SRQ PBL indirect levels. */
7914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK \
7916 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
7917 /* PBL pointer is physical start address. */
7918 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 \
7920 /* PBL pointer points to PTE table. */
7921 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 \
7923 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7924 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 \
7926 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LAST \
7927 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2
7928 /* SRQ page size. */
7929 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK \
7931 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_SFT 4
7933 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K \
7934 (UINT32_C(0x0) << 4)
7936 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K \
7937 (UINT32_C(0x1) << 4)
7939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K \
7940 (UINT32_C(0x2) << 4)
7942 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M \
7943 (UINT32_C(0x3) << 4)
7945 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M \
7946 (UINT32_C(0x4) << 4)
7948 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G \
7949 (UINT32_C(0x5) << 4)
7950 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_LAST \
7951 HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G
7952 /* CQ page size and level. */
7953 uint8_t cq_pg_size_cq_lvl;
7954 /* CQ PBL indirect levels. */
7955 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK \
7957 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
7958 /* PBL pointer is physical start address. */
7959 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 \
7961 /* PBL pointer points to PTE table. */
7962 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 \
7964 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
7965 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 \
7967 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LAST \
7968 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2
7970 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK \
7972 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_SFT 4
7974 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K \
7975 (UINT32_C(0x0) << 4)
7977 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K \
7978 (UINT32_C(0x1) << 4)
7980 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K \
7981 (UINT32_C(0x2) << 4)
7983 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M \
7984 (UINT32_C(0x3) << 4)
7986 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M \
7987 (UINT32_C(0x4) << 4)
7989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G \
7990 (UINT32_C(0x5) << 4)
7991 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_LAST \
7992 HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G
7993 /* VNIC page size and level. */
7994 uint8_t vnic_pg_size_vnic_lvl;
7995 /* VNIC PBL indirect levels. */
7996 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK \
7998 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
7999 /* PBL pointer is physical start address. */
8000 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 \
8002 /* PBL pointer points to PTE table. */
8003 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 \
8005 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8006 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 \
8008 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LAST \
8009 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2
8010 /* VNIC page size. */
8011 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK \
8013 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_SFT 4
8015 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K \
8016 (UINT32_C(0x0) << 4)
8018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K \
8019 (UINT32_C(0x1) << 4)
8021 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K \
8022 (UINT32_C(0x2) << 4)
8024 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M \
8025 (UINT32_C(0x3) << 4)
8027 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M \
8028 (UINT32_C(0x4) << 4)
8030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G \
8031 (UINT32_C(0x5) << 4)
8032 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_LAST \
8033 HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G
8034 /* Stat page size and level. */
8035 uint8_t stat_pg_size_stat_lvl;
8036 /* Stat PBL indirect levels. */
8037 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK \
8039 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
8040 /* PBL pointer is physical start address. */
8041 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 \
8043 /* PBL pointer points to PTE table. */
8044 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 \
8046 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8047 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 \
8049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LAST \
8050 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2
8051 /* Stat page size. */
8052 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK \
8054 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_SFT 4
8056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K \
8057 (UINT32_C(0x0) << 4)
8059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K \
8060 (UINT32_C(0x1) << 4)
8062 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K \
8063 (UINT32_C(0x2) << 4)
8065 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M \
8066 (UINT32_C(0x3) << 4)
8068 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M \
8069 (UINT32_C(0x4) << 4)
8071 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G \
8072 (UINT32_C(0x5) << 4)
8073 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_LAST \
8074 HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G
8075 /* TQM slow path page size and level. */
8076 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
8077 /* TQM slow path PBL indirect levels. */
8078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK \
8080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
8081 /* PBL pointer is physical start address. */
8082 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 \
8084 /* PBL pointer points to PTE table. */
8085 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 \
8087 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8088 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 \
8090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LAST \
8091 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2
8092 /* TQM slow path page size. */
8093 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK \
8095 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_SFT 4
8097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K \
8098 (UINT32_C(0x0) << 4)
8100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K \
8101 (UINT32_C(0x1) << 4)
8103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K \
8104 (UINT32_C(0x2) << 4)
8106 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M \
8107 (UINT32_C(0x3) << 4)
8109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M \
8110 (UINT32_C(0x4) << 4)
8112 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G \
8113 (UINT32_C(0x5) << 4)
8114 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_LAST \
8115 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G
8116 /* TQM ring 0 page size and level. */
8117 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
8118 /* TQM ring 0 PBL indirect levels. */
8119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK \
8121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
8122 /* PBL pointer is physical start address. */
8123 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 \
8125 /* PBL pointer points to PTE table. */
8126 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 \
8128 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8129 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 \
8131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LAST \
8132 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2
8133 /* TQM ring 0 page size. */
8134 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK \
8136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_SFT 4
8138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K \
8139 (UINT32_C(0x0) << 4)
8141 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K \
8142 (UINT32_C(0x1) << 4)
8144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K \
8145 (UINT32_C(0x2) << 4)
8147 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M \
8148 (UINT32_C(0x3) << 4)
8150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M \
8151 (UINT32_C(0x4) << 4)
8153 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G \
8154 (UINT32_C(0x5) << 4)
8155 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_LAST \
8156 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G
8157 /* TQM ring 1 page size and level. */
8158 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
8159 /* TQM ring 1 PBL indirect levels. */
8160 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK \
8162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
8163 /* PBL pointer is physical start address. */
8164 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 \
8166 /* PBL pointer points to PTE table. */
8167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 \
8169 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8170 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 \
8172 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LAST \
8173 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2
8174 /* TQM ring 1 page size. */
8175 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK \
8177 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_SFT 4
8179 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K \
8180 (UINT32_C(0x0) << 4)
8182 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K \
8183 (UINT32_C(0x1) << 4)
8185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K \
8186 (UINT32_C(0x2) << 4)
8188 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M \
8189 (UINT32_C(0x3) << 4)
8191 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M \
8192 (UINT32_C(0x4) << 4)
8194 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G \
8195 (UINT32_C(0x5) << 4)
8196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_LAST \
8197 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G
8198 /* TQM ring 2 page size and level. */
8199 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
8200 /* TQM ring 2 PBL indirect levels. */
8201 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK \
8203 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
8204 /* PBL pointer is physical start address. */
8205 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 \
8207 /* PBL pointer points to PTE table. */
8208 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 \
8210 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 \
8213 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LAST \
8214 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2
8215 /* TQM ring 2 page size. */
8216 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK \
8218 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_SFT 4
8220 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K \
8221 (UINT32_C(0x0) << 4)
8223 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K \
8224 (UINT32_C(0x1) << 4)
8226 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K \
8227 (UINT32_C(0x2) << 4)
8229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M \
8230 (UINT32_C(0x3) << 4)
8232 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M \
8233 (UINT32_C(0x4) << 4)
8235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G \
8236 (UINT32_C(0x5) << 4)
8237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_LAST \
8238 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G
8239 /* TQM ring 3 page size and level. */
8240 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
8241 /* TQM ring 3 PBL indirect levels. */
8242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK \
8244 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
8245 /* PBL pointer is physical start address. */
8246 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 \
8248 /* PBL pointer points to PTE table. */
8249 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 \
8251 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 \
8254 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LAST \
8255 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2
8256 /* TQM ring 3 page size. */
8257 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK \
8259 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_SFT 4
8261 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K \
8262 (UINT32_C(0x0) << 4)
8264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K \
8265 (UINT32_C(0x1) << 4)
8267 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K \
8268 (UINT32_C(0x2) << 4)
8270 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M \
8271 (UINT32_C(0x3) << 4)
8273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M \
8274 (UINT32_C(0x4) << 4)
8276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G \
8277 (UINT32_C(0x5) << 4)
8278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_LAST \
8279 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G
8280 /* TQM ring 4 page size and level. */
8281 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
8282 /* TQM ring 4 PBL indirect levels. */
8283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK \
8285 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
8286 /* PBL pointer is physical start address. */
8287 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 \
8289 /* PBL pointer points to PTE table. */
8290 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 \
8292 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 \
8295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LAST \
8296 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2
8297 /* TQM ring 4 page size. */
8298 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK \
8300 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_SFT 4
8302 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K \
8303 (UINT32_C(0x0) << 4)
8305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K \
8306 (UINT32_C(0x1) << 4)
8308 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K \
8309 (UINT32_C(0x2) << 4)
8311 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M \
8312 (UINT32_C(0x3) << 4)
8314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M \
8315 (UINT32_C(0x4) << 4)
8317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G \
8318 (UINT32_C(0x5) << 4)
8319 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_LAST \
8320 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G
8321 /* TQM ring 5 page size and level. */
8322 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
8323 /* TQM ring 5 PBL indirect levels. */
8324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK \
8326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
8327 /* PBL pointer is physical start address. */
8328 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 \
8330 /* PBL pointer points to PTE table. */
8331 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 \
8333 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8334 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 \
8336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LAST \
8337 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2
8338 /* TQM ring 5 page size. */
8339 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK \
8341 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_SFT 4
8343 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K \
8344 (UINT32_C(0x0) << 4)
8346 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K \
8347 (UINT32_C(0x1) << 4)
8349 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K \
8350 (UINT32_C(0x2) << 4)
8352 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M \
8353 (UINT32_C(0x3) << 4)
8355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M \
8356 (UINT32_C(0x4) << 4)
8358 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G \
8359 (UINT32_C(0x5) << 4)
8360 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_LAST \
8361 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G
8362 /* TQM ring 6 page size and level. */
8363 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
8364 /* TQM ring 6 PBL indirect levels. */
8365 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK \
8367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
8368 /* PBL pointer is physical start address. */
8369 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 \
8371 /* PBL pointer points to PTE table. */
8372 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 \
8374 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8375 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 \
8377 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LAST \
8378 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2
8379 /* TQM ring 6 page size. */
8380 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK \
8382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_SFT 4
8384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K \
8385 (UINT32_C(0x0) << 4)
8387 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K \
8388 (UINT32_C(0x1) << 4)
8390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K \
8391 (UINT32_C(0x2) << 4)
8393 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M \
8394 (UINT32_C(0x3) << 4)
8396 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M \
8397 (UINT32_C(0x4) << 4)
8399 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G \
8400 (UINT32_C(0x5) << 4)
8401 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_LAST \
8402 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G
8403 /* TQM ring 7 page size and level. */
8404 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
8405 /* TQM ring 7 PBL indirect levels. */
8406 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK \
8408 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
8409 /* PBL pointer is physical start address. */
8410 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 \
8412 /* PBL pointer points to PTE table. */
8413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 \
8415 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8416 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 \
8418 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LAST \
8419 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2
8420 /* TQM ring 7 page size. */
8421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK \
8423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_SFT 4
8425 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K \
8426 (UINT32_C(0x0) << 4)
8428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K \
8429 (UINT32_C(0x1) << 4)
8431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K \
8432 (UINT32_C(0x2) << 4)
8434 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M \
8435 (UINT32_C(0x3) << 4)
8437 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M \
8438 (UINT32_C(0x4) << 4)
8440 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G \
8441 (UINT32_C(0x5) << 4)
8442 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_LAST \
8443 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G
8444 /* MR/AV page size and level. */
8445 uint8_t mrav_pg_size_mrav_lvl;
8446 /* MR/AV PBL indirect levels. */
8447 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK \
8449 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
8450 /* PBL pointer is physical start address. */
8451 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 \
8453 /* PBL pointer points to PTE table. */
8454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 \
8456 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8457 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 \
8459 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LAST \
8460 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2
8461 /* MR/AV page size. */
8462 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK \
8464 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_SFT 4
8466 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K \
8467 (UINT32_C(0x0) << 4)
8469 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K \
8470 (UINT32_C(0x1) << 4)
8472 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K \
8473 (UINT32_C(0x2) << 4)
8475 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M \
8476 (UINT32_C(0x3) << 4)
8478 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M \
8479 (UINT32_C(0x4) << 4)
8481 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G \
8482 (UINT32_C(0x5) << 4)
8483 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_LAST \
8484 HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G
8485 /* Timer page size and level. */
8486 uint8_t tim_pg_size_tim_lvl;
8487 /* Timer PBL indirect levels. */
8488 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK \
8490 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
8491 /* PBL pointer is physical start address. */
8492 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 \
8494 /* PBL pointer points to PTE table. */
8495 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 \
8497 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8498 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 \
8500 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LAST \
8501 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2
8502 /* Timer page size. */
8503 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK \
8505 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_SFT 4
8507 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K \
8508 (UINT32_C(0x0) << 4)
8510 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K \
8511 (UINT32_C(0x1) << 4)
8513 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K \
8514 (UINT32_C(0x2) << 4)
8516 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M \
8517 (UINT32_C(0x3) << 4)
8519 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M \
8520 (UINT32_C(0x4) << 4)
8522 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G \
8523 (UINT32_C(0x5) << 4)
8524 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_LAST \
8525 HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G
8526 /* QP page directory. */
8527 uint64_t qpc_page_dir;
8528 /* SRQ page directory. */
8529 uint64_t srq_page_dir;
8530 /* CQ page directory. */
8531 uint64_t cq_page_dir;
8532 /* VNIC page directory. */
8533 uint64_t vnic_page_dir;
8534 /* Stat page directory. */
8535 uint64_t stat_page_dir;
8536 /* TQM slowpath page directory. */
8537 uint64_t tqm_sp_page_dir;
8538 /* TQM ring 0 page directory. */
8539 uint64_t tqm_ring0_page_dir;
8540 /* TQM ring 1 page directory. */
8541 uint64_t tqm_ring1_page_dir;
8542 /* TQM ring 2 page directory. */
8543 uint64_t tqm_ring2_page_dir;
8544 /* TQM ring 3 page directory. */
8545 uint64_t tqm_ring3_page_dir;
8546 /* TQM ring 4 page directory. */
8547 uint64_t tqm_ring4_page_dir;
8548 /* TQM ring 5 page directory. */
8549 uint64_t tqm_ring5_page_dir;
8550 /* TQM ring 6 page directory. */
8551 uint64_t tqm_ring6_page_dir;
8552 /* TQM ring 7 page directory. */
8553 uint64_t tqm_ring7_page_dir;
8554 /* MR/AV page directory. */
8555 uint64_t mrav_page_dir;
8556 /* Timer page directory. */
8557 uint64_t tim_page_dir;
8558 /* Number of QPs. */
8559 uint32_t qp_num_entries;
8560 /* Number of SRQs. */
8561 uint32_t srq_num_entries;
8562 /* Number of CQs. */
8563 uint32_t cq_num_entries;
8564 /* Number of Stats. */
8565 uint32_t stat_num_entries;
8566 /* Number of TQM slowpath entries. */
8567 uint32_t tqm_sp_num_entries;
8568 /* Number of TQM ring 0 entries. */
8569 uint32_t tqm_ring0_num_entries;
8570 /* Number of TQM ring 1 entries. */
8571 uint32_t tqm_ring1_num_entries;
8572 /* Number of TQM ring 2 entries. */
8573 uint32_t tqm_ring2_num_entries;
8574 /* Number of TQM ring 3 entries. */
8575 uint32_t tqm_ring3_num_entries;
8576 /* Number of TQM ring 4 entries. */
8577 uint32_t tqm_ring4_num_entries;
8578 /* Number of TQM ring 5 entries. */
8579 uint32_t tqm_ring5_num_entries;
8580 /* Number of TQM ring 6 entries. */
8581 uint32_t tqm_ring6_num_entries;
8582 /* Number of TQM ring 7 entries. */
8583 uint32_t tqm_ring7_num_entries;
8584 /* Number of MR/AV entries. */
8585 uint32_t mrav_num_entries;
8586 /* Number of Timer entries. */
8587 uint32_t tim_num_entries;
8588 /* Number of entries to reserve for QP1 */
8589 uint16_t qp_num_qp1_entries;
8590 /* Number of entries to reserve for L2 */
8591 uint16_t qp_num_l2_entries;
8592 /* Number of bytes that have been allocated for each context entry. */
8593 uint16_t qp_entry_size;
8594 /* Number of entries to reserve for L2 */
8595 uint16_t srq_num_l2_entries;
8596 /* Number of bytes that have been allocated for each context entry. */
8597 uint16_t srq_entry_size;
8598 /* Number of entries to reserve for L2 */
8599 uint16_t cq_num_l2_entries;
8600 /* Number of bytes that have been allocated for each context entry. */
8601 uint16_t cq_entry_size;
8602 /* Number of entries to reserve for VNIC entries */
8603 uint16_t vnic_num_vnic_entries;
8604 /* Number of entries to reserve for Ring table entries */
8605 uint16_t vnic_num_ring_table_entries;
8606 /* Number of bytes that have been allocated for each context entry. */
8607 uint16_t vnic_entry_size;
8608 /* Number of bytes that have been allocated for each context entry. */
8609 uint16_t stat_entry_size;
8610 /* Number of bytes that have been allocated for each context entry. */
8611 uint16_t tqm_entry_size;
8612 /* Number of bytes that have been allocated for each context entry. */
8613 uint16_t mrav_entry_size;
8614 /* Number of bytes that have been allocated for each context entry. */
8615 uint16_t tim_entry_size;
8616 } __attribute__((packed));
8618 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */
8619 struct hwrm_func_backing_store_cfg_output {
8620 /* The specific error status for the command. */
8621 uint16_t error_code;
8622 /* The HWRM command request type. */
8624 /* The sequence ID from the original command. */
8626 /* The length of the response data in number of bytes. */
8628 uint8_t unused_0[7];
8630 * This field is used in Output records to indicate that the output
8631 * is completely written to RAM. This field should be read as '1'
8632 * to indicate that the output has been completely written.
8633 * When writing a command completion or response to an internal processor,
8634 * the order of writes has to be such that this field is written last.
8637 } __attribute__((packed));
8639 /********************************
8640 * hwrm_func_backing_store_qcfg *
8641 ********************************/
8644 /* hwrm_func_backing_store_qcfg_input (size:128b/16B) */
8645 struct hwrm_func_backing_store_qcfg_input {
8646 /* The HWRM command request type. */
8649 * The completion ring to send the completion event on. This should
8650 * be the NQ ID returned from the `nq_alloc` HWRM command.
8654 * The sequence ID is used by the driver for tracking multiple
8655 * commands. This ID is treated as opaque data by the firmware and
8656 * the value is returned in the `hwrm_resp_hdr` upon completion.
8660 * The target ID of the command:
8661 * * 0x0-0xFFF8 - The function ID
8662 * * 0xFFF8-0xFFFE - Reserved for internal processors
8667 * A physical address pointer pointing to a host buffer that the
8668 * command's response data will be written. This can be either a host
8669 * physical address (HPA) or a guest physical address (GPA) and must
8670 * point to a physically contiguous block of memory.
8673 } __attribute__((packed));
8675 /* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */
8676 struct hwrm_func_backing_store_qcfg_output {
8677 /* The specific error status for the command. */
8678 uint16_t error_code;
8679 /* The HWRM command request type. */
8681 /* The sequence ID from the original command. */
8683 /* The length of the response data in number of bytes. */
8687 * When set, the firmware only uses on-chip resources and does not
8688 * expect any backing store to be provided by the host driver. This
8689 * mode provides minimal L2 functionality (e.g. limited L2 resources,
8692 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
8694 uint8_t unused_0[4];
8696 * This bit must be '1' for the qp fields to be
8699 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \
8702 * This bit must be '1' for the srq fields to be
8705 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \
8708 * This bit must be '1' for the cq fields to be
8711 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \
8714 * This bit must be '1' for the vnic fields to be
8717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \
8720 * This bit must be '1' for the stat fields to be
8723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \
8726 * This bit must be '1' for the tqm_sp fields to be
8729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \
8732 * This bit must be '1' for the tqm_ring0 fields to be
8735 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \
8738 * This bit must be '1' for the tqm_ring1 fields to be
8741 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \
8744 * This bit must be '1' for the tqm_ring2 fields to be
8747 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \
8750 * This bit must be '1' for the tqm_ring3 fields to be
8753 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \
8756 * This bit must be '1' for the tqm_ring4 fields to be
8759 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \
8762 * This bit must be '1' for the tqm_ring5 fields to be
8765 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \
8768 * This bit must be '1' for the tqm_ring6 fields to be
8771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \
8774 * This bit must be '1' for the tqm_ring7 fields to be
8777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \
8780 * This bit must be '1' for the mrav fields to be
8783 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \
8786 * This bit must be '1' for the tim fields to be
8789 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \
8791 /* QPC page size and level. */
8792 uint8_t qpc_pg_size_qpc_lvl;
8793 /* QPC PBL indirect levels. */
8794 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK \
8796 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
8797 /* PBL pointer is physical start address. */
8798 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 \
8800 /* PBL pointer points to PTE table. */
8801 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 \
8803 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 \
8806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LAST \
8807 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2
8808 /* QPC page size. */
8809 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK \
8811 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_SFT 4
8813 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K \
8814 (UINT32_C(0x0) << 4)
8816 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K \
8817 (UINT32_C(0x1) << 4)
8819 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K \
8820 (UINT32_C(0x2) << 4)
8822 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M \
8823 (UINT32_C(0x3) << 4)
8825 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M \
8826 (UINT32_C(0x4) << 4)
8828 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G \
8829 (UINT32_C(0x5) << 4)
8830 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_LAST \
8831 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G
8832 /* SRQ page size and level. */
8833 uint8_t srq_pg_size_srq_lvl;
8834 /* SRQ PBL indirect levels. */
8835 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK \
8837 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
8838 /* PBL pointer is physical start address. */
8839 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 \
8841 /* PBL pointer points to PTE table. */
8842 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 \
8844 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8845 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 \
8847 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LAST \
8848 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2
8849 /* SRQ page size. */
8850 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK \
8852 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_SFT 4
8854 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K \
8855 (UINT32_C(0x0) << 4)
8857 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K \
8858 (UINT32_C(0x1) << 4)
8860 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K \
8861 (UINT32_C(0x2) << 4)
8863 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M \
8864 (UINT32_C(0x3) << 4)
8866 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M \
8867 (UINT32_C(0x4) << 4)
8869 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G \
8870 (UINT32_C(0x5) << 4)
8871 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_LAST \
8872 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G
8873 /* CQ page size and level. */
8874 uint8_t cq_pg_size_cq_lvl;
8875 /* CQ PBL indirect levels. */
8876 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK \
8878 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
8879 /* PBL pointer is physical start address. */
8880 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 \
8882 /* PBL pointer points to PTE table. */
8883 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 \
8885 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8886 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 \
8888 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LAST \
8889 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2
8891 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK \
8893 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_SFT 4
8895 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K \
8896 (UINT32_C(0x0) << 4)
8898 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K \
8899 (UINT32_C(0x1) << 4)
8901 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K \
8902 (UINT32_C(0x2) << 4)
8904 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M \
8905 (UINT32_C(0x3) << 4)
8907 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M \
8908 (UINT32_C(0x4) << 4)
8910 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G \
8911 (UINT32_C(0x5) << 4)
8912 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_LAST \
8913 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G
8914 /* VNIC page size and level. */
8915 uint8_t vnic_pg_size_vnic_lvl;
8916 /* VNIC PBL indirect levels. */
8917 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK \
8919 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
8920 /* PBL pointer is physical start address. */
8921 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 \
8923 /* PBL pointer points to PTE table. */
8924 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 \
8926 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8927 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 \
8929 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LAST \
8930 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2
8931 /* VNIC page size. */
8932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK \
8934 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_SFT 4
8936 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K \
8937 (UINT32_C(0x0) << 4)
8939 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K \
8940 (UINT32_C(0x1) << 4)
8942 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K \
8943 (UINT32_C(0x2) << 4)
8945 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M \
8946 (UINT32_C(0x3) << 4)
8948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M \
8949 (UINT32_C(0x4) << 4)
8951 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G \
8952 (UINT32_C(0x5) << 4)
8953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_LAST \
8954 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G
8955 /* Stat page size and level. */
8956 uint8_t stat_pg_size_stat_lvl;
8957 /* Stat PBL indirect levels. */
8958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK \
8960 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
8961 /* PBL pointer is physical start address. */
8962 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 \
8964 /* PBL pointer points to PTE table. */
8965 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 \
8967 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
8968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 \
8970 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LAST \
8971 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2
8972 /* Stat page size. */
8973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK \
8975 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_SFT 4
8977 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K \
8978 (UINT32_C(0x0) << 4)
8980 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K \
8981 (UINT32_C(0x1) << 4)
8983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K \
8984 (UINT32_C(0x2) << 4)
8986 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M \
8987 (UINT32_C(0x3) << 4)
8989 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M \
8990 (UINT32_C(0x4) << 4)
8992 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G \
8993 (UINT32_C(0x5) << 4)
8994 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_LAST \
8995 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G
8996 /* TQM slow path page size and level. */
8997 uint8_t tqm_sp_pg_size_tqm_sp_lvl;
8998 /* TQM slow path PBL indirect levels. */
8999 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK \
9001 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
9002 /* PBL pointer is physical start address. */
9003 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 \
9005 /* PBL pointer points to PTE table. */
9006 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 \
9008 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9009 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 \
9011 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LAST \
9012 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2
9013 /* TQM slow path page size. */
9014 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK \
9016 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_SFT 4
9018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K \
9019 (UINT32_C(0x0) << 4)
9021 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K \
9022 (UINT32_C(0x1) << 4)
9024 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K \
9025 (UINT32_C(0x2) << 4)
9027 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M \
9028 (UINT32_C(0x3) << 4)
9030 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M \
9031 (UINT32_C(0x4) << 4)
9033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G \
9034 (UINT32_C(0x5) << 4)
9035 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_LAST \
9036 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G
9037 /* TQM ring 0 page size and level. */
9038 uint8_t tqm_ring0_pg_size_tqm_ring0_lvl;
9039 /* TQM ring 0 PBL indirect levels. */
9040 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK \
9042 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
9043 /* PBL pointer is physical start address. */
9044 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 \
9046 /* PBL pointer points to PTE table. */
9047 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 \
9049 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9050 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 \
9052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LAST \
9053 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2
9054 /* TQM ring 0 page size. */
9055 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK \
9057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_SFT 4
9059 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K \
9060 (UINT32_C(0x0) << 4)
9062 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K \
9063 (UINT32_C(0x1) << 4)
9065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K \
9066 (UINT32_C(0x2) << 4)
9068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M \
9069 (UINT32_C(0x3) << 4)
9071 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M \
9072 (UINT32_C(0x4) << 4)
9074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G \
9075 (UINT32_C(0x5) << 4)
9076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_LAST \
9077 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G
9078 /* TQM ring 1 page size and level. */
9079 uint8_t tqm_ring1_pg_size_tqm_ring1_lvl;
9080 /* TQM ring 1 PBL indirect levels. */
9081 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK \
9083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
9084 /* PBL pointer is physical start address. */
9085 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 \
9087 /* PBL pointer points to PTE table. */
9088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 \
9090 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9091 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 \
9093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LAST \
9094 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2
9095 /* TQM ring 1 page size. */
9096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK \
9098 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_SFT 4
9100 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K \
9101 (UINT32_C(0x0) << 4)
9103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K \
9104 (UINT32_C(0x1) << 4)
9106 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K \
9107 (UINT32_C(0x2) << 4)
9109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M \
9110 (UINT32_C(0x3) << 4)
9112 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M \
9113 (UINT32_C(0x4) << 4)
9115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G \
9116 (UINT32_C(0x5) << 4)
9117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_LAST \
9118 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G
9119 /* TQM ring 2 page size and level. */
9120 uint8_t tqm_ring2_pg_size_tqm_ring2_lvl;
9121 /* TQM ring 2 PBL indirect levels. */
9122 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK \
9124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
9125 /* PBL pointer is physical start address. */
9126 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 \
9128 /* PBL pointer points to PTE table. */
9129 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 \
9131 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 \
9134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LAST \
9135 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2
9136 /* TQM ring 2 page size. */
9137 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK \
9139 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_SFT 4
9141 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K \
9142 (UINT32_C(0x0) << 4)
9144 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K \
9145 (UINT32_C(0x1) << 4)
9147 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K \
9148 (UINT32_C(0x2) << 4)
9150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M \
9151 (UINT32_C(0x3) << 4)
9153 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M \
9154 (UINT32_C(0x4) << 4)
9156 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G \
9157 (UINT32_C(0x5) << 4)
9158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_LAST \
9159 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G
9160 /* TQM ring 3 page size and level. */
9161 uint8_t tqm_ring3_pg_size_tqm_ring3_lvl;
9162 /* TQM ring 3 PBL indirect levels. */
9163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK \
9165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
9166 /* PBL pointer is physical start address. */
9167 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 \
9169 /* PBL pointer points to PTE table. */
9170 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 \
9172 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9173 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 \
9175 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LAST \
9176 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2
9177 /* TQM ring 3 page size. */
9178 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK \
9180 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_SFT 4
9182 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K \
9183 (UINT32_C(0x0) << 4)
9185 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K \
9186 (UINT32_C(0x1) << 4)
9188 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K \
9189 (UINT32_C(0x2) << 4)
9191 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M \
9192 (UINT32_C(0x3) << 4)
9194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M \
9195 (UINT32_C(0x4) << 4)
9197 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G \
9198 (UINT32_C(0x5) << 4)
9199 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_LAST \
9200 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G
9201 /* TQM ring 4 page size and level. */
9202 uint8_t tqm_ring4_pg_size_tqm_ring4_lvl;
9203 /* TQM ring 4 PBL indirect levels. */
9204 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK \
9206 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
9207 /* PBL pointer is physical start address. */
9208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 \
9210 /* PBL pointer points to PTE table. */
9211 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 \
9213 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9214 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 \
9216 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LAST \
9217 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2
9218 /* TQM ring 4 page size. */
9219 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK \
9221 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_SFT 4
9223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K \
9224 (UINT32_C(0x0) << 4)
9226 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K \
9227 (UINT32_C(0x1) << 4)
9229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K \
9230 (UINT32_C(0x2) << 4)
9232 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M \
9233 (UINT32_C(0x3) << 4)
9235 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M \
9236 (UINT32_C(0x4) << 4)
9238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G \
9239 (UINT32_C(0x5) << 4)
9240 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_LAST \
9241 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G
9242 /* TQM ring 5 page size and level. */
9243 uint8_t tqm_ring5_pg_size_tqm_ring5_lvl;
9244 /* TQM ring 5 PBL indirect levels. */
9245 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK \
9247 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
9248 /* PBL pointer is physical start address. */
9249 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 \
9251 /* PBL pointer points to PTE table. */
9252 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 \
9254 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9255 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 \
9257 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LAST \
9258 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2
9259 /* TQM ring 5 page size. */
9260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK \
9262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_SFT 4
9264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K \
9265 (UINT32_C(0x0) << 4)
9267 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K \
9268 (UINT32_C(0x1) << 4)
9270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K \
9271 (UINT32_C(0x2) << 4)
9273 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M \
9274 (UINT32_C(0x3) << 4)
9276 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M \
9277 (UINT32_C(0x4) << 4)
9279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G \
9280 (UINT32_C(0x5) << 4)
9281 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_LAST \
9282 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G
9283 /* TQM ring 6 page size and level. */
9284 uint8_t tqm_ring6_pg_size_tqm_ring6_lvl;
9285 /* TQM ring 6 PBL indirect levels. */
9286 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK \
9288 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
9289 /* PBL pointer is physical start address. */
9290 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 \
9292 /* PBL pointer points to PTE table. */
9293 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 \
9295 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9296 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 \
9298 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LAST \
9299 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2
9300 /* TQM ring 6 page size. */
9301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK \
9303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_SFT 4
9305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K \
9306 (UINT32_C(0x0) << 4)
9308 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K \
9309 (UINT32_C(0x1) << 4)
9311 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K \
9312 (UINT32_C(0x2) << 4)
9314 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M \
9315 (UINT32_C(0x3) << 4)
9317 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M \
9318 (UINT32_C(0x4) << 4)
9320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G \
9321 (UINT32_C(0x5) << 4)
9322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_LAST \
9323 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G
9324 /* TQM ring 7 page size and level. */
9325 uint8_t tqm_ring7_pg_size_tqm_ring7_lvl;
9326 /* TQM ring 7 PBL indirect levels. */
9327 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK \
9329 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
9330 /* PBL pointer is physical start address. */
9331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 \
9333 /* PBL pointer points to PTE table. */
9334 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 \
9336 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9337 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 \
9339 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LAST \
9340 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2
9341 /* TQM ring 7 page size. */
9342 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK \
9344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_SFT 4
9346 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K \
9347 (UINT32_C(0x0) << 4)
9349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K \
9350 (UINT32_C(0x1) << 4)
9352 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K \
9353 (UINT32_C(0x2) << 4)
9355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M \
9356 (UINT32_C(0x3) << 4)
9358 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M \
9359 (UINT32_C(0x4) << 4)
9361 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G \
9362 (UINT32_C(0x5) << 4)
9363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_LAST \
9364 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G
9365 /* MR/AV page size and level. */
9366 uint8_t mrav_pg_size_mrav_lvl;
9367 /* MR/AV PBL indirect levels. */
9368 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK \
9370 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
9371 /* PBL pointer is physical start address. */
9372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 \
9374 /* PBL pointer points to PTE table. */
9375 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 \
9377 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 \
9380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LAST \
9381 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2
9382 /* MR/AV page size. */
9383 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK \
9385 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_SFT 4
9387 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K \
9388 (UINT32_C(0x0) << 4)
9390 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K \
9391 (UINT32_C(0x1) << 4)
9393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K \
9394 (UINT32_C(0x2) << 4)
9396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M \
9397 (UINT32_C(0x3) << 4)
9399 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M \
9400 (UINT32_C(0x4) << 4)
9402 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G \
9403 (UINT32_C(0x5) << 4)
9404 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_LAST \
9405 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G
9406 /* Timer page size and level. */
9407 uint8_t tim_pg_size_tim_lvl;
9408 /* Timer PBL indirect levels. */
9409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK \
9411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
9412 /* PBL pointer is physical start address. */
9413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 \
9415 /* PBL pointer points to PTE table. */
9416 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 \
9418 /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
9419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 \
9421 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LAST \
9422 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2
9423 /* Timer page size. */
9424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK \
9426 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_SFT 4
9428 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K \
9429 (UINT32_C(0x0) << 4)
9431 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K \
9432 (UINT32_C(0x1) << 4)
9434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K \
9435 (UINT32_C(0x2) << 4)
9437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M \
9438 (UINT32_C(0x3) << 4)
9440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M \
9441 (UINT32_C(0x4) << 4)
9443 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G \
9444 (UINT32_C(0x5) << 4)
9445 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_LAST \
9446 HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G
9447 /* QP page directory. */
9448 uint64_t qpc_page_dir;
9449 /* SRQ page directory. */
9450 uint64_t srq_page_dir;
9451 /* CQ page directory. */
9452 uint64_t cq_page_dir;
9453 /* VNIC page directory. */
9454 uint64_t vnic_page_dir;
9455 /* Stat page directory. */
9456 uint64_t stat_page_dir;
9457 /* TQM slowpath page directory. */
9458 uint64_t tqm_sp_page_dir;
9459 /* TQM ring 0 page directory. */
9460 uint64_t tqm_ring0_page_dir;
9461 /* TQM ring 1 page directory. */
9462 uint64_t tqm_ring1_page_dir;
9463 /* TQM ring 2 page directory. */
9464 uint64_t tqm_ring2_page_dir;
9465 /* TQM ring 3 page directory. */
9466 uint64_t tqm_ring3_page_dir;
9467 /* TQM ring 4 page directory. */
9468 uint64_t tqm_ring4_page_dir;
9469 /* TQM ring 5 page directory. */
9470 uint64_t tqm_ring5_page_dir;
9471 /* TQM ring 6 page directory. */
9472 uint64_t tqm_ring6_page_dir;
9473 /* TQM ring 7 page directory. */
9474 uint64_t tqm_ring7_page_dir;
9475 /* MR/AV page directory. */
9476 uint64_t mrav_page_dir;
9477 /* Timer page directory. */
9478 uint64_t tim_page_dir;
9479 /* Number of entries to reserve for QP1 */
9480 uint16_t qp_num_qp1_entries;
9481 /* Number of entries to reserve for L2 */
9482 uint16_t qp_num_l2_entries;
9483 /* Number of QPs. */
9484 uint32_t qp_num_entries;
9485 /* Number of SRQs. */
9486 uint32_t srq_num_entries;
9487 /* Number of entries to reserve for L2 */
9488 uint16_t srq_num_l2_entries;
9489 /* Number of entries to reserve for L2 */
9490 uint16_t cq_num_l2_entries;
9491 /* Number of CQs. */
9492 uint32_t cq_num_entries;
9493 /* Number of entries to reserve for VNIC entries */
9494 uint16_t vnic_num_vnic_entries;
9495 /* Number of entries to reserve for Ring table entries */
9496 uint16_t vnic_num_ring_table_entries;
9497 /* Number of Stats. */
9498 uint32_t stat_num_entries;
9499 /* Number of TQM slowpath entries. */
9500 uint32_t tqm_sp_num_entries;
9501 /* Number of TQM ring 0 entries. */
9502 uint32_t tqm_ring0_num_entries;
9503 /* Number of TQM ring 1 entries. */
9504 uint32_t tqm_ring1_num_entries;
9505 /* Number of TQM ring 2 entries. */
9506 uint32_t tqm_ring2_num_entries;
9507 /* Number of TQM ring 3 entries. */
9508 uint32_t tqm_ring3_num_entries;
9509 /* Number of TQM ring 4 entries. */
9510 uint32_t tqm_ring4_num_entries;
9511 /* Number of TQM ring 5 entries. */
9512 uint32_t tqm_ring5_num_entries;
9513 /* Number of TQM ring 6 entries. */
9514 uint32_t tqm_ring6_num_entries;
9515 /* Number of TQM ring 7 entries. */
9516 uint32_t tqm_ring7_num_entries;
9517 /* Number of MR/AV entries. */
9518 uint32_t mrav_num_entries;
9519 /* Number of Timer entries. */
9520 uint32_t tim_num_entries;
9521 uint8_t unused_1[7];
9523 * This field is used in Output records to indicate that the output
9524 * is completely written to RAM. This field should be read as '1'
9525 * to indicate that the output has been completely written.
9526 * When writing a command completion or response to an internal processor,
9527 * the order of writes has to be such that this field is written last.
9530 } __attribute__((packed));
9532 /*********************
9533 * hwrm_port_phy_cfg *
9534 *********************/
9537 /* hwrm_port_phy_cfg_input (size:448b/56B) */
9538 struct hwrm_port_phy_cfg_input {
9539 /* The HWRM command request type. */
9542 * The completion ring to send the completion event on. This should
9543 * be the NQ ID returned from the `nq_alloc` HWRM command.
9547 * The sequence ID is used by the driver for tracking multiple
9548 * commands. This ID is treated as opaque data by the firmware and
9549 * the value is returned in the `hwrm_resp_hdr` upon completion.
9553 * The target ID of the command:
9554 * * 0x0-0xFFF8 - The function ID
9555 * * 0xFFF8-0xFFFE - Reserved for internal processors
9560 * A physical address pointer pointing to a host buffer that the
9561 * command's response data will be written. This can be either a host
9562 * physical address (HPA) or a guest physical address (GPA) and must
9563 * point to a physically contiguous block of memory.
9568 * When this bit is set to '1', the PHY for the port shall
9571 * # If this bit is set to 1, then the HWRM shall reset the
9572 * PHY after applying PHY configuration changes specified
9574 * # In order to guarantee that PHY configuration changes
9575 * specified in this command take effect, the HWRM
9576 * client should set this flag to 1.
9577 * # If this bit is not set to 1, then the HWRM may reset
9578 * the PHY depending on the current PHY configuration and
9579 * settings specified in this command.
9581 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \
9583 /* deprecated bit. Do not use!!! */
9584 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \
9587 * When this bit is set to '1', the link shall be forced to
9588 * the force_link_speed value.
9590 * When this bit is set to '1', the HWRM client should
9591 * not enable any of the auto negotiation related
9592 * fields represented by auto_XXX fields in this command.
9593 * When this bit is set to '1' and the HWRM client has
9594 * enabled a auto_XXX field in this command, then the
9595 * HWRM shall ignore the enabled auto_XXX field.
9597 * When this bit is set to zero, the link
9598 * shall be allowed to autoneg.
9600 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \
9603 * When this bit is set to '1', the auto-negotiation process
9604 * shall be restarted on the link.
9606 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \
9609 * When this bit is set to '1', Energy Efficient Ethernet
9610 * (EEE) is requested to be enabled on this link.
9611 * If EEE is not supported on this port, then this flag
9612 * shall be ignored by the HWRM.
9614 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \
9617 * When this bit is set to '1', Energy Efficient Ethernet
9618 * (EEE) is requested to be disabled on this link.
9619 * If EEE is not supported on this port, then this flag
9620 * shall be ignored by the HWRM.
9622 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \
9625 * When this bit is set to '1' and EEE is enabled on this
9626 * link, then TX LPI is requested to be enabled on the link.
9627 * If EEE is not supported on this port, then this flag
9628 * shall be ignored by the HWRM.
9629 * If EEE is disabled on this port, then this flag shall be
9630 * ignored by the HWRM.
9632 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \
9635 * When this bit is set to '1' and EEE is enabled on this
9636 * link, then TX LPI is requested to be disabled on the link.
9637 * If EEE is not supported on this port, then this flag
9638 * shall be ignored by the HWRM.
9639 * If EEE is disabled on this port, then this flag shall be
9640 * ignored by the HWRM.
9642 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \
9645 * When set to 1, then the HWRM shall enable FEC autonegotitation
9646 * on this port if supported.
9647 * When set to 0, then this flag shall be ignored.
9648 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
9651 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \
9654 * When set to 1, then the HWRM shall disable FEC autonegotiation
9655 * on this port if supported.
9656 * When set to 0, then this flag shall be ignored.
9657 * If FEC autonegotiation is not supported, then the HWRM shall ignore this
9660 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \
9663 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
9664 * on this port if supported.
9665 * When set to 0, then this flag shall be ignored.
9666 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
9669 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \
9672 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
9673 * on this port if supported.
9674 * When set to 0, then this flag shall be ignored.
9675 * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this
9678 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \
9681 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)
9682 * on this port if supported.
9683 * When set to 0, then this flag shall be ignored.
9684 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
9687 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \
9690 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)
9691 * on this port if supported.
9692 * When set to 0, then this flag shall be ignored.
9693 * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this
9696 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \
9699 * When this bit is set to '1', the link shall be forced to
9702 * # When this bit is set to '1", all other
9703 * command input settings related to the link speed shall
9705 * Once the link state is forced down, it can be
9706 * explicitly cleared from that state by setting this flag
9708 * # If this flag is set to '0', then the link shall be
9709 * cleared from forced down state if the link is in forced
9711 * There may be conditions (e.g. out-of-band or sideband
9712 * configuration changes for the link) outside the scope
9713 * of the HWRM implementation that may clear forced down
9716 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \
9720 * This bit must be '1' for the auto_mode field to be
9723 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \
9726 * This bit must be '1' for the auto_duplex field to be
9729 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \
9732 * This bit must be '1' for the auto_pause field to be
9735 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \
9738 * This bit must be '1' for the auto_link_speed field to be
9741 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \
9744 * This bit must be '1' for the auto_link_speed_mask field to be
9747 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
9750 * This bit must be '1' for the wirespeed field to be
9753 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \
9756 * This bit must be '1' for the lpbk field to be
9759 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \
9762 * This bit must be '1' for the preemphasis field to be
9765 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \
9768 * This bit must be '1' for the force_pause field to be
9771 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \
9774 * This bit must be '1' for the eee_link_speed_mask field to be
9777 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
9780 * This bit must be '1' for the tx_lpi_timer field to be
9783 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \
9785 /* Port ID of port that is to be configured. */
9788 * This is the speed that will be used if the force
9789 * bit is '1'. If unsupported speed is selected, an error
9790 * will be generated.
9792 uint16_t force_link_speed;
9793 /* 100Mb link speed */
9794 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
9795 /* 1Gb link speed */
9796 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
9797 /* 2Gb link speed */
9798 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
9799 /* 25Gb link speed */
9800 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
9801 /* 10Gb link speed */
9802 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
9803 /* 20Mb link speed */
9804 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
9805 /* 25Gb link speed */
9806 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
9807 /* 40Gb link speed */
9808 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
9809 /* 50Gb link speed */
9810 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
9811 /* 100Gb link speed */
9812 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
9813 /* 10Mb link speed */
9814 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
9815 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
9816 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB
9818 * This value is used to identify what autoneg mode is
9819 * used when the link speed is not being forced.
9822 /* Disable autoneg or autoneg disabled. No speeds are selected. */
9823 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
9824 /* Select all possible speeds for autoneg mode. */
9825 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
9827 * Select only the auto_link_speed speed for autoneg mode. This mode has
9828 * been DEPRECATED. An HWRM client should not use this mode.
9830 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
9832 * Select the auto_link_speed or any speed below that speed for autoneg.
9833 * This mode has been DEPRECATED. An HWRM client should not use this mode.
9835 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
9837 * Select the speeds based on the corresponding link speed mask value
9840 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
9841 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \
9842 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK
9844 * This is the duplex setting that will be used if the autoneg_mode
9845 * is "one_speed" or "one_or_below".
9847 uint8_t auto_duplex;
9848 /* Half Duplex will be requested. */
9849 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
9850 /* Full duplex will be requested. */
9851 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
9852 /* Both Half and Full dupex will be requested. */
9853 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
9854 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \
9855 HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH
9857 * This value is used to configure the pause that will be
9858 * used for autonegotiation.
9859 * Add text on the usage of auto_pause and force_pause.
9863 * When this bit is '1', Generation of tx pause messages
9864 * has been requested. Disabled otherwise.
9866 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \
9869 * When this bit is '1', Reception of rx pause messages
9870 * has been requested. Disabled otherwise.
9872 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \
9875 * When set to 1, the advertisement of pause is enabled.
9877 * # When the auto_mode is not set to none and this flag is
9878 * set to 1, then the auto_pause bits on this port are being
9879 * advertised and autoneg pause results are being interpreted.
9880 * # When the auto_mode is not set to none and this
9881 * flag is set to 0, the pause is forced as indicated in
9882 * force_pause, and also advertised as auto_pause bits, but
9883 * the autoneg results are not interpreted since the pause
9884 * configuration is being forced.
9885 * # When the auto_mode is set to none and this flag is set to
9886 * 1, auto_pause bits should be ignored and should be set to 0.
9888 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \
9892 * This is the speed that will be used if the autoneg_mode
9893 * is "one_speed" or "one_or_below". If an unsupported speed
9894 * is selected, an error will be generated.
9896 uint16_t auto_link_speed;
9897 /* 100Mb link speed */
9898 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
9899 /* 1Gb link speed */
9900 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
9901 /* 2Gb link speed */
9902 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
9903 /* 25Gb link speed */
9904 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
9905 /* 10Gb link speed */
9906 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
9907 /* 20Mb link speed */
9908 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
9909 /* 25Gb link speed */
9910 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
9911 /* 40Gb link speed */
9912 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
9913 /* 50Gb link speed */
9914 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
9915 /* 100Gb link speed */
9916 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
9917 /* 10Mb link speed */
9918 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
9919 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
9920 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB
9922 * This is a mask of link speeds that will be used if
9923 * autoneg_mode is "mask". If unsupported speed is enabled
9924 * an error will be generated.
9926 uint16_t auto_link_speed_mask;
9927 /* 100Mb link speed (Half-duplex) */
9928 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
9930 /* 100Mb link speed (Full-duplex) */
9931 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
9933 /* 1Gb link speed (Half-duplex) */
9934 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
9936 /* 1Gb link speed (Full-duplex) */
9937 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
9939 /* 2Gb link speed */
9940 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
9942 /* 25Gb link speed */
9943 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
9945 /* 10Gb link speed */
9946 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
9948 /* 20Gb link speed */
9949 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
9951 /* 25Gb link speed */
9952 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
9954 /* 40Gb link speed */
9955 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
9957 /* 50Gb link speed */
9958 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
9960 /* 100Gb link speed */
9961 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
9963 /* 10Mb link speed (Half-duplex) */
9964 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
9966 /* 10Mb link speed (Full-duplex) */
9967 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
9969 /* This value controls the wirespeed feature. */
9971 /* Wirespeed feature is disabled. */
9972 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
9973 /* Wirespeed feature is enabled. */
9974 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
9975 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \
9976 HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON
9977 /* This value controls the loopback setting for the PHY. */
9979 /* No loopback is selected. Normal operation. */
9980 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
9982 * The HW will be configured with local loopback such that
9983 * host data is sent back to the host without modification.
9985 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
9987 * The HW will be configured with remote loopback such that
9988 * port logic will send packets back out the transmitter that
9991 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
9993 * The HW will be configured with external loopback such that
9994 * host data is sent on the trasmitter and based on the external
9995 * loopback connection the data will be received without modification.
9997 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
9998 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \
9999 HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL
10001 * This value is used to configure the pause that will be
10002 * used for force mode.
10004 uint8_t force_pause;
10006 * When this bit is '1', Generation of tx pause messages
10007 * is supported. Disabled otherwise.
10009 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
10011 * When this bit is '1', Reception of rx pause messages
10012 * is supported. Disabled otherwise.
10014 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
10017 * This value controls the pre-emphasis to be used for the
10018 * link. Driver should not set this value (use
10019 * enable.preemphasis = 0) unless driver is sure of setting.
10020 * Normally HWRM FW will determine proper pre-emphasis.
10022 uint32_t preemphasis;
10024 * Setting for link speed mask that is used to
10025 * advertise speeds during autonegotiation when EEE is enabled.
10026 * This field is valid only when EEE is enabled.
10027 * The speeds specified in this field shall be a subset of
10028 * speeds specified in auto_link_speed_mask.
10029 * If EEE is enabled,then at least one speed shall be provided
10032 uint16_t eee_link_speed_mask;
10034 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \
10036 /* 100Mb link speed (Full-duplex) */
10037 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \
10040 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \
10042 /* 1Gb link speed (Full-duplex) */
10043 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \
10046 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
10049 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
10051 /* 10Gb link speed */
10052 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
10054 uint8_t unused_2[2];
10056 * Reuested setting of TX LPI timer in microseconds.
10057 * This field is valid only when EEE is enabled and TX LPI is
10060 uint32_t tx_lpi_timer;
10061 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
10062 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
10064 } __attribute__((packed));
10066 /* hwrm_port_phy_cfg_output (size:128b/16B) */
10067 struct hwrm_port_phy_cfg_output {
10068 /* The specific error status for the command. */
10069 uint16_t error_code;
10070 /* The HWRM command request type. */
10072 /* The sequence ID from the original command. */
10074 /* The length of the response data in number of bytes. */
10076 uint8_t unused_0[7];
10078 * This field is used in Output records to indicate that the output
10079 * is completely written to RAM. This field should be read as '1'
10080 * to indicate that the output has been completely written.
10081 * When writing a command completion or response to an internal processor,
10082 * the order of writes has to be such that this field is written last.
10085 } __attribute__((packed));
10087 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
10088 struct hwrm_port_phy_cfg_cmd_err {
10090 * command specific error codes that goes to
10091 * the cmd_err field in Common HWRM Error Response.
10094 /* Unknown error */
10095 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
10096 /* Unable to complete operation due to invalid speed */
10097 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
10099 * retry the command since the phy is not ready.
10100 * retry count is returned in opaque_0.
10101 * This is only valid for the first command and
10102 * this value will not change for successive calls.
10103 * but if a 0 is returned at any time then this should
10104 * be treated as an un recoverable failure,
10106 * retry interval in milli seconds is returned in opaque_1.
10107 * This specifies the time that user should wait before
10108 * issuing the next port_phy_cfg command.
10110 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
10111 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \
10112 HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY
10113 uint8_t unused_0[7];
10114 } __attribute__((packed));
10116 /**********************
10117 * hwrm_port_phy_qcfg *
10118 **********************/
10121 /* hwrm_port_phy_qcfg_input (size:192b/24B) */
10122 struct hwrm_port_phy_qcfg_input {
10123 /* The HWRM command request type. */
10126 * The completion ring to send the completion event on. This should
10127 * be the NQ ID returned from the `nq_alloc` HWRM command.
10129 uint16_t cmpl_ring;
10131 * The sequence ID is used by the driver for tracking multiple
10132 * commands. This ID is treated as opaque data by the firmware and
10133 * the value is returned in the `hwrm_resp_hdr` upon completion.
10137 * The target ID of the command:
10138 * * 0x0-0xFFF8 - The function ID
10139 * * 0xFFF8-0xFFFE - Reserved for internal processors
10142 uint16_t target_id;
10144 * A physical address pointer pointing to a host buffer that the
10145 * command's response data will be written. This can be either a host
10146 * physical address (HPA) or a guest physical address (GPA) and must
10147 * point to a physically contiguous block of memory.
10149 uint64_t resp_addr;
10150 /* Port ID of port that is to be queried. */
10152 uint8_t unused_0[6];
10153 } __attribute__((packed));
10155 /* hwrm_port_phy_qcfg_output (size:768b/96B) */
10156 struct hwrm_port_phy_qcfg_output {
10157 /* The specific error status for the command. */
10158 uint16_t error_code;
10159 /* The HWRM command request type. */
10161 /* The sequence ID from the original command. */
10163 /* The length of the response data in number of bytes. */
10165 /* This value indicates the current link status. */
10167 /* There is no link or cable detected. */
10168 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
10169 /* There is no link, but a cable has been detected. */
10170 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
10171 /* There is a link. */
10172 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
10173 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \
10174 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK
10176 /* This value indicates the current link speed of the connection. */
10177 uint16_t link_speed;
10178 /* 100Mb link speed */
10179 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
10180 /* 1Gb link speed */
10181 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
10182 /* 2Gb link speed */
10183 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
10184 /* 25Gb link speed */
10185 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
10186 /* 10Gb link speed */
10187 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
10188 /* 20Mb link speed */
10189 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
10190 /* 25Gb link speed */
10191 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
10192 /* 40Gb link speed */
10193 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
10194 /* 50Gb link speed */
10195 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
10196 /* 100Gb link speed */
10197 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
10198 /* 10Mb link speed */
10199 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
10200 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
10201 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB
10203 * This value is indicates the duplex of the current
10206 uint8_t duplex_cfg;
10207 /* Half Duplex connection. */
10208 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
10209 /* Full duplex connection. */
10210 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
10211 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \
10212 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL
10214 * This value is used to indicate the current
10215 * pause configuration. When autoneg is enabled, this value
10216 * represents the autoneg results of pause configuration.
10220 * When this bit is '1', Generation of tx pause messages
10221 * is supported. Disabled otherwise.
10223 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
10225 * When this bit is '1', Reception of rx pause messages
10226 * is supported. Disabled otherwise.
10228 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
10230 * The supported speeds for the port. This is a bit mask.
10231 * For each speed that is supported, the corrresponding
10232 * bit will be set to '1'.
10234 uint16_t support_speeds;
10235 /* 100Mb link speed (Half-duplex) */
10236 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \
10238 /* 100Mb link speed (Full-duplex) */
10239 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \
10241 /* 1Gb link speed (Half-duplex) */
10242 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \
10244 /* 1Gb link speed (Full-duplex) */
10245 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \
10247 /* 2Gb link speed */
10248 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \
10250 /* 25Gb link speed */
10251 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \
10253 /* 10Gb link speed */
10254 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \
10256 /* 20Gb link speed */
10257 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \
10259 /* 25Gb link speed */
10260 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \
10262 /* 40Gb link speed */
10263 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \
10265 /* 50Gb link speed */
10266 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \
10268 /* 100Gb link speed */
10269 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \
10271 /* 10Mb link speed (Half-duplex) */
10272 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \
10274 /* 10Mb link speed (Full-duplex) */
10275 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
10278 * Current setting of forced link speed.
10279 * When the link speed is not being forced, this
10280 * value shall be set to 0.
10282 uint16_t force_link_speed;
10283 /* 100Mb link speed */
10284 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
10285 /* 1Gb link speed */
10286 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
10287 /* 2Gb link speed */
10288 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
10289 /* 25Gb link speed */
10290 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
10291 /* 10Gb link speed */
10292 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
10293 /* 20Mb link speed */
10294 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
10295 /* 25Gb link speed */
10296 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
10297 /* 40Gb link speed */
10298 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \
10300 /* 50Gb link speed */
10301 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \
10303 /* 100Gb link speed */
10304 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
10306 /* 10Mb link speed */
10307 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
10309 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \
10310 HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB
10311 /* Current setting of auto negotiation mode. */
10313 /* Disable autoneg or autoneg disabled. No speeds are selected. */
10314 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
10315 /* Select all possible speeds for autoneg mode. */
10316 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
10318 * Select only the auto_link_speed speed for autoneg mode. This mode has
10319 * been DEPRECATED. An HWRM client should not use this mode.
10321 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
10323 * Select the auto_link_speed or any speed below that speed for autoneg.
10324 * This mode has been DEPRECATED. An HWRM client should not use this mode.
10326 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
10328 * Select the speeds based on the corresponding link speed mask value
10329 * that is provided.
10331 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
10332 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \
10333 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK
10335 * Current setting of pause autonegotiation.
10336 * Move autoneg_pause flag here.
10338 uint8_t auto_pause;
10340 * When this bit is '1', Generation of tx pause messages
10341 * has been requested. Disabled otherwise.
10343 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \
10346 * When this bit is '1', Reception of rx pause messages
10347 * has been requested. Disabled otherwise.
10349 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \
10352 * When set to 1, the advertisement of pause is enabled.
10354 * # When the auto_mode is not set to none and this flag is
10355 * set to 1, then the auto_pause bits on this port are being
10356 * advertised and autoneg pause results are being interpreted.
10357 * # When the auto_mode is not set to none and this
10358 * flag is set to 0, the pause is forced as indicated in
10359 * force_pause, and also advertised as auto_pause bits, but
10360 * the autoneg results are not interpreted since the pause
10361 * configuration is being forced.
10362 * # When the auto_mode is set to none and this flag is set to
10363 * 1, auto_pause bits should be ignored and should be set to 0.
10365 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \
10368 * Current setting for auto_link_speed. This field is only
10369 * valid when auto_mode is set to "one_speed" or "one_or_below".
10371 uint16_t auto_link_speed;
10372 /* 100Mb link speed */
10373 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
10374 /* 1Gb link speed */
10375 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
10376 /* 2Gb link speed */
10377 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
10378 /* 25Gb link speed */
10379 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
10380 /* 10Gb link speed */
10381 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
10382 /* 20Mb link speed */
10383 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
10384 /* 25Gb link speed */
10385 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
10386 /* 40Gb link speed */
10387 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
10388 /* 50Gb link speed */
10389 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
10390 /* 100Gb link speed */
10391 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
10392 /* 10Mb link speed */
10393 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
10395 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \
10396 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB
10398 * Current setting for auto_link_speed_mask that is used to
10399 * advertise speeds during autonegotiation.
10400 * This field is only valid when auto_mode is set to "mask".
10401 * The speeds specified in this field shall be a subset of
10402 * supported speeds on this port.
10404 uint16_t auto_link_speed_mask;
10405 /* 100Mb link speed (Half-duplex) */
10406 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \
10408 /* 100Mb link speed (Full-duplex) */
10409 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \
10411 /* 1Gb link speed (Half-duplex) */
10412 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \
10414 /* 1Gb link speed (Full-duplex) */
10415 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \
10417 /* 2Gb link speed */
10418 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \
10420 /* 25Gb link speed */
10421 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \
10423 /* 10Gb link speed */
10424 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \
10426 /* 20Gb link speed */
10427 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \
10429 /* 25Gb link speed */
10430 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \
10432 /* 40Gb link speed */
10433 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \
10435 /* 50Gb link speed */
10436 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \
10438 /* 100Gb link speed */
10439 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \
10441 /* 10Mb link speed (Half-duplex) */
10442 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \
10444 /* 10Mb link speed (Full-duplex) */
10445 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
10447 /* Current setting for wirespeed. */
10449 /* Wirespeed feature is disabled. */
10450 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
10451 /* Wirespeed feature is enabled. */
10452 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
10453 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \
10454 HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON
10455 /* Current setting for loopback. */
10457 /* No loopback is selected. Normal operation. */
10458 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
10460 * The HW will be configured with local loopback such that
10461 * host data is sent back to the host without modification.
10463 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
10465 * The HW will be configured with remote loopback such that
10466 * port logic will send packets back out the transmitter that
10469 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
10471 * The HW will be configured with external loopback such that
10472 * host data is sent on the trasmitter and based on the external
10473 * loopback connection the data will be received without modification.
10475 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
10476 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \
10477 HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL
10479 * Current setting of forced pause.
10480 * When the pause configuration is not being forced, then
10481 * this value shall be set to 0.
10483 uint8_t force_pause;
10485 * When this bit is '1', Generation of tx pause messages
10486 * is supported. Disabled otherwise.
10488 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
10490 * When this bit is '1', Reception of rx pause messages
10491 * is supported. Disabled otherwise.
10493 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
10495 * This value indicates the current status of the optics module on
10498 uint8_t module_status;
10499 /* Module is inserted and accepted */
10500 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \
10502 /* Module is rejected and transmit side Laser is disabled. */
10503 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \
10505 /* Module mismatch warning. */
10506 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \
10508 /* Module is rejected and powered down. */
10509 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \
10511 /* Module is not inserted. */
10512 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \
10514 /* Module status is not applicable. */
10515 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \
10517 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \
10518 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE
10519 /* Current setting for preemphasis. */
10520 uint32_t preemphasis;
10521 /* This field represents the major version of the PHY. */
10523 /* This field represents the minor version of the PHY. */
10525 /* This field represents the build version of the PHY. */
10527 /* This value represents a PHY type. */
10530 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \
10533 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \
10535 /* BASE-KR4 (Deprecated) */
10536 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \
10539 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \
10542 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \
10544 /* BASE-KR2 (Deprecated) */
10545 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \
10548 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \
10551 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \
10554 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \
10556 /* EEE capable BASE-T */
10557 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \
10559 /* SGMII connected external PHY */
10560 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \
10562 /* 25G_BASECR_CA_L */
10563 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \
10565 /* 25G_BASECR_CA_S */
10566 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \
10568 /* 25G_BASECR_CA_N */
10569 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \
10572 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \
10575 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \
10578 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \
10581 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \
10584 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \
10586 /* 100G_BASESR10 */
10587 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \
10590 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \
10593 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \
10596 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \
10599 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \
10601 /* 40G_ACTIVE_CABLE */
10602 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \
10605 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \
10608 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \
10611 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
10613 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
10614 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
10615 /* This value represents a media type. */
10616 uint8_t media_type;
10618 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
10620 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
10621 /* Direct Attached Copper */
10622 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
10624 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
10625 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \
10626 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE
10627 /* This value represents a transceiver type. */
10628 uint8_t xcvr_pkg_type;
10629 /* PHY and MAC are in the same package */
10630 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \
10632 /* PHY and MAC are in different packages */
10633 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \
10635 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \
10636 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL
10637 uint8_t eee_config_phy_addr;
10638 /* This field represents PHY address. */
10639 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \
10641 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
10643 * This field represents flags related to EEE configuration.
10644 * These EEE configuration flags are valid only when the
10645 * auto_mode is not set to none (in other words autonegotiation
10648 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \
10650 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
10652 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
10653 * Speeds for autoneg with EEE mode enabled
10654 * are based on eee_link_speed_mask.
10656 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \
10659 * This flag is valid only when eee_enabled is set to 1.
10661 * # If eee_enabled is set to 0, then EEE mode is disabled
10662 * and this flag shall be ignored.
10663 * # If eee_enabled is set to 1 and this flag is set to 1,
10664 * then Energy Efficient Ethernet (EEE) mode is enabled
10666 * # If eee_enabled is set to 1 and this flag is set to 0,
10667 * then Energy Efficient Ethernet (EEE) mode is enabled
10668 * but is currently not in use.
10670 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \
10673 * This flag is valid only when eee_enabled is set to 1.
10675 * # If eee_enabled is set to 0, then EEE mode is disabled
10676 * and this flag shall be ignored.
10677 * # If eee_enabled is set to 1 and this flag is set to 1,
10678 * then Energy Efficient Ethernet (EEE) mode is enabled
10679 * and TX LPI is enabled.
10680 * # If eee_enabled is set to 1 and this flag is set to 0,
10681 * then Energy Efficient Ethernet (EEE) mode is enabled
10682 * but TX LPI is disabled.
10684 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \
10687 * When set to 1, the parallel detection is used to determine
10688 * the speed of the link partner.
10690 * Parallel detection is used when a autonegotiation capable
10691 * device is connected to a link parter that is not capable
10692 * of autonegotiation.
10694 uint8_t parallel_detect;
10696 * When set to 1, the parallel detection is used to determine
10697 * the speed of the link partner.
10699 * Parallel detection is used when a autonegotiation capable
10700 * device is connected to a link parter that is not capable
10701 * of autonegotiation.
10703 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
10705 * The advertised speeds for the port by the link partner.
10706 * Each advertised speed will be set to '1'.
10708 uint16_t link_partner_adv_speeds;
10709 /* 100Mb link speed (Half-duplex) */
10710 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \
10712 /* 100Mb link speed (Full-duplex) */
10713 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \
10715 /* 1Gb link speed (Half-duplex) */
10716 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \
10718 /* 1Gb link speed (Full-duplex) */
10719 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \
10721 /* 2Gb link speed */
10722 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \
10724 /* 25Gb link speed */
10725 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \
10727 /* 10Gb link speed */
10728 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \
10730 /* 20Gb link speed */
10731 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \
10733 /* 25Gb link speed */
10734 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \
10736 /* 40Gb link speed */
10737 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \
10739 /* 50Gb link speed */
10740 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \
10742 /* 100Gb link speed */
10743 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \
10745 /* 10Mb link speed (Half-duplex) */
10746 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \
10748 /* 10Mb link speed (Full-duplex) */
10749 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \
10752 * The advertised autoneg for the port by the link partner.
10753 * This field is deprecated and should be set to 0.
10755 uint8_t link_partner_adv_auto_mode;
10756 /* Disable autoneg or autoneg disabled. No speeds are selected. */
10757 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \
10759 /* Select all possible speeds for autoneg mode. */
10760 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \
10763 * Select only the auto_link_speed speed for autoneg mode. This mode has
10764 * been DEPRECATED. An HWRM client should not use this mode.
10766 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \
10769 * Select the auto_link_speed or any speed below that speed for autoneg.
10770 * This mode has been DEPRECATED. An HWRM client should not use this mode.
10772 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \
10775 * Select the speeds based on the corresponding link speed mask value
10776 * that is provided.
10778 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \
10780 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \
10781 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK
10782 /* The advertised pause settings on the port by the link partner. */
10783 uint8_t link_partner_adv_pause;
10785 * When this bit is '1', Generation of tx pause messages
10786 * is supported. Disabled otherwise.
10788 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \
10791 * When this bit is '1', Reception of rx pause messages
10792 * is supported. Disabled otherwise.
10794 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \
10797 * Current setting for link speed mask that is used to
10798 * advertise speeds during autonegotiation when EEE is enabled.
10799 * This field is valid only when eee_enabled flags is set to 1.
10800 * The speeds specified in this field shall be a subset of
10801 * speeds specified in auto_link_speed_mask.
10803 uint16_t adv_eee_link_speed_mask;
10805 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
10807 /* 100Mb link speed (Full-duplex) */
10808 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \
10811 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
10813 /* 1Gb link speed (Full-duplex) */
10814 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \
10817 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
10820 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
10822 /* 10Gb link speed */
10823 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \
10826 * Current setting for link speed mask that is advertised by
10827 * the link partner when EEE is enabled.
10828 * This field is valid only when eee_enabled flags is set to 1.
10830 uint16_t link_partner_adv_eee_link_speed_mask;
10832 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \
10834 /* 100Mb link speed (Full-duplex) */
10835 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \
10838 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \
10840 /* 1Gb link speed (Full-duplex) */
10841 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \
10844 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \
10847 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \
10849 /* 10Gb link speed */
10850 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \
10852 uint32_t xcvr_identifier_type_tx_lpi_timer;
10854 * Current setting of TX LPI timer in microseconds.
10855 * This field is valid only when_eee_enabled flag is set to 1
10856 * and tx_lpi_enabled is set to 1.
10858 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \
10860 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
10861 /* This value represents transceiver identifier type. */
10862 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \
10863 UINT32_C(0xff000000)
10864 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
10866 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \
10867 (UINT32_C(0x0) << 24)
10868 /* SFP/SFP+/SFP28 */
10869 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \
10870 (UINT32_C(0x3) << 24)
10872 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \
10873 (UINT32_C(0xc) << 24)
10875 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \
10876 (UINT32_C(0xd) << 24)
10878 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \
10879 (UINT32_C(0x11) << 24)
10880 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \
10881 HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28
10883 * This value represents the current configuration of
10884 * Forward Error Correction (FEC) on the port.
10888 * When set to 1, then FEC is not supported on this port. If this flag
10889 * is set to 1, then all other FEC configuration flags shall be ignored.
10890 * When set to 0, then FEC is supported as indicated by other
10891 * configuration flags.
10892 * If no cable is attached and the HWRM does not yet know the FEC
10893 * capability, then the HWRM shall set this flag to 1 when reporting
10896 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \
10899 * When set to 1, then FEC autonegotiation is supported on this port.
10900 * When set to 0, then FEC autonegotiation is not supported on this port.
10902 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \
10905 * When set to 1, then FEC autonegotiation is enabled on this port.
10906 * When set to 0, then FEC autonegotiation is disabled if supported.
10907 * This flag should be ignored if FEC autonegotiation is not supported on this port.
10909 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \
10912 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.
10913 * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.
10915 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \
10918 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.
10919 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.
10920 * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.
10922 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \
10925 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.
10926 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.
10928 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \
10931 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.
10932 * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.
10933 * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.
10935 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \
10938 * This value is indicates the duplex of the current
10939 * connection state.
10941 uint8_t duplex_state;
10942 /* Half Duplex connection. */
10943 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
10944 /* Full duplex connection. */
10945 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
10946 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \
10947 HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL
10948 /* Option flags fields. */
10949 uint8_t option_flags;
10950 /* When this bit is '1', Media auto detect is enabled. */
10951 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \
10954 * Up to 16 bytes of null padded ASCII string representing
10956 * If the string is set to null, then the vendor name is not
10959 char phy_vendor_name[16];
10961 * Up to 16 bytes of null padded ASCII string that
10962 * identifies vendor specific part number of the PHY.
10963 * If the string is set to null, then the vendor specific
10964 * part number is not available.
10966 char phy_vendor_partnumber[16];
10967 uint8_t unused_2[7];
10969 * This field is used in Output records to indicate that the output
10970 * is completely written to RAM. This field should be read as '1'
10971 * to indicate that the output has been completely written.
10972 * When writing a command completion or response to an internal processor,
10973 * the order of writes has to be such that this field is written last.
10976 } __attribute__((packed));
10978 /*********************
10979 * hwrm_port_mac_cfg *
10980 *********************/
10983 /* hwrm_port_mac_cfg_input (size:320b/40B) */
10984 struct hwrm_port_mac_cfg_input {
10985 /* The HWRM command request type. */
10988 * The completion ring to send the completion event on. This should
10989 * be the NQ ID returned from the `nq_alloc` HWRM command.
10991 uint16_t cmpl_ring;
10993 * The sequence ID is used by the driver for tracking multiple
10994 * commands. This ID is treated as opaque data by the firmware and
10995 * the value is returned in the `hwrm_resp_hdr` upon completion.
10999 * The target ID of the command:
11000 * * 0x0-0xFFF8 - The function ID
11001 * * 0xFFF8-0xFFFE - Reserved for internal processors
11004 uint16_t target_id;
11006 * A physical address pointer pointing to a host buffer that the
11007 * command's response data will be written. This can be either a host
11008 * physical address (HPA) or a guest physical address (GPA) and must
11009 * point to a physically contiguous block of memory.
11011 uint64_t resp_addr;
11013 * In this field, there are a number of CoS mappings related flags
11014 * that are used to configure CoS mappings and their corresponding
11015 * priorities in the hardware.
11016 * For the priorities of CoS mappings, the HWRM uses the following
11017 * priority order (high to low) by default:
11020 * # tunnel_vlan_pri
11023 * A subset of CoS mappings can be enabled.
11024 * If a priority is not specified for an enabled CoS mapping, the
11025 * priority will be assigned in the above order for the enabled CoS
11026 * mappings. For example, if vlan_pri and ip_dscp CoS mappings are
11027 * enabled and their priorities are not specified, the following
11028 * priority order (high to low) will be used by the HWRM:
11033 * vlan_pri CoS mapping together with default CoS with lower priority
11034 * are enabled by default by the HWRM.
11038 * When this bit is '1', this command will configure
11039 * the MAC to match the current link state of the PHY.
11040 * If the link is not established on the PHY, then this
11041 * bit has no effect.
11043 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \
11046 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11047 * is requested to be enabled.
11049 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \
11052 * When this bit is set to '1', tunnel VLAN PRI field to
11053 * CoS mapping is requested to be enabled.
11055 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
11058 * When this bit is set to '1', the IP DSCP to CoS mapping is
11059 * requested to be enabled.
11061 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \
11064 * When this bit is '1', the HWRM is requested to
11065 * enable timestamp capture capability on the receive side
11068 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
11071 * When this bit is '1', the HWRM is requested to
11072 * disable timestamp capture capability on the receive side
11075 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \
11078 * When this bit is '1', the HWRM is requested to
11079 * enable timestamp capture capability on the transmit side
11082 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
11085 * When this bit is '1', the HWRM is requested to
11086 * disable timestamp capture capability on the transmit side
11089 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \
11092 * When this bit is '1', the Out-Of-Box WoL is requested to
11093 * be enabled on this port.
11095 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \
11098 * When this bit is '1', the the Out-Of-Box WoL is requested to
11099 * be disabled on this port.
11101 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \
11104 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11105 * is requested to be disabled.
11107 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \
11110 * When this bit is set to '1', tunnel VLAN PRI field to
11111 * CoS mapping is requested to be disabled.
11113 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \
11116 * When this bit is set to '1', the IP DSCP to CoS mapping is
11117 * requested to be disabled.
11119 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
11123 * This bit must be '1' for the ipg field to be
11126 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \
11129 * This bit must be '1' for the lpbk field to be
11132 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \
11135 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
11138 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \
11141 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
11144 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \
11147 * This bit must be '1' for the dscp2cos_map_pri field to be
11150 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \
11153 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
11156 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \
11159 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
11162 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \
11165 * This bit must be '1' for the cos_field_cfg field to be
11168 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
11170 /* Port ID of port that is to be configured. */
11173 * This value is used to configure the minimum IPG that will
11174 * be sent between packets by this port.
11177 /* This value controls the loopback setting for the MAC. */
11179 /* No loopback is selected. Normal operation. */
11180 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
11182 * The HW will be configured with local loopback such that
11183 * host data is sent back to the host without modification.
11185 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
11187 * The HW will be configured with remote loopback such that
11188 * port logic will send packets back out the transmitter that
11191 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
11192 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \
11193 HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE
11195 * This value controls the priority setting of VLAN PRI to CoS
11196 * mapping based on VLAN Tags of inner packet headers of
11197 * tunneled packets or packet headers of non-tunneled packets.
11199 * # Each XXX_pri variable shall have a unique priority value
11200 * when it is being specified.
11201 * # When comparing priorities of mappings, higher value
11202 * indicates higher priority.
11203 * For example, a value of 0-3 is returned where 0 is being
11204 * the lowest priority and 3 is being the highest priority.
11206 uint8_t vlan_pri2cos_map_pri;
11207 /* Reserved field. */
11210 * This value controls the priority setting of VLAN PRI to CoS
11211 * mapping based on VLAN Tags of tunneled header.
11212 * This mapping only applies when tunneled headers
11215 * # Each XXX_pri variable shall have a unique priority value
11216 * when it is being specified.
11217 * # When comparing priorities of mappings, higher value
11218 * indicates higher priority.
11219 * For example, a value of 0-3 is returned where 0 is being
11220 * the lowest priority and 3 is being the highest priority.
11222 uint8_t tunnel_pri2cos_map_pri;
11224 * This value controls the priority setting of IP DSCP to CoS
11225 * mapping based on inner IP header of tunneled packets or
11226 * IP header of non-tunneled packets.
11228 * # Each XXX_pri variable shall have a unique priority value
11229 * when it is being specified.
11230 * # When comparing priorities of mappings, higher value
11231 * indicates higher priority.
11232 * For example, a value of 0-3 is returned where 0 is being
11233 * the lowest priority and 3 is being the highest priority.
11235 uint8_t dscp2pri_map_pri;
11237 * This is a 16-bit bit mask that is used to request a
11238 * specific configuration of time stamp capture of PTP messages
11239 * on the receive side of this port.
11240 * This field shall be ignored if the ptp_rx_ts_capture_enable
11241 * flag is not set in this command.
11242 * Otherwise, if bit 'i' is set, then the HWRM is being
11243 * requested to configure the receive side of the port to
11244 * capture the time stamp of every received PTP message
11245 * with messageType field value set to i.
11247 uint16_t rx_ts_capture_ptp_msg_type;
11249 * This is a 16-bit bit mask that is used to request a
11250 * specific configuration of time stamp capture of PTP messages
11251 * on the transmit side of this port.
11252 * This field shall be ignored if the ptp_tx_ts_capture_enable
11253 * flag is not set in this command.
11254 * Otherwise, if bit 'i' is set, then the HWRM is being
11255 * requested to configure the transmit sied of the port to
11256 * capture the time stamp of every transmitted PTP message
11257 * with messageType field value set to i.
11259 uint16_t tx_ts_capture_ptp_msg_type;
11260 /* Configuration of CoS fields. */
11261 uint8_t cos_field_cfg;
11263 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \
11266 * This field is used to specify selection of VLAN PRI value
11267 * based on whether one or two VLAN Tags are present in
11268 * the inner packet headers of tunneled packets or
11269 * non-tunneled packets.
11270 * This field is valid only if inner VLAN PRI to CoS mapping
11272 * If VLAN PRI to CoS mapping is not enabled, then this
11273 * field shall be ignored.
11275 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
11277 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
11280 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11281 * present in the inner packet headers
11283 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
11284 (UINT32_C(0x0) << 1)
11286 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11287 * present in the inner packet headers.
11288 * No VLAN PRI shall be selected for this configuration
11289 * if only one VLAN Tag is present in the inner
11292 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
11293 (UINT32_C(0x1) << 1)
11295 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11296 * are present in the inner packet headers
11298 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
11299 (UINT32_C(0x2) << 1)
11301 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
11302 (UINT32_C(0x3) << 1)
11303 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
11304 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
11306 * This field is used to specify selection of tunnel VLAN
11307 * PRI value based on whether one or two VLAN Tags are
11308 * present in tunnel headers.
11309 * This field is valid only if tunnel VLAN PRI to CoS mapping
11311 * If tunnel VLAN PRI to CoS mapping is not enabled, then this
11312 * field shall be ignored.
11314 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
11316 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
11319 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11320 * present in the tunnel packet headers
11322 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
11323 (UINT32_C(0x0) << 3)
11325 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11326 * present in the tunnel packet headers.
11327 * No tunnel VLAN PRI shall be selected for this
11328 * configuration if only one VLAN Tag is present in
11329 * the tunnel packet headers.
11331 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
11332 (UINT32_C(0x1) << 3)
11334 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11335 * are present in the tunnel packet headers
11337 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
11338 (UINT32_C(0x2) << 3)
11340 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
11341 (UINT32_C(0x3) << 3)
11342 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
11343 HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
11345 * This field shall be used to provide default CoS value
11346 * that has been configured on this port.
11347 * This field is valid only if default CoS mapping
11349 * If default CoS mapping is not enabled, then this
11350 * field shall be ignored.
11352 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
11354 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
11356 uint8_t unused_0[3];
11357 } __attribute__((packed));
11359 /* hwrm_port_mac_cfg_output (size:128b/16B) */
11360 struct hwrm_port_mac_cfg_output {
11361 /* The specific error status for the command. */
11362 uint16_t error_code;
11363 /* The HWRM command request type. */
11365 /* The sequence ID from the original command. */
11367 /* The length of the response data in number of bytes. */
11370 * This is the configured maximum length of Ethernet packet
11371 * payload that is allowed to be received on the port.
11372 * This value does not include the number of bytes used by
11373 * Ethernet header and trailer (CRC).
11377 * This is the configured maximum length of Ethernet packet
11378 * payload that is allowed to be transmitted on the port.
11379 * This value does not include the number of bytes used by
11380 * Ethernet header and trailer (CRC).
11383 /* Current configuration of the IPG value. */
11385 /* Current value of the loopback value. */
11387 /* No loopback is selected. Normal operation. */
11388 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11390 * The HW will be configured with local loopback such that
11391 * host data is sent back to the host without modification.
11393 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11395 * The HW will be configured with remote loopback such that
11396 * port logic will send packets back out the transmitter that
11399 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11400 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \
11401 HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE
11404 * This field is used in Output records to indicate that the output
11405 * is completely written to RAM. This field should be read as '1'
11406 * to indicate that the output has been completely written.
11407 * When writing a command completion or response to an internal processor,
11408 * the order of writes has to be such that this field is written last.
11411 } __attribute__((packed));
11413 /**********************
11414 * hwrm_port_mac_qcfg *
11415 **********************/
11418 /* hwrm_port_mac_qcfg_input (size:192b/24B) */
11419 struct hwrm_port_mac_qcfg_input {
11420 /* The HWRM command request type. */
11423 * The completion ring to send the completion event on. This should
11424 * be the NQ ID returned from the `nq_alloc` HWRM command.
11426 uint16_t cmpl_ring;
11428 * The sequence ID is used by the driver for tracking multiple
11429 * commands. This ID is treated as opaque data by the firmware and
11430 * the value is returned in the `hwrm_resp_hdr` upon completion.
11434 * The target ID of the command:
11435 * * 0x0-0xFFF8 - The function ID
11436 * * 0xFFF8-0xFFFE - Reserved for internal processors
11439 uint16_t target_id;
11441 * A physical address pointer pointing to a host buffer that the
11442 * command's response data will be written. This can be either a host
11443 * physical address (HPA) or a guest physical address (GPA) and must
11444 * point to a physically contiguous block of memory.
11446 uint64_t resp_addr;
11447 /* Port ID of port that is to be configured. */
11449 uint8_t unused_0[6];
11450 } __attribute__((packed));
11452 /* hwrm_port_mac_qcfg_output (size:192b/24B) */
11453 struct hwrm_port_mac_qcfg_output {
11454 /* The specific error status for the command. */
11455 uint16_t error_code;
11456 /* The HWRM command request type. */
11458 /* The sequence ID from the original command. */
11460 /* The length of the response data in number of bytes. */
11463 * This is the configured maximum length of Ethernet packet
11464 * payload that is allowed to be received on the port.
11465 * This value does not include the number of bytes used by the
11466 * Ethernet header and trailer (CRC).
11470 * This is the configured maximum length of Ethernet packet
11471 * payload that is allowed to be transmitted on the port.
11472 * This value does not include the number of bytes used by the
11473 * Ethernet header and trailer (CRC).
11477 * The minimum IPG that will
11478 * be sent between packets by this port.
11481 /* The loopback setting for the MAC. */
11483 /* No loopback is selected. Normal operation. */
11484 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
11486 * The HW will be configured with local loopback such that
11487 * host data is sent back to the host without modification.
11489 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
11491 * The HW will be configured with remote loopback such that
11492 * port logic will send packets back out the transmitter that
11495 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
11496 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \
11497 HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE
11499 * Priority setting for VLAN PRI to CoS mapping.
11500 * # Each XXX_pri variable shall have a unique priority value
11501 * when it is being used.
11502 * # When comparing priorities of mappings, higher value
11503 * indicates higher priority.
11504 * For example, a value of 0-3 is returned where 0 is being
11505 * the lowest priority and 3 is being the highest priority.
11506 * # If the correspoding CoS mapping is not enabled, then this
11507 * field should be ignored.
11508 * # This value indicates the normalized priority value retained
11511 uint8_t vlan_pri2cos_map_pri;
11513 * In this field, a number of CoS mappings related flags
11514 * are used to indicate configured CoS mappings.
11518 * When this bit is set to '1', the inner VLAN PRI to CoS mapping
11521 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \
11524 * When this bit is set to '1', tunnel VLAN PRI field to
11525 * CoS mapping is enabled.
11527 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \
11530 * When this bit is set to '1', the IP DSCP to CoS mapping is
11533 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \
11536 * When this bit is '1', the Out-Of-Box WoL is enabled on this
11539 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \
11541 /* When this bit is '1', PTP is enabled for RX on this port. */
11542 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \
11544 /* When this bit is '1', PTP is enabled for TX on this port. */
11545 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \
11548 * Priority setting for tunnel VLAN PRI to CoS mapping.
11549 * # Each XXX_pri variable shall have a unique priority value
11550 * when it is being used.
11551 * # When comparing priorities of mappings, higher value
11552 * indicates higher priority.
11553 * For example, a value of 0-3 is returned where 0 is being
11554 * the lowest priority and 3 is being the highest priority.
11555 * # If the correspoding CoS mapping is not enabled, then this
11556 * field should be ignored.
11557 * # This value indicates the normalized priority value retained
11560 uint8_t tunnel_pri2cos_map_pri;
11562 * Priority setting for DSCP to PRI mapping.
11563 * # Each XXX_pri variable shall have a unique priority value
11564 * when it is being used.
11565 * # When comparing priorities of mappings, higher value
11566 * indicates higher priority.
11567 * For example, a value of 0-3 is returned where 0 is being
11568 * the lowest priority and 3 is being the highest priority.
11569 * # If the correspoding CoS mapping is not enabled, then this
11570 * field should be ignored.
11571 * # This value indicates the normalized priority value retained
11574 uint8_t dscp2pri_map_pri;
11576 * This is a 16-bit bit mask that represents the
11577 * current configuration of time stamp capture of PTP messages
11578 * on the receive side of this port.
11579 * If bit 'i' is set, then the receive side of the port
11580 * is configured to capture the time stamp of every
11581 * received PTP message with messageType field value set
11583 * If all bits are set to 0 (i.e. field value set 0),
11584 * then the receive side of the port is not configured
11585 * to capture timestamp for PTP messages.
11586 * If all bits are set to 1, then the receive side of the
11587 * port is configured to capture timestamp for all PTP
11590 uint16_t rx_ts_capture_ptp_msg_type;
11592 * This is a 16-bit bit mask that represents the
11593 * current configuration of time stamp capture of PTP messages
11594 * on the transmit side of this port.
11595 * If bit 'i' is set, then the transmit side of the port
11596 * is configured to capture the time stamp of every
11597 * received PTP message with messageType field value set
11599 * If all bits are set to 0 (i.e. field value set 0),
11600 * then the transmit side of the port is not configured
11601 * to capture timestamp for PTP messages.
11602 * If all bits are set to 1, then the transmit side of the
11603 * port is configured to capture timestamp for all PTP
11606 uint16_t tx_ts_capture_ptp_msg_type;
11607 /* Configuration of CoS fields. */
11608 uint8_t cos_field_cfg;
11610 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \
11613 * This field is used for selecting VLAN PRI value
11614 * based on whether one or two VLAN Tags are present in
11615 * the inner packet headers of tunneled packets or
11616 * non-tunneled packets.
11618 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \
11620 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \
11623 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11624 * present in the inner packet headers
11626 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \
11627 (UINT32_C(0x0) << 1)
11629 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11630 * present in the inner packet headers.
11631 * No VLAN PRI is selected for this configuration
11632 * if only one VLAN Tag is present in the inner
11635 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \
11636 (UINT32_C(0x1) << 1)
11638 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11639 * are present in the inner packet headers
11641 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \
11642 (UINT32_C(0x2) << 1)
11644 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \
11645 (UINT32_C(0x3) << 1)
11646 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \
11647 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
11649 * This field is used for selecting tunnel VLAN PRI value
11650 * based on whether one or two VLAN Tags are present in
11651 * the tunnel headers of tunneled packets. This selection
11652 * does not apply to non-tunneled packets.
11654 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \
11656 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \
11659 * Select inner VLAN PRI when 1 or 2 VLAN Tags are
11660 * present in the tunnel packet headers
11662 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \
11663 (UINT32_C(0x0) << 3)
11665 * Select outer VLAN Tag PRI when 2 VLAN Tags are
11666 * present in the tunnel packet headers.
11667 * No VLAN PRI is selected for this configuration
11668 * if only one VLAN Tag is present in the tunnel
11671 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \
11672 (UINT32_C(0x1) << 3)
11674 * Select outermost VLAN PRI when 1 or 2 VLAN Tags
11675 * are present in the tunnel packet headers
11677 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \
11678 (UINT32_C(0x2) << 3)
11680 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \
11681 (UINT32_C(0x3) << 3)
11682 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \
11683 HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
11685 * This field is used to provide default CoS value that
11686 * has been configured on this port.
11688 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \
11690 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
11693 * This field is used in Output records to indicate that the output
11694 * is completely written to RAM. This field should be read as '1'
11695 * to indicate that the output has been completely written.
11696 * When writing a command completion or response to an internal processor,
11697 * the order of writes has to be such that this field is written last.
11700 } __attribute__((packed));
11702 /**************************
11703 * hwrm_port_mac_ptp_qcfg *
11704 **************************/
11707 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */
11708 struct hwrm_port_mac_ptp_qcfg_input {
11709 /* The HWRM command request type. */
11712 * The completion ring to send the completion event on. This should
11713 * be the NQ ID returned from the `nq_alloc` HWRM command.
11715 uint16_t cmpl_ring;
11717 * The sequence ID is used by the driver for tracking multiple
11718 * commands. This ID is treated as opaque data by the firmware and
11719 * the value is returned in the `hwrm_resp_hdr` upon completion.
11723 * The target ID of the command:
11724 * * 0x0-0xFFF8 - The function ID
11725 * * 0xFFF8-0xFFFE - Reserved for internal processors
11728 uint16_t target_id;
11730 * A physical address pointer pointing to a host buffer that the
11731 * command's response data will be written. This can be either a host
11732 * physical address (HPA) or a guest physical address (GPA) and must
11733 * point to a physically contiguous block of memory.
11735 uint64_t resp_addr;
11736 /* Port ID of port that is being queried. */
11738 uint8_t unused_0[6];
11739 } __attribute__((packed));
11741 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */
11742 struct hwrm_port_mac_ptp_qcfg_output {
11743 /* The specific error status for the command. */
11744 uint16_t error_code;
11745 /* The HWRM command request type. */
11747 /* The sequence ID from the original command. */
11749 /* The length of the response data in number of bytes. */
11752 * In this field, a number of PTP related flags
11753 * are used to indicate configured PTP capabilities.
11757 * When this bit is set to '1', the PTP related registers are
11758 * directly accessible by the host.
11760 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \
11763 * When this bit is set to '1', the PTP information is accessible
11764 * via HWRM commands.
11766 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
11768 uint8_t unused_0[3];
11769 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
11770 uint32_t rx_ts_reg_off_lower;
11771 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
11772 uint32_t rx_ts_reg_off_upper;
11773 /* Offset of the PTP register for the sequence ID for RX. */
11774 uint32_t rx_ts_reg_off_seq_id;
11775 /* Offset of the first PTP source ID for RX. */
11776 uint32_t rx_ts_reg_off_src_id_0;
11777 /* Offset of the second PTP source ID for RX. */
11778 uint32_t rx_ts_reg_off_src_id_1;
11779 /* Offset of the third PTP source ID for RX. */
11780 uint32_t rx_ts_reg_off_src_id_2;
11781 /* Offset of the domain ID for RX. */
11782 uint32_t rx_ts_reg_off_domain_id;
11783 /* Offset of the PTP FIFO register for RX. */
11784 uint32_t rx_ts_reg_off_fifo;
11785 /* Offset of the PTP advance FIFO register for RX. */
11786 uint32_t rx_ts_reg_off_fifo_adv;
11787 /* PTP timestamp granularity for RX. */
11788 uint32_t rx_ts_reg_off_granularity;
11789 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
11790 uint32_t tx_ts_reg_off_lower;
11791 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
11792 uint32_t tx_ts_reg_off_upper;
11793 /* Offset of the PTP register for the sequence ID for TX. */
11794 uint32_t tx_ts_reg_off_seq_id;
11795 /* Offset of the PTP FIFO register for TX. */
11796 uint32_t tx_ts_reg_off_fifo;
11797 /* PTP timestamp granularity for TX. */
11798 uint32_t tx_ts_reg_off_granularity;
11799 uint8_t unused_1[7];
11801 * This field is used in Output records to indicate that the output
11802 * is completely written to RAM. This field should be read as '1'
11803 * to indicate that the output has been completely written.
11804 * When writing a command completion or response to an internal processor,
11805 * the order of writes has to be such that this field is written last.
11808 } __attribute__((packed));
11810 /********************
11811 * hwrm_port_qstats *
11812 ********************/
11815 /* hwrm_port_qstats_input (size:320b/40B) */
11816 struct hwrm_port_qstats_input {
11817 /* The HWRM command request type. */
11820 * The completion ring to send the completion event on. This should
11821 * be the NQ ID returned from the `nq_alloc` HWRM command.
11823 uint16_t cmpl_ring;
11825 * The sequence ID is used by the driver for tracking multiple
11826 * commands. This ID is treated as opaque data by the firmware and
11827 * the value is returned in the `hwrm_resp_hdr` upon completion.
11831 * The target ID of the command:
11832 * * 0x0-0xFFF8 - The function ID
11833 * * 0xFFF8-0xFFFE - Reserved for internal processors
11836 uint16_t target_id;
11838 * A physical address pointer pointing to a host buffer that the
11839 * command's response data will be written. This can be either a host
11840 * physical address (HPA) or a guest physical address (GPA) and must
11841 * point to a physically contiguous block of memory.
11843 uint64_t resp_addr;
11844 /* Port ID of port that is being queried. */
11846 uint8_t unused_0[6];
11848 * This is the host address where
11849 * Tx port statistics will be stored
11851 uint64_t tx_stat_host_addr;
11853 * This is the host address where
11854 * Rx port statistics will be stored
11856 uint64_t rx_stat_host_addr;
11857 } __attribute__((packed));
11859 /* hwrm_port_qstats_output (size:128b/16B) */
11860 struct hwrm_port_qstats_output {
11861 /* The specific error status for the command. */
11862 uint16_t error_code;
11863 /* The HWRM command request type. */
11865 /* The sequence ID from the original command. */
11867 /* The length of the response data in number of bytes. */
11869 /* The size of TX port statistics block in bytes. */
11870 uint16_t tx_stat_size;
11871 /* The size of RX port statistics block in bytes. */
11872 uint16_t rx_stat_size;
11873 uint8_t unused_0[3];
11875 * This field is used in Output records to indicate that the output
11876 * is completely written to RAM. This field should be read as '1'
11877 * to indicate that the output has been completely written.
11878 * When writing a command completion or response to an internal processor,
11879 * the order of writes has to be such that this field is written last.
11882 } __attribute__((packed));
11884 /************************
11885 * hwrm_port_qstats_ext *
11886 ************************/
11889 /* hwrm_port_qstats_ext_input (size:320b/40B) */
11890 struct hwrm_port_qstats_ext_input {
11891 /* The HWRM command request type. */
11894 * The completion ring to send the completion event on. This should
11895 * be the NQ ID returned from the `nq_alloc` HWRM command.
11897 uint16_t cmpl_ring;
11899 * The sequence ID is used by the driver for tracking multiple
11900 * commands. This ID is treated as opaque data by the firmware and
11901 * the value is returned in the `hwrm_resp_hdr` upon completion.
11905 * The target ID of the command:
11906 * * 0x0-0xFFF8 - The function ID
11907 * * 0xFFF8-0xFFFE - Reserved for internal processors
11910 uint16_t target_id;
11912 * A physical address pointer pointing to a host buffer that the
11913 * command's response data will be written. This can be either a host
11914 * physical address (HPA) or a guest physical address (GPA) and must
11915 * point to a physically contiguous block of memory.
11917 uint64_t resp_addr;
11918 /* Port ID of port that is being queried. */
11921 * The size of TX port extended
11922 * statistics block in bytes.
11924 uint16_t tx_stat_size;
11926 * The size of RX port extended
11927 * statistics block in bytes
11929 uint16_t rx_stat_size;
11930 uint8_t unused_0[2];
11932 * This is the host address where
11933 * Tx port statistics will be stored
11935 uint64_t tx_stat_host_addr;
11937 * This is the host address where
11938 * Rx port statistics will be stored
11940 uint64_t rx_stat_host_addr;
11941 } __attribute__((packed));
11943 /* hwrm_port_qstats_ext_output (size:128b/16B) */
11944 struct hwrm_port_qstats_ext_output {
11945 /* The specific error status for the command. */
11946 uint16_t error_code;
11947 /* The HWRM command request type. */
11949 /* The sequence ID from the original command. */
11951 /* The length of the response data in number of bytes. */
11953 /* The size of TX port statistics block in bytes. */
11954 uint16_t tx_stat_size;
11955 /* The size of RX port statistics block in bytes. */
11956 uint16_t rx_stat_size;
11957 uint8_t unused_0[3];
11959 * This field is used in Output records to indicate that the output
11960 * is completely written to RAM. This field should be read as '1'
11961 * to indicate that the output has been completely written.
11962 * When writing a command completion or response to an internal processor,
11963 * the order of writes has to be such that this field is written last.
11966 } __attribute__((packed));
11968 /*************************
11969 * hwrm_port_lpbk_qstats *
11970 *************************/
11973 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */
11974 struct hwrm_port_lpbk_qstats_input {
11975 /* The HWRM command request type. */
11978 * The completion ring to send the completion event on. This should
11979 * be the NQ ID returned from the `nq_alloc` HWRM command.
11981 uint16_t cmpl_ring;
11983 * The sequence ID is used by the driver for tracking multiple
11984 * commands. This ID is treated as opaque data by the firmware and
11985 * the value is returned in the `hwrm_resp_hdr` upon completion.
11989 * The target ID of the command:
11990 * * 0x0-0xFFF8 - The function ID
11991 * * 0xFFF8-0xFFFE - Reserved for internal processors
11994 uint16_t target_id;
11996 * A physical address pointer pointing to a host buffer that the
11997 * command's response data will be written. This can be either a host
11998 * physical address (HPA) or a guest physical address (GPA) and must
11999 * point to a physically contiguous block of memory.
12001 uint64_t resp_addr;
12002 } __attribute__((packed));
12004 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */
12005 struct hwrm_port_lpbk_qstats_output {
12006 /* The specific error status for the command. */
12007 uint16_t error_code;
12008 /* The HWRM command request type. */
12010 /* The sequence ID from the original command. */
12012 /* The length of the response data in number of bytes. */
12014 /* Number of transmitted unicast frames */
12015 uint64_t lpbk_ucast_frames;
12016 /* Number of transmitted multicast frames */
12017 uint64_t lpbk_mcast_frames;
12018 /* Number of transmitted broadcast frames */
12019 uint64_t lpbk_bcast_frames;
12020 /* Number of transmitted bytes for unicast traffic */
12021 uint64_t lpbk_ucast_bytes;
12022 /* Number of transmitted bytes for multicast traffic */
12023 uint64_t lpbk_mcast_bytes;
12024 /* Number of transmitted bytes for broadcast traffic */
12025 uint64_t lpbk_bcast_bytes;
12026 /* Total Tx Drops for loopback traffic reported by STATS block */
12027 uint64_t tx_stat_discard;
12028 /* Total Tx Error Drops for loopback traffic reported by STATS block */
12029 uint64_t tx_stat_error;
12030 /* Total Rx Drops for loopback traffic reported by STATS block */
12031 uint64_t rx_stat_discard;
12032 /* Total Rx Error Drops for loopback traffic reported by STATS block */
12033 uint64_t rx_stat_error;
12034 uint8_t unused_0[7];
12036 * This field is used in Output records to indicate that the output
12037 * is completely written to RAM. This field should be read as '1'
12038 * to indicate that the output has been completely written.
12039 * When writing a command completion or response to an internal processor,
12040 * the order of writes has to be such that this field is written last.
12043 } __attribute__((packed));
12045 /***********************
12046 * hwrm_port_clr_stats *
12047 ***********************/
12050 /* hwrm_port_clr_stats_input (size:192b/24B) */
12051 struct hwrm_port_clr_stats_input {
12052 /* The HWRM command request type. */
12055 * The completion ring to send the completion event on. This should
12056 * be the NQ ID returned from the `nq_alloc` HWRM command.
12058 uint16_t cmpl_ring;
12060 * The sequence ID is used by the driver for tracking multiple
12061 * commands. This ID is treated as opaque data by the firmware and
12062 * the value is returned in the `hwrm_resp_hdr` upon completion.
12066 * The target ID of the command:
12067 * * 0x0-0xFFF8 - The function ID
12068 * * 0xFFF8-0xFFFE - Reserved for internal processors
12071 uint16_t target_id;
12073 * A physical address pointer pointing to a host buffer that the
12074 * command's response data will be written. This can be either a host
12075 * physical address (HPA) or a guest physical address (GPA) and must
12076 * point to a physically contiguous block of memory.
12078 uint64_t resp_addr;
12079 /* Port ID of port that is being queried. */
12081 uint8_t unused_0[6];
12082 } __attribute__((packed));
12084 /* hwrm_port_clr_stats_output (size:128b/16B) */
12085 struct hwrm_port_clr_stats_output {
12086 /* The specific error status for the command. */
12087 uint16_t error_code;
12088 /* The HWRM command request type. */
12090 /* The sequence ID from the original command. */
12092 /* The length of the response data in number of bytes. */
12094 uint8_t unused_0[7];
12096 * This field is used in Output records to indicate that the output
12097 * is completely written to RAM. This field should be read as '1'
12098 * to indicate that the output has been completely written.
12099 * When writing a command completion or response to an internal processor,
12100 * the order of writes has to be such that this field is written last.
12103 } __attribute__((packed));
12105 /****************************
12106 * hwrm_port_lpbk_clr_stats *
12107 ****************************/
12110 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */
12111 struct hwrm_port_lpbk_clr_stats_input {
12112 /* The HWRM command request type. */
12115 * The completion ring to send the completion event on. This should
12116 * be the NQ ID returned from the `nq_alloc` HWRM command.
12118 uint16_t cmpl_ring;
12120 * The sequence ID is used by the driver for tracking multiple
12121 * commands. This ID is treated as opaque data by the firmware and
12122 * the value is returned in the `hwrm_resp_hdr` upon completion.
12126 * The target ID of the command:
12127 * * 0x0-0xFFF8 - The function ID
12128 * * 0xFFF8-0xFFFE - Reserved for internal processors
12131 uint16_t target_id;
12133 * A physical address pointer pointing to a host buffer that the
12134 * command's response data will be written. This can be either a host
12135 * physical address (HPA) or a guest physical address (GPA) and must
12136 * point to a physically contiguous block of memory.
12138 uint64_t resp_addr;
12139 } __attribute__((packed));
12141 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
12142 struct hwrm_port_lpbk_clr_stats_output {
12143 /* The specific error status for the command. */
12144 uint16_t error_code;
12145 /* The HWRM command request type. */
12147 /* The sequence ID from the original command. */
12149 /* The length of the response data in number of bytes. */
12151 uint8_t unused_0[7];
12153 * This field is used in Output records to indicate that the output
12154 * is completely written to RAM. This field should be read as '1'
12155 * to indicate that the output has been completely written.
12156 * When writing a command completion or response to an internal processor,
12157 * the order of writes has to be such that this field is written last.
12160 } __attribute__((packed));
12162 /**********************
12163 * hwrm_port_ts_query *
12164 **********************/
12167 /* hwrm_port_ts_query_input (size:192b/24B) */
12168 struct hwrm_port_ts_query_input {
12169 /* The HWRM command request type. */
12172 * The completion ring to send the completion event on. This should
12173 * be the NQ ID returned from the `nq_alloc` HWRM command.
12175 uint16_t cmpl_ring;
12177 * The sequence ID is used by the driver for tracking multiple
12178 * commands. This ID is treated as opaque data by the firmware and
12179 * the value is returned in the `hwrm_resp_hdr` upon completion.
12183 * The target ID of the command:
12184 * * 0x0-0xFFF8 - The function ID
12185 * * 0xFFF8-0xFFFE - Reserved for internal processors
12188 uint16_t target_id;
12190 * A physical address pointer pointing to a host buffer that the
12191 * command's response data will be written. This can be either a host
12192 * physical address (HPA) or a guest physical address (GPA) and must
12193 * point to a physically contiguous block of memory.
12195 uint64_t resp_addr;
12198 * Enumeration denoting the RX, TX type of the resource.
12199 * This enumeration is used for resources that are similar for both
12200 * TX and RX paths of the chip.
12202 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
12204 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
12206 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
12207 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \
12208 HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
12209 /* Port ID of port that is being queried. */
12211 uint8_t unused_0[2];
12212 } __attribute__((packed));
12214 /* hwrm_port_ts_query_output (size:192b/24B) */
12215 struct hwrm_port_ts_query_output {
12216 /* The specific error status for the command. */
12217 uint16_t error_code;
12218 /* The HWRM command request type. */
12220 /* The sequence ID from the original command. */
12222 /* The length of the response data in number of bytes. */
12224 /* Timestamp value of PTP message captured. */
12225 uint64_t ptp_msg_ts;
12226 /* Sequence ID of the PTP message captured. */
12227 uint16_t ptp_msg_seqid;
12228 uint8_t unused_0[5];
12230 * This field is used in Output records to indicate that the output
12231 * is completely written to RAM. This field should be read as '1'
12232 * to indicate that the output has been completely written.
12233 * When writing a command completion or response to an internal processor,
12234 * the order of writes has to be such that this field is written last.
12237 } __attribute__((packed));
12239 /***********************
12240 * hwrm_port_phy_qcaps *
12241 ***********************/
12244 /* hwrm_port_phy_qcaps_input (size:192b/24B) */
12245 struct hwrm_port_phy_qcaps_input {
12246 /* The HWRM command request type. */
12249 * The completion ring to send the completion event on. This should
12250 * be the NQ ID returned from the `nq_alloc` HWRM command.
12252 uint16_t cmpl_ring;
12254 * The sequence ID is used by the driver for tracking multiple
12255 * commands. This ID is treated as opaque data by the firmware and
12256 * the value is returned in the `hwrm_resp_hdr` upon completion.
12260 * The target ID of the command:
12261 * * 0x0-0xFFF8 - The function ID
12262 * * 0xFFF8-0xFFFE - Reserved for internal processors
12265 uint16_t target_id;
12267 * A physical address pointer pointing to a host buffer that the
12268 * command's response data will be written. This can be either a host
12269 * physical address (HPA) or a guest physical address (GPA) and must
12270 * point to a physically contiguous block of memory.
12272 uint64_t resp_addr;
12273 /* Port ID of port that is being queried. */
12275 uint8_t unused_0[6];
12276 } __attribute__((packed));
12278 /* hwrm_port_phy_qcaps_output (size:192b/24B) */
12279 struct hwrm_port_phy_qcaps_output {
12280 /* The specific error status for the command. */
12281 uint16_t error_code;
12282 /* The HWRM command request type. */
12284 /* The sequence ID from the original command. */
12286 /* The length of the response data in number of bytes. */
12288 /* PHY capability flags */
12291 * If set to 1, then this field indicates that the
12292 * link is capable of supporting EEE.
12294 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \
12297 * If set to 1, then this field indicates that the
12298 * PHY is capable of supporting external loopback.
12300 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \
12303 * Reserved field. The HWRM shall set this field to 0.
12304 * An HWRM client shall ignore this field.
12306 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \
12308 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2
12309 /* Number of front panel ports for this device. */
12311 /* Not supported or unknown */
12312 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
12313 /* single port device */
12314 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
12315 /* 2-port device */
12316 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
12317 /* 3-port device */
12318 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
12319 /* 4-port device */
12320 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
12321 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \
12322 HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4
12324 * This is a bit mask to indicate what speeds are supported
12325 * as forced speeds on this link.
12326 * For each speed that can be forced on this link, the
12327 * corresponding mask bit shall be set to '1'.
12329 uint16_t supported_speeds_force_mode;
12330 /* 100Mb link speed (Half-duplex) */
12331 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \
12333 /* 100Mb link speed (Full-duplex) */
12334 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \
12336 /* 1Gb link speed (Half-duplex) */
12337 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \
12339 /* 1Gb link speed (Full-duplex) */
12340 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \
12342 /* 2Gb link speed */
12343 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \
12345 /* 25Gb link speed */
12346 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \
12348 /* 10Gb link speed */
12349 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \
12351 /* 20Gb link speed */
12352 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \
12354 /* 25Gb link speed */
12355 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \
12357 /* 40Gb link speed */
12358 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \
12360 /* 50Gb link speed */
12361 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \
12363 /* 100Gb link speed */
12364 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \
12366 /* 10Mb link speed (Half-duplex) */
12367 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \
12369 /* 10Mb link speed (Full-duplex) */
12370 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
12373 * This is a bit mask to indicate what speeds are supported
12374 * for autonegotiation on this link.
12375 * For each speed that can be autonegotiated on this link, the
12376 * corresponding mask bit shall be set to '1'.
12378 uint16_t supported_speeds_auto_mode;
12379 /* 100Mb link speed (Half-duplex) */
12380 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \
12382 /* 100Mb link speed (Full-duplex) */
12383 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \
12385 /* 1Gb link speed (Half-duplex) */
12386 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \
12388 /* 1Gb link speed (Full-duplex) */
12389 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \
12391 /* 2Gb link speed */
12392 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \
12394 /* 25Gb link speed */
12395 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \
12397 /* 10Gb link speed */
12398 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \
12400 /* 20Gb link speed */
12401 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \
12403 /* 25Gb link speed */
12404 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \
12406 /* 40Gb link speed */
12407 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \
12409 /* 50Gb link speed */
12410 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \
12412 /* 100Gb link speed */
12413 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \
12415 /* 10Mb link speed (Half-duplex) */
12416 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \
12418 /* 10Mb link speed (Full-duplex) */
12419 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
12422 * This is a bit mask to indicate what speeds are supported
12423 * for EEE on this link.
12424 * For each speed that can be autonegotiated when EEE is enabled
12425 * on this link, the corresponding mask bit shall be set to '1'.
12426 * This field is only valid when the eee_suppotred is set to '1'.
12428 uint16_t supported_speeds_eee_mode;
12430 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \
12432 /* 100Mb link speed (Full-duplex) */
12433 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \
12436 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \
12438 /* 1Gb link speed (Full-duplex) */
12439 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \
12442 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \
12445 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \
12447 /* 10Gb link speed */
12448 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \
12450 uint32_t tx_lpi_timer_low;
12452 * The lowest value of TX LPI timer that can be set on this link
12453 * when EEE is enabled. This value is in microseconds.
12454 * This field is valid only when_eee_supported is set to '1'.
12456 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \
12458 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
12460 * Reserved field. The HWRM shall set this field to 0.
12461 * An HWRM client shall ignore this field.
12463 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \
12464 UINT32_C(0xff000000)
12465 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
12466 uint32_t valid_tx_lpi_timer_high;
12468 * The highest value of TX LPI timer that can be set on this link
12469 * when EEE is enabled. This value is in microseconds.
12470 * This field is valid only when_eee_supported is set to '1'.
12472 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \
12474 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
12476 * This field is used in Output records to indicate that the output
12477 * is completely written to RAM. This field should be read as '1'
12478 * to indicate that the output has been completely written.
12479 * When writing a command completion or response to an internal processor,
12480 * the order of writes has to be such that this field is written last.
12482 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \
12483 UINT32_C(0xff000000)
12484 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
12485 } __attribute__((packed));
12487 /***************************
12488 * hwrm_port_phy_i2c_write *
12489 ***************************/
12492 /* hwrm_port_phy_i2c_write_input (size:832b/104B) */
12493 struct hwrm_port_phy_i2c_write_input {
12494 /* The HWRM command request type. */
12497 * The completion ring to send the completion event on. This should
12498 * be the NQ ID returned from the `nq_alloc` HWRM command.
12500 uint16_t cmpl_ring;
12502 * The sequence ID is used by the driver for tracking multiple
12503 * commands. This ID is treated as opaque data by the firmware and
12504 * the value is returned in the `hwrm_resp_hdr` upon completion.
12508 * The target ID of the command:
12509 * * 0x0-0xFFF8 - The function ID
12510 * * 0xFFF8-0xFFFE - Reserved for internal processors
12513 uint16_t target_id;
12515 * A physical address pointer pointing to a host buffer that the
12516 * command's response data will be written. This can be either a host
12517 * physical address (HPA) or a guest physical address (GPA) and must
12518 * point to a physically contiguous block of memory.
12520 uint64_t resp_addr;
12524 * This bit must be '1' for the page_offset field to be
12527 #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \
12529 /* Port ID of port. */
12531 /* 8-bit I2C slave address. */
12532 uint8_t i2c_slave_addr;
12534 /* The page number that is being accessed over I2C. */
12535 uint16_t page_number;
12536 /* Offset within the page that is being accessed over I2C. */
12537 uint16_t page_offset;
12539 * Length of data to write, in bytes starting at the offset
12540 * specified above. If the offset is not specified, then
12541 * the data shall be written from the beginning of the page.
12543 uint8_t data_length;
12544 uint8_t unused_1[7];
12545 /* Up to 64B of data. */
12547 } __attribute__((packed));
12549 /* hwrm_port_phy_i2c_write_output (size:128b/16B) */
12550 struct hwrm_port_phy_i2c_write_output {
12551 /* The specific error status for the command. */
12552 uint16_t error_code;
12553 /* The HWRM command request type. */
12555 /* The sequence ID from the original command. */
12557 /* The length of the response data in number of bytes. */
12559 uint8_t unused_0[7];
12561 * This field is used in Output records to indicate that the output
12562 * is completely written to RAM. This field should be read as '1'
12563 * to indicate that the output has been completely written.
12564 * When writing a command completion or response to an internal processor,
12565 * the order of writes has to be such that this field is written last.
12568 } __attribute__((packed));
12570 /**************************
12571 * hwrm_port_phy_i2c_read *
12572 **************************/
12575 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */
12576 struct hwrm_port_phy_i2c_read_input {
12577 /* The HWRM command request type. */
12580 * The completion ring to send the completion event on. This should
12581 * be the NQ ID returned from the `nq_alloc` HWRM command.
12583 uint16_t cmpl_ring;
12585 * The sequence ID is used by the driver for tracking multiple
12586 * commands. This ID is treated as opaque data by the firmware and
12587 * the value is returned in the `hwrm_resp_hdr` upon completion.
12591 * The target ID of the command:
12592 * * 0x0-0xFFF8 - The function ID
12593 * * 0xFFF8-0xFFFE - Reserved for internal processors
12596 uint16_t target_id;
12598 * A physical address pointer pointing to a host buffer that the
12599 * command's response data will be written. This can be either a host
12600 * physical address (HPA) or a guest physical address (GPA) and must
12601 * point to a physically contiguous block of memory.
12603 uint64_t resp_addr;
12607 * This bit must be '1' for the page_offset field to be
12610 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \
12612 /* Port ID of port. */
12614 /* 8-bit I2C slave address. */
12615 uint8_t i2c_slave_addr;
12617 /* The page number that is being accessed over I2C. */
12618 uint16_t page_number;
12619 /* Offset within the page that is being accessed over I2C. */
12620 uint16_t page_offset;
12622 * Length of data to read, in bytes starting at the offset
12623 * specified above. If the offset is not specified, then
12624 * the data shall be read from the beginning of the page.
12626 uint8_t data_length;
12627 uint8_t unused_1[7];
12628 } __attribute__((packed));
12630 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */
12631 struct hwrm_port_phy_i2c_read_output {
12632 /* The specific error status for the command. */
12633 uint16_t error_code;
12634 /* The HWRM command request type. */
12636 /* The sequence ID from the original command. */
12638 /* The length of the response data in number of bytes. */
12640 /* Up to 64B of data. */
12642 uint8_t unused_0[7];
12644 * This field is used in Output records to indicate that the output
12645 * is completely written to RAM. This field should be read as '1'
12646 * to indicate that the output has been completely written.
12647 * When writing a command completion or response to an internal processor,
12648 * the order of writes has to be such that this field is written last.
12651 } __attribute__((packed));
12653 /*********************
12654 * hwrm_port_led_cfg *
12655 *********************/
12658 /* hwrm_port_led_cfg_input (size:512b/64B) */
12659 struct hwrm_port_led_cfg_input {
12660 /* The HWRM command request type. */
12663 * The completion ring to send the completion event on. This should
12664 * be the NQ ID returned from the `nq_alloc` HWRM command.
12666 uint16_t cmpl_ring;
12668 * The sequence ID is used by the driver for tracking multiple
12669 * commands. This ID is treated as opaque data by the firmware and
12670 * the value is returned in the `hwrm_resp_hdr` upon completion.
12674 * The target ID of the command:
12675 * * 0x0-0xFFF8 - The function ID
12676 * * 0xFFF8-0xFFFE - Reserved for internal processors
12679 uint16_t target_id;
12681 * A physical address pointer pointing to a host buffer that the
12682 * command's response data will be written. This can be either a host
12683 * physical address (HPA) or a guest physical address (GPA) and must
12684 * point to a physically contiguous block of memory.
12686 uint64_t resp_addr;
12689 * This bit must be '1' for the led0_id field to be
12692 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
12695 * This bit must be '1' for the led0_state field to be
12698 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
12701 * This bit must be '1' for the led0_color field to be
12704 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
12707 * This bit must be '1' for the led0_blink_on field to be
12710 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
12713 * This bit must be '1' for the led0_blink_off field to be
12716 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
12719 * This bit must be '1' for the led0_group_id field to be
12722 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
12725 * This bit must be '1' for the led1_id field to be
12728 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
12731 * This bit must be '1' for the led1_state field to be
12734 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \
12737 * This bit must be '1' for the led1_color field to be
12740 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \
12743 * This bit must be '1' for the led1_blink_on field to be
12746 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \
12749 * This bit must be '1' for the led1_blink_off field to be
12752 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \
12755 * This bit must be '1' for the led1_group_id field to be
12758 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \
12761 * This bit must be '1' for the led2_id field to be
12764 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \
12767 * This bit must be '1' for the led2_state field to be
12770 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \
12773 * This bit must be '1' for the led2_color field to be
12776 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \
12779 * This bit must be '1' for the led2_blink_on field to be
12782 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \
12785 * This bit must be '1' for the led2_blink_off field to be
12788 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \
12791 * This bit must be '1' for the led2_group_id field to be
12794 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \
12797 * This bit must be '1' for the led3_id field to be
12800 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \
12803 * This bit must be '1' for the led3_state field to be
12806 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \
12809 * This bit must be '1' for the led3_color field to be
12812 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \
12815 * This bit must be '1' for the led3_blink_on field to be
12818 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \
12821 * This bit must be '1' for the led3_blink_off field to be
12824 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \
12827 * This bit must be '1' for the led3_group_id field to be
12830 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \
12832 /* Port ID of port whose LEDs are configured. */
12835 * The number of LEDs that are being configured.
12836 * Up to 4 LEDs can be configured with this command.
12839 /* Reserved field. */
12841 /* An identifier for the LED #0. */
12843 /* The requested state of the LED #0. */
12844 uint8_t led0_state;
12845 /* Default state of the LED */
12846 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
12848 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
12850 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
12852 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
12853 /* Blink Alternately */
12854 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
12855 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \
12856 HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT
12857 /* The requested color of LED #0. */
12858 uint8_t led0_color;
12860 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
12862 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
12864 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
12865 /* Green or Amber */
12866 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
12867 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \
12868 HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER
12871 * If the LED #0 state is "blink" or "blinkalt", then
12872 * this field represents the requested time in milliseconds
12873 * to keep LED on between cycles.
12875 uint16_t led0_blink_on;
12877 * If the LED #0 state is "blink" or "blinkalt", then
12878 * this field represents the requested time in milliseconds
12879 * to keep LED off between cycles.
12881 uint16_t led0_blink_off;
12883 * An identifier for the group of LEDs that LED #0 belongs
12885 * If set to 0, then the LED #0 shall not be grouped and
12886 * shall be treated as an individual resource.
12887 * For all other non-zero values of this field, LED #0 shall
12888 * be grouped together with the LEDs with the same group ID
12891 uint8_t led0_group_id;
12892 /* Reserved field. */
12894 /* An identifier for the LED #1. */
12896 /* The requested state of the LED #1. */
12897 uint8_t led1_state;
12898 /* Default state of the LED */
12899 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
12901 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
12903 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
12905 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
12906 /* Blink Alternately */
12907 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
12908 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \
12909 HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT
12910 /* The requested color of LED #1. */
12911 uint8_t led1_color;
12913 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
12915 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
12917 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
12918 /* Green or Amber */
12919 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
12920 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \
12921 HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER
12924 * If the LED #1 state is "blink" or "blinkalt", then
12925 * this field represents the requested time in milliseconds
12926 * to keep LED on between cycles.
12928 uint16_t led1_blink_on;
12930 * If the LED #1 state is "blink" or "blinkalt", then
12931 * this field represents the requested time in milliseconds
12932 * to keep LED off between cycles.
12934 uint16_t led1_blink_off;
12936 * An identifier for the group of LEDs that LED #1 belongs
12938 * If set to 0, then the LED #1 shall not be grouped and
12939 * shall be treated as an individual resource.
12940 * For all other non-zero values of this field, LED #1 shall
12941 * be grouped together with the LEDs with the same group ID
12944 uint8_t led1_group_id;
12945 /* Reserved field. */
12947 /* An identifier for the LED #2. */
12949 /* The requested state of the LED #2. */
12950 uint8_t led2_state;
12951 /* Default state of the LED */
12952 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
12954 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
12956 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
12958 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
12959 /* Blink Alternately */
12960 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
12961 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \
12962 HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT
12963 /* The requested color of LED #2. */
12964 uint8_t led2_color;
12966 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
12968 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
12970 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
12971 /* Green or Amber */
12972 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
12973 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \
12974 HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER
12977 * If the LED #2 state is "blink" or "blinkalt", then
12978 * this field represents the requested time in milliseconds
12979 * to keep LED on between cycles.
12981 uint16_t led2_blink_on;
12983 * If the LED #2 state is "blink" or "blinkalt", then
12984 * this field represents the requested time in milliseconds
12985 * to keep LED off between cycles.
12987 uint16_t led2_blink_off;
12989 * An identifier for the group of LEDs that LED #2 belongs
12991 * If set to 0, then the LED #2 shall not be grouped and
12992 * shall be treated as an individual resource.
12993 * For all other non-zero values of this field, LED #2 shall
12994 * be grouped together with the LEDs with the same group ID
12997 uint8_t led2_group_id;
12998 /* Reserved field. */
13000 /* An identifier for the LED #3. */
13002 /* The requested state of the LED #3. */
13003 uint8_t led3_state;
13004 /* Default state of the LED */
13005 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
13007 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
13009 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
13011 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
13012 /* Blink Alternately */
13013 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
13014 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \
13015 HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT
13016 /* The requested color of LED #3. */
13017 uint8_t led3_color;
13019 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
13021 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
13023 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
13024 /* Green or Amber */
13025 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
13026 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \
13027 HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER
13030 * If the LED #3 state is "blink" or "blinkalt", then
13031 * this field represents the requested time in milliseconds
13032 * to keep LED on between cycles.
13034 uint16_t led3_blink_on;
13036 * If the LED #3 state is "blink" or "blinkalt", then
13037 * this field represents the requested time in milliseconds
13038 * to keep LED off between cycles.
13040 uint16_t led3_blink_off;
13042 * An identifier for the group of LEDs that LED #3 belongs
13044 * If set to 0, then the LED #3 shall not be grouped and
13045 * shall be treated as an individual resource.
13046 * For all other non-zero values of this field, LED #3 shall
13047 * be grouped together with the LEDs with the same group ID
13050 uint8_t led3_group_id;
13051 /* Reserved field. */
13053 } __attribute__((packed));
13055 /* hwrm_port_led_cfg_output (size:128b/16B) */
13056 struct hwrm_port_led_cfg_output {
13057 /* The specific error status for the command. */
13058 uint16_t error_code;
13059 /* The HWRM command request type. */
13061 /* The sequence ID from the original command. */
13063 /* The length of the response data in number of bytes. */
13065 uint8_t unused_0[7];
13067 * This field is used in Output records to indicate that the output
13068 * is completely written to RAM. This field should be read as '1'
13069 * to indicate that the output has been completely written.
13070 * When writing a command completion or response to an internal processor,
13071 * the order of writes has to be such that this field is written last.
13074 } __attribute__((packed));
13076 /**********************
13077 * hwrm_port_led_qcfg *
13078 **********************/
13081 /* hwrm_port_led_qcfg_input (size:192b/24B) */
13082 struct hwrm_port_led_qcfg_input {
13083 /* The HWRM command request type. */
13086 * The completion ring to send the completion event on. This should
13087 * be the NQ ID returned from the `nq_alloc` HWRM command.
13089 uint16_t cmpl_ring;
13091 * The sequence ID is used by the driver for tracking multiple
13092 * commands. This ID is treated as opaque data by the firmware and
13093 * the value is returned in the `hwrm_resp_hdr` upon completion.
13097 * The target ID of the command:
13098 * * 0x0-0xFFF8 - The function ID
13099 * * 0xFFF8-0xFFFE - Reserved for internal processors
13102 uint16_t target_id;
13104 * A physical address pointer pointing to a host buffer that the
13105 * command's response data will be written. This can be either a host
13106 * physical address (HPA) or a guest physical address (GPA) and must
13107 * point to a physically contiguous block of memory.
13109 uint64_t resp_addr;
13110 /* Port ID of port whose LED configuration is being queried. */
13112 uint8_t unused_0[6];
13113 } __attribute__((packed));
13115 /* hwrm_port_led_qcfg_output (size:448b/56B) */
13116 struct hwrm_port_led_qcfg_output {
13117 /* The specific error status for the command. */
13118 uint16_t error_code;
13119 /* The HWRM command request type. */
13121 /* The sequence ID from the original command. */
13123 /* The length of the response data in number of bytes. */
13126 * The number of LEDs that are configured on this port.
13127 * Up to 4 LEDs can be returned in the response.
13130 /* An identifier for the LED #0. */
13132 /* The type of LED #0. */
13135 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
13137 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
13139 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
13140 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \
13141 HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID
13142 /* The current state of the LED #0. */
13143 uint8_t led0_state;
13144 /* Default state of the LED */
13145 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
13147 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
13149 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
13151 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
13152 /* Blink Alternately */
13153 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
13154 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \
13155 HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT
13156 /* The color of LED #0. */
13157 uint8_t led0_color;
13159 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
13161 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
13163 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
13164 /* Green or Amber */
13165 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
13166 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \
13167 HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER
13170 * If the LED #0 state is "blink" or "blinkalt", then
13171 * this field represents the requested time in milliseconds
13172 * to keep LED on between cycles.
13174 uint16_t led0_blink_on;
13176 * If the LED #0 state is "blink" or "blinkalt", then
13177 * this field represents the requested time in milliseconds
13178 * to keep LED off between cycles.
13180 uint16_t led0_blink_off;
13182 * An identifier for the group of LEDs that LED #0 belongs
13184 * If set to 0, then the LED #0 is not grouped.
13185 * For all other non-zero values of this field, LED #0 is
13186 * grouped together with the LEDs with the same group ID
13189 uint8_t led0_group_id;
13190 /* An identifier for the LED #1. */
13192 /* The type of LED #1. */
13195 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
13197 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
13199 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
13200 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \
13201 HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID
13202 /* The current state of the LED #1. */
13203 uint8_t led1_state;
13204 /* Default state of the LED */
13205 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
13207 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
13209 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
13211 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
13212 /* Blink Alternately */
13213 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
13214 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \
13215 HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT
13216 /* The color of LED #1. */
13217 uint8_t led1_color;
13219 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
13221 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
13223 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
13224 /* Green or Amber */
13225 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
13226 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \
13227 HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER
13230 * If the LED #1 state is "blink" or "blinkalt", then
13231 * this field represents the requested time in milliseconds
13232 * to keep LED on between cycles.
13234 uint16_t led1_blink_on;
13236 * If the LED #1 state is "blink" or "blinkalt", then
13237 * this field represents the requested time in milliseconds
13238 * to keep LED off between cycles.
13240 uint16_t led1_blink_off;
13242 * An identifier for the group of LEDs that LED #1 belongs
13244 * If set to 0, then the LED #1 is not grouped.
13245 * For all other non-zero values of this field, LED #1 is
13246 * grouped together with the LEDs with the same group ID
13249 uint8_t led1_group_id;
13250 /* An identifier for the LED #2. */
13252 /* The type of LED #2. */
13255 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
13257 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
13259 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
13260 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \
13261 HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID
13262 /* The current state of the LED #2. */
13263 uint8_t led2_state;
13264 /* Default state of the LED */
13265 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
13267 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
13269 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
13271 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
13272 /* Blink Alternately */
13273 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
13274 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \
13275 HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT
13276 /* The color of LED #2. */
13277 uint8_t led2_color;
13279 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
13281 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
13283 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
13284 /* Green or Amber */
13285 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
13286 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \
13287 HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER
13290 * If the LED #2 state is "blink" or "blinkalt", then
13291 * this field represents the requested time in milliseconds
13292 * to keep LED on between cycles.
13294 uint16_t led2_blink_on;
13296 * If the LED #2 state is "blink" or "blinkalt", then
13297 * this field represents the requested time in milliseconds
13298 * to keep LED off between cycles.
13300 uint16_t led2_blink_off;
13302 * An identifier for the group of LEDs that LED #2 belongs
13304 * If set to 0, then the LED #2 is not grouped.
13305 * For all other non-zero values of this field, LED #2 is
13306 * grouped together with the LEDs with the same group ID
13309 uint8_t led2_group_id;
13310 /* An identifier for the LED #3. */
13312 /* The type of LED #3. */
13315 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
13317 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
13319 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
13320 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \
13321 HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID
13322 /* The current state of the LED #3. */
13323 uint8_t led3_state;
13324 /* Default state of the LED */
13325 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
13327 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
13329 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
13331 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
13332 /* Blink Alternately */
13333 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
13334 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \
13335 HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT
13336 /* The color of LED #3. */
13337 uint8_t led3_color;
13339 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
13341 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
13343 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
13344 /* Green or Amber */
13345 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
13346 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \
13347 HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER
13350 * If the LED #3 state is "blink" or "blinkalt", then
13351 * this field represents the requested time in milliseconds
13352 * to keep LED on between cycles.
13354 uint16_t led3_blink_on;
13356 * If the LED #3 state is "blink" or "blinkalt", then
13357 * this field represents the requested time in milliseconds
13358 * to keep LED off between cycles.
13360 uint16_t led3_blink_off;
13362 * An identifier for the group of LEDs that LED #3 belongs
13364 * If set to 0, then the LED #3 is not grouped.
13365 * For all other non-zero values of this field, LED #3 is
13366 * grouped together with the LEDs with the same group ID
13369 uint8_t led3_group_id;
13370 uint8_t unused_4[6];
13372 * This field is used in Output records to indicate that the output
13373 * is completely written to RAM. This field should be read as '1'
13374 * to indicate that the output has been completely written.
13375 * When writing a command completion or response to an internal processor,
13376 * the order of writes has to be such that this field is written last.
13379 } __attribute__((packed));
13381 /***********************
13382 * hwrm_port_led_qcaps *
13383 ***********************/
13386 /* hwrm_port_led_qcaps_input (size:192b/24B) */
13387 struct hwrm_port_led_qcaps_input {
13388 /* The HWRM command request type. */
13391 * The completion ring to send the completion event on. This should
13392 * be the NQ ID returned from the `nq_alloc` HWRM command.
13394 uint16_t cmpl_ring;
13396 * The sequence ID is used by the driver for tracking multiple
13397 * commands. This ID is treated as opaque data by the firmware and
13398 * the value is returned in the `hwrm_resp_hdr` upon completion.
13402 * The target ID of the command:
13403 * * 0x0-0xFFF8 - The function ID
13404 * * 0xFFF8-0xFFFE - Reserved for internal processors
13407 uint16_t target_id;
13409 * A physical address pointer pointing to a host buffer that the
13410 * command's response data will be written. This can be either a host
13411 * physical address (HPA) or a guest physical address (GPA) and must
13412 * point to a physically contiguous block of memory.
13414 uint64_t resp_addr;
13415 /* Port ID of port whose LED configuration is being queried. */
13417 uint8_t unused_0[6];
13418 } __attribute__((packed));
13420 /* hwrm_port_led_qcaps_output (size:384b/48B) */
13421 struct hwrm_port_led_qcaps_output {
13422 /* The specific error status for the command. */
13423 uint16_t error_code;
13424 /* The HWRM command request type. */
13426 /* The sequence ID from the original command. */
13428 /* The length of the response data in number of bytes. */
13431 * The number of LEDs that are configured on this port.
13432 * Up to 4 LEDs can be returned in the response.
13435 /* Reserved for future use. */
13437 /* An identifier for the LED #0. */
13439 /* The type of LED #0. */
13442 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
13444 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
13446 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
13447 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \
13448 HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID
13450 * An identifier for the group of LEDs that LED #0 belongs
13452 * If set to 0, then the LED #0 cannot be grouped.
13453 * For all other non-zero values of this field, LED #0 is
13454 * grouped together with the LEDs with the same group ID
13457 uint8_t led0_group_id;
13459 /* The states supported by LED #0. */
13460 uint16_t led0_state_caps;
13462 * If set to 1, this LED is enabled.
13463 * If set to 0, this LED is disabled.
13465 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \
13468 * If set to 1, off state is supported on this LED.
13469 * If set to 0, off state is not supported on this LED.
13471 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \
13474 * If set to 1, on state is supported on this LED.
13475 * If set to 0, on state is not supported on this LED.
13477 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \
13480 * If set to 1, blink state is supported on this LED.
13481 * If set to 0, blink state is not supported on this LED.
13483 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \
13486 * If set to 1, blink_alt state is supported on this LED.
13487 * If set to 0, blink_alt state is not supported on this LED.
13489 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \
13491 /* The colors supported by LED #0. */
13492 uint16_t led0_color_caps;
13494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \
13497 * If set to 1, Amber color is supported on this LED.
13498 * If set to 0, Amber color is not supported on this LED.
13500 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \
13503 * If set to 1, Green color is supported on this LED.
13504 * If set to 0, Green color is not supported on this LED.
13506 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \
13508 /* An identifier for the LED #1. */
13510 /* The type of LED #1. */
13513 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
13515 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
13517 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
13518 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \
13519 HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID
13521 * An identifier for the group of LEDs that LED #1 belongs
13523 * If set to 0, then the LED #0 cannot be grouped.
13524 * For all other non-zero values of this field, LED #0 is
13525 * grouped together with the LEDs with the same group ID
13528 uint8_t led1_group_id;
13530 /* The states supported by LED #1. */
13531 uint16_t led1_state_caps;
13533 * If set to 1, this LED is enabled.
13534 * If set to 0, this LED is disabled.
13536 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \
13539 * If set to 1, off state is supported on this LED.
13540 * If set to 0, off state is not supported on this LED.
13542 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \
13545 * If set to 1, on state is supported on this LED.
13546 * If set to 0, on state is not supported on this LED.
13548 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \
13551 * If set to 1, blink state is supported on this LED.
13552 * If set to 0, blink state is not supported on this LED.
13554 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \
13557 * If set to 1, blink_alt state is supported on this LED.
13558 * If set to 0, blink_alt state is not supported on this LED.
13560 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \
13562 /* The colors supported by LED #1. */
13563 uint16_t led1_color_caps;
13565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \
13568 * If set to 1, Amber color is supported on this LED.
13569 * If set to 0, Amber color is not supported on this LED.
13571 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \
13574 * If set to 1, Green color is supported on this LED.
13575 * If set to 0, Green color is not supported on this LED.
13577 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \
13579 /* An identifier for the LED #2. */
13581 /* The type of LED #2. */
13584 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
13586 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
13588 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
13589 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \
13590 HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID
13592 * An identifier for the group of LEDs that LED #0 belongs
13594 * If set to 0, then the LED #0 cannot be grouped.
13595 * For all other non-zero values of this field, LED #0 is
13596 * grouped together with the LEDs with the same group ID
13599 uint8_t led2_group_id;
13601 /* The states supported by LED #2. */
13602 uint16_t led2_state_caps;
13604 * If set to 1, this LED is enabled.
13605 * If set to 0, this LED is disabled.
13607 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \
13610 * If set to 1, off state is supported on this LED.
13611 * If set to 0, off state is not supported on this LED.
13613 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \
13616 * If set to 1, on state is supported on this LED.
13617 * If set to 0, on state is not supported on this LED.
13619 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \
13622 * If set to 1, blink state is supported on this LED.
13623 * If set to 0, blink state is not supported on this LED.
13625 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \
13628 * If set to 1, blink_alt state is supported on this LED.
13629 * If set to 0, blink_alt state is not supported on this LED.
13631 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \
13633 /* The colors supported by LED #2. */
13634 uint16_t led2_color_caps;
13636 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \
13639 * If set to 1, Amber color is supported on this LED.
13640 * If set to 0, Amber color is not supported on this LED.
13642 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \
13645 * If set to 1, Green color is supported on this LED.
13646 * If set to 0, Green color is not supported on this LED.
13648 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \
13650 /* An identifier for the LED #3. */
13652 /* The type of LED #3. */
13655 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
13657 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
13659 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
13660 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \
13661 HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID
13663 * An identifier for the group of LEDs that LED #3 belongs
13665 * If set to 0, then the LED #0 cannot be grouped.
13666 * For all other non-zero values of this field, LED #0 is
13667 * grouped together with the LEDs with the same group ID
13670 uint8_t led3_group_id;
13672 /* The states supported by LED #3. */
13673 uint16_t led3_state_caps;
13675 * If set to 1, this LED is enabled.
13676 * If set to 0, this LED is disabled.
13678 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \
13681 * If set to 1, off state is supported on this LED.
13682 * If set to 0, off state is not supported on this LED.
13684 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \
13687 * If set to 1, on state is supported on this LED.
13688 * If set to 0, on state is not supported on this LED.
13690 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \
13693 * If set to 1, blink state is supported on this LED.
13694 * If set to 0, blink state is not supported on this LED.
13696 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \
13699 * If set to 1, blink_alt state is supported on this LED.
13700 * If set to 0, blink_alt state is not supported on this LED.
13702 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \
13704 /* The colors supported by LED #3. */
13705 uint16_t led3_color_caps;
13707 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \
13710 * If set to 1, Amber color is supported on this LED.
13711 * If set to 0, Amber color is not supported on this LED.
13713 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \
13716 * If set to 1, Green color is supported on this LED.
13717 * If set to 0, Green color is not supported on this LED.
13719 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \
13721 uint8_t unused_4[3];
13723 * This field is used in Output records to indicate that the output
13724 * is completely written to RAM. This field should be read as '1'
13725 * to indicate that the output has been completely written.
13726 * When writing a command completion or response to an internal processor,
13727 * the order of writes has to be such that this field is written last.
13730 } __attribute__((packed));
13732 /***********************
13733 * hwrm_queue_qportcfg *
13734 ***********************/
13737 /* hwrm_queue_qportcfg_input (size:192b/24B) */
13738 struct hwrm_queue_qportcfg_input {
13739 /* The HWRM command request type. */
13742 * The completion ring to send the completion event on. This should
13743 * be the NQ ID returned from the `nq_alloc` HWRM command.
13745 uint16_t cmpl_ring;
13747 * The sequence ID is used by the driver for tracking multiple
13748 * commands. This ID is treated as opaque data by the firmware and
13749 * the value is returned in the `hwrm_resp_hdr` upon completion.
13753 * The target ID of the command:
13754 * * 0x0-0xFFF8 - The function ID
13755 * * 0xFFF8-0xFFFE - Reserved for internal processors
13758 uint16_t target_id;
13760 * A physical address pointer pointing to a host buffer that the
13761 * command's response data will be written. This can be either a host
13762 * physical address (HPA) or a guest physical address (GPA) and must
13763 * point to a physically contiguous block of memory.
13765 uint64_t resp_addr;
13768 * Enumeration denoting the RX, TX type of the resource.
13769 * This enumeration is used for resources that are similar for both
13770 * TX and RX paths of the chip.
13772 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
13774 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
13776 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
13777 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \
13778 HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
13780 * Port ID of port for which the queue configuration is being
13781 * queried. This field is only required when sent by IPC.
13785 * Drivers will set this capability when it can use
13786 * queue_idx_service_profile to map the queues to application.
13788 uint8_t drv_qmap_cap;
13790 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
13792 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
13793 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \
13794 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED
13796 } __attribute__((packed));
13798 /* hwrm_queue_qportcfg_output (size:256b/32B) */
13799 struct hwrm_queue_qportcfg_output {
13800 /* The specific error status for the command. */
13801 uint16_t error_code;
13802 /* The HWRM command request type. */
13804 /* The sequence ID from the original command. */
13806 /* The length of the response data in number of bytes. */
13809 * The maximum number of queues that can be configured on this
13811 * Valid values range from 1 through 8.
13813 uint8_t max_configurable_queues;
13815 * The maximum number of lossless queues that can be configured
13817 * Valid values range from 0 through 8.
13819 uint8_t max_configurable_lossless_queues;
13821 * Bitmask indicating which queues can be configured by the
13822 * hwrm_queue_cfg command.
13824 * Each bit represents a specific queue where bit 0 represents
13825 * queue 0 and bit 7 represents queue 7.
13826 * # A value of 0 indicates that the queue is not configurable
13827 * by the hwrm_queue_cfg command.
13828 * # A value of 1 indicates that the queue is configurable.
13829 * # A hwrm_queue_cfg command shall return error when trying to
13830 * configure a queue not configurable.
13832 uint8_t queue_cfg_allowed;
13833 /* Information about queue configuration. */
13834 uint8_t queue_cfg_info;
13836 * If this flag is set to '1', then the queues are
13837 * configured asymmetrically on TX and RX sides.
13838 * If this flag is set to '0', then the queues are
13839 * configured symmetrically on TX and RX sides. For
13840 * symmetric configuration, the queue configuration
13841 * including queue ids and service profiles on the
13842 * TX side is the same as the corresponding queue
13843 * configuration on the RX side.
13845 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
13848 * Bitmask indicating which queues can be configured by the
13849 * hwrm_queue_pfcenable_cfg command.
13851 * Each bit represents a specific priority where bit 0 represents
13852 * priority 0 and bit 7 represents priority 7.
13853 * # A value of 0 indicates that the priority is not configurable by
13854 * the hwrm_queue_pfcenable_cfg command.
13855 * # A value of 1 indicates that the priority is configurable.
13856 * # A hwrm_queue_pfcenable_cfg command shall return error when
13857 * trying to configure a priority that is not configurable.
13859 uint8_t queue_pfcenable_cfg_allowed;
13861 * Bitmask indicating which queues can be configured by the
13862 * hwrm_queue_pri2cos_cfg command.
13864 * Each bit represents a specific queue where bit 0 represents
13865 * queue 0 and bit 7 represents queue 7.
13866 * # A value of 0 indicates that the queue is not configurable
13867 * by the hwrm_queue_pri2cos_cfg command.
13868 * # A value of 1 indicates that the queue is configurable.
13869 * # A hwrm_queue_pri2cos_cfg command shall return error when
13870 * trying to configure a queue that is not configurable.
13872 uint8_t queue_pri2cos_cfg_allowed;
13874 * Bitmask indicating which queues can be configured by the
13875 * hwrm_queue_pri2cos_cfg command.
13877 * Each bit represents a specific queue where bit 0 represents
13878 * queue 0 and bit 7 represents queue 7.
13879 * # A value of 0 indicates that the queue is not configurable
13880 * by the hwrm_queue_pri2cos_cfg command.
13881 * # A value of 1 indicates that the queue is configurable.
13882 * # A hwrm_queue_pri2cos_cfg command shall return error when
13883 * trying to configure a queue not configurable.
13885 uint8_t queue_cos2bw_cfg_allowed;
13887 * ID of CoS Queue 0.
13890 * # This ID can be used on any subsequent call to an hwrm command
13891 * that takes a queue id.
13892 * # IDs must always be queried by this command before any use
13893 * by the driver or software.
13894 * # Any driver or software should not make any assumptions about
13896 * # A value of 0xff indicates that the queue is not available.
13897 * # Available queues may not be in sequential order.
13900 /* This value is applicable to CoS queues only. */
13901 uint8_t queue_id0_service_profile;
13902 /* Lossy (best-effort) */
13903 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \
13905 /* Lossless (legacy) */
13906 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \
13908 /* Lossless RoCE */
13909 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \
13911 /* Lossy RoCE CNP */
13912 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \
13915 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \
13917 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13918 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \
13920 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \
13921 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN
13923 * ID of CoS Queue 1.
13926 * # This ID can be used on any subsequent call to an hwrm command
13927 * that takes a queue id.
13928 * # IDs must always be queried by this command before any use
13929 * by the driver or software.
13930 * # Any driver or software should not make any assumptions about
13932 * # A value of 0xff indicates that the queue is not available.
13933 * # Available queues may not be in sequential order.
13936 /* This value is applicable to CoS queues only. */
13937 uint8_t queue_id1_service_profile;
13938 /* Lossy (best-effort) */
13939 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \
13941 /* Lossless (legacy) */
13942 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \
13944 /* Lossless RoCE */
13945 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \
13947 /* Lossy RoCE CNP */
13948 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \
13951 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \
13953 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \
13956 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \
13957 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN
13959 * ID of CoS Queue 2.
13962 * # This ID can be used on any subsequent call to an hwrm command
13963 * that takes a queue id.
13964 * # IDs must always be queried by this command before any use
13965 * by the driver or software.
13966 * # Any driver or software should not make any assumptions about
13968 * # A value of 0xff indicates that the queue is not available.
13969 * # Available queues may not be in sequential order.
13972 /* This value is applicable to CoS queues only. */
13973 uint8_t queue_id2_service_profile;
13974 /* Lossy (best-effort) */
13975 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \
13977 /* Lossless (legacy) */
13978 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \
13980 /* Lossless RoCE */
13981 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \
13983 /* Lossy RoCE CNP */
13984 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \
13987 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \
13989 /* Set to 0xFF... (All Fs) if there is no service profile specified */
13990 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \
13992 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \
13993 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN
13995 * ID of CoS Queue 3.
13998 * # This ID can be used on any subsequent call to an hwrm command
13999 * that takes a queue id.
14000 * # IDs must always be queried by this command before any use
14001 * by the driver or software.
14002 * # Any driver or software should not make any assumptions about
14004 * # A value of 0xff indicates that the queue is not available.
14005 * # Available queues may not be in sequential order.
14008 /* This value is applicable to CoS queues only. */
14009 uint8_t queue_id3_service_profile;
14010 /* Lossy (best-effort) */
14011 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \
14013 /* Lossless (legacy) */
14014 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \
14016 /* Lossless RoCE */
14017 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \
14019 /* Lossy RoCE CNP */
14020 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14023 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \
14025 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14026 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \
14028 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \
14029 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN
14031 * ID of CoS Queue 4.
14034 * # This ID can be used on any subsequent call to an hwrm command
14035 * that takes a queue id.
14036 * # IDs must always be queried by this command before any use
14037 * by the driver or software.
14038 * # Any driver or software should not make any assumptions about
14040 * # A value of 0xff indicates that the queue is not available.
14041 * # Available queues may not be in sequential order.
14044 /* This value is applicable to CoS queues only. */
14045 uint8_t queue_id4_service_profile;
14046 /* Lossy (best-effort) */
14047 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \
14049 /* Lossless (legacy) */
14050 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \
14052 /* Lossless RoCE */
14053 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \
14055 /* Lossy RoCE CNP */
14056 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14059 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \
14061 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14062 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \
14064 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \
14065 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN
14067 * ID of CoS Queue 5.
14070 * # This ID can be used on any subsequent call to an hwrm command
14071 * that takes a queue id.
14072 * # IDs must always be queried by this command before any use
14073 * by the driver or software.
14074 * # Any driver or software should not make any assumptions about
14076 * # A value of 0xff indicates that the queue is not available.
14077 * # Available queues may not be in sequential order.
14080 /* This value is applicable to CoS queues only. */
14081 uint8_t queue_id5_service_profile;
14082 /* Lossy (best-effort) */
14083 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \
14085 /* Lossless (legacy) */
14086 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \
14088 /* Lossless RoCE */
14089 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \
14091 /* Lossy RoCE CNP */
14092 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14095 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \
14097 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \
14100 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \
14101 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN
14103 * ID of CoS Queue 6.
14106 * # This ID can be used on any subsequent call to an hwrm command
14107 * that takes a queue id.
14108 * # IDs must always be queried by this command before any use
14109 * by the driver or software.
14110 * # Any driver or software should not make any assumptions about
14112 * # A value of 0xff indicates that the queue is not available.
14113 * # Available queues may not be in sequential order.
14116 /* This value is applicable to CoS queues only. */
14117 uint8_t queue_id6_service_profile;
14118 /* Lossy (best-effort) */
14119 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \
14121 /* Lossless (legacy) */
14122 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \
14124 /* Lossless RoCE */
14125 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \
14127 /* Lossy RoCE CNP */
14128 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14131 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \
14133 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14134 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \
14136 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \
14137 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN
14139 * ID of CoS Queue 7.
14142 * # This ID can be used on any subsequent call to an hwrm command
14143 * that takes a queue id.
14144 * # IDs must always be queried by this command before any use
14145 * by the driver or software.
14146 * # Any driver or software should not make any assumptions about
14148 * # A value of 0xff indicates that the queue is not available.
14149 * # Available queues may not be in sequential order.
14152 /* This value is applicable to CoS queues only. */
14153 uint8_t queue_id7_service_profile;
14154 /* Lossy (best-effort) */
14155 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \
14157 /* Lossless (legacy) */
14158 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \
14160 /* Lossless RoCE */
14161 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \
14163 /* Lossy RoCE CNP */
14164 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \
14167 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \
14169 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14170 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \
14172 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \
14173 HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN
14175 * This field is used in Output records to indicate that the output
14176 * is completely written to RAM. This field should be read as '1'
14177 * to indicate that the output has been completely written.
14178 * When writing a command completion or response to an internal processor,
14179 * the order of writes has to be such that this field is written last.
14182 } __attribute__((packed));
14184 /*******************
14185 * hwrm_queue_qcfg *
14186 *******************/
14189 /* hwrm_queue_qcfg_input (size:192b/24B) */
14190 struct hwrm_queue_qcfg_input {
14191 /* The HWRM command request type. */
14194 * The completion ring to send the completion event on. This should
14195 * be the NQ ID returned from the `nq_alloc` HWRM command.
14197 uint16_t cmpl_ring;
14199 * The sequence ID is used by the driver for tracking multiple
14200 * commands. This ID is treated as opaque data by the firmware and
14201 * the value is returned in the `hwrm_resp_hdr` upon completion.
14205 * The target ID of the command:
14206 * * 0x0-0xFFF8 - The function ID
14207 * * 0xFFF8-0xFFFE - Reserved for internal processors
14210 uint16_t target_id;
14212 * A physical address pointer pointing to a host buffer that the
14213 * command's response data will be written. This can be either a host
14214 * physical address (HPA) or a guest physical address (GPA) and must
14215 * point to a physically contiguous block of memory.
14217 uint64_t resp_addr;
14220 * Enumeration denoting the RX, TX type of the resource.
14221 * This enumeration is used for resources that are similar for both
14222 * TX and RX paths of the chip.
14224 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
14226 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14228 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14229 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \
14230 HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
14231 /* Queue ID of the queue. */
14233 } __attribute__((packed));
14235 /* hwrm_queue_qcfg_output (size:128b/16B) */
14236 struct hwrm_queue_qcfg_output {
14237 /* The specific error status for the command. */
14238 uint16_t error_code;
14239 /* The HWRM command request type. */
14241 /* The sequence ID from the original command. */
14243 /* The length of the response data in number of bytes. */
14246 * This value is a the estimate packet length used in the
14249 uint32_t queue_len;
14250 /* This value is applicable to CoS queues only. */
14251 uint8_t service_profile;
14252 /* Lossy (best-effort) */
14253 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
14255 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
14256 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14257 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
14258 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \
14259 HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN
14260 /* Information about queue configuration. */
14261 uint8_t queue_cfg_info;
14263 * If this flag is set to '1', then the queue is
14264 * configured asymmetrically on TX and RX sides.
14265 * If this flag is set to '0', then this queue is
14266 * configured symmetrically on TX and RX sides.
14268 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
14272 * This field is used in Output records to indicate that the output
14273 * is completely written to RAM. This field should be read as '1'
14274 * to indicate that the output has been completely written.
14275 * When writing a command completion or response to an internal processor,
14276 * the order of writes has to be such that this field is written last.
14279 } __attribute__((packed));
14281 /******************
14283 ******************/
14286 /* hwrm_queue_cfg_input (size:320b/40B) */
14287 struct hwrm_queue_cfg_input {
14288 /* The HWRM command request type. */
14291 * The completion ring to send the completion event on. This should
14292 * be the NQ ID returned from the `nq_alloc` HWRM command.
14294 uint16_t cmpl_ring;
14296 * The sequence ID is used by the driver for tracking multiple
14297 * commands. This ID is treated as opaque data by the firmware and
14298 * the value is returned in the `hwrm_resp_hdr` upon completion.
14302 * The target ID of the command:
14303 * * 0x0-0xFFF8 - The function ID
14304 * * 0xFFF8-0xFFFE - Reserved for internal processors
14307 uint16_t target_id;
14309 * A physical address pointer pointing to a host buffer that the
14310 * command's response data will be written. This can be either a host
14311 * physical address (HPA) or a guest physical address (GPA) and must
14312 * point to a physically contiguous block of memory.
14314 uint64_t resp_addr;
14317 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
14318 * This enumeration is used for resources that are similar for both
14319 * TX and RX paths of the chip.
14321 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
14322 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
14324 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14326 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14327 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
14328 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
14329 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \
14330 HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
14333 * This bit must be '1' for the dflt_len field to be
14336 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
14338 * This bit must be '1' for the service_profile field to be
14341 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
14342 /* Queue ID of queue that is to be configured by this function. */
14345 * This value is a the estimate packet length used in the
14347 * Set to 0xFF... (All Fs) to not adjust this value.
14350 /* This value is applicable to CoS queues only. */
14351 uint8_t service_profile;
14352 /* Lossy (best-effort) */
14353 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
14355 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
14356 /* Set to 0xFF... (All Fs) if there is no service profile specified */
14357 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
14358 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \
14359 HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN
14360 uint8_t unused_0[7];
14361 } __attribute__((packed));
14363 /* hwrm_queue_cfg_output (size:128b/16B) */
14364 struct hwrm_queue_cfg_output {
14365 /* The specific error status for the command. */
14366 uint16_t error_code;
14367 /* The HWRM command request type. */
14369 /* The sequence ID from the original command. */
14371 /* The length of the response data in number of bytes. */
14373 uint8_t unused_0[7];
14375 * This field is used in Output records to indicate that the output
14376 * is completely written to RAM. This field should be read as '1'
14377 * to indicate that the output has been completely written.
14378 * When writing a command completion or response to an internal processor,
14379 * the order of writes has to be such that this field is written last.
14382 } __attribute__((packed));
14384 /*****************************
14385 * hwrm_queue_pfcenable_qcfg *
14386 *****************************/
14389 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */
14390 struct hwrm_queue_pfcenable_qcfg_input {
14391 /* The HWRM command request type. */
14394 * The completion ring to send the completion event on. This should
14395 * be the NQ ID returned from the `nq_alloc` HWRM command.
14397 uint16_t cmpl_ring;
14399 * The sequence ID is used by the driver for tracking multiple
14400 * commands. This ID is treated as opaque data by the firmware and
14401 * the value is returned in the `hwrm_resp_hdr` upon completion.
14405 * The target ID of the command:
14406 * * 0x0-0xFFF8 - The function ID
14407 * * 0xFFF8-0xFFFE - Reserved for internal processors
14410 uint16_t target_id;
14412 * A physical address pointer pointing to a host buffer that the
14413 * command's response data will be written. This can be either a host
14414 * physical address (HPA) or a guest physical address (GPA) and must
14415 * point to a physically contiguous block of memory.
14417 uint64_t resp_addr;
14419 * Port ID of port for which the table is being configured.
14420 * The HWRM needs to check whether this function is allowed
14421 * to configure pri2cos mapping on this port.
14424 uint8_t unused_0[6];
14425 } __attribute__((packed));
14427 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */
14428 struct hwrm_queue_pfcenable_qcfg_output {
14429 /* The specific error status for the command. */
14430 uint16_t error_code;
14431 /* The HWRM command request type. */
14433 /* The sequence ID from the original command. */
14435 /* The length of the response data in number of bytes. */
14438 /* If set to 1, then PFC is enabled on PRI 0. */
14439 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \
14441 /* If set to 1, then PFC is enabled on PRI 1. */
14442 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \
14444 /* If set to 1, then PFC is enabled on PRI 2. */
14445 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \
14447 /* If set to 1, then PFC is enabled on PRI 3. */
14448 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \
14450 /* If set to 1, then PFC is enabled on PRI 4. */
14451 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \
14453 /* If set to 1, then PFC is enabled on PRI 5. */
14454 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \
14456 /* If set to 1, then PFC is enabled on PRI 6. */
14457 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \
14459 /* If set to 1, then PFC is enabled on PRI 7. */
14460 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \
14462 uint8_t unused_0[3];
14464 * This field is used in Output records to indicate that the output
14465 * is completely written to RAM. This field should be read as '1'
14466 * to indicate that the output has been completely written.
14467 * When writing a command completion or response to an internal processor,
14468 * the order of writes has to be such that this field is written last.
14471 } __attribute__((packed));
14473 /****************************
14474 * hwrm_queue_pfcenable_cfg *
14475 ****************************/
14478 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */
14479 struct hwrm_queue_pfcenable_cfg_input {
14480 /* The HWRM command request type. */
14483 * The completion ring to send the completion event on. This should
14484 * be the NQ ID returned from the `nq_alloc` HWRM command.
14486 uint16_t cmpl_ring;
14488 * The sequence ID is used by the driver for tracking multiple
14489 * commands. This ID is treated as opaque data by the firmware and
14490 * the value is returned in the `hwrm_resp_hdr` upon completion.
14494 * The target ID of the command:
14495 * * 0x0-0xFFF8 - The function ID
14496 * * 0xFFF8-0xFFFE - Reserved for internal processors
14499 uint16_t target_id;
14501 * A physical address pointer pointing to a host buffer that the
14502 * command's response data will be written. This can be either a host
14503 * physical address (HPA) or a guest physical address (GPA) and must
14504 * point to a physically contiguous block of memory.
14506 uint64_t resp_addr;
14508 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
14509 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \
14511 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
14512 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \
14514 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
14515 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \
14517 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
14518 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \
14520 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
14521 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \
14523 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
14524 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \
14526 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
14527 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \
14529 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
14530 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \
14533 * Port ID of port for which the table is being configured.
14534 * The HWRM needs to check whether this function is allowed
14535 * to configure pri2cos mapping on this port.
14538 uint8_t unused_0[2];
14539 } __attribute__((packed));
14541 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */
14542 struct hwrm_queue_pfcenable_cfg_output {
14543 /* The specific error status for the command. */
14544 uint16_t error_code;
14545 /* The HWRM command request type. */
14547 /* The sequence ID from the original command. */
14549 /* The length of the response data in number of bytes. */
14551 uint8_t unused_0[7];
14553 * This field is used in Output records to indicate that the output
14554 * is completely written to RAM. This field should be read as '1'
14555 * to indicate that the output has been completely written.
14556 * When writing a command completion or response to an internal processor,
14557 * the order of writes has to be such that this field is written last.
14560 } __attribute__((packed));
14562 /***************************
14563 * hwrm_queue_pri2cos_qcfg *
14564 ***************************/
14567 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */
14568 struct hwrm_queue_pri2cos_qcfg_input {
14569 /* The HWRM command request type. */
14572 * The completion ring to send the completion event on. This should
14573 * be the NQ ID returned from the `nq_alloc` HWRM command.
14575 uint16_t cmpl_ring;
14577 * The sequence ID is used by the driver for tracking multiple
14578 * commands. This ID is treated as opaque data by the firmware and
14579 * the value is returned in the `hwrm_resp_hdr` upon completion.
14583 * The target ID of the command:
14584 * * 0x0-0xFFF8 - The function ID
14585 * * 0xFFF8-0xFFFE - Reserved for internal processors
14588 uint16_t target_id;
14590 * A physical address pointer pointing to a host buffer that the
14591 * command's response data will be written. This can be either a host
14592 * physical address (HPA) or a guest physical address (GPA) and must
14593 * point to a physically contiguous block of memory.
14595 uint64_t resp_addr;
14598 * Enumeration denoting the RX, TX type of the resource.
14599 * This enumeration is used for resources that are similar for both
14600 * TX and RX paths of the chip.
14602 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
14604 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14606 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14607 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \
14608 HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
14610 * When this bit is set to '0', the query is
14611 * for VLAN PRI field in tunnel headers.
14612 * When this bit is set to '1', the query is
14613 * for VLAN PRI field in inner packet headers.
14615 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
14617 * Port ID of port for which the table is being configured.
14618 * The HWRM needs to check whether this function is allowed
14619 * to configure pri2cos mapping on this port.
14622 uint8_t unused_0[3];
14623 } __attribute__((packed));
14625 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */
14626 struct hwrm_queue_pri2cos_qcfg_output {
14627 /* The specific error status for the command. */
14628 uint16_t error_code;
14629 /* The HWRM command request type. */
14631 /* The sequence ID from the original command. */
14633 /* The length of the response data in number of bytes. */
14636 * CoS Queue assigned to priority 0. This value can only
14637 * be changed before traffic has started.
14638 * A value of 0xff indicates that no CoS queue is assigned to the
14639 * specified priority.
14641 uint8_t pri0_cos_queue_id;
14643 * CoS Queue assigned to priority 1. This value can only
14644 * be changed before traffic has started.
14645 * A value of 0xff indicates that no CoS queue is assigned to the
14646 * specified priority.
14648 uint8_t pri1_cos_queue_id;
14650 * CoS Queue assigned to priority 2 This value can only
14651 * be changed before traffic has started.
14652 * A value of 0xff indicates that no CoS queue is assigned to the
14653 * specified priority.
14655 uint8_t pri2_cos_queue_id;
14657 * CoS Queue assigned to priority 3. This value can only
14658 * be changed before traffic has started.
14659 * A value of 0xff indicates that no CoS queue is assigned to the
14660 * specified priority.
14662 uint8_t pri3_cos_queue_id;
14664 * CoS Queue assigned to priority 4. This value can only
14665 * be changed before traffic has started.
14666 * A value of 0xff indicates that no CoS queue is assigned to the
14667 * specified priority.
14669 uint8_t pri4_cos_queue_id;
14671 * CoS Queue assigned to priority 5. This value can only
14672 * be changed before traffic has started.
14673 * A value of 0xff indicates that no CoS queue is assigned to the
14674 * specified priority.
14676 uint8_t pri5_cos_queue_id;
14678 * CoS Queue assigned to priority 6. This value can only
14679 * be changed before traffic has started.
14680 * A value of 0xff indicates that no CoS queue is assigned to the
14681 * specified priority.
14683 uint8_t pri6_cos_queue_id;
14685 * CoS Queue assigned to priority 7. This value can only
14686 * be changed before traffic has started.
14687 * A value of 0xff indicates that no CoS queue is assigned to the
14688 * specified priority.
14690 uint8_t pri7_cos_queue_id;
14691 /* Information about queue configuration. */
14692 uint8_t queue_cfg_info;
14694 * If this flag is set to '1', then the PRI to CoS
14695 * configuration is asymmetric on TX and RX sides.
14696 * If this flag is set to '0', then PRI to CoS configuration
14697 * is symmetric on TX and RX sides.
14699 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \
14701 uint8_t unused_0[6];
14703 * This field is used in Output records to indicate that the output
14704 * is completely written to RAM. This field should be read as '1'
14705 * to indicate that the output has been completely written.
14706 * When writing a command completion or response to an internal processor,
14707 * the order of writes has to be such that this field is written last.
14710 } __attribute__((packed));
14712 /**************************
14713 * hwrm_queue_pri2cos_cfg *
14714 **************************/
14717 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */
14718 struct hwrm_queue_pri2cos_cfg_input {
14719 /* The HWRM command request type. */
14722 * The completion ring to send the completion event on. This should
14723 * be the NQ ID returned from the `nq_alloc` HWRM command.
14725 uint16_t cmpl_ring;
14727 * The sequence ID is used by the driver for tracking multiple
14728 * commands. This ID is treated as opaque data by the firmware and
14729 * the value is returned in the `hwrm_resp_hdr` upon completion.
14733 * The target ID of the command:
14734 * * 0x0-0xFFF8 - The function ID
14735 * * 0xFFF8-0xFFFE - Reserved for internal processors
14738 uint16_t target_id;
14740 * A physical address pointer pointing to a host buffer that the
14741 * command's response data will be written. This can be either a host
14742 * physical address (HPA) or a guest physical address (GPA) and must
14743 * point to a physically contiguous block of memory.
14745 uint64_t resp_addr;
14748 * Enumeration denoting the RX, TX, or both directions applicable to the resource.
14749 * This enumeration is used for resources that are similar for both
14750 * TX and RX paths of the chip.
14752 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
14753 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
14755 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
14757 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
14758 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
14759 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
14760 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \
14761 HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
14763 * When this bit is set to '0', the mapping is requested
14764 * for VLAN PRI field in tunnel headers.
14765 * When this bit is set to '1', the mapping is requested
14766 * for VLAN PRI field in inner packet headers.
14768 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
14771 * This bit must be '1' for the pri0_cos_queue_id field to be
14774 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \
14777 * This bit must be '1' for the pri1_cos_queue_id field to be
14780 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \
14783 * This bit must be '1' for the pri2_cos_queue_id field to be
14786 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \
14789 * This bit must be '1' for the pri3_cos_queue_id field to be
14792 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \
14795 * This bit must be '1' for the pri4_cos_queue_id field to be
14798 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \
14801 * This bit must be '1' for the pri5_cos_queue_id field to be
14804 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \
14807 * This bit must be '1' for the pri6_cos_queue_id field to be
14810 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \
14813 * This bit must be '1' for the pri7_cos_queue_id field to be
14816 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \
14819 * Port ID of port for which the table is being configured.
14820 * The HWRM needs to check whether this function is allowed
14821 * to configure pri2cos mapping on this port.
14825 * CoS Queue assigned to priority 0. This value can only
14826 * be changed before traffic has started.
14828 uint8_t pri0_cos_queue_id;
14830 * CoS Queue assigned to priority 1. This value can only
14831 * be changed before traffic has started.
14833 uint8_t pri1_cos_queue_id;
14835 * CoS Queue assigned to priority 2 This value can only
14836 * be changed before traffic has started.
14838 uint8_t pri2_cos_queue_id;
14840 * CoS Queue assigned to priority 3. This value can only
14841 * be changed before traffic has started.
14843 uint8_t pri3_cos_queue_id;
14845 * CoS Queue assigned to priority 4. This value can only
14846 * be changed before traffic has started.
14848 uint8_t pri4_cos_queue_id;
14850 * CoS Queue assigned to priority 5. This value can only
14851 * be changed before traffic has started.
14853 uint8_t pri5_cos_queue_id;
14855 * CoS Queue assigned to priority 6. This value can only
14856 * be changed before traffic has started.
14858 uint8_t pri6_cos_queue_id;
14860 * CoS Queue assigned to priority 7. This value can only
14861 * be changed before traffic has started.
14863 uint8_t pri7_cos_queue_id;
14864 uint8_t unused_0[7];
14865 } __attribute__((packed));
14867 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */
14868 struct hwrm_queue_pri2cos_cfg_output {
14869 /* The specific error status for the command. */
14870 uint16_t error_code;
14871 /* The HWRM command request type. */
14873 /* The sequence ID from the original command. */
14875 /* The length of the response data in number of bytes. */
14877 uint8_t unused_0[7];
14879 * This field is used in Output records to indicate that the output
14880 * is completely written to RAM. This field should be read as '1'
14881 * to indicate that the output has been completely written.
14882 * When writing a command completion or response to an internal processor,
14883 * the order of writes has to be such that this field is written last.
14886 } __attribute__((packed));
14888 /**************************
14889 * hwrm_queue_cos2bw_qcfg *
14890 **************************/
14893 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */
14894 struct hwrm_queue_cos2bw_qcfg_input {
14895 /* The HWRM command request type. */
14898 * The completion ring to send the completion event on. This should
14899 * be the NQ ID returned from the `nq_alloc` HWRM command.
14901 uint16_t cmpl_ring;
14903 * The sequence ID is used by the driver for tracking multiple
14904 * commands. This ID is treated as opaque data by the firmware and
14905 * the value is returned in the `hwrm_resp_hdr` upon completion.
14909 * The target ID of the command:
14910 * * 0x0-0xFFF8 - The function ID
14911 * * 0xFFF8-0xFFFE - Reserved for internal processors
14914 uint16_t target_id;
14916 * A physical address pointer pointing to a host buffer that the
14917 * command's response data will be written. This can be either a host
14918 * physical address (HPA) or a guest physical address (GPA) and must
14919 * point to a physically contiguous block of memory.
14921 uint64_t resp_addr;
14923 * Port ID of port for which the table is being configured.
14924 * The HWRM needs to check whether this function is allowed
14925 * to configure TC BW assignment on this port.
14928 uint8_t unused_0[6];
14929 } __attribute__((packed));
14931 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */
14932 struct hwrm_queue_cos2bw_qcfg_output {
14933 /* The specific error status for the command. */
14934 uint16_t error_code;
14935 /* The HWRM command request type. */
14937 /* The sequence ID from the original command. */
14939 /* The length of the response data in number of bytes. */
14941 /* ID of CoS Queue 0. */
14946 * Minimum BW allocated to CoS Queue.
14947 * The HWRM will translate this value into byte counter and
14948 * time interval used for this COS inside the device.
14950 uint32_t queue_id0_min_bw;
14951 /* The bandwidth value. */
14952 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
14953 UINT32_C(0xfffffff)
14954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
14956 /* The granularity of the value (bits or bytes). */
14957 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \
14958 UINT32_C(0x10000000)
14959 /* Value is in bits. */
14960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
14961 (UINT32_C(0x0) << 28)
14962 /* Value is in bytes. */
14963 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
14964 (UINT32_C(0x1) << 28)
14965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
14966 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
14967 /* bw_value_unit is 3 b */
14968 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
14969 UINT32_C(0xe0000000)
14970 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
14972 /* Value is in Mb or MB (base 10). */
14973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
14974 (UINT32_C(0x0) << 29)
14975 /* Value is in Kb or KB (base 10). */
14976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
14977 (UINT32_C(0x2) << 29)
14978 /* Value is in bits or bytes. */
14979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
14980 (UINT32_C(0x4) << 29)
14981 /* Value is in Gb or GB (base 10). */
14982 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
14983 (UINT32_C(0x6) << 29)
14984 /* Value is in 1/100th of a percentage of total bandwidth. */
14985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
14986 (UINT32_C(0x1) << 29)
14988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
14989 (UINT32_C(0x7) << 29)
14990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
14991 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
14993 * Maximum BW allocated to CoS Queue.
14994 * The HWRM will translate this value into byte counter and
14995 * time interval used for this COS inside the device.
14997 uint32_t queue_id0_max_bw;
14998 /* The bandwidth value. */
14999 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
15000 UINT32_C(0xfffffff)
15001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
15003 /* The granularity of the value (bits or bytes). */
15004 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \
15005 UINT32_C(0x10000000)
15006 /* Value is in bits. */
15007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
15008 (UINT32_C(0x0) << 28)
15009 /* Value is in bytes. */
15010 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
15011 (UINT32_C(0x1) << 28)
15012 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
15013 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
15014 /* bw_value_unit is 3 b */
15015 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
15016 UINT32_C(0xe0000000)
15017 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
15019 /* Value is in Mb or MB (base 10). */
15020 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
15021 (UINT32_C(0x0) << 29)
15022 /* Value is in Kb or KB (base 10). */
15023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
15024 (UINT32_C(0x2) << 29)
15025 /* Value is in bits or bytes. */
15026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
15027 (UINT32_C(0x4) << 29)
15028 /* Value is in Gb or GB (base 10). */
15029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
15030 (UINT32_C(0x6) << 29)
15031 /* Value is in 1/100th of a percentage of total bandwidth. */
15032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15033 (UINT32_C(0x1) << 29)
15035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
15036 (UINT32_C(0x7) << 29)
15037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
15038 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
15039 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15040 uint8_t queue_id0_tsa_assign;
15041 /* Strict Priority */
15042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \
15044 /* Enhanced Transmission Selection */
15045 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
15048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
15051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
15054 * Priority level for strict priority. Valid only when the
15055 * tsa_assign is 0 - Strict Priority (SP)
15056 * 0..7 - Valid values.
15057 * 8..255 - Reserved.
15059 uint8_t queue_id0_pri_lvl;
15061 * Weight used to allocate remaining BW for this COS after
15062 * servicing guaranteed bandwidths for all COS.
15064 uint8_t queue_id0_bw_weight;
15065 /* ID of CoS Queue 1. */
15068 * Minimum BW allocated to CoS Queue.
15069 * The HWRM will translate this value into byte counter and
15070 * time interval used for this COS inside the device.
15072 uint32_t queue_id1_min_bw;
15073 /* The bandwidth value. */
15074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
15075 UINT32_C(0xfffffff)
15076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
15078 /* The granularity of the value (bits or bytes). */
15079 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \
15080 UINT32_C(0x10000000)
15081 /* Value is in bits. */
15082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
15083 (UINT32_C(0x0) << 28)
15084 /* Value is in bytes. */
15085 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
15086 (UINT32_C(0x1) << 28)
15087 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
15088 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
15089 /* bw_value_unit is 3 b */
15090 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
15091 UINT32_C(0xe0000000)
15092 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
15094 /* Value is in Mb or MB (base 10). */
15095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
15096 (UINT32_C(0x0) << 29)
15097 /* Value is in Kb or KB (base 10). */
15098 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
15099 (UINT32_C(0x2) << 29)
15100 /* Value is in bits or bytes. */
15101 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
15102 (UINT32_C(0x4) << 29)
15103 /* Value is in Gb or GB (base 10). */
15104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
15105 (UINT32_C(0x6) << 29)
15106 /* Value is in 1/100th of a percentage of total bandwidth. */
15107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15108 (UINT32_C(0x1) << 29)
15110 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
15111 (UINT32_C(0x7) << 29)
15112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
15113 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
15115 * Maximum BW allocated to CoS queue.
15116 * The HWRM will translate this value into byte counter and
15117 * time interval used for this COS inside the device.
15119 uint32_t queue_id1_max_bw;
15120 /* The bandwidth value. */
15121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
15122 UINT32_C(0xfffffff)
15123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
15125 /* The granularity of the value (bits or bytes). */
15126 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \
15127 UINT32_C(0x10000000)
15128 /* Value is in bits. */
15129 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
15130 (UINT32_C(0x0) << 28)
15131 /* Value is in bytes. */
15132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
15133 (UINT32_C(0x1) << 28)
15134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
15135 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
15136 /* bw_value_unit is 3 b */
15137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
15138 UINT32_C(0xe0000000)
15139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
15141 /* Value is in Mb or MB (base 10). */
15142 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
15143 (UINT32_C(0x0) << 29)
15144 /* Value is in Kb or KB (base 10). */
15145 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
15146 (UINT32_C(0x2) << 29)
15147 /* Value is in bits or bytes. */
15148 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
15149 (UINT32_C(0x4) << 29)
15150 /* Value is in Gb or GB (base 10). */
15151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
15152 (UINT32_C(0x6) << 29)
15153 /* Value is in 1/100th of a percentage of total bandwidth. */
15154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15155 (UINT32_C(0x1) << 29)
15157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
15158 (UINT32_C(0x7) << 29)
15159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
15160 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
15161 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15162 uint8_t queue_id1_tsa_assign;
15163 /* Strict Priority */
15164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \
15166 /* Enhanced Transmission Selection */
15167 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
15170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
15173 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
15176 * Priority level for strict priority. Valid only when the
15177 * tsa_assign is 0 - Strict Priority (SP)
15178 * 0..7 - Valid values.
15179 * 8..255 - Reserved.
15181 uint8_t queue_id1_pri_lvl;
15183 * Weight used to allocate remaining BW for this COS after
15184 * servicing guaranteed bandwidths for all COS.
15186 uint8_t queue_id1_bw_weight;
15187 /* ID of CoS Queue 2. */
15190 * Minimum BW allocated to CoS Queue.
15191 * The HWRM will translate this value into byte counter and
15192 * time interval used for this COS inside the device.
15194 uint32_t queue_id2_min_bw;
15195 /* The bandwidth value. */
15196 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
15197 UINT32_C(0xfffffff)
15198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
15200 /* The granularity of the value (bits or bytes). */
15201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \
15202 UINT32_C(0x10000000)
15203 /* Value is in bits. */
15204 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
15205 (UINT32_C(0x0) << 28)
15206 /* Value is in bytes. */
15207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
15208 (UINT32_C(0x1) << 28)
15209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
15210 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
15211 /* bw_value_unit is 3 b */
15212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
15213 UINT32_C(0xe0000000)
15214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
15216 /* Value is in Mb or MB (base 10). */
15217 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
15218 (UINT32_C(0x0) << 29)
15219 /* Value is in Kb or KB (base 10). */
15220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
15221 (UINT32_C(0x2) << 29)
15222 /* Value is in bits or bytes. */
15223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
15224 (UINT32_C(0x4) << 29)
15225 /* Value is in Gb or GB (base 10). */
15226 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
15227 (UINT32_C(0x6) << 29)
15228 /* Value is in 1/100th of a percentage of total bandwidth. */
15229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15230 (UINT32_C(0x1) << 29)
15232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
15233 (UINT32_C(0x7) << 29)
15234 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
15235 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
15237 * Maximum BW allocated to CoS queue.
15238 * The HWRM will translate this value into byte counter and
15239 * time interval used for this COS inside the device.
15241 uint32_t queue_id2_max_bw;
15242 /* The bandwidth value. */
15243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
15244 UINT32_C(0xfffffff)
15245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
15247 /* The granularity of the value (bits or bytes). */
15248 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \
15249 UINT32_C(0x10000000)
15250 /* Value is in bits. */
15251 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
15252 (UINT32_C(0x0) << 28)
15253 /* Value is in bytes. */
15254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
15255 (UINT32_C(0x1) << 28)
15256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
15257 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
15258 /* bw_value_unit is 3 b */
15259 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
15260 UINT32_C(0xe0000000)
15261 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
15263 /* Value is in Mb or MB (base 10). */
15264 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
15265 (UINT32_C(0x0) << 29)
15266 /* Value is in Kb or KB (base 10). */
15267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
15268 (UINT32_C(0x2) << 29)
15269 /* Value is in bits or bytes. */
15270 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
15271 (UINT32_C(0x4) << 29)
15272 /* Value is in Gb or GB (base 10). */
15273 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
15274 (UINT32_C(0x6) << 29)
15275 /* Value is in 1/100th of a percentage of total bandwidth. */
15276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15277 (UINT32_C(0x1) << 29)
15279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
15280 (UINT32_C(0x7) << 29)
15281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
15282 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
15283 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15284 uint8_t queue_id2_tsa_assign;
15285 /* Strict Priority */
15286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \
15288 /* Enhanced Transmission Selection */
15289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
15292 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
15295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
15298 * Priority level for strict priority. Valid only when the
15299 * tsa_assign is 0 - Strict Priority (SP)
15300 * 0..7 - Valid values.
15301 * 8..255 - Reserved.
15303 uint8_t queue_id2_pri_lvl;
15305 * Weight used to allocate remaining BW for this COS after
15306 * servicing guaranteed bandwidths for all COS.
15308 uint8_t queue_id2_bw_weight;
15309 /* ID of CoS Queue 3. */
15312 * Minimum BW allocated to CoS Queue.
15313 * The HWRM will translate this value into byte counter and
15314 * time interval used for this COS inside the device.
15316 uint32_t queue_id3_min_bw;
15317 /* The bandwidth value. */
15318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
15319 UINT32_C(0xfffffff)
15320 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
15322 /* The granularity of the value (bits or bytes). */
15323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \
15324 UINT32_C(0x10000000)
15325 /* Value is in bits. */
15326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
15327 (UINT32_C(0x0) << 28)
15328 /* Value is in bytes. */
15329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
15330 (UINT32_C(0x1) << 28)
15331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
15332 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
15333 /* bw_value_unit is 3 b */
15334 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
15335 UINT32_C(0xe0000000)
15336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
15338 /* Value is in Mb or MB (base 10). */
15339 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
15340 (UINT32_C(0x0) << 29)
15341 /* Value is in Kb or KB (base 10). */
15342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
15343 (UINT32_C(0x2) << 29)
15344 /* Value is in bits or bytes. */
15345 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
15346 (UINT32_C(0x4) << 29)
15347 /* Value is in Gb or GB (base 10). */
15348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
15349 (UINT32_C(0x6) << 29)
15350 /* Value is in 1/100th of a percentage of total bandwidth. */
15351 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15352 (UINT32_C(0x1) << 29)
15354 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
15355 (UINT32_C(0x7) << 29)
15356 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
15357 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
15359 * Maximum BW allocated to CoS queue.
15360 * The HWRM will translate this value into byte counter and
15361 * time interval used for this COS inside the device.
15363 uint32_t queue_id3_max_bw;
15364 /* The bandwidth value. */
15365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
15366 UINT32_C(0xfffffff)
15367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
15369 /* The granularity of the value (bits or bytes). */
15370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \
15371 UINT32_C(0x10000000)
15372 /* Value is in bits. */
15373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
15374 (UINT32_C(0x0) << 28)
15375 /* Value is in bytes. */
15376 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
15377 (UINT32_C(0x1) << 28)
15378 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
15379 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
15380 /* bw_value_unit is 3 b */
15381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
15382 UINT32_C(0xe0000000)
15383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
15385 /* Value is in Mb or MB (base 10). */
15386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
15387 (UINT32_C(0x0) << 29)
15388 /* Value is in Kb or KB (base 10). */
15389 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
15390 (UINT32_C(0x2) << 29)
15391 /* Value is in bits or bytes. */
15392 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
15393 (UINT32_C(0x4) << 29)
15394 /* Value is in Gb or GB (base 10). */
15395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
15396 (UINT32_C(0x6) << 29)
15397 /* Value is in 1/100th of a percentage of total bandwidth. */
15398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15399 (UINT32_C(0x1) << 29)
15401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
15402 (UINT32_C(0x7) << 29)
15403 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
15404 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
15405 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15406 uint8_t queue_id3_tsa_assign;
15407 /* Strict Priority */
15408 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \
15410 /* Enhanced Transmission Selection */
15411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
15414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
15417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
15420 * Priority level for strict priority. Valid only when the
15421 * tsa_assign is 0 - Strict Priority (SP)
15422 * 0..7 - Valid values.
15423 * 8..255 - Reserved.
15425 uint8_t queue_id3_pri_lvl;
15427 * Weight used to allocate remaining BW for this COS after
15428 * servicing guaranteed bandwidths for all COS.
15430 uint8_t queue_id3_bw_weight;
15431 /* ID of CoS Queue 4. */
15434 * Minimum BW allocated to CoS Queue.
15435 * The HWRM will translate this value into byte counter and
15436 * time interval used for this COS inside the device.
15438 uint32_t queue_id4_min_bw;
15439 /* The bandwidth value. */
15440 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
15441 UINT32_C(0xfffffff)
15442 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
15444 /* The granularity of the value (bits or bytes). */
15445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \
15446 UINT32_C(0x10000000)
15447 /* Value is in bits. */
15448 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
15449 (UINT32_C(0x0) << 28)
15450 /* Value is in bytes. */
15451 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
15452 (UINT32_C(0x1) << 28)
15453 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
15454 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
15455 /* bw_value_unit is 3 b */
15456 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
15457 UINT32_C(0xe0000000)
15458 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
15460 /* Value is in Mb or MB (base 10). */
15461 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
15462 (UINT32_C(0x0) << 29)
15463 /* Value is in Kb or KB (base 10). */
15464 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
15465 (UINT32_C(0x2) << 29)
15466 /* Value is in bits or bytes. */
15467 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
15468 (UINT32_C(0x4) << 29)
15469 /* Value is in Gb or GB (base 10). */
15470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
15471 (UINT32_C(0x6) << 29)
15472 /* Value is in 1/100th of a percentage of total bandwidth. */
15473 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15474 (UINT32_C(0x1) << 29)
15476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
15477 (UINT32_C(0x7) << 29)
15478 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
15479 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
15481 * Maximum BW allocated to CoS queue.
15482 * The HWRM will translate this value into byte counter and
15483 * time interval used for this COS inside the device.
15485 uint32_t queue_id4_max_bw;
15486 /* The bandwidth value. */
15487 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
15488 UINT32_C(0xfffffff)
15489 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
15491 /* The granularity of the value (bits or bytes). */
15492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \
15493 UINT32_C(0x10000000)
15494 /* Value is in bits. */
15495 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
15496 (UINT32_C(0x0) << 28)
15497 /* Value is in bytes. */
15498 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
15499 (UINT32_C(0x1) << 28)
15500 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
15501 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
15502 /* bw_value_unit is 3 b */
15503 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
15504 UINT32_C(0xe0000000)
15505 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
15507 /* Value is in Mb or MB (base 10). */
15508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
15509 (UINT32_C(0x0) << 29)
15510 /* Value is in Kb or KB (base 10). */
15511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
15512 (UINT32_C(0x2) << 29)
15513 /* Value is in bits or bytes. */
15514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
15515 (UINT32_C(0x4) << 29)
15516 /* Value is in Gb or GB (base 10). */
15517 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
15518 (UINT32_C(0x6) << 29)
15519 /* Value is in 1/100th of a percentage of total bandwidth. */
15520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15521 (UINT32_C(0x1) << 29)
15523 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
15524 (UINT32_C(0x7) << 29)
15525 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
15526 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
15527 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15528 uint8_t queue_id4_tsa_assign;
15529 /* Strict Priority */
15530 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \
15532 /* Enhanced Transmission Selection */
15533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
15536 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
15539 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
15542 * Priority level for strict priority. Valid only when the
15543 * tsa_assign is 0 - Strict Priority (SP)
15544 * 0..7 - Valid values.
15545 * 8..255 - Reserved.
15547 uint8_t queue_id4_pri_lvl;
15549 * Weight used to allocate remaining BW for this COS after
15550 * servicing guaranteed bandwidths for all COS.
15552 uint8_t queue_id4_bw_weight;
15553 /* ID of CoS Queue 5. */
15556 * Minimum BW allocated to CoS Queue.
15557 * The HWRM will translate this value into byte counter and
15558 * time interval used for this COS inside the device.
15560 uint32_t queue_id5_min_bw;
15561 /* The bandwidth value. */
15562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
15563 UINT32_C(0xfffffff)
15564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
15566 /* The granularity of the value (bits or bytes). */
15567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \
15568 UINT32_C(0x10000000)
15569 /* Value is in bits. */
15570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
15571 (UINT32_C(0x0) << 28)
15572 /* Value is in bytes. */
15573 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
15574 (UINT32_C(0x1) << 28)
15575 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
15576 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
15577 /* bw_value_unit is 3 b */
15578 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
15579 UINT32_C(0xe0000000)
15580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
15582 /* Value is in Mb or MB (base 10). */
15583 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
15584 (UINT32_C(0x0) << 29)
15585 /* Value is in Kb or KB (base 10). */
15586 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
15587 (UINT32_C(0x2) << 29)
15588 /* Value is in bits or bytes. */
15589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
15590 (UINT32_C(0x4) << 29)
15591 /* Value is in Gb or GB (base 10). */
15592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
15593 (UINT32_C(0x6) << 29)
15594 /* Value is in 1/100th of a percentage of total bandwidth. */
15595 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15596 (UINT32_C(0x1) << 29)
15598 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
15599 (UINT32_C(0x7) << 29)
15600 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
15601 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
15603 * Maximum BW allocated to CoS queue.
15604 * The HWRM will translate this value into byte counter and
15605 * time interval used for this COS inside the device.
15607 uint32_t queue_id5_max_bw;
15608 /* The bandwidth value. */
15609 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
15610 UINT32_C(0xfffffff)
15611 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
15613 /* The granularity of the value (bits or bytes). */
15614 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \
15615 UINT32_C(0x10000000)
15616 /* Value is in bits. */
15617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
15618 (UINT32_C(0x0) << 28)
15619 /* Value is in bytes. */
15620 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
15621 (UINT32_C(0x1) << 28)
15622 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
15623 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
15624 /* bw_value_unit is 3 b */
15625 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
15626 UINT32_C(0xe0000000)
15627 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
15629 /* Value is in Mb or MB (base 10). */
15630 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
15631 (UINT32_C(0x0) << 29)
15632 /* Value is in Kb or KB (base 10). */
15633 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
15634 (UINT32_C(0x2) << 29)
15635 /* Value is in bits or bytes. */
15636 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
15637 (UINT32_C(0x4) << 29)
15638 /* Value is in Gb or GB (base 10). */
15639 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
15640 (UINT32_C(0x6) << 29)
15641 /* Value is in 1/100th of a percentage of total bandwidth. */
15642 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15643 (UINT32_C(0x1) << 29)
15645 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
15646 (UINT32_C(0x7) << 29)
15647 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
15648 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
15649 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15650 uint8_t queue_id5_tsa_assign;
15651 /* Strict Priority */
15652 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \
15654 /* Enhanced Transmission Selection */
15655 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
15658 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
15661 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
15664 * Priority level for strict priority. Valid only when the
15665 * tsa_assign is 0 - Strict Priority (SP)
15666 * 0..7 - Valid values.
15667 * 8..255 - Reserved.
15669 uint8_t queue_id5_pri_lvl;
15671 * Weight used to allocate remaining BW for this COS after
15672 * servicing guaranteed bandwidths for all COS.
15674 uint8_t queue_id5_bw_weight;
15675 /* ID of CoS Queue 6. */
15678 * Minimum BW allocated to CoS Queue.
15679 * The HWRM will translate this value into byte counter and
15680 * time interval used for this COS inside the device.
15682 uint32_t queue_id6_min_bw;
15683 /* The bandwidth value. */
15684 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
15685 UINT32_C(0xfffffff)
15686 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
15688 /* The granularity of the value (bits or bytes). */
15689 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \
15690 UINT32_C(0x10000000)
15691 /* Value is in bits. */
15692 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
15693 (UINT32_C(0x0) << 28)
15694 /* Value is in bytes. */
15695 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
15696 (UINT32_C(0x1) << 28)
15697 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
15698 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
15699 /* bw_value_unit is 3 b */
15700 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
15701 UINT32_C(0xe0000000)
15702 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
15704 /* Value is in Mb or MB (base 10). */
15705 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
15706 (UINT32_C(0x0) << 29)
15707 /* Value is in Kb or KB (base 10). */
15708 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
15709 (UINT32_C(0x2) << 29)
15710 /* Value is in bits or bytes. */
15711 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
15712 (UINT32_C(0x4) << 29)
15713 /* Value is in Gb or GB (base 10). */
15714 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
15715 (UINT32_C(0x6) << 29)
15716 /* Value is in 1/100th of a percentage of total bandwidth. */
15717 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15718 (UINT32_C(0x1) << 29)
15720 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
15721 (UINT32_C(0x7) << 29)
15722 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
15723 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
15725 * Maximum BW allocated to CoS queue.
15726 * The HWRM will translate this value into byte counter and
15727 * time interval used for this COS inside the device.
15729 uint32_t queue_id6_max_bw;
15730 /* The bandwidth value. */
15731 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
15732 UINT32_C(0xfffffff)
15733 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
15735 /* The granularity of the value (bits or bytes). */
15736 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \
15737 UINT32_C(0x10000000)
15738 /* Value is in bits. */
15739 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
15740 (UINT32_C(0x0) << 28)
15741 /* Value is in bytes. */
15742 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
15743 (UINT32_C(0x1) << 28)
15744 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
15745 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
15746 /* bw_value_unit is 3 b */
15747 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
15748 UINT32_C(0xe0000000)
15749 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
15751 /* Value is in Mb or MB (base 10). */
15752 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
15753 (UINT32_C(0x0) << 29)
15754 /* Value is in Kb or KB (base 10). */
15755 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
15756 (UINT32_C(0x2) << 29)
15757 /* Value is in bits or bytes. */
15758 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
15759 (UINT32_C(0x4) << 29)
15760 /* Value is in Gb or GB (base 10). */
15761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
15762 (UINT32_C(0x6) << 29)
15763 /* Value is in 1/100th of a percentage of total bandwidth. */
15764 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15765 (UINT32_C(0x1) << 29)
15767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
15768 (UINT32_C(0x7) << 29)
15769 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
15770 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
15771 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15772 uint8_t queue_id6_tsa_assign;
15773 /* Strict Priority */
15774 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \
15776 /* Enhanced Transmission Selection */
15777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
15780 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
15783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
15786 * Priority level for strict priority. Valid only when the
15787 * tsa_assign is 0 - Strict Priority (SP)
15788 * 0..7 - Valid values.
15789 * 8..255 - Reserved.
15791 uint8_t queue_id6_pri_lvl;
15793 * Weight used to allocate remaining BW for this COS after
15794 * servicing guaranteed bandwidths for all COS.
15796 uint8_t queue_id6_bw_weight;
15797 /* ID of CoS Queue 7. */
15800 * Minimum BW allocated to CoS Queue.
15801 * The HWRM will translate this value into byte counter and
15802 * time interval used for this COS inside the device.
15804 uint32_t queue_id7_min_bw;
15805 /* The bandwidth value. */
15806 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
15807 UINT32_C(0xfffffff)
15808 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
15810 /* The granularity of the value (bits or bytes). */
15811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \
15812 UINT32_C(0x10000000)
15813 /* Value is in bits. */
15814 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
15815 (UINT32_C(0x0) << 28)
15816 /* Value is in bytes. */
15817 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
15818 (UINT32_C(0x1) << 28)
15819 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
15820 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
15821 /* bw_value_unit is 3 b */
15822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
15823 UINT32_C(0xe0000000)
15824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
15826 /* Value is in Mb or MB (base 10). */
15827 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
15828 (UINT32_C(0x0) << 29)
15829 /* Value is in Kb or KB (base 10). */
15830 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
15831 (UINT32_C(0x2) << 29)
15832 /* Value is in bits or bytes. */
15833 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
15834 (UINT32_C(0x4) << 29)
15835 /* Value is in Gb or GB (base 10). */
15836 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
15837 (UINT32_C(0x6) << 29)
15838 /* Value is in 1/100th of a percentage of total bandwidth. */
15839 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
15840 (UINT32_C(0x1) << 29)
15842 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
15843 (UINT32_C(0x7) << 29)
15844 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
15845 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
15847 * Maximum BW allocated to CoS queue.
15848 * The HWRM will translate this value into byte counter and
15849 * time interval used for this COS inside the device.
15851 uint32_t queue_id7_max_bw;
15852 /* The bandwidth value. */
15853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
15854 UINT32_C(0xfffffff)
15855 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
15857 /* The granularity of the value (bits or bytes). */
15858 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \
15859 UINT32_C(0x10000000)
15860 /* Value is in bits. */
15861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
15862 (UINT32_C(0x0) << 28)
15863 /* Value is in bytes. */
15864 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
15865 (UINT32_C(0x1) << 28)
15866 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
15867 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
15868 /* bw_value_unit is 3 b */
15869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
15870 UINT32_C(0xe0000000)
15871 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
15873 /* Value is in Mb or MB (base 10). */
15874 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
15875 (UINT32_C(0x0) << 29)
15876 /* Value is in Kb or KB (base 10). */
15877 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
15878 (UINT32_C(0x2) << 29)
15879 /* Value is in bits or bytes. */
15880 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
15881 (UINT32_C(0x4) << 29)
15882 /* Value is in Gb or GB (base 10). */
15883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
15884 (UINT32_C(0x6) << 29)
15885 /* Value is in 1/100th of a percentage of total bandwidth. */
15886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
15887 (UINT32_C(0x1) << 29)
15889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
15890 (UINT32_C(0x7) << 29)
15891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
15892 HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
15893 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
15894 uint8_t queue_id7_tsa_assign;
15895 /* Strict Priority */
15896 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \
15898 /* Enhanced Transmission Selection */
15899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
15902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
15905 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
15908 * Priority level for strict priority. Valid only when the
15909 * tsa_assign is 0 - Strict Priority (SP)
15910 * 0..7 - Valid values.
15911 * 8..255 - Reserved.
15913 uint8_t queue_id7_pri_lvl;
15915 * Weight used to allocate remaining BW for this COS after
15916 * servicing guaranteed bandwidths for all COS.
15918 uint8_t queue_id7_bw_weight;
15919 uint8_t unused_2[4];
15921 * This field is used in Output records to indicate that the output
15922 * is completely written to RAM. This field should be read as '1'
15923 * to indicate that the output has been completely written.
15924 * When writing a command completion or response to an internal processor,
15925 * the order of writes has to be such that this field is written last.
15928 } __attribute__((packed));
15930 /*************************
15931 * hwrm_queue_cos2bw_cfg *
15932 *************************/
15935 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */
15936 struct hwrm_queue_cos2bw_cfg_input {
15937 /* The HWRM command request type. */
15940 * The completion ring to send the completion event on. This should
15941 * be the NQ ID returned from the `nq_alloc` HWRM command.
15943 uint16_t cmpl_ring;
15945 * The sequence ID is used by the driver for tracking multiple
15946 * commands. This ID is treated as opaque data by the firmware and
15947 * the value is returned in the `hwrm_resp_hdr` upon completion.
15951 * The target ID of the command:
15952 * * 0x0-0xFFF8 - The function ID
15953 * * 0xFFF8-0xFFFE - Reserved for internal processors
15956 uint16_t target_id;
15958 * A physical address pointer pointing to a host buffer that the
15959 * command's response data will be written. This can be either a host
15960 * physical address (HPA) or a guest physical address (GPA) and must
15961 * point to a physically contiguous block of memory.
15963 uint64_t resp_addr;
15967 * If this bit is set to 1, then all queue_id0 related
15968 * parameters in this command are valid.
15970 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \
15973 * If this bit is set to 1, then all queue_id1 related
15974 * parameters in this command are valid.
15976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \
15979 * If this bit is set to 1, then all queue_id2 related
15980 * parameters in this command are valid.
15982 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \
15985 * If this bit is set to 1, then all queue_id3 related
15986 * parameters in this command are valid.
15988 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \
15991 * If this bit is set to 1, then all queue_id4 related
15992 * parameters in this command are valid.
15994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \
15997 * If this bit is set to 1, then all queue_id5 related
15998 * parameters in this command are valid.
16000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \
16003 * If this bit is set to 1, then all queue_id6 related
16004 * parameters in this command are valid.
16006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \
16009 * If this bit is set to 1, then all queue_id7 related
16010 * parameters in this command are valid.
16012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \
16015 * Port ID of port for which the table is being configured.
16016 * The HWRM needs to check whether this function is allowed
16017 * to configure TC BW assignment on this port.
16020 /* ID of CoS Queue 0. */
16024 * Minimum BW allocated to CoS Queue.
16025 * The HWRM will translate this value into byte counter and
16026 * time interval used for this COS inside the device.
16028 uint32_t queue_id0_min_bw;
16029 /* The bandwidth value. */
16030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \
16031 UINT32_C(0xfffffff)
16032 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \
16034 /* The granularity of the value (bits or bytes). */
16035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \
16036 UINT32_C(0x10000000)
16037 /* Value is in bits. */
16038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \
16039 (UINT32_C(0x0) << 28)
16040 /* Value is in bytes. */
16041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \
16042 (UINT32_C(0x1) << 28)
16043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \
16044 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
16045 /* bw_value_unit is 3 b */
16046 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \
16047 UINT32_C(0xe0000000)
16048 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \
16050 /* Value is in Mb or MB (base 10). */
16051 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \
16052 (UINT32_C(0x0) << 29)
16053 /* Value is in Kb or KB (base 10). */
16054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \
16055 (UINT32_C(0x2) << 29)
16056 /* Value is in bits or bytes. */
16057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \
16058 (UINT32_C(0x4) << 29)
16059 /* Value is in Gb or GB (base 10). */
16060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \
16061 (UINT32_C(0x6) << 29)
16062 /* Value is in 1/100th of a percentage of total bandwidth. */
16063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16064 (UINT32_C(0x1) << 29)
16066 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \
16067 (UINT32_C(0x7) << 29)
16068 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \
16069 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
16071 * Maximum BW allocated to CoS Queue.
16072 * The HWRM will translate this value into byte counter and
16073 * time interval used for this COS inside the device.
16075 uint32_t queue_id0_max_bw;
16076 /* The bandwidth value. */
16077 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \
16078 UINT32_C(0xfffffff)
16079 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \
16081 /* The granularity of the value (bits or bytes). */
16082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \
16083 UINT32_C(0x10000000)
16084 /* Value is in bits. */
16085 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \
16086 (UINT32_C(0x0) << 28)
16087 /* Value is in bytes. */
16088 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \
16089 (UINT32_C(0x1) << 28)
16090 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \
16091 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
16092 /* bw_value_unit is 3 b */
16093 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \
16094 UINT32_C(0xe0000000)
16095 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \
16097 /* Value is in Mb or MB (base 10). */
16098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \
16099 (UINT32_C(0x0) << 29)
16100 /* Value is in Kb or KB (base 10). */
16101 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \
16102 (UINT32_C(0x2) << 29)
16103 /* Value is in bits or bytes. */
16104 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \
16105 (UINT32_C(0x4) << 29)
16106 /* Value is in Gb or GB (base 10). */
16107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \
16108 (UINT32_C(0x6) << 29)
16109 /* Value is in 1/100th of a percentage of total bandwidth. */
16110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16111 (UINT32_C(0x1) << 29)
16113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \
16114 (UINT32_C(0x7) << 29)
16115 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \
16116 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
16117 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16118 uint8_t queue_id0_tsa_assign;
16119 /* Strict Priority */
16120 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \
16122 /* Enhanced Transmission Selection */
16123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \
16126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \
16129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \
16132 * Priority level for strict priority. Valid only when the
16133 * tsa_assign is 0 - Strict Priority (SP)
16134 * 0..7 - Valid values.
16135 * 8..255 - Reserved.
16137 uint8_t queue_id0_pri_lvl;
16139 * Weight used to allocate remaining BW for this COS after
16140 * servicing guaranteed bandwidths for all COS.
16142 uint8_t queue_id0_bw_weight;
16143 /* ID of CoS Queue 1. */
16146 * Minimum BW allocated to CoS Queue.
16147 * The HWRM will translate this value into byte counter and
16148 * time interval used for this COS inside the device.
16150 uint32_t queue_id1_min_bw;
16151 /* The bandwidth value. */
16152 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \
16153 UINT32_C(0xfffffff)
16154 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \
16156 /* The granularity of the value (bits or bytes). */
16157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \
16158 UINT32_C(0x10000000)
16159 /* Value is in bits. */
16160 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \
16161 (UINT32_C(0x0) << 28)
16162 /* Value is in bytes. */
16163 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \
16164 (UINT32_C(0x1) << 28)
16165 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \
16166 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
16167 /* bw_value_unit is 3 b */
16168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \
16169 UINT32_C(0xe0000000)
16170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \
16172 /* Value is in Mb or MB (base 10). */
16173 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \
16174 (UINT32_C(0x0) << 29)
16175 /* Value is in Kb or KB (base 10). */
16176 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \
16177 (UINT32_C(0x2) << 29)
16178 /* Value is in bits or bytes. */
16179 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \
16180 (UINT32_C(0x4) << 29)
16181 /* Value is in Gb or GB (base 10). */
16182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \
16183 (UINT32_C(0x6) << 29)
16184 /* Value is in 1/100th of a percentage of total bandwidth. */
16185 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16186 (UINT32_C(0x1) << 29)
16188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \
16189 (UINT32_C(0x7) << 29)
16190 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \
16191 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
16193 * Maximum BW allocated to CoS queue.
16194 * The HWRM will translate this value into byte counter and
16195 * time interval used for this COS inside the device.
16197 uint32_t queue_id1_max_bw;
16198 /* The bandwidth value. */
16199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \
16200 UINT32_C(0xfffffff)
16201 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \
16203 /* The granularity of the value (bits or bytes). */
16204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \
16205 UINT32_C(0x10000000)
16206 /* Value is in bits. */
16207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \
16208 (UINT32_C(0x0) << 28)
16209 /* Value is in bytes. */
16210 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \
16211 (UINT32_C(0x1) << 28)
16212 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \
16213 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
16214 /* bw_value_unit is 3 b */
16215 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \
16216 UINT32_C(0xe0000000)
16217 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \
16219 /* Value is in Mb or MB (base 10). */
16220 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \
16221 (UINT32_C(0x0) << 29)
16222 /* Value is in Kb or KB (base 10). */
16223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \
16224 (UINT32_C(0x2) << 29)
16225 /* Value is in bits or bytes. */
16226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \
16227 (UINT32_C(0x4) << 29)
16228 /* Value is in Gb or GB (base 10). */
16229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \
16230 (UINT32_C(0x6) << 29)
16231 /* Value is in 1/100th of a percentage of total bandwidth. */
16232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16233 (UINT32_C(0x1) << 29)
16235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \
16236 (UINT32_C(0x7) << 29)
16237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \
16238 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
16239 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16240 uint8_t queue_id1_tsa_assign;
16241 /* Strict Priority */
16242 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \
16244 /* Enhanced Transmission Selection */
16245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \
16248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \
16251 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \
16254 * Priority level for strict priority. Valid only when the
16255 * tsa_assign is 0 - Strict Priority (SP)
16256 * 0..7 - Valid values.
16257 * 8..255 - Reserved.
16259 uint8_t queue_id1_pri_lvl;
16261 * Weight used to allocate remaining BW for this COS after
16262 * servicing guaranteed bandwidths for all COS.
16264 uint8_t queue_id1_bw_weight;
16265 /* ID of CoS Queue 2. */
16268 * Minimum BW allocated to CoS Queue.
16269 * The HWRM will translate this value into byte counter and
16270 * time interval used for this COS inside the device.
16272 uint32_t queue_id2_min_bw;
16273 /* The bandwidth value. */
16274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \
16275 UINT32_C(0xfffffff)
16276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \
16278 /* The granularity of the value (bits or bytes). */
16279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \
16280 UINT32_C(0x10000000)
16281 /* Value is in bits. */
16282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \
16283 (UINT32_C(0x0) << 28)
16284 /* Value is in bytes. */
16285 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \
16286 (UINT32_C(0x1) << 28)
16287 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \
16288 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
16289 /* bw_value_unit is 3 b */
16290 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \
16291 UINT32_C(0xe0000000)
16292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \
16294 /* Value is in Mb or MB (base 10). */
16295 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \
16296 (UINT32_C(0x0) << 29)
16297 /* Value is in Kb or KB (base 10). */
16298 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \
16299 (UINT32_C(0x2) << 29)
16300 /* Value is in bits or bytes. */
16301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \
16302 (UINT32_C(0x4) << 29)
16303 /* Value is in Gb or GB (base 10). */
16304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \
16305 (UINT32_C(0x6) << 29)
16306 /* Value is in 1/100th of a percentage of total bandwidth. */
16307 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16308 (UINT32_C(0x1) << 29)
16310 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \
16311 (UINT32_C(0x7) << 29)
16312 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \
16313 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
16315 * Maximum BW allocated to CoS queue.
16316 * The HWRM will translate this value into byte counter and
16317 * time interval used for this COS inside the device.
16319 uint32_t queue_id2_max_bw;
16320 /* The bandwidth value. */
16321 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \
16322 UINT32_C(0xfffffff)
16323 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \
16325 /* The granularity of the value (bits or bytes). */
16326 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \
16327 UINT32_C(0x10000000)
16328 /* Value is in bits. */
16329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \
16330 (UINT32_C(0x0) << 28)
16331 /* Value is in bytes. */
16332 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \
16333 (UINT32_C(0x1) << 28)
16334 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \
16335 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
16336 /* bw_value_unit is 3 b */
16337 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \
16338 UINT32_C(0xe0000000)
16339 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \
16341 /* Value is in Mb or MB (base 10). */
16342 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \
16343 (UINT32_C(0x0) << 29)
16344 /* Value is in Kb or KB (base 10). */
16345 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \
16346 (UINT32_C(0x2) << 29)
16347 /* Value is in bits or bytes. */
16348 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \
16349 (UINT32_C(0x4) << 29)
16350 /* Value is in Gb or GB (base 10). */
16351 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \
16352 (UINT32_C(0x6) << 29)
16353 /* Value is in 1/100th of a percentage of total bandwidth. */
16354 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16355 (UINT32_C(0x1) << 29)
16357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \
16358 (UINT32_C(0x7) << 29)
16359 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \
16360 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
16361 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16362 uint8_t queue_id2_tsa_assign;
16363 /* Strict Priority */
16364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \
16366 /* Enhanced Transmission Selection */
16367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \
16370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \
16373 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \
16376 * Priority level for strict priority. Valid only when the
16377 * tsa_assign is 0 - Strict Priority (SP)
16378 * 0..7 - Valid values.
16379 * 8..255 - Reserved.
16381 uint8_t queue_id2_pri_lvl;
16383 * Weight used to allocate remaining BW for this COS after
16384 * servicing guaranteed bandwidths for all COS.
16386 uint8_t queue_id2_bw_weight;
16387 /* ID of CoS Queue 3. */
16390 * Minimum BW allocated to CoS Queue.
16391 * The HWRM will translate this value into byte counter and
16392 * time interval used for this COS inside the device.
16394 uint32_t queue_id3_min_bw;
16395 /* The bandwidth value. */
16396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \
16397 UINT32_C(0xfffffff)
16398 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \
16400 /* The granularity of the value (bits or bytes). */
16401 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \
16402 UINT32_C(0x10000000)
16403 /* Value is in bits. */
16404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \
16405 (UINT32_C(0x0) << 28)
16406 /* Value is in bytes. */
16407 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \
16408 (UINT32_C(0x1) << 28)
16409 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \
16410 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
16411 /* bw_value_unit is 3 b */
16412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \
16413 UINT32_C(0xe0000000)
16414 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \
16416 /* Value is in Mb or MB (base 10). */
16417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \
16418 (UINT32_C(0x0) << 29)
16419 /* Value is in Kb or KB (base 10). */
16420 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \
16421 (UINT32_C(0x2) << 29)
16422 /* Value is in bits or bytes. */
16423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \
16424 (UINT32_C(0x4) << 29)
16425 /* Value is in Gb or GB (base 10). */
16426 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \
16427 (UINT32_C(0x6) << 29)
16428 /* Value is in 1/100th of a percentage of total bandwidth. */
16429 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16430 (UINT32_C(0x1) << 29)
16432 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \
16433 (UINT32_C(0x7) << 29)
16434 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \
16435 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
16437 * Maximum BW allocated to CoS queue.
16438 * The HWRM will translate this value into byte counter and
16439 * time interval used for this COS inside the device.
16441 uint32_t queue_id3_max_bw;
16442 /* The bandwidth value. */
16443 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \
16444 UINT32_C(0xfffffff)
16445 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \
16447 /* The granularity of the value (bits or bytes). */
16448 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \
16449 UINT32_C(0x10000000)
16450 /* Value is in bits. */
16451 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \
16452 (UINT32_C(0x0) << 28)
16453 /* Value is in bytes. */
16454 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \
16455 (UINT32_C(0x1) << 28)
16456 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \
16457 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
16458 /* bw_value_unit is 3 b */
16459 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \
16460 UINT32_C(0xe0000000)
16461 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \
16463 /* Value is in Mb or MB (base 10). */
16464 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \
16465 (UINT32_C(0x0) << 29)
16466 /* Value is in Kb or KB (base 10). */
16467 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \
16468 (UINT32_C(0x2) << 29)
16469 /* Value is in bits or bytes. */
16470 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \
16471 (UINT32_C(0x4) << 29)
16472 /* Value is in Gb or GB (base 10). */
16473 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \
16474 (UINT32_C(0x6) << 29)
16475 /* Value is in 1/100th of a percentage of total bandwidth. */
16476 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16477 (UINT32_C(0x1) << 29)
16479 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \
16480 (UINT32_C(0x7) << 29)
16481 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \
16482 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
16483 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16484 uint8_t queue_id3_tsa_assign;
16485 /* Strict Priority */
16486 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \
16488 /* Enhanced Transmission Selection */
16489 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \
16492 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \
16495 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \
16498 * Priority level for strict priority. Valid only when the
16499 * tsa_assign is 0 - Strict Priority (SP)
16500 * 0..7 - Valid values.
16501 * 8..255 - Reserved.
16503 uint8_t queue_id3_pri_lvl;
16505 * Weight used to allocate remaining BW for this COS after
16506 * servicing guaranteed bandwidths for all COS.
16508 uint8_t queue_id3_bw_weight;
16509 /* ID of CoS Queue 4. */
16512 * Minimum BW allocated to CoS Queue.
16513 * The HWRM will translate this value into byte counter and
16514 * time interval used for this COS inside the device.
16516 uint32_t queue_id4_min_bw;
16517 /* The bandwidth value. */
16518 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \
16519 UINT32_C(0xfffffff)
16520 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \
16522 /* The granularity of the value (bits or bytes). */
16523 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \
16524 UINT32_C(0x10000000)
16525 /* Value is in bits. */
16526 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \
16527 (UINT32_C(0x0) << 28)
16528 /* Value is in bytes. */
16529 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \
16530 (UINT32_C(0x1) << 28)
16531 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \
16532 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
16533 /* bw_value_unit is 3 b */
16534 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \
16535 UINT32_C(0xe0000000)
16536 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \
16538 /* Value is in Mb or MB (base 10). */
16539 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \
16540 (UINT32_C(0x0) << 29)
16541 /* Value is in Kb or KB (base 10). */
16542 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \
16543 (UINT32_C(0x2) << 29)
16544 /* Value is in bits or bytes. */
16545 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \
16546 (UINT32_C(0x4) << 29)
16547 /* Value is in Gb or GB (base 10). */
16548 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \
16549 (UINT32_C(0x6) << 29)
16550 /* Value is in 1/100th of a percentage of total bandwidth. */
16551 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16552 (UINT32_C(0x1) << 29)
16554 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \
16555 (UINT32_C(0x7) << 29)
16556 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \
16557 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
16559 * Maximum BW allocated to CoS queue.
16560 * The HWRM will translate this value into byte counter and
16561 * time interval used for this COS inside the device.
16563 uint32_t queue_id4_max_bw;
16564 /* The bandwidth value. */
16565 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \
16566 UINT32_C(0xfffffff)
16567 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \
16569 /* The granularity of the value (bits or bytes). */
16570 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \
16571 UINT32_C(0x10000000)
16572 /* Value is in bits. */
16573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \
16574 (UINT32_C(0x0) << 28)
16575 /* Value is in bytes. */
16576 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \
16577 (UINT32_C(0x1) << 28)
16578 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \
16579 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
16580 /* bw_value_unit is 3 b */
16581 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \
16582 UINT32_C(0xe0000000)
16583 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \
16585 /* Value is in Mb or MB (base 10). */
16586 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \
16587 (UINT32_C(0x0) << 29)
16588 /* Value is in Kb or KB (base 10). */
16589 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \
16590 (UINT32_C(0x2) << 29)
16591 /* Value is in bits or bytes. */
16592 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \
16593 (UINT32_C(0x4) << 29)
16594 /* Value is in Gb or GB (base 10). */
16595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \
16596 (UINT32_C(0x6) << 29)
16597 /* Value is in 1/100th of a percentage of total bandwidth. */
16598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16599 (UINT32_C(0x1) << 29)
16601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \
16602 (UINT32_C(0x7) << 29)
16603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \
16604 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
16605 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16606 uint8_t queue_id4_tsa_assign;
16607 /* Strict Priority */
16608 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \
16610 /* Enhanced Transmission Selection */
16611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \
16614 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \
16617 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \
16620 * Priority level for strict priority. Valid only when the
16621 * tsa_assign is 0 - Strict Priority (SP)
16622 * 0..7 - Valid values.
16623 * 8..255 - Reserved.
16625 uint8_t queue_id4_pri_lvl;
16627 * Weight used to allocate remaining BW for this COS after
16628 * servicing guaranteed bandwidths for all COS.
16630 uint8_t queue_id4_bw_weight;
16631 /* ID of CoS Queue 5. */
16634 * Minimum BW allocated to CoS Queue.
16635 * The HWRM will translate this value into byte counter and
16636 * time interval used for this COS inside the device.
16638 uint32_t queue_id5_min_bw;
16639 /* The bandwidth value. */
16640 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \
16641 UINT32_C(0xfffffff)
16642 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \
16644 /* The granularity of the value (bits or bytes). */
16645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \
16646 UINT32_C(0x10000000)
16647 /* Value is in bits. */
16648 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \
16649 (UINT32_C(0x0) << 28)
16650 /* Value is in bytes. */
16651 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \
16652 (UINT32_C(0x1) << 28)
16653 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \
16654 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
16655 /* bw_value_unit is 3 b */
16656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \
16657 UINT32_C(0xe0000000)
16658 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \
16660 /* Value is in Mb or MB (base 10). */
16661 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \
16662 (UINT32_C(0x0) << 29)
16663 /* Value is in Kb or KB (base 10). */
16664 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \
16665 (UINT32_C(0x2) << 29)
16666 /* Value is in bits or bytes. */
16667 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \
16668 (UINT32_C(0x4) << 29)
16669 /* Value is in Gb or GB (base 10). */
16670 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \
16671 (UINT32_C(0x6) << 29)
16672 /* Value is in 1/100th of a percentage of total bandwidth. */
16673 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16674 (UINT32_C(0x1) << 29)
16676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \
16677 (UINT32_C(0x7) << 29)
16678 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \
16679 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
16681 * Maximum BW allocated to CoS queue.
16682 * The HWRM will translate this value into byte counter and
16683 * time interval used for this COS inside the device.
16685 uint32_t queue_id5_max_bw;
16686 /* The bandwidth value. */
16687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \
16688 UINT32_C(0xfffffff)
16689 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \
16691 /* The granularity of the value (bits or bytes). */
16692 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \
16693 UINT32_C(0x10000000)
16694 /* Value is in bits. */
16695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \
16696 (UINT32_C(0x0) << 28)
16697 /* Value is in bytes. */
16698 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \
16699 (UINT32_C(0x1) << 28)
16700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \
16701 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
16702 /* bw_value_unit is 3 b */
16703 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \
16704 UINT32_C(0xe0000000)
16705 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \
16707 /* Value is in Mb or MB (base 10). */
16708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \
16709 (UINT32_C(0x0) << 29)
16710 /* Value is in Kb or KB (base 10). */
16711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \
16712 (UINT32_C(0x2) << 29)
16713 /* Value is in bits or bytes. */
16714 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \
16715 (UINT32_C(0x4) << 29)
16716 /* Value is in Gb or GB (base 10). */
16717 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \
16718 (UINT32_C(0x6) << 29)
16719 /* Value is in 1/100th of a percentage of total bandwidth. */
16720 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16721 (UINT32_C(0x1) << 29)
16723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \
16724 (UINT32_C(0x7) << 29)
16725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \
16726 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
16727 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16728 uint8_t queue_id5_tsa_assign;
16729 /* Strict Priority */
16730 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \
16732 /* Enhanced Transmission Selection */
16733 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \
16736 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \
16739 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \
16742 * Priority level for strict priority. Valid only when the
16743 * tsa_assign is 0 - Strict Priority (SP)
16744 * 0..7 - Valid values.
16745 * 8..255 - Reserved.
16747 uint8_t queue_id5_pri_lvl;
16749 * Weight used to allocate remaining BW for this COS after
16750 * servicing guaranteed bandwidths for all COS.
16752 uint8_t queue_id5_bw_weight;
16753 /* ID of CoS Queue 6. */
16756 * Minimum BW allocated to CoS Queue.
16757 * The HWRM will translate this value into byte counter and
16758 * time interval used for this COS inside the device.
16760 uint32_t queue_id6_min_bw;
16761 /* The bandwidth value. */
16762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \
16763 UINT32_C(0xfffffff)
16764 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \
16766 /* The granularity of the value (bits or bytes). */
16767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \
16768 UINT32_C(0x10000000)
16769 /* Value is in bits. */
16770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \
16771 (UINT32_C(0x0) << 28)
16772 /* Value is in bytes. */
16773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \
16774 (UINT32_C(0x1) << 28)
16775 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \
16776 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
16777 /* bw_value_unit is 3 b */
16778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \
16779 UINT32_C(0xe0000000)
16780 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \
16782 /* Value is in Mb or MB (base 10). */
16783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \
16784 (UINT32_C(0x0) << 29)
16785 /* Value is in Kb or KB (base 10). */
16786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \
16787 (UINT32_C(0x2) << 29)
16788 /* Value is in bits or bytes. */
16789 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \
16790 (UINT32_C(0x4) << 29)
16791 /* Value is in Gb or GB (base 10). */
16792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \
16793 (UINT32_C(0x6) << 29)
16794 /* Value is in 1/100th of a percentage of total bandwidth. */
16795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16796 (UINT32_C(0x1) << 29)
16798 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \
16799 (UINT32_C(0x7) << 29)
16800 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \
16801 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
16803 * Maximum BW allocated to CoS queue.
16804 * The HWRM will translate this value into byte counter and
16805 * time interval used for this COS inside the device.
16807 uint32_t queue_id6_max_bw;
16808 /* The bandwidth value. */
16809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \
16810 UINT32_C(0xfffffff)
16811 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \
16813 /* The granularity of the value (bits or bytes). */
16814 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \
16815 UINT32_C(0x10000000)
16816 /* Value is in bits. */
16817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \
16818 (UINT32_C(0x0) << 28)
16819 /* Value is in bytes. */
16820 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \
16821 (UINT32_C(0x1) << 28)
16822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \
16823 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
16824 /* bw_value_unit is 3 b */
16825 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \
16826 UINT32_C(0xe0000000)
16827 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \
16829 /* Value is in Mb or MB (base 10). */
16830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \
16831 (UINT32_C(0x0) << 29)
16832 /* Value is in Kb or KB (base 10). */
16833 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \
16834 (UINT32_C(0x2) << 29)
16835 /* Value is in bits or bytes. */
16836 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \
16837 (UINT32_C(0x4) << 29)
16838 /* Value is in Gb or GB (base 10). */
16839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \
16840 (UINT32_C(0x6) << 29)
16841 /* Value is in 1/100th of a percentage of total bandwidth. */
16842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16843 (UINT32_C(0x1) << 29)
16845 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \
16846 (UINT32_C(0x7) << 29)
16847 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \
16848 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
16849 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16850 uint8_t queue_id6_tsa_assign;
16851 /* Strict Priority */
16852 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \
16854 /* Enhanced Transmission Selection */
16855 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \
16858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \
16861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \
16864 * Priority level for strict priority. Valid only when the
16865 * tsa_assign is 0 - Strict Priority (SP)
16866 * 0..7 - Valid values.
16867 * 8..255 - Reserved.
16869 uint8_t queue_id6_pri_lvl;
16871 * Weight used to allocate remaining BW for this COS after
16872 * servicing guaranteed bandwidths for all COS.
16874 uint8_t queue_id6_bw_weight;
16875 /* ID of CoS Queue 7. */
16878 * Minimum BW allocated to CoS Queue.
16879 * The HWRM will translate this value into byte counter and
16880 * time interval used for this COS inside the device.
16882 uint32_t queue_id7_min_bw;
16883 /* The bandwidth value. */
16884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \
16885 UINT32_C(0xfffffff)
16886 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \
16888 /* The granularity of the value (bits or bytes). */
16889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \
16890 UINT32_C(0x10000000)
16891 /* Value is in bits. */
16892 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \
16893 (UINT32_C(0x0) << 28)
16894 /* Value is in bytes. */
16895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \
16896 (UINT32_C(0x1) << 28)
16897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \
16898 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
16899 /* bw_value_unit is 3 b */
16900 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \
16901 UINT32_C(0xe0000000)
16902 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \
16904 /* Value is in Mb or MB (base 10). */
16905 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \
16906 (UINT32_C(0x0) << 29)
16907 /* Value is in Kb or KB (base 10). */
16908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \
16909 (UINT32_C(0x2) << 29)
16910 /* Value is in bits or bytes. */
16911 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \
16912 (UINT32_C(0x4) << 29)
16913 /* Value is in Gb or GB (base 10). */
16914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \
16915 (UINT32_C(0x6) << 29)
16916 /* Value is in 1/100th of a percentage of total bandwidth. */
16917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \
16918 (UINT32_C(0x1) << 29)
16920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \
16921 (UINT32_C(0x7) << 29)
16922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \
16923 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
16925 * Maximum BW allocated to CoS queue.
16926 * The HWRM will translate this value into byte counter and
16927 * time interval used for this COS inside the device.
16929 uint32_t queue_id7_max_bw;
16930 /* The bandwidth value. */
16931 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \
16932 UINT32_C(0xfffffff)
16933 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \
16935 /* The granularity of the value (bits or bytes). */
16936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \
16937 UINT32_C(0x10000000)
16938 /* Value is in bits. */
16939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \
16940 (UINT32_C(0x0) << 28)
16941 /* Value is in bytes. */
16942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \
16943 (UINT32_C(0x1) << 28)
16944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \
16945 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
16946 /* bw_value_unit is 3 b */
16947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \
16948 UINT32_C(0xe0000000)
16949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \
16951 /* Value is in Mb or MB (base 10). */
16952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \
16953 (UINT32_C(0x0) << 29)
16954 /* Value is in Kb or KB (base 10). */
16955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \
16956 (UINT32_C(0x2) << 29)
16957 /* Value is in bits or bytes. */
16958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \
16959 (UINT32_C(0x4) << 29)
16960 /* Value is in Gb or GB (base 10). */
16961 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \
16962 (UINT32_C(0x6) << 29)
16963 /* Value is in 1/100th of a percentage of total bandwidth. */
16964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
16965 (UINT32_C(0x1) << 29)
16967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \
16968 (UINT32_C(0x7) << 29)
16969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \
16970 HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
16971 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
16972 uint8_t queue_id7_tsa_assign;
16973 /* Strict Priority */
16974 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \
16976 /* Enhanced Transmission Selection */
16977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \
16980 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \
16983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \
16986 * Priority level for strict priority. Valid only when the
16987 * tsa_assign is 0 - Strict Priority (SP)
16988 * 0..7 - Valid values.
16989 * 8..255 - Reserved.
16991 uint8_t queue_id7_pri_lvl;
16993 * Weight used to allocate remaining BW for this COS after
16994 * servicing guaranteed bandwidths for all COS.
16996 uint8_t queue_id7_bw_weight;
16997 uint8_t unused_1[5];
16998 } __attribute__((packed));
17000 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */
17001 struct hwrm_queue_cos2bw_cfg_output {
17002 /* The specific error status for the command. */
17003 uint16_t error_code;
17004 /* The HWRM command request type. */
17006 /* The sequence ID from the original command. */
17008 /* The length of the response data in number of bytes. */
17010 uint8_t unused_0[7];
17012 * This field is used in Output records to indicate that the output
17013 * is completely written to RAM. This field should be read as '1'
17014 * to indicate that the output has been completely written.
17015 * When writing a command completion or response to an internal processor,
17016 * the order of writes has to be such that this field is written last.
17019 } __attribute__((packed));
17021 /*************************
17022 * hwrm_queue_dscp_qcaps *
17023 *************************/
17026 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */
17027 struct hwrm_queue_dscp_qcaps_input {
17028 /* The HWRM command request type. */
17031 * The completion ring to send the completion event on. This should
17032 * be the NQ ID returned from the `nq_alloc` HWRM command.
17034 uint16_t cmpl_ring;
17036 * The sequence ID is used by the driver for tracking multiple
17037 * commands. This ID is treated as opaque data by the firmware and
17038 * the value is returned in the `hwrm_resp_hdr` upon completion.
17042 * The target ID of the command:
17043 * * 0x0-0xFFF8 - The function ID
17044 * * 0xFFF8-0xFFFE - Reserved for internal processors
17047 uint16_t target_id;
17049 * A physical address pointer pointing to a host buffer that the
17050 * command's response data will be written. This can be either a host
17051 * physical address (HPA) or a guest physical address (GPA) and must
17052 * point to a physically contiguous block of memory.
17054 uint64_t resp_addr;
17056 * Port ID of port for which the table is being configured.
17057 * The HWRM needs to check whether this function is allowed
17058 * to configure pri2cos mapping on this port.
17061 uint8_t unused_0[7];
17062 } __attribute__((packed));
17064 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */
17065 struct hwrm_queue_dscp_qcaps_output {
17066 /* The specific error status for the command. */
17067 uint16_t error_code;
17068 /* The HWRM command request type. */
17070 /* The sequence ID from the original command. */
17072 /* The length of the response data in number of bytes. */
17074 /* The number of bits provided by the hardware for the DSCP value. */
17075 uint8_t num_dscp_bits;
17077 /* Max number of DSCP-MASK-PRI entries supported. */
17078 uint16_t max_entries;
17079 uint8_t unused_1[3];
17081 * This field is used in Output records to indicate that the output
17082 * is completely written to RAM. This field should be read as '1'
17083 * to indicate that the output has been completely written.
17084 * When writing a command completion or response to an internal processor,
17085 * the order of writes has to be such that this field is written last.
17088 } __attribute__((packed));
17090 /****************************
17091 * hwrm_queue_dscp2pri_qcfg *
17092 ****************************/
17095 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */
17096 struct hwrm_queue_dscp2pri_qcfg_input {
17097 /* The HWRM command request type. */
17100 * The completion ring to send the completion event on. This should
17101 * be the NQ ID returned from the `nq_alloc` HWRM command.
17103 uint16_t cmpl_ring;
17105 * The sequence ID is used by the driver for tracking multiple
17106 * commands. This ID is treated as opaque data by the firmware and
17107 * the value is returned in the `hwrm_resp_hdr` upon completion.
17111 * The target ID of the command:
17112 * * 0x0-0xFFF8 - The function ID
17113 * * 0xFFF8-0xFFFE - Reserved for internal processors
17116 uint16_t target_id;
17118 * A physical address pointer pointing to a host buffer that the
17119 * command's response data will be written. This can be either a host
17120 * physical address (HPA) or a guest physical address (GPA) and must
17121 * point to a physically contiguous block of memory.
17123 uint64_t resp_addr;
17125 * This is the host address where the 24-bits DSCP-MASK-PRI
17126 * tuple(s) will be copied to.
17128 uint64_t dest_data_addr;
17130 * Port ID of port for which the table is being configured.
17131 * The HWRM needs to check whether this function is allowed
17132 * to configure pri2cos mapping on this port.
17136 /* Size of the buffer pointed to by dest_data_addr. */
17137 uint16_t dest_data_buffer_size;
17138 uint8_t unused_1[4];
17139 } __attribute__((packed));
17141 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */
17142 struct hwrm_queue_dscp2pri_qcfg_output {
17143 /* The specific error status for the command. */
17144 uint16_t error_code;
17145 /* The HWRM command request type. */
17147 /* The sequence ID from the original command. */
17149 /* The length of the response data in number of bytes. */
17152 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to
17153 * by the dest_data_addr.
17155 uint16_t entry_cnt;
17157 * This is the default PRI which un-initialized DSCP values are
17160 uint8_t default_pri;
17161 uint8_t unused_0[4];
17163 * This field is used in Output records to indicate that the output
17164 * is completely written to RAM. This field should be read as '1'
17165 * to indicate that the output has been completely written.
17166 * When writing a command completion or response to an internal processor,
17167 * the order of writes has to be such that this field is written last.
17170 } __attribute__((packed));
17172 /***************************
17173 * hwrm_queue_dscp2pri_cfg *
17174 ***************************/
17177 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */
17178 struct hwrm_queue_dscp2pri_cfg_input {
17179 /* The HWRM command request type. */
17182 * The completion ring to send the completion event on. This should
17183 * be the NQ ID returned from the `nq_alloc` HWRM command.
17185 uint16_t cmpl_ring;
17187 * The sequence ID is used by the driver for tracking multiple
17188 * commands. This ID is treated as opaque data by the firmware and
17189 * the value is returned in the `hwrm_resp_hdr` upon completion.
17193 * The target ID of the command:
17194 * * 0x0-0xFFF8 - The function ID
17195 * * 0xFFF8-0xFFFE - Reserved for internal processors
17198 uint16_t target_id;
17200 * A physical address pointer pointing to a host buffer that the
17201 * command's response data will be written. This can be either a host
17202 * physical address (HPA) or a guest physical address (GPA) and must
17203 * point to a physically contiguous block of memory.
17205 uint64_t resp_addr;
17207 * This is the host address where the 24-bits DSCP-MASK-PRI tuple
17208 * will be copied from.
17210 uint64_t src_data_addr;
17212 /* use_hw_default_pri is 1 b */
17213 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \
17217 * This bit must be '1' for the default_pri field to be
17220 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \
17223 * Port ID of port for which the table is being configured.
17224 * The HWRM needs to check whether this function is allowed
17225 * to configure pri2cos mapping on this port.
17229 * This is the default PRI which un-initialized DSCP values will be
17232 uint8_t default_pri;
17234 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
17235 * to by src_data_addr.
17237 uint16_t entry_cnt;
17238 uint8_t unused_0[4];
17239 } __attribute__((packed));
17241 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */
17242 struct hwrm_queue_dscp2pri_cfg_output {
17243 /* The specific error status for the command. */
17244 uint16_t error_code;
17245 /* The HWRM command request type. */
17247 /* The sequence ID from the original command. */
17249 /* The length of the response data in number of bytes. */
17251 uint8_t unused_0[7];
17253 * This field is used in Output records to indicate that the output
17254 * is completely written to RAM. This field should be read as '1'
17255 * to indicate that the output has been completely written.
17256 * When writing a command completion or response to an internal processor,
17257 * the order of writes has to be such that this field is written last.
17260 } __attribute__((packed));
17262 /*******************
17263 * hwrm_vnic_alloc *
17264 *******************/
17267 /* hwrm_vnic_alloc_input (size:192b/24B) */
17268 struct hwrm_vnic_alloc_input {
17269 /* The HWRM command request type. */
17272 * The completion ring to send the completion event on. This should
17273 * be the NQ ID returned from the `nq_alloc` HWRM command.
17275 uint16_t cmpl_ring;
17277 * The sequence ID is used by the driver for tracking multiple
17278 * commands. This ID is treated as opaque data by the firmware and
17279 * the value is returned in the `hwrm_resp_hdr` upon completion.
17283 * The target ID of the command:
17284 * * 0x0-0xFFF8 - The function ID
17285 * * 0xFFF8-0xFFFE - Reserved for internal processors
17288 uint16_t target_id;
17290 * A physical address pointer pointing to a host buffer that the
17291 * command's response data will be written. This can be either a host
17292 * physical address (HPA) or a guest physical address (GPA) and must
17293 * point to a physically contiguous block of memory.
17295 uint64_t resp_addr;
17298 * When this bit is '1', this VNIC is requested to
17299 * be the default VNIC for this function.
17301 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
17302 uint8_t unused_0[4];
17303 } __attribute__((packed));
17305 /* hwrm_vnic_alloc_output (size:128b/16B) */
17306 struct hwrm_vnic_alloc_output {
17307 /* The specific error status for the command. */
17308 uint16_t error_code;
17309 /* The HWRM command request type. */
17311 /* The sequence ID from the original command. */
17313 /* The length of the response data in number of bytes. */
17315 /* Logical vnic ID */
17317 uint8_t unused_0[3];
17319 * This field is used in Output records to indicate that the output
17320 * is completely written to RAM. This field should be read as '1'
17321 * to indicate that the output has been completely written.
17322 * When writing a command completion or response to an internal processor,
17323 * the order of writes has to be such that this field is written last.
17326 } __attribute__((packed));
17328 /******************
17330 ******************/
17333 /* hwrm_vnic_free_input (size:192b/24B) */
17334 struct hwrm_vnic_free_input {
17335 /* The HWRM command request type. */
17338 * The completion ring to send the completion event on. This should
17339 * be the NQ ID returned from the `nq_alloc` HWRM command.
17341 uint16_t cmpl_ring;
17343 * The sequence ID is used by the driver for tracking multiple
17344 * commands. This ID is treated as opaque data by the firmware and
17345 * the value is returned in the `hwrm_resp_hdr` upon completion.
17349 * The target ID of the command:
17350 * * 0x0-0xFFF8 - The function ID
17351 * * 0xFFF8-0xFFFE - Reserved for internal processors
17354 uint16_t target_id;
17356 * A physical address pointer pointing to a host buffer that the
17357 * command's response data will be written. This can be either a host
17358 * physical address (HPA) or a guest physical address (GPA) and must
17359 * point to a physically contiguous block of memory.
17361 uint64_t resp_addr;
17362 /* Logical vnic ID */
17364 uint8_t unused_0[4];
17365 } __attribute__((packed));
17367 /* hwrm_vnic_free_output (size:128b/16B) */
17368 struct hwrm_vnic_free_output {
17369 /* The specific error status for the command. */
17370 uint16_t error_code;
17371 /* The HWRM command request type. */
17373 /* The sequence ID from the original command. */
17375 /* The length of the response data in number of bytes. */
17377 uint8_t unused_0[7];
17379 * This field is used in Output records to indicate that the output
17380 * is completely written to RAM. This field should be read as '1'
17381 * to indicate that the output has been completely written.
17382 * When writing a command completion or response to an internal processor,
17383 * the order of writes has to be such that this field is written last.
17386 } __attribute__((packed));
17393 /* hwrm_vnic_cfg_input (size:320b/40B) */
17394 struct hwrm_vnic_cfg_input {
17395 /* The HWRM command request type. */
17398 * The completion ring to send the completion event on. This should
17399 * be the NQ ID returned from the `nq_alloc` HWRM command.
17401 uint16_t cmpl_ring;
17403 * The sequence ID is used by the driver for tracking multiple
17404 * commands. This ID is treated as opaque data by the firmware and
17405 * the value is returned in the `hwrm_resp_hdr` upon completion.
17409 * The target ID of the command:
17410 * * 0x0-0xFFF8 - The function ID
17411 * * 0xFFF8-0xFFFE - Reserved for internal processors
17414 uint16_t target_id;
17416 * A physical address pointer pointing to a host buffer that the
17417 * command's response data will be written. This can be either a host
17418 * physical address (HPA) or a guest physical address (GPA) and must
17419 * point to a physically contiguous block of memory.
17421 uint64_t resp_addr;
17424 * When this bit is '1', the VNIC is requested to
17425 * be the default VNIC for the function.
17427 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \
17430 * When this bit is '1', the VNIC is being configured to
17431 * strip VLAN in the RX path.
17432 * If set to '0', then VLAN stripping is disabled on
17435 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \
17438 * When this bit is '1', the VNIC is being configured to
17439 * buffer receive packets in the hardware until the host
17440 * posts new receive buffers.
17441 * If set to '0', then bd_stall is being configured to be
17442 * disabled on this VNIC.
17444 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \
17447 * When this bit is '1', the VNIC is being configured to
17448 * receive both RoCE and non-RoCE traffic.
17449 * If set to '0', then this VNIC is not configured to be
17450 * operating in dual VNIC mode.
17452 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
17455 * When this flag is set to '1', the VNIC is requested to
17456 * be configured to receive only RoCE traffic.
17457 * If this flag is set to '0', then this flag shall be
17458 * ignored by the HWRM.
17459 * If roce_dual_vnic_mode flag is set to '1'
17460 * or roce_mirroring_capable_vnic_mode flag to 1,
17461 * then the HWRM client shall not set this flag to '1'.
17463 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
17466 * When a VNIC uses one destination ring group for certain
17467 * application (e.g. Receive Flow Steering) where
17468 * exact match is used to direct packets to a VNIC with one
17469 * destination ring group only, there is no need to configure
17470 * RSS indirection table for that VNIC as only one destination
17471 * ring group is used.
17473 * This flag is used to enable a mode where
17474 * RSS is enabled in the VNIC using a RSS context
17475 * for computing RSS hash but the RSS indirection table is
17476 * not configured using hwrm_vnic_rss_cfg.
17478 * If this mode is enabled, then the driver should not program
17479 * RSS indirection table for the RSS context that is used for
17480 * computing RSS hash only.
17482 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \
17485 * When this bit is '1', the VNIC is being configured to
17486 * receive both RoCE and non-RoCE traffic, but forward only the
17487 * RoCE traffic further. Also, RoCE traffic can be mirrored to
17490 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
17494 * This bit must be '1' for the dflt_ring_grp field to be
17497 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \
17500 * This bit must be '1' for the rss_rule field to be
17503 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \
17506 * This bit must be '1' for the cos_rule field to be
17509 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \
17512 * This bit must be '1' for the lb_rule field to be
17515 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \
17518 * This bit must be '1' for the mru field to be
17521 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \
17524 * This bit must be '1' for the default_rx_ring_id field to be
17527 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \
17530 * This bit must be '1' for the default_cmpl_ring_id field to be
17533 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \
17535 /* Logical vnic ID */
17538 * Default Completion ring for the VNIC. This ring will
17539 * be chosen if packet does not match any RSS rules and if
17540 * there is no COS rule.
17542 uint16_t dflt_ring_grp;
17544 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
17545 * there is no RSS rule.
17549 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
17550 * there is no COS rule.
17554 * RSS ID for load balancing rule/table structure.
17555 * 0xFF... (All Fs) if there is no LB rule.
17559 * The maximum receive unit of the vnic.
17560 * Each vnic is associated with a function.
17561 * The vnic mru value overwrites the mru setting of the
17562 * associated function.
17563 * The HWRM shall make sure that vnic mru does not exceed
17564 * the mru of the port the function is associated with.
17568 * Default Rx ring for the VNIC. This ring will
17569 * be chosen if packet does not match any RSS rules.
17570 * The aggregation ring associated with the Rx ring is
17571 * implied based on the Rx ring specified when the
17572 * aggregation ring was allocated.
17574 uint16_t default_rx_ring_id;
17576 * Default completion ring for the VNIC. This ring will
17577 * be chosen if packet does not match any RSS rules.
17579 uint16_t default_cmpl_ring_id;
17580 } __attribute__((packed));
17582 /* hwrm_vnic_cfg_output (size:128b/16B) */
17583 struct hwrm_vnic_cfg_output {
17584 /* The specific error status for the command. */
17585 uint16_t error_code;
17586 /* The HWRM command request type. */
17588 /* The sequence ID from the original command. */
17590 /* The length of the response data in number of bytes. */
17592 uint8_t unused_0[7];
17594 * This field is used in Output records to indicate that the output
17595 * is completely written to RAM. This field should be read as '1'
17596 * to indicate that the output has been completely written.
17597 * When writing a command completion or response to an internal processor,
17598 * the order of writes has to be such that this field is written last.
17601 } __attribute__((packed));
17603 /******************
17605 ******************/
17608 /* hwrm_vnic_qcfg_input (size:256b/32B) */
17609 struct hwrm_vnic_qcfg_input {
17610 /* The HWRM command request type. */
17613 * The completion ring to send the completion event on. This should
17614 * be the NQ ID returned from the `nq_alloc` HWRM command.
17616 uint16_t cmpl_ring;
17618 * The sequence ID is used by the driver for tracking multiple
17619 * commands. This ID is treated as opaque data by the firmware and
17620 * the value is returned in the `hwrm_resp_hdr` upon completion.
17624 * The target ID of the command:
17625 * * 0x0-0xFFF8 - The function ID
17626 * * 0xFFF8-0xFFFE - Reserved for internal processors
17629 uint16_t target_id;
17631 * A physical address pointer pointing to a host buffer that the
17632 * command's response data will be written. This can be either a host
17633 * physical address (HPA) or a guest physical address (GPA) and must
17634 * point to a physically contiguous block of memory.
17636 uint64_t resp_addr;
17639 * This bit must be '1' for the vf_id_valid field to be
17642 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
17643 /* Logical vnic ID */
17645 /* ID of Virtual Function whose VNIC resource is being queried. */
17647 uint8_t unused_0[6];
17648 } __attribute__((packed));
17650 /* hwrm_vnic_qcfg_output (size:256b/32B) */
17651 struct hwrm_vnic_qcfg_output {
17652 /* The specific error status for the command. */
17653 uint16_t error_code;
17654 /* The HWRM command request type. */
17656 /* The sequence ID from the original command. */
17658 /* The length of the response data in number of bytes. */
17660 /* Default Completion ring for the VNIC. */
17661 uint16_t dflt_ring_grp;
17663 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
17664 * there is no RSS rule.
17668 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
17669 * there is no COS rule.
17673 * RSS ID for load balancing rule/table structure.
17674 * 0xFF... (All Fs) if there is no LB rule.
17677 /* The maximum receive unit of the vnic. */
17679 uint8_t unused_0[2];
17682 * When this bit is '1', the VNIC is the default VNIC for
17685 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \
17688 * When this bit is '1', the VNIC is configured to
17689 * strip VLAN in the RX path.
17690 * If set to '0', then VLAN stripping is disabled on
17693 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \
17696 * When this bit is '1', the VNIC is configured to
17697 * buffer receive packets in the hardware until the host
17698 * posts new receive buffers.
17699 * If set to '0', then bd_stall is disabled on
17702 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \
17705 * When this bit is '1', the VNIC is configured to
17706 * receive both RoCE and non-RoCE traffic.
17707 * If set to '0', then this VNIC is not configured to
17708 * operate in dual VNIC mode.
17710 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \
17713 * When this flag is set to '1', the VNIC is configured to
17714 * receive only RoCE traffic.
17715 * When this flag is set to '0', the VNIC is not configured
17716 * to receive only RoCE traffic.
17717 * If roce_dual_vnic_mode flag and this flag both are set
17718 * to '1', then it is an invalid configuration of the
17719 * VNIC. The HWRM should not allow that type of
17720 * mis-configuration by HWRM clients.
17722 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \
17725 * When a VNIC uses one destination ring group for certain
17726 * application (e.g. Receive Flow Steering) where
17727 * exact match is used to direct packets to a VNIC with one
17728 * destination ring group only, there is no need to configure
17729 * RSS indirection table for that VNIC as only one destination
17730 * ring group is used.
17732 * When this bit is set to '1', then the VNIC is enabled in a
17733 * mode where RSS is enabled in the VNIC using a RSS context
17734 * for computing RSS hash but the RSS indirection table is
17737 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \
17740 * When this bit is '1', the VNIC is configured to
17741 * receive both RoCE and non-RoCE traffic, but forward only
17742 * RoCE traffic further. Also RoCE traffic can be mirrored to
17745 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \
17747 uint8_t unused_1[7];
17749 * This field is used in Output records to indicate that the output
17750 * is completely written to RAM. This field should be read as '1'
17751 * to indicate that the output has been completely written.
17752 * When writing a command completion or response to an internal processor,
17753 * the order of writes has to be such that this field is written last.
17756 } __attribute__((packed));
17758 /*******************
17759 * hwrm_vnic_qcaps *
17760 *******************/
17763 /* hwrm_vnic_qcaps_input (size:192b/24B) */
17764 struct hwrm_vnic_qcaps_input {
17765 /* The HWRM command request type. */
17768 * The completion ring to send the completion event on. This should
17769 * be the NQ ID returned from the `nq_alloc` HWRM command.
17771 uint16_t cmpl_ring;
17773 * The sequence ID is used by the driver for tracking multiple
17774 * commands. This ID is treated as opaque data by the firmware and
17775 * the value is returned in the `hwrm_resp_hdr` upon completion.
17779 * The target ID of the command:
17780 * * 0x0-0xFFF8 - The function ID
17781 * * 0xFFF8-0xFFFE - Reserved for internal processors
17784 uint16_t target_id;
17786 * A physical address pointer pointing to a host buffer that the
17787 * command's response data will be written. This can be either a host
17788 * physical address (HPA) or a guest physical address (GPA) and must
17789 * point to a physically contiguous block of memory.
17791 uint64_t resp_addr;
17793 uint8_t unused_0[4];
17794 } __attribute__((packed));
17796 /* hwrm_vnic_qcaps_output (size:192b/24B) */
17797 struct hwrm_vnic_qcaps_output {
17798 /* The specific error status for the command. */
17799 uint16_t error_code;
17800 /* The HWRM command request type. */
17802 /* The sequence ID from the original command. */
17804 /* The length of the response data in number of bytes. */
17806 /* The maximum receive unit that is settable on a vnic. */
17808 uint8_t unused_0[2];
17811 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \
17814 * When this bit is '1', the capability of stripping VLAN in
17815 * the RX path is supported on VNIC(s).
17816 * If set to '0', then VLAN stripping capability is
17817 * not supported on VNIC(s).
17819 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \
17822 * When this bit is '1', the capability to buffer receive
17823 * packets in the hardware until the host posts new receive buffers
17824 * is supported on VNIC(s).
17825 * If set to '0', then bd_stall capability is not supported
17828 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \
17831 * When this bit is '1', the capability to
17832 * receive both RoCE and non-RoCE traffic on VNIC(s) is
17834 * If set to '0', then the capability to receive
17835 * both RoCE and non-RoCE traffic on VNIC(s) is
17838 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \
17841 * When this bit is set to '1', the capability to configure
17842 * a VNIC to receive only RoCE traffic is supported.
17843 * When this flag is set to '0', the VNIC capability to
17844 * configure to receive only RoCE traffic is not supported.
17846 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \
17849 * When this bit is set to '1', then the capability to enable
17850 * a VNIC in a mode where RSS context without configuring
17851 * RSS indirection table is supported (for RSS hash computation).
17852 * When this bit is set to '0', then a VNIC can not be configured
17853 * with a mode to enable RSS context without configuring RSS
17854 * indirection table.
17856 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \
17859 * When this bit is '1', the capability to
17860 * mirror the the RoCE traffic is supported.
17861 * If set to '0', then the capability to mirror the
17862 * RoCE traffic is not supported.
17864 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \
17867 * When this bit is '1', the outermost RSS hashing capability
17868 * is supported. If set to '0', then the outermost RSS hashing
17869 * capability is not supported.
17871 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
17873 uint8_t unused_1[7];
17875 * This field is used in Output records to indicate that the output
17876 * is completely written to RAM. This field should be read as '1'
17877 * to indicate that the output has been completely written.
17878 * When writing a command completion or response to an internal processor,
17879 * the order of writes has to be such that this field is written last.
17882 } __attribute__((packed));
17884 /*********************
17885 * hwrm_vnic_tpa_cfg *
17886 *********************/
17889 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */
17890 struct hwrm_vnic_tpa_cfg_input {
17891 /* The HWRM command request type. */
17894 * The completion ring to send the completion event on. This should
17895 * be the NQ ID returned from the `nq_alloc` HWRM command.
17897 uint16_t cmpl_ring;
17899 * The sequence ID is used by the driver for tracking multiple
17900 * commands. This ID is treated as opaque data by the firmware and
17901 * the value is returned in the `hwrm_resp_hdr` upon completion.
17905 * The target ID of the command:
17906 * * 0x0-0xFFF8 - The function ID
17907 * * 0xFFF8-0xFFFE - Reserved for internal processors
17910 uint16_t target_id;
17912 * A physical address pointer pointing to a host buffer that the
17913 * command's response data will be written. This can be either a host
17914 * physical address (HPA) or a guest physical address (GPA) and must
17915 * point to a physically contiguous block of memory.
17917 uint64_t resp_addr;
17920 * When this bit is '1', the VNIC shall be configured to
17921 * perform transparent packet aggregation (TPA) of
17922 * non-tunneled TCP packets.
17924 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \
17927 * When this bit is '1', the VNIC shall be configured to
17928 * perform transparent packet aggregation (TPA) of
17929 * tunneled TCP packets.
17931 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \
17934 * When this bit is '1', the VNIC shall be configured to
17935 * perform transparent packet aggregation (TPA) according
17936 * to Windows Receive Segment Coalescing (RSC) rules.
17938 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \
17941 * When this bit is '1', the VNIC shall be configured to
17942 * perform transparent packet aggregation (TPA) according
17943 * to Linux Generic Receive Offload (GRO) rules.
17945 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \
17948 * When this bit is '1', the VNIC shall be configured to
17949 * perform transparent packet aggregation (TPA) for TCP
17950 * packets with IP ECN set to non-zero.
17952 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \
17955 * When this bit is '1', the VNIC shall be configured to
17956 * perform transparent packet aggregation (TPA) for
17957 * GRE tunneled TCP packets only if all packets have the
17958 * same GRE sequence.
17960 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
17963 * When this bit is '1' and the GRO mode is enabled,
17964 * the VNIC shall be configured to
17965 * perform transparent packet aggregation (TPA) for
17966 * TCP/IPv4 packets with consecutively increasing IPIDs.
17967 * In other words, the last packet that is being
17968 * aggregated to an already existing aggregation context
17969 * shall have IPID 1 more than the IPID of the last packet
17970 * that was aggregated in that aggregation context.
17972 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \
17975 * When this bit is '1' and the GRO mode is enabled,
17976 * the VNIC shall be configured to
17977 * perform transparent packet aggregation (TPA) for
17978 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
17981 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
17985 * This bit must be '1' for the max_agg_segs field to be
17988 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
17990 * This bit must be '1' for the max_aggs field to be
17993 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
17995 * This bit must be '1' for the max_agg_timer field to be
17998 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
18000 * This bit must be '1' for the min_agg_len field to be
18003 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
18004 /* Logical vnic ID */
18007 * This is the maximum number of TCP segments that can
18008 * be aggregated (unit is Log2). Max value is 31.
18010 uint16_t max_agg_segs;
18012 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
18014 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
18016 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
18018 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
18019 /* Any segment size larger than this is not valid */
18020 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
18021 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \
18022 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
18024 * This is the maximum number of aggregations this VNIC is
18025 * allowed (unit is Log2). Max value is 7
18028 /* 1 aggregation */
18029 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
18030 /* 2 aggregations */
18031 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
18032 /* 4 aggregations */
18033 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
18034 /* 8 aggregations */
18035 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
18036 /* 16 aggregations */
18037 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
18038 /* Any aggregation size larger than this is not valid */
18039 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
18040 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \
18041 HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX
18042 uint8_t unused_0[2];
18044 * This is the maximum amount of time allowed for
18045 * an aggregation context to complete after it was initiated.
18047 uint32_t max_agg_timer;
18049 * This is the minimum amount of payload length required to
18050 * start an aggregation context.
18052 uint32_t min_agg_len;
18053 } __attribute__((packed));
18055 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */
18056 struct hwrm_vnic_tpa_cfg_output {
18057 /* The specific error status for the command. */
18058 uint16_t error_code;
18059 /* The HWRM command request type. */
18061 /* The sequence ID from the original command. */
18063 /* The length of the response data in number of bytes. */
18065 uint8_t unused_0[7];
18067 * This field is used in Output records to indicate that the output
18068 * is completely written to RAM. This field should be read as '1'
18069 * to indicate that the output has been completely written.
18070 * When writing a command completion or response to an internal processor,
18071 * the order of writes has to be such that this field is written last.
18074 } __attribute__((packed));
18076 /**********************
18077 * hwrm_vnic_tpa_qcfg *
18078 **********************/
18081 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */
18082 struct hwrm_vnic_tpa_qcfg_input {
18083 /* The HWRM command request type. */
18086 * The completion ring to send the completion event on. This should
18087 * be the NQ ID returned from the `nq_alloc` HWRM command.
18089 uint16_t cmpl_ring;
18091 * The sequence ID is used by the driver for tracking multiple
18092 * commands. This ID is treated as opaque data by the firmware and
18093 * the value is returned in the `hwrm_resp_hdr` upon completion.
18097 * The target ID of the command:
18098 * * 0x0-0xFFF8 - The function ID
18099 * * 0xFFF8-0xFFFE - Reserved for internal processors
18102 uint16_t target_id;
18104 * A physical address pointer pointing to a host buffer that the
18105 * command's response data will be written. This can be either a host
18106 * physical address (HPA) or a guest physical address (GPA) and must
18107 * point to a physically contiguous block of memory.
18109 uint64_t resp_addr;
18110 /* Logical vnic ID */
18112 uint8_t unused_0[6];
18113 } __attribute__((packed));
18115 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */
18116 struct hwrm_vnic_tpa_qcfg_output {
18117 /* The specific error status for the command. */
18118 uint16_t error_code;
18119 /* The HWRM command request type. */
18121 /* The sequence ID from the original command. */
18123 /* The length of the response data in number of bytes. */
18127 * When this bit is '1', the VNIC is configured to
18128 * perform transparent packet aggregation (TPA) of
18129 * non-tunneled TCP packets.
18131 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \
18134 * When this bit is '1', the VNIC is configured to
18135 * perform transparent packet aggregation (TPA) of
18136 * tunneled TCP packets.
18138 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \
18141 * When this bit is '1', the VNIC is configured to
18142 * perform transparent packet aggregation (TPA) according
18143 * to Windows Receive Segment Coalescing (RSC) rules.
18145 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \
18148 * When this bit is '1', the VNIC is configured to
18149 * perform transparent packet aggregation (TPA) according
18150 * to Linux Generic Receive Offload (GRO) rules.
18152 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \
18155 * When this bit is '1', the VNIC is configured to
18156 * perform transparent packet aggregation (TPA) for TCP
18157 * packets with IP ECN set to non-zero.
18159 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \
18162 * When this bit is '1', the VNIC is configured to
18163 * perform transparent packet aggregation (TPA) for
18164 * GRE tunneled TCP packets only if all packets have the
18165 * same GRE sequence.
18167 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \
18170 * When this bit is '1' and the GRO mode is enabled,
18171 * the VNIC is configured to
18172 * perform transparent packet aggregation (TPA) for
18173 * TCP/IPv4 packets with consecutively increasing IPIDs.
18174 * In other words, the last packet that is being
18175 * aggregated to an already existing aggregation context
18176 * shall have IPID 1 more than the IPID of the last packet
18177 * that was aggregated in that aggregation context.
18179 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \
18182 * When this bit is '1' and the GRO mode is enabled,
18183 * the VNIC is configured to
18184 * perform transparent packet aggregation (TPA) for
18185 * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)
18188 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \
18191 * This is the maximum number of TCP segments that can
18192 * be aggregated (unit is Log2). Max value is 31.
18194 uint16_t max_agg_segs;
18196 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
18198 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
18200 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
18202 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
18203 /* Any segment size larger than this is not valid */
18204 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
18205 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \
18206 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX
18208 * This is the maximum number of aggregations this VNIC is
18209 * allowed (unit is Log2). Max value is 7
18212 /* 1 aggregation */
18213 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
18214 /* 2 aggregations */
18215 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
18216 /* 4 aggregations */
18217 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
18218 /* 8 aggregations */
18219 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
18220 /* 16 aggregations */
18221 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
18222 /* Any aggregation size larger than this is not valid */
18223 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
18224 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \
18225 HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX
18227 * This is the maximum amount of time allowed for
18228 * an aggregation context to complete after it was initiated.
18230 uint32_t max_agg_timer;
18232 * This is the minimum amount of payload length required to
18233 * start an aggregation context.
18235 uint32_t min_agg_len;
18236 uint8_t unused_0[7];
18238 * This field is used in Output records to indicate that the output
18239 * is completely written to RAM. This field should be read as '1'
18240 * to indicate that the output has been completely written.
18241 * When writing a command completion or response to an internal processor,
18242 * the order of writes has to be such that this field is written last.
18245 } __attribute__((packed));
18247 /*********************
18248 * hwrm_vnic_rss_cfg *
18249 *********************/
18252 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */
18253 struct hwrm_vnic_rss_cfg_input {
18254 /* The HWRM command request type. */
18257 * The completion ring to send the completion event on. This should
18258 * be the NQ ID returned from the `nq_alloc` HWRM command.
18260 uint16_t cmpl_ring;
18262 * The sequence ID is used by the driver for tracking multiple
18263 * commands. This ID is treated as opaque data by the firmware and
18264 * the value is returned in the `hwrm_resp_hdr` upon completion.
18268 * The target ID of the command:
18269 * * 0x0-0xFFF8 - The function ID
18270 * * 0xFFF8-0xFFFE - Reserved for internal processors
18273 uint16_t target_id;
18275 * A physical address pointer pointing to a host buffer that the
18276 * command's response data will be written. This can be either a host
18277 * physical address (HPA) or a guest physical address (GPA) and must
18278 * point to a physically contiguous block of memory.
18280 uint64_t resp_addr;
18281 uint32_t hash_type;
18283 * When this bit is '1', the RSS hash shall be computed
18284 * over source and destination IPv4 addresses of IPv4
18287 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18289 * When this bit is '1', the RSS hash shall be computed
18290 * over source/destination IPv4 addresses and
18291 * source/destination ports of TCP/IPv4 packets.
18293 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18295 * When this bit is '1', the RSS hash shall be computed
18296 * over source/destination IPv4 addresses and
18297 * source/destination ports of UDP/IPv4 packets.
18299 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18301 * When this bit is '1', the RSS hash shall be computed
18302 * over source and destination IPv4 addresses of IPv6
18305 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18307 * When this bit is '1', the RSS hash shall be computed
18308 * over source/destination IPv6 addresses and
18309 * source/destination ports of TCP/IPv6 packets.
18311 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18313 * When this bit is '1', the RSS hash shall be computed
18314 * over source/destination IPv6 addresses and
18315 * source/destination ports of UDP/IPv6 packets.
18317 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18318 /* VNIC ID of VNIC associated with RSS table being configured. */
18321 * Specifies which VNIC ring table pair to configure.
18322 * Valid values range from 0 to 7.
18324 uint8_t ring_table_pair_index;
18325 /* Flags to specify different RSS hash modes. */
18326 uint8_t hash_mode_flags;
18328 * When this bit is '1', it indicates using current RSS
18329 * hash mode setting configured in the device.
18331 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \
18334 * When this bit is '1', it indicates requesting support of
18335 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18336 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18337 * packets, the RSS hash is computed over the normal
18338 * src/dest l3 and src/dest l4 headers.
18340 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18343 * When this bit is '1', it indicates requesting support of
18344 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18345 * tunnel packets. For none-tunnel packets, the RSS hash is
18346 * computed over the normal src/dest l3 headers.
18348 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18351 * When this bit is '1', it indicates requesting support of
18352 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18353 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18354 * packets, the RSS hash is computed over the normal
18355 * src/dest l3 and src/dest l4 headers.
18357 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18360 * When this bit is '1', it indicates requesting support of
18361 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18362 * tunnel packets. For none-tunnel packets, the RSS hash is
18363 * computed over the normal src/dest l3 headers.
18365 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18367 /* This is the address for rss ring group table */
18368 uint64_t ring_grp_tbl_addr;
18369 /* This is the address for rss hash key table */
18370 uint64_t hash_key_tbl_addr;
18371 /* Index to the rss indirection table. */
18372 uint16_t rss_ctx_idx;
18373 uint8_t unused_1[6];
18374 } __attribute__((packed));
18376 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */
18377 struct hwrm_vnic_rss_cfg_output {
18378 /* The specific error status for the command. */
18379 uint16_t error_code;
18380 /* The HWRM command request type. */
18382 /* The sequence ID from the original command. */
18384 /* The length of the response data in number of bytes. */
18386 uint8_t unused_0[7];
18388 * This field is used in Output records to indicate that the output
18389 * is completely written to RAM. This field should be read as '1'
18390 * to indicate that the output has been completely written.
18391 * When writing a command completion or response to an internal processor,
18392 * the order of writes has to be such that this field is written last.
18395 } __attribute__((packed));
18397 /**********************
18398 * hwrm_vnic_rss_qcfg *
18399 **********************/
18402 /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */
18403 struct hwrm_vnic_rss_qcfg_input {
18404 /* The HWRM command request type. */
18407 * The completion ring to send the completion event on. This should
18408 * be the NQ ID returned from the `nq_alloc` HWRM command.
18410 uint16_t cmpl_ring;
18412 * The sequence ID is used by the driver for tracking multiple
18413 * commands. This ID is treated as opaque data by the firmware and
18414 * the value is returned in the `hwrm_resp_hdr` upon completion.
18418 * The target ID of the command:
18419 * * 0x0-0xFFF8 - The function ID
18420 * * 0xFFF8-0xFFFE - Reserved for internal processors
18423 uint16_t target_id;
18425 * A physical address pointer pointing to a host buffer that the
18426 * command's response data will be written. This can be either a host
18427 * physical address (HPA) or a guest physical address (GPA) and must
18428 * point to a physically contiguous block of memory.
18430 uint64_t resp_addr;
18431 /* Index to the rss indirection table. */
18432 uint16_t rss_ctx_idx;
18433 uint8_t unused_0[6];
18434 } __attribute__((packed));
18436 /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */
18437 struct hwrm_vnic_rss_qcfg_output {
18438 /* The specific error status for the command. */
18439 uint16_t error_code;
18440 /* The HWRM command request type. */
18442 /* The sequence ID from the original command. */
18444 /* The length of the response data in number of bytes. */
18446 uint32_t hash_type;
18448 * When this bit is '1', the RSS hash shall be computed
18449 * over source and destination IPv4 addresses of IPv4
18452 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
18454 * When this bit is '1', the RSS hash shall be computed
18455 * over source/destination IPv4 addresses and
18456 * source/destination ports of TCP/IPv4 packets.
18458 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
18460 * When this bit is '1', the RSS hash shall be computed
18461 * over source/destination IPv4 addresses and
18462 * source/destination ports of UDP/IPv4 packets.
18464 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
18466 * When this bit is '1', the RSS hash shall be computed
18467 * over source and destination IPv4 addresses of IPv6
18470 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
18472 * When this bit is '1', the RSS hash shall be computed
18473 * over source/destination IPv6 addresses and
18474 * source/destination ports of TCP/IPv6 packets.
18476 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
18478 * When this bit is '1', the RSS hash shall be computed
18479 * over source/destination IPv6 addresses and
18480 * source/destination ports of UDP/IPv6 packets.
18482 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
18483 uint8_t unused_0[4];
18484 /* This is the value of rss hash key */
18485 uint32_t hash_key[10];
18486 /* Flags to specify different RSS hash modes. */
18487 uint8_t hash_mode_flags;
18489 * When this bit is '1', it indicates using current RSS
18490 * hash mode setting configured in the device.
18492 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \
18495 * When this bit is '1', it indicates requesting support of
18496 * RSS hashing over innermost 4 tuples {l3.src, l3.dest,
18497 * l4.src, l4.dest} for tunnel packets. For none-tunnel
18498 * packets, the RSS hash is computed over the normal
18499 * src/dest l3 and src/dest l4 headers.
18501 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \
18504 * When this bit is '1', it indicates requesting support of
18505 * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for
18506 * tunnel packets. For none-tunnel packets, the RSS hash is
18507 * computed over the normal src/dest l3 headers.
18509 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \
18512 * When this bit is '1', it indicates requesting support of
18513 * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,
18514 * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel
18515 * packets, the RSS hash is computed over the normal
18516 * src/dest l3 and src/dest l4 headers.
18518 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \
18521 * When this bit is '1', it indicates requesting support of
18522 * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for
18523 * tunnel packets. For none-tunnel packets, the RSS hash is
18524 * computed over the normal src/dest l3 headers.
18526 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \
18528 uint8_t unused_1[6];
18530 * This field is used in Output records to indicate that the output
18531 * is completely written to RAM. This field should be read as '1'
18532 * to indicate that the output has been completely written.
18533 * When writing a command completion or response to an internal processor,
18534 * the order of writes has to be such that this field is written last.
18537 } __attribute__((packed));
18539 /**************************
18540 * hwrm_vnic_plcmodes_cfg *
18541 **************************/
18544 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */
18545 struct hwrm_vnic_plcmodes_cfg_input {
18546 /* The HWRM command request type. */
18549 * The completion ring to send the completion event on. This should
18550 * be the NQ ID returned from the `nq_alloc` HWRM command.
18552 uint16_t cmpl_ring;
18554 * The sequence ID is used by the driver for tracking multiple
18555 * commands. This ID is treated as opaque data by the firmware and
18556 * the value is returned in the `hwrm_resp_hdr` upon completion.
18560 * The target ID of the command:
18561 * * 0x0-0xFFF8 - The function ID
18562 * * 0xFFF8-0xFFFE - Reserved for internal processors
18565 uint16_t target_id;
18567 * A physical address pointer pointing to a host buffer that the
18568 * command's response data will be written. This can be either a host
18569 * physical address (HPA) or a guest physical address (GPA) and must
18570 * point to a physically contiguous block of memory.
18572 uint64_t resp_addr;
18575 * When this bit is '1', the VNIC shall be configured to
18576 * use regular placement algorithm.
18577 * By default, the regular placement algorithm shall be
18578 * enabled on the VNIC.
18580 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \
18583 * When this bit is '1', the VNIC shall be configured
18584 * use the jumbo placement algorithm.
18586 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \
18589 * When this bit is '1', the VNIC shall be configured
18590 * to enable Header-Data split for IPv4 packets according
18591 * to the following rules:
18592 * # If the packet is identified as TCP/IPv4, then the
18593 * packet is split at the beginning of the TCP payload.
18594 * # If the packet is identified as UDP/IPv4, then the
18595 * packet is split at the beginning of UDP payload.
18596 * # If the packet is identified as non-TCP and non-UDP
18597 * IPv4 packet, then the packet is split at the beginning
18598 * of the upper layer protocol header carried in the IPv4
18601 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \
18604 * When this bit is '1', the VNIC shall be configured
18605 * to enable Header-Data split for IPv6 packets according
18606 * to the following rules:
18607 * # If the packet is identified as TCP/IPv6, then the
18608 * packet is split at the beginning of the TCP payload.
18609 * # If the packet is identified as UDP/IPv6, then the
18610 * packet is split at the beginning of UDP payload.
18611 * # If the packet is identified as non-TCP and non-UDP
18612 * IPv6 packet, then the packet is split at the beginning
18613 * of the upper layer protocol header carried in the IPv6
18616 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \
18619 * When this bit is '1', the VNIC shall be configured
18620 * to enable Header-Data split for FCoE packets at the
18621 * beginning of FC payload.
18623 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \
18626 * When this bit is '1', the VNIC shall be configured
18627 * to enable Header-Data split for RoCE packets at the
18628 * beginning of RoCE payload (after BTH/GRH headers).
18630 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \
18634 * This bit must be '1' for the jumbo_thresh_valid field to be
18637 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \
18640 * This bit must be '1' for the hds_offset_valid field to be
18643 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \
18646 * This bit must be '1' for the hds_threshold_valid field to be
18649 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \
18651 /* Logical vnic ID */
18654 * When jumbo placement algorithm is enabled, this value
18655 * is used to determine the threshold for jumbo placement.
18656 * Packets with length larger than this value will be
18657 * placed according to the jumbo placement algorithm.
18659 uint16_t jumbo_thresh;
18661 * This value is used to determine the offset into
18662 * packet buffer where the split data (payload) will be
18663 * placed according to one of of HDS placement algorithm.
18665 * The lengths of packet buffers provided for split data
18666 * shall be larger than this value.
18668 uint16_t hds_offset;
18670 * When one of the HDS placement algorithm is enabled, this
18671 * value is used to determine the threshold for HDS
18673 * Packets with length larger than this value will be
18674 * placed according to the HDS placement algorithm.
18675 * This value shall be in multiple of 4 bytes.
18677 uint16_t hds_threshold;
18678 uint8_t unused_0[6];
18679 } __attribute__((packed));
18681 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */
18682 struct hwrm_vnic_plcmodes_cfg_output {
18683 /* The specific error status for the command. */
18684 uint16_t error_code;
18685 /* The HWRM command request type. */
18687 /* The sequence ID from the original command. */
18689 /* The length of the response data in number of bytes. */
18691 uint8_t unused_0[7];
18693 * This field is used in Output records to indicate that the output
18694 * is completely written to RAM. This field should be read as '1'
18695 * to indicate that the output has been completely written.
18696 * When writing a command completion or response to an internal processor,
18697 * the order of writes has to be such that this field is written last.
18700 } __attribute__((packed));
18702 /***************************
18703 * hwrm_vnic_plcmodes_qcfg *
18704 ***************************/
18707 /* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */
18708 struct hwrm_vnic_plcmodes_qcfg_input {
18709 /* The HWRM command request type. */
18712 * The completion ring to send the completion event on. This should
18713 * be the NQ ID returned from the `nq_alloc` HWRM command.
18715 uint16_t cmpl_ring;
18717 * The sequence ID is used by the driver for tracking multiple
18718 * commands. This ID is treated as opaque data by the firmware and
18719 * the value is returned in the `hwrm_resp_hdr` upon completion.
18723 * The target ID of the command:
18724 * * 0x0-0xFFF8 - The function ID
18725 * * 0xFFF8-0xFFFE - Reserved for internal processors
18728 uint16_t target_id;
18730 * A physical address pointer pointing to a host buffer that the
18731 * command's response data will be written. This can be either a host
18732 * physical address (HPA) or a guest physical address (GPA) and must
18733 * point to a physically contiguous block of memory.
18735 uint64_t resp_addr;
18736 /* Logical vnic ID */
18738 uint8_t unused_0[4];
18739 } __attribute__((packed));
18741 /* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */
18742 struct hwrm_vnic_plcmodes_qcfg_output {
18743 /* The specific error status for the command. */
18744 uint16_t error_code;
18745 /* The HWRM command request type. */
18747 /* The sequence ID from the original command. */
18749 /* The length of the response data in number of bytes. */
18753 * When this bit is '1', the VNIC is configured to
18754 * use regular placement algorithm.
18756 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \
18759 * When this bit is '1', the VNIC is configured to
18760 * use the jumbo placement algorithm.
18762 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \
18765 * When this bit is '1', the VNIC is configured
18766 * to enable Header-Data split for IPv4 packets.
18768 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \
18771 * When this bit is '1', the VNIC is configured
18772 * to enable Header-Data split for IPv6 packets.
18774 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \
18777 * When this bit is '1', the VNIC is configured
18778 * to enable Header-Data split for FCoE packets.
18780 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \
18783 * When this bit is '1', the VNIC is configured
18784 * to enable Header-Data split for RoCE packets.
18786 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \
18789 * When this bit is '1', the VNIC is configured
18790 * to be the default VNIC of the requesting function.
18792 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \
18795 * When jumbo placement algorithm is enabled, this value
18796 * is used to determine the threshold for jumbo placement.
18797 * Packets with length larger than this value will be
18798 * placed according to the jumbo placement algorithm.
18800 uint16_t jumbo_thresh;
18802 * This value is used to determine the offset into
18803 * packet buffer where the split data (payload) will be
18804 * placed according to one of of HDS placement algorithm.
18806 * The lengths of packet buffers provided for split data
18807 * shall be larger than this value.
18809 uint16_t hds_offset;
18811 * When one of the HDS placement algorithm is enabled, this
18812 * value is used to determine the threshold for HDS
18814 * Packets with length larger than this value will be
18815 * placed according to the HDS placement algorithm.
18816 * This value shall be in multiple of 4 bytes.
18818 uint16_t hds_threshold;
18819 uint8_t unused_0[5];
18821 * This field is used in Output records to indicate that the output
18822 * is completely written to RAM. This field should be read as '1'
18823 * to indicate that the output has been completely written.
18824 * When writing a command completion or response to an internal processor,
18825 * the order of writes has to be such that this field is written last.
18828 } __attribute__((packed));
18830 /**********************************
18831 * hwrm_vnic_rss_cos_lb_ctx_alloc *
18832 **********************************/
18835 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */
18836 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
18837 /* The HWRM command request type. */
18840 * The completion ring to send the completion event on. This should
18841 * be the NQ ID returned from the `nq_alloc` HWRM command.
18843 uint16_t cmpl_ring;
18845 * The sequence ID is used by the driver for tracking multiple
18846 * commands. This ID is treated as opaque data by the firmware and
18847 * the value is returned in the `hwrm_resp_hdr` upon completion.
18851 * The target ID of the command:
18852 * * 0x0-0xFFF8 - The function ID
18853 * * 0xFFF8-0xFFFE - Reserved for internal processors
18856 uint16_t target_id;
18858 * A physical address pointer pointing to a host buffer that the
18859 * command's response data will be written. This can be either a host
18860 * physical address (HPA) or a guest physical address (GPA) and must
18861 * point to a physically contiguous block of memory.
18863 uint64_t resp_addr;
18864 } __attribute__((packed));
18866 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */
18867 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
18868 /* The specific error status for the command. */
18869 uint16_t error_code;
18870 /* The HWRM command request type. */
18872 /* The sequence ID from the original command. */
18874 /* The length of the response data in number of bytes. */
18876 /* rss_cos_lb_ctx_id is 16 b */
18877 uint16_t rss_cos_lb_ctx_id;
18878 uint8_t unused_0[5];
18880 * This field is used in Output records to indicate that the output
18881 * is completely written to RAM. This field should be read as '1'
18882 * to indicate that the output has been completely written.
18883 * When writing a command completion or response to an internal processor,
18884 * the order of writes has to be such that this field is written last.
18887 } __attribute__((packed));
18889 /*********************************
18890 * hwrm_vnic_rss_cos_lb_ctx_free *
18891 *********************************/
18894 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */
18895 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
18896 /* The HWRM command request type. */
18899 * The completion ring to send the completion event on. This should
18900 * be the NQ ID returned from the `nq_alloc` HWRM command.
18902 uint16_t cmpl_ring;
18904 * The sequence ID is used by the driver for tracking multiple
18905 * commands. This ID is treated as opaque data by the firmware and
18906 * the value is returned in the `hwrm_resp_hdr` upon completion.
18910 * The target ID of the command:
18911 * * 0x0-0xFFF8 - The function ID
18912 * * 0xFFF8-0xFFFE - Reserved for internal processors
18915 uint16_t target_id;
18917 * A physical address pointer pointing to a host buffer that the
18918 * command's response data will be written. This can be either a host
18919 * physical address (HPA) or a guest physical address (GPA) and must
18920 * point to a physically contiguous block of memory.
18922 uint64_t resp_addr;
18923 /* rss_cos_lb_ctx_id is 16 b */
18924 uint16_t rss_cos_lb_ctx_id;
18925 uint8_t unused_0[6];
18926 } __attribute__((packed));
18928 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */
18929 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
18930 /* The specific error status for the command. */
18931 uint16_t error_code;
18932 /* The HWRM command request type. */
18934 /* The sequence ID from the original command. */
18936 /* The length of the response data in number of bytes. */
18938 uint8_t unused_0[7];
18940 * This field is used in Output records to indicate that the output
18941 * is completely written to RAM. This field should be read as '1'
18942 * to indicate that the output has been completely written.
18943 * When writing a command completion or response to an internal processor,
18944 * the order of writes has to be such that this field is written last.
18947 } __attribute__((packed));
18949 /*******************
18950 * hwrm_ring_alloc *
18951 *******************/
18954 /* hwrm_ring_alloc_input (size:640b/80B) */
18955 struct hwrm_ring_alloc_input {
18956 /* The HWRM command request type. */
18959 * The completion ring to send the completion event on. This should
18960 * be the NQ ID returned from the `nq_alloc` HWRM command.
18962 uint16_t cmpl_ring;
18964 * The sequence ID is used by the driver for tracking multiple
18965 * commands. This ID is treated as opaque data by the firmware and
18966 * the value is returned in the `hwrm_resp_hdr` upon completion.
18970 * The target ID of the command:
18971 * * 0x0-0xFFF8 - The function ID
18972 * * 0xFFF8-0xFFFE - Reserved for internal processors
18975 uint16_t target_id;
18977 * A physical address pointer pointing to a host buffer that the
18978 * command's response data will be written. This can be either a host
18979 * physical address (HPA) or a guest physical address (GPA) and must
18980 * point to a physically contiguous block of memory.
18982 uint64_t resp_addr;
18985 * This bit must be '1' for the ring_arb_cfg field to be
18988 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \
18991 * This bit must be '1' for the stat_ctx_id_valid field to be
18994 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \
18997 * This bit must be '1' for the max_bw_valid field to be
19000 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \
19003 * This bit must be '1' for the rx_ring_id field to be
19006 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \
19009 * This bit must be '1' for the nq_ring_id field to be
19012 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \
19015 * This bit must be '1' for the rx_buf_size field to be
19018 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \
19022 /* L2 Completion Ring (CR) */
19023 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19025 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
19027 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
19028 /* RoCE Notification Completion Ring (ROCE_CR) */
19029 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19030 /* RX Aggregation Ring */
19031 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
19032 /* Notification Queue */
19033 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
19034 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \
19035 HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ
19036 uint8_t unused_0[3];
19038 * This value is a pointer to the page table for the
19041 uint64_t page_tbl_addr;
19042 /* First Byte Offset of the first entry in the first page. */
19045 * Actual page size in 2^page_size. The supported range is increments
19046 * in powers of 2 from 16 bytes to 1GB.
19048 * Page size is 16 B.
19050 * Page size is 4 KB.
19052 * Page size is 8 KB.
19054 * Page size is 64 KB.
19056 * Page size is 2 MB.
19058 * Page size is 4 MB.
19060 * Page size is 1 GB.
19064 * This value indicates the depth of page table.
19065 * For this version of the specification, value other than 0 or
19066 * 1 shall be considered as an invalid value.
19067 * When the page_tbl_depth = 0, then it is treated as a
19068 * special case with the following.
19069 * 1. FBO and page size fields are not valid.
19070 * 2. page_tbl_addr is the physical address of the first
19071 * element of the ring.
19073 uint8_t page_tbl_depth;
19074 uint8_t unused_1[2];
19076 * Number of 16B units in the ring. Minimum size for
19077 * a ring is 16 16B entries.
19081 * Logical ring number for the ring to be allocated.
19082 * This value determines the position in the doorbell
19083 * area where the update to the ring will be made.
19085 * For completion rings, this value is also the MSI-X
19086 * vector number for the function the completion ring is
19089 uint16_t logical_id;
19091 * This field is used only when ring_type is a TX ring.
19092 * This value indicates what completion ring the TX ring
19093 * is associated with.
19095 uint16_t cmpl_ring_id;
19097 * This field is used only when ring_type is a TX ring.
19098 * This value indicates what CoS queue the TX ring
19099 * is associated with.
19103 * When allocating a Rx ring or Rx aggregation ring, this field
19104 * specifies the size of the buffer descriptors posted to the ring.
19106 uint16_t rx_buf_size;
19108 * When allocating an Rx aggregation ring, this field
19109 * specifies the associated Rx ring ID.
19111 uint16_t rx_ring_id;
19113 * When allocating a completion ring, this field
19114 * specifies the associated NQ ring ID.
19116 uint16_t nq_ring_id;
19118 * This field is used only when ring_type is a TX ring.
19119 * This field is used to configure arbitration related
19120 * parameters for a TX ring.
19122 uint16_t ring_arb_cfg;
19123 /* Arbitration policy used for the ring. */
19124 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \
19126 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
19128 * Use strict priority for the TX ring.
19129 * Priority value is specified in arb_policy_param
19131 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \
19134 * Use weighted fair queue arbitration for the TX ring.
19135 * Weight is specified in arb_policy_param
19137 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \
19139 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \
19140 HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
19141 /* Reserved field. */
19142 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \
19144 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
19146 * Arbitration policy specific parameter.
19147 * # For strict priority arbitration policy, this field
19148 * represents a priority value. If set to 0, then the priority
19149 * is not specified and the HWRM is allowed to select
19150 * any priority for this TX ring.
19151 * # For weighted fair queue arbitration policy, this field
19152 * represents a weight value. If set to 0, then the weight
19153 * is not specified and the HWRM is allowed to select
19154 * any weight for this TX ring.
19156 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \
19158 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
19161 * This field is reserved for the future use.
19162 * It shall be set to 0.
19164 uint32_t reserved3;
19166 * This field is used only when ring_type is a TX ring.
19167 * This input indicates what statistics context this ring
19168 * should be associated with.
19170 uint32_t stat_ctx_id;
19172 * This field is reserved for the future use.
19173 * It shall be set to 0.
19175 uint32_t reserved4;
19177 * This field is used only when ring_type is a TX ring
19178 * to specify maximum BW allocated to the TX ring.
19179 * The HWRM will translate this value into byte counter and
19180 * time interval used for this ring inside the device.
19183 /* The bandwidth value. */
19184 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \
19185 UINT32_C(0xfffffff)
19186 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
19187 /* The granularity of the value (bits or bytes). */
19188 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \
19189 UINT32_C(0x10000000)
19190 /* Value is in bits. */
19191 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \
19192 (UINT32_C(0x0) << 28)
19193 /* Value is in bytes. */
19194 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \
19195 (UINT32_C(0x1) << 28)
19196 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \
19197 HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
19198 /* bw_value_unit is 3 b */
19199 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \
19200 UINT32_C(0xe0000000)
19201 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
19202 /* Value is in Mb or MB (base 10). */
19203 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \
19204 (UINT32_C(0x0) << 29)
19205 /* Value is in Kb or KB (base 10). */
19206 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \
19207 (UINT32_C(0x2) << 29)
19208 /* Value is in bits or bytes. */
19209 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \
19210 (UINT32_C(0x4) << 29)
19211 /* Value is in Gb or GB (base 10). */
19212 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \
19213 (UINT32_C(0x6) << 29)
19214 /* Value is in 1/100th of a percentage of total bandwidth. */
19215 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \
19216 (UINT32_C(0x1) << 29)
19218 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \
19219 (UINT32_C(0x7) << 29)
19220 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \
19221 HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
19223 * This field is used only when ring_type is a Completion ring.
19224 * This value indicates what interrupt mode should be used
19225 * on this completion ring.
19226 * Note: In the legacy interrupt mode, no more than 16
19227 * completion rings are allowed.
19231 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
19233 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
19235 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
19236 /* No Interrupt - Polled mode */
19237 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
19238 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \
19239 HWRM_RING_ALLOC_INPUT_INT_MODE_POLL
19240 uint8_t unused_4[3];
19241 } __attribute__((packed));
19243 /* hwrm_ring_alloc_output (size:128b/16B) */
19244 struct hwrm_ring_alloc_output {
19245 /* The specific error status for the command. */
19246 uint16_t error_code;
19247 /* The HWRM command request type. */
19249 /* The sequence ID from the original command. */
19251 /* The length of the response data in number of bytes. */
19254 * Physical number of ring allocated.
19255 * This value shall be unique for a ring type.
19258 /* Logical number of ring allocated. */
19259 uint16_t logical_ring_id;
19260 uint8_t unused_0[3];
19262 * This field is used in Output records to indicate that the output
19263 * is completely written to RAM. This field should be read as '1'
19264 * to indicate that the output has been completely written.
19265 * When writing a command completion or response to an internal processor,
19266 * the order of writes has to be such that this field is written last.
19269 } __attribute__((packed));
19271 /******************
19273 ******************/
19276 /* hwrm_ring_free_input (size:192b/24B) */
19277 struct hwrm_ring_free_input {
19278 /* The HWRM command request type. */
19281 * The completion ring to send the completion event on. This should
19282 * be the NQ ID returned from the `nq_alloc` HWRM command.
19284 uint16_t cmpl_ring;
19286 * The sequence ID is used by the driver for tracking multiple
19287 * commands. This ID is treated as opaque data by the firmware and
19288 * the value is returned in the `hwrm_resp_hdr` upon completion.
19292 * The target ID of the command:
19293 * * 0x0-0xFFF8 - The function ID
19294 * * 0xFFF8-0xFFFE - Reserved for internal processors
19297 uint16_t target_id;
19299 * A physical address pointer pointing to a host buffer that the
19300 * command's response data will be written. This can be either a host
19301 * physical address (HPA) or a guest physical address (GPA) and must
19302 * point to a physically contiguous block of memory.
19304 uint64_t resp_addr;
19307 /* L2 Completion Ring (CR) */
19308 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19310 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
19312 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
19313 /* RoCE Notification Completion Ring (ROCE_CR) */
19314 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19315 /* RX Aggregation Ring */
19316 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
19317 /* Notification Queue */
19318 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
19319 #define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \
19320 HWRM_RING_FREE_INPUT_RING_TYPE_NQ
19322 /* Physical number of ring allocated. */
19324 uint8_t unused_1[4];
19325 } __attribute__((packed));
19327 /* hwrm_ring_free_output (size:128b/16B) */
19328 struct hwrm_ring_free_output {
19329 /* The specific error status for the command. */
19330 uint16_t error_code;
19331 /* The HWRM command request type. */
19333 /* The sequence ID from the original command. */
19335 /* The length of the response data in number of bytes. */
19337 uint8_t unused_0[7];
19339 * This field is used in Output records to indicate that the output
19340 * is completely written to RAM. This field should be read as '1'
19341 * to indicate that the output has been completely written.
19342 * When writing a command completion or response to an internal processor,
19343 * the order of writes has to be such that this field is written last.
19346 } __attribute__((packed));
19348 /**************************************
19349 * hwrm_ring_cmpl_ring_qaggint_params *
19350 **************************************/
19353 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */
19354 struct hwrm_ring_cmpl_ring_qaggint_params_input {
19355 /* The HWRM command request type. */
19358 * The completion ring to send the completion event on. This should
19359 * be the NQ ID returned from the `nq_alloc` HWRM command.
19361 uint16_t cmpl_ring;
19363 * The sequence ID is used by the driver for tracking multiple
19364 * commands. This ID is treated as opaque data by the firmware and
19365 * the value is returned in the `hwrm_resp_hdr` upon completion.
19369 * The target ID of the command:
19370 * * 0x0-0xFFF8 - The function ID
19371 * * 0xFFF8-0xFFFE - Reserved for internal processors
19374 uint16_t target_id;
19376 * A physical address pointer pointing to a host buffer that the
19377 * command's response data will be written. This can be either a host
19378 * physical address (HPA) or a guest physical address (GPA) and must
19379 * point to a physically contiguous block of memory.
19381 uint64_t resp_addr;
19382 /* Physical number of completion ring. */
19384 uint8_t unused_0[6];
19385 } __attribute__((packed));
19387 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */
19388 struct hwrm_ring_cmpl_ring_qaggint_params_output {
19389 /* The specific error status for the command. */
19390 uint16_t error_code;
19391 /* The HWRM command request type. */
19393 /* The sequence ID from the original command. */
19395 /* The length of the response data in number of bytes. */
19399 * When this bit is set to '1', interrupt max
19400 * timer is reset whenever a completion is received.
19402 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \
19405 * When this bit is set to '1', ring idle mode
19406 * aggregation will be enabled.
19408 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \
19411 * Number of completions to aggregate before DMA
19412 * during the normal mode.
19414 uint16_t num_cmpl_dma_aggr;
19416 * Number of completions to aggregate before DMA
19417 * during the interrupt mode.
19419 uint16_t num_cmpl_dma_aggr_during_int;
19421 * Timer in unit of 80-nsec used to aggregate completions before
19422 * DMA during the normal mode (not in interrupt mode).
19424 uint16_t cmpl_aggr_dma_tmr;
19426 * Timer in unit of 80-nsec used to aggregate completions before
19427 * DMA during the interrupt mode.
19429 uint16_t cmpl_aggr_dma_tmr_during_int;
19430 /* Minimum time (in unit of 80-nsec) between two interrupts. */
19431 uint16_t int_lat_tmr_min;
19433 * Maximum wait time (in unit of 80-nsec) spent aggregating
19434 * completions before signaling the interrupt after the
19435 * interrupt is enabled.
19437 uint16_t int_lat_tmr_max;
19439 * Minimum number of completions aggregated before signaling
19442 uint16_t num_cmpl_aggr_int;
19443 uint8_t unused_0[7];
19445 * This field is used in Output records to indicate that the output
19446 * is completely written to RAM. This field should be read as '1'
19447 * to indicate that the output has been completely written.
19448 * When writing a command completion or response to an internal processor,
19449 * the order of writes has to be such that this field is written last.
19452 } __attribute__((packed));
19454 /*****************************************
19455 * hwrm_ring_cmpl_ring_cfg_aggint_params *
19456 *****************************************/
19459 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */
19460 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
19461 /* The HWRM command request type. */
19464 * The completion ring to send the completion event on. This should
19465 * be the NQ ID returned from the `nq_alloc` HWRM command.
19467 uint16_t cmpl_ring;
19469 * The sequence ID is used by the driver for tracking multiple
19470 * commands. This ID is treated as opaque data by the firmware and
19471 * the value is returned in the `hwrm_resp_hdr` upon completion.
19475 * The target ID of the command:
19476 * * 0x0-0xFFF8 - The function ID
19477 * * 0xFFF8-0xFFFE - Reserved for internal processors
19480 uint16_t target_id;
19482 * A physical address pointer pointing to a host buffer that the
19483 * command's response data will be written. This can be either a host
19484 * physical address (HPA) or a guest physical address (GPA) and must
19485 * point to a physically contiguous block of memory.
19487 uint64_t resp_addr;
19488 /* Physical number of completion ring. */
19492 * When this bit is set to '1', interrupt latency max
19493 * timer is reset whenever a completion is received.
19495 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \
19498 * When this bit is set to '1', ring idle mode
19499 * aggregation will be enabled.
19501 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \
19504 * Set this flag to 1 when configuring parameters on a
19505 * notification queue. Set this flag to 0 when configuring
19506 * parameters on a completion queue.
19508 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \
19511 * Number of completions to aggregate before DMA
19512 * during the normal mode.
19514 uint16_t num_cmpl_dma_aggr;
19516 * Number of completions to aggregate before DMA
19517 * during the interrupt mode.
19519 uint16_t num_cmpl_dma_aggr_during_int;
19521 * Timer in unit of 80-nsec used to aggregate completions before
19522 * DMA during the normal mode (not in interrupt mode).
19524 uint16_t cmpl_aggr_dma_tmr;
19526 * Timer in unit of 80-nsec used to aggregate completions before
19527 * DMA during the interrupt mode.
19529 uint16_t cmpl_aggr_dma_tmr_during_int;
19530 /* Minimum time (in unit of 80-nsec) between two interrupts. */
19531 uint16_t int_lat_tmr_min;
19533 * Maximum wait time (in unit of 80-nsec) spent aggregating
19534 * cmpls before signaling the interrupt after the
19535 * interrupt is enabled.
19537 uint16_t int_lat_tmr_max;
19539 * Minimum number of completions aggregated before signaling
19542 uint16_t num_cmpl_aggr_int;
19544 * Bitfield that indicates which parameters are to be applied. Only
19545 * required when configuring devices with notification queues, and
19546 * used in that case to set certain parameters on completion queues
19547 * and others on notification queues.
19551 * This bit must be '1' for the num_cmpl_dma_aggr field to be
19554 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \
19557 * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be
19560 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \
19563 * This bit must be '1' for the cmpl_aggr_dma_tmr field to be
19566 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \
19569 * This bit must be '1' for the int_lat_tmr_min field to be
19572 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \
19575 * This bit must be '1' for the int_lat_tmr_max field to be
19578 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \
19581 * This bit must be '1' for the num_cmpl_aggr_int field to be
19584 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \
19586 uint8_t unused_0[4];
19587 } __attribute__((packed));
19589 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */
19590 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
19591 /* The specific error status for the command. */
19592 uint16_t error_code;
19593 /* The HWRM command request type. */
19595 /* The sequence ID from the original command. */
19597 /* The length of the response data in number of bytes. */
19599 uint8_t unused_0[7];
19601 * This field is used in Output records to indicate that the output
19602 * is completely written to RAM. This field should be read as '1'
19603 * to indicate that the output has been completely written.
19604 * When writing a command completion or response to an internal processor,
19605 * the order of writes has to be such that this field is written last.
19608 } __attribute__((packed));
19610 /*******************
19611 * hwrm_ring_reset *
19612 *******************/
19615 /* hwrm_ring_reset_input (size:192b/24B) */
19616 struct hwrm_ring_reset_input {
19617 /* The HWRM command request type. */
19620 * The completion ring to send the completion event on. This should
19621 * be the NQ ID returned from the `nq_alloc` HWRM command.
19623 uint16_t cmpl_ring;
19625 * The sequence ID is used by the driver for tracking multiple
19626 * commands. This ID is treated as opaque data by the firmware and
19627 * the value is returned in the `hwrm_resp_hdr` upon completion.
19631 * The target ID of the command:
19632 * * 0x0-0xFFF8 - The function ID
19633 * * 0xFFF8-0xFFFE - Reserved for internal processors
19636 uint16_t target_id;
19638 * A physical address pointer pointing to a host buffer that the
19639 * command's response data will be written. This can be either a host
19640 * physical address (HPA) or a guest physical address (GPA) and must
19641 * point to a physically contiguous block of memory.
19643 uint64_t resp_addr;
19646 /* L2 Completion Ring (CR) */
19647 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
19649 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
19651 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
19652 /* RoCE Notification Completion Ring (ROCE_CR) */
19653 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
19654 #define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \
19655 HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL
19657 /* Physical number of the ring. */
19659 uint8_t unused_1[4];
19660 } __attribute__((packed));
19662 /* hwrm_ring_reset_output (size:128b/16B) */
19663 struct hwrm_ring_reset_output {
19664 /* The specific error status for the command. */
19665 uint16_t error_code;
19666 /* The HWRM command request type. */
19668 /* The sequence ID from the original command. */
19670 /* The length of the response data in number of bytes. */
19672 uint8_t unused_0[7];
19674 * This field is used in Output records to indicate that the output
19675 * is completely written to RAM. This field should be read as '1'
19676 * to indicate that the output has been completely written.
19677 * When writing a command completion or response to an internal processor,
19678 * the order of writes has to be such that this field is written last.
19681 } __attribute__((packed));
19683 /***********************
19684 * hwrm_ring_grp_alloc *
19685 ***********************/
19688 /* hwrm_ring_grp_alloc_input (size:192b/24B) */
19689 struct hwrm_ring_grp_alloc_input {
19690 /* The HWRM command request type. */
19693 * The completion ring to send the completion event on. This should
19694 * be the NQ ID returned from the `nq_alloc` HWRM command.
19696 uint16_t cmpl_ring;
19698 * The sequence ID is used by the driver for tracking multiple
19699 * commands. This ID is treated as opaque data by the firmware and
19700 * the value is returned in the `hwrm_resp_hdr` upon completion.
19704 * The target ID of the command:
19705 * * 0x0-0xFFF8 - The function ID
19706 * * 0xFFF8-0xFFFE - Reserved for internal processors
19709 uint16_t target_id;
19711 * A physical address pointer pointing to a host buffer that the
19712 * command's response data will be written. This can be either a host
19713 * physical address (HPA) or a guest physical address (GPA) and must
19714 * point to a physically contiguous block of memory.
19716 uint64_t resp_addr;
19718 * This value identifies the CR associated with the ring
19723 * This value identifies the main RR associated with the ring
19728 * This value identifies the aggregation RR associated with
19729 * the ring group. If this value is 0xFF... (All Fs), then no
19730 * Aggregation ring will be set.
19734 * This value identifies the statistics context associated
19735 * with the ring group.
19738 } __attribute__((packed));
19740 /* hwrm_ring_grp_alloc_output (size:128b/16B) */
19741 struct hwrm_ring_grp_alloc_output {
19742 /* The specific error status for the command. */
19743 uint16_t error_code;
19744 /* The HWRM command request type. */
19746 /* The sequence ID from the original command. */
19748 /* The length of the response data in number of bytes. */
19751 * This is the ring group ID value. Use this value to program
19752 * the default ring group for the VNIC or as table entries
19753 * in an RSS/COS context.
19755 uint32_t ring_group_id;
19756 uint8_t unused_0[3];
19758 * This field is used in Output records to indicate that the output
19759 * is completely written to RAM. This field should be read as '1'
19760 * to indicate that the output has been completely written.
19761 * When writing a command completion or response to an internal processor,
19762 * the order of writes has to be such that this field is written last.
19765 } __attribute__((packed));
19767 /**********************
19768 * hwrm_ring_grp_free *
19769 **********************/
19772 /* hwrm_ring_grp_free_input (size:192b/24B) */
19773 struct hwrm_ring_grp_free_input {
19774 /* The HWRM command request type. */
19777 * The completion ring to send the completion event on. This should
19778 * be the NQ ID returned from the `nq_alloc` HWRM command.
19780 uint16_t cmpl_ring;
19782 * The sequence ID is used by the driver for tracking multiple
19783 * commands. This ID is treated as opaque data by the firmware and
19784 * the value is returned in the `hwrm_resp_hdr` upon completion.
19788 * The target ID of the command:
19789 * * 0x0-0xFFF8 - The function ID
19790 * * 0xFFF8-0xFFFE - Reserved for internal processors
19793 uint16_t target_id;
19795 * A physical address pointer pointing to a host buffer that the
19796 * command's response data will be written. This can be either a host
19797 * physical address (HPA) or a guest physical address (GPA) and must
19798 * point to a physically contiguous block of memory.
19800 uint64_t resp_addr;
19801 /* This is the ring group ID value. */
19802 uint32_t ring_group_id;
19803 uint8_t unused_0[4];
19804 } __attribute__((packed));
19806 /* hwrm_ring_grp_free_output (size:128b/16B) */
19807 struct hwrm_ring_grp_free_output {
19808 /* The specific error status for the command. */
19809 uint16_t error_code;
19810 /* The HWRM command request type. */
19812 /* The sequence ID from the original command. */
19814 /* The length of the response data in number of bytes. */
19816 uint8_t unused_0[7];
19818 * This field is used in Output records to indicate that the output
19819 * is completely written to RAM. This field should be read as '1'
19820 * to indicate that the output has been completely written.
19821 * When writing a command completion or response to an internal processor,
19822 * the order of writes has to be such that this field is written last.
19825 } __attribute__((packed));
19827 /****************************
19828 * hwrm_cfa_l2_filter_alloc *
19829 ****************************/
19832 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
19833 struct hwrm_cfa_l2_filter_alloc_input {
19834 /* The HWRM command request type. */
19837 * The completion ring to send the completion event on. This should
19838 * be the NQ ID returned from the `nq_alloc` HWRM command.
19840 uint16_t cmpl_ring;
19842 * The sequence ID is used by the driver for tracking multiple
19843 * commands. This ID is treated as opaque data by the firmware and
19844 * the value is returned in the `hwrm_resp_hdr` upon completion.
19848 * The target ID of the command:
19849 * * 0x0-0xFFF8 - The function ID
19850 * * 0xFFF8-0xFFFE - Reserved for internal processors
19853 uint16_t target_id;
19855 * A physical address pointer pointing to a host buffer that the
19856 * command's response data will be written. This can be either a host
19857 * physical address (HPA) or a guest physical address (GPA) and must
19858 * point to a physically contiguous block of memory.
19860 uint64_t resp_addr;
19863 * Enumeration denoting the RX, TX type of the resource.
19864 * This enumeration is used for resources that are similar for both
19865 * TX and RX paths of the chip.
19867 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \
19870 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \
19873 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \
19875 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \
19876 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
19877 /* Setting of this flag indicates the applicability to the loopback path. */
19878 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
19881 * Setting of this flag indicates drop action. If this flag is not set,
19882 * then it should be considered accept action.
19884 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \
19887 * If this flag is set, all t_l2_* fields are invalid
19888 * and they should not be specified.
19889 * If this flag is set, then l2_* fields refer to
19890 * fields of outermost L2 header.
19892 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \
19896 * This bit must be '1' for the l2_addr field to be
19899 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
19902 * This bit must be '1' for the l2_addr_mask field to be
19905 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \
19908 * This bit must be '1' for the l2_ovlan field to be
19911 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \
19914 * This bit must be '1' for the l2_ovlan_mask field to be
19917 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \
19920 * This bit must be '1' for the l2_ivlan field to be
19923 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
19926 * This bit must be '1' for the l2_ivlan_mask field to be
19929 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \
19932 * This bit must be '1' for the t_l2_addr field to be
19935 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \
19938 * This bit must be '1' for the t_l2_addr_mask field to be
19941 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \
19944 * This bit must be '1' for the t_l2_ovlan field to be
19947 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \
19950 * This bit must be '1' for the t_l2_ovlan_mask field to be
19953 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \
19956 * This bit must be '1' for the t_l2_ivlan field to be
19959 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \
19962 * This bit must be '1' for the t_l2_ivlan_mask field to be
19965 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \
19968 * This bit must be '1' for the src_type field to be
19971 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \
19974 * This bit must be '1' for the src_id field to be
19977 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \
19980 * This bit must be '1' for the tunnel_type field to be
19983 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
19986 * This bit must be '1' for the dst_id field to be
19989 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
19992 * This bit must be '1' for the mirror_vnic_id field to be
19995 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
19998 * This value sets the match value for the L2 MAC address.
19999 * Destination MAC address for RX path.
20000 * Source MAC address for TX path.
20002 uint8_t l2_addr[6];
20003 uint8_t unused_0[2];
20005 * This value sets the mask value for the L2 address.
20006 * A value of 0 will mask the corresponding bit from
20009 uint8_t l2_addr_mask[6];
20010 /* This value sets VLAN ID value for outer VLAN. */
20013 * This value sets the mask value for the ovlan id.
20014 * A value of 0 will mask the corresponding bit from
20017 uint16_t l2_ovlan_mask;
20018 /* This value sets VLAN ID value for inner VLAN. */
20021 * This value sets the mask value for the ivlan id.
20022 * A value of 0 will mask the corresponding bit from
20025 uint16_t l2_ivlan_mask;
20026 uint8_t unused_1[2];
20028 * This value sets the match value for the tunnel
20030 * Destination MAC address for RX path.
20031 * Source MAC address for TX path.
20033 uint8_t t_l2_addr[6];
20034 uint8_t unused_2[2];
20036 * This value sets the mask value for the tunnel L2
20038 * A value of 0 will mask the corresponding bit from
20041 uint8_t t_l2_addr_mask[6];
20042 /* This value sets VLAN ID value for tunnel outer VLAN. */
20043 uint16_t t_l2_ovlan;
20045 * This value sets the mask value for the tunnel ovlan id.
20046 * A value of 0 will mask the corresponding bit from
20049 uint16_t t_l2_ovlan_mask;
20050 /* This value sets VLAN ID value for tunnel inner VLAN. */
20051 uint16_t t_l2_ivlan;
20053 * This value sets the mask value for the tunnel ivlan id.
20054 * A value of 0 will mask the corresponding bit from
20057 uint16_t t_l2_ivlan_mask;
20058 /* This value identifies the type of source of the packet. */
20061 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
20062 /* Physical function */
20063 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
20064 /* Virtual function */
20065 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
20066 /* Virtual NIC of a function */
20067 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
20068 /* Embedded processor for CFA management */
20069 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
20070 /* Embedded processor for OOB management */
20071 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
20072 /* Embedded processor for RoCE */
20073 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
20074 /* Embedded processor for network proxy functions */
20075 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
20076 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \
20077 HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG
20080 * This value is the id of the source.
20081 * For a network port, it represents port_id.
20082 * For a physical function, it represents fid.
20083 * For a virtual function, it represents vf_id.
20084 * For a vnic, it represents vnic_id.
20085 * For embedded processors, this id is not valid.
20088 * 1. The function ID is implied if it src_id is
20089 * not provided for a src_type that is either
20093 uint8_t tunnel_type;
20095 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
20097 /* Virtual eXtensible Local Area Network (VXLAN) */
20098 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20100 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
20101 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
20103 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
20104 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
20107 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
20109 /* Generic Network Virtualization Encapsulation (Geneve) */
20110 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
20112 /* Multi-Protocol Lable Switching (MPLS) */
20113 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
20115 /* Stateless Transport Tunnel (STT) */
20116 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
20118 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
20119 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
20121 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20122 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20124 /* Any tunneled traffic */
20125 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
20127 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
20128 HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
20131 * If set, this value shall represent the
20132 * Logical VNIC ID of the destination VNIC for the RX
20133 * path and network port id of the destination port for
20138 * Logical VNIC ID of the VNIC where traffic is
20141 uint16_t mirror_vnic_id;
20143 * This hint is provided to help in placing
20144 * the filter in the filter table.
20147 /* No preference */
20148 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
20150 /* Above the given filter */
20151 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \
20153 /* Below the given filter */
20154 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \
20156 /* As high as possible */
20157 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \
20159 /* As low as possible */
20160 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \
20162 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
20163 HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN
20167 * This is the ID of the filter that goes along with
20170 * This field is valid only for the following values.
20171 * 1 - Above the given filter
20172 * 2 - Below the given filter
20174 uint64_t l2_filter_id_hint;
20175 } __attribute__((packed));
20177 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */
20178 struct hwrm_cfa_l2_filter_alloc_output {
20179 /* The specific error status for the command. */
20180 uint16_t error_code;
20181 /* The HWRM command request type. */
20183 /* The sequence ID from the original command. */
20185 /* The length of the response data in number of bytes. */
20188 * This value identifies a set of CFA data structures used for an L2
20191 uint64_t l2_filter_id;
20193 * This is the ID of the flow associated with this
20195 * This value shall be used to match and associate the
20196 * flow identifier returned in completion records.
20197 * A value of 0xFFFFFFFF shall indicate no flow id.
20200 uint8_t unused_0[3];
20202 * This field is used in Output records to indicate that the output
20203 * is completely written to RAM. This field should be read as '1'
20204 * to indicate that the output has been completely written.
20205 * When writing a command completion or response to an internal processor,
20206 * the order of writes has to be such that this field is written last.
20209 } __attribute__((packed));
20211 /***************************
20212 * hwrm_cfa_l2_filter_free *
20213 ***************************/
20216 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */
20217 struct hwrm_cfa_l2_filter_free_input {
20218 /* The HWRM command request type. */
20221 * The completion ring to send the completion event on. This should
20222 * be the NQ ID returned from the `nq_alloc` HWRM command.
20224 uint16_t cmpl_ring;
20226 * The sequence ID is used by the driver for tracking multiple
20227 * commands. This ID is treated as opaque data by the firmware and
20228 * the value is returned in the `hwrm_resp_hdr` upon completion.
20232 * The target ID of the command:
20233 * * 0x0-0xFFF8 - The function ID
20234 * * 0xFFF8-0xFFFE - Reserved for internal processors
20237 uint16_t target_id;
20239 * A physical address pointer pointing to a host buffer that the
20240 * command's response data will be written. This can be either a host
20241 * physical address (HPA) or a guest physical address (GPA) and must
20242 * point to a physically contiguous block of memory.
20244 uint64_t resp_addr;
20246 * This value identifies a set of CFA data structures used for an L2
20249 uint64_t l2_filter_id;
20250 } __attribute__((packed));
20252 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */
20253 struct hwrm_cfa_l2_filter_free_output {
20254 /* The specific error status for the command. */
20255 uint16_t error_code;
20256 /* The HWRM command request type. */
20258 /* The sequence ID from the original command. */
20260 /* The length of the response data in number of bytes. */
20262 uint8_t unused_0[7];
20264 * This field is used in Output records to indicate that the output
20265 * is completely written to RAM. This field should be read as '1'
20266 * to indicate that the output has been completely written.
20267 * When writing a command completion or response to an internal processor,
20268 * the order of writes has to be such that this field is written last.
20271 } __attribute__((packed));
20273 /**************************
20274 * hwrm_cfa_l2_filter_cfg *
20275 **************************/
20278 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */
20279 struct hwrm_cfa_l2_filter_cfg_input {
20280 /* The HWRM command request type. */
20283 * The completion ring to send the completion event on. This should
20284 * be the NQ ID returned from the `nq_alloc` HWRM command.
20286 uint16_t cmpl_ring;
20288 * The sequence ID is used by the driver for tracking multiple
20289 * commands. This ID is treated as opaque data by the firmware and
20290 * the value is returned in the `hwrm_resp_hdr` upon completion.
20294 * The target ID of the command:
20295 * * 0x0-0xFFF8 - The function ID
20296 * * 0xFFF8-0xFFFE - Reserved for internal processors
20299 uint16_t target_id;
20301 * A physical address pointer pointing to a host buffer that the
20302 * command's response data will be written. This can be either a host
20303 * physical address (HPA) or a guest physical address (GPA) and must
20304 * point to a physically contiguous block of memory.
20306 uint64_t resp_addr;
20309 * Enumeration denoting the RX, TX type of the resource.
20310 * This enumeration is used for resources that are similar for both
20311 * TX and RX paths of the chip.
20313 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
20315 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
20317 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
20318 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \
20319 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
20321 * Setting of this flag indicates drop action. If this flag is not set,
20322 * then it should be considered accept action.
20324 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
20327 * This bit must be '1' for the dst_id field to be
20330 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \
20333 * This bit must be '1' for the new_mirror_vnic_id field to be
20336 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
20339 * This value identifies a set of CFA data structures used for an L2
20342 uint64_t l2_filter_id;
20344 * If set, this value shall represent the
20345 * Logical VNIC ID of the destination VNIC for the RX
20346 * path and network port id of the destination port for
20351 * New Logical VNIC ID of the VNIC where traffic is
20354 uint32_t new_mirror_vnic_id;
20355 } __attribute__((packed));
20357 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */
20358 struct hwrm_cfa_l2_filter_cfg_output {
20359 /* The specific error status for the command. */
20360 uint16_t error_code;
20361 /* The HWRM command request type. */
20363 /* The sequence ID from the original command. */
20365 /* The length of the response data in number of bytes. */
20367 uint8_t unused_0[7];
20369 * This field is used in Output records to indicate that the output
20370 * is completely written to RAM. This field should be read as '1'
20371 * to indicate that the output has been completely written.
20372 * When writing a command completion or response to an internal processor,
20373 * the order of writes has to be such that this field is written last.
20376 } __attribute__((packed));
20378 /***************************
20379 * hwrm_cfa_l2_set_rx_mask *
20380 ***************************/
20383 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */
20384 struct hwrm_cfa_l2_set_rx_mask_input {
20385 /* The HWRM command request type. */
20388 * The completion ring to send the completion event on. This should
20389 * be the NQ ID returned from the `nq_alloc` HWRM command.
20391 uint16_t cmpl_ring;
20393 * The sequence ID is used by the driver for tracking multiple
20394 * commands. This ID is treated as opaque data by the firmware and
20395 * the value is returned in the `hwrm_resp_hdr` upon completion.
20399 * The target ID of the command:
20400 * * 0x0-0xFFF8 - The function ID
20401 * * 0xFFF8-0xFFFE - Reserved for internal processors
20404 uint16_t target_id;
20406 * A physical address pointer pointing to a host buffer that the
20407 * command's response data will be written. This can be either a host
20408 * physical address (HPA) or a guest physical address (GPA) and must
20409 * point to a physically contiguous block of memory.
20411 uint64_t resp_addr;
20416 * When this bit is '1', the function is requested to accept
20417 * multi-cast packets specified by the multicast addr table.
20419 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \
20422 * When this bit is '1', the function is requested to accept
20423 * all multi-cast packets.
20425 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \
20428 * When this bit is '1', the function is requested to accept
20429 * broadcast packets.
20431 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \
20434 * When this bit is '1', the function is requested to be
20435 * put in the promiscuous mode.
20437 * The HWRM should accept any function to set up
20438 * promiscuous mode.
20440 * The HWRM shall follow the semantics below for the
20441 * promiscuous mode support.
20442 * # When partitioning is not enabled on a port
20443 * (i.e. single PF on the port), then the PF shall
20444 * be allowed to be in the promiscuous mode. When the
20445 * PF is in the promiscuous mode, then it shall
20446 * receive all host bound traffic on that port.
20447 * # When partitioning is enabled on a port
20448 * (i.e. multiple PFs per port) and a PF on that
20449 * port is in the promiscuous mode, then the PF
20450 * receives all traffic within that partition as
20451 * identified by a unique identifier for the
20452 * PF (e.g. S-Tag). If a unique outer VLAN
20453 * for the PF is specified, then the setting of
20454 * promiscuous mode on that PF shall result in the
20455 * PF receiving all host bound traffic with matching
20457 * # A VF shall can be set in the promiscuous mode.
20458 * In the promiscuous mode, the VF does not receive any
20459 * traffic unless a unique outer VLAN for the
20460 * VF is specified. If a unique outer VLAN
20461 * for the VF is specified, then the setting of
20462 * promiscuous mode on that VF shall result in the
20463 * VF receiving all host bound traffic with the
20464 * matching outer VLAN.
20465 * # The HWRM shall allow the setting of promiscuous
20466 * mode on a function independently from the
20467 * promiscuous mode settings on other functions.
20469 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \
20472 * If this flag is set, the corresponding RX
20473 * filters shall be set up to cover multicast/broadcast
20474 * filters for the outermost Layer 2 destination MAC
20477 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \
20480 * If this flag is set, the corresponding RX
20481 * filters shall be set up to cover multicast/broadcast
20482 * filters for the VLAN-tagged packets that match the
20483 * TPID and VID fields of VLAN tags in the VLAN tag
20484 * table specified in this command.
20486 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \
20489 * If this flag is set, the corresponding RX
20490 * filters shall be set up to cover multicast/broadcast
20491 * filters for non-VLAN tagged packets and VLAN-tagged
20492 * packets that match the TPID and VID fields of VLAN
20493 * tags in the VLAN tag table specified in this command.
20495 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \
20498 * If this flag is set, the corresponding RX
20499 * filters shall be set up to cover multicast/broadcast
20500 * filters for non-VLAN tagged packets and VLAN-tagged
20501 * packets matching any VLAN tag.
20503 * If this flag is set, then the HWRM shall ignore
20504 * VLAN tags specified in vlan_tag_tbl.
20506 * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan
20507 * flags is set, then the HWRM shall ignore
20508 * VLAN tags specified in vlan_tag_tbl.
20510 * The HWRM client shall set at most one flag out of
20511 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.
20513 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \
20515 /* This is the address for mcast address tbl. */
20516 uint64_t mc_tbl_addr;
20518 * This value indicates how many entries in mc_tbl are valid.
20519 * Each entry is 6 bytes.
20521 uint32_t num_mc_entries;
20522 uint8_t unused_0[4];
20524 * This is the address for VLAN tag table.
20525 * Each VLAN entry in the table is 4 bytes of a VLAN tag
20526 * including TPID, PCP, DEI, and VID fields in network byte
20529 uint64_t vlan_tag_tbl_addr;
20531 * This value indicates how many entries in vlan_tag_tbl are
20532 * valid. Each entry is 4 bytes.
20534 uint32_t num_vlan_tags;
20535 uint8_t unused_1[4];
20536 } __attribute__((packed));
20538 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */
20539 struct hwrm_cfa_l2_set_rx_mask_output {
20540 /* The specific error status for the command. */
20541 uint16_t error_code;
20542 /* The HWRM command request type. */
20544 /* The sequence ID from the original command. */
20546 /* The length of the response data in number of bytes. */
20548 uint8_t unused_0[7];
20550 * This field is used in Output records to indicate that the output
20551 * is completely written to RAM. This field should be read as '1'
20552 * to indicate that the output has been completely written.
20553 * When writing a command completion or response to an internal processor,
20554 * the order of writes has to be such that this field is written last.
20557 } __attribute__((packed));
20559 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */
20560 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
20562 * command specific error codes that goes to
20563 * the cmd_err field in Common HWRM Error Response.
20566 /* Unknown error */
20567 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \
20569 /* Unable to complete operation due to conflict with Ntuple Filter */
20570 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \
20572 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \
20573 HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR
20574 uint8_t unused_0[7];
20575 } __attribute__((packed));
20577 /*******************************
20578 * hwrm_cfa_vlan_antispoof_cfg *
20579 *******************************/
20582 /* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */
20583 struct hwrm_cfa_vlan_antispoof_cfg_input {
20584 /* The HWRM command request type. */
20587 * The completion ring to send the completion event on. This should
20588 * be the NQ ID returned from the `nq_alloc` HWRM command.
20590 uint16_t cmpl_ring;
20592 * The sequence ID is used by the driver for tracking multiple
20593 * commands. This ID is treated as opaque data by the firmware and
20594 * the value is returned in the `hwrm_resp_hdr` upon completion.
20598 * The target ID of the command:
20599 * * 0x0-0xFFF8 - The function ID
20600 * * 0xFFF8-0xFFFE - Reserved for internal processors
20603 uint16_t target_id;
20605 * A physical address pointer pointing to a host buffer that the
20606 * command's response data will be written. This can be either a host
20607 * physical address (HPA) or a guest physical address (GPA) and must
20608 * point to a physically contiguous block of memory.
20610 uint64_t resp_addr;
20612 * Function ID of the function that is being configured.
20613 * Only valid for a VF FID configured by the PF.
20616 uint8_t unused_0[2];
20617 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
20618 uint32_t num_vlan_entries;
20620 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
20621 * antispoof table. Each table entry contains the 16-bit TPID
20622 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
20623 * all in network order to match hwrm_cfa_l2_set_rx_mask.
20624 * For an individual VLAN entry, the mask value should be 0xfff
20625 * for the 12-bit VLAN ID.
20627 uint64_t vlan_tag_mask_tbl_addr;
20628 } __attribute__((packed));
20630 /* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */
20631 struct hwrm_cfa_vlan_antispoof_cfg_output {
20632 /* The specific error status for the command. */
20633 uint16_t error_code;
20634 /* The HWRM command request type. */
20636 /* The sequence ID from the original command. */
20638 /* The length of the response data in number of bytes. */
20640 uint8_t unused_0[7];
20642 * This field is used in Output records to indicate that the output
20643 * is completely written to RAM. This field should be read as '1'
20644 * to indicate that the output has been completely written.
20645 * When writing a command completion or response to an internal processor,
20646 * the order of writes has to be such that this field is written last.
20649 } __attribute__((packed));
20651 /********************************
20652 * hwrm_cfa_vlan_antispoof_qcfg *
20653 ********************************/
20656 /* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */
20657 struct hwrm_cfa_vlan_antispoof_qcfg_input {
20658 /* The HWRM command request type. */
20661 * The completion ring to send the completion event on. This should
20662 * be the NQ ID returned from the `nq_alloc` HWRM command.
20664 uint16_t cmpl_ring;
20666 * The sequence ID is used by the driver for tracking multiple
20667 * commands. This ID is treated as opaque data by the firmware and
20668 * the value is returned in the `hwrm_resp_hdr` upon completion.
20672 * The target ID of the command:
20673 * * 0x0-0xFFF8 - The function ID
20674 * * 0xFFF8-0xFFFE - Reserved for internal processors
20677 uint16_t target_id;
20679 * A physical address pointer pointing to a host buffer that the
20680 * command's response data will be written. This can be either a host
20681 * physical address (HPA) or a guest physical address (GPA) and must
20682 * point to a physically contiguous block of memory.
20684 uint64_t resp_addr;
20686 * Function ID of the function that is being queried.
20687 * Only valid for a VF FID queried by the PF.
20690 uint8_t unused_0[2];
20692 * Maximum number of VLAN entries the firmware is allowed to DMA
20693 * to vlan_tag_mask_tbl.
20695 uint32_t max_vlan_entries;
20697 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN
20698 * antispoof table to which firmware will DMA to. Each table
20699 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
20700 * 16-bit VLAN ID, and a 16-bit mask, all in network order to
20701 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,
20702 * the mask value should be 0xfff for the 12-bit VLAN ID.
20704 uint64_t vlan_tag_mask_tbl_addr;
20705 } __attribute__((packed));
20707 /* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */
20708 struct hwrm_cfa_vlan_antispoof_qcfg_output {
20709 /* The specific error status for the command. */
20710 uint16_t error_code;
20711 /* The HWRM command request type. */
20713 /* The sequence ID from the original command. */
20715 /* The length of the response data in number of bytes. */
20717 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
20718 uint32_t num_vlan_entries;
20719 uint8_t unused_0[3];
20721 * This field is used in Output records to indicate that the output
20722 * is completely written to RAM. This field should be read as '1'
20723 * to indicate that the output has been completely written.
20724 * When writing a command completion or response to an internal processor,
20725 * the order of writes has to be such that this field is written last.
20728 } __attribute__((packed));
20730 /********************************
20731 * hwrm_cfa_tunnel_filter_alloc *
20732 ********************************/
20735 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */
20736 struct hwrm_cfa_tunnel_filter_alloc_input {
20737 /* The HWRM command request type. */
20740 * The completion ring to send the completion event on. This should
20741 * be the NQ ID returned from the `nq_alloc` HWRM command.
20743 uint16_t cmpl_ring;
20745 * The sequence ID is used by the driver for tracking multiple
20746 * commands. This ID is treated as opaque data by the firmware and
20747 * the value is returned in the `hwrm_resp_hdr` upon completion.
20751 * The target ID of the command:
20752 * * 0x0-0xFFF8 - The function ID
20753 * * 0xFFF8-0xFFFE - Reserved for internal processors
20756 uint16_t target_id;
20758 * A physical address pointer pointing to a host buffer that the
20759 * command's response data will be written. This can be either a host
20760 * physical address (HPA) or a guest physical address (GPA) and must
20761 * point to a physically contiguous block of memory.
20763 uint64_t resp_addr;
20765 /* Setting of this flag indicates the applicability to the loopback path. */
20766 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
20770 * This bit must be '1' for the l2_filter_id field to be
20773 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
20776 * This bit must be '1' for the l2_addr field to be
20779 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \
20782 * This bit must be '1' for the l2_ivlan field to be
20785 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \
20788 * This bit must be '1' for the l3_addr field to be
20791 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \
20794 * This bit must be '1' for the l3_addr_type field to be
20797 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \
20800 * This bit must be '1' for the t_l3_addr_type field to be
20803 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \
20806 * This bit must be '1' for the t_l3_addr field to be
20809 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \
20812 * This bit must be '1' for the tunnel_type field to be
20815 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
20818 * This bit must be '1' for the vni field to be
20821 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \
20824 * This bit must be '1' for the dst_vnic_id field to be
20827 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \
20830 * This bit must be '1' for the mirror_vnic_id field to be
20833 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
20836 * This value identifies a set of CFA data structures used for an L2
20839 uint64_t l2_filter_id;
20841 * This value sets the match value for the inner L2
20843 * Destination MAC address for RX path.
20844 * Source MAC address for TX path.
20846 uint8_t l2_addr[6];
20848 * This value sets VLAN ID value for inner VLAN.
20849 * Only 12-bits of VLAN ID are used in setting the filter.
20853 * The value of inner destination IP address to be used in filtering.
20854 * For IPv4, first four bytes represent the IP address.
20856 uint32_t l3_addr[4];
20858 * The value of tunnel destination IP address to be used in filtering.
20859 * For IPv4, first four bytes represent the IP address.
20861 uint32_t t_l3_addr[4];
20863 * This value indicates the type of inner IP address.
20866 * All others are invalid.
20868 uint8_t l3_addr_type;
20870 * This value indicates the type of tunnel IP address.
20873 * All others are invalid.
20875 uint8_t t_l3_addr_type;
20877 uint8_t tunnel_type;
20879 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
20881 /* Virtual eXtensible Local Area Network (VXLAN) */
20882 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
20884 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
20885 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
20887 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
20888 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
20891 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
20893 /* Generic Network Virtualization Encapsulation (Geneve) */
20894 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
20896 /* Multi-Protocol Lable Switching (MPLS) */
20897 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
20899 /* Stateless Transport Tunnel (STT) */
20900 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
20902 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
20903 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
20905 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
20906 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
20908 /* Any tunneled traffic */
20909 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
20911 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
20912 HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
20914 * tunnel_flags allows the user to indicate the tunnel tag detection
20915 * for the tunnel type specified in tunnel_type.
20917 uint8_t tunnel_flags;
20919 * If the tunnel_type is geneve, then this bit indicates if we
20920 * need to match the geneve OAM packet.
20921 * If the tunnel_type is nvgre or gre, then this bit indicates if
20922 * we need to detect checksum present bit in geneve header.
20923 * If the tunnel_type is mpls, then this bit indicates if we need
20924 * to match mpls packet with explicit IPV4/IPV6 null header.
20926 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \
20929 * If the tunnel_type is geneve, then this bit indicates if we
20930 * need to detect the critical option bit set in the oam packet.
20931 * If the tunnel_type is nvgre or gre, then this bit indicates
20932 * if we need to match nvgre packets with key present bit set in
20934 * If the tunnel_type is mpls, then this bit indicates if we
20935 * need to match mpls packet with S bit from inner/second label.
20937 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \
20940 * If the tunnel_type is geneve, then this bit indicates if we
20941 * need to match geneve packet with extended header bit set in
20943 * If the tunnel_type is nvgre or gre, then this bit indicates
20944 * if we need to match nvgre packets with sequence number
20945 * present bit set in gre header.
20946 * If the tunnel_type is mpls, then this bit indicates if we
20947 * need to match mpls packet with S bit from out/first label.
20949 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \
20952 * Virtual Network Identifier (VNI). Only valid with
20953 * tunnel_types VXLAN, NVGRE, and Geneve.
20954 * Only lower 24-bits of VNI field are used
20955 * in setting up the filter.
20958 /* Logical VNIC ID of the destination VNIC. */
20959 uint32_t dst_vnic_id;
20961 * Logical VNIC ID of the VNIC where traffic is
20964 uint32_t mirror_vnic_id;
20965 } __attribute__((packed));
20967 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */
20968 struct hwrm_cfa_tunnel_filter_alloc_output {
20969 /* The specific error status for the command. */
20970 uint16_t error_code;
20971 /* The HWRM command request type. */
20973 /* The sequence ID from the original command. */
20975 /* The length of the response data in number of bytes. */
20977 /* This value is an opaque id into CFA data structures. */
20978 uint64_t tunnel_filter_id;
20980 * This is the ID of the flow associated with this
20982 * This value shall be used to match and associate the
20983 * flow identifier returned in completion records.
20984 * A value of 0xFFFFFFFF shall indicate no flow id.
20987 uint8_t unused_0[3];
20989 * This field is used in Output records to indicate that the output
20990 * is completely written to RAM. This field should be read as '1'
20991 * to indicate that the output has been completely written.
20992 * When writing a command completion or response to an internal processor,
20993 * the order of writes has to be such that this field is written last.
20996 } __attribute__((packed));
20998 /*******************************
20999 * hwrm_cfa_tunnel_filter_free *
21000 *******************************/
21003 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */
21004 struct hwrm_cfa_tunnel_filter_free_input {
21005 /* The HWRM command request type. */
21008 * The completion ring to send the completion event on. This should
21009 * be the NQ ID returned from the `nq_alloc` HWRM command.
21011 uint16_t cmpl_ring;
21013 * The sequence ID is used by the driver for tracking multiple
21014 * commands. This ID is treated as opaque data by the firmware and
21015 * the value is returned in the `hwrm_resp_hdr` upon completion.
21019 * The target ID of the command:
21020 * * 0x0-0xFFF8 - The function ID
21021 * * 0xFFF8-0xFFFE - Reserved for internal processors
21024 uint16_t target_id;
21026 * A physical address pointer pointing to a host buffer that the
21027 * command's response data will be written. This can be either a host
21028 * physical address (HPA) or a guest physical address (GPA) and must
21029 * point to a physically contiguous block of memory.
21031 uint64_t resp_addr;
21032 /* This value is an opaque id into CFA data structures. */
21033 uint64_t tunnel_filter_id;
21034 } __attribute__((packed));
21036 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */
21037 struct hwrm_cfa_tunnel_filter_free_output {
21038 /* The specific error status for the command. */
21039 uint16_t error_code;
21040 /* The HWRM command request type. */
21042 /* The sequence ID from the original command. */
21044 /* The length of the response data in number of bytes. */
21046 uint8_t unused_0[7];
21048 * This field is used in Output records to indicate that the output
21049 * is completely written to RAM. This field should be read as '1'
21050 * to indicate that the output has been completely written.
21051 * When writing a command completion or response to an internal processor,
21052 * the order of writes has to be such that this field is written last.
21055 } __attribute__((packed));
21057 /***************************************
21058 * hwrm_cfa_redirect_tunnel_type_alloc *
21059 ***************************************/
21062 /* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */
21063 struct hwrm_cfa_redirect_tunnel_type_alloc_input {
21064 /* The HWRM command request type. */
21067 * The completion ring to send the completion event on. This should
21068 * be the NQ ID returned from the `nq_alloc` HWRM command.
21070 uint16_t cmpl_ring;
21072 * The sequence ID is used by the driver for tracking multiple
21073 * commands. This ID is treated as opaque data by the firmware and
21074 * the value is returned in the `hwrm_resp_hdr` upon completion.
21078 * The target ID of the command:
21079 * * 0x0-0xFFF8 - The function ID
21080 * * 0xFFF8-0xFFFE - Reserved for internal processors
21083 uint16_t target_id;
21085 * A physical address pointer pointing to a host buffer that the
21086 * command's response data will be written. This can be either a host
21087 * physical address (HPA) or a guest physical address (GPA) and must
21088 * point to a physically contiguous block of memory.
21090 uint64_t resp_addr;
21091 /* The destination function id, to whom the traffic is redirected. */
21094 uint8_t tunnel_type;
21096 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21098 /* Virtual eXtensible Local Area Network (VXLAN) */
21099 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21101 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21102 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21104 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21105 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21108 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21110 /* Generic Network Virtualization Encapsulation (Geneve) */
21111 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21113 /* Multi-Protocol Lable Switching (MPLS) */
21114 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21116 /* Stateless Transport Tunnel (STT) */
21117 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \
21119 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21120 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21122 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21123 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21125 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21126 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21128 /* Any tunneled traffic */
21129 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21131 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21132 HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21133 /* Tunnel alloc flags. */
21135 /* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */
21136 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \
21138 uint8_t unused_0[4];
21139 } __attribute__((packed));
21141 /* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */
21142 struct hwrm_cfa_redirect_tunnel_type_alloc_output {
21143 /* The specific error status for the command. */
21144 uint16_t error_code;
21145 /* The HWRM command request type. */
21147 /* The sequence ID from the original command. */
21149 /* The length of the response data in number of bytes. */
21151 uint8_t unused_0[7];
21153 * This field is used in Output records to indicate that the output
21154 * is completely written to RAM. This field should be read as '1'
21155 * to indicate that the output has been completely written.
21156 * When writing a command completion or response to an internal processor,
21157 * the order of writes has to be such that this field is written last.
21160 } __attribute__((packed));
21162 /**************************************
21163 * hwrm_cfa_redirect_tunnel_type_free *
21164 **************************************/
21167 /* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */
21168 struct hwrm_cfa_redirect_tunnel_type_free_input {
21169 /* The HWRM command request type. */
21172 * The completion ring to send the completion event on. This should
21173 * be the NQ ID returned from the `nq_alloc` HWRM command.
21175 uint16_t cmpl_ring;
21177 * The sequence ID is used by the driver for tracking multiple
21178 * commands. This ID is treated as opaque data by the firmware and
21179 * the value is returned in the `hwrm_resp_hdr` upon completion.
21183 * The target ID of the command:
21184 * * 0x0-0xFFF8 - The function ID
21185 * * 0xFFF8-0xFFFE - Reserved for internal processors
21188 uint16_t target_id;
21190 * A physical address pointer pointing to a host buffer that the
21191 * command's response data will be written. This can be either a host
21192 * physical address (HPA) or a guest physical address (GPA) and must
21193 * point to a physically contiguous block of memory.
21195 uint64_t resp_addr;
21196 /* The destination function id, to whom the traffic is redirected. */
21199 uint8_t tunnel_type;
21201 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \
21203 /* Virtual eXtensible Local Area Network (VXLAN) */
21204 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \
21206 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21207 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \
21209 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21210 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \
21213 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \
21215 /* Generic Network Virtualization Encapsulation (Geneve) */
21216 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \
21218 /* Multi-Protocol Lable Switching (MPLS) */
21219 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \
21221 /* Stateless Transport Tunnel (STT) */
21222 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \
21224 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \
21227 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21228 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21230 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21233 /* Any tunneled traffic */
21234 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21236 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \
21237 HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL
21238 uint8_t unused_0[5];
21239 } __attribute__((packed));
21241 /* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */
21242 struct hwrm_cfa_redirect_tunnel_type_free_output {
21243 /* The specific error status for the command. */
21244 uint16_t error_code;
21245 /* The HWRM command request type. */
21247 /* The sequence ID from the original command. */
21249 /* The length of the response data in number of bytes. */
21251 uint8_t unused_0[7];
21253 * This field is used in Output records to indicate that the output
21254 * is completely written to RAM. This field should be read as '1'
21255 * to indicate that the output has been completely written.
21256 * When writing a command completion or response to an internal processor,
21257 * the order of writes has to be such that this field is written last.
21260 } __attribute__((packed));
21262 /**************************************
21263 * hwrm_cfa_redirect_tunnel_type_info *
21264 **************************************/
21267 /* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */
21268 struct hwrm_cfa_redirect_tunnel_type_info_input {
21269 /* The HWRM command request type. */
21272 * The completion ring to send the completion event on. This should
21273 * be the NQ ID returned from the `nq_alloc` HWRM command.
21275 uint16_t cmpl_ring;
21277 * The sequence ID is used by the driver for tracking multiple
21278 * commands. This ID is treated as opaque data by the firmware and
21279 * the value is returned in the `hwrm_resp_hdr` upon completion.
21283 * The target ID of the command:
21284 * * 0x0-0xFFF8 - The function ID
21285 * * 0xFFF8-0xFFFE - Reserved for internal processors
21288 uint16_t target_id;
21290 * A physical address pointer pointing to a host buffer that the
21291 * command's response data will be written. This can be either a host
21292 * physical address (HPA) or a guest physical address (GPA) and must
21293 * point to a physically contiguous block of memory.
21295 uint64_t resp_addr;
21296 /* The source function id. */
21299 uint8_t tunnel_type;
21301 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \
21303 /* Virtual eXtensible Local Area Network (VXLAN) */
21304 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \
21306 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21307 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \
21309 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21310 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \
21313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \
21315 /* Generic Network Virtualization Encapsulation (Geneve) */
21316 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \
21318 /* Multi-Protocol Lable Switching (MPLS) */
21319 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \
21321 /* Stateless Transport Tunnel (STT) */
21322 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \
21324 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21325 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \
21327 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21328 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21330 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
21331 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
21333 /* Any tunneled traffic */
21334 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21336 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \
21337 HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL
21338 uint8_t unused_0[5];
21339 } __attribute__((packed));
21341 /* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */
21342 struct hwrm_cfa_redirect_tunnel_type_info_output {
21343 /* The specific error status for the command. */
21344 uint16_t error_code;
21345 /* The HWRM command request type. */
21347 /* The sequence ID from the original command. */
21349 /* The length of the response data in number of bytes. */
21351 /* The destination function id, to whom the traffic is redirected. */
21353 uint8_t unused_0[5];
21355 * This field is used in Output records to indicate that the output
21356 * is completely written to RAM. This field should be read as '1'
21357 * to indicate that the output has been completely written.
21358 * When writing a command completion or response to an internal processor,
21359 * the order of writes has to be such that this field is written last.
21362 } __attribute__((packed));
21364 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */
21365 struct hwrm_vxlan_ipv4_hdr {
21366 /* IPv4 version and header length. */
21368 /* IPv4 header length */
21369 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
21370 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
21372 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
21373 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4
21374 /* IPv4 type of service. */
21376 /* IPv4 identification. */
21378 /* IPv4 flags and offset. */
21379 uint16_t flags_frag_offset;
21382 /* IPv4 protocol. */
21384 /* IPv4 source address. */
21385 uint32_t src_ip_addr;
21386 /* IPv4 destination address. */
21387 uint32_t dest_ip_addr;
21388 } __attribute__((packed));
21390 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */
21391 struct hwrm_vxlan_ipv6_hdr {
21392 /* IPv6 version, traffic class and flow label. */
21393 uint32_t ver_tc_flow_label;
21394 /* IPv6 version shift */
21395 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \
21397 /* IPv6 version mask */
21398 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \
21399 UINT32_C(0xf0000000)
21400 /* IPv6 TC shift */
21401 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \
21404 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \
21405 UINT32_C(0xff00000)
21406 /* IPv6 flow label shift */
21407 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \
21409 /* IPv6 flow label mask */
21410 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \
21412 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \
21413 HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
21414 /* IPv6 payload length. */
21415 uint16_t payload_len;
21416 /* IPv6 next header. */
21420 /* IPv6 source address. */
21421 uint32_t src_ip_addr[4];
21422 /* IPv6 destination address. */
21423 uint32_t dest_ip_addr[4];
21424 } __attribute__((packed));
21426 /* hwrm_cfa_encap_data_vxlan (size:576b/72B) */
21427 struct hwrm_cfa_encap_data_vxlan {
21428 /* Source MAC address. */
21429 uint8_t src_mac_addr[6];
21432 /* Destination MAC address. */
21433 uint8_t dst_mac_addr[6];
21434 /* Number of VLAN tags. */
21435 uint8_t num_vlan_tags;
21438 /* Outer VLAN TPID. */
21439 uint16_t ovlan_tpid;
21440 /* Outer VLAN TCI. */
21441 uint16_t ovlan_tci;
21442 /* Inner VLAN TPID. */
21443 uint16_t ivlan_tpid;
21444 /* Inner VLAN TCI. */
21445 uint16_t ivlan_tci;
21446 /* L3 header fields. */
21448 /* IP version mask. */
21449 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
21450 /* IP version 4. */
21451 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
21452 /* IP version 6. */
21453 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
21454 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \
21455 HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6
21456 /* UDP source port. */
21458 /* UDP destination port. */
21460 /* VXLAN Network Identifier. */
21462 } __attribute__((packed));
21464 /*******************************
21465 * hwrm_cfa_encap_record_alloc *
21466 *******************************/
21469 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */
21470 struct hwrm_cfa_encap_record_alloc_input {
21471 /* The HWRM command request type. */
21474 * The completion ring to send the completion event on. This should
21475 * be the NQ ID returned from the `nq_alloc` HWRM command.
21477 uint16_t cmpl_ring;
21479 * The sequence ID is used by the driver for tracking multiple
21480 * commands. This ID is treated as opaque data by the firmware and
21481 * the value is returned in the `hwrm_resp_hdr` upon completion.
21485 * The target ID of the command:
21486 * * 0x0-0xFFF8 - The function ID
21487 * * 0xFFF8-0xFFFE - Reserved for internal processors
21490 uint16_t target_id;
21492 * A physical address pointer pointing to a host buffer that the
21493 * command's response data will be written. This can be either a host
21494 * physical address (HPA) or a guest physical address (GPA) and must
21495 * point to a physically contiguous block of memory.
21497 uint64_t resp_addr;
21499 /* Setting of this flag indicates the applicability to the loopback path. */
21500 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
21502 /* Encapsulation Type. */
21503 uint8_t encap_type;
21504 /* Virtual eXtensible Local Area Network (VXLAN) */
21505 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \
21507 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21508 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \
21510 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
21511 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \
21514 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \
21516 /* Generic Network Virtualization Encapsulation (Geneve) */
21517 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \
21519 /* Multi-Protocol Lable Switching (MPLS) */
21520 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \
21523 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \
21525 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21526 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \
21528 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
21529 HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE
21530 uint8_t unused_0[3];
21531 /* This value is encap data used for the given encap type. */
21532 uint32_t encap_data[20];
21533 } __attribute__((packed));
21535 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */
21536 struct hwrm_cfa_encap_record_alloc_output {
21537 /* The specific error status for the command. */
21538 uint16_t error_code;
21539 /* The HWRM command request type. */
21541 /* The sequence ID from the original command. */
21543 /* The length of the response data in number of bytes. */
21545 /* This value is an opaque id into CFA data structures. */
21546 uint32_t encap_record_id;
21547 uint8_t unused_0[3];
21549 * This field is used in Output records to indicate that the output
21550 * is completely written to RAM. This field should be read as '1'
21551 * to indicate that the output has been completely written.
21552 * When writing a command completion or response to an internal processor,
21553 * the order of writes has to be such that this field is written last.
21556 } __attribute__((packed));
21558 /******************************
21559 * hwrm_cfa_encap_record_free *
21560 ******************************/
21563 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */
21564 struct hwrm_cfa_encap_record_free_input {
21565 /* The HWRM command request type. */
21568 * The completion ring to send the completion event on. This should
21569 * be the NQ ID returned from the `nq_alloc` HWRM command.
21571 uint16_t cmpl_ring;
21573 * The sequence ID is used by the driver for tracking multiple
21574 * commands. This ID is treated as opaque data by the firmware and
21575 * the value is returned in the `hwrm_resp_hdr` upon completion.
21579 * The target ID of the command:
21580 * * 0x0-0xFFF8 - The function ID
21581 * * 0xFFF8-0xFFFE - Reserved for internal processors
21584 uint16_t target_id;
21586 * A physical address pointer pointing to a host buffer that the
21587 * command's response data will be written. This can be either a host
21588 * physical address (HPA) or a guest physical address (GPA) and must
21589 * point to a physically contiguous block of memory.
21591 uint64_t resp_addr;
21592 /* This value is an opaque id into CFA data structures. */
21593 uint32_t encap_record_id;
21594 uint8_t unused_0[4];
21595 } __attribute__((packed));
21597 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */
21598 struct hwrm_cfa_encap_record_free_output {
21599 /* The specific error status for the command. */
21600 uint16_t error_code;
21601 /* The HWRM command request type. */
21603 /* The sequence ID from the original command. */
21605 /* The length of the response data in number of bytes. */
21607 uint8_t unused_0[7];
21609 * This field is used in Output records to indicate that the output
21610 * is completely written to RAM. This field should be read as '1'
21611 * to indicate that the output has been completely written.
21612 * When writing a command completion or response to an internal processor,
21613 * the order of writes has to be such that this field is written last.
21616 } __attribute__((packed));
21618 /********************************
21619 * hwrm_cfa_ntuple_filter_alloc *
21620 ********************************/
21623 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
21624 struct hwrm_cfa_ntuple_filter_alloc_input {
21625 /* The HWRM command request type. */
21628 * The completion ring to send the completion event on. This should
21629 * be the NQ ID returned from the `nq_alloc` HWRM command.
21631 uint16_t cmpl_ring;
21633 * The sequence ID is used by the driver for tracking multiple
21634 * commands. This ID is treated as opaque data by the firmware and
21635 * the value is returned in the `hwrm_resp_hdr` upon completion.
21639 * The target ID of the command:
21640 * * 0x0-0xFFF8 - The function ID
21641 * * 0xFFF8-0xFFFE - Reserved for internal processors
21644 uint16_t target_id;
21646 * A physical address pointer pointing to a host buffer that the
21647 * command's response data will be written. This can be either a host
21648 * physical address (HPA) or a guest physical address (GPA) and must
21649 * point to a physically contiguous block of memory.
21651 uint64_t resp_addr;
21653 /* Setting of this flag indicates the applicability to the loopback path. */
21654 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \
21657 * Setting of this flag indicates drop action. If this flag is not set,
21658 * then it should be considered accept action.
21660 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \
21663 * Setting of this flag indicates that a meter is expected to be attached
21664 * to this flow. This hint can be used when choosing the action record
21665 * format required for the flow.
21667 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
21671 * This bit must be '1' for the l2_filter_id field to be
21674 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
21677 * This bit must be '1' for the ethertype field to be
21680 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
21683 * This bit must be '1' for the tunnel_type field to be
21686 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
21689 * This bit must be '1' for the src_macaddr field to be
21692 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
21695 * This bit must be '1' for the ipaddr_type field to be
21698 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
21701 * This bit must be '1' for the src_ipaddr field to be
21704 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
21707 * This bit must be '1' for the src_ipaddr_mask field to be
21710 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \
21713 * This bit must be '1' for the dst_ipaddr field to be
21716 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
21719 * This bit must be '1' for the dst_ipaddr_mask field to be
21722 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \
21725 * This bit must be '1' for the ip_protocol field to be
21728 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
21731 * This bit must be '1' for the src_port field to be
21734 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
21737 * This bit must be '1' for the src_port_mask field to be
21740 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \
21743 * This bit must be '1' for the dst_port field to be
21746 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
21749 * This bit must be '1' for the dst_port_mask field to be
21752 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \
21755 * This bit must be '1' for the pri_hint field to be
21758 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \
21761 * This bit must be '1' for the ntuple_filter_id field to be
21764 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \
21767 * This bit must be '1' for the dst_id field to be
21770 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
21773 * This bit must be '1' for the mirror_vnic_id field to be
21776 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
21779 * This bit must be '1' for the dst_macaddr field to be
21782 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
21785 * This value identifies a set of CFA data structures used for an L2
21788 uint64_t l2_filter_id;
21790 * This value indicates the source MAC address in
21791 * the Ethernet header.
21793 uint8_t src_macaddr[6];
21794 /* This value indicates the ethertype in the Ethernet header. */
21795 uint16_t ethertype;
21797 * This value indicates the type of IP address.
21800 * All others are invalid.
21802 uint8_t ip_addr_type;
21804 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
21807 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
21810 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
21812 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
21813 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
21815 * The value of protocol filed in IP header.
21816 * Applies to UDP and TCP traffic.
21820 uint8_t ip_protocol;
21822 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
21825 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
21828 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
21830 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
21831 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
21833 * If set, this value shall represent the
21834 * Logical VNIC ID of the destination VNIC for the RX
21835 * path and network port id of the destination port for
21840 * Logical VNIC ID of the VNIC where traffic is
21843 uint16_t mirror_vnic_id;
21845 * This value indicates the tunnel type for this filter.
21846 * If this field is not specified, then the filter shall
21847 * apply to both non-tunneled and tunneled packets.
21848 * If this field conflicts with the tunnel_type specified
21849 * in the l2_filter_id, then the HWRM shall return an
21850 * error for this command.
21852 uint8_t tunnel_type;
21854 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
21856 /* Virtual eXtensible Local Area Network (VXLAN) */
21857 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
21859 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
21860 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
21862 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
21863 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
21866 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
21868 /* Generic Network Virtualization Encapsulation (Geneve) */
21869 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
21871 /* Multi-Protocol Lable Switching (MPLS) */
21872 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
21874 /* Stateless Transport Tunnel (STT) */
21875 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
21877 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
21878 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
21880 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
21881 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
21883 /* Any tunneled traffic */
21884 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
21886 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
21887 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
21889 * This hint is provided to help in placing
21890 * the filter in the filter table.
21893 /* No preference */
21894 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \
21896 /* Above the given filter */
21897 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \
21899 /* Below the given filter */
21900 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \
21902 /* As high as possible */
21903 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \
21905 /* As low as possible */
21906 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \
21908 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \
21909 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST
21911 * The value of source IP address to be used in filtering.
21912 * For IPv4, first four bytes represent the IP address.
21914 uint32_t src_ipaddr[4];
21916 * The value of source IP address mask to be used in
21918 * For IPv4, first four bytes represent the IP address mask.
21920 uint32_t src_ipaddr_mask[4];
21922 * The value of destination IP address to be used in filtering.
21923 * For IPv4, first four bytes represent the IP address.
21925 uint32_t dst_ipaddr[4];
21927 * The value of destination IP address mask to be used in
21929 * For IPv4, first four bytes represent the IP address mask.
21931 uint32_t dst_ipaddr_mask[4];
21933 * The value of source port to be used in filtering.
21934 * Applies to UDP and TCP traffic.
21938 * The value of source port mask to be used in filtering.
21939 * Applies to UDP and TCP traffic.
21941 uint16_t src_port_mask;
21943 * The value of destination port to be used in filtering.
21944 * Applies to UDP and TCP traffic.
21948 * The value of destination port mask to be used in
21950 * Applies to UDP and TCP traffic.
21952 uint16_t dst_port_mask;
21954 * This is the ID of the filter that goes along with
21957 uint64_t ntuple_filter_id_hint;
21958 } __attribute__((packed));
21960 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
21961 struct hwrm_cfa_ntuple_filter_alloc_output {
21962 /* The specific error status for the command. */
21963 uint16_t error_code;
21964 /* The HWRM command request type. */
21966 /* The sequence ID from the original command. */
21968 /* The length of the response data in number of bytes. */
21970 /* This value is an opaque id into CFA data structures. */
21971 uint64_t ntuple_filter_id;
21973 * This is the ID of the flow associated with this
21975 * This value shall be used to match and associate the
21976 * flow identifier returned in completion records.
21977 * A value of 0xFFFFFFFF shall indicate no flow id.
21980 uint8_t unused_0[3];
21982 * This field is used in Output records to indicate that the output
21983 * is completely written to RAM. This field should be read as '1'
21984 * to indicate that the output has been completely written.
21985 * When writing a command completion or response to an internal processor,
21986 * the order of writes has to be such that this field is written last.
21989 } __attribute__((packed));
21991 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */
21992 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
21994 * command specific error codes that goes to
21995 * the cmd_err field in Common HWRM Error Response.
21998 /* Unknown error */
21999 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \
22001 /* Unable to complete operation due to conflict with Rx Mask VLAN */
22002 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \
22004 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \
22005 HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR
22006 uint8_t unused_0[7];
22007 } __attribute__((packed));
22009 /*******************************
22010 * hwrm_cfa_ntuple_filter_free *
22011 *******************************/
22014 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */
22015 struct hwrm_cfa_ntuple_filter_free_input {
22016 /* The HWRM command request type. */
22019 * The completion ring to send the completion event on. This should
22020 * be the NQ ID returned from the `nq_alloc` HWRM command.
22022 uint16_t cmpl_ring;
22024 * The sequence ID is used by the driver for tracking multiple
22025 * commands. This ID is treated as opaque data by the firmware and
22026 * the value is returned in the `hwrm_resp_hdr` upon completion.
22030 * The target ID of the command:
22031 * * 0x0-0xFFF8 - The function ID
22032 * * 0xFFF8-0xFFFE - Reserved for internal processors
22035 uint16_t target_id;
22037 * A physical address pointer pointing to a host buffer that the
22038 * command's response data will be written. This can be either a host
22039 * physical address (HPA) or a guest physical address (GPA) and must
22040 * point to a physically contiguous block of memory.
22042 uint64_t resp_addr;
22043 /* This value is an opaque id into CFA data structures. */
22044 uint64_t ntuple_filter_id;
22045 } __attribute__((packed));
22047 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */
22048 struct hwrm_cfa_ntuple_filter_free_output {
22049 /* The specific error status for the command. */
22050 uint16_t error_code;
22051 /* The HWRM command request type. */
22053 /* The sequence ID from the original command. */
22055 /* The length of the response data in number of bytes. */
22057 uint8_t unused_0[7];
22059 * This field is used in Output records to indicate that the output
22060 * is completely written to RAM. This field should be read as '1'
22061 * to indicate that the output has been completely written.
22062 * When writing a command completion or response to an internal processor,
22063 * the order of writes has to be such that this field is written last.
22066 } __attribute__((packed));
22068 /******************************
22069 * hwrm_cfa_ntuple_filter_cfg *
22070 ******************************/
22073 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */
22074 struct hwrm_cfa_ntuple_filter_cfg_input {
22075 /* The HWRM command request type. */
22078 * The completion ring to send the completion event on. This should
22079 * be the NQ ID returned from the `nq_alloc` HWRM command.
22081 uint16_t cmpl_ring;
22083 * The sequence ID is used by the driver for tracking multiple
22084 * commands. This ID is treated as opaque data by the firmware and
22085 * the value is returned in the `hwrm_resp_hdr` upon completion.
22089 * The target ID of the command:
22090 * * 0x0-0xFFF8 - The function ID
22091 * * 0xFFF8-0xFFFE - Reserved for internal processors
22094 uint16_t target_id;
22096 * A physical address pointer pointing to a host buffer that the
22097 * command's response data will be written. This can be either a host
22098 * physical address (HPA) or a guest physical address (GPA) and must
22099 * point to a physically contiguous block of memory.
22101 uint64_t resp_addr;
22104 * This bit must be '1' for the new_dst_id field to be
22107 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \
22110 * This bit must be '1' for the new_mirror_vnic_id field to be
22113 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
22116 * This bit must be '1' for the new_meter_instance_id field to be
22119 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
22121 uint8_t unused_0[4];
22122 /* This value is an opaque id into CFA data structures. */
22123 uint64_t ntuple_filter_id;
22125 * If set, this value shall represent the new
22126 * Logical VNIC ID of the destination VNIC for the RX
22127 * path and new network port id of the destination port for
22130 uint32_t new_dst_id;
22132 * New Logical VNIC ID of the VNIC where traffic is
22135 uint32_t new_mirror_vnic_id;
22137 * New meter to attach to the flow. Specifying the
22138 * invalid instance ID is used to remove any existing
22139 * meter from the flow.
22141 uint16_t new_meter_instance_id;
22143 * A value of 0xfff is considered invalid and implies the
22144 * instance is not configured.
22146 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
22148 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
22149 HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
22150 uint8_t unused_1[6];
22151 } __attribute__((packed));
22153 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */
22154 struct hwrm_cfa_ntuple_filter_cfg_output {
22155 /* The specific error status for the command. */
22156 uint16_t error_code;
22157 /* The HWRM command request type. */
22159 /* The sequence ID from the original command. */
22161 /* The length of the response data in number of bytes. */
22163 uint8_t unused_0[7];
22165 * This field is used in Output records to indicate that the output
22166 * is completely written to RAM. This field should be read as '1'
22167 * to indicate that the output has been completely written.
22168 * When writing a command completion or response to an internal processor,
22169 * the order of writes has to be such that this field is written last.
22172 } __attribute__((packed));
22174 /**************************
22175 * hwrm_cfa_em_flow_alloc *
22176 **************************/
22179 /* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */
22180 struct hwrm_cfa_em_flow_alloc_input {
22181 /* The HWRM command request type. */
22184 * The completion ring to send the completion event on. This should
22185 * be the NQ ID returned from the `nq_alloc` HWRM command.
22187 uint16_t cmpl_ring;
22189 * The sequence ID is used by the driver for tracking multiple
22190 * commands. This ID is treated as opaque data by the firmware and
22191 * the value is returned in the `hwrm_resp_hdr` upon completion.
22195 * The target ID of the command:
22196 * * 0x0-0xFFF8 - The function ID
22197 * * 0xFFF8-0xFFFE - Reserved for internal processors
22200 uint16_t target_id;
22202 * A physical address pointer pointing to a host buffer that the
22203 * command's response data will be written. This can be either a host
22204 * physical address (HPA) or a guest physical address (GPA) and must
22205 * point to a physically contiguous block of memory.
22207 uint64_t resp_addr;
22210 * Enumeration denoting the RX, TX type of the resource.
22211 * This enumeration is used for resources that are similar for both
22212 * TX and RX paths of the chip.
22214 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
22216 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
22218 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
22219 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \
22220 HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
22222 * Setting of this flag indicates enabling of a byte counter for a given
22225 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
22227 * Setting of this flag indicates enabling of a packet counter for a given
22230 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
22231 /* Setting of this flag indicates de-capsulation action for the given flow. */
22232 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
22233 /* Setting of this flag indicates encapsulation action for the given flow. */
22234 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
22236 * Setting of this flag indicates drop action. If this flag is not set,
22237 * then it should be considered accept action.
22239 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
22241 * Setting of this flag indicates that a meter is expected to be attached
22242 * to this flow. This hint can be used when choosing the action record
22243 * format required for the flow.
22245 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
22248 * This bit must be '1' for the l2_filter_id field to be
22251 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \
22254 * This bit must be '1' for the tunnel_type field to be
22257 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
22260 * This bit must be '1' for the tunnel_id field to be
22263 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \
22266 * This bit must be '1' for the src_macaddr field to be
22269 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \
22272 * This bit must be '1' for the dst_macaddr field to be
22275 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \
22278 * This bit must be '1' for the ovlan_vid field to be
22281 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \
22284 * This bit must be '1' for the ivlan_vid field to be
22287 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \
22290 * This bit must be '1' for the ethertype field to be
22293 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \
22296 * This bit must be '1' for the src_ipaddr field to be
22299 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \
22302 * This bit must be '1' for the dst_ipaddr field to be
22305 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \
22308 * This bit must be '1' for the ipaddr_type field to be
22311 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
22314 * This bit must be '1' for the ip_protocol field to be
22317 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
22320 * This bit must be '1' for the src_port field to be
22323 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \
22326 * This bit must be '1' for the dst_port field to be
22329 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \
22332 * This bit must be '1' for the dst_id field to be
22335 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \
22338 * This bit must be '1' for the mirror_vnic_id field to be
22341 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
22344 * This bit must be '1' for the encap_record_id field to be
22347 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \
22350 * This bit must be '1' for the meter_instance_id field to be
22353 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \
22356 * This value identifies a set of CFA data structures used for an L2
22359 uint64_t l2_filter_id;
22361 uint8_t tunnel_type;
22363 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
22365 /* Virtual eXtensible Local Area Network (VXLAN) */
22366 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
22368 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
22369 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
22371 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
22372 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
22375 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
22377 /* Generic Network Virtualization Encapsulation (Geneve) */
22378 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
22380 /* Multi-Protocol Lable Switching (MPLS) */
22381 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
22383 /* Stateless Transport Tunnel (STT) */
22384 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
22386 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
22387 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
22389 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
22390 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
22392 /* Any tunneled traffic */
22393 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
22395 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
22396 HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
22397 uint8_t unused_0[3];
22399 * Tunnel identifier.
22400 * Virtual Network Identifier (VNI). Only valid with
22401 * tunnel_types VXLAN, NVGRE, and Geneve.
22402 * Only lower 24-bits of VNI field are used
22403 * in setting up the filter.
22405 uint32_t tunnel_id;
22407 * This value indicates the source MAC address in
22408 * the Ethernet header.
22410 uint8_t src_macaddr[6];
22411 /* The meter instance to attach to the flow. */
22412 uint16_t meter_instance_id;
22414 * A value of 0xfff is considered invalid and implies the
22415 * instance is not configured.
22417 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \
22419 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \
22420 HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID
22422 * This value indicates the destination MAC address in
22423 * the Ethernet header.
22425 uint8_t dst_macaddr[6];
22427 * This value indicates the VLAN ID of the outer VLAN tag
22428 * in the Ethernet header.
22430 uint16_t ovlan_vid;
22432 * This value indicates the VLAN ID of the inner VLAN tag
22433 * in the Ethernet header.
22435 uint16_t ivlan_vid;
22436 /* This value indicates the ethertype in the Ethernet header. */
22437 uint16_t ethertype;
22439 * This value indicates the type of IP address.
22442 * All others are invalid.
22444 uint8_t ip_addr_type;
22446 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
22448 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
22450 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
22451 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
22452 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
22454 * The value of protocol filed in IP header.
22455 * Applies to UDP and TCP traffic.
22459 uint8_t ip_protocol;
22461 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
22463 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
22465 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
22466 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \
22467 HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP
22468 uint8_t unused_1[2];
22470 * The value of source IP address to be used in filtering.
22471 * For IPv4, first four bytes represent the IP address.
22473 uint32_t src_ipaddr[4];
22475 * big_endian = True
22476 * The value of destination IP address to be used in filtering.
22477 * For IPv4, first four bytes represent the IP address.
22479 uint32_t dst_ipaddr[4];
22481 * The value of source port to be used in filtering.
22482 * Applies to UDP and TCP traffic.
22486 * The value of destination port to be used in filtering.
22487 * Applies to UDP and TCP traffic.
22491 * If set, this value shall represent the
22492 * Logical VNIC ID of the destination VNIC for the RX
22493 * path and network port id of the destination port for
22498 * Logical VNIC ID of the VNIC where traffic is
22501 uint16_t mirror_vnic_id;
22502 /* Logical ID of the encapsulation record. */
22503 uint32_t encap_record_id;
22504 uint8_t unused_2[4];
22505 } __attribute__((packed));
22507 /* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */
22508 struct hwrm_cfa_em_flow_alloc_output {
22509 /* The specific error status for the command. */
22510 uint16_t error_code;
22511 /* The HWRM command request type. */
22513 /* The sequence ID from the original command. */
22515 /* The length of the response data in number of bytes. */
22517 /* This value is an opaque id into CFA data structures. */
22518 uint64_t em_filter_id;
22520 * This is the ID of the flow associated with this
22522 * This value shall be used to match and associate the
22523 * flow identifier returned in completion records.
22524 * A value of 0xFFFFFFFF shall indicate no flow id.
22527 uint8_t unused_0[3];
22529 * This field is used in Output records to indicate that the output
22530 * is completely written to RAM. This field should be read as '1'
22531 * to indicate that the output has been completely written.
22532 * When writing a command completion or response to an internal processor,
22533 * the order of writes has to be such that this field is written last.
22536 } __attribute__((packed));
22538 /*************************
22539 * hwrm_cfa_em_flow_free *
22540 *************************/
22543 /* hwrm_cfa_em_flow_free_input (size:192b/24B) */
22544 struct hwrm_cfa_em_flow_free_input {
22545 /* The HWRM command request type. */
22548 * The completion ring to send the completion event on. This should
22549 * be the NQ ID returned from the `nq_alloc` HWRM command.
22551 uint16_t cmpl_ring;
22553 * The sequence ID is used by the driver for tracking multiple
22554 * commands. This ID is treated as opaque data by the firmware and
22555 * the value is returned in the `hwrm_resp_hdr` upon completion.
22559 * The target ID of the command:
22560 * * 0x0-0xFFF8 - The function ID
22561 * * 0xFFF8-0xFFFE - Reserved for internal processors
22564 uint16_t target_id;
22566 * A physical address pointer pointing to a host buffer that the
22567 * command's response data will be written. This can be either a host
22568 * physical address (HPA) or a guest physical address (GPA) and must
22569 * point to a physically contiguous block of memory.
22571 uint64_t resp_addr;
22572 /* This value is an opaque id into CFA data structures. */
22573 uint64_t em_filter_id;
22574 } __attribute__((packed));
22576 /* hwrm_cfa_em_flow_free_output (size:128b/16B) */
22577 struct hwrm_cfa_em_flow_free_output {
22578 /* The specific error status for the command. */
22579 uint16_t error_code;
22580 /* The HWRM command request type. */
22582 /* The sequence ID from the original command. */
22584 /* The length of the response data in number of bytes. */
22586 uint8_t unused_0[7];
22588 * This field is used in Output records to indicate that the output
22589 * is completely written to RAM. This field should be read as '1'
22590 * to indicate that the output has been completely written.
22591 * When writing a command completion or response to an internal processor,
22592 * the order of writes has to be such that this field is written last.
22595 } __attribute__((packed));
22597 /************************
22598 * hwrm_cfa_em_flow_cfg *
22599 ************************/
22602 /* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */
22603 struct hwrm_cfa_em_flow_cfg_input {
22604 /* The HWRM command request type. */
22607 * The completion ring to send the completion event on. This should
22608 * be the NQ ID returned from the `nq_alloc` HWRM command.
22610 uint16_t cmpl_ring;
22612 * The sequence ID is used by the driver for tracking multiple
22613 * commands. This ID is treated as opaque data by the firmware and
22614 * the value is returned in the `hwrm_resp_hdr` upon completion.
22618 * The target ID of the command:
22619 * * 0x0-0xFFF8 - The function ID
22620 * * 0xFFF8-0xFFFE - Reserved for internal processors
22623 uint16_t target_id;
22625 * A physical address pointer pointing to a host buffer that the
22626 * command's response data will be written. This can be either a host
22627 * physical address (HPA) or a guest physical address (GPA) and must
22628 * point to a physically contiguous block of memory.
22630 uint64_t resp_addr;
22633 * This bit must be '1' for the new_dst_id field to be
22636 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \
22639 * This bit must be '1' for the new_mirror_vnic_id field to be
22642 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \
22645 * This bit must be '1' for the new_meter_instance_id field to be
22648 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
22650 uint8_t unused_0[4];
22651 /* This value is an opaque id into CFA data structures. */
22652 uint64_t em_filter_id;
22654 * If set, this value shall represent the new
22655 * Logical VNIC ID of the destination VNIC for the RX
22656 * path and network port id of the destination port for
22659 uint32_t new_dst_id;
22661 * New Logical VNIC ID of the VNIC where traffic is
22664 uint32_t new_mirror_vnic_id;
22666 * New meter to attach to the flow. Specifying the
22667 * invalid instance ID is used to remove any existing
22668 * meter from the flow.
22670 uint16_t new_meter_instance_id;
22672 * A value of 0xfff is considered invalid and implies the
22673 * instance is not configured.
22675 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \
22677 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \
22678 HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID
22679 uint8_t unused_1[6];
22680 } __attribute__((packed));
22682 /* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */
22683 struct hwrm_cfa_em_flow_cfg_output {
22684 /* The specific error status for the command. */
22685 uint16_t error_code;
22686 /* The HWRM command request type. */
22688 /* The sequence ID from the original command. */
22690 /* The length of the response data in number of bytes. */
22692 uint8_t unused_0[7];
22694 * This field is used in Output records to indicate that the output
22695 * is completely written to RAM. This field should be read as '1'
22696 * to indicate that the output has been completely written.
22697 * When writing a command completion or response to an internal processor,
22698 * the order of writes has to be such that this field is written last.
22701 } __attribute__((packed));
22703 /********************************
22704 * hwrm_cfa_meter_profile_alloc *
22705 ********************************/
22708 /* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
22709 struct hwrm_cfa_meter_profile_alloc_input {
22710 /* The HWRM command request type. */
22713 * The completion ring to send the completion event on. This should
22714 * be the NQ ID returned from the `nq_alloc` HWRM command.
22716 uint16_t cmpl_ring;
22718 * The sequence ID is used by the driver for tracking multiple
22719 * commands. This ID is treated as opaque data by the firmware and
22720 * the value is returned in the `hwrm_resp_hdr` upon completion.
22724 * The target ID of the command:
22725 * * 0x0-0xFFF8 - The function ID
22726 * * 0xFFF8-0xFFFE - Reserved for internal processors
22729 uint16_t target_id;
22731 * A physical address pointer pointing to a host buffer that the
22732 * command's response data will be written. This can be either a host
22733 * physical address (HPA) or a guest physical address (GPA) and must
22734 * point to a physically contiguous block of memory.
22736 uint64_t resp_addr;
22739 * Enumeration denoting the RX, TX type of the resource.
22740 * This enumeration is used for resources that are similar for both
22741 * TX and RX paths of the chip.
22743 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
22745 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
22748 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
22750 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
22751 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
22752 /* The meter algorithm type. */
22753 uint8_t meter_type;
22754 /* RFC 2697 (srTCM) */
22755 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
22757 /* RFC 2698 (trTCM) */
22758 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
22760 /* RFC 4115 (trTCM) */
22761 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
22763 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
22764 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
22766 * This field is reserved for the future use.
22767 * It shall be set to 0.
22769 uint16_t reserved1;
22771 * This field is reserved for the future use.
22772 * It shall be set to 0.
22774 uint32_t reserved2;
22775 /* A meter rate specified in bytes-per-second. */
22776 uint32_t commit_rate;
22777 /* The bandwidth value. */
22778 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
22779 UINT32_C(0xfffffff)
22780 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
22782 /* The granularity of the value (bits or bytes). */
22783 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
22784 UINT32_C(0x10000000)
22785 /* Value is in bits. */
22786 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
22787 (UINT32_C(0x0) << 28)
22788 /* Value is in bytes. */
22789 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
22790 (UINT32_C(0x1) << 28)
22791 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
22792 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
22793 /* bw_value_unit is 3 b */
22794 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
22795 UINT32_C(0xe0000000)
22796 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
22798 /* Value is in Mb or MB (base 10). */
22799 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
22800 (UINT32_C(0x0) << 29)
22801 /* Value is in Kb or KB (base 10). */
22802 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
22803 (UINT32_C(0x2) << 29)
22804 /* Value is in bits or bytes. */
22805 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
22806 (UINT32_C(0x4) << 29)
22807 /* Value is in Gb or GB (base 10). */
22808 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
22809 (UINT32_C(0x6) << 29)
22810 /* Value is in 1/100th of a percentage of total bandwidth. */
22811 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
22812 (UINT32_C(0x1) << 29)
22814 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
22815 (UINT32_C(0x7) << 29)
22816 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
22817 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
22818 /* A meter burst size specified in bytes. */
22819 uint32_t commit_burst;
22820 /* The bandwidth value. */
22821 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
22822 UINT32_C(0xfffffff)
22823 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
22825 /* The granularity of the value (bits or bytes). */
22826 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
22827 UINT32_C(0x10000000)
22828 /* Value is in bits. */
22829 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
22830 (UINT32_C(0x0) << 28)
22831 /* Value is in bytes. */
22832 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
22833 (UINT32_C(0x1) << 28)
22834 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
22835 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
22836 /* bw_value_unit is 3 b */
22837 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
22838 UINT32_C(0xe0000000)
22839 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
22841 /* Value is in Mb or MB (base 10). */
22842 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
22843 (UINT32_C(0x0) << 29)
22844 /* Value is in Kb or KB (base 10). */
22845 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
22846 (UINT32_C(0x2) << 29)
22847 /* Value is in bits or bytes. */
22848 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
22849 (UINT32_C(0x4) << 29)
22850 /* Value is in Gb or GB (base 10). */
22851 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
22852 (UINT32_C(0x6) << 29)
22853 /* Value is in 1/100th of a percentage of total bandwidth. */
22854 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
22855 (UINT32_C(0x1) << 29)
22857 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
22858 (UINT32_C(0x7) << 29)
22859 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
22860 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
22861 /* A meter rate specified in bytes-per-second. */
22862 uint32_t excess_peak_rate;
22863 /* The bandwidth value. */
22864 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
22865 UINT32_C(0xfffffff)
22866 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
22868 /* The granularity of the value (bits or bytes). */
22869 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
22870 UINT32_C(0x10000000)
22871 /* Value is in bits. */
22872 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
22873 (UINT32_C(0x0) << 28)
22874 /* Value is in bytes. */
22875 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
22876 (UINT32_C(0x1) << 28)
22877 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
22878 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
22879 /* bw_value_unit is 3 b */
22880 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
22881 UINT32_C(0xe0000000)
22882 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
22884 /* Value is in Mb or MB (base 10). */
22885 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
22886 (UINT32_C(0x0) << 29)
22887 /* Value is in Kb or KB (base 10). */
22888 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
22889 (UINT32_C(0x2) << 29)
22890 /* Value is in bits or bytes. */
22891 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
22892 (UINT32_C(0x4) << 29)
22893 /* Value is in Gb or GB (base 10). */
22894 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
22895 (UINT32_C(0x6) << 29)
22896 /* Value is in 1/100th of a percentage of total bandwidth. */
22897 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
22898 (UINT32_C(0x1) << 29)
22900 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
22901 (UINT32_C(0x7) << 29)
22902 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
22903 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
22904 /* A meter burst size specified in bytes. */
22905 uint32_t excess_peak_burst;
22906 /* The bandwidth value. */
22907 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
22908 UINT32_C(0xfffffff)
22909 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
22911 /* The granularity of the value (bits or bytes). */
22912 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
22913 UINT32_C(0x10000000)
22914 /* Value is in bits. */
22915 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
22916 (UINT32_C(0x0) << 28)
22917 /* Value is in bytes. */
22918 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
22919 (UINT32_C(0x1) << 28)
22920 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
22921 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
22922 /* bw_value_unit is 3 b */
22923 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
22924 UINT32_C(0xe0000000)
22925 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
22927 /* Value is in Mb or MB (base 10). */
22928 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
22929 (UINT32_C(0x0) << 29)
22930 /* Value is in Kb or KB (base 10). */
22931 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
22932 (UINT32_C(0x2) << 29)
22933 /* Value is in bits or bytes. */
22934 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
22935 (UINT32_C(0x4) << 29)
22936 /* Value is in Gb or GB (base 10). */
22937 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
22938 (UINT32_C(0x6) << 29)
22939 /* Value is in 1/100th of a percentage of total bandwidth. */
22940 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
22941 (UINT32_C(0x1) << 29)
22943 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
22944 (UINT32_C(0x7) << 29)
22945 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
22946 HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
22947 } __attribute__((packed));
22949 /* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
22950 struct hwrm_cfa_meter_profile_alloc_output {
22951 /* The specific error status for the command. */
22952 uint16_t error_code;
22953 /* The HWRM command request type. */
22955 /* The sequence ID from the original command. */
22957 /* The length of the response data in number of bytes. */
22959 /* This value identifies a meter profile in CFA. */
22960 uint16_t meter_profile_id;
22962 * A value of 0xfff is considered invalid and implies the
22963 * profile is not configured.
22965 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
22967 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
22968 HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
22969 uint8_t unused_0[5];
22971 * This field is used in Output records to indicate that the output
22972 * is completely written to RAM. This field should be read as '1'
22973 * to indicate that the output has been completely written.
22974 * When writing a command completion or response to an internal processor,
22975 * the order of writes has to be such that this field is written last.
22978 } __attribute__((packed));
22980 /*******************************
22981 * hwrm_cfa_meter_profile_free *
22982 *******************************/
22985 /* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
22986 struct hwrm_cfa_meter_profile_free_input {
22987 /* The HWRM command request type. */
22990 * The completion ring to send the completion event on. This should
22991 * be the NQ ID returned from the `nq_alloc` HWRM command.
22993 uint16_t cmpl_ring;
22995 * The sequence ID is used by the driver for tracking multiple
22996 * commands. This ID is treated as opaque data by the firmware and
22997 * the value is returned in the `hwrm_resp_hdr` upon completion.
23001 * The target ID of the command:
23002 * * 0x0-0xFFF8 - The function ID
23003 * * 0xFFF8-0xFFFE - Reserved for internal processors
23006 uint16_t target_id;
23008 * A physical address pointer pointing to a host buffer that the
23009 * command's response data will be written. This can be either a host
23010 * physical address (HPA) or a guest physical address (GPA) and must
23011 * point to a physically contiguous block of memory.
23013 uint64_t resp_addr;
23016 * Enumeration denoting the RX, TX type of the resource.
23017 * This enumeration is used for resources that are similar for both
23018 * TX and RX paths of the chip.
23020 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
23022 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
23025 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
23027 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
23028 HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
23030 /* This value identifies a meter profile in CFA. */
23031 uint16_t meter_profile_id;
23033 * A value of 0xfff is considered invalid and implies the
23034 * profile is not configured.
23036 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
23038 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
23039 HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
23040 uint8_t unused_1[4];
23041 } __attribute__((packed));
23043 /* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
23044 struct hwrm_cfa_meter_profile_free_output {
23045 /* The specific error status for the command. */
23046 uint16_t error_code;
23047 /* The HWRM command request type. */
23049 /* The sequence ID from the original command. */
23051 /* The length of the response data in number of bytes. */
23053 uint8_t unused_0[7];
23055 * This field is used in Output records to indicate that the output
23056 * is completely written to RAM. This field should be read as '1'
23057 * to indicate that the output has been completely written.
23058 * When writing a command completion or response to an internal processor,
23059 * the order of writes has to be such that this field is written last.
23062 } __attribute__((packed));
23064 /******************************
23065 * hwrm_cfa_meter_profile_cfg *
23066 ******************************/
23069 /* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
23070 struct hwrm_cfa_meter_profile_cfg_input {
23071 /* The HWRM command request type. */
23074 * The completion ring to send the completion event on. This should
23075 * be the NQ ID returned from the `nq_alloc` HWRM command.
23077 uint16_t cmpl_ring;
23079 * The sequence ID is used by the driver for tracking multiple
23080 * commands. This ID is treated as opaque data by the firmware and
23081 * the value is returned in the `hwrm_resp_hdr` upon completion.
23085 * The target ID of the command:
23086 * * 0x0-0xFFF8 - The function ID
23087 * * 0xFFF8-0xFFFE - Reserved for internal processors
23090 uint16_t target_id;
23092 * A physical address pointer pointing to a host buffer that the
23093 * command's response data will be written. This can be either a host
23094 * physical address (HPA) or a guest physical address (GPA) and must
23095 * point to a physically contiguous block of memory.
23097 uint64_t resp_addr;
23100 * Enumeration denoting the RX, TX type of the resource.
23101 * This enumeration is used for resources that are similar for both
23102 * TX and RX paths of the chip.
23104 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
23106 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
23108 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
23109 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
23110 HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
23111 /* The meter algorithm type. */
23112 uint8_t meter_type;
23113 /* RFC 2697 (srTCM) */
23114 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
23116 /* RFC 2698 (trTCM) */
23117 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
23119 /* RFC 4115 (trTCM) */
23120 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
23122 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
23123 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
23124 /* This value identifies a meter profile in CFA. */
23125 uint16_t meter_profile_id;
23127 * A value of 0xfff is considered invalid and implies the
23128 * profile is not configured.
23130 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
23132 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
23133 HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
23135 * This field is reserved for the future use.
23136 * It shall be set to 0.
23139 /* A meter rate specified in bytes-per-second. */
23140 uint32_t commit_rate;
23141 /* The bandwidth value. */
23142 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
23143 UINT32_C(0xfffffff)
23144 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
23146 /* The granularity of the value (bits or bytes). */
23147 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
23148 UINT32_C(0x10000000)
23149 /* Value is in bits. */
23150 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
23151 (UINT32_C(0x0) << 28)
23152 /* Value is in bytes. */
23153 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
23154 (UINT32_C(0x1) << 28)
23155 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
23156 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
23157 /* bw_value_unit is 3 b */
23158 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
23159 UINT32_C(0xe0000000)
23160 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
23162 /* Value is in Mb or MB (base 10). */
23163 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
23164 (UINT32_C(0x0) << 29)
23165 /* Value is in Kb or KB (base 10). */
23166 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
23167 (UINT32_C(0x2) << 29)
23168 /* Value is in bits or bytes. */
23169 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
23170 (UINT32_C(0x4) << 29)
23171 /* Value is in Gb or GB (base 10). */
23172 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
23173 (UINT32_C(0x6) << 29)
23174 /* Value is in 1/100th of a percentage of total bandwidth. */
23175 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
23176 (UINT32_C(0x1) << 29)
23178 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
23179 (UINT32_C(0x7) << 29)
23180 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
23181 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
23182 /* A meter burst size specified in bytes. */
23183 uint32_t commit_burst;
23184 /* The bandwidth value. */
23185 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
23186 UINT32_C(0xfffffff)
23187 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
23189 /* The granularity of the value (bits or bytes). */
23190 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
23191 UINT32_C(0x10000000)
23192 /* Value is in bits. */
23193 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
23194 (UINT32_C(0x0) << 28)
23195 /* Value is in bytes. */
23196 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
23197 (UINT32_C(0x1) << 28)
23198 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
23199 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
23200 /* bw_value_unit is 3 b */
23201 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
23202 UINT32_C(0xe0000000)
23203 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
23205 /* Value is in Mb or MB (base 10). */
23206 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
23207 (UINT32_C(0x0) << 29)
23208 /* Value is in Kb or KB (base 10). */
23209 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
23210 (UINT32_C(0x2) << 29)
23211 /* Value is in bits or bytes. */
23212 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
23213 (UINT32_C(0x4) << 29)
23214 /* Value is in Gb or GB (base 10). */
23215 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
23216 (UINT32_C(0x6) << 29)
23217 /* Value is in 1/100th of a percentage of total bandwidth. */
23218 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
23219 (UINT32_C(0x1) << 29)
23221 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
23222 (UINT32_C(0x7) << 29)
23223 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
23224 HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
23225 /* A meter rate specified in bytes-per-second. */
23226 uint32_t excess_peak_rate;
23227 /* The bandwidth value. */
23228 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
23229 UINT32_C(0xfffffff)
23230 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
23232 /* The granularity of the value (bits or bytes). */
23233 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
23234 UINT32_C(0x10000000)
23235 /* Value is in bits. */
23236 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
23237 (UINT32_C(0x0) << 28)
23238 /* Value is in bytes. */
23239 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
23240 (UINT32_C(0x1) << 28)
23241 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
23242 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
23243 /* bw_value_unit is 3 b */
23244 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
23245 UINT32_C(0xe0000000)
23246 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
23248 /* Value is in Mb or MB (base 10). */
23249 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
23250 (UINT32_C(0x0) << 29)
23251 /* Value is in Kb or KB (base 10). */
23252 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
23253 (UINT32_C(0x2) << 29)
23254 /* Value is in bits or bytes. */
23255 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
23256 (UINT32_C(0x4) << 29)
23257 /* Value is in Gb or GB (base 10). */
23258 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
23259 (UINT32_C(0x6) << 29)
23260 /* Value is in 1/100th of a percentage of total bandwidth. */
23261 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
23262 (UINT32_C(0x1) << 29)
23264 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
23265 (UINT32_C(0x7) << 29)
23266 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
23267 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
23268 /* A meter burst size specified in bytes. */
23269 uint32_t excess_peak_burst;
23270 /* The bandwidth value. */
23271 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
23272 UINT32_C(0xfffffff)
23273 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
23275 /* The granularity of the value (bits or bytes). */
23276 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
23277 UINT32_C(0x10000000)
23278 /* Value is in bits. */
23279 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
23280 (UINT32_C(0x0) << 28)
23281 /* Value is in bytes. */
23282 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
23283 (UINT32_C(0x1) << 28)
23284 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
23285 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
23286 /* bw_value_unit is 3 b */
23287 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
23288 UINT32_C(0xe0000000)
23289 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
23291 /* Value is in Mb or MB (base 10). */
23292 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
23293 (UINT32_C(0x0) << 29)
23294 /* Value is in Kb or KB (base 10). */
23295 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
23296 (UINT32_C(0x2) << 29)
23297 /* Value is in bits or bytes. */
23298 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
23299 (UINT32_C(0x4) << 29)
23300 /* Value is in Gb or GB (base 10). */
23301 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
23302 (UINT32_C(0x6) << 29)
23303 /* Value is in 1/100th of a percentage of total bandwidth. */
23304 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
23305 (UINT32_C(0x1) << 29)
23307 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
23308 (UINT32_C(0x7) << 29)
23309 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
23310 HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
23311 } __attribute__((packed));
23313 /* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
23314 struct hwrm_cfa_meter_profile_cfg_output {
23315 /* The specific error status for the command. */
23316 uint16_t error_code;
23317 /* The HWRM command request type. */
23319 /* The sequence ID from the original command. */
23321 /* The length of the response data in number of bytes. */
23323 uint8_t unused_0[7];
23325 * This field is used in Output records to indicate that the output
23326 * is completely written to RAM. This field should be read as '1'
23327 * to indicate that the output has been completely written.
23328 * When writing a command completion or response to an internal processor,
23329 * the order of writes has to be such that this field is written last.
23332 } __attribute__((packed));
23334 /*********************************
23335 * hwrm_cfa_meter_instance_alloc *
23336 *********************************/
23339 /* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
23340 struct hwrm_cfa_meter_instance_alloc_input {
23341 /* The HWRM command request type. */
23344 * The completion ring to send the completion event on. This should
23345 * be the NQ ID returned from the `nq_alloc` HWRM command.
23347 uint16_t cmpl_ring;
23349 * The sequence ID is used by the driver for tracking multiple
23350 * commands. This ID is treated as opaque data by the firmware and
23351 * the value is returned in the `hwrm_resp_hdr` upon completion.
23355 * The target ID of the command:
23356 * * 0x0-0xFFF8 - The function ID
23357 * * 0xFFF8-0xFFFE - Reserved for internal processors
23360 uint16_t target_id;
23362 * A physical address pointer pointing to a host buffer that the
23363 * command's response data will be written. This can be either a host
23364 * physical address (HPA) or a guest physical address (GPA) and must
23365 * point to a physically contiguous block of memory.
23367 uint64_t resp_addr;
23370 * Enumeration denoting the RX, TX type of the resource.
23371 * This enumeration is used for resources that are similar for both
23372 * TX and RX paths of the chip.
23374 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
23377 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
23380 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
23382 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
23383 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
23385 /* This value identifies a meter profile in CFA. */
23386 uint16_t meter_profile_id;
23388 * A value of 0xfff is considered invalid and implies the
23389 * profile is not configured.
23391 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
23393 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
23394 HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
23395 uint8_t unused_1[4];
23396 } __attribute__((packed));
23398 /* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
23399 struct hwrm_cfa_meter_instance_alloc_output {
23400 /* The specific error status for the command. */
23401 uint16_t error_code;
23402 /* The HWRM command request type. */
23404 /* The sequence ID from the original command. */
23406 /* The length of the response data in number of bytes. */
23408 /* This value identifies a meter instance in CFA. */
23409 uint16_t meter_instance_id;
23411 * A value of 0xfff is considered invalid and implies the
23412 * instance is not configured.
23414 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
23416 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
23417 HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
23418 uint8_t unused_0[5];
23420 * This field is used in Output records to indicate that the output
23421 * is completely written to RAM. This field should be read as '1'
23422 * to indicate that the output has been completely written.
23423 * When writing a command completion or response to an internal processor,
23424 * the order of writes has to be such that this field is written last.
23427 } __attribute__((packed));
23429 /********************************
23430 * hwrm_cfa_meter_instance_free *
23431 ********************************/
23434 /* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
23435 struct hwrm_cfa_meter_instance_free_input {
23436 /* The HWRM command request type. */
23439 * The completion ring to send the completion event on. This should
23440 * be the NQ ID returned from the `nq_alloc` HWRM command.
23442 uint16_t cmpl_ring;
23444 * The sequence ID is used by the driver for tracking multiple
23445 * commands. This ID is treated as opaque data by the firmware and
23446 * the value is returned in the `hwrm_resp_hdr` upon completion.
23450 * The target ID of the command:
23451 * * 0x0-0xFFF8 - The function ID
23452 * * 0xFFF8-0xFFFE - Reserved for internal processors
23455 uint16_t target_id;
23457 * A physical address pointer pointing to a host buffer that the
23458 * command's response data will be written. This can be either a host
23459 * physical address (HPA) or a guest physical address (GPA) and must
23460 * point to a physically contiguous block of memory.
23462 uint64_t resp_addr;
23465 * Enumeration denoting the RX, TX type of the resource.
23466 * This enumeration is used for resources that are similar for both
23467 * TX and RX paths of the chip.
23469 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
23471 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
23474 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
23476 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
23477 HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
23479 /* This value identifies a meter instance in CFA. */
23480 uint16_t meter_instance_id;
23482 * A value of 0xfff is considered invalid and implies the
23483 * instance is not configured.
23485 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
23487 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
23488 HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
23489 uint8_t unused_1[4];
23490 } __attribute__((packed));
23492 /* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
23493 struct hwrm_cfa_meter_instance_free_output {
23494 /* The specific error status for the command. */
23495 uint16_t error_code;
23496 /* The HWRM command request type. */
23498 /* The sequence ID from the original command. */
23500 /* The length of the response data in number of bytes. */
23502 uint8_t unused_0[7];
23504 * This field is used in Output records to indicate that the output
23505 * is completely written to RAM. This field should be read as '1'
23506 * to indicate that the output has been completely written.
23507 * When writing a command completion or response to an internal processor,
23508 * the order of writes has to be such that this field is written last.
23511 } __attribute__((packed));
23513 /*******************************
23514 * hwrm_cfa_decap_filter_alloc *
23515 *******************************/
23518 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
23519 struct hwrm_cfa_decap_filter_alloc_input {
23520 /* The HWRM command request type. */
23523 * The completion ring to send the completion event on. This should
23524 * be the NQ ID returned from the `nq_alloc` HWRM command.
23526 uint16_t cmpl_ring;
23528 * The sequence ID is used by the driver for tracking multiple
23529 * commands. This ID is treated as opaque data by the firmware and
23530 * the value is returned in the `hwrm_resp_hdr` upon completion.
23534 * The target ID of the command:
23535 * * 0x0-0xFFF8 - The function ID
23536 * * 0xFFF8-0xFFFE - Reserved for internal processors
23539 uint16_t target_id;
23541 * A physical address pointer pointing to a host buffer that the
23542 * command's response data will be written. This can be either a host
23543 * physical address (HPA) or a guest physical address (GPA) and must
23544 * point to a physically contiguous block of memory.
23546 uint64_t resp_addr;
23548 /* ovs_tunnel is 1 b */
23549 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
23553 * This bit must be '1' for the tunnel_type field to be
23556 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
23559 * This bit must be '1' for the tunnel_id field to be
23562 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
23565 * This bit must be '1' for the src_macaddr field to be
23568 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
23571 * This bit must be '1' for the dst_macaddr field to be
23574 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
23577 * This bit must be '1' for the ovlan_vid field to be
23580 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
23583 * This bit must be '1' for the ivlan_vid field to be
23586 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
23589 * This bit must be '1' for the t_ovlan_vid field to be
23592 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
23595 * This bit must be '1' for the t_ivlan_vid field to be
23598 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
23601 * This bit must be '1' for the ethertype field to be
23604 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
23607 * This bit must be '1' for the src_ipaddr field to be
23610 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
23613 * This bit must be '1' for the dst_ipaddr field to be
23616 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
23619 * This bit must be '1' for the ipaddr_type field to be
23622 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
23625 * This bit must be '1' for the ip_protocol field to be
23628 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
23631 * This bit must be '1' for the src_port field to be
23634 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
23637 * This bit must be '1' for the dst_port field to be
23640 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
23643 * This bit must be '1' for the dst_id field to be
23646 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
23649 * This bit must be '1' for the mirror_vnic_id field to be
23652 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
23655 * Tunnel identifier.
23656 * Virtual Network Identifier (VNI). Only valid with
23657 * tunnel_types VXLAN, NVGRE, and Geneve.
23658 * Only lower 24-bits of VNI field are used
23659 * in setting up the filter.
23661 uint32_t tunnel_id;
23663 uint8_t tunnel_type;
23665 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
23667 /* Virtual eXtensible Local Area Network (VXLAN) */
23668 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
23670 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
23671 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
23673 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
23674 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
23677 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
23679 /* Generic Network Virtualization Encapsulation (Geneve) */
23680 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
23682 /* Multi-Protocol Lable Switching (MPLS) */
23683 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
23685 /* Stateless Transport Tunnel (STT) */
23686 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
23688 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
23689 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
23691 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
23692 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
23694 /* Any tunneled traffic */
23695 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
23697 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
23698 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
23702 * This value indicates the source MAC address in
23703 * the Ethernet header.
23705 uint8_t src_macaddr[6];
23706 uint8_t unused_2[2];
23708 * This value indicates the destination MAC address in
23709 * the Ethernet header.
23711 uint8_t dst_macaddr[6];
23713 * This value indicates the VLAN ID of the outer VLAN tag
23714 * in the Ethernet header.
23716 uint16_t ovlan_vid;
23718 * This value indicates the VLAN ID of the inner VLAN tag
23719 * in the Ethernet header.
23721 uint16_t ivlan_vid;
23723 * This value indicates the VLAN ID of the outer VLAN tag
23724 * in the tunnel Ethernet header.
23726 uint16_t t_ovlan_vid;
23728 * This value indicates the VLAN ID of the inner VLAN tag
23729 * in the tunnel Ethernet header.
23731 uint16_t t_ivlan_vid;
23732 /* This value indicates the ethertype in the Ethernet header. */
23733 uint16_t ethertype;
23735 * This value indicates the type of IP address.
23738 * All others are invalid.
23740 uint8_t ip_addr_type;
23742 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
23745 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
23748 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
23750 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
23751 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
23753 * The value of protocol filed in IP header.
23754 * Applies to UDP and TCP traffic.
23758 uint8_t ip_protocol;
23760 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
23763 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
23766 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
23768 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
23769 HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
23773 * The value of source IP address to be used in filtering.
23774 * For IPv4, first four bytes represent the IP address.
23776 uint32_t src_ipaddr[4];
23778 * The value of destination IP address to be used in filtering.
23779 * For IPv4, first four bytes represent the IP address.
23781 uint32_t dst_ipaddr[4];
23783 * The value of source port to be used in filtering.
23784 * Applies to UDP and TCP traffic.
23788 * The value of destination port to be used in filtering.
23789 * Applies to UDP and TCP traffic.
23793 * If set, this value shall represent the
23794 * Logical VNIC ID of the destination VNIC for the RX
23799 * If set, this value shall represent the L2 context that matches the L2
23800 * information of the decap filter.
23802 uint16_t l2_ctxt_ref_id;
23803 } __attribute__((packed));
23805 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
23806 struct hwrm_cfa_decap_filter_alloc_output {
23807 /* The specific error status for the command. */
23808 uint16_t error_code;
23809 /* The HWRM command request type. */
23811 /* The sequence ID from the original command. */
23813 /* The length of the response data in number of bytes. */
23815 /* This value is an opaque id into CFA data structures. */
23816 uint32_t decap_filter_id;
23817 uint8_t unused_0[3];
23819 * This field is used in Output records to indicate that the output
23820 * is completely written to RAM. This field should be read as '1'
23821 * to indicate that the output has been completely written.
23822 * When writing a command completion or response to an internal processor,
23823 * the order of writes has to be such that this field is written last.
23826 } __attribute__((packed));
23828 /******************************
23829 * hwrm_cfa_decap_filter_free *
23830 ******************************/
23833 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
23834 struct hwrm_cfa_decap_filter_free_input {
23835 /* The HWRM command request type. */
23838 * The completion ring to send the completion event on. This should
23839 * be the NQ ID returned from the `nq_alloc` HWRM command.
23841 uint16_t cmpl_ring;
23843 * The sequence ID is used by the driver for tracking multiple
23844 * commands. This ID is treated as opaque data by the firmware and
23845 * the value is returned in the `hwrm_resp_hdr` upon completion.
23849 * The target ID of the command:
23850 * * 0x0-0xFFF8 - The function ID
23851 * * 0xFFF8-0xFFFE - Reserved for internal processors
23854 uint16_t target_id;
23856 * A physical address pointer pointing to a host buffer that the
23857 * command's response data will be written. This can be either a host
23858 * physical address (HPA) or a guest physical address (GPA) and must
23859 * point to a physically contiguous block of memory.
23861 uint64_t resp_addr;
23862 /* This value is an opaque id into CFA data structures. */
23863 uint32_t decap_filter_id;
23864 uint8_t unused_0[4];
23865 } __attribute__((packed));
23867 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
23868 struct hwrm_cfa_decap_filter_free_output {
23869 /* The specific error status for the command. */
23870 uint16_t error_code;
23871 /* The HWRM command request type. */
23873 /* The sequence ID from the original command. */
23875 /* The length of the response data in number of bytes. */
23877 uint8_t unused_0[7];
23879 * This field is used in Output records to indicate that the output
23880 * is completely written to RAM. This field should be read as '1'
23881 * to indicate that the output has been completely written.
23882 * When writing a command completion or response to an internal processor,
23883 * the order of writes has to be such that this field is written last.
23886 } __attribute__((packed));
23888 /***********************
23889 * hwrm_cfa_flow_alloc *
23890 ***********************/
23893 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
23894 struct hwrm_cfa_flow_alloc_input {
23895 /* The HWRM command request type. */
23898 * The completion ring to send the completion event on. This should
23899 * be the NQ ID returned from the `nq_alloc` HWRM command.
23901 uint16_t cmpl_ring;
23903 * The sequence ID is used by the driver for tracking multiple
23904 * commands. This ID is treated as opaque data by the firmware and
23905 * the value is returned in the `hwrm_resp_hdr` upon completion.
23909 * The target ID of the command:
23910 * * 0x0-0xFFF8 - The function ID
23911 * * 0xFFF8-0xFFFE - Reserved for internal processors
23914 uint16_t target_id;
23916 * A physical address pointer pointing to a host buffer that the
23917 * command's response data will be written. This can be either a host
23918 * physical address (HPA) or a guest physical address (GPA) and must
23919 * point to a physically contiguous block of memory.
23921 uint64_t resp_addr;
23923 /* tunnel is 1 b */
23924 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
23925 /* num_vlan is 2 b */
23926 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
23927 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
23929 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
23930 (UINT32_C(0x0) << 1)
23932 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
23933 (UINT32_C(0x1) << 1)
23935 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
23936 (UINT32_C(0x2) << 1)
23937 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
23938 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
23939 /* Enumeration denoting the Flow Type. */
23940 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
23941 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
23943 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
23944 (UINT32_C(0x0) << 3)
23946 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
23947 (UINT32_C(0x1) << 3)
23949 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
23950 (UINT32_C(0x2) << 3)
23951 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
23952 HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
23958 /* Tunnel handle valid when tunnel flag is set. */
23959 uint32_t tunnel_handle;
23960 uint16_t action_flags;
23962 * Setting of this flag indicates drop action. If this flag is not set,
23963 * then it should be considered accept action.
23965 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
23967 /* recycle is 1 b */
23968 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
23971 * Setting of this flag indicates drop action. If this flag is not set,
23972 * then it should be considered accept action.
23974 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
23977 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
23979 /* tunnel is 1 b */
23980 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
23982 /* nat_src is 1 b */
23983 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
23985 /* nat_dest is 1 b */
23986 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
23988 /* nat_ipv4_address is 1 b */
23989 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
23991 /* l2_header_rewrite is 1 b */
23992 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
23994 /* ttl_decrement is 1 b */
23995 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
23998 * Tx Flow: pf or vf fid.
24002 /* VLAN tpid, valid when push_vlan flag is set. */
24003 uint16_t l2_rewrite_vlan_tpid;
24004 /* VLAN tci, valid when push_vlan flag is set. */
24005 uint16_t l2_rewrite_vlan_tci;
24006 /* Meter id, valid when meter flag is set. */
24007 uint16_t act_meter_id;
24008 /* Flow with the same l2 context tcam key. */
24009 uint16_t ref_flow_handle;
24010 /* This value sets the match value for the ethertype. */
24011 uint16_t ethertype;
24012 /* valid when num tags is 1 or 2. */
24013 uint16_t outer_vlan_tci;
24014 /* This value sets the match value for the Destination MAC address. */
24016 /* valid when num tags is 2. */
24017 uint16_t inner_vlan_tci;
24018 /* This value sets the match value for the Source MAC address. */
24020 /* The bit length of destination IP address mask. */
24021 uint8_t ip_dst_mask_len;
24022 /* The bit length of source IP address mask. */
24023 uint8_t ip_src_mask_len;
24024 /* The value of destination IPv4/IPv6 address. */
24025 uint32_t ip_dst[4];
24026 /* The source IPv4/IPv6 address. */
24027 uint32_t ip_src[4];
24029 * The value of source port.
24030 * Applies to UDP and TCP traffic.
24032 uint16_t l4_src_port;
24034 * The value of source port mask.
24035 * Applies to UDP and TCP traffic.
24037 uint16_t l4_src_port_mask;
24039 * The value of destination port.
24040 * Applies to UDP and TCP traffic.
24042 uint16_t l4_dst_port;
24044 * The value of destination port mask.
24045 * Applies to UDP and TCP traffic.
24047 uint16_t l4_dst_port_mask;
24049 * NAT IPv4/6 address based on address type flag.
24050 * 0 values are ignored.
24052 uint32_t nat_ip_address[4];
24053 /* L2 header re-write Destination MAC address. */
24054 uint16_t l2_rewrite_dmac[3];
24056 * The NAT source/destination port based on direction flag.
24057 * Applies to UDP and TCP traffic.
24058 * 0 values are ignored.
24061 /* L2 header re-write Source MAC address. */
24062 uint16_t l2_rewrite_smac[3];
24063 /* The value of ip protocol. */
24066 } __attribute__((packed));
24068 /* hwrm_cfa_flow_alloc_output (size:128b/16B) */
24069 struct hwrm_cfa_flow_alloc_output {
24070 /* The specific error status for the command. */
24071 uint16_t error_code;
24072 /* The HWRM command request type. */
24074 /* The sequence ID from the original command. */
24076 /* The length of the response data in number of bytes. */
24078 /* Flow record index. */
24079 uint16_t flow_handle;
24080 uint8_t unused_0[5];
24082 * This field is used in Output records to indicate that the output
24083 * is completely written to RAM. This field should be read as '1'
24084 * to indicate that the output has been completely written.
24085 * When writing a command completion or response to an internal processor,
24086 * the order of writes has to be such that this field is written last.
24089 } __attribute__((packed));
24091 /**********************
24092 * hwrm_cfa_flow_free *
24093 **********************/
24096 /* hwrm_cfa_flow_free_input (size:192b/24B) */
24097 struct hwrm_cfa_flow_free_input {
24098 /* The HWRM command request type. */
24101 * The completion ring to send the completion event on. This should
24102 * be the NQ ID returned from the `nq_alloc` HWRM command.
24104 uint16_t cmpl_ring;
24106 * The sequence ID is used by the driver for tracking multiple
24107 * commands. This ID is treated as opaque data by the firmware and
24108 * the value is returned in the `hwrm_resp_hdr` upon completion.
24112 * The target ID of the command:
24113 * * 0x0-0xFFF8 - The function ID
24114 * * 0xFFF8-0xFFFE - Reserved for internal processors
24117 uint16_t target_id;
24119 * A physical address pointer pointing to a host buffer that the
24120 * command's response data will be written. This can be either a host
24121 * physical address (HPA) or a guest physical address (GPA) and must
24122 * point to a physically contiguous block of memory.
24124 uint64_t resp_addr;
24125 /* Flow record index. */
24126 uint16_t flow_handle;
24127 uint8_t unused_0[6];
24128 } __attribute__((packed));
24130 /* hwrm_cfa_flow_free_output (size:256b/32B) */
24131 struct hwrm_cfa_flow_free_output {
24132 /* The specific error status for the command. */
24133 uint16_t error_code;
24134 /* The HWRM command request type. */
24136 /* The sequence ID from the original command. */
24138 /* The length of the response data in number of bytes. */
24140 /* packet is 64 b */
24144 uint8_t unused_0[7];
24146 * This field is used in Output records to indicate that the output
24147 * is completely written to RAM. This field should be read as '1'
24148 * to indicate that the output has been completely written.
24149 * When writing a command completion or response to an internal processor,
24150 * the order of writes has to be such that this field is written last.
24153 } __attribute__((packed));
24155 /**********************
24156 * hwrm_cfa_flow_info *
24157 **********************/
24160 /* hwrm_cfa_flow_info_input (size:192b/24B) */
24161 struct hwrm_cfa_flow_info_input {
24162 /* The HWRM command request type. */
24165 * The completion ring to send the completion event on. This should
24166 * be the NQ ID returned from the `nq_alloc` HWRM command.
24168 uint16_t cmpl_ring;
24170 * The sequence ID is used by the driver for tracking multiple
24171 * commands. This ID is treated as opaque data by the firmware and
24172 * the value is returned in the `hwrm_resp_hdr` upon completion.
24176 * The target ID of the command:
24177 * * 0x0-0xFFF8 - The function ID
24178 * * 0xFFF8-0xFFFE - Reserved for internal processors
24181 uint16_t target_id;
24183 * A physical address pointer pointing to a host buffer that the
24184 * command's response data will be written. This can be either a host
24185 * physical address (HPA) or a guest physical address (GPA) and must
24186 * point to a physically contiguous block of memory.
24188 uint64_t resp_addr;
24189 /* Flow record index. */
24190 uint16_t flow_handle;
24191 /* Max flow handle */
24192 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
24194 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
24195 /* CNP flow handle */
24196 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
24198 /* Direction rx = 1 */
24199 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
24201 uint8_t unused_0[6];
24202 } __attribute__((packed));
24204 /* hwrm_cfa_flow_info_output (size:448b/56B) */
24205 struct hwrm_cfa_flow_info_output {
24206 /* The specific error status for the command. */
24207 uint16_t error_code;
24208 /* The HWRM command request type. */
24210 /* The sequence ID from the original command. */
24212 /* The length of the response data in number of bytes. */
24216 /* profile is 8 b */
24218 /* src_fid is 16 b */
24220 /* dst_fid is 16 b */
24222 /* l2_ctxt_id is 16 b */
24223 uint16_t l2_ctxt_id;
24224 /* em_info is 64 b */
24226 /* tcam_info is 64 b */
24227 uint64_t tcam_info;
24228 /* vfp_tcam_info is 64 b */
24229 uint64_t vfp_tcam_info;
24230 /* ar_id is 16 b */
24232 /* flow_handle is 16 b */
24233 uint16_t flow_handle;
24234 /* tunnel_handle is 32 b */
24235 uint32_t tunnel_handle;
24236 uint8_t unused_0[7];
24238 * This field is used in Output records to indicate that the output
24239 * is completely written to RAM. This field should be read as '1'
24240 * to indicate that the output has been completely written.
24241 * When writing a command completion or response to an internal processor,
24242 * the order of writes has to be such that this field is written last.
24245 } __attribute__((packed));
24247 /***********************
24248 * hwrm_cfa_flow_flush *
24249 ***********************/
24252 /* hwrm_cfa_flow_flush_input (size:192b/24B) */
24253 struct hwrm_cfa_flow_flush_input {
24254 /* The HWRM command request type. */
24257 * The completion ring to send the completion event on. This should
24258 * be the NQ ID returned from the `nq_alloc` HWRM command.
24260 uint16_t cmpl_ring;
24262 * The sequence ID is used by the driver for tracking multiple
24263 * commands. This ID is treated as opaque data by the firmware and
24264 * the value is returned in the `hwrm_resp_hdr` upon completion.
24268 * The target ID of the command:
24269 * * 0x0-0xFFF8 - The function ID
24270 * * 0xFFF8-0xFFFE - Reserved for internal processors
24273 uint16_t target_id;
24275 * A physical address pointer pointing to a host buffer that the
24276 * command's response data will be written. This can be either a host
24277 * physical address (HPA) or a guest physical address (GPA) and must
24278 * point to a physically contiguous block of memory.
24280 uint64_t resp_addr;
24282 uint8_t unused_0[4];
24283 } __attribute__((packed));
24285 /* hwrm_cfa_flow_flush_output (size:128b/16B) */
24286 struct hwrm_cfa_flow_flush_output {
24287 /* The specific error status for the command. */
24288 uint16_t error_code;
24289 /* The HWRM command request type. */
24291 /* The sequence ID from the original command. */
24293 /* The length of the response data in number of bytes. */
24295 uint8_t unused_0[7];
24297 * This field is used in Output records to indicate that the output
24298 * is completely written to RAM. This field should be read as '1'
24299 * to indicate that the output has been completely written.
24300 * When writing a command completion or response to an internal processor,
24301 * the order of writes has to be such that this field is written last.
24304 } __attribute__((packed));
24306 /***********************
24307 * hwrm_cfa_flow_stats *
24308 ***********************/
24311 /* hwrm_cfa_flow_stats_input (size:320b/40B) */
24312 struct hwrm_cfa_flow_stats_input {
24313 /* The HWRM command request type. */
24316 * The completion ring to send the completion event on. This should
24317 * be the NQ ID returned from the `nq_alloc` HWRM command.
24319 uint16_t cmpl_ring;
24321 * The sequence ID is used by the driver for tracking multiple
24322 * commands. This ID is treated as opaque data by the firmware and
24323 * the value is returned in the `hwrm_resp_hdr` upon completion.
24327 * The target ID of the command:
24328 * * 0x0-0xFFF8 - The function ID
24329 * * 0xFFF8-0xFFFE - Reserved for internal processors
24332 uint16_t target_id;
24334 * A physical address pointer pointing to a host buffer that the
24335 * command's response data will be written. This can be either a host
24336 * physical address (HPA) or a guest physical address (GPA) and must
24337 * point to a physically contiguous block of memory.
24339 uint64_t resp_addr;
24341 uint16_t num_flows;
24343 uint16_t flow_handle_0;
24345 uint16_t flow_handle_1;
24347 uint16_t flow_handle_2;
24349 uint16_t flow_handle_3;
24351 uint16_t flow_handle_4;
24353 uint16_t flow_handle_5;
24355 uint16_t flow_handle_6;
24357 uint16_t flow_handle_7;
24359 uint16_t flow_handle_8;
24361 uint16_t flow_handle_9;
24362 uint8_t unused_0[2];
24363 } __attribute__((packed));
24365 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */
24366 struct hwrm_cfa_flow_stats_output {
24367 /* The specific error status for the command. */
24368 uint16_t error_code;
24369 /* The HWRM command request type. */
24371 /* The sequence ID from the original command. */
24373 /* The length of the response data in number of bytes. */
24375 /* packet_0 is 64 b */
24377 /* packet_1 is 64 b */
24379 /* packet_2 is 64 b */
24381 /* packet_3 is 64 b */
24383 /* packet_4 is 64 b */
24385 /* packet_5 is 64 b */
24387 /* packet_6 is 64 b */
24389 /* packet_7 is 64 b */
24391 /* packet_8 is 64 b */
24393 /* packet_9 is 64 b */
24395 /* byte_0 is 64 b */
24397 /* byte_1 is 64 b */
24399 /* byte_2 is 64 b */
24401 /* byte_3 is 64 b */
24403 /* byte_4 is 64 b */
24405 /* byte_5 is 64 b */
24407 /* byte_6 is 64 b */
24409 /* byte_7 is 64 b */
24411 /* byte_8 is 64 b */
24413 /* byte_9 is 64 b */
24415 uint8_t unused_0[7];
24417 * This field is used in Output records to indicate that the output
24418 * is completely written to RAM. This field should be read as '1'
24419 * to indicate that the output has been completely written.
24420 * When writing a command completion or response to an internal processor,
24421 * the order of writes has to be such that this field is written last.
24424 } __attribute__((packed));
24426 /**************************
24427 * hwrm_cfa_vf_pair_alloc *
24428 **************************/
24431 /* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */
24432 struct hwrm_cfa_vf_pair_alloc_input {
24433 /* The HWRM command request type. */
24436 * The completion ring to send the completion event on. This should
24437 * be the NQ ID returned from the `nq_alloc` HWRM command.
24439 uint16_t cmpl_ring;
24441 * The sequence ID is used by the driver for tracking multiple
24442 * commands. This ID is treated as opaque data by the firmware and
24443 * the value is returned in the `hwrm_resp_hdr` upon completion.
24447 * The target ID of the command:
24448 * * 0x0-0xFFF8 - The function ID
24449 * * 0xFFF8-0xFFFE - Reserved for internal processors
24452 uint16_t target_id;
24454 * A physical address pointer pointing to a host buffer that the
24455 * command's response data will be written. This can be either a host
24456 * physical address (HPA) or a guest physical address (GPA) and must
24457 * point to a physically contiguous block of memory.
24459 uint64_t resp_addr;
24460 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24462 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24464 uint8_t unused_0[4];
24465 /* VF Pair name (32 byte string). */
24466 char pair_name[32];
24467 } __attribute__((packed));
24469 /* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */
24470 struct hwrm_cfa_vf_pair_alloc_output {
24471 /* The specific error status for the command. */
24472 uint16_t error_code;
24473 /* The HWRM command request type. */
24475 /* The sequence ID from the original command. */
24477 /* The length of the response data in number of bytes. */
24479 uint8_t unused_0[7];
24481 * This field is used in Output records to indicate that the output
24482 * is completely written to RAM. This field should be read as '1'
24483 * to indicate that the output has been completely written.
24484 * When writing a command completion or response to an internal processor,
24485 * the order of writes has to be such that this field is written last.
24488 } __attribute__((packed));
24490 /*************************
24491 * hwrm_cfa_vf_pair_free *
24492 *************************/
24495 /* hwrm_cfa_vf_pair_free_input (size:384b/48B) */
24496 struct hwrm_cfa_vf_pair_free_input {
24497 /* The HWRM command request type. */
24500 * The completion ring to send the completion event on. This should
24501 * be the NQ ID returned from the `nq_alloc` HWRM command.
24503 uint16_t cmpl_ring;
24505 * The sequence ID is used by the driver for tracking multiple
24506 * commands. This ID is treated as opaque data by the firmware and
24507 * the value is returned in the `hwrm_resp_hdr` upon completion.
24511 * The target ID of the command:
24512 * * 0x0-0xFFF8 - The function ID
24513 * * 0xFFF8-0xFFFE - Reserved for internal processors
24516 uint16_t target_id;
24518 * A physical address pointer pointing to a host buffer that the
24519 * command's response data will be written. This can be either a host
24520 * physical address (HPA) or a guest physical address (GPA) and must
24521 * point to a physically contiguous block of memory.
24523 uint64_t resp_addr;
24524 /* VF Pair name (32 byte string). */
24525 char pair_name[32];
24526 } __attribute__((packed));
24528 /* hwrm_cfa_vf_pair_free_output (size:128b/16B) */
24529 struct hwrm_cfa_vf_pair_free_output {
24530 /* The specific error status for the command. */
24531 uint16_t error_code;
24532 /* The HWRM command request type. */
24534 /* The sequence ID from the original command. */
24536 /* The length of the response data in number of bytes. */
24538 uint8_t unused_0[7];
24540 * This field is used in Output records to indicate that the output
24541 * is completely written to RAM. This field should be read as '1'
24542 * to indicate that the output has been completely written.
24543 * When writing a command completion or response to an internal processor,
24544 * the order of writes has to be such that this field is written last.
24547 } __attribute__((packed));
24549 /*************************
24550 * hwrm_cfa_vf_pair_info *
24551 *************************/
24554 /* hwrm_cfa_vf_pair_info_input (size:448b/56B) */
24555 struct hwrm_cfa_vf_pair_info_input {
24556 /* The HWRM command request type. */
24559 * The completion ring to send the completion event on. This should
24560 * be the NQ ID returned from the `nq_alloc` HWRM command.
24562 uint16_t cmpl_ring;
24564 * The sequence ID is used by the driver for tracking multiple
24565 * commands. This ID is treated as opaque data by the firmware and
24566 * the value is returned in the `hwrm_resp_hdr` upon completion.
24570 * The target ID of the command:
24571 * * 0x0-0xFFF8 - The function ID
24572 * * 0xFFF8-0xFFFE - Reserved for internal processors
24575 uint16_t target_id;
24577 * A physical address pointer pointing to a host buffer that the
24578 * command's response data will be written. This can be either a host
24579 * physical address (HPA) or a guest physical address (GPA) and must
24580 * point to a physically contiguous block of memory.
24582 uint64_t resp_addr;
24584 /* If this flag is set, lookup by name else lookup by index. */
24585 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
24586 /* vf pair table index. */
24587 uint16_t vf_pair_index;
24588 uint8_t unused_0[2];
24589 /* VF Pair name (32 byte string). */
24590 char vf_pair_name[32];
24591 } __attribute__((packed));
24593 /* hwrm_cfa_vf_pair_info_output (size:512b/64B) */
24594 struct hwrm_cfa_vf_pair_info_output {
24595 /* The specific error status for the command. */
24596 uint16_t error_code;
24597 /* The HWRM command request type. */
24599 /* The sequence ID from the original command. */
24601 /* The length of the response data in number of bytes. */
24603 /* vf pair table index. */
24604 uint16_t next_vf_pair_index;
24605 /* vf pair member a's vf_fid. */
24607 /* vf pair member a's Linux logical VF number. */
24608 uint16_t vf_a_index;
24609 /* vf pair member b's vf_fid. */
24611 /* vf pair member a's Linux logical VF number. */
24612 uint16_t vf_b_index;
24613 /* vf pair state. */
24614 uint8_t pair_state;
24615 /* Pair has been allocated */
24616 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
24617 /* Both pair members are active */
24618 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
24619 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
24620 HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
24621 uint8_t unused_0[5];
24622 /* VF Pair name (32 byte string). */
24623 char pair_name[32];
24624 uint8_t unused_1[7];
24626 * This field is used in Output records to indicate that the output
24627 * is completely written to RAM. This field should be read as '1'
24628 * to indicate that the output has been completely written.
24629 * When writing a command completion or response to an internal processor,
24630 * the order of writes has to be such that this field is written last.
24633 } __attribute__((packed));
24635 /***********************
24636 * hwrm_cfa_pair_alloc *
24637 ***********************/
24640 /* hwrm_cfa_pair_alloc_input (size:576b/72B) */
24641 struct hwrm_cfa_pair_alloc_input {
24642 /* The HWRM command request type. */
24645 * The completion ring to send the completion event on. This should
24646 * be the NQ ID returned from the `nq_alloc` HWRM command.
24648 uint16_t cmpl_ring;
24650 * The sequence ID is used by the driver for tracking multiple
24651 * commands. This ID is treated as opaque data by the firmware and
24652 * the value is returned in the `hwrm_resp_hdr` upon completion.
24656 * The target ID of the command:
24657 * * 0x0-0xFFF8 - The function ID
24658 * * 0xFFF8-0xFFFE - Reserved for internal processors
24661 uint16_t target_id;
24663 * A physical address pointer pointing to a host buffer that the
24664 * command's response data will be written. This can be either a host
24665 * physical address (HPA) or a guest physical address (GPA) and must
24666 * point to a physically contiguous block of memory.
24668 uint64_t resp_addr;
24669 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */
24671 /* Pair between VF on local host with PF or VF on specified host. */
24672 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
24673 /* Pair between REP on local host with PF or VF on specified host. */
24674 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
24675 /* Pair between REP on local host with REP on specified host. */
24676 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
24677 /* Pair for the proxy interface. */
24678 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
24679 /* Pair for the PF interface. */
24680 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
24681 /* Modify exiting rep2fn pair and move pair to new PF. */
24682 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
24683 /* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */
24684 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
24685 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \
24686 HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL
24688 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24690 /* Logical Host (0xff-local host). */
24692 /* Logical PF (0xff-PF for command channel). */
24694 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24696 /* Loopback port (0xff-internal loopback), valid for mode-3. */
24698 /* Priority used for encap of loopback packets valid for mode-3. */
24700 /* New PF for rep2fn modify, valid for mode 5. */
24701 uint16_t new_pf_fid;
24704 * This bit must be '1' for the q_ab field to be
24707 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
24709 * This bit must be '1' for the q_ba field to be
24712 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
24714 * This bit must be '1' for the fc_ab field to be
24717 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
24719 * This bit must be '1' for the fc_ba field to be
24722 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
24723 /* VF Pair name (32 byte string). */
24724 char pair_name[32];
24726 * The q_ab value specifies the logical index of the TX/RX CoS
24727 * queue to be assigned for traffic in the A to B direction of
24728 * the interface pair. The default value is 0.
24732 * The q_ba value specifies the logical index of the TX/RX CoS
24733 * queue to be assigned for traffic in the B to A direction of
24734 * the interface pair. The default value is 1.
24738 * Specifies whether RX ring flow control is disabled (0) or enabled
24739 * (1) in the A to B direction. The default value is 0, meaning that
24740 * packets will be dropped when the B-side RX rings are full.
24744 * Specifies whether RX ring flow control is disabled (0) or enabled
24745 * (1) in the B to A direction. The default value is 1, meaning that
24746 * the RX CoS queue will be flow controlled when the A-side RX rings
24750 uint8_t unused_1[4];
24751 } __attribute__((packed));
24753 /* hwrm_cfa_pair_alloc_output (size:192b/24B) */
24754 struct hwrm_cfa_pair_alloc_output {
24755 /* The specific error status for the command. */
24756 uint16_t error_code;
24757 /* The HWRM command request type. */
24759 /* The sequence ID from the original command. */
24761 /* The length of the response data in number of bytes. */
24763 /* Only valid for modes 1 and 2. */
24764 uint16_t rx_cfa_code_a;
24765 /* Only valid for modes 1 and 2. */
24766 uint16_t tx_cfa_action_a;
24767 /* Only valid for mode 2. */
24768 uint16_t rx_cfa_code_b;
24769 /* Only valid for mode 2. */
24770 uint16_t tx_cfa_action_b;
24771 uint8_t unused_0[7];
24773 * This field is used in Output records to indicate that the output
24774 * is completely written to RAM. This field should be read as '1'
24775 * to indicate that the output has been completely written.
24776 * When writing a command completion or response to an internal processor,
24777 * the order of writes has to be such that this field is written last.
24780 } __attribute__((packed));
24782 /**********************
24783 * hwrm_cfa_pair_free *
24784 **********************/
24787 /* hwrm_cfa_pair_free_input (size:384b/48B) */
24788 struct hwrm_cfa_pair_free_input {
24789 /* The HWRM command request type. */
24792 * The completion ring to send the completion event on. This should
24793 * be the NQ ID returned from the `nq_alloc` HWRM command.
24795 uint16_t cmpl_ring;
24797 * The sequence ID is used by the driver for tracking multiple
24798 * commands. This ID is treated as opaque data by the firmware and
24799 * the value is returned in the `hwrm_resp_hdr` upon completion.
24803 * The target ID of the command:
24804 * * 0x0-0xFFF8 - The function ID
24805 * * 0xFFF8-0xFFFE - Reserved for internal processors
24808 uint16_t target_id;
24810 * A physical address pointer pointing to a host buffer that the
24811 * command's response data will be written. This can be either a host
24812 * physical address (HPA) or a guest physical address (GPA) and must
24813 * point to a physically contiguous block of memory.
24815 uint64_t resp_addr;
24816 /* VF Pair name (32 byte string). */
24817 char pair_name[32];
24818 } __attribute__((packed));
24820 /* hwrm_cfa_pair_free_output (size:128b/16B) */
24821 struct hwrm_cfa_pair_free_output {
24822 /* The specific error status for the command. */
24823 uint16_t error_code;
24824 /* The HWRM command request type. */
24826 /* The sequence ID from the original command. */
24828 /* The length of the response data in number of bytes. */
24830 uint8_t unused_0[7];
24832 * This field is used in Output records to indicate that the output
24833 * is completely written to RAM. This field should be read as '1'
24834 * to indicate that the output has been completely written.
24835 * When writing a command completion or response to an internal processor,
24836 * the order of writes has to be such that this field is written last.
24839 } __attribute__((packed));
24841 /**********************
24842 * hwrm_cfa_pair_info *
24843 **********************/
24846 /* hwrm_cfa_pair_info_input (size:448b/56B) */
24847 struct hwrm_cfa_pair_info_input {
24848 /* The HWRM command request type. */
24851 * The completion ring to send the completion event on. This should
24852 * be the NQ ID returned from the `nq_alloc` HWRM command.
24854 uint16_t cmpl_ring;
24856 * The sequence ID is used by the driver for tracking multiple
24857 * commands. This ID is treated as opaque data by the firmware and
24858 * the value is returned in the `hwrm_resp_hdr` upon completion.
24862 * The target ID of the command:
24863 * * 0x0-0xFFF8 - The function ID
24864 * * 0xFFF8-0xFFFE - Reserved for internal processors
24867 uint16_t target_id;
24869 * A physical address pointer pointing to a host buffer that the
24870 * command's response data will be written. This can be either a host
24871 * physical address (HPA) or a guest physical address (GPA) and must
24872 * point to a physically contiguous block of memory.
24874 uint64_t resp_addr;
24876 /* If this flag is set, lookup by name else lookup by index. */
24877 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
24878 /* If this flag is set, lookup by PF id and VF id. */
24879 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
24880 /* Pair table index. */
24881 uint16_t pair_index;
24882 /* Pair pf index. */
24884 /* Pair vf index. */
24886 /* Pair name (32 byte string). */
24887 char pair_name[32];
24888 } __attribute__((packed));
24890 /* hwrm_cfa_pair_info_output (size:576b/72B) */
24891 struct hwrm_cfa_pair_info_output {
24892 /* The specific error status for the command. */
24893 uint16_t error_code;
24894 /* The HWRM command request type. */
24896 /* The sequence ID from the original command. */
24898 /* The length of the response data in number of bytes. */
24900 /* Pair table index. */
24901 uint16_t next_pair_index;
24902 /* Pair member a's fid. */
24904 /* Logical host number. */
24905 uint8_t host_a_index;
24906 /* Logical PF number. */
24907 uint8_t pf_a_index;
24908 /* Pair member a's Linux logical VF number. */
24909 uint16_t vf_a_index;
24911 uint16_t rx_cfa_code_a;
24912 /* Tx CFA action. */
24913 uint16_t tx_cfa_action_a;
24914 /* Pair member b's fid. */
24916 /* Logical host number. */
24917 uint8_t host_b_index;
24918 /* Logical PF number. */
24919 uint8_t pf_b_index;
24920 /* Pair member a's Linux logical VF number. */
24921 uint16_t vf_b_index;
24923 uint16_t rx_cfa_code_b;
24924 /* Tx CFA action. */
24925 uint16_t tx_cfa_action_b;
24926 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
24928 /* Pair between VF on local host with PF or VF on specified host. */
24929 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
24930 /* Pair between REP on local host with PF or VF on specified host. */
24931 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
24932 /* Pair between REP on local host with REP on specified host. */
24933 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
24934 /* Pair for the proxy interface. */
24935 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
24936 /* Pair for the PF interface. */
24937 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
24938 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \
24939 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR
24941 uint8_t pair_state;
24942 /* Pair has been allocated */
24943 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
24944 /* Both pair members are active */
24945 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
24946 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \
24947 HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE
24948 /* Pair name (32 byte string). */
24949 char pair_name[32];
24950 uint8_t unused_0[7];
24952 * This field is used in Output records to indicate that the output
24953 * is completely written to RAM. This field should be read as '1'
24954 * to indicate that the output has been completely written.
24955 * When writing a command completion or response to an internal processor,
24956 * the order of writes has to be such that this field is written last.
24959 } __attribute__((packed));
24961 /**********************
24962 * hwrm_cfa_vfr_alloc *
24963 **********************/
24966 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */
24967 struct hwrm_cfa_vfr_alloc_input {
24968 /* The HWRM command request type. */
24971 * The completion ring to send the completion event on. This should
24972 * be the NQ ID returned from the `nq_alloc` HWRM command.
24974 uint16_t cmpl_ring;
24976 * The sequence ID is used by the driver for tracking multiple
24977 * commands. This ID is treated as opaque data by the firmware and
24978 * the value is returned in the `hwrm_resp_hdr` upon completion.
24982 * The target ID of the command:
24983 * * 0x0-0xFFF8 - The function ID
24984 * * 0xFFF8-0xFFFE - Reserved for internal processors
24987 uint16_t target_id;
24989 * A physical address pointer pointing to a host buffer that the
24990 * command's response data will be written. This can be either a host
24991 * physical address (HPA) or a guest physical address (GPA) and must
24992 * point to a physically contiguous block of memory.
24994 uint64_t resp_addr;
24995 /* Logical VF number (range: 0 -> MAX_VFS -1). */
24998 * This field is reserved for the future use.
24999 * It shall be set to 0.
25002 uint8_t unused_0[4];
25003 /* VF Representor name (32 byte string). */
25005 } __attribute__((packed));
25007 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */
25008 struct hwrm_cfa_vfr_alloc_output {
25009 /* The specific error status for the command. */
25010 uint16_t error_code;
25011 /* The HWRM command request type. */
25013 /* The sequence ID from the original command. */
25015 /* The length of the response data in number of bytes. */
25018 uint16_t rx_cfa_code;
25019 /* Tx CFA action. */
25020 uint16_t tx_cfa_action;
25021 uint8_t unused_0[3];
25023 * This field is used in Output records to indicate that the output
25024 * is completely written to RAM. This field should be read as '1'
25025 * to indicate that the output has been completely written.
25026 * When writing a command completion or response to an internal processor,
25027 * the order of writes has to be such that this field is written last.
25030 } __attribute__((packed));
25032 /*********************
25033 * hwrm_cfa_vfr_free *
25034 *********************/
25037 /* hwrm_cfa_vfr_free_input (size:384b/48B) */
25038 struct hwrm_cfa_vfr_free_input {
25039 /* The HWRM command request type. */
25042 * The completion ring to send the completion event on. This should
25043 * be the NQ ID returned from the `nq_alloc` HWRM command.
25045 uint16_t cmpl_ring;
25047 * The sequence ID is used by the driver for tracking multiple
25048 * commands. This ID is treated as opaque data by the firmware and
25049 * the value is returned in the `hwrm_resp_hdr` upon completion.
25053 * The target ID of the command:
25054 * * 0x0-0xFFF8 - The function ID
25055 * * 0xFFF8-0xFFFE - Reserved for internal processors
25058 uint16_t target_id;
25060 * A physical address pointer pointing to a host buffer that the
25061 * command's response data will be written. This can be either a host
25062 * physical address (HPA) or a guest physical address (GPA) and must
25063 * point to a physically contiguous block of memory.
25065 uint64_t resp_addr;
25066 /* VF Representor name (32 byte string). */
25068 } __attribute__((packed));
25070 /* hwrm_cfa_vfr_free_output (size:128b/16B) */
25071 struct hwrm_cfa_vfr_free_output {
25072 /* The specific error status for the command. */
25073 uint16_t error_code;
25074 /* The HWRM command request type. */
25076 /* The sequence ID from the original command. */
25078 /* The length of the response data in number of bytes. */
25080 uint8_t unused_0[7];
25082 * This field is used in Output records to indicate that the output
25083 * is completely written to RAM. This field should be read as '1'
25084 * to indicate that the output has been completely written.
25085 * When writing a command completion or response to an internal processor,
25086 * the order of writes has to be such that this field is written last.
25089 } __attribute__((packed));
25091 /******************************
25092 * hwrm_tunnel_dst_port_query *
25093 ******************************/
25096 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
25097 struct hwrm_tunnel_dst_port_query_input {
25098 /* The HWRM command request type. */
25101 * The completion ring to send the completion event on. This should
25102 * be the NQ ID returned from the `nq_alloc` HWRM command.
25104 uint16_t cmpl_ring;
25106 * The sequence ID is used by the driver for tracking multiple
25107 * commands. This ID is treated as opaque data by the firmware and
25108 * the value is returned in the `hwrm_resp_hdr` upon completion.
25112 * The target ID of the command:
25113 * * 0x0-0xFFF8 - The function ID
25114 * * 0xFFF8-0xFFFE - Reserved for internal processors
25117 uint16_t target_id;
25119 * A physical address pointer pointing to a host buffer that the
25120 * command's response data will be written. This can be either a host
25121 * physical address (HPA) or a guest physical address (GPA) and must
25122 * point to a physically contiguous block of memory.
25124 uint64_t resp_addr;
25126 uint8_t tunnel_type;
25127 /* Virtual eXtensible Local Area Network (VXLAN) */
25128 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \
25130 /* Generic Network Virtualization Encapsulation (Geneve) */
25131 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \
25133 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25134 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25136 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25137 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25139 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
25140 HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
25141 uint8_t unused_0[7];
25142 } __attribute__((packed));
25144 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */
25145 struct hwrm_tunnel_dst_port_query_output {
25146 /* The specific error status for the command. */
25147 uint16_t error_code;
25148 /* The HWRM command request type. */
25150 /* The sequence ID from the original command. */
25152 /* The length of the response data in number of bytes. */
25155 * This field represents the identifier of L4 destination port
25156 * used for the given tunnel type. This field is valid for
25157 * specific tunnel types that use layer 4 (e.g. UDP)
25158 * transports for tunneling.
25160 uint16_t tunnel_dst_port_id;
25162 * This field represents the value of L4 destination port
25163 * identified by tunnel_dst_port_id. This field is valid for
25164 * specific tunnel types that use layer 4 (e.g. UDP)
25165 * transports for tunneling.
25166 * This field is in network byte order.
25168 * A value of 0 means that the destination port is not
25171 uint16_t tunnel_dst_port_val;
25172 uint8_t unused_0[3];
25174 * This field is used in Output records to indicate that the output
25175 * is completely written to RAM. This field should be read as '1'
25176 * to indicate that the output has been completely written.
25177 * When writing a command completion or response to an internal processor,
25178 * the order of writes has to be such that this field is written last.
25181 } __attribute__((packed));
25183 /******************************
25184 * hwrm_tunnel_dst_port_alloc *
25185 ******************************/
25188 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */
25189 struct hwrm_tunnel_dst_port_alloc_input {
25190 /* The HWRM command request type. */
25193 * The completion ring to send the completion event on. This should
25194 * be the NQ ID returned from the `nq_alloc` HWRM command.
25196 uint16_t cmpl_ring;
25198 * The sequence ID is used by the driver for tracking multiple
25199 * commands. This ID is treated as opaque data by the firmware and
25200 * the value is returned in the `hwrm_resp_hdr` upon completion.
25204 * The target ID of the command:
25205 * * 0x0-0xFFF8 - The function ID
25206 * * 0xFFF8-0xFFFE - Reserved for internal processors
25209 uint16_t target_id;
25211 * A physical address pointer pointing to a host buffer that the
25212 * command's response data will be written. This can be either a host
25213 * physical address (HPA) or a guest physical address (GPA) and must
25214 * point to a physically contiguous block of memory.
25216 uint64_t resp_addr;
25218 uint8_t tunnel_type;
25219 /* Virtual eXtensible Local Area Network (VXLAN) */
25220 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
25222 /* Generic Network Virtualization Encapsulation (Geneve) */
25223 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
25225 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25226 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25228 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25229 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25231 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
25232 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
25235 * This field represents the value of L4 destination port used
25236 * for the given tunnel type. This field is valid for
25237 * specific tunnel types that use layer 4 (e.g. UDP)
25238 * transports for tunneling.
25240 * This field is in network byte order.
25242 * A value of 0 shall fail the command.
25244 uint16_t tunnel_dst_port_val;
25245 uint8_t unused_1[4];
25246 } __attribute__((packed));
25248 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */
25249 struct hwrm_tunnel_dst_port_alloc_output {
25250 /* The specific error status for the command. */
25251 uint16_t error_code;
25252 /* The HWRM command request type. */
25254 /* The sequence ID from the original command. */
25256 /* The length of the response data in number of bytes. */
25259 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
25260 * types that has l4 destination port parameters.
25262 uint16_t tunnel_dst_port_id;
25263 uint8_t unused_0[5];
25265 * This field is used in Output records to indicate that the output
25266 * is completely written to RAM. This field should be read as '1'
25267 * to indicate that the output has been completely written.
25268 * When writing a command completion or response to an internal processor,
25269 * the order of writes has to be such that this field is written last.
25272 } __attribute__((packed));
25274 /*****************************
25275 * hwrm_tunnel_dst_port_free *
25276 *****************************/
25279 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */
25280 struct hwrm_tunnel_dst_port_free_input {
25281 /* The HWRM command request type. */
25284 * The completion ring to send the completion event on. This should
25285 * be the NQ ID returned from the `nq_alloc` HWRM command.
25287 uint16_t cmpl_ring;
25289 * The sequence ID is used by the driver for tracking multiple
25290 * commands. This ID is treated as opaque data by the firmware and
25291 * the value is returned in the `hwrm_resp_hdr` upon completion.
25295 * The target ID of the command:
25296 * * 0x0-0xFFF8 - The function ID
25297 * * 0xFFF8-0xFFFE - Reserved for internal processors
25300 uint16_t target_id;
25302 * A physical address pointer pointing to a host buffer that the
25303 * command's response data will be written. This can be either a host
25304 * physical address (HPA) or a guest physical address (GPA) and must
25305 * point to a physically contiguous block of memory.
25307 uint64_t resp_addr;
25309 uint8_t tunnel_type;
25310 /* Virtual eXtensible Local Area Network (VXLAN) */
25311 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \
25313 /* Generic Network Virtualization Encapsulation (Geneve) */
25314 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \
25316 /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
25317 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \
25319 /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
25320 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
25322 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
25323 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
25326 * Identifier of a tunnel L4 destination port value. Only applies to tunnel
25327 * types that has l4 destination port parameters.
25329 uint16_t tunnel_dst_port_id;
25330 uint8_t unused_1[4];
25331 } __attribute__((packed));
25333 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */
25334 struct hwrm_tunnel_dst_port_free_output {
25335 /* The specific error status for the command. */
25336 uint16_t error_code;
25337 /* The HWRM command request type. */
25339 /* The sequence ID from the original command. */
25341 /* The length of the response data in number of bytes. */
25343 uint8_t unused_1[7];
25345 * This field is used in Output records to indicate that the output
25346 * is completely written to RAM. This field should be read as '1'
25347 * to indicate that the output has been completely written.
25348 * When writing a command completion or response to an internal processor,
25349 * the order of writes has to be such that this field is written last.
25352 } __attribute__((packed));
25354 /* ctx_hw_stats (size:1280b/160B) */
25355 struct ctx_hw_stats {
25356 /* Number of received unicast packets */
25357 uint64_t rx_ucast_pkts;
25358 /* Number of received multicast packets */
25359 uint64_t rx_mcast_pkts;
25360 /* Number of received broadcast packets */
25361 uint64_t rx_bcast_pkts;
25362 /* Number of discarded packets on received path */
25363 uint64_t rx_discard_pkts;
25364 /* Number of dropped packets on received path */
25365 uint64_t rx_drop_pkts;
25366 /* Number of received bytes for unicast traffic */
25367 uint64_t rx_ucast_bytes;
25368 /* Number of received bytes for multicast traffic */
25369 uint64_t rx_mcast_bytes;
25370 /* Number of received bytes for broadcast traffic */
25371 uint64_t rx_bcast_bytes;
25372 /* Number of transmitted unicast packets */
25373 uint64_t tx_ucast_pkts;
25374 /* Number of transmitted multicast packets */
25375 uint64_t tx_mcast_pkts;
25376 /* Number of transmitted broadcast packets */
25377 uint64_t tx_bcast_pkts;
25378 /* Number of discarded packets on transmit path */
25379 uint64_t tx_discard_pkts;
25380 /* Number of dropped packets on transmit path */
25381 uint64_t tx_drop_pkts;
25382 /* Number of transmitted bytes for unicast traffic */
25383 uint64_t tx_ucast_bytes;
25384 /* Number of transmitted bytes for multicast traffic */
25385 uint64_t tx_mcast_bytes;
25386 /* Number of transmitted bytes for broadcast traffic */
25387 uint64_t tx_bcast_bytes;
25388 /* Number of TPA packets */
25390 /* Number of TPA bytes */
25391 uint64_t tpa_bytes;
25392 /* Number of TPA events */
25393 uint64_t tpa_events;
25394 /* Number of TPA aborts */
25395 uint64_t tpa_aborts;
25396 } __attribute__((packed));
25398 /***********************
25399 * hwrm_stat_ctx_alloc *
25400 ***********************/
25403 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */
25404 struct hwrm_stat_ctx_alloc_input {
25405 /* The HWRM command request type. */
25408 * The completion ring to send the completion event on. This should
25409 * be the NQ ID returned from the `nq_alloc` HWRM command.
25411 uint16_t cmpl_ring;
25413 * The sequence ID is used by the driver for tracking multiple
25414 * commands. This ID is treated as opaque data by the firmware and
25415 * the value is returned in the `hwrm_resp_hdr` upon completion.
25419 * The target ID of the command:
25420 * * 0x0-0xFFF8 - The function ID
25421 * * 0xFFF8-0xFFFE - Reserved for internal processors
25424 uint16_t target_id;
25426 * A physical address pointer pointing to a host buffer that the
25427 * command's response data will be written. This can be either a host
25428 * physical address (HPA) or a guest physical address (GPA) and must
25429 * point to a physically contiguous block of memory.
25431 uint64_t resp_addr;
25432 /* This is the address for statistic block. */
25433 uint64_t stats_dma_addr;
25435 * The statistic block update period in ms.
25436 * e.g. 250ms, 500ms, 750ms, 1000ms.
25437 * If update_period_ms is 0, then the stats update
25438 * shall be never done and the DMA address shall not be used.
25439 * In this case, the stat block can only be read by
25440 * hwrm_stat_ctx_query command.
25442 uint32_t update_period_ms;
25444 * This field is used to specify statistics context specific
25445 * configuration flags.
25447 uint8_t stat_ctx_flags;
25449 * When this bit is set to '1', the statistics context shall be
25450 * allocated for RoCE traffic only. In this case, traffic other
25451 * than offloaded RoCE traffic shall not be included in this
25452 * statistic context.
25453 * When this bit is set to '0', the statistics context shall be
25454 * used for the network traffic other than offloaded RoCE traffic.
25456 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
25457 uint8_t unused_0[3];
25458 } __attribute__((packed));
25460 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */
25461 struct hwrm_stat_ctx_alloc_output {
25462 /* The specific error status for the command. */
25463 uint16_t error_code;
25464 /* The HWRM command request type. */
25466 /* The sequence ID from the original command. */
25468 /* The length of the response data in number of bytes. */
25470 /* This is the statistics context ID value. */
25471 uint32_t stat_ctx_id;
25472 uint8_t unused_0[3];
25474 * This field is used in Output records to indicate that the output
25475 * is completely written to RAM. This field should be read as '1'
25476 * to indicate that the output has been completely written.
25477 * When writing a command completion or response to an internal processor,
25478 * the order of writes has to be such that this field is written last.
25481 } __attribute__((packed));
25483 /**********************
25484 * hwrm_stat_ctx_free *
25485 **********************/
25488 /* hwrm_stat_ctx_free_input (size:192b/24B) */
25489 struct hwrm_stat_ctx_free_input {
25490 /* The HWRM command request type. */
25493 * The completion ring to send the completion event on. This should
25494 * be the NQ ID returned from the `nq_alloc` HWRM command.
25496 uint16_t cmpl_ring;
25498 * The sequence ID is used by the driver for tracking multiple
25499 * commands. This ID is treated as opaque data by the firmware and
25500 * the value is returned in the `hwrm_resp_hdr` upon completion.
25504 * The target ID of the command:
25505 * * 0x0-0xFFF8 - The function ID
25506 * * 0xFFF8-0xFFFE - Reserved for internal processors
25509 uint16_t target_id;
25511 * A physical address pointer pointing to a host buffer that the
25512 * command's response data will be written. This can be either a host
25513 * physical address (HPA) or a guest physical address (GPA) and must
25514 * point to a physically contiguous block of memory.
25516 uint64_t resp_addr;
25517 /* ID of the statistics context that is being queried. */
25518 uint32_t stat_ctx_id;
25519 uint8_t unused_0[4];
25520 } __attribute__((packed));
25522 /* hwrm_stat_ctx_free_output (size:128b/16B) */
25523 struct hwrm_stat_ctx_free_output {
25524 /* The specific error status for the command. */
25525 uint16_t error_code;
25526 /* The HWRM command request type. */
25528 /* The sequence ID from the original command. */
25530 /* The length of the response data in number of bytes. */
25532 /* This is the statistics context ID value. */
25533 uint32_t stat_ctx_id;
25534 uint8_t unused_0[3];
25536 * This field is used in Output records to indicate that the output
25537 * is completely written to RAM. This field should be read as '1'
25538 * to indicate that the output has been completely written.
25539 * When writing a command completion or response to an internal processor,
25540 * the order of writes has to be such that this field is written last.
25543 } __attribute__((packed));
25545 /***********************
25546 * hwrm_stat_ctx_query *
25547 ***********************/
25550 /* hwrm_stat_ctx_query_input (size:192b/24B) */
25551 struct hwrm_stat_ctx_query_input {
25552 /* The HWRM command request type. */
25555 * The completion ring to send the completion event on. This should
25556 * be the NQ ID returned from the `nq_alloc` HWRM command.
25558 uint16_t cmpl_ring;
25560 * The sequence ID is used by the driver for tracking multiple
25561 * commands. This ID is treated as opaque data by the firmware and
25562 * the value is returned in the `hwrm_resp_hdr` upon completion.
25566 * The target ID of the command:
25567 * * 0x0-0xFFF8 - The function ID
25568 * * 0xFFF8-0xFFFE - Reserved for internal processors
25571 uint16_t target_id;
25573 * A physical address pointer pointing to a host buffer that the
25574 * command's response data will be written. This can be either a host
25575 * physical address (HPA) or a guest physical address (GPA) and must
25576 * point to a physically contiguous block of memory.
25578 uint64_t resp_addr;
25579 /* ID of the statistics context that is being queried. */
25580 uint32_t stat_ctx_id;
25581 uint8_t unused_0[4];
25582 } __attribute__((packed));
25584 /* hwrm_stat_ctx_query_output (size:1408b/176B) */
25585 struct hwrm_stat_ctx_query_output {
25586 /* The specific error status for the command. */
25587 uint16_t error_code;
25588 /* The HWRM command request type. */
25590 /* The sequence ID from the original command. */
25592 /* The length of the response data in number of bytes. */
25594 /* Number of transmitted unicast packets */
25595 uint64_t tx_ucast_pkts;
25596 /* Number of transmitted multicast packets */
25597 uint64_t tx_mcast_pkts;
25598 /* Number of transmitted broadcast packets */
25599 uint64_t tx_bcast_pkts;
25600 /* Number of transmitted packets with error */
25601 uint64_t tx_err_pkts;
25602 /* Number of dropped packets on transmit path */
25603 uint64_t tx_drop_pkts;
25604 /* Number of transmitted bytes for unicast traffic */
25605 uint64_t tx_ucast_bytes;
25606 /* Number of transmitted bytes for multicast traffic */
25607 uint64_t tx_mcast_bytes;
25608 /* Number of transmitted bytes for broadcast traffic */
25609 uint64_t tx_bcast_bytes;
25610 /* Number of received unicast packets */
25611 uint64_t rx_ucast_pkts;
25612 /* Number of received multicast packets */
25613 uint64_t rx_mcast_pkts;
25614 /* Number of received broadcast packets */
25615 uint64_t rx_bcast_pkts;
25616 /* Number of received packets with error */
25617 uint64_t rx_err_pkts;
25618 /* Number of dropped packets on received path */
25619 uint64_t rx_drop_pkts;
25620 /* Number of received bytes for unicast traffic */
25621 uint64_t rx_ucast_bytes;
25622 /* Number of received bytes for multicast traffic */
25623 uint64_t rx_mcast_bytes;
25624 /* Number of received bytes for broadcast traffic */
25625 uint64_t rx_bcast_bytes;
25626 /* Number of aggregated unicast packets */
25627 uint64_t rx_agg_pkts;
25628 /* Number of aggregated unicast bytes */
25629 uint64_t rx_agg_bytes;
25630 /* Number of aggregation events */
25631 uint64_t rx_agg_events;
25632 /* Number of aborted aggregations */
25633 uint64_t rx_agg_aborts;
25634 uint8_t unused_0[7];
25636 * This field is used in Output records to indicate that the output
25637 * is completely written to RAM. This field should be read as '1'
25638 * to indicate that the output has been completely written.
25639 * When writing a command completion or response to an internal processor,
25640 * the order of writes has to be such that this field is written last.
25643 } __attribute__((packed));
25645 /***************************
25646 * hwrm_stat_ctx_clr_stats *
25647 ***************************/
25650 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */
25651 struct hwrm_stat_ctx_clr_stats_input {
25652 /* The HWRM command request type. */
25655 * The completion ring to send the completion event on. This should
25656 * be the NQ ID returned from the `nq_alloc` HWRM command.
25658 uint16_t cmpl_ring;
25660 * The sequence ID is used by the driver for tracking multiple
25661 * commands. This ID is treated as opaque data by the firmware and
25662 * the value is returned in the `hwrm_resp_hdr` upon completion.
25666 * The target ID of the command:
25667 * * 0x0-0xFFF8 - The function ID
25668 * * 0xFFF8-0xFFFE - Reserved for internal processors
25671 uint16_t target_id;
25673 * A physical address pointer pointing to a host buffer that the
25674 * command's response data will be written. This can be either a host
25675 * physical address (HPA) or a guest physical address (GPA) and must
25676 * point to a physically contiguous block of memory.
25678 uint64_t resp_addr;
25679 /* ID of the statistics context that is being queried. */
25680 uint32_t stat_ctx_id;
25681 uint8_t unused_0[4];
25682 } __attribute__((packed));
25684 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */
25685 struct hwrm_stat_ctx_clr_stats_output {
25686 /* The specific error status for the command. */
25687 uint16_t error_code;
25688 /* The HWRM command request type. */
25690 /* The sequence ID from the original command. */
25692 /* The length of the response data in number of bytes. */
25694 uint8_t unused_0[7];
25696 * This field is used in Output records to indicate that the output
25697 * is completely written to RAM. This field should be read as '1'
25698 * to indicate that the output has been completely written.
25699 * When writing a command completion or response to an internal processor,
25700 * the order of writes has to be such that this field is written last.
25703 } __attribute__((packed));
25705 /********************
25706 * hwrm_pcie_qstats *
25707 ********************/
25710 /* hwrm_pcie_qstats_input (size:256b/32B) */
25711 struct hwrm_pcie_qstats_input {
25712 /* The HWRM command request type. */
25715 * The completion ring to send the completion event on. This should
25716 * be the NQ ID returned from the `nq_alloc` HWRM command.
25718 uint16_t cmpl_ring;
25720 * The sequence ID is used by the driver for tracking multiple
25721 * commands. This ID is treated as opaque data by the firmware and
25722 * the value is returned in the `hwrm_resp_hdr` upon completion.
25726 * The target ID of the command:
25727 * * 0x0-0xFFF8 - The function ID
25728 * * 0xFFF8-0xFFFE - Reserved for internal processors
25731 uint16_t target_id;
25733 * A physical address pointer pointing to a host buffer that the
25734 * command's response data will be written. This can be either a host
25735 * physical address (HPA) or a guest physical address (GPA) and must
25736 * point to a physically contiguous block of memory.
25738 uint64_t resp_addr;
25740 * The size of PCIe statistics block in bytes.
25741 * Firmware will DMA the PCIe statistics to
25742 * the host with this field size in the response.
25744 uint16_t pcie_stat_size;
25745 uint8_t unused_0[6];
25747 * This is the host address where
25748 * PCIe statistics will be stored
25750 uint64_t pcie_stat_host_addr;
25751 } __attribute__((packed));
25753 /* hwrm_pcie_qstats_output (size:128b/16B) */
25754 struct hwrm_pcie_qstats_output {
25755 /* The specific error status for the command. */
25756 uint16_t error_code;
25757 /* The HWRM command request type. */
25759 /* The sequence ID from the original command. */
25761 /* The length of the response data in number of bytes. */
25763 /* The size of PCIe statistics block in bytes. */
25764 uint16_t pcie_stat_size;
25765 uint8_t unused_0[5];
25767 * This field is used in Output records to indicate that the output
25768 * is completely written to RAM. This field should be read as '1'
25769 * to indicate that the output has been completely written.
25770 * When writing a command completion or response to an internal processor,
25771 * the order of writes has to be such that this field is written last.
25774 } __attribute__((packed));
25776 /* Port Tx Statistics Formats */
25777 /* tx_port_stats (size:3264b/408B) */
25778 struct tx_port_stats {
25779 /* Total Number of 64 Bytes frames transmitted */
25780 uint64_t tx_64b_frames;
25781 /* Total Number of 65-127 Bytes frames transmitted */
25782 uint64_t tx_65b_127b_frames;
25783 /* Total Number of 128-255 Bytes frames transmitted */
25784 uint64_t tx_128b_255b_frames;
25785 /* Total Number of 256-511 Bytes frames transmitted */
25786 uint64_t tx_256b_511b_frames;
25787 /* Total Number of 512-1023 Bytes frames transmitted */
25788 uint64_t tx_512b_1023b_frames;
25789 /* Total Number of 1024-1518 Bytes frames transmitted */
25790 uint64_t tx_1024b_1518_frames;
25792 * Total Number of each good VLAN (exludes FCS errors)
25793 * frame transmitted which is 1519 to 1522 bytes in length
25794 * inclusive (excluding framing bits but including FCS bytes).
25796 uint64_t tx_good_vlan_frames;
25797 /* Total Number of 1519-2047 Bytes frames transmitted */
25798 uint64_t tx_1519b_2047_frames;
25799 /* Total Number of 2048-4095 Bytes frames transmitted */
25800 uint64_t tx_2048b_4095b_frames;
25801 /* Total Number of 4096-9216 Bytes frames transmitted */
25802 uint64_t tx_4096b_9216b_frames;
25803 /* Total Number of 9217-16383 Bytes frames transmitted */
25804 uint64_t tx_9217b_16383b_frames;
25805 /* Total Number of good frames transmitted */
25806 uint64_t tx_good_frames;
25807 /* Total Number of frames transmitted */
25808 uint64_t tx_total_frames;
25809 /* Total number of unicast frames transmitted */
25810 uint64_t tx_ucast_frames;
25811 /* Total number of multicast frames transmitted */
25812 uint64_t tx_mcast_frames;
25813 /* Total number of broadcast frames transmitted */
25814 uint64_t tx_bcast_frames;
25815 /* Total number of PAUSE control frames transmitted */
25816 uint64_t tx_pause_frames;
25818 * Total number of PFC/per-priority PAUSE
25819 * control frames transmitted
25821 uint64_t tx_pfc_frames;
25822 /* Total number of jabber frames transmitted */
25823 uint64_t tx_jabber_frames;
25824 /* Total number of frames transmitted with FCS error */
25825 uint64_t tx_fcs_err_frames;
25826 /* Total number of control frames transmitted */
25827 uint64_t tx_control_frames;
25828 /* Total number of over-sized frames transmitted */
25829 uint64_t tx_oversz_frames;
25830 /* Total number of frames with single deferral */
25831 uint64_t tx_single_dfrl_frames;
25832 /* Total number of frames with multiple deferrals */
25833 uint64_t tx_multi_dfrl_frames;
25834 /* Total number of frames with single collision */
25835 uint64_t tx_single_coll_frames;
25836 /* Total number of frames with multiple collisions */
25837 uint64_t tx_multi_coll_frames;
25838 /* Total number of frames with late collisions */
25839 uint64_t tx_late_coll_frames;
25840 /* Total number of frames with excessive collisions */
25841 uint64_t tx_excessive_coll_frames;
25842 /* Total number of fragmented frames transmitted */
25843 uint64_t tx_frag_frames;
25844 /* Total number of transmit errors */
25846 /* Total number of single VLAN tagged frames transmitted */
25847 uint64_t tx_tagged_frames;
25848 /* Total number of double VLAN tagged frames transmitted */
25849 uint64_t tx_dbl_tagged_frames;
25850 /* Total number of runt frames transmitted */
25851 uint64_t tx_runt_frames;
25852 /* Total number of TX FIFO under runs */
25853 uint64_t tx_fifo_underruns;
25855 * Total number of PFC frames with PFC enabled bit for
25856 * Pri 0 transmitted
25858 uint64_t tx_pfc_ena_frames_pri0;
25860 * Total number of PFC frames with PFC enabled bit for
25861 * Pri 1 transmitted
25863 uint64_t tx_pfc_ena_frames_pri1;
25865 * Total number of PFC frames with PFC enabled bit for
25866 * Pri 2 transmitted
25868 uint64_t tx_pfc_ena_frames_pri2;
25870 * Total number of PFC frames with PFC enabled bit for
25871 * Pri 3 transmitted
25873 uint64_t tx_pfc_ena_frames_pri3;
25875 * Total number of PFC frames with PFC enabled bit for
25876 * Pri 4 transmitted
25878 uint64_t tx_pfc_ena_frames_pri4;
25880 * Total number of PFC frames with PFC enabled bit for
25881 * Pri 5 transmitted
25883 uint64_t tx_pfc_ena_frames_pri5;
25885 * Total number of PFC frames with PFC enabled bit for
25886 * Pri 6 transmitted
25888 uint64_t tx_pfc_ena_frames_pri6;
25890 * Total number of PFC frames with PFC enabled bit for
25891 * Pri 7 transmitted
25893 uint64_t tx_pfc_ena_frames_pri7;
25894 /* Total number of EEE LPI Events on TX */
25895 uint64_t tx_eee_lpi_events;
25896 /* EEE LPI Duration Counter on TX */
25897 uint64_t tx_eee_lpi_duration;
25899 * Total number of Link Level Flow Control (LLFC) messages
25902 uint64_t tx_llfc_logical_msgs;
25903 /* Total number of HCFC messages transmitted */
25904 uint64_t tx_hcfc_msgs;
25905 /* Total number of TX collisions */
25906 uint64_t tx_total_collisions;
25907 /* Total number of transmitted bytes */
25909 /* Total number of end-to-end HOL frames */
25910 uint64_t tx_xthol_frames;
25911 /* Total Tx Drops per Port reported by STATS block */
25912 uint64_t tx_stat_discard;
25913 /* Total Tx Error Drops per Port reported by STATS block */
25914 uint64_t tx_stat_error;
25915 } __attribute__((packed));
25917 /* Port Rx Statistics Formats */
25918 /* rx_port_stats (size:4224b/528B) */
25919 struct rx_port_stats {
25920 /* Total Number of 64 Bytes frames received */
25921 uint64_t rx_64b_frames;
25922 /* Total Number of 65-127 Bytes frames received */
25923 uint64_t rx_65b_127b_frames;
25924 /* Total Number of 128-255 Bytes frames received */
25925 uint64_t rx_128b_255b_frames;
25926 /* Total Number of 256-511 Bytes frames received */
25927 uint64_t rx_256b_511b_frames;
25928 /* Total Number of 512-1023 Bytes frames received */
25929 uint64_t rx_512b_1023b_frames;
25930 /* Total Number of 1024-1518 Bytes frames received */
25931 uint64_t rx_1024b_1518_frames;
25933 * Total Number of each good VLAN (exludes FCS errors)
25934 * frame received which is 1519 to 1522 bytes in length
25935 * inclusive (excluding framing bits but including FCS bytes).
25937 uint64_t rx_good_vlan_frames;
25938 /* Total Number of 1519-2047 Bytes frames received */
25939 uint64_t rx_1519b_2047b_frames;
25940 /* Total Number of 2048-4095 Bytes frames received */
25941 uint64_t rx_2048b_4095b_frames;
25942 /* Total Number of 4096-9216 Bytes frames received */
25943 uint64_t rx_4096b_9216b_frames;
25944 /* Total Number of 9217-16383 Bytes frames received */
25945 uint64_t rx_9217b_16383b_frames;
25946 /* Total number of frames received */
25947 uint64_t rx_total_frames;
25948 /* Total number of unicast frames received */
25949 uint64_t rx_ucast_frames;
25950 /* Total number of multicast frames received */
25951 uint64_t rx_mcast_frames;
25952 /* Total number of broadcast frames received */
25953 uint64_t rx_bcast_frames;
25954 /* Total number of received frames with FCS error */
25955 uint64_t rx_fcs_err_frames;
25956 /* Total number of control frames received */
25957 uint64_t rx_ctrl_frames;
25958 /* Total number of PAUSE frames received */
25959 uint64_t rx_pause_frames;
25960 /* Total number of PFC frames received */
25961 uint64_t rx_pfc_frames;
25963 * Total number of frames received with an unsupported
25966 uint64_t rx_unsupported_opcode_frames;
25968 * Total number of frames received with an unsupported
25969 * DA for pause and PFC
25971 uint64_t rx_unsupported_da_pausepfc_frames;
25972 /* Total number of frames received with an unsupported SA */
25973 uint64_t rx_wrong_sa_frames;
25974 /* Total number of received packets with alignment error */
25975 uint64_t rx_align_err_frames;
25976 /* Total number of received frames with out-of-range length */
25977 uint64_t rx_oor_len_frames;
25978 /* Total number of received frames with error termination */
25979 uint64_t rx_code_err_frames;
25981 * Total number of received frames with a false carrier is
25982 * detected during idle, as defined by RX_ER samples active
25983 * and RXD is 0xE. The event is reported along with the
25984 * statistics generated on the next received frame. Only
25985 * one false carrier condition can be detected and logged
25988 * Carrier event, valid for 10M/100M speed modes only.
25990 uint64_t rx_false_carrier_frames;
25991 /* Total number of over-sized frames received */
25992 uint64_t rx_ovrsz_frames;
25993 /* Total number of jabber packets received */
25994 uint64_t rx_jbr_frames;
25995 /* Total number of received frames with MTU error */
25996 uint64_t rx_mtu_err_frames;
25997 /* Total number of received frames with CRC match */
25998 uint64_t rx_match_crc_frames;
25999 /* Total number of frames received promiscuously */
26000 uint64_t rx_promiscuous_frames;
26002 * Total number of received frames with one or two VLAN
26005 uint64_t rx_tagged_frames;
26006 /* Total number of received frames with two VLAN tags */
26007 uint64_t rx_double_tagged_frames;
26008 /* Total number of truncated frames received */
26009 uint64_t rx_trunc_frames;
26010 /* Total number of good frames (without errors) received */
26011 uint64_t rx_good_frames;
26013 * Total number of received PFC frames with transition from
26014 * XON to XOFF on Pri 0
26016 uint64_t rx_pfc_xon2xoff_frames_pri0;
26018 * Total number of received PFC frames with transition from
26019 * XON to XOFF on Pri 1
26021 uint64_t rx_pfc_xon2xoff_frames_pri1;
26023 * Total number of received PFC frames with transition from
26024 * XON to XOFF on Pri 2
26026 uint64_t rx_pfc_xon2xoff_frames_pri2;
26028 * Total number of received PFC frames with transition from
26029 * XON to XOFF on Pri 3
26031 uint64_t rx_pfc_xon2xoff_frames_pri3;
26033 * Total number of received PFC frames with transition from
26034 * XON to XOFF on Pri 4
26036 uint64_t rx_pfc_xon2xoff_frames_pri4;
26038 * Total number of received PFC frames with transition from
26039 * XON to XOFF on Pri 5
26041 uint64_t rx_pfc_xon2xoff_frames_pri5;
26043 * Total number of received PFC frames with transition from
26044 * XON to XOFF on Pri 6
26046 uint64_t rx_pfc_xon2xoff_frames_pri6;
26048 * Total number of received PFC frames with transition from
26049 * XON to XOFF on Pri 7
26051 uint64_t rx_pfc_xon2xoff_frames_pri7;
26053 * Total number of received PFC frames with PFC enabled
26056 uint64_t rx_pfc_ena_frames_pri0;
26058 * Total number of received PFC frames with PFC enabled
26061 uint64_t rx_pfc_ena_frames_pri1;
26063 * Total number of received PFC frames with PFC enabled
26066 uint64_t rx_pfc_ena_frames_pri2;
26068 * Total number of received PFC frames with PFC enabled
26071 uint64_t rx_pfc_ena_frames_pri3;
26073 * Total number of received PFC frames with PFC enabled
26076 uint64_t rx_pfc_ena_frames_pri4;
26078 * Total number of received PFC frames with PFC enabled
26081 uint64_t rx_pfc_ena_frames_pri5;
26083 * Total number of received PFC frames with PFC enabled
26086 uint64_t rx_pfc_ena_frames_pri6;
26088 * Total number of received PFC frames with PFC enabled
26091 uint64_t rx_pfc_ena_frames_pri7;
26092 /* Total Number of frames received with SCH CRC error */
26093 uint64_t rx_sch_crc_err_frames;
26094 /* Total Number of under-sized frames received */
26095 uint64_t rx_undrsz_frames;
26096 /* Total Number of fragmented frames received */
26097 uint64_t rx_frag_frames;
26098 /* Total number of RX EEE LPI Events */
26099 uint64_t rx_eee_lpi_events;
26100 /* EEE LPI Duration Counter on RX */
26101 uint64_t rx_eee_lpi_duration;
26103 * Total number of physical type Link Level Flow Control
26104 * (LLFC) messages received
26106 uint64_t rx_llfc_physical_msgs;
26108 * Total number of logical type Link Level Flow Control
26109 * (LLFC) messages received
26111 uint64_t rx_llfc_logical_msgs;
26113 * Total number of logical type Link Level Flow Control
26114 * (LLFC) messages received with CRC error
26116 uint64_t rx_llfc_msgs_with_crc_err;
26117 /* Total number of HCFC messages received */
26118 uint64_t rx_hcfc_msgs;
26119 /* Total number of HCFC messages received with CRC error */
26120 uint64_t rx_hcfc_msgs_with_crc_err;
26121 /* Total number of received bytes */
26123 /* Total number of bytes received in runt frames */
26124 uint64_t rx_runt_bytes;
26125 /* Total number of runt frames received */
26126 uint64_t rx_runt_frames;
26127 /* Total Rx Discards per Port reported by STATS block */
26128 uint64_t rx_stat_discard;
26129 uint64_t rx_stat_err;
26130 } __attribute__((packed));
26132 /* Port Rx Statistics extended Formats */
26133 /* rx_port_stats_ext (size:320b/40B) */
26134 struct rx_port_stats_ext {
26135 /* Number of times link state changed to down */
26136 uint64_t link_down_events;
26137 /* Number of times the idle rings with pause bit are found */
26138 uint64_t continuous_pause_events;
26139 /* Number of times the active rings pause bit resumed back */
26140 uint64_t resume_pause_events;
26141 /* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */
26142 uint64_t continuous_roce_pause_events;
26143 /* Number of times, the ROCE cos queue PFC is enabled back */
26144 uint64_t resume_roce_pause_events;
26145 } __attribute__((packed));
26147 /* PCIe Statistics Formats */
26148 /* pcie_ctx_hw_stats (size:768b/96B) */
26149 struct pcie_ctx_hw_stats {
26150 /* Number of physical layer receiver errors */
26151 uint64_t pcie_pl_signal_integrity;
26152 /* Number of DLLP CRC errors detected by Data Link Layer */
26153 uint64_t pcie_dl_signal_integrity;
26155 * Number of TLP LCRC and sequence number errors detected
26156 * by Data Link Layer
26158 uint64_t pcie_tl_signal_integrity;
26159 /* Number of times LTSSM entered Recovery state */
26160 uint64_t pcie_link_integrity;
26161 /* Number of TLP bytes that have been trasmitted */
26162 uint64_t pcie_tx_traffic_rate;
26163 /* Number of TLP bytes that have been received */
26164 uint64_t pcie_rx_traffic_rate;
26165 /* Number of DLLP bytes that have been trasmitted */
26166 uint64_t pcie_tx_dllp_statistics;
26167 /* Number of DLLP bytes that have been received */
26168 uint64_t pcie_rx_dllp_statistics;
26170 * Number of times spent in each phase of gen3
26173 uint64_t pcie_equalization_time;
26174 /* Records the last 16 transitions of the LTSSM */
26175 uint32_t pcie_ltssm_histogram[4];
26177 * Record the last 8 reasons on why LTSSM transitioned
26180 uint64_t pcie_recovery_histogram;
26181 } __attribute__((packed));
26183 /**********************
26184 * hwrm_exec_fwd_resp *
26185 **********************/
26188 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */
26189 struct hwrm_exec_fwd_resp_input {
26190 /* The HWRM command request type. */
26193 * The completion ring to send the completion event on. This should
26194 * be the NQ ID returned from the `nq_alloc` HWRM command.
26196 uint16_t cmpl_ring;
26198 * The sequence ID is used by the driver for tracking multiple
26199 * commands. This ID is treated as opaque data by the firmware and
26200 * the value is returned in the `hwrm_resp_hdr` upon completion.
26204 * The target ID of the command:
26205 * * 0x0-0xFFF8 - The function ID
26206 * * 0xFFF8-0xFFFE - Reserved for internal processors
26209 uint16_t target_id;
26211 * A physical address pointer pointing to a host buffer that the
26212 * command's response data will be written. This can be either a host
26213 * physical address (HPA) or a guest physical address (GPA) and must
26214 * point to a physically contiguous block of memory.
26216 uint64_t resp_addr;
26218 * This is an encapsulated request. This request should
26219 * be executed by the HWRM and the response should be
26220 * provided in the response buffer inside the encapsulated
26223 uint32_t encap_request[26];
26225 * This value indicates the target id of the response to
26226 * the encapsulated request.
26227 * 0x0 - 0xFFF8 - Used for function ids
26228 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26231 uint16_t encap_resp_target_id;
26232 uint8_t unused_0[6];
26233 } __attribute__((packed));
26235 /* hwrm_exec_fwd_resp_output (size:128b/16B) */
26236 struct hwrm_exec_fwd_resp_output {
26237 /* The specific error status for the command. */
26238 uint16_t error_code;
26239 /* The HWRM command request type. */
26241 /* The sequence ID from the original command. */
26243 /* The length of the response data in number of bytes. */
26245 uint8_t unused_0[7];
26247 * This field is used in Output records to indicate that the output
26248 * is completely written to RAM. This field should be read as '1'
26249 * to indicate that the output has been completely written.
26250 * When writing a command completion or response to an internal processor,
26251 * the order of writes has to be such that this field is written last.
26254 } __attribute__((packed));
26256 /************************
26257 * hwrm_reject_fwd_resp *
26258 ************************/
26261 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */
26262 struct hwrm_reject_fwd_resp_input {
26263 /* The HWRM command request type. */
26266 * The completion ring to send the completion event on. This should
26267 * be the NQ ID returned from the `nq_alloc` HWRM command.
26269 uint16_t cmpl_ring;
26271 * The sequence ID is used by the driver for tracking multiple
26272 * commands. This ID is treated as opaque data by the firmware and
26273 * the value is returned in the `hwrm_resp_hdr` upon completion.
26277 * The target ID of the command:
26278 * * 0x0-0xFFF8 - The function ID
26279 * * 0xFFF8-0xFFFE - Reserved for internal processors
26282 uint16_t target_id;
26284 * A physical address pointer pointing to a host buffer that the
26285 * command's response data will be written. This can be either a host
26286 * physical address (HPA) or a guest physical address (GPA) and must
26287 * point to a physically contiguous block of memory.
26289 uint64_t resp_addr;
26291 * This is an encapsulated request. This request should
26292 * be rejected by the HWRM and the error response should be
26293 * provided in the response buffer inside the encapsulated
26296 uint32_t encap_request[26];
26298 * This value indicates the target id of the response to
26299 * the encapsulated request.
26300 * 0x0 - 0xFFF8 - Used for function ids
26301 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26304 uint16_t encap_resp_target_id;
26305 uint8_t unused_0[6];
26306 } __attribute__((packed));
26308 /* hwrm_reject_fwd_resp_output (size:128b/16B) */
26309 struct hwrm_reject_fwd_resp_output {
26310 /* The specific error status for the command. */
26311 uint16_t error_code;
26312 /* The HWRM command request type. */
26314 /* The sequence ID from the original command. */
26316 /* The length of the response data in number of bytes. */
26318 uint8_t unused_0[7];
26320 * This field is used in Output records to indicate that the output
26321 * is completely written to RAM. This field should be read as '1'
26322 * to indicate that the output has been completely written.
26323 * When writing a command completion or response to an internal processor,
26324 * the order of writes has to be such that this field is written last.
26327 } __attribute__((packed));
26334 /* hwrm_fwd_resp_input (size:1024b/128B) */
26335 struct hwrm_fwd_resp_input {
26336 /* The HWRM command request type. */
26339 * The completion ring to send the completion event on. This should
26340 * be the NQ ID returned from the `nq_alloc` HWRM command.
26342 uint16_t cmpl_ring;
26344 * The sequence ID is used by the driver for tracking multiple
26345 * commands. This ID is treated as opaque data by the firmware and
26346 * the value is returned in the `hwrm_resp_hdr` upon completion.
26350 * The target ID of the command:
26351 * * 0x0-0xFFF8 - The function ID
26352 * * 0xFFF8-0xFFFE - Reserved for internal processors
26355 uint16_t target_id;
26357 * A physical address pointer pointing to a host buffer that the
26358 * command's response data will be written. This can be either a host
26359 * physical address (HPA) or a guest physical address (GPA) and must
26360 * point to a physically contiguous block of memory.
26362 uint64_t resp_addr;
26364 * This value indicates the target id of the encapsulated
26366 * 0x0 - 0xFFF8 - Used for function ids
26367 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26370 uint16_t encap_resp_target_id;
26372 * This value indicates the completion ring the encapsulated
26373 * response will be optionally completed on. If the value is
26374 * -1, then no CR completion shall be generated for the
26375 * encapsulated response. Any other value must be a
26376 * valid CR ring_id value. If a valid encap_resp_cmpl_ring
26377 * is provided, then a CR completion shall be generated for
26378 * the encapsulated response.
26380 uint16_t encap_resp_cmpl_ring;
26381 /* This field indicates the length of encapsulated response. */
26382 uint16_t encap_resp_len;
26386 * This is the host address where the encapsulated response
26388 * This area must be 16B aligned and must be cleared to zero
26389 * before the original request is made.
26391 uint64_t encap_resp_addr;
26392 /* This is an encapsulated response. */
26393 uint32_t encap_resp[24];
26394 } __attribute__((packed));
26396 /* hwrm_fwd_resp_output (size:128b/16B) */
26397 struct hwrm_fwd_resp_output {
26398 /* The specific error status for the command. */
26399 uint16_t error_code;
26400 /* The HWRM command request type. */
26402 /* The sequence ID from the original command. */
26404 /* The length of the response data in number of bytes. */
26406 uint8_t unused_0[7];
26408 * This field is used in Output records to indicate that the output
26409 * is completely written to RAM. This field should be read as '1'
26410 * to indicate that the output has been completely written.
26411 * When writing a command completion or response to an internal processor,
26412 * the order of writes has to be such that this field is written last.
26415 } __attribute__((packed));
26417 /*****************************
26418 * hwrm_fwd_async_event_cmpl *
26419 *****************************/
26422 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */
26423 struct hwrm_fwd_async_event_cmpl_input {
26424 /* The HWRM command request type. */
26427 * The completion ring to send the completion event on. This should
26428 * be the NQ ID returned from the `nq_alloc` HWRM command.
26430 uint16_t cmpl_ring;
26432 * The sequence ID is used by the driver for tracking multiple
26433 * commands. This ID is treated as opaque data by the firmware and
26434 * the value is returned in the `hwrm_resp_hdr` upon completion.
26438 * The target ID of the command:
26439 * * 0x0-0xFFF8 - The function ID
26440 * * 0xFFF8-0xFFFE - Reserved for internal processors
26443 uint16_t target_id;
26445 * A physical address pointer pointing to a host buffer that the
26446 * command's response data will be written. This can be either a host
26447 * physical address (HPA) or a guest physical address (GPA) and must
26448 * point to a physically contiguous block of memory.
26450 uint64_t resp_addr;
26452 * This value indicates the target id of the encapsulated
26453 * asynchronous event.
26454 * 0x0 - 0xFFF8 - Used for function ids
26455 * 0xFFF8 - 0xFFFE - Reserved for internal processors
26456 * 0xFFFF - Broadcast to all children VFs (only applicable when
26457 * a PF is the requester)
26459 uint16_t encap_async_event_target_id;
26460 uint8_t unused_0[6];
26461 /* This is an encapsulated asynchronous event completion. */
26462 uint32_t encap_async_event_cmpl[4];
26463 } __attribute__((packed));
26465 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */
26466 struct hwrm_fwd_async_event_cmpl_output {
26467 /* The specific error status for the command. */
26468 uint16_t error_code;
26469 /* The HWRM command request type. */
26471 /* The sequence ID from the original command. */
26473 /* The length of the response data in number of bytes. */
26475 uint8_t unused_0[7];
26477 * This field is used in Output records to indicate that the output
26478 * is completely written to RAM. This field should be read as '1'
26479 * to indicate that the output has been completely written.
26480 * When writing a command completion or response to an internal processor,
26481 * the order of writes has to be such that this field is written last.
26484 } __attribute__((packed));
26486 /**************************
26487 * hwrm_nvm_raw_write_blk *
26488 **************************/
26491 /* hwrm_nvm_raw_write_blk_input (size:256b/32B) */
26492 struct hwrm_nvm_raw_write_blk_input {
26493 /* The HWRM command request type. */
26496 * The completion ring to send the completion event on. This should
26497 * be the NQ ID returned from the `nq_alloc` HWRM command.
26499 uint16_t cmpl_ring;
26501 * The sequence ID is used by the driver for tracking multiple
26502 * commands. This ID is treated as opaque data by the firmware and
26503 * the value is returned in the `hwrm_resp_hdr` upon completion.
26507 * The target ID of the command:
26508 * * 0x0-0xFFF8 - The function ID
26509 * * 0xFFF8-0xFFFE - Reserved for internal processors
26512 uint16_t target_id;
26514 * A physical address pointer pointing to a host buffer that the
26515 * command's response data will be written. This can be either a host
26516 * physical address (HPA) or a guest physical address (GPA) and must
26517 * point to a physically contiguous block of memory.
26519 uint64_t resp_addr;
26521 * 64-bit Host Source Address.
26522 * This is the loation of the source data to be written.
26524 uint64_t host_src_addr;
26526 * 32-bit Destination Address.
26527 * This is the NVRAM byte-offset where the source data will be written to.
26529 uint32_t dest_addr;
26530 /* Length of data to be written, in bytes. */
26532 } __attribute__((packed));
26534 /* hwrm_nvm_raw_write_blk_output (size:128b/16B) */
26535 struct hwrm_nvm_raw_write_blk_output {
26536 /* The specific error status for the command. */
26537 uint16_t error_code;
26538 /* The HWRM command request type. */
26540 /* The sequence ID from the original command. */
26542 /* The length of the response data in number of bytes. */
26544 uint8_t unused_0[7];
26546 * This field is used in Output records to indicate that the output
26547 * is completely written to RAM. This field should be read as '1'
26548 * to indicate that the output has been completely written.
26549 * When writing a command completion or response to an internal processor,
26550 * the order of writes has to be such that this field is written last.
26553 } __attribute__((packed));
26560 /* hwrm_nvm_read_input (size:320b/40B) */
26561 struct hwrm_nvm_read_input {
26562 /* The HWRM command request type. */
26565 * The completion ring to send the completion event on. This should
26566 * be the NQ ID returned from the `nq_alloc` HWRM command.
26568 uint16_t cmpl_ring;
26570 * The sequence ID is used by the driver for tracking multiple
26571 * commands. This ID is treated as opaque data by the firmware and
26572 * the value is returned in the `hwrm_resp_hdr` upon completion.
26576 * The target ID of the command:
26577 * * 0x0-0xFFF8 - The function ID
26578 * * 0xFFF8-0xFFFE - Reserved for internal processors
26581 uint16_t target_id;
26583 * A physical address pointer pointing to a host buffer that the
26584 * command's response data will be written. This can be either a host
26585 * physical address (HPA) or a guest physical address (GPA) and must
26586 * point to a physically contiguous block of memory.
26588 uint64_t resp_addr;
26590 * 64-bit Host Destination Address.
26591 * This is the host address where the data will be written to.
26593 uint64_t host_dest_addr;
26594 /* The 0-based index of the directory entry. */
26596 uint8_t unused_0[2];
26597 /* The NVRAM byte-offset to read from. */
26599 /* The length of the data to be read, in bytes. */
26601 uint8_t unused_1[4];
26602 } __attribute__((packed));
26604 /* hwrm_nvm_read_output (size:128b/16B) */
26605 struct hwrm_nvm_read_output {
26606 /* The specific error status for the command. */
26607 uint16_t error_code;
26608 /* The HWRM command request type. */
26610 /* The sequence ID from the original command. */
26612 /* The length of the response data in number of bytes. */
26614 uint8_t unused_0[7];
26616 * This field is used in Output records to indicate that the output
26617 * is completely written to RAM. This field should be read as '1'
26618 * to indicate that the output has been completely written.
26619 * When writing a command completion or response to an internal processor,
26620 * the order of writes has to be such that this field is written last.
26623 } __attribute__((packed));
26625 /*********************
26626 * hwrm_nvm_raw_dump *
26627 *********************/
26630 /* hwrm_nvm_raw_dump_input (size:256b/32B) */
26631 struct hwrm_nvm_raw_dump_input {
26632 /* The HWRM command request type. */
26635 * The completion ring to send the completion event on. This should
26636 * be the NQ ID returned from the `nq_alloc` HWRM command.
26638 uint16_t cmpl_ring;
26640 * The sequence ID is used by the driver for tracking multiple
26641 * commands. This ID is treated as opaque data by the firmware and
26642 * the value is returned in the `hwrm_resp_hdr` upon completion.
26646 * The target ID of the command:
26647 * * 0x0-0xFFF8 - The function ID
26648 * * 0xFFF8-0xFFFE - Reserved for internal processors
26651 uint16_t target_id;
26653 * A physical address pointer pointing to a host buffer that the
26654 * command's response data will be written. This can be either a host
26655 * physical address (HPA) or a guest physical address (GPA) and must
26656 * point to a physically contiguous block of memory.
26658 uint64_t resp_addr;
26660 * 64-bit Host Destination Address.
26661 * This is the host address where the data will be written to.
26663 uint64_t host_dest_addr;
26664 /* 32-bit NVRAM byte-offset to read from. */
26666 /* Total length of NVRAM contents to be read, in bytes. */
26668 } __attribute__((packed));
26670 /* hwrm_nvm_raw_dump_output (size:128b/16B) */
26671 struct hwrm_nvm_raw_dump_output {
26672 /* The specific error status for the command. */
26673 uint16_t error_code;
26674 /* The HWRM command request type. */
26676 /* The sequence ID from the original command. */
26678 /* The length of the response data in number of bytes. */
26680 uint8_t unused_0[7];
26682 * This field is used in Output records to indicate that the output
26683 * is completely written to RAM. This field should be read as '1'
26684 * to indicate that the output has been completely written.
26685 * When writing a command completion or response to an internal processor,
26686 * the order of writes has to be such that this field is written last.
26689 } __attribute__((packed));
26691 /****************************
26692 * hwrm_nvm_get_dir_entries *
26693 ****************************/
26696 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */
26697 struct hwrm_nvm_get_dir_entries_input {
26698 /* The HWRM command request type. */
26701 * The completion ring to send the completion event on. This should
26702 * be the NQ ID returned from the `nq_alloc` HWRM command.
26704 uint16_t cmpl_ring;
26706 * The sequence ID is used by the driver for tracking multiple
26707 * commands. This ID is treated as opaque data by the firmware and
26708 * the value is returned in the `hwrm_resp_hdr` upon completion.
26712 * The target ID of the command:
26713 * * 0x0-0xFFF8 - The function ID
26714 * * 0xFFF8-0xFFFE - Reserved for internal processors
26717 uint16_t target_id;
26719 * A physical address pointer pointing to a host buffer that the
26720 * command's response data will be written. This can be either a host
26721 * physical address (HPA) or a guest physical address (GPA) and must
26722 * point to a physically contiguous block of memory.
26724 uint64_t resp_addr;
26726 * 64-bit Host Destination Address.
26727 * This is the host address where the directory will be written.
26729 uint64_t host_dest_addr;
26730 } __attribute__((packed));
26732 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */
26733 struct hwrm_nvm_get_dir_entries_output {
26734 /* The specific error status for the command. */
26735 uint16_t error_code;
26736 /* The HWRM command request type. */
26738 /* The sequence ID from the original command. */
26740 /* The length of the response data in number of bytes. */
26742 uint8_t unused_0[7];
26744 * This field is used in Output records to indicate that the output
26745 * is completely written to RAM. This field should be read as '1'
26746 * to indicate that the output has been completely written.
26747 * When writing a command completion or response to an internal processor,
26748 * the order of writes has to be such that this field is written last.
26751 } __attribute__((packed));
26753 /*************************
26754 * hwrm_nvm_get_dir_info *
26755 *************************/
26758 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */
26759 struct hwrm_nvm_get_dir_info_input {
26760 /* The HWRM command request type. */
26763 * The completion ring to send the completion event on. This should
26764 * be the NQ ID returned from the `nq_alloc` HWRM command.
26766 uint16_t cmpl_ring;
26768 * The sequence ID is used by the driver for tracking multiple
26769 * commands. This ID is treated as opaque data by the firmware and
26770 * the value is returned in the `hwrm_resp_hdr` upon completion.
26774 * The target ID of the command:
26775 * * 0x0-0xFFF8 - The function ID
26776 * * 0xFFF8-0xFFFE - Reserved for internal processors
26779 uint16_t target_id;
26781 * A physical address pointer pointing to a host buffer that the
26782 * command's response data will be written. This can be either a host
26783 * physical address (HPA) or a guest physical address (GPA) and must
26784 * point to a physically contiguous block of memory.
26786 uint64_t resp_addr;
26787 } __attribute__((packed));
26789 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */
26790 struct hwrm_nvm_get_dir_info_output {
26791 /* The specific error status for the command. */
26792 uint16_t error_code;
26793 /* The HWRM command request type. */
26795 /* The sequence ID from the original command. */
26797 /* The length of the response data in number of bytes. */
26799 /* Number of directory entries in the directory. */
26801 /* Size of each directory entry, in bytes. */
26802 uint32_t entry_length;
26803 uint8_t unused_0[7];
26805 * This field is used in Output records to indicate that the output
26806 * is completely written to RAM. This field should be read as '1'
26807 * to indicate that the output has been completely written.
26808 * When writing a command completion or response to an internal processor,
26809 * the order of writes has to be such that this field is written last.
26812 } __attribute__((packed));
26814 /******************
26816 ******************/
26819 /* hwrm_nvm_write_input (size:384b/48B) */
26820 struct hwrm_nvm_write_input {
26821 /* The HWRM command request type. */
26824 * The completion ring to send the completion event on. This should
26825 * be the NQ ID returned from the `nq_alloc` HWRM command.
26827 uint16_t cmpl_ring;
26829 * The sequence ID is used by the driver for tracking multiple
26830 * commands. This ID is treated as opaque data by the firmware and
26831 * the value is returned in the `hwrm_resp_hdr` upon completion.
26835 * The target ID of the command:
26836 * * 0x0-0xFFF8 - The function ID
26837 * * 0xFFF8-0xFFFE - Reserved for internal processors
26840 uint16_t target_id;
26842 * A physical address pointer pointing to a host buffer that the
26843 * command's response data will be written. This can be either a host
26844 * physical address (HPA) or a guest physical address (GPA) and must
26845 * point to a physically contiguous block of memory.
26847 uint64_t resp_addr;
26849 * 64-bit Host Source Address.
26850 * This is where the source data is.
26852 uint64_t host_src_addr;
26853 /* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */
26856 * Directory ordinal.
26857 * The 0-based instance of the combined Directory Entry Type and Extension.
26859 uint16_t dir_ordinal;
26860 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file bnxnvm_defs.h). */
26862 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */
26865 * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.
26866 * The data length stored in the directory entry will be updated to reflect this value once the write is complete.
26868 uint32_t dir_data_length;
26873 * When this bit is '1', the original active image
26874 * will not be removed. TBD: what purpose is this?
26876 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \
26879 * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).
26880 * If this value is less than the specified data length, it will be ignored.
26881 * The response will contain the actual allocated item length, which may be greater than the requested item length.
26882 * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accomodate
26883 * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).
26885 uint32_t dir_item_length;
26887 } __attribute__((packed));
26889 /* hwrm_nvm_write_output (size:128b/16B) */
26890 struct hwrm_nvm_write_output {
26891 /* The specific error status for the command. */
26892 uint16_t error_code;
26893 /* The HWRM command request type. */
26895 /* The sequence ID from the original command. */
26897 /* The length of the response data in number of bytes. */
26900 * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.
26901 * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.
26903 uint32_t dir_item_length;
26904 /* The directory index of the created or modified item. */
26908 * This field is used in Output records to indicate that the output
26909 * is completely written to RAM. This field should be read as '1'
26910 * to indicate that the output has been completely written.
26911 * When writing a command completion or response to an internal processor,
26912 * the order of writes has to be such that this field is written last.
26915 } __attribute__((packed));
26917 /* hwrm_nvm_write_cmd_err (size:64b/8B) */
26918 struct hwrm_nvm_write_cmd_err {
26920 * command specific error codes that goes to
26921 * the cmd_err field in Common HWRM Error Response.
26924 /* Unknown error */
26925 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
26926 /* Unable to complete operation due to fragmentation */
26927 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
26928 /* nvm is completely full. */
26929 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
26930 #define HWRM_NVM_WRITE_CMD_ERR_CODE_LAST \
26931 HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE
26932 uint8_t unused_0[7];
26933 } __attribute__((packed));
26935 /*******************
26936 * hwrm_nvm_modify *
26937 *******************/
26940 /* hwrm_nvm_modify_input (size:320b/40B) */
26941 struct hwrm_nvm_modify_input {
26942 /* The HWRM command request type. */
26945 * The completion ring to send the completion event on. This should
26946 * be the NQ ID returned from the `nq_alloc` HWRM command.
26948 uint16_t cmpl_ring;
26950 * The sequence ID is used by the driver for tracking multiple
26951 * commands. This ID is treated as opaque data by the firmware and
26952 * the value is returned in the `hwrm_resp_hdr` upon completion.
26956 * The target ID of the command:
26957 * * 0x0-0xFFF8 - The function ID
26958 * * 0xFFF8-0xFFFE - Reserved for internal processors
26961 uint16_t target_id;
26963 * A physical address pointer pointing to a host buffer that the
26964 * command's response data will be written. This can be either a host
26965 * physical address (HPA) or a guest physical address (GPA) and must
26966 * point to a physically contiguous block of memory.
26968 uint64_t resp_addr;
26970 * 64-bit Host Source Address.
26971 * This is where the modified data is.
26973 uint64_t host_src_addr;
26974 /* 16-bit directory entry index. */
26976 uint8_t unused_0[2];
26977 /* 32-bit NVRAM byte-offset to modify content from. */
26980 * Length of data to be modified, in bytes. The length shall
26984 uint8_t unused_1[4];
26985 } __attribute__((packed));
26987 /* hwrm_nvm_modify_output (size:128b/16B) */
26988 struct hwrm_nvm_modify_output {
26989 /* The specific error status for the command. */
26990 uint16_t error_code;
26991 /* The HWRM command request type. */
26993 /* The sequence ID from the original command. */
26995 /* The length of the response data in number of bytes. */
26997 uint8_t unused_0[7];
26999 * This field is used in Output records to indicate that the output
27000 * is completely written to RAM. This field should be read as '1'
27001 * to indicate that the output has been completely written.
27002 * When writing a command completion or response to an internal processor,
27003 * the order of writes has to be such that this field is written last.
27006 } __attribute__((packed));
27008 /***************************
27009 * hwrm_nvm_find_dir_entry *
27010 ***************************/
27013 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */
27014 struct hwrm_nvm_find_dir_entry_input {
27015 /* The HWRM command request type. */
27018 * The completion ring to send the completion event on. This should
27019 * be the NQ ID returned from the `nq_alloc` HWRM command.
27021 uint16_t cmpl_ring;
27023 * The sequence ID is used by the driver for tracking multiple
27024 * commands. This ID is treated as opaque data by the firmware and
27025 * the value is returned in the `hwrm_resp_hdr` upon completion.
27029 * The target ID of the command:
27030 * * 0x0-0xFFF8 - The function ID
27031 * * 0xFFF8-0xFFFE - Reserved for internal processors
27034 uint16_t target_id;
27036 * A physical address pointer pointing to a host buffer that the
27037 * command's response data will be written. This can be either a host
27038 * physical address (HPA) or a guest physical address (GPA) and must
27039 * point to a physically contiguous block of memory.
27041 uint64_t resp_addr;
27044 * This bit must be '1' for the dir_idx_valid field to be
27047 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID \
27049 /* Directory Entry Index */
27051 /* Directory Entry (Image) Type */
27054 * Directory ordinal.
27055 * The instance of this Directory Type
27057 uint16_t dir_ordinal;
27058 /* The Directory Entry Extension flags. */
27060 /* This value indicates the search option using dir_ordinal. */
27061 uint8_t opt_ordinal;
27062 /* This value indicates the search option using dir_ordinal. */
27063 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
27064 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
27065 /* Equal to specified ordinal value. */
27066 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
27067 /* Greater than or equal to specified ordinal value */
27068 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
27069 /* Greater than specified ordinal value */
27070 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
27071 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_LAST \
27072 HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT
27073 uint8_t unused_0[3];
27074 } __attribute__((packed));
27076 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */
27077 struct hwrm_nvm_find_dir_entry_output {
27078 /* The specific error status for the command. */
27079 uint16_t error_code;
27080 /* The HWRM command request type. */
27082 /* The sequence ID from the original command. */
27084 /* The length of the response data in number of bytes. */
27086 /* Allocated NVRAM for this directory entry, in bytes. */
27087 uint32_t dir_item_length;
27088 /* Size of the stored data for this directory entry, in bytes. */
27089 uint32_t dir_data_length;
27091 * Firmware version.
27092 * Only valid if the directory entry is for embedded firmware stored in APE_BIN Format.
27095 /* Directory ordinal. */
27096 uint16_t dir_ordinal;
27097 /* Directory Entry Index */
27099 uint8_t unused_0[7];
27101 * This field is used in Output records to indicate that the output
27102 * is completely written to RAM. This field should be read as '1'
27103 * to indicate that the output has been completely written.
27104 * When writing a command completion or response to an internal processor,
27105 * the order of writes has to be such that this field is written last.
27108 } __attribute__((packed));
27110 /****************************
27111 * hwrm_nvm_erase_dir_entry *
27112 ****************************/
27115 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */
27116 struct hwrm_nvm_erase_dir_entry_input {
27117 /* The HWRM command request type. */
27120 * The completion ring to send the completion event on. This should
27121 * be the NQ ID returned from the `nq_alloc` HWRM command.
27123 uint16_t cmpl_ring;
27125 * The sequence ID is used by the driver for tracking multiple
27126 * commands. This ID is treated as opaque data by the firmware and
27127 * the value is returned in the `hwrm_resp_hdr` upon completion.
27131 * The target ID of the command:
27132 * * 0x0-0xFFF8 - The function ID
27133 * * 0xFFF8-0xFFFE - Reserved for internal processors
27136 uint16_t target_id;
27138 * A physical address pointer pointing to a host buffer that the
27139 * command's response data will be written. This can be either a host
27140 * physical address (HPA) or a guest physical address (GPA) and must
27141 * point to a physically contiguous block of memory.
27143 uint64_t resp_addr;
27144 /* Directory Entry Index */
27146 uint8_t unused_0[6];
27147 } __attribute__((packed));
27149 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */
27150 struct hwrm_nvm_erase_dir_entry_output {
27151 /* The specific error status for the command. */
27152 uint16_t error_code;
27153 /* The HWRM command request type. */
27155 /* The sequence ID from the original command. */
27157 /* The length of the response data in number of bytes. */
27159 uint8_t unused_0[7];
27161 * This field is used in Output records to indicate that the output
27162 * is completely written to RAM. This field should be read as '1'
27163 * to indicate that the output has been completely written.
27164 * When writing a command completion or response to an internal processor,
27165 * the order of writes has to be such that this field is written last.
27168 } __attribute__((packed));
27170 /*************************
27171 * hwrm_nvm_get_dev_info *
27172 *************************/
27175 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */
27176 struct hwrm_nvm_get_dev_info_input {
27177 /* The HWRM command request type. */
27180 * The completion ring to send the completion event on. This should
27181 * be the NQ ID returned from the `nq_alloc` HWRM command.
27183 uint16_t cmpl_ring;
27185 * The sequence ID is used by the driver for tracking multiple
27186 * commands. This ID is treated as opaque data by the firmware and
27187 * the value is returned in the `hwrm_resp_hdr` upon completion.
27191 * The target ID of the command:
27192 * * 0x0-0xFFF8 - The function ID
27193 * * 0xFFF8-0xFFFE - Reserved for internal processors
27196 uint16_t target_id;
27198 * A physical address pointer pointing to a host buffer that the
27199 * command's response data will be written. This can be either a host
27200 * physical address (HPA) or a guest physical address (GPA) and must
27201 * point to a physically contiguous block of memory.
27203 uint64_t resp_addr;
27204 } __attribute__((packed));
27206 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */
27207 struct hwrm_nvm_get_dev_info_output {
27208 /* The specific error status for the command. */
27209 uint16_t error_code;
27210 /* The HWRM command request type. */
27212 /* The sequence ID from the original command. */
27214 /* The length of the response data in number of bytes. */
27216 /* Manufacturer ID. */
27217 uint16_t manufacturer_id;
27219 uint16_t device_id;
27220 /* Sector size of the NVRAM device. */
27221 uint32_t sector_size;
27222 /* Total size, in bytes of the NVRAM device. */
27223 uint32_t nvram_size;
27224 uint32_t reserved_size;
27225 /* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
27226 uint32_t available_size;
27227 uint8_t unused_0[3];
27229 * This field is used in Output records to indicate that the output
27230 * is completely written to RAM. This field should be read as '1'
27231 * to indicate that the output has been completely written.
27232 * When writing a command completion or response to an internal processor,
27233 * the order of writes has to be such that this field is written last.
27236 } __attribute__((packed));
27238 /**************************
27239 * hwrm_nvm_mod_dir_entry *
27240 **************************/
27243 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */
27244 struct hwrm_nvm_mod_dir_entry_input {
27245 /* The HWRM command request type. */
27248 * The completion ring to send the completion event on. This should
27249 * be the NQ ID returned from the `nq_alloc` HWRM command.
27251 uint16_t cmpl_ring;
27253 * The sequence ID is used by the driver for tracking multiple
27254 * commands. This ID is treated as opaque data by the firmware and
27255 * the value is returned in the `hwrm_resp_hdr` upon completion.
27259 * The target ID of the command:
27260 * * 0x0-0xFFF8 - The function ID
27261 * * 0xFFF8-0xFFFE - Reserved for internal processors
27264 uint16_t target_id;
27266 * A physical address pointer pointing to a host buffer that the
27267 * command's response data will be written. This can be either a host
27268 * physical address (HPA) or a guest physical address (GPA) and must
27269 * point to a physically contiguous block of memory.
27271 uint64_t resp_addr;
27274 * This bit must be '1' for the checksum field to be
27277 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
27278 /* Directory Entry Index */
27281 * Directory ordinal.
27282 * The (0-based) instance of this Directory Type.
27284 uint16_t dir_ordinal;
27285 /* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */
27287 /* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */
27290 * If valid, then this field updates the checksum
27291 * value of the content in the directory entry.
27294 } __attribute__((packed));
27296 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */
27297 struct hwrm_nvm_mod_dir_entry_output {
27298 /* The specific error status for the command. */
27299 uint16_t error_code;
27300 /* The HWRM command request type. */
27302 /* The sequence ID from the original command. */
27304 /* The length of the response data in number of bytes. */
27306 uint8_t unused_0[7];
27308 * This field is used in Output records to indicate that the output
27309 * is completely written to RAM. This field should be read as '1'
27310 * to indicate that the output has been completely written.
27311 * When writing a command completion or response to an internal processor,
27312 * the order of writes has to be such that this field is written last.
27315 } __attribute__((packed));
27317 /**************************
27318 * hwrm_nvm_verify_update *
27319 **************************/
27322 /* hwrm_nvm_verify_update_input (size:192b/24B) */
27323 struct hwrm_nvm_verify_update_input {
27324 /* The HWRM command request type. */
27327 * The completion ring to send the completion event on. This should
27328 * be the NQ ID returned from the `nq_alloc` HWRM command.
27330 uint16_t cmpl_ring;
27332 * The sequence ID is used by the driver for tracking multiple
27333 * commands. This ID is treated as opaque data by the firmware and
27334 * the value is returned in the `hwrm_resp_hdr` upon completion.
27338 * The target ID of the command:
27339 * * 0x0-0xFFF8 - The function ID
27340 * * 0xFFF8-0xFFFE - Reserved for internal processors
27343 uint16_t target_id;
27345 * A physical address pointer pointing to a host buffer that the
27346 * command's response data will be written. This can be either a host
27347 * physical address (HPA) or a guest physical address (GPA) and must
27348 * point to a physically contiguous block of memory.
27350 uint64_t resp_addr;
27351 /* Directory Entry Type, to be verified. */
27354 * Directory ordinal.
27355 * The instance of the Directory Type to be verified.
27357 uint16_t dir_ordinal;
27359 * The Directory Entry Extension flags.
27360 * The "UPDATE" extension flag must be set in this value.
27361 * A corresponding directory entry with the same type and ordinal values but *without*
27362 * the "UPDATE" extension flag must also exist. The other flags of the extension must
27363 * be identical between the active and update entries.
27366 uint8_t unused_0[2];
27367 } __attribute__((packed));
27369 /* hwrm_nvm_verify_update_output (size:128b/16B) */
27370 struct hwrm_nvm_verify_update_output {
27371 /* The specific error status for the command. */
27372 uint16_t error_code;
27373 /* The HWRM command request type. */
27375 /* The sequence ID from the original command. */
27377 /* The length of the response data in number of bytes. */
27379 uint8_t unused_0[7];
27381 * This field is used in Output records to indicate that the output
27382 * is completely written to RAM. This field should be read as '1'
27383 * to indicate that the output has been completely written.
27384 * When writing a command completion or response to an internal processor,
27385 * the order of writes has to be such that this field is written last.
27388 } __attribute__((packed));
27390 /***************************
27391 * hwrm_nvm_install_update *
27392 ***************************/
27395 /* hwrm_nvm_install_update_input (size:192b/24B) */
27396 struct hwrm_nvm_install_update_input {
27397 /* The HWRM command request type. */
27400 * The completion ring to send the completion event on. This should
27401 * be the NQ ID returned from the `nq_alloc` HWRM command.
27403 uint16_t cmpl_ring;
27405 * The sequence ID is used by the driver for tracking multiple
27406 * commands. This ID is treated as opaque data by the firmware and
27407 * the value is returned in the `hwrm_resp_hdr` upon completion.
27411 * The target ID of the command:
27412 * * 0x0-0xFFF8 - The function ID
27413 * * 0xFFF8-0xFFFE - Reserved for internal processors
27416 uint16_t target_id;
27418 * A physical address pointer pointing to a host buffer that the
27419 * command's response data will be written. This can be either a host
27420 * physical address (HPA) or a guest physical address (GPA) and must
27421 * point to a physically contiguous block of memory.
27423 uint64_t resp_addr;
27425 * Installation type. If the value 3 through 0xffff is used,
27426 * only packaged items with that type value will be installed and
27427 * conditional installation directives for those packaged items
27428 * will be over-ridden (i.e. 'create' or 'replace' will be treated
27431 uint32_t install_type;
27433 * Perform a normal package installation. Conditional installation
27434 * directives (e.g. 'create' and 'replace') of packaged items
27435 * will be followed.
27437 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
27439 * Install all packaged items regardless of installation directive
27440 * (i.e. treat all packaged items as though they have an installation
27441 * directive of 'install').
27443 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL \
27444 UINT32_C(0xffffffff)
27445 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_LAST \
27446 HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL
27448 /* If set to 1, then securely erase all unused locations in persistent storage. */
27449 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \
27452 * If set to 1, then unspecifed images, images not in the package file, will be safely deleted.
27453 * When combined with erase_unused_space then unspecified images will be securely erased.
27455 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \
27458 * If set to 1, FW will defragment the NVM if defragmentation is required for the update.
27459 * Allow additional time for this command to complete if this bit is set to 1.
27461 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \
27463 uint8_t unused_0[2];
27464 } __attribute__((packed));
27466 /* hwrm_nvm_install_update_output (size:192b/24B) */
27467 struct hwrm_nvm_install_update_output {
27468 /* The specific error status for the command. */
27469 uint16_t error_code;
27470 /* The HWRM command request type. */
27472 /* The sequence ID from the original command. */
27474 /* The length of the response data in number of bytes. */
27477 * Bit-mask of successfully installed items.
27478 * Bit-0 corresponding to the first packaged item, Bit-1 for the second item, etc.
27479 * A value of 0 indicates that no items were successfully installed.
27481 uint64_t installed_items;
27482 /* result is 8 b */
27484 /* There was no problem with the package installation. */
27485 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
27486 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_LAST \
27487 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS
27488 /* problem_item is 8 b */
27489 uint8_t problem_item;
27490 /* There was no problem with any packaged items. */
27491 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE \
27493 /* There was a problem with the NVM package itself. */
27494 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE \
27496 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_LAST \
27497 HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE
27498 /* reset_required is 8 b */
27499 uint8_t reset_required;
27501 * No reset is required for installed/updated firmware or
27502 * microcode to take effect.
27504 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE \
27507 * A PCIe reset (e.g. system reboot) is
27508 * required for newly installed/updated firmware or
27509 * microcode to take effect.
27511 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI \
27514 * A controller power reset (e.g. system power-cycle) is
27515 * required for newly installed/updated firmware or
27516 * microcode to take effect. Some newly installed/updated
27517 * firmware or microcode may still take effect upon the
27520 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER \
27522 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_LAST \
27523 HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER
27524 uint8_t unused_0[4];
27526 * This field is used in Output records to indicate that the output
27527 * is completely written to RAM. This field should be read as '1'
27528 * to indicate that the output has been completely written.
27529 * When writing a command completion or response to an internal processor,
27530 * the order of writes has to be such that this field is written last.
27533 } __attribute__((packed));
27535 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */
27536 struct hwrm_nvm_install_update_cmd_err {
27538 * command specific error codes that goes to
27539 * the cmd_err field in Common HWRM Error Response.
27542 /* Unknown error */
27543 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27544 /* Unable to complete operation due to fragmentation */
27545 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
27546 /* nvm is completely full. */
27547 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
27548 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \
27549 HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE
27550 uint8_t unused_0[7];
27551 } __attribute__((packed));
27553 /******************
27555 ******************/
27558 /* hwrm_nvm_flush_input (size:128b/16B) */
27559 struct hwrm_nvm_flush_input {
27560 /* The HWRM command request type. */
27563 * The completion ring to send the completion event on. This should
27564 * be the NQ ID returned from the `nq_alloc` HWRM command.
27566 uint16_t cmpl_ring;
27568 * The sequence ID is used by the driver for tracking multiple
27569 * commands. This ID is treated as opaque data by the firmware and
27570 * the value is returned in the `hwrm_resp_hdr` upon completion.
27574 * The target ID of the command:
27575 * * 0x0-0xFFF8 - The function ID
27576 * * 0xFFF8-0xFFFE - Reserved for internal processors
27579 uint16_t target_id;
27581 * A physical address pointer pointing to a host buffer that the
27582 * command's response data will be written. This can be either a host
27583 * physical address (HPA) or a guest physical address (GPA) and must
27584 * point to a physically contiguous block of memory.
27586 uint64_t resp_addr;
27587 } __attribute__((packed));
27589 /* hwrm_nvm_flush_output (size:128b/16B) */
27590 struct hwrm_nvm_flush_output {
27591 /* The specific error status for the command. */
27592 uint16_t error_code;
27593 /* The HWRM command request type. */
27595 /* The sequence ID from the original command. */
27597 /* The length of the response data in number of bytes. */
27599 uint8_t unused_0[7];
27601 * This field is used in Output records to indicate that the output
27602 * is completely written to RAM. This field should be read as '1'
27603 * to indicate that the output has been completely written.
27604 * When writing a command completion or response to an internal processor,
27605 * the order of writes has to be such that this field is written last.
27608 } __attribute__((packed));
27610 /* hwrm_nvm_flush_cmd_err (size:64b/8B) */
27611 struct hwrm_nvm_flush_cmd_err {
27613 * command specific error codes that goes to
27614 * the cmd_err field in Common HWRM Error Response.
27617 /* Unknown error */
27618 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27619 /* flush could not be performed */
27620 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
27621 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_LAST \
27622 HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL
27623 uint8_t unused_0[7];
27624 } __attribute__((packed));
27626 /*************************
27627 * hwrm_nvm_get_variable *
27628 *************************/
27631 /* hwrm_nvm_get_variable_input (size:320b/40B) */
27632 struct hwrm_nvm_get_variable_input {
27633 /* The HWRM command request type. */
27636 * The completion ring to send the completion event on. This should
27637 * be the NQ ID returned from the `nq_alloc` HWRM command.
27639 uint16_t cmpl_ring;
27641 * The sequence ID is used by the driver for tracking multiple
27642 * commands. This ID is treated as opaque data by the firmware and
27643 * the value is returned in the `hwrm_resp_hdr` upon completion.
27647 * The target ID of the command:
27648 * * 0x0-0xFFF8 - The function ID
27649 * * 0xFFF8-0xFFFE - Reserved for internal processors
27652 uint16_t target_id;
27654 * A physical address pointer pointing to a host buffer that the
27655 * command's response data will be written. This can be either a host
27656 * physical address (HPA) or a guest physical address (GPA) and must
27657 * point to a physically contiguous block of memory.
27659 uint64_t resp_addr;
27661 * This is the host address where
27662 * nvm variable will be stored
27664 uint64_t dest_data_addr;
27665 /* size of data in bits */
27667 /* nvm cfg option number */
27668 uint16_t option_num;
27670 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27672 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
27674 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_LAST \
27675 HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
27677 * Number of dimensions for this nvm configuration variable.
27678 * This value indicates how many of the indexN values to use.
27679 * A value of 0 means that none of the indexN values are valid.
27680 * A value of 1 requires at index0 is valued, a value of 2
27681 * requires that index0 and index1 are valid, and so forth
27683 uint16_t dimensions;
27684 /* index for the 1st dimensions */
27686 /* index for the 2nd dimensions */
27688 /* index for the 3rd dimensions */
27690 /* index for the 4th dimensions */
27694 * When this bit is set to 1, the factory default value will be returned,
27695 * 0 returns the operational value.
27697 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT \
27700 } __attribute__((packed));
27702 /* hwrm_nvm_get_variable_output (size:128b/16B) */
27703 struct hwrm_nvm_get_variable_output {
27704 /* The specific error status for the command. */
27705 uint16_t error_code;
27706 /* The HWRM command request type. */
27708 /* The sequence ID from the original command. */
27710 /* The length of the response data in number of bytes. */
27712 /* size of data of the actual variable retrieved in bits */
27715 * option_num is the option number for the data retrieved. It is possible in the
27716 * future that the option number returned would be different than requested. This
27717 * condition could occur if an option is deprecated and a new option id is defined
27718 * with similar characteristics, but has a slightly different definition. This
27719 * also makes it convenient for the caller to identify the variable result with
27720 * the option id from the response.
27722 uint16_t option_num;
27724 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27726 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF \
27728 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_LAST \
27729 HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF
27730 uint8_t unused_0[3];
27732 * This field is used in Output records to indicate that the output
27733 * is completely written to RAM. This field should be read as '1'
27734 * to indicate that the output has been completely written.
27735 * When writing a command completion or response to an internal processor,
27736 * the order of writes has to be such that this field is written last.
27739 } __attribute__((packed));
27741 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */
27742 struct hwrm_nvm_get_variable_cmd_err {
27744 * command specific error codes that goes to
27745 * the cmd_err field in Common HWRM Error Response.
27748 /* Unknown error */
27749 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27750 /* variable does not exist */
27751 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27752 /* configuration is corrupted and the variable cannot be saved */
27753 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27754 /* length specified is too small */
27755 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
27756 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LAST \
27757 HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT
27758 uint8_t unused_0[7];
27759 } __attribute__((packed));
27761 /*************************
27762 * hwrm_nvm_set_variable *
27763 *************************/
27766 /* hwrm_nvm_set_variable_input (size:320b/40B) */
27767 struct hwrm_nvm_set_variable_input {
27768 /* The HWRM command request type. */
27771 * The completion ring to send the completion event on. This should
27772 * be the NQ ID returned from the `nq_alloc` HWRM command.
27774 uint16_t cmpl_ring;
27776 * The sequence ID is used by the driver for tracking multiple
27777 * commands. This ID is treated as opaque data by the firmware and
27778 * the value is returned in the `hwrm_resp_hdr` upon completion.
27782 * The target ID of the command:
27783 * * 0x0-0xFFF8 - The function ID
27784 * * 0xFFF8-0xFFFE - Reserved for internal processors
27787 uint16_t target_id;
27789 * A physical address pointer pointing to a host buffer that the
27790 * command's response data will be written. This can be either a host
27791 * physical address (HPA) or a guest physical address (GPA) and must
27792 * point to a physically contiguous block of memory.
27794 uint64_t resp_addr;
27796 * This is the host address where
27797 * nvm variable will be copied from
27799 uint64_t src_data_addr;
27800 /* size of data in bits */
27802 /* nvm cfg option number */
27803 uint16_t option_num;
27805 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
27807 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF \
27809 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_LAST \
27810 HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF
27812 * Number of dimensions for this nvm configuration variable.
27813 * This value indicates how many of the indexN values to use.
27814 * A value of 0 means that none of the indexN values are valid.
27815 * A value of 1 requires at index0 is valued, a value of 2
27816 * requires that index0 and index1 are valid, and so forth
27818 uint16_t dimensions;
27819 /* index for the 1st dimensions */
27821 /* index for the 2nd dimensions */
27823 /* index for the 3rd dimensions */
27825 /* index for the 4th dimensions */
27828 /* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */
27829 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \
27831 /* encryption method */
27832 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK \
27834 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
27835 /* No encryption. */
27836 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE \
27837 (UINT32_C(0x0) << 1)
27838 /* one-way encryption. */
27839 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 \
27840 (UINT32_C(0x1) << 1)
27841 /* symmetric AES256 encryption. */
27842 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 \
27843 (UINT32_C(0x2) << 1)
27844 /* SHA1 digest appended to plaintext contents, for authentication */
27845 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH \
27846 (UINT32_C(0x3) << 1)
27847 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST \
27848 HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH
27850 } __attribute__((packed));
27852 /* hwrm_nvm_set_variable_output (size:128b/16B) */
27853 struct hwrm_nvm_set_variable_output {
27854 /* The specific error status for the command. */
27855 uint16_t error_code;
27856 /* The HWRM command request type. */
27858 /* The sequence ID from the original command. */
27860 /* The length of the response data in number of bytes. */
27862 uint8_t unused_0[7];
27864 * This field is used in Output records to indicate that the output
27865 * is completely written to RAM. This field should be read as '1'
27866 * to indicate that the output has been completely written.
27867 * When writing a command completion or response to an internal processor,
27868 * the order of writes has to be such that this field is written last.
27871 } __attribute__((packed));
27873 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */
27874 struct hwrm_nvm_set_variable_cmd_err {
27876 * command specific error codes that goes to
27877 * the cmd_err field in Common HWRM Error Response.
27880 /* Unknown error */
27881 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27882 /* variable does not exist */
27883 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
27884 /* configuration is corrupted and the variable cannot be saved */
27885 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
27886 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_LAST \
27887 HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR
27888 uint8_t unused_0[7];
27889 } __attribute__((packed));
27891 /****************************
27892 * hwrm_nvm_validate_option *
27893 ****************************/
27896 /* hwrm_nvm_validate_option_input (size:320b/40B) */
27897 struct hwrm_nvm_validate_option_input {
27898 /* The HWRM command request type. */
27901 * The completion ring to send the completion event on. This should
27902 * be the NQ ID returned from the `nq_alloc` HWRM command.
27904 uint16_t cmpl_ring;
27906 * The sequence ID is used by the driver for tracking multiple
27907 * commands. This ID is treated as opaque data by the firmware and
27908 * the value is returned in the `hwrm_resp_hdr` upon completion.
27912 * The target ID of the command:
27913 * * 0x0-0xFFF8 - The function ID
27914 * * 0xFFF8-0xFFFE - Reserved for internal processors
27917 uint16_t target_id;
27919 * A physical address pointer pointing to a host buffer that the
27920 * command's response data will be written. This can be either a host
27921 * physical address (HPA) or a guest physical address (GPA) and must
27922 * point to a physically contiguous block of memory.
27924 uint64_t resp_addr;
27926 * This is the host address where
27927 * nvm variable will be copied from
27929 uint64_t src_data_addr;
27930 /* size of data in bits */
27932 /* nvm cfg option number */
27933 uint16_t option_num;
27935 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 \
27938 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF \
27940 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_LAST \
27941 HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF
27943 * Number of dimensions for this nvm configuration variable.
27944 * This value indicates how many of the indexN values to use.
27945 * A value of 0 means that none of the indexN values are valid.
27946 * A value of 1 requires at index0 is valued, a value of 2
27947 * requires that index0 and index1 are valid, and so forth
27949 uint16_t dimensions;
27950 /* index for the 1st dimensions */
27952 /* index for the 2nd dimensions */
27954 /* index for the 3rd dimensions */
27956 /* index for the 4th dimensions */
27958 uint8_t unused_0[2];
27959 } __attribute__((packed));
27961 /* hwrm_nvm_validate_option_output (size:128b/16B) */
27962 struct hwrm_nvm_validate_option_output {
27963 /* The specific error status for the command. */
27964 uint16_t error_code;
27965 /* The HWRM command request type. */
27967 /* The sequence ID from the original command. */
27969 /* The length of the response data in number of bytes. */
27972 /* indicates that the value provided for the option is not matching with the saved data. */
27973 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
27974 /* indicates that the value provided for the option is matching the saved data. */
27975 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
27976 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_LAST \
27977 HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH
27978 uint8_t unused_0[6];
27980 * This field is used in Output records to indicate that the output
27981 * is completely written to RAM. This field should be read as '1'
27982 * to indicate that the output has been completely written.
27983 * When writing a command completion or response to an internal processor,
27984 * the order of writes has to be such that this field is written last.
27987 } __attribute__((packed));
27989 /* hwrm_nvm_validate_option_cmd_err (size:64b/8B) */
27990 struct hwrm_nvm_validate_option_cmd_err {
27992 * command specific error codes that goes to
27993 * the cmd_err field in Common HWRM Error Response.
27996 /* Unknown error */
27997 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
27998 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_LAST \
27999 HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN
28000 uint8_t unused_0[7];
28001 } __attribute__((packed));
28003 /*****************************
28004 * hwrm_nvm_factory_defaults *
28005 *****************************/
28008 /* hwrm_nvm_factory_defaults_input (size:192b/24B) */
28009 struct hwrm_nvm_factory_defaults_input {
28010 /* The HWRM command request type. */
28013 * The completion ring to send the completion event on. This should
28014 * be the NQ ID returned from the `nq_alloc` HWRM command.
28016 uint16_t cmpl_ring;
28018 * The sequence ID is used by the driver for tracking multiple
28019 * commands. This ID is treated as opaque data by the firmware and
28020 * the value is returned in the `hwrm_resp_hdr` upon completion.
28024 * The target ID of the command:
28025 * * 0x0-0xFFF8 - The function ID
28026 * * 0xFFF8-0xFFFE - Reserved for internal processors
28029 uint16_t target_id;
28031 * A physical address pointer pointing to a host buffer that the
28032 * command's response data will be written. This can be either a host
28033 * physical address (HPA) or a guest physical address (GPA) and must
28034 * point to a physically contiguous block of memory.
28036 uint64_t resp_addr;
28039 /* If set to 1, it will trigger restoration of factory default settings */
28040 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
28041 /* If set to 1, it will trigger creation of factory default settings */
28042 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
28043 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \
28044 HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE
28045 uint8_t unused_0[7];
28046 } __attribute__((packed));
28048 /* hwrm_nvm_factory_defaults_output (size:128b/16B) */
28049 struct hwrm_nvm_factory_defaults_output {
28050 /* The specific error status for the command. */
28051 uint16_t error_code;
28052 /* The HWRM command request type. */
28054 /* The sequence ID from the original command. */
28056 /* The length of the response data in number of bytes. */
28059 /* factory defaults created successfully. */
28060 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \
28062 /* factory defaults restored successfully. */
28063 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \
28065 /* factory defaults already created. */
28066 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \
28068 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \
28069 HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY
28070 uint8_t unused_0[6];
28072 * This field is used in Output records to indicate that the output
28073 * is completely written to RAM. This field should be read as '1'
28074 * to indicate that the output has been completely written.
28075 * When writing a command completion or response to an internal processor,
28076 * the order of writes has to be such that this field is written last.
28079 } __attribute__((packed));
28081 /* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */
28082 struct hwrm_nvm_factory_defaults_cmd_err {
28084 * command specific error codes that goes to
28085 * the cmd_err field in Common HWRM Error Response.
28088 /* Unknown error */
28089 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \
28091 /* valid configuration not present to create defaults */
28092 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \
28094 /* No saved configuration present to restore, restore failed */
28095 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \
28097 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \
28098 HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG
28099 uint8_t unused_0[7];
28100 } __attribute__((packed));
28102 #endif /* _HSI_STRUCT_DEF_DPDK_H_ */