1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2021 Broadcom
6 #include <rte_common.h>
8 #include "cfa_resource_types.h"
10 #include "tf_identifier.h"
14 #include "tf_if_tbl.h"
16 #include "tf_msg_common.h"
18 #define TF_DEV_P4_PARIF_MAX 16
19 #define TF_DEV_P4_PF_MASK 0xfUL
21 const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
22 [CFA_RESOURCE_TYPE_P4_MCG] = "mc_group",
23 [CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ",
24 [CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16",
25 [CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64",
26 [CFA_RESOURCE_TYPE_P4_SP_MAC] = "sp_mac ",
27 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4",
28 [CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6",
29 [CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ",
30 [CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port",
31 [CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4",
32 [CFA_RESOURCE_TYPE_P4_METER] = "meter ",
33 [CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ",
34 [CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act",
35 [CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act",
36 [CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act",
37 [CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act",
38 [CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act",
39 [CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act",
40 [CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act",
41 [CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act",
42 [CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act",
43 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi",
44 [CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo",
45 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
46 [CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo",
47 [CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func",
48 [CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam",
49 [CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ",
50 [CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec ",
51 [CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ",
52 [CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ",
53 [CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof",
54 [CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror ",
55 [CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ",
56 [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
60 * Device specific function that retrieves the MAX number of HCAPI
61 * types the device supports.
64 * Pointer to TF handle
67 * Pointer to the MAX number of CFA resource types supported
70 * - (0) if successful.
71 * - (-EINVAL) on failure.
74 tf_dev_p4_get_max_types(struct tf *tfp,
77 if (max_types == NULL || tfp == NULL)
80 *max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
85 * Device specific function that retrieves a human readable
86 * string to identify a CFA resource type.
89 * Pointer to TF handle
92 * HCAPI CFA resource id
98 * - (0) if successful.
99 * - (-EINVAL) on failure.
102 tf_dev_p4_get_resource_str(struct tf *tfp __rte_unused,
103 uint16_t resource_id,
104 const char **resource_str)
106 if (resource_str == NULL)
109 if (resource_id > CFA_RESOURCE_TYPE_P4_LAST)
112 *resource_str = tf_resource_str_p4[resource_id];
118 * Device specific function that retrieves the WC TCAM slices the
122 * Pointer to TF handle
125 * Pointer to the WC TCAM slice size
127 * [out] num_slices_per_row
128 * Pointer to the WC TCAM row slice configuration
131 * - (0) if successful.
132 * - (-EINVAL) on failure.
135 tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
136 enum tf_tcam_tbl_type type,
138 uint16_t *num_slices_per_row)
140 #define CFA_P4_WC_TCAM_SLICES_PER_ROW 2
141 #define CFA_P4_WC_TCAM_SLICE_SIZE 12
143 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
144 *num_slices_per_row = CFA_P4_WC_TCAM_SLICES_PER_ROW;
145 if (key_sz > *num_slices_per_row * CFA_P4_WC_TCAM_SLICE_SIZE)
147 } else { /* for other type of tcam */
148 *num_slices_per_row = 1;
155 tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
156 uint16_t parif_bitmask,
160 uint16_t sz_in_bytes)
162 uint32_t parif_pf[2] = { 0 };
163 uint32_t parif_pf_mask[2] = { 0 };
167 if (sz_in_bytes != sizeof(uint64_t))
170 for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
171 if (parif_bitmask & (1UL << parif)) {
174 parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
175 parif_pf[0] |= pf << shift;
177 shift = 4 * (parif - 8);
178 parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
179 parif_pf[1] |= pf << shift;
183 tfp_memcpy(data, parif_pf, sz_in_bytes);
184 tfp_memcpy(mask, parif_pf_mask, sz_in_bytes);
189 static int tf_dev_p4_get_mailbox(void)
194 static int tf_dev_p4_word_align(uint16_t size)
196 return ((((size) + 31) >> 5) * 4);
200 * Truflow P4 device specific functions
202 const struct tf_dev_ops tf_dev_ops_p4_init = {
203 .tf_dev_get_max_types = tf_dev_p4_get_max_types,
204 .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
205 .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
206 .tf_dev_alloc_ident = NULL,
207 .tf_dev_free_ident = NULL,
208 .tf_dev_search_ident = NULL,
209 .tf_dev_get_ident_resc_info = NULL,
210 .tf_dev_get_tbl_info = NULL,
211 .tf_dev_alloc_ext_tbl = NULL,
212 .tf_dev_alloc_tbl = NULL,
213 .tf_dev_free_ext_tbl = NULL,
214 .tf_dev_free_tbl = NULL,
215 .tf_dev_alloc_search_tbl = NULL,
216 .tf_dev_set_tbl = NULL,
217 .tf_dev_set_ext_tbl = NULL,
218 .tf_dev_get_tbl = NULL,
219 .tf_dev_get_bulk_tbl = NULL,
220 .tf_dev_get_tbl_resc_info = NULL,
221 .tf_dev_alloc_tcam = NULL,
222 .tf_dev_free_tcam = NULL,
223 .tf_dev_alloc_search_tcam = NULL,
224 .tf_dev_set_tcam = NULL,
225 .tf_dev_get_tcam = NULL,
226 .tf_dev_get_tcam_resc_info = NULL,
227 .tf_dev_insert_int_em_entry = NULL,
228 .tf_dev_delete_int_em_entry = NULL,
229 .tf_dev_insert_ext_em_entry = NULL,
230 .tf_dev_delete_ext_em_entry = NULL,
231 .tf_dev_get_em_resc_info = NULL,
232 .tf_dev_alloc_tbl_scope = NULL,
233 .tf_dev_map_tbl_scope = NULL,
234 .tf_dev_map_parif = NULL,
235 .tf_dev_free_tbl_scope = NULL,
236 .tf_dev_set_if_tbl = NULL,
237 .tf_dev_get_if_tbl = NULL,
238 .tf_dev_set_global_cfg = NULL,
239 .tf_dev_get_global_cfg = NULL,
240 .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
241 .tf_dev_word_align = NULL,
245 * Truflow P4 device specific functions
247 const struct tf_dev_ops tf_dev_ops_p4 = {
248 .tf_dev_get_max_types = tf_dev_p4_get_max_types,
249 .tf_dev_get_resource_str = tf_dev_p4_get_resource_str,
250 .tf_dev_get_tcam_slice_info = tf_dev_p4_get_tcam_slice_info,
251 .tf_dev_alloc_ident = tf_ident_alloc,
252 .tf_dev_free_ident = tf_ident_free,
253 .tf_dev_search_ident = tf_ident_search,
254 .tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
255 .tf_dev_get_tbl_info = NULL,
256 .tf_dev_alloc_tbl = tf_tbl_alloc,
257 .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
258 .tf_dev_free_tbl = tf_tbl_free,
259 .tf_dev_free_ext_tbl = tf_tbl_ext_free,
260 .tf_dev_alloc_search_tbl = tf_tbl_alloc_search,
261 .tf_dev_set_tbl = tf_tbl_set,
262 .tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
263 .tf_dev_get_tbl = tf_tbl_get,
264 .tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
265 .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
266 .tf_dev_alloc_tcam = tf_tcam_alloc,
267 .tf_dev_free_tcam = tf_tcam_free,
268 .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
269 .tf_dev_set_tcam = tf_tcam_set,
270 .tf_dev_get_tcam = NULL,
271 .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
272 .tf_dev_insert_int_em_entry = tf_em_insert_int_entry,
273 .tf_dev_delete_int_em_entry = tf_em_delete_int_entry,
274 .tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry,
275 .tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry,
276 .tf_dev_get_em_resc_info = tf_em_get_resc_info,
277 .tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc,
278 .tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope,
279 .tf_dev_map_parif = tf_dev_p4_map_parif,
280 .tf_dev_free_tbl_scope = tf_em_ext_common_free,
281 .tf_dev_set_if_tbl = tf_if_tbl_set,
282 .tf_dev_get_if_tbl = tf_if_tbl_get,
283 .tf_dev_set_global_cfg = tf_global_cfg_set,
284 .tf_dev_get_global_cfg = tf_global_cfg_get,
285 .tf_dev_get_mailbox = tf_dev_p4_get_mailbox,
286 .tf_dev_word_align = tf_dev_p4_word_align,
287 .tf_dev_cfa_key_hash = hcapi_cfa_p4_key_hash