1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2021 Broadcom
6 #ifndef _TF_DEVICE_P4_H_
7 #define _TF_DEVICE_P4_H_
9 #include "cfa_resource_types.h"
12 #include "tf_if_tbl.h"
13 #include "tf_global_cfg.h"
15 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
16 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH },
17 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW },
18 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC },
19 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },
20 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },
21 /* CFA_RESOURCE_TYPE_P4_L2_FUNC */
22 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
25 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
26 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH },
27 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW },
28 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM },
29 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM },
30 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM },
31 /* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */
32 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
33 /* CFA_RESOURCE_TYPE_P4_VEB_TCAM */
34 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
37 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
38 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION },
39 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG },
40 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B },
41 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B },
42 /* CFA_RESOURCE_TYPE_P4_ENCAP_32B */
43 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
44 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B },
45 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC },
46 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 },
47 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 },
48 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B },
49 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },
50 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },
51 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 },
52 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF },
53 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER },
54 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR },
55 /* CFA_RESOURCE_TYPE_P4_UPAR */
56 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
57 /* CFA_RESOURCE_TYPE_P4_EPOC */
58 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
59 /* CFA_RESOURCE_TYPE_P4_METADATA */
60 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
61 /* CFA_RESOURCE_TYPE_P4_CT_STATE */
62 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
63 /* CFA_RESOURCE_TYPE_P4_RANGE_PROF */
64 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
65 /* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */
66 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
67 /* CFA_RESOURCE_TYPE_P4_LAG */
68 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
69 /* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */
70 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
71 /* CFA_RESOURCE_TYPE_P4_EM_FBK */
72 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
73 /* CFA_RESOURCE_TYPE_P4_WC_FKB */
74 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
75 /* CFA_RESOURCE_TYPE_P4_EXT */
76 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
79 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
80 /* CFA_RESOURCE_TYPE_P4_EM_REC */
81 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
82 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
85 struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {
86 /* CFA_RESOURCE_TYPE_P4_EM_REC */
87 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
88 { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
91 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
92 { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
93 /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
94 { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
97 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
98 { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
99 { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
100 { TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
101 { TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
102 { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
103 { TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
106 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
107 { TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
108 { TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
110 #endif /* _TF_DEVICE_P4_H_ */