drivers/net/bnxt/tf_core/tf_device_p4.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P4_H_
   7 #define _TF_DEVICE_P4_H_
   8
   9 #include <cfa_resource_types.h>
  10
  11 #include "tf_core.h"
  12 #include "tf_rm_new.h"
  13
  14 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
  15         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP },
  16         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_FUNC },
  17         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },
  18         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },
  19         /* CFA_RESOURCE_TYPE_P4_L2_FUNC */
  20         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
  21 };
  22
  23 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
  24         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM },
  25         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_PROF_TCAM },
  26         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_WC_TCAM },
  27         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_TCAM },
  28         /* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */
  29         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  30         /* CFA_RESOURCE_TYPE_P4_VEB_TCAM */
  31         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
  32 };
  33
  34 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
  35         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_FULL_ACTION },
  36         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_MCG },
  37         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_8B },
  38         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_16B },
  39         /* CFA_RESOURCE_TYPE_P4_ENCAP_32B */
  40         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  41         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_ENCAP_64B },
  42         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_MAC },
  43         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 },
  44         /* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 */
  45         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  46         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_COUNTER_64B },
  47         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_SPORT },
  48         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_DPORT },
  49         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_S_IPV4 },
  50         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_D_IPV4 },
  51         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_S_IPV6 },
  52         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_NAT_D_IPV6 },
  53         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER_PROF },
  54         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_METER },
  55         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_MIRROR },
  56         /* CFA_RESOURCE_TYPE_P4_UPAR */
  57         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  58         /* CFA_RESOURCE_TYPE_P4_EPOC */
  59         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  60         /* CFA_RESOURCE_TYPE_P4_METADATA */
  61         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  62         /* CFA_RESOURCE_TYPE_P4_CT_STATE */
  63         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  64         /* CFA_RESOURCE_TYPE_P4_RANGE_PROF */
  65         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  66         /* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */
  67         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  68         /* CFA_RESOURCE_TYPE_P4_LAG */
  69         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  70         /* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */
  71         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  72         /* CFA_RESOURCE_TYPE_P4_EM_FBK */
  73         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  74         /* CFA_RESOURCE_TYPE_P4_WC_FKB */
  75         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  76         /* CFA_RESOURCE_TYPE_P4_EXT */
  77         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
  78 };
  79
  80 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
  81         /* CFA_RESOURCE_TYPE_P4_EM_REC */
  82         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  83         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
  84 };
  85
  86 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
  87         { TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
  88         /* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
  89         { TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
  90 };
  91
  92 #endif /* _TF_DEVICE_P4_H_ */