drivers/net/bnxt/tf_core/tf_device_p4.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P4_H_
   7 #define _TF_DEVICE_P4_H_
   8
   9 #include "cfa_resource_types.h"
  10 #include "tf_core.h"
  11 #include "tf_rm.h"
  12 #include "tf_if_tbl.h"
  13 #include "tf_global_cfg.h"
  14
  15 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
  16         [TF_IDENT_TYPE_L2_CTXT_HIGH] = {
  17                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH
  18         },
  19         [TF_IDENT_TYPE_L2_CTXT_LOW] = {
  20                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW
  21         },
  22         [TF_IDENT_TYPE_PROF_FUNC] = {
  23                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC
  24         },
  25         [TF_IDENT_TYPE_WC_PROF] = {
  26                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID
  27         },
  28         [TF_IDENT_TYPE_EM_PROF] = {
  29                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID
  30         },
  31 };
  32
  33 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
  34         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
  35                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH
  36         },
  37         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
  38                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW
  39         },
  40         [TF_TCAM_TBL_TYPE_PROF_TCAM] = {
  41                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM
  42         },
  43         [TF_TCAM_TBL_TYPE_WC_TCAM] = {
  44                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM
  45         },
  46         [TF_TCAM_TBL_TYPE_SP_TCAM] = {
  47                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM
  48         },
  49 };
  50
  51 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
  52         [TF_TBL_TYPE_FULL_ACT_RECORD] = {
  53                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION
  54         },
  55         [TF_TBL_TYPE_MCAST_GROUPS] = {
  56                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG
  57         },
  58         [TF_TBL_TYPE_ACT_ENCAP_8B] = {
  59                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B
  60         },
  61         [TF_TBL_TYPE_ACT_ENCAP_16B] = {
  62                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B
  63         },
  64         [TF_TBL_TYPE_ACT_ENCAP_64B] = {
  65                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B
  66         },
  67         [TF_TBL_TYPE_ACT_SP_SMAC] = {
  68                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC
  69         },
  70         [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
  71                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4
  72         },
  73         [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
  74                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6
  75         },
  76         [TF_TBL_TYPE_ACT_STATS_64] = {
  77                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B
  78         },
  79         [TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
  80                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4
  81         },
  82         [TF_TBL_TYPE_METER_PROF] = {
  83                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF
  84         },
  85         [TF_TBL_TYPE_METER_INST] = {
  86                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER
  87         },
  88         [TF_TBL_TYPE_MIRROR_CONFIG] = {
  89                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR
  90         },
  91
  92 };
  93
  94 struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
  95         [TF_EM_TBL_TYPE_TBL_SCOPE] = {
  96                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE
  97         },
  98 };
  99
 100 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
 101         [TF_EM_TBL_TYPE_EM_RECORD] = {
 102                 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC
 103         },
 104 };
 105
 106 /* Note that hcapi_types from this table are from hcapi_cfa_p4.h
 107  * These are not CFA resource types because they are not allocated
 108  * CFA resources - they are identifiers for the interface tables
 109  * shared between the firmware and the host.  It may make sense to
 110  * move these types to cfa_resource_types.h.
 111  */
 112 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
 113         [TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = {
 114                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT
 115         },
 116         [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {
 117                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR
 118         },
 119         [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {
 120                 TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR
 121         },
 122         [TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = {
 123                 TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR
 124         },
 125 };
 126
 127 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
 128         [TF_TUNNEL_ENCAP] = {
 129                 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP
 130         },
 131         [TF_ACTION_BLOCK] = {
 132                 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK
 133         },
 134 };
 135 #endif /* _TF_DEVICE_P4_H_ */