1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2021 Broadcom
6 #include <rte_common.h>
8 #include "cfa_resource_types.h"
10 #include "tf_identifier.h"
14 #include "tf_tcam_shared.h"
15 #endif /* TF_TCAM_SHARED */
17 #include "tf_if_tbl.h"
19 #include "tf_msg_common.h"
20 #include "tf_tbl_sram.h"
22 #define TF_DEV_P58_PARIF_MAX 16
23 #define TF_DEV_P58_PF_MASK 0xfUL
25 /* For print alignment, make all entries 8 chars in this table */
26 const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
27 [CFA_RESOURCE_TYPE_P58_METER] = "meter ",
28 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_0] = "sram_bk0",
29 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_1] = "sram_bk1",
30 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_2] = "sram_bk2",
31 [CFA_RESOURCE_TYPE_P58_SRAM_BANK_3] = "sram_bk3",
32 [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH] = "l2ctx_hi",
33 [CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW] = "l2ctx_lo",
34 [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
35 [CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW] = "l2ctr_lo",
36 [CFA_RESOURCE_TYPE_P58_PROF_FUNC] = "prf_func",
37 [CFA_RESOURCE_TYPE_P58_PROF_TCAM] = "prf_tcam",
38 [CFA_RESOURCE_TYPE_P58_EM_PROF_ID] = "em_prof ",
39 [CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID] = "wc_prof ",
40 [CFA_RESOURCE_TYPE_P58_EM_REC] = "em_rec ",
41 [CFA_RESOURCE_TYPE_P58_WC_TCAM] = "wc_tcam ",
42 [CFA_RESOURCE_TYPE_P58_METER_PROF] = "mtr_prof",
43 [CFA_RESOURCE_TYPE_P58_MIRROR] = "mirror ",
44 [CFA_RESOURCE_TYPE_P58_EM_FKB] = "em_fkb ",
45 [CFA_RESOURCE_TYPE_P58_WC_FKB] = "wc_fkb ",
46 [CFA_RESOURCE_TYPE_P58_VEB_TCAM] = "veb ",
47 [CFA_RESOURCE_TYPE_P58_METADATA] = "metadata",
48 [CFA_RESOURCE_TYPE_P58_METER_DROP_CNT] = "meter_dc",
51 struct tf_rm_element_cfg tf_tbl_p58[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
52 [TF_DIR_RX][TF_TBL_TYPE_EM_FKB] = {
53 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
56 [TF_DIR_RX][TF_TBL_TYPE_WC_FKB] = {
57 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
60 [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
61 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
64 [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
65 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
68 [TF_DIR_RX][TF_TBL_TYPE_METER_DROP_CNT] = {
69 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
72 [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
73 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
76 [TF_DIR_RX][TF_TBL_TYPE_METADATA] = {
77 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
80 /* Policy - ARs in bank 1 */
81 [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
82 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
83 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
86 [TF_DIR_RX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
87 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
88 .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
89 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
92 /* Policy - Encaps in bank 2 */
93 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
94 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
95 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
98 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
99 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
100 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
101 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
104 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
105 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
106 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
107 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
110 [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
111 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
112 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
113 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
116 /* Policy - Modify in bank 2 with Encaps */
117 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_8B] = {
118 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
119 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
120 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
123 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
124 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
125 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
126 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
129 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
130 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
131 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
132 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
135 [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
136 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
137 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
138 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
141 /* Policy - SP in bank 0 */
142 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
143 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
144 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
147 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
148 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
149 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
150 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
153 [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
154 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
155 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
156 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
159 /* Policy - Stats in bank 3 */
160 [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
161 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
162 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
165 [TF_DIR_TX][TF_TBL_TYPE_EM_FKB] = {
166 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
169 [TF_DIR_TX][TF_TBL_TYPE_WC_FKB] = {
170 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
173 [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
174 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
177 [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
178 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
181 [TF_DIR_TX][TF_TBL_TYPE_METER_DROP_CNT] = {
182 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_DROP_CNT,
185 [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
186 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
189 [TF_DIR_TX][TF_TBL_TYPE_METADATA] = {
190 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METADATA,
193 /* Policy - ARs in bank 1 */
194 [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
195 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
196 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
199 [TF_DIR_TX][TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
200 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
201 .parent_subtype = TF_TBL_TYPE_FULL_ACT_RECORD,
202 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
205 /* Policy - Encaps in bank 2 */
206 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
207 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
208 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
211 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
212 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
213 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
214 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
217 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_32B] = {
218 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
219 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
220 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
223 [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
224 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
225 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
226 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
229 /* Policy - Modify in bank 2 with Encaps */
230 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_8B] = {
231 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
232 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
233 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
236 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_16B] = {
237 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
238 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
239 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
242 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_32B] = {
243 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
244 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
245 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
248 [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_64B] = {
249 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
250 .parent_subtype = TF_TBL_TYPE_ACT_ENCAP_8B,
251 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
254 /* Policy - SP in bank 0 */
255 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
256 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
257 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
260 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
261 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
262 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
263 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
266 [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
267 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
268 .parent_subtype = TF_TBL_TYPE_ACT_SP_SMAC,
269 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
272 /* Policy - Stats in bank 3 */
273 [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
274 .cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
275 .hcapi_type = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
281 * Device specific function that retrieves the MAX number of HCAPI
282 * types the device supports.
285 * Pointer to TF handle
288 * Pointer to the MAX number of HCAPI types supported
291 * - (0) if successful.
292 * - (-EINVAL) on failure.
295 tf_dev_p58_get_max_types(struct tf *tfp,
298 if (max_types == NULL || tfp == NULL)
301 *max_types = CFA_RESOURCE_TYPE_P58_LAST + 1;
306 * Device specific function that retrieves a human readable
307 * string to identify a CFA resource type.
310 * Pointer to TF handle
313 * HCAPI CFA resource id
319 * - (0) if successful.
320 * - (-EINVAL) on failure.
323 tf_dev_p58_get_resource_str(struct tf *tfp __rte_unused,
324 uint16_t resource_id,
325 const char **resource_str)
327 if (resource_str == NULL)
330 if (resource_id > CFA_RESOURCE_TYPE_P58_LAST)
333 *resource_str = tf_resource_str_p58[resource_id];
339 * Device specific function that set the WC TCAM slices the
343 * Pointer to TF handle
345 * [in] num_slices_per_row
346 * The WC TCAM row slice configuration
349 * - (0) if successful.
350 * - (-EINVAL) on failure.
353 tf_dev_p58_set_tcam_slice_info(struct tf *tfp,
354 enum tf_wc_num_slice num_slices_per_row)
357 struct tf_session *tfs = NULL;
359 /* Retrieve the session information */
360 rc = tf_session_get_session_internal(tfp, &tfs);
364 switch (num_slices_per_row) {
365 case TF_WC_TCAM_1_SLICE_PER_ROW:
366 case TF_WC_TCAM_2_SLICE_PER_ROW:
367 case TF_WC_TCAM_4_SLICE_PER_ROW:
368 tfs->wc_num_slices_per_row = num_slices_per_row;
378 * Device specific function that retrieves the TCAM slices the
382 * Pointer to TF handle
390 * [out] num_slices_per_row
391 * Pointer to the WC TCAM row slice configuration
394 * - (0) if successful.
395 * - (-EINVAL) on failure.
398 tf_dev_p58_get_tcam_slice_info(struct tf *tfp,
399 enum tf_tcam_tbl_type type,
401 uint16_t *num_slices_per_row)
404 struct tf_session *tfs = NULL;
406 /* Retrieve the session information */
407 rc = tf_session_get_session_internal(tfp, &tfs);
411 #define CFA_P58_WC_TCAM_SLICE_SIZE 24
412 if (type == TF_TCAM_TBL_TYPE_WC_TCAM) {
413 *num_slices_per_row = tfs->wc_num_slices_per_row;
414 if (key_sz > *num_slices_per_row * CFA_P58_WC_TCAM_SLICE_SIZE)
416 } else { /* for other type of tcam */
417 *num_slices_per_row = 1;
423 static int tf_dev_p58_get_mailbox(void)
428 static int tf_dev_p58_word_align(uint16_t size)
430 return ((((size) + 63) >> 6) * 8);
434 * Device specific function that retrieves the increment
435 * required for certain table types in a shared session
441 * pointer to parms structure
444 * - (0) if successful.
445 * - (-EINVAL) on failure.
447 static int tf_dev_p58_get_shared_tbl_increment(struct tf *tfp __rte_unused,
448 struct tf_get_shared_tbl_increment_parms *parms)
450 switch (parms->type) {
451 case TF_TBL_TYPE_FULL_ACT_RECORD:
452 case TF_TBL_TYPE_COMPACT_ACT_RECORD:
453 case TF_TBL_TYPE_ACT_ENCAP_8B:
454 case TF_TBL_TYPE_ACT_ENCAP_16B:
455 case TF_TBL_TYPE_ACT_ENCAP_32B:
456 case TF_TBL_TYPE_ACT_ENCAP_64B:
457 case TF_TBL_TYPE_ACT_SP_SMAC:
458 case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
459 case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
460 case TF_TBL_TYPE_ACT_STATS_64:
461 case TF_TBL_TYPE_ACT_MODIFY_IPV4:
462 case TF_TBL_TYPE_ACT_MODIFY_8B:
463 case TF_TBL_TYPE_ACT_MODIFY_16B:
464 case TF_TBL_TYPE_ACT_MODIFY_32B:
465 case TF_TBL_TYPE_ACT_MODIFY_64B:
466 parms->increment_cnt = 8;
469 parms->increment_cnt = 1;
476 * Indicates whether the index table type is SRAM managed
479 * Pointer to TF handle
482 * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
485 * - (0) if the table is not managed by the SRAM manager
486 * - (1) if the table is managed by the SRAM manager
488 static bool tf_dev_p58_is_sram_managed(struct tf *tfp __rte_unused,
489 enum tf_tbl_type type)
492 case TF_TBL_TYPE_FULL_ACT_RECORD:
493 case TF_TBL_TYPE_COMPACT_ACT_RECORD:
494 case TF_TBL_TYPE_ACT_ENCAP_8B:
495 case TF_TBL_TYPE_ACT_ENCAP_16B:
496 case TF_TBL_TYPE_ACT_ENCAP_32B:
497 case TF_TBL_TYPE_ACT_ENCAP_64B:
498 case TF_TBL_TYPE_ACT_SP_SMAC:
499 case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
500 case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
501 case TF_TBL_TYPE_ACT_STATS_64:
502 case TF_TBL_TYPE_ACT_MODIFY_IPV4:
503 case TF_TBL_TYPE_ACT_MODIFY_8B:
504 case TF_TBL_TYPE_ACT_MODIFY_16B:
505 case TF_TBL_TYPE_ACT_MODIFY_32B:
506 case TF_TBL_TYPE_ACT_MODIFY_64B:
513 #define TF_DEV_P58_BANK_SZ_64B 2048
515 * Get SRAM table information.
517 * Converts an internal RM allocated element offset to
518 * a user address and vice versa.
521 * Pointer to TF handle
524 * Truflow index table type, e.g. TF_TYPE_FULL_ACT_RECORD
527 * Pointer to the Base address of the associated SRAM bank used for
528 * the type of record allocated.
531 * Pointer to the factor to be used as a multiplier to translate
532 * between the RM units to the user address. SRAM manages 64B entries
533 * Addresses must be shifted to an 8B address.
536 * - (0) if successful.
537 * - (-EINVAL) on failure.
539 static int tf_dev_p58_get_sram_tbl_info(struct tf *tfp __rte_unused,
541 enum tf_tbl_type type,
546 struct tf_rm_get_hcapi_parms parms;
550 parms.subtype = type;
551 parms.hcapi_type = &hcapi_type;
553 rc = tf_rm_get_hcapi_type(&parms);
560 switch (hcapi_type) {
561 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0:
565 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1:
566 *base = TF_DEV_P58_BANK_SZ_64B;
569 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2:
570 *base = TF_DEV_P58_BANK_SZ_64B * 2;
573 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3:
574 *base = TF_DEV_P58_BANK_SZ_64B * 3;
586 * Device specific function that maps the hcapi resource types
590 * CFA resource type bitmap
593 * Pointer to identifier type bitmap
596 * Pointer to tcam type bitmap
599 * Pointer to table type bitmap
602 * Pointer to em type bitmap
605 * - (0) if successful.
606 * - (-EINVAL) on failure.
608 static int tf_dev_p58_map_hcapi_caps(uint64_t hcapi_caps,
609 uint32_t *ident_caps,
621 for (i = 0; i <= CFA_RESOURCE_TYPE_P58_LAST; i++) {
622 if (hcapi_caps & 1ULL << i) {
623 switch (tf_hcapi_res_map_p58[i].module_type) {
624 case TF_MODULE_TYPE_IDENTIFIER:
625 *ident_caps |= tf_hcapi_res_map_p58[i].type_caps;
627 case TF_MODULE_TYPE_TABLE:
628 *tbl_caps |= tf_hcapi_res_map_p58[i].type_caps;
630 case TF_MODULE_TYPE_TCAM:
631 *tcam_caps |= tf_hcapi_res_map_p58[i].type_caps;
633 case TF_MODULE_TYPE_EM:
634 *em_caps |= tf_hcapi_res_map_p58[i].type_caps;
646 * Device specific function that retrieve the sram resource
649 * Point to resources query result
651 * [out] sram_bank_caps
652 * Pointer to SRAM bank capabilities
654 * [out] dynamic_sram_capable
655 * Pointer to dynamic sram capable
658 * - (0) if successful.
659 * - (-EINVAL) on failure.
661 static int tf_dev_p58_get_sram_resources(void *q,
662 uint32_t *sram_bank_caps,
663 bool *dynamic_sram_capable)
666 struct tf_rm_resc_req_entry *query = q;
668 for (i = 0; i < CFA_RESOURCE_TYPE_P58_LAST + 1; i++) {
669 switch (query[i].type) {
670 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_0:
671 sram_bank_caps[0] = query[i].max;
673 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_1:
674 sram_bank_caps[1] = query[i].max;
676 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_2:
677 sram_bank_caps[2] = query[i].max;
679 case CFA_RESOURCE_TYPE_P58_SRAM_BANK_3:
680 sram_bank_caps[3] = query[i].max;
687 *dynamic_sram_capable = false;
692 static int sram_bank_hcapi_type[] = {
693 CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
694 CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
695 CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
696 CFA_RESOURCE_TYPE_P58_SRAM_BANK_3
700 * Device specific function that set the sram policy
703 * Receive or transmit direction
709 * - (0) if successful.
710 * - (-EINVAL) on failure.
712 static int tf_dev_p58_set_sram_policy(enum tf_dir dir,
713 enum tf_sram_bank_id *bank_id)
715 struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];
717 uint8_t parent[TF_SRAM_BANK_ID_MAX] = { 0xFF, 0xFF, 0xFF, 0xFF };
719 for (type = TF_TBL_TYPE_FULL_ACT_RECORD;
720 type <= TF_TBL_TYPE_ACT_MODIFY_64B; type++) {
721 if (bank_id[type] >= TF_SRAM_BANK_ID_MAX)
724 rm_cfg[type].hcapi_type = sram_bank_hcapi_type[bank_id[type]];
725 if (parent[bank_id[type]] == 0xFF) {
726 parent[bank_id[type]] = type;
727 rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_PARENT;
728 rm_cfg[type].parent_subtype = 0;
729 if (rm_cfg[type].slices == 0)
730 rm_cfg[type].slices = 1;
732 rm_cfg[type].cfg_type = TF_RM_ELEM_CFG_HCAPI_BA_CHILD;
733 rm_cfg[type].parent_subtype = parent[bank_id[type]];
741 * Device specific function that get the sram policy
744 * Receive or transmit direction
747 * pointer to SRAM bank id
750 * - (0) if successful.
751 * - (-EINVAL) on failure.
753 static int tf_dev_p58_get_sram_policy(enum tf_dir dir,
754 enum tf_sram_bank_id *bank_id)
756 struct tf_rm_element_cfg *rm_cfg = tf_tbl_p58[dir];
759 for (type = TF_TBL_TYPE_FULL_ACT_RECORD;
760 type < TF_TBL_TYPE_ACT_MODIFY_64B + 1; type++)
761 bank_id[type] = rm_cfg[type].hcapi_type - CFA_RESOURCE_TYPE_P58_SRAM_BANK_0;
767 * Truflow P58 device specific functions
769 const struct tf_dev_ops tf_dev_ops_p58_init = {
770 .tf_dev_get_max_types = tf_dev_p58_get_max_types,
771 .tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
772 .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
773 .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
774 .tf_dev_alloc_ident = NULL,
775 .tf_dev_free_ident = NULL,
776 .tf_dev_search_ident = NULL,
777 .tf_dev_get_ident_resc_info = NULL,
778 .tf_dev_get_tbl_info = NULL,
779 .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
780 .tf_dev_alloc_ext_tbl = NULL,
781 .tf_dev_alloc_tbl = NULL,
782 .tf_dev_alloc_sram_tbl = NULL,
783 .tf_dev_free_ext_tbl = NULL,
784 .tf_dev_free_tbl = NULL,
785 .tf_dev_free_sram_tbl = NULL,
786 .tf_dev_set_tbl = NULL,
787 .tf_dev_set_ext_tbl = NULL,
788 .tf_dev_set_sram_tbl = NULL,
789 .tf_dev_get_tbl = NULL,
790 .tf_dev_get_sram_tbl = NULL,
791 .tf_dev_get_bulk_tbl = NULL,
792 .tf_dev_get_bulk_sram_tbl = NULL,
793 .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
794 .tf_dev_get_tbl_resc_info = NULL,
795 .tf_dev_alloc_tcam = NULL,
796 .tf_dev_free_tcam = NULL,
797 .tf_dev_alloc_search_tcam = NULL,
798 .tf_dev_set_tcam = NULL,
799 .tf_dev_get_tcam = NULL,
800 .tf_dev_get_tcam_resc_info = NULL,
801 .tf_dev_insert_int_em_entry = NULL,
802 .tf_dev_delete_int_em_entry = NULL,
803 .tf_dev_insert_ext_em_entry = NULL,
804 .tf_dev_delete_ext_em_entry = NULL,
805 .tf_dev_get_em_resc_info = NULL,
806 .tf_dev_alloc_tbl_scope = NULL,
807 .tf_dev_map_tbl_scope = NULL,
808 .tf_dev_map_parif = NULL,
809 .tf_dev_free_tbl_scope = NULL,
810 .tf_dev_set_if_tbl = NULL,
811 .tf_dev_get_if_tbl = NULL,
812 .tf_dev_set_global_cfg = NULL,
813 .tf_dev_get_global_cfg = NULL,
814 .tf_dev_get_mailbox = tf_dev_p58_get_mailbox,
815 .tf_dev_word_align = NULL,
816 .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,
817 .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,
818 .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,
819 .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,
823 * Truflow P58 device specific functions
825 const struct tf_dev_ops tf_dev_ops_p58 = {
826 .tf_dev_get_max_types = tf_dev_p58_get_max_types,
827 .tf_dev_get_resource_str = tf_dev_p58_get_resource_str,
828 .tf_dev_set_tcam_slice_info = tf_dev_p58_set_tcam_slice_info,
829 .tf_dev_get_tcam_slice_info = tf_dev_p58_get_tcam_slice_info,
830 .tf_dev_alloc_ident = tf_ident_alloc,
831 .tf_dev_free_ident = tf_ident_free,
832 .tf_dev_search_ident = tf_ident_search,
833 .tf_dev_get_ident_resc_info = tf_ident_get_resc_info,
834 .tf_dev_is_sram_managed = tf_dev_p58_is_sram_managed,
835 .tf_dev_get_tbl_info = tf_dev_p58_get_sram_tbl_info,
836 .tf_dev_alloc_tbl = tf_tbl_alloc,
837 .tf_dev_alloc_sram_tbl = tf_tbl_sram_alloc,
838 .tf_dev_alloc_ext_tbl = tf_tbl_ext_alloc,
839 .tf_dev_free_tbl = tf_tbl_free,
840 .tf_dev_free_ext_tbl = tf_tbl_ext_free,
841 .tf_dev_free_sram_tbl = tf_tbl_sram_free,
842 .tf_dev_set_tbl = tf_tbl_set,
843 .tf_dev_set_ext_tbl = tf_tbl_ext_common_set,
844 .tf_dev_set_sram_tbl = tf_tbl_sram_set,
845 .tf_dev_get_tbl = tf_tbl_get,
846 .tf_dev_get_sram_tbl = tf_tbl_sram_get,
847 .tf_dev_get_bulk_tbl = tf_tbl_bulk_get,
848 .tf_dev_get_bulk_sram_tbl = tf_tbl_sram_bulk_get,
849 .tf_dev_get_shared_tbl_increment = tf_dev_p58_get_shared_tbl_increment,
850 .tf_dev_get_tbl_resc_info = tf_tbl_get_resc_info,
851 #ifdef TF_TCAM_SHARED
852 .tf_dev_alloc_tcam = tf_tcam_shared_alloc,
853 .tf_dev_free_tcam = tf_tcam_shared_free,
854 .tf_dev_set_tcam = tf_tcam_shared_set,
855 .tf_dev_get_tcam = tf_tcam_shared_get,
856 .tf_dev_move_tcam = tf_tcam_shared_move_p58,
857 .tf_dev_clear_tcam = tf_tcam_shared_clear,
858 #else /* !TF_TCAM_SHARED */
859 .tf_dev_alloc_tcam = tf_tcam_alloc,
860 .tf_dev_free_tcam = tf_tcam_free,
861 .tf_dev_set_tcam = tf_tcam_set,
862 .tf_dev_get_tcam = tf_tcam_get,
864 .tf_dev_alloc_search_tcam = tf_tcam_alloc_search,
865 .tf_dev_get_tcam_resc_info = tf_tcam_get_resc_info,
866 .tf_dev_insert_int_em_entry = tf_em_hash_insert_int_entry,
867 .tf_dev_delete_int_em_entry = tf_em_hash_delete_int_entry,
868 .tf_dev_move_int_em_entry = tf_em_move_int_entry,
869 .tf_dev_insert_ext_em_entry = NULL,
870 .tf_dev_delete_ext_em_entry = NULL,
871 .tf_dev_get_em_resc_info = tf_em_get_resc_info,
872 .tf_dev_alloc_tbl_scope = NULL,
873 .tf_dev_map_tbl_scope = NULL,
874 .tf_dev_map_parif = NULL,
875 .tf_dev_free_tbl_scope = NULL,
876 .tf_dev_set_if_tbl = tf_if_tbl_set,
877 .tf_dev_get_if_tbl = tf_if_tbl_get,
878 .tf_dev_set_global_cfg = tf_global_cfg_set,
879 .tf_dev_get_global_cfg = tf_global_cfg_get,
880 .tf_dev_get_mailbox = tf_dev_p58_get_mailbox,
881 .tf_dev_word_align = tf_dev_p58_word_align,
882 .tf_dev_cfa_key_hash = hcapi_cfa_p58_key_hash,
883 .tf_dev_map_hcapi_caps = tf_dev_p58_map_hcapi_caps,
884 .tf_dev_get_sram_resources = tf_dev_p58_get_sram_resources,
885 .tf_dev_set_sram_policy = tf_dev_p58_set_sram_policy,
886 .tf_dev_get_sram_policy = tf_dev_p58_get_sram_policy,