drivers/net/bnxt/tf_core/tf_device_p58.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P58_H_
   7 #define _TF_DEVICE_P58_H_
   8
   9 #include "cfa_resource_types.h"
  10 #include "tf_core.h"
  11 #include "tf_rm.h"
  12 #include "tf_if_tbl.h"
  13 #include "tf_global_cfg.h"
  14
  15 struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
  16         [TF_IDENT_TYPE_L2_CTXT_HIGH] = {
  17                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH,
  18                 0, 0, 0
  19         },
  20         [TF_IDENT_TYPE_L2_CTXT_LOW] = {
  21                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW,
  22                 0, 0, 0
  23         },
  24         [TF_IDENT_TYPE_PROF_FUNC] = {
  25                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC,
  26                 0, 0, 0
  27         },
  28         [TF_IDENT_TYPE_WC_PROF] = {
  29                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID,
  30                 0, 0, 0
  31         },
  32         [TF_IDENT_TYPE_EM_PROF] = {
  33                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID,
  34                 0, 0, 0
  35         },
  36 };
  37
  38 struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
  39         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
  40                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH,
  41                 0, 0, 0
  42         },
  43         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
  44                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW,
  45                 0, 0, 0
  46         },
  47         [TF_TCAM_TBL_TYPE_PROF_TCAM] = {
  48                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM,
  49                 0, 0, 0
  50         },
  51         [TF_TCAM_TBL_TYPE_WC_TCAM] = {
  52                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM,
  53                 0, 0, 0
  54         },
  55         [TF_TCAM_TBL_TYPE_VEB_TCAM] = {
  56                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM,
  57                 0, 0, 0
  58         },
  59 };
  60
  61 struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
  62         [TF_TBL_TYPE_EM_FKB] = {
  63                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB,
  64                 0, 0, 0
  65         },
  66         [TF_TBL_TYPE_WC_FKB] = {
  67                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB,
  68                 0, 0, 0
  69         },
  70         [TF_TBL_TYPE_METER_PROF] = {
  71                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF,
  72                 0, 0, 0
  73         },
  74         [TF_TBL_TYPE_METER_INST] = {
  75                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER,
  76                 0, 0, 0
  77         },
  78         [TF_TBL_TYPE_MIRROR_CONFIG] = {
  79                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR,
  80                 0, 0, 0
  81         },
  82         /* Policy - ARs in bank 1 */
  83         [TF_TBL_TYPE_FULL_ACT_RECORD] = {
  84                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
  85                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
  86                 .slices          = 1,
  87                 .divider         = 8,
  88         },
  89         [TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
  90                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
  91                 .parent_subtype  = TF_TBL_TYPE_FULL_ACT_RECORD,
  92                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
  93                 .slices          = 1,
  94                 .divider         = 8,
  95         },
  96         /* Policy - Encaps in bank 2 */
  97         [TF_TBL_TYPE_ACT_ENCAP_8B] = {
  98                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
  99                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 100                 .slices          = 1,
 101                 .divider         = 8,
 102         },
 103         [TF_TBL_TYPE_ACT_ENCAP_16B] = {
 104                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 105                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 106                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 107                 .slices          = 1,
 108                 .divider         = 8,
 109         },
 110         [TF_TBL_TYPE_ACT_ENCAP_32B] = {
 111                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 112                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 113                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 114                 .slices          = 1,
 115                 .divider         = 8,
 116         },
 117         [TF_TBL_TYPE_ACT_ENCAP_64B] = {
 118                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 119                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 120                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 121                 .slices          = 1,
 122                 .divider         = 8,
 123         },
 124         /* Policy - Modify in bank 2 with Encaps */
 125         [TF_TBL_TYPE_ACT_MODIFY_8B] = {
 126                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 127                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 128                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 129                 .slices          = 1,
 130                 .divider         = 8,
 131         },
 132         [TF_TBL_TYPE_ACT_MODIFY_16B] = {
 133                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 134                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 135                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 136                 .slices          = 1,
 137                 .divider         = 8,
 138         },
 139         [TF_TBL_TYPE_ACT_MODIFY_32B] = {
 140                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 141                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 142                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 143                 .slices          = 1,
 144                 .divider         = 8,
 145         },
 146         [TF_TBL_TYPE_ACT_MODIFY_64B] = {
 147                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 148                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 149                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 150                 .slices          = 1,
 151                 .divider         = 8,
 152         },
 153         /* Policy - SP in bank 0 */
 154         [TF_TBL_TYPE_ACT_SP_SMAC] = {
 155                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
 156                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 157                 .slices          = 1,
 158                 .divider         = 8,
 159         },
 160         [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
 161                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 162                 .parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,
 163                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 164                 .slices          = 1,
 165                 .divider         = 8,
 166         },
 167         [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
 168                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 169                 .parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,
 170                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 171                 .slices          = 1,
 172                 .divider         = 8,
 173         },
 174         /* Policy - Stats in bank 3 */
 175         [TF_TBL_TYPE_ACT_STATS_64] = {
 176                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
 177                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
 178                 .slices          = 1,
 179                 .divider         = 8,
 180         },
 181 };
 182
 183 struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
 184         [TF_EM_TBL_TYPE_EM_RECORD] = {
 185                 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC,
 186                 0, 0, 0
 187         },
 188 };
 189
 190 struct tf_if_tbl_cfg tf_if_tbl_p58[TF_IF_TBL_TYPE_MAX] = {
 191         [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {
 192                 TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_DFLT_ACT_REC_PTR},
 193         [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {
 194                 TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_ERR_ACT_REC_PTR},
 195         [TF_IF_TBL_TYPE_ILT] = {
 196                 TF_IF_TBL_CFG, CFA_P58_TBL_ILT},
 197         [TF_IF_TBL_TYPE_VSPT] = {
 198                 TF_IF_TBL_CFG, CFA_P58_TBL_VSPT},
 199 };
 200
 201 struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
 202         [TF_TUNNEL_ENCAP] = {
 203                 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP
 204         },
 205         [TF_ACTION_BLOCK] = {
 206                 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK
 207         },
 208         [TF_COUNTER_CFG] = {
 209                 TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
 210         },
 211 };
 212 #endif /* _TF_DEVICE_P58_H_ */