drivers/net/bnxt/tf_core/tf_device_p58.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _TF_DEVICE_P58_H_
   7 #define _TF_DEVICE_P58_H_
   8
   9 #include "cfa_resource_types.h"
  10 #include "tf_core.h"
  11 #include "tf_rm.h"
  12 #include "tf_if_tbl.h"
  13 #include "tf_global_cfg.h"
  14
  15 struct tf_rm_element_cfg tf_ident_p58[TF_IDENT_TYPE_MAX] = {
  16         [TF_IDENT_TYPE_L2_CTXT_HIGH] = {
  17                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH
  18         },
  19         [TF_IDENT_TYPE_L2_CTXT_LOW] = {
  20                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW
  21         },
  22         [TF_IDENT_TYPE_PROF_FUNC] = {
  23                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_FUNC
  24         },
  25         [TF_IDENT_TYPE_WC_PROF] = {
  26                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID
  27         },
  28         [TF_IDENT_TYPE_EM_PROF] = {
  29                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_PROF_ID
  30         },
  31 };
  32
  33 struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
  34         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
  35                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH
  36         },
  37         [TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
  38                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW
  39         },
  40         [TF_TCAM_TBL_TYPE_PROF_TCAM] = {
  41                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_PROF_TCAM
  42         },
  43         [TF_TCAM_TBL_TYPE_WC_TCAM] = {
  44                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_TCAM
  45         },
  46         [TF_TCAM_TBL_TYPE_VEB_TCAM] = {
  47                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_VEB_TCAM
  48         },
  49 };
  50
  51 struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
  52         [TF_TBL_TYPE_EM_FKB] = {
  53                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB
  54         },
  55         [TF_TBL_TYPE_WC_FKB] = {
  56                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB
  57         },
  58         [TF_TBL_TYPE_METER_PROF] = {
  59                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF
  60         },
  61         [TF_TBL_TYPE_METER_INST] = {
  62                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER
  63         },
  64         [TF_TBL_TYPE_MIRROR_CONFIG] = {
  65                 TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_MIRROR
  66         },
  67         /* Policy - ARs in bank 1 */
  68         [TF_TBL_TYPE_FULL_ACT_RECORD] = {
  69                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
  70                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
  71                 .slices          = 1,
  72                 .divider         = 8,
  73         },
  74         [TF_TBL_TYPE_COMPACT_ACT_RECORD] = {
  75                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
  76                 .parent_subtype  = TF_TBL_TYPE_FULL_ACT_RECORD,
  77                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_1,
  78                 .slices          = 1,
  79                 .divider         = 8,
  80         },
  81         /* Policy - Encaps in bank 2 */
  82         [TF_TBL_TYPE_ACT_ENCAP_8B] = {
  83                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
  84                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
  85                 .slices          = 1,
  86                 .divider         = 8,
  87         },
  88         [TF_TBL_TYPE_ACT_ENCAP_16B] = {
  89                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
  90                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
  91                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
  92                 .slices          = 1,
  93                 .divider         = 8,
  94         },
  95         [TF_TBL_TYPE_ACT_ENCAP_32B] = {
  96                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
  97                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
  98                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
  99                 .slices          = 1,
 100                 .divider         = 8,
 101         },
 102         [TF_TBL_TYPE_ACT_ENCAP_64B] = {
 103                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 104                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 105                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 106                 .slices          = 1,
 107                 .divider         = 8,
 108         },
 109         /* Policy - Modify in bank 2 with Encaps */
 110         [TF_TBL_TYPE_ACT_MODIFY_8B] = {
 111                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 112                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 113                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 114                 .slices          = 1,
 115                 .divider         = 8,
 116         },
 117         [TF_TBL_TYPE_ACT_MODIFY_16B] = {
 118                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 119                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 120                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 121                 .slices          = 1,
 122                 .divider         = 8,
 123         },
 124         [TF_TBL_TYPE_ACT_MODIFY_32B] = {
 125                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 126                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 127                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 128                 .slices          = 1,
 129                 .divider         = 8,
 130         },
 131         [TF_TBL_TYPE_ACT_MODIFY_64B] = {
 132                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 133                 .parent_subtype  = TF_TBL_TYPE_ACT_ENCAP_8B,
 134                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_2,
 135                 .slices          = 1,
 136                 .divider         = 8,
 137         },
 138         /* Policy - SP in bank 0 */
 139         [TF_TBL_TYPE_ACT_SP_SMAC] = {
 140                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
 141                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 142                 .slices          = 1,
 143                 .divider         = 8,
 144         },
 145         [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
 146                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 147                 .parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,
 148                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 149                 .slices          = 1,
 150                 .divider         = 8,
 151         },
 152         [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
 153                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_CHILD,
 154                 .parent_subtype  = TF_TBL_TYPE_ACT_SP_SMAC,
 155                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_0,
 156                 .slices          = 1,
 157                 .divider         = 8,
 158         },
 159         /* Policy - Stats in bank 3 */
 160         [TF_TBL_TYPE_ACT_STATS_64] = {
 161                 .cfg_type        = TF_RM_ELEM_CFG_HCAPI_BA_PARENT,
 162                 .hcapi_type      = CFA_RESOURCE_TYPE_P58_SRAM_BANK_3,
 163                 .slices          = 1,
 164                 .divider         = 8,
 165         },
 166 };
 167
 168 struct tf_rm_element_cfg tf_em_int_p58[TF_EM_TBL_TYPE_MAX] = {
 169         [TF_EM_TBL_TYPE_EM_RECORD] = {
 170                 TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P58_EM_REC
 171         },
 172 };
 173
 174 struct tf_if_tbl_cfg tf_if_tbl_p58[TF_IF_TBL_TYPE_MAX] = {
 175         [TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {
 176                 TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_DFLT_ACT_REC_PTR},
 177         [TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {
 178                 TF_IF_TBL_CFG, CFA_P58_TBL_PROF_PARIF_ERR_ACT_REC_PTR},
 179         [TF_IF_TBL_TYPE_ILT] = {
 180                 TF_IF_TBL_CFG, CFA_P58_TBL_ILT},
 181         [TF_IF_TBL_TYPE_VSPT] = {
 182                 TF_IF_TBL_CFG, CFA_P58_TBL_VSPT},
 183 };
 184
 185 struct tf_global_cfg_cfg tf_global_cfg_p58[TF_GLOBAL_CFG_TYPE_MAX] = {
 186         [TF_TUNNEL_ENCAP] = {
 187                 TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP
 188         },
 189         [TF_ACTION_BLOCK] = {
 190                 TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK
 191         },
 192         [TF_COUNTER_CFG] = {
 193                 TF_GLOBAL_CFG_CFG_HCAPI, TF_COUNTER_CFG
 194         },
 195 };
 196 #endif /* _TF_DEVICE_P58_H_ */