1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Broadcom
6 #ifndef _TF_RESOURCES_H_
7 #define _TF_RESOURCES_H_
10 * Hardware specific MAX values
11 * NOTE: Should really come from the chip_cfg.h in some MAX form or HCAPI
14 /* Common HW resources for all chip variants */
15 #define TF_NUM_L2_CTXT_TCAM 1024 /* < Number of L2 context TCAM
18 #define TF_NUM_PROF_FUNC 128 /* < Number prof_func ID */
19 #define TF_NUM_PROF_TCAM 1024 /* < Number entries in profile
22 #define TF_NUM_EM_PROF_ID 64 /* < Number software EM Profile
25 #define TF_NUM_WC_PROF_ID 256 /* < Number WC profile IDs */
26 #define TF_NUM_WC_TCAM_ROW 512 /* < Number of rows in WC TCAM */
27 #define TF_NUM_METER_PROF 256 /* < Number of meter profiles */
28 #define TF_NUM_METER 1024 /* < Number of meter instances */
29 #define TF_NUM_MIRROR 2 /* < Number of mirror instances */
30 #define TF_NUM_UPAR 2 /* < Number of UPAR instances */
32 /* Wh+/SR specific HW resources */
33 #define TF_NUM_SP_TCAM 512 /* < Number of Source Property TCAM
37 /* SR/SR2 specific HW resources */
38 #define TF_NUM_L2_FUNC 256 /* < Number of L2 Func */
41 /* Thor, SR2 common HW resources */
42 #define TF_NUM_FKB 1 /* < Number of Flexible Key Builder
46 /* SR2 specific HW resources */
47 #define TF_NUM_TBL_SCOPE 16 /* < Number of TBL scopes */
48 #define TF_NUM_EPOCH0 1 /* < Number of Epoch0 */
49 #define TF_NUM_EPOCH1 1 /* < Number of Epoch1 */
50 #define TF_NUM_METADATA 8 /* < Number of MetaData Profiles */
51 #define TF_NUM_CT_STATE 32 /* < Number of Connection Tracking
54 #define TF_NUM_RANGE_PROF 16 /* < Number of Range Profiles */
55 #define TF_NUM_RANGE_ENTRY (64 * 1024) /* < Number of Range Entries */
56 #define TF_NUM_LAG_ENTRY 256 /* < Number of LAG Entries */
59 * Common for the Reserved Resource defines below:
62 * For resources where a priority level plays a role, i.e. l2 ctx
63 * tcam entries, both a number of resources and a begin/end pair is
64 * required. The begin/end is used to assure TFLIB gets the correct
65 * priority setting for that resource.
67 * For EM records there is no priority required thus a number of
68 * resources is sufficient.
71 * 64 L2 CTXT TCAM entries would in a max 1024 pool be entry
72 * 0-63 as HW presents 0 as the highest priority entry.
75 * Handled as regular resources as there is no priority required.
77 * Common for these resources is that they are handled per direction,
84 #define TF_RSVD_L2_CTXT_TCAM_RX 64
85 #define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_RX 0
86 #define TF_RSVD_L2_CTXT_TCAM_END_IDX_RX (TF_RSVD_L2_CTXT_RX - 1)
87 #define TF_RSVD_L2_CTXT_TCAM_TX 960
88 #define TF_RSVD_L2_CTXT_TCAM_BEGIN_IDX_TX 0
89 #define TF_RSVD_L2_CTXT_TCAM_END_IDX_TX (TF_RSVD_L2_CTXT_TX - 1)
92 #define TF_RSVD_PROF_FUNC_RX 64
93 #define TF_RSVD_PROF_FUNC_BEGIN_IDX_RX 64
94 #define TF_RSVD_PROF_FUNC_END_IDX_RX 127
95 #define TF_RSVD_PROF_FUNC_TX 64
96 #define TF_RSVD_PROF_FUNC_BEGIN_IDX_TX 64
97 #define TF_RSVD_PROF_FUNC_END_IDX_TX 127
99 #define TF_RSVD_PROF_TCAM_RX 64
100 #define TF_RSVD_PROF_TCAM_BEGIN_IDX_RX 960
101 #define TF_RSVD_PROF_TCAM_END_IDX_RX 1023
102 #define TF_RSVD_PROF_TCAM_TX 64
103 #define TF_RSVD_PROF_TCAM_BEGIN_IDX_TX 960
104 #define TF_RSVD_PROF_TCAM_END_IDX_TX 1023
106 /* EM Profiles IDs */
107 #define TF_RSVD_EM_PROF_ID_RX 64
108 #define TF_RSVD_EM_PROF_ID_BEGIN_IDX_RX 0
109 #define TF_RSVD_EM_PROF_ID_END_IDX_RX 63 /* Less on CU+ then SR */
110 #define TF_RSVD_EM_PROF_ID_TX 64
111 #define TF_RSVD_EM_PROF_ID_BEGIN_IDX_TX 0
112 #define TF_RSVD_EM_PROF_ID_END_IDX_TX 63 /* Less on CU+ then SR */
115 #define TF_RSVD_EM_REC_RX 16000
116 #define TF_RSVD_EM_REC_BEGIN_IDX_RX 0
117 #define TF_RSVD_EM_REC_TX 16000
118 #define TF_RSVD_EM_REC_BEGIN_IDX_TX 0
121 #define TF_RSVD_WC_TCAM_PROF_ID_RX 128
122 #define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_RX 128
123 #define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_RX 255
124 #define TF_RSVD_WC_TCAM_PROF_ID_TX 128
125 #define TF_RSVD_WC_TCAM_PROF_ID_BEGIN_IDX_TX 128
126 #define TF_RSVD_WC_TCAM_PROF_ID_END_IDX_TX 255
128 #define TF_RSVD_WC_TCAM_RX 64
129 #define TF_RSVD_WC_TCAM_BEGIN_IDX_RX 0
130 #define TF_RSVD_WC_TCAM_END_IDX_RX 63
131 #define TF_RSVD_WC_TCAM_TX 64
132 #define TF_RSVD_WC_TCAM_BEGIN_IDX_TX 0
133 #define TF_RSVD_WC_TCAM_END_IDX_TX 63
135 #define TF_RSVD_METER_PROF_RX 0
136 #define TF_RSVD_METER_PROF_BEGIN_IDX_RX 0
137 #define TF_RSVD_METER_PROF_END_IDX_RX 0
138 #define TF_RSVD_METER_PROF_TX 0
139 #define TF_RSVD_METER_PROF_BEGIN_IDX_TX 0
140 #define TF_RSVD_METER_PROF_END_IDX_TX 0
142 #define TF_RSVD_METER_INST_RX 0
143 #define TF_RSVD_METER_INST_BEGIN_IDX_RX 0
144 #define TF_RSVD_METER_INST_END_IDX_RX 0
145 #define TF_RSVD_METER_INST_TX 0
146 #define TF_RSVD_METER_INST_BEGIN_IDX_TX 0
147 #define TF_RSVD_METER_INST_END_IDX_TX 0
150 /* Not yet supported fully in the infra */
151 #define TF_RSVD_MIRROR_RX 0
152 #define TF_RSVD_MIRROR_BEGIN_IDX_RX 0
153 #define TF_RSVD_MIRROR_END_IDX_RX 0
154 #define TF_RSVD_MIRROR_TX 0
155 #define TF_RSVD_MIRROR_BEGIN_IDX_TX 0
156 #define TF_RSVD_MIRROR_END_IDX_TX 0
159 /* Not yet supported fully in the infra */
160 #define TF_RSVD_UPAR_RX 0
161 #define TF_RSVD_UPAR_BEGIN_IDX_RX 0
162 #define TF_RSVD_UPAR_END_IDX_RX 0
163 #define TF_RSVD_UPAR_TX 0
164 #define TF_RSVD_UPAR_BEGIN_IDX_TX 0
165 #define TF_RSVD_UPAR_END_IDX_TX 0
167 /* Source Properties */
168 /* Not yet supported fully in the infra */
169 #define TF_RSVD_SP_TCAM_RX 0
170 #define TF_RSVD_SP_TCAM_BEGIN_IDX_RX 0
171 #define TF_RSVD_SP_TCAM_END_IDX_RX 0
172 #define TF_RSVD_SP_TCAM_TX 0
173 #define TF_RSVD_SP_TCAM_BEGIN_IDX_TX 0
174 #define TF_RSVD_SP_TCAM_END_IDX_TX 0
177 #define TF_RSVD_L2_FUNC_RX 0
178 #define TF_RSVD_L2_FUNC_BEGIN_IDX_RX 0
179 #define TF_RSVD_L2_FUNC_END_IDX_RX 0
180 #define TF_RSVD_L2_FUNC_TX 0
181 #define TF_RSVD_L2_FUNC_BEGIN_IDX_TX 0
182 #define TF_RSVD_L2_FUNC_END_IDX_TX 0
185 #define TF_RSVD_FKB_RX 0
186 #define TF_RSVD_FKB_BEGIN_IDX_RX 0
187 #define TF_RSVD_FKB_END_IDX_RX 0
188 #define TF_RSVD_FKB_TX 0
189 #define TF_RSVD_FKB_BEGIN_IDX_TX 0
190 #define TF_RSVD_FKB_END_IDX_TX 0
193 #define TF_RSVD_TBL_SCOPE_RX 1
194 #define TF_RSVD_TBL_SCOPE_BEGIN_IDX_RX 0
195 #define TF_RSVD_TBL_SCOPE_END_IDX_RX 1
196 #define TF_RSVD_TBL_SCOPE_TX 1
197 #define TF_RSVD_TBL_SCOPE_BEGIN_IDX_TX 0
198 #define TF_RSVD_TBL_SCOPE_END_IDX_TX 1
201 /* Not yet supported fully in the infra */
202 #define TF_RSVD_EPOCH0_RX 0
203 #define TF_RSVD_EPOCH0_BEGIN_IDX_RX 0
204 #define TF_RSVD_EPOCH0_END_IDX_RX 0
205 #define TF_RSVD_EPOCH0_TX 0
206 #define TF_RSVD_EPOCH0_BEGIN_IDX_TX 0
207 #define TF_RSVD_EPOCH0_END_IDX_TX 0
210 /* Not yet supported fully in the infra */
211 #define TF_RSVD_EPOCH1_RX 0
212 #define TF_RSVD_EPOCH1_BEGIN_IDX_RX 0
213 #define TF_RSVD_EPOCH1_END_IDX_RX 0
214 #define TF_RSVD_EPOCH1_TX 0
215 #define TF_RSVD_EPOCH1_BEGIN_IDX_TX 0
216 #define TF_RSVD_EPOCH1_END_IDX_TX 0
219 /* Not yet supported fully in the infra */
220 #define TF_RSVD_METADATA_RX 0
221 #define TF_RSVD_METADATA_BEGIN_IDX_RX 0
222 #define TF_RSVD_METADATA_END_IDX_RX 0
223 #define TF_RSVD_METADATA_TX 0
224 #define TF_RSVD_METADATA_BEGIN_IDX_TX 0
225 #define TF_RSVD_METADATA_END_IDX_TX 0
228 /* Not yet supported fully in the infra */
229 #define TF_RSVD_CT_STATE_RX 0
230 #define TF_RSVD_CT_STATE_BEGIN_IDX_RX 0
231 #define TF_RSVD_CT_STATE_END_IDX_RX 0
232 #define TF_RSVD_CT_STATE_TX 0
233 #define TF_RSVD_CT_STATE_BEGIN_IDX_TX 0
234 #define TF_RSVD_CT_STATE_END_IDX_TX 0
237 /* Not yet supported fully in the infra */
238 #define TF_RSVD_RANGE_PROF_RX 0
239 #define TF_RSVD_RANGE_PROF_BEGIN_IDX_RX 0
240 #define TF_RSVD_RANGE_PROF_END_IDX_RX 0
241 #define TF_RSVD_RANGE_PROF_TX 0
242 #define TF_RSVD_RANGE_PROF_BEGIN_IDX_TX 0
243 #define TF_RSVD_RANGE_PROF_END_IDX_TX 0
246 /* Not yet supported fully in the infra */
247 #define TF_RSVD_RANGE_ENTRY_RX 0
248 #define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_RX 0
249 #define TF_RSVD_RANGE_ENTRY_END_IDX_RX 0
250 #define TF_RSVD_RANGE_ENTRY_TX 0
251 #define TF_RSVD_RANGE_ENTRY_BEGIN_IDX_TX 0
252 #define TF_RSVD_RANGE_ENTRY_END_IDX_TX 0
255 /* Not yet supported fully in the infra */
256 #define TF_RSVD_LAG_ENTRY_RX 0
257 #define TF_RSVD_LAG_ENTRY_BEGIN_IDX_RX 0
258 #define TF_RSVD_LAG_ENTRY_END_IDX_RX 0
259 #define TF_RSVD_LAG_ENTRY_TX 0
260 #define TF_RSVD_LAG_ENTRY_BEGIN_IDX_TX 0
261 #define TF_RSVD_LAG_ENTRY_END_IDX_TX 0
265 * Limited to the types that CFA provides.
267 #define TF_RSVD_SRAM_FULL_ACTION_RX 8001
268 #define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_RX 0
269 #define TF_RSVD_SRAM_FULL_ACTION_TX 8001
270 #define TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_TX 0
272 /* Not yet supported fully in the infra */
273 #define TF_RSVD_SRAM_MCG_RX 0
274 #define TF_RSVD_SRAM_MCG_BEGIN_IDX_RX 0
275 /* Multicast Group on TX is not supported */
276 #define TF_RSVD_SRAM_MCG_TX 0
277 #define TF_RSVD_SRAM_MCG_BEGIN_IDX_TX 0
279 /* First encap of 8B RX is reserved by CFA */
280 #define TF_RSVD_SRAM_ENCAP_8B_RX 32
281 #define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_RX 0
282 /* First encap of 8B TX is reserved by CFA */
283 #define TF_RSVD_SRAM_ENCAP_8B_TX 0
284 #define TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_TX 0
286 #define TF_RSVD_SRAM_ENCAP_16B_RX 16
287 #define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_RX 0
288 /* First encap of 16B TX is reserved by CFA */
289 #define TF_RSVD_SRAM_ENCAP_16B_TX 20
290 #define TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_TX 0
292 /* Encap of 64B on RX is not supported */
293 #define TF_RSVD_SRAM_ENCAP_64B_RX 0
294 #define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_RX 0
295 /* First encap of 64B TX is reserved by CFA */
296 #define TF_RSVD_SRAM_ENCAP_64B_TX 1007
297 #define TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_TX 0
299 #define TF_RSVD_SRAM_SP_SMAC_RX 0
300 #define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_RX 0
301 #define TF_RSVD_SRAM_SP_SMAC_TX 0
302 #define TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_TX 0
304 /* SRAM SP IPV4 on RX is not supported */
305 #define TF_RSVD_SRAM_SP_SMAC_IPV4_RX 0
306 #define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_RX 0
307 #define TF_RSVD_SRAM_SP_SMAC_IPV4_TX 511
308 #define TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_TX 0
310 /* SRAM SP IPV6 on RX is not supported */
311 #define TF_RSVD_SRAM_SP_SMAC_IPV6_RX 0
312 #define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_RX 0
313 /* Not yet supported fully in infra */
314 #define TF_RSVD_SRAM_SP_SMAC_IPV6_TX 0
315 #define TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_TX 0
317 #define TF_RSVD_SRAM_COUNTER_64B_RX 160
318 #define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_RX 0
319 #define TF_RSVD_SRAM_COUNTER_64B_TX 160
320 #define TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_TX 0
322 #define TF_RSVD_SRAM_NAT_SPORT_RX 0
323 #define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_RX 0
324 #define TF_RSVD_SRAM_NAT_SPORT_TX 0
325 #define TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_TX 0
327 #define TF_RSVD_SRAM_NAT_DPORT_RX 0
328 #define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_RX 0
329 #define TF_RSVD_SRAM_NAT_DPORT_TX 0
330 #define TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_TX 0
332 #define TF_RSVD_SRAM_NAT_S_IPV4_RX 0
333 #define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_RX 0
334 #define TF_RSVD_SRAM_NAT_S_IPV4_TX 0
335 #define TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_TX 0
337 #define TF_RSVD_SRAM_NAT_D_IPV4_RX 0
338 #define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_RX 0
339 #define TF_RSVD_SRAM_NAT_D_IPV4_TX 0
340 #define TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_TX 0
342 /* HW Resource Pool names */
344 #define TF_L2_CTXT_TCAM_POOL_NAME l2_ctxt_tcam_pool
345 #define TF_L2_CTXT_TCAM_POOL_NAME_RX l2_ctxt_tcam_pool_rx
346 #define TF_L2_CTXT_TCAM_POOL_NAME_TX l2_ctxt_tcam_pool_tx
348 #define TF_PROF_FUNC_POOL_NAME prof_func_pool
349 #define TF_PROF_FUNC_POOL_NAME_RX prof_func_pool_rx
350 #define TF_PROF_FUNC_POOL_NAME_TX prof_func_pool_tx
352 #define TF_PROF_TCAM_POOL_NAME prof_tcam_pool
353 #define TF_PROF_TCAM_POOL_NAME_RX prof_tcam_pool_rx
354 #define TF_PROF_TCAM_POOL_NAME_TX prof_tcam_pool_tx
356 #define TF_EM_PROF_ID_POOL_NAME em_prof_id_pool
357 #define TF_EM_PROF_ID_POOL_NAME_RX em_prof_id_pool_rx
358 #define TF_EM_PROF_ID_POOL_NAME_TX em_prof_id_pool_tx
360 #define TF_WC_TCAM_PROF_ID_POOL_NAME wc_tcam_prof_id_pool
361 #define TF_WC_TCAM_PROF_ID_POOL_NAME_RX wc_tcam_prof_id_pool_rx
362 #define TF_WC_TCAM_PROF_ID_POOL_NAME_TX wc_tcam_prof_id_pool_tx
364 #define TF_WC_TCAM_POOL_NAME wc_tcam_pool
365 #define TF_WC_TCAM_POOL_NAME_RX wc_tcam_pool_rx
366 #define TF_WC_TCAM_POOL_NAME_TX wc_tcam_pool_tx
368 #define TF_METER_PROF_POOL_NAME meter_prof_pool
369 #define TF_METER_PROF_POOL_NAME_RX meter_prof_pool_rx
370 #define TF_METER_PROF_POOL_NAME_TX meter_prof_pool_tx
372 #define TF_METER_INST_POOL_NAME meter_inst_pool
373 #define TF_METER_INST_POOL_NAME_RX meter_inst_pool_rx
374 #define TF_METER_INST_POOL_NAME_TX meter_inst_pool_tx
376 #define TF_MIRROR_POOL_NAME mirror_pool
377 #define TF_MIRROR_POOL_NAME_RX mirror_pool_rx
378 #define TF_MIRROR_POOL_NAME_TX mirror_pool_tx
380 #define TF_UPAR_POOL_NAME upar_pool
381 #define TF_UPAR_POOL_NAME_RX upar_pool_rx
382 #define TF_UPAR_POOL_NAME_TX upar_pool_tx
384 #define TF_SP_TCAM_POOL_NAME sp_tcam_pool
385 #define TF_SP_TCAM_POOL_NAME_RX sp_tcam_pool_rx
386 #define TF_SP_TCAM_POOL_NAME_TX sp_tcam_pool_tx
388 #define TF_FKB_POOL_NAME fkb_pool
389 #define TF_FKB_POOL_NAME_RX fkb_pool_rx
390 #define TF_FKB_POOL_NAME_TX fkb_pool_tx
392 #define TF_TBL_SCOPE_POOL_NAME tbl_scope_pool
393 #define TF_TBL_SCOPE_POOL_NAME_RX tbl_scope_pool_rx
394 #define TF_TBL_SCOPE_POOL_NAME_TX tbl_scope_pool_tx
396 #define TF_L2_FUNC_POOL_NAME l2_func_pool
397 #define TF_L2_FUNC_POOL_NAME_RX l2_func_pool_rx
398 #define TF_L2_FUNC_POOL_NAME_TX l2_func_pool_tx
400 #define TF_EPOCH0_POOL_NAME epoch0_pool
401 #define TF_EPOCH0_POOL_NAME_RX epoch0_pool_rx
402 #define TF_EPOCH0_POOL_NAME_TX epoch0_pool_tx
404 #define TF_EPOCH1_POOL_NAME epoch1_pool
405 #define TF_EPOCH1_POOL_NAME_RX epoch1_pool_rx
406 #define TF_EPOCH1_POOL_NAME_TX epoch1_pool_tx
408 #define TF_METADATA_POOL_NAME metadata_pool
409 #define TF_METADATA_POOL_NAME_RX metadata_pool_rx
410 #define TF_METADATA_POOL_NAME_TX metadata_pool_tx
412 #define TF_CT_STATE_POOL_NAME ct_state_pool
413 #define TF_CT_STATE_POOL_NAME_RX ct_state_pool_rx
414 #define TF_CT_STATE_POOL_NAME_TX ct_state_pool_tx
416 #define TF_RANGE_PROF_POOL_NAME range_prof_pool
417 #define TF_RANGE_PROF_POOL_NAME_RX range_prof_pool_rx
418 #define TF_RANGE_PROF_POOL_NAME_TX range_prof_pool_tx
420 #define TF_RANGE_ENTRY_POOL_NAME range_entry_pool
421 #define TF_RANGE_ENTRY_POOL_NAME_RX range_entry_pool_rx
422 #define TF_RANGE_ENTRY_POOL_NAME_TX range_entry_pool_tx
424 #define TF_LAG_ENTRY_POOL_NAME lag_entry_pool
425 #define TF_LAG_ENTRY_POOL_NAME_RX lag_entry_pool_rx
426 #define TF_LAG_ENTRY_POOL_NAME_TX lag_entry_pool_tx
428 /* SRAM Resource Pool names */
429 #define TF_SRAM_FULL_ACTION_POOL_NAME sram_full_action_pool
430 #define TF_SRAM_FULL_ACTION_POOL_NAME_RX sram_full_action_pool_rx
431 #define TF_SRAM_FULL_ACTION_POOL_NAME_TX sram_full_action_pool_tx
433 #define TF_SRAM_MCG_POOL_NAME sram_mcg_pool
434 #define TF_SRAM_MCG_POOL_NAME_RX sram_mcg_pool_rx
435 #define TF_SRAM_MCG_POOL_NAME_TX sram_mcg_pool_tx
437 #define TF_SRAM_ENCAP_8B_POOL_NAME sram_encap_8b_pool
438 #define TF_SRAM_ENCAP_8B_POOL_NAME_RX sram_encap_8b_pool_rx
439 #define TF_SRAM_ENCAP_8B_POOL_NAME_TX sram_encap_8b_pool_tx
441 #define TF_SRAM_ENCAP_16B_POOL_NAME sram_encap_16b_pool
442 #define TF_SRAM_ENCAP_16B_POOL_NAME_RX sram_encap_16b_pool_rx
443 #define TF_SRAM_ENCAP_16B_POOL_NAME_TX sram_encap_16b_pool_tx
445 #define TF_SRAM_ENCAP_64B_POOL_NAME sram_encap_64b_pool
446 #define TF_SRAM_ENCAP_64B_POOL_NAME_RX sram_encap_64b_pool_rx
447 #define TF_SRAM_ENCAP_64B_POOL_NAME_TX sram_encap_64b_pool_tx
449 #define TF_SRAM_SP_SMAC_POOL_NAME sram_sp_smac_pool
450 #define TF_SRAM_SP_SMAC_POOL_NAME_RX sram_sp_smac_pool_rx
451 #define TF_SRAM_SP_SMAC_POOL_NAME_TX sram_sp_smac_pool_tx
453 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME sram_sp_smac_ipv4_pool
454 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_RX sram_sp_smac_ipv4_pool_rx
455 #define TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX sram_sp_smac_ipv4_pool_tx
457 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME sram_sp_smac_ipv6_pool
458 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_RX sram_sp_smac_ipv6_pool_rx
459 #define TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX sram_sp_smac_ipv6_pool_tx
461 #define TF_SRAM_STATS_64B_POOL_NAME sram_stats_64b_pool
462 #define TF_SRAM_STATS_64B_POOL_NAME_RX sram_stats_64b_pool_rx
463 #define TF_SRAM_STATS_64B_POOL_NAME_TX sram_stats_64b_pool_tx
465 #define TF_SRAM_NAT_SPORT_POOL_NAME sram_nat_sport_pool
466 #define TF_SRAM_NAT_SPORT_POOL_NAME_RX sram_nat_sport_pool_rx
467 #define TF_SRAM_NAT_SPORT_POOL_NAME_TX sram_nat_sport_pool_tx
469 #define TF_SRAM_NAT_DPORT_POOL_NAME sram_nat_dport_pool
470 #define TF_SRAM_NAT_DPORT_POOL_NAME_RX sram_nat_dport_pool_rx
471 #define TF_SRAM_NAT_DPORT_POOL_NAME_TX sram_nat_dport_pool_tx
473 #define TF_SRAM_NAT_S_IPV4_POOL_NAME sram_nat_s_ipv4_pool
474 #define TF_SRAM_NAT_S_IPV4_POOL_NAME_RX sram_nat_s_ipv4_pool_rx
475 #define TF_SRAM_NAT_S_IPV4_POOL_NAME_TX sram_nat_s_ipv4_pool_tx
477 #define TF_SRAM_NAT_D_IPV4_POOL_NAME sram_nat_d_ipv4_pool
478 #define TF_SRAM_NAT_D_IPV4_POOL_NAME_RX sram_nat_d_ipv4_pool_rx
479 #define TF_SRAM_NAT_D_IPV4_POOL_NAME_TX sram_nat_d_ipv4_pool_tx
481 /* Sw Resource Pool Names */
483 #define TF_L2_CTXT_REMAP_POOL_NAME l2_ctxt_remap_pool
484 #define TF_L2_CTXT_REMAP_POOL_NAME_RX l2_ctxt_remap_pool_rx
485 #define TF_L2_CTXT_REMAP_POOL_NAME_TX l2_ctxt_remap_pool_tx
488 /** HW Resource types
490 enum tf_resource_type_hw {
491 /* Common HW resources for all chip variants */
492 TF_RESC_TYPE_HW_L2_CTXT_TCAM,
493 TF_RESC_TYPE_HW_PROF_FUNC,
494 TF_RESC_TYPE_HW_PROF_TCAM,
495 TF_RESC_TYPE_HW_EM_PROF_ID,
496 TF_RESC_TYPE_HW_EM_REC,
497 TF_RESC_TYPE_HW_WC_TCAM_PROF_ID,
498 TF_RESC_TYPE_HW_WC_TCAM,
499 TF_RESC_TYPE_HW_METER_PROF,
500 TF_RESC_TYPE_HW_METER_INST,
501 TF_RESC_TYPE_HW_MIRROR,
502 TF_RESC_TYPE_HW_UPAR,
503 /* Wh+/SR specific HW resources */
504 TF_RESC_TYPE_HW_SP_TCAM,
505 /* SR/SR2 specific HW resources */
506 TF_RESC_TYPE_HW_L2_FUNC,
507 /* Thor, SR2 common HW resources */
509 /* SR2 specific HW resources */
510 TF_RESC_TYPE_HW_TBL_SCOPE,
511 TF_RESC_TYPE_HW_EPOCH0,
512 TF_RESC_TYPE_HW_EPOCH1,
513 TF_RESC_TYPE_HW_METADATA,
514 TF_RESC_TYPE_HW_CT_STATE,
515 TF_RESC_TYPE_HW_RANGE_PROF,
516 TF_RESC_TYPE_HW_RANGE_ENTRY,
517 TF_RESC_TYPE_HW_LAG_ENTRY,
521 /** HW Resource types
523 enum tf_resource_type_sram {
524 TF_RESC_TYPE_SRAM_FULL_ACTION,
525 TF_RESC_TYPE_SRAM_MCG,
526 TF_RESC_TYPE_SRAM_ENCAP_8B,
527 TF_RESC_TYPE_SRAM_ENCAP_16B,
528 TF_RESC_TYPE_SRAM_ENCAP_64B,
529 TF_RESC_TYPE_SRAM_SP_SMAC,
530 TF_RESC_TYPE_SRAM_SP_SMAC_IPV4,
531 TF_RESC_TYPE_SRAM_SP_SMAC_IPV6,
532 TF_RESC_TYPE_SRAM_COUNTER_64B,
533 TF_RESC_TYPE_SRAM_NAT_SPORT,
534 TF_RESC_TYPE_SRAM_NAT_DPORT,
535 TF_RESC_TYPE_SRAM_NAT_S_IPV4,
536 TF_RESC_TYPE_SRAM_NAT_D_IPV4,
537 TF_RESC_TYPE_SRAM_MAX
540 #endif /* _TF_RESOURCES_H_ */