drivers/net/bnxt/tf_ulp/ulp_template_db.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2019 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 /*
   7  * date: Mon Mar  9 02:37:53 2020
   8  * version: 0.0
   9  */
  10
  11 #ifndef ULP_TEMPLATE_DB_H_
  12 #define ULP_TEMPLATE_DB_H_
  13
  14 #define BNXT_ULP_MAX_NUM_DEVICES 4
  15 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
  16 #define BNXT_ULP_INGRESS_HDR_MATCH_SZ 2
  17 #define BNXT_ULP_EGRESS_HDR_MATCH_SZ 1
  18 #define BNXT_ULP_INGRESS_ACT_MATCH_SZ 2
  19 #define BNXT_ULP_EGRESS_ACT_MATCH_SZ 1
  20
  21 enum bnxt_ulp_action_bit {
  22         BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
  23         BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
  24         BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
  25         BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
  26         BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
  27         BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
  28         BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
  29         BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
  30         BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
  31         BNXT_ULP_ACTION_BIT_OF_POP_MPLS      = 0x0000000000000200,
  32         BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS     = 0x0000000000000400,
  33         BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
  34         BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
  35         BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
  36         BNXT_ULP_ACTION_BIT_OF_POP_VLAN      = 0x0000000000004000,
  37         BNXT_ULP_ACTION_BIT_OF_PUSH_VLAN     = 0x0000000000008000,
  38         BNXT_ULP_ACTION_BIT_OF_SET_VLAN_PCP  = 0x0000000000010000,
  39         BNXT_ULP_ACTION_BIT_OF_SET_VLAN_VID  = 0x0000000000020000,
  40         BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
  41         BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
  42         BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
  43         BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
  44         BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
  45         BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
  46         BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
  47         BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
  48         BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
  49         BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
  50 };
  51
  52 enum bnxt_ulp_hdr_bit {
  53         BNXT_ULP_HDR_BIT_SVIF                = 0x0000000000000001,
  54         BNXT_ULP_HDR_BIT_O_ETH               = 0x0000000000000002,
  55         BNXT_ULP_HDR_BIT_OO_VLAN             = 0x0000000000000004,
  56         BNXT_ULP_HDR_BIT_OI_VLAN             = 0x0000000000000008,
  57         BNXT_ULP_HDR_BIT_O_L3                = 0x0000000000000010,
  58         BNXT_ULP_HDR_BIT_O_IPV4              = 0x0000000000000020,
  59         BNXT_ULP_HDR_BIT_O_IPV6              = 0x0000000000000040,
  60         BNXT_ULP_HDR_BIT_O_L4                = 0x0000000000000080,
  61         BNXT_ULP_HDR_BIT_O_TCP               = 0x0000000000000100,
  62         BNXT_ULP_HDR_BIT_O_UDP               = 0x0000000000000200,
  63         BNXT_ULP_HDR_BIT_T_VXLAN             = 0x0000000000000400,
  64         BNXT_ULP_HDR_BIT_T_GRE               = 0x0000000000000800,
  65         BNXT_ULP_HDR_BIT_I_ETH               = 0x0000000000001000,
  66         BNXT_ULP_HDR_BIT_IO_VLAN             = 0x0000000000002000,
  67         BNXT_ULP_HDR_BIT_II_VLAN             = 0x0000000000004000,
  68         BNXT_ULP_HDR_BIT_I_L3                = 0x0000000000008000,
  69         BNXT_ULP_HDR_BIT_I_IPV4              = 0x0000000000010000,
  70         BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000020000,
  71         BNXT_ULP_HDR_BIT_I_L4                = 0x0000000000040000,
  72         BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000080000,
  73         BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000100000,
  74         BNXT_ULP_HDR_BIT_LAST                = 0x0000000000200000
  75 };
  76
  77 enum bnxt_ulp_byte_order {
  78         BNXT_ULP_BYTE_ORDER_BE,
  79         BNXT_ULP_BYTE_ORDER_LE,
  80         BNXT_ULP_BYTE_ORDER_LAST
  81 };
  82
  83 enum bnxt_ulp_device_id {
  84         BNXT_ULP_DEVICE_ID_WH_PLUS,
  85         BNXT_ULP_DEVICE_ID_THOR,
  86         BNXT_ULP_DEVICE_ID_STINGRAY,
  87         BNXT_ULP_DEVICE_ID_STINGRAY2,
  88         BNXT_ULP_DEVICE_ID_LAST
  89 };
  90
  91 enum bnxt_ulp_fmf_mask {
  92         BNXT_ULP_FMF_MASK_IGNORE,
  93         BNXT_ULP_FMF_MASK_ANY,
  94         BNXT_ULP_FMF_MASK_EXACT,
  95         BNXT_ULP_FMF_MASK_WILDCARD,
  96         BNXT_ULP_FMF_MASK_LAST
  97 };
  98
  99 enum bnxt_ulp_fmf_spec {
 100         BNXT_ULP_FMF_SPEC_IGNORE = 0,
 101         BNXT_ULP_FMF_SPEC_LAST = 1
 102 };
 103
 104 enum bnxt_ulp_mark_enable {
 105         BNXT_ULP_MARK_ENABLE_NO = 0,
 106         BNXT_ULP_MARK_ENABLE_YES = 1,
 107         BNXT_ULP_MARK_ENABLE_LAST = 2
 108 };
 109
 110 enum bnxt_ulp_hdr_field {
 111         BNXT_ULP_HDR_FIELD_MPLS_TAG_NUM = 0,
 112         BNXT_ULP_HDR_FIELD_O_VTAG_NUM = 1,
 113         BNXT_ULP_HDR_FIELD_I_VTAG_NUM = 2,
 114         BNXT_ULP_HDR_FIELD_SVIF_INDEX = 3,
 115         BNXT_ULP_HDR_FIELD_LAST = 4
 116 };
 117
 118 enum bnxt_ulp_mask_opc {
 119         BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
 120         BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
 121         BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
 122         BNXT_ULP_MASK_OPC_ADD_PAD = 3,
 123         BNXT_ULP_MASK_OPC_LAST = 4
 124 };
 125
 126 enum bnxt_ulp_priority {
 127         BNXT_ULP_PRIORITY_LEVEL_0 = 0,
 128         BNXT_ULP_PRIORITY_LEVEL_1 = 1,
 129         BNXT_ULP_PRIORITY_LEVEL_2 = 2,
 130         BNXT_ULP_PRIORITY_LEVEL_3 = 3,
 131         BNXT_ULP_PRIORITY_LEVEL_4 = 4,
 132         BNXT_ULP_PRIORITY_LEVEL_5 = 5,
 133         BNXT_ULP_PRIORITY_LEVEL_6 = 6,
 134         BNXT_ULP_PRIORITY_LEVEL_7 = 7,
 135         BNXT_ULP_PRIORITY_NOT_USED = 8,
 136         BNXT_ULP_PRIORITY_LAST = 9
 137 };
 138
 139 enum bnxt_ulp_regfile_index {
 140         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 0,
 141         BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 1,
 142         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 2,
 143         BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 3,
 144         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 4,
 145         BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 5,
 146         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 6,
 147         BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 7,
 148         BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 8,
 149         BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 9,
 150         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 10,
 151         BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 11,
 152         BNXT_ULP_REGFILE_INDEX_NOT_USED = 12,
 153         BNXT_ULP_REGFILE_INDEX_LAST = 13
 154 };
 155
 156 enum bnxt_ulp_resource_func {
 157         BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE = 0,
 158         BNXT_ULP_RESOURCE_FUNC_EM_TABLE = 1,
 159         BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE = 2,
 160         BNXT_ULP_RESOURCE_FUNC_IDENTIFIER = 3,
 161         BNXT_ULP_RESOURCE_FUNC_HW_FID = 4,
 162         BNXT_ULP_RESOURCE_FUNC_LAST = 5
 163 };
 164
 165 enum bnxt_ulp_result_opc {
 166         BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT = 0,
 167         BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP = 1,
 168         BNXT_ULP_RESULT_OPC_SET_TO_ACT_PROP_SZ = 2,
 169         BNXT_ULP_RESULT_OPC_SET_TO_REGFILE = 3,
 170         BNXT_ULP_RESULT_OPC_LAST = 4
 171 };
 172
 173 enum bnxt_ulp_search_before_alloc {
 174         BNXT_ULP_SEARCH_BEFORE_ALLOC_NO = 0,
 175         BNXT_ULP_SEARCH_BEFORE_ALLOC_YES = 1,
 176         BNXT_ULP_SEARCH_BEFORE_ALLOC_LAST = 2
 177 };
 178
 179 enum bnxt_ulp_spec_opc {
 180         BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
 181         BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
 182         BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
 183         BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
 184         BNXT_ULP_SPEC_OPC_LAST = 4
 185 };
 186
 187 enum bnxt_ulp_sym {
 188         BNXT_ULP_SYM_BIG_ENDIAN = 0,
 189         BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
 190         BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
 191         BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
 192         BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
 193         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
 194         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
 195         BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
 196         BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
 197         BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
 198         BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
 199         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
 200         BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
 201         BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
 202         BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
 203         BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
 204         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
 205         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
 206         BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
 207         BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
 208         BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
 209         BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
 210         BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
 211         BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
 212         BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
 213         BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 214         BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
 215         BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
 216         BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
 217         BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
 218         BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
 219         BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
 220         BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
 221         BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
 222         BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
 223         BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
 224         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
 225         BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
 226         BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
 227         BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
 228         BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
 229         BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
 230         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
 231         BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 232         BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
 233         BNXT_ULP_SYM_NO = 0,
 234         BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
 235         BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
 236         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
 237         BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
 238         BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
 239         BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
 240         BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
 241         BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
 242         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
 243         BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
 244         BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
 245         BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
 246         BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
 247         BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
 248         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
 249         BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
 250         BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
 251         BNXT_ULP_SYM_YES = 1
 252 };
 253
 254 enum bnxt_ulp_act_prop_sz {
 255         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN_SZ = 4,
 256         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SZ = 4,
 257         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_SZ = 4,
 258         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_TYPE = 4,
 259         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG_NUM = 4,
 260         BNXT_ULP_ACT_PROP_SZ_ENCAP_L3_TYPE = 4,
 261         BNXT_ULP_ACT_PROP_SZ_MPLS_POP_NUM = 4,
 262         BNXT_ULP_ACT_PROP_SZ_MPLS_PUSH_NUM = 4,
 263         BNXT_ULP_ACT_PROP_SZ_VNIC = 4,
 264         BNXT_ULP_ACT_PROP_SZ_VPORT = 4,
 265         BNXT_ULP_ACT_PROP_SZ_MARK = 4,
 266         BNXT_ULP_ACT_PROP_SZ_COUNT = 4,
 267         BNXT_ULP_ACT_PROP_SZ_METER = 4,
 268         BNXT_ULP_ACT_PROP_SZ_SET_MAC_SRC = 8,
 269         BNXT_ULP_ACT_PROP_SZ_SET_MAC_DST = 8,
 270         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_VLAN = 4,
 271         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_PCP = 4,
 272         BNXT_ULP_ACT_PROP_SZ_OF_SET_VLAN_VID = 4,
 273         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_SRC = 4,
 274         BNXT_ULP_ACT_PROP_SZ_SET_IPV4_DST = 4,
 275         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_SRC = 16,
 276         BNXT_ULP_ACT_PROP_SZ_SET_IPV6_DST = 16,
 277         BNXT_ULP_ACT_PROP_SZ_SET_TP_SRC = 4,
 278         BNXT_ULP_ACT_PROP_SZ_SET_TP_DST = 4,
 279         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_0 = 4,
 280         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_1 = 4,
 281         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_2 = 4,
 282         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_3 = 4,
 283         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_4 = 4,
 284         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_5 = 4,
 285         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_6 = 4,
 286         BNXT_ULP_ACT_PROP_SZ_OF_PUSH_MPLS_7 = 4,
 287         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_DMAC = 6,
 288         BNXT_ULP_ACT_PROP_SZ_ENCAP_L2_SMAC = 6,
 289         BNXT_ULP_ACT_PROP_SZ_ENCAP_VTAG = 8,
 290         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP = 32,
 291         BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 292         BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 293         BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
 294         BNXT_ULP_ACT_PROP_SZ_LAST = 4
 295 };
 296
 297 enum bnxt_ulp_act_prop_idx {
 298         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN_SZ = 0,
 299         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SZ = 4,
 300         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_SZ = 8,
 301         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_TYPE = 12,
 302         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG_NUM = 16,
 303         BNXT_ULP_ACT_PROP_IDX_ENCAP_L3_TYPE = 20,
 304         BNXT_ULP_ACT_PROP_IDX_MPLS_POP_NUM = 24,
 305         BNXT_ULP_ACT_PROP_IDX_MPLS_PUSH_NUM = 28,
 306         BNXT_ULP_ACT_PROP_IDX_VNIC = 32,
 307         BNXT_ULP_ACT_PROP_IDX_VPORT = 36,
 308         BNXT_ULP_ACT_PROP_IDX_MARK = 40,
 309         BNXT_ULP_ACT_PROP_IDX_COUNT = 44,
 310         BNXT_ULP_ACT_PROP_IDX_METER = 48,
 311         BNXT_ULP_ACT_PROP_IDX_SET_MAC_SRC = 52,
 312         BNXT_ULP_ACT_PROP_IDX_SET_MAC_DST = 60,
 313         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_VLAN = 68,
 314         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_PCP = 72,
 315         BNXT_ULP_ACT_PROP_IDX_OF_SET_VLAN_VID = 76,
 316         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_SRC = 80,
 317         BNXT_ULP_ACT_PROP_IDX_SET_IPV4_DST = 84,
 318         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_SRC = 88,
 319         BNXT_ULP_ACT_PROP_IDX_SET_IPV6_DST = 104,
 320         BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC = 120,
 321         BNXT_ULP_ACT_PROP_IDX_SET_TP_DST = 124,
 322         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_0 = 128,
 323         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_1 = 132,
 324         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_2 = 136,
 325         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_3 = 140,
 326         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_4 = 144,
 327         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_5 = 148,
 328         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_6 = 152,
 329         BNXT_ULP_ACT_PROP_IDX_OF_PUSH_MPLS_7 = 156,
 330         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_DMAC = 160,
 331         BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC = 166,
 332         BNXT_ULP_ACT_PROP_IDX_ENCAP_VTAG = 172,
 333         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP = 180,
 334         BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 212,
 335         BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 228,
 336         BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 232,
 337         BNXT_ULP_ACT_PROP_IDX_LAST = 264
 338 };
 339
 340 #endif /* _ULP_TEMPLATE_DB_H_ */